1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
42 } __attribute__((packed));
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
55 } __attribute__((packed));
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The SRT EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 #define TLV_TYPE_LAST \
92 TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY
95 /* tlv (size:64b/8B) */
98 * The command discriminator is used to differentiate between various
99 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
100 * command messages as well as newer TLV encapsulated HWRM commands.
102 * For TLV encapsulated messages this field must be 0x8000.
108 * Indicates the presence of additional TLV encapsulated data
111 #define TLV_FLAGS_MORE UINT32_C(0x1)
112 /* Last TLV in a sequence of TLVs. */
113 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
114 /* More TLVs follow this TLV. */
115 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
117 * When an HWRM receiver detects a TLV type that it does not
118 * support with the TLV required flag set, the receiver must
119 * reject the HWRM message with an error code indicating an
120 * unsupported TLV type.
122 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
124 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
126 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
127 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
129 * This field defines the TLV type value which is divided into
130 * two ranges to differentiate between global and local TLV types.
131 * Global TLV types must be unique across all defined TLV types.
132 * Local TLV types are valid only for extensions to a given
133 * HWRM message and may be repeated across different HWRM message
134 * types. There is a direct correlation of each HWRM message type
135 * to a single global TLV type value.
137 * Global TLV range: `0 - (63k-1)`
139 * Local TLV range: `63k - (64k-1)`
143 * Length of the message data encapsulated by this TLV in bytes.
144 * This length does not include the size of the TLV header itself
145 * and it must be an integer multiple of 8B.
148 } __attribute__((packed));
151 /* input (size:128b/16B) */
154 * This value indicates what type of request this is. The format
155 * for the rest of the command is determined by this field.
159 * This value indicates the what completion ring the request will
160 * be optionally completed on. If the value is -1, then no
161 * CR completion will be generated. Any other value must be a
162 * valid CR ring_id value for this function.
165 /* This value indicates the command sequence number. */
168 * Target ID of this command.
170 * 0x0 - 0xFFF8 - Used for function ids
171 * 0xFFF8 - 0xFFFE - Reserved for internal processors
176 * This is the host address where the response will be written
177 * when the request is complete. This area must be 16B aligned
178 * and must be cleared to zero before the request is made.
181 } __attribute__((packed));
184 /* output (size:64b/8B) */
187 * Pass/Fail or error type
189 * Note: receiver to verify the in parameters, and fail the call
190 * with an error when appropriate
193 /* This field returns the type of original request. */
195 /* This field provides original sequence number of the command. */
198 * This field is the length of the response in bytes. The
199 * last byte of the response is a valid flag that will read
200 * as '1' when the command has been completely written to
204 } __attribute__((packed));
206 /* Short Command Structure */
207 /* hwrm_short_input (size:128b/16B) */
208 struct hwrm_short_input {
210 * This field indicates the type of request in the request buffer.
211 * The format for the rest of the command (request) is determined
216 * This field indicates a signature that is used to identify short
217 * form of the command listed here. This field shall be set to
221 /* Signature indicating this is a short form of HWRM command */
222 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
223 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
224 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
225 /* The target ID of the command */
227 /* Default target_id (0x0) to maintain compatibility with old driver */
228 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
229 /* Reserved for user-space HWRM interface */
230 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
231 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
232 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
233 /* This value indicates the length of the request. */
236 * This is the host address where the request was written.
237 * This area must be 16B aligned.
240 } __attribute__((packed));
244 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
245 * # So only structure definition is provided here.
247 /* cmd_nums (size:64b/8B) */
250 * This version of the specification defines the commands listed in
251 * the table below. The following are general implementation
252 * requirements for these commands:
254 * # All commands listed below that are marked neither
255 * reserved nor experimental shall be implemented by the HWRM.
256 * # A HWRM client compliant to this specification should not use
257 * commands outside of the list below.
258 * # A HWRM client compliant to this specification should not use
259 * command numbers marked reserved below.
260 * # A command marked experimental below may not be implemented
262 * # A command marked experimental may change in the
263 * future version of the HWRM specification.
264 * # A command not listed below may be implemented by the HWRM.
265 * The behavior of commands that are not listed below is outside
266 * the scope of this specification.
269 #define HWRM_VER_GET UINT32_C(0x0)
270 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
271 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
272 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
273 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
274 /* Reserved for future use. */
275 #define HWRM_RESERVED1 UINT32_C(0x10)
276 #define HWRM_FUNC_RESET UINT32_C(0x11)
277 #define HWRM_FUNC_GETFID UINT32_C(0x12)
278 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
279 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
280 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
281 #define HWRM_FUNC_QCFG UINT32_C(0x16)
282 #define HWRM_FUNC_CFG UINT32_C(0x17)
283 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
284 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
285 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
286 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
287 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
288 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
289 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
290 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
291 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
292 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
294 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
295 #define HWRM_PORT_QSTATS UINT32_C(0x23)
296 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
298 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
300 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
301 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
302 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
304 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
305 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
306 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
307 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
308 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
309 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
310 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
311 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
312 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
313 #define HWRM_QUEUE_CFG UINT32_C(0x32)
314 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
315 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
316 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
317 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
318 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
319 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
320 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
321 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
323 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 #define HWRM_RING_ALLOC UINT32_C(0x50)
341 #define HWRM_RING_FREE UINT32_C(0x51)
342 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
343 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
344 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
345 #define HWRM_RING_RESET UINT32_C(0x5e)
346 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
347 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
348 /* Reserved for future use. */
349 #define HWRM_RESERVED5 UINT32_C(0x64)
350 /* Reserved for future use. */
351 #define HWRM_RESERVED6 UINT32_C(0x65)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
353 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
354 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
355 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
356 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
357 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
358 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
359 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
360 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
362 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
364 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
366 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
367 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
369 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
371 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
373 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
374 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
375 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
376 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
377 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
378 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
379 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
380 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
381 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
382 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
383 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
384 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
385 #define HWRM_FW_RESET UINT32_C(0xc0)
386 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
387 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
388 #define HWRM_FW_SYNC UINT32_C(0xc3)
389 #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4)
390 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
391 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
392 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
394 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
396 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
398 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
400 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
402 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
403 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
404 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
405 #define HWRM_FWD_RESP UINT32_C(0xd2)
406 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
407 #define HWRM_OEM_CMD UINT32_C(0xd4)
408 /* Tells the fw to run PRBS test on a given port and lane. */
409 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
410 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
411 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
412 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
413 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
414 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
416 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
418 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
420 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
422 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
424 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
426 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
428 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
430 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
432 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
434 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
436 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
438 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
440 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
442 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
444 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
446 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
448 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
450 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
452 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
453 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
454 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
455 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
457 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
459 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
461 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
463 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
464 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
465 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
467 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
469 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
471 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
473 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
475 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
477 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
479 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
481 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
483 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
485 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
487 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
489 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
491 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
493 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
495 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
497 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
499 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
501 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
503 #define HWRM_CFA_TFLIB UINT32_C(0x125)
504 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
505 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
506 /* Engine CKV - Add a new CKEK used to encrypt keys. */
507 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
508 /* Engine CKV - Delete a previously added CKEK. */
509 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
510 /* Engine CKV - Add a new key to the key vault. */
511 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
512 /* Engine CKV - Delete a key from the key vault. */
513 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
514 /* Engine CKV - Delete all keys from the key vault. */
515 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
516 /* Engine CKV - Get random data. */
517 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
518 /* Engine CKV - Generate and encrypt a new AES key. */
519 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
520 /* Engine CKV - Configure a label index with a label value. */
521 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
522 /* Engine CKV - Query a label */
523 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
524 /* Engine - Query the available queue groups configuration. */
525 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
526 /* Engine - Query the queue groups assigned to a function. */
527 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
528 /* Engine - Query the available queue group meter profile configuration. */
529 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
530 /* Engine - Query the configuration of a queue group meter profile. */
531 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
532 /* Engine - Allocate a queue group meter profile. */
533 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
534 /* Engine - Free a queue group meter profile. */
535 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
536 /* Engine - Query the meters assigned to a queue group. */
537 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
538 /* Engine - Bind a queue group meter profile to a queue group. */
539 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
540 /* Engine - Unbind a queue group meter profile from a queue group. */
541 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
542 /* Engine - Bind a queue group to a function. */
543 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
544 /* Engine - Query the scheduling group configuration. */
545 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
546 /* Engine - Query the queue groups assigned to a scheduling group. */
547 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
548 /* Engine - Query the configuration of a scheduling group's meter profiles. */
549 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
550 /* Engine - Configure a scheduling group's meter profiles. */
551 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
552 /* Engine - Bind a queue group to a scheduling group. */
553 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
554 /* Engine - Unbind a queue group from its scheduling group. */
555 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
556 /* Engine - Query the Engine configuration. */
557 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
558 /* Engine - Configure the statistics accumulator for an Engine. */
559 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
560 /* Engine - Clear the statistics accumulator for an Engine. */
561 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
562 /* Engine - Query the statistics accumulator for an Engine. */
563 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
564 /* Engine - Allocate an Engine RQ. */
565 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
566 /* Engine - Free an Engine RQ. */
567 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
568 /* Engine - Allocate an Engine CQ. */
569 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
570 /* Engine - Free an Engine CQ. */
571 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
572 /* Engine - Allocate an NQ. */
573 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
574 /* Engine - Free an NQ. */
575 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
576 /* Engine - Set the on-die RQE credit update location. */
577 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
578 /* Engine - Query the engine function configuration. */
579 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
581 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
583 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
585 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
587 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
589 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
590 /* Configures the BW of any VF */
591 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
592 /* Queries the BW of any VF */
593 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
594 /* Queries pf ids belong to specified host(s) */
595 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
597 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
599 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
601 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
603 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
605 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
607 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
608 /* Returns the current value of a free running counter from the device. */
609 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
611 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
613 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
615 * Tells the fw to run the DMA read from the host and DMA write
618 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
620 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
622 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
624 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
626 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
627 #define HWRM_DBG_DUMP UINT32_C(0xff14)
629 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
631 #define HWRM_DBG_CFG UINT32_C(0xff16)
633 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
635 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
637 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
639 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
641 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
643 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
645 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
647 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
649 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
650 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
651 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
652 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
653 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
654 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
655 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
656 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
657 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
658 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
659 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
660 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
661 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
662 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
663 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
664 #define HWRM_NVM_READ UINT32_C(0xfffd)
665 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
666 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
667 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
668 uint16_t unused_0[3];
669 } __attribute__((packed));
672 /* ret_codes (size:64b/8B) */
675 /* Request was successfully executed by the HWRM. */
676 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
677 /* The HWRM failed to execute the request. */
678 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
680 * The request contains invalid argument(s) or input
683 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
685 * The requester is not allowed to access the requested
686 * resource. This error code shall be provided in a
687 * response to a request to query or modify an existing
688 * resource that is not accessible by the requester.
690 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
692 * The HWRM is unable to allocate the requested resource.
693 * This code only applies to requests for HWRM resource
696 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
698 * Invalid combination of flags is specified in the
701 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
703 * Invalid combination of enables fields is specified in
706 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
708 * Request contains a required TLV that is not supported by
709 * the installed version of firmware.
711 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
713 * No firmware buffer available to accept the request. Driver
714 * should retry the request.
716 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
718 * This error code is only reported by firmware when some
719 * sub-option of a supported HWRM command is unsupported.
721 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
723 * This error code is only reported by firmware when the specific
724 * request is not able to process when the HOT reset in progress.
726 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
728 * This error code is only reported by firmware when the registered
729 * driver instances are not capable of hot reset.
731 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
733 * This error code is only reported by the firmware when during
734 * flow allocation when a requeest for a flow counter fails because
735 * the number of flow counters are exhausted.
737 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
739 * This error code is only reported by firmware when the registered
740 * driver instances requested to offloaded a flow but was unable to because
741 * the requested key's hash collides with the installed keys.
743 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
745 * This error code is only reported by firmware when the registered
746 * driver instances requested to offloaded a flow but was unable to because
747 * the same key has already been installed.
749 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
751 * Generic HWRM execution error that represents an
754 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
756 * This value indicates that the HWRM response is in TLV format and
757 * should be interpreted as one or more TLVs starting with the
758 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
759 * by itself, just an indicatation that the response should be parsed
760 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
762 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
764 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
765 /* Unsupported or invalid command */
766 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
767 #define HWRM_ERR_CODE_LAST \
768 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
769 uint16_t unused_0[3];
770 } __attribute__((packed));
773 /* hwrm_err_output (size:128b/16B) */
774 struct hwrm_err_output {
776 * Pass/Fail or error type
778 * Note: receiver to verify the in parameters, and fail the call
779 * with an error when appropriate
782 /* This field returns the type of original request. */
784 /* This field provides original sequence number of the command. */
787 * This field is the length of the response in bytes. The
788 * last byte of the response is a valid flag that will read
789 * as '1' when the command has been completely written to
793 /* debug info for this error response. */
795 /* debug info for this error response. */
798 * In the case of an error response, command specific error
799 * code is returned in this field.
803 * This field is used in Output records to indicate that the output
804 * is completely written to RAM. This field should be read as '1'
805 * to indicate that the output has been completely written.
806 * When writing a command completion or response to an internal processor,
807 * the order of writes has to be such that this field is written last.
810 } __attribute__((packed));
812 * Following is the signature for HWRM message field that indicates not
813 * applicable (All F's). Need to cast it the size of the field if needed.
815 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
816 /* hwrm_func_buf_rgtr */
817 #define HWRM_MAX_REQ_LEN 128
818 /* hwrm_cfa_flow_info */
819 #define HWRM_MAX_RESP_LEN 704
820 /* 7 bit indirection table index. */
821 #define HW_HASH_INDEX_SIZE 0x80
822 #define HW_HASH_KEY_SIZE 40
823 /* valid key for HWRM response */
824 #define HWRM_RESP_VALID_KEY 1
825 /* Reserved for BONO processor */
826 #define HWRM_TARGET_ID_BONO 0xFFF8
827 /* Reserved for KONG processor */
828 #define HWRM_TARGET_ID_KONG 0xFFF9
829 /* Reserved for APE processor */
830 #define HWRM_TARGET_ID_APE 0xFFFA
832 * This value will be used by tools for User-space HWRM Interface.
833 * When tool execute any HWRM command with this target_id, firmware
834 * will copy the response and/or data payload via register space instead
837 #define HWRM_TARGET_ID_TOOLS 0xFFFD
838 #define HWRM_VERSION_MAJOR 1
839 #define HWRM_VERSION_MINOR 10
840 #define HWRM_VERSION_UPDATE 0
841 /* non-zero means beta version */
842 #define HWRM_VERSION_RSVD 91
843 #define HWRM_VERSION_STR "1.10.0.91"
850 /* hwrm_ver_get_input (size:192b/24B) */
851 struct hwrm_ver_get_input {
852 /* The HWRM command request type. */
855 * The completion ring to send the completion event on. This should
856 * be the NQ ID returned from the `nq_alloc` HWRM command.
860 * The sequence ID is used by the driver for tracking multiple
861 * commands. This ID is treated as opaque data by the firmware and
862 * the value is returned in the `hwrm_resp_hdr` upon completion.
866 * The target ID of the command:
867 * * 0x0-0xFFF8 - The function ID
868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
869 * * 0xFFFD - Reserved for user-space HWRM interface
874 * A physical address pointer pointing to a host buffer that the
875 * command's response data will be written. This can be either a host
876 * physical address (HPA) or a guest physical address (GPA) and must
877 * point to a physically contiguous block of memory.
881 * This field represents the major version of HWRM interface
882 * specification supported by the driver HWRM implementation.
883 * The interface major version is intended to change only when
884 * non backward compatible changes are made to the HWRM
885 * interface specification.
887 uint8_t hwrm_intf_maj;
889 * This field represents the minor version of HWRM interface
890 * specification supported by the driver HWRM implementation.
891 * A change in interface minor version is used to reflect
892 * significant backward compatible modification to HWRM
893 * interface specification.
894 * This can be due to addition or removal of functionality.
895 * HWRM interface specifications with the same major version
896 * but different minor versions are compatible.
898 uint8_t hwrm_intf_min;
900 * This field represents the update version of HWRM interface
901 * specification supported by the driver HWRM implementation.
902 * The interface update version is used to reflect minor
903 * changes or bug fixes to a released HWRM interface
906 uint8_t hwrm_intf_upd;
908 } __attribute__((packed));
910 /* hwrm_ver_get_output (size:1408b/176B) */
911 struct hwrm_ver_get_output {
912 /* The specific error status for the command. */
914 /* The HWRM command request type. */
916 /* The sequence ID from the original command. */
918 /* The length of the response data in number of bytes. */
921 * This field represents the major version of HWRM interface
922 * specification supported by the HWRM implementation.
923 * The interface major version is intended to change only when
924 * non backward compatible changes are made to the HWRM
925 * interface specification.
926 * A HWRM implementation that is compliant with this
927 * specification shall provide value of 1 in this field.
929 uint8_t hwrm_intf_maj_8b;
931 * This field represents the minor version of HWRM interface
932 * specification supported by the HWRM implementation.
933 * A change in interface minor version is used to reflect
934 * significant backward compatible modification to HWRM
935 * interface specification.
936 * This can be due to addition or removal of functionality.
937 * HWRM interface specifications with the same major version
938 * but different minor versions are compatible.
939 * A HWRM implementation that is compliant with this
940 * specification shall provide value of 2 in this field.
942 uint8_t hwrm_intf_min_8b;
944 * This field represents the update version of HWRM interface
945 * specification supported by the HWRM implementation.
946 * The interface update version is used to reflect minor
947 * changes or bug fixes to a released HWRM interface
949 * A HWRM implementation that is compliant with this
950 * specification shall provide value of 2 in this field.
952 uint8_t hwrm_intf_upd_8b;
953 uint8_t hwrm_intf_rsvd_8b;
955 * This field represents the major version of HWRM firmware.
956 * A change in firmware major version represents a major
959 uint8_t hwrm_fw_maj_8b;
961 * This field represents the minor version of HWRM firmware.
962 * A change in firmware minor version represents significant
963 * firmware functionality changes.
965 uint8_t hwrm_fw_min_8b;
967 * This field represents the build version of HWRM firmware.
968 * A change in firmware build version represents bug fixes
969 * to a released firmware.
971 uint8_t hwrm_fw_bld_8b;
973 * This field is a reserved field. This field can be used to
974 * represent firmware branches or customer specific releases
975 * tied to a specific (major,minor,update) version of the
978 uint8_t hwrm_fw_rsvd_8b;
980 * This field represents the major version of mgmt firmware.
981 * A change in major version represents a major release.
983 uint8_t mgmt_fw_maj_8b;
985 * This field represents the minor version of mgmt firmware.
986 * A change in minor version represents significant
987 * functionality changes.
989 uint8_t mgmt_fw_min_8b;
991 * This field represents the build version of mgmt firmware.
992 * A change in update version represents bug fixes.
994 uint8_t mgmt_fw_bld_8b;
996 * This field is a reserved field. This field can be used to
997 * represent firmware branches or customer specific releases
998 * tied to a specific (major,minor,update) version
1000 uint8_t mgmt_fw_rsvd_8b;
1002 * This field represents the major version of network
1004 * A change in major version represents a major release.
1006 uint8_t netctrl_fw_maj_8b;
1008 * This field represents the minor version of network
1010 * A change in minor version represents significant
1011 * functionality changes.
1013 uint8_t netctrl_fw_min_8b;
1015 * This field represents the build version of network
1017 * A change in update version represents bug fixes.
1019 uint8_t netctrl_fw_bld_8b;
1021 * This field is a reserved field. This field can be used to
1022 * represent firmware branches or customer specific releases
1023 * tied to a specific (major,minor,update) version
1025 uint8_t netctrl_fw_rsvd_8b;
1027 * This field is used to indicate device's capabilities and
1030 uint32_t dev_caps_cfg;
1032 * If set to 1, then secure firmware update behavior
1034 * If set to 0, then secure firmware update behavior is
1037 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1040 * If set to 1, then firmware based DCBX agent is supported.
1041 * If set to 0, then firmware based DCBX agent capability
1042 * is not supported on this device.
1044 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1047 * If set to 1, then HWRM short command format is supported.
1048 * If set to 0, then HWRM short command format is not supported.
1050 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1053 * If set to 1, then HWRM short command format is required.
1054 * If set to 0, then HWRM short command format is not required.
1056 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1059 * If set to 1, then the KONG host mailbox channel is supported.
1060 * If set to 0, then the KONG host mailbox channel is not supported.
1061 * By default, this flag should be 0 for older version of core firmware.
1063 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1066 * If set to 1, then the 64bit flow handle is supported in addition to the
1067 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1068 * supported. By default, this flag should be 0 for older version of core firmware.
1070 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1073 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1074 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1075 * If set to 0, then filter types not supported.
1076 * By default, this flag should be 0 for older version of core firmware.
1078 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1081 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1082 * If set to 0, firmware can't supported virtio vSwitch offload model.
1083 * By default, this flag should be 0 for older version of core firmware.
1085 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1088 * If set to 1, firmware is capable to support trusted VF.
1089 * If set to 0, firmware is not capable to support trusted VF.
1090 * By default, this flag should be 0 for older version of core firmware.
1092 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1095 * If set to 1, firmware is capable to support flow aging.
1096 * If set to 0, firmware is not capable to support flow aging.
1097 * By default, this flag should be 0 for older version of core firmware.
1099 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1102 * If set to 1, firmware is capable to support advanced flow counters like,
1103 * Meter drop counters and EEM counters.
1104 * If set to 0, firmware is not capable to support advanced flow counters.
1105 * By default, this flag should be 0 for older version of core firmware.
1107 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1110 * If set to 1, the firmware is able to support the use of the CFA
1111 * Extended Exact Match(EEM) feature.
1112 * If set to 0, firmware is not capable to support the use of the
1114 * By default, this flag should be 0 for older version of core firmware.
1116 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1119 * If set to 1, the firmware is able to support advance CFA flow management
1120 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1121 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1123 * By default, this flag should be 0 for older version of core firmware.
1125 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1128 * If set to 1, the firmware is able to support TFLIB features.
1129 * If set to 0, then the firmware doesn’t support TFLIB features.
1130 * By default, this flag should be 0 for older version of core firmware.
1132 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1135 * This field represents the major version of RoCE firmware.
1136 * A change in major version represents a major release.
1138 uint8_t roce_fw_maj_8b;
1140 * This field represents the minor version of RoCE firmware.
1141 * A change in minor version represents significant
1142 * functionality changes.
1144 uint8_t roce_fw_min_8b;
1146 * This field represents the build version of RoCE firmware.
1147 * A change in update version represents bug fixes.
1149 uint8_t roce_fw_bld_8b;
1151 * This field is a reserved field. This field can be used to
1152 * represent firmware branches or customer specific releases
1153 * tied to a specific (major,minor,update) version
1155 uint8_t roce_fw_rsvd_8b;
1157 * This field represents the name of HWRM FW (ASCII chars
1158 * with NULL at the end).
1160 char hwrm_fw_name[16];
1162 * This field represents the name of mgmt FW (ASCII chars
1163 * with NULL at the end).
1165 char mgmt_fw_name[16];
1167 * This field represents the name of network control
1168 * firmware (ASCII chars with NULL at the end).
1170 char netctrl_fw_name[16];
1171 /* This field represents the active board package name. */
1172 char active_pkg_name[16];
1174 * This field represents the name of RoCE FW (ASCII chars
1175 * with NULL at the end).
1177 char roce_fw_name[16];
1178 /* This field returns the chip number. */
1180 /* This field returns the revision of chip. */
1182 /* This field returns the chip metal number. */
1184 /* This field returns the bond id of the chip. */
1185 uint8_t chip_bond_id;
1186 /* This value indicates the type of platform used for chip implementation. */
1187 uint8_t chip_platform_type;
1189 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1190 /* FPGA platform of the chip. */
1191 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1192 /* Palladium platform of the chip. */
1193 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1194 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1195 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1197 * This field returns the maximum value of request window that
1198 * is supported by the HWRM. The request window is mapped
1199 * into device address space using MMIO.
1201 uint16_t max_req_win_len;
1203 * This field returns the maximum value of response buffer in
1206 uint16_t max_resp_len;
1208 * This field returns the default request timeout value in
1211 uint16_t def_req_timeout;
1213 * This field will indicate if any subsystems is not fully
1218 * If set to 1, it will indicate to host drivers that firmware is
1219 * not ready to start full blown HWRM commands. Host drivers should
1220 * re-try HWRM_VER_GET with some timeout period. The timeout period
1221 * can be selected up to 5 seconds.
1222 * For Example, PCIe hot-plug:
1223 * Hot plug timing is system dependent. It generally takes up to
1224 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1225 * If set to 0, device is ready to accept all HWRM commands.
1227 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1229 * If set to 1, external version present.
1230 * If set to 0, external version not present.
1232 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1233 uint8_t unused_0[2];
1235 * For backward compatibility this field must be set to 1.
1236 * Older drivers might look for this field to be 1 before
1237 * processing the message.
1241 * This field represents the major version of HWRM interface
1242 * specification supported by the HWRM implementation.
1243 * The interface major version is intended to change only when
1244 * non backward compatible changes are made to the HWRM
1245 * interface specification. A HWRM implementation that is
1246 * compliant with this specification shall provide value of 1
1249 uint16_t hwrm_intf_major;
1251 * This field represents the minor version of HWRM interface
1252 * specification supported by the HWRM implementation.
1253 * A change in interface minor version is used to reflect
1254 * significant backward compatible modification to HWRM
1255 * interface specification. This can be due to addition or
1256 * removal of functionality. HWRM interface specifications
1257 * with the same major version but different minor versions are
1258 * compatible. A HWRM implementation that is compliant with
1259 * this specification shall provide value of 2 in this field.
1261 uint16_t hwrm_intf_minor;
1263 * This field represents the update version of HWRM interface
1264 * specification supported by the HWRM implementation. The
1265 * interface update version is used to reflect minor changes or
1266 * bug fixes to a released HWRM interface specification.
1267 * A HWRM implementation that is compliant with this
1268 * specification shall provide value of 2 in this field.
1270 uint16_t hwrm_intf_build;
1272 * This field represents the patch version of HWRM interface
1273 * specification supported by the HWRM implementation.
1275 uint16_t hwrm_intf_patch;
1277 * This field represents the major version of HWRM firmware.
1278 * A change in firmware major version represents a major
1281 uint16_t hwrm_fw_major;
1283 * This field represents the minor version of HWRM firmware.
1284 * A change in firmware minor version represents significant
1285 * firmware functionality changes.
1287 uint16_t hwrm_fw_minor;
1289 * This field represents the build version of HWRM firmware.
1290 * A change in firmware build version represents bug fixes to
1291 * a released firmware.
1293 uint16_t hwrm_fw_build;
1295 * This field is a reserved field.
1296 * This field can be used to represent firmware branches or customer
1297 * specific releases tied to a specific (major,minor,update) version
1298 * of the HWRM firmware.
1300 uint16_t hwrm_fw_patch;
1302 * This field represents the major version of mgmt firmware.
1303 * A change in major version represents a major release.
1305 uint16_t mgmt_fw_major;
1307 * This field represents the minor version of HWRM firmware.
1308 * A change in firmware minor version represents significant
1309 * firmware functionality changes.
1311 uint16_t mgmt_fw_minor;
1313 * This field represents the build version of mgmt firmware.
1314 * A change in update version represents bug fixes.
1316 uint16_t mgmt_fw_build;
1318 * This field is a reserved field. This field can be used to
1319 * represent firmware branches or customer specific releases
1320 * tied to a specific (major,minor,update) version.
1322 uint16_t mgmt_fw_patch;
1324 * This field represents the major version of network control
1325 * firmware. A change in major version represents
1328 uint16_t netctrl_fw_major;
1330 * This field represents the minor version of network control
1331 * firmware. A change in minor version represents significant
1332 * functionality changes.
1334 uint16_t netctrl_fw_minor;
1336 * This field represents the build version of network control
1337 * firmware. A change in update version represents bug fixes.
1339 uint16_t netctrl_fw_build;
1341 * This field is a reserved field. This field can be used to
1342 * represent firmware branches or customer specific releases
1343 * tied to a specific (major,minor,update) version
1345 uint16_t netctrl_fw_patch;
1347 * This field represents the major version of RoCE firmware.
1348 * A change in major version represents a major release.
1350 uint16_t roce_fw_major;
1352 * This field represents the minor version of RoCE firmware.
1353 * A change in minor version represents significant
1354 * functionality changes.
1356 uint16_t roce_fw_minor;
1358 * This field represents the build version of RoCE firmware.
1359 * A change in update version represents bug fixes.
1361 uint16_t roce_fw_build;
1363 * This field is a reserved field. This field can be used to
1364 * represent firmware branches or customer specific releases
1365 * tied to a specific (major,minor,update) version
1367 uint16_t roce_fw_patch;
1369 * This field returns the maximum extended request length acceptable
1370 * by the device which allows requests greater than mailbox size when
1371 * used with the short cmd request format.
1373 uint16_t max_ext_req_len;
1374 uint8_t unused_1[5];
1376 * This field is used in Output records to indicate that the output
1377 * is completely written to RAM. This field should be read as '1'
1378 * to indicate that the output has been completely written.
1379 * When writing a command completion or response to an internal processor,
1380 * the order of writes has to be such that this field is written last.
1383 } __attribute__((packed));
1385 /* bd_base (size:64b/8B) */
1388 /* This value identifies the type of buffer descriptor. */
1389 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1390 #define BD_BASE_TYPE_SFT 0
1392 * Indicates that this BD is 16B long and is used for
1393 * normal L2 packet transmission.
1395 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1397 * Indicates that this BD is 1BB long and is an empty
1398 * TX BD. Not valid for use by the driver.
1400 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1402 * Indicates that this BD is 16B long and is an RX Producer
1403 * (ie. empty) buffer descriptor.
1405 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1407 * Indicates that this BD is 16B long and is an RX
1408 * Producer Buffer BD.
1410 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1412 * Indicates that this BD is 16B long and is an
1413 * RX Producer Assembly Buffer Descriptor.
1415 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1417 * Indicates that this BD is 32B long and is used for
1418 * normal L2 packet transmission.
1420 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1422 * Indicates that this BD is 32B long and is used for
1423 * L2 packet transmission for small packets that require
1426 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1427 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1428 uint8_t unused_1[7];
1429 } __attribute__((packed));
1431 /* tx_bd_short (size:128b/16B) */
1432 struct tx_bd_short {
1434 * All bits in this field must be valid on the first BD of a packet.
1435 * Only the packet_end bit must be valid for the remaining BDs
1438 uint16_t flags_type;
1439 /* This value identifies the type of buffer descriptor. */
1440 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1441 #define TX_BD_SHORT_TYPE_SFT 0
1443 * Indicates that this BD is 16B long and is used for
1444 * normal L2 packet transmission.
1446 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1447 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1449 * All bits in this field must be valid on the first BD of a packet.
1450 * Only the packet_end bit must be valid for the remaining BDs
1453 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1454 #define TX_BD_SHORT_FLAGS_SFT 6
1456 * If set to 1, the packet ends with the data in the buffer
1457 * pointed to by this descriptor. This flag must be
1458 * valid on every BD.
1460 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1462 * If set to 1, the device will not generate a completion for
1463 * this transmit packet unless there is an error in it's
1466 * is set to 0, then the packet will be completed normally.
1468 * This bit must be valid only on the first BD of a packet.
1470 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1472 * This value indicates how many 16B BD locations are consumed
1473 * in the ring by this packet.
1474 * A value of 1 indicates that this BD is the only BD (and that
1475 * the it is a short BD). A value
1476 * of 3 indicates either 3 short BDs or 1 long BD and one short
1477 * BD in the packet. A value of 0 indicates
1478 * that there are 32 BD locations in the packet (the maximum).
1480 * This field is valid only on the first BD of a packet.
1482 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1483 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1485 * This value is a hint for the length of the entire packet.
1486 * It is used by the chip to optimize internal processing.
1488 * The packet will be dropped if the hint is too short.
1490 * This field is valid only on the first BD of a packet.
1492 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1493 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1494 /* indicates packet length < 512B */
1495 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1496 /* indicates 512 <= packet length < 1KB */
1497 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1498 /* indicates 1KB <= packet length < 2KB */
1499 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1500 /* indicates packet length >= 2KB */
1501 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1502 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1503 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1505 * If set to 1, the device immediately updates the Send Consumer
1506 * Index after the buffer associated with this descriptor has
1507 * been transferred via DMA to NIC memory from host memory. An
1508 * interrupt may or may not be generated according to the state
1509 * of the interrupt avoidance mechanisms. If this bit
1510 * is set to 0, then the Consumer Index is only updated as soon
1511 * as one of the host interrupt coalescing conditions has been met.
1513 * This bit must be valid on the first BD of a packet.
1515 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1517 * This is the length of the host physical buffer this BD describes
1520 * This field must be valid on all BDs of a packet.
1524 * The opaque data field is pass through to the completion and can be
1525 * used for any data that the driver wants to associate with the
1528 * This field must be valid on the first BD of a packet.
1532 * This is the host physical address for the portion of the packet
1533 * described by this TX BD.
1535 * This value must be valid on all BDs of a packet.
1538 } __attribute__((packed));
1540 /* tx_bd_long (size:128b/16B) */
1542 /* This value identifies the type of buffer descriptor. */
1543 uint16_t flags_type;
1545 * This value indicates the type of buffer descriptor.
1548 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1549 #define TX_BD_LONG_TYPE_SFT 0
1551 * Indicates that this BD is 32B long and is used for
1552 * normal L2 packet transmission.
1554 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1555 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1557 * All bits in this field must be valid on the first BD of a packet.
1558 * Only the packet_end bit must be valid for the remaining BDs
1561 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1562 #define TX_BD_LONG_FLAGS_SFT 6
1564 * If set to 1, the packet ends with the data in the buffer
1565 * pointed to by this descriptor. This flag must be
1566 * valid on every BD.
1568 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1570 * If set to 1, the device will not generate a completion for
1571 * this transmit packet unless there is an error in it's
1574 * is set to 0, then the packet will be completed normally.
1576 * This bit must be valid only on the first BD of a packet.
1578 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1580 * This value indicates how many 16B BD locations are consumed
1581 * in the ring by this packet.
1582 * A value of 1 indicates that this BD is the only BD (and that
1583 * the it is a short BD). A value
1584 * of 3 indicates either 3 short BDs or 1 long BD and one short
1585 * BD in the packet. A value of 0 indicates
1586 * that there are 32 BD locations in the packet (the maximum).
1588 * This field is valid only on the first BD of a packet.
1590 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1591 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1593 * This value is a hint for the length of the entire packet.
1594 * It is used by the chip to optimize internal processing.
1596 * The packet will be dropped if the hint is too short.
1598 * This field is valid only on the first BD of a packet.
1600 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1601 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1602 /* indicates packet length < 512B */
1603 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1604 /* indicates 512 <= packet length < 1KB */
1605 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1606 /* indicates 1KB <= packet length < 2KB */
1607 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1608 /* indicates packet length >= 2KB */
1609 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1610 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1612 * If set to 1, the device immediately updates the Send Consumer
1613 * Index after the buffer associated with this descriptor has
1614 * been transferred via DMA to NIC memory from host memory. An
1615 * interrupt may or may not be generated according to the state
1616 * of the interrupt avoidance mechanisms. If this bit
1617 * is set to 0, then the Consumer Index is only updated as soon
1618 * as one of the host interrupt coalescing conditions has been met.
1620 * This bit must be valid on the first BD of a packet.
1622 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1624 * This is the length of the host physical buffer this BD describes
1627 * This field must be valid on all BDs of a packet.
1631 * The opaque data field is pass through to the completion and can be
1632 * used for any data that the driver wants to associate with the
1635 * This field must be valid on the first BD of a packet.
1639 * This is the host physical address for the portion of the packet
1640 * described by this TX BD.
1642 * This value must be valid on all BDs of a packet.
1645 } __attribute__((packed));
1647 /* Last 16 bytes of tx_bd_long. */
1648 /* tx_bd_long_hi (size:128b/16B) */
1649 struct tx_bd_long_hi {
1651 * All bits in this field must be valid on the first BD of a packet.
1652 * Their value on other BDs of the packet will be ignored.
1656 * If set to 1, the controller replaces the TCP/UPD checksum
1657 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1658 * checksum field of the encapsulated TCP/UDP packets with the
1659 * hardware calculated TCP/UDP checksum for the packet associated
1660 * with this descriptor. The flag is ignored if the LSO flag is set.
1662 * This bit must be valid on the first BD of a packet.
1664 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1666 * If set to 1, the controller replaces the IP checksum of the
1667 * normal packets, or the inner IP checksum of the encapsulated
1668 * packets with the hardware calculated IP checksum for the
1669 * packet associated with this descriptor.
1671 * This bit must be valid on the first BD of a packet.
1673 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1675 * If set to 1, the controller will not append an Ethernet CRC
1676 * to the end of the frame.
1678 * This bit must be valid on the first BD of a packet.
1680 * Packet must be 64B or longer when this flag is set. It is not
1681 * useful to use this bit with any form of TX offload such as
1682 * CSO or LSO. The intent is that the packet from the host already
1683 * has a valid Ethernet CRC on the packet.
1685 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1687 * If set to 1, the device will record the time at which the packet
1688 * was actually transmitted at the TX MAC.
1690 * This bit must be valid on the first BD of a packet.
1692 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1694 * If set to 1, The controller replaces the tunnel IP checksum
1695 * field with hardware calculated IP checksum for the IP header
1696 * of the packet associated with this descriptor.
1698 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1699 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1700 * bit is set, outer UDP checksum will be calculated for the following
1702 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1703 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1704 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1705 * checksum will not be calculated.
1706 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1707 * as part of LSO operation.
1709 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1711 * If set to 1, the device will treat this packet with LSO(Large
1712 * Send Offload) processing for both normal or encapsulated
1713 * packets, which is a form of TCP segmentation. When this bit
1714 * is 1, the hdr_size and mss fields must be valid. The driver
1715 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1716 * flags since the controller will replace the appropriate
1717 * checksum fields for segmented packets.
1719 * When this bit is 1, the hdr_size and mss fields must be valid.
1721 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1723 * If set to zero when LSO is '1', then the IPID will be treated
1724 * as a 16b number and will be wrapped if it exceeds a value of
1727 * If set to one when LSO is '1', then the IPID will be treated
1728 * as a 15b number and will be wrapped if it exceeds a value 0f
1731 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1733 * If set to zero when LSO is '1', then the IPID of the tunnel
1734 * IP header will not be modified during LSO operations.
1736 * If set to one when LSO is '1', then the IPID of the tunnel
1737 * IP header will be incremented for each subsequent segment of an
1740 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1743 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1745 * If set to '1', then the RoCE ICRC will be appended to the
1746 * packet. Packet must be a valid RoCE format packet.
1748 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1750 * If set to '1', then the FCoE CRC will be appended to the
1751 * packet. Packet must be a valid FCoE format packet.
1753 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1756 * When LSO is '1', this field must contain the offset of the
1757 * TCP payload from the beginning of the packet in as
1758 * 16b words. In case of encapsulated/tunneling packet, this field
1759 * contains the offset of the inner TCP payload from beginning of the
1760 * packet as 16-bit words.
1762 * This value must be valid on the first BD of a packet.
1764 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1765 #define TX_BD_LONG_HDR_SIZE_SFT 0
1768 * This is the MSS value that will be used to do the LSO processing.
1769 * The value is the length in bytes of the TCP payload for each
1770 * segment generated by the LSO operation.
1772 * This value must be valid on the first BD of a packet.
1774 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1775 #define TX_BD_LONG_MSS_SFT 0
1778 * This value selects a CFA action to perform on the packet.
1779 * Set this value to zero if no CFA action is desired.
1781 * This value must be valid on the first BD of a packet.
1783 uint16_t cfa_action;
1785 * This value is action meta-data that defines CFA edit operations
1786 * that are done in addition to any action editing.
1789 /* When key=1, This is the VLAN tag VID value. */
1790 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1791 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1792 /* When key=1, This is the VLAN tag DE value. */
1793 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1794 /* When key=1, This is the VLAN tag PRI value. */
1795 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1796 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1797 /* When key=1, This is the VLAN tag TPID select value. */
1798 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1799 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1801 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1803 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1805 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1807 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1809 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1810 /* Value programmed in CFA VLANTPID register. */
1811 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1812 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1813 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1814 /* When key=1, This is the VLAN tag TPID select value. */
1815 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1816 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1818 * This field identifies the type of edit to be performed
1821 * This value must be valid on the first BD of a packet.
1823 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1824 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1826 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1828 * - meta[17:16] - TPID select value (0 = 0x8100).
1829 * - meta[15:12] - PRI/DE value.
1830 * - meta[11:0] - VID value.
1832 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1833 #define TX_BD_LONG_CFA_META_KEY_LAST \
1834 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1835 } __attribute__((packed));
1838 * This structure is used to inform the NIC of packet data that needs to be
1839 * transmitted with additional processing that requires extra data such as
1840 * VLAN insertion plus attached inline data. This BD type may be used to
1841 * improve latency for small packets needing the additional extended features
1842 * supported by long BDs.
1844 /* tx_bd_long_inline (size:256b/32B) */
1845 struct tx_bd_long_inline {
1846 uint16_t flags_type;
1847 /* This value identifies the type of buffer descriptor. */
1848 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1849 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1851 * This type of BD is 32B long and is used for inline L2 packet
1854 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1855 #define TX_BD_LONG_INLINE_TYPE_LAST \
1856 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1858 * All bits in this field may be set on the first BD of a packet.
1859 * Only the packet_end bit may be set in non-first BDs.
1861 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1862 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1864 * If set to 1, the packet ends with the data in the buffer
1865 * pointed to by this descriptor. This flag must be
1866 * valid on every BD.
1868 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1870 * If set to 1, the device will not generate a completion for
1871 * this transmit packet unless there is an error in its processing.
1872 * If this bit is set to 0, then the packet will be completed
1875 * This bit may be set only on the first BD of a packet.
1877 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1879 * This value indicates how many 16B BD locations are consumed
1880 * in the ring by this packet, including the BD and inline
1883 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1884 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1885 /* This field is deprecated. */
1886 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1887 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1889 * If set to 1, the device immediately updates the Send Consumer
1890 * Index after the buffer associated with this descriptor has
1891 * been transferred via DMA to NIC memory from host memory. An
1892 * interrupt may or may not be generated according to the state
1893 * of the interrupt avoidance mechanisms. If this bit
1894 * is set to 0, then the Consumer Index is only updated as soon
1895 * as one of the host interrupt coalescing conditions has been met.
1897 * This bit must be valid on the first BD of a packet.
1899 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1901 * This is the length of the inline data, not including BD length, in
1903 * The maximum value is 480.
1905 * This field must be valid on all BDs of a packet.
1909 * The opaque data field is passed through to the completion and can be
1910 * used for any data that the driver wants to associate with the transmit
1913 * This field must be valid on the first BD of a packet.
1918 * All bits in this field must be valid on the first BD of a packet.
1919 * Their value on other BDs of the packet is ignored.
1923 * If set to 1, the controller replaces the TCP/UPD checksum
1924 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1925 * checksum field of the encapsulated TCP/UDP packets with the
1926 * hardware calculated TCP/UDP checksum for the packet associated
1927 * with this descriptor. The flag is ignored if the LSO flag is set.
1929 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1931 * If set to 1, the controller replaces the IP checksum of the
1932 * normal packets, or the inner IP checksum of the encapsulated
1933 * packets with the hardware calculated IP checksum for the
1934 * packet associated with this descriptor.
1936 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1938 * If set to 1, the controller will not append an Ethernet CRC
1939 * to the end of the frame.
1941 * Packet must be 64B or longer when this flag is set. It is not
1942 * useful to use this bit with any form of TX offload such as
1943 * CSO or LSO. The intent is that the packet from the host already
1944 * has a valid Ethernet CRC on the packet.
1946 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1948 * If set to 1, the device will record the time at which the packet
1949 * was actually transmitted at the TX MAC.
1951 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1953 * If set to 1, the controller replaces the tunnel IP checksum
1954 * field with hardware calculated IP checksum for the IP header
1955 * of the packet associated with this descriptor. The hardware
1956 * updates an outer UDP checksum if it is non-zero.
1958 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1960 * This bit must be 0 for BDs of this type. LSO is not supported with
1963 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1964 /* Since LSO is not supported with inline BDs, this bit is not used. */
1965 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1966 /* Since LSO is not supported with inline BDs, this bit is not used. */
1967 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1969 * If set to '1', then the RoCE ICRC will be appended to the
1970 * packet. Packet must be a valid RoCE format packet.
1972 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1974 * If set to '1', then the FCoE CRC will be appended to the
1975 * packet. Packet must be a valid FCoE format packet.
1977 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1982 * This value selects a CFA action to perform on the packet.
1983 * Set this value to zero if no CFA action is desired.
1985 * This value must be valid on the first BD of a packet.
1987 uint16_t cfa_action;
1989 * This value is action meta-data that defines CFA edit operations
1990 * that are done in addition to any action editing.
1993 /* When key = 1, this is the VLAN tag VID value. */
1994 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1996 /* When key = 1, this is the VLAN tag DE value. */
1997 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1998 /* When key = 1, this is the VLAN tag PRI value. */
1999 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2000 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2001 /* When key = 1, this is the VLAN tag TPID select value. */
2002 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2003 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2005 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2006 (UINT32_C(0x0) << 16)
2008 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2009 (UINT32_C(0x1) << 16)
2011 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2012 (UINT32_C(0x2) << 16)
2014 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2015 (UINT32_C(0x3) << 16)
2017 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2018 (UINT32_C(0x4) << 16)
2019 /* Value programmed in CFA VLANTPID register. */
2020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2021 (UINT32_C(0x5) << 16)
2022 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2023 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2024 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2026 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2028 * This field identifies the type of edit to be performed
2031 * This value must be valid on the first BD of a packet.
2033 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2034 UINT32_C(0xf0000000)
2035 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2037 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2038 (UINT32_C(0x0) << 28)
2040 * - meta[17:16] - TPID select value (0 = 0x8100).
2041 * - meta[15:12] - PRI/DE value.
2042 * - meta[11:0] - VID value.
2044 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2045 (UINT32_C(0x1) << 28)
2046 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2047 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2048 } __attribute__((packed));
2050 /* tx_bd_empty (size:128b/16B) */
2051 struct tx_bd_empty {
2052 /* This value identifies the type of buffer descriptor. */
2054 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2055 #define TX_BD_EMPTY_TYPE_SFT 0
2057 * Indicates that this BD is 1BB long and is an empty
2058 * TX BD. Not valid for use by the driver.
2060 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2061 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2062 uint8_t unused_1[3];
2064 uint8_t unused_3[3];
2065 uint8_t unused_4[8];
2066 } __attribute__((packed));
2068 /* rx_prod_pkt_bd (size:128b/16B) */
2069 struct rx_prod_pkt_bd {
2070 /* This value identifies the type of buffer descriptor. */
2071 uint16_t flags_type;
2072 /* This value identifies the type of buffer descriptor. */
2073 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2074 #define RX_PROD_PKT_BD_TYPE_SFT 0
2076 * Indicates that this BD is 16B long and is an RX Producer
2077 * (ie. empty) buffer descriptor.
2079 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2080 #define RX_PROD_PKT_BD_TYPE_LAST \
2081 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2082 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2083 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2085 * If set to 1, the packet will be placed at the address plus
2086 * 2B. The 2 Bytes of padding will be written as zero.
2088 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2090 * If set to 1, the packet write will be padded out to the
2091 * nearest cache-line with zero value padding.
2093 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2095 * This value is the number of additional buffers in the ring that
2096 * describe the buffer space to be consumed for the this packet.
2097 * If the value is zero, then the packet must fit within the
2098 * space described by this BD. If this value is 1 or more, it
2099 * indicates how many additional "buffer" BDs are in the ring
2100 * immediately following this BD to be used for the same
2103 * Even if the packet to be placed does not need all the
2104 * additional buffers, they will be consumed anyway.
2106 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2107 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2109 * This is the length in Bytes of the host physical buffer where
2110 * data for the packet may be placed in host memory.
2114 * The opaque data field is pass through to the completion and can be
2115 * used for any data that the driver wants to associate with this
2116 * receive buffer set.
2120 * This is the host physical address where data for the packet may
2121 * by placed in host memory.
2124 } __attribute__((packed));
2126 /* rx_prod_bfr_bd (size:128b/16B) */
2127 struct rx_prod_bfr_bd {
2128 /* This value identifies the type of buffer descriptor. */
2129 uint16_t flags_type;
2130 /* This value identifies the type of buffer descriptor. */
2131 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2132 #define RX_PROD_BFR_BD_TYPE_SFT 0
2134 * Indicates that this BD is 16B long and is an RX
2135 * Producer Buffer BD.
2137 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2138 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2139 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2140 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2142 * This is the length in Bytes of the host physical buffer where
2143 * data for the packet may be placed in host memory.
2146 /* This field is not used. */
2149 * This is the host physical address where data for the packet may
2150 * by placed in host memory.
2153 } __attribute__((packed));
2155 /* rx_prod_agg_bd (size:128b/16B) */
2156 struct rx_prod_agg_bd {
2157 /* This value identifies the type of buffer descriptor. */
2158 uint16_t flags_type;
2159 /* This value identifies the type of buffer descriptor. */
2160 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2161 #define RX_PROD_AGG_BD_TYPE_SFT 0
2163 * Indicates that this BD is 16B long and is an
2164 * RX Producer Assembly Buffer Descriptor.
2166 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2167 #define RX_PROD_AGG_BD_TYPE_LAST \
2168 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2169 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2170 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2172 * If set to 1, the packet write will be padded out to the
2173 * nearest cache-line with zero value padding.
2175 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2177 * This is the length in Bytes of the host physical buffer where
2178 * data for the packet may be placed in host memory.
2182 * The opaque data field is pass through to the completion and can be
2183 * used for any data that the driver wants to associate with this
2184 * receive assembly buffer.
2188 * This is the host physical address where data for the packet may
2189 * by placed in host memory.
2192 } __attribute__((packed));
2194 /* cmpl_base (size:128b/16B) */
2198 * This field indicates the exact type of the completion.
2199 * By convention, the LSB identifies the length of the
2200 * record in 16B units. Even values indicate 16B
2201 * records. Odd values indicate 32B
2204 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2205 #define CMPL_BASE_TYPE_SFT 0
2208 * Completion of TX packet. Length = 16B
2210 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2213 * Completion of and L2 RX packet. Length = 32B
2215 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2217 * RX Aggregation Buffer completion :
2218 * Completion of an L2 aggregation buffer in support of
2219 * TPA, HDS, or Jumbo packet completion. Length = 16B
2221 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2223 * RX L2 TPA Start Completion:
2224 * Completion at the beginning of a TPA operation.
2227 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2229 * RX L2 TPA End Completion:
2230 * Completion at the end of a TPA operation.
2233 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2235 * Statistics Ejection Completion:
2236 * Completion of statistics data ejection buffer.
2239 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2241 * HWRM Command Completion:
2242 * Completion of an HWRM command.
2244 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2245 /* Forwarded HWRM Request */
2246 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2247 /* Forwarded HWRM Response */
2248 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2249 /* HWRM Asynchronous Event Information */
2250 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2251 /* CQ Notification */
2252 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2253 /* SRQ Threshold Event */
2254 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2255 /* DBQ Threshold Event */
2256 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2257 /* QP Async Notification */
2258 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2259 /* Function Async Notification */
2260 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2261 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2267 * This value is written by the NIC such that it will be different
2268 * for each pass through the completion queue. The even passes
2269 * will write 1. The odd passes will write 0.
2272 #define CMPL_BASE_V UINT32_C(0x1)
2273 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2274 #define CMPL_BASE_INFO3_SFT 1
2277 } __attribute__((packed));
2279 /* tx_cmpl (size:128b/16B) */
2281 uint16_t flags_type;
2283 * This field indicates the exact type of the completion.
2284 * By convention, the LSB identifies the length of the
2285 * record in 16B units. Even values indicate 16B
2286 * records. Odd values indicate 32B
2289 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2290 #define TX_CMPL_TYPE_SFT 0
2293 * Completion of TX packet. Length = 16B
2295 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2296 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2297 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2298 #define TX_CMPL_FLAGS_SFT 6
2300 * When this bit is '1', it indicates a packet that has an
2301 * error of some type. Type of error is indicated in
2304 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2306 * When this bit is '1', it indicates that the packet completed
2307 * was transmitted using the push acceleration data provided
2308 * by the driver. When this bit is '0', it indicates that the
2309 * packet had not push acceleration data written or was executed
2310 * as a normal packet even though push data was provided.
2312 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2313 /* unused1 is 16 b */
2316 * This is a copy of the opaque field from the first TX BD of this
2317 * transmitted packet.
2322 * This value is written by the NIC such that it will be different
2323 * for each pass through the completion queue. The even passes
2324 * will write 1. The odd passes will write 0.
2326 #define TX_CMPL_V UINT32_C(0x1)
2327 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2328 #define TX_CMPL_ERRORS_SFT 1
2330 * This error indicates that there was some sort of problem
2331 * with the BDs for the packet.
2333 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2334 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2336 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2339 * BDs were not formatted correctly.
2341 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2342 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2343 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2345 * When this bit is '1', it indicates that the length of
2346 * the packet was zero. No packet was transmitted.
2348 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2350 * When this bit is '1', it indicates that the packet
2351 * was longer than the programmed limit in TDI. No
2352 * packet was transmitted.
2354 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2356 * When this bit is '1', it indicates that one or more of the
2357 * BDs associated with this packet generated a PCI error.
2358 * This probably means the address was not valid.
2360 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2362 * When this bit is '1', it indicates that the packet was longer
2363 * than indicated by the hint. No packet was transmitted.
2365 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2367 * When this bit is '1', it indicates that the packet was
2368 * dropped due to Poison TLP error on one or more of the
2369 * TLPs in the PXP completion.
2371 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2372 /* unused2 is 16 b */
2374 /* unused3 is 32 b */
2376 } __attribute__((packed));
2378 /* rx_pkt_cmpl (size:128b/16B) */
2379 struct rx_pkt_cmpl {
2380 uint16_t flags_type;
2382 * This field indicates the exact type of the completion.
2383 * By convention, the LSB identifies the length of the
2384 * record in 16B units. Even values indicate 16B
2385 * records. Odd values indicate 32B
2388 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2389 #define RX_PKT_CMPL_TYPE_SFT 0
2392 * Completion of and L2 RX packet. Length = 32B
2394 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2395 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2396 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2397 #define RX_PKT_CMPL_FLAGS_SFT 6
2399 * When this bit is '1', it indicates a packet that has an
2400 * error of some type. Type of error is indicated in
2403 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2404 /* This field indicates how the packet was placed in the buffer. */
2405 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2406 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2409 * Packet was placed using normal algorithm.
2411 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2414 * Packet was placed using jumbo algorithm.
2416 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2418 * Header/Data Separation:
2419 * Packet was placed using Header/Data separation algorithm.
2420 * The separation location is indicated by the itype field.
2422 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2423 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2424 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2425 /* This bit is '1' if the RSS field in this completion is valid. */
2426 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2428 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2430 * This value indicates what the inner packet determined for the
2433 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2434 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2437 * Indicates that the packet type was not known.
2439 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2440 (UINT32_C(0x0) << 12)
2443 * Indicates that the packet was an IP packet, but further
2444 * classification was not possible.
2446 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2447 (UINT32_C(0x1) << 12)
2450 * Indicates that the packet was IP and TCP.
2451 * This indicates that the payload_offset field is valid.
2453 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2454 (UINT32_C(0x2) << 12)
2457 * Indicates that the packet was IP and UDP.
2458 * This indicates that the payload_offset field is valid.
2460 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2461 (UINT32_C(0x3) << 12)
2464 * Indicates that the packet was recognized as a FCoE.
2465 * This also indicates that the payload_offset field is valid.
2467 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2468 (UINT32_C(0x4) << 12)
2471 * Indicates that the packet was recognized as a RoCE.
2472 * This also indicates that the payload_offset field is valid.
2474 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2475 (UINT32_C(0x5) << 12)
2478 * Indicates that the packet was recognized as ICMP.
2479 * This indicates that the payload_offset field is valid.
2481 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2482 (UINT32_C(0x7) << 12)
2484 * PtP packet wo/timestamp:
2485 * Indicates that the packet was recognized as a PtP
2488 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2489 (UINT32_C(0x8) << 12)
2491 * PtP packet w/timestamp:
2492 * Indicates that the packet was recognized as a PtP
2493 * packet and that a timestamp was taken for the packet.
2495 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2496 (UINT32_C(0x9) << 12)
2497 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2498 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2500 * This is the length of the data for the packet stored in the
2501 * buffer(s) identified by the opaque value. This includes
2502 * the packet BD and any associated buffer BDs. This does not include
2503 * the the length of any data places in aggregation BDs.
2507 * This is a copy of the opaque field from the RX BD this completion
2511 uint8_t agg_bufs_v1;
2513 * This value is written by the NIC such that it will be different
2514 * for each pass through the completion queue. The even passes
2515 * will write 1. The odd passes will write 0.
2517 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2519 * This value is the number of aggregation buffers that follow this
2520 * entry in the completion ring that are a part of this packet.
2521 * If the value is zero, then the packet is completely contained
2522 * in the buffer space provided for the packet in the RX ring.
2524 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2525 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2526 /* unused1 is 2 b */
2527 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2528 #define RX_PKT_CMPL_UNUSED1_SFT 6
2530 * This is the RSS hash type for the packet. The value is packed
2531 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2533 * The value of tuple_extrac_op provides the information about
2534 * what fields the hash was computed on.
2535 * * 0: The RSS hash was computed over source IP address,
2536 * destination IP address, source port, and destination port of inner
2537 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2538 * the packet headers are considered inner packet headers for the RSS
2539 * hash computation purpose.
2540 * * 1: The RSS hash was computed over source IP address and destination
2541 * IP address of inner IP header. Note: For non-tunneled packets,
2542 * the packet headers are considered inner packet headers for the RSS
2543 * hash computation purpose.
2544 * * 2: The RSS hash was computed over source IP address,
2545 * destination IP address, source port, and destination port of
2546 * IP and TCP or UDP headers of outer tunnel headers.
2547 * Note: For non-tunneled packets, this value is not applicable.
2548 * * 3: The RSS hash was computed over source IP address and
2549 * destination IP address of IP header of outer tunnel headers.
2550 * Note: For non-tunneled packets, this value is not applicable.
2552 * Note that 4-tuples values listed above are applicable
2553 * for layer 4 protocols supported and enabled for RSS in the hardware,
2554 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2555 * enabled for TCP traffic only, then the values of tuple_extract_op
2556 * corresponding to 4-tuples are only valid for TCP traffic.
2558 uint8_t rss_hash_type;
2560 * This value indicates the offset in bytes from the beginning of the packet
2561 * where the inner payload starts. This value is valid for TCP, UDP,
2562 * FCoE, and RoCE packets.
2564 * A value of zero indicates that header is 256B into the packet.
2566 uint8_t payload_offset;
2567 /* unused2 is 8 b */
2570 * This value is the RSS hash value calculated for the packet
2571 * based on the mode bits and key value in the VNIC.
2574 } __attribute__((packed));
2576 /* Last 16 bytes of rx_pkt_cmpl. */
2577 /* rx_pkt_cmpl_hi (size:128b/16B) */
2578 struct rx_pkt_cmpl_hi {
2581 * This indicates that the ip checksum was calculated for the
2582 * inner packet and that the ip_cs_error field indicates if there
2585 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2587 * This indicates that the TCP, UDP or ICMP checksum was
2588 * calculated for the inner packet and that the l4_cs_error field
2589 * indicates if there was an error.
2591 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2593 * This indicates that the ip checksum was calculated for the
2594 * tunnel header and that the t_ip_cs_error field indicates if there
2597 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2599 * This indicates that the UDP checksum was
2600 * calculated for the tunnel packet and that the t_l4_cs_error field
2601 * indicates if there was an error.
2603 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2604 /* This value indicates what format the metadata field is. */
2605 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2606 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2607 /* No metadata informtaion. Value is zero. */
2608 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2609 (UINT32_C(0x0) << 4)
2611 * The metadata field contains the VLAN tag and TPID value.
2612 * - metadata[11:0] contains the vlan VID value.
2613 * - metadata[12] contains the vlan DE value.
2614 * - metadata[15:13] contains the vlan PRI value.
2615 * - metadata[31:16] contains the vlan TPID value.
2617 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2618 (UINT32_C(0x1) << 4)
2620 * If ext_meta_format is equal to 1, the metadata field
2621 * contains the lower 16b of the tunnel ID value, justified
2623 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2624 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2625 * - NVGRE = TNI[23:0] -> Tenant Network ID
2626 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2627 * - IPV4 = 0 (not populated)
2628 * - IPV6 = Flow Label[19:0]
2629 * - PPPoE = sessionID[15:0]
2630 * - MPLs = Outer label[19:0]
2631 * - UPAR = Selected[31:0] with bit mask
2633 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2634 (UINT32_C(0x2) << 4)
2636 * if ext_meta_format is equal to 1, metadata field contains
2637 * 16b metadata from the prepended header (chdr_data).
2639 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2640 (UINT32_C(0x3) << 4)
2642 * If ext_meta_format is equal to 1, the metadata field contains
2643 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2645 * - metadata[8:0] contains the outer_l3_offset.
2646 * - metadata[17:9] contains the inner_l2_offset.
2647 * - metadata[26:18] contains the inner_l3_offset.
2648 * - metadata[31:27] contains the inner_l4_size.
2650 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2651 (UINT32_C(0x4) << 4)
2652 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2653 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2655 * This field indicates the IP type for the inner-most IP header.
2656 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2657 * This value is only valid if itype indicates a packet
2658 * with an IP header.
2660 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2662 * This indicates that the complete 1's complement checksum was
2663 * calculated for the packet.
2665 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2667 * The combination of this value and meta_format indicated what
2668 * format the metadata field is.
2670 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2671 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2673 * This value is the complete 1's complement checksum calculated from
2674 * the start of the outer L3 header to the end of the packet (not
2675 * including the ethernet crc). It is valid when the
2676 * 'complete_checksum_calc' flag is set.
2678 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2679 UINT32_C(0xffff0000)
2680 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2682 * This is data from the CFA block as indicated by the meta_format
2686 /* When meta_format=1, this value is the VLAN VID. */
2687 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2688 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2689 /* When meta_format=1, this value is the VLAN DE. */
2690 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2691 /* When meta_format=1, this value is the VLAN PRI. */
2692 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2693 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2694 /* When meta_format=1, this value is the VLAN TPID. */
2695 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2696 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2699 * This value is written by the NIC such that it will be different
2700 * for each pass through the completion queue. The even passes
2701 * will write 1. The odd passes will write 0.
2703 #define RX_PKT_CMPL_V2 \
2705 #define RX_PKT_CMPL_ERRORS_MASK \
2707 #define RX_PKT_CMPL_ERRORS_SFT 1
2709 * This error indicates that there was some sort of problem with
2710 * the BDs for the packet that was found after part of the
2711 * packet was already placed. The packet should be treated as
2714 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2716 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2717 /* No buffer error */
2718 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2719 (UINT32_C(0x0) << 1)
2722 * Packet did not fit into packet buffer provided.
2723 * For regular placement, this means the packet did not fit
2724 * in the buffer provided. For HDS and jumbo placement, this
2725 * means that the packet could not be placed into 7 physical
2728 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2729 (UINT32_C(0x1) << 1)
2732 * All BDs needed for the packet were not on-chip when
2733 * the packet arrived.
2735 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2736 (UINT32_C(0x2) << 1)
2739 * BDs were not formatted correctly.
2741 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2742 (UINT32_C(0x3) << 1)
2745 * There was a bad_format error on the previous operation
2747 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2748 (UINT32_C(0x5) << 1)
2749 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2750 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2752 * This indicates that there was an error in the IP header
2755 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2758 * This indicates that there was an error in the TCP, UDP
2761 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2764 * This indicates that there was an error in the tunnel
2765 * IP header checksum.
2767 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2770 * This indicates that there was an error in the tunnel
2773 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2776 * This indicates that there was a CRC error on either an FCoE
2777 * or RoCE packet. The itype indicates the packet type.
2779 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2782 * This indicates that there was an error in the tunnel
2783 * portion of the packet when this
2784 * field is non-zero.
2786 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2788 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2790 * No additional error occurred on the tunnel portion
2791 * or the packet of the packet does not have a tunnel.
2793 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2794 (UINT32_C(0x0) << 9)
2796 * Indicates that IP header version does not match
2797 * expectation from L2 Ethertype for IPv4 and IPv6
2798 * in the tunnel header.
2800 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2801 (UINT32_C(0x1) << 9)
2803 * Indicates that header length is out of range in the
2804 * tunnel header. Valid for
2807 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2808 (UINT32_C(0x2) << 9)
2810 * Indicates that the physical packet is shorter than that
2811 * claimed by the PPPoE header length for a tunnel PPPoE
2814 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2815 (UINT32_C(0x3) << 9)
2817 * Indicates that physical packet is shorter than that claimed
2818 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2819 * tunnel packet packets.
2821 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2822 (UINT32_C(0x4) << 9)
2824 * Indicates that the physical packet is shorter than that
2825 * claimed by the tunnel UDP header length for a tunnel
2826 * UDP packet that is not fragmented.
2828 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2829 (UINT32_C(0x5) << 9)
2831 * indicates that the IPv4 TTL or IPv6 hop limit check
2832 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2833 * for IPv4, and IPv6.
2835 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2836 (UINT32_C(0x6) << 9)
2837 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2838 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2840 * This indicates that there was an error in the inner
2841 * portion of the packet when this
2842 * field is non-zero.
2844 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2846 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2848 * No additional error occurred on the tunnel portion
2849 * or the packet of the packet does not have a tunnel.
2851 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2852 (UINT32_C(0x0) << 12)
2854 * Indicates that IP header version does not match
2855 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2856 * option other than VFT was parsed on
2859 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2860 (UINT32_C(0x1) << 12)
2862 * indicates that header length is out of range. Valid for
2865 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2866 (UINT32_C(0x2) << 12)
2868 * indicates that the IPv4 TTL or IPv6 hop limit check
2869 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2871 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2872 (UINT32_C(0x3) << 12)
2874 * Indicates that physical packet is shorter than that
2875 * claimed by the l3 header length. Valid for IPv4,
2876 * IPv6 packet or RoCE packets.
2878 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2879 (UINT32_C(0x4) << 12)
2881 * Indicates that the physical packet is shorter than that
2882 * claimed by the UDP header length for a UDP packet that is
2885 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2886 (UINT32_C(0x5) << 12)
2888 * Indicates that TCP header length > IP payload. Valid for
2891 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2892 (UINT32_C(0x6) << 12)
2893 /* Indicates that TCP header length < 5. Valid for TCP. */
2894 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2895 (UINT32_C(0x7) << 12)
2897 * Indicates that TCP option headers result in a TCP header
2898 * size that does not match data offset in TCP header. Valid
2901 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2902 (UINT32_C(0x8) << 12)
2903 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2904 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2906 * This field identifies the CFA action rule that was used for this
2912 * This value holds the reordering sequence number for the packet.
2913 * If the reordering sequence is not valid, then this value is zero.
2914 * The reordering domain for the packet is in the bottom 8 to 10b of
2915 * the rss_hash value. The bottom 20b of this value contain the
2916 * ordering domain value for the packet.
2918 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2919 #define RX_PKT_CMPL_REORDER_SFT 0
2920 } __attribute__((packed));
2923 * This TPA completion structure is used on devices where the
2924 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
2926 /* rx_tpa_start_cmpl (size:128b/16B) */
2927 struct rx_tpa_start_cmpl {
2928 uint16_t flags_type;
2930 * This field indicates the exact type of the completion.
2931 * By convention, the LSB identifies the length of the
2932 * record in 16B units. Even values indicate 16B
2933 * records. Odd values indicate 32B
2936 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2937 #define RX_TPA_START_CMPL_TYPE_SFT 0
2939 * RX L2 TPA Start Completion:
2940 * Completion at the beginning of a TPA operation.
2943 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2944 #define RX_TPA_START_CMPL_TYPE_LAST \
2945 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2946 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2947 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2948 /* This bit will always be '0' for TPA start completions. */
2949 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2950 /* This field indicates how the packet was placed in the buffer. */
2951 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2952 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2955 * TPA Packet was placed using jumbo algorithm. This means
2956 * that the first buffer will be filled with data before
2957 * moving to aggregation buffers. Each aggregation buffer
2958 * will be filled before moving to the next aggregation
2961 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2962 (UINT32_C(0x1) << 7)
2964 * Header/Data Separation:
2965 * Packet was placed using Header/Data separation algorithm.
2966 * The separation location is indicated by the itype field.
2968 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2969 (UINT32_C(0x2) << 7)
2972 * Packet will be placed using GRO/Jumbo where the first
2973 * packet is filled with data. Subsequent packets will be
2974 * placed such that any one packet does not span two
2975 * aggregation buffers unless it starts at the beginning of
2976 * an aggregation buffer.
2978 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2979 (UINT32_C(0x5) << 7)
2981 * GRO/Header-Data Separation:
2982 * Packet will be placed using GRO/HDS where the header
2983 * is in the first packet.
2984 * Payload of each packet will be
2985 * placed such that any one packet does not span two
2986 * aggregation buffers unless it starts at the beginning of
2987 * an aggregation buffer.
2989 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2990 (UINT32_C(0x6) << 7)
2991 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2992 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2993 /* This bit is '1' if the RSS field in this completion is valid. */
2994 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2996 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2998 * This value indicates what the inner packet determined for the
3001 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3002 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
3005 * Indicates that the packet was IP and TCP.
3007 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
3008 (UINT32_C(0x2) << 12)
3009 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
3010 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
3012 * This value indicates the amount of packet data written to the
3013 * buffer the opaque field in this completion corresponds to.
3017 * This is a copy of the opaque field from the RX BD this completion
3022 * This value is written by the NIC such that it will be different
3023 * for each pass through the completion queue. The even passes
3024 * will write 1. The odd passes will write 0.
3028 * This value is written by the NIC such that it will be different
3029 * for each pass through the completion queue. The even passes
3030 * will write 1. The odd passes will write 0.
3032 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3033 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3035 * This is the RSS hash type for the packet. The value is packed
3036 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3038 * The value of tuple_extrac_op provides the information about
3039 * what fields the hash was computed on.
3040 * * 0: The RSS hash was computed over source IP address,
3041 * destination IP address, source port, and destination port of inner
3042 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3043 * the packet headers are considered inner packet headers for the RSS
3044 * hash computation purpose.
3045 * * 1: The RSS hash was computed over source IP address and destination
3046 * IP address of inner IP header. Note: For non-tunneled packets,
3047 * the packet headers are considered inner packet headers for the RSS
3048 * hash computation purpose.
3049 * * 2: The RSS hash was computed over source IP address,
3050 * destination IP address, source port, and destination port of
3051 * IP and TCP or UDP headers of outer tunnel headers.
3052 * Note: For non-tunneled packets, this value is not applicable.
3053 * * 3: The RSS hash was computed over source IP address and
3054 * destination IP address of IP header of outer tunnel headers.
3055 * Note: For non-tunneled packets, this value is not applicable.
3057 * Note that 4-tuples values listed above are applicable
3058 * for layer 4 protocols supported and enabled for RSS in the hardware,
3059 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3060 * enabled for TCP traffic only, then the values of tuple_extract_op
3061 * corresponding to 4-tuples are only valid for TCP traffic.
3063 uint8_t rss_hash_type;
3065 * This is the aggregation ID that the completion is associated
3066 * with. Use this number to correlate the TPA start completion
3067 * with the TPA end completion.
3070 /* unused2 is 9 b */
3071 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3072 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3074 * This is the aggregation ID that the completion is associated
3075 * with. Use this number to correlate the TPA start completion
3076 * with the TPA end completion.
3078 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3079 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3081 * This value is the RSS hash value calculated for the packet
3082 * based on the mode bits and key value in the VNIC.
3085 } __attribute__((packed));
3088 * Last 16 bytes of rx_tpa_start_cmpl.
3090 * This TPA completion structure is used on devices where the
3091 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3093 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3094 struct rx_tpa_start_cmpl_hi {
3097 * This indicates that the ip checksum was calculated for the
3098 * inner packet and that the sum passed for all segments
3099 * included in the aggregation.
3101 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3103 * This indicates that the TCP, UDP or ICMP checksum was
3104 * calculated for the inner packet and that the sum passed
3105 * for all segments included in the aggregation.
3107 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3109 * This indicates that the ip checksum was calculated for the
3110 * tunnel header and that the sum passed for all segments
3111 * included in the aggregation.
3113 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3115 * This indicates that the UDP checksum was
3116 * calculated for the tunnel packet and that the sum passed for
3117 * all segments included in the aggregation.
3119 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3120 /* This value indicates what format the metadata field is. */
3121 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3122 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3123 /* No metadata information. Value is zero. */
3124 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3125 (UINT32_C(0x0) << 4)
3127 * The metadata field contains the VLAN tag and TPID value.
3128 * - metadata[11:0] contains the vlan VID value.
3129 * - metadata[12] contains the vlan DE value.
3130 * - metadata[15:13] contains the vlan PRI value.
3131 * - metadata[31:16] contains the vlan TPID value.
3133 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3134 (UINT32_C(0x1) << 4)
3135 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3136 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
3138 * This field indicates the IP type for the inner-most IP header.
3139 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3141 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3143 * This is data from the CFA block as indicated by the meta_format
3147 /* When meta_format=1, this value is the VLAN VID. */
3148 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3149 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3150 /* When meta_format=1, this value is the VLAN DE. */
3151 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3152 /* When meta_format=1, this value is the VLAN PRI. */
3153 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3154 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3155 /* When meta_format=1, this value is the VLAN TPID. */
3156 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3157 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3160 * This value is written by the NIC such that it will be different
3161 * for each pass through the completion queue. The even passes
3162 * will write 1. The odd passes will write 0.
3164 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3166 * This field identifies the CFA action rule that was used for this
3171 * This is the size in bytes of the inner most L4 header.
3172 * This can be subtracted from the payload_offset to determine
3173 * the start of the inner most L4 header.
3175 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3177 * This is the offset from the beginning of the packet in bytes for
3178 * the outer L3 header. If there is no outer L3 header, then this
3181 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3182 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3184 * This is the offset from the beginning of the packet in bytes for
3185 * the inner most L2 header.
3187 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3188 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3190 * This is the offset from the beginning of the packet in bytes for
3191 * the inner most L3 header.
3193 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3194 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3196 * This is the size in bytes of the inner most L4 header.
3197 * This can be subtracted from the payload_offset to determine
3198 * the start of the inner most L4 header.
3200 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3201 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3202 } __attribute__((packed));
3205 * This TPA completion structure is used on devices where the
3206 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3208 /* rx_tpa_end_cmpl (size:128b/16B) */
3209 struct rx_tpa_end_cmpl {
3210 uint16_t flags_type;
3212 * This field indicates the exact type of the completion.
3213 * By convention, the LSB identifies the length of the
3214 * record in 16B units. Even values indicate 16B
3215 * records. Odd values indicate 32B
3218 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3219 #define RX_TPA_END_CMPL_TYPE_SFT 0
3221 * RX L2 TPA End Completion:
3222 * Completion at the end of a TPA operation.
3225 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3226 #define RX_TPA_END_CMPL_TYPE_LAST \
3227 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3228 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3229 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3231 * When this bit is '1', it indicates a packet that has an
3232 * error of some type. Type of error is indicated in
3235 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3236 /* This field indicates how the packet was placed in the buffer. */
3237 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3238 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3241 * TPA Packet was placed using jumbo algorithm. This means
3242 * that the first buffer will be filled with data before
3243 * moving to aggregation buffers. Each aggregation buffer
3244 * will be filled before moving to the next aggregation
3247 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3248 (UINT32_C(0x1) << 7)
3250 * Header/Data Separation:
3251 * Packet was placed using Header/Data separation algorithm.
3252 * The separation location is indicated by the itype field.
3254 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3255 (UINT32_C(0x2) << 7)
3258 * Packet will be placed using GRO/Jumbo where the first
3259 * packet is filled with data. Subsequent packets will be
3260 * placed such that any one packet does not span two
3261 * aggregation buffers unless it starts at the beginning of
3262 * an aggregation buffer.
3264 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3265 (UINT32_C(0x5) << 7)
3267 * GRO/Header-Data Separation:
3268 * Packet will be placed using GRO/HDS where the header
3269 * is in the first packet.
3270 * Payload of each packet will be
3271 * placed such that any one packet does not span two
3272 * aggregation buffers unless it starts at the beginning of
3273 * an aggregation buffer.
3275 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3276 (UINT32_C(0x6) << 7)
3277 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3278 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3280 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3281 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3283 * This value indicates what the inner packet determined for the
3286 * Indicates that the packet was IP and TCP. This indicates
3287 * that the ip_cs field is valid and that the tcp_udp_cs
3288 * field is valid and contains the TCP checksum.
3289 * This also indicates that the payload_offset field is valid.
3291 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3292 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3294 * This value is zero for TPA End completions.
3295 * There is no data in the buffer that corresponds to the opaque
3296 * value in this completion.
3300 * This is a copy of the opaque field from the RX BD this completion
3305 * This value is written by the NIC such that it will be different
3306 * for each pass through the completion queue. The even passes
3307 * will write 1. The odd passes will write 0.
3309 uint8_t agg_bufs_v1;
3311 * This value is written by the NIC such that it will be different
3312 * for each pass through the completion queue. The even passes
3313 * will write 1. The odd passes will write 0.
3315 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3317 * This value is the number of aggregation buffers that follow this
3318 * entry in the completion ring that are a part of this aggregation
3320 * If the value is zero, then the packet is completely contained
3321 * in the buffer space provided in the aggregation start completion.
3323 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3324 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3325 /* This value is the number of segments in the TPA operation. */
3328 * This value indicates the offset in bytes from the beginning of the packet
3329 * where the inner payload starts. This value is valid for TCP, UDP,
3330 * FCoE, and RoCE packets.
3332 * A value of zero indicates an offset of 256 bytes.
3334 uint8_t payload_offset;
3336 /* unused2 is 1 b */
3337 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3339 * This is the aggregation ID that the completion is associated
3340 * with. Use this number to correlate the TPA start completion
3341 * with the TPA end completion.
3343 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3344 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3346 * For non-GRO packets, this value is the
3347 * timestamp delta between earliest and latest timestamp values for
3348 * TPA packet. If packets were not time stamped, then delta will be
3351 * For GRO packets, this field is zero except for the following
3354 * Timestamp present indication. When '0', no Timestamp
3355 * option is in the packet. When '1', then a Timestamp
3356 * option is present in the packet.
3359 } __attribute__((packed));
3362 * Last 16 bytes of rx_tpa_end_cmpl.
3364 * This TPA completion structure is used on devices where the
3365 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3367 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3368 struct rx_tpa_end_cmpl_hi {
3369 uint32_t tpa_dup_acks;
3371 * This value is the number of duplicate ACKs that have been
3372 * received as part of the TPA operation.
3374 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3375 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3377 * This value is the valid when TPA completion is active. It
3378 * indicates the length of the longest segment of the TPA operation
3379 * for LRO mode and the length of the first segment in GRO mode.
3381 * This value may be used by GRO software to re-construct the original
3382 * packet stream from the TPA packet. This is the length of all
3383 * but the last segment for GRO. In LRO mode this value may be used
3384 * to indicate MSS size to the stack.
3386 uint16_t tpa_seg_len;
3387 /* unused4 is 16 b */
3391 * This value is written by the NIC such that it will be different
3392 * for each pass through the completion queue. The even passes
3393 * will write 1. The odd passes will write 0.
3395 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3396 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3397 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3399 * This error indicates that there was some sort of problem with
3400 * the BDs for the packet that was found after part of the
3401 * packet was already placed. The packet should be treated as
3404 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3405 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3407 * This error occurs when there is a fatal HW problem in
3408 * the chip only. It indicates that there were not
3409 * BDs on chip but that there was adequate reservation.
3410 * provided by the TPA block.
3412 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3413 (UINT32_C(0x2) << 1)
3415 * This error occurs when TPA block was not configured to
3416 * reserve adequate BDs for TPA operations on this RX
3417 * ring. All data for the TPA operation was not placed.
3419 * This error can also be generated when the number of
3420 * segments is not programmed correctly in TPA and the
3421 * 33 total aggregation buffers allowed for the TPA
3422 * operation has been exceeded.
3424 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3425 (UINT32_C(0x4) << 1)
3426 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3427 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3428 /* unused5 is 16 b */
3431 * This is the opaque value that was completed for the TPA start
3432 * completion that corresponds to this TPA end completion.
3434 uint32_t start_opaque;
3435 } __attribute__((packed));
3438 * This TPA completion structure is used on devices where the
3439 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3441 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
3442 struct rx_tpa_v2_start_cmpl {
3443 uint16_t flags_type;
3445 * This field indicates the exact type of the completion.
3446 * By convention, the LSB identifies the length of the
3447 * record in 16B units. Even values indicate 16B
3448 * records. Odd values indicate 32B
3451 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
3453 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
3455 * RX L2 TPA Start Completion:
3456 * Completion at the beginning of a TPA operation.
3459 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
3461 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
3462 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
3463 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
3465 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
3466 /* This bit will always be '0' for TPA start completions. */
3467 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
3469 /* This field indicates how the packet was placed in the buffer. */
3470 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
3472 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
3475 * TPA Packet was placed using jumbo algorithm. This means
3476 * that the first buffer will be filled with data before
3477 * moving to aggregation buffers. Each aggregation buffer
3478 * will be filled before moving to the next aggregation
3481 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3482 (UINT32_C(0x1) << 7)
3484 * Header/Data Separation:
3485 * Packet was placed using Header/Data separation algorithm.
3486 * The separation location is indicated by the itype field.
3488 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
3489 (UINT32_C(0x2) << 7)
3492 * Packet will be placed using GRO/Jumbo where the first
3493 * packet is filled with data. Subsequent packets will be
3494 * placed such that any one packet does not span two
3495 * aggregation buffers unless it starts at the beginning of
3496 * an aggregation buffer.
3498 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3499 (UINT32_C(0x5) << 7)
3501 * GRO/Header-Data Separation:
3502 * Packet will be placed using GRO/HDS where the header
3503 * is in the first packet.
3504 * Payload of each packet will be
3505 * placed such that any one packet does not span two
3506 * aggregation buffers unless it starts at the beginning of
3507 * an aggregation buffer.
3509 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3510 (UINT32_C(0x6) << 7)
3511 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
3512 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3513 /* This bit is '1' if the RSS field in this completion is valid. */
3514 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
3517 * For devices that support timestamps, when this bit is cleared the
3518 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3519 * field contains the 32b timestamp for
3520 * the packet from the MAC. When this bit is set, the
3521 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3522 * field contains the outer_l3_offset, inner_l2_offset,
3523 * inner_l3_offset, and inner_l4_size.
3525 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
3528 * This value indicates what the inner packet determined for the
3531 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
3533 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
3536 * Indicates that the packet was IP and TCP.
3538 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
3539 (UINT32_C(0x2) << 12)
3540 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
3541 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
3543 * This value indicates the amount of packet data written to the
3544 * buffer the opaque field in this completion corresponds to.
3548 * This is a copy of the opaque field from the RX BD this completion
3553 * This value is written by the NIC such that it will be different
3554 * for each pass through the completion queue. The even passes
3555 * will write 1. The odd passes will write 0.
3559 * This value is written by the NIC such that it will be different
3560 * for each pass through the completion queue. The even passes
3561 * will write 1. The odd passes will write 0.
3563 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
3564 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
3566 * This is the RSS hash type for the packet. The value is packed
3567 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3569 * The value of tuple_extrac_op provides the information about
3570 * what fields the hash was computed on.
3571 * * 0: The RSS hash was computed over source IP address,
3572 * destination IP address, source port, and destination port of inner
3573 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3574 * the packet headers are considered inner packet headers for the RSS
3575 * hash computation purpose.
3576 * * 1: The RSS hash was computed over source IP address and destination
3577 * IP address of inner IP header. Note: For non-tunneled packets,
3578 * the packet headers are considered inner packet headers for the RSS
3579 * hash computation purpose.
3580 * * 2: The RSS hash was computed over source IP address,
3581 * destination IP address, source port, and destination port of
3582 * IP and TCP or UDP headers of outer tunnel headers.
3583 * Note: For non-tunneled packets, this value is not applicable.
3584 * * 3: The RSS hash was computed over source IP address and
3585 * destination IP address of IP header of outer tunnel headers.
3586 * Note: For non-tunneled packets, this value is not applicable.
3588 * Note that 4-tuples values listed above are applicable
3589 * for layer 4 protocols supported and enabled for RSS in the hardware,
3590 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3591 * enabled for TCP traffic only, then the values of tuple_extract_op
3592 * corresponding to 4-tuples are only valid for TCP traffic.
3594 uint8_t rss_hash_type;
3596 * This is the aggregation ID that the completion is associated
3597 * with. Use this number to correlate the TPA start completion
3598 * with the TPA end completion.
3602 * This value is the RSS hash value calculated for the packet
3603 * based on the mode bits and key value in the VNIC.
3606 } __attribute__((packed));
3609 * Last 16 bytes of rx_tpa_v2_start_cmpl.
3611 * This TPA completion structure is used on devices where the
3612 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3614 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
3615 struct rx_tpa_v2_start_cmpl_hi {
3618 * This indicates that the ip checksum was calculated for the
3619 * inner packet and that the sum passed for all segments
3620 * included in the aggregation.
3622 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
3625 * This indicates that the TCP, UDP or ICMP checksum was
3626 * calculated for the inner packet and that the sum passed
3627 * for all segments included in the aggregation.
3629 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
3632 * This indicates that the ip checksum was calculated for the
3633 * tunnel header and that the sum passed for all segments
3634 * included in the aggregation.
3636 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
3639 * This indicates that the UDP checksum was
3640 * calculated for the tunnel packet and that the sum passed for
3641 * all segments included in the aggregation.
3643 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
3645 /* This value indicates what format the metadata field is. */
3646 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
3648 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3649 /* No metadata informtaion. Value is zero. */
3650 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
3651 (UINT32_C(0x0) << 4)
3653 * The metadata field contains the VLAN tag and TPID value.
3654 * - metadata[11:0] contains the vlan VID value.
3655 * - metadata[12] contains the vlan DE value.
3656 * - metadata[15:13] contains the vlan PRI value.
3657 * - metadata[31:16] contains the vlan TPID value.
3659 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3660 (UINT32_C(0x1) << 4)
3662 * If ext_meta_format is equal to 1, the metadata field
3663 * contains the lower 16b of the tunnel ID value, justified
3665 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3666 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3667 * - NVGRE = TNI[23:0] -> Tenant Network ID
3668 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3669 * - IPV4 = 0 (not populated)
3670 * - IPV6 = Flow Label[19:0]
3671 * - PPPoE = sessionID[15:0]
3672 * - MPLs = Outer label[19:0]
3673 * - UPAR = Selected[31:0] with bit mask
3675 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3676 (UINT32_C(0x2) << 4)
3678 * if ext_meta_format is equal to 1, metadata field contains
3679 * 16b metadata from the prepended header (chdr_data).
3681 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3682 (UINT32_C(0x3) << 4)
3684 * If ext_meta_format is equal to 1, the metadata field contains
3685 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3687 * - metadata[8:0] contains the outer_l3_offset.
3688 * - metadata[17:9] contains the inner_l2_offset.
3689 * - metadata[26:18] contains the inner_l3_offset.
3690 * - metadata[31:27] contains the inner_l4_size.
3692 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3693 (UINT32_C(0x4) << 4)
3694 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
3695 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3697 * This field indicates the IP type for the inner-most IP header.
3698 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3700 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
3703 * This indicates that the complete 1's complement checksum was
3704 * calculated for the packet.
3706 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3709 * The combination of this value and meta_format indicated what
3710 * format the metadata field is.
3712 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3714 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3716 * This value is the complete 1's complement checksum calculated from
3717 * the start of the outer L3 header to the end of the packet (not
3718 * including the ethernet crc). It is valid when the
3719 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3720 * the complete checksum is calculated for the first packet in the
3723 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3724 UINT32_C(0xffff0000)
3725 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3727 * This is data from the CFA block as indicated by the meta_format
3731 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
3732 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3733 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
3734 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
3735 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
3736 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
3737 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3738 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
3739 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
3740 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3741 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
3744 * This value is written by the NIC such that it will be different
3745 * for each pass through the completion queue. The even passes
3746 * will write 1. The odd passes will write 0.
3748 #define RX_TPA_V2_START_CMPL_V2 \
3750 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
3752 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
3754 * This error indicates that there was some sort of problem with
3755 * the BDs for the packet that was found after part of the
3756 * packet was already placed. The packet should be treated as
3759 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
3761 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3762 /* No buffer error */
3763 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3764 (UINT32_C(0x0) << 1)
3767 * BDs were not formatted correctly.
3769 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3770 (UINT32_C(0x3) << 1)
3773 * There was a bad_format error on the previous operation
3775 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3776 (UINT32_C(0x5) << 1)
3777 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3778 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3780 * This field identifies the CFA action rule that was used for this
3785 * For devices that support timestamps this field is overridden
3786 * with the timestamp value. When `flags.timestamp_fld_format` is
3787 * cleared, this field contains the 32b timestamp for the packet from the
3790 * When `flags.timestamp_fld_format` is set, this field contains the
3791 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
3794 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3796 * This is the offset from the beginning of the packet in bytes for
3797 * the outer L3 header. If there is no outer L3 header, then this
3800 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3801 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
3803 * This is the offset from the beginning of the packet in bytes for
3804 * the inner most L2 header.
3806 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3807 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
3809 * This is the offset from the beginning of the packet in bytes for
3810 * the inner most L3 header.
3812 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3813 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
3815 * This is the size in bytes of the inner most L4 header.
3816 * This can be subtracted from the payload_offset to determine
3817 * the start of the inner most L4 header.
3819 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3820 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
3821 } __attribute__((packed));
3824 * This TPA completion structure is used on devices where the
3825 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3827 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
3828 struct rx_tpa_v2_end_cmpl {
3829 uint16_t flags_type;
3831 * This field indicates the exact type of the completion.
3832 * By convention, the LSB identifies the length of the
3833 * record in 16B units. Even values indicate 16B
3834 * records. Odd values indicate 32B
3837 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3838 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
3840 * RX L2 TPA End Completion:
3841 * Completion at the end of a TPA operation.
3844 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3845 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
3846 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
3847 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3848 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
3850 * When this bit is '1', it indicates a packet that has an
3851 * error of some type. Type of error is indicated in
3854 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3855 /* This field indicates how the packet was placed in the buffer. */
3856 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3857 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
3860 * TPA Packet was placed using jumbo algorithm. This means
3861 * that the first buffer will be filled with data before
3862 * moving to aggregation buffers. Each aggregation buffer
3863 * will be filled before moving to the next aggregation
3866 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3867 (UINT32_C(0x1) << 7)
3869 * Header/Data Separation:
3870 * Packet was placed using Header/Data separation algorithm.
3871 * The separation location is indicated by the itype field.
3873 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
3874 (UINT32_C(0x2) << 7)
3877 * Packet will be placed using GRO/Jumbo where the first
3878 * packet is filled with data. Subsequent packets will be
3879 * placed such that any one packet does not span two
3880 * aggregation buffers unless it starts at the beginning of
3881 * an aggregation buffer.
3883 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3884 (UINT32_C(0x5) << 7)
3886 * GRO/Header-Data Separation:
3887 * Packet will be placed using GRO/HDS where the header
3888 * is in the first packet.
3889 * Payload of each packet will be
3890 * placed such that any one packet does not span two
3891 * aggregation buffers unless it starts at the beginning of
3892 * an aggregation buffer.
3894 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3895 (UINT32_C(0x6) << 7)
3896 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
3897 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3899 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3900 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
3902 * This value indicates what the inner packet determined for the
3905 * Indicates that the packet was IP and TCP. This indicates
3906 * that the ip_cs field is valid and that the tcp_udp_cs
3907 * field is valid and contains the TCP checksum.
3908 * This also indicates that the payload_offset field is valid.
3910 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3911 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
3913 * This value is zero for TPA End completions.
3914 * There is no data in the buffer that corresponds to the opaque
3915 * value in this completion.
3919 * This is a copy of the opaque field from the RX BD this completion
3925 * This value is written by the NIC such that it will be different
3926 * for each pass through the completion queue. The even passes
3927 * will write 1. The odd passes will write 0.
3929 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
3930 /* This value is the number of segments in the TPA operation. */
3933 * This is the aggregation ID that the completion is associated
3934 * with. Use this number to correlate the TPA start completion
3935 * with the TPA end completion.
3939 * For non-GRO packets, this value is the
3940 * timestamp delta between earliest and latest timestamp values for
3941 * TPA packet. If packets were not time stamped, then delta will be
3944 * For GRO packets, this field is zero except for the following
3947 * Timestamp present indication. When '0', no Timestamp
3948 * option is in the packet. When '1', then a Timestamp
3949 * option is present in the packet.
3952 } __attribute__((packed));
3955 * Last 16 bytes of rx_tpa_v2_end_cmpl.
3957 * This TPA completion structure is used on devices where the
3958 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3960 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
3961 struct rx_tpa_v2_end_cmpl_hi {
3963 * This value is the number of duplicate ACKs that have been
3964 * received as part of the TPA operation.
3966 uint16_t tpa_dup_acks;
3968 * This value is the number of duplicate ACKs that have been
3969 * received as part of the TPA operation.
3971 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3972 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
3974 * This value indicated the offset in bytes from the beginning of
3975 * the packet where the inner payload starts. This value is valid
3976 * for TCP, UDP, FCoE and RoCE packets
3978 uint8_t payload_offset;
3980 * The value is the total number of aggregation buffers that were
3981 * used in the TPA operation. All TPA aggregation buffer completions
3982 * precede the TPA End completion. If the value is zero, then the
3983 * aggregation is completely contained in the buffer space provided
3984 * in the aggregation start completion.
3985 * Note that the field is simply provided as a cross check.
3987 uint8_t tpa_agg_bufs;
3989 * This value is the valid when TPA completion is active. It
3990 * indicates the length of the longest segment of the TPA operation
3991 * for LRO mode and the length of the first segment in GRO mode.
3993 * This value may be used by GRO software to re-construct the original
3994 * packet stream from the TPA packet. This is the length of all
3995 * but the last segment for GRO. In LRO mode this value may be used
3996 * to indicate MSS size to the stack.
3998 uint16_t tpa_seg_len;
4002 * This value is written by the NIC such that it will be different
4003 * for each pass through the completion queue. The even passes
4004 * will write 1. The odd passes will write 0.
4006 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
4007 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
4009 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
4011 * This error indicates that there was some sort of problem with
4012 * the BDs for the packet that was found after part of the
4013 * packet was already placed. The packet should be treated as
4016 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
4018 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4019 /* No buffer error */
4020 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4021 (UINT32_C(0x0) << 1)
4023 * This error occurs when there is a fatal HW problem in
4024 * the chip only. It indicates that there were not
4025 * BDs on chip but that there was adequate reservation.
4026 * provided by the TPA block.
4028 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4029 (UINT32_C(0x2) << 1)
4032 * BDs were not formatted correctly.
4034 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4035 (UINT32_C(0x3) << 1)
4037 * This error occurs when TPA block was not configured to
4038 * reserve adequate BDs for TPA operations on this RX
4039 * ring. All data for the TPA operation was not placed.
4041 * This error can also be generated when the number of
4042 * segments is not programmed correctly in TPA and the
4043 * 33 total aggregation buffers allowed for the TPA
4044 * operation has been exceeded.
4046 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4047 (UINT32_C(0x4) << 1)
4050 * There was a bad_format error on the previous operation
4052 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4053 (UINT32_C(0x5) << 1)
4054 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4055 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4058 * This is the opaque value that was completed for the TPA start
4059 * completion that corresponds to this TPA end completion.
4061 uint32_t start_opaque;
4062 } __attribute__((packed));
4065 * This TPA completion structure is used on devices where the
4066 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4068 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
4069 struct rx_tpa_v2_abuf_cmpl {
4072 * This field indicates the exact type of the completion.
4073 * By convention, the LSB identifies the length of the
4074 * record in 16B units. Even values indicate 16B
4075 * records. Odd values indicate 32B
4078 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4079 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
4081 * RX TPA Aggregation Buffer completion :
4082 * Completion of an L2 aggregation buffer in support of
4083 * TPA packet completion. Length = 16B
4085 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
4086 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
4087 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
4089 * This is the length of the data for the packet stored in this
4090 * aggregation buffer identified by the opaque value. This does not
4091 * include the length of any
4092 * data placed in other aggregation BDs or in the packet or buffer
4093 * BDs. This length does not include any space added due to
4094 * hdr_offset register during HDS placement mode.
4098 * This is a copy of the opaque field from the RX BD this aggregation
4099 * buffer corresponds to.
4104 * This value is written by the NIC such that it will be different
4105 * for each pass through the completion queue. The even passes
4106 * will write 1. The odd passes will write 0.
4108 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
4110 * This is the aggregation ID that the completion is associated with. Use
4111 * this number to correlate the TPA agg completion with the TPA start
4112 * completion and the TPA end completion.
4116 } __attribute__((packed));
4118 /* rx_abuf_cmpl (size:128b/16B) */
4119 struct rx_abuf_cmpl {
4122 * This field indicates the exact type of the completion.
4123 * By convention, the LSB identifies the length of the
4124 * record in 16B units. Even values indicate 16B
4125 * records. Odd values indicate 32B
4128 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4129 #define RX_ABUF_CMPL_TYPE_SFT 0
4131 * RX Aggregation Buffer completion :
4132 * Completion of an L2 aggregation buffer in support of
4133 * TPA, HDS, or Jumbo packet completion. Length = 16B
4135 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
4136 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
4138 * This is the length of the data for the packet stored in this
4139 * aggregation buffer identified by the opaque value. This does not
4140 * include the length of any
4141 * data placed in other aggregation BDs or in the packet or buffer
4142 * BDs. This length does not include any space added due to
4143 * hdr_offset register during HDS placement mode.
4147 * This is a copy of the opaque field from the RX BD this aggregation
4148 * buffer corresponds to.
4153 * This value is written by the NIC such that it will be different
4154 * for each pass through the completion queue. The even passes
4155 * will write 1. The odd passes will write 0.
4157 #define RX_ABUF_CMPL_V UINT32_C(0x1)
4158 /* unused3 is 32 b */
4160 } __attribute__((packed));
4162 /* eject_cmpl (size:128b/16B) */
4166 * This field indicates the exact type of the completion.
4167 * By convention, the LSB identifies the length of the
4168 * record in 16B units. Even values indicate 16B
4169 * records. Odd values indicate 32B
4172 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
4173 #define EJECT_CMPL_TYPE_SFT 0
4175 * Statistics Ejection Completion:
4176 * Completion of statistics data ejection buffer.
4179 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
4180 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
4181 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4182 #define EJECT_CMPL_FLAGS_SFT 6
4184 * When this bit is '1', it indicates a packet that has an
4185 * error of some type. Type of error is indicated in
4188 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4190 * This is the length of the statistics data stored in this
4195 * This is a copy of the opaque field from the RX BD this ejection
4196 * buffer corresponds to.
4201 * This value is written by the NIC such that it will be different
4202 * for each pass through the completion queue. The even passes
4203 * will write 1. The odd passes will write 0.
4205 #define EJECT_CMPL_V UINT32_C(0x1)
4206 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4207 #define EJECT_CMPL_ERRORS_SFT 1
4209 * This error indicates that there was some sort of problem with
4210 * the BDs for statistics ejection. The statistics ejection should
4211 * be treated as invalid
4213 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4214 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4215 /* No buffer error */
4216 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4217 (UINT32_C(0x0) << 1)
4220 * Statistics did not fit into aggregation buffer provided.
4222 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4223 (UINT32_C(0x1) << 1)
4226 * BDs were not formatted correctly.
4228 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4229 (UINT32_C(0x3) << 1)
4232 * There was a bad_format error on the previous operation
4234 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4235 (UINT32_C(0x5) << 1)
4236 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4237 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4238 /* reserved16 is 16 b */
4239 uint16_t reserved16;
4240 /* unused3 is 32 b */
4242 } __attribute__((packed));
4244 /* hwrm_cmpl (size:128b/16B) */
4248 * This field indicates the exact type of the completion.
4249 * By convention, the LSB identifies the length of the
4250 * record in 16B units. Even values indicate 16B
4251 * records. Odd values indicate 32B
4254 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
4255 #define HWRM_CMPL_TYPE_SFT 0
4257 * HWRM Command Completion:
4258 * Completion of an HWRM command.
4260 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
4261 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
4262 /* This is the sequence_id of the HWRM command that has completed. */
4263 uint16_t sequence_id;
4264 /* unused2 is 32 b */
4268 * This value is written by the NIC such that it will be different
4269 * for each pass through the completion queue. The even passes
4270 * will write 1. The odd passes will write 0.
4272 #define HWRM_CMPL_V UINT32_C(0x1)
4273 /* unused4 is 32 b */
4275 } __attribute__((packed));
4277 /* hwrm_fwd_req_cmpl (size:128b/16B) */
4278 struct hwrm_fwd_req_cmpl {
4280 * This field indicates the exact type of the completion.
4281 * By convention, the LSB identifies the length of the
4282 * record in 16B units. Even values indicate 16B
4283 * records. Odd values indicate 32B
4286 uint16_t req_len_type;
4288 * This field indicates the exact type of the completion.
4289 * By convention, the LSB identifies the length of the
4290 * record in 16B units. Even values indicate 16B
4291 * records. Odd values indicate 32B
4294 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
4295 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
4296 /* Forwarded HWRM Request */
4297 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4298 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
4299 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
4300 /* Length of forwarded request in bytes. */
4301 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
4302 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
4304 * Source ID of this request.
4305 * Typically used in forwarding requests and responses.
4306 * 0x0 - 0xFFF8 - Used for function ids
4307 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4311 /* unused1 is 32 b */
4313 /* Address of forwarded request. */
4314 uint32_t req_buf_addr_v[2];
4316 * This value is written by the NIC such that it will be different
4317 * for each pass through the completion queue. The even passes
4318 * will write 1. The odd passes will write 0.
4320 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
4321 /* Address of forwarded request. */
4322 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4323 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
4324 } __attribute__((packed));
4326 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
4327 struct hwrm_fwd_resp_cmpl {
4330 * This field indicates the exact type of the completion.
4331 * By convention, the LSB identifies the length of the
4332 * record in 16B units. Even values indicate 16B
4333 * records. Odd values indicate 32B
4336 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
4337 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
4338 /* Forwarded HWRM Response */
4339 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4340 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
4341 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
4343 * Source ID of this response.
4344 * Typically used in forwarding requests and responses.
4345 * 0x0 - 0xFFF8 - Used for function ids
4346 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4350 /* Length of forwarded response in bytes. */
4352 /* unused2 is 16 b */
4354 /* Address of forwarded request. */
4355 uint32_t resp_buf_addr_v[2];
4357 * This value is written by the NIC such that it will be different
4358 * for each pass through the completion queue. The even passes
4359 * will write 1. The odd passes will write 0.
4361 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
4362 /* Address of forwarded request. */
4363 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4364 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
4365 } __attribute__((packed));
4367 /* hwrm_async_event_cmpl (size:128b/16B) */
4368 struct hwrm_async_event_cmpl {
4371 * This field indicates the exact type of the completion.
4372 * By convention, the LSB identifies the length of the
4373 * record in 16B units. Even values indicate 16B
4374 * records. Odd values indicate 32B
4377 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
4378 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
4379 /* HWRM Asynchronous Event Information */
4380 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4381 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
4382 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
4383 /* Identifiers of events. */
4385 /* Link status changed */
4386 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
4388 /* Link MTU changed */
4389 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
4391 /* Link speed changed */
4392 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
4394 /* DCB Configuration changed */
4395 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
4397 /* Port connection not allowed */
4398 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4400 /* Link speed configuration was not allowed */
4401 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4403 /* Link speed configuration change */
4404 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4406 /* Port PHY configuration change */
4407 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
4409 /* Reset notification to clients */
4410 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
4412 /* Master function selection event */
4413 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
4415 /* Function driver unloaded */
4416 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
4418 /* Function driver loaded */
4419 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
4421 /* Function FLR related processing has completed */
4422 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4424 /* PF driver unloaded */
4425 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
4427 /* PF driver loaded */
4428 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
4430 /* VF Function Level Reset (FLR) */
4431 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
4433 /* VF MAC Address Change */
4434 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
4436 /* PF-VF communication channel status change. */
4437 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4439 /* VF Configuration Change */
4440 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
4442 /* LLFC/PFC Configuration Change */
4443 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
4445 /* Default VNIC Configuration Change */
4446 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
4449 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
4452 * A debug notification being posted to the driver. These
4453 * notifications are purely for diagnostic purpose and should not be
4454 * used for functional purpose. The driver is not supposed to act
4455 * on these messages except to log/record it.
4457 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
4460 * An EEM flow cached memory flush for all flows request event being
4461 * posted to the PF driver.
4463 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
4466 * An EEM flow cache memory flush completion event being posted to the
4467 * firmware by the PF driver. This is indication that host EEM flush
4468 * has completed by the PF.
4470 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
4473 * A tcp flag action change event being posted to the PF or trusted VF
4474 * driver by the firmware. The PF or trusted VF driver should query
4475 * the firmware for the new TCP flag action update after receiving
4478 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
4481 * An EEM flow active event being posted to the PF or trusted VF driver
4482 * by the firmware. The PF or trusted VF driver should update the
4483 * flow's aging timer after receiving this async event.
4485 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
4488 * A eem cfg change event being posted to the trusted VF driver by the
4489 * firmware if the parent PF EEM configuration changed.
4491 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
4493 /* TFLIB unique default VNIC Configuration Change */
4494 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
4496 /* TFLIB unique link status changed */
4497 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
4500 * A trace log message. This contains firmware trace logs string
4501 * embedded in the asynchronous message. This is an experimental
4502 * event, not meant for production use at this time.
4504 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
4507 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
4509 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
4510 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
4511 /* Event specific data */
4512 uint32_t event_data2;
4515 * This value is written by the NIC such that it will be different
4516 * for each pass through the completion queue. The even passes
4517 * will write 1. The odd passes will write 0.
4519 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
4521 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
4522 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
4523 /* 8-lsb timestamp from POR (100-msec resolution) */
4524 uint8_t timestamp_lo;
4525 /* 16-lsb timestamp from POR (100-msec resolution) */
4526 uint16_t timestamp_hi;
4527 /* Event specific data */
4528 uint32_t event_data1;
4529 } __attribute__((packed));
4531 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
4532 struct hwrm_async_event_cmpl_link_status_change {
4535 * This field indicates the exact type of the completion.
4536 * By convention, the LSB identifies the length of the
4537 * record in 16B units. Even values indicate 16B
4538 * records. Odd values indicate 32B
4541 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
4543 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
4544 /* HWRM Asynchronous Event Information */
4545 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4547 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
4548 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4549 /* Identifiers of events. */
4551 /* Link status changed */
4552 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
4554 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
4555 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
4556 /* Event specific data */
4557 uint32_t event_data2;
4560 * This value is written by the NIC such that it will be different
4561 * for each pass through the completion queue. The even passes
4562 * will write 1. The odd passes will write 0.
4564 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
4567 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
4569 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
4570 /* 8-lsb timestamp from POR (100-msec resolution) */
4571 uint8_t timestamp_lo;
4572 /* 16-lsb timestamp from POR (100-msec resolution) */
4573 uint16_t timestamp_hi;
4574 /* Event specific data */
4575 uint32_t event_data1;
4576 /* Indicates link status change */
4577 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
4580 * If this bit set to 0, then it indicates that the link
4581 * was up and it went down.
4583 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4586 * If this bit is set to 1, then it indicates that the link
4587 * was down and it went up.
4589 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4591 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4592 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4593 /* Indicates the physical port this link status change occur */
4594 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4596 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4599 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4601 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4603 /* Indicates the physical function this event occurred on. */
4604 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4606 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4608 } __attribute__((packed));
4610 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4611 struct hwrm_async_event_cmpl_link_mtu_change {
4614 * This field indicates the exact type of the completion.
4615 * By convention, the LSB identifies the length of the
4616 * record in 16B units. Even values indicate 16B
4617 * records. Odd values indicate 32B
4620 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4622 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4623 /* HWRM Asynchronous Event Information */
4624 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4626 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4627 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4628 /* Identifiers of events. */
4630 /* Link MTU changed */
4631 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4633 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4634 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4635 /* Event specific data */
4636 uint32_t event_data2;
4639 * This value is written by the NIC such that it will be different
4640 * for each pass through the completion queue. The even passes
4641 * will write 1. The odd passes will write 0.
4643 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4645 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4647 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4648 /* 8-lsb timestamp from POR (100-msec resolution) */
4649 uint8_t timestamp_lo;
4650 /* 16-lsb timestamp from POR (100-msec resolution) */
4651 uint16_t timestamp_hi;
4652 /* Event specific data */
4653 uint32_t event_data1;
4654 /* The new MTU of the link in bytes. */
4655 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4657 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4658 } __attribute__((packed));
4660 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4661 struct hwrm_async_event_cmpl_link_speed_change {
4664 * This field indicates the exact type of the completion.
4665 * By convention, the LSB identifies the length of the
4666 * record in 16B units. Even values indicate 16B
4667 * records. Odd values indicate 32B
4670 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4673 /* HWRM Asynchronous Event Information */
4674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4676 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4677 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4678 /* Identifiers of events. */
4680 /* Link speed changed */
4681 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4683 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4684 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4685 /* Event specific data */
4686 uint32_t event_data2;
4689 * This value is written by the NIC such that it will be different
4690 * for each pass through the completion queue. The even passes
4691 * will write 1. The odd passes will write 0.
4693 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4698 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4699 /* 8-lsb timestamp from POR (100-msec resolution) */
4700 uint8_t timestamp_lo;
4701 /* 16-lsb timestamp from POR (100-msec resolution) */
4702 uint16_t timestamp_hi;
4703 /* Event specific data */
4704 uint32_t event_data1;
4706 * When this bit is '1', the link was forced to the
4707 * force_link_speed value.
4709 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4711 /* The new link speed in 100 Mbps units. */
4712 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4714 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4716 /* 100Mb link speed */
4717 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4718 (UINT32_C(0x1) << 1)
4719 /* 1Gb link speed */
4720 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4721 (UINT32_C(0xa) << 1)
4722 /* 2Gb link speed */
4723 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4724 (UINT32_C(0x14) << 1)
4725 /* 25Gb link speed */
4726 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4727 (UINT32_C(0x19) << 1)
4728 /* 10Gb link speed */
4729 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4730 (UINT32_C(0x64) << 1)
4731 /* 20Mb link speed */
4732 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4733 (UINT32_C(0xc8) << 1)
4734 /* 25Gb link speed */
4735 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4736 (UINT32_C(0xfa) << 1)
4737 /* 40Gb link speed */
4738 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4739 (UINT32_C(0x190) << 1)
4740 /* 50Gb link speed */
4741 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4742 (UINT32_C(0x1f4) << 1)
4743 /* 100Gb link speed */
4744 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4745 (UINT32_C(0x3e8) << 1)
4746 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4747 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4749 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4750 UINT32_C(0xffff0000)
4751 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4753 } __attribute__((packed));
4755 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4756 struct hwrm_async_event_cmpl_dcb_config_change {
4759 * This field indicates the exact type of the completion.
4760 * By convention, the LSB identifies the length of the
4761 * record in 16B units. Even values indicate 16B
4762 * records. Odd values indicate 32B
4765 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4767 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4768 /* HWRM Asynchronous Event Information */
4769 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4771 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4772 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4773 /* Identifiers of events. */
4775 /* DCB Configuration changed */
4776 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4778 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4779 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4780 /* Event specific data */
4781 uint32_t event_data2;
4782 /* ETS configuration change */
4783 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4785 /* PFC configuration change */
4786 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4788 /* APP configuration change */
4789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4793 * This value is written by the NIC such that it will be different
4794 * for each pass through the completion queue. The even passes
4795 * will write 1. The odd passes will write 0.
4797 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4800 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4802 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4803 /* 8-lsb timestamp from POR (100-msec resolution) */
4804 uint8_t timestamp_lo;
4805 /* 16-lsb timestamp from POR (100-msec resolution) */
4806 uint16_t timestamp_hi;
4807 /* Event specific data */
4808 uint32_t event_data1;
4810 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4812 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4814 /* Priority recommended for RoCE traffic */
4815 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4817 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4820 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4821 (UINT32_C(0xff) << 16)
4822 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4823 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4824 /* Priority recommended for L2 traffic */
4825 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4826 UINT32_C(0xff000000)
4827 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4830 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4831 (UINT32_C(0xff) << 24)
4832 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4833 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4834 } __attribute__((packed));
4836 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4837 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4840 * This field indicates the exact type of the completion.
4841 * By convention, the LSB identifies the length of the
4842 * record in 16B units. Even values indicate 16B
4843 * records. Odd values indicate 32B
4846 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4848 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4850 /* HWRM Asynchronous Event Information */
4851 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4853 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4854 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4855 /* Identifiers of events. */
4857 /* Port connection not allowed */
4858 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4860 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4861 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4862 /* Event specific data */
4863 uint32_t event_data2;
4866 * This value is written by the NIC such that it will be different
4867 * for each pass through the completion queue. The even passes
4868 * will write 1. The odd passes will write 0.
4870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4873 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4876 /* 8-lsb timestamp from POR (100-msec resolution) */
4877 uint8_t timestamp_lo;
4878 /* 16-lsb timestamp from POR (100-msec resolution) */
4879 uint16_t timestamp_hi;
4880 /* Event specific data */
4881 uint32_t event_data1;
4883 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4885 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4888 * This value indicates the current port level enforcement policy
4889 * for the optics module when there is an optical module mismatch
4890 * and port is not connected.
4892 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4894 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4896 /* No enforcement */
4897 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4898 (UINT32_C(0x0) << 16)
4899 /* Disable Transmit side Laser. */
4900 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4901 (UINT32_C(0x1) << 16)
4902 /* Raise a warning message. */
4903 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4904 (UINT32_C(0x2) << 16)
4905 /* Power down the module. */
4906 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4907 (UINT32_C(0x3) << 16)
4908 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4909 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4910 } __attribute__((packed));
4912 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4913 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4916 * This field indicates the exact type of the completion.
4917 * By convention, the LSB identifies the length of the
4918 * record in 16B units. Even values indicate 16B
4919 * records. Odd values indicate 32B
4922 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4924 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4926 /* HWRM Asynchronous Event Information */
4927 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4929 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4930 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4931 /* Identifiers of events. */
4933 /* Link speed configuration was not allowed */
4934 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4936 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4937 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4938 /* Event specific data */
4939 uint32_t event_data2;
4942 * This value is written by the NIC such that it will be different
4943 * for each pass through the completion queue. The even passes
4944 * will write 1. The odd passes will write 0.
4946 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4949 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4951 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4952 /* 8-lsb timestamp from POR (100-msec resolution) */
4953 uint8_t timestamp_lo;
4954 /* 16-lsb timestamp from POR (100-msec resolution) */
4955 uint16_t timestamp_hi;
4956 /* Event specific data */
4957 uint32_t event_data1;
4959 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4961 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4963 } __attribute__((packed));
4965 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4966 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4969 * This field indicates the exact type of the completion.
4970 * By convention, the LSB identifies the length of the
4971 * record in 16B units. Even values indicate 16B
4972 * records. Odd values indicate 32B
4975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4977 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4979 /* HWRM Asynchronous Event Information */
4980 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4982 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4983 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4984 /* Identifiers of events. */
4986 /* Link speed configuration change */
4987 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4989 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4990 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4991 /* Event specific data */
4992 uint32_t event_data2;
4995 * This value is written by the NIC such that it will be different
4996 * for each pass through the completion queue. The even passes
4997 * will write 1. The odd passes will write 0.
4999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
5002 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
5004 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
5005 /* 8-lsb timestamp from POR (100-msec resolution) */
5006 uint8_t timestamp_lo;
5007 /* 16-lsb timestamp from POR (100-msec resolution) */
5008 uint16_t timestamp_hi;
5009 /* Event specific data */
5010 uint32_t event_data1;
5012 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5014 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5017 * If set to 1, it indicates that the supported link speeds
5018 * configuration on the port has changed.
5019 * If set to 0, then there is no change in supported link speeds
5022 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
5025 * If set to 1, it indicates that the link speed configuration
5026 * on the port has become illegal or invalid.
5027 * If set to 0, then the link speed configuration on the port is
5030 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
5032 } __attribute__((packed));
5034 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
5035 struct hwrm_async_event_cmpl_port_phy_cfg_change {
5038 * This field indicates the exact type of the completion.
5039 * By convention, the LSB identifies the length of the
5040 * record in 16B units. Even values indicate 16B
5041 * records. Odd values indicate 32B
5044 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
5046 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
5048 /* HWRM Asynchronous Event Information */
5049 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5051 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
5052 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5053 /* Identifiers of events. */
5055 /* Port PHY configuration change */
5056 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
5058 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
5059 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
5060 /* Event specific data */
5061 uint32_t event_data2;
5064 * This value is written by the NIC such that it will be different
5065 * for each pass through the completion queue. The even passes
5066 * will write 1. The odd passes will write 0.
5068 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
5071 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
5073 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
5074 /* 8-lsb timestamp from POR (100-msec resolution) */
5075 uint8_t timestamp_lo;
5076 /* 16-lsb timestamp from POR (100-msec resolution) */
5077 uint16_t timestamp_hi;
5078 /* Event specific data */
5079 uint32_t event_data1;
5081 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5083 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5086 * If set to 1, it indicates that the FEC
5087 * configuration on the port has changed.
5088 * If set to 0, then there is no change in FEC configuration.
5090 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
5093 * If set to 1, it indicates that the EEE configuration
5094 * on the port has changed.
5095 * If set to 0, then there is no change in EEE configuration
5098 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
5101 * If set to 1, it indicates that the pause configuration
5102 * on the PHY has changed.
5103 * If set to 0, then there is no change in the pause
5104 * configuration on the PHY.
5106 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
5108 } __attribute__((packed));
5110 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
5111 struct hwrm_async_event_cmpl_reset_notify {
5114 * This field indicates the exact type of the completion.
5115 * By convention, the LSB identifies the length of the
5116 * record in 16B units. Even values indicate 16B
5117 * records. Odd values indicate 32B
5120 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
5122 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
5123 /* HWRM Asynchronous Event Information */
5124 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
5126 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
5127 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
5128 /* Identifiers of events. */
5130 /* Notify clients of imminent reset. */
5131 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
5133 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
5134 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
5135 /* Event specific data */
5136 uint32_t event_data2;
5139 * This value is written by the NIC such that it will be different
5140 * for each pass through the completion queue. The even passes
5141 * will write 1. The odd passes will write 0.
5143 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
5145 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
5146 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
5148 * 8-lsb timestamp (100-msec resolution)
5149 * The Minimum time required for the Firmware readiness after sending this
5150 * notification to the driver instances.
5152 uint8_t timestamp_lo;
5154 * 16-lsb timestamp (100-msec resolution)
5155 * The Maximum Firmware Reset bail out value in the order of 100
5156 * milli seconds. The driver instances will use this value to re-initiate the
5157 * registration process again if the core firmware didn’t set the ready
5160 uint16_t timestamp_hi;
5161 /* Event specific data */
5162 uint32_t event_data1;
5163 /* Indicates driver action requested */
5164 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
5166 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
5169 * If set to 1, it indicates that the l2 client should
5170 * stop sending in band traffic to Nitro.
5171 * if set to 0, there is no change in L2 client behavior.
5173 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
5176 * If set to 1, it indicates that the L2 client should
5177 * bring down the interface.
5178 * If set to 0, then there is no change in L2 client behavior.
5180 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
5182 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
5183 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
5184 /* Indicates reason for reset. */
5185 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
5187 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
5189 /* A management client has requested reset. */
5190 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
5191 (UINT32_C(0x1) << 8)
5192 /* A fatal firmware exception has occurred. */
5193 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
5194 (UINT32_C(0x2) << 8)
5195 /* A non-fatal firmware exception has occurred. */
5196 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
5197 (UINT32_C(0x3) << 8)
5198 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
5199 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
5201 * Minimum time before driver should attempt access - units 100ms ticks.
5204 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
5205 UINT32_C(0xffff0000)
5206 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
5208 } __attribute__((packed));
5210 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
5211 struct hwrm_async_event_cmpl_error_recovery {
5214 * This field indicates the exact type of the completion.
5215 * By convention, the LSB identifies the length of the
5216 * record in 16B units. Even values indicate 16B
5217 * records. Odd values indicate 32B
5220 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
5222 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
5223 /* HWRM Asynchronous Event Information */
5224 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
5226 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
5227 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
5228 /* Identifiers of events. */
5231 * This async notification message can be used for selecting or
5232 * deselecting master function for error recovery,
5233 * and to communicate to all the functions whether error recovery
5234 * was enabled/disabled.
5236 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
5238 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
5239 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
5240 /* Event specific data */
5241 uint32_t event_data2;
5244 * This value is written by the NIC such that it will be different
5245 * for each pass through the completion queue. The even passes
5246 * will write 1. The odd passes will write 0.
5248 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
5250 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
5251 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
5252 /* 8-lsb timestamp (100-msec resolution) */
5253 uint8_t timestamp_lo;
5254 /* 16-lsb timestamp (100-msec resolution) */
5255 uint16_t timestamp_hi;
5256 /* Event specific data */
5257 uint32_t event_data1;
5258 /* Indicates driver action requested */
5259 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
5261 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
5264 * If set to 1, this function is selected as Master function.
5265 * This function has responsibility to do 'chip reset' when it
5266 * detects a fatal error. If set to 0, master function functionality
5267 * is disabled on this function.
5269 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
5272 * If set to 1, error recovery is enabled.
5273 * If set to 0, error recovery is disabled.
5275 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
5277 } __attribute__((packed));
5279 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
5280 struct hwrm_async_event_cmpl_func_drvr_unload {
5283 * This field indicates the exact type of the completion.
5284 * By convention, the LSB identifies the length of the
5285 * record in 16B units. Even values indicate 16B
5286 * records. Odd values indicate 32B
5289 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
5291 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
5292 /* HWRM Asynchronous Event Information */
5293 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5295 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
5296 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5297 /* Identifiers of events. */
5299 /* Function driver unloaded */
5300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
5302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
5303 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
5304 /* Event specific data */
5305 uint32_t event_data2;
5308 * This value is written by the NIC such that it will be different
5309 * for each pass through the completion queue. The even passes
5310 * will write 1. The odd passes will write 0.
5312 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
5314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
5316 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
5317 /* 8-lsb timestamp from POR (100-msec resolution) */
5318 uint8_t timestamp_lo;
5319 /* 16-lsb timestamp from POR (100-msec resolution) */
5320 uint16_t timestamp_hi;
5321 /* Event specific data */
5322 uint32_t event_data1;
5324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5326 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
5328 } __attribute__((packed));
5330 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
5331 struct hwrm_async_event_cmpl_func_drvr_load {
5334 * This field indicates the exact type of the completion.
5335 * By convention, the LSB identifies the length of the
5336 * record in 16B units. Even values indicate 16B
5337 * records. Odd values indicate 32B
5340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
5342 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
5343 /* HWRM Asynchronous Event Information */
5344 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
5347 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5348 /* Identifiers of events. */
5350 /* Function driver loaded */
5351 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
5353 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
5354 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
5355 /* Event specific data */
5356 uint32_t event_data2;
5359 * This value is written by the NIC such that it will be different
5360 * for each pass through the completion queue. The even passes
5361 * will write 1. The odd passes will write 0.
5363 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
5365 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5366 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
5367 /* 8-lsb timestamp from POR (100-msec resolution) */
5368 uint8_t timestamp_lo;
5369 /* 16-lsb timestamp from POR (100-msec resolution) */
5370 uint16_t timestamp_hi;
5371 /* Event specific data */
5372 uint32_t event_data1;
5374 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5376 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5377 } __attribute__((packed));
5379 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
5380 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
5383 * This field indicates the exact type of the completion.
5384 * By convention, the LSB identifies the length of the
5385 * record in 16B units. Even values indicate 16B
5386 * records. Odd values indicate 32B
5389 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
5391 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
5393 /* HWRM Asynchronous Event Information */
5394 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
5396 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
5397 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
5398 /* Identifiers of events. */
5400 /* Function FLR related processing has completed */
5401 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
5403 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
5404 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
5405 /* Event specific data */
5406 uint32_t event_data2;
5409 * This value is written by the NIC such that it will be different
5410 * for each pass through the completion queue. The even passes
5411 * will write 1. The odd passes will write 0.
5413 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
5416 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
5418 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
5419 /* 8-lsb timestamp from POR (100-msec resolution) */
5420 uint8_t timestamp_lo;
5421 /* 16-lsb timestamp from POR (100-msec resolution) */
5422 uint16_t timestamp_hi;
5423 /* Event specific data */
5424 uint32_t event_data1;
5426 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
5428 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
5430 } __attribute__((packed));
5432 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
5433 struct hwrm_async_event_cmpl_pf_drvr_unload {
5436 * This field indicates the exact type of the completion.
5437 * By convention, the LSB identifies the length of the
5438 * record in 16B units. Even values indicate 16B
5439 * records. Odd values indicate 32B
5442 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
5444 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
5445 /* HWRM Asynchronous Event Information */
5446 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5448 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
5449 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5450 /* Identifiers of events. */
5452 /* PF driver unloaded */
5453 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
5455 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
5456 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
5457 /* Event specific data */
5458 uint32_t event_data2;
5461 * This value is written by the NIC such that it will be different
5462 * for each pass through the completion queue. The even passes
5463 * will write 1. The odd passes will write 0.
5465 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
5467 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
5468 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
5469 /* 8-lsb timestamp from POR (100-msec resolution) */
5470 uint8_t timestamp_lo;
5471 /* 16-lsb timestamp from POR (100-msec resolution) */
5472 uint16_t timestamp_hi;
5473 /* Event specific data */
5474 uint32_t event_data1;
5476 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5478 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
5479 /* Indicates the physical port this pf belongs to */
5480 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
5482 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
5483 } __attribute__((packed));
5485 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
5486 struct hwrm_async_event_cmpl_pf_drvr_load {
5489 * This field indicates the exact type of the completion.
5490 * By convention, the LSB identifies the length of the
5491 * record in 16B units. Even values indicate 16B
5492 * records. Odd values indicate 32B
5495 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
5497 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
5498 /* HWRM Asynchronous Event Information */
5499 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5501 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
5502 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5503 /* Identifiers of events. */
5505 /* PF driver loaded */
5506 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
5508 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
5509 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
5510 /* Event specific data */
5511 uint32_t event_data2;
5514 * This value is written by the NIC such that it will be different
5515 * for each pass through the completion queue. The even passes
5516 * will write 1. The odd passes will write 0.
5518 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
5520 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5521 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
5522 /* 8-lsb timestamp from POR (100-msec resolution) */
5523 uint8_t timestamp_lo;
5524 /* 16-lsb timestamp from POR (100-msec resolution) */
5525 uint16_t timestamp_hi;
5526 /* Event specific data */
5527 uint32_t event_data1;
5529 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5532 /* Indicates the physical port this pf belongs to */
5533 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
5535 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
5536 } __attribute__((packed));
5538 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
5539 struct hwrm_async_event_cmpl_vf_flr {
5542 * This field indicates the exact type of the completion.
5543 * By convention, the LSB identifies the length of the
5544 * record in 16B units. Even values indicate 16B
5545 * records. Odd values indicate 32B
5548 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
5550 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
5551 /* HWRM Asynchronous Event Information */
5552 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
5554 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
5555 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
5556 /* Identifiers of events. */
5558 /* VF Function Level Reset (FLR) */
5559 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
5560 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
5561 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
5562 /* Event specific data */
5563 uint32_t event_data2;
5566 * This value is written by the NIC such that it will be different
5567 * for each pass through the completion queue. The even passes
5568 * will write 1. The odd passes will write 0.
5570 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
5572 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
5573 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
5574 /* 8-lsb timestamp from POR (100-msec resolution) */
5575 uint8_t timestamp_lo;
5576 /* 16-lsb timestamp from POR (100-msec resolution) */
5577 uint16_t timestamp_hi;
5578 /* Event specific data */
5579 uint32_t event_data1;
5581 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
5583 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5584 /* Indicates the physical function this event occurred on. */
5585 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5587 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5588 } __attribute__((packed));
5590 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5591 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5594 * This field indicates the exact type of the completion.
5595 * By convention, the LSB identifies the length of the
5596 * record in 16B units. Even values indicate 16B
5597 * records. Odd values indicate 32B
5600 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5602 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5603 /* HWRM Asynchronous Event Information */
5604 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5606 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5607 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5608 /* Identifiers of events. */
5610 /* VF MAC Address Change */
5611 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5613 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5614 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5615 /* Event specific data */
5616 uint32_t event_data2;
5619 * This value is written by the NIC such that it will be different
5620 * for each pass through the completion queue. The even passes
5621 * will write 1. The odd passes will write 0.
5623 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5626 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5628 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5629 /* 8-lsb timestamp from POR (100-msec resolution) */
5630 uint8_t timestamp_lo;
5631 /* 16-lsb timestamp from POR (100-msec resolution) */
5632 uint16_t timestamp_hi;
5633 /* Event specific data */
5634 uint32_t event_data1;
5636 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5638 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5640 } __attribute__((packed));
5642 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5643 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5646 * This field indicates the exact type of the completion.
5647 * By convention, the LSB identifies the length of the
5648 * record in 16B units. Even values indicate 16B
5649 * records. Odd values indicate 32B
5652 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5654 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5656 /* HWRM Asynchronous Event Information */
5657 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5659 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5660 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5661 /* Identifiers of events. */
5663 /* PF-VF communication channel status change. */
5664 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5666 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5667 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5668 /* Event specific data */
5669 uint32_t event_data2;
5672 * This value is written by the NIC such that it will be different
5673 * for each pass through the completion queue. The even passes
5674 * will write 1. The odd passes will write 0.
5676 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5679 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5681 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5682 /* 8-lsb timestamp from POR (100-msec resolution) */
5683 uint8_t timestamp_lo;
5684 /* 16-lsb timestamp from POR (100-msec resolution) */
5685 uint16_t timestamp_hi;
5686 /* Event specific data */
5687 uint32_t event_data1;
5689 * If this bit is set to 1, then it indicates that the PF-VF
5690 * communication was lost and it is established.
5691 * If this bit set to 0, then it indicates that the PF-VF
5692 * communication was established and it is lost.
5694 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5696 } __attribute__((packed));
5698 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5699 struct hwrm_async_event_cmpl_vf_cfg_change {
5702 * This field indicates the exact type of the completion.
5703 * By convention, the LSB identifies the length of the
5704 * record in 16B units. Even values indicate 16B
5705 * records. Odd values indicate 32B
5708 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5710 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5711 /* HWRM Asynchronous Event Information */
5712 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5714 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5715 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5716 /* Identifiers of events. */
5718 /* VF Configuration Change */
5719 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5721 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5722 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5723 /* Event specific data */
5724 uint32_t event_data2;
5727 * This value is written by the NIC such that it will be different
5728 * for each pass through the completion queue. The even passes
5729 * will write 1. The odd passes will write 0.
5731 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5733 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5734 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5735 /* 8-lsb timestamp from POR (100-msec resolution) */
5736 uint8_t timestamp_lo;
5737 /* 16-lsb timestamp from POR (100-msec resolution) */
5738 uint16_t timestamp_hi;
5740 * Each flag provided in this field indicates a specific VF
5741 * configuration change. At least one of these flags shall be set to 1
5742 * when an asynchronous event completion of this type is provided
5745 uint32_t event_data1;
5747 * If this bit is set to 1, then the value of MTU
5748 * was changed on this VF.
5749 * If set to 0, then this bit should be ignored.
5751 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5754 * If this bit is set to 1, then the value of MRU
5755 * was changed on this VF.
5756 * If set to 0, then this bit should be ignored.
5758 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5761 * If this bit is set to 1, then the value of default MAC
5762 * address was changed on this VF.
5763 * If set to 0, then this bit should be ignored.
5765 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5768 * If this bit is set to 1, then the value of default VLAN
5769 * was changed on this VF.
5770 * If set to 0, then this bit should be ignored.
5772 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5775 * If this bit is set to 1, then the value of trusted VF enable
5776 * was changed on this VF.
5777 * If set to 0, then this bit should be ignored.
5779 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5781 } __attribute__((packed));
5783 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5784 struct hwrm_async_event_cmpl_llfc_pfc_change {
5787 * This field indicates the exact type of the completion.
5788 * By convention, the LSB identifies the length of the
5789 * record in 16B units. Even values indicate 16B
5790 * records. Odd values indicate 32B
5793 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5795 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5796 /* HWRM Asynchronous Event Information */
5797 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5799 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5800 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5801 /* unused1 is 10 b */
5802 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5804 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5805 /* Identifiers of events. */
5807 /* LLFC/PFC Configuration Change */
5808 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5810 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5811 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5812 /* Event specific data */
5813 uint32_t event_data2;
5816 * This value is written by the NIC such that it will be different
5817 * for each pass through the completion queue. The even passes
5818 * will write 1. The odd passes will write 0.
5820 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5822 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5824 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5825 /* 8-lsb timestamp from POR (100-msec resolution) */
5826 uint8_t timestamp_lo;
5827 /* 16-lsb timestamp from POR (100-msec resolution) */
5828 uint16_t timestamp_hi;
5829 /* Event specific data */
5830 uint32_t event_data1;
5831 /* Indicates llfc pfc status change */
5832 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5834 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5837 * If this field set to 1, then it indicates that llfc is
5840 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5843 * If this field is set to 2, then it indicates that pfc
5846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5849 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5850 /* Indicates the physical port this llfc pfc change occur */
5851 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5853 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5856 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5858 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5860 } __attribute__((packed));
5862 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5863 struct hwrm_async_event_cmpl_default_vnic_change {
5866 * This field indicates the exact type of the completion.
5867 * By convention, the LSB identifies the length of the
5868 * record in 16B units. Even values indicate 16B
5869 * records. Odd values indicate 32B
5872 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5874 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5876 /* HWRM Asynchronous Event Information */
5877 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5879 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5880 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5881 /* unused1 is 10 b */
5882 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5884 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5886 /* Identifiers of events. */
5888 /* Notification of a default vnic allocaiton or free */
5889 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5891 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5892 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5893 /* Event specific data */
5894 uint32_t event_data2;
5897 * This value is written by the NIC such that it will be different
5898 * for each pass through the completion queue. The even passes
5899 * will write 1. The odd passes will write 0.
5901 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5904 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5906 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5907 /* 8-lsb timestamp from POR (100-msec resolution) */
5908 uint8_t timestamp_lo;
5909 /* 16-lsb timestamp from POR (100-msec resolution) */
5910 uint16_t timestamp_hi;
5911 /* Event specific data */
5912 uint32_t event_data1;
5913 /* Indicates default vnic configuration change */
5914 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5916 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5919 * If this field is set to 1, then it indicates that
5920 * a default VNIC has been allocate.
5922 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5925 * If this field is set to 2, then it indicates that
5926 * a default VNIC has been freed.
5928 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5930 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5931 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5932 /* Indicates the physical function this event occurred on. */
5933 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5935 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5937 /* Indicates the virtual function this event occurred on */
5938 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5940 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5942 } __attribute__((packed));
5944 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5945 struct hwrm_async_event_cmpl_hw_flow_aged {
5948 * This field indicates the exact type of the completion.
5949 * By convention, the LSB identifies the length of the
5950 * record in 16B units. Even values indicate 16B
5951 * records. Odd values indicate 32B
5954 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5956 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5957 /* HWRM Asynchronous Event Information */
5958 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5960 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5961 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5962 /* Identifiers of events. */
5964 /* Notification of a hw flow aged */
5965 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5967 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5968 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5969 /* Event specific data */
5970 uint32_t event_data2;
5973 * This value is written by the NIC such that it will be different
5974 * for each pass through the completion queue. The even passes
5975 * will write 1. The odd passes will write 0.
5977 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5979 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5980 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5981 /* 8-lsb timestamp from POR (100-msec resolution) */
5982 uint8_t timestamp_lo;
5983 /* 16-lsb timestamp from POR (100-msec resolution) */
5984 uint16_t timestamp_hi;
5985 /* Event specific data */
5986 uint32_t event_data1;
5987 /* Indicates flow ID this event occurred on. */
5988 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5989 UINT32_C(0x7fffffff)
5990 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5992 /* Indicates flow direction this event occurred on. */
5993 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5994 UINT32_C(0x80000000)
5996 * If this bit set to 0, then it indicates that the aged
5997 * event was rx flow.
5999 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
6000 (UINT32_C(0x0) << 31)
6002 * If this bit is set to 1, then it indicates that the aged
6003 * event was tx flow.
6005 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
6006 (UINT32_C(0x1) << 31)
6007 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
6008 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
6009 } __attribute__((packed));
6011 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
6012 struct hwrm_async_event_cmpl_eem_cache_flush_req {
6015 * This field indicates the exact type of the completion.
6016 * By convention, the LSB identifies the length of the
6017 * record in 16B units. Even values indicate 16B
6018 * records. Odd values indicate 32B
6021 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
6023 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
6025 /* HWRM Asynchronous Event Information */
6026 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
6028 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
6029 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
6030 /* Identifiers of events. */
6032 /* Notification of a eem_cache_flush request */
6033 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6035 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
6036 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
6037 /* Event specific data */
6038 uint32_t event_data2;
6041 * This value is written by the NIC such that it will be different
6042 * for each pass through the completion queue. The even passes
6043 * will write 1. The odd passes will write 0.
6045 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
6048 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
6050 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
6051 /* 8-lsb timestamp from POR (100-msec resolution) */
6052 uint8_t timestamp_lo;
6053 /* 16-lsb timestamp from POR (100-msec resolution) */
6054 uint16_t timestamp_hi;
6055 /* Event specific data */
6056 uint32_t event_data1;
6057 } __attribute__((packed));
6059 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
6060 struct hwrm_async_event_cmpl_eem_cache_flush_done {
6063 * This field indicates the exact type of the completion.
6064 * By convention, the LSB identifies the length of the
6065 * record in 16B units. Even values indicate 16B
6066 * records. Odd values indicate 32B
6069 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
6071 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
6073 /* HWRM Asynchronous Event Information */
6074 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
6076 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
6077 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
6078 /* Identifiers of events. */
6081 * Notification of a host eem_cache_flush has completed. This event
6082 * is generated by the host driver.
6084 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6086 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
6087 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
6088 /* Event specific data */
6089 uint32_t event_data2;
6092 * This value is written by the NIC such that it will be different
6093 * for each pass through the completion queue. The even passes
6094 * will write 1. The odd passes will write 0.
6096 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
6099 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
6101 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
6102 /* 8-lsb timestamp from POR (100-msec resolution) */
6103 uint8_t timestamp_lo;
6104 /* 16-lsb timestamp from POR (100-msec resolution) */
6105 uint16_t timestamp_hi;
6106 /* Event specific data */
6107 uint32_t event_data1;
6108 /* Indicates function ID that this event occurred on. */
6109 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
6111 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
6113 } __attribute__((packed));
6115 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
6116 struct hwrm_async_event_cmpl_tcp_flag_action_change {
6119 * This field indicates the exact type of the completion.
6120 * By convention, the LSB identifies the length of the
6121 * record in 16B units. Even values indicate 16B
6122 * records. Odd values indicate 32B
6125 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
6127 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
6129 /* HWRM Asynchronous Event Information */
6130 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6132 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
6133 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
6134 /* Identifiers of events. */
6136 /* Notification of tcp flag action change */
6137 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6139 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
6140 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
6141 /* Event specific data */
6142 uint32_t event_data2;
6145 * This value is written by the NIC such that it will be different
6146 * for each pass through the completion queue. The even passes
6147 * will write 1. The odd passes will write 0.
6149 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
6152 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
6154 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
6155 /* 8-lsb timestamp from POR (100-msec resolution) */
6156 uint8_t timestamp_lo;
6157 /* 16-lsb timestamp from POR (100-msec resolution) */
6158 uint16_t timestamp_hi;
6159 /* Event specific data */
6160 uint32_t event_data1;
6161 } __attribute__((packed));
6163 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
6164 struct hwrm_async_event_cmpl_eem_flow_active {
6167 * This field indicates the exact type of the completion.
6168 * By convention, the LSB identifies the length of the
6169 * record in 16B units. Even values indicate 16B
6170 * records. Odd values indicate 32B
6173 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
6175 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
6176 /* HWRM Asynchronous Event Information */
6177 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
6179 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
6180 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
6181 /* Identifiers of events. */
6183 /* Notification of an active eem flow */
6184 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
6186 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
6187 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
6188 /* Event specific data */
6189 uint32_t event_data2;
6190 /* Indicates the 2nd global id this event occurred on. */
6191 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
6192 UINT32_C(0x3fffffff)
6193 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
6196 * Indicates flow direction of the flow identified by
6199 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
6200 UINT32_C(0x40000000)
6201 /* If this bit is set to 0, then it indicates that this rx flow. */
6202 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
6203 (UINT32_C(0x0) << 30)
6204 /* If this bit is set to 1, then it indicates that this tx flow. */
6205 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
6206 (UINT32_C(0x1) << 30)
6207 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
6208 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
6211 * This value is written by the NIC such that it will be different
6212 * for each pass through the completion queue. The even passes
6213 * will write 1. The odd passes will write 0.
6215 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
6217 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
6219 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
6220 /* 8-lsb timestamp from POR (100-msec resolution) */
6221 uint8_t timestamp_lo;
6222 /* 16-lsb timestamp from POR (100-msec resolution) */
6223 uint16_t timestamp_hi;
6224 /* Event specific data */
6225 uint32_t event_data1;
6226 /* Indicates the 1st global id this event occurred on. */
6227 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
6228 UINT32_C(0x3fffffff)
6229 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
6232 * Indicates flow direction of the flow identified by the
6235 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
6236 UINT32_C(0x40000000)
6237 /* If this bit is set to 0, then it indicates that this is rx flow. */
6238 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
6239 (UINT32_C(0x0) << 30)
6240 /* If this bit is set to 1, then it indicates that this is tx flow. */
6241 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
6242 (UINT32_C(0x1) << 30)
6243 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
6244 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
6246 * Indicates EEM flow aging mode this event occurred on. If
6247 * this bit is set to 0, the event_data1 is the EEM global
6248 * ID. If this bit is set to 1, the event_data1 is the number
6249 * of global ID in the context memory.
6251 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
6252 UINT32_C(0x80000000)
6253 /* EEM flow aging mode 0. */
6254 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
6255 (UINT32_C(0x0) << 31)
6256 /* EEM flow aging mode 1. */
6257 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
6258 (UINT32_C(0x1) << 31)
6259 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
6260 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
6261 } __attribute__((packed));
6263 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
6264 struct hwrm_async_event_cmpl_eem_cfg_change {
6267 * This field indicates the exact type of the completion.
6268 * By convention, the LSB identifies the length of the
6269 * record in 16B units. Even values indicate 16B
6270 * records. Odd values indicate 32B
6273 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
6275 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
6276 /* HWRM Asynchronous Event Information */
6277 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6279 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
6280 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6281 /* Identifiers of events. */
6283 /* Notification of EEM configuration change */
6284 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
6286 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
6288 /* Event specific data */
6289 uint32_t event_data2;
6292 * This value is written by the NIC such that it will be different
6293 * for each pass through the completion queue. The even passes
6294 * will write 1. The odd passes will write 0.
6296 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
6298 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
6299 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
6300 /* 8-lsb timestamp from POR (100-msec resolution) */
6301 uint8_t timestamp_lo;
6302 /* 16-lsb timestamp from POR (100-msec resolution) */
6303 uint16_t timestamp_hi;
6304 /* Event specific data */
6305 uint32_t event_data1;
6307 * Value of 1 to indicate EEM TX configuration is enabled. Value of
6308 * 0 to indicate the EEM TX configuration is disabled.
6310 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
6313 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
6314 * to indicate the EEM RX configuration is disabled.
6316 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
6318 } __attribute__((packed));
6320 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
6321 struct hwrm_async_event_cmpl_fw_trace_msg {
6324 * This field indicates the exact type of the completion.
6325 * By convention, the LSB identifies the length of the
6326 * record in 16B units. Even values indicate 16B
6327 * records. Odd values indicate 32B
6330 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
6332 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
6333 /* HWRM Asynchronous Event Information */
6334 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
6336 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
6337 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
6338 /* Identifiers of events. */
6340 /* Firmware trace log message */
6341 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
6343 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
6344 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
6345 /* Trace byte 0 to 3 */
6346 uint32_t event_data2;
6348 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
6350 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
6352 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
6354 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
6356 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
6358 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
6360 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
6361 UINT32_C(0xff000000)
6362 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
6365 * This value is written by the NIC such that it will be different
6366 * for each pass through the completion queue. The even passes
6367 * will write 1. The odd passes will write 0.
6369 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
6371 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
6372 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
6374 uint8_t timestamp_lo;
6375 /* Indicates if the string is partial or complete. */
6376 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
6378 /* Complete string */
6379 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
6381 /* Partial string */
6382 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
6384 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
6385 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
6386 /* Indicates the firmware that sent the trace message. */
6387 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
6389 /* Primary firmware */
6390 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
6391 (UINT32_C(0x0) << 1)
6392 /* Secondary firmware */
6393 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
6394 (UINT32_C(0x1) << 1)
6395 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
6396 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
6397 /* Trace byte 4 to 5 */
6398 uint16_t timestamp_hi;
6400 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
6402 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
6404 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
6406 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
6407 /* Trace byte 6 to 9 */
6408 uint32_t event_data1;
6410 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
6412 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
6414 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
6416 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
6418 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
6420 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
6422 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
6423 UINT32_C(0xff000000)
6424 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
6425 } __attribute__((packed));
6427 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
6428 struct hwrm_async_event_cmpl_hwrm_error {
6431 * This field indicates the exact type of the completion.
6432 * By convention, the LSB identifies the length of the
6433 * record in 16B units. Even values indicate 16B
6434 * records. Odd values indicate 32B
6437 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
6439 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
6440 /* HWRM Asynchronous Event Information */
6441 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
6443 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
6444 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
6445 /* Identifiers of events. */
6448 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
6450 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
6451 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
6452 /* Event specific data */
6453 uint32_t event_data2;
6454 /* Severity of HWRM Error */
6455 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
6457 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
6459 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
6461 /* Non-fatal Error */
6462 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
6465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
6467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
6468 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
6471 * This value is written by the NIC such that it will be different
6472 * for each pass through the completion queue. The even passes
6473 * will write 1. The odd passes will write 0.
6475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
6477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
6478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
6479 /* 8-lsb timestamp from POR (100-msec resolution) */
6480 uint8_t timestamp_lo;
6481 /* 16-lsb timestamp from POR (100-msec resolution) */
6482 uint16_t timestamp_hi;
6483 /* Event specific data */
6484 uint32_t event_data1;
6485 /* Time stamp for error event */
6486 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
6488 } __attribute__((packed));
6490 /*******************
6492 *******************/
6495 /* hwrm_func_reset_input (size:192b/24B) */
6496 struct hwrm_func_reset_input {
6497 /* The HWRM command request type. */
6500 * The completion ring to send the completion event on. This should
6501 * be the NQ ID returned from the `nq_alloc` HWRM command.
6505 * The sequence ID is used by the driver for tracking multiple
6506 * commands. This ID is treated as opaque data by the firmware and
6507 * the value is returned in the `hwrm_resp_hdr` upon completion.
6511 * The target ID of the command:
6512 * * 0x0-0xFFF8 - The function ID
6513 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6514 * * 0xFFFD - Reserved for user-space HWRM interface
6519 * A physical address pointer pointing to a host buffer that the
6520 * command's response data will be written. This can be either a host
6521 * physical address (HPA) or a guest physical address (GPA) and must
6522 * point to a physically contiguous block of memory.
6527 * This bit must be '1' for the vf_id_valid field to be
6530 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
6532 * The ID of the VF that this PF is trying to reset.
6533 * Only the parent PF shall be allowed to reset a child VF.
6535 * A parent PF driver shall use this field only when a specific child VF
6536 * is requested to be reset.
6539 /* This value indicates the level of a function reset. */
6540 uint8_t func_reset_level;
6542 * Reset the caller function and its children VFs (if any). If no
6543 * children functions exist, then reset the caller function only.
6545 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
6547 /* Reset the caller function only */
6548 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
6551 * Reset all children VFs of the caller function driver if the
6552 * caller is a PF driver.
6553 * It is an error to specify this level by a VF driver.
6554 * It is an error to specify this level by a PF driver with
6557 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
6560 * Reset a specific VF of the caller function driver if the caller
6561 * is the parent PF driver.
6562 * It is an error to specify this level by a VF driver.
6563 * It is an error to specify this level by a PF driver that is not
6564 * the parent of the VF that is being requested to reset.
6566 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
6568 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
6569 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
6571 } __attribute__((packed));
6573 /* hwrm_func_reset_output (size:128b/16B) */
6574 struct hwrm_func_reset_output {
6575 /* The specific error status for the command. */
6576 uint16_t error_code;
6577 /* The HWRM command request type. */
6579 /* The sequence ID from the original command. */
6581 /* The length of the response data in number of bytes. */
6583 uint8_t unused_0[7];
6585 * This field is used in Output records to indicate that the output
6586 * is completely written to RAM. This field should be read as '1'
6587 * to indicate that the output has been completely written.
6588 * When writing a command completion or response to an internal processor,
6589 * the order of writes has to be such that this field is written last.
6592 } __attribute__((packed));
6594 /********************
6595 * hwrm_func_getfid *
6596 ********************/
6599 /* hwrm_func_getfid_input (size:192b/24B) */
6600 struct hwrm_func_getfid_input {
6601 /* The HWRM command request type. */
6604 * The completion ring to send the completion event on. This should
6605 * be the NQ ID returned from the `nq_alloc` HWRM command.
6609 * The sequence ID is used by the driver for tracking multiple
6610 * commands. This ID is treated as opaque data by the firmware and
6611 * the value is returned in the `hwrm_resp_hdr` upon completion.
6615 * The target ID of the command:
6616 * * 0x0-0xFFF8 - The function ID
6617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6618 * * 0xFFFD - Reserved for user-space HWRM interface
6623 * A physical address pointer pointing to a host buffer that the
6624 * command's response data will be written. This can be either a host
6625 * physical address (HPA) or a guest physical address (GPA) and must
6626 * point to a physically contiguous block of memory.
6631 * This bit must be '1' for the pci_id field to be
6634 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6636 * This value is the PCI ID of the queried function.
6637 * If ARI is enabled, then it is
6638 * Bus Number (8b):Function Number(8b). Otherwise, it is
6639 * Bus Number (8b):Device Number (5b):Function Number(3b).
6642 uint8_t unused_0[2];
6643 } __attribute__((packed));
6645 /* hwrm_func_getfid_output (size:128b/16B) */
6646 struct hwrm_func_getfid_output {
6647 /* The specific error status for the command. */
6648 uint16_t error_code;
6649 /* The HWRM command request type. */
6651 /* The sequence ID from the original command. */
6653 /* The length of the response data in number of bytes. */
6656 * FID value. This value is used to identify operations on the PCI
6657 * bus as belonging to a particular PCI function.
6660 uint8_t unused_0[5];
6662 * This field is used in Output records to indicate that the output
6663 * is completely written to RAM. This field should be read as '1'
6664 * to indicate that the output has been completely written.
6665 * When writing a command completion or response to an internal processor,
6666 * the order of writes has to be such that this field is written last.
6669 } __attribute__((packed));
6671 /**********************
6672 * hwrm_func_vf_alloc *
6673 **********************/
6676 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6677 struct hwrm_func_vf_alloc_input {
6678 /* The HWRM command request type. */
6681 * The completion ring to send the completion event on. This should
6682 * be the NQ ID returned from the `nq_alloc` HWRM command.
6686 * The sequence ID is used by the driver for tracking multiple
6687 * commands. This ID is treated as opaque data by the firmware and
6688 * the value is returned in the `hwrm_resp_hdr` upon completion.
6692 * The target ID of the command:
6693 * * 0x0-0xFFF8 - The function ID
6694 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6695 * * 0xFFFD - Reserved for user-space HWRM interface
6700 * A physical address pointer pointing to a host buffer that the
6701 * command's response data will be written. This can be either a host
6702 * physical address (HPA) or a guest physical address (GPA) and must
6703 * point to a physically contiguous block of memory.
6708 * This bit must be '1' for the first_vf_id field to be
6711 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6713 * This value is used to identify a Virtual Function (VF).
6714 * The scope of VF ID is local within a PF.
6716 uint16_t first_vf_id;
6717 /* The number of virtual functions requested. */
6719 } __attribute__((packed));
6721 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6722 struct hwrm_func_vf_alloc_output {
6723 /* The specific error status for the command. */
6724 uint16_t error_code;
6725 /* The HWRM command request type. */
6727 /* The sequence ID from the original command. */
6729 /* The length of the response data in number of bytes. */
6731 /* The ID of the first VF allocated. */
6732 uint16_t first_vf_id;
6733 uint8_t unused_0[5];
6735 * This field is used in Output records to indicate that the output
6736 * is completely written to RAM. This field should be read as '1'
6737 * to indicate that the output has been completely written.
6738 * When writing a command completion or response to an internal processor,
6739 * the order of writes has to be such that this field is written last.
6742 } __attribute__((packed));
6744 /*********************
6745 * hwrm_func_vf_free *
6746 *********************/
6749 /* hwrm_func_vf_free_input (size:192b/24B) */
6750 struct hwrm_func_vf_free_input {
6751 /* The HWRM command request type. */
6754 * The completion ring to send the completion event on. This should
6755 * be the NQ ID returned from the `nq_alloc` HWRM command.
6759 * The sequence ID is used by the driver for tracking multiple
6760 * commands. This ID is treated as opaque data by the firmware and
6761 * the value is returned in the `hwrm_resp_hdr` upon completion.
6765 * The target ID of the command:
6766 * * 0x0-0xFFF8 - The function ID
6767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6768 * * 0xFFFD - Reserved for user-space HWRM interface
6773 * A physical address pointer pointing to a host buffer that the
6774 * command's response data will be written. This can be either a host
6775 * physical address (HPA) or a guest physical address (GPA) and must
6776 * point to a physically contiguous block of memory.
6781 * This bit must be '1' for the first_vf_id field to be
6784 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6786 * This value is used to identify a Virtual Function (VF).
6787 * The scope of VF ID is local within a PF.
6789 uint16_t first_vf_id;
6791 * The number of virtual functions requested.
6792 * 0xFFFF - Cleanup all children of this PF.
6795 } __attribute__((packed));
6797 /* hwrm_func_vf_free_output (size:128b/16B) */
6798 struct hwrm_func_vf_free_output {
6799 /* The specific error status for the command. */
6800 uint16_t error_code;
6801 /* The HWRM command request type. */
6803 /* The sequence ID from the original command. */
6805 /* The length of the response data in number of bytes. */
6807 uint8_t unused_0[7];
6809 * This field is used in Output records to indicate that the output
6810 * is completely written to RAM. This field should be read as '1'
6811 * to indicate that the output has been completely written.
6812 * When writing a command completion or response to an internal processor,
6813 * the order of writes has to be such that this field is written last.
6816 } __attribute__((packed));
6818 /********************
6819 * hwrm_func_vf_cfg *
6820 ********************/
6823 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6824 struct hwrm_func_vf_cfg_input {
6825 /* The HWRM command request type. */
6828 * The completion ring to send the completion event on. This should
6829 * be the NQ ID returned from the `nq_alloc` HWRM command.
6833 * The sequence ID is used by the driver for tracking multiple
6834 * commands. This ID is treated as opaque data by the firmware and
6835 * the value is returned in the `hwrm_resp_hdr` upon completion.
6839 * The target ID of the command:
6840 * * 0x0-0xFFF8 - The function ID
6841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6842 * * 0xFFFD - Reserved for user-space HWRM interface
6847 * A physical address pointer pointing to a host buffer that the
6848 * command's response data will be written. This can be either a host
6849 * physical address (HPA) or a guest physical address (GPA) and must
6850 * point to a physically contiguous block of memory.
6855 * This bit must be '1' for the mtu field to be
6858 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6861 * This bit must be '1' for the guest_vlan field to be
6864 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6867 * This bit must be '1' for the async_event_cr field to be
6870 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6873 * This bit must be '1' for the dflt_mac_addr field to be
6876 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6879 * This bit must be '1' for the num_rsscos_ctxs field to be
6882 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6885 * This bit must be '1' for the num_cmpl_rings field to be
6888 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6891 * This bit must be '1' for the num_tx_rings field to be
6894 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6897 * This bit must be '1' for the num_rx_rings field to be
6900 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6903 * This bit must be '1' for the num_l2_ctxs field to be
6906 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6909 * This bit must be '1' for the num_vnics field to be
6912 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
6915 * This bit must be '1' for the num_stat_ctxs field to be
6918 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6921 * This bit must be '1' for the num_hw_ring_grps field to be
6924 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6927 * The maximum transmission unit requested on the function.
6928 * The HWRM should make sure that the mtu of
6929 * the function does not exceed the mtu of the physical
6930 * port that this function is associated with.
6932 * In addition to requesting mtu per function, it is
6933 * possible to configure mtu per transmit ring.
6934 * By default, the mtu of each transmit ring associated
6935 * with a function is equal to the mtu of the function.
6936 * The HWRM should make sure that the mtu of each transmit
6937 * ring that is assigned to a function has a valid mtu.
6941 * The guest VLAN for the function being configured.
6942 * This field's format is same as 802.1Q Tag's
6943 * Tag Control Information (TCI) format that includes both
6944 * Priority Code Point (PCP) and VLAN Identifier (VID).
6946 uint16_t guest_vlan;
6948 * ID of the target completion ring for receiving asynchronous
6949 * event completions. If this field is not valid, then the
6950 * HWRM shall use the default completion ring of the function
6951 * that is being configured as the target completion ring for
6952 * providing any asynchronous event completions for that
6954 * If this field is valid, then the HWRM shall use the
6955 * completion ring identified by this ID as the target
6956 * completion ring for providing any asynchronous event
6957 * completions for the function that is being configured.
6959 uint16_t async_event_cr;
6961 * This value is the current MAC address requested by the VF
6962 * driver to be configured on this VF. A value of
6963 * 00-00-00-00-00-00 indicates no MAC address configuration
6964 * is requested by the VF driver.
6965 * The parent PF driver may reject or overwrite this
6968 uint8_t dflt_mac_addr[6];
6971 * This bit requests that the firmware test to see if all the assets
6972 * requested in this command (i.e. number of TX rings) are available.
6973 * The firmware will return an error if the requested assets are
6974 * not available. The firwmare will NOT reserve the assets if they
6977 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6980 * This bit requests that the firmware test to see if all the assets
6981 * requested in this command (i.e. number of RX rings) are available.
6982 * The firmware will return an error if the requested assets are
6983 * not available. The firwmare will NOT reserve the assets if they
6986 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6989 * This bit requests that the firmware test to see if all the assets
6990 * requested in this command (i.e. number of CMPL rings) are available.
6991 * The firmware will return an error if the requested assets are
6992 * not available. The firwmare will NOT reserve the assets if they
6995 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6998 * This bit requests that the firmware test to see if all the assets
6999 * requested in this command (i.e. number of RSS ctx) are available.
7000 * The firmware will return an error if the requested assets are
7001 * not available. The firwmare will NOT reserve the assets if they
7004 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7007 * This bit requests that the firmware test to see if all the assets
7008 * requested in this command (i.e. number of ring groups) are available.
7009 * The firmware will return an error if the requested assets are
7010 * not available. The firwmare will NOT reserve the assets if they
7013 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7016 * This bit requests that the firmware test to see if all the assets
7017 * requested in this command (i.e. number of stat ctx) are available.
7018 * The firmware will return an error if the requested assets are
7019 * not available. The firwmare will NOT reserve the assets if they
7022 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7025 * This bit requests that the firmware test to see if all the assets
7026 * requested in this command (i.e. number of VNICs) are available.
7027 * The firmware will return an error if the requested assets are
7028 * not available. The firwmare will NOT reserve the assets if they
7031 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7034 * This bit requests that the firmware test to see if all the assets
7035 * requested in this command (i.e. number of L2 ctx) are available.
7036 * The firmware will return an error if the requested assets are
7037 * not available. The firwmare will NOT reserve the assets if they
7040 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7042 /* The number of RSS/COS contexts requested for the VF. */
7043 uint16_t num_rsscos_ctxs;
7044 /* The number of completion rings requested for the VF. */
7045 uint16_t num_cmpl_rings;
7046 /* The number of transmit rings requested for the VF. */
7047 uint16_t num_tx_rings;
7048 /* The number of receive rings requested for the VF. */
7049 uint16_t num_rx_rings;
7050 /* The number of L2 contexts requested for the VF. */
7051 uint16_t num_l2_ctxs;
7052 /* The number of vnics requested for the VF. */
7054 /* The number of statistic contexts requested for the VF. */
7055 uint16_t num_stat_ctxs;
7056 /* The number of HW ring groups requested for the VF. */
7057 uint16_t num_hw_ring_grps;
7058 uint8_t unused_0[4];
7059 } __attribute__((packed));
7061 /* hwrm_func_vf_cfg_output (size:128b/16B) */
7062 struct hwrm_func_vf_cfg_output {
7063 /* The specific error status for the command. */
7064 uint16_t error_code;
7065 /* The HWRM command request type. */
7067 /* The sequence ID from the original command. */
7069 /* The length of the response data in number of bytes. */
7071 uint8_t unused_0[7];
7073 * This field is used in Output records to indicate that the output
7074 * is completely written to RAM. This field should be read as '1'
7075 * to indicate that the output has been completely written.
7076 * When writing a command completion or response to an internal processor,
7077 * the order of writes has to be such that this field is written last.
7080 } __attribute__((packed));
7082 /*******************
7084 *******************/
7087 /* hwrm_func_qcaps_input (size:192b/24B) */
7088 struct hwrm_func_qcaps_input {
7089 /* The HWRM command request type. */
7092 * The completion ring to send the completion event on. This should
7093 * be the NQ ID returned from the `nq_alloc` HWRM command.
7097 * The sequence ID is used by the driver for tracking multiple
7098 * commands. This ID is treated as opaque data by the firmware and
7099 * the value is returned in the `hwrm_resp_hdr` upon completion.
7103 * The target ID of the command:
7104 * * 0x0-0xFFF8 - The function ID
7105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7106 * * 0xFFFD - Reserved for user-space HWRM interface
7111 * A physical address pointer pointing to a host buffer that the
7112 * command's response data will be written. This can be either a host
7113 * physical address (HPA) or a guest physical address (GPA) and must
7114 * point to a physically contiguous block of memory.
7118 * Function ID of the function that is being queried.
7119 * 0xFF... (All Fs) if the query is for the requesting
7123 uint8_t unused_0[6];
7124 } __attribute__((packed));
7126 /* hwrm_func_qcaps_output (size:640b/80B) */
7127 struct hwrm_func_qcaps_output {
7128 /* The specific error status for the command. */
7129 uint16_t error_code;
7130 /* The HWRM command request type. */
7132 /* The sequence ID from the original command. */
7134 /* The length of the response data in number of bytes. */
7137 * FID value. This value is used to identify operations on the PCI
7138 * bus as belonging to a particular PCI function.
7142 * Port ID of port that this function is associated with.
7143 * Valid only for the PF.
7144 * 0xFF... (All Fs) if this function is not associated with
7146 * 0xFF... (All Fs) if this function is called from a VF.
7150 /* If 1, then Push mode is supported on this function. */
7151 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
7154 * If 1, then the global MSI-X auto-masking is enabled for the
7157 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
7160 * If 1, then the Precision Time Protocol (PTP) processing
7161 * is supported on this function.
7162 * The HWRM should enable PTP on only a single Physical
7163 * Function (PF) per port.
7165 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
7168 * If 1, then RDMA over Converged Ethernet (RoCE) v1
7169 * is supported on this function.
7171 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
7174 * If 1, then RDMA over Converged Ethernet (RoCE) v2
7175 * is supported on this function.
7177 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
7180 * If 1, then control and configuration of WoL magic packet
7181 * are supported on this function.
7183 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
7186 * If 1, then control and configuration of bitmap pattern
7187 * packet are supported on this function.
7189 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
7192 * If set to 1, then the control and configuration of rate limit
7193 * of an allocated TX ring on the queried function is supported.
7195 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
7198 * If 1, then control and configuration of minimum and
7199 * maximum bandwidths are supported on the queried function.
7201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
7204 * If the query is for a VF, then this flag shall be ignored.
7205 * If this query is for a PF and this flag is set to 1,
7206 * then the PF has the capability to set the rate limits
7207 * on the TX rings of its children VFs.
7208 * If this query is for a PF and this flag is set to 0, then
7209 * the PF does not have the capability to set the rate limits
7210 * on the TX rings of its children VFs.
7212 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
7215 * If the query is for a VF, then this flag shall be ignored.
7216 * If this query is for a PF and this flag is set to 1,
7217 * then the PF has the capability to set the minimum and/or
7218 * maximum bandwidths for its children VFs.
7219 * If this query is for a PF and this flag is set to 0, then
7220 * the PF does not have the capability to set the minimum or
7221 * maximum bandwidths for its children VFs.
7223 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
7226 * Standard TX Ring mode is used for the allocation of TX ring
7227 * and underlying scheduling resources that allow bandwidth
7228 * reservation and limit settings on the queried function.
7229 * If set to 1, then standard TX ring mode is supported
7230 * on the queried function.
7231 * If set to 0, then standard TX ring mode is not available
7232 * on the queried function.
7234 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
7237 * If the query is for a VF, then this flag shall be ignored,
7238 * If this query is for a PF and this flag is set to 1,
7239 * then the PF has the capability to detect GENEVE tunnel
7242 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
7245 * If the query is for a VF, then this flag shall be ignored,
7246 * If this query is for a PF and this flag is set to 1,
7247 * then the PF has the capability to detect NVGRE tunnel
7250 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
7253 * If the query is for a VF, then this flag shall be ignored,
7254 * If this query is for a PF and this flag is set to 1,
7255 * then the PF has the capability to detect GRE tunnel
7258 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
7261 * If the query is for a VF, then this flag shall be ignored,
7262 * If this query is for a PF and this flag is set to 1,
7263 * then the PF has the capability to detect MPLS tunnel
7266 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
7269 * If the query is for a VF, then this flag shall be ignored,
7270 * If this query is for a PF and this flag is set to 1,
7271 * then the PF has the capability to support pcie stats.
7273 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
7276 * If the query is for a VF, then this flag shall be ignored,
7277 * If this query is for a PF and this flag is set to 1,
7278 * then the PF has the capability to adopt the VF's belonging
7281 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
7284 * If the query is for a VF, then this flag shall be ignored,
7285 * If this query is for a PF and this flag is set to 1,
7286 * then the PF has the administrative privilege to configure another PF
7288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
7291 * If the query is for a VF, then this flag shall be ignored.
7292 * If this query is for a PF and this flag is set to 1, then
7293 * the PF will know that the firmware has the capability to track
7294 * the virtual link status.
7296 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
7299 * If 1, then this function supports the push mode that uses
7300 * write combine buffers and the long inline tx buffer descriptor.
7302 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
7305 * If 1, then FW has capability to allocate TX rings dynamically
7306 * in ring alloc even if PF reserved pool is zero.
7307 * This bit will be used only for PFs.
7309 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7312 * When this bit is '1', it indicates that core firmware is
7313 * capable of Hot Reset.
7315 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
7318 * This flag will be set to 1 by the FW if FW supports adapter error
7321 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
7324 * If the query is for a VF, then this flag shall be ignored.
7325 * If this query is for a PF and this flag is set to 1, then
7326 * the PF has the capability to support extended stats.
7328 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
7331 * If the query is for a VF, then this flag shall be ignored.
7332 * If this query is for a PF and this flag is set to 1, then host
7333 * must initiate reset or reload (or fastboot) the firmware image
7334 * upon detection of device shutdown state.
7336 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
7339 * This value is current MAC address configured for this
7340 * function. A value of 00-00-00-00-00-00 indicates no
7341 * MAC address is currently configured.
7343 uint8_t mac_address[6];
7345 * The maximum number of RSS/COS contexts that can be
7346 * allocated to the function.
7348 uint16_t max_rsscos_ctx;
7350 * The maximum number of completion rings that can be
7351 * allocated to the function.
7353 uint16_t max_cmpl_rings;
7355 * The maximum number of transmit rings that can be
7356 * allocated to the function.
7358 uint16_t max_tx_rings;
7360 * The maximum number of receive rings that can be
7361 * allocated to the function.
7363 uint16_t max_rx_rings;
7365 * The maximum number of L2 contexts that can be
7366 * allocated to the function.
7368 uint16_t max_l2_ctxs;
7370 * The maximum number of VNICs that can be
7371 * allocated to the function.
7375 * The identifier for the first VF enabled on a PF. This
7376 * is valid only on the PF with SR-IOV enabled.
7377 * 0xFF... (All Fs) if this command is called on a PF with
7378 * SR-IOV disabled or on a VF.
7380 uint16_t first_vf_id;
7382 * The maximum number of VFs that can be
7383 * allocated to the function. This is valid only on the
7384 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
7385 * command is called on a PF with SR-IOV disabled or
7390 * The maximum number of statistic contexts that can be
7391 * allocated to the function.
7393 uint16_t max_stat_ctx;
7395 * The maximum number of Encapsulation records that can be
7396 * offloaded by this function.
7398 uint32_t max_encap_records;
7400 * The maximum number of decapsulation records that can
7401 * be offloaded by this function.
7403 uint32_t max_decap_records;
7405 * The maximum number of Exact Match (EM) flows that can be
7406 * offloaded by this function on the TX side.
7408 uint32_t max_tx_em_flows;
7410 * The maximum number of Wildcard Match (WM) flows that can
7411 * be offloaded by this function on the TX side.
7413 uint32_t max_tx_wm_flows;
7415 * The maximum number of Exact Match (EM) flows that can be
7416 * offloaded by this function on the RX side.
7418 uint32_t max_rx_em_flows;
7420 * The maximum number of Wildcard Match (WM) flows that can
7421 * be offloaded by this function on the RX side.
7423 uint32_t max_rx_wm_flows;
7425 * The maximum number of multicast filters that can
7426 * be supported by this function on the RX side.
7428 uint32_t max_mcast_filters;
7430 * The maximum value of flow_id that can be supported
7431 * in completion records.
7433 uint32_t max_flow_id;
7435 * The maximum number of HW ring groups that can be
7436 * supported on this function.
7438 uint32_t max_hw_ring_grps;
7440 * The maximum number of strict priority transmit rings
7441 * that can be allocated to the function.
7442 * This number indicates the maximum number of TX rings
7443 * that can be assigned strict priorities out of the
7444 * maximum number of TX rings that can be allocated
7445 * (max_tx_rings) to the function.
7447 uint16_t max_sp_tx_rings;
7450 * This field is used in Output records to indicate that the output
7451 * is completely written to RAM. This field should be read as '1'
7452 * to indicate that the output has been completely written.
7453 * When writing a command completion or response to an internal processor,
7454 * the order of writes has to be such that this field is written last.
7457 } __attribute__((packed));
7464 /* hwrm_func_qcfg_input (size:192b/24B) */
7465 struct hwrm_func_qcfg_input {
7466 /* The HWRM command request type. */
7469 * The completion ring to send the completion event on. This should
7470 * be the NQ ID returned from the `nq_alloc` HWRM command.
7474 * The sequence ID is used by the driver for tracking multiple
7475 * commands. This ID is treated as opaque data by the firmware and
7476 * the value is returned in the `hwrm_resp_hdr` upon completion.
7480 * The target ID of the command:
7481 * * 0x0-0xFFF8 - The function ID
7482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7483 * * 0xFFFD - Reserved for user-space HWRM interface
7488 * A physical address pointer pointing to a host buffer that the
7489 * command's response data will be written. This can be either a host
7490 * physical address (HPA) or a guest physical address (GPA) and must
7491 * point to a physically contiguous block of memory.
7495 * Function ID of the function that is being queried.
7496 * 0xFF... (All Fs) if the query is for the requesting
7500 uint8_t unused_0[6];
7501 } __attribute__((packed));
7503 /* hwrm_func_qcfg_output (size:704b/88B) */
7504 struct hwrm_func_qcfg_output {
7505 /* The specific error status for the command. */
7506 uint16_t error_code;
7507 /* The HWRM command request type. */
7509 /* The sequence ID from the original command. */
7511 /* The length of the response data in number of bytes. */
7514 * FID value. This value is used to identify operations on the PCI
7515 * bus as belonging to a particular PCI function.
7519 * Port ID of port that this function is associated with.
7520 * 0xFF... (All Fs) if this function is not associated with
7525 * This value is the current VLAN setting for this
7526 * function. The value of 0 for this field indicates
7527 * no priority tagging or VLAN is used.
7528 * This field's format is same as 802.1Q Tag's
7529 * Tag Control Information (TCI) format that includes both
7530 * Priority Code Point (PCP) and VLAN Identifier (VID).
7535 * If 1, then magic packet based Out-Of-Box WoL is enabled on
7536 * the port associated with this function.
7538 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
7541 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
7542 * on the port associated with this function.
7544 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
7547 * If set to 1, then FW based DCBX agent is enabled and running on
7548 * the port associated with this function.
7549 * If set to 0, then DCBX agent is not running in the firmware.
7551 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
7554 * Standard TX Ring mode is used for the allocation of TX ring
7555 * and underlying scheduling resources that allow bandwidth
7556 * reservation and limit settings on the queried function.
7557 * If set to 1, then standard TX ring mode is enabled
7558 * on the queried function.
7559 * If set to 0, then the standard TX ring mode is disabled
7560 * on the queried function. In this extended TX ring resource
7561 * mode, the minimum and maximum bandwidth settings are not
7562 * supported to allow the allocation of TX rings to span multiple
7565 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
7568 * If set to 1 then FW based LLDP agent is enabled and running on
7569 * the port associated with this function.
7570 * If set to 0 then the LLDP agent is not running in the firmware.
7572 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
7575 * If set to 1, then multi-host mode is active for this function.
7576 * If set to 0, then multi-host mode is inactive for this function
7577 * or not applicable for this device.
7579 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
7582 * If the function that is being queried is a PF, then the HWRM shall
7583 * set this field to 0 and the HWRM client shall ignore this field.
7584 * If the function that is being queried is a VF, then the HWRM shall
7585 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
7586 * shall set this field to 0.
7588 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
7591 * If set to 1, then secure mode is enabled for this function or device.
7592 * If set to 0, then secure mode is disabled (or normal mode) for this
7593 * function or device.
7595 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
7598 * If set to 1, then this PF is enabled with a preboot driver that
7599 * requires access to the legacy L2 ring model and legacy 32b
7600 * doorbells. If set to 0, then this PF is not allowed to use
7601 * the legacy L2 rings. This feature is not allowed on VFs and
7602 * is only relevant for devices that require a context backing
7605 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
7608 * This value is current MAC address configured for this
7609 * function. A value of 00-00-00-00-00-00 indicates no
7610 * MAC address is currently configured.
7612 uint8_t mac_address[6];
7614 * This value is current PCI ID of this
7615 * function. If ARI is enabled, then it is
7616 * Bus Number (8b):Function Number(8b). Otherwise, it is
7617 * Bus Number (8b):Device Number (4b):Function Number(4b).
7618 * If multi-host mode is active, the 4 lsb will indicate
7619 * the PF index for this function.
7623 * The number of RSS/COS contexts currently
7624 * allocated to the function.
7626 uint16_t alloc_rsscos_ctx;
7628 * The number of completion rings currently allocated to
7629 * the function. This does not include the rings allocated
7630 * to any children functions if any.
7632 uint16_t alloc_cmpl_rings;
7634 * The number of transmit rings currently allocated to
7635 * the function. This does not include the rings allocated
7636 * to any children functions if any.
7638 uint16_t alloc_tx_rings;
7640 * The number of receive rings currently allocated to
7641 * the function. This does not include the rings allocated
7642 * to any children functions if any.
7644 uint16_t alloc_rx_rings;
7645 /* The allocated number of L2 contexts to the function. */
7646 uint16_t alloc_l2_ctx;
7647 /* The allocated number of vnics to the function. */
7648 uint16_t alloc_vnics;
7650 * The maximum transmission unit of the function.
7651 * If the reported mtu value is non-zero then it will used for the
7652 * rings allocated on this function. otherwise the default
7653 * value is used if ring MTU is not specified.
7657 * The maximum receive unit of the function.
7658 * For vnics allocated on this function, this default
7659 * value is used if vnic MRU is not specified.
7662 /* The statistics context assigned to a function. */
7663 uint16_t stat_ctx_id;
7665 * The HWRM shall return Unknown value for this field
7666 * when this command is used to query VF's configuration.
7668 uint8_t port_partition_type;
7669 /* Single physical function */
7670 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
7671 /* Multiple physical functions */
7672 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
7673 /* Network Partitioning 1.0 */
7674 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
7675 /* Network Partitioning 1.5 */
7676 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
7677 /* Network Partitioning 2.0 */
7678 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
7680 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
7682 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7683 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7685 * This field will indicate number of physical functions on this port_partition.
7686 * HWRM shall return unavail (i.e. value of 0) for this field
7687 * when this command is used to query VF's configuration or
7688 * from older firmware that doesn't support this field.
7690 uint8_t port_pf_cnt;
7691 /* number of PFs is not available */
7692 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7693 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7694 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7696 * The default VNIC ID assigned to a function that is
7699 uint16_t dflt_vnic_id;
7700 uint16_t max_mtu_configured;
7702 * Minimum BW allocated for this function.
7703 * The HWRM will translate this value into byte counter and
7704 * time interval used for the scheduler inside the device.
7705 * A value of 0 indicates the minimum bandwidth is not
7709 /* The bandwidth value. */
7710 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7712 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7713 /* The granularity of the value (bits or bytes). */
7714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7715 UINT32_C(0x10000000)
7716 /* Value is in bits. */
7717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7718 (UINT32_C(0x0) << 28)
7719 /* Value is in bytes. */
7720 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7721 (UINT32_C(0x1) << 28)
7722 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7723 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7724 /* bw_value_unit is 3 b */
7725 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7726 UINT32_C(0xe0000000)
7727 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7728 /* Value is in Mb or MB (base 10). */
7729 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7730 (UINT32_C(0x0) << 29)
7731 /* Value is in Kb or KB (base 10). */
7732 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7733 (UINT32_C(0x2) << 29)
7734 /* Value is in bits or bytes. */
7735 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7736 (UINT32_C(0x4) << 29)
7737 /* Value is in Gb or GB (base 10). */
7738 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7739 (UINT32_C(0x6) << 29)
7740 /* Value is in 1/100th of a percentage of total bandwidth. */
7741 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7742 (UINT32_C(0x1) << 29)
7744 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7745 (UINT32_C(0x7) << 29)
7746 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7747 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7749 * Maximum BW allocated for this function.
7750 * The HWRM will translate this value into byte counter and
7751 * time interval used for the scheduler inside the device.
7752 * A value of 0 indicates that the maximum bandwidth is not
7756 /* The bandwidth value. */
7757 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7759 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7760 /* The granularity of the value (bits or bytes). */
7761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7762 UINT32_C(0x10000000)
7763 /* Value is in bits. */
7764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7765 (UINT32_C(0x0) << 28)
7766 /* Value is in bytes. */
7767 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7768 (UINT32_C(0x1) << 28)
7769 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7770 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7771 /* bw_value_unit is 3 b */
7772 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7773 UINT32_C(0xe0000000)
7774 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7775 /* Value is in Mb or MB (base 10). */
7776 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7777 (UINT32_C(0x0) << 29)
7778 /* Value is in Kb or KB (base 10). */
7779 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7780 (UINT32_C(0x2) << 29)
7781 /* Value is in bits or bytes. */
7782 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7783 (UINT32_C(0x4) << 29)
7784 /* Value is in Gb or GB (base 10). */
7785 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7786 (UINT32_C(0x6) << 29)
7787 /* Value is in 1/100th of a percentage of total bandwidth. */
7788 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7789 (UINT32_C(0x1) << 29)
7791 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7792 (UINT32_C(0x7) << 29)
7793 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7794 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7796 * This value indicates the Edge virtual bridge mode for the
7797 * domain that this function belongs to.
7800 /* No Edge Virtual Bridging (EVB) */
7801 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7802 /* Virtual Ethernet Bridge (VEB) */
7803 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7804 /* Virtual Ethernet Port Aggregator (VEPA) */
7805 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7806 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7807 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7810 * This value indicates the PCIE device cache line size.
7811 * The cache line size allows the DMA writes to terminate and
7812 * start at the cache boundary.
7814 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7816 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7817 /* Cache Line Size 64 bytes */
7818 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7820 /* Cache Line Size 128 bytes */
7821 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7823 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7824 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7825 /* This value is the virtual link admin state setting. */
7826 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7828 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7829 /* Admin link state is in forced down mode. */
7830 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7831 (UINT32_C(0x0) << 2)
7832 /* Admin link state is in forced up mode. */
7833 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7834 (UINT32_C(0x1) << 2)
7835 /* Admin link state is in auto mode - follows the physical link state. */
7836 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7837 (UINT32_C(0x2) << 2)
7838 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7839 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7840 /* Reserved for future. */
7841 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7843 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7845 * The number of VFs that are allocated to the function.
7846 * This is valid only on the PF with SR-IOV enabled.
7847 * 0xFF... (All Fs) if this command is called on a PF with
7848 * SR-IOV disabled or on a VF.
7852 * The number of allocated multicast filters for this
7853 * function on the RX side.
7855 uint32_t alloc_mcast_filters;
7857 * The number of allocated HW ring groups for this
7860 uint32_t alloc_hw_ring_grps;
7862 * The number of strict priority transmit rings out of
7863 * currently allocated TX rings to the function
7866 uint16_t alloc_sp_tx_rings;
7868 * The number of statistics contexts
7869 * currently reserved for the function.
7871 uint16_t alloc_stat_ctx;
7873 * This field specifies how many NQs are reserved for the PF.
7874 * Remaining NQs that belong to the PF are available for VFs.
7875 * Once a PF has created VFs, it cannot change how many NQs are
7876 * reserved for itself (since the NQs must be contiguous in HW).
7878 uint16_t alloc_msix;
7880 * The number of registered VF’s associated with the PF. This field
7881 * should be ignored when the request received on the VF interface.
7882 * This field will be updated on the PF interface to initiate
7883 * the unregister request on PF in the HOT Reset Process.
7885 uint16_t registered_vfs;
7887 * The size of the doorbell BAR in KBytes reserved for L2 including
7888 * any area that is shared between L2 and RoCE. The L2 driver
7889 * should only map the L2 portion of the doorbell BAR. Any rounding
7890 * of the BAR size to the native CPU page size should be performed
7891 * by the driver. If the value is zero, no special partitioning
7892 * of the doorbell BAR between L2 and RoCE is required.
7894 uint16_t l2_doorbell_bar_size_kb;
7897 * For backward compatibility this field must be set to 1.
7898 * Older drivers might look for this field to be 1 before
7899 * processing the message.
7903 * This GRC address location is used by the Host driver interfaces to poll
7904 * the adapter ready state to re-initiate the registration process again
7905 * after receiving the RESET Notify event.
7907 uint32_t reset_addr_poll;
7908 uint8_t unused_2[3];
7910 * This field is used in Output records to indicate that the output
7911 * is completely written to RAM. This field should be read as '1'
7912 * to indicate that the output has been completely written.
7913 * When writing a command completion or response to an internal processor,
7914 * the order of writes has to be such that this field is written last.
7917 } __attribute__((packed));
7924 /* hwrm_func_cfg_input (size:704b/88B) */
7925 struct hwrm_func_cfg_input {
7926 /* The HWRM command request type. */
7929 * The completion ring to send the completion event on. This should
7930 * be the NQ ID returned from the `nq_alloc` HWRM command.
7934 * The sequence ID is used by the driver for tracking multiple
7935 * commands. This ID is treated as opaque data by the firmware and
7936 * the value is returned in the `hwrm_resp_hdr` upon completion.
7940 * The target ID of the command:
7941 * * 0x0-0xFFF8 - The function ID
7942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7943 * * 0xFFFD - Reserved for user-space HWRM interface
7948 * A physical address pointer pointing to a host buffer that the
7949 * command's response data will be written. This can be either a host
7950 * physical address (HPA) or a guest physical address (GPA) and must
7951 * point to a physically contiguous block of memory.
7955 * Function ID of the function that is being
7957 * If set to 0xFF... (All Fs), then the the configuration is
7958 * for the requesting function.
7962 * This field specifies how many NQs will be reserved for the PF.
7963 * Remaining NQs that belong to the PF become available for VFs.
7964 * Once a PF has created VFs, it cannot change how many NQs are
7965 * reserved for itself (since the NQs must be contiguous in HW).
7970 * When this bit is '1', the function is disabled with
7971 * source MAC address check.
7972 * This is an anti-spoofing check. If this flag is set,
7973 * then the function shall be configured to disallow
7974 * transmission of frames with the source MAC address that
7975 * is configured for this function.
7977 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
7980 * When this bit is '1', the function is enabled with
7981 * source MAC address check.
7982 * This is an anti-spoofing check. If this flag is set,
7983 * then the function shall be configured to allow
7984 * transmission of frames with the source MAC address that
7985 * is configured for this function.
7987 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
7990 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
7992 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7994 * Standard TX Ring mode is used for the allocation of TX ring
7995 * and underlying scheduling resources that allow bandwidth
7996 * reservation and limit settings on the queried function.
7997 * If set to 1, then standard TX ring mode is requested to be
7998 * enabled on the function being configured.
8000 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
8003 * Standard TX Ring mode is used for the allocation of TX ring
8004 * and underlying scheduling resources that allow bandwidth
8005 * reservation and limit settings on the queried function.
8006 * If set to 1, then the standard TX ring mode is requested to
8007 * be disabled on the function being configured. In this extended
8008 * TX ring resource mode, the minimum and maximum bandwidth settings
8009 * are not supported to allow the allocation of TX rings to
8010 * span multiple scheduler nodes.
8012 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
8015 * If this bit is set, virtual mac address configured
8016 * in this command will be persistent over warm boot.
8018 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
8021 * This bit only applies to the VF. If this bit is set, the statistic
8022 * context counters will not be cleared when the statistic context is freed
8023 * or a function reset is called on VF. This bit will be cleared when the PF
8024 * is unloaded or a function reset is called on the PF.
8026 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
8029 * This bit requests that the firmware test to see if all the assets
8030 * requested in this command (i.e. number of TX rings) are available.
8031 * The firmware will return an error if the requested assets are
8032 * not available. The firwmare will NOT reserve the assets if they
8035 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8038 * This bit requests that the firmware test to see if all the assets
8039 * requested in this command (i.e. number of RX rings) are available.
8040 * The firmware will return an error if the requested assets are
8041 * not available. The firwmare will NOT reserve the assets if they
8044 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8047 * This bit requests that the firmware test to see if all the assets
8048 * requested in this command (i.e. number of CMPL rings) are available.
8049 * The firmware will return an error if the requested assets are
8050 * not available. The firwmare will NOT reserve the assets if they
8053 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8056 * This bit requests that the firmware test to see if all the assets
8057 * requested in this command (i.e. number of RSS ctx) are available.
8058 * The firmware will return an error if the requested assets are
8059 * not available. The firwmare will NOT reserve the assets if they
8062 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8065 * This bit requests that the firmware test to see if all the assets
8066 * requested in this command (i.e. number of ring groups) are available.
8067 * The firmware will return an error if the requested assets are
8068 * not available. The firwmare will NOT reserve the assets if they
8071 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8074 * This bit requests that the firmware test to see if all the assets
8075 * requested in this command (i.e. number of stat ctx) are available.
8076 * The firmware will return an error if the requested assets are
8077 * not available. The firwmare will NOT reserve the assets if they
8080 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8083 * This bit requests that the firmware test to see if all the assets
8084 * requested in this command (i.e. number of VNICs) are available.
8085 * The firmware will return an error if the requested assets are
8086 * not available. The firwmare will NOT reserve the assets if they
8089 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8092 * This bit requests that the firmware test to see if all the assets
8093 * requested in this command (i.e. number of L2 ctx) are available.
8094 * The firmware will return an error if the requested assets are
8095 * not available. The firwmare will NOT reserve the assets if they
8098 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8101 * This configuration change can be initiated by a PF driver. This
8102 * configuration request shall be targeted to a VF. From local host
8103 * resident HWRM clients, only the parent PF driver shall be allowed
8104 * to initiate this change on one of its children VFs. If this bit is
8105 * set to 1, then the VF that is being configured is requested to be
8108 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
8111 * When this bit it set, even if PF reserved pool size is zero,
8112 * FW will allow driver to create TX rings in ring alloc,
8113 * by reserving TX ring, S3 node dynamically.
8115 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
8118 * This bit requests that the firmware test to see if all the assets
8119 * requested in this command (i.e. number of NQ rings) are available.
8120 * The firmware will return an error if the requested assets are
8121 * not available. The firwmare will NOT reserve the assets if they
8124 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
8127 * This configuration change can be initiated by a PF driver. This
8128 * configuration request shall be targeted to a VF. From local host
8129 * resident HWRM clients, only the parent PF driver shall be allowed
8130 * to initiate this change on one of its children VFs. If this bit is
8131 * set to 1, then the VF that is being configured is requested to be
8134 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
8137 * This bit is used by preboot drivers on a PF that require access
8138 * to the legacy L2 ring model and legacy 32b doorbells. This
8139 * feature is not allowed on VFs and is only relevant for devices
8140 * that require a context backing store.
8142 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8146 * This bit must be '1' for the mtu field to be
8149 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
8152 * This bit must be '1' for the mru field to be
8155 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
8158 * This bit must be '1' for the num_rsscos_ctxs field to be
8161 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8164 * This bit must be '1' for the num_cmpl_rings field to be
8167 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8170 * This bit must be '1' for the num_tx_rings field to be
8173 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8176 * This bit must be '1' for the num_rx_rings field to be
8179 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8182 * This bit must be '1' for the num_l2_ctxs field to be
8185 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8188 * This bit must be '1' for the num_vnics field to be
8191 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
8194 * This bit must be '1' for the num_stat_ctxs field to be
8197 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8200 * This bit must be '1' for the dflt_mac_addr field to be
8203 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8206 * This bit must be '1' for the dflt_vlan field to be
8209 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
8212 * This bit must be '1' for the dflt_ip_addr field to be
8215 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
8218 * This bit must be '1' for the min_bw field to be
8221 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
8224 * This bit must be '1' for the max_bw field to be
8227 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
8230 * This bit must be '1' for the async_event_cr field to be
8233 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8236 * This bit must be '1' for the vlan_antispoof_mode field to be
8239 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
8242 * This bit must be '1' for the allowed_vlan_pris field to be
8245 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
8248 * This bit must be '1' for the evb_mode field to be
8251 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
8254 * This bit must be '1' for the num_mcast_filters field to be
8257 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
8260 * This bit must be '1' for the num_hw_ring_grps field to be
8263 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8266 * This bit must be '1' for the cache_linesize field to be
8269 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
8272 * This bit must be '1' for the num_msix field to be
8275 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
8278 * This bit must be '1' for the link admin state field to be
8281 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
8284 * The maximum transmission unit of the function.
8285 * The HWRM should make sure that the mtu of
8286 * the function does not exceed the mtu of the physical
8287 * port that this function is associated with.
8289 * In addition to configuring mtu per function, it is
8290 * possible to configure mtu per transmit ring.
8291 * By default, the mtu of each transmit ring associated
8292 * with a function is equal to the mtu of the function.
8293 * The HWRM should make sure that the mtu of each transmit
8294 * ring that is assigned to a function has a valid mtu.
8298 * The maximum receive unit of the function.
8299 * The HWRM should make sure that the mru of
8300 * the function does not exceed the mru of the physical
8301 * port that this function is associated with.
8303 * In addition to configuring mru per function, it is
8304 * possible to configure mru per vnic.
8305 * By default, the mru of each vnic associated
8306 * with a function is equal to the mru of the function.
8307 * The HWRM should make sure that the mru of each vnic
8308 * that is assigned to a function has a valid mru.
8312 * The number of RSS/COS contexts requested for the
8315 uint16_t num_rsscos_ctxs;
8317 * The number of completion rings requested for the
8318 * function. This does not include the rings allocated
8319 * to any children functions if any.
8321 uint16_t num_cmpl_rings;
8323 * The number of transmit rings requested for the function.
8324 * This does not include the rings allocated to any
8325 * children functions if any.
8327 uint16_t num_tx_rings;
8329 * The number of receive rings requested for the function.
8330 * This does not include the rings allocated
8331 * to any children functions if any.
8333 uint16_t num_rx_rings;
8334 /* The requested number of L2 contexts for the function. */
8335 uint16_t num_l2_ctxs;
8336 /* The requested number of vnics for the function. */
8338 /* The requested number of statistic contexts for the function. */
8339 uint16_t num_stat_ctxs;
8341 * The number of HW ring groups that should
8342 * be reserved for this function.
8344 uint16_t num_hw_ring_grps;
8345 /* The default MAC address for the function being configured. */
8346 uint8_t dflt_mac_addr[6];
8348 * The default VLAN for the function being configured.
8349 * This field's format is same as 802.1Q Tag's
8350 * Tag Control Information (TCI) format that includes both
8351 * Priority Code Point (PCP) and VLAN Identifier (VID).
8355 * The default IP address for the function being configured.
8356 * This address is only used in enabling source property check.
8358 uint32_t dflt_ip_addr[4];
8360 * Minimum BW allocated for this function.
8361 * The HWRM will translate this value into byte counter and
8362 * time interval used for the scheduler inside the device.
8365 /* The bandwidth value. */
8366 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
8368 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
8369 /* The granularity of the value (bits or bytes). */
8370 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
8371 UINT32_C(0x10000000)
8372 /* Value is in bits. */
8373 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
8374 (UINT32_C(0x0) << 28)
8375 /* Value is in bytes. */
8376 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
8377 (UINT32_C(0x1) << 28)
8378 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
8379 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
8380 /* bw_value_unit is 3 b */
8381 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8382 UINT32_C(0xe0000000)
8383 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8384 /* Value is in Mb or MB (base 10). */
8385 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8386 (UINT32_C(0x0) << 29)
8387 /* Value is in Kb or KB (base 10). */
8388 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8389 (UINT32_C(0x2) << 29)
8390 /* Value is in bits or bytes. */
8391 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8392 (UINT32_C(0x4) << 29)
8393 /* Value is in Gb or GB (base 10). */
8394 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8395 (UINT32_C(0x6) << 29)
8396 /* Value is in 1/100th of a percentage of total bandwidth. */
8397 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8398 (UINT32_C(0x1) << 29)
8400 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8401 (UINT32_C(0x7) << 29)
8402 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8403 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8405 * Maximum BW allocated for this function.
8406 * The HWRM will translate this value into byte counter and
8407 * time interval used for the scheduler inside the device.
8410 /* The bandwidth value. */
8411 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
8413 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
8414 /* The granularity of the value (bits or bytes). */
8415 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
8416 UINT32_C(0x10000000)
8417 /* Value is in bits. */
8418 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
8419 (UINT32_C(0x0) << 28)
8420 /* Value is in bytes. */
8421 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
8422 (UINT32_C(0x1) << 28)
8423 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
8424 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
8425 /* bw_value_unit is 3 b */
8426 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8427 UINT32_C(0xe0000000)
8428 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8429 /* Value is in Mb or MB (base 10). */
8430 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8431 (UINT32_C(0x0) << 29)
8432 /* Value is in Kb or KB (base 10). */
8433 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8434 (UINT32_C(0x2) << 29)
8435 /* Value is in bits or bytes. */
8436 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8437 (UINT32_C(0x4) << 29)
8438 /* Value is in Gb or GB (base 10). */
8439 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8440 (UINT32_C(0x6) << 29)
8441 /* Value is in 1/100th of a percentage of total bandwidth. */
8442 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8443 (UINT32_C(0x1) << 29)
8445 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8446 (UINT32_C(0x7) << 29)
8447 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8448 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8450 * ID of the target completion ring for receiving asynchronous
8451 * event completions. If this field is not valid, then the
8452 * HWRM shall use the default completion ring of the function
8453 * that is being configured as the target completion ring for
8454 * providing any asynchronous event completions for that
8456 * If this field is valid, then the HWRM shall use the
8457 * completion ring identified by this ID as the target
8458 * completion ring for providing any asynchronous event
8459 * completions for the function that is being configured.
8461 uint16_t async_event_cr;
8462 /* VLAN Anti-spoofing mode. */
8463 uint8_t vlan_antispoof_mode;
8464 /* No VLAN anti-spoofing checks are enabled */
8465 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
8467 /* Validate VLAN against the configured VLAN(s) */
8468 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
8470 /* Insert VLAN if it does not exist, otherwise discard */
8471 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
8473 /* Insert VLAN if it does not exist, override VLAN if it exists */
8474 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
8476 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
8477 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
8479 * This bit field defines VLAN PRIs that are allowed on
8481 * If nth bit is set, then VLAN PRI n is allowed on this
8484 uint8_t allowed_vlan_pris;
8486 * The HWRM shall allow a PF driver to change EVB mode for the
8487 * partition it belongs to.
8488 * The HWRM shall not allow a VF driver to change the EVB mode.
8489 * The HWRM shall take into account the switching of EVB mode
8490 * from one to another and reconfigure hardware resources as
8492 * The switching from VEB to VEPA mode requires
8493 * the disabling of the loopback traffic. Additionally,
8494 * source knock outs are handled differently in VEB and VEPA
8498 /* No Edge Virtual Bridging (EVB) */
8499 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8500 /* Virtual Ethernet Bridge (VEB) */
8501 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
8502 /* Virtual Ethernet Port Aggregator (VEPA) */
8503 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
8504 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
8505 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
8508 * This value indicates the PCIE device cache line size.
8509 * The cache line size allows the DMA writes to terminate and
8510 * start at the cache boundary.
8512 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
8514 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8515 /* Cache Line Size 64 bytes */
8516 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8518 /* Cache Line Size 128 bytes */
8519 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8521 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
8522 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8523 /* This value is the virtual link admin state setting. */
8524 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8526 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8527 /* Admin state is forced down. */
8528 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8529 (UINT32_C(0x0) << 2)
8530 /* Admin state is forced up. */
8531 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8532 (UINT32_C(0x1) << 2)
8533 /* Admin state is in auto mode - is to follow the physical link state. */
8534 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8535 (UINT32_C(0x2) << 2)
8536 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8537 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8538 /* Reserved for future. */
8539 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
8541 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
8543 * The number of multicast filters that should
8544 * be reserved for this function on the RX side.
8546 uint16_t num_mcast_filters;
8547 } __attribute__((packed));
8549 /* hwrm_func_cfg_output (size:128b/16B) */
8550 struct hwrm_func_cfg_output {
8551 /* The specific error status for the command. */
8552 uint16_t error_code;
8553 /* The HWRM command request type. */
8555 /* The sequence ID from the original command. */
8557 /* The length of the response data in number of bytes. */
8559 uint8_t unused_0[7];
8561 * This field is used in Output records to indicate that the output
8562 * is completely written to RAM. This field should be read as '1'
8563 * to indicate that the output has been completely written.
8564 * When writing a command completion or response to an internal processor,
8565 * the order of writes has to be such that this field is written last.
8568 } __attribute__((packed));
8570 /********************
8571 * hwrm_func_qstats *
8572 ********************/
8575 /* hwrm_func_qstats_input (size:192b/24B) */
8576 struct hwrm_func_qstats_input {
8577 /* The HWRM command request type. */
8580 * The completion ring to send the completion event on. This should
8581 * be the NQ ID returned from the `nq_alloc` HWRM command.
8585 * The sequence ID is used by the driver for tracking multiple
8586 * commands. This ID is treated as opaque data by the firmware and
8587 * the value is returned in the `hwrm_resp_hdr` upon completion.
8591 * The target ID of the command:
8592 * * 0x0-0xFFF8 - The function ID
8593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8594 * * 0xFFFD - Reserved for user-space HWRM interface
8599 * A physical address pointer pointing to a host buffer that the
8600 * command's response data will be written. This can be either a host
8601 * physical address (HPA) or a guest physical address (GPA) and must
8602 * point to a physically contiguous block of memory.
8606 * Function ID of the function that is being queried.
8607 * 0xFF... (All Fs) if the query is for the requesting
8611 uint8_t unused_0[6];
8612 } __attribute__((packed));
8614 /* hwrm_func_qstats_output (size:1408b/176B) */
8615 struct hwrm_func_qstats_output {
8616 /* The specific error status for the command. */
8617 uint16_t error_code;
8618 /* The HWRM command request type. */
8620 /* The sequence ID from the original command. */
8622 /* The length of the response data in number of bytes. */
8624 /* Number of transmitted unicast packets on the function. */
8625 uint64_t tx_ucast_pkts;
8626 /* Number of transmitted multicast packets on the function. */
8627 uint64_t tx_mcast_pkts;
8628 /* Number of transmitted broadcast packets on the function. */
8629 uint64_t tx_bcast_pkts;
8631 * Number of transmitted packets that were discarded due to
8632 * internal NIC resource problems. For transmit, this
8633 * can only happen if TMP is configured to allow dropping
8634 * in HOL blocking conditions, which is not a normal
8637 uint64_t tx_discard_pkts;
8639 * Number of dropped packets on transmit path on the function.
8640 * These are packets that have been marked for drop by
8641 * the TE CFA block or are packets that exceeded the
8642 * transmit MTU limit for the function.
8644 uint64_t tx_drop_pkts;
8645 /* Number of transmitted bytes for unicast traffic on the function. */
8646 uint64_t tx_ucast_bytes;
8647 /* Number of transmitted bytes for multicast traffic on the function. */
8648 uint64_t tx_mcast_bytes;
8649 /* Number of transmitted bytes for broadcast traffic on the function. */
8650 uint64_t tx_bcast_bytes;
8651 /* Number of received unicast packets on the function. */
8652 uint64_t rx_ucast_pkts;
8653 /* Number of received multicast packets on the function. */
8654 uint64_t rx_mcast_pkts;
8655 /* Number of received broadcast packets on the function. */
8656 uint64_t rx_bcast_pkts;
8658 * Number of received packets that were discarded on the function
8659 * due to resource limitations. This can happen for 3 reasons.
8660 * # The BD used for the packet has a bad format.
8661 * # There were no BDs available in the ring for the packet.
8662 * # There were no BDs available on-chip for the packet.
8664 uint64_t rx_discard_pkts;
8666 * Number of dropped packets on received path on the function.
8667 * These are packets that have been marked for drop by the
8670 uint64_t rx_drop_pkts;
8671 /* Number of received bytes for unicast traffic on the function. */
8672 uint64_t rx_ucast_bytes;
8673 /* Number of received bytes for multicast traffic on the function. */
8674 uint64_t rx_mcast_bytes;
8675 /* Number of received bytes for broadcast traffic on the function. */
8676 uint64_t rx_bcast_bytes;
8677 /* Number of aggregated unicast packets on the function. */
8678 uint64_t rx_agg_pkts;
8679 /* Number of aggregated unicast bytes on the function. */
8680 uint64_t rx_agg_bytes;
8681 /* Number of aggregation events on the function. */
8682 uint64_t rx_agg_events;
8683 /* Number of aborted aggregations on the function. */
8684 uint64_t rx_agg_aborts;
8685 uint8_t unused_0[7];
8687 * This field is used in Output records to indicate that the output
8688 * is completely written to RAM. This field should be read as '1'
8689 * to indicate that the output has been completely written.
8690 * When writing a command completion or response to an internal processor,
8691 * the order of writes has to be such that this field is written last.
8694 } __attribute__((packed));
8696 /***********************
8697 * hwrm_func_clr_stats *
8698 ***********************/
8701 /* hwrm_func_clr_stats_input (size:192b/24B) */
8702 struct hwrm_func_clr_stats_input {
8703 /* The HWRM command request type. */
8706 * The completion ring to send the completion event on. This should
8707 * be the NQ ID returned from the `nq_alloc` HWRM command.
8711 * The sequence ID is used by the driver for tracking multiple
8712 * commands. This ID is treated as opaque data by the firmware and
8713 * the value is returned in the `hwrm_resp_hdr` upon completion.
8717 * The target ID of the command:
8718 * * 0x0-0xFFF8 - The function ID
8719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8720 * * 0xFFFD - Reserved for user-space HWRM interface
8725 * A physical address pointer pointing to a host buffer that the
8726 * command's response data will be written. This can be either a host
8727 * physical address (HPA) or a guest physical address (GPA) and must
8728 * point to a physically contiguous block of memory.
8732 * Function ID of the function.
8733 * 0xFF... (All Fs) if the query is for the requesting
8737 uint8_t unused_0[6];
8738 } __attribute__((packed));
8740 /* hwrm_func_clr_stats_output (size:128b/16B) */
8741 struct hwrm_func_clr_stats_output {
8742 /* The specific error status for the command. */
8743 uint16_t error_code;
8744 /* The HWRM command request type. */
8746 /* The sequence ID from the original command. */
8748 /* The length of the response data in number of bytes. */
8750 uint8_t unused_0[7];
8752 * This field is used in Output records to indicate that the output
8753 * is completely written to RAM. This field should be read as '1'
8754 * to indicate that the output has been completely written.
8755 * When writing a command completion or response to an internal processor,
8756 * the order of writes has to be such that this field is written last.
8759 } __attribute__((packed));
8761 /**************************
8762 * hwrm_func_vf_resc_free *
8763 **************************/
8766 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8767 struct hwrm_func_vf_resc_free_input {
8768 /* The HWRM command request type. */
8771 * The completion ring to send the completion event on. This should
8772 * be the NQ ID returned from the `nq_alloc` HWRM command.
8776 * The sequence ID is used by the driver for tracking multiple
8777 * commands. This ID is treated as opaque data by the firmware and
8778 * the value is returned in the `hwrm_resp_hdr` upon completion.
8782 * The target ID of the command:
8783 * * 0x0-0xFFF8 - The function ID
8784 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8785 * * 0xFFFD - Reserved for user-space HWRM interface
8790 * A physical address pointer pointing to a host buffer that the
8791 * command's response data will be written. This can be either a host
8792 * physical address (HPA) or a guest physical address (GPA) and must
8793 * point to a physically contiguous block of memory.
8797 * This value is used to identify a Virtual Function (VF).
8798 * The scope of VF ID is local within a PF.
8801 uint8_t unused_0[6];
8802 } __attribute__((packed));
8804 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8805 struct hwrm_func_vf_resc_free_output {
8806 /* The specific error status for the command. */
8807 uint16_t error_code;
8808 /* The HWRM command request type. */
8810 /* The sequence ID from the original command. */
8812 /* The length of the response data in number of bytes. */
8814 uint8_t unused_0[7];
8816 * This field is used in Output records to indicate that the output
8817 * is completely written to RAM. This field should be read as '1'
8818 * to indicate that the output has been completely written.
8819 * When writing a command completion or response to an internal processor,
8820 * the order of writes has to be such that this field is written last.
8823 } __attribute__((packed));
8825 /**********************
8826 * hwrm_func_drv_rgtr *
8827 **********************/
8830 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8831 struct hwrm_func_drv_rgtr_input {
8832 /* The HWRM command request type. */
8835 * The completion ring to send the completion event on. This should
8836 * be the NQ ID returned from the `nq_alloc` HWRM command.
8840 * The sequence ID is used by the driver for tracking multiple
8841 * commands. This ID is treated as opaque data by the firmware and
8842 * the value is returned in the `hwrm_resp_hdr` upon completion.
8846 * The target ID of the command:
8847 * * 0x0-0xFFF8 - The function ID
8848 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8849 * * 0xFFFD - Reserved for user-space HWRM interface
8854 * A physical address pointer pointing to a host buffer that the
8855 * command's response data will be written. This can be either a host
8856 * physical address (HPA) or a guest physical address (GPA) and must
8857 * point to a physically contiguous block of memory.
8862 * When this bit is '1', the function driver is requesting
8863 * all requests from its children VF drivers to be
8864 * forwarded to itself.
8865 * This flag can only be set by the PF driver.
8866 * If a VF driver sets this flag, it should be ignored
8869 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8872 * When this bit is '1', the function is requesting none of
8873 * the requests from its children VF drivers to be
8874 * forwarded to itself.
8875 * This flag can only be set by the PF driver.
8876 * If a VF driver sets this flag, it should be ignored
8879 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
8882 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
8883 * fields shall be ignored and ver_maj, ver_min, ver_upd
8884 * and ver_patch shall be used for the driver version information.
8885 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
8886 * fields shall be used for the driver version information and
8887 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
8889 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
8892 * When this bit is '1', the function is indicating support of
8893 * 64bit flow handle. The firmware that only supports 64bit flow
8894 * handle should check this bit before allowing processing of
8895 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
8896 * with 64bit flow handle support can only be compatible with drivers
8897 * that support 64bit flow handle. The legacy drivers that don't support
8898 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
8899 * running with new firmware that only supports 64bit flow handle. The new
8900 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
8901 * status to the legacy driver when encounters these commands.
8903 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
8906 * When this bit is '1', the function is indicating support of
8907 * Hot Reset. The driver interface will destroy the resources,
8908 * unregister the function and register again up on receiving
8909 * the RESET_NOTIFY Async notification from the core firmware.
8910 * The core firmware will this use flag and trigger the Hot Reset
8911 * process only if all the registered driver instances are capable
8914 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
8917 * When this bit is 1, the function is indicating the support of the
8918 * error recovery capability. Error recovery support will be used by
8919 * firmware only if all the driver instances support error recovery
8920 * process. By setting this bit, driver is indicating support for
8921 * corresponding async event completion message. These will be
8922 * delivered to the driver even if they did not register for it.
8923 * If supported, after receiving reset notify async event with fatal
8924 * flag set in event data1, then all the drivers have to tear down
8925 * their resources without sending any HWRM commands to FW.
8927 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
8930 * When this bit is 1, the function is indicating the support of the
8931 * Master capability. The Firmware will use this capability to select
8932 * the Master function. The master function will be used to initiate
8933 * designated functionality like error recovery etc. If none of the
8934 * registered PFs or trusted VFs indicate this support, then
8935 * firmware will select the 1st registered PF as Master capable
8938 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
8942 * This bit must be '1' for the os_type field to be
8945 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
8948 * This bit must be '1' for the ver field to be
8951 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
8954 * This bit must be '1' for the timestamp field to be
8957 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
8960 * This bit must be '1' for the vf_req_fwd field to be
8963 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
8966 * This bit must be '1' for the async_event_fwd field to be
8969 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
8971 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8974 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8975 /* Other OS not listed below. */
8976 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
8978 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8980 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8982 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8984 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
8986 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8987 /* VMware ESXi OS. */
8988 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
8989 /* Microsoft Windows 8 64-bit OS. */
8990 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8991 /* Microsoft Windows Server 2012 R2 OS. */
8992 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8994 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8995 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
8996 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
8997 /* This is the 8bit major version of the driver. */
8999 /* This is the 8bit minor version of the driver. */
9001 /* This is the 8bit update version of the driver. */
9003 uint8_t unused_0[3];
9005 * This is a 32-bit timestamp provided by the driver for
9007 * The timestamp is in multiples of 1ms.
9010 uint8_t unused_1[4];
9012 * This is a 256-bit bit mask provided by the PF driver for
9013 * letting the HWRM know what commands issued by the VF driver
9014 * to the HWRM should be forwarded to the PF driver.
9015 * Nth bit refers to the Nth req_type.
9017 * Setting Nth bit to 1 indicates that requests from the
9018 * VF driver with req_type equal to N shall be forwarded to
9019 * the parent PF driver.
9021 * This field is not valid for the VF driver.
9023 uint32_t vf_req_fwd[8];
9025 * This is a 256-bit bit mask provided by the function driver
9026 * (PF or VF driver) to indicate the list of asynchronous event
9027 * completions to be forwarded.
9029 * Nth bit refers to the Nth event_id.
9031 * Setting Nth bit to 1 by the function driver shall result in
9032 * the HWRM forwarding asynchronous event completion with
9033 * event_id equal to N.
9035 * If all bits are set to 0 (value of 0), then the HWRM shall
9036 * not forward any asynchronous event completion to this
9039 uint32_t async_event_fwd[8];
9040 /* This is the 16bit major version of the driver. */
9042 /* This is the 16bit minor version of the driver. */
9044 /* This is the 16bit update version of the driver. */
9046 /* This is the 16bit patch version of the driver. */
9048 } __attribute__((packed));
9050 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
9051 struct hwrm_func_drv_rgtr_output {
9052 /* The specific error status for the command. */
9053 uint16_t error_code;
9054 /* The HWRM command request type. */
9056 /* The sequence ID from the original command. */
9058 /* The length of the response data in number of bytes. */
9062 * When this bit is '1', it indicates that the
9063 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
9065 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
9067 uint8_t unused_0[3];
9069 * This field is used in Output records to indicate that the output
9070 * is completely written to RAM. This field should be read as '1'
9071 * to indicate that the output has been completely written.
9072 * When writing a command completion or response to an internal processor,
9073 * the order of writes has to be such that this field is written last.
9076 } __attribute__((packed));
9078 /************************
9079 * hwrm_func_drv_unrgtr *
9080 ************************/
9083 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
9084 struct hwrm_func_drv_unrgtr_input {
9085 /* The HWRM command request type. */
9088 * The completion ring to send the completion event on. This should
9089 * be the NQ ID returned from the `nq_alloc` HWRM command.
9093 * The sequence ID is used by the driver for tracking multiple
9094 * commands. This ID is treated as opaque data by the firmware and
9095 * the value is returned in the `hwrm_resp_hdr` upon completion.
9099 * The target ID of the command:
9100 * * 0x0-0xFFF8 - The function ID
9101 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9102 * * 0xFFFD - Reserved for user-space HWRM interface
9107 * A physical address pointer pointing to a host buffer that the
9108 * command's response data will be written. This can be either a host
9109 * physical address (HPA) or a guest physical address (GPA) and must
9110 * point to a physically contiguous block of memory.
9115 * When this bit is '1', the function driver is notifying
9116 * the HWRM to prepare for the shutdown.
9118 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
9120 uint8_t unused_0[4];
9121 } __attribute__((packed));
9123 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
9124 struct hwrm_func_drv_unrgtr_output {
9125 /* The specific error status for the command. */
9126 uint16_t error_code;
9127 /* The HWRM command request type. */
9129 /* The sequence ID from the original command. */
9131 /* The length of the response data in number of bytes. */
9133 uint8_t unused_0[7];
9135 * This field is used in Output records to indicate that the output
9136 * is completely written to RAM. This field should be read as '1'
9137 * to indicate that the output has been completely written.
9138 * When writing a command completion or response to an internal processor,
9139 * the order of writes has to be such that this field is written last.
9142 } __attribute__((packed));
9144 /**********************
9145 * hwrm_func_buf_rgtr *
9146 **********************/
9149 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
9150 struct hwrm_func_buf_rgtr_input {
9151 /* The HWRM command request type. */
9154 * The completion ring to send the completion event on. This should
9155 * be the NQ ID returned from the `nq_alloc` HWRM command.
9159 * The sequence ID is used by the driver for tracking multiple
9160 * commands. This ID is treated as opaque data by the firmware and
9161 * the value is returned in the `hwrm_resp_hdr` upon completion.
9165 * The target ID of the command:
9166 * * 0x0-0xFFF8 - The function ID
9167 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9168 * * 0xFFFD - Reserved for user-space HWRM interface
9173 * A physical address pointer pointing to a host buffer that the
9174 * command's response data will be written. This can be either a host
9175 * physical address (HPA) or a guest physical address (GPA) and must
9176 * point to a physically contiguous block of memory.
9181 * This bit must be '1' for the vf_id field to be
9184 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9186 * This bit must be '1' for the err_buf_addr field to be
9189 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
9191 * This value is used to identify a Virtual Function (VF).
9192 * The scope of VF ID is local within a PF.
9196 * This field represents the number of pages used for request
9199 uint16_t req_buf_num_pages;
9201 * This field represents the page size used for request
9204 uint16_t req_buf_page_size;
9206 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
9208 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
9210 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
9212 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
9214 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
9216 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
9218 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
9219 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
9220 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
9221 /* The length of the request buffer per VF in bytes. */
9222 uint16_t req_buf_len;
9223 /* The length of the response buffer in bytes. */
9224 uint16_t resp_buf_len;
9225 uint8_t unused_0[2];
9226 /* This field represents the page address of page #0. */
9227 uint64_t req_buf_page_addr0;
9228 /* This field represents the page address of page #1. */
9229 uint64_t req_buf_page_addr1;
9230 /* This field represents the page address of page #2. */
9231 uint64_t req_buf_page_addr2;
9232 /* This field represents the page address of page #3. */
9233 uint64_t req_buf_page_addr3;
9234 /* This field represents the page address of page #4. */
9235 uint64_t req_buf_page_addr4;
9236 /* This field represents the page address of page #5. */
9237 uint64_t req_buf_page_addr5;
9238 /* This field represents the page address of page #6. */
9239 uint64_t req_buf_page_addr6;
9240 /* This field represents the page address of page #7. */
9241 uint64_t req_buf_page_addr7;
9242 /* This field represents the page address of page #8. */
9243 uint64_t req_buf_page_addr8;
9244 /* This field represents the page address of page #9. */
9245 uint64_t req_buf_page_addr9;
9247 * This field is used to receive the error reporting from
9248 * the chipset. Only applicable for PFs.
9250 uint64_t error_buf_addr;
9252 * This field is used to receive the response forwarded by the
9255 uint64_t resp_buf_addr;
9256 } __attribute__((packed));
9258 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
9259 struct hwrm_func_buf_rgtr_output {
9260 /* The specific error status for the command. */
9261 uint16_t error_code;
9262 /* The HWRM command request type. */
9264 /* The sequence ID from the original command. */
9266 /* The length of the response data in number of bytes. */
9268 uint8_t unused_0[7];
9270 * This field is used in Output records to indicate that the output
9271 * is completely written to RAM. This field should be read as '1'
9272 * to indicate that the output has been completely written.
9273 * When writing a command completion or response to an internal processor,
9274 * the order of writes has to be such that this field is written last.
9277 } __attribute__((packed));
9279 /************************
9280 * hwrm_func_buf_unrgtr *
9281 ************************/
9284 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
9285 struct hwrm_func_buf_unrgtr_input {
9286 /* The HWRM command request type. */
9289 * The completion ring to send the completion event on. This should
9290 * be the NQ ID returned from the `nq_alloc` HWRM command.
9294 * The sequence ID is used by the driver for tracking multiple
9295 * commands. This ID is treated as opaque data by the firmware and
9296 * the value is returned in the `hwrm_resp_hdr` upon completion.
9300 * The target ID of the command:
9301 * * 0x0-0xFFF8 - The function ID
9302 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9303 * * 0xFFFD - Reserved for user-space HWRM interface
9308 * A physical address pointer pointing to a host buffer that the
9309 * command's response data will be written. This can be either a host
9310 * physical address (HPA) or a guest physical address (GPA) and must
9311 * point to a physically contiguous block of memory.
9316 * This bit must be '1' for the vf_id field to be
9319 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9321 * This value is used to identify a Virtual Function (VF).
9322 * The scope of VF ID is local within a PF.
9325 uint8_t unused_0[2];
9326 } __attribute__((packed));
9328 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
9329 struct hwrm_func_buf_unrgtr_output {
9330 /* The specific error status for the command. */
9331 uint16_t error_code;
9332 /* The HWRM command request type. */
9334 /* The sequence ID from the original command. */
9336 /* The length of the response data in number of bytes. */
9338 uint8_t unused_0[7];
9340 * This field is used in Output records to indicate that the output
9341 * is completely written to RAM. This field should be read as '1'
9342 * to indicate that the output has been completely written.
9343 * When writing a command completion or response to an internal processor,
9344 * the order of writes has to be such that this field is written last.
9347 } __attribute__((packed));
9349 /**********************
9350 * hwrm_func_drv_qver *
9351 **********************/
9354 /* hwrm_func_drv_qver_input (size:192b/24B) */
9355 struct hwrm_func_drv_qver_input {
9356 /* The HWRM command request type. */
9359 * The completion ring to send the completion event on. This should
9360 * be the NQ ID returned from the `nq_alloc` HWRM command.
9364 * The sequence ID is used by the driver for tracking multiple
9365 * commands. This ID is treated as opaque data by the firmware and
9366 * the value is returned in the `hwrm_resp_hdr` upon completion.
9370 * The target ID of the command:
9371 * * 0x0-0xFFF8 - The function ID
9372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9373 * * 0xFFFD - Reserved for user-space HWRM interface
9378 * A physical address pointer pointing to a host buffer that the
9379 * command's response data will be written. This can be either a host
9380 * physical address (HPA) or a guest physical address (GPA) and must
9381 * point to a physically contiguous block of memory.
9384 /* Reserved for future use. */
9387 * Function ID of the function that is being queried.
9388 * 0xFF... (All Fs) if the query is for the requesting
9392 uint8_t unused_0[2];
9393 } __attribute__((packed));
9395 /* hwrm_func_drv_qver_output (size:256b/32B) */
9396 struct hwrm_func_drv_qver_output {
9397 /* The specific error status for the command. */
9398 uint16_t error_code;
9399 /* The HWRM command request type. */
9401 /* The sequence ID from the original command. */
9403 /* The length of the response data in number of bytes. */
9405 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9408 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9409 /* Other OS not listed below. */
9410 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
9412 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9414 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9416 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9418 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
9420 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9421 /* VMware ESXi OS. */
9422 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
9423 /* Microsoft Windows 8 64-bit OS. */
9424 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9425 /* Microsoft Windows Server 2012 R2 OS. */
9426 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9428 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9429 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
9430 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
9431 /* This is the 8bit major version of the driver. */
9433 /* This is the 8bit minor version of the driver. */
9435 /* This is the 8bit update version of the driver. */
9437 uint8_t unused_0[3];
9438 /* This is the 16bit major version of the driver. */
9440 /* This is the 16bit minor version of the driver. */
9442 /* This is the 16bit update version of the driver. */
9444 /* This is the 16bit patch version of the driver. */
9446 uint8_t unused_1[7];
9448 * This field is used in Output records to indicate that the output
9449 * is completely written to RAM. This field should be read as '1'
9450 * to indicate that the output has been completely written.
9451 * When writing a command completion or response to an internal processor,
9452 * the order of writes has to be such that this field is written last.
9455 } __attribute__((packed));
9457 /****************************
9458 * hwrm_func_resource_qcaps *
9459 ****************************/
9462 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
9463 struct hwrm_func_resource_qcaps_input {
9464 /* The HWRM command request type. */
9467 * The completion ring to send the completion event on. This should
9468 * be the NQ ID returned from the `nq_alloc` HWRM command.
9472 * The sequence ID is used by the driver for tracking multiple
9473 * commands. This ID is treated as opaque data by the firmware and
9474 * the value is returned in the `hwrm_resp_hdr` upon completion.
9478 * The target ID of the command:
9479 * * 0x0-0xFFF8 - The function ID
9480 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9481 * * 0xFFFD - Reserved for user-space HWRM interface
9486 * A physical address pointer pointing to a host buffer that the
9487 * command's response data will be written. This can be either a host
9488 * physical address (HPA) or a guest physical address (GPA) and must
9489 * point to a physically contiguous block of memory.
9493 * Function ID of the function that is being queried.
9494 * 0xFF... (All Fs) if the query is for the requesting
9498 uint8_t unused_0[6];
9499 } __attribute__((packed));
9501 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
9502 struct hwrm_func_resource_qcaps_output {
9503 /* The specific error status for the command. */
9504 uint16_t error_code;
9505 /* The HWRM command request type. */
9507 /* The sequence ID from the original command. */
9509 /* The length of the response data in number of bytes. */
9511 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
9513 /* Maximum guaranteed number of MSI-X vectors supported by function */
9515 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
9516 uint16_t vf_reservation_strategy;
9517 /* The PF driver should evenly divide its remaining resources among all VFs. */
9518 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
9520 /* The PF driver should only reserve minimal resources for each VF. */
9521 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
9524 * The PF driver should not reserve any resources for each VF until the
9525 * the VF interface is brought up.
9527 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
9529 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
9530 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
9531 /* Minimum guaranteed number of RSS/COS contexts */
9532 uint16_t min_rsscos_ctx;
9533 /* Maximum non-guaranteed number of RSS/COS contexts */
9534 uint16_t max_rsscos_ctx;
9535 /* Minimum guaranteed number of completion rings */
9536 uint16_t min_cmpl_rings;
9537 /* Maximum non-guaranteed number of completion rings */
9538 uint16_t max_cmpl_rings;
9539 /* Minimum guaranteed number of transmit rings */
9540 uint16_t min_tx_rings;
9541 /* Maximum non-guaranteed number of transmit rings */
9542 uint16_t max_tx_rings;
9543 /* Minimum guaranteed number of receive rings */
9544 uint16_t min_rx_rings;
9545 /* Maximum non-guaranteed number of receive rings */
9546 uint16_t max_rx_rings;
9547 /* Minimum guaranteed number of L2 contexts */
9548 uint16_t min_l2_ctxs;
9549 /* Maximum non-guaranteed number of L2 contexts */
9550 uint16_t max_l2_ctxs;
9551 /* Minimum guaranteed number of VNICs */
9553 /* Maximum non-guaranteed number of VNICs */
9555 /* Minimum guaranteed number of statistic contexts */
9556 uint16_t min_stat_ctx;
9557 /* Maximum non-guaranteed number of statistic contexts */
9558 uint16_t max_stat_ctx;
9559 /* Minimum guaranteed number of ring groups */
9560 uint16_t min_hw_ring_grps;
9561 /* Maximum non-guaranteed number of ring groups */
9562 uint16_t max_hw_ring_grps;
9564 * Maximum number of inputs into the transmit scheduler for this function.
9565 * The number of TX rings assigned to the function cannot exceed this value.
9567 uint16_t max_tx_scheduler_inputs;
9570 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
9571 * feature to reserve all minimum resources when minimum >= 1, otherwise
9574 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
9576 uint8_t unused_0[5];
9578 * This field is used in Output records to indicate that the output
9579 * is completely written to RAM. This field should be read as '1'
9580 * to indicate that the output has been completely written.
9581 * When writing a command completion or response to an internal processor,
9582 * the order of writes has to be such that this field is written last.
9585 } __attribute__((packed));
9587 /*********************************
9588 * hwrm_func_backing_store_qcaps *
9589 *********************************/
9592 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
9593 struct hwrm_func_backing_store_qcaps_input {
9594 /* The HWRM command request type. */
9597 * The completion ring to send the completion event on. This should
9598 * be the NQ ID returned from the `nq_alloc` HWRM command.
9602 * The sequence ID is used by the driver for tracking multiple
9603 * commands. This ID is treated as opaque data by the firmware and
9604 * the value is returned in the `hwrm_resp_hdr` upon completion.
9608 * The target ID of the command:
9609 * * 0x0-0xFFF8 - The function ID
9610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9611 * * 0xFFFD - Reserved for user-space HWRM interface
9616 * A physical address pointer pointing to a host buffer that the
9617 * command's response data will be written. This can be either a host
9618 * physical address (HPA) or a guest physical address (GPA) and must
9619 * point to a physically contiguous block of memory.
9622 } __attribute__((packed));
9624 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
9625 struct hwrm_func_backing_store_qcaps_output {
9626 /* The specific error status for the command. */
9627 uint16_t error_code;
9628 /* The HWRM command request type. */
9630 /* The sequence ID from the original command. */
9632 /* The length of the response data in number of bytes. */
9634 /* Maximum number of QP context entries supported for this function. */
9635 uint32_t qp_max_entries;
9637 * Minimum number of QP context entries that are needed to be reserved
9638 * for QP1 for the PF and its VFs. PF drivers must allocate at least
9639 * this many QP context entries, even if RoCE will not be used.
9641 uint16_t qp_min_qp1_entries;
9642 /* Maximum number of QP context entries that can be used for L2. */
9643 uint16_t qp_max_l2_entries;
9644 /* Number of bytes that must be allocated for each context entry. */
9645 uint16_t qp_entry_size;
9646 /* Maximum number of SRQ context entries that can be used for L2. */
9647 uint16_t srq_max_l2_entries;
9648 /* Maximum number of SRQ context entries supported for this function. */
9649 uint32_t srq_max_entries;
9650 /* Number of bytes that must be allocated for each context entry. */
9651 uint16_t srq_entry_size;
9652 /* Maximum number of CQ context entries that can be used for L2. */
9653 uint16_t cq_max_l2_entries;
9654 /* Maximum number of CQ context entries supported for this function. */
9655 uint32_t cq_max_entries;
9656 /* Number of bytes that must be allocated for each context entry. */
9657 uint16_t cq_entry_size;
9658 /* Maximum number of VNIC context entries supported for this function. */
9659 uint16_t vnic_max_vnic_entries;
9660 /* Maximum number of Ring table context entries supported for this function. */
9661 uint16_t vnic_max_ring_table_entries;
9662 /* Number of bytes that must be allocated for each context entry. */
9663 uint16_t vnic_entry_size;
9664 /* Maximum number of statistic context entries supported for this function. */
9665 uint32_t stat_max_entries;
9666 /* Number of bytes that must be allocated for each context entry. */
9667 uint16_t stat_entry_size;
9668 /* Number of bytes that must be allocated for each context entry. */
9669 uint16_t tqm_entry_size;
9670 /* Minimum number of TQM context entries required per ring. */
9671 uint32_t tqm_min_entries_per_ring;
9673 * Maximum number of TQM context entries supported per ring. This is
9674 * actually a recommended TQM queue size based on worst case usage of
9677 * TQM fastpath rings should be sized large enough to accommodate the
9678 * maximum number of QPs (either L2 or RoCE, or both if shared)
9679 * that can be enqueued to the TQM ring.
9681 * TQM slowpath rings should be sized as follows:
9683 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9686 * num_vnics is the number of VNICs allocated in the VNIC backing store
9687 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9688 * num_roce_qps is the number of RoCE QPs in the QP backing store
9689 * tqm_min_size is tqm_min_entries_per_ring reported by
9690 * HWRM_FUNC_BACKING_STORE_QCAPS
9692 * Note that TQM ring sizes cannot be extended while the system is
9693 * operational. If a PF driver needs to extend a TQM ring, it needs
9694 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9695 * the backing store.
9697 uint32_t tqm_max_entries_per_ring;
9699 * Maximum number of MR plus AV context entries supported for this
9702 uint32_t mrav_max_entries;
9703 /* Number of bytes that must be allocated for each context entry. */
9704 uint16_t mrav_entry_size;
9705 /* Number of bytes that must be allocated for each context entry. */
9706 uint16_t tim_entry_size;
9707 /* Maximum number of Timer context entries supported for this function. */
9708 uint32_t tim_max_entries;
9710 * When this field is zero, the 32b `mrav_num_entries` field in the
9711 * `backing_store_cfg` and `backing_store_qcfg` commands represents
9712 * the total number of MR plus AV entries allowed in the MR/AV backing
9715 * When this field is non-zero, the 32b `mrav_num_entries` field in
9716 * the `backing_store_cfg` and `backing_store_qcfg` commands is
9717 * logically divided into two 16b fields. Bits `[31:16]` represents
9718 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
9719 * Both of these values are represented in a unit granularity
9720 * specified by this field. For example, if this field is 16 and
9721 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
9722 * is 8192 and the number of AV entries is 4096.
9724 uint16_t mrav_num_entries_units;
9726 * The number of entries specified for any TQM ring must be a
9727 * multiple of this value to prevent any resource allocation
9730 uint8_t tqm_entries_multiple;
9732 * This field is used in Output records to indicate that the output
9733 * is completely written to RAM. This field should be read as '1'
9734 * to indicate that the output has been completely written.
9735 * When writing a command completion or response to an internal processor,
9736 * the order of writes has to be such that this field is written last.
9739 } __attribute__((packed));
9741 /*******************************
9742 * hwrm_func_backing_store_cfg *
9743 *******************************/
9746 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9747 struct hwrm_func_backing_store_cfg_input {
9748 /* The HWRM command request type. */
9751 * The completion ring to send the completion event on. This should
9752 * be the NQ ID returned from the `nq_alloc` HWRM command.
9756 * The sequence ID is used by the driver for tracking multiple
9757 * commands. This ID is treated as opaque data by the firmware and
9758 * the value is returned in the `hwrm_resp_hdr` upon completion.
9762 * The target ID of the command:
9763 * * 0x0-0xFFF8 - The function ID
9764 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9765 * * 0xFFFD - Reserved for user-space HWRM interface
9770 * A physical address pointer pointing to a host buffer that the
9771 * command's response data will be written. This can be either a host
9772 * physical address (HPA) or a guest physical address (GPA) and must
9773 * point to a physically contiguous block of memory.
9778 * When set, the firmware only uses on-chip resources and does not
9779 * expect any backing store to be provided by the host driver. This
9780 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9786 * When set, the 32b `mrav_num_entries` field is logically divided
9787 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
9789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
9793 * This bit must be '1' for the qp fields to be
9796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9799 * This bit must be '1' for the srq fields to be
9802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9805 * This bit must be '1' for the cq fields to be
9808 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9811 * This bit must be '1' for the vnic fields to be
9814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9817 * This bit must be '1' for the stat fields to be
9820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9823 * This bit must be '1' for the tqm_sp fields to be
9826 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9829 * This bit must be '1' for the tqm_ring0 fields to be
9832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9835 * This bit must be '1' for the tqm_ring1 fields to be
9838 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9841 * This bit must be '1' for the tqm_ring2 fields to be
9844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9847 * This bit must be '1' for the tqm_ring3 fields to be
9850 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9853 * This bit must be '1' for the tqm_ring4 fields to be
9856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9859 * This bit must be '1' for the tqm_ring5 fields to be
9862 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
9865 * This bit must be '1' for the tqm_ring6 fields to be
9868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
9871 * This bit must be '1' for the tqm_ring7 fields to be
9874 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
9877 * This bit must be '1' for the mrav fields to be
9880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
9883 * This bit must be '1' for the tim fields to be
9886 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
9888 /* QPC page size and level. */
9889 uint8_t qpc_pg_size_qpc_lvl;
9890 /* QPC PBL indirect levels. */
9891 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
9893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
9894 /* PBL pointer is physical start address. */
9895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
9897 /* PBL pointer points to PTE table. */
9898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
9900 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9901 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
9903 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
9904 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
9905 /* QPC page size. */
9906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
9908 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
9910 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
9911 (UINT32_C(0x0) << 4)
9913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
9914 (UINT32_C(0x1) << 4)
9916 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
9917 (UINT32_C(0x2) << 4)
9919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
9920 (UINT32_C(0x3) << 4)
9922 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
9923 (UINT32_C(0x4) << 4)
9925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
9926 (UINT32_C(0x5) << 4)
9927 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
9928 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
9929 /* SRQ page size and level. */
9930 uint8_t srq_pg_size_srq_lvl;
9931 /* SRQ PBL indirect levels. */
9932 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
9934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
9935 /* PBL pointer is physical start address. */
9936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
9938 /* PBL pointer points to PTE table. */
9939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
9941 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9942 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
9944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
9945 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
9946 /* SRQ page size. */
9947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
9949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
9951 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
9952 (UINT32_C(0x0) << 4)
9954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
9955 (UINT32_C(0x1) << 4)
9957 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
9958 (UINT32_C(0x2) << 4)
9960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
9961 (UINT32_C(0x3) << 4)
9963 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
9964 (UINT32_C(0x4) << 4)
9966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
9967 (UINT32_C(0x5) << 4)
9968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
9969 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
9970 /* CQ page size and level. */
9971 uint8_t cq_pg_size_cq_lvl;
9972 /* CQ PBL indirect levels. */
9973 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
9975 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
9976 /* PBL pointer is physical start address. */
9977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
9979 /* PBL pointer points to PTE table. */
9980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
9982 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9983 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
9985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
9986 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
9988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
9990 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
9992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
9993 (UINT32_C(0x0) << 4)
9995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
9996 (UINT32_C(0x1) << 4)
9998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
9999 (UINT32_C(0x2) << 4)
10001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
10002 (UINT32_C(0x3) << 4)
10004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
10005 (UINT32_C(0x4) << 4)
10007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
10008 (UINT32_C(0x5) << 4)
10009 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
10010 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
10011 /* VNIC page size and level. */
10012 uint8_t vnic_pg_size_vnic_lvl;
10013 /* VNIC PBL indirect levels. */
10014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
10016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
10017 /* PBL pointer is physical start address. */
10018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
10020 /* PBL pointer points to PTE table. */
10021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
10023 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10024 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
10026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
10027 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
10028 /* VNIC page size. */
10029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
10031 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
10033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
10034 (UINT32_C(0x0) << 4)
10036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
10037 (UINT32_C(0x1) << 4)
10039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
10040 (UINT32_C(0x2) << 4)
10042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
10043 (UINT32_C(0x3) << 4)
10045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
10046 (UINT32_C(0x4) << 4)
10048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
10049 (UINT32_C(0x5) << 4)
10050 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
10051 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
10052 /* Stat page size and level. */
10053 uint8_t stat_pg_size_stat_lvl;
10054 /* Stat PBL indirect levels. */
10055 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
10057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
10058 /* PBL pointer is physical start address. */
10059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
10061 /* PBL pointer points to PTE table. */
10062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
10064 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
10067 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
10068 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
10069 /* Stat page size. */
10070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
10072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
10074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
10075 (UINT32_C(0x0) << 4)
10077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
10078 (UINT32_C(0x1) << 4)
10080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
10081 (UINT32_C(0x2) << 4)
10083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
10084 (UINT32_C(0x3) << 4)
10086 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
10087 (UINT32_C(0x4) << 4)
10089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
10090 (UINT32_C(0x5) << 4)
10091 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
10092 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
10093 /* TQM slow path page size and level. */
10094 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10095 /* TQM slow path PBL indirect levels. */
10096 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
10098 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
10099 /* PBL pointer is physical start address. */
10100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
10102 /* PBL pointer points to PTE table. */
10103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
10105 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
10108 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
10109 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
10110 /* TQM slow path page size. */
10111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
10113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
10115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
10116 (UINT32_C(0x0) << 4)
10118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
10119 (UINT32_C(0x1) << 4)
10121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
10122 (UINT32_C(0x2) << 4)
10124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
10125 (UINT32_C(0x3) << 4)
10127 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
10128 (UINT32_C(0x4) << 4)
10130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
10131 (UINT32_C(0x5) << 4)
10132 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
10133 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
10134 /* TQM ring 0 page size and level. */
10135 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10136 /* TQM ring 0 PBL indirect levels. */
10137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
10139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
10140 /* PBL pointer is physical start address. */
10141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
10143 /* PBL pointer points to PTE table. */
10144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
10146 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
10149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
10150 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
10151 /* TQM ring 0 page size. */
10152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
10154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
10156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
10157 (UINT32_C(0x0) << 4)
10159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
10160 (UINT32_C(0x1) << 4)
10162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
10163 (UINT32_C(0x2) << 4)
10165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
10166 (UINT32_C(0x3) << 4)
10168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
10169 (UINT32_C(0x4) << 4)
10171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
10172 (UINT32_C(0x5) << 4)
10173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
10174 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
10175 /* TQM ring 1 page size and level. */
10176 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10177 /* TQM ring 1 PBL indirect levels. */
10178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
10180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
10181 /* PBL pointer is physical start address. */
10182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
10184 /* PBL pointer points to PTE table. */
10185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
10187 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
10190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
10191 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
10192 /* TQM ring 1 page size. */
10193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
10195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
10197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
10198 (UINT32_C(0x0) << 4)
10200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
10201 (UINT32_C(0x1) << 4)
10203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
10204 (UINT32_C(0x2) << 4)
10206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
10207 (UINT32_C(0x3) << 4)
10209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
10210 (UINT32_C(0x4) << 4)
10212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
10213 (UINT32_C(0x5) << 4)
10214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
10215 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
10216 /* TQM ring 2 page size and level. */
10217 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10218 /* TQM ring 2 PBL indirect levels. */
10219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
10221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
10222 /* PBL pointer is physical start address. */
10223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
10225 /* PBL pointer points to PTE table. */
10226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
10228 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
10231 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
10232 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
10233 /* TQM ring 2 page size. */
10234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
10236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
10238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
10239 (UINT32_C(0x0) << 4)
10241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
10242 (UINT32_C(0x1) << 4)
10244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
10245 (UINT32_C(0x2) << 4)
10247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
10248 (UINT32_C(0x3) << 4)
10250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
10251 (UINT32_C(0x4) << 4)
10253 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
10254 (UINT32_C(0x5) << 4)
10255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
10256 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
10257 /* TQM ring 3 page size and level. */
10258 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10259 /* TQM ring 3 PBL indirect levels. */
10260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
10262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
10263 /* PBL pointer is physical start address. */
10264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
10266 /* PBL pointer points to PTE table. */
10267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
10269 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
10272 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
10273 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
10274 /* TQM ring 3 page size. */
10275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
10277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
10279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
10280 (UINT32_C(0x0) << 4)
10282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
10283 (UINT32_C(0x1) << 4)
10285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
10286 (UINT32_C(0x2) << 4)
10288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
10289 (UINT32_C(0x3) << 4)
10291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
10292 (UINT32_C(0x4) << 4)
10294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
10295 (UINT32_C(0x5) << 4)
10296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
10297 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
10298 /* TQM ring 4 page size and level. */
10299 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10300 /* TQM ring 4 PBL indirect levels. */
10301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
10303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
10304 /* PBL pointer is physical start address. */
10305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
10307 /* PBL pointer points to PTE table. */
10308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
10310 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
10313 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
10314 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
10315 /* TQM ring 4 page size. */
10316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
10318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
10320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
10321 (UINT32_C(0x0) << 4)
10323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
10324 (UINT32_C(0x1) << 4)
10326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
10327 (UINT32_C(0x2) << 4)
10329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
10330 (UINT32_C(0x3) << 4)
10332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
10333 (UINT32_C(0x4) << 4)
10335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
10336 (UINT32_C(0x5) << 4)
10337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
10338 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
10339 /* TQM ring 5 page size and level. */
10340 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10341 /* TQM ring 5 PBL indirect levels. */
10342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
10344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
10345 /* PBL pointer is physical start address. */
10346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
10348 /* PBL pointer points to PTE table. */
10349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
10351 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
10354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
10355 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
10356 /* TQM ring 5 page size. */
10357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
10359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
10361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
10362 (UINT32_C(0x0) << 4)
10364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
10365 (UINT32_C(0x1) << 4)
10367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
10368 (UINT32_C(0x2) << 4)
10370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
10371 (UINT32_C(0x3) << 4)
10373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
10374 (UINT32_C(0x4) << 4)
10376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
10377 (UINT32_C(0x5) << 4)
10378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
10379 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
10380 /* TQM ring 6 page size and level. */
10381 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10382 /* TQM ring 6 PBL indirect levels. */
10383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
10385 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
10386 /* PBL pointer is physical start address. */
10387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
10389 /* PBL pointer points to PTE table. */
10390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
10392 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
10395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
10396 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
10397 /* TQM ring 6 page size. */
10398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
10400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
10402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
10403 (UINT32_C(0x0) << 4)
10405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
10406 (UINT32_C(0x1) << 4)
10408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
10409 (UINT32_C(0x2) << 4)
10411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
10412 (UINT32_C(0x3) << 4)
10414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
10415 (UINT32_C(0x4) << 4)
10417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
10418 (UINT32_C(0x5) << 4)
10419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
10420 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
10421 /* TQM ring 7 page size and level. */
10422 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10423 /* TQM ring 7 PBL indirect levels. */
10424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
10426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
10427 /* PBL pointer is physical start address. */
10428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
10430 /* PBL pointer points to PTE table. */
10431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
10433 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
10436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
10437 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
10438 /* TQM ring 7 page size. */
10439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
10441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
10443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
10444 (UINT32_C(0x0) << 4)
10446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
10447 (UINT32_C(0x1) << 4)
10449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
10450 (UINT32_C(0x2) << 4)
10452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
10453 (UINT32_C(0x3) << 4)
10455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
10456 (UINT32_C(0x4) << 4)
10458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
10459 (UINT32_C(0x5) << 4)
10460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
10461 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
10462 /* MR/AV page size and level. */
10463 uint8_t mrav_pg_size_mrav_lvl;
10464 /* MR/AV PBL indirect levels. */
10465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
10467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
10468 /* PBL pointer is physical start address. */
10469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
10471 /* PBL pointer points to PTE table. */
10472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
10474 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
10477 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
10478 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
10479 /* MR/AV page size. */
10480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
10482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
10484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
10485 (UINT32_C(0x0) << 4)
10487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
10488 (UINT32_C(0x1) << 4)
10490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
10491 (UINT32_C(0x2) << 4)
10493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
10494 (UINT32_C(0x3) << 4)
10496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
10497 (UINT32_C(0x4) << 4)
10499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
10500 (UINT32_C(0x5) << 4)
10501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
10502 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
10503 /* Timer page size and level. */
10504 uint8_t tim_pg_size_tim_lvl;
10505 /* Timer PBL indirect levels. */
10506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
10508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
10509 /* PBL pointer is physical start address. */
10510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
10512 /* PBL pointer points to PTE table. */
10513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
10515 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
10518 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
10519 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
10520 /* Timer page size. */
10521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
10523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
10525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
10526 (UINT32_C(0x0) << 4)
10528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
10529 (UINT32_C(0x1) << 4)
10531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
10532 (UINT32_C(0x2) << 4)
10534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
10535 (UINT32_C(0x3) << 4)
10537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
10538 (UINT32_C(0x4) << 4)
10540 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
10541 (UINT32_C(0x5) << 4)
10542 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
10543 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
10544 /* QP page directory. */
10545 uint64_t qpc_page_dir;
10546 /* SRQ page directory. */
10547 uint64_t srq_page_dir;
10548 /* CQ page directory. */
10549 uint64_t cq_page_dir;
10550 /* VNIC page directory. */
10551 uint64_t vnic_page_dir;
10552 /* Stat page directory. */
10553 uint64_t stat_page_dir;
10554 /* TQM slowpath page directory. */
10555 uint64_t tqm_sp_page_dir;
10556 /* TQM ring 0 page directory. */
10557 uint64_t tqm_ring0_page_dir;
10558 /* TQM ring 1 page directory. */
10559 uint64_t tqm_ring1_page_dir;
10560 /* TQM ring 2 page directory. */
10561 uint64_t tqm_ring2_page_dir;
10562 /* TQM ring 3 page directory. */
10563 uint64_t tqm_ring3_page_dir;
10564 /* TQM ring 4 page directory. */
10565 uint64_t tqm_ring4_page_dir;
10566 /* TQM ring 5 page directory. */
10567 uint64_t tqm_ring5_page_dir;
10568 /* TQM ring 6 page directory. */
10569 uint64_t tqm_ring6_page_dir;
10570 /* TQM ring 7 page directory. */
10571 uint64_t tqm_ring7_page_dir;
10572 /* MR/AV page directory. */
10573 uint64_t mrav_page_dir;
10574 /* Timer page directory. */
10575 uint64_t tim_page_dir;
10576 /* Number of QPs. */
10577 uint32_t qp_num_entries;
10578 /* Number of SRQs. */
10579 uint32_t srq_num_entries;
10580 /* Number of CQs. */
10581 uint32_t cq_num_entries;
10582 /* Number of Stats. */
10583 uint32_t stat_num_entries;
10585 * Number of TQM slowpath entries.
10587 * TQM slowpath rings should be sized as follows:
10589 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
10592 * num_vnics is the number of VNICs allocated in the VNIC backing store
10593 * num_l2_tx_rings is the number of L2 rings in the QP backing store
10594 * num_roce_qps is the number of RoCE QPs in the QP backing store
10595 * tqm_min_size is tqm_min_entries_per_ring reported by
10596 * HWRM_FUNC_BACKING_STORE_QCAPS
10598 * Note that TQM ring sizes cannot be extended while the system is
10599 * operational. If a PF driver needs to extend a TQM ring, it needs
10600 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10601 * the backing store.
10603 uint32_t tqm_sp_num_entries;
10605 * Number of TQM ring 0 entries.
10607 * TQM fastpath rings should be sized large enough to accommodate the
10608 * maximum number of QPs (either L2 or RoCE, or both if shared)
10609 * that can be enqueued to the TQM ring.
10611 * Note that TQM ring sizes cannot be extended while the system is
10612 * operational. If a PF driver needs to extend a TQM ring, it needs
10613 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10614 * the backing store.
10616 uint32_t tqm_ring0_num_entries;
10618 * Number of TQM ring 1 entries.
10620 * TQM fastpath rings should be sized large enough to accommodate the
10621 * maximum number of QPs (either L2 or RoCE, or both if shared)
10622 * that can be enqueued to the TQM ring.
10624 * Note that TQM ring sizes cannot be extended while the system is
10625 * operational. If a PF driver needs to extend a TQM ring, it needs
10626 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10627 * the backing store.
10629 uint32_t tqm_ring1_num_entries;
10631 * Number of TQM ring 2 entries.
10633 * TQM fastpath rings should be sized large enough to accommodate the
10634 * maximum number of QPs (either L2 or RoCE, or both if shared)
10635 * that can be enqueued to the TQM ring.
10637 * Note that TQM ring sizes cannot be extended while the system is
10638 * operational. If a PF driver needs to extend a TQM ring, it needs
10639 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10640 * the backing store.
10642 uint32_t tqm_ring2_num_entries;
10644 * Number of TQM ring 3 entries.
10646 * TQM fastpath rings should be sized large enough to accommodate the
10647 * maximum number of QPs (either L2 or RoCE, or both if shared)
10648 * that can be enqueued to the TQM ring.
10650 * Note that TQM ring sizes cannot be extended while the system is
10651 * operational. If a PF driver needs to extend a TQM ring, it needs
10652 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10653 * the backing store.
10655 uint32_t tqm_ring3_num_entries;
10657 * Number of TQM ring 4 entries.
10659 * TQM fastpath rings should be sized large enough to accommodate the
10660 * maximum number of QPs (either L2 or RoCE, or both if shared)
10661 * that can be enqueued to the TQM ring.
10663 * Note that TQM ring sizes cannot be extended while the system is
10664 * operational. If a PF driver needs to extend a TQM ring, it needs
10665 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10666 * the backing store.
10668 uint32_t tqm_ring4_num_entries;
10670 * Number of TQM ring 5 entries.
10672 * TQM fastpath rings should be sized large enough to accommodate the
10673 * maximum number of QPs (either L2 or RoCE, or both if shared)
10674 * that can be enqueued to the TQM ring.
10676 * Note that TQM ring sizes cannot be extended while the system is
10677 * operational. If a PF driver needs to extend a TQM ring, it needs
10678 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10679 * the backing store.
10681 uint32_t tqm_ring5_num_entries;
10683 * Number of TQM ring 6 entries.
10685 * TQM fastpath rings should be sized large enough to accommodate the
10686 * maximum number of QPs (either L2 or RoCE, or both if shared)
10687 * that can be enqueued to the TQM ring.
10689 * Note that TQM ring sizes cannot be extended while the system is
10690 * operational. If a PF driver needs to extend a TQM ring, it needs
10691 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10692 * the backing store.
10694 uint32_t tqm_ring6_num_entries;
10696 * Number of TQM ring 7 entries.
10698 * TQM fastpath rings should be sized large enough to accommodate the
10699 * maximum number of QPs (either L2 or RoCE, or both if shared)
10700 * that can be enqueued to the TQM ring.
10702 * Note that TQM ring sizes cannot be extended while the system is
10703 * operational. If a PF driver needs to extend a TQM ring, it needs
10704 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10705 * the backing store.
10707 uint32_t tqm_ring7_num_entries;
10709 * If the MR/AV split reservation flag is not set, then this field
10710 * represents the total number of MR plus AV entries. For versions
10711 * of firmware that support the split reservation, when it is not
10712 * specified half of the entries will be reserved for MRs and the
10713 * other half for AVs.
10715 * If the MR/AV split reservation flag is set, then this
10716 * field is logically divided into two 16b fields. Bits `[31:16]`
10717 * represents the `mr_num_entries` and bits `[15:0]` represents
10718 * `av_num_entries`. The granularity of these values is defined by
10719 * the `mrav_num_entries_unit` field returned by the
10720 * `backing_store_qcaps` command.
10722 uint32_t mrav_num_entries;
10723 /* Number of Timer entries. */
10724 uint32_t tim_num_entries;
10725 /* Number of entries to reserve for QP1 */
10726 uint16_t qp_num_qp1_entries;
10727 /* Number of entries to reserve for L2 */
10728 uint16_t qp_num_l2_entries;
10729 /* Number of bytes that have been allocated for each context entry. */
10730 uint16_t qp_entry_size;
10731 /* Number of entries to reserve for L2 */
10732 uint16_t srq_num_l2_entries;
10733 /* Number of bytes that have been allocated for each context entry. */
10734 uint16_t srq_entry_size;
10735 /* Number of entries to reserve for L2 */
10736 uint16_t cq_num_l2_entries;
10737 /* Number of bytes that have been allocated for each context entry. */
10738 uint16_t cq_entry_size;
10739 /* Number of entries to reserve for VNIC entries */
10740 uint16_t vnic_num_vnic_entries;
10741 /* Number of entries to reserve for Ring table entries */
10742 uint16_t vnic_num_ring_table_entries;
10743 /* Number of bytes that have been allocated for each context entry. */
10744 uint16_t vnic_entry_size;
10745 /* Number of bytes that have been allocated for each context entry. */
10746 uint16_t stat_entry_size;
10747 /* Number of bytes that have been allocated for each context entry. */
10748 uint16_t tqm_entry_size;
10749 /* Number of bytes that have been allocated for each context entry. */
10750 uint16_t mrav_entry_size;
10751 /* Number of bytes that have been allocated for each context entry. */
10752 uint16_t tim_entry_size;
10753 } __attribute__((packed));
10755 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
10756 struct hwrm_func_backing_store_cfg_output {
10757 /* The specific error status for the command. */
10758 uint16_t error_code;
10759 /* The HWRM command request type. */
10761 /* The sequence ID from the original command. */
10763 /* The length of the response data in number of bytes. */
10765 uint8_t unused_0[7];
10767 * This field is used in Output records to indicate that the output
10768 * is completely written to RAM. This field should be read as '1'
10769 * to indicate that the output has been completely written.
10770 * When writing a command completion or response to an internal processor,
10771 * the order of writes has to be such that this field is written last.
10774 } __attribute__((packed));
10776 /********************************
10777 * hwrm_func_backing_store_qcfg *
10778 ********************************/
10781 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10782 struct hwrm_func_backing_store_qcfg_input {
10783 /* The HWRM command request type. */
10786 * The completion ring to send the completion event on. This should
10787 * be the NQ ID returned from the `nq_alloc` HWRM command.
10789 uint16_t cmpl_ring;
10791 * The sequence ID is used by the driver for tracking multiple
10792 * commands. This ID is treated as opaque data by the firmware and
10793 * the value is returned in the `hwrm_resp_hdr` upon completion.
10797 * The target ID of the command:
10798 * * 0x0-0xFFF8 - The function ID
10799 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10800 * * 0xFFFD - Reserved for user-space HWRM interface
10803 uint16_t target_id;
10805 * A physical address pointer pointing to a host buffer that the
10806 * command's response data will be written. This can be either a host
10807 * physical address (HPA) or a guest physical address (GPA) and must
10808 * point to a physically contiguous block of memory.
10810 uint64_t resp_addr;
10811 } __attribute__((packed));
10813 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10814 struct hwrm_func_backing_store_qcfg_output {
10815 /* The specific error status for the command. */
10816 uint16_t error_code;
10817 /* The HWRM command request type. */
10819 /* The sequence ID from the original command. */
10821 /* The length of the response data in number of bytes. */
10825 * When set, the firmware only uses on-chip resources and does not
10826 * expect any backing store to be provided by the host driver. This
10827 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10833 * When set, the 32b `mrav_num_entries` field is logically divided
10834 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10836 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10838 uint8_t unused_0[4];
10840 * This bit must be '1' for the qp fields to be
10843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10846 * This bit must be '1' for the srq fields to be
10849 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10852 * This bit must be '1' for the cq fields to be
10855 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10858 * This bit must be '1' for the vnic fields to be
10861 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
10864 * This bit must be '1' for the stat fields to be
10867 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
10870 * This bit must be '1' for the tqm_sp fields to be
10873 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
10876 * This bit must be '1' for the tqm_ring0 fields to be
10879 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
10882 * This bit must be '1' for the tqm_ring1 fields to be
10885 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
10888 * This bit must be '1' for the tqm_ring2 fields to be
10891 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
10894 * This bit must be '1' for the tqm_ring3 fields to be
10897 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
10900 * This bit must be '1' for the tqm_ring4 fields to be
10903 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
10906 * This bit must be '1' for the tqm_ring5 fields to be
10909 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
10912 * This bit must be '1' for the tqm_ring6 fields to be
10915 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
10918 * This bit must be '1' for the tqm_ring7 fields to be
10921 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
10924 * This bit must be '1' for the mrav fields to be
10927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
10930 * This bit must be '1' for the tim fields to be
10933 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
10935 /* QPC page size and level. */
10936 uint8_t qpc_pg_size_qpc_lvl;
10937 /* QPC PBL indirect levels. */
10938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
10940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
10941 /* PBL pointer is physical start address. */
10942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
10944 /* PBL pointer points to PTE table. */
10945 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
10947 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
10950 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
10951 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
10952 /* QPC page size. */
10953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
10955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
10957 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
10958 (UINT32_C(0x0) << 4)
10960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
10961 (UINT32_C(0x1) << 4)
10963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
10964 (UINT32_C(0x2) << 4)
10966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
10967 (UINT32_C(0x3) << 4)
10969 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
10970 (UINT32_C(0x4) << 4)
10972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
10973 (UINT32_C(0x5) << 4)
10974 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
10975 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
10976 /* SRQ page size and level. */
10977 uint8_t srq_pg_size_srq_lvl;
10978 /* SRQ PBL indirect levels. */
10979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
10981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
10982 /* PBL pointer is physical start address. */
10983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
10985 /* PBL pointer points to PTE table. */
10986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
10988 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
10991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
10992 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
10993 /* SRQ page size. */
10994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
10996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
10998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
10999 (UINT32_C(0x0) << 4)
11001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
11002 (UINT32_C(0x1) << 4)
11004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
11005 (UINT32_C(0x2) << 4)
11007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
11008 (UINT32_C(0x3) << 4)
11010 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
11011 (UINT32_C(0x4) << 4)
11013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
11014 (UINT32_C(0x5) << 4)
11015 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
11016 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
11017 /* CQ page size and level. */
11018 uint8_t cq_pg_size_cq_lvl;
11019 /* CQ PBL indirect levels. */
11020 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
11022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
11023 /* PBL pointer is physical start address. */
11024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
11026 /* PBL pointer points to PTE table. */
11027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
11029 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
11032 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
11033 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
11034 /* CQ page size. */
11035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
11037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
11039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
11040 (UINT32_C(0x0) << 4)
11042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
11043 (UINT32_C(0x1) << 4)
11045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
11046 (UINT32_C(0x2) << 4)
11048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
11049 (UINT32_C(0x3) << 4)
11051 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
11052 (UINT32_C(0x4) << 4)
11054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
11055 (UINT32_C(0x5) << 4)
11056 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
11057 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
11058 /* VNIC page size and level. */
11059 uint8_t vnic_pg_size_vnic_lvl;
11060 /* VNIC PBL indirect levels. */
11061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
11063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
11064 /* PBL pointer is physical start address. */
11065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
11067 /* PBL pointer points to PTE table. */
11068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
11070 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
11073 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
11074 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
11075 /* VNIC page size. */
11076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
11078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
11080 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
11081 (UINT32_C(0x0) << 4)
11083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
11084 (UINT32_C(0x1) << 4)
11086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
11087 (UINT32_C(0x2) << 4)
11089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
11090 (UINT32_C(0x3) << 4)
11092 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
11093 (UINT32_C(0x4) << 4)
11095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
11096 (UINT32_C(0x5) << 4)
11097 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
11098 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
11099 /* Stat page size and level. */
11100 uint8_t stat_pg_size_stat_lvl;
11101 /* Stat PBL indirect levels. */
11102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
11104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
11105 /* PBL pointer is physical start address. */
11106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
11108 /* PBL pointer points to PTE table. */
11109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
11111 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
11114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
11115 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
11116 /* Stat page size. */
11117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
11119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
11121 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
11122 (UINT32_C(0x0) << 4)
11124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
11125 (UINT32_C(0x1) << 4)
11127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
11128 (UINT32_C(0x2) << 4)
11130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
11131 (UINT32_C(0x3) << 4)
11133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
11134 (UINT32_C(0x4) << 4)
11136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
11137 (UINT32_C(0x5) << 4)
11138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
11139 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
11140 /* TQM slow path page size and level. */
11141 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
11142 /* TQM slow path PBL indirect levels. */
11143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
11145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
11146 /* PBL pointer is physical start address. */
11147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
11149 /* PBL pointer points to PTE table. */
11150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
11152 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
11155 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
11156 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
11157 /* TQM slow path page size. */
11158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
11160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
11162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
11163 (UINT32_C(0x0) << 4)
11165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
11166 (UINT32_C(0x1) << 4)
11168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
11169 (UINT32_C(0x2) << 4)
11171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
11172 (UINT32_C(0x3) << 4)
11174 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
11175 (UINT32_C(0x4) << 4)
11177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
11178 (UINT32_C(0x5) << 4)
11179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
11180 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
11181 /* TQM ring 0 page size and level. */
11182 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
11183 /* TQM ring 0 PBL indirect levels. */
11184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
11186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
11187 /* PBL pointer is physical start address. */
11188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
11190 /* PBL pointer points to PTE table. */
11191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
11193 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
11196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
11197 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
11198 /* TQM ring 0 page size. */
11199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
11201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
11203 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
11204 (UINT32_C(0x0) << 4)
11206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
11207 (UINT32_C(0x1) << 4)
11209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
11210 (UINT32_C(0x2) << 4)
11212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
11213 (UINT32_C(0x3) << 4)
11215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
11216 (UINT32_C(0x4) << 4)
11218 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
11219 (UINT32_C(0x5) << 4)
11220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
11221 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
11222 /* TQM ring 1 page size and level. */
11223 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
11224 /* TQM ring 1 PBL indirect levels. */
11225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
11227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
11228 /* PBL pointer is physical start address. */
11229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
11231 /* PBL pointer points to PTE table. */
11232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
11234 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
11237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
11238 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
11239 /* TQM ring 1 page size. */
11240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
11242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
11244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
11245 (UINT32_C(0x0) << 4)
11247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
11248 (UINT32_C(0x1) << 4)
11250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
11251 (UINT32_C(0x2) << 4)
11253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
11254 (UINT32_C(0x3) << 4)
11256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
11257 (UINT32_C(0x4) << 4)
11259 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
11260 (UINT32_C(0x5) << 4)
11261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
11262 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
11263 /* TQM ring 2 page size and level. */
11264 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
11265 /* TQM ring 2 PBL indirect levels. */
11266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
11268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
11269 /* PBL pointer is physical start address. */
11270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
11272 /* PBL pointer points to PTE table. */
11273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
11275 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
11278 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
11279 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
11280 /* TQM ring 2 page size. */
11281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
11283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
11285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
11286 (UINT32_C(0x0) << 4)
11288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
11289 (UINT32_C(0x1) << 4)
11291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
11292 (UINT32_C(0x2) << 4)
11294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
11295 (UINT32_C(0x3) << 4)
11297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
11298 (UINT32_C(0x4) << 4)
11300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
11301 (UINT32_C(0x5) << 4)
11302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
11303 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
11304 /* TQM ring 3 page size and level. */
11305 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
11306 /* TQM ring 3 PBL indirect levels. */
11307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
11309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
11310 /* PBL pointer is physical start address. */
11311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
11313 /* PBL pointer points to PTE table. */
11314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
11316 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
11319 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
11320 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
11321 /* TQM ring 3 page size. */
11322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
11324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
11326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
11327 (UINT32_C(0x0) << 4)
11329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
11330 (UINT32_C(0x1) << 4)
11332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
11333 (UINT32_C(0x2) << 4)
11335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
11336 (UINT32_C(0x3) << 4)
11338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
11339 (UINT32_C(0x4) << 4)
11341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
11342 (UINT32_C(0x5) << 4)
11343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
11344 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
11345 /* TQM ring 4 page size and level. */
11346 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
11347 /* TQM ring 4 PBL indirect levels. */
11348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
11350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
11351 /* PBL pointer is physical start address. */
11352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
11354 /* PBL pointer points to PTE table. */
11355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
11357 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
11360 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
11361 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
11362 /* TQM ring 4 page size. */
11363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
11365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
11367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
11368 (UINT32_C(0x0) << 4)
11370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
11371 (UINT32_C(0x1) << 4)
11373 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
11374 (UINT32_C(0x2) << 4)
11376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
11377 (UINT32_C(0x3) << 4)
11379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
11380 (UINT32_C(0x4) << 4)
11382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
11383 (UINT32_C(0x5) << 4)
11384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
11385 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
11386 /* TQM ring 5 page size and level. */
11387 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
11388 /* TQM ring 5 PBL indirect levels. */
11389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
11391 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
11392 /* PBL pointer is physical start address. */
11393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
11395 /* PBL pointer points to PTE table. */
11396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
11398 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
11401 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
11402 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
11403 /* TQM ring 5 page size. */
11404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
11406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
11408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
11409 (UINT32_C(0x0) << 4)
11411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
11412 (UINT32_C(0x1) << 4)
11414 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
11415 (UINT32_C(0x2) << 4)
11417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
11418 (UINT32_C(0x3) << 4)
11420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
11421 (UINT32_C(0x4) << 4)
11423 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
11424 (UINT32_C(0x5) << 4)
11425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
11426 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
11427 /* TQM ring 6 page size and level. */
11428 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
11429 /* TQM ring 6 PBL indirect levels. */
11430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
11432 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
11433 /* PBL pointer is physical start address. */
11434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
11436 /* PBL pointer points to PTE table. */
11437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
11439 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
11442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
11443 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
11444 /* TQM ring 6 page size. */
11445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
11447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
11449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
11450 (UINT32_C(0x0) << 4)
11452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
11453 (UINT32_C(0x1) << 4)
11455 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
11456 (UINT32_C(0x2) << 4)
11458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
11459 (UINT32_C(0x3) << 4)
11461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
11462 (UINT32_C(0x4) << 4)
11464 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
11465 (UINT32_C(0x5) << 4)
11466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
11467 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
11468 /* TQM ring 7 page size and level. */
11469 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
11470 /* TQM ring 7 PBL indirect levels. */
11471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
11473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
11474 /* PBL pointer is physical start address. */
11475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
11477 /* PBL pointer points to PTE table. */
11478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
11480 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
11483 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
11484 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
11485 /* TQM ring 7 page size. */
11486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
11488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
11490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
11491 (UINT32_C(0x0) << 4)
11493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
11494 (UINT32_C(0x1) << 4)
11496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
11497 (UINT32_C(0x2) << 4)
11499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
11500 (UINT32_C(0x3) << 4)
11502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
11503 (UINT32_C(0x4) << 4)
11505 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
11506 (UINT32_C(0x5) << 4)
11507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
11508 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
11509 /* MR/AV page size and level. */
11510 uint8_t mrav_pg_size_mrav_lvl;
11511 /* MR/AV PBL indirect levels. */
11512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
11514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
11515 /* PBL pointer is physical start address. */
11516 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
11518 /* PBL pointer points to PTE table. */
11519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
11521 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
11524 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
11525 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
11526 /* MR/AV page size. */
11527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
11529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
11531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
11532 (UINT32_C(0x0) << 4)
11534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
11535 (UINT32_C(0x1) << 4)
11537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
11538 (UINT32_C(0x2) << 4)
11540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
11541 (UINT32_C(0x3) << 4)
11543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
11544 (UINT32_C(0x4) << 4)
11546 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
11547 (UINT32_C(0x5) << 4)
11548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
11549 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
11550 /* Timer page size and level. */
11551 uint8_t tim_pg_size_tim_lvl;
11552 /* Timer PBL indirect levels. */
11553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
11555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
11556 /* PBL pointer is physical start address. */
11557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
11559 /* PBL pointer points to PTE table. */
11560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
11562 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
11565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
11566 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
11567 /* Timer page size. */
11568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
11570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
11572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
11573 (UINT32_C(0x0) << 4)
11575 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
11576 (UINT32_C(0x1) << 4)
11578 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
11579 (UINT32_C(0x2) << 4)
11581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
11582 (UINT32_C(0x3) << 4)
11584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
11585 (UINT32_C(0x4) << 4)
11587 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
11588 (UINT32_C(0x5) << 4)
11589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
11590 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
11591 /* QP page directory. */
11592 uint64_t qpc_page_dir;
11593 /* SRQ page directory. */
11594 uint64_t srq_page_dir;
11595 /* CQ page directory. */
11596 uint64_t cq_page_dir;
11597 /* VNIC page directory. */
11598 uint64_t vnic_page_dir;
11599 /* Stat page directory. */
11600 uint64_t stat_page_dir;
11601 /* TQM slowpath page directory. */
11602 uint64_t tqm_sp_page_dir;
11603 /* TQM ring 0 page directory. */
11604 uint64_t tqm_ring0_page_dir;
11605 /* TQM ring 1 page directory. */
11606 uint64_t tqm_ring1_page_dir;
11607 /* TQM ring 2 page directory. */
11608 uint64_t tqm_ring2_page_dir;
11609 /* TQM ring 3 page directory. */
11610 uint64_t tqm_ring3_page_dir;
11611 /* TQM ring 4 page directory. */
11612 uint64_t tqm_ring4_page_dir;
11613 /* TQM ring 5 page directory. */
11614 uint64_t tqm_ring5_page_dir;
11615 /* TQM ring 6 page directory. */
11616 uint64_t tqm_ring6_page_dir;
11617 /* TQM ring 7 page directory. */
11618 uint64_t tqm_ring7_page_dir;
11619 /* MR/AV page directory. */
11620 uint64_t mrav_page_dir;
11621 /* Timer page directory. */
11622 uint64_t tim_page_dir;
11623 /* Number of entries to reserve for QP1 */
11624 uint16_t qp_num_qp1_entries;
11625 /* Number of entries to reserve for L2 */
11626 uint16_t qp_num_l2_entries;
11627 /* Number of QPs. */
11628 uint32_t qp_num_entries;
11629 /* Number of SRQs. */
11630 uint32_t srq_num_entries;
11631 /* Number of entries to reserve for L2 */
11632 uint16_t srq_num_l2_entries;
11633 /* Number of entries to reserve for L2 */
11634 uint16_t cq_num_l2_entries;
11635 /* Number of CQs. */
11636 uint32_t cq_num_entries;
11637 /* Number of entries to reserve for VNIC entries */
11638 uint16_t vnic_num_vnic_entries;
11639 /* Number of entries to reserve for Ring table entries */
11640 uint16_t vnic_num_ring_table_entries;
11641 /* Number of Stats. */
11642 uint32_t stat_num_entries;
11643 /* Number of TQM slowpath entries. */
11644 uint32_t tqm_sp_num_entries;
11645 /* Number of TQM ring 0 entries. */
11646 uint32_t tqm_ring0_num_entries;
11647 /* Number of TQM ring 1 entries. */
11648 uint32_t tqm_ring1_num_entries;
11649 /* Number of TQM ring 2 entries. */
11650 uint32_t tqm_ring2_num_entries;
11651 /* Number of TQM ring 3 entries. */
11652 uint32_t tqm_ring3_num_entries;
11653 /* Number of TQM ring 4 entries. */
11654 uint32_t tqm_ring4_num_entries;
11655 /* Number of TQM ring 5 entries. */
11656 uint32_t tqm_ring5_num_entries;
11657 /* Number of TQM ring 6 entries. */
11658 uint32_t tqm_ring6_num_entries;
11659 /* Number of TQM ring 7 entries. */
11660 uint32_t tqm_ring7_num_entries;
11662 * If the MR/AV split reservation flag is not set, then this field
11663 * represents the total number of MR plus AV entries. For versions
11664 * of firmware that support the split reservation, when it is not
11665 * specified half of the entries will be reserved for MRs and the
11666 * other half for AVs.
11668 * If the MR/AV split reservation flag is set, then this
11669 * field is logically divided into two 16b fields. Bits `[31:16]`
11670 * represents the `mr_num_entries` and bits `[15:0]` represents
11671 * `av_num_entries`. The granularity of these values is defined by
11672 * the `mrav_num_entries_unit` field returned by the
11673 * `backing_store_qcaps` command.
11675 uint32_t mrav_num_entries;
11676 /* Number of Timer entries. */
11677 uint32_t tim_num_entries;
11678 uint8_t unused_1[7];
11680 * This field is used in Output records to indicate that the output
11681 * is completely written to RAM. This field should be read as 1
11682 * to indicate that the output has been completely written.
11683 * When writing a command completion or response to an internal
11684 * processor, the order of writes has to be such that this field
11688 } __attribute__((packed));
11690 /****************************
11691 * hwrm_error_recovery_qcfg *
11692 ****************************/
11695 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
11696 struct hwrm_error_recovery_qcfg_input {
11697 /* The HWRM command request type. */
11700 * The completion ring to send the completion event on. This should
11701 * be the NQ ID returned from the `nq_alloc` HWRM command.
11703 uint16_t cmpl_ring;
11705 * The sequence ID is used by the driver for tracking multiple
11706 * commands. This ID is treated as opaque data by the firmware and
11707 * the value is returned in the `hwrm_resp_hdr` upon completion.
11711 * The target ID of the command:
11712 * * 0x0-0xFFF8 - The function ID
11713 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11714 * * 0xFFFD - Reserved for user-space HWRM interface
11717 uint16_t target_id;
11719 * A physical address pointer pointing to a host buffer that the
11720 * command's response data will be written. This can be either a host
11721 * physical address (HPA) or a guest physical address (GPA) and must
11722 * point to a physically contiguous block of memory.
11724 uint64_t resp_addr;
11725 uint8_t unused_0[8];
11726 } __attribute__((packed));
11728 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
11729 struct hwrm_error_recovery_qcfg_output {
11730 /* The specific error status for the command. */
11731 uint16_t error_code;
11732 /* The HWRM command request type. */
11734 /* The sequence ID from the original command. */
11736 /* The length of the response data in number of bytes. */
11740 * When this flag is set to 1, error recovery will be initiated
11741 * through master function driver.
11743 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
11745 * When this flag is set to 1, error recovery will be performed
11746 * through Co processor.
11748 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
11750 * Driver Polling frequency. This value is in units of 100msec.
11751 * Typical value would be 10 to indicate 1sec.
11752 * Drivers can poll FW health status, Heartbeat, reset_counter with
11755 uint32_t driver_polling_freq;
11757 * This value is in units of 100msec.
11758 * Typical value would be 30 to indicate 3sec.
11759 * Master function wait period from detecting a fatal error to
11760 * initiating reset. In this time period Master PF expects every
11761 * active driver will detect fatal error.
11763 uint32_t master_func_wait_period;
11765 * This value is in units of 100msec.
11766 * Typical value would be 50 to indicate 5sec.
11767 * Normal function wait period from fatal error detection to
11768 * polling FW health status. In this time period, drivers should not
11769 * do any PCIe MMIO transaction and should not send any HWRM commands.
11771 uint32_t normal_func_wait_period;
11773 * This value is in units of 100msec.
11774 * Typical value would be 20 to indicate 2sec.
11775 * This field indicates that, master function wait period after chip
11776 * reset. After this time, master function should reinitialize with
11779 uint32_t master_func_wait_period_after_reset;
11781 * This value is in units of 100msec.
11782 * Typical value would be 60 to indicate 6sec.
11783 * This field is applicable to both master and normal functions.
11784 * Even after chip reset, if FW status not changed to ready,
11785 * then all the functions can poll for this much time and bailout.
11787 uint32_t max_bailout_time_after_reset;
11789 * FW health status register.
11790 * Lower 2 bits indicates address space location and upper 30 bits
11791 * indicates upper 30bits of the register address.
11792 * A value of 0xFFFF-FFFF indicates this register does not exist.
11794 uint32_t fw_health_status_reg;
11795 /* Lower 2 bits indicates address space location. */
11796 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11798 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11801 * If value is 0, this register is located in PCIe config space.
11802 * Drivers have to map appropriate window to access this
11805 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11808 * If value is 1, this register is located in GRC address space.
11809 * Drivers have to map appropriate window to access this
11812 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11815 * If value is 2, this register is located in first BAR address
11816 * space. Drivers have to map appropriate window to access this
11819 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11822 * If value is 3, this register is located in second BAR address
11823 * space. Drivers have to map appropriate window to access this
11824 * Drivers have to map appropriate window to access this
11827 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11829 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11830 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11831 /* Upper 30bits of the register address. */
11832 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11833 UINT32_C(0xfffffffc)
11834 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11837 * FW HeartBeat register.
11838 * Lower 2 bits indicates address space location and upper 30 bits
11839 * indicates actual address.
11840 * A value of 0xFFFF-FFFF indicates this register does not exist.
11842 uint32_t fw_heartbeat_reg;
11843 /* Lower 2 bits indicates address space location. */
11844 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11846 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11849 * If value is 0, this register is located in PCIe config space.
11850 * Drivers have to map appropriate window to access this
11853 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11856 * If value is 1, this register is located in GRC address space.
11857 * Drivers have to map appropriate window to access this
11860 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11863 * If value is 2, this register is located in first BAR address
11864 * space. Drivers have to map appropriate window to access this
11867 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
11870 * If value is 3, this register is located in second BAR address
11871 * space. Drivers have to map appropriate window to access this
11874 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
11876 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
11877 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
11878 /* Upper 30bits of the register address. */
11879 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
11880 UINT32_C(0xfffffffc)
11881 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
11884 * FW reset counter.
11885 * Lower 2 bits indicates address space location and upper 30 bits
11886 * indicates actual address.
11887 * A value of 0xFFFF-FFFF indicates this register does not exist.
11889 uint32_t fw_reset_cnt_reg;
11890 /* Lower 2 bits indicates address space location. */
11891 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
11893 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
11896 * If value is 0, this register is located in PCIe config space.
11897 * Drivers have to map appropriate window to access this
11900 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
11903 * If value is 1, this register is located in GRC address space.
11904 * Drivers have to map appropriate window to access this
11907 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
11910 * If value is 2, this register is located in first BAR address
11911 * space. Drivers have to map appropriate window to access this
11914 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
11917 * If value is 3, this register is located in second BAR address
11918 * space. Drivers have to map appropriate window to access this
11921 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
11923 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
11924 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
11925 /* Upper 30bits of the register address. */
11926 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
11927 UINT32_C(0xfffffffc)
11928 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
11931 * Reset Inprogress Register address for PFs.
11932 * Lower 2 bits indicates address space location and upper 30 bits
11933 * indicates actual address.
11934 * A value of 0xFFFF-FFFF indicates this register does not exist.
11936 uint32_t reset_inprogress_reg;
11937 /* Lower 2 bits indicates address space location. */
11938 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
11940 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
11943 * If value is 0, this register is located in PCIe config space.
11944 * Drivers have to map appropriate window to access this
11947 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
11950 * If value is 1, this register is located in GRC address space.
11951 * Drivers have to map appropriate window to access this
11954 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
11957 * If value is 2, this register is located in first BAR address
11958 * space. Drivers have to map appropriate window to access this
11961 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
11964 * If value is 3, this register is located in second BAR address
11965 * space. Drivers have to map appropriate window to access this
11968 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
11970 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
11971 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
11972 /* Upper 30bits of the register address. */
11973 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
11974 UINT32_C(0xfffffffc)
11975 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
11977 /* This field indicates the mask value for reset_inprogress_reg. */
11978 uint32_t reset_inprogress_reg_mask;
11979 uint8_t unused_0[3];
11981 * Array of registers and value count to reset the Chip
11982 * Each array count has reset_reg, reset_reg_val, delay_after_reset
11983 * in TLV format. Depending upon Chip type, number of reset registers
11984 * will vary. Drivers have to write reset_reg_val in the reset_reg
11985 * location in the same sequence in order to recover from a fatal
11988 uint8_t reg_array_cnt;
11991 * Lower 2 bits indicates address space location and upper 30 bits
11992 * indicates actual address.
11993 * A value of 0xFFFF-FFFF indicates this register does not exist.
11995 uint32_t reset_reg[16];
11996 /* Lower 2 bits indicates address space location. */
11997 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
11999 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
12001 * If value is 0, this register is located in PCIe config space.
12002 * Drivers have to map appropriate window to access this
12005 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
12008 * If value is 1, this register is located in GRC address space.
12009 * Drivers have to map appropriate window to access this
12012 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
12015 * If value is 2, this register is located in first BAR address
12016 * space. Drivers have to map appropriate window to access this
12019 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
12022 * If value is 3, this register is located in second BAR address
12023 * space. Drivers have to map appropriate window to access this
12026 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
12028 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
12029 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
12030 /* Upper 30bits of the register address. */
12031 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
12032 UINT32_C(0xfffffffc)
12033 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
12034 /* Value to be written in reset_reg to reset the controller. */
12035 uint32_t reset_reg_val[16];
12037 * This value is in units of 1msec.
12038 * Typical value would be 10 to indicate 10msec.
12039 * Some of the operations like Core reset require delay before
12040 * accessing PCIE MMIO register space.
12041 * If this value is non-zero, drivers have to wait for
12042 * this much time after writing reset_reg_val in reset_reg.
12044 uint8_t delay_after_reset[16];
12045 uint8_t unused_1[7];
12047 * This field is used in Output records to indicate that the output
12048 * is completely written to RAM. This field should be read as '1'
12049 * to indicate that the output has been completely written.
12050 * When writing a command completion or response to an internal
12051 * processor, the order of writes has to be such that this field
12055 } __attribute__((packed));
12057 /***********************
12058 * hwrm_func_vlan_qcfg *
12059 ***********************/
12062 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
12063 struct hwrm_func_vlan_qcfg_input {
12064 /* The HWRM command request type. */
12067 * The completion ring to send the completion event on. This should
12068 * be the NQ ID returned from the `nq_alloc` HWRM command.
12070 uint16_t cmpl_ring;
12072 * The sequence ID is used by the driver for tracking multiple
12073 * commands. This ID is treated as opaque data by the firmware and
12074 * the value is returned in the `hwrm_resp_hdr` upon completion.
12078 * The target ID of the command:
12079 * * 0x0-0xFFF8 - The function ID
12080 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12081 * * 0xFFFD - Reserved for user-space HWRM interface
12084 uint16_t target_id;
12086 * A physical address pointer pointing to a host buffer that the
12087 * command's response data will be written. This can be either a host
12088 * physical address (HPA) or a guest physical address (GPA) and must
12089 * point to a physically contiguous block of memory.
12091 uint64_t resp_addr;
12093 * Function ID of the function that is being
12095 * If set to 0xFF... (All Fs), then the configuration is
12096 * for the requesting function.
12099 uint8_t unused_0[6];
12100 } __attribute__((packed));
12102 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
12103 struct hwrm_func_vlan_qcfg_output {
12104 /* The specific error status for the command. */
12105 uint16_t error_code;
12106 /* The HWRM command request type. */
12108 /* The sequence ID from the original command. */
12110 /* The length of the response data in number of bytes. */
12113 /* S-TAG VLAN identifier configured for the function. */
12115 /* S-TAG PCP value configured for the function. */
12119 * S-TAG TPID value configured for the function. This field is specified in
12120 * network byte order.
12122 uint16_t stag_tpid;
12123 /* C-TAG VLAN identifier configured for the function. */
12125 /* C-TAG PCP value configured for the function. */
12129 * C-TAG TPID value configured for the function. This field is specified in
12130 * network byte order.
12132 uint16_t ctag_tpid;
12137 uint8_t unused_3[3];
12139 * This field is used in Output records to indicate that the output
12140 * is completely written to RAM. This field should be read as '1'
12141 * to indicate that the output has been completely written.
12142 * When writing a command completion or response to an internal processor,
12143 * the order of writes has to be such that this field is written last.
12146 } __attribute__((packed));
12148 /**********************
12149 * hwrm_func_vlan_cfg *
12150 **********************/
12153 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
12154 struct hwrm_func_vlan_cfg_input {
12155 /* The HWRM command request type. */
12158 * The completion ring to send the completion event on. This should
12159 * be the NQ ID returned from the `nq_alloc` HWRM command.
12161 uint16_t cmpl_ring;
12163 * The sequence ID is used by the driver for tracking multiple
12164 * commands. This ID is treated as opaque data by the firmware and
12165 * the value is returned in the `hwrm_resp_hdr` upon completion.
12169 * The target ID of the command:
12170 * * 0x0-0xFFF8 - The function ID
12171 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12172 * * 0xFFFD - Reserved for user-space HWRM interface
12175 uint16_t target_id;
12177 * A physical address pointer pointing to a host buffer that the
12178 * command's response data will be written. This can be either a host
12179 * physical address (HPA) or a guest physical address (GPA) and must
12180 * point to a physically contiguous block of memory.
12182 uint64_t resp_addr;
12184 * Function ID of the function that is being
12186 * If set to 0xFF... (All Fs), then the configuration is
12187 * for the requesting function.
12190 uint8_t unused_0[2];
12193 * This bit must be '1' for the stag_vid field to be
12196 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
12198 * This bit must be '1' for the ctag_vid field to be
12201 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
12203 * This bit must be '1' for the stag_pcp field to be
12206 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
12208 * This bit must be '1' for the ctag_pcp field to be
12211 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
12213 * This bit must be '1' for the stag_tpid field to be
12216 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
12218 * This bit must be '1' for the ctag_tpid field to be
12221 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
12222 /* S-TAG VLAN identifier configured for the function. */
12224 /* S-TAG PCP value configured for the function. */
12228 * S-TAG TPID value configured for the function. This field is specified in
12229 * network byte order.
12231 uint16_t stag_tpid;
12232 /* C-TAG VLAN identifier configured for the function. */
12234 /* C-TAG PCP value configured for the function. */
12238 * C-TAG TPID value configured for the function. This field is specified in
12239 * network byte order.
12241 uint16_t ctag_tpid;
12246 uint8_t unused_3[4];
12247 } __attribute__((packed));
12249 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
12250 struct hwrm_func_vlan_cfg_output {
12251 /* The specific error status for the command. */
12252 uint16_t error_code;
12253 /* The HWRM command request type. */
12255 /* The sequence ID from the original command. */
12257 /* The length of the response data in number of bytes. */
12259 uint8_t unused_0[7];
12261 * This field is used in Output records to indicate that the output
12262 * is completely written to RAM. This field should be read as '1'
12263 * to indicate that the output has been completely written.
12264 * When writing a command completion or response to an internal processor,
12265 * the order of writes has to be such that this field is written last.
12268 } __attribute__((packed));
12270 /*******************************
12271 * hwrm_func_vf_vnic_ids_query *
12272 *******************************/
12275 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
12276 struct hwrm_func_vf_vnic_ids_query_input {
12277 /* The HWRM command request type. */
12280 * The completion ring to send the completion event on. This should
12281 * be the NQ ID returned from the `nq_alloc` HWRM command.
12283 uint16_t cmpl_ring;
12285 * The sequence ID is used by the driver for tracking multiple
12286 * commands. This ID is treated as opaque data by the firmware and
12287 * the value is returned in the `hwrm_resp_hdr` upon completion.
12291 * The target ID of the command:
12292 * * 0x0-0xFFF8 - The function ID
12293 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12294 * * 0xFFFD - Reserved for user-space HWRM interface
12297 uint16_t target_id;
12299 * A physical address pointer pointing to a host buffer that the
12300 * command's response data will be written. This can be either a host
12301 * physical address (HPA) or a guest physical address (GPA) and must
12302 * point to a physically contiguous block of memory.
12304 uint64_t resp_addr;
12306 * This value is used to identify a Virtual Function (VF).
12307 * The scope of VF ID is local within a PF.
12310 uint8_t unused_0[2];
12311 /* Max number of vnic ids in vnic id table */
12312 uint32_t max_vnic_id_cnt;
12313 /* This is the address for VF VNIC ID table */
12314 uint64_t vnic_id_tbl_addr;
12315 } __attribute__((packed));
12317 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
12318 struct hwrm_func_vf_vnic_ids_query_output {
12319 /* The specific error status for the command. */
12320 uint16_t error_code;
12321 /* The HWRM command request type. */
12323 /* The sequence ID from the original command. */
12325 /* The length of the response data in number of bytes. */
12328 * Actual number of vnic ids
12330 * Each VNIC ID is written as a 32-bit number.
12332 uint32_t vnic_id_cnt;
12333 uint8_t unused_0[3];
12335 * This field is used in Output records to indicate that the output
12336 * is completely written to RAM. This field should be read as '1'
12337 * to indicate that the output has been completely written.
12338 * When writing a command completion or response to an internal processor,
12339 * the order of writes has to be such that this field is written last.
12342 } __attribute__((packed));
12344 /***********************
12345 * hwrm_func_vf_bw_cfg *
12346 ***********************/
12349 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
12350 struct hwrm_func_vf_bw_cfg_input {
12351 /* The HWRM command request type. */
12354 * The completion ring to send the completion event on. This should
12355 * be the NQ ID returned from the `nq_alloc` HWRM command.
12357 uint16_t cmpl_ring;
12359 * The sequence ID is used by the driver for tracking multiple
12360 * commands. This ID is treated as opaque data by the firmware and
12361 * the value is returned in the `hwrm_resp_hdr` upon completion.
12365 * The target ID of the command:
12366 * * 0x0-0xFFF8 - The function ID
12367 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12368 * * 0xFFFD - Reserved for user-space HWRM interface
12371 uint16_t target_id;
12373 * A physical address pointer pointing to a host buffer that the
12374 * command's response data will be written. This can be either a host
12375 * physical address (HPA) or a guest physical address (GPA) and must
12376 * point to a physically contiguous block of memory.
12378 uint64_t resp_addr;
12380 * The number of VF functions that are being configured.
12381 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
12384 uint16_t unused[3];
12385 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12387 /* The physical VF id the adjustment will be made to. */
12388 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12389 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
12391 * This field configures the rate scale percentage of the VF as specified
12392 * by the physical VF id.
12394 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
12395 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
12396 /* 0% of the max tx rate */
12397 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
12398 (UINT32_C(0x0) << 12)
12399 /* 6.66% of the max tx rate */
12400 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
12401 (UINT32_C(0x1) << 12)
12402 /* 13.33% of the max tx rate */
12403 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
12404 (UINT32_C(0x2) << 12)
12405 /* 20% of the max tx rate */
12406 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
12407 (UINT32_C(0x3) << 12)
12408 /* 26.66% of the max tx rate */
12409 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
12410 (UINT32_C(0x4) << 12)
12411 /* 33% of the max tx rate */
12412 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
12413 (UINT32_C(0x5) << 12)
12414 /* 40% of the max tx rate */
12415 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
12416 (UINT32_C(0x6) << 12)
12417 /* 46.66% of the max tx rate */
12418 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
12419 (UINT32_C(0x7) << 12)
12420 /* 53.33% of the max tx rate */
12421 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
12422 (UINT32_C(0x8) << 12)
12423 /* 60% of the max tx rate */
12424 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
12425 (UINT32_C(0x9) << 12)
12426 /* 66.66% of the max tx rate */
12427 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
12428 (UINT32_C(0xa) << 12)
12429 /* 53.33% of the max tx rate */
12430 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
12431 (UINT32_C(0xb) << 12)
12432 /* 80% of the max tx rate */
12433 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
12434 (UINT32_C(0xc) << 12)
12435 /* 86.66% of the max tx rate */
12436 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
12437 (UINT32_C(0xd) << 12)
12438 /* 93.33% of the max tx rate */
12439 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
12440 (UINT32_C(0xe) << 12)
12441 /* 100% of the max tx rate */
12442 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
12443 (UINT32_C(0xf) << 12)
12444 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
12445 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
12446 } __attribute__((packed));
12448 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
12449 struct hwrm_func_vf_bw_cfg_output {
12450 /* The specific error status for the command. */
12451 uint16_t error_code;
12452 /* The HWRM command request type. */
12454 /* The sequence ID from the original command. */
12456 /* The length of the response data in number of bytes. */
12458 uint8_t unused_0[7];
12460 * This field is used in Output records to indicate that the output
12461 * is completely written to RAM. This field should be read as '1'
12462 * to indicate that the output has been completely written.
12463 * When writing a command completion or response to an internal processor,
12464 * the order of writes has to be such that this field is written last.
12467 } __attribute__((packed));
12469 /************************
12470 * hwrm_func_vf_bw_qcfg *
12471 ************************/
12474 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
12475 struct hwrm_func_vf_bw_qcfg_input {
12476 /* The HWRM command request type. */
12479 * The completion ring to send the completion event on. This should
12480 * be the NQ ID returned from the `nq_alloc` HWRM command.
12482 uint16_t cmpl_ring;
12484 * The sequence ID is used by the driver for tracking multiple
12485 * commands. This ID is treated as opaque data by the firmware and
12486 * the value is returned in the `hwrm_resp_hdr` upon completion.
12490 * The target ID of the command:
12491 * * 0x0-0xFFF8 - The function ID
12492 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12493 * * 0xFFFD - Reserved for user-space HWRM interface
12496 uint16_t target_id;
12498 * A physical address pointer pointing to a host buffer that the
12499 * command's response data will be written. This can be either a host
12500 * physical address (HPA) or a guest physical address (GPA) and must
12501 * point to a physically contiguous block of memory.
12503 uint64_t resp_addr;
12505 * The number of VF functions that are being queried.
12506 * The inline response space allows the host to query up to 50 VFs'
12507 * rate scale percentage
12510 uint16_t unused[3];
12511 /* These 16-bit fields contain the VF fid */
12513 /* The physical VF id of interest */
12514 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12515 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
12516 } __attribute__((packed));
12518 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
12519 struct hwrm_func_vf_bw_qcfg_output {
12520 /* The specific error status for the command. */
12521 uint16_t error_code;
12522 /* The HWRM command request type. */
12524 /* The sequence ID from the original command. */
12526 /* The length of the response data in number of bytes. */
12529 * The number of VF functions that are being queried.
12530 * The inline response space allows the host to query up to 50 VFs' rate
12534 uint16_t unused[3];
12535 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12537 /* The physical VF id the adjustment will be made to. */
12538 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
12539 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
12541 * This field configures the rate scale percentage of the VF as specified
12542 * by the physical VF id.
12544 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
12545 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
12546 /* 0% of the max tx rate */
12547 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
12548 (UINT32_C(0x0) << 12)
12549 /* 6.66% of the max tx rate */
12550 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
12551 (UINT32_C(0x1) << 12)
12552 /* 13.33% of the max tx rate */
12553 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
12554 (UINT32_C(0x2) << 12)
12555 /* 20% of the max tx rate */
12556 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
12557 (UINT32_C(0x3) << 12)
12558 /* 26.66% of the max tx rate */
12559 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
12560 (UINT32_C(0x4) << 12)
12561 /* 33% of the max tx rate */
12562 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
12563 (UINT32_C(0x5) << 12)
12564 /* 40% of the max tx rate */
12565 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
12566 (UINT32_C(0x6) << 12)
12567 /* 46.66% of the max tx rate */
12568 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
12569 (UINT32_C(0x7) << 12)
12570 /* 53.33% of the max tx rate */
12571 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
12572 (UINT32_C(0x8) << 12)
12573 /* 60% of the max tx rate */
12574 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
12575 (UINT32_C(0x9) << 12)
12576 /* 66.66% of the max tx rate */
12577 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
12578 (UINT32_C(0xa) << 12)
12579 /* 53.33% of the max tx rate */
12580 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
12581 (UINT32_C(0xb) << 12)
12582 /* 80% of the max tx rate */
12583 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
12584 (UINT32_C(0xc) << 12)
12585 /* 86.66% of the max tx rate */
12586 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
12587 (UINT32_C(0xd) << 12)
12588 /* 93.33% of the max tx rate */
12589 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
12590 (UINT32_C(0xe) << 12)
12591 /* 100% of the max tx rate */
12592 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
12593 (UINT32_C(0xf) << 12)
12594 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
12595 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
12596 uint8_t unused_0[7];
12598 * This field is used in Output records to indicate that the output
12599 * is completely written to RAM. This field should be read as '1'
12600 * to indicate that the output has been completely written.
12601 * When writing a command completion or response to an internal processor,
12602 * the order of writes has to be such that this field is written last.
12605 } __attribute__((packed));
12607 /***************************
12608 * hwrm_func_drv_if_change *
12609 ***************************/
12612 /* hwrm_func_drv_if_change_input (size:192b/24B) */
12613 struct hwrm_func_drv_if_change_input {
12614 /* The HWRM command request type. */
12617 * The completion ring to send the completion event on. This should
12618 * be the NQ ID returned from the `nq_alloc` HWRM command.
12620 uint16_t cmpl_ring;
12622 * The sequence ID is used by the driver for tracking multiple
12623 * commands. This ID is treated as opaque data by the firmware and
12624 * the value is returned in the `hwrm_resp_hdr` upon completion.
12628 * The target ID of the command:
12629 * * 0x0-0xFFF8 - The function ID
12630 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12631 * * 0xFFFD - Reserved for user-space HWRM interface
12634 uint16_t target_id;
12636 * A physical address pointer pointing to a host buffer that the
12637 * command's response data will be written. This can be either a host
12638 * physical address (HPA) or a guest physical address (GPA) and must
12639 * point to a physically contiguous block of memory.
12641 uint64_t resp_addr;
12644 * When this bit is '1', the function driver is indicating
12645 * that the IF state is changing to UP state. The call should
12646 * be made at the beginning of the driver's open call before
12647 * resources are allocated. After making the call, the driver
12648 * should check the response to see if any resources may have
12649 * changed (see the response below). If the driver fails
12650 * the open call, the driver should make this call again with
12651 * this bit cleared to indicate that the IF state is not UP.
12652 * During the driver's close call when the IF state is changing
12653 * to DOWN, the driver should make this call with the bit cleared
12654 * after all resources have been freed.
12656 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
12658 } __attribute__((packed));
12660 /* hwrm_func_drv_if_change_output (size:128b/16B) */
12661 struct hwrm_func_drv_if_change_output {
12662 /* The specific error status for the command. */
12663 uint16_t error_code;
12664 /* The HWRM command request type. */
12666 /* The sequence ID from the original command. */
12668 /* The length of the response data in number of bytes. */
12672 * When this bit is '1', it indicates that the resources reserved
12673 * for this function may have changed. The driver should check
12674 * resource capabilities and reserve resources again before
12675 * allocating resources.
12677 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
12680 * When this bit is '1', it indicates that the firmware got changed / reset.
12681 * The driver should do complete re-initialization when that bit is set.
12683 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
12685 uint8_t unused_0[3];
12687 * This field is used in Output records to indicate that the output
12688 * is completely written to RAM. This field should be read as '1'
12689 * to indicate that the output has been completely written.
12690 * When writing a command completion or response to an internal processor,
12691 * the order of writes has to be such that this field is written last.
12694 } __attribute__((packed));
12696 /*******************************
12697 * hwrm_func_host_pf_ids_query *
12698 *******************************/
12701 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
12702 struct hwrm_func_host_pf_ids_query_input {
12703 /* The HWRM command request type. */
12706 * The completion ring to send the completion event on. This should
12707 * be the NQ ID returned from the `nq_alloc` HWRM command.
12709 uint16_t cmpl_ring;
12711 * The sequence ID is used by the driver for tracking multiple
12712 * commands. This ID is treated as opaque data by the firmware and
12713 * the value is returned in the `hwrm_resp_hdr` upon completion.
12717 * The target ID of the command:
12718 * * 0x0-0xFFF8 - The function ID
12719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12720 * * 0xFFFD - Reserved for user-space HWRM interface
12723 uint16_t target_id;
12725 * A physical address pointer pointing to a host buffer that the
12726 * command's response data will be written. This can be either a host
12727 * physical address (HPA) or a guest physical address (GPA) and must
12728 * point to a physically contiguous block of memory.
12730 uint64_t resp_addr;
12733 * # If this bit is set to '1', the query will contain PF(s)
12734 * belongs to SOC host.
12736 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
12738 * # If this bit is set to '1', the query will contain PF(s)
12739 * belongs to EP0 host.
12741 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
12743 * # If this bit is set to '1', the query will contain PF(s)
12744 * belongs to EP1 host.
12746 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
12748 * # If this bit is set to '1', the query will contain PF(s)
12749 * belongs to EP2 host.
12751 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
12753 * # If this bit is set to '1', the query will contain PF(s)
12754 * belongs to EP3 host.
12756 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
12758 * This provides a filter of what PF(s) will be returned in the
12763 * all available PF(s) belong to the host(s) (defined in the
12764 * host field). This includes the hidden PFs.
12766 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
12768 * all available PF(s) belong to the host(s) (defined in the
12769 * host field) that is available for L2 traffic.
12771 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
12773 * all available PF(s) belong to the host(s) (defined in the
12774 * host field) that is available for ROCE traffic.
12776 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
12777 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
12778 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
12779 uint8_t unused_1[6];
12780 } __attribute__((packed));
12782 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
12783 struct hwrm_func_host_pf_ids_query_output {
12784 /* The specific error status for the command. */
12785 uint16_t error_code;
12786 /* The HWRM command request type. */
12788 /* The sequence ID from the original command. */
12790 /* The length of the response data in number of bytes. */
12792 /* This provides the first PF ID of the device. */
12793 uint16_t first_pf_id;
12794 uint16_t pf_ordinal_mask;
12796 * When this bit is '1', it indicates first PF belongs to one of
12797 * the hosts defined in the input request.
12799 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
12802 * When this bit is '1', it indicates 2nd PF belongs to one of the
12803 * hosts defined in the input request.
12805 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
12808 * When this bit is '1', it indicates 3rd PF belongs to one of the
12809 * hosts defined in the input request.
12811 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
12814 * When this bit is '1', it indicates 4th PF belongs to one of the
12815 * hosts defined in the input request.
12817 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
12820 * When this bit is '1', it indicates 5th PF belongs to one of the
12821 * hosts defined in the input request.
12823 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
12826 * When this bit is '1', it indicates 6th PF belongs to one of the
12827 * hosts defined in the input request.
12829 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
12832 * When this bit is '1', it indicates 7th PF belongs to one of the
12833 * hosts defined in the input request.
12835 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
12838 * When this bit is '1', it indicates 8th PF belongs to one of the
12839 * hosts defined in the input request.
12841 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
12844 * When this bit is '1', it indicates 9th PF belongs to one of the
12845 * hosts defined in the input request.
12847 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
12850 * When this bit is '1', it indicates 10th PF belongs to one of the
12851 * hosts defined in the input request.
12853 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
12856 * When this bit is '1', it indicates 11th PF belongs to one of the
12857 * hosts defined in the input request.
12859 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
12862 * When this bit is '1', it indicates 12th PF belongs to one of the
12863 * hosts defined in the input request.
12865 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
12868 * When this bit is '1', it indicates 13th PF belongs to one of the
12869 * hosts defined in the input request.
12871 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
12874 * When this bit is '1', it indicates 14th PF belongs to one of the
12875 * hosts defined in the input request.
12877 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
12880 * When this bit is '1', it indicates 15th PF belongs to one of the
12881 * hosts defined in the input request.
12883 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
12886 * When this bit is '1', it indicates 16th PF belongs to one of the
12887 * hosts defined in the input request.
12889 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
12891 uint8_t unused_1[3];
12893 * This field is used in Output records to indicate that the output
12894 * is completely written to RAM. This field should be read as '1'
12895 * to indicate that the output has been completely written.
12896 * When writing a command completion or response to an internal processor,
12897 * the order of writes has to be such that this field is written last.
12900 } __attribute__((packed));
12902 /*********************
12903 * hwrm_port_phy_cfg *
12904 *********************/
12907 /* hwrm_port_phy_cfg_input (size:448b/56B) */
12908 struct hwrm_port_phy_cfg_input {
12909 /* The HWRM command request type. */
12912 * The completion ring to send the completion event on. This should
12913 * be the NQ ID returned from the `nq_alloc` HWRM command.
12915 uint16_t cmpl_ring;
12917 * The sequence ID is used by the driver for tracking multiple
12918 * commands. This ID is treated as opaque data by the firmware and
12919 * the value is returned in the `hwrm_resp_hdr` upon completion.
12923 * The target ID of the command:
12924 * * 0x0-0xFFF8 - The function ID
12925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12926 * * 0xFFFD - Reserved for user-space HWRM interface
12929 uint16_t target_id;
12931 * A physical address pointer pointing to a host buffer that the
12932 * command's response data will be written. This can be either a host
12933 * physical address (HPA) or a guest physical address (GPA) and must
12934 * point to a physically contiguous block of memory.
12936 uint64_t resp_addr;
12939 * When this bit is set to '1', the PHY for the port shall
12942 * # If this bit is set to 1, then the HWRM shall reset the
12943 * PHY after applying PHY configuration changes specified
12945 * # In order to guarantee that PHY configuration changes
12946 * specified in this command take effect, the HWRM
12947 * client should set this flag to 1.
12948 * # If this bit is not set to 1, then the HWRM may reset
12949 * the PHY depending on the current PHY configuration and
12950 * settings specified in this command.
12952 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
12954 /* deprecated bit. Do not use!!! */
12955 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
12958 * When this bit is set to '1', the link shall be forced to
12959 * the force_link_speed value.
12961 * When this bit is set to '1', the HWRM client should
12962 * not enable any of the auto negotiation related
12963 * fields represented by auto_XXX fields in this command.
12964 * When this bit is set to '1' and the HWRM client has
12965 * enabled a auto_XXX field in this command, then the
12966 * HWRM shall ignore the enabled auto_XXX field.
12968 * When this bit is set to zero, the link
12969 * shall be allowed to autoneg.
12971 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
12974 * When this bit is set to '1', the auto-negotiation process
12975 * shall be restarted on the link.
12977 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
12980 * When this bit is set to '1', Energy Efficient Ethernet
12981 * (EEE) is requested to be enabled on this link.
12982 * If EEE is not supported on this port, then this flag
12983 * shall be ignored by the HWRM.
12985 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
12988 * When this bit is set to '1', Energy Efficient Ethernet
12989 * (EEE) is requested to be disabled on this link.
12990 * If EEE is not supported on this port, then this flag
12991 * shall be ignored by the HWRM.
12993 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
12996 * When this bit is set to '1' and EEE is enabled on this
12997 * link, then TX LPI is requested to be enabled on the link.
12998 * If EEE is not supported on this port, then this flag
12999 * shall be ignored by the HWRM.
13000 * If EEE is disabled on this port, then this flag shall be
13001 * ignored by the HWRM.
13003 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
13006 * When this bit is set to '1' and EEE is enabled on this
13007 * link, then TX LPI is requested to be disabled on the link.
13008 * If EEE is not supported on this port, then this flag
13009 * shall be ignored by the HWRM.
13010 * If EEE is disabled on this port, then this flag shall be
13011 * ignored by the HWRM.
13013 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
13016 * When set to 1, then the HWRM shall enable FEC autonegotitation
13017 * on this port if supported.
13018 * When set to 0, then this flag shall be ignored.
13019 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13022 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
13025 * When set to 1, then the HWRM shall disable FEC autonegotiation
13026 * on this port if supported.
13027 * When set to 0, then this flag shall be ignored.
13028 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13031 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
13034 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
13035 * on this port if supported.
13036 * When set to 0, then this flag shall be ignored.
13037 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13040 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
13043 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
13044 * on this port if supported.
13045 * When set to 0, then this flag shall be ignored.
13046 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13049 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
13052 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
13053 * on this port if supported.
13054 * When set to 0, then this flag shall be ignored.
13055 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13058 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
13061 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
13062 * on this port if supported.
13063 * When set to 0, then this flag shall be ignored.
13064 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13067 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
13070 * When this bit is set to '1', the link shall be forced to
13073 * # When this bit is set to '1", all other
13074 * command input settings related to the link speed shall
13076 * Once the link state is forced down, it can be
13077 * explicitly cleared from that state by setting this flag
13079 * # If this flag is set to '0', then the link shall be
13080 * cleared from forced down state if the link is in forced
13082 * There may be conditions (e.g. out-of-band or sideband
13083 * configuration changes for the link) outside the scope
13084 * of the HWRM implementation that may clear forced down
13087 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
13091 * This bit must be '1' for the auto_mode field to be
13094 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
13097 * This bit must be '1' for the auto_duplex field to be
13100 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
13103 * This bit must be '1' for the auto_pause field to be
13106 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
13109 * This bit must be '1' for the auto_link_speed field to be
13112 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
13115 * This bit must be '1' for the auto_link_speed_mask field to be
13118 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
13121 * This bit must be '1' for the wirespeed field to be
13124 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
13127 * This bit must be '1' for the lpbk field to be
13130 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
13133 * This bit must be '1' for the preemphasis field to be
13136 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
13139 * This bit must be '1' for the force_pause field to be
13142 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
13145 * This bit must be '1' for the eee_link_speed_mask field to be
13148 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
13151 * This bit must be '1' for the tx_lpi_timer field to be
13154 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
13156 /* Port ID of port that is to be configured. */
13159 * This is the speed that will be used if the force
13160 * bit is '1'. If unsupported speed is selected, an error
13161 * will be generated.
13163 uint16_t force_link_speed;
13164 /* 100Mb link speed */
13165 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13166 /* 1Gb link speed */
13167 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13168 /* 2Gb link speed */
13169 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13170 /* 25Gb link speed */
13171 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13172 /* 10Gb link speed */
13173 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13174 /* 20Mb link speed */
13175 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13176 /* 25Gb link speed */
13177 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13178 /* 40Gb link speed */
13179 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
13180 /* 50Gb link speed */
13181 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
13182 /* 100Gb link speed */
13183 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
13184 /* 200Gb link speed */
13185 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
13186 /* 10Mb link speed */
13187 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
13188 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
13189 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
13191 * This value is used to identify what autoneg mode is
13192 * used when the link speed is not being forced.
13195 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13196 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
13197 /* Select all possible speeds for autoneg mode. */
13198 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13200 * Select only the auto_link_speed speed for autoneg mode. This mode has
13201 * been DEPRECATED. An HWRM client should not use this mode.
13203 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13205 * Select the auto_link_speed or any speed below that speed for autoneg.
13206 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13208 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13210 * Select the speeds based on the corresponding link speed mask value
13211 * that is provided.
13213 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13214 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
13215 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
13217 * This is the duplex setting that will be used if the autoneg_mode
13218 * is "one_speed" or "one_or_below".
13220 uint8_t auto_duplex;
13221 /* Half Duplex will be requested. */
13222 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
13223 /* Full duplex will be requested. */
13224 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
13225 /* Both Half and Full dupex will be requested. */
13226 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
13227 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
13228 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
13230 * This value is used to configure the pause that will be
13231 * used for autonegotiation.
13232 * Add text on the usage of auto_pause and force_pause.
13234 uint8_t auto_pause;
13236 * When this bit is '1', Generation of tx pause messages
13237 * has been requested. Disabled otherwise.
13239 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
13242 * When this bit is '1', Reception of rx pause messages
13243 * has been requested. Disabled otherwise.
13245 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
13248 * When set to 1, the advertisement of pause is enabled.
13250 * # When the auto_mode is not set to none and this flag is
13251 * set to 1, then the auto_pause bits on this port are being
13252 * advertised and autoneg pause results are being interpreted.
13253 * # When the auto_mode is not set to none and this
13254 * flag is set to 0, the pause is forced as indicated in
13255 * force_pause, and also advertised as auto_pause bits, but
13256 * the autoneg results are not interpreted since the pause
13257 * configuration is being forced.
13258 * # When the auto_mode is set to none and this flag is set to
13259 * 1, auto_pause bits should be ignored and should be set to 0.
13261 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13265 * This is the speed that will be used if the autoneg_mode
13266 * is "one_speed" or "one_or_below". If an unsupported speed
13267 * is selected, an error will be generated.
13269 uint16_t auto_link_speed;
13270 /* 100Mb link speed */
13271 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13272 /* 1Gb link speed */
13273 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13274 /* 2Gb link speed */
13275 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13276 /* 25Gb link speed */
13277 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13278 /* 10Gb link speed */
13279 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13280 /* 20Mb link speed */
13281 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13282 /* 25Gb link speed */
13283 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13284 /* 40Gb link speed */
13285 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13286 /* 50Gb link speed */
13287 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13288 /* 100Gb link speed */
13289 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13290 /* 200Gb link speed */
13291 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13292 /* 10Mb link speed */
13293 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
13294 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
13295 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
13297 * This is a mask of link speeds that will be used if
13298 * autoneg_mode is "mask". If unsupported speed is enabled
13299 * an error will be generated.
13301 uint16_t auto_link_speed_mask;
13302 /* 100Mb link speed (Half-duplex) */
13303 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13305 /* 100Mb link speed (Full-duplex) */
13306 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
13308 /* 1Gb link speed (Half-duplex) */
13309 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13311 /* 1Gb link speed (Full-duplex) */
13312 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
13314 /* 2Gb link speed */
13315 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
13317 /* 25Gb link speed */
13318 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13320 /* 10Gb link speed */
13321 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
13323 /* 20Gb link speed */
13324 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
13326 /* 25Gb link speed */
13327 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
13329 /* 40Gb link speed */
13330 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
13332 /* 50Gb link speed */
13333 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
13335 /* 100Gb link speed */
13336 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
13338 /* 10Mb link speed (Half-duplex) */
13339 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13341 /* 10Mb link speed (Full-duplex) */
13342 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
13344 /* 200Gb link speed */
13345 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
13347 /* This value controls the wirespeed feature. */
13349 /* Wirespeed feature is disabled. */
13350 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
13351 /* Wirespeed feature is enabled. */
13352 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
13353 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
13354 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
13355 /* This value controls the loopback setting for the PHY. */
13357 /* No loopback is selected. Normal operation. */
13358 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13360 * The HW will be configured with local loopback such that
13361 * host data is sent back to the host without modification.
13363 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13365 * The HW will be configured with remote loopback such that
13366 * port logic will send packets back out the transmitter that
13369 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13371 * The HW will be configured with external loopback such that
13372 * host data is sent on the trasmitter and based on the external
13373 * loopback connection the data will be received without modification.
13375 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
13376 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
13377 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
13379 * This value is used to configure the pause that will be
13380 * used for force mode.
13382 uint8_t force_pause;
13384 * When this bit is '1', Generation of tx pause messages
13385 * is supported. Disabled otherwise.
13387 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13389 * When this bit is '1', Reception of rx pause messages
13390 * is supported. Disabled otherwise.
13392 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13395 * This value controls the pre-emphasis to be used for the
13396 * link. Driver should not set this value (use
13397 * enable.preemphasis = 0) unless driver is sure of setting.
13398 * Normally HWRM FW will determine proper pre-emphasis.
13400 uint32_t preemphasis;
13402 * Setting for link speed mask that is used to
13403 * advertise speeds during autonegotiation when EEE is enabled.
13404 * This field is valid only when EEE is enabled.
13405 * The speeds specified in this field shall be a subset of
13406 * speeds specified in auto_link_speed_mask.
13407 * If EEE is enabled,then at least one speed shall be provided
13410 uint16_t eee_link_speed_mask;
13412 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
13414 /* 100Mb link speed (Full-duplex) */
13415 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
13418 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
13420 /* 1Gb link speed (Full-duplex) */
13421 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
13424 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
13427 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
13429 /* 10Gb link speed */
13430 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
13432 uint8_t unused_2[2];
13434 * Reuested setting of TX LPI timer in microseconds.
13435 * This field is valid only when EEE is enabled and TX LPI is
13438 uint32_t tx_lpi_timer;
13439 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
13440 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
13442 } __attribute__((packed));
13444 /* hwrm_port_phy_cfg_output (size:128b/16B) */
13445 struct hwrm_port_phy_cfg_output {
13446 /* The specific error status for the command. */
13447 uint16_t error_code;
13448 /* The HWRM command request type. */
13450 /* The sequence ID from the original command. */
13452 /* The length of the response data in number of bytes. */
13454 uint8_t unused_0[7];
13456 * This field is used in Output records to indicate that the output
13457 * is completely written to RAM. This field should be read as '1'
13458 * to indicate that the output has been completely written.
13459 * When writing a command completion or response to an internal processor,
13460 * the order of writes has to be such that this field is written last.
13463 } __attribute__((packed));
13465 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
13466 struct hwrm_port_phy_cfg_cmd_err {
13468 * command specific error codes that goes to
13469 * the cmd_err field in Common HWRM Error Response.
13472 /* Unknown error */
13473 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
13474 /* Unable to complete operation due to invalid speed */
13475 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
13477 * retry the command since the phy is not ready.
13478 * retry count is returned in opaque_0.
13479 * This is only valid for the first command and
13480 * this value will not change for successive calls.
13481 * but if a 0 is returned at any time then this should
13482 * be treated as an un recoverable failure,
13484 * retry interval in milli seconds is returned in opaque_1.
13485 * This specifies the time that user should wait before
13486 * issuing the next port_phy_cfg command.
13488 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
13489 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
13490 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
13491 uint8_t unused_0[7];
13492 } __attribute__((packed));
13494 /**********************
13495 * hwrm_port_phy_qcfg *
13496 **********************/
13499 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
13500 struct hwrm_port_phy_qcfg_input {
13501 /* The HWRM command request type. */
13504 * The completion ring to send the completion event on. This should
13505 * be the NQ ID returned from the `nq_alloc` HWRM command.
13507 uint16_t cmpl_ring;
13509 * The sequence ID is used by the driver for tracking multiple
13510 * commands. This ID is treated as opaque data by the firmware and
13511 * the value is returned in the `hwrm_resp_hdr` upon completion.
13515 * The target ID of the command:
13516 * * 0x0-0xFFF8 - The function ID
13517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13518 * * 0xFFFD - Reserved for user-space HWRM interface
13521 uint16_t target_id;
13523 * A physical address pointer pointing to a host buffer that the
13524 * command's response data will be written. This can be either a host
13525 * physical address (HPA) or a guest physical address (GPA) and must
13526 * point to a physically contiguous block of memory.
13528 uint64_t resp_addr;
13529 /* Port ID of port that is to be queried. */
13531 uint8_t unused_0[6];
13532 } __attribute__((packed));
13534 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
13535 struct hwrm_port_phy_qcfg_output {
13536 /* The specific error status for the command. */
13537 uint16_t error_code;
13538 /* The HWRM command request type. */
13540 /* The sequence ID from the original command. */
13542 /* The length of the response data in number of bytes. */
13544 /* This value indicates the current link status. */
13546 /* There is no link or cable detected. */
13547 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
13548 /* There is no link, but a cable has been detected. */
13549 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
13550 /* There is a link. */
13551 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
13552 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
13553 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
13555 /* This value indicates the current link speed of the connection. */
13556 uint16_t link_speed;
13557 /* 100Mb link speed */
13558 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
13559 /* 1Gb link speed */
13560 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
13561 /* 2Gb link speed */
13562 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
13563 /* 25Gb link speed */
13564 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
13565 /* 10Gb link speed */
13566 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
13567 /* 20Mb link speed */
13568 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
13569 /* 25Gb link speed */
13570 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
13571 /* 40Gb link speed */
13572 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
13573 /* 50Gb link speed */
13574 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
13575 /* 100Gb link speed */
13576 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
13577 /* 200Gb link speed */
13578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
13579 /* 10Mb link speed */
13580 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
13581 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
13582 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
13584 * This value is indicates the duplex of the current
13587 uint8_t duplex_cfg;
13588 /* Half Duplex connection. */
13589 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
13590 /* Full duplex connection. */
13591 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
13592 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
13593 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
13595 * This value is used to indicate the current
13596 * pause configuration. When autoneg is enabled, this value
13597 * represents the autoneg results of pause configuration.
13601 * When this bit is '1', Generation of tx pause messages
13602 * is supported. Disabled otherwise.
13604 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
13606 * When this bit is '1', Reception of rx pause messages
13607 * is supported. Disabled otherwise.
13609 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
13611 * The supported speeds for the port. This is a bit mask.
13612 * For each speed that is supported, the corrresponding
13613 * bit will be set to '1'.
13615 uint16_t support_speeds;
13616 /* 100Mb link speed (Half-duplex) */
13617 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
13619 /* 100Mb link speed (Full-duplex) */
13620 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
13622 /* 1Gb link speed (Half-duplex) */
13623 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
13625 /* 1Gb link speed (Full-duplex) */
13626 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
13628 /* 2Gb link speed */
13629 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
13631 /* 25Gb link speed */
13632 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
13634 /* 10Gb link speed */
13635 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
13637 /* 20Gb link speed */
13638 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
13640 /* 25Gb link speed */
13641 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
13643 /* 40Gb link speed */
13644 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
13646 /* 50Gb link speed */
13647 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
13649 /* 100Gb link speed */
13650 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
13652 /* 10Mb link speed (Half-duplex) */
13653 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
13655 /* 10Mb link speed (Full-duplex) */
13656 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
13658 /* 200Gb link speed */
13659 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
13662 * Current setting of forced link speed.
13663 * When the link speed is not being forced, this
13664 * value shall be set to 0.
13666 uint16_t force_link_speed;
13667 /* 100Mb link speed */
13668 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13669 /* 1Gb link speed */
13670 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13671 /* 2Gb link speed */
13672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13673 /* 25Gb link speed */
13674 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13675 /* 10Gb link speed */
13676 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13677 /* 20Mb link speed */
13678 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13679 /* 25Gb link speed */
13680 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13681 /* 40Gb link speed */
13682 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
13684 /* 50Gb link speed */
13685 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
13687 /* 100Gb link speed */
13688 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
13690 /* 200Gb link speed */
13691 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
13693 /* 10Mb link speed */
13694 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
13696 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
13697 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
13698 /* Current setting of auto negotiation mode. */
13700 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13701 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
13702 /* Select all possible speeds for autoneg mode. */
13703 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13705 * Select only the auto_link_speed speed for autoneg mode. This mode has
13706 * been DEPRECATED. An HWRM client should not use this mode.
13708 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13710 * Select the auto_link_speed or any speed below that speed for autoneg.
13711 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13713 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13715 * Select the speeds based on the corresponding link speed mask value
13716 * that is provided.
13718 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13719 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
13720 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
13722 * Current setting of pause autonegotiation.
13723 * Move autoneg_pause flag here.
13725 uint8_t auto_pause;
13727 * When this bit is '1', Generation of tx pause messages
13728 * has been requested. Disabled otherwise.
13730 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
13733 * When this bit is '1', Reception of rx pause messages
13734 * has been requested. Disabled otherwise.
13736 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
13739 * When set to 1, the advertisement of pause is enabled.
13741 * # When the auto_mode is not set to none and this flag is
13742 * set to 1, then the auto_pause bits on this port are being
13743 * advertised and autoneg pause results are being interpreted.
13744 * # When the auto_mode is not set to none and this
13745 * flag is set to 0, the pause is forced as indicated in
13746 * force_pause, and also advertised as auto_pause bits, but
13747 * the autoneg results are not interpreted since the pause
13748 * configuration is being forced.
13749 * # When the auto_mode is set to none and this flag is set to
13750 * 1, auto_pause bits should be ignored and should be set to 0.
13752 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13755 * Current setting for auto_link_speed. This field is only
13756 * valid when auto_mode is set to "one_speed" or "one_or_below".
13758 uint16_t auto_link_speed;
13759 /* 100Mb link speed */
13760 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13761 /* 1Gb link speed */
13762 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13763 /* 2Gb link speed */
13764 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13765 /* 25Gb link speed */
13766 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13767 /* 10Gb link speed */
13768 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13769 /* 20Mb link speed */
13770 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13771 /* 25Gb link speed */
13772 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13773 /* 40Gb link speed */
13774 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13775 /* 50Gb link speed */
13776 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13777 /* 100Gb link speed */
13778 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13779 /* 200Gb link speed */
13780 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13781 /* 10Mb link speed */
13782 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
13784 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
13785 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
13787 * Current setting for auto_link_speed_mask that is used to
13788 * advertise speeds during autonegotiation.
13789 * This field is only valid when auto_mode is set to "mask".
13790 * The speeds specified in this field shall be a subset of
13791 * supported speeds on this port.
13793 uint16_t auto_link_speed_mask;
13794 /* 100Mb link speed (Half-duplex) */
13795 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13797 /* 100Mb link speed (Full-duplex) */
13798 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
13800 /* 1Gb link speed (Half-duplex) */
13801 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13803 /* 1Gb link speed (Full-duplex) */
13804 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
13806 /* 2Gb link speed */
13807 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
13809 /* 25Gb link speed */
13810 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13812 /* 10Gb link speed */
13813 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
13815 /* 20Gb link speed */
13816 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
13818 /* 25Gb link speed */
13819 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
13821 /* 40Gb link speed */
13822 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
13824 /* 50Gb link speed */
13825 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
13827 /* 100Gb link speed */
13828 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
13830 /* 10Mb link speed (Half-duplex) */
13831 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13833 /* 10Mb link speed (Full-duplex) */
13834 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
13836 /* 200Gb link speed */
13837 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
13839 /* Current setting for wirespeed. */
13841 /* Wirespeed feature is disabled. */
13842 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
13843 /* Wirespeed feature is enabled. */
13844 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
13845 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
13846 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
13847 /* Current setting for loopback. */
13849 /* No loopback is selected. Normal operation. */
13850 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13852 * The HW will be configured with local loopback such that
13853 * host data is sent back to the host without modification.
13855 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13857 * The HW will be configured with remote loopback such that
13858 * port logic will send packets back out the transmitter that
13861 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13863 * The HW will be configured with external loopback such that
13864 * host data is sent on the trasmitter and based on the external
13865 * loopback connection the data will be received without modification.
13867 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
13868 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
13869 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
13871 * Current setting of forced pause.
13872 * When the pause configuration is not being forced, then
13873 * this value shall be set to 0.
13875 uint8_t force_pause;
13877 * When this bit is '1', Generation of tx pause messages
13878 * is supported. Disabled otherwise.
13880 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13882 * When this bit is '1', Reception of rx pause messages
13883 * is supported. Disabled otherwise.
13885 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13887 * This value indicates the current status of the optics module on
13890 uint8_t module_status;
13891 /* Module is inserted and accepted */
13892 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
13894 /* Module is rejected and transmit side Laser is disabled. */
13895 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
13897 /* Module mismatch warning. */
13898 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
13900 /* Module is rejected and powered down. */
13901 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
13903 /* Module is not inserted. */
13904 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
13906 /* Module status is not applicable. */
13907 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
13909 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
13910 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
13911 /* Current setting for preemphasis. */
13912 uint32_t preemphasis;
13913 /* This field represents the major version of the PHY. */
13915 /* This field represents the minor version of the PHY. */
13917 /* This field represents the build version of the PHY. */
13919 /* This value represents a PHY type. */
13922 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
13925 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
13927 /* BASE-KR4 (Deprecated) */
13928 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
13931 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
13934 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
13936 /* BASE-KR2 (Deprecated) */
13937 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
13940 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
13943 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
13946 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
13948 /* EEE capable BASE-T */
13949 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
13951 /* SGMII connected external PHY */
13952 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
13954 /* 25G_BASECR_CA_L */
13955 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
13957 /* 25G_BASECR_CA_S */
13958 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
13960 /* 25G_BASECR_CA_N */
13961 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
13964 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
13967 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
13970 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
13973 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
13976 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
13978 /* 100G_BASESR10 */
13979 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
13982 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
13985 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
13988 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
13991 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
13993 /* 40G_ACTIVE_CABLE */
13994 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
13997 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
14000 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
14003 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
14006 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
14009 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
14012 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
14015 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
14017 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
14018 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
14019 /* This value represents a media type. */
14020 uint8_t media_type;
14022 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
14024 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
14025 /* Direct Attached Copper */
14026 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
14028 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
14029 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
14030 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
14031 /* This value represents a transceiver type. */
14032 uint8_t xcvr_pkg_type;
14033 /* PHY and MAC are in the same package */
14034 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
14036 /* PHY and MAC are in different packages */
14037 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
14039 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
14040 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
14041 uint8_t eee_config_phy_addr;
14042 /* This field represents PHY address. */
14043 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
14045 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
14047 * This field represents flags related to EEE configuration.
14048 * These EEE configuration flags are valid only when the
14049 * auto_mode is not set to none (in other words autonegotiation
14052 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
14054 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
14056 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
14057 * Speeds for autoneg with EEE mode enabled
14058 * are based on eee_link_speed_mask.
14060 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
14063 * This flag is valid only when eee_enabled is set to 1.
14065 * # If eee_enabled is set to 0, then EEE mode is disabled
14066 * and this flag shall be ignored.
14067 * # If eee_enabled is set to 1 and this flag is set to 1,
14068 * then Energy Efficient Ethernet (EEE) mode is enabled
14070 * # If eee_enabled is set to 1 and this flag is set to 0,
14071 * then Energy Efficient Ethernet (EEE) mode is enabled
14072 * but is currently not in use.
14074 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
14077 * This flag is valid only when eee_enabled is set to 1.
14079 * # If eee_enabled is set to 0, then EEE mode is disabled
14080 * and this flag shall be ignored.
14081 * # If eee_enabled is set to 1 and this flag is set to 1,
14082 * then Energy Efficient Ethernet (EEE) mode is enabled
14083 * and TX LPI is enabled.
14084 * # If eee_enabled is set to 1 and this flag is set to 0,
14085 * then Energy Efficient Ethernet (EEE) mode is enabled
14086 * but TX LPI is disabled.
14088 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
14091 * When set to 1, the parallel detection is used to determine
14092 * the speed of the link partner.
14094 * Parallel detection is used when a autonegotiation capable
14095 * device is connected to a link parter that is not capable
14096 * of autonegotiation.
14098 uint8_t parallel_detect;
14100 * When set to 1, the parallel detection is used to determine
14101 * the speed of the link partner.
14103 * Parallel detection is used when a autonegotiation capable
14104 * device is connected to a link parter that is not capable
14105 * of autonegotiation.
14107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
14109 * The advertised speeds for the port by the link partner.
14110 * Each advertised speed will be set to '1'.
14112 uint16_t link_partner_adv_speeds;
14113 /* 100Mb link speed (Half-duplex) */
14114 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
14116 /* 100Mb link speed (Full-duplex) */
14117 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
14119 /* 1Gb link speed (Half-duplex) */
14120 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
14122 /* 1Gb link speed (Full-duplex) */
14123 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
14125 /* 2Gb link speed */
14126 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
14128 /* 25Gb link speed */
14129 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
14131 /* 10Gb link speed */
14132 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
14134 /* 20Gb link speed */
14135 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
14137 /* 25Gb link speed */
14138 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
14140 /* 40Gb link speed */
14141 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
14143 /* 50Gb link speed */
14144 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
14146 /* 100Gb link speed */
14147 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
14149 /* 10Mb link speed (Half-duplex) */
14150 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
14152 /* 10Mb link speed (Full-duplex) */
14153 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
14156 * The advertised autoneg for the port by the link partner.
14157 * This field is deprecated and should be set to 0.
14159 uint8_t link_partner_adv_auto_mode;
14160 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14161 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
14163 /* Select all possible speeds for autoneg mode. */
14164 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
14167 * Select only the auto_link_speed speed for autoneg mode. This mode has
14168 * been DEPRECATED. An HWRM client should not use this mode.
14170 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
14173 * Select the auto_link_speed or any speed below that speed for autoneg.
14174 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14176 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
14179 * Select the speeds based on the corresponding link speed mask value
14180 * that is provided.
14182 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
14184 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
14185 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
14186 /* The advertised pause settings on the port by the link partner. */
14187 uint8_t link_partner_adv_pause;
14189 * When this bit is '1', Generation of tx pause messages
14190 * is supported. Disabled otherwise.
14192 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
14195 * When this bit is '1', Reception of rx pause messages
14196 * is supported. Disabled otherwise.
14198 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
14201 * Current setting for link speed mask that is used to
14202 * advertise speeds during autonegotiation when EEE is enabled.
14203 * This field is valid only when eee_enabled flags is set to 1.
14204 * The speeds specified in this field shall be a subset of
14205 * speeds specified in auto_link_speed_mask.
14207 uint16_t adv_eee_link_speed_mask;
14209 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14211 /* 100Mb link speed (Full-duplex) */
14212 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
14215 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14217 /* 1Gb link speed (Full-duplex) */
14218 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
14221 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14224 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14226 /* 10Gb link speed */
14227 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
14230 * Current setting for link speed mask that is advertised by
14231 * the link partner when EEE is enabled.
14232 * This field is valid only when eee_enabled flags is set to 1.
14234 uint16_t link_partner_adv_eee_link_speed_mask;
14236 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14238 /* 100Mb link speed (Full-duplex) */
14239 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
14242 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14244 /* 1Gb link speed (Full-duplex) */
14245 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
14248 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14251 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14253 /* 10Gb link speed */
14254 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
14256 uint32_t xcvr_identifier_type_tx_lpi_timer;
14258 * Current setting of TX LPI timer in microseconds.
14259 * This field is valid only when_eee_enabled flag is set to 1
14260 * and tx_lpi_enabled is set to 1.
14262 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
14264 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
14265 /* This value represents transceiver identifier type. */
14266 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
14267 UINT32_C(0xff000000)
14268 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
14270 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
14271 (UINT32_C(0x0) << 24)
14272 /* SFP/SFP+/SFP28 */
14273 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
14274 (UINT32_C(0x3) << 24)
14276 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
14277 (UINT32_C(0xc) << 24)
14279 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
14280 (UINT32_C(0xd) << 24)
14282 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
14283 (UINT32_C(0x11) << 24)
14284 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
14285 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
14287 * This value represents the current configuration of
14288 * Forward Error Correction (FEC) on the port.
14292 * When set to 1, then FEC is not supported on this port. If this flag
14293 * is set to 1, then all other FEC configuration flags shall be ignored.
14294 * When set to 0, then FEC is supported as indicated by other
14295 * configuration flags.
14296 * If no cable is attached and the HWRM does not yet know the FEC
14297 * capability, then the HWRM shall set this flag to 1 when reporting
14300 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
14303 * When set to 1, then FEC autonegotiation is supported on this port.
14304 * When set to 0, then FEC autonegotiation is not supported on this port.
14306 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
14309 * When set to 1, then FEC autonegotiation is enabled on this port.
14310 * When set to 0, then FEC autonegotiation is disabled if supported.
14311 * This flag should be ignored if FEC autonegotiation is not supported on this port.
14313 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
14316 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
14317 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
14319 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
14322 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
14323 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
14324 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
14326 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
14329 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
14330 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
14332 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
14335 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
14336 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
14337 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
14339 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
14342 * This value is indicates the duplex of the current
14343 * connection state.
14345 uint8_t duplex_state;
14346 /* Half Duplex connection. */
14347 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
14348 /* Full duplex connection. */
14349 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
14350 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
14351 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
14352 /* Option flags fields. */
14353 uint8_t option_flags;
14354 /* When this bit is '1', Media auto detect is enabled. */
14355 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
14358 * Up to 16 bytes of null padded ASCII string representing
14360 * If the string is set to null, then the vendor name is not
14363 char phy_vendor_name[16];
14365 * Up to 16 bytes of null padded ASCII string that
14366 * identifies vendor specific part number of the PHY.
14367 * If the string is set to null, then the vendor specific
14368 * part number is not available.
14370 char phy_vendor_partnumber[16];
14371 uint8_t unused_2[7];
14373 * This field is used in Output records to indicate that the output
14374 * is completely written to RAM. This field should be read as '1'
14375 * to indicate that the output has been completely written.
14376 * When writing a command completion or response to an internal processor,
14377 * the order of writes has to be such that this field is written last.
14380 } __attribute__((packed));
14382 /*********************
14383 * hwrm_port_mac_cfg *
14384 *********************/
14387 /* hwrm_port_mac_cfg_input (size:384b/48B) */
14388 struct hwrm_port_mac_cfg_input {
14389 /* The HWRM command request type. */
14392 * The completion ring to send the completion event on. This should
14393 * be the NQ ID returned from the `nq_alloc` HWRM command.
14395 uint16_t cmpl_ring;
14397 * The sequence ID is used by the driver for tracking multiple
14398 * commands. This ID is treated as opaque data by the firmware and
14399 * the value is returned in the `hwrm_resp_hdr` upon completion.
14403 * The target ID of the command:
14404 * * 0x0-0xFFF8 - The function ID
14405 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14406 * * 0xFFFD - Reserved for user-space HWRM interface
14409 uint16_t target_id;
14411 * A physical address pointer pointing to a host buffer that the
14412 * command's response data will be written. This can be either a host
14413 * physical address (HPA) or a guest physical address (GPA) and must
14414 * point to a physically contiguous block of memory.
14416 uint64_t resp_addr;
14418 * In this field, there are a number of CoS mappings related flags
14419 * that are used to configure CoS mappings and their corresponding
14420 * priorities in the hardware.
14421 * For the priorities of CoS mappings, the HWRM uses the following
14422 * priority order (high to low) by default:
14425 * # tunnel_vlan_pri
14428 * A subset of CoS mappings can be enabled.
14429 * If a priority is not specified for an enabled CoS mapping, the
14430 * priority will be assigned in the above order for the enabled CoS
14431 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
14432 * enabled and their priorities are not specified, the following
14433 * priority order (high to low) will be used by the HWRM:
14438 * vlan_pri CoS mapping together with default CoS with lower priority
14439 * are enabled by default by the HWRM.
14443 * When this bit is '1', this command will configure
14444 * the MAC to match the current link state of the PHY.
14445 * If the link is not established on the PHY, then this
14446 * bit has no effect.
14448 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
14451 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14452 * is requested to be enabled.
14454 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14457 * When this bit is set to '1', tunnel VLAN PRI field to
14458 * CoS mapping is requested to be enabled.
14460 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14463 * When this bit is set to '1', the IP DSCP to CoS mapping is
14464 * requested to be enabled.
14466 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
14469 * When this bit is '1', the HWRM is requested to
14470 * enable timestamp capture capability on the receive side
14473 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14476 * When this bit is '1', the HWRM is requested to
14477 * disable timestamp capture capability on the receive side
14480 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
14483 * When this bit is '1', the HWRM is requested to
14484 * enable timestamp capture capability on the transmit side
14487 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14490 * When this bit is '1', the HWRM is requested to
14491 * disable timestamp capture capability on the transmit side
14494 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
14497 * When this bit is '1', the Out-Of-Box WoL is requested to
14498 * be enabled on this port.
14500 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
14503 * When this bit is '1', the the Out-Of-Box WoL is requested to
14504 * be disabled on this port.
14506 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
14509 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14510 * is requested to be disabled.
14512 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
14515 * When this bit is set to '1', tunnel VLAN PRI field to
14516 * CoS mapping is requested to be disabled.
14518 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
14521 * When this bit is set to '1', the IP DSCP to CoS mapping is
14522 * requested to be disabled.
14524 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
14527 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
14528 * bit is set, then the device uses one step Tx timestamping.
14529 * This bit is temporary and used for experimental purposes.
14531 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
14535 * This bit must be '1' for the ipg field to be
14538 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
14541 * This bit must be '1' for the lpbk field to be
14544 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
14547 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
14550 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
14553 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
14556 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
14559 * This bit must be '1' for the dscp2cos_map_pri field to be
14562 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
14565 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
14568 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
14571 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
14574 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
14577 * This bit must be '1' for the cos_field_cfg field to be
14580 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
14583 * This bit must be '1' for the ptp_freq_adj_ppb field to be
14586 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
14588 /* Port ID of port that is to be configured. */
14591 * This value is used to configure the minimum IPG that will
14592 * be sent between packets by this port.
14595 /* This value controls the loopback setting for the MAC. */
14597 /* No loopback is selected. Normal operation. */
14598 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
14600 * The HW will be configured with local loopback such that
14601 * host data is sent back to the host without modification.
14603 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
14605 * The HW will be configured with remote loopback such that
14606 * port logic will send packets back out the transmitter that
14609 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
14610 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
14611 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
14613 * This value controls the priority setting of VLAN PRI to CoS
14614 * mapping based on VLAN Tags of inner packet headers of
14615 * tunneled packets or packet headers of non-tunneled packets.
14617 * # Each XXX_pri variable shall have a unique priority value
14618 * when it is being specified.
14619 * # When comparing priorities of mappings, higher value
14620 * indicates higher priority.
14621 * For example, a value of 0-3 is returned where 0 is being
14622 * the lowest priority and 3 is being the highest priority.
14624 uint8_t vlan_pri2cos_map_pri;
14625 /* Reserved field. */
14628 * This value controls the priority setting of VLAN PRI to CoS
14629 * mapping based on VLAN Tags of tunneled header.
14630 * This mapping only applies when tunneled headers
14633 * # Each XXX_pri variable shall have a unique priority value
14634 * when it is being specified.
14635 * # When comparing priorities of mappings, higher value
14636 * indicates higher priority.
14637 * For example, a value of 0-3 is returned where 0 is being
14638 * the lowest priority and 3 is being the highest priority.
14640 uint8_t tunnel_pri2cos_map_pri;
14642 * This value controls the priority setting of IP DSCP to CoS
14643 * mapping based on inner IP header of tunneled packets or
14644 * IP header of non-tunneled packets.
14646 * # Each XXX_pri variable shall have a unique priority value
14647 * when it is being specified.
14648 * # When comparing priorities of mappings, higher value
14649 * indicates higher priority.
14650 * For example, a value of 0-3 is returned where 0 is being
14651 * the lowest priority and 3 is being the highest priority.
14653 uint8_t dscp2pri_map_pri;
14655 * This is a 16-bit bit mask that is used to request a
14656 * specific configuration of time stamp capture of PTP messages
14657 * on the receive side of this port.
14658 * This field shall be ignored if the ptp_rx_ts_capture_enable
14659 * flag is not set in this command.
14660 * Otherwise, if bit 'i' is set, then the HWRM is being
14661 * requested to configure the receive side of the port to
14662 * capture the time stamp of every received PTP message
14663 * with messageType field value set to i.
14665 uint16_t rx_ts_capture_ptp_msg_type;
14667 * This is a 16-bit bit mask that is used to request a
14668 * specific configuration of time stamp capture of PTP messages
14669 * on the transmit side of this port.
14670 * This field shall be ignored if the ptp_tx_ts_capture_enable
14671 * flag is not set in this command.
14672 * Otherwise, if bit 'i' is set, then the HWRM is being
14673 * requested to configure the transmit sied of the port to
14674 * capture the time stamp of every transmitted PTP message
14675 * with messageType field value set to i.
14677 uint16_t tx_ts_capture_ptp_msg_type;
14678 /* Configuration of CoS fields. */
14679 uint8_t cos_field_cfg;
14681 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
14684 * This field is used to specify selection of VLAN PRI value
14685 * based on whether one or two VLAN Tags are present in
14686 * the inner packet headers of tunneled packets or
14687 * non-tunneled packets.
14688 * This field is valid only if inner VLAN PRI to CoS mapping
14690 * If VLAN PRI to CoS mapping is not enabled, then this
14691 * field shall be ignored.
14693 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14695 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14698 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14699 * present in the inner packet headers
14701 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14702 (UINT32_C(0x0) << 1)
14704 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14705 * present in the inner packet headers.
14706 * No VLAN PRI shall be selected for this configuration
14707 * if only one VLAN Tag is present in the inner
14710 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14711 (UINT32_C(0x1) << 1)
14713 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14714 * are present in the inner packet headers
14716 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14717 (UINT32_C(0x2) << 1)
14719 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14720 (UINT32_C(0x3) << 1)
14721 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14722 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14724 * This field is used to specify selection of tunnel VLAN
14725 * PRI value based on whether one or two VLAN Tags are
14726 * present in tunnel headers.
14727 * This field is valid only if tunnel VLAN PRI to CoS mapping
14729 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
14730 * field shall be ignored.
14732 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14734 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14737 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14738 * present in the tunnel packet headers
14740 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14741 (UINT32_C(0x0) << 3)
14743 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14744 * present in the tunnel packet headers.
14745 * No tunnel VLAN PRI shall be selected for this
14746 * configuration if only one VLAN Tag is present in
14747 * the tunnel packet headers.
14749 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14750 (UINT32_C(0x1) << 3)
14752 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14753 * are present in the tunnel packet headers
14755 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14756 (UINT32_C(0x2) << 3)
14758 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14759 (UINT32_C(0x3) << 3)
14760 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14761 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14763 * This field shall be used to provide default CoS value
14764 * that has been configured on this port.
14765 * This field is valid only if default CoS mapping
14767 * If default CoS mapping is not enabled, then this
14768 * field shall be ignored.
14770 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14772 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14774 uint8_t unused_0[3];
14776 * This signed field specifies by how much to adjust the frequency
14777 * of sync timer updates (measured in parts per billion).
14779 int32_t ptp_freq_adj_ppb;
14780 uint8_t unused_1[4];
14781 } __attribute__((packed));
14783 /* hwrm_port_mac_cfg_output (size:128b/16B) */
14784 struct hwrm_port_mac_cfg_output {
14785 /* The specific error status for the command. */
14786 uint16_t error_code;
14787 /* The HWRM command request type. */
14789 /* The sequence ID from the original command. */
14791 /* The length of the response data in number of bytes. */
14794 * This is the configured maximum length of Ethernet packet
14795 * payload that is allowed to be received on the port.
14796 * This value does not include the number of bytes used by
14797 * Ethernet header and trailer (CRC).
14801 * This is the configured maximum length of Ethernet packet
14802 * payload that is allowed to be transmitted on the port.
14803 * This value does not include the number of bytes used by
14804 * Ethernet header and trailer (CRC).
14807 /* Current configuration of the IPG value. */
14809 /* Current value of the loopback value. */
14811 /* No loopback is selected. Normal operation. */
14812 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14814 * The HW will be configured with local loopback such that
14815 * host data is sent back to the host without modification.
14817 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14819 * The HW will be configured with remote loopback such that
14820 * port logic will send packets back out the transmitter that
14823 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14824 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
14825 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
14828 * This field is used in Output records to indicate that the output
14829 * is completely written to RAM. This field should be read as '1'
14830 * to indicate that the output has been completely written.
14831 * When writing a command completion or response to an internal processor,
14832 * the order of writes has to be such that this field is written last.
14835 } __attribute__((packed));
14837 /**********************
14838 * hwrm_port_mac_qcfg *
14839 **********************/
14842 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
14843 struct hwrm_port_mac_qcfg_input {
14844 /* The HWRM command request type. */
14847 * The completion ring to send the completion event on. This should
14848 * be the NQ ID returned from the `nq_alloc` HWRM command.
14850 uint16_t cmpl_ring;
14852 * The sequence ID is used by the driver for tracking multiple
14853 * commands. This ID is treated as opaque data by the firmware and
14854 * the value is returned in the `hwrm_resp_hdr` upon completion.
14858 * The target ID of the command:
14859 * * 0x0-0xFFF8 - The function ID
14860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14861 * * 0xFFFD - Reserved for user-space HWRM interface
14864 uint16_t target_id;
14866 * A physical address pointer pointing to a host buffer that the
14867 * command's response data will be written. This can be either a host
14868 * physical address (HPA) or a guest physical address (GPA) and must
14869 * point to a physically contiguous block of memory.
14871 uint64_t resp_addr;
14872 /* Port ID of port that is to be configured. */
14874 uint8_t unused_0[6];
14875 } __attribute__((packed));
14877 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
14878 struct hwrm_port_mac_qcfg_output {
14879 /* The specific error status for the command. */
14880 uint16_t error_code;
14881 /* The HWRM command request type. */
14883 /* The sequence ID from the original command. */
14885 /* The length of the response data in number of bytes. */
14888 * This is the configured maximum length of Ethernet packet
14889 * payload that is allowed to be received on the port.
14890 * This value does not include the number of bytes used by the
14891 * Ethernet header and trailer (CRC).
14895 * This is the configured maximum length of Ethernet packet
14896 * payload that is allowed to be transmitted on the port.
14897 * This value does not include the number of bytes used by the
14898 * Ethernet header and trailer (CRC).
14902 * The minimum IPG that will
14903 * be sent between packets by this port.
14906 /* The loopback setting for the MAC. */
14908 /* No loopback is selected. Normal operation. */
14909 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14911 * The HW will be configured with local loopback such that
14912 * host data is sent back to the host without modification.
14914 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14916 * The HW will be configured with remote loopback such that
14917 * port logic will send packets back out the transmitter that
14920 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14921 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
14922 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
14924 * Priority setting for VLAN PRI to CoS mapping.
14925 * # Each XXX_pri variable shall have a unique priority value
14926 * when it is being used.
14927 * # When comparing priorities of mappings, higher value
14928 * indicates higher priority.
14929 * For example, a value of 0-3 is returned where 0 is being
14930 * the lowest priority and 3 is being the highest priority.
14931 * # If the correspoding CoS mapping is not enabled, then this
14932 * field should be ignored.
14933 * # This value indicates the normalized priority value retained
14936 uint8_t vlan_pri2cos_map_pri;
14938 * In this field, a number of CoS mappings related flags
14939 * are used to indicate configured CoS mappings.
14943 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14946 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14949 * When this bit is set to '1', tunnel VLAN PRI field to
14950 * CoS mapping is enabled.
14952 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14955 * When this bit is set to '1', the IP DSCP to CoS mapping is
14958 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
14961 * When this bit is '1', the Out-Of-Box WoL is enabled on this
14964 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
14966 /* When this bit is '1', PTP is enabled for RX on this port. */
14967 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14969 /* When this bit is '1', PTP is enabled for TX on this port. */
14970 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14973 * Priority setting for tunnel VLAN PRI to CoS mapping.
14974 * # Each XXX_pri variable shall have a unique priority value
14975 * when it is being used.
14976 * # When comparing priorities of mappings, higher value
14977 * indicates higher priority.
14978 * For example, a value of 0-3 is returned where 0 is being
14979 * the lowest priority and 3 is being the highest priority.
14980 * # If the correspoding CoS mapping is not enabled, then this
14981 * field should be ignored.
14982 * # This value indicates the normalized priority value retained
14985 uint8_t tunnel_pri2cos_map_pri;
14987 * Priority setting for DSCP to PRI mapping.
14988 * # Each XXX_pri variable shall have a unique priority value
14989 * when it is being used.
14990 * # When comparing priorities of mappings, higher value
14991 * indicates higher priority.
14992 * For example, a value of 0-3 is returned where 0 is being
14993 * the lowest priority and 3 is being the highest priority.
14994 * # If the correspoding CoS mapping is not enabled, then this
14995 * field should be ignored.
14996 * # This value indicates the normalized priority value retained
14999 uint8_t dscp2pri_map_pri;
15001 * This is a 16-bit bit mask that represents the
15002 * current configuration of time stamp capture of PTP messages
15003 * on the receive side of this port.
15004 * If bit 'i' is set, then the receive side of the port
15005 * is configured to capture the time stamp of every
15006 * received PTP message with messageType field value set
15008 * If all bits are set to 0 (i.e. field value set 0),
15009 * then the receive side of the port is not configured
15010 * to capture timestamp for PTP messages.
15011 * If all bits are set to 1, then the receive side of the
15012 * port is configured to capture timestamp for all PTP
15015 uint16_t rx_ts_capture_ptp_msg_type;
15017 * This is a 16-bit bit mask that represents the
15018 * current configuration of time stamp capture of PTP messages
15019 * on the transmit side of this port.
15020 * If bit 'i' is set, then the transmit side of the port
15021 * is configured to capture the time stamp of every
15022 * received PTP message with messageType field value set
15024 * If all bits are set to 0 (i.e. field value set 0),
15025 * then the transmit side of the port is not configured
15026 * to capture timestamp for PTP messages.
15027 * If all bits are set to 1, then the transmit side of the
15028 * port is configured to capture timestamp for all PTP
15031 uint16_t tx_ts_capture_ptp_msg_type;
15032 /* Configuration of CoS fields. */
15033 uint8_t cos_field_cfg;
15035 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
15038 * This field is used for selecting VLAN PRI value
15039 * based on whether one or two VLAN Tags are present in
15040 * the inner packet headers of tunneled packets or
15041 * non-tunneled packets.
15043 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15045 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15048 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15049 * present in the inner packet headers
15051 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15052 (UINT32_C(0x0) << 1)
15054 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15055 * present in the inner packet headers.
15056 * No VLAN PRI is selected for this configuration
15057 * if only one VLAN Tag is present in the inner
15060 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15061 (UINT32_C(0x1) << 1)
15063 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15064 * are present in the inner packet headers
15066 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15067 (UINT32_C(0x2) << 1)
15069 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15070 (UINT32_C(0x3) << 1)
15071 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15072 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15074 * This field is used for selecting tunnel VLAN PRI value
15075 * based on whether one or two VLAN Tags are present in
15076 * the tunnel headers of tunneled packets. This selection
15077 * does not apply to non-tunneled packets.
15079 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15081 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15084 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15085 * present in the tunnel packet headers
15087 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15088 (UINT32_C(0x0) << 3)
15090 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15091 * present in the tunnel packet headers.
15092 * No VLAN PRI is selected for this configuration
15093 * if only one VLAN Tag is present in the tunnel
15096 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15097 (UINT32_C(0x1) << 3)
15099 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15100 * are present in the tunnel packet headers
15102 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15103 (UINT32_C(0x2) << 3)
15105 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15106 (UINT32_C(0x3) << 3)
15107 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15108 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15110 * This field is used to provide default CoS value that
15111 * has been configured on this port.
15113 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15115 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15118 * This field is used in Output records to indicate that the output
15119 * is completely written to RAM. This field should be read as '1'
15120 * to indicate that the output has been completely written.
15121 * When writing a command completion or response to an internal processor,
15122 * the order of writes has to be such that this field is written last.
15125 } __attribute__((packed));
15127 /**************************
15128 * hwrm_port_mac_ptp_qcfg *
15129 **************************/
15132 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
15133 struct hwrm_port_mac_ptp_qcfg_input {
15134 /* The HWRM command request type. */
15137 * The completion ring to send the completion event on. This should
15138 * be the NQ ID returned from the `nq_alloc` HWRM command.
15140 uint16_t cmpl_ring;
15142 * The sequence ID is used by the driver for tracking multiple
15143 * commands. This ID is treated as opaque data by the firmware and
15144 * the value is returned in the `hwrm_resp_hdr` upon completion.
15148 * The target ID of the command:
15149 * * 0x0-0xFFF8 - The function ID
15150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15151 * * 0xFFFD - Reserved for user-space HWRM interface
15154 uint16_t target_id;
15156 * A physical address pointer pointing to a host buffer that the
15157 * command's response data will be written. This can be either a host
15158 * physical address (HPA) or a guest physical address (GPA) and must
15159 * point to a physically contiguous block of memory.
15161 uint64_t resp_addr;
15162 /* Port ID of port that is being queried. */
15164 uint8_t unused_0[6];
15165 } __attribute__((packed));
15167 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
15168 struct hwrm_port_mac_ptp_qcfg_output {
15169 /* The specific error status for the command. */
15170 uint16_t error_code;
15171 /* The HWRM command request type. */
15173 /* The sequence ID from the original command. */
15175 /* The length of the response data in number of bytes. */
15178 * In this field, a number of PTP related flags
15179 * are used to indicate configured PTP capabilities.
15183 * When this bit is set to '1', the PTP related registers are
15184 * directly accessible by the host.
15186 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
15189 * When this bit is set to '1', the PTP information is accessible
15190 * via HWRM commands.
15192 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
15195 * When this bit is set to '1', the device supports one-step
15198 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
15200 uint8_t unused_0[3];
15201 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
15202 uint32_t rx_ts_reg_off_lower;
15203 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
15204 uint32_t rx_ts_reg_off_upper;
15205 /* Offset of the PTP register for the sequence ID for RX. */
15206 uint32_t rx_ts_reg_off_seq_id;
15207 /* Offset of the first PTP source ID for RX. */
15208 uint32_t rx_ts_reg_off_src_id_0;
15209 /* Offset of the second PTP source ID for RX. */
15210 uint32_t rx_ts_reg_off_src_id_1;
15211 /* Offset of the third PTP source ID for RX. */
15212 uint32_t rx_ts_reg_off_src_id_2;
15213 /* Offset of the domain ID for RX. */
15214 uint32_t rx_ts_reg_off_domain_id;
15215 /* Offset of the PTP FIFO register for RX. */
15216 uint32_t rx_ts_reg_off_fifo;
15217 /* Offset of the PTP advance FIFO register for RX. */
15218 uint32_t rx_ts_reg_off_fifo_adv;
15219 /* PTP timestamp granularity for RX. */
15220 uint32_t rx_ts_reg_off_granularity;
15221 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
15222 uint32_t tx_ts_reg_off_lower;
15223 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
15224 uint32_t tx_ts_reg_off_upper;
15225 /* Offset of the PTP register for the sequence ID for TX. */
15226 uint32_t tx_ts_reg_off_seq_id;
15227 /* Offset of the PTP FIFO register for TX. */
15228 uint32_t tx_ts_reg_off_fifo;
15229 /* PTP timestamp granularity for TX. */
15230 uint32_t tx_ts_reg_off_granularity;
15231 uint8_t unused_1[7];
15233 * This field is used in Output records to indicate that the output
15234 * is completely written to RAM. This field should be read as '1'
15235 * to indicate that the output has been completely written.
15236 * When writing a command completion or response to an internal processor,
15237 * the order of writes has to be such that this field is written last.
15240 } __attribute__((packed));
15242 /* Port Tx Statistics Formats */
15243 /* tx_port_stats (size:3264b/408B) */
15244 struct tx_port_stats {
15245 /* Total Number of 64 Bytes frames transmitted */
15246 uint64_t tx_64b_frames;
15247 /* Total Number of 65-127 Bytes frames transmitted */
15248 uint64_t tx_65b_127b_frames;
15249 /* Total Number of 128-255 Bytes frames transmitted */
15250 uint64_t tx_128b_255b_frames;
15251 /* Total Number of 256-511 Bytes frames transmitted */
15252 uint64_t tx_256b_511b_frames;
15253 /* Total Number of 512-1023 Bytes frames transmitted */
15254 uint64_t tx_512b_1023b_frames;
15255 /* Total Number of 1024-1518 Bytes frames transmitted */
15256 uint64_t tx_1024b_1518b_frames;
15258 * Total Number of each good VLAN (exludes FCS errors)
15259 * frame transmitted which is 1519 to 1522 bytes in length
15260 * inclusive (excluding framing bits but including FCS bytes).
15262 uint64_t tx_good_vlan_frames;
15263 /* Total Number of 1519-2047 Bytes frames transmitted */
15264 uint64_t tx_1519b_2047b_frames;
15265 /* Total Number of 2048-4095 Bytes frames transmitted */
15266 uint64_t tx_2048b_4095b_frames;
15267 /* Total Number of 4096-9216 Bytes frames transmitted */
15268 uint64_t tx_4096b_9216b_frames;
15269 /* Total Number of 9217-16383 Bytes frames transmitted */
15270 uint64_t tx_9217b_16383b_frames;
15271 /* Total Number of good frames transmitted */
15272 uint64_t tx_good_frames;
15273 /* Total Number of frames transmitted */
15274 uint64_t tx_total_frames;
15275 /* Total number of unicast frames transmitted */
15276 uint64_t tx_ucast_frames;
15277 /* Total number of multicast frames transmitted */
15278 uint64_t tx_mcast_frames;
15279 /* Total number of broadcast frames transmitted */
15280 uint64_t tx_bcast_frames;
15281 /* Total number of PAUSE control frames transmitted */
15282 uint64_t tx_pause_frames;
15284 * Total number of PFC/per-priority PAUSE
15285 * control frames transmitted
15287 uint64_t tx_pfc_frames;
15288 /* Total number of jabber frames transmitted */
15289 uint64_t tx_jabber_frames;
15290 /* Total number of frames transmitted with FCS error */
15291 uint64_t tx_fcs_err_frames;
15292 /* Total number of control frames transmitted */
15293 uint64_t tx_control_frames;
15294 /* Total number of over-sized frames transmitted */
15295 uint64_t tx_oversz_frames;
15296 /* Total number of frames with single deferral */
15297 uint64_t tx_single_dfrl_frames;
15298 /* Total number of frames with multiple deferrals */
15299 uint64_t tx_multi_dfrl_frames;
15300 /* Total number of frames with single collision */
15301 uint64_t tx_single_coll_frames;
15302 /* Total number of frames with multiple collisions */
15303 uint64_t tx_multi_coll_frames;
15304 /* Total number of frames with late collisions */
15305 uint64_t tx_late_coll_frames;
15306 /* Total number of frames with excessive collisions */
15307 uint64_t tx_excessive_coll_frames;
15308 /* Total number of fragmented frames transmitted */
15309 uint64_t tx_frag_frames;
15310 /* Total number of transmit errors */
15312 /* Total number of single VLAN tagged frames transmitted */
15313 uint64_t tx_tagged_frames;
15314 /* Total number of double VLAN tagged frames transmitted */
15315 uint64_t tx_dbl_tagged_frames;
15316 /* Total number of runt frames transmitted */
15317 uint64_t tx_runt_frames;
15318 /* Total number of TX FIFO under runs */
15319 uint64_t tx_fifo_underruns;
15321 * Total number of PFC frames with PFC enabled bit for
15322 * Pri 0 transmitted
15324 uint64_t tx_pfc_ena_frames_pri0;
15326 * Total number of PFC frames with PFC enabled bit for
15327 * Pri 1 transmitted
15329 uint64_t tx_pfc_ena_frames_pri1;
15331 * Total number of PFC frames with PFC enabled bit for
15332 * Pri 2 transmitted
15334 uint64_t tx_pfc_ena_frames_pri2;
15336 * Total number of PFC frames with PFC enabled bit for
15337 * Pri 3 transmitted
15339 uint64_t tx_pfc_ena_frames_pri3;
15341 * Total number of PFC frames with PFC enabled bit for
15342 * Pri 4 transmitted
15344 uint64_t tx_pfc_ena_frames_pri4;
15346 * Total number of PFC frames with PFC enabled bit for
15347 * Pri 5 transmitted
15349 uint64_t tx_pfc_ena_frames_pri5;
15351 * Total number of PFC frames with PFC enabled bit for
15352 * Pri 6 transmitted
15354 uint64_t tx_pfc_ena_frames_pri6;
15356 * Total number of PFC frames with PFC enabled bit for
15357 * Pri 7 transmitted
15359 uint64_t tx_pfc_ena_frames_pri7;
15360 /* Total number of EEE LPI Events on TX */
15361 uint64_t tx_eee_lpi_events;
15362 /* EEE LPI Duration Counter on TX */
15363 uint64_t tx_eee_lpi_duration;
15365 * Total number of Link Level Flow Control (LLFC) messages
15368 uint64_t tx_llfc_logical_msgs;
15369 /* Total number of HCFC messages transmitted */
15370 uint64_t tx_hcfc_msgs;
15371 /* Total number of TX collisions */
15372 uint64_t tx_total_collisions;
15373 /* Total number of transmitted bytes */
15375 /* Total number of end-to-end HOL frames */
15376 uint64_t tx_xthol_frames;
15377 /* Total Tx Drops per Port reported by STATS block */
15378 uint64_t tx_stat_discard;
15379 /* Total Tx Error Drops per Port reported by STATS block */
15380 uint64_t tx_stat_error;
15381 } __attribute__((packed));
15383 /* Port Rx Statistics Formats */
15384 /* rx_port_stats (size:4224b/528B) */
15385 struct rx_port_stats {
15386 /* Total Number of 64 Bytes frames received */
15387 uint64_t rx_64b_frames;
15388 /* Total Number of 65-127 Bytes frames received */
15389 uint64_t rx_65b_127b_frames;
15390 /* Total Number of 128-255 Bytes frames received */
15391 uint64_t rx_128b_255b_frames;
15392 /* Total Number of 256-511 Bytes frames received */
15393 uint64_t rx_256b_511b_frames;
15394 /* Total Number of 512-1023 Bytes frames received */
15395 uint64_t rx_512b_1023b_frames;
15396 /* Total Number of 1024-1518 Bytes frames received */
15397 uint64_t rx_1024b_1518b_frames;
15399 * Total Number of each good VLAN (exludes FCS errors)
15400 * frame received which is 1519 to 1522 bytes in length
15401 * inclusive (excluding framing bits but including FCS bytes).
15403 uint64_t rx_good_vlan_frames;
15404 /* Total Number of 1519-2047 Bytes frames received */
15405 uint64_t rx_1519b_2047b_frames;
15406 /* Total Number of 2048-4095 Bytes frames received */
15407 uint64_t rx_2048b_4095b_frames;
15408 /* Total Number of 4096-9216 Bytes frames received */
15409 uint64_t rx_4096b_9216b_frames;
15410 /* Total Number of 9217-16383 Bytes frames received */
15411 uint64_t rx_9217b_16383b_frames;
15412 /* Total number of frames received */
15413 uint64_t rx_total_frames;
15414 /* Total number of unicast frames received */
15415 uint64_t rx_ucast_frames;
15416 /* Total number of multicast frames received */
15417 uint64_t rx_mcast_frames;
15418 /* Total number of broadcast frames received */
15419 uint64_t rx_bcast_frames;
15420 /* Total number of received frames with FCS error */
15421 uint64_t rx_fcs_err_frames;
15422 /* Total number of control frames received */
15423 uint64_t rx_ctrl_frames;
15424 /* Total number of PAUSE frames received */
15425 uint64_t rx_pause_frames;
15426 /* Total number of PFC frames received */
15427 uint64_t rx_pfc_frames;
15429 * Total number of frames received with an unsupported
15432 uint64_t rx_unsupported_opcode_frames;
15434 * Total number of frames received with an unsupported
15435 * DA for pause and PFC
15437 uint64_t rx_unsupported_da_pausepfc_frames;
15438 /* Total number of frames received with an unsupported SA */
15439 uint64_t rx_wrong_sa_frames;
15440 /* Total number of received packets with alignment error */
15441 uint64_t rx_align_err_frames;
15442 /* Total number of received frames with out-of-range length */
15443 uint64_t rx_oor_len_frames;
15444 /* Total number of received frames with error termination */
15445 uint64_t rx_code_err_frames;
15447 * Total number of received frames with a false carrier is
15448 * detected during idle, as defined by RX_ER samples active
15449 * and RXD is 0xE. The event is reported along with the
15450 * statistics generated on the next received frame. Only
15451 * one false carrier condition can be detected and logged
15454 * Carrier event, valid for 10M/100M speed modes only.
15456 uint64_t rx_false_carrier_frames;
15457 /* Total number of over-sized frames received */
15458 uint64_t rx_ovrsz_frames;
15459 /* Total number of jabber packets received */
15460 uint64_t rx_jbr_frames;
15461 /* Total number of received frames with MTU error */
15462 uint64_t rx_mtu_err_frames;
15463 /* Total number of received frames with CRC match */
15464 uint64_t rx_match_crc_frames;
15465 /* Total number of frames received promiscuously */
15466 uint64_t rx_promiscuous_frames;
15468 * Total number of received frames with one or two VLAN
15471 uint64_t rx_tagged_frames;
15472 /* Total number of received frames with two VLAN tags */
15473 uint64_t rx_double_tagged_frames;
15474 /* Total number of truncated frames received */
15475 uint64_t rx_trunc_frames;
15476 /* Total number of good frames (without errors) received */
15477 uint64_t rx_good_frames;
15479 * Total number of received PFC frames with transition from
15480 * XON to XOFF on Pri 0
15482 uint64_t rx_pfc_xon2xoff_frames_pri0;
15484 * Total number of received PFC frames with transition from
15485 * XON to XOFF on Pri 1
15487 uint64_t rx_pfc_xon2xoff_frames_pri1;
15489 * Total number of received PFC frames with transition from
15490 * XON to XOFF on Pri 2
15492 uint64_t rx_pfc_xon2xoff_frames_pri2;
15494 * Total number of received PFC frames with transition from
15495 * XON to XOFF on Pri 3
15497 uint64_t rx_pfc_xon2xoff_frames_pri3;
15499 * Total number of received PFC frames with transition from
15500 * XON to XOFF on Pri 4
15502 uint64_t rx_pfc_xon2xoff_frames_pri4;
15504 * Total number of received PFC frames with transition from
15505 * XON to XOFF on Pri 5
15507 uint64_t rx_pfc_xon2xoff_frames_pri5;
15509 * Total number of received PFC frames with transition from
15510 * XON to XOFF on Pri 6
15512 uint64_t rx_pfc_xon2xoff_frames_pri6;
15514 * Total number of received PFC frames with transition from
15515 * XON to XOFF on Pri 7
15517 uint64_t rx_pfc_xon2xoff_frames_pri7;
15519 * Total number of received PFC frames with PFC enabled
15522 uint64_t rx_pfc_ena_frames_pri0;
15524 * Total number of received PFC frames with PFC enabled
15527 uint64_t rx_pfc_ena_frames_pri1;
15529 * Total number of received PFC frames with PFC enabled
15532 uint64_t rx_pfc_ena_frames_pri2;
15534 * Total number of received PFC frames with PFC enabled
15537 uint64_t rx_pfc_ena_frames_pri3;
15539 * Total number of received PFC frames with PFC enabled
15542 uint64_t rx_pfc_ena_frames_pri4;
15544 * Total number of received PFC frames with PFC enabled
15547 uint64_t rx_pfc_ena_frames_pri5;
15549 * Total number of received PFC frames with PFC enabled
15552 uint64_t rx_pfc_ena_frames_pri6;
15554 * Total number of received PFC frames with PFC enabled
15557 uint64_t rx_pfc_ena_frames_pri7;
15558 /* Total Number of frames received with SCH CRC error */
15559 uint64_t rx_sch_crc_err_frames;
15560 /* Total Number of under-sized frames received */
15561 uint64_t rx_undrsz_frames;
15562 /* Total Number of fragmented frames received */
15563 uint64_t rx_frag_frames;
15564 /* Total number of RX EEE LPI Events */
15565 uint64_t rx_eee_lpi_events;
15566 /* EEE LPI Duration Counter on RX */
15567 uint64_t rx_eee_lpi_duration;
15569 * Total number of physical type Link Level Flow Control
15570 * (LLFC) messages received
15572 uint64_t rx_llfc_physical_msgs;
15574 * Total number of logical type Link Level Flow Control
15575 * (LLFC) messages received
15577 uint64_t rx_llfc_logical_msgs;
15579 * Total number of logical type Link Level Flow Control
15580 * (LLFC) messages received with CRC error
15582 uint64_t rx_llfc_msgs_with_crc_err;
15583 /* Total number of HCFC messages received */
15584 uint64_t rx_hcfc_msgs;
15585 /* Total number of HCFC messages received with CRC error */
15586 uint64_t rx_hcfc_msgs_with_crc_err;
15587 /* Total number of received bytes */
15589 /* Total number of bytes received in runt frames */
15590 uint64_t rx_runt_bytes;
15591 /* Total number of runt frames received */
15592 uint64_t rx_runt_frames;
15593 /* Total Rx Discards per Port reported by STATS block */
15594 uint64_t rx_stat_discard;
15595 uint64_t rx_stat_err;
15596 } __attribute__((packed));
15598 /********************
15599 * hwrm_port_qstats *
15600 ********************/
15603 /* hwrm_port_qstats_input (size:320b/40B) */
15604 struct hwrm_port_qstats_input {
15605 /* The HWRM command request type. */
15608 * The completion ring to send the completion event on. This should
15609 * be the NQ ID returned from the `nq_alloc` HWRM command.
15611 uint16_t cmpl_ring;
15613 * The sequence ID is used by the driver for tracking multiple
15614 * commands. This ID is treated as opaque data by the firmware and
15615 * the value is returned in the `hwrm_resp_hdr` upon completion.
15619 * The target ID of the command:
15620 * * 0x0-0xFFF8 - The function ID
15621 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15622 * * 0xFFFD - Reserved for user-space HWRM interface
15625 uint16_t target_id;
15627 * A physical address pointer pointing to a host buffer that the
15628 * command's response data will be written. This can be either a host
15629 * physical address (HPA) or a guest physical address (GPA) and must
15630 * point to a physically contiguous block of memory.
15632 uint64_t resp_addr;
15633 /* Port ID of port that is being queried. */
15635 uint8_t unused_0[6];
15637 * This is the host address where
15638 * Tx port statistics will be stored
15640 uint64_t tx_stat_host_addr;
15642 * This is the host address where
15643 * Rx port statistics will be stored
15645 uint64_t rx_stat_host_addr;
15646 } __attribute__((packed));
15648 /* hwrm_port_qstats_output (size:128b/16B) */
15649 struct hwrm_port_qstats_output {
15650 /* The specific error status for the command. */
15651 uint16_t error_code;
15652 /* The HWRM command request type. */
15654 /* The sequence ID from the original command. */
15656 /* The length of the response data in number of bytes. */
15658 /* The size of TX port statistics block in bytes. */
15659 uint16_t tx_stat_size;
15660 /* The size of RX port statistics block in bytes. */
15661 uint16_t rx_stat_size;
15662 uint8_t unused_0[3];
15664 * This field is used in Output records to indicate that the output
15665 * is completely written to RAM. This field should be read as '1'
15666 * to indicate that the output has been completely written.
15667 * When writing a command completion or response to an internal processor,
15668 * the order of writes has to be such that this field is written last.
15671 } __attribute__((packed));
15673 /* Port Tx Statistics extended Formats */
15674 /* tx_port_stats_ext (size:2048b/256B) */
15675 struct tx_port_stats_ext {
15676 /* Total number of tx bytes count on cos queue 0 */
15677 uint64_t tx_bytes_cos0;
15678 /* Total number of tx bytes count on cos queue 1 */
15679 uint64_t tx_bytes_cos1;
15680 /* Total number of tx bytes count on cos queue 2 */
15681 uint64_t tx_bytes_cos2;
15682 /* Total number of tx bytes count on cos queue 3 */
15683 uint64_t tx_bytes_cos3;
15684 /* Total number of tx bytes count on cos queue 4 */
15685 uint64_t tx_bytes_cos4;
15686 /* Total number of tx bytes count on cos queue 5 */
15687 uint64_t tx_bytes_cos5;
15688 /* Total number of tx bytes count on cos queue 6 */
15689 uint64_t tx_bytes_cos6;
15690 /* Total number of tx bytes count on cos queue 7 */
15691 uint64_t tx_bytes_cos7;
15692 /* Total number of tx packets count on cos queue 0 */
15693 uint64_t tx_packets_cos0;
15694 /* Total number of tx packets count on cos queue 1 */
15695 uint64_t tx_packets_cos1;
15696 /* Total number of tx packets count on cos queue 2 */
15697 uint64_t tx_packets_cos2;
15698 /* Total number of tx packets count on cos queue 3 */
15699 uint64_t tx_packets_cos3;
15700 /* Total number of tx packets count on cos queue 4 */
15701 uint64_t tx_packets_cos4;
15702 /* Total number of tx packets count on cos queue 5 */
15703 uint64_t tx_packets_cos5;
15704 /* Total number of tx packets count on cos queue 6 */
15705 uint64_t tx_packets_cos6;
15706 /* Total number of tx packets count on cos queue 7 */
15707 uint64_t tx_packets_cos7;
15708 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15709 uint64_t pfc_pri0_tx_duration_us;
15710 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15711 uint64_t pfc_pri0_tx_transitions;
15712 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15713 uint64_t pfc_pri1_tx_duration_us;
15714 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15715 uint64_t pfc_pri1_tx_transitions;
15716 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15717 uint64_t pfc_pri2_tx_duration_us;
15718 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15719 uint64_t pfc_pri2_tx_transitions;
15720 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15721 uint64_t pfc_pri3_tx_duration_us;
15722 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15723 uint64_t pfc_pri3_tx_transitions;
15724 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15725 uint64_t pfc_pri4_tx_duration_us;
15726 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15727 uint64_t pfc_pri4_tx_transitions;
15728 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15729 uint64_t pfc_pri5_tx_duration_us;
15730 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15731 uint64_t pfc_pri5_tx_transitions;
15732 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15733 uint64_t pfc_pri6_tx_duration_us;
15734 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15735 uint64_t pfc_pri6_tx_transitions;
15736 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15737 uint64_t pfc_pri7_tx_duration_us;
15738 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15739 uint64_t pfc_pri7_tx_transitions;
15740 } __attribute__((packed));
15742 /* Port Rx Statistics extended Formats */
15743 /* rx_port_stats_ext (size:3648b/456B) */
15744 struct rx_port_stats_ext {
15745 /* Number of times link state changed to down */
15746 uint64_t link_down_events;
15747 /* Number of times the idle rings with pause bit are found */
15748 uint64_t continuous_pause_events;
15749 /* Number of times the active rings pause bit resumed back */
15750 uint64_t resume_pause_events;
15751 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
15752 uint64_t continuous_roce_pause_events;
15753 /* Number of times, the ROCE cos queue PFC is enabled back */
15754 uint64_t resume_roce_pause_events;
15755 /* Total number of rx bytes count on cos queue 0 */
15756 uint64_t rx_bytes_cos0;
15757 /* Total number of rx bytes count on cos queue 1 */
15758 uint64_t rx_bytes_cos1;
15759 /* Total number of rx bytes count on cos queue 2 */
15760 uint64_t rx_bytes_cos2;
15761 /* Total number of rx bytes count on cos queue 3 */
15762 uint64_t rx_bytes_cos3;
15763 /* Total number of rx bytes count on cos queue 4 */
15764 uint64_t rx_bytes_cos4;
15765 /* Total number of rx bytes count on cos queue 5 */
15766 uint64_t rx_bytes_cos5;
15767 /* Total number of rx bytes count on cos queue 6 */
15768 uint64_t rx_bytes_cos6;
15769 /* Total number of rx bytes count on cos queue 7 */
15770 uint64_t rx_bytes_cos7;
15771 /* Total number of rx packets count on cos queue 0 */
15772 uint64_t rx_packets_cos0;
15773 /* Total number of rx packets count on cos queue 1 */
15774 uint64_t rx_packets_cos1;
15775 /* Total number of rx packets count on cos queue 2 */
15776 uint64_t rx_packets_cos2;
15777 /* Total number of rx packets count on cos queue 3 */
15778 uint64_t rx_packets_cos3;
15779 /* Total number of rx packets count on cos queue 4 */
15780 uint64_t rx_packets_cos4;
15781 /* Total number of rx packets count on cos queue 5 */
15782 uint64_t rx_packets_cos5;
15783 /* Total number of rx packets count on cos queue 6 */
15784 uint64_t rx_packets_cos6;
15785 /* Total number of rx packets count on cos queue 7 */
15786 uint64_t rx_packets_cos7;
15787 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15788 uint64_t pfc_pri0_rx_duration_us;
15789 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15790 uint64_t pfc_pri0_rx_transitions;
15791 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15792 uint64_t pfc_pri1_rx_duration_us;
15793 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15794 uint64_t pfc_pri1_rx_transitions;
15795 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15796 uint64_t pfc_pri2_rx_duration_us;
15797 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15798 uint64_t pfc_pri2_rx_transitions;
15799 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15800 uint64_t pfc_pri3_rx_duration_us;
15801 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15802 uint64_t pfc_pri3_rx_transitions;
15803 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15804 uint64_t pfc_pri4_rx_duration_us;
15805 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15806 uint64_t pfc_pri4_rx_transitions;
15807 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15808 uint64_t pfc_pri5_rx_duration_us;
15809 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15810 uint64_t pfc_pri5_rx_transitions;
15811 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15812 uint64_t pfc_pri6_rx_duration_us;
15813 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15814 uint64_t pfc_pri6_rx_transitions;
15815 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15816 uint64_t pfc_pri7_rx_duration_us;
15817 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15818 uint64_t pfc_pri7_rx_transitions;
15819 /* Total number of received bits */
15821 /* The number of events where the port receive buffer was over 85% full */
15822 uint64_t rx_buffer_passed_threshold;
15824 * The number of symbol errors that wasn't corrected by FEC correction
15827 uint64_t rx_pcs_symbol_err;
15828 /* The number of corrected bits on the port according to active FEC */
15829 uint64_t rx_corrected_bits;
15830 /* Total number of rx discard bytes count on cos queue 0 */
15831 uint64_t rx_discard_bytes_cos0;
15832 /* Total number of rx discard bytes count on cos queue 1 */
15833 uint64_t rx_discard_bytes_cos1;
15834 /* Total number of rx discard bytes count on cos queue 2 */
15835 uint64_t rx_discard_bytes_cos2;
15836 /* Total number of rx discard bytes count on cos queue 3 */
15837 uint64_t rx_discard_bytes_cos3;
15838 /* Total number of rx discard bytes count on cos queue 4 */
15839 uint64_t rx_discard_bytes_cos4;
15840 /* Total number of rx discard bytes count on cos queue 5 */
15841 uint64_t rx_discard_bytes_cos5;
15842 /* Total number of rx discard bytes count on cos queue 6 */
15843 uint64_t rx_discard_bytes_cos6;
15844 /* Total number of rx discard bytes count on cos queue 7 */
15845 uint64_t rx_discard_bytes_cos7;
15846 /* Total number of rx discard packets count on cos queue 0 */
15847 uint64_t rx_discard_packets_cos0;
15848 /* Total number of rx discard packets count on cos queue 1 */
15849 uint64_t rx_discard_packets_cos1;
15850 /* Total number of rx discard packets count on cos queue 2 */
15851 uint64_t rx_discard_packets_cos2;
15852 /* Total number of rx discard packets count on cos queue 3 */
15853 uint64_t rx_discard_packets_cos3;
15854 /* Total number of rx discard packets count on cos queue 4 */
15855 uint64_t rx_discard_packets_cos4;
15856 /* Total number of rx discard packets count on cos queue 5 */
15857 uint64_t rx_discard_packets_cos5;
15858 /* Total number of rx discard packets count on cos queue 6 */
15859 uint64_t rx_discard_packets_cos6;
15860 /* Total number of rx discard packets count on cos queue 7 */
15861 uint64_t rx_discard_packets_cos7;
15862 } __attribute__((packed));
15864 /************************
15865 * hwrm_port_qstats_ext *
15866 ************************/
15869 /* hwrm_port_qstats_ext_input (size:320b/40B) */
15870 struct hwrm_port_qstats_ext_input {
15871 /* The HWRM command request type. */
15874 * The completion ring to send the completion event on. This should
15875 * be the NQ ID returned from the `nq_alloc` HWRM command.
15877 uint16_t cmpl_ring;
15879 * The sequence ID is used by the driver for tracking multiple
15880 * commands. This ID is treated as opaque data by the firmware and
15881 * the value is returned in the `hwrm_resp_hdr` upon completion.
15885 * The target ID of the command:
15886 * * 0x0-0xFFF8 - The function ID
15887 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15888 * * 0xFFFD - Reserved for user-space HWRM interface
15891 uint16_t target_id;
15893 * A physical address pointer pointing to a host buffer that the
15894 * command's response data will be written. This can be either a host
15895 * physical address (HPA) or a guest physical address (GPA) and must
15896 * point to a physically contiguous block of memory.
15898 uint64_t resp_addr;
15899 /* Port ID of port that is being queried. */
15902 * The size of TX port extended
15903 * statistics block in bytes.
15905 uint16_t tx_stat_size;
15907 * The size of RX port extended
15908 * statistics block in bytes
15910 uint16_t rx_stat_size;
15911 uint8_t unused_0[2];
15913 * This is the host address where
15914 * Tx port statistics will be stored
15916 uint64_t tx_stat_host_addr;
15918 * This is the host address where
15919 * Rx port statistics will be stored
15921 uint64_t rx_stat_host_addr;
15922 } __attribute__((packed));
15924 /* hwrm_port_qstats_ext_output (size:128b/16B) */
15925 struct hwrm_port_qstats_ext_output {
15926 /* The specific error status for the command. */
15927 uint16_t error_code;
15928 /* The HWRM command request type. */
15930 /* The sequence ID from the original command. */
15932 /* The length of the response data in number of bytes. */
15934 /* The size of TX port statistics block in bytes. */
15935 uint16_t tx_stat_size;
15936 /* The size of RX port statistics block in bytes. */
15937 uint16_t rx_stat_size;
15938 /* Total number of active cos queues available. */
15939 uint16_t total_active_cos_queues;
15942 * If set to 1, then this field indicates that clear
15943 * roce specific counters is supported.
15945 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
15948 * This field is used in Output records to indicate that the output
15949 * is completely written to RAM. This field should be read as '1'
15950 * to indicate that the output has been completely written.
15951 * When writing a command completion or response to an internal processor,
15952 * the order of writes has to be such that this field is written last.
15955 } __attribute__((packed));
15957 /*************************
15958 * hwrm_port_lpbk_qstats *
15959 *************************/
15962 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
15963 struct hwrm_port_lpbk_qstats_input {
15964 /* The HWRM command request type. */
15967 * The completion ring to send the completion event on. This should
15968 * be the NQ ID returned from the `nq_alloc` HWRM command.
15970 uint16_t cmpl_ring;
15972 * The sequence ID is used by the driver for tracking multiple
15973 * commands. This ID is treated as opaque data by the firmware and
15974 * the value is returned in the `hwrm_resp_hdr` upon completion.
15978 * The target ID of the command:
15979 * * 0x0-0xFFF8 - The function ID
15980 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15981 * * 0xFFFD - Reserved for user-space HWRM interface
15984 uint16_t target_id;
15986 * A physical address pointer pointing to a host buffer that the
15987 * command's response data will be written. This can be either a host
15988 * physical address (HPA) or a guest physical address (GPA) and must
15989 * point to a physically contiguous block of memory.
15991 uint64_t resp_addr;
15992 } __attribute__((packed));
15994 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
15995 struct hwrm_port_lpbk_qstats_output {
15996 /* The specific error status for the command. */
15997 uint16_t error_code;
15998 /* The HWRM command request type. */
16000 /* The sequence ID from the original command. */
16002 /* The length of the response data in number of bytes. */
16004 /* Number of transmitted unicast frames */
16005 uint64_t lpbk_ucast_frames;
16006 /* Number of transmitted multicast frames */
16007 uint64_t lpbk_mcast_frames;
16008 /* Number of transmitted broadcast frames */
16009 uint64_t lpbk_bcast_frames;
16010 /* Number of transmitted bytes for unicast traffic */
16011 uint64_t lpbk_ucast_bytes;
16012 /* Number of transmitted bytes for multicast traffic */
16013 uint64_t lpbk_mcast_bytes;
16014 /* Number of transmitted bytes for broadcast traffic */
16015 uint64_t lpbk_bcast_bytes;
16016 /* Total Tx Drops for loopback traffic reported by STATS block */
16017 uint64_t tx_stat_discard;
16018 /* Total Tx Error Drops for loopback traffic reported by STATS block */
16019 uint64_t tx_stat_error;
16020 /* Total Rx Drops for loopback traffic reported by STATS block */
16021 uint64_t rx_stat_discard;
16022 /* Total Rx Error Drops for loopback traffic reported by STATS block */
16023 uint64_t rx_stat_error;
16024 uint8_t unused_0[7];
16026 * This field is used in Output records to indicate that the output
16027 * is completely written to RAM. This field should be read as '1'
16028 * to indicate that the output has been completely written.
16029 * When writing a command completion or response to an internal processor,
16030 * the order of writes has to be such that this field is written last.
16033 } __attribute__((packed));
16035 /***********************
16036 * hwrm_port_clr_stats *
16037 ***********************/
16040 /* hwrm_port_clr_stats_input (size:192b/24B) */
16041 struct hwrm_port_clr_stats_input {
16042 /* The HWRM command request type. */
16045 * The completion ring to send the completion event on. This should
16046 * be the NQ ID returned from the `nq_alloc` HWRM command.
16048 uint16_t cmpl_ring;
16050 * The sequence ID is used by the driver for tracking multiple
16051 * commands. This ID is treated as opaque data by the firmware and
16052 * the value is returned in the `hwrm_resp_hdr` upon completion.
16056 * The target ID of the command:
16057 * * 0x0-0xFFF8 - The function ID
16058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16059 * * 0xFFFD - Reserved for user-space HWRM interface
16062 uint16_t target_id;
16064 * A physical address pointer pointing to a host buffer that the
16065 * command's response data will be written. This can be either a host
16066 * physical address (HPA) or a guest physical address (GPA) and must
16067 * point to a physically contiguous block of memory.
16069 uint64_t resp_addr;
16070 /* Port ID of port that is being queried. */
16074 * If set to 1, then this field indicates clear the following RoCE
16075 * specific counters.
16076 * RoCE associated TX/RX cos counters
16077 * CNP associated TX/RX cos counters
16078 * RoCE/CNP specific TX/RX flow counters
16079 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
16080 * This flag is honored only when RoCE is enabled on that port.
16082 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
16083 uint8_t unused_0[5];
16084 } __attribute__((packed));
16086 /* hwrm_port_clr_stats_output (size:128b/16B) */
16087 struct hwrm_port_clr_stats_output {
16088 /* The specific error status for the command. */
16089 uint16_t error_code;
16090 /* The HWRM command request type. */
16092 /* The sequence ID from the original command. */
16094 /* The length of the response data in number of bytes. */
16096 uint8_t unused_0[7];
16098 * This field is used in Output records to indicate that the output
16099 * is completely written to RAM. This field should be read as '1'
16100 * to indicate that the output has been completely written.
16101 * When writing a command completion or response to an internal processor,
16102 * the order of writes has to be such that this field is written last.
16105 } __attribute__((packed));
16107 /***********************
16108 * hwrm_port_phy_qcaps *
16109 ***********************/
16112 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
16113 struct hwrm_port_phy_qcaps_input {
16114 /* The HWRM command request type. */
16117 * The completion ring to send the completion event on. This should
16118 * be the NQ ID returned from the `nq_alloc` HWRM command.
16120 uint16_t cmpl_ring;
16122 * The sequence ID is used by the driver for tracking multiple
16123 * commands. This ID is treated as opaque data by the firmware and
16124 * the value is returned in the `hwrm_resp_hdr` upon completion.
16128 * The target ID of the command:
16129 * * 0x0-0xFFF8 - The function ID
16130 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16131 * * 0xFFFD - Reserved for user-space HWRM interface
16134 uint16_t target_id;
16136 * A physical address pointer pointing to a host buffer that the
16137 * command's response data will be written. This can be either a host
16138 * physical address (HPA) or a guest physical address (GPA) and must
16139 * point to a physically contiguous block of memory.
16141 uint64_t resp_addr;
16142 /* Port ID of port that is being queried. */
16144 uint8_t unused_0[6];
16145 } __attribute__((packed));
16147 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
16148 struct hwrm_port_phy_qcaps_output {
16149 /* The specific error status for the command. */
16150 uint16_t error_code;
16151 /* The HWRM command request type. */
16153 /* The sequence ID from the original command. */
16155 /* The length of the response data in number of bytes. */
16157 /* PHY capability flags */
16160 * If set to 1, then this field indicates that the
16161 * link is capable of supporting EEE.
16163 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
16166 * If set to 1, then this field indicates that the
16167 * PHY is capable of supporting external loopback.
16169 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
16172 * Reserved field. The HWRM shall set this field to 0.
16173 * An HWRM client shall ignore this field.
16175 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
16177 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
16178 /* Number of front panel ports for this device. */
16180 /* Not supported or unknown */
16181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
16182 /* single port device */
16183 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
16184 /* 2-port device */
16185 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
16186 /* 3-port device */
16187 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
16188 /* 4-port device */
16189 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
16190 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
16191 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
16193 * This is a bit mask to indicate what speeds are supported
16194 * as forced speeds on this link.
16195 * For each speed that can be forced on this link, the
16196 * corresponding mask bit shall be set to '1'.
16198 uint16_t supported_speeds_force_mode;
16199 /* 100Mb link speed (Half-duplex) */
16200 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
16202 /* 100Mb link speed (Full-duplex) */
16203 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
16205 /* 1Gb link speed (Half-duplex) */
16206 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
16208 /* 1Gb link speed (Full-duplex) */
16209 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
16211 /* 2Gb link speed */
16212 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
16214 /* 25Gb link speed */
16215 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
16217 /* 10Gb link speed */
16218 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
16220 /* 20Gb link speed */
16221 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
16223 /* 25Gb link speed */
16224 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
16226 /* 40Gb link speed */
16227 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
16229 /* 50Gb link speed */
16230 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
16232 /* 100Gb link speed */
16233 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
16235 /* 10Mb link speed (Half-duplex) */
16236 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
16238 /* 10Mb link speed (Full-duplex) */
16239 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
16241 /* 200Gb link speed */
16242 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
16245 * This is a bit mask to indicate what speeds are supported
16246 * for autonegotiation on this link.
16247 * For each speed that can be autonegotiated on this link, the
16248 * corresponding mask bit shall be set to '1'.
16250 uint16_t supported_speeds_auto_mode;
16251 /* 100Mb link speed (Half-duplex) */
16252 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
16254 /* 100Mb link speed (Full-duplex) */
16255 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
16257 /* 1Gb link speed (Half-duplex) */
16258 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
16260 /* 1Gb link speed (Full-duplex) */
16261 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
16263 /* 2Gb link speed */
16264 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
16266 /* 25Gb link speed */
16267 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
16269 /* 10Gb link speed */
16270 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
16272 /* 20Gb link speed */
16273 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
16275 /* 25Gb link speed */
16276 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
16278 /* 40Gb link speed */
16279 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
16281 /* 50Gb link speed */
16282 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
16284 /* 100Gb link speed */
16285 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
16287 /* 10Mb link speed (Half-duplex) */
16288 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
16290 /* 10Mb link speed (Full-duplex) */
16291 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
16293 /* 200Gb link speed */
16294 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
16297 * This is a bit mask to indicate what speeds are supported
16298 * for EEE on this link.
16299 * For each speed that can be autonegotiated when EEE is enabled
16300 * on this link, the corresponding mask bit shall be set to '1'.
16301 * This field is only valid when the eee_suppotred is set to '1'.
16303 uint16_t supported_speeds_eee_mode;
16305 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
16307 /* 100Mb link speed (Full-duplex) */
16308 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
16311 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
16313 /* 1Gb link speed (Full-duplex) */
16314 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
16317 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
16320 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
16322 /* 10Gb link speed */
16323 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
16325 uint32_t tx_lpi_timer_low;
16327 * The lowest value of TX LPI timer that can be set on this link
16328 * when EEE is enabled. This value is in microseconds.
16329 * This field is valid only when_eee_supported is set to '1'.
16331 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
16333 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
16335 * Reserved field. The HWRM shall set this field to 0.
16336 * An HWRM client shall ignore this field.
16338 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
16339 UINT32_C(0xff000000)
16340 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
16341 uint32_t valid_tx_lpi_timer_high;
16343 * The highest value of TX LPI timer that can be set on this link
16344 * when EEE is enabled. This value is in microseconds.
16345 * This field is valid only when_eee_supported is set to '1'.
16347 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
16349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
16351 * This field is used in Output records to indicate that the output
16352 * is completely written to RAM. This field should be read as '1'
16353 * to indicate that the output has been completely written.
16354 * When writing a command completion or response to an internal processor,
16355 * the order of writes has to be such that this field is written last.
16357 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
16358 UINT32_C(0xff000000)
16359 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
16360 } __attribute__((packed));
16362 /****************************
16363 * hwrm_port_phy_mdio_write *
16364 ****************************/
16367 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
16368 struct hwrm_port_phy_mdio_write_input {
16369 /* The HWRM command request type. */
16372 * The completion ring to send the completion event on. This should
16373 * be the NQ ID returned from the `nq_alloc` HWRM command.
16375 uint16_t cmpl_ring;
16377 * The sequence ID is used by the driver for tracking multiple
16378 * commands. This ID is treated as opaque data by the firmware and
16379 * the value is returned in the `hwrm_resp_hdr` upon completion.
16383 * The target ID of the command:
16384 * * 0x0-0xFFF8 - The function ID
16385 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16386 * * 0xFFFD - Reserved for user-space HWRM interface
16389 uint16_t target_id;
16391 * A physical address pointer pointing to a host buffer that the
16392 * command's response data will be written. This can be either a host
16393 * physical address (HPA) or a guest physical address (GPA) and must
16394 * point to a physically contiguous block of memory.
16396 uint64_t resp_addr;
16397 /* Reserved for future use. */
16398 uint32_t unused_0[2];
16399 /* Port ID of port. */
16401 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16403 /* 8-bit device address. */
16405 /* 16-bit register address. */
16407 /* 16-bit register data. */
16410 * When this bit is set to 1 a Clause 45 mdio access is done.
16411 * when this bit is set to 0 a Clause 22 mdio access is done.
16415 uint8_t unused_1[7];
16416 } __attribute__((packed));
16418 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
16419 struct hwrm_port_phy_mdio_write_output {
16420 /* The specific error status for the command. */
16421 uint16_t error_code;
16422 /* The HWRM command request type. */
16424 /* The sequence ID from the original command. */
16426 /* The length of the response data in number of bytes. */
16428 uint8_t unused_0[7];
16430 * This field is used in Output records to indicate that the output
16431 * is completely written to RAM. This field should be read as '1'
16432 * to indicate that the output has been completely written.
16433 * When writing a command completion or response to an internal processor,
16434 * the order of writes has to be such that this field is written last.
16437 } __attribute__((packed));
16439 /***************************
16440 * hwrm_port_phy_mdio_read *
16441 ***************************/
16444 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
16445 struct hwrm_port_phy_mdio_read_input {
16446 /* The HWRM command request type. */
16449 * The completion ring to send the completion event on. This should
16450 * be the NQ ID returned from the `nq_alloc` HWRM command.
16452 uint16_t cmpl_ring;
16454 * The sequence ID is used by the driver for tracking multiple
16455 * commands. This ID is treated as opaque data by the firmware and
16456 * the value is returned in the `hwrm_resp_hdr` upon completion.
16460 * The target ID of the command:
16461 * * 0x0-0xFFF8 - The function ID
16462 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16463 * * 0xFFFD - Reserved for user-space HWRM interface
16466 uint16_t target_id;
16468 * A physical address pointer pointing to a host buffer that the
16469 * command's response data will be written. This can be either a host
16470 * physical address (HPA) or a guest physical address (GPA) and must
16471 * point to a physically contiguous block of memory.
16473 uint64_t resp_addr;
16474 /* Reserved for future use. */
16475 uint32_t unused_0[2];
16476 /* Port ID of port. */
16478 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16480 /* 8-bit device address. */
16482 /* 16-bit register address. */
16485 * When this bit is set to 1 a Clause 45 mdio access is done.
16486 * when this bit is set to 0 a Clause 22 mdio access is done.
16491 } __attribute__((packed));
16493 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
16494 struct hwrm_port_phy_mdio_read_output {
16495 /* The specific error status for the command. */
16496 uint16_t error_code;
16497 /* The HWRM command request type. */
16499 /* The sequence ID from the original command. */
16501 /* The length of the response data in number of bytes. */
16503 /* 16-bit register data. */
16505 uint8_t unused_0[5];
16507 * This field is used in Output records to indicate that the output
16508 * is completely written to RAM. This field should be read as '1'
16509 * to indicate that the output has been completely written.
16510 * When writing a command completion or response to an internal processor,
16511 * the order of writes has to be such that this field is written last.
16514 } __attribute__((packed));
16516 /*********************
16517 * hwrm_port_led_cfg *
16518 *********************/
16521 /* hwrm_port_led_cfg_input (size:512b/64B) */
16522 struct hwrm_port_led_cfg_input {
16523 /* The HWRM command request type. */
16526 * The completion ring to send the completion event on. This should
16527 * be the NQ ID returned from the `nq_alloc` HWRM command.
16529 uint16_t cmpl_ring;
16531 * The sequence ID is used by the driver for tracking multiple
16532 * commands. This ID is treated as opaque data by the firmware and
16533 * the value is returned in the `hwrm_resp_hdr` upon completion.
16537 * The target ID of the command:
16538 * * 0x0-0xFFF8 - The function ID
16539 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16540 * * 0xFFFD - Reserved for user-space HWRM interface
16543 uint16_t target_id;
16545 * A physical address pointer pointing to a host buffer that the
16546 * command's response data will be written. This can be either a host
16547 * physical address (HPA) or a guest physical address (GPA) and must
16548 * point to a physically contiguous block of memory.
16550 uint64_t resp_addr;
16553 * This bit must be '1' for the led0_id field to be
16556 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
16559 * This bit must be '1' for the led0_state field to be
16562 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
16565 * This bit must be '1' for the led0_color field to be
16568 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
16571 * This bit must be '1' for the led0_blink_on field to be
16574 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
16577 * This bit must be '1' for the led0_blink_off field to be
16580 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
16583 * This bit must be '1' for the led0_group_id field to be
16586 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
16589 * This bit must be '1' for the led1_id field to be
16592 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
16595 * This bit must be '1' for the led1_state field to be
16598 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
16601 * This bit must be '1' for the led1_color field to be
16604 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
16607 * This bit must be '1' for the led1_blink_on field to be
16610 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
16613 * This bit must be '1' for the led1_blink_off field to be
16616 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
16619 * This bit must be '1' for the led1_group_id field to be
16622 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
16625 * This bit must be '1' for the led2_id field to be
16628 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
16631 * This bit must be '1' for the led2_state field to be
16634 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
16637 * This bit must be '1' for the led2_color field to be
16640 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
16643 * This bit must be '1' for the led2_blink_on field to be
16646 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
16649 * This bit must be '1' for the led2_blink_off field to be
16652 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
16655 * This bit must be '1' for the led2_group_id field to be
16658 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
16661 * This bit must be '1' for the led3_id field to be
16664 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
16667 * This bit must be '1' for the led3_state field to be
16670 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
16673 * This bit must be '1' for the led3_color field to be
16676 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
16679 * This bit must be '1' for the led3_blink_on field to be
16682 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
16685 * This bit must be '1' for the led3_blink_off field to be
16688 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
16691 * This bit must be '1' for the led3_group_id field to be
16694 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
16696 /* Port ID of port whose LEDs are configured. */
16699 * The number of LEDs that are being configured.
16700 * Up to 4 LEDs can be configured with this command.
16703 /* Reserved field. */
16705 /* An identifier for the LED #0. */
16707 /* The requested state of the LED #0. */
16708 uint8_t led0_state;
16709 /* Default state of the LED */
16710 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16712 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
16714 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
16716 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
16717 /* Blink Alternately */
16718 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
16719 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
16720 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
16721 /* The requested color of LED #0. */
16722 uint8_t led0_color;
16724 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
16726 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
16728 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
16729 /* Green or Amber */
16730 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
16731 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
16732 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
16735 * If the LED #0 state is "blink" or "blinkalt", then
16736 * this field represents the requested time in milliseconds
16737 * to keep LED on between cycles.
16739 uint16_t led0_blink_on;
16741 * If the LED #0 state is "blink" or "blinkalt", then
16742 * this field represents the requested time in milliseconds
16743 * to keep LED off between cycles.
16745 uint16_t led0_blink_off;
16747 * An identifier for the group of LEDs that LED #0 belongs
16749 * If set to 0, then the LED #0 shall not be grouped and
16750 * shall be treated as an individual resource.
16751 * For all other non-zero values of this field, LED #0 shall
16752 * be grouped together with the LEDs with the same group ID
16755 uint8_t led0_group_id;
16756 /* Reserved field. */
16758 /* An identifier for the LED #1. */
16760 /* The requested state of the LED #1. */
16761 uint8_t led1_state;
16762 /* Default state of the LED */
16763 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
16765 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
16767 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
16769 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
16770 /* Blink Alternately */
16771 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16772 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
16773 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
16774 /* The requested color of LED #1. */
16775 uint8_t led1_color;
16777 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16779 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16781 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16782 /* Green or Amber */
16783 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16784 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
16785 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
16788 * If the LED #1 state is "blink" or "blinkalt", then
16789 * this field represents the requested time in milliseconds
16790 * to keep LED on between cycles.
16792 uint16_t led1_blink_on;
16794 * If the LED #1 state is "blink" or "blinkalt", then
16795 * this field represents the requested time in milliseconds
16796 * to keep LED off between cycles.
16798 uint16_t led1_blink_off;
16800 * An identifier for the group of LEDs that LED #1 belongs
16802 * If set to 0, then the LED #1 shall not be grouped and
16803 * shall be treated as an individual resource.
16804 * For all other non-zero values of this field, LED #1 shall
16805 * be grouped together with the LEDs with the same group ID
16808 uint8_t led1_group_id;
16809 /* Reserved field. */
16811 /* An identifier for the LED #2. */
16813 /* The requested state of the LED #2. */
16814 uint8_t led2_state;
16815 /* Default state of the LED */
16816 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16818 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
16820 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
16822 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
16823 /* Blink Alternately */
16824 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16825 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
16826 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
16827 /* The requested color of LED #2. */
16828 uint8_t led2_color;
16830 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16832 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16834 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16835 /* Green or Amber */
16836 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16837 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
16838 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
16841 * If the LED #2 state is "blink" or "blinkalt", then
16842 * this field represents the requested time in milliseconds
16843 * to keep LED on between cycles.
16845 uint16_t led2_blink_on;
16847 * If the LED #2 state is "blink" or "blinkalt", then
16848 * this field represents the requested time in milliseconds
16849 * to keep LED off between cycles.
16851 uint16_t led2_blink_off;
16853 * An identifier for the group of LEDs that LED #2 belongs
16855 * If set to 0, then the LED #2 shall not be grouped and
16856 * shall be treated as an individual resource.
16857 * For all other non-zero values of this field, LED #2 shall
16858 * be grouped together with the LEDs with the same group ID
16861 uint8_t led2_group_id;
16862 /* Reserved field. */
16864 /* An identifier for the LED #3. */
16866 /* The requested state of the LED #3. */
16867 uint8_t led3_state;
16868 /* Default state of the LED */
16869 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16871 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
16873 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
16875 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
16876 /* Blink Alternately */
16877 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16878 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
16879 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
16880 /* The requested color of LED #3. */
16881 uint8_t led3_color;
16883 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16885 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16887 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16888 /* Green or Amber */
16889 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16890 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
16891 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
16894 * If the LED #3 state is "blink" or "blinkalt", then
16895 * this field represents the requested time in milliseconds
16896 * to keep LED on between cycles.
16898 uint16_t led3_blink_on;
16900 * If the LED #3 state is "blink" or "blinkalt", then
16901 * this field represents the requested time in milliseconds
16902 * to keep LED off between cycles.
16904 uint16_t led3_blink_off;
16906 * An identifier for the group of LEDs that LED #3 belongs
16908 * If set to 0, then the LED #3 shall not be grouped and
16909 * shall be treated as an individual resource.
16910 * For all other non-zero values of this field, LED #3 shall
16911 * be grouped together with the LEDs with the same group ID
16914 uint8_t led3_group_id;
16915 /* Reserved field. */
16917 } __attribute__((packed));
16919 /* hwrm_port_led_cfg_output (size:128b/16B) */
16920 struct hwrm_port_led_cfg_output {
16921 /* The specific error status for the command. */
16922 uint16_t error_code;
16923 /* The HWRM command request type. */
16925 /* The sequence ID from the original command. */
16927 /* The length of the response data in number of bytes. */
16929 uint8_t unused_0[7];
16931 * This field is used in Output records to indicate that the output
16932 * is completely written to RAM. This field should be read as '1'
16933 * to indicate that the output has been completely written.
16934 * When writing a command completion or response to an internal processor,
16935 * the order of writes has to be such that this field is written last.
16938 } __attribute__((packed));
16940 /**********************
16941 * hwrm_port_led_qcfg *
16942 **********************/
16945 /* hwrm_port_led_qcfg_input (size:192b/24B) */
16946 struct hwrm_port_led_qcfg_input {
16947 /* The HWRM command request type. */
16950 * The completion ring to send the completion event on. This should
16951 * be the NQ ID returned from the `nq_alloc` HWRM command.
16953 uint16_t cmpl_ring;
16955 * The sequence ID is used by the driver for tracking multiple
16956 * commands. This ID is treated as opaque data by the firmware and
16957 * the value is returned in the `hwrm_resp_hdr` upon completion.
16961 * The target ID of the command:
16962 * * 0x0-0xFFF8 - The function ID
16963 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16964 * * 0xFFFD - Reserved for user-space HWRM interface
16967 uint16_t target_id;
16969 * A physical address pointer pointing to a host buffer that the
16970 * command's response data will be written. This can be either a host
16971 * physical address (HPA) or a guest physical address (GPA) and must
16972 * point to a physically contiguous block of memory.
16974 uint64_t resp_addr;
16975 /* Port ID of port whose LED configuration is being queried. */
16977 uint8_t unused_0[6];
16978 } __attribute__((packed));
16980 /* hwrm_port_led_qcfg_output (size:448b/56B) */
16981 struct hwrm_port_led_qcfg_output {
16982 /* The specific error status for the command. */
16983 uint16_t error_code;
16984 /* The HWRM command request type. */
16986 /* The sequence ID from the original command. */
16988 /* The length of the response data in number of bytes. */
16991 * The number of LEDs that are configured on this port.
16992 * Up to 4 LEDs can be returned in the response.
16995 /* An identifier for the LED #0. */
16997 /* The type of LED #0. */
17000 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17002 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17004 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17005 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
17006 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
17007 /* The current state of the LED #0. */
17008 uint8_t led0_state;
17009 /* Default state of the LED */
17010 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
17012 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
17014 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
17016 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
17017 /* Blink Alternately */
17018 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
17019 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
17020 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
17021 /* The color of LED #0. */
17022 uint8_t led0_color;
17024 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
17026 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
17028 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
17029 /* Green or Amber */
17030 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
17031 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
17032 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
17035 * If the LED #0 state is "blink" or "blinkalt", then
17036 * this field represents the requested time in milliseconds
17037 * to keep LED on between cycles.
17039 uint16_t led0_blink_on;
17041 * If the LED #0 state is "blink" or "blinkalt", then
17042 * this field represents the requested time in milliseconds
17043 * to keep LED off between cycles.
17045 uint16_t led0_blink_off;
17047 * An identifier for the group of LEDs that LED #0 belongs
17049 * If set to 0, then the LED #0 is not grouped.
17050 * For all other non-zero values of this field, LED #0 is
17051 * grouped together with the LEDs with the same group ID
17054 uint8_t led0_group_id;
17055 /* An identifier for the LED #1. */
17057 /* The type of LED #1. */
17060 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17062 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17064 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17065 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
17066 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
17067 /* The current state of the LED #1. */
17068 uint8_t led1_state;
17069 /* Default state of the LED */
17070 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
17072 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
17074 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
17076 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
17077 /* Blink Alternately */
17078 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
17079 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
17080 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
17081 /* The color of LED #1. */
17082 uint8_t led1_color;
17084 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
17086 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
17088 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
17089 /* Green or Amber */
17090 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
17091 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
17092 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
17095 * If the LED #1 state is "blink" or "blinkalt", then
17096 * this field represents the requested time in milliseconds
17097 * to keep LED on between cycles.
17099 uint16_t led1_blink_on;
17101 * If the LED #1 state is "blink" or "blinkalt", then
17102 * this field represents the requested time in milliseconds
17103 * to keep LED off between cycles.
17105 uint16_t led1_blink_off;
17107 * An identifier for the group of LEDs that LED #1 belongs
17109 * If set to 0, then the LED #1 is not grouped.
17110 * For all other non-zero values of this field, LED #1 is
17111 * grouped together with the LEDs with the same group ID
17114 uint8_t led1_group_id;
17115 /* An identifier for the LED #2. */
17117 /* The type of LED #2. */
17120 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17125 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
17126 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
17127 /* The current state of the LED #2. */
17128 uint8_t led2_state;
17129 /* Default state of the LED */
17130 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
17132 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
17134 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
17136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
17137 /* Blink Alternately */
17138 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
17139 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
17140 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
17141 /* The color of LED #2. */
17142 uint8_t led2_color;
17144 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
17146 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
17148 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
17149 /* Green or Amber */
17150 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
17151 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
17152 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
17155 * If the LED #2 state is "blink" or "blinkalt", then
17156 * this field represents the requested time in milliseconds
17157 * to keep LED on between cycles.
17159 uint16_t led2_blink_on;
17161 * If the LED #2 state is "blink" or "blinkalt", then
17162 * this field represents the requested time in milliseconds
17163 * to keep LED off between cycles.
17165 uint16_t led2_blink_off;
17167 * An identifier for the group of LEDs that LED #2 belongs
17169 * If set to 0, then the LED #2 is not grouped.
17170 * For all other non-zero values of this field, LED #2 is
17171 * grouped together with the LEDs with the same group ID
17174 uint8_t led2_group_id;
17175 /* An identifier for the LED #3. */
17177 /* The type of LED #3. */
17180 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17184 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17185 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
17186 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
17187 /* The current state of the LED #3. */
17188 uint8_t led3_state;
17189 /* Default state of the LED */
17190 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17192 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
17194 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
17196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
17197 /* Blink Alternately */
17198 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17199 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
17200 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
17201 /* The color of LED #3. */
17202 uint8_t led3_color;
17204 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17206 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17208 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
17209 /* Green or Amber */
17210 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
17211 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
17212 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
17215 * If the LED #3 state is "blink" or "blinkalt", then
17216 * this field represents the requested time in milliseconds
17217 * to keep LED on between cycles.
17219 uint16_t led3_blink_on;
17221 * If the LED #3 state is "blink" or "blinkalt", then
17222 * this field represents the requested time in milliseconds
17223 * to keep LED off between cycles.
17225 uint16_t led3_blink_off;
17227 * An identifier for the group of LEDs that LED #3 belongs
17229 * If set to 0, then the LED #3 is not grouped.
17230 * For all other non-zero values of this field, LED #3 is
17231 * grouped together with the LEDs with the same group ID
17234 uint8_t led3_group_id;
17235 uint8_t unused_4[6];
17237 * This field is used in Output records to indicate that the output
17238 * is completely written to RAM. This field should be read as '1'
17239 * to indicate that the output has been completely written.
17240 * When writing a command completion or response to an internal processor,
17241 * the order of writes has to be such that this field is written last.
17244 } __attribute__((packed));
17246 /***********************
17247 * hwrm_port_led_qcaps *
17248 ***********************/
17251 /* hwrm_port_led_qcaps_input (size:192b/24B) */
17252 struct hwrm_port_led_qcaps_input {
17253 /* The HWRM command request type. */
17256 * The completion ring to send the completion event on. This should
17257 * be the NQ ID returned from the `nq_alloc` HWRM command.
17259 uint16_t cmpl_ring;
17261 * The sequence ID is used by the driver for tracking multiple
17262 * commands. This ID is treated as opaque data by the firmware and
17263 * the value is returned in the `hwrm_resp_hdr` upon completion.
17267 * The target ID of the command:
17268 * * 0x0-0xFFF8 - The function ID
17269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17270 * * 0xFFFD - Reserved for user-space HWRM interface
17273 uint16_t target_id;
17275 * A physical address pointer pointing to a host buffer that the
17276 * command's response data will be written. This can be either a host
17277 * physical address (HPA) or a guest physical address (GPA) and must
17278 * point to a physically contiguous block of memory.
17280 uint64_t resp_addr;
17281 /* Port ID of port whose LED configuration is being queried. */
17283 uint8_t unused_0[6];
17284 } __attribute__((packed));
17286 /* hwrm_port_led_qcaps_output (size:384b/48B) */
17287 struct hwrm_port_led_qcaps_output {
17288 /* The specific error status for the command. */
17289 uint16_t error_code;
17290 /* The HWRM command request type. */
17292 /* The sequence ID from the original command. */
17294 /* The length of the response data in number of bytes. */
17297 * The number of LEDs that are configured on this port.
17298 * Up to 4 LEDs can be returned in the response.
17301 /* Reserved for future use. */
17303 /* An identifier for the LED #0. */
17305 /* The type of LED #0. */
17308 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17310 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17312 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17313 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
17314 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
17316 * An identifier for the group of LEDs that LED #0 belongs
17318 * If set to 0, then the LED #0 cannot be grouped.
17319 * For all other non-zero values of this field, LED #0 is
17320 * grouped together with the LEDs with the same group ID
17323 uint8_t led0_group_id;
17325 /* The states supported by LED #0. */
17326 uint16_t led0_state_caps;
17328 * If set to 1, this LED is enabled.
17329 * If set to 0, this LED is disabled.
17331 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
17334 * If set to 1, off state is supported on this LED.
17335 * If set to 0, off state is not supported on this LED.
17337 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
17340 * If set to 1, on state is supported on this LED.
17341 * If set to 0, on state is not supported on this LED.
17343 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
17346 * If set to 1, blink state is supported on this LED.
17347 * If set to 0, blink state is not supported on this LED.
17349 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
17352 * If set to 1, blink_alt state is supported on this LED.
17353 * If set to 0, blink_alt state is not supported on this LED.
17355 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
17357 /* The colors supported by LED #0. */
17358 uint16_t led0_color_caps;
17360 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
17363 * If set to 1, Amber color is supported on this LED.
17364 * If set to 0, Amber color is not supported on this LED.
17366 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
17369 * If set to 1, Green color is supported on this LED.
17370 * If set to 0, Green color is not supported on this LED.
17372 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
17374 /* An identifier for the LED #1. */
17376 /* The type of LED #1. */
17379 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17381 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17383 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17384 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
17385 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
17387 * An identifier for the group of LEDs that LED #1 belongs
17389 * If set to 0, then the LED #0 cannot be grouped.
17390 * For all other non-zero values of this field, LED #0 is
17391 * grouped together with the LEDs with the same group ID
17394 uint8_t led1_group_id;
17396 /* The states supported by LED #1. */
17397 uint16_t led1_state_caps;
17399 * If set to 1, this LED is enabled.
17400 * If set to 0, this LED is disabled.
17402 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
17405 * If set to 1, off state is supported on this LED.
17406 * If set to 0, off state is not supported on this LED.
17408 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
17411 * If set to 1, on state is supported on this LED.
17412 * If set to 0, on state is not supported on this LED.
17414 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
17417 * If set to 1, blink state is supported on this LED.
17418 * If set to 0, blink state is not supported on this LED.
17420 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
17423 * If set to 1, blink_alt state is supported on this LED.
17424 * If set to 0, blink_alt state is not supported on this LED.
17426 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
17428 /* The colors supported by LED #1. */
17429 uint16_t led1_color_caps;
17431 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
17434 * If set to 1, Amber color is supported on this LED.
17435 * If set to 0, Amber color is not supported on this LED.
17437 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
17440 * If set to 1, Green color is supported on this LED.
17441 * If set to 0, Green color is not supported on this LED.
17443 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
17445 /* An identifier for the LED #2. */
17447 /* The type of LED #2. */
17450 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17452 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17454 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17455 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
17456 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
17458 * An identifier for the group of LEDs that LED #0 belongs
17460 * If set to 0, then the LED #0 cannot be grouped.
17461 * For all other non-zero values of this field, LED #0 is
17462 * grouped together with the LEDs with the same group ID
17465 uint8_t led2_group_id;
17467 /* The states supported by LED #2. */
17468 uint16_t led2_state_caps;
17470 * If set to 1, this LED is enabled.
17471 * If set to 0, this LED is disabled.
17473 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
17476 * If set to 1, off state is supported on this LED.
17477 * If set to 0, off state is not supported on this LED.
17479 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
17482 * If set to 1, on state is supported on this LED.
17483 * If set to 0, on state is not supported on this LED.
17485 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
17488 * If set to 1, blink state is supported on this LED.
17489 * If set to 0, blink state is not supported on this LED.
17491 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
17494 * If set to 1, blink_alt state is supported on this LED.
17495 * If set to 0, blink_alt state is not supported on this LED.
17497 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
17499 /* The colors supported by LED #2. */
17500 uint16_t led2_color_caps;
17502 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
17505 * If set to 1, Amber color is supported on this LED.
17506 * If set to 0, Amber color is not supported on this LED.
17508 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
17511 * If set to 1, Green color is supported on this LED.
17512 * If set to 0, Green color is not supported on this LED.
17514 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
17516 /* An identifier for the LED #3. */
17518 /* The type of LED #3. */
17521 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17523 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17525 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17526 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
17527 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
17529 * An identifier for the group of LEDs that LED #3 belongs
17531 * If set to 0, then the LED #0 cannot be grouped.
17532 * For all other non-zero values of this field, LED #0 is
17533 * grouped together with the LEDs with the same group ID
17536 uint8_t led3_group_id;
17538 /* The states supported by LED #3. */
17539 uint16_t led3_state_caps;
17541 * If set to 1, this LED is enabled.
17542 * If set to 0, this LED is disabled.
17544 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
17547 * If set to 1, off state is supported on this LED.
17548 * If set to 0, off state is not supported on this LED.
17550 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
17553 * If set to 1, on state is supported on this LED.
17554 * If set to 0, on state is not supported on this LED.
17556 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
17559 * If set to 1, blink state is supported on this LED.
17560 * If set to 0, blink state is not supported on this LED.
17562 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
17565 * If set to 1, blink_alt state is supported on this LED.
17566 * If set to 0, blink_alt state is not supported on this LED.
17568 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
17570 /* The colors supported by LED #3. */
17571 uint16_t led3_color_caps;
17573 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
17576 * If set to 1, Amber color is supported on this LED.
17577 * If set to 0, Amber color is not supported on this LED.
17579 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
17582 * If set to 1, Green color is supported on this LED.
17583 * If set to 0, Green color is not supported on this LED.
17585 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
17587 uint8_t unused_4[3];
17589 * This field is used in Output records to indicate that the output
17590 * is completely written to RAM. This field should be read as '1'
17591 * to indicate that the output has been completely written.
17592 * When writing a command completion or response to an internal processor,
17593 * the order of writes has to be such that this field is written last.
17596 } __attribute__((packed));
17598 /***********************
17599 * hwrm_port_prbs_test *
17600 ***********************/
17603 /* hwrm_port_prbs_test_input (size:384b/48B) */
17604 struct hwrm_port_prbs_test_input {
17605 /* The HWRM command request type. */
17608 * The completion ring to send the completion event on. This should
17609 * be the NQ ID returned from the `nq_alloc` HWRM command.
17611 uint16_t cmpl_ring;
17613 * The sequence ID is used by the driver for tracking multiple
17614 * commands. This ID is treated as opaque data by the firmware and
17615 * the value is returned in the `hwrm_resp_hdr` upon completion.
17619 * The target ID of the command:
17620 * * 0x0-0xFFF8 - The function ID
17621 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17622 * * 0xFFFD - Reserved for user-space HWRM interface
17625 uint16_t target_id;
17627 * A physical address pointer pointing to a host buffer that the
17628 * command's response data will be written. This can be either a host
17629 * physical address (HPA) or a guest physical address (GPA) and must
17630 * point to a physically contiguous block of memory.
17632 uint64_t resp_addr;
17633 /* Host address data is to DMA'd to. */
17634 uint64_t resp_data_addr;
17636 * Size of the buffer pointed to by resp_data_addr. The firmware may
17637 * use this entire buffer or less than the entire buffer, but never more.
17642 /* Port ID of port where PRBS test to be run. */
17644 /* Polynomial selection for PRBS test. */
17647 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
17649 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
17651 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
17653 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
17655 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
17657 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
17659 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
17661 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
17662 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
17663 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
17665 * Configuration bits for PRBS test.
17666 * Use enable bit to start/stop test.
17667 * Use tx/rx lane map bits to run test on specific lanes,
17668 * if set to 0 test will be run on all lanes.
17670 uint16_t prbs_config;
17672 * Set 0 to stop test currently in progress
17673 * Set 1 to start test with configuration provided.
17675 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
17678 * If set to 1, tx_lane_map bitmap should have lane bits set.
17679 * If set to 0, test will be run on all lanes for this port.
17681 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
17684 * If set to 1, rx_lane_map bitmap should have lane bits set.
17685 * If set to 0, test will be run on all lanes for this port.
17687 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
17689 /* Duration in seconds to run the PRBS test. */
17692 * If tx_lane_map_valid is set to 1, this field is a bitmap
17693 * of tx lanes to run PRBS test. bit0 = lane0,
17694 * bit1 = lane1 ..bit31 = lane31
17696 uint32_t tx_lane_map;
17698 * If rx_lane_map_valid is set to 1, this field is a bitmap
17699 * of rx lanes to run PRBS test. bit0 = lane0,
17700 * bit1 = lane1 ..bit31 = lane31
17702 uint32_t rx_lane_map;
17703 } __attribute__((packed));
17705 /* hwrm_port_prbs_test_output (size:128b/16B) */
17706 struct hwrm_port_prbs_test_output {
17707 /* The specific error status for the command. */
17708 uint16_t error_code;
17709 /* The HWRM command request type. */
17711 /* The sequence ID from the original command. */
17713 /* The length of the response data in number of bytes. */
17715 /* Total length of stored data. */
17716 uint16_t total_data_len;
17718 uint8_t unused_1[3];
17720 * This field is used in Output records to indicate that the output
17721 * is completely written to RAM. This field should be read as '1'
17722 * to indicate that the output has been completely written.
17723 * When writing a command completion or response to an internal processor,
17724 * the order of writes has to be such that this field is written last.
17727 } __attribute__((packed));
17729 /***********************
17730 * hwrm_queue_qportcfg *
17731 ***********************/
17734 /* hwrm_queue_qportcfg_input (size:192b/24B) */
17735 struct hwrm_queue_qportcfg_input {
17736 /* The HWRM command request type. */
17739 * The completion ring to send the completion event on. This should
17740 * be the NQ ID returned from the `nq_alloc` HWRM command.
17742 uint16_t cmpl_ring;
17744 * The sequence ID is used by the driver for tracking multiple
17745 * commands. This ID is treated as opaque data by the firmware and
17746 * the value is returned in the `hwrm_resp_hdr` upon completion.
17750 * The target ID of the command:
17751 * * 0x0-0xFFF8 - The function ID
17752 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17753 * * 0xFFFD - Reserved for user-space HWRM interface
17756 uint16_t target_id;
17758 * A physical address pointer pointing to a host buffer that the
17759 * command's response data will be written. This can be either a host
17760 * physical address (HPA) or a guest physical address (GPA) and must
17761 * point to a physically contiguous block of memory.
17763 uint64_t resp_addr;
17766 * Enumeration denoting the RX, TX type of the resource.
17767 * This enumeration is used for resources that are similar for both
17768 * TX and RX paths of the chip.
17770 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17772 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17774 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17775 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
17776 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
17778 * Port ID of port for which the queue configuration is being
17779 * queried. This field is only required when sent by IPC.
17783 * Drivers will set this capability when it can use
17784 * queue_idx_service_profile to map the queues to application.
17786 uint8_t drv_qmap_cap;
17788 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
17790 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
17791 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
17792 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
17794 } __attribute__((packed));
17796 /* hwrm_queue_qportcfg_output (size:256b/32B) */
17797 struct hwrm_queue_qportcfg_output {
17798 /* The specific error status for the command. */
17799 uint16_t error_code;
17800 /* The HWRM command request type. */
17802 /* The sequence ID from the original command. */
17804 /* The length of the response data in number of bytes. */
17807 * The maximum number of queues that can be configured on this
17809 * Valid values range from 1 through 8.
17811 uint8_t max_configurable_queues;
17813 * The maximum number of lossless queues that can be configured
17815 * Valid values range from 0 through 8.
17817 uint8_t max_configurable_lossless_queues;
17819 * Bitmask indicating which queues can be configured by the
17820 * hwrm_queue_cfg command.
17822 * Each bit represents a specific queue where bit 0 represents
17823 * queue 0 and bit 7 represents queue 7.
17824 * # A value of 0 indicates that the queue is not configurable
17825 * by the hwrm_queue_cfg command.
17826 * # A value of 1 indicates that the queue is configurable.
17827 * # A hwrm_queue_cfg command shall return error when trying to
17828 * configure a queue not configurable.
17830 uint8_t queue_cfg_allowed;
17831 /* Information about queue configuration. */
17832 uint8_t queue_cfg_info;
17834 * If this flag is set to '1', then the queues are
17835 * configured asymmetrically on TX and RX sides.
17836 * If this flag is set to '0', then the queues are
17837 * configured symmetrically on TX and RX sides. For
17838 * symmetric configuration, the queue configuration
17839 * including queue ids and service profiles on the
17840 * TX side is the same as the corresponding queue
17841 * configuration on the RX side.
17843 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17846 * Bitmask indicating which queues can be configured by the
17847 * hwrm_queue_pfcenable_cfg command.
17849 * Each bit represents a specific priority where bit 0 represents
17850 * priority 0 and bit 7 represents priority 7.
17851 * # A value of 0 indicates that the priority is not configurable by
17852 * the hwrm_queue_pfcenable_cfg command.
17853 * # A value of 1 indicates that the priority is configurable.
17854 * # A hwrm_queue_pfcenable_cfg command shall return error when
17855 * trying to configure a priority that is not configurable.
17857 uint8_t queue_pfcenable_cfg_allowed;
17859 * Bitmask indicating which queues can be configured by the
17860 * hwrm_queue_pri2cos_cfg command.
17862 * Each bit represents a specific queue where bit 0 represents
17863 * queue 0 and bit 7 represents queue 7.
17864 * # A value of 0 indicates that the queue is not configurable
17865 * by the hwrm_queue_pri2cos_cfg command.
17866 * # A value of 1 indicates that the queue is configurable.
17867 * # A hwrm_queue_pri2cos_cfg command shall return error when
17868 * trying to configure a queue that is not configurable.
17870 uint8_t queue_pri2cos_cfg_allowed;
17872 * Bitmask indicating which queues can be configured by the
17873 * hwrm_queue_pri2cos_cfg command.
17875 * Each bit represents a specific queue where bit 0 represents
17876 * queue 0 and bit 7 represents queue 7.
17877 * # A value of 0 indicates that the queue is not configurable
17878 * by the hwrm_queue_pri2cos_cfg command.
17879 * # A value of 1 indicates that the queue is configurable.
17880 * # A hwrm_queue_pri2cos_cfg command shall return error when
17881 * trying to configure a queue not configurable.
17883 uint8_t queue_cos2bw_cfg_allowed;
17885 * ID of CoS Queue 0.
17888 * # This ID can be used on any subsequent call to an hwrm command
17889 * that takes a queue id.
17890 * # IDs must always be queried by this command before any use
17891 * by the driver or software.
17892 * # Any driver or software should not make any assumptions about
17894 * # A value of 0xff indicates that the queue is not available.
17895 * # Available queues may not be in sequential order.
17898 /* This value is applicable to CoS queues only. */
17899 uint8_t queue_id0_service_profile;
17900 /* Lossy (best-effort) */
17901 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
17903 /* Lossless (legacy) */
17904 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
17906 /* Lossless RoCE */
17907 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
17909 /* Lossy RoCE CNP */
17910 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17913 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
17915 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17916 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
17918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
17919 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
17921 * ID of CoS Queue 1.
17924 * # This ID can be used on any subsequent call to an hwrm command
17925 * that takes a queue id.
17926 * # IDs must always be queried by this command before any use
17927 * by the driver or software.
17928 * # Any driver or software should not make any assumptions about
17930 * # A value of 0xff indicates that the queue is not available.
17931 * # Available queues may not be in sequential order.
17934 /* This value is applicable to CoS queues only. */
17935 uint8_t queue_id1_service_profile;
17936 /* Lossy (best-effort) */
17937 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
17939 /* Lossless (legacy) */
17940 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
17942 /* Lossless RoCE */
17943 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
17945 /* Lossy RoCE CNP */
17946 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17949 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
17951 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17952 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
17954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
17955 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
17957 * ID of CoS Queue 2.
17960 * # This ID can be used on any subsequent call to an hwrm command
17961 * that takes a queue id.
17962 * # IDs must always be queried by this command before any use
17963 * by the driver or software.
17964 * # Any driver or software should not make any assumptions about
17966 * # A value of 0xff indicates that the queue is not available.
17967 * # Available queues may not be in sequential order.
17970 /* This value is applicable to CoS queues only. */
17971 uint8_t queue_id2_service_profile;
17972 /* Lossy (best-effort) */
17973 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
17975 /* Lossless (legacy) */
17976 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
17978 /* Lossless RoCE */
17979 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
17981 /* Lossy RoCE CNP */
17982 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17985 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
17987 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17988 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
17990 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
17991 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
17993 * ID of CoS Queue 3.
17996 * # This ID can be used on any subsequent call to an hwrm command
17997 * that takes a queue id.
17998 * # IDs must always be queried by this command before any use
17999 * by the driver or software.
18000 * # Any driver or software should not make any assumptions about
18002 * # A value of 0xff indicates that the queue is not available.
18003 * # Available queues may not be in sequential order.
18006 /* This value is applicable to CoS queues only. */
18007 uint8_t queue_id3_service_profile;
18008 /* Lossy (best-effort) */
18009 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
18011 /* Lossless (legacy) */
18012 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
18014 /* Lossless RoCE */
18015 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
18017 /* Lossy RoCE CNP */
18018 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18021 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
18023 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18024 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
18026 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
18027 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
18029 * ID of CoS Queue 4.
18032 * # This ID can be used on any subsequent call to an hwrm command
18033 * that takes a queue id.
18034 * # IDs must always be queried by this command before any use
18035 * by the driver or software.
18036 * # Any driver or software should not make any assumptions about
18038 * # A value of 0xff indicates that the queue is not available.
18039 * # Available queues may not be in sequential order.
18042 /* This value is applicable to CoS queues only. */
18043 uint8_t queue_id4_service_profile;
18044 /* Lossy (best-effort) */
18045 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
18047 /* Lossless (legacy) */
18048 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
18050 /* Lossless RoCE */
18051 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
18053 /* Lossy RoCE CNP */
18054 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18057 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
18059 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18060 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
18062 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
18063 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
18065 * ID of CoS Queue 5.
18068 * # This ID can be used on any subsequent call to an hwrm command
18069 * that takes a queue id.
18070 * # IDs must always be queried by this command before any use
18071 * by the driver or software.
18072 * # Any driver or software should not make any assumptions about
18074 * # A value of 0xff indicates that the queue is not available.
18075 * # Available queues may not be in sequential order.
18078 /* This value is applicable to CoS queues only. */
18079 uint8_t queue_id5_service_profile;
18080 /* Lossy (best-effort) */
18081 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
18083 /* Lossless (legacy) */
18084 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
18086 /* Lossless RoCE */
18087 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
18089 /* Lossy RoCE CNP */
18090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18093 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
18095 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18096 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
18098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
18099 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
18101 * ID of CoS Queue 6.
18104 * # This ID can be used on any subsequent call to an hwrm command
18105 * that takes a queue id.
18106 * # IDs must always be queried by this command before any use
18107 * by the driver or software.
18108 * # Any driver or software should not make any assumptions about
18110 * # A value of 0xff indicates that the queue is not available.
18111 * # Available queues may not be in sequential order.
18114 /* This value is applicable to CoS queues only. */
18115 uint8_t queue_id6_service_profile;
18116 /* Lossy (best-effort) */
18117 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
18119 /* Lossless (legacy) */
18120 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
18122 /* Lossless RoCE */
18123 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
18125 /* Lossy RoCE CNP */
18126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18129 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
18131 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18132 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
18134 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
18135 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
18137 * ID of CoS Queue 7.
18140 * # This ID can be used on any subsequent call to an hwrm command
18141 * that takes a queue id.
18142 * # IDs must always be queried by this command before any use
18143 * by the driver or software.
18144 * # Any driver or software should not make any assumptions about
18146 * # A value of 0xff indicates that the queue is not available.
18147 * # Available queues may not be in sequential order.
18150 /* This value is applicable to CoS queues only. */
18151 uint8_t queue_id7_service_profile;
18152 /* Lossy (best-effort) */
18153 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
18155 /* Lossless (legacy) */
18156 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
18158 /* Lossless RoCE */
18159 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
18161 /* Lossy RoCE CNP */
18162 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18165 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
18167 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18168 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
18170 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
18171 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
18173 * This field is used in Output records to indicate that the output
18174 * is completely written to RAM. This field should be read as '1'
18175 * to indicate that the output has been completely written.
18176 * When writing a command completion or response to an internal processor,
18177 * the order of writes has to be such that this field is written last.
18180 } __attribute__((packed));
18182 /*******************
18183 * hwrm_queue_qcfg *
18184 *******************/
18187 /* hwrm_queue_qcfg_input (size:192b/24B) */
18188 struct hwrm_queue_qcfg_input {
18189 /* The HWRM command request type. */
18192 * The completion ring to send the completion event on. This should
18193 * be the NQ ID returned from the `nq_alloc` HWRM command.
18195 uint16_t cmpl_ring;
18197 * The sequence ID is used by the driver for tracking multiple
18198 * commands. This ID is treated as opaque data by the firmware and
18199 * the value is returned in the `hwrm_resp_hdr` upon completion.
18203 * The target ID of the command:
18204 * * 0x0-0xFFF8 - The function ID
18205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18206 * * 0xFFFD - Reserved for user-space HWRM interface
18209 uint16_t target_id;
18211 * A physical address pointer pointing to a host buffer that the
18212 * command's response data will be written. This can be either a host
18213 * physical address (HPA) or a guest physical address (GPA) and must
18214 * point to a physically contiguous block of memory.
18216 uint64_t resp_addr;
18219 * Enumeration denoting the RX, TX type of the resource.
18220 * This enumeration is used for resources that are similar for both
18221 * TX and RX paths of the chip.
18223 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18225 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18227 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18228 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
18229 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
18230 /* Queue ID of the queue. */
18232 } __attribute__((packed));
18234 /* hwrm_queue_qcfg_output (size:128b/16B) */
18235 struct hwrm_queue_qcfg_output {
18236 /* The specific error status for the command. */
18237 uint16_t error_code;
18238 /* The HWRM command request type. */
18240 /* The sequence ID from the original command. */
18242 /* The length of the response data in number of bytes. */
18245 * This value is a the estimate packet length used in the
18248 uint32_t queue_len;
18249 /* This value is applicable to CoS queues only. */
18250 uint8_t service_profile;
18251 /* Lossy (best-effort) */
18252 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18254 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18255 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18256 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18257 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
18258 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
18259 /* Information about queue configuration. */
18260 uint8_t queue_cfg_info;
18262 * If this flag is set to '1', then the queue is
18263 * configured asymmetrically on TX and RX sides.
18264 * If this flag is set to '0', then this queue is
18265 * configured symmetrically on TX and RX sides.
18267 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18271 * This field is used in Output records to indicate that the output
18272 * is completely written to RAM. This field should be read as '1'
18273 * to indicate that the output has been completely written.
18274 * When writing a command completion or response to an internal processor,
18275 * the order of writes has to be such that this field is written last.
18278 } __attribute__((packed));
18280 /******************
18282 ******************/
18285 /* hwrm_queue_cfg_input (size:320b/40B) */
18286 struct hwrm_queue_cfg_input {
18287 /* The HWRM command request type. */
18290 * The completion ring to send the completion event on. This should
18291 * be the NQ ID returned from the `nq_alloc` HWRM command.
18293 uint16_t cmpl_ring;
18295 * The sequence ID is used by the driver for tracking multiple
18296 * commands. This ID is treated as opaque data by the firmware and
18297 * the value is returned in the `hwrm_resp_hdr` upon completion.
18301 * The target ID of the command:
18302 * * 0x0-0xFFF8 - The function ID
18303 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18304 * * 0xFFFD - Reserved for user-space HWRM interface
18307 uint16_t target_id;
18309 * A physical address pointer pointing to a host buffer that the
18310 * command's response data will be written. This can be either a host
18311 * physical address (HPA) or a guest physical address (GPA) and must
18312 * point to a physically contiguous block of memory.
18314 uint64_t resp_addr;
18317 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18318 * This enumeration is used for resources that are similar for both
18319 * TX and RX paths of the chip.
18321 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18322 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
18324 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18326 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18327 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18328 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18329 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
18330 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
18333 * This bit must be '1' for the dflt_len field to be
18336 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
18338 * This bit must be '1' for the service_profile field to be
18341 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
18342 /* Queue ID of queue that is to be configured by this function. */
18345 * This value is a the estimate packet length used in the
18347 * Set to 0xFF... (All Fs) to not adjust this value.
18350 /* This value is applicable to CoS queues only. */
18351 uint8_t service_profile;
18352 /* Lossy (best-effort) */
18353 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18355 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18356 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18357 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18358 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
18359 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
18360 uint8_t unused_0[7];
18361 } __attribute__((packed));
18363 /* hwrm_queue_cfg_output (size:128b/16B) */
18364 struct hwrm_queue_cfg_output {
18365 /* The specific error status for the command. */
18366 uint16_t error_code;
18367 /* The HWRM command request type. */
18369 /* The sequence ID from the original command. */
18371 /* The length of the response data in number of bytes. */
18373 uint8_t unused_0[7];
18375 * This field is used in Output records to indicate that the output
18376 * is completely written to RAM. This field should be read as '1'
18377 * to indicate that the output has been completely written.
18378 * When writing a command completion or response to an internal processor,
18379 * the order of writes has to be such that this field is written last.
18382 } __attribute__((packed));
18384 /*****************************
18385 * hwrm_queue_pfcenable_qcfg *
18386 *****************************/
18389 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
18390 struct hwrm_queue_pfcenable_qcfg_input {
18391 /* The HWRM command request type. */
18394 * The completion ring to send the completion event on. This should
18395 * be the NQ ID returned from the `nq_alloc` HWRM command.
18397 uint16_t cmpl_ring;
18399 * The sequence ID is used by the driver for tracking multiple
18400 * commands. This ID is treated as opaque data by the firmware and
18401 * the value is returned in the `hwrm_resp_hdr` upon completion.
18405 * The target ID of the command:
18406 * * 0x0-0xFFF8 - The function ID
18407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18408 * * 0xFFFD - Reserved for user-space HWRM interface
18411 uint16_t target_id;
18413 * A physical address pointer pointing to a host buffer that the
18414 * command's response data will be written. This can be either a host
18415 * physical address (HPA) or a guest physical address (GPA) and must
18416 * point to a physically contiguous block of memory.
18418 uint64_t resp_addr;
18420 * Port ID of port for which the table is being configured.
18421 * The HWRM needs to check whether this function is allowed
18422 * to configure pri2cos mapping on this port.
18425 uint8_t unused_0[6];
18426 } __attribute__((packed));
18428 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
18429 struct hwrm_queue_pfcenable_qcfg_output {
18430 /* The specific error status for the command. */
18431 uint16_t error_code;
18432 /* The HWRM command request type. */
18434 /* The sequence ID from the original command. */
18436 /* The length of the response data in number of bytes. */
18439 /* If set to 1, then PFC is enabled on PRI 0. */
18440 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
18442 /* If set to 1, then PFC is enabled on PRI 1. */
18443 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
18445 /* If set to 1, then PFC is enabled on PRI 2. */
18446 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
18448 /* If set to 1, then PFC is enabled on PRI 3. */
18449 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
18451 /* If set to 1, then PFC is enabled on PRI 4. */
18452 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
18454 /* If set to 1, then PFC is enabled on PRI 5. */
18455 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
18457 /* If set to 1, then PFC is enabled on PRI 6. */
18458 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
18460 /* If set to 1, then PFC is enabled on PRI 7. */
18461 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
18463 uint8_t unused_0[3];
18465 * This field is used in Output records to indicate that the output
18466 * is completely written to RAM. This field should be read as '1'
18467 * to indicate that the output has been completely written.
18468 * When writing a command completion or response to an internal processor,
18469 * the order of writes has to be such that this field is written last.
18472 } __attribute__((packed));
18474 /****************************
18475 * hwrm_queue_pfcenable_cfg *
18476 ****************************/
18479 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
18480 struct hwrm_queue_pfcenable_cfg_input {
18481 /* The HWRM command request type. */
18484 * The completion ring to send the completion event on. This should
18485 * be the NQ ID returned from the `nq_alloc` HWRM command.
18487 uint16_t cmpl_ring;
18489 * The sequence ID is used by the driver for tracking multiple
18490 * commands. This ID is treated as opaque data by the firmware and
18491 * the value is returned in the `hwrm_resp_hdr` upon completion.
18495 * The target ID of the command:
18496 * * 0x0-0xFFF8 - The function ID
18497 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18498 * * 0xFFFD - Reserved for user-space HWRM interface
18501 uint16_t target_id;
18503 * A physical address pointer pointing to a host buffer that the
18504 * command's response data will be written. This can be either a host
18505 * physical address (HPA) or a guest physical address (GPA) and must
18506 * point to a physically contiguous block of memory.
18508 uint64_t resp_addr;
18510 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
18511 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
18513 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
18514 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
18516 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
18517 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
18519 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
18520 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
18522 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
18523 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
18525 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
18526 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
18528 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
18529 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
18531 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
18532 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
18535 * Port ID of port for which the table is being configured.
18536 * The HWRM needs to check whether this function is allowed
18537 * to configure pri2cos mapping on this port.
18540 uint8_t unused_0[2];
18541 } __attribute__((packed));
18543 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
18544 struct hwrm_queue_pfcenable_cfg_output {
18545 /* The specific error status for the command. */
18546 uint16_t error_code;
18547 /* The HWRM command request type. */
18549 /* The sequence ID from the original command. */
18551 /* The length of the response data in number of bytes. */
18553 uint8_t unused_0[7];
18555 * This field is used in Output records to indicate that the output
18556 * is completely written to RAM. This field should be read as '1'
18557 * to indicate that the output has been completely written.
18558 * When writing a command completion or response to an internal processor,
18559 * the order of writes has to be such that this field is written last.
18562 } __attribute__((packed));
18564 /***************************
18565 * hwrm_queue_pri2cos_qcfg *
18566 ***************************/
18569 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
18570 struct hwrm_queue_pri2cos_qcfg_input {
18571 /* The HWRM command request type. */
18574 * The completion ring to send the completion event on. This should
18575 * be the NQ ID returned from the `nq_alloc` HWRM command.
18577 uint16_t cmpl_ring;
18579 * The sequence ID is used by the driver for tracking multiple
18580 * commands. This ID is treated as opaque data by the firmware and
18581 * the value is returned in the `hwrm_resp_hdr` upon completion.
18585 * The target ID of the command:
18586 * * 0x0-0xFFF8 - The function ID
18587 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18588 * * 0xFFFD - Reserved for user-space HWRM interface
18591 uint16_t target_id;
18593 * A physical address pointer pointing to a host buffer that the
18594 * command's response data will be written. This can be either a host
18595 * physical address (HPA) or a guest physical address (GPA) and must
18596 * point to a physically contiguous block of memory.
18598 uint64_t resp_addr;
18601 * Enumeration denoting the RX, TX type of the resource.
18602 * This enumeration is used for resources that are similar for both
18603 * TX and RX paths of the chip.
18605 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18607 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18609 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18610 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
18611 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
18613 * When this bit is set to '0', the query is
18614 * for VLAN PRI field in tunnel headers.
18615 * When this bit is set to '1', the query is
18616 * for VLAN PRI field in inner packet headers.
18618 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
18620 * Port ID of port for which the table is being configured.
18621 * The HWRM needs to check whether this function is allowed
18622 * to configure pri2cos mapping on this port.
18625 uint8_t unused_0[3];
18626 } __attribute__((packed));
18628 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
18629 struct hwrm_queue_pri2cos_qcfg_output {
18630 /* The specific error status for the command. */
18631 uint16_t error_code;
18632 /* The HWRM command request type. */
18634 /* The sequence ID from the original command. */
18636 /* The length of the response data in number of bytes. */
18639 * CoS Queue assigned to priority 0. This value can only
18640 * be changed before traffic has started.
18641 * A value of 0xff indicates that no CoS queue is assigned to the
18642 * specified priority.
18644 uint8_t pri0_cos_queue_id;
18646 * CoS Queue assigned to priority 1. This value can only
18647 * be changed before traffic has started.
18648 * A value of 0xff indicates that no CoS queue is assigned to the
18649 * specified priority.
18651 uint8_t pri1_cos_queue_id;
18653 * CoS Queue assigned to priority 2 This value can only
18654 * be changed before traffic has started.
18655 * A value of 0xff indicates that no CoS queue is assigned to the
18656 * specified priority.
18658 uint8_t pri2_cos_queue_id;
18660 * CoS Queue assigned to priority 3. This value can only
18661 * be changed before traffic has started.
18662 * A value of 0xff indicates that no CoS queue is assigned to the
18663 * specified priority.
18665 uint8_t pri3_cos_queue_id;
18667 * CoS Queue assigned to priority 4. This value can only
18668 * be changed before traffic has started.
18669 * A value of 0xff indicates that no CoS queue is assigned to the
18670 * specified priority.
18672 uint8_t pri4_cos_queue_id;
18674 * CoS Queue assigned to priority 5. This value can only
18675 * be changed before traffic has started.
18676 * A value of 0xff indicates that no CoS queue is assigned to the
18677 * specified priority.
18679 uint8_t pri5_cos_queue_id;
18681 * CoS Queue assigned to priority 6. This value can only
18682 * be changed before traffic has started.
18683 * A value of 0xff indicates that no CoS queue is assigned to the
18684 * specified priority.
18686 uint8_t pri6_cos_queue_id;
18688 * CoS Queue assigned to priority 7. This value can only
18689 * be changed before traffic has started.
18690 * A value of 0xff indicates that no CoS queue is assigned to the
18691 * specified priority.
18693 uint8_t pri7_cos_queue_id;
18694 /* Information about queue configuration. */
18695 uint8_t queue_cfg_info;
18697 * If this flag is set to '1', then the PRI to CoS
18698 * configuration is asymmetric on TX and RX sides.
18699 * If this flag is set to '0', then PRI to CoS configuration
18700 * is symmetric on TX and RX sides.
18702 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18704 uint8_t unused_0[6];
18706 * This field is used in Output records to indicate that the output
18707 * is completely written to RAM. This field should be read as '1'
18708 * to indicate that the output has been completely written.
18709 * When writing a command completion or response to an internal processor,
18710 * the order of writes has to be such that this field is written last.
18713 } __attribute__((packed));
18715 /**************************
18716 * hwrm_queue_pri2cos_cfg *
18717 **************************/
18720 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
18721 struct hwrm_queue_pri2cos_cfg_input {
18722 /* The HWRM command request type. */
18725 * The completion ring to send the completion event on. This should
18726 * be the NQ ID returned from the `nq_alloc` HWRM command.
18728 uint16_t cmpl_ring;
18730 * The sequence ID is used by the driver for tracking multiple
18731 * commands. This ID is treated as opaque data by the firmware and
18732 * the value is returned in the `hwrm_resp_hdr` upon completion.
18736 * The target ID of the command:
18737 * * 0x0-0xFFF8 - The function ID
18738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18739 * * 0xFFFD - Reserved for user-space HWRM interface
18742 uint16_t target_id;
18744 * A physical address pointer pointing to a host buffer that the
18745 * command's response data will be written. This can be either a host
18746 * physical address (HPA) or a guest physical address (GPA) and must
18747 * point to a physically contiguous block of memory.
18749 uint64_t resp_addr;
18752 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18753 * This enumeration is used for resources that are similar for both
18754 * TX and RX paths of the chip.
18756 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18757 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
18759 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18761 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18762 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18763 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18764 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
18765 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
18767 * When this bit is set to '0', the mapping is requested
18768 * for VLAN PRI field in tunnel headers.
18769 * When this bit is set to '1', the mapping is requested
18770 * for VLAN PRI field in inner packet headers.
18772 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
18775 * This bit must be '1' for the pri0_cos_queue_id field to be
18778 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
18781 * This bit must be '1' for the pri1_cos_queue_id field to be
18784 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
18787 * This bit must be '1' for the pri2_cos_queue_id field to be
18790 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
18793 * This bit must be '1' for the pri3_cos_queue_id field to be
18796 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
18799 * This bit must be '1' for the pri4_cos_queue_id field to be
18802 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
18805 * This bit must be '1' for the pri5_cos_queue_id field to be
18808 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
18811 * This bit must be '1' for the pri6_cos_queue_id field to be
18814 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
18817 * This bit must be '1' for the pri7_cos_queue_id field to be
18820 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
18823 * Port ID of port for which the table is being configured.
18824 * The HWRM needs to check whether this function is allowed
18825 * to configure pri2cos mapping on this port.
18829 * CoS Queue assigned to priority 0. This value can only
18830 * be changed before traffic has started.
18832 uint8_t pri0_cos_queue_id;
18834 * CoS Queue assigned to priority 1. This value can only
18835 * be changed before traffic has started.
18837 uint8_t pri1_cos_queue_id;
18839 * CoS Queue assigned to priority 2 This value can only
18840 * be changed before traffic has started.
18842 uint8_t pri2_cos_queue_id;
18844 * CoS Queue assigned to priority 3. This value can only
18845 * be changed before traffic has started.
18847 uint8_t pri3_cos_queue_id;
18849 * CoS Queue assigned to priority 4. This value can only
18850 * be changed before traffic has started.
18852 uint8_t pri4_cos_queue_id;
18854 * CoS Queue assigned to priority 5. This value can only
18855 * be changed before traffic has started.
18857 uint8_t pri5_cos_queue_id;
18859 * CoS Queue assigned to priority 6. This value can only
18860 * be changed before traffic has started.
18862 uint8_t pri6_cos_queue_id;
18864 * CoS Queue assigned to priority 7. This value can only
18865 * be changed before traffic has started.
18867 uint8_t pri7_cos_queue_id;
18868 uint8_t unused_0[7];
18869 } __attribute__((packed));
18871 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
18872 struct hwrm_queue_pri2cos_cfg_output {
18873 /* The specific error status for the command. */
18874 uint16_t error_code;
18875 /* The HWRM command request type. */
18877 /* The sequence ID from the original command. */
18879 /* The length of the response data in number of bytes. */
18881 uint8_t unused_0[7];
18883 * This field is used in Output records to indicate that the output
18884 * is completely written to RAM. This field should be read as '1'
18885 * to indicate that the output has been completely written.
18886 * When writing a command completion or response to an internal processor,
18887 * the order of writes has to be such that this field is written last.
18890 } __attribute__((packed));
18892 /**************************
18893 * hwrm_queue_cos2bw_qcfg *
18894 **************************/
18897 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
18898 struct hwrm_queue_cos2bw_qcfg_input {
18899 /* The HWRM command request type. */
18902 * The completion ring to send the completion event on. This should
18903 * be the NQ ID returned from the `nq_alloc` HWRM command.
18905 uint16_t cmpl_ring;
18907 * The sequence ID is used by the driver for tracking multiple
18908 * commands. This ID is treated as opaque data by the firmware and
18909 * the value is returned in the `hwrm_resp_hdr` upon completion.
18913 * The target ID of the command:
18914 * * 0x0-0xFFF8 - The function ID
18915 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18916 * * 0xFFFD - Reserved for user-space HWRM interface
18919 uint16_t target_id;
18921 * A physical address pointer pointing to a host buffer that the
18922 * command's response data will be written. This can be either a host
18923 * physical address (HPA) or a guest physical address (GPA) and must
18924 * point to a physically contiguous block of memory.
18926 uint64_t resp_addr;
18928 * Port ID of port for which the table is being configured.
18929 * The HWRM needs to check whether this function is allowed
18930 * to configure TC BW assignment on this port.
18933 uint8_t unused_0[6];
18934 } __attribute__((packed));
18936 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
18937 struct hwrm_queue_cos2bw_qcfg_output {
18938 /* The specific error status for the command. */
18939 uint16_t error_code;
18940 /* The HWRM command request type. */
18942 /* The sequence ID from the original command. */
18944 /* The length of the response data in number of bytes. */
18946 /* ID of CoS Queue 0. */
18951 * Minimum BW allocated to CoS Queue.
18952 * The HWRM will translate this value into byte counter and
18953 * time interval used for this COS inside the device.
18955 uint32_t queue_id0_min_bw;
18956 /* The bandwidth value. */
18957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
18958 UINT32_C(0xfffffff)
18959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
18961 /* The granularity of the value (bits or bytes). */
18962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
18963 UINT32_C(0x10000000)
18964 /* Value is in bits. */
18965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
18966 (UINT32_C(0x0) << 28)
18967 /* Value is in bytes. */
18968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
18969 (UINT32_C(0x1) << 28)
18970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
18971 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
18972 /* bw_value_unit is 3 b */
18973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
18974 UINT32_C(0xe0000000)
18975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
18977 /* Value is in Mb or MB (base 10). */
18978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
18979 (UINT32_C(0x0) << 29)
18980 /* Value is in Kb or KB (base 10). */
18981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
18982 (UINT32_C(0x2) << 29)
18983 /* Value is in bits or bytes. */
18984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
18985 (UINT32_C(0x4) << 29)
18986 /* Value is in Gb or GB (base 10). */
18987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
18988 (UINT32_C(0x6) << 29)
18989 /* Value is in 1/100th of a percentage of total bandwidth. */
18990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18991 (UINT32_C(0x1) << 29)
18993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
18994 (UINT32_C(0x7) << 29)
18995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
18996 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
18998 * Maximum BW allocated to CoS Queue.
18999 * The HWRM will translate this value into byte counter and
19000 * time interval used for this COS inside the device.
19002 uint32_t queue_id0_max_bw;
19003 /* The bandwidth value. */
19004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
19005 UINT32_C(0xfffffff)
19006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
19008 /* The granularity of the value (bits or bytes). */
19009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
19010 UINT32_C(0x10000000)
19011 /* Value is in bits. */
19012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
19013 (UINT32_C(0x0) << 28)
19014 /* Value is in bytes. */
19015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
19016 (UINT32_C(0x1) << 28)
19017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
19018 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
19019 /* bw_value_unit is 3 b */
19020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
19021 UINT32_C(0xe0000000)
19022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
19024 /* Value is in Mb or MB (base 10). */
19025 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
19026 (UINT32_C(0x0) << 29)
19027 /* Value is in Kb or KB (base 10). */
19028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
19029 (UINT32_C(0x2) << 29)
19030 /* Value is in bits or bytes. */
19031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
19032 (UINT32_C(0x4) << 29)
19033 /* Value is in Gb or GB (base 10). */
19034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
19035 (UINT32_C(0x6) << 29)
19036 /* Value is in 1/100th of a percentage of total bandwidth. */
19037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19038 (UINT32_C(0x1) << 29)
19040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
19041 (UINT32_C(0x7) << 29)
19042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
19043 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
19044 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19045 uint8_t queue_id0_tsa_assign;
19046 /* Strict Priority */
19047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
19049 /* Enhanced Transmission Selection */
19050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
19053 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
19056 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
19059 * Priority level for strict priority. Valid only when the
19060 * tsa_assign is 0 - Strict Priority (SP)
19061 * 0..7 - Valid values.
19062 * 8..255 - Reserved.
19064 uint8_t queue_id0_pri_lvl;
19066 * Weight used to allocate remaining BW for this COS after
19067 * servicing guaranteed bandwidths for all COS.
19069 uint8_t queue_id0_bw_weight;
19070 /* ID of CoS Queue 1. */
19073 * Minimum BW allocated to CoS Queue.
19074 * The HWRM will translate this value into byte counter and
19075 * time interval used for this COS inside the device.
19077 uint32_t queue_id1_min_bw;
19078 /* The bandwidth value. */
19079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
19080 UINT32_C(0xfffffff)
19081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
19083 /* The granularity of the value (bits or bytes). */
19084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
19085 UINT32_C(0x10000000)
19086 /* Value is in bits. */
19087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
19088 (UINT32_C(0x0) << 28)
19089 /* Value is in bytes. */
19090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
19091 (UINT32_C(0x1) << 28)
19092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
19093 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
19094 /* bw_value_unit is 3 b */
19095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
19096 UINT32_C(0xe0000000)
19097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
19099 /* Value is in Mb or MB (base 10). */
19100 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
19101 (UINT32_C(0x0) << 29)
19102 /* Value is in Kb or KB (base 10). */
19103 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
19104 (UINT32_C(0x2) << 29)
19105 /* Value is in bits or bytes. */
19106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
19107 (UINT32_C(0x4) << 29)
19108 /* Value is in Gb or GB (base 10). */
19109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
19110 (UINT32_C(0x6) << 29)
19111 /* Value is in 1/100th of a percentage of total bandwidth. */
19112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19113 (UINT32_C(0x1) << 29)
19115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
19116 (UINT32_C(0x7) << 29)
19117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
19118 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
19120 * Maximum BW allocated to CoS queue.
19121 * The HWRM will translate this value into byte counter and
19122 * time interval used for this COS inside the device.
19124 uint32_t queue_id1_max_bw;
19125 /* The bandwidth value. */
19126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
19127 UINT32_C(0xfffffff)
19128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
19130 /* The granularity of the value (bits or bytes). */
19131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
19132 UINT32_C(0x10000000)
19133 /* Value is in bits. */
19134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
19135 (UINT32_C(0x0) << 28)
19136 /* Value is in bytes. */
19137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19138 (UINT32_C(0x1) << 28)
19139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19140 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19141 /* bw_value_unit is 3 b */
19142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19143 UINT32_C(0xe0000000)
19144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19146 /* Value is in Mb or MB (base 10). */
19147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19148 (UINT32_C(0x0) << 29)
19149 /* Value is in Kb or KB (base 10). */
19150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19151 (UINT32_C(0x2) << 29)
19152 /* Value is in bits or bytes. */
19153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19154 (UINT32_C(0x4) << 29)
19155 /* Value is in Gb or GB (base 10). */
19156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19157 (UINT32_C(0x6) << 29)
19158 /* Value is in 1/100th of a percentage of total bandwidth. */
19159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19160 (UINT32_C(0x1) << 29)
19162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19163 (UINT32_C(0x7) << 29)
19164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19165 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19166 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19167 uint8_t queue_id1_tsa_assign;
19168 /* Strict Priority */
19169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19171 /* Enhanced Transmission Selection */
19172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19175 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19178 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19181 * Priority level for strict priority. Valid only when the
19182 * tsa_assign is 0 - Strict Priority (SP)
19183 * 0..7 - Valid values.
19184 * 8..255 - Reserved.
19186 uint8_t queue_id1_pri_lvl;
19188 * Weight used to allocate remaining BW for this COS after
19189 * servicing guaranteed bandwidths for all COS.
19191 uint8_t queue_id1_bw_weight;
19192 /* ID of CoS Queue 2. */
19195 * Minimum BW allocated to CoS Queue.
19196 * The HWRM will translate this value into byte counter and
19197 * time interval used for this COS inside the device.
19199 uint32_t queue_id2_min_bw;
19200 /* The bandwidth value. */
19201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19202 UINT32_C(0xfffffff)
19203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19205 /* The granularity of the value (bits or bytes). */
19206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
19207 UINT32_C(0x10000000)
19208 /* Value is in bits. */
19209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19210 (UINT32_C(0x0) << 28)
19211 /* Value is in bytes. */
19212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19213 (UINT32_C(0x1) << 28)
19214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19215 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19216 /* bw_value_unit is 3 b */
19217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19218 UINT32_C(0xe0000000)
19219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19221 /* Value is in Mb or MB (base 10). */
19222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19223 (UINT32_C(0x0) << 29)
19224 /* Value is in Kb or KB (base 10). */
19225 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19226 (UINT32_C(0x2) << 29)
19227 /* Value is in bits or bytes. */
19228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19229 (UINT32_C(0x4) << 29)
19230 /* Value is in Gb or GB (base 10). */
19231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19232 (UINT32_C(0x6) << 29)
19233 /* Value is in 1/100th of a percentage of total bandwidth. */
19234 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19235 (UINT32_C(0x1) << 29)
19237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19238 (UINT32_C(0x7) << 29)
19239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19240 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19242 * Maximum BW allocated to CoS queue.
19243 * The HWRM will translate this value into byte counter and
19244 * time interval used for this COS inside the device.
19246 uint32_t queue_id2_max_bw;
19247 /* The bandwidth value. */
19248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19249 UINT32_C(0xfffffff)
19250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19252 /* The granularity of the value (bits or bytes). */
19253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
19254 UINT32_C(0x10000000)
19255 /* Value is in bits. */
19256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19257 (UINT32_C(0x0) << 28)
19258 /* Value is in bytes. */
19259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19260 (UINT32_C(0x1) << 28)
19261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19262 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19263 /* bw_value_unit is 3 b */
19264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19265 UINT32_C(0xe0000000)
19266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19268 /* Value is in Mb or MB (base 10). */
19269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19270 (UINT32_C(0x0) << 29)
19271 /* Value is in Kb or KB (base 10). */
19272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19273 (UINT32_C(0x2) << 29)
19274 /* Value is in bits or bytes. */
19275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19276 (UINT32_C(0x4) << 29)
19277 /* Value is in Gb or GB (base 10). */
19278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19279 (UINT32_C(0x6) << 29)
19280 /* Value is in 1/100th of a percentage of total bandwidth. */
19281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19282 (UINT32_C(0x1) << 29)
19284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19285 (UINT32_C(0x7) << 29)
19286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19287 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19288 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19289 uint8_t queue_id2_tsa_assign;
19290 /* Strict Priority */
19291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19293 /* Enhanced Transmission Selection */
19294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19297 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19300 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
19303 * Priority level for strict priority. Valid only when the
19304 * tsa_assign is 0 - Strict Priority (SP)
19305 * 0..7 - Valid values.
19306 * 8..255 - Reserved.
19308 uint8_t queue_id2_pri_lvl;
19310 * Weight used to allocate remaining BW for this COS after
19311 * servicing guaranteed bandwidths for all COS.
19313 uint8_t queue_id2_bw_weight;
19314 /* ID of CoS Queue 3. */
19317 * Minimum BW allocated to CoS Queue.
19318 * The HWRM will translate this value into byte counter and
19319 * time interval used for this COS inside the device.
19321 uint32_t queue_id3_min_bw;
19322 /* The bandwidth value. */
19323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
19324 UINT32_C(0xfffffff)
19325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
19327 /* The granularity of the value (bits or bytes). */
19328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
19329 UINT32_C(0x10000000)
19330 /* Value is in bits. */
19331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
19332 (UINT32_C(0x0) << 28)
19333 /* Value is in bytes. */
19334 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
19335 (UINT32_C(0x1) << 28)
19336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
19337 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
19338 /* bw_value_unit is 3 b */
19339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
19340 UINT32_C(0xe0000000)
19341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
19343 /* Value is in Mb or MB (base 10). */
19344 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
19345 (UINT32_C(0x0) << 29)
19346 /* Value is in Kb or KB (base 10). */
19347 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
19348 (UINT32_C(0x2) << 29)
19349 /* Value is in bits or bytes. */
19350 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
19351 (UINT32_C(0x4) << 29)
19352 /* Value is in Gb or GB (base 10). */
19353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
19354 (UINT32_C(0x6) << 29)
19355 /* Value is in 1/100th of a percentage of total bandwidth. */
19356 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19357 (UINT32_C(0x1) << 29)
19359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
19360 (UINT32_C(0x7) << 29)
19361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
19362 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
19364 * Maximum BW allocated to CoS queue.
19365 * The HWRM will translate this value into byte counter and
19366 * time interval used for this COS inside the device.
19368 uint32_t queue_id3_max_bw;
19369 /* The bandwidth value. */
19370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
19371 UINT32_C(0xfffffff)
19372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
19374 /* The granularity of the value (bits or bytes). */
19375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
19376 UINT32_C(0x10000000)
19377 /* Value is in bits. */
19378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
19379 (UINT32_C(0x0) << 28)
19380 /* Value is in bytes. */
19381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
19382 (UINT32_C(0x1) << 28)
19383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
19384 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
19385 /* bw_value_unit is 3 b */
19386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
19387 UINT32_C(0xe0000000)
19388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
19390 /* Value is in Mb or MB (base 10). */
19391 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
19392 (UINT32_C(0x0) << 29)
19393 /* Value is in Kb or KB (base 10). */
19394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
19395 (UINT32_C(0x2) << 29)
19396 /* Value is in bits or bytes. */
19397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
19398 (UINT32_C(0x4) << 29)
19399 /* Value is in Gb or GB (base 10). */
19400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
19401 (UINT32_C(0x6) << 29)
19402 /* Value is in 1/100th of a percentage of total bandwidth. */
19403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19404 (UINT32_C(0x1) << 29)
19406 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
19407 (UINT32_C(0x7) << 29)
19408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
19409 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
19410 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19411 uint8_t queue_id3_tsa_assign;
19412 /* Strict Priority */
19413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
19415 /* Enhanced Transmission Selection */
19416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
19419 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
19422 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
19425 * Priority level for strict priority. Valid only when the
19426 * tsa_assign is 0 - Strict Priority (SP)
19427 * 0..7 - Valid values.
19428 * 8..255 - Reserved.
19430 uint8_t queue_id3_pri_lvl;
19432 * Weight used to allocate remaining BW for this COS after
19433 * servicing guaranteed bandwidths for all COS.
19435 uint8_t queue_id3_bw_weight;
19436 /* ID of CoS Queue 4. */
19439 * Minimum BW allocated to CoS Queue.
19440 * The HWRM will translate this value into byte counter and
19441 * time interval used for this COS inside the device.
19443 uint32_t queue_id4_min_bw;
19444 /* The bandwidth value. */
19445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
19446 UINT32_C(0xfffffff)
19447 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
19449 /* The granularity of the value (bits or bytes). */
19450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
19451 UINT32_C(0x10000000)
19452 /* Value is in bits. */
19453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
19454 (UINT32_C(0x0) << 28)
19455 /* Value is in bytes. */
19456 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
19457 (UINT32_C(0x1) << 28)
19458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
19459 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
19460 /* bw_value_unit is 3 b */
19461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
19462 UINT32_C(0xe0000000)
19463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
19465 /* Value is in Mb or MB (base 10). */
19466 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
19467 (UINT32_C(0x0) << 29)
19468 /* Value is in Kb or KB (base 10). */
19469 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
19470 (UINT32_C(0x2) << 29)
19471 /* Value is in bits or bytes. */
19472 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
19473 (UINT32_C(0x4) << 29)
19474 /* Value is in Gb or GB (base 10). */
19475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
19476 (UINT32_C(0x6) << 29)
19477 /* Value is in 1/100th of a percentage of total bandwidth. */
19478 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19479 (UINT32_C(0x1) << 29)
19481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
19482 (UINT32_C(0x7) << 29)
19483 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
19484 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
19486 * Maximum BW allocated to CoS queue.
19487 * The HWRM will translate this value into byte counter and
19488 * time interval used for this COS inside the device.
19490 uint32_t queue_id4_max_bw;
19491 /* The bandwidth value. */
19492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
19493 UINT32_C(0xfffffff)
19494 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
19496 /* The granularity of the value (bits or bytes). */
19497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
19498 UINT32_C(0x10000000)
19499 /* Value is in bits. */
19500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
19501 (UINT32_C(0x0) << 28)
19502 /* Value is in bytes. */
19503 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
19504 (UINT32_C(0x1) << 28)
19505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
19506 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
19507 /* bw_value_unit is 3 b */
19508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
19509 UINT32_C(0xe0000000)
19510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
19512 /* Value is in Mb or MB (base 10). */
19513 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
19514 (UINT32_C(0x0) << 29)
19515 /* Value is in Kb or KB (base 10). */
19516 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
19517 (UINT32_C(0x2) << 29)
19518 /* Value is in bits or bytes. */
19519 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
19520 (UINT32_C(0x4) << 29)
19521 /* Value is in Gb or GB (base 10). */
19522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
19523 (UINT32_C(0x6) << 29)
19524 /* Value is in 1/100th of a percentage of total bandwidth. */
19525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19526 (UINT32_C(0x1) << 29)
19528 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
19529 (UINT32_C(0x7) << 29)
19530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
19531 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
19532 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19533 uint8_t queue_id4_tsa_assign;
19534 /* Strict Priority */
19535 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
19537 /* Enhanced Transmission Selection */
19538 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
19541 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
19544 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
19547 * Priority level for strict priority. Valid only when the
19548 * tsa_assign is 0 - Strict Priority (SP)
19549 * 0..7 - Valid values.
19550 * 8..255 - Reserved.
19552 uint8_t queue_id4_pri_lvl;
19554 * Weight used to allocate remaining BW for this COS after
19555 * servicing guaranteed bandwidths for all COS.
19557 uint8_t queue_id4_bw_weight;
19558 /* ID of CoS Queue 5. */
19561 * Minimum BW allocated to CoS Queue.
19562 * The HWRM will translate this value into byte counter and
19563 * time interval used for this COS inside the device.
19565 uint32_t queue_id5_min_bw;
19566 /* The bandwidth value. */
19567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
19568 UINT32_C(0xfffffff)
19569 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
19571 /* The granularity of the value (bits or bytes). */
19572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
19573 UINT32_C(0x10000000)
19574 /* Value is in bits. */
19575 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
19576 (UINT32_C(0x0) << 28)
19577 /* Value is in bytes. */
19578 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
19579 (UINT32_C(0x1) << 28)
19580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
19581 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
19582 /* bw_value_unit is 3 b */
19583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
19584 UINT32_C(0xe0000000)
19585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
19587 /* Value is in Mb or MB (base 10). */
19588 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
19589 (UINT32_C(0x0) << 29)
19590 /* Value is in Kb or KB (base 10). */
19591 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
19592 (UINT32_C(0x2) << 29)
19593 /* Value is in bits or bytes. */
19594 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
19595 (UINT32_C(0x4) << 29)
19596 /* Value is in Gb or GB (base 10). */
19597 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
19598 (UINT32_C(0x6) << 29)
19599 /* Value is in 1/100th of a percentage of total bandwidth. */
19600 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19601 (UINT32_C(0x1) << 29)
19603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
19604 (UINT32_C(0x7) << 29)
19605 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
19606 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
19608 * Maximum BW allocated to CoS queue.
19609 * The HWRM will translate this value into byte counter and
19610 * time interval used for this COS inside the device.
19612 uint32_t queue_id5_max_bw;
19613 /* The bandwidth value. */
19614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
19615 UINT32_C(0xfffffff)
19616 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
19618 /* The granularity of the value (bits or bytes). */
19619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
19620 UINT32_C(0x10000000)
19621 /* Value is in bits. */
19622 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
19623 (UINT32_C(0x0) << 28)
19624 /* Value is in bytes. */
19625 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
19626 (UINT32_C(0x1) << 28)
19627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
19628 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
19629 /* bw_value_unit is 3 b */
19630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
19631 UINT32_C(0xe0000000)
19632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
19634 /* Value is in Mb or MB (base 10). */
19635 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
19636 (UINT32_C(0x0) << 29)
19637 /* Value is in Kb or KB (base 10). */
19638 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
19639 (UINT32_C(0x2) << 29)
19640 /* Value is in bits or bytes. */
19641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
19642 (UINT32_C(0x4) << 29)
19643 /* Value is in Gb or GB (base 10). */
19644 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
19645 (UINT32_C(0x6) << 29)
19646 /* Value is in 1/100th of a percentage of total bandwidth. */
19647 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19648 (UINT32_C(0x1) << 29)
19650 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
19651 (UINT32_C(0x7) << 29)
19652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
19653 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
19654 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19655 uint8_t queue_id5_tsa_assign;
19656 /* Strict Priority */
19657 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
19659 /* Enhanced Transmission Selection */
19660 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
19663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
19666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
19669 * Priority level for strict priority. Valid only when the
19670 * tsa_assign is 0 - Strict Priority (SP)
19671 * 0..7 - Valid values.
19672 * 8..255 - Reserved.
19674 uint8_t queue_id5_pri_lvl;
19676 * Weight used to allocate remaining BW for this COS after
19677 * servicing guaranteed bandwidths for all COS.
19679 uint8_t queue_id5_bw_weight;
19680 /* ID of CoS Queue 6. */
19683 * Minimum BW allocated to CoS Queue.
19684 * The HWRM will translate this value into byte counter and
19685 * time interval used for this COS inside the device.
19687 uint32_t queue_id6_min_bw;
19688 /* The bandwidth value. */
19689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
19690 UINT32_C(0xfffffff)
19691 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
19693 /* The granularity of the value (bits or bytes). */
19694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
19695 UINT32_C(0x10000000)
19696 /* Value is in bits. */
19697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
19698 (UINT32_C(0x0) << 28)
19699 /* Value is in bytes. */
19700 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
19701 (UINT32_C(0x1) << 28)
19702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
19703 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
19704 /* bw_value_unit is 3 b */
19705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
19706 UINT32_C(0xe0000000)
19707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
19709 /* Value is in Mb or MB (base 10). */
19710 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
19711 (UINT32_C(0x0) << 29)
19712 /* Value is in Kb or KB (base 10). */
19713 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
19714 (UINT32_C(0x2) << 29)
19715 /* Value is in bits or bytes. */
19716 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
19717 (UINT32_C(0x4) << 29)
19718 /* Value is in Gb or GB (base 10). */
19719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
19720 (UINT32_C(0x6) << 29)
19721 /* Value is in 1/100th of a percentage of total bandwidth. */
19722 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19723 (UINT32_C(0x1) << 29)
19725 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
19726 (UINT32_C(0x7) << 29)
19727 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
19728 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
19730 * Maximum BW allocated to CoS queue.
19731 * The HWRM will translate this value into byte counter and
19732 * time interval used for this COS inside the device.
19734 uint32_t queue_id6_max_bw;
19735 /* The bandwidth value. */
19736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
19737 UINT32_C(0xfffffff)
19738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
19740 /* The granularity of the value (bits or bytes). */
19741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
19742 UINT32_C(0x10000000)
19743 /* Value is in bits. */
19744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
19745 (UINT32_C(0x0) << 28)
19746 /* Value is in bytes. */
19747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
19748 (UINT32_C(0x1) << 28)
19749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
19750 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
19751 /* bw_value_unit is 3 b */
19752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
19753 UINT32_C(0xe0000000)
19754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
19756 /* Value is in Mb or MB (base 10). */
19757 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
19758 (UINT32_C(0x0) << 29)
19759 /* Value is in Kb or KB (base 10). */
19760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
19761 (UINT32_C(0x2) << 29)
19762 /* Value is in bits or bytes. */
19763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
19764 (UINT32_C(0x4) << 29)
19765 /* Value is in Gb or GB (base 10). */
19766 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
19767 (UINT32_C(0x6) << 29)
19768 /* Value is in 1/100th of a percentage of total bandwidth. */
19769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19770 (UINT32_C(0x1) << 29)
19772 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
19773 (UINT32_C(0x7) << 29)
19774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
19775 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
19776 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19777 uint8_t queue_id6_tsa_assign;
19778 /* Strict Priority */
19779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
19781 /* Enhanced Transmission Selection */
19782 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
19785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
19788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
19791 * Priority level for strict priority. Valid only when the
19792 * tsa_assign is 0 - Strict Priority (SP)
19793 * 0..7 - Valid values.
19794 * 8..255 - Reserved.
19796 uint8_t queue_id6_pri_lvl;
19798 * Weight used to allocate remaining BW for this COS after
19799 * servicing guaranteed bandwidths for all COS.
19801 uint8_t queue_id6_bw_weight;
19802 /* ID of CoS Queue 7. */
19805 * Minimum BW allocated to CoS Queue.
19806 * The HWRM will translate this value into byte counter and
19807 * time interval used for this COS inside the device.
19809 uint32_t queue_id7_min_bw;
19810 /* The bandwidth value. */
19811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
19812 UINT32_C(0xfffffff)
19813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
19815 /* The granularity of the value (bits or bytes). */
19816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
19817 UINT32_C(0x10000000)
19818 /* Value is in bits. */
19819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
19820 (UINT32_C(0x0) << 28)
19821 /* Value is in bytes. */
19822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
19823 (UINT32_C(0x1) << 28)
19824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
19825 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
19826 /* bw_value_unit is 3 b */
19827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
19828 UINT32_C(0xe0000000)
19829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
19831 /* Value is in Mb or MB (base 10). */
19832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
19833 (UINT32_C(0x0) << 29)
19834 /* Value is in Kb or KB (base 10). */
19835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
19836 (UINT32_C(0x2) << 29)
19837 /* Value is in bits or bytes. */
19838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
19839 (UINT32_C(0x4) << 29)
19840 /* Value is in Gb or GB (base 10). */
19841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
19842 (UINT32_C(0x6) << 29)
19843 /* Value is in 1/100th of a percentage of total bandwidth. */
19844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19845 (UINT32_C(0x1) << 29)
19847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
19848 (UINT32_C(0x7) << 29)
19849 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
19850 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
19852 * Maximum BW allocated to CoS queue.
19853 * The HWRM will translate this value into byte counter and
19854 * time interval used for this COS inside the device.
19856 uint32_t queue_id7_max_bw;
19857 /* The bandwidth value. */
19858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
19859 UINT32_C(0xfffffff)
19860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
19862 /* The granularity of the value (bits or bytes). */
19863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
19864 UINT32_C(0x10000000)
19865 /* Value is in bits. */
19866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
19867 (UINT32_C(0x0) << 28)
19868 /* Value is in bytes. */
19869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
19870 (UINT32_C(0x1) << 28)
19871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
19872 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
19873 /* bw_value_unit is 3 b */
19874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
19875 UINT32_C(0xe0000000)
19876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
19878 /* Value is in Mb or MB (base 10). */
19879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
19880 (UINT32_C(0x0) << 29)
19881 /* Value is in Kb or KB (base 10). */
19882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
19883 (UINT32_C(0x2) << 29)
19884 /* Value is in bits or bytes. */
19885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
19886 (UINT32_C(0x4) << 29)
19887 /* Value is in Gb or GB (base 10). */
19888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
19889 (UINT32_C(0x6) << 29)
19890 /* Value is in 1/100th of a percentage of total bandwidth. */
19891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19892 (UINT32_C(0x1) << 29)
19894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
19895 (UINT32_C(0x7) << 29)
19896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
19897 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
19898 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19899 uint8_t queue_id7_tsa_assign;
19900 /* Strict Priority */
19901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
19903 /* Enhanced Transmission Selection */
19904 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
19907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
19910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
19913 * Priority level for strict priority. Valid only when the
19914 * tsa_assign is 0 - Strict Priority (SP)
19915 * 0..7 - Valid values.
19916 * 8..255 - Reserved.
19918 uint8_t queue_id7_pri_lvl;
19920 * Weight used to allocate remaining BW for this COS after
19921 * servicing guaranteed bandwidths for all COS.
19923 uint8_t queue_id7_bw_weight;
19924 uint8_t unused_2[4];
19926 * This field is used in Output records to indicate that the output
19927 * is completely written to RAM. This field should be read as '1'
19928 * to indicate that the output has been completely written.
19929 * When writing a command completion or response to an internal processor,
19930 * the order of writes has to be such that this field is written last.
19933 } __attribute__((packed));
19935 /*************************
19936 * hwrm_queue_cos2bw_cfg *
19937 *************************/
19940 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
19941 struct hwrm_queue_cos2bw_cfg_input {
19942 /* The HWRM command request type. */
19945 * The completion ring to send the completion event on. This should
19946 * be the NQ ID returned from the `nq_alloc` HWRM command.
19948 uint16_t cmpl_ring;
19950 * The sequence ID is used by the driver for tracking multiple
19951 * commands. This ID is treated as opaque data by the firmware and
19952 * the value is returned in the `hwrm_resp_hdr` upon completion.
19956 * The target ID of the command:
19957 * * 0x0-0xFFF8 - The function ID
19958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19959 * * 0xFFFD - Reserved for user-space HWRM interface
19962 uint16_t target_id;
19964 * A physical address pointer pointing to a host buffer that the
19965 * command's response data will be written. This can be either a host
19966 * physical address (HPA) or a guest physical address (GPA) and must
19967 * point to a physically contiguous block of memory.
19969 uint64_t resp_addr;
19973 * If this bit is set to 1, then all queue_id0 related
19974 * parameters in this command are valid.
19976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
19979 * If this bit is set to 1, then all queue_id1 related
19980 * parameters in this command are valid.
19982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
19985 * If this bit is set to 1, then all queue_id2 related
19986 * parameters in this command are valid.
19988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
19991 * If this bit is set to 1, then all queue_id3 related
19992 * parameters in this command are valid.
19994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
19997 * If this bit is set to 1, then all queue_id4 related
19998 * parameters in this command are valid.
20000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
20003 * If this bit is set to 1, then all queue_id5 related
20004 * parameters in this command are valid.
20006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
20009 * If this bit is set to 1, then all queue_id6 related
20010 * parameters in this command are valid.
20012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
20015 * If this bit is set to 1, then all queue_id7 related
20016 * parameters in this command are valid.
20018 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
20021 * Port ID of port for which the table is being configured.
20022 * The HWRM needs to check whether this function is allowed
20023 * to configure TC BW assignment on this port.
20026 /* ID of CoS Queue 0. */
20030 * Minimum BW allocated to CoS Queue.
20031 * The HWRM will translate this value into byte counter and
20032 * time interval used for this COS inside the device.
20034 uint32_t queue_id0_min_bw;
20035 /* The bandwidth value. */
20036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
20037 UINT32_C(0xfffffff)
20038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
20040 /* The granularity of the value (bits or bytes). */
20041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
20042 UINT32_C(0x10000000)
20043 /* Value is in bits. */
20044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
20045 (UINT32_C(0x0) << 28)
20046 /* Value is in bytes. */
20047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
20048 (UINT32_C(0x1) << 28)
20049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
20050 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
20051 /* bw_value_unit is 3 b */
20052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
20053 UINT32_C(0xe0000000)
20054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
20056 /* Value is in Mb or MB (base 10). */
20057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
20058 (UINT32_C(0x0) << 29)
20059 /* Value is in Kb or KB (base 10). */
20060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
20061 (UINT32_C(0x2) << 29)
20062 /* Value is in bits or bytes. */
20063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
20064 (UINT32_C(0x4) << 29)
20065 /* Value is in Gb or GB (base 10). */
20066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
20067 (UINT32_C(0x6) << 29)
20068 /* Value is in 1/100th of a percentage of total bandwidth. */
20069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20070 (UINT32_C(0x1) << 29)
20072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
20073 (UINT32_C(0x7) << 29)
20074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
20075 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
20077 * Maximum BW allocated to CoS Queue.
20078 * The HWRM will translate this value into byte counter and
20079 * time interval used for this COS inside the device.
20081 uint32_t queue_id0_max_bw;
20082 /* The bandwidth value. */
20083 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
20084 UINT32_C(0xfffffff)
20085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
20087 /* The granularity of the value (bits or bytes). */
20088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
20089 UINT32_C(0x10000000)
20090 /* Value is in bits. */
20091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
20092 (UINT32_C(0x0) << 28)
20093 /* Value is in bytes. */
20094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
20095 (UINT32_C(0x1) << 28)
20096 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
20097 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
20098 /* bw_value_unit is 3 b */
20099 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
20100 UINT32_C(0xe0000000)
20101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
20103 /* Value is in Mb or MB (base 10). */
20104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
20105 (UINT32_C(0x0) << 29)
20106 /* Value is in Kb or KB (base 10). */
20107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
20108 (UINT32_C(0x2) << 29)
20109 /* Value is in bits or bytes. */
20110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
20111 (UINT32_C(0x4) << 29)
20112 /* Value is in Gb or GB (base 10). */
20113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
20114 (UINT32_C(0x6) << 29)
20115 /* Value is in 1/100th of a percentage of total bandwidth. */
20116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20117 (UINT32_C(0x1) << 29)
20119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
20120 (UINT32_C(0x7) << 29)
20121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
20122 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
20123 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20124 uint8_t queue_id0_tsa_assign;
20125 /* Strict Priority */
20126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
20128 /* Enhanced Transmission Selection */
20129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
20132 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
20135 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
20138 * Priority level for strict priority. Valid only when the
20139 * tsa_assign is 0 - Strict Priority (SP)
20140 * 0..7 - Valid values.
20141 * 8..255 - Reserved.
20143 uint8_t queue_id0_pri_lvl;
20145 * Weight used to allocate remaining BW for this COS after
20146 * servicing guaranteed bandwidths for all COS.
20148 uint8_t queue_id0_bw_weight;
20149 /* ID of CoS Queue 1. */
20152 * Minimum BW allocated to CoS Queue.
20153 * The HWRM will translate this value into byte counter and
20154 * time interval used for this COS inside the device.
20156 uint32_t queue_id1_min_bw;
20157 /* The bandwidth value. */
20158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
20159 UINT32_C(0xfffffff)
20160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
20162 /* The granularity of the value (bits or bytes). */
20163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
20164 UINT32_C(0x10000000)
20165 /* Value is in bits. */
20166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
20167 (UINT32_C(0x0) << 28)
20168 /* Value is in bytes. */
20169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
20170 (UINT32_C(0x1) << 28)
20171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
20172 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
20173 /* bw_value_unit is 3 b */
20174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
20175 UINT32_C(0xe0000000)
20176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
20178 /* Value is in Mb or MB (base 10). */
20179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
20180 (UINT32_C(0x0) << 29)
20181 /* Value is in Kb or KB (base 10). */
20182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
20183 (UINT32_C(0x2) << 29)
20184 /* Value is in bits or bytes. */
20185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
20186 (UINT32_C(0x4) << 29)
20187 /* Value is in Gb or GB (base 10). */
20188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
20189 (UINT32_C(0x6) << 29)
20190 /* Value is in 1/100th of a percentage of total bandwidth. */
20191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20192 (UINT32_C(0x1) << 29)
20194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
20195 (UINT32_C(0x7) << 29)
20196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
20197 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
20199 * Maximum BW allocated to CoS queue.
20200 * The HWRM will translate this value into byte counter and
20201 * time interval used for this COS inside the device.
20203 uint32_t queue_id1_max_bw;
20204 /* The bandwidth value. */
20205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
20206 UINT32_C(0xfffffff)
20207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
20209 /* The granularity of the value (bits or bytes). */
20210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
20211 UINT32_C(0x10000000)
20212 /* Value is in bits. */
20213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
20214 (UINT32_C(0x0) << 28)
20215 /* Value is in bytes. */
20216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
20217 (UINT32_C(0x1) << 28)
20218 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
20219 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
20220 /* bw_value_unit is 3 b */
20221 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
20222 UINT32_C(0xe0000000)
20223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
20225 /* Value is in Mb or MB (base 10). */
20226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
20227 (UINT32_C(0x0) << 29)
20228 /* Value is in Kb or KB (base 10). */
20229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
20230 (UINT32_C(0x2) << 29)
20231 /* Value is in bits or bytes. */
20232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
20233 (UINT32_C(0x4) << 29)
20234 /* Value is in Gb or GB (base 10). */
20235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
20236 (UINT32_C(0x6) << 29)
20237 /* Value is in 1/100th of a percentage of total bandwidth. */
20238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20239 (UINT32_C(0x1) << 29)
20241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
20242 (UINT32_C(0x7) << 29)
20243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
20244 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
20245 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20246 uint8_t queue_id1_tsa_assign;
20247 /* Strict Priority */
20248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
20250 /* Enhanced Transmission Selection */
20251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
20254 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
20257 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
20260 * Priority level for strict priority. Valid only when the
20261 * tsa_assign is 0 - Strict Priority (SP)
20262 * 0..7 - Valid values.
20263 * 8..255 - Reserved.
20265 uint8_t queue_id1_pri_lvl;
20267 * Weight used to allocate remaining BW for this COS after
20268 * servicing guaranteed bandwidths for all COS.
20270 uint8_t queue_id1_bw_weight;
20271 /* ID of CoS Queue 2. */
20274 * Minimum BW allocated to CoS Queue.
20275 * The HWRM will translate this value into byte counter and
20276 * time interval used for this COS inside the device.
20278 uint32_t queue_id2_min_bw;
20279 /* The bandwidth value. */
20280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
20281 UINT32_C(0xfffffff)
20282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
20284 /* The granularity of the value (bits or bytes). */
20285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
20286 UINT32_C(0x10000000)
20287 /* Value is in bits. */
20288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
20289 (UINT32_C(0x0) << 28)
20290 /* Value is in bytes. */
20291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
20292 (UINT32_C(0x1) << 28)
20293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
20294 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
20295 /* bw_value_unit is 3 b */
20296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
20297 UINT32_C(0xe0000000)
20298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
20300 /* Value is in Mb or MB (base 10). */
20301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
20302 (UINT32_C(0x0) << 29)
20303 /* Value is in Kb or KB (base 10). */
20304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
20305 (UINT32_C(0x2) << 29)
20306 /* Value is in bits or bytes. */
20307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
20308 (UINT32_C(0x4) << 29)
20309 /* Value is in Gb or GB (base 10). */
20310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
20311 (UINT32_C(0x6) << 29)
20312 /* Value is in 1/100th of a percentage of total bandwidth. */
20313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20314 (UINT32_C(0x1) << 29)
20316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
20317 (UINT32_C(0x7) << 29)
20318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
20319 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
20321 * Maximum BW allocated to CoS queue.
20322 * The HWRM will translate this value into byte counter and
20323 * time interval used for this COS inside the device.
20325 uint32_t queue_id2_max_bw;
20326 /* The bandwidth value. */
20327 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
20328 UINT32_C(0xfffffff)
20329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
20331 /* The granularity of the value (bits or bytes). */
20332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
20333 UINT32_C(0x10000000)
20334 /* Value is in bits. */
20335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
20336 (UINT32_C(0x0) << 28)
20337 /* Value is in bytes. */
20338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
20339 (UINT32_C(0x1) << 28)
20340 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
20341 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
20342 /* bw_value_unit is 3 b */
20343 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
20344 UINT32_C(0xe0000000)
20345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
20347 /* Value is in Mb or MB (base 10). */
20348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
20349 (UINT32_C(0x0) << 29)
20350 /* Value is in Kb or KB (base 10). */
20351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
20352 (UINT32_C(0x2) << 29)
20353 /* Value is in bits or bytes. */
20354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
20355 (UINT32_C(0x4) << 29)
20356 /* Value is in Gb or GB (base 10). */
20357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
20358 (UINT32_C(0x6) << 29)
20359 /* Value is in 1/100th of a percentage of total bandwidth. */
20360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20361 (UINT32_C(0x1) << 29)
20363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
20364 (UINT32_C(0x7) << 29)
20365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
20366 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
20367 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20368 uint8_t queue_id2_tsa_assign;
20369 /* Strict Priority */
20370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
20372 /* Enhanced Transmission Selection */
20373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
20376 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
20379 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
20382 * Priority level for strict priority. Valid only when the
20383 * tsa_assign is 0 - Strict Priority (SP)
20384 * 0..7 - Valid values.
20385 * 8..255 - Reserved.
20387 uint8_t queue_id2_pri_lvl;
20389 * Weight used to allocate remaining BW for this COS after
20390 * servicing guaranteed bandwidths for all COS.
20392 uint8_t queue_id2_bw_weight;
20393 /* ID of CoS Queue 3. */
20396 * Minimum BW allocated to CoS Queue.
20397 * The HWRM will translate this value into byte counter and
20398 * time interval used for this COS inside the device.
20400 uint32_t queue_id3_min_bw;
20401 /* The bandwidth value. */
20402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
20403 UINT32_C(0xfffffff)
20404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
20406 /* The granularity of the value (bits or bytes). */
20407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
20408 UINT32_C(0x10000000)
20409 /* Value is in bits. */
20410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
20411 (UINT32_C(0x0) << 28)
20412 /* Value is in bytes. */
20413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
20414 (UINT32_C(0x1) << 28)
20415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
20416 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
20417 /* bw_value_unit is 3 b */
20418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
20419 UINT32_C(0xe0000000)
20420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
20422 /* Value is in Mb or MB (base 10). */
20423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
20424 (UINT32_C(0x0) << 29)
20425 /* Value is in Kb or KB (base 10). */
20426 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
20427 (UINT32_C(0x2) << 29)
20428 /* Value is in bits or bytes. */
20429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
20430 (UINT32_C(0x4) << 29)
20431 /* Value is in Gb or GB (base 10). */
20432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
20433 (UINT32_C(0x6) << 29)
20434 /* Value is in 1/100th of a percentage of total bandwidth. */
20435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20436 (UINT32_C(0x1) << 29)
20438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
20439 (UINT32_C(0x7) << 29)
20440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
20441 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
20443 * Maximum BW allocated to CoS queue.
20444 * The HWRM will translate this value into byte counter and
20445 * time interval used for this COS inside the device.
20447 uint32_t queue_id3_max_bw;
20448 /* The bandwidth value. */
20449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
20450 UINT32_C(0xfffffff)
20451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
20453 /* The granularity of the value (bits or bytes). */
20454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
20455 UINT32_C(0x10000000)
20456 /* Value is in bits. */
20457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
20458 (UINT32_C(0x0) << 28)
20459 /* Value is in bytes. */
20460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
20461 (UINT32_C(0x1) << 28)
20462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
20463 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
20464 /* bw_value_unit is 3 b */
20465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
20466 UINT32_C(0xe0000000)
20467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
20469 /* Value is in Mb or MB (base 10). */
20470 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
20471 (UINT32_C(0x0) << 29)
20472 /* Value is in Kb or KB (base 10). */
20473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
20474 (UINT32_C(0x2) << 29)
20475 /* Value is in bits or bytes. */
20476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
20477 (UINT32_C(0x4) << 29)
20478 /* Value is in Gb or GB (base 10). */
20479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
20480 (UINT32_C(0x6) << 29)
20481 /* Value is in 1/100th of a percentage of total bandwidth. */
20482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20483 (UINT32_C(0x1) << 29)
20485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
20486 (UINT32_C(0x7) << 29)
20487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
20488 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
20489 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20490 uint8_t queue_id3_tsa_assign;
20491 /* Strict Priority */
20492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
20494 /* Enhanced Transmission Selection */
20495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
20498 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
20501 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
20504 * Priority level for strict priority. Valid only when the
20505 * tsa_assign is 0 - Strict Priority (SP)
20506 * 0..7 - Valid values.
20507 * 8..255 - Reserved.
20509 uint8_t queue_id3_pri_lvl;
20511 * Weight used to allocate remaining BW for this COS after
20512 * servicing guaranteed bandwidths for all COS.
20514 uint8_t queue_id3_bw_weight;
20515 /* ID of CoS Queue 4. */
20518 * Minimum BW allocated to CoS Queue.
20519 * The HWRM will translate this value into byte counter and
20520 * time interval used for this COS inside the device.
20522 uint32_t queue_id4_min_bw;
20523 /* The bandwidth value. */
20524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
20525 UINT32_C(0xfffffff)
20526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
20528 /* The granularity of the value (bits or bytes). */
20529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
20530 UINT32_C(0x10000000)
20531 /* Value is in bits. */
20532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
20533 (UINT32_C(0x0) << 28)
20534 /* Value is in bytes. */
20535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
20536 (UINT32_C(0x1) << 28)
20537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
20538 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
20539 /* bw_value_unit is 3 b */
20540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
20541 UINT32_C(0xe0000000)
20542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
20544 /* Value is in Mb or MB (base 10). */
20545 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
20546 (UINT32_C(0x0) << 29)
20547 /* Value is in Kb or KB (base 10). */
20548 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
20549 (UINT32_C(0x2) << 29)
20550 /* Value is in bits or bytes. */
20551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
20552 (UINT32_C(0x4) << 29)
20553 /* Value is in Gb or GB (base 10). */
20554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
20555 (UINT32_C(0x6) << 29)
20556 /* Value is in 1/100th of a percentage of total bandwidth. */
20557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20558 (UINT32_C(0x1) << 29)
20560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
20561 (UINT32_C(0x7) << 29)
20562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
20563 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
20565 * Maximum BW allocated to CoS queue.
20566 * The HWRM will translate this value into byte counter and
20567 * time interval used for this COS inside the device.
20569 uint32_t queue_id4_max_bw;
20570 /* The bandwidth value. */
20571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
20572 UINT32_C(0xfffffff)
20573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
20575 /* The granularity of the value (bits or bytes). */
20576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
20577 UINT32_C(0x10000000)
20578 /* Value is in bits. */
20579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
20580 (UINT32_C(0x0) << 28)
20581 /* Value is in bytes. */
20582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
20583 (UINT32_C(0x1) << 28)
20584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
20585 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
20586 /* bw_value_unit is 3 b */
20587 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
20588 UINT32_C(0xe0000000)
20589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
20591 /* Value is in Mb or MB (base 10). */
20592 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
20593 (UINT32_C(0x0) << 29)
20594 /* Value is in Kb or KB (base 10). */
20595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
20596 (UINT32_C(0x2) << 29)
20597 /* Value is in bits or bytes. */
20598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
20599 (UINT32_C(0x4) << 29)
20600 /* Value is in Gb or GB (base 10). */
20601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
20602 (UINT32_C(0x6) << 29)
20603 /* Value is in 1/100th of a percentage of total bandwidth. */
20604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20605 (UINT32_C(0x1) << 29)
20607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
20608 (UINT32_C(0x7) << 29)
20609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
20610 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
20611 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20612 uint8_t queue_id4_tsa_assign;
20613 /* Strict Priority */
20614 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
20616 /* Enhanced Transmission Selection */
20617 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
20620 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
20623 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
20626 * Priority level for strict priority. Valid only when the
20627 * tsa_assign is 0 - Strict Priority (SP)
20628 * 0..7 - Valid values.
20629 * 8..255 - Reserved.
20631 uint8_t queue_id4_pri_lvl;
20633 * Weight used to allocate remaining BW for this COS after
20634 * servicing guaranteed bandwidths for all COS.
20636 uint8_t queue_id4_bw_weight;
20637 /* ID of CoS Queue 5. */
20640 * Minimum BW allocated to CoS Queue.
20641 * The HWRM will translate this value into byte counter and
20642 * time interval used for this COS inside the device.
20644 uint32_t queue_id5_min_bw;
20645 /* The bandwidth value. */
20646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
20647 UINT32_C(0xfffffff)
20648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
20650 /* The granularity of the value (bits or bytes). */
20651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
20652 UINT32_C(0x10000000)
20653 /* Value is in bits. */
20654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
20655 (UINT32_C(0x0) << 28)
20656 /* Value is in bytes. */
20657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
20658 (UINT32_C(0x1) << 28)
20659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
20660 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
20661 /* bw_value_unit is 3 b */
20662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
20663 UINT32_C(0xe0000000)
20664 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
20666 /* Value is in Mb or MB (base 10). */
20667 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
20668 (UINT32_C(0x0) << 29)
20669 /* Value is in Kb or KB (base 10). */
20670 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
20671 (UINT32_C(0x2) << 29)
20672 /* Value is in bits or bytes. */
20673 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
20674 (UINT32_C(0x4) << 29)
20675 /* Value is in Gb or GB (base 10). */
20676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
20677 (UINT32_C(0x6) << 29)
20678 /* Value is in 1/100th of a percentage of total bandwidth. */
20679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20680 (UINT32_C(0x1) << 29)
20682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
20683 (UINT32_C(0x7) << 29)
20684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
20685 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
20687 * Maximum BW allocated to CoS queue.
20688 * The HWRM will translate this value into byte counter and
20689 * time interval used for this COS inside the device.
20691 uint32_t queue_id5_max_bw;
20692 /* The bandwidth value. */
20693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
20694 UINT32_C(0xfffffff)
20695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
20697 /* The granularity of the value (bits or bytes). */
20698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
20699 UINT32_C(0x10000000)
20700 /* Value is in bits. */
20701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
20702 (UINT32_C(0x0) << 28)
20703 /* Value is in bytes. */
20704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
20705 (UINT32_C(0x1) << 28)
20706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
20707 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
20708 /* bw_value_unit is 3 b */
20709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
20710 UINT32_C(0xe0000000)
20711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
20713 /* Value is in Mb or MB (base 10). */
20714 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
20715 (UINT32_C(0x0) << 29)
20716 /* Value is in Kb or KB (base 10). */
20717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
20718 (UINT32_C(0x2) << 29)
20719 /* Value is in bits or bytes. */
20720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
20721 (UINT32_C(0x4) << 29)
20722 /* Value is in Gb or GB (base 10). */
20723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
20724 (UINT32_C(0x6) << 29)
20725 /* Value is in 1/100th of a percentage of total bandwidth. */
20726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20727 (UINT32_C(0x1) << 29)
20729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
20730 (UINT32_C(0x7) << 29)
20731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
20732 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
20733 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20734 uint8_t queue_id5_tsa_assign;
20735 /* Strict Priority */
20736 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
20738 /* Enhanced Transmission Selection */
20739 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
20742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
20745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
20748 * Priority level for strict priority. Valid only when the
20749 * tsa_assign is 0 - Strict Priority (SP)
20750 * 0..7 - Valid values.
20751 * 8..255 - Reserved.
20753 uint8_t queue_id5_pri_lvl;
20755 * Weight used to allocate remaining BW for this COS after
20756 * servicing guaranteed bandwidths for all COS.
20758 uint8_t queue_id5_bw_weight;
20759 /* ID of CoS Queue 6. */
20762 * Minimum BW allocated to CoS Queue.
20763 * The HWRM will translate this value into byte counter and
20764 * time interval used for this COS inside the device.
20766 uint32_t queue_id6_min_bw;
20767 /* The bandwidth value. */
20768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
20769 UINT32_C(0xfffffff)
20770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
20772 /* The granularity of the value (bits or bytes). */
20773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
20774 UINT32_C(0x10000000)
20775 /* Value is in bits. */
20776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
20777 (UINT32_C(0x0) << 28)
20778 /* Value is in bytes. */
20779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
20780 (UINT32_C(0x1) << 28)
20781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
20782 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
20783 /* bw_value_unit is 3 b */
20784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
20785 UINT32_C(0xe0000000)
20786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
20788 /* Value is in Mb or MB (base 10). */
20789 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
20790 (UINT32_C(0x0) << 29)
20791 /* Value is in Kb or KB (base 10). */
20792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
20793 (UINT32_C(0x2) << 29)
20794 /* Value is in bits or bytes. */
20795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
20796 (UINT32_C(0x4) << 29)
20797 /* Value is in Gb or GB (base 10). */
20798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
20799 (UINT32_C(0x6) << 29)
20800 /* Value is in 1/100th of a percentage of total bandwidth. */
20801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20802 (UINT32_C(0x1) << 29)
20804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
20805 (UINT32_C(0x7) << 29)
20806 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
20807 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
20809 * Maximum BW allocated to CoS queue.
20810 * The HWRM will translate this value into byte counter and
20811 * time interval used for this COS inside the device.
20813 uint32_t queue_id6_max_bw;
20814 /* The bandwidth value. */
20815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
20816 UINT32_C(0xfffffff)
20817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
20819 /* The granularity of the value (bits or bytes). */
20820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
20821 UINT32_C(0x10000000)
20822 /* Value is in bits. */
20823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
20824 (UINT32_C(0x0) << 28)
20825 /* Value is in bytes. */
20826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
20827 (UINT32_C(0x1) << 28)
20828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
20829 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
20830 /* bw_value_unit is 3 b */
20831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
20832 UINT32_C(0xe0000000)
20833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
20835 /* Value is in Mb or MB (base 10). */
20836 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
20837 (UINT32_C(0x0) << 29)
20838 /* Value is in Kb or KB (base 10). */
20839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
20840 (UINT32_C(0x2) << 29)
20841 /* Value is in bits or bytes. */
20842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
20843 (UINT32_C(0x4) << 29)
20844 /* Value is in Gb or GB (base 10). */
20845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
20846 (UINT32_C(0x6) << 29)
20847 /* Value is in 1/100th of a percentage of total bandwidth. */
20848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20849 (UINT32_C(0x1) << 29)
20851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
20852 (UINT32_C(0x7) << 29)
20853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
20854 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
20855 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20856 uint8_t queue_id6_tsa_assign;
20857 /* Strict Priority */
20858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
20860 /* Enhanced Transmission Selection */
20861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
20864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
20867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
20870 * Priority level for strict priority. Valid only when the
20871 * tsa_assign is 0 - Strict Priority (SP)
20872 * 0..7 - Valid values.
20873 * 8..255 - Reserved.
20875 uint8_t queue_id6_pri_lvl;
20877 * Weight used to allocate remaining BW for this COS after
20878 * servicing guaranteed bandwidths for all COS.
20880 uint8_t queue_id6_bw_weight;
20881 /* ID of CoS Queue 7. */
20884 * Minimum BW allocated to CoS Queue.
20885 * The HWRM will translate this value into byte counter and
20886 * time interval used for this COS inside the device.
20888 uint32_t queue_id7_min_bw;
20889 /* The bandwidth value. */
20890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
20891 UINT32_C(0xfffffff)
20892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
20894 /* The granularity of the value (bits or bytes). */
20895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
20896 UINT32_C(0x10000000)
20897 /* Value is in bits. */
20898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
20899 (UINT32_C(0x0) << 28)
20900 /* Value is in bytes. */
20901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
20902 (UINT32_C(0x1) << 28)
20903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
20904 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
20905 /* bw_value_unit is 3 b */
20906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
20907 UINT32_C(0xe0000000)
20908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
20910 /* Value is in Mb or MB (base 10). */
20911 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
20912 (UINT32_C(0x0) << 29)
20913 /* Value is in Kb or KB (base 10). */
20914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
20915 (UINT32_C(0x2) << 29)
20916 /* Value is in bits or bytes. */
20917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
20918 (UINT32_C(0x4) << 29)
20919 /* Value is in Gb or GB (base 10). */
20920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
20921 (UINT32_C(0x6) << 29)
20922 /* Value is in 1/100th of a percentage of total bandwidth. */
20923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20924 (UINT32_C(0x1) << 29)
20926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
20927 (UINT32_C(0x7) << 29)
20928 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
20929 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
20931 * Maximum BW allocated to CoS queue.
20932 * The HWRM will translate this value into byte counter and
20933 * time interval used for this COS inside the device.
20935 uint32_t queue_id7_max_bw;
20936 /* The bandwidth value. */
20937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
20938 UINT32_C(0xfffffff)
20939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
20941 /* The granularity of the value (bits or bytes). */
20942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
20943 UINT32_C(0x10000000)
20944 /* Value is in bits. */
20945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
20946 (UINT32_C(0x0) << 28)
20947 /* Value is in bytes. */
20948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
20949 (UINT32_C(0x1) << 28)
20950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
20951 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
20952 /* bw_value_unit is 3 b */
20953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
20954 UINT32_C(0xe0000000)
20955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
20957 /* Value is in Mb or MB (base 10). */
20958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
20959 (UINT32_C(0x0) << 29)
20960 /* Value is in Kb or KB (base 10). */
20961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
20962 (UINT32_C(0x2) << 29)
20963 /* Value is in bits or bytes. */
20964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
20965 (UINT32_C(0x4) << 29)
20966 /* Value is in Gb or GB (base 10). */
20967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
20968 (UINT32_C(0x6) << 29)
20969 /* Value is in 1/100th of a percentage of total bandwidth. */
20970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20971 (UINT32_C(0x1) << 29)
20973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
20974 (UINT32_C(0x7) << 29)
20975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
20976 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
20977 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20978 uint8_t queue_id7_tsa_assign;
20979 /* Strict Priority */
20980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
20982 /* Enhanced Transmission Selection */
20983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
20986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
20989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
20992 * Priority level for strict priority. Valid only when the
20993 * tsa_assign is 0 - Strict Priority (SP)
20994 * 0..7 - Valid values.
20995 * 8..255 - Reserved.
20997 uint8_t queue_id7_pri_lvl;
20999 * Weight used to allocate remaining BW for this COS after
21000 * servicing guaranteed bandwidths for all COS.
21002 uint8_t queue_id7_bw_weight;
21003 uint8_t unused_1[5];
21004 } __attribute__((packed));
21006 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
21007 struct hwrm_queue_cos2bw_cfg_output {
21008 /* The specific error status for the command. */
21009 uint16_t error_code;
21010 /* The HWRM command request type. */
21012 /* The sequence ID from the original command. */
21014 /* The length of the response data in number of bytes. */
21016 uint8_t unused_0[7];
21018 * This field is used in Output records to indicate that the output
21019 * is completely written to RAM. This field should be read as '1'
21020 * to indicate that the output has been completely written.
21021 * When writing a command completion or response to an internal processor,
21022 * the order of writes has to be such that this field is written last.
21025 } __attribute__((packed));
21027 /*******************
21028 * hwrm_vnic_alloc *
21029 *******************/
21032 /* hwrm_vnic_alloc_input (size:192b/24B) */
21033 struct hwrm_vnic_alloc_input {
21034 /* The HWRM command request type. */
21037 * The completion ring to send the completion event on. This should
21038 * be the NQ ID returned from the `nq_alloc` HWRM command.
21040 uint16_t cmpl_ring;
21042 * The sequence ID is used by the driver for tracking multiple
21043 * commands. This ID is treated as opaque data by the firmware and
21044 * the value is returned in the `hwrm_resp_hdr` upon completion.
21048 * The target ID of the command:
21049 * * 0x0-0xFFF8 - The function ID
21050 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21051 * * 0xFFFD - Reserved for user-space HWRM interface
21054 uint16_t target_id;
21056 * A physical address pointer pointing to a host buffer that the
21057 * command's response data will be written. This can be either a host
21058 * physical address (HPA) or a guest physical address (GPA) and must
21059 * point to a physically contiguous block of memory.
21061 uint64_t resp_addr;
21064 * When this bit is '1', this VNIC is requested to
21065 * be the default VNIC for this function.
21067 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
21068 uint8_t unused_0[4];
21069 } __attribute__((packed));
21071 /* hwrm_vnic_alloc_output (size:128b/16B) */
21072 struct hwrm_vnic_alloc_output {
21073 /* The specific error status for the command. */
21074 uint16_t error_code;
21075 /* The HWRM command request type. */
21077 /* The sequence ID from the original command. */
21079 /* The length of the response data in number of bytes. */
21081 /* Logical vnic ID */
21083 uint8_t unused_0[3];
21085 * This field is used in Output records to indicate that the output
21086 * is completely written to RAM. This field should be read as '1'
21087 * to indicate that the output has been completely written.
21088 * When writing a command completion or response to an internal processor,
21089 * the order of writes has to be such that this field is written last.
21092 } __attribute__((packed));
21094 /******************
21096 ******************/
21099 /* hwrm_vnic_free_input (size:192b/24B) */
21100 struct hwrm_vnic_free_input {
21101 /* The HWRM command request type. */
21104 * The completion ring to send the completion event on. This should
21105 * be the NQ ID returned from the `nq_alloc` HWRM command.
21107 uint16_t cmpl_ring;
21109 * The sequence ID is used by the driver for tracking multiple
21110 * commands. This ID is treated as opaque data by the firmware and
21111 * the value is returned in the `hwrm_resp_hdr` upon completion.
21115 * The target ID of the command:
21116 * * 0x0-0xFFF8 - The function ID
21117 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21118 * * 0xFFFD - Reserved for user-space HWRM interface
21121 uint16_t target_id;
21123 * A physical address pointer pointing to a host buffer that the
21124 * command's response data will be written. This can be either a host
21125 * physical address (HPA) or a guest physical address (GPA) and must
21126 * point to a physically contiguous block of memory.
21128 uint64_t resp_addr;
21129 /* Logical vnic ID */
21131 uint8_t unused_0[4];
21132 } __attribute__((packed));
21134 /* hwrm_vnic_free_output (size:128b/16B) */
21135 struct hwrm_vnic_free_output {
21136 /* The specific error status for the command. */
21137 uint16_t error_code;
21138 /* The HWRM command request type. */
21140 /* The sequence ID from the original command. */
21142 /* The length of the response data in number of bytes. */
21144 uint8_t unused_0[7];
21146 * This field is used in Output records to indicate that the output
21147 * is completely written to RAM. This field should be read as '1'
21148 * to indicate that the output has been completely written.
21149 * When writing a command completion or response to an internal processor,
21150 * the order of writes has to be such that this field is written last.
21153 } __attribute__((packed));
21160 /* hwrm_vnic_cfg_input (size:320b/40B) */
21161 struct hwrm_vnic_cfg_input {
21162 /* The HWRM command request type. */
21165 * The completion ring to send the completion event on. This should
21166 * be the NQ ID returned from the `nq_alloc` HWRM command.
21168 uint16_t cmpl_ring;
21170 * The sequence ID is used by the driver for tracking multiple
21171 * commands. This ID is treated as opaque data by the firmware and
21172 * the value is returned in the `hwrm_resp_hdr` upon completion.
21176 * The target ID of the command:
21177 * * 0x0-0xFFF8 - The function ID
21178 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21179 * * 0xFFFD - Reserved for user-space HWRM interface
21182 uint16_t target_id;
21184 * A physical address pointer pointing to a host buffer that the
21185 * command's response data will be written. This can be either a host
21186 * physical address (HPA) or a guest physical address (GPA) and must
21187 * point to a physically contiguous block of memory.
21189 uint64_t resp_addr;
21192 * When this bit is '1', the VNIC is requested to
21193 * be the default VNIC for the function.
21195 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
21198 * When this bit is '1', the VNIC is being configured to
21199 * strip VLAN in the RX path.
21200 * If set to '0', then VLAN stripping is disabled on
21203 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
21206 * When this bit is '1', the VNIC is being configured to
21207 * buffer receive packets in the hardware until the host
21208 * posts new receive buffers.
21209 * If set to '0', then bd_stall is being configured to be
21210 * disabled on this VNIC.
21212 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
21215 * When this bit is '1', the VNIC is being configured to
21216 * receive both RoCE and non-RoCE traffic.
21217 * If set to '0', then this VNIC is not configured to be
21218 * operating in dual VNIC mode.
21220 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21223 * When this flag is set to '1', the VNIC is requested to
21224 * be configured to receive only RoCE traffic.
21225 * If this flag is set to '0', then this flag shall be
21226 * ignored by the HWRM.
21227 * If roce_dual_vnic_mode flag is set to '1'
21228 * or roce_mirroring_capable_vnic_mode flag to 1,
21229 * then the HWRM client shall not set this flag to '1'.
21231 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21234 * When a VNIC uses one destination ring group for certain
21235 * application (e.g. Receive Flow Steering) where
21236 * exact match is used to direct packets to a VNIC with one
21237 * destination ring group only, there is no need to configure
21238 * RSS indirection table for that VNIC as only one destination
21239 * ring group is used.
21241 * This flag is used to enable a mode where
21242 * RSS is enabled in the VNIC using a RSS context
21243 * for computing RSS hash but the RSS indirection table is
21244 * not configured using hwrm_vnic_rss_cfg.
21246 * If this mode is enabled, then the driver should not program
21247 * RSS indirection table for the RSS context that is used for
21248 * computing RSS hash only.
21250 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
21253 * When this bit is '1', the VNIC is being configured to
21254 * receive both RoCE and non-RoCE traffic, but forward only the
21255 * RoCE traffic further. Also, RoCE traffic can be mirrored to
21258 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21262 * This bit must be '1' for the dflt_ring_grp field to be
21265 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
21268 * This bit must be '1' for the rss_rule field to be
21271 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
21274 * This bit must be '1' for the cos_rule field to be
21277 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
21280 * This bit must be '1' for the lb_rule field to be
21283 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
21286 * This bit must be '1' for the mru field to be
21289 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
21292 * This bit must be '1' for the default_rx_ring_id field to be
21295 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
21298 * This bit must be '1' for the default_cmpl_ring_id field to be
21301 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
21303 /* Logical vnic ID */
21306 * Default Completion ring for the VNIC. This ring will
21307 * be chosen if packet does not match any RSS rules and if
21308 * there is no COS rule.
21310 uint16_t dflt_ring_grp;
21312 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21313 * there is no RSS rule.
21317 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21318 * there is no COS rule.
21322 * RSS ID for load balancing rule/table structure.
21323 * 0xFF... (All Fs) if there is no LB rule.
21327 * The maximum receive unit of the vnic.
21328 * Each vnic is associated with a function.
21329 * The vnic mru value overwrites the mru setting of the
21330 * associated function.
21331 * The HWRM shall make sure that vnic mru does not exceed
21332 * the mru of the port the function is associated with.
21336 * Default Rx ring for the VNIC. This ring will
21337 * be chosen if packet does not match any RSS rules.
21338 * The aggregation ring associated with the Rx ring is
21339 * implied based on the Rx ring specified when the
21340 * aggregation ring was allocated.
21342 uint16_t default_rx_ring_id;
21344 * Default completion ring for the VNIC. This ring will
21345 * be chosen if packet does not match any RSS rules.
21347 uint16_t default_cmpl_ring_id;
21348 } __attribute__((packed));
21350 /* hwrm_vnic_cfg_output (size:128b/16B) */
21351 struct hwrm_vnic_cfg_output {
21352 /* The specific error status for the command. */
21353 uint16_t error_code;
21354 /* The HWRM command request type. */
21356 /* The sequence ID from the original command. */
21358 /* The length of the response data in number of bytes. */
21360 uint8_t unused_0[7];
21362 * This field is used in Output records to indicate that the output
21363 * is completely written to RAM. This field should be read as '1'
21364 * to indicate that the output has been completely written.
21365 * When writing a command completion or response to an internal processor,
21366 * the order of writes has to be such that this field is written last.
21369 } __attribute__((packed));
21371 /******************
21373 ******************/
21376 /* hwrm_vnic_qcfg_input (size:256b/32B) */
21377 struct hwrm_vnic_qcfg_input {
21378 /* The HWRM command request type. */
21381 * The completion ring to send the completion event on. This should
21382 * be the NQ ID returned from the `nq_alloc` HWRM command.
21384 uint16_t cmpl_ring;
21386 * The sequence ID is used by the driver for tracking multiple
21387 * commands. This ID is treated as opaque data by the firmware and
21388 * the value is returned in the `hwrm_resp_hdr` upon completion.
21392 * The target ID of the command:
21393 * * 0x0-0xFFF8 - The function ID
21394 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21395 * * 0xFFFD - Reserved for user-space HWRM interface
21398 uint16_t target_id;
21400 * A physical address pointer pointing to a host buffer that the
21401 * command's response data will be written. This can be either a host
21402 * physical address (HPA) or a guest physical address (GPA) and must
21403 * point to a physically contiguous block of memory.
21405 uint64_t resp_addr;
21408 * This bit must be '1' for the vf_id_valid field to be
21411 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
21412 /* Logical vnic ID */
21414 /* ID of Virtual Function whose VNIC resource is being queried. */
21416 uint8_t unused_0[6];
21417 } __attribute__((packed));
21419 /* hwrm_vnic_qcfg_output (size:256b/32B) */
21420 struct hwrm_vnic_qcfg_output {
21421 /* The specific error status for the command. */
21422 uint16_t error_code;
21423 /* The HWRM command request type. */
21425 /* The sequence ID from the original command. */
21427 /* The length of the response data in number of bytes. */
21429 /* Default Completion ring for the VNIC. */
21430 uint16_t dflt_ring_grp;
21432 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21433 * there is no RSS rule.
21437 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21438 * there is no COS rule.
21442 * RSS ID for load balancing rule/table structure.
21443 * 0xFF... (All Fs) if there is no LB rule.
21446 /* The maximum receive unit of the vnic. */
21448 uint8_t unused_0[2];
21451 * When this bit is '1', the VNIC is the default VNIC for
21454 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
21457 * When this bit is '1', the VNIC is configured to
21458 * strip VLAN in the RX path.
21459 * If set to '0', then VLAN stripping is disabled on
21462 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
21465 * When this bit is '1', the VNIC is configured to
21466 * buffer receive packets in the hardware until the host
21467 * posts new receive buffers.
21468 * If set to '0', then bd_stall is disabled on
21471 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
21474 * When this bit is '1', the VNIC is configured to
21475 * receive both RoCE and non-RoCE traffic.
21476 * If set to '0', then this VNIC is not configured to
21477 * operate in dual VNIC mode.
21479 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21482 * When this flag is set to '1', the VNIC is configured to
21483 * receive only RoCE traffic.
21484 * When this flag is set to '0', the VNIC is not configured
21485 * to receive only RoCE traffic.
21486 * If roce_dual_vnic_mode flag and this flag both are set
21487 * to '1', then it is an invalid configuration of the
21488 * VNIC. The HWRM should not allow that type of
21489 * mis-configuration by HWRM clients.
21491 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21494 * When a VNIC uses one destination ring group for certain
21495 * application (e.g. Receive Flow Steering) where
21496 * exact match is used to direct packets to a VNIC with one
21497 * destination ring group only, there is no need to configure
21498 * RSS indirection table for that VNIC as only one destination
21499 * ring group is used.
21501 * When this bit is set to '1', then the VNIC is enabled in a
21502 * mode where RSS is enabled in the VNIC using a RSS context
21503 * for computing RSS hash but the RSS indirection table is
21506 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
21509 * When this bit is '1', the VNIC is configured to
21510 * receive both RoCE and non-RoCE traffic, but forward only
21511 * RoCE traffic further. Also RoCE traffic can be mirrored to
21514 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21516 uint8_t unused_1[7];
21518 * This field is used in Output records to indicate that the output
21519 * is completely written to RAM. This field should be read as '1'
21520 * to indicate that the output has been completely written.
21521 * When writing a command completion or response to an internal processor,
21522 * the order of writes has to be such that this field is written last.
21525 } __attribute__((packed));
21527 /*******************
21528 * hwrm_vnic_qcaps *
21529 *******************/
21532 /* hwrm_vnic_qcaps_input (size:192b/24B) */
21533 struct hwrm_vnic_qcaps_input {
21534 /* The HWRM command request type. */
21537 * The completion ring to send the completion event on. This should
21538 * be the NQ ID returned from the `nq_alloc` HWRM command.
21540 uint16_t cmpl_ring;
21542 * The sequence ID is used by the driver for tracking multiple
21543 * commands. This ID is treated as opaque data by the firmware and
21544 * the value is returned in the `hwrm_resp_hdr` upon completion.
21548 * The target ID of the command:
21549 * * 0x0-0xFFF8 - The function ID
21550 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21551 * * 0xFFFD - Reserved for user-space HWRM interface
21554 uint16_t target_id;
21556 * A physical address pointer pointing to a host buffer that the
21557 * command's response data will be written. This can be either a host
21558 * physical address (HPA) or a guest physical address (GPA) and must
21559 * point to a physically contiguous block of memory.
21561 uint64_t resp_addr;
21563 uint8_t unused_0[4];
21564 } __attribute__((packed));
21566 /* hwrm_vnic_qcaps_output (size:192b/24B) */
21567 struct hwrm_vnic_qcaps_output {
21568 /* The specific error status for the command. */
21569 uint16_t error_code;
21570 /* The HWRM command request type. */
21572 /* The sequence ID from the original command. */
21574 /* The length of the response data in number of bytes. */
21576 /* The maximum receive unit that is settable on a vnic. */
21578 uint8_t unused_0[2];
21581 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
21584 * When this bit is '1', the capability of stripping VLAN in
21585 * the RX path is supported on VNIC(s).
21586 * If set to '0', then VLAN stripping capability is
21587 * not supported on VNIC(s).
21589 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
21592 * When this bit is '1', the capability to buffer receive
21593 * packets in the hardware until the host posts new receive buffers
21594 * is supported on VNIC(s).
21595 * If set to '0', then bd_stall capability is not supported
21598 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
21601 * When this bit is '1', the capability to
21602 * receive both RoCE and non-RoCE traffic on VNIC(s) is
21604 * If set to '0', then the capability to receive
21605 * both RoCE and non-RoCE traffic on VNIC(s) is
21608 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
21611 * When this bit is set to '1', the capability to configure
21612 * a VNIC to receive only RoCE traffic is supported.
21613 * When this flag is set to '0', the VNIC capability to
21614 * configure to receive only RoCE traffic is not supported.
21616 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
21619 * When this bit is set to '1', then the capability to enable
21620 * a VNIC in a mode where RSS context without configuring
21621 * RSS indirection table is supported (for RSS hash computation).
21622 * When this bit is set to '0', then a VNIC can not be configured
21623 * with a mode to enable RSS context without configuring RSS
21624 * indirection table.
21626 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
21629 * When this bit is '1', the capability to
21630 * mirror the the RoCE traffic is supported.
21631 * If set to '0', then the capability to mirror the
21632 * RoCE traffic is not supported.
21634 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
21637 * When this bit is '1', the outermost RSS hashing capability
21638 * is supported. If set to '0', then the outermost RSS hashing
21639 * capability is not supported.
21641 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
21644 * This field advertises the maximum concurrent TPA aggregations
21645 * supported by the VNIC on new devices that support TPA v2.
21646 * '0' means that TPA v2 is not supported.
21648 uint16_t max_aggs_supported;
21649 uint8_t unused_1[5];
21651 * This field is used in Output records to indicate that the output
21652 * is completely written to RAM. This field should be read as '1'
21653 * to indicate that the output has been completely written.
21654 * When writing a command completion or response to an internal processor,
21655 * the order of writes has to be such that this field is written last.
21658 } __attribute__((packed));
21660 /*********************
21661 * hwrm_vnic_tpa_cfg *
21662 *********************/
21665 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
21666 struct hwrm_vnic_tpa_cfg_input {
21667 /* The HWRM command request type. */
21670 * The completion ring to send the completion event on. This should
21671 * be the NQ ID returned from the `nq_alloc` HWRM command.
21673 uint16_t cmpl_ring;
21675 * The sequence ID is used by the driver for tracking multiple
21676 * commands. This ID is treated as opaque data by the firmware and
21677 * the value is returned in the `hwrm_resp_hdr` upon completion.
21681 * The target ID of the command:
21682 * * 0x0-0xFFF8 - The function ID
21683 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21684 * * 0xFFFD - Reserved for user-space HWRM interface
21687 uint16_t target_id;
21689 * A physical address pointer pointing to a host buffer that the
21690 * command's response data will be written. This can be either a host
21691 * physical address (HPA) or a guest physical address (GPA) and must
21692 * point to a physically contiguous block of memory.
21694 uint64_t resp_addr;
21697 * When this bit is '1', the VNIC shall be configured to
21698 * perform transparent packet aggregation (TPA) of
21699 * non-tunneled TCP packets.
21701 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
21704 * When this bit is '1', the VNIC shall be configured to
21705 * perform transparent packet aggregation (TPA) of
21706 * tunneled TCP packets.
21708 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
21711 * When this bit is '1', the VNIC shall be configured to
21712 * perform transparent packet aggregation (TPA) according
21713 * to Windows Receive Segment Coalescing (RSC) rules.
21715 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
21718 * When this bit is '1', the VNIC shall be configured to
21719 * perform transparent packet aggregation (TPA) according
21720 * to Linux Generic Receive Offload (GRO) rules.
21722 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
21725 * When this bit is '1', the VNIC shall be configured to
21726 * perform transparent packet aggregation (TPA) for TCP
21727 * packets with IP ECN set to non-zero.
21729 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
21732 * When this bit is '1', the VNIC shall be configured to
21733 * perform transparent packet aggregation (TPA) for
21734 * GRE tunneled TCP packets only if all packets have the
21735 * same GRE sequence.
21737 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
21740 * When this bit is '1' and the GRO mode is enabled,
21741 * the VNIC shall be configured to
21742 * perform transparent packet aggregation (TPA) for
21743 * TCP/IPv4 packets with consecutively increasing IPIDs.
21744 * In other words, the last packet that is being
21745 * aggregated to an already existing aggregation context
21746 * shall have IPID 1 more than the IPID of the last packet
21747 * that was aggregated in that aggregation context.
21749 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
21752 * When this bit is '1' and the GRO mode is enabled,
21753 * the VNIC shall be configured to
21754 * perform transparent packet aggregation (TPA) for
21755 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
21758 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
21761 * When this bit is '1' and the GRO mode is enabled,
21762 * the VNIC shall DMA payload data using GRO rules.
21763 * When this bit is '0', the VNIC shall DMA payload data
21764 * using the more efficient LRO rules of filling all
21765 * aggregation buffers.
21767 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
21771 * This bit must be '1' for the max_agg_segs field to be
21774 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
21776 * This bit must be '1' for the max_aggs field to be
21779 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
21781 * This bit must be '1' for the max_agg_timer field to be
21784 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
21785 /* deprecated bit. Do not use!!! */
21786 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
21787 /* Logical vnic ID */
21790 * This is the maximum number of TCP segments that can
21791 * be aggregated (unit is Log2). Max value is 31. On new
21792 * devices supporting TPA v2, the unit is multiples of 4 and
21793 * valid values are > 0 and <= 63.
21795 uint16_t max_agg_segs;
21797 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
21799 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
21801 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
21803 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
21804 /* Any segment size larger than this is not valid */
21805 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
21806 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
21807 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
21809 * This is the maximum number of aggregations this VNIC is
21810 * allowed (unit is Log2). Max value is 7. On new devices
21811 * supporting TPA v2, this is in unit of 1 and must be > 0
21812 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
21813 * to enable TPA v2.
21816 /* 1 aggregation */
21817 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
21818 /* 2 aggregations */
21819 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
21820 /* 4 aggregations */
21821 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
21822 /* 8 aggregations */
21823 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
21824 /* 16 aggregations */
21825 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
21826 /* Any aggregation size larger than this is not valid */
21827 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
21828 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
21829 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
21830 uint8_t unused_0[2];
21832 * This is the maximum amount of time allowed for
21833 * an aggregation context to complete after it was initiated.
21835 uint32_t max_agg_timer;
21837 * This is the minimum amount of payload length required to
21838 * start an aggregation context. This field is deprecated and
21839 * should be set to 0. The minimum length is set by firmware
21840 * and can be queried using hwrm_vnic_tpa_qcfg.
21842 uint32_t min_agg_len;
21843 } __attribute__((packed));
21845 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
21846 struct hwrm_vnic_tpa_cfg_output {
21847 /* The specific error status for the command. */
21848 uint16_t error_code;
21849 /* The HWRM command request type. */
21851 /* The sequence ID from the original command. */
21853 /* The length of the response data in number of bytes. */
21855 uint8_t unused_0[7];
21857 * This field is used in Output records to indicate that the output
21858 * is completely written to RAM. This field should be read as '1'
21859 * to indicate that the output has been completely written.
21860 * When writing a command completion or response to an internal processor,
21861 * the order of writes has to be such that this field is written last.
21864 } __attribute__((packed));
21866 /*********************
21867 * hwrm_vnic_rss_cfg *
21868 *********************/
21871 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
21872 struct hwrm_vnic_rss_cfg_input {
21873 /* The HWRM command request type. */
21876 * The completion ring to send the completion event on. This should
21877 * be the NQ ID returned from the `nq_alloc` HWRM command.
21879 uint16_t cmpl_ring;
21881 * The sequence ID is used by the driver for tracking multiple
21882 * commands. This ID is treated as opaque data by the firmware and
21883 * the value is returned in the `hwrm_resp_hdr` upon completion.
21887 * The target ID of the command:
21888 * * 0x0-0xFFF8 - The function ID
21889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21890 * * 0xFFFD - Reserved for user-space HWRM interface
21893 uint16_t target_id;
21895 * A physical address pointer pointing to a host buffer that the
21896 * command's response data will be written. This can be either a host
21897 * physical address (HPA) or a guest physical address (GPA) and must
21898 * point to a physically contiguous block of memory.
21900 uint64_t resp_addr;
21901 uint32_t hash_type;
21903 * When this bit is '1', the RSS hash shall be computed
21904 * over source and destination IPv4 addresses of IPv4
21907 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
21909 * When this bit is '1', the RSS hash shall be computed
21910 * over source/destination IPv4 addresses and
21911 * source/destination ports of TCP/IPv4 packets.
21913 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
21915 * When this bit is '1', the RSS hash shall be computed
21916 * over source/destination IPv4 addresses and
21917 * source/destination ports of UDP/IPv4 packets.
21919 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
21921 * When this bit is '1', the RSS hash shall be computed
21922 * over source and destination IPv4 addresses of IPv6
21925 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
21927 * When this bit is '1', the RSS hash shall be computed
21928 * over source/destination IPv6 addresses and
21929 * source/destination ports of TCP/IPv6 packets.
21931 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
21933 * When this bit is '1', the RSS hash shall be computed
21934 * over source/destination IPv6 addresses and
21935 * source/destination ports of UDP/IPv6 packets.
21937 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
21938 /* VNIC ID of VNIC associated with RSS table being configured. */
21941 * Specifies which VNIC ring table pair to configure.
21942 * Valid values range from 0 to 7.
21944 uint8_t ring_table_pair_index;
21945 /* Flags to specify different RSS hash modes. */
21946 uint8_t hash_mode_flags;
21948 * When this bit is '1', it indicates using current RSS
21949 * hash mode setting configured in the device.
21951 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
21954 * When this bit is '1', it indicates requesting support of
21955 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
21956 * l4.src, l4.dest} for tunnel packets. For none-tunnel
21957 * packets, the RSS hash is computed over the normal
21958 * src/dest l3 and src/dest l4 headers.
21960 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
21963 * When this bit is '1', it indicates requesting support of
21964 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21965 * tunnel packets. For none-tunnel packets, the RSS hash is
21966 * computed over the normal src/dest l3 headers.
21968 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21971 * When this bit is '1', it indicates requesting support of
21972 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21973 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21974 * packets, the RSS hash is computed over the normal
21975 * src/dest l3 and src/dest l4 headers.
21977 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21980 * When this bit is '1', it indicates requesting support of
21981 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21982 * tunnel packets. For none-tunnel packets, the RSS hash is
21983 * computed over the normal src/dest l3 headers.
21985 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21987 /* This is the address for rss ring group table */
21988 uint64_t ring_grp_tbl_addr;
21989 /* This is the address for rss hash key table */
21990 uint64_t hash_key_tbl_addr;
21991 /* Index to the rss indirection table. */
21992 uint16_t rss_ctx_idx;
21993 uint8_t unused_1[6];
21994 } __attribute__((packed));
21996 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
21997 struct hwrm_vnic_rss_cfg_output {
21998 /* The specific error status for the command. */
21999 uint16_t error_code;
22000 /* The HWRM command request type. */
22002 /* The sequence ID from the original command. */
22004 /* The length of the response data in number of bytes. */
22006 uint8_t unused_0[7];
22008 * This field is used in Output records to indicate that the output
22009 * is completely written to RAM. This field should be read as '1'
22010 * to indicate that the output has been completely written.
22011 * When writing a command completion or response to an internal processor,
22012 * the order of writes has to be such that this field is written last.
22015 } __attribute__((packed));
22017 /**********************
22018 * hwrm_vnic_rss_qcfg *
22019 **********************/
22022 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
22023 struct hwrm_vnic_rss_qcfg_input {
22024 /* The HWRM command request type. */
22027 * The completion ring to send the completion event on. This should
22028 * be the NQ ID returned from the `nq_alloc` HWRM command.
22030 uint16_t cmpl_ring;
22032 * The sequence ID is used by the driver for tracking multiple
22033 * commands. This ID is treated as opaque data by the firmware and
22034 * the value is returned in the `hwrm_resp_hdr` upon completion.
22038 * The target ID of the command:
22039 * * 0x0-0xFFF8 - The function ID
22040 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22041 * * 0xFFFD - Reserved for user-space HWRM interface
22044 uint16_t target_id;
22046 * A physical address pointer pointing to a host buffer that the
22047 * command's response data will be written. This can be either a host
22048 * physical address (HPA) or a guest physical address (GPA) and must
22049 * point to a physically contiguous block of memory.
22051 uint64_t resp_addr;
22052 /* Index to the rss indirection table. */
22053 uint16_t rss_ctx_idx;
22054 uint8_t unused_0[6];
22055 } __attribute__((packed));
22057 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
22058 struct hwrm_vnic_rss_qcfg_output {
22059 /* The specific error status for the command. */
22060 uint16_t error_code;
22061 /* The HWRM command request type. */
22063 /* The sequence ID from the original command. */
22065 /* The length of the response data in number of bytes. */
22067 uint32_t hash_type;
22069 * When this bit is '1', the RSS hash shall be computed
22070 * over source and destination IPv4 addresses of IPv4
22073 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
22075 * When this bit is '1', the RSS hash shall be computed
22076 * over source/destination IPv4 addresses and
22077 * source/destination ports of TCP/IPv4 packets.
22079 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
22081 * When this bit is '1', the RSS hash shall be computed
22082 * over source/destination IPv4 addresses and
22083 * source/destination ports of UDP/IPv4 packets.
22085 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
22087 * When this bit is '1', the RSS hash shall be computed
22088 * over source and destination IPv4 addresses of IPv6
22091 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
22093 * When this bit is '1', the RSS hash shall be computed
22094 * over source/destination IPv6 addresses and
22095 * source/destination ports of TCP/IPv6 packets.
22097 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
22099 * When this bit is '1', the RSS hash shall be computed
22100 * over source/destination IPv6 addresses and
22101 * source/destination ports of UDP/IPv6 packets.
22103 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
22104 uint8_t unused_0[4];
22105 /* This is the value of rss hash key */
22106 uint32_t hash_key[10];
22107 /* Flags to specify different RSS hash modes. */
22108 uint8_t hash_mode_flags;
22110 * When this bit is '1', it indicates using current RSS
22111 * hash mode setting configured in the device.
22113 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
22116 * When this bit is '1', it indicates requesting support of
22117 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
22118 * l4.src, l4.dest} for tunnel packets. For none-tunnel
22119 * packets, the RSS hash is computed over the normal
22120 * src/dest l3 and src/dest l4 headers.
22122 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
22125 * When this bit is '1', it indicates requesting support of
22126 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
22127 * tunnel packets. For none-tunnel packets, the RSS hash is
22128 * computed over the normal src/dest l3 headers.
22130 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
22133 * When this bit is '1', it indicates requesting support of
22134 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
22135 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
22136 * packets, the RSS hash is computed over the normal
22137 * src/dest l3 and src/dest l4 headers.
22139 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
22142 * When this bit is '1', it indicates requesting support of
22143 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
22144 * tunnel packets. For none-tunnel packets, the RSS hash is
22145 * computed over the normal src/dest l3 headers.
22147 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
22149 uint8_t unused_1[6];
22151 * This field is used in Output records to indicate that the output
22152 * is completely written to RAM. This field should be read as '1'
22153 * to indicate that the output has been completely written.
22154 * When writing a command completion or response to an internal processor,
22155 * the order of writes has to be such that this field is written last.
22158 } __attribute__((packed));
22160 /**************************
22161 * hwrm_vnic_plcmodes_cfg *
22162 **************************/
22165 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
22166 struct hwrm_vnic_plcmodes_cfg_input {
22167 /* The HWRM command request type. */
22170 * The completion ring to send the completion event on. This should
22171 * be the NQ ID returned from the `nq_alloc` HWRM command.
22173 uint16_t cmpl_ring;
22175 * The sequence ID is used by the driver for tracking multiple
22176 * commands. This ID is treated as opaque data by the firmware and
22177 * the value is returned in the `hwrm_resp_hdr` upon completion.
22181 * The target ID of the command:
22182 * * 0x0-0xFFF8 - The function ID
22183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22184 * * 0xFFFD - Reserved for user-space HWRM interface
22187 uint16_t target_id;
22189 * A physical address pointer pointing to a host buffer that the
22190 * command's response data will be written. This can be either a host
22191 * physical address (HPA) or a guest physical address (GPA) and must
22192 * point to a physically contiguous block of memory.
22194 uint64_t resp_addr;
22197 * When this bit is '1', the VNIC shall be configured to
22198 * use regular placement algorithm.
22199 * By default, the regular placement algorithm shall be
22200 * enabled on the VNIC.
22202 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
22205 * When this bit is '1', the VNIC shall be configured
22206 * use the jumbo placement algorithm.
22208 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
22211 * When this bit is '1', the VNIC shall be configured
22212 * to enable Header-Data split for IPv4 packets according
22213 * to the following rules:
22214 * # If the packet is identified as TCP/IPv4, then the
22215 * packet is split at the beginning of the TCP payload.
22216 * # If the packet is identified as UDP/IPv4, then the
22217 * packet is split at the beginning of UDP payload.
22218 * # If the packet is identified as non-TCP and non-UDP
22219 * IPv4 packet, then the packet is split at the beginning
22220 * of the upper layer protocol header carried in the IPv4
22223 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
22226 * When this bit is '1', the VNIC shall be configured
22227 * to enable Header-Data split for IPv6 packets according
22228 * to the following rules:
22229 * # If the packet is identified as TCP/IPv6, then the
22230 * packet is split at the beginning of the TCP payload.
22231 * # If the packet is identified as UDP/IPv6, then the
22232 * packet is split at the beginning of UDP payload.
22233 * # If the packet is identified as non-TCP and non-UDP
22234 * IPv6 packet, then the packet is split at the beginning
22235 * of the upper layer protocol header carried in the IPv6
22238 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
22241 * When this bit is '1', the VNIC shall be configured
22242 * to enable Header-Data split for FCoE packets at the
22243 * beginning of FC payload.
22245 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
22248 * When this bit is '1', the VNIC shall be configured
22249 * to enable Header-Data split for RoCE packets at the
22250 * beginning of RoCE payload (after BTH/GRH headers).
22252 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
22256 * This bit must be '1' for the jumbo_thresh_valid field to be
22259 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
22262 * This bit must be '1' for the hds_offset_valid field to be
22265 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
22268 * This bit must be '1' for the hds_threshold_valid field to be
22271 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
22273 /* Logical vnic ID */
22276 * When jumbo placement algorithm is enabled, this value
22277 * is used to determine the threshold for jumbo placement.
22278 * Packets with length larger than this value will be
22279 * placed according to the jumbo placement algorithm.
22281 uint16_t jumbo_thresh;
22283 * This value is used to determine the offset into
22284 * packet buffer where the split data (payload) will be
22285 * placed according to one of of HDS placement algorithm.
22287 * The lengths of packet buffers provided for split data
22288 * shall be larger than this value.
22290 uint16_t hds_offset;
22292 * When one of the HDS placement algorithm is enabled, this
22293 * value is used to determine the threshold for HDS
22295 * Packets with length larger than this value will be
22296 * placed according to the HDS placement algorithm.
22297 * This value shall be in multiple of 4 bytes.
22299 uint16_t hds_threshold;
22300 uint8_t unused_0[6];
22301 } __attribute__((packed));
22303 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
22304 struct hwrm_vnic_plcmodes_cfg_output {
22305 /* The specific error status for the command. */
22306 uint16_t error_code;
22307 /* The HWRM command request type. */
22309 /* The sequence ID from the original command. */
22311 /* The length of the response data in number of bytes. */
22313 uint8_t unused_0[7];
22315 * This field is used in Output records to indicate that the output
22316 * is completely written to RAM. This field should be read as '1'
22317 * to indicate that the output has been completely written.
22318 * When writing a command completion or response to an internal processor,
22319 * the order of writes has to be such that this field is written last.
22322 } __attribute__((packed));
22324 /***************************
22325 * hwrm_vnic_plcmodes_qcfg *
22326 ***************************/
22329 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
22330 struct hwrm_vnic_plcmodes_qcfg_input {
22331 /* The HWRM command request type. */
22334 * The completion ring to send the completion event on. This should
22335 * be the NQ ID returned from the `nq_alloc` HWRM command.
22337 uint16_t cmpl_ring;
22339 * The sequence ID is used by the driver for tracking multiple
22340 * commands. This ID is treated as opaque data by the firmware and
22341 * the value is returned in the `hwrm_resp_hdr` upon completion.
22345 * The target ID of the command:
22346 * * 0x0-0xFFF8 - The function ID
22347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22348 * * 0xFFFD - Reserved for user-space HWRM interface
22351 uint16_t target_id;
22353 * A physical address pointer pointing to a host buffer that the
22354 * command's response data will be written. This can be either a host
22355 * physical address (HPA) or a guest physical address (GPA) and must
22356 * point to a physically contiguous block of memory.
22358 uint64_t resp_addr;
22359 /* Logical vnic ID */
22361 uint8_t unused_0[4];
22362 } __attribute__((packed));
22364 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
22365 struct hwrm_vnic_plcmodes_qcfg_output {
22366 /* The specific error status for the command. */
22367 uint16_t error_code;
22368 /* The HWRM command request type. */
22370 /* The sequence ID from the original command. */
22372 /* The length of the response data in number of bytes. */
22376 * When this bit is '1', the VNIC is configured to
22377 * use regular placement algorithm.
22379 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
22382 * When this bit is '1', the VNIC is configured to
22383 * use the jumbo placement algorithm.
22385 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
22388 * When this bit is '1', the VNIC is configured
22389 * to enable Header-Data split for IPv4 packets.
22391 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
22394 * When this bit is '1', the VNIC is configured
22395 * to enable Header-Data split for IPv6 packets.
22397 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
22400 * When this bit is '1', the VNIC is configured
22401 * to enable Header-Data split for FCoE packets.
22403 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
22406 * When this bit is '1', the VNIC is configured
22407 * to enable Header-Data split for RoCE packets.
22409 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
22412 * When this bit is '1', the VNIC is configured
22413 * to be the default VNIC of the requesting function.
22415 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
22418 * When jumbo placement algorithm is enabled, this value
22419 * is used to determine the threshold for jumbo placement.
22420 * Packets with length larger than this value will be
22421 * placed according to the jumbo placement algorithm.
22423 uint16_t jumbo_thresh;
22425 * This value is used to determine the offset into
22426 * packet buffer where the split data (payload) will be
22427 * placed according to one of of HDS placement algorithm.
22429 * The lengths of packet buffers provided for split data
22430 * shall be larger than this value.
22432 uint16_t hds_offset;
22434 * When one of the HDS placement algorithm is enabled, this
22435 * value is used to determine the threshold for HDS
22437 * Packets with length larger than this value will be
22438 * placed according to the HDS placement algorithm.
22439 * This value shall be in multiple of 4 bytes.
22441 uint16_t hds_threshold;
22442 uint8_t unused_0[5];
22444 * This field is used in Output records to indicate that the output
22445 * is completely written to RAM. This field should be read as '1'
22446 * to indicate that the output has been completely written.
22447 * When writing a command completion or response to an internal processor,
22448 * the order of writes has to be such that this field is written last.
22451 } __attribute__((packed));
22453 /**********************************
22454 * hwrm_vnic_rss_cos_lb_ctx_alloc *
22455 **********************************/
22458 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
22459 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
22460 /* The HWRM command request type. */
22463 * The completion ring to send the completion event on. This should
22464 * be the NQ ID returned from the `nq_alloc` HWRM command.
22466 uint16_t cmpl_ring;
22468 * The sequence ID is used by the driver for tracking multiple
22469 * commands. This ID is treated as opaque data by the firmware and
22470 * the value is returned in the `hwrm_resp_hdr` upon completion.
22474 * The target ID of the command:
22475 * * 0x0-0xFFF8 - The function ID
22476 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22477 * * 0xFFFD - Reserved for user-space HWRM interface
22480 uint16_t target_id;
22482 * A physical address pointer pointing to a host buffer that the
22483 * command's response data will be written. This can be either a host
22484 * physical address (HPA) or a guest physical address (GPA) and must
22485 * point to a physically contiguous block of memory.
22487 uint64_t resp_addr;
22488 } __attribute__((packed));
22490 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
22491 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
22492 /* The specific error status for the command. */
22493 uint16_t error_code;
22494 /* The HWRM command request type. */
22496 /* The sequence ID from the original command. */
22498 /* The length of the response data in number of bytes. */
22500 /* rss_cos_lb_ctx_id is 16 b */
22501 uint16_t rss_cos_lb_ctx_id;
22502 uint8_t unused_0[5];
22504 * This field is used in Output records to indicate that the output
22505 * is completely written to RAM. This field should be read as '1'
22506 * to indicate that the output has been completely written.
22507 * When writing a command completion or response to an internal processor,
22508 * the order of writes has to be such that this field is written last.
22511 } __attribute__((packed));
22513 /*********************************
22514 * hwrm_vnic_rss_cos_lb_ctx_free *
22515 *********************************/
22518 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
22519 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
22520 /* The HWRM command request type. */
22523 * The completion ring to send the completion event on. This should
22524 * be the NQ ID returned from the `nq_alloc` HWRM command.
22526 uint16_t cmpl_ring;
22528 * The sequence ID is used by the driver for tracking multiple
22529 * commands. This ID is treated as opaque data by the firmware and
22530 * the value is returned in the `hwrm_resp_hdr` upon completion.
22534 * The target ID of the command:
22535 * * 0x0-0xFFF8 - The function ID
22536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22537 * * 0xFFFD - Reserved for user-space HWRM interface
22540 uint16_t target_id;
22542 * A physical address pointer pointing to a host buffer that the
22543 * command's response data will be written. This can be either a host
22544 * physical address (HPA) or a guest physical address (GPA) and must
22545 * point to a physically contiguous block of memory.
22547 uint64_t resp_addr;
22548 /* rss_cos_lb_ctx_id is 16 b */
22549 uint16_t rss_cos_lb_ctx_id;
22550 uint8_t unused_0[6];
22551 } __attribute__((packed));
22553 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
22554 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
22555 /* The specific error status for the command. */
22556 uint16_t error_code;
22557 /* The HWRM command request type. */
22559 /* The sequence ID from the original command. */
22561 /* The length of the response data in number of bytes. */
22563 uint8_t unused_0[7];
22565 * This field is used in Output records to indicate that the output
22566 * is completely written to RAM. This field should be read as '1'
22567 * to indicate that the output has been completely written.
22568 * When writing a command completion or response to an internal processor,
22569 * the order of writes has to be such that this field is written last.
22572 } __attribute__((packed));
22574 /*******************
22575 * hwrm_ring_alloc *
22576 *******************/
22579 /* hwrm_ring_alloc_input (size:704b/88B) */
22580 struct hwrm_ring_alloc_input {
22581 /* The HWRM command request type. */
22584 * The completion ring to send the completion event on. This should
22585 * be the NQ ID returned from the `nq_alloc` HWRM command.
22587 uint16_t cmpl_ring;
22589 * The sequence ID is used by the driver for tracking multiple
22590 * commands. This ID is treated as opaque data by the firmware and
22591 * the value is returned in the `hwrm_resp_hdr` upon completion.
22595 * The target ID of the command:
22596 * * 0x0-0xFFF8 - The function ID
22597 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22598 * * 0xFFFD - Reserved for user-space HWRM interface
22601 uint16_t target_id;
22603 * A physical address pointer pointing to a host buffer that the
22604 * command's response data will be written. This can be either a host
22605 * physical address (HPA) or a guest physical address (GPA) and must
22606 * point to a physically contiguous block of memory.
22608 uint64_t resp_addr;
22611 * This bit must be '1' for the ring_arb_cfg field to be
22614 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
22617 * This bit must be '1' for the stat_ctx_id_valid field to be
22620 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
22623 * This bit must be '1' for the max_bw_valid field to be
22626 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
22629 * This bit must be '1' for the rx_ring_id field to be
22632 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
22635 * This bit must be '1' for the nq_ring_id field to be
22638 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
22641 * This bit must be '1' for the rx_buf_size field to be
22644 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
22648 /* L2 Completion Ring (CR) */
22649 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22651 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
22653 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
22654 /* RoCE Notification Completion Ring (ROCE_CR) */
22655 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22656 /* RX Aggregation Ring */
22657 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22658 /* Notification Queue */
22659 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22660 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
22661 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
22663 /* Ring allocation flags. */
22666 * For Rx rings, the incoming packet data can be placed at either
22667 * a 0B or 2B offset from the start of the Rx packet buffer. When
22668 * '1', the received packet will be padded with 2B of zeros at the
22669 * front of the packet. Note that this flag is only used for
22670 * Rx rings and is ignored for all other rings included Rx
22671 * Aggregation rings.
22673 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
22675 * This value is a pointer to the page table for the
22678 uint64_t page_tbl_addr;
22679 /* First Byte Offset of the first entry in the first page. */
22682 * Actual page size in 2^page_size. The supported range is increments
22683 * in powers of 2 from 16 bytes to 1GB.
22685 * Page size is 16 B.
22687 * Page size is 4 KB.
22689 * Page size is 8 KB.
22691 * Page size is 64 KB.
22693 * Page size is 2 MB.
22695 * Page size is 4 MB.
22697 * Page size is 1 GB.
22701 * This value indicates the depth of page table.
22702 * For this version of the specification, value other than 0 or
22703 * 1 shall be considered as an invalid value.
22704 * When the page_tbl_depth = 0, then it is treated as a
22705 * special case with the following.
22706 * 1. FBO and page size fields are not valid.
22707 * 2. page_tbl_addr is the physical address of the first
22708 * element of the ring.
22710 uint8_t page_tbl_depth;
22711 uint8_t unused_1[2];
22713 * Number of 16B units in the ring. Minimum size for
22714 * a ring is 16 16B entries.
22718 * Logical ring number for the ring to be allocated.
22719 * This value determines the position in the doorbell
22720 * area where the update to the ring will be made.
22722 * For completion rings, this value is also the MSI-X
22723 * vector number for the function the completion ring is
22726 uint16_t logical_id;
22728 * This field is used only when ring_type is a TX ring.
22729 * This value indicates what completion ring the TX ring
22730 * is associated with.
22732 uint16_t cmpl_ring_id;
22734 * This field is used only when ring_type is a TX ring.
22735 * This value indicates what CoS queue the TX ring
22736 * is associated with.
22740 * When allocating a Rx ring or Rx aggregation ring, this field
22741 * specifies the size of the buffer descriptors posted to the ring.
22743 uint16_t rx_buf_size;
22745 * When allocating an Rx aggregation ring, this field
22746 * specifies the associated Rx ring ID.
22748 uint16_t rx_ring_id;
22750 * When allocating a completion ring, this field
22751 * specifies the associated NQ ring ID.
22753 uint16_t nq_ring_id;
22755 * This field is used only when ring_type is a TX ring.
22756 * This field is used to configure arbitration related
22757 * parameters for a TX ring.
22759 uint16_t ring_arb_cfg;
22760 /* Arbitration policy used for the ring. */
22761 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
22763 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
22765 * Use strict priority for the TX ring.
22766 * Priority value is specified in arb_policy_param
22768 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
22771 * Use weighted fair queue arbitration for the TX ring.
22772 * Weight is specified in arb_policy_param
22774 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
22776 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
22777 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
22778 /* Reserved field. */
22779 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
22781 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
22783 * Arbitration policy specific parameter.
22784 * # For strict priority arbitration policy, this field
22785 * represents a priority value. If set to 0, then the priority
22786 * is not specified and the HWRM is allowed to select
22787 * any priority for this TX ring.
22788 * # For weighted fair queue arbitration policy, this field
22789 * represents a weight value. If set to 0, then the weight
22790 * is not specified and the HWRM is allowed to select
22791 * any weight for this TX ring.
22793 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
22795 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
22798 * This field is reserved for the future use.
22799 * It shall be set to 0.
22801 uint32_t reserved3;
22803 * This field is used only when ring_type is a TX ring.
22804 * This input indicates what statistics context this ring
22805 * should be associated with.
22807 uint32_t stat_ctx_id;
22809 * This field is reserved for the future use.
22810 * It shall be set to 0.
22812 uint32_t reserved4;
22814 * This field is used only when ring_type is a TX ring
22815 * to specify maximum BW allocated to the TX ring.
22816 * The HWRM will translate this value into byte counter and
22817 * time interval used for this ring inside the device.
22820 /* The bandwidth value. */
22821 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
22822 UINT32_C(0xfffffff)
22823 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
22824 /* The granularity of the value (bits or bytes). */
22825 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
22826 UINT32_C(0x10000000)
22827 /* Value is in bits. */
22828 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
22829 (UINT32_C(0x0) << 28)
22830 /* Value is in bytes. */
22831 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
22832 (UINT32_C(0x1) << 28)
22833 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
22834 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
22835 /* bw_value_unit is 3 b */
22836 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
22837 UINT32_C(0xe0000000)
22838 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
22839 /* Value is in Mb or MB (base 10). */
22840 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
22841 (UINT32_C(0x0) << 29)
22842 /* Value is in Kb or KB (base 10). */
22843 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
22844 (UINT32_C(0x2) << 29)
22845 /* Value is in bits or bytes. */
22846 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
22847 (UINT32_C(0x4) << 29)
22848 /* Value is in Gb or GB (base 10). */
22849 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
22850 (UINT32_C(0x6) << 29)
22851 /* Value is in 1/100th of a percentage of total bandwidth. */
22852 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22853 (UINT32_C(0x1) << 29)
22855 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
22856 (UINT32_C(0x7) << 29)
22857 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
22858 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
22860 * This field is used only when ring_type is a Completion ring.
22861 * This value indicates what interrupt mode should be used
22862 * on this completion ring.
22863 * Note: In the legacy interrupt mode, no more than 16
22864 * completion rings are allowed.
22868 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
22870 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
22872 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
22873 /* No Interrupt - Polled mode */
22874 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
22875 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
22876 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
22877 uint8_t unused_4[3];
22879 * The cq_handle is specified when allocating a completion ring. For
22880 * devices that support NQs, this cq_handle will be included in the
22881 * NQE to specify which CQ should be read to retrieve the completion
22884 uint64_t cq_handle;
22885 } __attribute__((packed));
22887 /* hwrm_ring_alloc_output (size:128b/16B) */
22888 struct hwrm_ring_alloc_output {
22889 /* The specific error status for the command. */
22890 uint16_t error_code;
22891 /* The HWRM command request type. */
22893 /* The sequence ID from the original command. */
22895 /* The length of the response data in number of bytes. */
22898 * Physical number of ring allocated.
22899 * This value shall be unique for a ring type.
22902 /* Logical number of ring allocated. */
22903 uint16_t logical_ring_id;
22904 uint8_t unused_0[3];
22906 * This field is used in Output records to indicate that the output
22907 * is completely written to RAM. This field should be read as '1'
22908 * to indicate that the output has been completely written.
22909 * When writing a command completion or response to an internal processor,
22910 * the order of writes has to be such that this field is written last.
22913 } __attribute__((packed));
22915 /******************
22917 ******************/
22920 /* hwrm_ring_free_input (size:192b/24B) */
22921 struct hwrm_ring_free_input {
22922 /* The HWRM command request type. */
22925 * The completion ring to send the completion event on. This should
22926 * be the NQ ID returned from the `nq_alloc` HWRM command.
22928 uint16_t cmpl_ring;
22930 * The sequence ID is used by the driver for tracking multiple
22931 * commands. This ID is treated as opaque data by the firmware and
22932 * the value is returned in the `hwrm_resp_hdr` upon completion.
22936 * The target ID of the command:
22937 * * 0x0-0xFFF8 - The function ID
22938 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22939 * * 0xFFFD - Reserved for user-space HWRM interface
22942 uint16_t target_id;
22944 * A physical address pointer pointing to a host buffer that the
22945 * command's response data will be written. This can be either a host
22946 * physical address (HPA) or a guest physical address (GPA) and must
22947 * point to a physically contiguous block of memory.
22949 uint64_t resp_addr;
22952 /* L2 Completion Ring (CR) */
22953 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22955 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
22957 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
22958 /* RoCE Notification Completion Ring (ROCE_CR) */
22959 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22960 /* RX Aggregation Ring */
22961 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22962 /* Notification Queue */
22963 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22964 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
22965 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
22967 /* Physical number of ring allocated. */
22969 uint8_t unused_1[4];
22970 } __attribute__((packed));
22972 /* hwrm_ring_free_output (size:128b/16B) */
22973 struct hwrm_ring_free_output {
22974 /* The specific error status for the command. */
22975 uint16_t error_code;
22976 /* The HWRM command request type. */
22978 /* The sequence ID from the original command. */
22980 /* The length of the response data in number of bytes. */
22982 uint8_t unused_0[7];
22984 * This field is used in Output records to indicate that the output
22985 * is completely written to RAM. This field should be read as '1'
22986 * to indicate that the output has been completely written.
22987 * When writing a command completion or response to an internal processor,
22988 * the order of writes has to be such that this field is written last.
22991 } __attribute__((packed));
22993 /*******************
22994 * hwrm_ring_reset *
22995 *******************/
22998 /* hwrm_ring_reset_input (size:192b/24B) */
22999 struct hwrm_ring_reset_input {
23000 /* The HWRM command request type. */
23003 * The completion ring to send the completion event on. This should
23004 * be the NQ ID returned from the `nq_alloc` HWRM command.
23006 uint16_t cmpl_ring;
23008 * The sequence ID is used by the driver for tracking multiple
23009 * commands. This ID is treated as opaque data by the firmware and
23010 * the value is returned in the `hwrm_resp_hdr` upon completion.
23014 * The target ID of the command:
23015 * * 0x0-0xFFF8 - The function ID
23016 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23017 * * 0xFFFD - Reserved for user-space HWRM interface
23020 uint16_t target_id;
23022 * A physical address pointer pointing to a host buffer that the
23023 * command's response data will be written. This can be either a host
23024 * physical address (HPA) or a guest physical address (GPA) and must
23025 * point to a physically contiguous block of memory.
23027 uint64_t resp_addr;
23030 /* L2 Completion Ring (CR) */
23031 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
23033 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
23035 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
23036 /* RoCE Notification Completion Ring (ROCE_CR) */
23037 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
23038 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
23039 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
23041 /* Physical number of the ring. */
23043 uint8_t unused_1[4];
23044 } __attribute__((packed));
23046 /* hwrm_ring_reset_output (size:128b/16B) */
23047 struct hwrm_ring_reset_output {
23048 /* The specific error status for the command. */
23049 uint16_t error_code;
23050 /* The HWRM command request type. */
23052 /* The sequence ID from the original command. */
23054 /* The length of the response data in number of bytes. */
23056 uint8_t unused_0[4];
23057 /* Position of consumer index after ring reset completes. */
23058 uint8_t consumer_idx[3];
23060 * This field is used in Output records to indicate that the output
23061 * is completely written to RAM. This field should be read as '1'
23062 * to indicate that the output has been completely written.
23063 * When writing a command completion or response to an internal processor,
23064 * the order of writes has to be such that this field is written last.
23067 } __attribute__((packed));
23069 /**************************
23070 * hwrm_ring_aggint_qcaps *
23071 **************************/
23074 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
23075 struct hwrm_ring_aggint_qcaps_input {
23076 /* The HWRM command request type. */
23079 * The completion ring to send the completion event on. This should
23080 * be the NQ ID returned from the `nq_alloc` HWRM command.
23082 uint16_t cmpl_ring;
23084 * The sequence ID is used by the driver for tracking multiple
23085 * commands. This ID is treated as opaque data by the firmware and
23086 * the value is returned in the `hwrm_resp_hdr` upon completion.
23090 * The target ID of the command:
23091 * * 0x0-0xFFF8 - The function ID
23092 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23093 * * 0xFFFD - Reserved for user-space HWRM interface
23096 uint16_t target_id;
23098 * A physical address pointer pointing to a host buffer that the
23099 * command's response data will be written. This can be either a host
23100 * physical address (HPA) or a guest physical address (GPA) and must
23101 * point to a physically contiguous block of memory.
23103 uint64_t resp_addr;
23104 } __attribute__((packed));
23106 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
23107 struct hwrm_ring_aggint_qcaps_output {
23108 /* The specific error status for the command. */
23109 uint16_t error_code;
23110 /* The HWRM command request type. */
23112 /* The sequence ID from the original command. */
23114 /* The length of the response data in number of bytes. */
23116 uint32_t cmpl_params;
23118 * When this bit is set to '1', int_lat_tmr_min can be configured
23119 * on completion rings.
23121 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
23124 * When this bit is set to '1', int_lat_tmr_max can be configured
23125 * on completion rings.
23127 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
23130 * When this bit is set to '1', timer_reset can be enabled
23131 * on completion rings.
23133 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
23136 * When this bit is set to '1', ring_idle can be enabled
23137 * on completion rings.
23139 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
23142 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
23143 * on completion rings.
23145 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
23148 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
23149 * on completion rings.
23151 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
23154 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
23155 * on completion rings.
23157 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
23160 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
23161 * on completion rings.
23163 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
23166 * When this bit is set to '1', num_cmpl_aggr_int can be configured
23167 * on completion rings.
23169 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
23171 uint32_t nq_params;
23173 * When this bit is set to '1', int_lat_tmr_min can be configured
23174 * on notification queues.
23176 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
23178 /* Minimum value for num_cmpl_dma_aggr */
23179 uint16_t num_cmpl_dma_aggr_min;
23180 /* Maximum value for num_cmpl_dma_aggr */
23181 uint16_t num_cmpl_dma_aggr_max;
23182 /* Minimum value for num_cmpl_dma_aggr_during_int */
23183 uint16_t num_cmpl_dma_aggr_during_int_min;
23184 /* Maximum value for num_cmpl_dma_aggr_during_int */
23185 uint16_t num_cmpl_dma_aggr_during_int_max;
23186 /* Minimum value for cmpl_aggr_dma_tmr */
23187 uint16_t cmpl_aggr_dma_tmr_min;
23188 /* Maximum value for cmpl_aggr_dma_tmr */
23189 uint16_t cmpl_aggr_dma_tmr_max;
23190 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
23191 uint16_t cmpl_aggr_dma_tmr_during_int_min;
23192 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
23193 uint16_t cmpl_aggr_dma_tmr_during_int_max;
23194 /* Minimum value for int_lat_tmr_min */
23195 uint16_t int_lat_tmr_min_min;
23196 /* Maximum value for int_lat_tmr_min */
23197 uint16_t int_lat_tmr_min_max;
23198 /* Minimum value for int_lat_tmr_max */
23199 uint16_t int_lat_tmr_max_min;
23200 /* Maximum value for int_lat_tmr_max */
23201 uint16_t int_lat_tmr_max_max;
23202 /* Minimum value for num_cmpl_aggr_int */
23203 uint16_t num_cmpl_aggr_int_min;
23204 /* Maximum value for num_cmpl_aggr_int */
23205 uint16_t num_cmpl_aggr_int_max;
23206 /* The units for timer parameters, in nanoseconds. */
23207 uint16_t timer_units;
23208 uint8_t unused_0[1];
23210 * This field is used in Output records to indicate that the output
23211 * is completely written to RAM. This field should be read as '1'
23212 * to indicate that the output has been completely written.
23213 * When writing a command completion or response to an internal processor,
23214 * the order of writes has to be such that this field is written last.
23217 } __attribute__((packed));
23219 /**************************************
23220 * hwrm_ring_cmpl_ring_qaggint_params *
23221 **************************************/
23224 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
23225 struct hwrm_ring_cmpl_ring_qaggint_params_input {
23226 /* The HWRM command request type. */
23229 * The completion ring to send the completion event on. This should
23230 * be the NQ ID returned from the `nq_alloc` HWRM command.
23232 uint16_t cmpl_ring;
23234 * The sequence ID is used by the driver for tracking multiple
23235 * commands. This ID is treated as opaque data by the firmware and
23236 * the value is returned in the `hwrm_resp_hdr` upon completion.
23240 * The target ID of the command:
23241 * * 0x0-0xFFF8 - The function ID
23242 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23243 * * 0xFFFD - Reserved for user-space HWRM interface
23246 uint16_t target_id;
23248 * A physical address pointer pointing to a host buffer that the
23249 * command's response data will be written. This can be either a host
23250 * physical address (HPA) or a guest physical address (GPA) and must
23251 * point to a physically contiguous block of memory.
23253 uint64_t resp_addr;
23254 /* Physical number of completion ring. */
23256 uint8_t unused_0[6];
23257 } __attribute__((packed));
23259 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
23260 struct hwrm_ring_cmpl_ring_qaggint_params_output {
23261 /* The specific error status for the command. */
23262 uint16_t error_code;
23263 /* The HWRM command request type. */
23265 /* The sequence ID from the original command. */
23267 /* The length of the response data in number of bytes. */
23271 * When this bit is set to '1', interrupt max
23272 * timer is reset whenever a completion is received.
23274 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
23277 * When this bit is set to '1', ring idle mode
23278 * aggregation will be enabled.
23280 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
23283 * Number of completions to aggregate before DMA
23284 * during the normal mode.
23286 uint16_t num_cmpl_dma_aggr;
23288 * Number of completions to aggregate before DMA
23289 * during the interrupt mode.
23291 uint16_t num_cmpl_dma_aggr_during_int;
23293 * Timer in unit of 80-nsec used to aggregate completions before
23294 * DMA during the normal mode (not in interrupt mode).
23296 uint16_t cmpl_aggr_dma_tmr;
23298 * Timer in unit of 80-nsec used to aggregate completions before
23299 * DMA during the interrupt mode.
23301 uint16_t cmpl_aggr_dma_tmr_during_int;
23302 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23303 uint16_t int_lat_tmr_min;
23305 * Maximum wait time (in unit of 80-nsec) spent aggregating
23306 * completions before signaling the interrupt after the
23307 * interrupt is enabled.
23309 uint16_t int_lat_tmr_max;
23311 * Minimum number of completions aggregated before signaling
23314 uint16_t num_cmpl_aggr_int;
23315 uint8_t unused_0[7];
23317 * This field is used in Output records to indicate that the output
23318 * is completely written to RAM. This field should be read as '1'
23319 * to indicate that the output has been completely written.
23320 * When writing a command completion or response to an internal processor,
23321 * the order of writes has to be such that this field is written last.
23324 } __attribute__((packed));
23326 /*****************************************
23327 * hwrm_ring_cmpl_ring_cfg_aggint_params *
23328 *****************************************/
23331 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
23332 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
23333 /* The HWRM command request type. */
23336 * The completion ring to send the completion event on. This should
23337 * be the NQ ID returned from the `nq_alloc` HWRM command.
23339 uint16_t cmpl_ring;
23341 * The sequence ID is used by the driver for tracking multiple
23342 * commands. This ID is treated as opaque data by the firmware and
23343 * the value is returned in the `hwrm_resp_hdr` upon completion.
23347 * The target ID of the command:
23348 * * 0x0-0xFFF8 - The function ID
23349 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23350 * * 0xFFFD - Reserved for user-space HWRM interface
23353 uint16_t target_id;
23355 * A physical address pointer pointing to a host buffer that the
23356 * command's response data will be written. This can be either a host
23357 * physical address (HPA) or a guest physical address (GPA) and must
23358 * point to a physically contiguous block of memory.
23360 uint64_t resp_addr;
23361 /* Physical number of completion ring. */
23365 * When this bit is set to '1', interrupt latency max
23366 * timer is reset whenever a completion is received.
23368 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
23371 * When this bit is set to '1', ring idle mode
23372 * aggregation will be enabled.
23374 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
23377 * Set this flag to 1 when configuring parameters on a
23378 * notification queue. Set this flag to 0 when configuring
23379 * parameters on a completion queue.
23381 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
23384 * Number of completions to aggregate before DMA
23385 * during the normal mode.
23387 uint16_t num_cmpl_dma_aggr;
23389 * Number of completions to aggregate before DMA
23390 * during the interrupt mode.
23392 uint16_t num_cmpl_dma_aggr_during_int;
23394 * Timer in unit of 80-nsec used to aggregate completions before
23395 * DMA during the normal mode (not in interrupt mode).
23397 uint16_t cmpl_aggr_dma_tmr;
23399 * Timer in unit of 80-nsec used to aggregate completions before
23400 * DMA during the interrupt mode.
23402 uint16_t cmpl_aggr_dma_tmr_during_int;
23403 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23404 uint16_t int_lat_tmr_min;
23406 * Maximum wait time (in unit of 80-nsec) spent aggregating
23407 * cmpls before signaling the interrupt after the
23408 * interrupt is enabled.
23410 uint16_t int_lat_tmr_max;
23412 * Minimum number of completions aggregated before signaling
23415 uint16_t num_cmpl_aggr_int;
23417 * Bitfield that indicates which parameters are to be applied. Only
23418 * required when configuring devices with notification queues, and
23419 * used in that case to set certain parameters on completion queues
23420 * and others on notification queues.
23424 * This bit must be '1' for the num_cmpl_dma_aggr field to be
23427 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
23430 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
23433 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
23436 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
23439 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
23442 * This bit must be '1' for the int_lat_tmr_min field to be
23445 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
23448 * This bit must be '1' for the int_lat_tmr_max field to be
23451 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
23454 * This bit must be '1' for the num_cmpl_aggr_int field to be
23457 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
23459 uint8_t unused_0[4];
23460 } __attribute__((packed));
23462 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
23463 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
23464 /* The specific error status for the command. */
23465 uint16_t error_code;
23466 /* The HWRM command request type. */
23468 /* The sequence ID from the original command. */
23470 /* The length of the response data in number of bytes. */
23472 uint8_t unused_0[7];
23474 * This field is used in Output records to indicate that the output
23475 * is completely written to RAM. This field should be read as '1'
23476 * to indicate that the output has been completely written.
23477 * When writing a command completion or response to an internal processor,
23478 * the order of writes has to be such that this field is written last.
23481 } __attribute__((packed));
23483 /***********************
23484 * hwrm_ring_grp_alloc *
23485 ***********************/
23488 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
23489 struct hwrm_ring_grp_alloc_input {
23490 /* The HWRM command request type. */
23493 * The completion ring to send the completion event on. This should
23494 * be the NQ ID returned from the `nq_alloc` HWRM command.
23496 uint16_t cmpl_ring;
23498 * The sequence ID is used by the driver for tracking multiple
23499 * commands. This ID is treated as opaque data by the firmware and
23500 * the value is returned in the `hwrm_resp_hdr` upon completion.
23504 * The target ID of the command:
23505 * * 0x0-0xFFF8 - The function ID
23506 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23507 * * 0xFFFD - Reserved for user-space HWRM interface
23510 uint16_t target_id;
23512 * A physical address pointer pointing to a host buffer that the
23513 * command's response data will be written. This can be either a host
23514 * physical address (HPA) or a guest physical address (GPA) and must
23515 * point to a physically contiguous block of memory.
23517 uint64_t resp_addr;
23519 * This value identifies the CR associated with the ring
23524 * This value identifies the main RR associated with the ring
23529 * This value identifies the aggregation RR associated with
23530 * the ring group. If this value is 0xFF... (All Fs), then no
23531 * Aggregation ring will be set.
23535 * This value identifies the statistics context associated
23536 * with the ring group.
23539 } __attribute__((packed));
23541 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
23542 struct hwrm_ring_grp_alloc_output {
23543 /* The specific error status for the command. */
23544 uint16_t error_code;
23545 /* The HWRM command request type. */
23547 /* The sequence ID from the original command. */
23549 /* The length of the response data in number of bytes. */
23552 * This is the ring group ID value. Use this value to program
23553 * the default ring group for the VNIC or as table entries
23554 * in an RSS/COS context.
23556 uint32_t ring_group_id;
23557 uint8_t unused_0[3];
23559 * This field is used in Output records to indicate that the output
23560 * is completely written to RAM. This field should be read as '1'
23561 * to indicate that the output has been completely written.
23562 * When writing a command completion or response to an internal processor,
23563 * the order of writes has to be such that this field is written last.
23566 } __attribute__((packed));
23568 /**********************
23569 * hwrm_ring_grp_free *
23570 **********************/
23573 /* hwrm_ring_grp_free_input (size:192b/24B) */
23574 struct hwrm_ring_grp_free_input {
23575 /* The HWRM command request type. */
23578 * The completion ring to send the completion event on. This should
23579 * be the NQ ID returned from the `nq_alloc` HWRM command.
23581 uint16_t cmpl_ring;
23583 * The sequence ID is used by the driver for tracking multiple
23584 * commands. This ID is treated as opaque data by the firmware and
23585 * the value is returned in the `hwrm_resp_hdr` upon completion.
23589 * The target ID of the command:
23590 * * 0x0-0xFFF8 - The function ID
23591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23592 * * 0xFFFD - Reserved for user-space HWRM interface
23595 uint16_t target_id;
23597 * A physical address pointer pointing to a host buffer that the
23598 * command's response data will be written. This can be either a host
23599 * physical address (HPA) or a guest physical address (GPA) and must
23600 * point to a physically contiguous block of memory.
23602 uint64_t resp_addr;
23603 /* This is the ring group ID value. */
23604 uint32_t ring_group_id;
23605 uint8_t unused_0[4];
23606 } __attribute__((packed));
23608 /* hwrm_ring_grp_free_output (size:128b/16B) */
23609 struct hwrm_ring_grp_free_output {
23610 /* The specific error status for the command. */
23611 uint16_t error_code;
23612 /* The HWRM command request type. */
23614 /* The sequence ID from the original command. */
23616 /* The length of the response data in number of bytes. */
23618 uint8_t unused_0[7];
23620 * This field is used in Output records to indicate that the output
23621 * is completely written to RAM. This field should be read as '1'
23622 * to indicate that the output has been completely written.
23623 * When writing a command completion or response to an internal processor,
23624 * the order of writes has to be such that this field is written last.
23627 } __attribute__((packed));
23629 * special reserved flow ID to identify per function default
23630 * flows for vSwitch offload
23632 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
23634 * special reserved flow ID to identify per function RoCEv1
23637 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
23639 * special reserved flow ID to identify per function RoCEv2
23642 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
23644 * special reserved flow ID to identify per function RoCEv2
23647 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
23649 /****************************
23650 * hwrm_cfa_l2_filter_alloc *
23651 ****************************/
23654 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
23655 struct hwrm_cfa_l2_filter_alloc_input {
23656 /* The HWRM command request type. */
23659 * The completion ring to send the completion event on. This should
23660 * be the NQ ID returned from the `nq_alloc` HWRM command.
23662 uint16_t cmpl_ring;
23664 * The sequence ID is used by the driver for tracking multiple
23665 * commands. This ID is treated as opaque data by the firmware and
23666 * the value is returned in the `hwrm_resp_hdr` upon completion.
23670 * The target ID of the command:
23671 * * 0x0-0xFFF8 - The function ID
23672 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23673 * * 0xFFFD - Reserved for user-space HWRM interface
23676 uint16_t target_id;
23678 * A physical address pointer pointing to a host buffer that the
23679 * command's response data will be written. This can be either a host
23680 * physical address (HPA) or a guest physical address (GPA) and must
23681 * point to a physically contiguous block of memory.
23683 uint64_t resp_addr;
23686 * Enumeration denoting the RX, TX type of the resource.
23687 * This enumeration is used for resources that are similar for both
23688 * TX and RX paths of the chip.
23690 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
23693 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
23696 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
23698 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
23699 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
23700 /* Setting of this flag indicates the applicability to the loopback path. */
23701 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23704 * Setting of this flag indicates drop action. If this flag is not set,
23705 * then it should be considered accept action.
23707 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
23710 * If this flag is set, all t_l2_* fields are invalid
23711 * and they should not be specified.
23712 * If this flag is set, then l2_* fields refer to
23713 * fields of outermost L2 header.
23715 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
23718 * Enumeration denoting NO_ROCE_L2 to support old drivers.
23719 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
23721 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
23723 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
23724 /* To support old drivers */
23725 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
23726 (UINT32_C(0x0) << 4)
23727 /* Only L2 traffic */
23728 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
23729 (UINT32_C(0x1) << 4)
23730 /* Roce & L2 traffic */
23731 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
23732 (UINT32_C(0x2) << 4)
23733 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
23734 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
23736 * Setting of this flag indicates that no XDP filter is created with
23738 * 0 - legacy behavior, XDP filter is created with L2 filter
23739 * 1 - XDP filter won't be created with L2 filter
23741 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
23744 * Setting this flag to 1 indicate the L2 fields in this command
23745 * pertain to source fields. Setting this flag to 0 indicate the
23746 * L2 fields in this command pertain to the destination fields
23747 * and this is the default/legacy behavior.
23749 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
23753 * This bit must be '1' for the l2_addr field to be
23756 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
23759 * This bit must be '1' for the l2_addr_mask field to be
23762 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
23765 * This bit must be '1' for the l2_ovlan field to be
23768 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
23771 * This bit must be '1' for the l2_ovlan_mask field to be
23774 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
23777 * This bit must be '1' for the l2_ivlan field to be
23780 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
23783 * This bit must be '1' for the l2_ivlan_mask field to be
23786 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
23789 * This bit must be '1' for the t_l2_addr field to be
23792 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
23795 * This bit must be '1' for the t_l2_addr_mask field to be
23798 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
23801 * This bit must be '1' for the t_l2_ovlan field to be
23804 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
23807 * This bit must be '1' for the t_l2_ovlan_mask field to be
23810 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
23813 * This bit must be '1' for the t_l2_ivlan field to be
23816 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
23819 * This bit must be '1' for the t_l2_ivlan_mask field to be
23822 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
23825 * This bit must be '1' for the src_type field to be
23828 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
23831 * This bit must be '1' for the src_id field to be
23834 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
23837 * This bit must be '1' for the tunnel_type field to be
23840 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23843 * This bit must be '1' for the dst_id field to be
23846 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23849 * This bit must be '1' for the mirror_vnic_id field to be
23852 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23855 * This bit must be '1' for the num_vlans field to be
23858 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
23861 * This bit must be '1' for the t_num_vlans field to be
23864 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
23867 * This value sets the match value for the L2 MAC address.
23868 * Destination MAC address for RX path.
23869 * Source MAC address for TX path.
23871 uint8_t l2_addr[6];
23872 /* This value sets the match value for the number of VLANs. */
23875 * This value sets the match value for the number of VLANs
23876 * in the tunnel headers.
23878 uint8_t t_num_vlans;
23880 * This value sets the mask value for the L2 address.
23881 * A value of 0 will mask the corresponding bit from
23884 uint8_t l2_addr_mask[6];
23885 /* This value sets VLAN ID value for outer VLAN. */
23888 * This value sets the mask value for the ovlan id.
23889 * A value of 0 will mask the corresponding bit from
23892 uint16_t l2_ovlan_mask;
23893 /* This value sets VLAN ID value for inner VLAN. */
23896 * This value sets the mask value for the ivlan id.
23897 * A value of 0 will mask the corresponding bit from
23900 uint16_t l2_ivlan_mask;
23901 uint8_t unused_1[2];
23903 * This value sets the match value for the tunnel
23905 * Destination MAC address for RX path.
23906 * Source MAC address for TX path.
23908 uint8_t t_l2_addr[6];
23909 uint8_t unused_2[2];
23911 * This value sets the mask value for the tunnel L2
23913 * A value of 0 will mask the corresponding bit from
23916 uint8_t t_l2_addr_mask[6];
23917 /* This value sets VLAN ID value for tunnel outer VLAN. */
23918 uint16_t t_l2_ovlan;
23920 * This value sets the mask value for the tunnel ovlan id.
23921 * A value of 0 will mask the corresponding bit from
23924 uint16_t t_l2_ovlan_mask;
23925 /* This value sets VLAN ID value for tunnel inner VLAN. */
23926 uint16_t t_l2_ivlan;
23928 * This value sets the mask value for the tunnel ivlan id.
23929 * A value of 0 will mask the corresponding bit from
23932 uint16_t t_l2_ivlan_mask;
23933 /* This value identifies the type of source of the packet. */
23936 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
23937 /* Physical function */
23938 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
23939 /* Virtual function */
23940 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
23941 /* Virtual NIC of a function */
23942 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
23943 /* Embedded processor for CFA management */
23944 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
23945 /* Embedded processor for OOB management */
23946 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
23947 /* Embedded processor for RoCE */
23948 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
23949 /* Embedded processor for network proxy functions */
23950 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
23951 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
23952 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
23955 * This value is the id of the source.
23956 * For a network port, it represents port_id.
23957 * For a physical function, it represents fid.
23958 * For a virtual function, it represents vf_id.
23959 * For a vnic, it represents vnic_id.
23960 * For embedded processors, this id is not valid.
23963 * 1. The function ID is implied if it src_id is
23964 * not provided for a src_type that is either
23968 uint8_t tunnel_type;
23970 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23972 /* Virtual eXtensible Local Area Network (VXLAN) */
23973 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23975 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23976 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23978 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23979 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23982 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23984 /* Generic Network Virtualization Encapsulation (Geneve) */
23985 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23987 /* Multi-Protocol Lable Switching (MPLS) */
23988 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23990 /* Stateless Transport Tunnel (STT) */
23991 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23993 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23994 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23996 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23997 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23999 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24000 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24002 /* Use fixed layer 2 ether type of 0xFFFF */
24003 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24005 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24006 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24008 /* Any tunneled traffic */
24009 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24011 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24012 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24015 * If set, this value shall represent the
24016 * Logical VNIC ID of the destination VNIC for the RX
24017 * path and network port id of the destination port for
24022 * Logical VNIC ID of the VNIC where traffic is
24025 uint16_t mirror_vnic_id;
24027 * This hint is provided to help in placing
24028 * the filter in the filter table.
24031 /* No preference */
24032 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
24034 /* Above the given filter */
24035 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
24037 /* Below the given filter */
24038 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
24040 /* As high as possible */
24041 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
24043 /* As low as possible */
24044 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
24046 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
24047 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
24051 * This is the ID of the filter that goes along with
24054 * This field is valid only for the following values.
24055 * 1 - Above the given filter
24056 * 2 - Below the given filter
24058 uint64_t l2_filter_id_hint;
24059 } __attribute__((packed));
24061 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
24062 struct hwrm_cfa_l2_filter_alloc_output {
24063 /* The specific error status for the command. */
24064 uint16_t error_code;
24065 /* The HWRM command request type. */
24067 /* The sequence ID from the original command. */
24069 /* The length of the response data in number of bytes. */
24072 * This value identifies a set of CFA data structures used for an L2
24075 uint64_t l2_filter_id;
24077 * The flow id value in bit 0-29 is the actual ID of the flow
24078 * associated with this filter and it shall be used to match
24079 * and associate the flow identifier returned in completion
24080 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24081 * shall indicate no valid flow id.
24084 /* Indicate the flow id value. */
24085 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24086 UINT32_C(0x3fffffff)
24087 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24088 /* Indicate type of the flow. */
24089 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24090 UINT32_C(0x40000000)
24092 * If this bit set to 0, then it indicates that the flow is
24095 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24096 (UINT32_C(0x0) << 30)
24098 * If this bit is set to 1, then it indicates that the flow is
24101 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24102 (UINT32_C(0x1) << 30)
24103 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24104 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24105 /* Indicate the flow direction. */
24106 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24107 UINT32_C(0x80000000)
24108 /* If this bit set to 0, then it indicates rx flow. */
24109 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24110 (UINT32_C(0x0) << 31)
24111 /* If this bit is set to 1, then it indicates that tx flow. */
24112 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24113 (UINT32_C(0x1) << 31)
24114 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24115 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24116 uint8_t unused_0[3];
24118 * This field is used in Output records to indicate that the output
24119 * is completely written to RAM. This field should be read as '1'
24120 * to indicate that the output has been completely written.
24121 * When writing a command completion or response to an internal processor,
24122 * the order of writes has to be such that this field is written last.
24125 } __attribute__((packed));
24127 /***************************
24128 * hwrm_cfa_l2_filter_free *
24129 ***************************/
24132 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
24133 struct hwrm_cfa_l2_filter_free_input {
24134 /* The HWRM command request type. */
24137 * The completion ring to send the completion event on. This should
24138 * be the NQ ID returned from the `nq_alloc` HWRM command.
24140 uint16_t cmpl_ring;
24142 * The sequence ID is used by the driver for tracking multiple
24143 * commands. This ID is treated as opaque data by the firmware and
24144 * the value is returned in the `hwrm_resp_hdr` upon completion.
24148 * The target ID of the command:
24149 * * 0x0-0xFFF8 - The function ID
24150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24151 * * 0xFFFD - Reserved for user-space HWRM interface
24154 uint16_t target_id;
24156 * A physical address pointer pointing to a host buffer that the
24157 * command's response data will be written. This can be either a host
24158 * physical address (HPA) or a guest physical address (GPA) and must
24159 * point to a physically contiguous block of memory.
24161 uint64_t resp_addr;
24163 * This value identifies a set of CFA data structures used for an L2
24166 uint64_t l2_filter_id;
24167 } __attribute__((packed));
24169 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
24170 struct hwrm_cfa_l2_filter_free_output {
24171 /* The specific error status for the command. */
24172 uint16_t error_code;
24173 /* The HWRM command request type. */
24175 /* The sequence ID from the original command. */
24177 /* The length of the response data in number of bytes. */
24179 uint8_t unused_0[7];
24181 * This field is used in Output records to indicate that the output
24182 * is completely written to RAM. This field should be read as '1'
24183 * to indicate that the output has been completely written.
24184 * When writing a command completion or response to an internal processor,
24185 * the order of writes has to be such that this field is written last.
24188 } __attribute__((packed));
24190 /**************************
24191 * hwrm_cfa_l2_filter_cfg *
24192 **************************/
24195 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
24196 struct hwrm_cfa_l2_filter_cfg_input {
24197 /* The HWRM command request type. */
24200 * The completion ring to send the completion event on. This should
24201 * be the NQ ID returned from the `nq_alloc` HWRM command.
24203 uint16_t cmpl_ring;
24205 * The sequence ID is used by the driver for tracking multiple
24206 * commands. This ID is treated as opaque data by the firmware and
24207 * the value is returned in the `hwrm_resp_hdr` upon completion.
24211 * The target ID of the command:
24212 * * 0x0-0xFFF8 - The function ID
24213 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24214 * * 0xFFFD - Reserved for user-space HWRM interface
24217 uint16_t target_id;
24219 * A physical address pointer pointing to a host buffer that the
24220 * command's response data will be written. This can be either a host
24221 * physical address (HPA) or a guest physical address (GPA) and must
24222 * point to a physically contiguous block of memory.
24224 uint64_t resp_addr;
24227 * Enumeration denoting the RX, TX type of the resource.
24228 * This enumeration is used for resources that are similar for both
24229 * TX and RX paths of the chip.
24231 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
24234 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
24237 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
24239 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
24240 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
24242 * Setting of this flag indicates drop action. If this flag is not set,
24243 * then it should be considered accept action.
24245 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
24248 * Enumeration denoting NO_ROCE_L2 to support old drivers.
24249 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
24251 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
24253 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
24254 /* To support old drivers */
24255 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
24256 (UINT32_C(0x0) << 2)
24257 /* Only L2 traffic */
24258 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
24259 (UINT32_C(0x1) << 2)
24260 /* Roce & L2 traffic */
24261 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
24262 (UINT32_C(0x2) << 2)
24263 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
24264 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
24267 * This bit must be '1' for the dst_id field to be
24270 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
24273 * This bit must be '1' for the new_mirror_vnic_id field to be
24276 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
24279 * This value identifies a set of CFA data structures used for an L2
24282 uint64_t l2_filter_id;
24284 * If set, this value shall represent the
24285 * Logical VNIC ID of the destination VNIC for the RX
24286 * path and network port id of the destination port for
24291 * New Logical VNIC ID of the VNIC where traffic is
24294 uint32_t new_mirror_vnic_id;
24295 } __attribute__((packed));
24297 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
24298 struct hwrm_cfa_l2_filter_cfg_output {
24299 /* The specific error status for the command. */
24300 uint16_t error_code;
24301 /* The HWRM command request type. */
24303 /* The sequence ID from the original command. */
24305 /* The length of the response data in number of bytes. */
24307 uint8_t unused_0[7];
24309 * This field is used in Output records to indicate that the output
24310 * is completely written to RAM. This field should be read as '1'
24311 * to indicate that the output has been completely written.
24312 * When writing a command completion or response to an internal processor,
24313 * the order of writes has to be such that this field is written last.
24316 } __attribute__((packed));
24318 /***************************
24319 * hwrm_cfa_l2_set_rx_mask *
24320 ***************************/
24323 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
24324 struct hwrm_cfa_l2_set_rx_mask_input {
24325 /* The HWRM command request type. */
24328 * The completion ring to send the completion event on. This should
24329 * be the NQ ID returned from the `nq_alloc` HWRM command.
24331 uint16_t cmpl_ring;
24333 * The sequence ID is used by the driver for tracking multiple
24334 * commands. This ID is treated as opaque data by the firmware and
24335 * the value is returned in the `hwrm_resp_hdr` upon completion.
24339 * The target ID of the command:
24340 * * 0x0-0xFFF8 - The function ID
24341 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24342 * * 0xFFFD - Reserved for user-space HWRM interface
24345 uint16_t target_id;
24347 * A physical address pointer pointing to a host buffer that the
24348 * command's response data will be written. This can be either a host
24349 * physical address (HPA) or a guest physical address (GPA) and must
24350 * point to a physically contiguous block of memory.
24352 uint64_t resp_addr;
24357 * When this bit is '1', the function is requested to accept
24358 * multi-cast packets specified by the multicast addr table.
24360 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
24363 * When this bit is '1', the function is requested to accept
24364 * all multi-cast packets.
24366 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
24369 * When this bit is '1', the function is requested to accept
24370 * broadcast packets.
24372 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
24375 * When this bit is '1', the function is requested to be
24376 * put in the promiscuous mode.
24378 * The HWRM should accept any function to set up
24379 * promiscuous mode.
24381 * The HWRM shall follow the semantics below for the
24382 * promiscuous mode support.
24383 * # When partitioning is not enabled on a port
24384 * (i.e. single PF on the port), then the PF shall
24385 * be allowed to be in the promiscuous mode. When the
24386 * PF is in the promiscuous mode, then it shall
24387 * receive all host bound traffic on that port.
24388 * # When partitioning is enabled on a port
24389 * (i.e. multiple PFs per port) and a PF on that
24390 * port is in the promiscuous mode, then the PF
24391 * receives all traffic within that partition as
24392 * identified by a unique identifier for the
24393 * PF (e.g. S-Tag). If a unique outer VLAN
24394 * for the PF is specified, then the setting of
24395 * promiscuous mode on that PF shall result in the
24396 * PF receiving all host bound traffic with matching
24398 * # A VF shall can be set in the promiscuous mode.
24399 * In the promiscuous mode, the VF does not receive any
24400 * traffic unless a unique outer VLAN for the
24401 * VF is specified. If a unique outer VLAN
24402 * for the VF is specified, then the setting of
24403 * promiscuous mode on that VF shall result in the
24404 * VF receiving all host bound traffic with the
24405 * matching outer VLAN.
24406 * # The HWRM shall allow the setting of promiscuous
24407 * mode on a function independently from the
24408 * promiscuous mode settings on other functions.
24410 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
24413 * If this flag is set, the corresponding RX
24414 * filters shall be set up to cover multicast/broadcast
24415 * filters for the outermost Layer 2 destination MAC
24418 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
24421 * If this flag is set, the corresponding RX
24422 * filters shall be set up to cover multicast/broadcast
24423 * filters for the VLAN-tagged packets that match the
24424 * TPID and VID fields of VLAN tags in the VLAN tag
24425 * table specified in this command.
24427 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
24430 * If this flag is set, the corresponding RX
24431 * filters shall be set up to cover multicast/broadcast
24432 * filters for non-VLAN tagged packets and VLAN-tagged
24433 * packets that match the TPID and VID fields of VLAN
24434 * tags in the VLAN tag table specified in this command.
24436 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
24439 * If this flag is set, the corresponding RX
24440 * filters shall be set up to cover multicast/broadcast
24441 * filters for non-VLAN tagged packets and VLAN-tagged
24442 * packets matching any VLAN tag.
24444 * If this flag is set, then the HWRM shall ignore
24445 * VLAN tags specified in vlan_tag_tbl.
24447 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
24448 * flags is set, then the HWRM shall ignore
24449 * VLAN tags specified in vlan_tag_tbl.
24451 * The HWRM client shall set at most one flag out of
24452 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
24454 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
24456 /* This is the address for mcast address tbl. */
24457 uint64_t mc_tbl_addr;
24459 * This value indicates how many entries in mc_tbl are valid.
24460 * Each entry is 6 bytes.
24462 uint32_t num_mc_entries;
24463 uint8_t unused_0[4];
24465 * This is the address for VLAN tag table.
24466 * Each VLAN entry in the table is 4 bytes of a VLAN tag
24467 * including TPID, PCP, DEI, and VID fields in network byte
24470 uint64_t vlan_tag_tbl_addr;
24472 * This value indicates how many entries in vlan_tag_tbl are
24473 * valid. Each entry is 4 bytes.
24475 uint32_t num_vlan_tags;
24476 uint8_t unused_1[4];
24477 } __attribute__((packed));
24479 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
24480 struct hwrm_cfa_l2_set_rx_mask_output {
24481 /* The specific error status for the command. */
24482 uint16_t error_code;
24483 /* The HWRM command request type. */
24485 /* The sequence ID from the original command. */
24487 /* The length of the response data in number of bytes. */
24489 uint8_t unused_0[7];
24491 * This field is used in Output records to indicate that the output
24492 * is completely written to RAM. This field should be read as '1'
24493 * to indicate that the output has been completely written.
24494 * When writing a command completion or response to an internal processor,
24495 * the order of writes has to be such that this field is written last.
24498 } __attribute__((packed));
24500 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
24501 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
24503 * command specific error codes that goes to
24504 * the cmd_err field in Common HWRM Error Response.
24507 /* Unknown error */
24508 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
24510 /* Unable to complete operation due to conflict with Ntuple Filter */
24511 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
24513 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
24514 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
24515 uint8_t unused_0[7];
24516 } __attribute__((packed));
24518 /*******************************
24519 * hwrm_cfa_vlan_antispoof_cfg *
24520 *******************************/
24523 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
24524 struct hwrm_cfa_vlan_antispoof_cfg_input {
24525 /* The HWRM command request type. */
24528 * The completion ring to send the completion event on. This should
24529 * be the NQ ID returned from the `nq_alloc` HWRM command.
24531 uint16_t cmpl_ring;
24533 * The sequence ID is used by the driver for tracking multiple
24534 * commands. This ID is treated as opaque data by the firmware and
24535 * the value is returned in the `hwrm_resp_hdr` upon completion.
24539 * The target ID of the command:
24540 * * 0x0-0xFFF8 - The function ID
24541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24542 * * 0xFFFD - Reserved for user-space HWRM interface
24545 uint16_t target_id;
24547 * A physical address pointer pointing to a host buffer that the
24548 * command's response data will be written. This can be either a host
24549 * physical address (HPA) or a guest physical address (GPA) and must
24550 * point to a physically contiguous block of memory.
24552 uint64_t resp_addr;
24554 * Function ID of the function that is being configured.
24555 * Only valid for a VF FID configured by the PF.
24558 uint8_t unused_0[2];
24559 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
24560 uint32_t num_vlan_entries;
24562 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24563 * antispoof table. Each table entry contains the 16-bit TPID
24564 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
24565 * all in network order to match hwrm_cfa_l2_set_rx_mask.
24566 * For an individual VLAN entry, the mask value should be 0xfff
24567 * for the 12-bit VLAN ID.
24569 uint64_t vlan_tag_mask_tbl_addr;
24570 } __attribute__((packed));
24572 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
24573 struct hwrm_cfa_vlan_antispoof_cfg_output {
24574 /* The specific error status for the command. */
24575 uint16_t error_code;
24576 /* The HWRM command request type. */
24578 /* The sequence ID from the original command. */
24580 /* The length of the response data in number of bytes. */
24582 uint8_t unused_0[7];
24584 * This field is used in Output records to indicate that the output
24585 * is completely written to RAM. This field should be read as '1'
24586 * to indicate that the output has been completely written.
24587 * When writing a command completion or response to an internal processor,
24588 * the order of writes has to be such that this field is written last.
24591 } __attribute__((packed));
24593 /********************************
24594 * hwrm_cfa_vlan_antispoof_qcfg *
24595 ********************************/
24598 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
24599 struct hwrm_cfa_vlan_antispoof_qcfg_input {
24600 /* The HWRM command request type. */
24603 * The completion ring to send the completion event on. This should
24604 * be the NQ ID returned from the `nq_alloc` HWRM command.
24606 uint16_t cmpl_ring;
24608 * The sequence ID is used by the driver for tracking multiple
24609 * commands. This ID is treated as opaque data by the firmware and
24610 * the value is returned in the `hwrm_resp_hdr` upon completion.
24614 * The target ID of the command:
24615 * * 0x0-0xFFF8 - The function ID
24616 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24617 * * 0xFFFD - Reserved for user-space HWRM interface
24620 uint16_t target_id;
24622 * A physical address pointer pointing to a host buffer that the
24623 * command's response data will be written. This can be either a host
24624 * physical address (HPA) or a guest physical address (GPA) and must
24625 * point to a physically contiguous block of memory.
24627 uint64_t resp_addr;
24629 * Function ID of the function that is being queried.
24630 * Only valid for a VF FID queried by the PF.
24633 uint8_t unused_0[2];
24635 * Maximum number of VLAN entries the firmware is allowed to DMA
24636 * to vlan_tag_mask_tbl.
24638 uint32_t max_vlan_entries;
24640 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24641 * antispoof table to which firmware will DMA to. Each table
24642 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
24643 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
24644 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
24645 * the mask value should be 0xfff for the 12-bit VLAN ID.
24647 uint64_t vlan_tag_mask_tbl_addr;
24648 } __attribute__((packed));
24650 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
24651 struct hwrm_cfa_vlan_antispoof_qcfg_output {
24652 /* The specific error status for the command. */
24653 uint16_t error_code;
24654 /* The HWRM command request type. */
24656 /* The sequence ID from the original command. */
24658 /* The length of the response data in number of bytes. */
24660 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
24661 uint32_t num_vlan_entries;
24662 uint8_t unused_0[3];
24664 * This field is used in Output records to indicate that the output
24665 * is completely written to RAM. This field should be read as '1'
24666 * to indicate that the output has been completely written.
24667 * When writing a command completion or response to an internal processor,
24668 * the order of writes has to be such that this field is written last.
24671 } __attribute__((packed));
24673 /********************************
24674 * hwrm_cfa_tunnel_filter_alloc *
24675 ********************************/
24678 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
24679 struct hwrm_cfa_tunnel_filter_alloc_input {
24680 /* The HWRM command request type. */
24683 * The completion ring to send the completion event on. This should
24684 * be the NQ ID returned from the `nq_alloc` HWRM command.
24686 uint16_t cmpl_ring;
24688 * The sequence ID is used by the driver for tracking multiple
24689 * commands. This ID is treated as opaque data by the firmware and
24690 * the value is returned in the `hwrm_resp_hdr` upon completion.
24694 * The target ID of the command:
24695 * * 0x0-0xFFF8 - The function ID
24696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24697 * * 0xFFFD - Reserved for user-space HWRM interface
24700 uint16_t target_id;
24702 * A physical address pointer pointing to a host buffer that the
24703 * command's response data will be written. This can be either a host
24704 * physical address (HPA) or a guest physical address (GPA) and must
24705 * point to a physically contiguous block of memory.
24707 uint64_t resp_addr;
24709 /* Setting of this flag indicates the applicability to the loopback path. */
24710 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
24714 * This bit must be '1' for the l2_filter_id field to be
24717 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24720 * This bit must be '1' for the l2_addr field to be
24723 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
24726 * This bit must be '1' for the l2_ivlan field to be
24729 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
24732 * This bit must be '1' for the l3_addr field to be
24735 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
24738 * This bit must be '1' for the l3_addr_type field to be
24741 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
24744 * This bit must be '1' for the t_l3_addr_type field to be
24747 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
24750 * This bit must be '1' for the t_l3_addr field to be
24753 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
24756 * This bit must be '1' for the tunnel_type field to be
24759 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24762 * This bit must be '1' for the vni field to be
24765 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
24768 * This bit must be '1' for the dst_vnic_id field to be
24771 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
24774 * This bit must be '1' for the mirror_vnic_id field to be
24777 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
24780 * This value identifies a set of CFA data structures used for an L2
24783 uint64_t l2_filter_id;
24785 * This value sets the match value for the inner L2
24787 * Destination MAC address for RX path.
24788 * Source MAC address for TX path.
24790 uint8_t l2_addr[6];
24792 * This value sets VLAN ID value for inner VLAN.
24793 * Only 12-bits of VLAN ID are used in setting the filter.
24797 * The value of inner destination IP address to be used in filtering.
24798 * For IPv4, first four bytes represent the IP address.
24800 uint32_t l3_addr[4];
24802 * The value of tunnel destination IP address to be used in filtering.
24803 * For IPv4, first four bytes represent the IP address.
24805 uint32_t t_l3_addr[4];
24807 * This value indicates the type of inner IP address.
24810 * All others are invalid.
24812 uint8_t l3_addr_type;
24814 * This value indicates the type of tunnel IP address.
24817 * All others are invalid.
24819 uint8_t t_l3_addr_type;
24821 uint8_t tunnel_type;
24823 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
24825 /* Virtual eXtensible Local Area Network (VXLAN) */
24826 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24828 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24829 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
24831 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24832 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
24835 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24837 /* Generic Network Virtualization Encapsulation (Geneve) */
24838 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24840 /* Multi-Protocol Lable Switching (MPLS) */
24841 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24843 /* Stateless Transport Tunnel (STT) */
24844 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
24846 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24847 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24849 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24850 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24852 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24853 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24855 /* Use fixed layer 2 ether type of 0xFFFF */
24856 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24858 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24859 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24861 /* Any tunneled traffic */
24862 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24864 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24865 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24867 * tunnel_flags allows the user to indicate the tunnel tag detection
24868 * for the tunnel type specified in tunnel_type.
24870 uint8_t tunnel_flags;
24872 * If the tunnel_type is geneve, then this bit indicates if we
24873 * need to match the geneve OAM packet.
24874 * If the tunnel_type is nvgre or gre, then this bit indicates if
24875 * we need to detect checksum present bit in geneve header.
24876 * If the tunnel_type is mpls, then this bit indicates if we need
24877 * to match mpls packet with explicit IPV4/IPV6 null header.
24879 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
24882 * If the tunnel_type is geneve, then this bit indicates if we
24883 * need to detect the critical option bit set in the oam packet.
24884 * If the tunnel_type is nvgre or gre, then this bit indicates
24885 * if we need to match nvgre packets with key present bit set in
24887 * If the tunnel_type is mpls, then this bit indicates if we
24888 * need to match mpls packet with S bit from inner/second label.
24890 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
24893 * If the tunnel_type is geneve, then this bit indicates if we
24894 * need to match geneve packet with extended header bit set in
24896 * If the tunnel_type is nvgre or gre, then this bit indicates
24897 * if we need to match nvgre packets with sequence number
24898 * present bit set in gre header.
24899 * If the tunnel_type is mpls, then this bit indicates if we
24900 * need to match mpls packet with S bit from out/first label.
24902 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
24905 * Virtual Network Identifier (VNI). Only valid with
24906 * tunnel_types VXLAN, NVGRE, and Geneve.
24907 * Only lower 24-bits of VNI field are used
24908 * in setting up the filter.
24911 /* Logical VNIC ID of the destination VNIC. */
24912 uint32_t dst_vnic_id;
24914 * Logical VNIC ID of the VNIC where traffic is
24917 uint32_t mirror_vnic_id;
24918 } __attribute__((packed));
24920 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
24921 struct hwrm_cfa_tunnel_filter_alloc_output {
24922 /* The specific error status for the command. */
24923 uint16_t error_code;
24924 /* The HWRM command request type. */
24926 /* The sequence ID from the original command. */
24928 /* The length of the response data in number of bytes. */
24930 /* This value is an opaque id into CFA data structures. */
24931 uint64_t tunnel_filter_id;
24933 * The flow id value in bit 0-29 is the actual ID of the flow
24934 * associated with this filter and it shall be used to match
24935 * and associate the flow identifier returned in completion
24936 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24937 * shall indicate no valid flow id.
24940 /* Indicate the flow id value. */
24941 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24942 UINT32_C(0x3fffffff)
24943 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24944 /* Indicate type of the flow. */
24945 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24946 UINT32_C(0x40000000)
24948 * If this bit set to 0, then it indicates that the flow is
24951 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24952 (UINT32_C(0x0) << 30)
24954 * If this bit is set to 1, then it indicates that the flow is
24957 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24958 (UINT32_C(0x1) << 30)
24959 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24960 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24961 /* Indicate the flow direction. */
24962 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24963 UINT32_C(0x80000000)
24964 /* If this bit set to 0, then it indicates rx flow. */
24965 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24966 (UINT32_C(0x0) << 31)
24967 /* If this bit is set to 1, then it indicates that tx flow. */
24968 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24969 (UINT32_C(0x1) << 31)
24970 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24971 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24972 uint8_t unused_0[3];
24974 * This field is used in Output records to indicate that the output
24975 * is completely written to RAM. This field should be read as '1'
24976 * to indicate that the output has been completely written.
24977 * When writing a command completion or response to an internal processor,
24978 * the order of writes has to be such that this field is written last.
24981 } __attribute__((packed));
24983 /*******************************
24984 * hwrm_cfa_tunnel_filter_free *
24985 *******************************/
24988 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
24989 struct hwrm_cfa_tunnel_filter_free_input {
24990 /* The HWRM command request type. */
24993 * The completion ring to send the completion event on. This should
24994 * be the NQ ID returned from the `nq_alloc` HWRM command.
24996 uint16_t cmpl_ring;
24998 * The sequence ID is used by the driver for tracking multiple
24999 * commands. This ID is treated as opaque data by the firmware and
25000 * the value is returned in the `hwrm_resp_hdr` upon completion.
25004 * The target ID of the command:
25005 * * 0x0-0xFFF8 - The function ID
25006 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25007 * * 0xFFFD - Reserved for user-space HWRM interface
25010 uint16_t target_id;
25012 * A physical address pointer pointing to a host buffer that the
25013 * command's response data will be written. This can be either a host
25014 * physical address (HPA) or a guest physical address (GPA) and must
25015 * point to a physically contiguous block of memory.
25017 uint64_t resp_addr;
25018 /* This value is an opaque id into CFA data structures. */
25019 uint64_t tunnel_filter_id;
25020 } __attribute__((packed));
25022 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
25023 struct hwrm_cfa_tunnel_filter_free_output {
25024 /* The specific error status for the command. */
25025 uint16_t error_code;
25026 /* The HWRM command request type. */
25028 /* The sequence ID from the original command. */
25030 /* The length of the response data in number of bytes. */
25032 uint8_t unused_0[7];
25034 * This field is used in Output records to indicate that the output
25035 * is completely written to RAM. This field should be read as '1'
25036 * to indicate that the output has been completely written.
25037 * When writing a command completion or response to an internal processor,
25038 * the order of writes has to be such that this field is written last.
25041 } __attribute__((packed));
25043 /***************************************
25044 * hwrm_cfa_redirect_tunnel_type_alloc *
25045 ***************************************/
25048 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
25049 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
25050 /* The HWRM command request type. */
25053 * The completion ring to send the completion event on. This should
25054 * be the NQ ID returned from the `nq_alloc` HWRM command.
25056 uint16_t cmpl_ring;
25058 * The sequence ID is used by the driver for tracking multiple
25059 * commands. This ID is treated as opaque data by the firmware and
25060 * the value is returned in the `hwrm_resp_hdr` upon completion.
25064 * The target ID of the command:
25065 * * 0x0-0xFFF8 - The function ID
25066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25067 * * 0xFFFD - Reserved for user-space HWRM interface
25070 uint16_t target_id;
25072 * A physical address pointer pointing to a host buffer that the
25073 * command's response data will be written. This can be either a host
25074 * physical address (HPA) or a guest physical address (GPA) and must
25075 * point to a physically contiguous block of memory.
25077 uint64_t resp_addr;
25078 /* The destination function id, to whom the traffic is redirected. */
25081 uint8_t tunnel_type;
25083 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25085 /* Virtual eXtensible Local Area Network (VXLAN) */
25086 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25088 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25089 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25091 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25092 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25095 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25097 /* Generic Network Virtualization Encapsulation (Geneve) */
25098 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25100 /* Multi-Protocol Lable Switching (MPLS) */
25101 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25103 /* Stateless Transport Tunnel (STT) */
25104 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
25106 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25107 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25109 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25110 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25112 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25113 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25115 /* Use fixed layer 2 ether type of 0xFFFF */
25116 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25118 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25119 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25121 /* Any tunneled traffic */
25122 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25124 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25125 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25126 /* Tunnel alloc flags. */
25128 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
25129 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
25131 uint8_t unused_0[4];
25132 } __attribute__((packed));
25134 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
25135 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
25136 /* The specific error status for the command. */
25137 uint16_t error_code;
25138 /* The HWRM command request type. */
25140 /* The sequence ID from the original command. */
25142 /* The length of the response data in number of bytes. */
25144 uint8_t unused_0[7];
25146 * This field is used in Output records to indicate that the output
25147 * is completely written to RAM. This field should be read as '1'
25148 * to indicate that the output has been completely written.
25149 * When writing a command completion or response to an internal processor,
25150 * the order of writes has to be such that this field is written last.
25153 } __attribute__((packed));
25155 /**************************************
25156 * hwrm_cfa_redirect_tunnel_type_free *
25157 **************************************/
25160 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
25161 struct hwrm_cfa_redirect_tunnel_type_free_input {
25162 /* The HWRM command request type. */
25165 * The completion ring to send the completion event on. This should
25166 * be the NQ ID returned from the `nq_alloc` HWRM command.
25168 uint16_t cmpl_ring;
25170 * The sequence ID is used by the driver for tracking multiple
25171 * commands. This ID is treated as opaque data by the firmware and
25172 * the value is returned in the `hwrm_resp_hdr` upon completion.
25176 * The target ID of the command:
25177 * * 0x0-0xFFF8 - The function ID
25178 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25179 * * 0xFFFD - Reserved for user-space HWRM interface
25182 uint16_t target_id;
25184 * A physical address pointer pointing to a host buffer that the
25185 * command's response data will be written. This can be either a host
25186 * physical address (HPA) or a guest physical address (GPA) and must
25187 * point to a physically contiguous block of memory.
25189 uint64_t resp_addr;
25190 /* The destination function id, to whom the traffic is redirected. */
25193 uint8_t tunnel_type;
25195 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
25197 /* Virtual eXtensible Local Area Network (VXLAN) */
25198 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
25200 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25201 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
25203 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25204 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
25207 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
25209 /* Generic Network Virtualization Encapsulation (Geneve) */
25210 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
25212 /* Multi-Protocol Lable Switching (MPLS) */
25213 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
25215 /* Stateless Transport Tunnel (STT) */
25216 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
25218 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25219 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
25221 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25222 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25224 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25227 /* Use fixed layer 2 ether type of 0xFFFF */
25228 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
25230 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25233 /* Any tunneled traffic */
25234 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25236 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
25237 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
25238 uint8_t unused_0[5];
25239 } __attribute__((packed));
25241 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
25242 struct hwrm_cfa_redirect_tunnel_type_free_output {
25243 /* The specific error status for the command. */
25244 uint16_t error_code;
25245 /* The HWRM command request type. */
25247 /* The sequence ID from the original command. */
25249 /* The length of the response data in number of bytes. */
25251 uint8_t unused_0[7];
25253 * This field is used in Output records to indicate that the output
25254 * is completely written to RAM. This field should be read as '1'
25255 * to indicate that the output has been completely written.
25256 * When writing a command completion or response to an internal processor,
25257 * the order of writes has to be such that this field is written last.
25260 } __attribute__((packed));
25262 /**************************************
25263 * hwrm_cfa_redirect_tunnel_type_info *
25264 **************************************/
25267 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
25268 struct hwrm_cfa_redirect_tunnel_type_info_input {
25269 /* The HWRM command request type. */
25272 * The completion ring to send the completion event on. This should
25273 * be the NQ ID returned from the `nq_alloc` HWRM command.
25275 uint16_t cmpl_ring;
25277 * The sequence ID is used by the driver for tracking multiple
25278 * commands. This ID is treated as opaque data by the firmware and
25279 * the value is returned in the `hwrm_resp_hdr` upon completion.
25283 * The target ID of the command:
25284 * * 0x0-0xFFF8 - The function ID
25285 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25286 * * 0xFFFD - Reserved for user-space HWRM interface
25289 uint16_t target_id;
25291 * A physical address pointer pointing to a host buffer that the
25292 * command's response data will be written. This can be either a host
25293 * physical address (HPA) or a guest physical address (GPA) and must
25294 * point to a physically contiguous block of memory.
25296 uint64_t resp_addr;
25297 /* The source function id. */
25300 uint8_t tunnel_type;
25302 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
25304 /* Virtual eXtensible Local Area Network (VXLAN) */
25305 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
25307 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25308 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
25310 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25311 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
25314 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
25316 /* Generic Network Virtualization Encapsulation (Geneve) */
25317 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
25319 /* Multi-Protocol Lable Switching (MPLS) */
25320 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
25322 /* Stateless Transport Tunnel (STT) */
25323 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
25325 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25326 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
25328 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25329 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25331 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25332 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25334 /* Use fixed layer 2 ether type of 0xFFFF */
25335 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
25337 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25338 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25340 /* Any tunneled traffic */
25341 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25343 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
25344 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
25345 uint8_t unused_0[5];
25346 } __attribute__((packed));
25348 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
25349 struct hwrm_cfa_redirect_tunnel_type_info_output {
25350 /* The specific error status for the command. */
25351 uint16_t error_code;
25352 /* The HWRM command request type. */
25354 /* The sequence ID from the original command. */
25356 /* The length of the response data in number of bytes. */
25358 /* The destination function id, to whom the traffic is redirected. */
25360 uint8_t unused_0[5];
25362 * This field is used in Output records to indicate that the output
25363 * is completely written to RAM. This field should be read as '1'
25364 * to indicate that the output has been completely written.
25365 * When writing a command completion or response to an internal processor,
25366 * the order of writes has to be such that this field is written last.
25369 } __attribute__((packed));
25371 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
25372 struct hwrm_vxlan_ipv4_hdr {
25373 /* IPv4 version and header length. */
25375 /* IPv4 header length */
25376 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
25377 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
25379 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
25380 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
25381 /* IPv4 type of service. */
25383 /* IPv4 identification. */
25385 /* IPv4 flags and offset. */
25386 uint16_t flags_frag_offset;
25389 /* IPv4 protocol. */
25391 /* IPv4 source address. */
25392 uint32_t src_ip_addr;
25393 /* IPv4 destination address. */
25394 uint32_t dest_ip_addr;
25395 } __attribute__((packed));
25397 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
25398 struct hwrm_vxlan_ipv6_hdr {
25399 /* IPv6 version, traffic class and flow label. */
25400 uint32_t ver_tc_flow_label;
25401 /* IPv6 version shift */
25402 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
25404 /* IPv6 version mask */
25405 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
25406 UINT32_C(0xf0000000)
25407 /* IPv6 TC shift */
25408 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
25411 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
25412 UINT32_C(0xff00000)
25413 /* IPv6 flow label shift */
25414 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
25416 /* IPv6 flow label mask */
25417 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
25419 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
25420 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
25421 /* IPv6 payload length. */
25422 uint16_t payload_len;
25423 /* IPv6 next header. */
25427 /* IPv6 source address. */
25428 uint32_t src_ip_addr[4];
25429 /* IPv6 destination address. */
25430 uint32_t dest_ip_addr[4];
25431 } __attribute__((packed));
25433 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
25434 struct hwrm_cfa_encap_data_vxlan {
25435 /* Source MAC address. */
25436 uint8_t src_mac_addr[6];
25439 /* Destination MAC address. */
25440 uint8_t dst_mac_addr[6];
25441 /* Number of VLAN tags. */
25442 uint8_t num_vlan_tags;
25445 /* Outer VLAN TPID. */
25446 uint16_t ovlan_tpid;
25447 /* Outer VLAN TCI. */
25448 uint16_t ovlan_tci;
25449 /* Inner VLAN TPID. */
25450 uint16_t ivlan_tpid;
25451 /* Inner VLAN TCI. */
25452 uint16_t ivlan_tci;
25453 /* L3 header fields. */
25455 /* IP version mask. */
25456 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
25457 /* IP version 4. */
25458 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
25459 /* IP version 6. */
25460 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
25461 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
25462 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
25463 /* UDP source port. */
25465 /* UDP destination port. */
25467 /* VXLAN Network Identifier. */
25469 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
25470 uint8_t hdr_rsvd0[3];
25471 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
25473 /* VXLAN header flags field. */
25476 } __attribute__((packed));
25478 /*******************************
25479 * hwrm_cfa_encap_record_alloc *
25480 *******************************/
25483 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
25484 struct hwrm_cfa_encap_record_alloc_input {
25485 /* The HWRM command request type. */
25488 * The completion ring to send the completion event on. This should
25489 * be the NQ ID returned from the `nq_alloc` HWRM command.
25491 uint16_t cmpl_ring;
25493 * The sequence ID is used by the driver for tracking multiple
25494 * commands. This ID is treated as opaque data by the firmware and
25495 * the value is returned in the `hwrm_resp_hdr` upon completion.
25499 * The target ID of the command:
25500 * * 0x0-0xFFF8 - The function ID
25501 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25502 * * 0xFFFD - Reserved for user-space HWRM interface
25505 uint16_t target_id;
25507 * A physical address pointer pointing to a host buffer that the
25508 * command's response data will be written. This can be either a host
25509 * physical address (HPA) or a guest physical address (GPA) and must
25510 * point to a physically contiguous block of memory.
25512 uint64_t resp_addr;
25514 /* Setting of this flag indicates the applicability to the loopback path. */
25515 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
25518 * Setting of this flag indicates this encap record is external encap record.
25519 * Resetting of this flag indicates this flag is internal encap record and
25520 * this is the default setting.
25522 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
25524 /* Encapsulation Type. */
25525 uint8_t encap_type;
25526 /* Virtual eXtensible Local Area Network (VXLAN) */
25527 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
25529 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25530 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
25532 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
25533 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
25536 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
25538 /* Generic Network Virtualization Encapsulation (Geneve) */
25539 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
25541 /* Multi-Protocol Lable Switching (MPLS) */
25542 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
25545 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
25547 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25548 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
25550 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25551 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
25553 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25554 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
25556 /* Use fixed layer 2 ether type of 0xFFFF */
25557 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
25559 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25560 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
25562 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
25563 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
25564 uint8_t unused_0[3];
25565 /* This value is encap data used for the given encap type. */
25566 uint32_t encap_data[20];
25567 } __attribute__((packed));
25569 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
25570 struct hwrm_cfa_encap_record_alloc_output {
25571 /* The specific error status for the command. */
25572 uint16_t error_code;
25573 /* The HWRM command request type. */
25575 /* The sequence ID from the original command. */
25577 /* The length of the response data in number of bytes. */
25579 /* This value is an opaque id into CFA data structures. */
25580 uint32_t encap_record_id;
25581 uint8_t unused_0[3];
25583 * This field is used in Output records to indicate that the output
25584 * is completely written to RAM. This field should be read as '1'
25585 * to indicate that the output has been completely written.
25586 * When writing a command completion or response to an internal processor,
25587 * the order of writes has to be such that this field is written last.
25590 } __attribute__((packed));
25592 /******************************
25593 * hwrm_cfa_encap_record_free *
25594 ******************************/
25597 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
25598 struct hwrm_cfa_encap_record_free_input {
25599 /* The HWRM command request type. */
25602 * The completion ring to send the completion event on. This should
25603 * be the NQ ID returned from the `nq_alloc` HWRM command.
25605 uint16_t cmpl_ring;
25607 * The sequence ID is used by the driver for tracking multiple
25608 * commands. This ID is treated as opaque data by the firmware and
25609 * the value is returned in the `hwrm_resp_hdr` upon completion.
25613 * The target ID of the command:
25614 * * 0x0-0xFFF8 - The function ID
25615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25616 * * 0xFFFD - Reserved for user-space HWRM interface
25619 uint16_t target_id;
25621 * A physical address pointer pointing to a host buffer that the
25622 * command's response data will be written. This can be either a host
25623 * physical address (HPA) or a guest physical address (GPA) and must
25624 * point to a physically contiguous block of memory.
25626 uint64_t resp_addr;
25627 /* This value is an opaque id into CFA data structures. */
25628 uint32_t encap_record_id;
25629 uint8_t unused_0[4];
25630 } __attribute__((packed));
25632 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
25633 struct hwrm_cfa_encap_record_free_output {
25634 /* The specific error status for the command. */
25635 uint16_t error_code;
25636 /* The HWRM command request type. */
25638 /* The sequence ID from the original command. */
25640 /* The length of the response data in number of bytes. */
25642 uint8_t unused_0[7];
25644 * This field is used in Output records to indicate that the output
25645 * is completely written to RAM. This field should be read as '1'
25646 * to indicate that the output has been completely written.
25647 * When writing a command completion or response to an internal processor,
25648 * the order of writes has to be such that this field is written last.
25651 } __attribute__((packed));
25653 /********************************
25654 * hwrm_cfa_ntuple_filter_alloc *
25655 ********************************/
25658 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
25659 struct hwrm_cfa_ntuple_filter_alloc_input {
25660 /* The HWRM command request type. */
25663 * The completion ring to send the completion event on. This should
25664 * be the NQ ID returned from the `nq_alloc` HWRM command.
25666 uint16_t cmpl_ring;
25668 * The sequence ID is used by the driver for tracking multiple
25669 * commands. This ID is treated as opaque data by the firmware and
25670 * the value is returned in the `hwrm_resp_hdr` upon completion.
25674 * The target ID of the command:
25675 * * 0x0-0xFFF8 - The function ID
25676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25677 * * 0xFFFD - Reserved for user-space HWRM interface
25680 uint16_t target_id;
25682 * A physical address pointer pointing to a host buffer that the
25683 * command's response data will be written. This can be either a host
25684 * physical address (HPA) or a guest physical address (GPA) and must
25685 * point to a physically contiguous block of memory.
25687 uint64_t resp_addr;
25689 /* Setting of this flag indicates the applicability to the loopback path. */
25690 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
25693 * Setting of this flag indicates drop action. If this flag is not set,
25694 * then it should be considered accept action.
25696 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
25699 * Setting of this flag indicates that a meter is expected to be attached
25700 * to this flow. This hint can be used when choosing the action record
25701 * format required for the flow.
25703 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
25706 * Setting of this flag indicates that the dest_id field contains function ID.
25707 * If this is not set it indicates dest_id is VNIC or VPORT.
25709 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
25713 * This bit must be '1' for the l2_filter_id field to be
25716 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
25719 * This bit must be '1' for the ethertype field to be
25722 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
25725 * This bit must be '1' for the tunnel_type field to be
25728 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
25731 * This bit must be '1' for the src_macaddr field to be
25734 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
25737 * This bit must be '1' for the ipaddr_type field to be
25740 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25743 * This bit must be '1' for the src_ipaddr field to be
25746 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
25749 * This bit must be '1' for the src_ipaddr_mask field to be
25752 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
25755 * This bit must be '1' for the dst_ipaddr field to be
25758 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
25761 * This bit must be '1' for the dst_ipaddr_mask field to be
25764 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
25767 * This bit must be '1' for the ip_protocol field to be
25770 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25773 * This bit must be '1' for the src_port field to be
25776 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
25779 * This bit must be '1' for the src_port_mask field to be
25782 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
25785 * This bit must be '1' for the dst_port field to be
25788 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
25791 * This bit must be '1' for the dst_port_mask field to be
25794 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
25797 * This bit must be '1' for the pri_hint field to be
25800 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
25803 * This bit must be '1' for the ntuple_filter_id field to be
25806 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
25809 * This bit must be '1' for the dst_id field to be
25812 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
25815 * This bit must be '1' for the mirror_vnic_id field to be
25818 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25821 * This bit must be '1' for the dst_macaddr field to be
25824 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
25827 * This bit must be '1' for the rfs_ring_tbl_idx field to be
25830 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
25833 * This value identifies a set of CFA data structures used for an L2
25836 uint64_t l2_filter_id;
25838 * This value indicates the source MAC address in
25839 * the Ethernet header.
25841 uint8_t src_macaddr[6];
25842 /* This value indicates the ethertype in the Ethernet header. */
25843 uint16_t ethertype;
25845 * This value indicates the type of IP address.
25848 * All others are invalid.
25850 uint8_t ip_addr_type;
25852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
25855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
25858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
25860 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25861 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25863 * The value of protocol filed in IP header.
25864 * Applies to UDP and TCP traffic.
25868 uint8_t ip_protocol;
25870 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
25873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
25876 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
25878 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
25879 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
25881 * If set, this value shall represent the
25882 * Logical VNIC ID of the destination VNIC for the RX
25883 * path and network port id of the destination port for
25888 * Logical VNIC ID of the VNIC where traffic is
25891 uint16_t mirror_vnic_id;
25893 * This value indicates the tunnel type for this filter.
25894 * If this field is not specified, then the filter shall
25895 * apply to both non-tunneled and tunneled packets.
25896 * If this field conflicts with the tunnel_type specified
25897 * in the l2_filter_id, then the HWRM shall return an
25898 * error for this command.
25900 uint8_t tunnel_type;
25902 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25904 /* Virtual eXtensible Local Area Network (VXLAN) */
25905 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25907 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25908 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25910 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25911 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25914 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25916 /* Generic Network Virtualization Encapsulation (Geneve) */
25917 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25919 /* Multi-Protocol Lable Switching (MPLS) */
25920 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25922 /* Stateless Transport Tunnel (STT) */
25923 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25925 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25926 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25928 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25929 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25931 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25932 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25934 /* Use fixed layer 2 ether type of 0xFFFF */
25935 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25937 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25938 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25940 /* Any tunneled traffic */
25941 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25943 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25944 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25946 * This hint is provided to help in placing
25947 * the filter in the filter table.
25950 /* No preference */
25951 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
25953 /* Above the given filter */
25954 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
25956 /* Below the given filter */
25957 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
25959 /* As high as possible */
25960 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
25962 /* As low as possible */
25963 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
25965 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
25966 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
25968 * The value of source IP address to be used in filtering.
25969 * For IPv4, first four bytes represent the IP address.
25971 uint32_t src_ipaddr[4];
25973 * The value of source IP address mask to be used in
25975 * For IPv4, first four bytes represent the IP address mask.
25977 uint32_t src_ipaddr_mask[4];
25979 * The value of destination IP address to be used in filtering.
25980 * For IPv4, first four bytes represent the IP address.
25982 uint32_t dst_ipaddr[4];
25984 * The value of destination IP address mask to be used in
25986 * For IPv4, first four bytes represent the IP address mask.
25988 uint32_t dst_ipaddr_mask[4];
25990 * The value of source port to be used in filtering.
25991 * Applies to UDP and TCP traffic.
25995 * The value of source port mask to be used in filtering.
25996 * Applies to UDP and TCP traffic.
25998 uint16_t src_port_mask;
26000 * The value of destination port to be used in filtering.
26001 * Applies to UDP and TCP traffic.
26005 * The value of destination port mask to be used in
26007 * Applies to UDP and TCP traffic.
26009 uint16_t dst_port_mask;
26011 * This is the ID of the filter that goes along with
26014 uint64_t ntuple_filter_id_hint;
26016 * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
26017 * This index is used in lieu of the RSS hash when selecting the
26018 * index into the RSS table to determine the rx ring.
26020 uint16_t rfs_ring_tbl_idx;
26021 uint8_t unused_0[6];
26022 } __attribute__((packed));
26024 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
26025 struct hwrm_cfa_ntuple_filter_alloc_output {
26026 /* The specific error status for the command. */
26027 uint16_t error_code;
26028 /* The HWRM command request type. */
26030 /* The sequence ID from the original command. */
26032 /* The length of the response data in number of bytes. */
26034 /* This value is an opaque id into CFA data structures. */
26035 uint64_t ntuple_filter_id;
26037 * The flow id value in bit 0-29 is the actual ID of the flow
26038 * associated with this filter and it shall be used to match
26039 * and associate the flow identifier returned in completion
26040 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26041 * shall indicate no valid flow id.
26044 /* Indicate the flow id value. */
26045 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26046 UINT32_C(0x3fffffff)
26047 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26048 /* Indicate type of the flow. */
26049 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
26050 UINT32_C(0x40000000)
26052 * If this bit set to 0, then it indicates that the flow is
26055 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26056 (UINT32_C(0x0) << 30)
26058 * If this bit is set to 1, then it indicates that the flow is
26061 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26062 (UINT32_C(0x1) << 30)
26063 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26064 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26065 /* Indicate the flow direction. */
26066 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
26067 UINT32_C(0x80000000)
26068 /* If this bit set to 0, then it indicates rx flow. */
26069 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26070 (UINT32_C(0x0) << 31)
26071 /* If this bit is set to 1, then it indicates that tx flow. */
26072 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26073 (UINT32_C(0x1) << 31)
26074 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26075 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26076 uint8_t unused_0[3];
26078 * This field is used in Output records to indicate that the output
26079 * is completely written to RAM. This field should be read as '1'
26080 * to indicate that the output has been completely written.
26081 * When writing a command completion or response to an internal processor,
26082 * the order of writes has to be such that this field is written last.
26085 } __attribute__((packed));
26087 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
26088 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
26090 * command specific error codes that goes to
26091 * the cmd_err field in Common HWRM Error Response.
26094 /* Unknown error */
26095 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
26097 /* Unable to complete operation due to conflict with Rx Mask VLAN */
26098 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
26100 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
26101 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
26102 uint8_t unused_0[7];
26103 } __attribute__((packed));
26105 /*******************************
26106 * hwrm_cfa_ntuple_filter_free *
26107 *******************************/
26110 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
26111 struct hwrm_cfa_ntuple_filter_free_input {
26112 /* The HWRM command request type. */
26115 * The completion ring to send the completion event on. This should
26116 * be the NQ ID returned from the `nq_alloc` HWRM command.
26118 uint16_t cmpl_ring;
26120 * The sequence ID is used by the driver for tracking multiple
26121 * commands. This ID is treated as opaque data by the firmware and
26122 * the value is returned in the `hwrm_resp_hdr` upon completion.
26126 * The target ID of the command:
26127 * * 0x0-0xFFF8 - The function ID
26128 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26129 * * 0xFFFD - Reserved for user-space HWRM interface
26132 uint16_t target_id;
26134 * A physical address pointer pointing to a host buffer that the
26135 * command's response data will be written. This can be either a host
26136 * physical address (HPA) or a guest physical address (GPA) and must
26137 * point to a physically contiguous block of memory.
26139 uint64_t resp_addr;
26140 /* This value is an opaque id into CFA data structures. */
26141 uint64_t ntuple_filter_id;
26142 } __attribute__((packed));
26144 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
26145 struct hwrm_cfa_ntuple_filter_free_output {
26146 /* The specific error status for the command. */
26147 uint16_t error_code;
26148 /* The HWRM command request type. */
26150 /* The sequence ID from the original command. */
26152 /* The length of the response data in number of bytes. */
26154 uint8_t unused_0[7];
26156 * This field is used in Output records to indicate that the output
26157 * is completely written to RAM. This field should be read as '1'
26158 * to indicate that the output has been completely written.
26159 * When writing a command completion or response to an internal processor,
26160 * the order of writes has to be such that this field is written last.
26163 } __attribute__((packed));
26165 /******************************
26166 * hwrm_cfa_ntuple_filter_cfg *
26167 ******************************/
26170 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
26171 struct hwrm_cfa_ntuple_filter_cfg_input {
26172 /* The HWRM command request type. */
26175 * The completion ring to send the completion event on. This should
26176 * be the NQ ID returned from the `nq_alloc` HWRM command.
26178 uint16_t cmpl_ring;
26180 * The sequence ID is used by the driver for tracking multiple
26181 * commands. This ID is treated as opaque data by the firmware and
26182 * the value is returned in the `hwrm_resp_hdr` upon completion.
26186 * The target ID of the command:
26187 * * 0x0-0xFFF8 - The function ID
26188 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26189 * * 0xFFFD - Reserved for user-space HWRM interface
26192 uint16_t target_id;
26194 * A physical address pointer pointing to a host buffer that the
26195 * command's response data will be written. This can be either a host
26196 * physical address (HPA) or a guest physical address (GPA) and must
26197 * point to a physically contiguous block of memory.
26199 uint64_t resp_addr;
26202 * This bit must be '1' for the new_dst_id field to be
26205 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
26208 * This bit must be '1' for the new_mirror_vnic_id field to be
26211 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
26214 * This bit must be '1' for the new_meter_instance_id field to be
26217 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
26221 * Setting this bit to 1 indicates that dest_id field contains FID.
26222 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
26224 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
26226 /* This value is an opaque id into CFA data structures. */
26227 uint64_t ntuple_filter_id;
26229 * If set, this value shall represent the new
26230 * Logical VNIC ID of the destination VNIC for the RX
26231 * path and new network port id of the destination port for
26234 uint32_t new_dst_id;
26236 * New Logical VNIC ID of the VNIC where traffic is
26239 uint32_t new_mirror_vnic_id;
26241 * New meter to attach to the flow. Specifying the
26242 * invalid instance ID is used to remove any existing
26243 * meter from the flow.
26245 uint16_t new_meter_instance_id;
26247 * A value of 0xfff is considered invalid and implies the
26248 * instance is not configured.
26250 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
26252 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
26253 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
26254 uint8_t unused_1[6];
26255 } __attribute__((packed));
26257 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
26258 struct hwrm_cfa_ntuple_filter_cfg_output {
26259 /* The specific error status for the command. */
26260 uint16_t error_code;
26261 /* The HWRM command request type. */
26263 /* The sequence ID from the original command. */
26265 /* The length of the response data in number of bytes. */
26267 uint8_t unused_0[7];
26269 * This field is used in Output records to indicate that the output
26270 * is completely written to RAM. This field should be read as '1'
26271 * to indicate that the output has been completely written.
26272 * When writing a command completion or response to an internal processor,
26273 * the order of writes has to be such that this field is written last.
26276 } __attribute__((packed));
26278 /**************************
26279 * hwrm_cfa_em_flow_alloc *
26280 **************************/
26283 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
26284 struct hwrm_cfa_em_flow_alloc_input {
26285 /* The HWRM command request type. */
26288 * The completion ring to send the completion event on. This should
26289 * be the NQ ID returned from the `nq_alloc` HWRM command.
26291 uint16_t cmpl_ring;
26293 * The sequence ID is used by the driver for tracking multiple
26294 * commands. This ID is treated as opaque data by the firmware and
26295 * the value is returned in the `hwrm_resp_hdr` upon completion.
26299 * The target ID of the command:
26300 * * 0x0-0xFFF8 - The function ID
26301 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26302 * * 0xFFFD - Reserved for user-space HWRM interface
26305 uint16_t target_id;
26307 * A physical address pointer pointing to a host buffer that the
26308 * command's response data will be written. This can be either a host
26309 * physical address (HPA) or a guest physical address (GPA) and must
26310 * point to a physically contiguous block of memory.
26312 uint64_t resp_addr;
26315 * Enumeration denoting the RX, TX type of the resource.
26316 * This enumeration is used for resources that are similar for both
26317 * TX and RX paths of the chip.
26319 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26321 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26323 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26324 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
26325 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
26327 * Setting of this flag indicates enabling of a byte counter for a given
26330 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
26332 * Setting of this flag indicates enabling of a packet counter for a given
26335 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
26336 /* Setting of this flag indicates de-capsulation action for the given flow. */
26337 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
26338 /* Setting of this flag indicates encapsulation action for the given flow. */
26339 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
26341 * Setting of this flag indicates drop action. If this flag is not set,
26342 * then it should be considered accept action.
26344 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
26346 * Setting of this flag indicates that a meter is expected to be attached
26347 * to this flow. This hint can be used when choosing the action record
26348 * format required for the flow.
26350 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
26353 * This bit must be '1' for the l2_filter_id field to be
26356 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
26359 * This bit must be '1' for the tunnel_type field to be
26362 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26365 * This bit must be '1' for the tunnel_id field to be
26368 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
26371 * This bit must be '1' for the src_macaddr field to be
26374 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
26377 * This bit must be '1' for the dst_macaddr field to be
26380 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
26383 * This bit must be '1' for the ovlan_vid field to be
26386 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
26389 * This bit must be '1' for the ivlan_vid field to be
26392 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
26395 * This bit must be '1' for the ethertype field to be
26398 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
26401 * This bit must be '1' for the src_ipaddr field to be
26404 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
26407 * This bit must be '1' for the dst_ipaddr field to be
26410 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
26413 * This bit must be '1' for the ipaddr_type field to be
26416 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
26419 * This bit must be '1' for the ip_protocol field to be
26422 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
26425 * This bit must be '1' for the src_port field to be
26428 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
26431 * This bit must be '1' for the dst_port field to be
26434 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
26437 * This bit must be '1' for the dst_id field to be
26440 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
26443 * This bit must be '1' for the mirror_vnic_id field to be
26446 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26449 * This bit must be '1' for the encap_record_id field to be
26452 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
26455 * This bit must be '1' for the meter_instance_id field to be
26458 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
26461 * This value identifies a set of CFA data structures used for an L2
26464 uint64_t l2_filter_id;
26466 uint8_t tunnel_type;
26468 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26470 /* Virtual eXtensible Local Area Network (VXLAN) */
26471 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26473 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26474 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26476 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26477 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26480 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26482 /* Generic Network Virtualization Encapsulation (Geneve) */
26483 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26485 /* Multi-Protocol Lable Switching (MPLS) */
26486 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26488 /* Stateless Transport Tunnel (STT) */
26489 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
26491 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26492 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26494 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26495 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26497 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26498 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26500 /* Use fixed layer 2 ether type of 0xFFFF */
26501 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26503 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26504 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26506 /* Any tunneled traffic */
26507 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26509 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26510 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26511 uint8_t unused_0[3];
26513 * Tunnel identifier.
26514 * Virtual Network Identifier (VNI). Only valid with
26515 * tunnel_types VXLAN, NVGRE, and Geneve.
26516 * Only lower 24-bits of VNI field are used
26517 * in setting up the filter.
26519 uint32_t tunnel_id;
26521 * This value indicates the source MAC address in
26522 * the Ethernet header.
26524 uint8_t src_macaddr[6];
26525 /* The meter instance to attach to the flow. */
26526 uint16_t meter_instance_id;
26528 * A value of 0xfff is considered invalid and implies the
26529 * instance is not configured.
26531 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
26533 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
26534 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
26536 * This value indicates the destination MAC address in
26537 * the Ethernet header.
26539 uint8_t dst_macaddr[6];
26541 * This value indicates the VLAN ID of the outer VLAN tag
26542 * in the Ethernet header.
26544 uint16_t ovlan_vid;
26546 * This value indicates the VLAN ID of the inner VLAN tag
26547 * in the Ethernet header.
26549 uint16_t ivlan_vid;
26550 /* This value indicates the ethertype in the Ethernet header. */
26551 uint16_t ethertype;
26553 * This value indicates the type of IP address.
26556 * All others are invalid.
26558 uint8_t ip_addr_type;
26560 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
26562 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
26564 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
26565 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
26566 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
26568 * The value of protocol filed in IP header.
26569 * Applies to UDP and TCP traffic.
26573 uint8_t ip_protocol;
26575 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
26577 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
26579 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
26580 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
26581 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
26582 uint8_t unused_1[2];
26584 * The value of source IP address to be used in filtering.
26585 * For IPv4, first four bytes represent the IP address.
26587 uint32_t src_ipaddr[4];
26589 * big_endian = True
26590 * The value of destination IP address to be used in filtering.
26591 * For IPv4, first four bytes represent the IP address.
26593 uint32_t dst_ipaddr[4];
26595 * The value of source port to be used in filtering.
26596 * Applies to UDP and TCP traffic.
26600 * The value of destination port to be used in filtering.
26601 * Applies to UDP and TCP traffic.
26605 * If set, this value shall represent the
26606 * Logical VNIC ID of the destination VNIC for the RX
26607 * path and network port id of the destination port for
26612 * Logical VNIC ID of the VNIC where traffic is
26615 uint16_t mirror_vnic_id;
26616 /* Logical ID of the encapsulation record. */
26617 uint32_t encap_record_id;
26618 uint8_t unused_2[4];
26619 } __attribute__((packed));
26621 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
26622 struct hwrm_cfa_em_flow_alloc_output {
26623 /* The specific error status for the command. */
26624 uint16_t error_code;
26625 /* The HWRM command request type. */
26627 /* The sequence ID from the original command. */
26629 /* The length of the response data in number of bytes. */
26631 /* This value is an opaque id into CFA data structures. */
26632 uint64_t em_filter_id;
26634 * The flow id value in bit 0-29 is the actual ID of the flow
26635 * associated with this filter and it shall be used to match
26636 * and associate the flow identifier returned in completion
26637 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26638 * shall indicate no valid flow id.
26641 /* Indicate the flow id value. */
26642 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26643 UINT32_C(0x3fffffff)
26644 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26645 /* Indicate type of the flow. */
26646 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
26647 UINT32_C(0x40000000)
26649 * If this bit set to 0, then it indicates that the flow is
26652 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26653 (UINT32_C(0x0) << 30)
26655 * If this bit is set to 1, then it indicates that the flow is
26658 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26659 (UINT32_C(0x1) << 30)
26660 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26661 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26662 /* Indicate the flow direction. */
26663 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
26664 UINT32_C(0x80000000)
26665 /* If this bit set to 0, then it indicates rx flow. */
26666 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26667 (UINT32_C(0x0) << 31)
26668 /* If this bit is set to 1, then it indicates that tx flow. */
26669 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26670 (UINT32_C(0x1) << 31)
26671 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26672 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26673 uint8_t unused_0[3];
26675 * This field is used in Output records to indicate that the output
26676 * is completely written to RAM. This field should be read as '1'
26677 * to indicate that the output has been completely written.
26678 * When writing a command completion or response to an internal processor,
26679 * the order of writes has to be such that this field is written last.
26682 } __attribute__((packed));
26684 /*************************
26685 * hwrm_cfa_em_flow_free *
26686 *************************/
26689 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
26690 struct hwrm_cfa_em_flow_free_input {
26691 /* The HWRM command request type. */
26694 * The completion ring to send the completion event on. This should
26695 * be the NQ ID returned from the `nq_alloc` HWRM command.
26697 uint16_t cmpl_ring;
26699 * The sequence ID is used by the driver for tracking multiple
26700 * commands. This ID is treated as opaque data by the firmware and
26701 * the value is returned in the `hwrm_resp_hdr` upon completion.
26705 * The target ID of the command:
26706 * * 0x0-0xFFF8 - The function ID
26707 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26708 * * 0xFFFD - Reserved for user-space HWRM interface
26711 uint16_t target_id;
26713 * A physical address pointer pointing to a host buffer that the
26714 * command's response data will be written. This can be either a host
26715 * physical address (HPA) or a guest physical address (GPA) and must
26716 * point to a physically contiguous block of memory.
26718 uint64_t resp_addr;
26719 /* This value is an opaque id into CFA data structures. */
26720 uint64_t em_filter_id;
26721 } __attribute__((packed));
26723 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
26724 struct hwrm_cfa_em_flow_free_output {
26725 /* The specific error status for the command. */
26726 uint16_t error_code;
26727 /* The HWRM command request type. */
26729 /* The sequence ID from the original command. */
26731 /* The length of the response data in number of bytes. */
26733 uint8_t unused_0[7];
26735 * This field is used in Output records to indicate that the output
26736 * is completely written to RAM. This field should be read as '1'
26737 * to indicate that the output has been completely written.
26738 * When writing a command completion or response to an internal processor,
26739 * the order of writes has to be such that this field is written last.
26742 } __attribute__((packed));
26744 /************************
26745 * hwrm_cfa_meter_qcaps *
26746 ************************/
26749 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
26750 struct hwrm_cfa_meter_qcaps_input {
26751 /* The HWRM command request type. */
26754 * The completion ring to send the completion event on. This should
26755 * be the NQ ID returned from the `nq_alloc` HWRM command.
26757 uint16_t cmpl_ring;
26759 * The sequence ID is used by the driver for tracking multiple
26760 * commands. This ID is treated as opaque data by the firmware and
26761 * the value is returned in the `hwrm_resp_hdr` upon completion.
26765 * The target ID of the command:
26766 * * 0x0-0xFFF8 - The function ID
26767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26768 * * 0xFFFD - Reserved for user-space HWRM interface
26771 uint16_t target_id;
26773 * A physical address pointer pointing to a host buffer that the
26774 * command's response data will be written. This can be either a host
26775 * physical address (HPA) or a guest physical address (GPA) and must
26776 * point to a physically contiguous block of memory.
26778 uint64_t resp_addr;
26779 } __attribute__((packed));
26781 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
26782 struct hwrm_cfa_meter_qcaps_output {
26783 /* The specific error status for the command. */
26784 uint16_t error_code;
26785 /* The HWRM command request type. */
26787 /* The sequence ID from the original command. */
26789 /* The length of the response data in number of bytes. */
26793 * Enumeration denoting the clock at which the Meter is running with.
26794 * This enumeration is used for resources that are similar for both
26795 * TX and RX paths of the chip.
26797 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
26798 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
26800 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
26802 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
26803 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
26804 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
26805 uint8_t unused_0[4];
26807 * The minimum guaranteed number of tx meter profiles supported
26808 * for this function.
26810 uint16_t min_tx_profile;
26812 * The maximum non-guaranteed number of tx meter profiles supported
26813 * for this function.
26815 uint16_t max_tx_profile;
26817 * The minimum guaranteed number of rx meter profiles supported
26818 * for this function.
26820 uint16_t min_rx_profile;
26822 * The maximum non-guaranteed number of rx meter profiles supported
26823 * for this function.
26825 uint16_t max_rx_profile;
26827 * The minimum guaranteed number of tx meter instances supported
26828 * for this function.
26830 uint16_t min_tx_instance;
26832 * The maximum non-guaranteed number of tx meter instances supported
26833 * for this function.
26835 uint16_t max_tx_instance;
26837 * The minimum guaranteed number of rx meter instances supported
26838 * for this function.
26840 uint16_t min_rx_instance;
26842 * The maximum non-guaranteed number of rx meter instances supported
26843 * for this function.
26845 uint16_t max_rx_instance;
26846 uint8_t unused_1[7];
26848 * This field is used in Output records to indicate that the output
26849 * is completely written to RAM. This field should be read as '1'
26850 * to indicate that the output has been completely written.
26851 * When writing a command completion or response to an internal processor,
26852 * the order of writes has to be such that this field is written last.
26855 } __attribute__((packed));
26857 /********************************
26858 * hwrm_cfa_meter_profile_alloc *
26859 ********************************/
26862 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
26863 struct hwrm_cfa_meter_profile_alloc_input {
26864 /* The HWRM command request type. */
26867 * The completion ring to send the completion event on. This should
26868 * be the NQ ID returned from the `nq_alloc` HWRM command.
26870 uint16_t cmpl_ring;
26872 * The sequence ID is used by the driver for tracking multiple
26873 * commands. This ID is treated as opaque data by the firmware and
26874 * the value is returned in the `hwrm_resp_hdr` upon completion.
26878 * The target ID of the command:
26879 * * 0x0-0xFFF8 - The function ID
26880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26881 * * 0xFFFD - Reserved for user-space HWRM interface
26884 uint16_t target_id;
26886 * A physical address pointer pointing to a host buffer that the
26887 * command's response data will be written. This can be either a host
26888 * physical address (HPA) or a guest physical address (GPA) and must
26889 * point to a physically contiguous block of memory.
26891 uint64_t resp_addr;
26894 * Enumeration denoting the RX, TX type of the resource.
26895 * This enumeration is used for resources that are similar for both
26896 * TX and RX paths of the chip.
26898 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26900 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
26903 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
26905 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
26906 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
26907 /* The meter algorithm type. */
26908 uint8_t meter_type;
26909 /* RFC 2697 (srTCM) */
26910 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
26912 /* RFC 2698 (trTCM) */
26913 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
26915 /* RFC 4115 (trTCM) */
26916 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
26918 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
26919 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
26921 * This field is reserved for the future use.
26922 * It shall be set to 0.
26924 uint16_t reserved1;
26926 * This field is reserved for the future use.
26927 * It shall be set to 0.
26929 uint32_t reserved2;
26930 /* A meter rate specified in bytes-per-second. */
26931 uint32_t commit_rate;
26932 /* The bandwidth value. */
26933 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
26934 UINT32_C(0xfffffff)
26935 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
26937 /* The granularity of the value (bits or bytes). */
26938 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
26939 UINT32_C(0x10000000)
26940 /* Value is in bits. */
26941 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
26942 (UINT32_C(0x0) << 28)
26943 /* Value is in bytes. */
26944 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
26945 (UINT32_C(0x1) << 28)
26946 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
26947 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
26948 /* bw_value_unit is 3 b */
26949 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
26950 UINT32_C(0xe0000000)
26951 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
26953 /* Value is in Mb or MB (base 10). */
26954 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
26955 (UINT32_C(0x0) << 29)
26956 /* Value is in Kb or KB (base 10). */
26957 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
26958 (UINT32_C(0x2) << 29)
26959 /* Value is in bits or bytes. */
26960 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
26961 (UINT32_C(0x4) << 29)
26962 /* Value is in Gb or GB (base 10). */
26963 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
26964 (UINT32_C(0x6) << 29)
26965 /* Value is in 1/100th of a percentage of total bandwidth. */
26966 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26967 (UINT32_C(0x1) << 29)
26969 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
26970 (UINT32_C(0x7) << 29)
26971 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
26972 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
26973 /* A meter burst size specified in bytes. */
26974 uint32_t commit_burst;
26975 /* The bandwidth value. */
26976 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
26977 UINT32_C(0xfffffff)
26978 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
26980 /* The granularity of the value (bits or bytes). */
26981 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
26982 UINT32_C(0x10000000)
26983 /* Value is in bits. */
26984 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
26985 (UINT32_C(0x0) << 28)
26986 /* Value is in bytes. */
26987 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
26988 (UINT32_C(0x1) << 28)
26989 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
26990 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
26991 /* bw_value_unit is 3 b */
26992 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
26993 UINT32_C(0xe0000000)
26994 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
26996 /* Value is in Mb or MB (base 10). */
26997 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
26998 (UINT32_C(0x0) << 29)
26999 /* Value is in Kb or KB (base 10). */
27000 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
27001 (UINT32_C(0x2) << 29)
27002 /* Value is in bits or bytes. */
27003 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
27004 (UINT32_C(0x4) << 29)
27005 /* Value is in Gb or GB (base 10). */
27006 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
27007 (UINT32_C(0x6) << 29)
27008 /* Value is in 1/100th of a percentage of total bandwidth. */
27009 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27010 (UINT32_C(0x1) << 29)
27011 /* Invalid value */
27012 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
27013 (UINT32_C(0x7) << 29)
27014 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
27015 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
27016 /* A meter rate specified in bytes-per-second. */
27017 uint32_t excess_peak_rate;
27018 /* The bandwidth value. */
27019 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27020 UINT32_C(0xfffffff)
27021 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27023 /* The granularity of the value (bits or bytes). */
27024 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
27025 UINT32_C(0x10000000)
27026 /* Value is in bits. */
27027 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27028 (UINT32_C(0x0) << 28)
27029 /* Value is in bytes. */
27030 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27031 (UINT32_C(0x1) << 28)
27032 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27033 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27034 /* bw_value_unit is 3 b */
27035 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27036 UINT32_C(0xe0000000)
27037 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27039 /* Value is in Mb or MB (base 10). */
27040 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27041 (UINT32_C(0x0) << 29)
27042 /* Value is in Kb or KB (base 10). */
27043 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27044 (UINT32_C(0x2) << 29)
27045 /* Value is in bits or bytes. */
27046 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27047 (UINT32_C(0x4) << 29)
27048 /* Value is in Gb or GB (base 10). */
27049 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27050 (UINT32_C(0x6) << 29)
27051 /* Value is in 1/100th of a percentage of total bandwidth. */
27052 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27053 (UINT32_C(0x1) << 29)
27055 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27056 (UINT32_C(0x7) << 29)
27057 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27058 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27059 /* A meter burst size specified in bytes. */
27060 uint32_t excess_peak_burst;
27061 /* The bandwidth value. */
27062 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27063 UINT32_C(0xfffffff)
27064 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27066 /* The granularity of the value (bits or bytes). */
27067 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
27068 UINT32_C(0x10000000)
27069 /* Value is in bits. */
27070 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27071 (UINT32_C(0x0) << 28)
27072 /* Value is in bytes. */
27073 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27074 (UINT32_C(0x1) << 28)
27075 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27076 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27077 /* bw_value_unit is 3 b */
27078 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27079 UINT32_C(0xe0000000)
27080 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27082 /* Value is in Mb or MB (base 10). */
27083 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27084 (UINT32_C(0x0) << 29)
27085 /* Value is in Kb or KB (base 10). */
27086 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27087 (UINT32_C(0x2) << 29)
27088 /* Value is in bits or bytes. */
27089 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27090 (UINT32_C(0x4) << 29)
27091 /* Value is in Gb or GB (base 10). */
27092 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27093 (UINT32_C(0x6) << 29)
27094 /* Value is in 1/100th of a percentage of total bandwidth. */
27095 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27096 (UINT32_C(0x1) << 29)
27098 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27099 (UINT32_C(0x7) << 29)
27100 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27101 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27102 } __attribute__((packed));
27104 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
27105 struct hwrm_cfa_meter_profile_alloc_output {
27106 /* The specific error status for the command. */
27107 uint16_t error_code;
27108 /* The HWRM command request type. */
27110 /* The sequence ID from the original command. */
27112 /* The length of the response data in number of bytes. */
27114 /* This value identifies a meter profile in CFA. */
27115 uint16_t meter_profile_id;
27117 * A value of 0xfff is considered invalid and implies the
27118 * profile is not configured.
27120 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
27122 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
27123 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
27124 uint8_t unused_0[5];
27126 * This field is used in Output records to indicate that the output
27127 * is completely written to RAM. This field should be read as '1'
27128 * to indicate that the output has been completely written.
27129 * When writing a command completion or response to an internal processor,
27130 * the order of writes has to be such that this field is written last.
27133 } __attribute__((packed));
27135 /*******************************
27136 * hwrm_cfa_meter_profile_free *
27137 *******************************/
27140 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
27141 struct hwrm_cfa_meter_profile_free_input {
27142 /* The HWRM command request type. */
27145 * The completion ring to send the completion event on. This should
27146 * be the NQ ID returned from the `nq_alloc` HWRM command.
27148 uint16_t cmpl_ring;
27150 * The sequence ID is used by the driver for tracking multiple
27151 * commands. This ID is treated as opaque data by the firmware and
27152 * the value is returned in the `hwrm_resp_hdr` upon completion.
27156 * The target ID of the command:
27157 * * 0x0-0xFFF8 - The function ID
27158 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27159 * * 0xFFFD - Reserved for user-space HWRM interface
27162 uint16_t target_id;
27164 * A physical address pointer pointing to a host buffer that the
27165 * command's response data will be written. This can be either a host
27166 * physical address (HPA) or a guest physical address (GPA) and must
27167 * point to a physically contiguous block of memory.
27169 uint64_t resp_addr;
27172 * Enumeration denoting the RX, TX type of the resource.
27173 * This enumeration is used for resources that are similar for both
27174 * TX and RX paths of the chip.
27176 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27178 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
27181 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
27183 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
27184 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
27186 /* This value identifies a meter profile in CFA. */
27187 uint16_t meter_profile_id;
27189 * A value of 0xfff is considered invalid and implies the
27190 * profile is not configured.
27192 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
27194 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
27195 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
27196 uint8_t unused_1[4];
27197 } __attribute__((packed));
27199 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
27200 struct hwrm_cfa_meter_profile_free_output {
27201 /* The specific error status for the command. */
27202 uint16_t error_code;
27203 /* The HWRM command request type. */
27205 /* The sequence ID from the original command. */
27207 /* The length of the response data in number of bytes. */
27209 uint8_t unused_0[7];
27211 * This field is used in Output records to indicate that the output
27212 * is completely written to RAM. This field should be read as '1'
27213 * to indicate that the output has been completely written.
27214 * When writing a command completion or response to an internal processor,
27215 * the order of writes has to be such that this field is written last.
27218 } __attribute__((packed));
27220 /******************************
27221 * hwrm_cfa_meter_profile_cfg *
27222 ******************************/
27225 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
27226 struct hwrm_cfa_meter_profile_cfg_input {
27227 /* The HWRM command request type. */
27230 * The completion ring to send the completion event on. This should
27231 * be the NQ ID returned from the `nq_alloc` HWRM command.
27233 uint16_t cmpl_ring;
27235 * The sequence ID is used by the driver for tracking multiple
27236 * commands. This ID is treated as opaque data by the firmware and
27237 * the value is returned in the `hwrm_resp_hdr` upon completion.
27241 * The target ID of the command:
27242 * * 0x0-0xFFF8 - The function ID
27243 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27244 * * 0xFFFD - Reserved for user-space HWRM interface
27247 uint16_t target_id;
27249 * A physical address pointer pointing to a host buffer that the
27250 * command's response data will be written. This can be either a host
27251 * physical address (HPA) or a guest physical address (GPA) and must
27252 * point to a physically contiguous block of memory.
27254 uint64_t resp_addr;
27257 * Enumeration denoting the RX, TX type of the resource.
27258 * This enumeration is used for resources that are similar for both
27259 * TX and RX paths of the chip.
27261 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27263 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27265 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27266 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
27267 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
27268 /* The meter algorithm type. */
27269 uint8_t meter_type;
27270 /* RFC 2697 (srTCM) */
27271 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
27273 /* RFC 2698 (trTCM) */
27274 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
27276 /* RFC 4115 (trTCM) */
27277 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
27279 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
27280 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
27281 /* This value identifies a meter profile in CFA. */
27282 uint16_t meter_profile_id;
27284 * A value of 0xfff is considered invalid and implies the
27285 * profile is not configured.
27287 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27289 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
27290 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
27292 * This field is reserved for the future use.
27293 * It shall be set to 0.
27296 /* A meter rate specified in bytes-per-second. */
27297 uint32_t commit_rate;
27298 /* The bandwidth value. */
27299 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
27300 UINT32_C(0xfffffff)
27301 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
27303 /* The granularity of the value (bits or bytes). */
27304 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
27305 UINT32_C(0x10000000)
27306 /* Value is in bits. */
27307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
27308 (UINT32_C(0x0) << 28)
27309 /* Value is in bytes. */
27310 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
27311 (UINT32_C(0x1) << 28)
27312 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
27313 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
27314 /* bw_value_unit is 3 b */
27315 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
27316 UINT32_C(0xe0000000)
27317 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
27319 /* Value is in Mb or MB (base 10). */
27320 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
27321 (UINT32_C(0x0) << 29)
27322 /* Value is in Kb or KB (base 10). */
27323 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
27324 (UINT32_C(0x2) << 29)
27325 /* Value is in bits or bytes. */
27326 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
27327 (UINT32_C(0x4) << 29)
27328 /* Value is in Gb or GB (base 10). */
27329 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
27330 (UINT32_C(0x6) << 29)
27331 /* Value is in 1/100th of a percentage of total bandwidth. */
27332 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27333 (UINT32_C(0x1) << 29)
27335 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
27336 (UINT32_C(0x7) << 29)
27337 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
27338 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
27339 /* A meter burst size specified in bytes. */
27340 uint32_t commit_burst;
27341 /* The bandwidth value. */
27342 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
27343 UINT32_C(0xfffffff)
27344 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
27346 /* The granularity of the value (bits or bytes). */
27347 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
27348 UINT32_C(0x10000000)
27349 /* Value is in bits. */
27350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
27351 (UINT32_C(0x0) << 28)
27352 /* Value is in bytes. */
27353 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
27354 (UINT32_C(0x1) << 28)
27355 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
27356 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
27357 /* bw_value_unit is 3 b */
27358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
27359 UINT32_C(0xe0000000)
27360 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
27362 /* Value is in Mb or MB (base 10). */
27363 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
27364 (UINT32_C(0x0) << 29)
27365 /* Value is in Kb or KB (base 10). */
27366 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
27367 (UINT32_C(0x2) << 29)
27368 /* Value is in bits or bytes. */
27369 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
27370 (UINT32_C(0x4) << 29)
27371 /* Value is in Gb or GB (base 10). */
27372 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
27373 (UINT32_C(0x6) << 29)
27374 /* Value is in 1/100th of a percentage of total bandwidth. */
27375 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27376 (UINT32_C(0x1) << 29)
27377 /* Invalid value */
27378 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
27379 (UINT32_C(0x7) << 29)
27380 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
27381 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
27382 /* A meter rate specified in bytes-per-second. */
27383 uint32_t excess_peak_rate;
27384 /* The bandwidth value. */
27385 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27386 UINT32_C(0xfffffff)
27387 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27389 /* The granularity of the value (bits or bytes). */
27390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
27391 UINT32_C(0x10000000)
27392 /* Value is in bits. */
27393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27394 (UINT32_C(0x0) << 28)
27395 /* Value is in bytes. */
27396 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27397 (UINT32_C(0x1) << 28)
27398 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27399 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27400 /* bw_value_unit is 3 b */
27401 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27402 UINT32_C(0xe0000000)
27403 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27405 /* Value is in Mb or MB (base 10). */
27406 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27407 (UINT32_C(0x0) << 29)
27408 /* Value is in Kb or KB (base 10). */
27409 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27410 (UINT32_C(0x2) << 29)
27411 /* Value is in bits or bytes. */
27412 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27413 (UINT32_C(0x4) << 29)
27414 /* Value is in Gb or GB (base 10). */
27415 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27416 (UINT32_C(0x6) << 29)
27417 /* Value is in 1/100th of a percentage of total bandwidth. */
27418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27419 (UINT32_C(0x1) << 29)
27421 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27422 (UINT32_C(0x7) << 29)
27423 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27424 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27425 /* A meter burst size specified in bytes. */
27426 uint32_t excess_peak_burst;
27427 /* The bandwidth value. */
27428 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27429 UINT32_C(0xfffffff)
27430 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27432 /* The granularity of the value (bits or bytes). */
27433 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
27434 UINT32_C(0x10000000)
27435 /* Value is in bits. */
27436 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27437 (UINT32_C(0x0) << 28)
27438 /* Value is in bytes. */
27439 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27440 (UINT32_C(0x1) << 28)
27441 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27442 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27443 /* bw_value_unit is 3 b */
27444 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27445 UINT32_C(0xe0000000)
27446 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27448 /* Value is in Mb or MB (base 10). */
27449 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27450 (UINT32_C(0x0) << 29)
27451 /* Value is in Kb or KB (base 10). */
27452 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27453 (UINT32_C(0x2) << 29)
27454 /* Value is in bits or bytes. */
27455 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27456 (UINT32_C(0x4) << 29)
27457 /* Value is in Gb or GB (base 10). */
27458 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27459 (UINT32_C(0x6) << 29)
27460 /* Value is in 1/100th of a percentage of total bandwidth. */
27461 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27462 (UINT32_C(0x1) << 29)
27464 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27465 (UINT32_C(0x7) << 29)
27466 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27467 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27468 } __attribute__((packed));
27470 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
27471 struct hwrm_cfa_meter_profile_cfg_output {
27472 /* The specific error status for the command. */
27473 uint16_t error_code;
27474 /* The HWRM command request type. */
27476 /* The sequence ID from the original command. */
27478 /* The length of the response data in number of bytes. */
27480 uint8_t unused_0[7];
27482 * This field is used in Output records to indicate that the output
27483 * is completely written to RAM. This field should be read as '1'
27484 * to indicate that the output has been completely written.
27485 * When writing a command completion or response to an internal processor,
27486 * the order of writes has to be such that this field is written last.
27489 } __attribute__((packed));
27491 /*********************************
27492 * hwrm_cfa_meter_instance_alloc *
27493 *********************************/
27496 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
27497 struct hwrm_cfa_meter_instance_alloc_input {
27498 /* The HWRM command request type. */
27501 * The completion ring to send the completion event on. This should
27502 * be the NQ ID returned from the `nq_alloc` HWRM command.
27504 uint16_t cmpl_ring;
27506 * The sequence ID is used by the driver for tracking multiple
27507 * commands. This ID is treated as opaque data by the firmware and
27508 * the value is returned in the `hwrm_resp_hdr` upon completion.
27512 * The target ID of the command:
27513 * * 0x0-0xFFF8 - The function ID
27514 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27515 * * 0xFFFD - Reserved for user-space HWRM interface
27518 uint16_t target_id;
27520 * A physical address pointer pointing to a host buffer that the
27521 * command's response data will be written. This can be either a host
27522 * physical address (HPA) or a guest physical address (GPA) and must
27523 * point to a physically contiguous block of memory.
27525 uint64_t resp_addr;
27528 * Enumeration denoting the RX, TX type of the resource.
27529 * This enumeration is used for resources that are similar for both
27530 * TX and RX paths of the chip.
27532 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
27535 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
27538 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
27540 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
27541 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
27543 /* This value identifies a meter profile in CFA. */
27544 uint16_t meter_profile_id;
27546 * A value of 0xffff is considered invalid and implies the
27547 * profile is not configured.
27549 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
27551 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
27552 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
27553 uint8_t unused_1[4];
27554 } __attribute__((packed));
27556 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
27557 struct hwrm_cfa_meter_instance_alloc_output {
27558 /* The specific error status for the command. */
27559 uint16_t error_code;
27560 /* The HWRM command request type. */
27562 /* The sequence ID from the original command. */
27564 /* The length of the response data in number of bytes. */
27566 /* This value identifies a meter instance in CFA. */
27567 uint16_t meter_instance_id;
27569 * A value of 0xffff is considered invalid and implies the
27570 * instance is not configured.
27572 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
27574 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
27575 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
27576 uint8_t unused_0[5];
27578 * This field is used in Output records to indicate that the output
27579 * is completely written to RAM. This field should be read as '1'
27580 * to indicate that the output has been completely written.
27581 * When writing a command completion or response to an internal processor,
27582 * the order of writes has to be such that this field is written last.
27585 } __attribute__((packed));
27587 /*******************************
27588 * hwrm_cfa_meter_instance_cfg *
27589 *******************************/
27592 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
27593 struct hwrm_cfa_meter_instance_cfg_input {
27594 /* The HWRM command request type. */
27597 * The completion ring to send the completion event on. This should
27598 * be the NQ ID returned from the `nq_alloc` HWRM command.
27600 uint16_t cmpl_ring;
27602 * The sequence ID is used by the driver for tracking multiple
27603 * commands. This ID is treated as opaque data by the firmware and
27604 * the value is returned in the `hwrm_resp_hdr` upon completion.
27608 * The target ID of the command:
27609 * * 0x0-0xFFF8 - The function ID
27610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27611 * * 0xFFFD - Reserved for user-space HWRM interface
27614 uint16_t target_id;
27616 * A physical address pointer pointing to a host buffer that the
27617 * command's response data will be written. This can be either a host
27618 * physical address (HPA) or a guest physical address (GPA) and must
27619 * point to a physically contiguous block of memory.
27621 uint64_t resp_addr;
27624 * Enumeration denoting the RX, TX type of the resource.
27625 * This enumeration is used for resources that are similar for both
27626 * TX and RX paths of the chip.
27628 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27630 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
27633 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
27635 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
27636 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
27639 * This value identifies a new meter profile to be associated with
27640 * the meter instance specified in this command.
27642 uint16_t meter_profile_id;
27644 * A value of 0xffff is considered invalid and implies the
27645 * profile is not configured.
27647 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27649 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
27650 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
27652 * This value identifies the ID of a meter instance that needs to be updated with
27653 * a new meter profile specified in this command.
27655 uint16_t meter_instance_id;
27656 uint8_t unused_1[2];
27657 } __attribute__((packed));
27659 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
27660 struct hwrm_cfa_meter_instance_cfg_output {
27661 /* The specific error status for the command. */
27662 uint16_t error_code;
27663 /* The HWRM command request type. */
27665 /* The sequence ID from the original command. */
27667 /* The length of the response data in number of bytes. */
27669 uint8_t unused_0[7];
27671 * This field is used in Output records to indicate that the output
27672 * is completely written to RAM. This field should be read as '1'
27673 * to indicate that the output has been completely written.
27674 * When writing a command completion or response to an internal processor,
27675 * the order of writes has to be such that this field is written last.
27678 } __attribute__((packed));
27680 /********************************
27681 * hwrm_cfa_meter_instance_free *
27682 ********************************/
27685 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
27686 struct hwrm_cfa_meter_instance_free_input {
27687 /* The HWRM command request type. */
27690 * The completion ring to send the completion event on. This should
27691 * be the NQ ID returned from the `nq_alloc` HWRM command.
27693 uint16_t cmpl_ring;
27695 * The sequence ID is used by the driver for tracking multiple
27696 * commands. This ID is treated as opaque data by the firmware and
27697 * the value is returned in the `hwrm_resp_hdr` upon completion.
27701 * The target ID of the command:
27702 * * 0x0-0xFFF8 - The function ID
27703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27704 * * 0xFFFD - Reserved for user-space HWRM interface
27707 uint16_t target_id;
27709 * A physical address pointer pointing to a host buffer that the
27710 * command's response data will be written. This can be either a host
27711 * physical address (HPA) or a guest physical address (GPA) and must
27712 * point to a physically contiguous block of memory.
27714 uint64_t resp_addr;
27717 * Enumeration denoting the RX, TX type of the resource.
27718 * This enumeration is used for resources that are similar for both
27719 * TX and RX paths of the chip.
27721 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27723 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
27726 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
27728 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
27729 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
27731 /* This value identifies a meter instance in CFA. */
27732 uint16_t meter_instance_id;
27734 * A value of 0xfff is considered invalid and implies the
27735 * instance is not configured.
27737 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
27739 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
27740 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
27741 uint8_t unused_1[4];
27742 } __attribute__((packed));
27744 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
27745 struct hwrm_cfa_meter_instance_free_output {
27746 /* The specific error status for the command. */
27747 uint16_t error_code;
27748 /* The HWRM command request type. */
27750 /* The sequence ID from the original command. */
27752 /* The length of the response data in number of bytes. */
27754 uint8_t unused_0[7];
27756 * This field is used in Output records to indicate that the output
27757 * is completely written to RAM. This field should be read as '1'
27758 * to indicate that the output has been completely written.
27759 * When writing a command completion or response to an internal processor,
27760 * the order of writes has to be such that this field is written last.
27763 } __attribute__((packed));
27765 /*******************************
27766 * hwrm_cfa_decap_filter_alloc *
27767 *******************************/
27770 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
27771 struct hwrm_cfa_decap_filter_alloc_input {
27772 /* The HWRM command request type. */
27775 * The completion ring to send the completion event on. This should
27776 * be the NQ ID returned from the `nq_alloc` HWRM command.
27778 uint16_t cmpl_ring;
27780 * The sequence ID is used by the driver for tracking multiple
27781 * commands. This ID is treated as opaque data by the firmware and
27782 * the value is returned in the `hwrm_resp_hdr` upon completion.
27786 * The target ID of the command:
27787 * * 0x0-0xFFF8 - The function ID
27788 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27789 * * 0xFFFD - Reserved for user-space HWRM interface
27792 uint16_t target_id;
27794 * A physical address pointer pointing to a host buffer that the
27795 * command's response data will be written. This can be either a host
27796 * physical address (HPA) or a guest physical address (GPA) and must
27797 * point to a physically contiguous block of memory.
27799 uint64_t resp_addr;
27801 /* ovs_tunnel is 1 b */
27802 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
27806 * This bit must be '1' for the tunnel_type field to be
27809 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27812 * This bit must be '1' for the tunnel_id field to be
27815 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
27818 * This bit must be '1' for the src_macaddr field to be
27821 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
27824 * This bit must be '1' for the dst_macaddr field to be
27827 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
27830 * This bit must be '1' for the ovlan_vid field to be
27833 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
27836 * This bit must be '1' for the ivlan_vid field to be
27839 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
27842 * This bit must be '1' for the t_ovlan_vid field to be
27845 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
27848 * This bit must be '1' for the t_ivlan_vid field to be
27851 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
27854 * This bit must be '1' for the ethertype field to be
27857 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
27860 * This bit must be '1' for the src_ipaddr field to be
27863 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27866 * This bit must be '1' for the dst_ipaddr field to be
27869 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
27872 * This bit must be '1' for the ipaddr_type field to be
27875 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27878 * This bit must be '1' for the ip_protocol field to be
27881 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27884 * This bit must be '1' for the src_port field to be
27887 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
27890 * This bit must be '1' for the dst_port field to be
27893 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
27896 * This bit must be '1' for the dst_id field to be
27899 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27902 * This bit must be '1' for the mirror_vnic_id field to be
27905 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27908 * Tunnel identifier.
27909 * Virtual Network Identifier (VNI). Only valid with
27910 * tunnel_types VXLAN, NVGRE, and Geneve.
27911 * Only lower 24-bits of VNI field are used
27912 * in setting up the filter.
27914 uint32_t tunnel_id;
27916 uint8_t tunnel_type;
27918 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27920 /* Virtual eXtensible Local Area Network (VXLAN) */
27921 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27923 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27924 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27926 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27927 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27930 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27932 /* Generic Network Virtualization Encapsulation (Geneve) */
27933 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27935 /* Multi-Protocol Lable Switching (MPLS) */
27936 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27938 /* Stateless Transport Tunnel (STT) */
27939 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27941 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27942 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27944 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27945 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27947 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27948 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27950 /* Use fixed layer 2 ether type of 0xFFFF */
27951 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27953 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27954 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27956 /* Any tunneled traffic */
27957 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27959 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27960 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27964 * This value indicates the source MAC address in
27965 * the Ethernet header.
27967 uint8_t src_macaddr[6];
27968 uint8_t unused_2[2];
27970 * This value indicates the destination MAC address in
27971 * the Ethernet header.
27973 uint8_t dst_macaddr[6];
27975 * This value indicates the VLAN ID of the outer VLAN tag
27976 * in the Ethernet header.
27978 uint16_t ovlan_vid;
27980 * This value indicates the VLAN ID of the inner VLAN tag
27981 * in the Ethernet header.
27983 uint16_t ivlan_vid;
27985 * This value indicates the VLAN ID of the outer VLAN tag
27986 * in the tunnel Ethernet header.
27988 uint16_t t_ovlan_vid;
27990 * This value indicates the VLAN ID of the inner VLAN tag
27991 * in the tunnel Ethernet header.
27993 uint16_t t_ivlan_vid;
27994 /* This value indicates the ethertype in the Ethernet header. */
27995 uint16_t ethertype;
27997 * This value indicates the type of IP address.
28000 * All others are invalid.
28002 uint8_t ip_addr_type;
28004 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
28007 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
28010 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
28012 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
28013 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
28015 * The value of protocol filed in IP header.
28016 * Applies to UDP and TCP traffic.
28020 uint8_t ip_protocol;
28022 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
28025 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
28028 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
28030 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
28031 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
28035 * The value of source IP address to be used in filtering.
28036 * For IPv4, first four bytes represent the IP address.
28038 uint32_t src_ipaddr[4];
28040 * The value of destination IP address to be used in filtering.
28041 * For IPv4, first four bytes represent the IP address.
28043 uint32_t dst_ipaddr[4];
28045 * The value of source port to be used in filtering.
28046 * Applies to UDP and TCP traffic.
28050 * The value of destination port to be used in filtering.
28051 * Applies to UDP and TCP traffic.
28055 * If set, this value shall represent the
28056 * Logical VNIC ID of the destination VNIC for the RX
28061 * If set, this value shall represent the L2 context that matches the L2
28062 * information of the decap filter.
28064 uint16_t l2_ctxt_ref_id;
28065 } __attribute__((packed));
28067 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
28068 struct hwrm_cfa_decap_filter_alloc_output {
28069 /* The specific error status for the command. */
28070 uint16_t error_code;
28071 /* The HWRM command request type. */
28073 /* The sequence ID from the original command. */
28075 /* The length of the response data in number of bytes. */
28077 /* This value is an opaque id into CFA data structures. */
28078 uint32_t decap_filter_id;
28079 uint8_t unused_0[3];
28081 * This field is used in Output records to indicate that the output
28082 * is completely written to RAM. This field should be read as '1'
28083 * to indicate that the output has been completely written.
28084 * When writing a command completion or response to an internal processor,
28085 * the order of writes has to be such that this field is written last.
28088 } __attribute__((packed));
28090 /******************************
28091 * hwrm_cfa_decap_filter_free *
28092 ******************************/
28095 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
28096 struct hwrm_cfa_decap_filter_free_input {
28097 /* The HWRM command request type. */
28100 * The completion ring to send the completion event on. This should
28101 * be the NQ ID returned from the `nq_alloc` HWRM command.
28103 uint16_t cmpl_ring;
28105 * The sequence ID is used by the driver for tracking multiple
28106 * commands. This ID is treated as opaque data by the firmware and
28107 * the value is returned in the `hwrm_resp_hdr` upon completion.
28111 * The target ID of the command:
28112 * * 0x0-0xFFF8 - The function ID
28113 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28114 * * 0xFFFD - Reserved for user-space HWRM interface
28117 uint16_t target_id;
28119 * A physical address pointer pointing to a host buffer that the
28120 * command's response data will be written. This can be either a host
28121 * physical address (HPA) or a guest physical address (GPA) and must
28122 * point to a physically contiguous block of memory.
28124 uint64_t resp_addr;
28125 /* This value is an opaque id into CFA data structures. */
28126 uint32_t decap_filter_id;
28127 uint8_t unused_0[4];
28128 } __attribute__((packed));
28130 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
28131 struct hwrm_cfa_decap_filter_free_output {
28132 /* The specific error status for the command. */
28133 uint16_t error_code;
28134 /* The HWRM command request type. */
28136 /* The sequence ID from the original command. */
28138 /* The length of the response data in number of bytes. */
28140 uint8_t unused_0[7];
28142 * This field is used in Output records to indicate that the output
28143 * is completely written to RAM. This field should be read as '1'
28144 * to indicate that the output has been completely written.
28145 * When writing a command completion or response to an internal processor,
28146 * the order of writes has to be such that this field is written last.
28149 } __attribute__((packed));
28151 /***********************
28152 * hwrm_cfa_flow_alloc *
28153 ***********************/
28156 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
28157 struct hwrm_cfa_flow_alloc_input {
28158 /* The HWRM command request type. */
28161 * The completion ring to send the completion event on. This should
28162 * be the NQ ID returned from the `nq_alloc` HWRM command.
28164 uint16_t cmpl_ring;
28166 * The sequence ID is used by the driver for tracking multiple
28167 * commands. This ID is treated as opaque data by the firmware and
28168 * the value is returned in the `hwrm_resp_hdr` upon completion.
28172 * The target ID of the command:
28173 * * 0x0-0xFFF8 - The function ID
28174 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28175 * * 0xFFFD - Reserved for user-space HWRM interface
28178 uint16_t target_id;
28180 * A physical address pointer pointing to a host buffer that the
28181 * command's response data will be written. This can be either a host
28182 * physical address (HPA) or a guest physical address (GPA) and must
28183 * point to a physically contiguous block of memory.
28185 uint64_t resp_addr;
28187 /* tunnel is 1 b */
28188 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
28190 /* num_vlan is 2 b */
28191 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
28193 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
28195 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
28196 (UINT32_C(0x0) << 1)
28198 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
28199 (UINT32_C(0x1) << 1)
28201 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
28202 (UINT32_C(0x2) << 1)
28203 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
28204 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
28205 /* Enumeration denoting the Flow Type. */
28206 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
28208 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
28210 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
28211 (UINT32_C(0x0) << 3)
28213 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
28214 (UINT32_C(0x1) << 3)
28216 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
28217 (UINT32_C(0x2) << 3)
28218 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
28219 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
28221 * when set to 1, indicates TX flow offload for function specified in src_fid and
28222 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
28223 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
28224 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
28225 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
28226 * belong to the children VFs of the same PF to indicate VM to VM flow.
28228 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
28231 * when set to 1, indicates RX flow offload for function specified in dst_fid and
28232 * the src_fid should be set to invalid value.
28234 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
28237 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
28238 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
28239 * This flag is only valid when the flow direction is RX.
28241 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
28243 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
28244 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
28251 /* Tunnel handle valid when tunnel flag is set. */
28252 uint32_t tunnel_handle;
28253 uint16_t action_flags;
28255 * Setting of this flag indicates drop action. If this flag is not set,
28256 * then it should be considered accept action.
28258 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
28260 /* recycle is 1 b */
28261 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
28264 * Setting of this flag indicates drop action. If this flag is not set,
28265 * then it should be considered accept action.
28267 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
28270 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
28272 /* tunnel is 1 b */
28273 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
28275 /* nat_src is 1 b */
28276 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
28278 /* nat_dest is 1 b */
28279 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
28281 /* nat_ipv4_address is 1 b */
28282 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
28284 /* l2_header_rewrite is 1 b */
28285 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
28287 /* ttl_decrement is 1 b */
28288 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
28291 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28292 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28293 * indicates decap of tunnel header and encap L2 header. The type of tunnel
28294 * is specified in the tunnel_type field.
28296 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
28298 /* If set to 1, flow aging is enabled for this flow. */
28299 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
28302 * If set to 1 an attempt will be made to try to offload this flow to the
28303 * most optimal flow table resource. If set to 0, the flow will be
28304 * placed to the default flow table resource.
28306 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
28309 * If set to 1 there will be no attempt to allocate an on-chip try to
28310 * offload this flow. If set to 0, which will keep compatibility with the
28311 * older drivers, will cause the FW to attempt to allocate an on-chip flow
28312 * counter for the newly created flow. This will keep the existing behavior
28313 * with EM flows which always had an associated flow counter.
28315 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
28318 * Tx Flow: pf or vf fid.
28322 /* VLAN tpid, valid when push_vlan flag is set. */
28323 uint16_t l2_rewrite_vlan_tpid;
28324 /* VLAN tci, valid when push_vlan flag is set. */
28325 uint16_t l2_rewrite_vlan_tci;
28326 /* Meter id, valid when meter flag is set. */
28327 uint16_t act_meter_id;
28328 /* Flow with the same l2 context tcam key. */
28329 uint16_t ref_flow_handle;
28330 /* This value sets the match value for the ethertype. */
28331 uint16_t ethertype;
28332 /* valid when num tags is 1 or 2. */
28333 uint16_t outer_vlan_tci;
28334 /* This value sets the match value for the Destination MAC address. */
28336 /* valid when num tags is 2. */
28337 uint16_t inner_vlan_tci;
28338 /* This value sets the match value for the Source MAC address. */
28340 /* The bit length of destination IP address mask. */
28341 uint8_t ip_dst_mask_len;
28342 /* The bit length of source IP address mask. */
28343 uint8_t ip_src_mask_len;
28344 /* The value of destination IPv4/IPv6 address. */
28345 uint32_t ip_dst[4];
28346 /* The source IPv4/IPv6 address. */
28347 uint32_t ip_src[4];
28349 * The value of source port.
28350 * Applies to UDP and TCP traffic.
28352 uint16_t l4_src_port;
28354 * The value of source port mask.
28355 * Applies to UDP and TCP traffic.
28357 uint16_t l4_src_port_mask;
28359 * The value of destination port.
28360 * Applies to UDP and TCP traffic.
28362 uint16_t l4_dst_port;
28364 * The value of destination port mask.
28365 * Applies to UDP and TCP traffic.
28367 uint16_t l4_dst_port_mask;
28369 * NAT IPv4/6 address based on address type flag.
28370 * 0 values are ignored.
28372 uint32_t nat_ip_address[4];
28373 /* L2 header re-write Destination MAC address. */
28374 uint16_t l2_rewrite_dmac[3];
28376 * The NAT source/destination port based on direction flag.
28377 * Applies to UDP and TCP traffic.
28378 * 0 values are ignored.
28381 /* L2 header re-write Source MAC address. */
28382 uint16_t l2_rewrite_smac[3];
28383 /* The value of ip protocol. */
28386 uint8_t tunnel_type;
28388 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28390 /* Virtual eXtensible Local Area Network (VXLAN) */
28391 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28393 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28394 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28396 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28397 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28400 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28402 /* Generic Network Virtualization Encapsulation (Geneve) */
28403 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28405 /* Multi-Protocol Lable Switching (MPLS) */
28406 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28408 /* Stateless Transport Tunnel (STT) */
28409 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
28411 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28412 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28414 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28415 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28417 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28418 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28420 /* Use fixed layer 2 ether type of 0xFFFF */
28421 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28423 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28424 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28426 /* Any tunneled traffic */
28427 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28429 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28430 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28431 } __attribute__((packed));
28433 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
28434 struct hwrm_cfa_flow_alloc_output {
28435 /* The specific error status for the command. */
28436 uint16_t error_code;
28437 /* The HWRM command request type. */
28439 /* The sequence ID from the original command. */
28441 /* The length of the response data in number of bytes. */
28443 /* Flow record index. */
28444 uint16_t flow_handle;
28445 uint8_t unused_0[2];
28447 * The flow id value in bit 0-29 is the actual ID of the flow
28448 * associated with this filter and it shall be used to match
28449 * and associate the flow identifier returned in completion
28450 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28451 * shall indicate no valid flow id.
28454 /* Indicate the flow id value. */
28455 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28456 UINT32_C(0x3fffffff)
28457 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28458 /* Indicate type of the flow. */
28459 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
28460 UINT32_C(0x40000000)
28462 * If this bit set to 0, then it indicates that the flow is
28465 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28466 (UINT32_C(0x0) << 30)
28468 * If this bit is set to 1, then it indicates that the flow is
28471 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28472 (UINT32_C(0x1) << 30)
28473 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28474 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28475 /* Indicate the flow direction. */
28476 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
28477 UINT32_C(0x80000000)
28478 /* If this bit set to 0, then it indicates rx flow. */
28479 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28480 (UINT32_C(0x0) << 31)
28481 /* If this bit is set to 1, then it indicates that tx flow. */
28482 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28483 (UINT32_C(0x1) << 31)
28484 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28485 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28486 /* This value identifies a set of CFA data structures used for a flow. */
28487 uint64_t ext_flow_handle;
28488 uint32_t flow_counter_id;
28489 uint8_t unused_1[3];
28491 * This field is used in Output records to indicate that the output
28492 * is completely written to RAM. This field should be read as '1'
28493 * to indicate that the output has been completely written.
28494 * When writing a command completion or response to an internal processor,
28495 * the order of writes has to be such that this field is written last.
28498 } __attribute__((packed));
28500 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
28501 struct hwrm_cfa_flow_alloc_cmd_err {
28503 * command specific error codes that goes to
28504 * the cmd_err field in Common HWRM Error Response.
28507 /* Unknown error */
28508 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28509 /* No more L2 Context TCAM */
28510 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
28511 /* No more action records */
28512 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
28513 /* No more flow counters */
28514 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
28515 /* No more wild-card TCAM */
28516 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
28517 /* Hash collsion in exact match tables */
28518 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
28519 /* Key is already installed */
28520 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
28521 /* Flow Context DB is out of resource */
28522 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
28523 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
28524 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
28525 uint8_t unused_0[7];
28526 } __attribute__((packed));
28528 /**********************
28529 * hwrm_cfa_flow_free *
28530 **********************/
28533 /* hwrm_cfa_flow_free_input (size:256b/32B) */
28534 struct hwrm_cfa_flow_free_input {
28535 /* The HWRM command request type. */
28538 * The completion ring to send the completion event on. This should
28539 * be the NQ ID returned from the `nq_alloc` HWRM command.
28541 uint16_t cmpl_ring;
28543 * The sequence ID is used by the driver for tracking multiple
28544 * commands. This ID is treated as opaque data by the firmware and
28545 * the value is returned in the `hwrm_resp_hdr` upon completion.
28549 * The target ID of the command:
28550 * * 0x0-0xFFF8 - The function ID
28551 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28552 * * 0xFFFD - Reserved for user-space HWRM interface
28555 uint16_t target_id;
28557 * A physical address pointer pointing to a host buffer that the
28558 * command's response data will be written. This can be either a host
28559 * physical address (HPA) or a guest physical address (GPA) and must
28560 * point to a physically contiguous block of memory.
28562 uint64_t resp_addr;
28563 /* Flow record index. */
28564 uint16_t flow_handle;
28566 /* Flow counter id to be freed. */
28567 uint32_t flow_counter_id;
28568 /* This value identifies a set of CFA data structures used for a flow. */
28569 uint64_t ext_flow_handle;
28570 } __attribute__((packed));
28572 /* hwrm_cfa_flow_free_output (size:256b/32B) */
28573 struct hwrm_cfa_flow_free_output {
28574 /* The specific error status for the command. */
28575 uint16_t error_code;
28576 /* The HWRM command request type. */
28578 /* The sequence ID from the original command. */
28580 /* The length of the response data in number of bytes. */
28582 /* packet is 64 b */
28586 uint8_t unused_0[7];
28588 * This field is used in Output records to indicate that the output
28589 * is completely written to RAM. This field should be read as '1'
28590 * to indicate that the output has been completely written.
28591 * When writing a command completion or response to an internal processor,
28592 * the order of writes has to be such that this field is written last.
28595 } __attribute__((packed));
28597 /* hwrm_cfa_flow_action_data (size:960b/120B) */
28598 struct hwrm_cfa_flow_action_data {
28599 uint16_t action_flags;
28600 /* Setting of this flag indicates accept action. */
28601 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
28603 /* Setting of this flag indicates recycle action. */
28604 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
28606 /* Setting of this flag indicates drop action. */
28607 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
28609 /* Setting of this flag indicates meter action. */
28610 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
28612 /* Setting of this flag indicates tunnel action. */
28613 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
28616 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28617 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28618 * indicates decap of tunnel header and encap L2 header.
28620 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
28622 /* Setting of this flag indicates ttl decrement action. */
28623 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
28625 /* If set to 1, flow aging is enabled for this flow. */
28626 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
28628 /* Setting of this flag indicates encap action.. */
28629 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
28631 /* Setting of this flag indicates decap action.. */
28632 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
28635 uint16_t act_meter_id;
28638 /* vport number. */
28640 /* The NAT source/destination. */
28642 uint16_t unused_0[3];
28643 /* NAT IPv4/IPv6 address. */
28644 uint32_t nat_ip_address[4];
28645 /* Encapsulation Type. */
28646 uint8_t encap_type;
28647 /* Virtual eXtensible Local Area Network (VXLAN) */
28648 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
28649 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28650 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
28651 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
28652 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
28654 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
28655 /* Generic Network Virtualization Encapsulation (Geneve) */
28656 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
28657 /* Multi-Protocol Lable Switching (MPLS) */
28658 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
28660 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
28661 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28662 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
28663 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28664 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
28665 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28666 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
28667 /* Use fixed layer 2 ether type of 0xFFFF */
28668 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
28669 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28670 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
28671 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
28672 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
28674 /* This value is encap data for the associated encap type. */
28675 uint32_t encap_data[20];
28676 } __attribute__((packed));
28678 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
28679 struct hwrm_cfa_flow_tunnel_hdr_data {
28681 uint8_t tunnel_type;
28683 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
28685 /* Virtual eXtensible Local Area Network (VXLAN) */
28686 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
28688 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28689 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
28691 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28692 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
28695 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
28697 /* Generic Network Virtualization Encapsulation (Geneve) */
28698 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
28700 /* Multi-Protocol Lable Switching (MPLS) */
28701 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
28703 /* Stateless Transport Tunnel (STT) */
28704 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
28706 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28707 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
28709 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28710 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
28712 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28713 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
28715 /* Use fixed layer 2 ether type of 0xFFFF */
28716 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
28718 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28719 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
28721 /* Any tunneled traffic */
28722 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
28724 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
28725 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
28728 * Tunnel identifier.
28729 * Virtual Network Identifier (VNI).
28731 uint32_t tunnel_id;
28732 } __attribute__((packed));
28734 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
28735 struct hwrm_cfa_flow_l4_key_data {
28736 /* The value of source port. */
28737 uint16_t l4_src_port;
28738 /* The value of destination port. */
28739 uint16_t l4_dst_port;
28741 } __attribute__((packed));
28743 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
28744 struct hwrm_cfa_flow_l3_key_data {
28745 /* The value of ip protocol. */
28746 uint8_t ip_protocol;
28747 uint8_t unused_0[7];
28748 /* The value of destination IPv4/IPv6 address. */
28749 uint32_t ip_dst[4];
28750 /* The source IPv4/IPv6 address. */
28751 uint32_t ip_src[4];
28752 /* NAT IPv4/IPv6 address. */
28753 uint32_t nat_ip_address[4];
28754 uint32_t unused[2];
28755 } __attribute__((packed));
28757 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
28758 struct hwrm_cfa_flow_l2_key_data {
28759 /* Destination MAC address. */
28762 /* Source MAC address. */
28765 /* L2 header re-write Destination MAC address. */
28766 uint16_t l2_rewrite_dmac[3];
28768 /* L2 header re-write Source MAC address. */
28769 uint16_t l2_rewrite_smac[3];
28771 uint16_t ethertype;
28772 /* Number of VLAN tags. */
28773 uint16_t num_vlan_tags;
28775 uint16_t l2_rewrite_vlan_tpid;
28777 uint16_t l2_rewrite_vlan_tci;
28778 uint8_t unused_3[2];
28779 /* Outer VLAN TPID. */
28780 uint16_t ovlan_tpid;
28781 /* Outer VLAN TCI. */
28782 uint16_t ovlan_tci;
28783 /* Inner VLAN TPID. */
28784 uint16_t ivlan_tpid;
28785 /* Inner VLAN TCI. */
28786 uint16_t ivlan_tci;
28788 } __attribute__((packed));
28790 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
28791 struct hwrm_cfa_flow_key_data {
28792 /* Flow associated tunnel L2 header key info. */
28793 uint32_t t_l2_key_data[14];
28794 /* Flow associated tunnel L2 header mask info. */
28795 uint32_t t_l2_key_mask[14];
28796 /* Flow associated tunnel L3 header key info. */
28797 uint32_t t_l3_key_data[16];
28798 /* Flow associated tunnel L3 header mask info. */
28799 uint32_t t_l3_key_mask[16];
28800 /* Flow associated tunnel L4 header key info. */
28801 uint32_t t_l4_key_data[2];
28802 /* Flow associated tunnel L4 header mask info. */
28803 uint32_t t_l4_key_mask[2];
28804 /* Flow associated tunnel header info. */
28805 uint32_t tunnel_hdr[2];
28806 /* Flow associated L2 header key info. */
28807 uint32_t l2_key_data[14];
28808 /* Flow associated L2 header mask info. */
28809 uint32_t l2_key_mask[14];
28810 /* Flow associated L3 header key info. */
28811 uint32_t l3_key_data[16];
28812 /* Flow associated L3 header mask info. */
28813 uint32_t l3_key_mask[16];
28814 /* Flow associated L4 header key info. */
28815 uint32_t l4_key_data[2];
28816 /* Flow associated L4 header mask info. */
28817 uint32_t l4_key_mask[2];
28818 } __attribute__((packed));
28820 /**********************
28821 * hwrm_cfa_flow_info *
28822 **********************/
28825 /* hwrm_cfa_flow_info_input (size:256b/32B) */
28826 struct hwrm_cfa_flow_info_input {
28827 /* The HWRM command request type. */
28830 * The completion ring to send the completion event on. This should
28831 * be the NQ ID returned from the `nq_alloc` HWRM command.
28833 uint16_t cmpl_ring;
28835 * The sequence ID is used by the driver for tracking multiple
28836 * commands. This ID is treated as opaque data by the firmware and
28837 * the value is returned in the `hwrm_resp_hdr` upon completion.
28841 * The target ID of the command:
28842 * * 0x0-0xFFF8 - The function ID
28843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28844 * * 0xFFFD - Reserved for user-space HWRM interface
28847 uint16_t target_id;
28849 * A physical address pointer pointing to a host buffer that the
28850 * command's response data will be written. This can be either a host
28851 * physical address (HPA) or a guest physical address (GPA) and must
28852 * point to a physically contiguous block of memory.
28854 uint64_t resp_addr;
28855 /* Flow record index. */
28856 uint16_t flow_handle;
28857 /* Max flow handle */
28858 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
28860 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
28861 /* CNP flow handle */
28862 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
28864 /* RoCEv1 flow handle */
28865 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
28867 /* RoCEv2 flow handle */
28868 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
28870 /* Direction rx = 1 */
28871 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
28873 uint8_t unused_0[6];
28874 /* This value identifies a set of CFA data structures used for a flow. */
28875 uint64_t ext_flow_handle;
28876 } __attribute__((packed));
28878 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
28879 struct hwrm_cfa_flow_info_output {
28880 /* The specific error status for the command. */
28881 uint16_t error_code;
28882 /* The HWRM command request type. */
28884 /* The sequence ID from the original command. */
28886 /* The length of the response data in number of bytes. */
28889 /* When set to 1, indicates the configuration is the TX flow. */
28890 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
28891 /* When set to 1, indicates the configuration is the RX flow. */
28892 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
28893 /* profile is 8 b */
28895 /* src_fid is 16 b */
28897 /* dst_fid is 16 b */
28899 /* l2_ctxt_id is 16 b */
28900 uint16_t l2_ctxt_id;
28901 /* em_info is 64 b */
28903 /* tcam_info is 64 b */
28904 uint64_t tcam_info;
28905 /* vfp_tcam_info is 64 b */
28906 uint64_t vfp_tcam_info;
28907 /* ar_id is 16 b */
28909 /* flow_handle is 16 b */
28910 uint16_t flow_handle;
28911 /* tunnel_handle is 32 b */
28912 uint32_t tunnel_handle;
28913 /* The flow aging timer for the flow, the unit is 100 milliseconds */
28914 uint16_t flow_timer;
28915 uint8_t unused_0[6];
28916 /* Flow associated L2, L3 and L4 headers info. */
28917 uint32_t flow_key_data[130];
28918 /* Flow associated action record info. */
28919 uint32_t flow_action_info[30];
28920 uint8_t unused_1[7];
28922 * This field is used in Output records to indicate that the output
28923 * is completely written to RAM. This field should be read as '1'
28924 * to indicate that the output has been completely written.
28925 * When writing a command completion or response to an internal processor,
28926 * the order of writes has to be such that this field is written last.
28929 } __attribute__((packed));
28931 /***********************
28932 * hwrm_cfa_flow_flush *
28933 ***********************/
28936 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
28937 struct hwrm_cfa_flow_flush_input {
28938 /* The HWRM command request type. */
28941 * The completion ring to send the completion event on. This should
28942 * be the NQ ID returned from the `nq_alloc` HWRM command.
28944 uint16_t cmpl_ring;
28946 * The sequence ID is used by the driver for tracking multiple
28947 * commands. This ID is treated as opaque data by the firmware and
28948 * the value is returned in the `hwrm_resp_hdr` upon completion.
28952 * The target ID of the command:
28953 * * 0x0-0xFFF8 - The function ID
28954 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28955 * * 0xFFFD - Reserved for user-space HWRM interface
28958 uint16_t target_id;
28960 * A physical address pointer pointing to a host buffer that the
28961 * command's response data will be written. This can be either a host
28962 * physical address (HPA) or a guest physical address (GPA) and must
28963 * point to a physically contiguous block of memory.
28965 uint64_t resp_addr;
28966 /* flags is 32 b */
28969 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
28970 * fields are valid. The flow flush operation should only flush the flows from the
28971 * flow table specified. This flag is set to 0 by older driver. For older firmware,
28972 * setting this flag has no effect.
28974 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
28977 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
28978 * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
28979 * setting this flag has no effect.
28981 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
28984 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
28985 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
28987 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
28989 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
28990 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
28991 UINT32_C(0x8000000)
28993 * This specifies the size of flow handle entries provided by the driver
28994 * in the flow table specified below. Only two flow handle size enums are defined.
28996 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
28997 UINT32_C(0xc0000000)
28998 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
29000 /* The flow handle is 16bit */
29001 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
29002 (UINT32_C(0x0) << 30)
29003 /* The flow handle is 64bit */
29004 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
29005 (UINT32_C(0x1) << 30)
29006 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
29007 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
29008 /* Specify page size of the flow table memory. */
29010 /* The page size is 4K */
29011 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29012 /* The page size is 8K */
29013 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29014 /* The page size is 64K */
29015 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29016 /* The page size is 256K */
29017 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29018 /* The page size is 1M */
29019 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29020 /* The page size is 2M */
29021 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29022 /* The page size is 4M */
29023 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29024 /* The page size is 1G */
29025 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29026 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
29027 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
29028 /* FLow table memory indirect levels. */
29029 uint8_t page_level;
29030 /* PBL pointer is physical start address. */
29031 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29032 /* PBL pointer points to PTE table. */
29033 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29034 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29035 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29036 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
29037 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
29038 /* number of flows in the flow table */
29039 uint16_t num_flows;
29040 /* Pointer to the PBL, or PDL depending on number of levels */
29042 } __attribute__((packed));
29044 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
29045 struct hwrm_cfa_flow_flush_output {
29046 /* The specific error status for the command. */
29047 uint16_t error_code;
29048 /* The HWRM command request type. */
29050 /* The sequence ID from the original command. */
29052 /* The length of the response data in number of bytes. */
29054 uint8_t unused_0[7];
29056 * This field is used in Output records to indicate that the output
29057 * is completely written to RAM. This field should be read as '1'
29058 * to indicate that the output has been completely written.
29059 * When writing a command completion or response to an internal processor,
29060 * the order of writes has to be such that this field is written last.
29063 } __attribute__((packed));
29065 /***********************
29066 * hwrm_cfa_flow_stats *
29067 ***********************/
29070 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
29071 struct hwrm_cfa_flow_stats_input {
29072 /* The HWRM command request type. */
29075 * The completion ring to send the completion event on. This should
29076 * be the NQ ID returned from the `nq_alloc` HWRM command.
29078 uint16_t cmpl_ring;
29080 * The sequence ID is used by the driver for tracking multiple
29081 * commands. This ID is treated as opaque data by the firmware and
29082 * the value is returned in the `hwrm_resp_hdr` upon completion.
29086 * The target ID of the command:
29087 * * 0x0-0xFFF8 - The function ID
29088 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29089 * * 0xFFFD - Reserved for user-space HWRM interface
29092 uint16_t target_id;
29094 * A physical address pointer pointing to a host buffer that the
29095 * command's response data will be written. This can be either a host
29096 * physical address (HPA) or a guest physical address (GPA) and must
29097 * point to a physically contiguous block of memory.
29099 uint64_t resp_addr;
29101 uint16_t num_flows;
29103 uint16_t flow_handle_0;
29105 uint16_t flow_handle_1;
29107 uint16_t flow_handle_2;
29109 uint16_t flow_handle_3;
29111 uint16_t flow_handle_4;
29113 uint16_t flow_handle_5;
29115 uint16_t flow_handle_6;
29117 uint16_t flow_handle_7;
29119 uint16_t flow_handle_8;
29121 uint16_t flow_handle_9;
29122 uint8_t unused_0[2];
29123 /* Flow ID of a flow. */
29124 uint32_t flow_id_0;
29125 /* Flow ID of a flow. */
29126 uint32_t flow_id_1;
29127 /* Flow ID of a flow. */
29128 uint32_t flow_id_2;
29129 /* Flow ID of a flow. */
29130 uint32_t flow_id_3;
29131 /* Flow ID of a flow. */
29132 uint32_t flow_id_4;
29133 /* Flow ID of a flow. */
29134 uint32_t flow_id_5;
29135 /* Flow ID of a flow. */
29136 uint32_t flow_id_6;
29137 /* Flow ID of a flow. */
29138 uint32_t flow_id_7;
29139 /* Flow ID of a flow. */
29140 uint32_t flow_id_8;
29141 /* Flow ID of a flow. */
29142 uint32_t flow_id_9;
29143 } __attribute__((packed));
29145 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
29146 struct hwrm_cfa_flow_stats_output {
29147 /* The specific error status for the command. */
29148 uint16_t error_code;
29149 /* The HWRM command request type. */
29151 /* The sequence ID from the original command. */
29153 /* The length of the response data in number of bytes. */
29155 /* packet_0 is 64 b */
29157 /* packet_1 is 64 b */
29159 /* packet_2 is 64 b */
29161 /* packet_3 is 64 b */
29163 /* packet_4 is 64 b */
29165 /* packet_5 is 64 b */
29167 /* packet_6 is 64 b */
29169 /* packet_7 is 64 b */
29171 /* packet_8 is 64 b */
29173 /* packet_9 is 64 b */
29175 /* byte_0 is 64 b */
29177 /* byte_1 is 64 b */
29179 /* byte_2 is 64 b */
29181 /* byte_3 is 64 b */
29183 /* byte_4 is 64 b */
29185 /* byte_5 is 64 b */
29187 /* byte_6 is 64 b */
29189 /* byte_7 is 64 b */
29191 /* byte_8 is 64 b */
29193 /* byte_9 is 64 b */
29195 uint8_t unused_0[7];
29197 * This field is used in Output records to indicate that the output
29198 * is completely written to RAM. This field should be read as '1'
29199 * to indicate that the output has been completely written.
29200 * When writing a command completion or response to an internal processor,
29201 * the order of writes has to be such that this field is written last.
29204 } __attribute__((packed));
29206 /***********************************
29207 * hwrm_cfa_flow_aging_timer_reset *
29208 ***********************************/
29211 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
29212 struct hwrm_cfa_flow_aging_timer_reset_input {
29213 /* The HWRM command request type. */
29216 * The completion ring to send the completion event on. This should
29217 * be the NQ ID returned from the `nq_alloc` HWRM command.
29219 uint16_t cmpl_ring;
29221 * The sequence ID is used by the driver for tracking multiple
29222 * commands. This ID is treated as opaque data by the firmware and
29223 * the value is returned in the `hwrm_resp_hdr` upon completion.
29227 * The target ID of the command:
29228 * * 0x0-0xFFF8 - The function ID
29229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29230 * * 0xFFFD - Reserved for user-space HWRM interface
29233 uint16_t target_id;
29235 * A physical address pointer pointing to a host buffer that the
29236 * command's response data will be written. This can be either a host
29237 * physical address (HPA) or a guest physical address (GPA) and must
29238 * point to a physically contiguous block of memory.
29240 uint64_t resp_addr;
29241 /* Flow record index. */
29242 uint16_t flow_handle;
29243 uint8_t unused_0[2];
29245 * New flow timer value for the flow specified in the ext_flow_handle.
29246 * The flow timer unit is 100ms.
29248 uint32_t flow_timer;
29249 /* This value identifies a set of CFA data structures used for a flow. */
29250 uint64_t ext_flow_handle;
29251 } __attribute__((packed));
29253 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
29254 struct hwrm_cfa_flow_aging_timer_reset_output {
29255 /* The specific error status for the command. */
29256 uint16_t error_code;
29257 /* The HWRM command request type. */
29259 /* The sequence ID from the original command. */
29261 /* The length of the response data in number of bytes. */
29263 uint8_t unused_0[7];
29265 * This field is used in Output records to indicate that the output
29266 * is completely written to RAM. This field should be read as '1'
29267 * to indicate that the output has been completely written.
29268 * When writing a command completion or response to an internal processor,
29269 * the order of writes has to be such that this field is written last.
29272 } __attribute__((packed));
29274 /***************************
29275 * hwrm_cfa_flow_aging_cfg *
29276 ***************************/
29279 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
29280 struct hwrm_cfa_flow_aging_cfg_input {
29281 /* The HWRM command request type. */
29284 * The completion ring to send the completion event on. This should
29285 * be the NQ ID returned from the `nq_alloc` HWRM command.
29287 uint16_t cmpl_ring;
29289 * The sequence ID is used by the driver for tracking multiple
29290 * commands. This ID is treated as opaque data by the firmware and
29291 * the value is returned in the `hwrm_resp_hdr` upon completion.
29295 * The target ID of the command:
29296 * * 0x0-0xFFF8 - The function ID
29297 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29298 * * 0xFFFD - Reserved for user-space HWRM interface
29301 uint16_t target_id;
29303 * A physical address pointer pointing to a host buffer that the
29304 * command's response data will be written. This can be either a host
29305 * physical address (HPA) or a guest physical address (GPA) and must
29306 * point to a physically contiguous block of memory.
29308 uint64_t resp_addr;
29309 /* The bit field to enable per flow aging configuration. */
29311 /* This bit must be '1' for the tcp flow timer field to be configured */
29312 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
29314 /* This bit must be '1' for the tcp finish timer field to be configured */
29315 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
29317 /* This bit must be '1' for the udp flow timer field to be configured */
29318 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
29320 /* This bit must be '1' for the eem dma interval field to be configured */
29321 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
29323 /* This bit must be '1' for the eem notice interval field to be configured */
29324 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
29326 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
29327 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
29329 /* This bit must be '1' for the eem context memory ID field to be configured */
29330 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
29332 /* This bit must be '1' for the eem context memory type field to be configured */
29333 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
29336 /* Enumeration denoting the RX, TX type of the resource. */
29337 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29339 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29341 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29342 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
29343 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
29344 /* Enumeration denoting the enable, disable eem flow aging configuration. */
29345 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
29347 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
29348 (UINT32_C(0x0) << 1)
29350 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
29351 (UINT32_C(0x1) << 1)
29352 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
29353 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
29355 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
29356 uint32_t tcp_flow_timer;
29357 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
29358 uint32_t tcp_fin_timer;
29359 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
29360 uint32_t udp_flow_timer;
29361 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29362 uint16_t eem_dma_interval;
29363 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29364 uint16_t eem_notice_interval;
29365 /* The maximum entries number in the eem context memory. */
29366 uint32_t eem_ctx_max_entries;
29367 /* The context memory ID for eem flow aging. */
29368 uint16_t eem_ctx_id;
29369 uint16_t eem_ctx_mem_type;
29370 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
29371 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
29373 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
29374 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
29375 uint8_t unused_1[4];
29376 } __attribute__((packed));
29378 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
29379 struct hwrm_cfa_flow_aging_cfg_output {
29380 /* The specific error status for the command. */
29381 uint16_t error_code;
29382 /* The HWRM command request type. */
29384 /* The sequence ID from the original command. */
29386 /* The length of the response data in number of bytes. */
29388 uint8_t unused_0[7];
29390 * This field is used in Output records to indicate that the output
29391 * is completely written to RAM. This field should be read as '1'
29392 * to indicate that the output has been completely written.
29393 * When writing a command completion or response to an internal processor,
29394 * the order of writes has to be such that this field is written last.
29397 } __attribute__((packed));
29399 /****************************
29400 * hwrm_cfa_flow_aging_qcfg *
29401 ****************************/
29404 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
29405 struct hwrm_cfa_flow_aging_qcfg_input {
29406 /* The HWRM command request type. */
29409 * The completion ring to send the completion event on. This should
29410 * be the NQ ID returned from the `nq_alloc` HWRM command.
29412 uint16_t cmpl_ring;
29414 * The sequence ID is used by the driver for tracking multiple
29415 * commands. This ID is treated as opaque data by the firmware and
29416 * the value is returned in the `hwrm_resp_hdr` upon completion.
29420 * The target ID of the command:
29421 * * 0x0-0xFFF8 - The function ID
29422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29423 * * 0xFFFD - Reserved for user-space HWRM interface
29426 uint16_t target_id;
29428 * A physical address pointer pointing to a host buffer that the
29429 * command's response data will be written. This can be either a host
29430 * physical address (HPA) or a guest physical address (GPA) and must
29431 * point to a physically contiguous block of memory.
29433 uint64_t resp_addr;
29434 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29436 /* Enumeration denoting the RX, TX type of the resource. */
29437 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29439 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29441 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29442 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
29443 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
29444 uint8_t unused_0[7];
29445 } __attribute__((packed));
29447 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
29448 struct hwrm_cfa_flow_aging_qcfg_output {
29449 /* The specific error status for the command. */
29450 uint16_t error_code;
29451 /* The HWRM command request type. */
29453 /* The sequence ID from the original command. */
29455 /* The length of the response data in number of bytes. */
29457 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
29458 uint32_t tcp_flow_timer;
29459 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29460 uint32_t tcp_fin_timer;
29461 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
29462 uint32_t udp_flow_timer;
29463 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29464 uint16_t eem_dma_interval;
29465 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29466 uint16_t eem_notice_interval;
29467 /* The maximum entries number in the eem context memory. */
29468 uint32_t eem_ctx_max_entries;
29469 /* The context memory ID for eem flow aging. */
29470 uint16_t eem_ctx_id;
29471 /* The context memory type for eem flow aging. */
29472 uint16_t eem_ctx_mem_type;
29473 uint8_t unused_0[7];
29475 * This field is used in Output records to indicate that the output
29476 * is completely written to RAM. This field should be read as '1'
29477 * to indicate that the output has been completely written.
29478 * When writing a command completion or response to an internal processor,
29479 * the order of writes has to be such that this field is written last.
29482 } __attribute__((packed));
29484 /*****************************
29485 * hwrm_cfa_flow_aging_qcaps *
29486 *****************************/
29489 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
29490 struct hwrm_cfa_flow_aging_qcaps_input {
29491 /* The HWRM command request type. */
29494 * The completion ring to send the completion event on. This should
29495 * be the NQ ID returned from the `nq_alloc` HWRM command.
29497 uint16_t cmpl_ring;
29499 * The sequence ID is used by the driver for tracking multiple
29500 * commands. This ID is treated as opaque data by the firmware and
29501 * the value is returned in the `hwrm_resp_hdr` upon completion.
29505 * The target ID of the command:
29506 * * 0x0-0xFFF8 - The function ID
29507 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29508 * * 0xFFFD - Reserved for user-space HWRM interface
29511 uint16_t target_id;
29513 * A physical address pointer pointing to a host buffer that the
29514 * command's response data will be written. This can be either a host
29515 * physical address (HPA) or a guest physical address (GPA) and must
29516 * point to a physically contiguous block of memory.
29518 uint64_t resp_addr;
29519 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29521 /* Enumeration denoting the RX, TX type of the resource. */
29522 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
29524 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29526 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29527 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
29528 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
29529 uint8_t unused_0[7];
29530 } __attribute__((packed));
29532 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
29533 struct hwrm_cfa_flow_aging_qcaps_output {
29534 /* The specific error status for the command. */
29535 uint16_t error_code;
29536 /* The HWRM command request type. */
29538 /* The sequence ID from the original command. */
29540 /* The length of the response data in number of bytes. */
29542 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
29543 uint32_t max_tcp_flow_timer;
29544 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29545 uint32_t max_tcp_fin_timer;
29546 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
29547 uint32_t max_udp_flow_timer;
29548 /* The maximum aging flows that HW can support. */
29549 uint32_t max_aging_flows;
29550 uint8_t unused_0[7];
29552 * This field is used in Output records to indicate that the output
29553 * is completely written to RAM. This field should be read as '1'
29554 * to indicate that the output has been completely written.
29555 * When writing a command completion or response to an internal processor,
29556 * the order of writes has to be such that this field is written last.
29559 } __attribute__((packed));
29561 /**********************************
29562 * hwrm_cfa_tcp_flag_process_qcfg *
29563 **********************************/
29566 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
29567 struct hwrm_cfa_tcp_flag_process_qcfg_input {
29568 /* The HWRM command request type. */
29571 * The completion ring to send the completion event on. This should
29572 * be the NQ ID returned from the `nq_alloc` HWRM command.
29574 uint16_t cmpl_ring;
29576 * The sequence ID is used by the driver for tracking multiple
29577 * commands. This ID is treated as opaque data by the firmware and
29578 * the value is returned in the `hwrm_resp_hdr` upon completion.
29582 * The target ID of the command:
29583 * * 0x0-0xFFF8 - The function ID
29584 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29585 * * 0xFFFD - Reserved for user-space HWRM interface
29588 uint16_t target_id;
29590 * A physical address pointer pointing to a host buffer that the
29591 * command's response data will be written. This can be either a host
29592 * physical address (HPA) or a guest physical address (GPA) and must
29593 * point to a physically contiguous block of memory.
29595 uint64_t resp_addr;
29596 } __attribute__((packed));
29598 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
29599 struct hwrm_cfa_tcp_flag_process_qcfg_output {
29600 /* The specific error status for the command. */
29601 uint16_t error_code;
29602 /* The HWRM command request type. */
29604 /* The sequence ID from the original command. */
29606 /* The length of the response data in number of bytes. */
29608 /* The port 0 RX mirror action record ID. */
29609 uint16_t rx_ar_id_port0;
29610 /* The port 1 RX mirror action record ID. */
29611 uint16_t rx_ar_id_port1;
29612 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
29613 uint16_t tx_ar_id_port0;
29614 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
29615 uint16_t tx_ar_id_port1;
29616 uint8_t unused_0[7];
29618 * This field is used in Output records to indicate that the output
29619 * is completely written to RAM. This field should be read as '1'
29620 * to indicate that the output has been completely written.
29621 * When writing a command completion or response to an internal processor,
29622 * the order of writes has to be such that this field is written last.
29625 } __attribute__((packed));
29627 /**********************
29628 * hwrm_cfa_pair_info *
29629 **********************/
29632 /* hwrm_cfa_pair_info_input (size:448b/56B) */
29633 struct hwrm_cfa_pair_info_input {
29634 /* The HWRM command request type. */
29637 * The completion ring to send the completion event on. This should
29638 * be the NQ ID returned from the `nq_alloc` HWRM command.
29640 uint16_t cmpl_ring;
29642 * The sequence ID is used by the driver for tracking multiple
29643 * commands. This ID is treated as opaque data by the firmware and
29644 * the value is returned in the `hwrm_resp_hdr` upon completion.
29648 * The target ID of the command:
29649 * * 0x0-0xFFF8 - The function ID
29650 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29651 * * 0xFFFD - Reserved for user-space HWRM interface
29654 uint16_t target_id;
29656 * A physical address pointer pointing to a host buffer that the
29657 * command's response data will be written. This can be either a host
29658 * physical address (HPA) or a guest physical address (GPA) and must
29659 * point to a physically contiguous block of memory.
29661 uint64_t resp_addr;
29663 /* If this flag is set, lookup by name else lookup by index. */
29664 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
29665 /* If this flag is set, lookup by PF id and VF id. */
29666 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
29667 /* Pair table index. */
29668 uint16_t pair_index;
29669 /* Pair pf index. */
29671 /* Pair vf index. */
29673 /* Pair name (32 byte string). */
29674 char pair_name[32];
29675 } __attribute__((packed));
29677 /* hwrm_cfa_pair_info_output (size:576b/72B) */
29678 struct hwrm_cfa_pair_info_output {
29679 /* The specific error status for the command. */
29680 uint16_t error_code;
29681 /* The HWRM command request type. */
29683 /* The sequence ID from the original command. */
29685 /* The length of the response data in number of bytes. */
29687 /* Pair table index. */
29688 uint16_t next_pair_index;
29689 /* Pair member a's fid. */
29691 /* Logical host number. */
29692 uint8_t host_a_index;
29693 /* Logical PF number. */
29694 uint8_t pf_a_index;
29695 /* Pair member a's Linux logical VF number. */
29696 uint16_t vf_a_index;
29698 uint16_t rx_cfa_code_a;
29699 /* Tx CFA action. */
29700 uint16_t tx_cfa_action_a;
29701 /* Pair member b's fid. */
29703 /* Logical host number. */
29704 uint8_t host_b_index;
29705 /* Logical PF number. */
29706 uint8_t pf_b_index;
29707 /* Pair member a's Linux logical VF number. */
29708 uint16_t vf_b_index;
29710 uint16_t rx_cfa_code_b;
29711 /* Tx CFA action. */
29712 uint16_t tx_cfa_action_b;
29713 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
29715 /* Pair between VF on local host with PF or VF on specified host. */
29716 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
29717 /* Pair between REP on local host with PF or VF on specified host. */
29718 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
29719 /* Pair between REP on local host with REP on specified host. */
29720 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
29721 /* Pair for the proxy interface. */
29722 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
29723 /* Pair for the PF interface. */
29724 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
29725 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
29726 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
29728 uint8_t pair_state;
29729 /* Pair has been allocated */
29730 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
29731 /* Both pair members are active */
29732 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
29733 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
29734 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
29735 /* Pair name (32 byte string). */
29736 char pair_name[32];
29737 uint8_t unused_0[7];
29739 * This field is used in Output records to indicate that the output
29740 * is completely written to RAM. This field should be read as '1'
29741 * to indicate that the output has been completely written.
29742 * When writing a command completion or response to an internal processor,
29743 * the order of writes has to be such that this field is written last.
29746 } __attribute__((packed));
29748 /***************************************
29749 * hwrm_cfa_redirect_query_tunnel_type *
29750 ***************************************/
29753 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
29754 struct hwrm_cfa_redirect_query_tunnel_type_input {
29755 /* The HWRM command request type. */
29758 * The completion ring to send the completion event on. This should
29759 * be the NQ ID returned from the `nq_alloc` HWRM command.
29761 uint16_t cmpl_ring;
29763 * The sequence ID is used by the driver for tracking multiple
29764 * commands. This ID is treated as opaque data by the firmware and
29765 * the value is returned in the `hwrm_resp_hdr` upon completion.
29769 * The target ID of the command:
29770 * * 0x0-0xFFF8 - The function ID
29771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29772 * * 0xFFFD - Reserved for user-space HWRM interface
29775 uint16_t target_id;
29777 * A physical address pointer pointing to a host buffer that the
29778 * command's response data will be written. This can be either a host
29779 * physical address (HPA) or a guest physical address (GPA) and must
29780 * point to a physically contiguous block of memory.
29782 uint64_t resp_addr;
29783 /* The source function id. */
29785 uint8_t unused_0[6];
29786 } __attribute__((packed));
29788 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
29789 struct hwrm_cfa_redirect_query_tunnel_type_output {
29790 /* The specific error status for the command. */
29791 uint16_t error_code;
29792 /* The HWRM command request type. */
29794 /* The sequence ID from the original command. */
29796 /* The length of the response data in number of bytes. */
29799 uint32_t tunnel_mask;
29801 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
29803 /* Virtual eXtensible Local Area Network (VXLAN) */
29804 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
29806 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29807 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
29809 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29810 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
29813 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
29815 /* Generic Network Virtualization Encapsulation (Geneve) */
29816 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
29818 /* Multi-Protocol Lable Switching (MPLS) */
29819 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
29821 /* Stateless Transport Tunnel (STT) */
29822 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
29824 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29825 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
29827 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29828 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
29830 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29831 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
29833 /* Any tunneled traffic */
29834 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
29836 /* Use fixed layer 2 ether type of 0xFFFF */
29837 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
29839 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29840 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
29842 uint8_t unused_0[3];
29844 * This field is used in Output records to indicate that the output
29845 * is completely written to RAM. This field should be read as '1'
29846 * to indicate that the output has been completely written.
29847 * When writing a command completion or response to an internal processor,
29848 * the order of writes has to be such that this field is written last.
29851 } __attribute__((packed));
29853 /*************************
29854 * hwrm_cfa_ctx_mem_rgtr *
29855 *************************/
29858 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
29859 struct hwrm_cfa_ctx_mem_rgtr_input {
29860 /* The HWRM command request type. */
29863 * The completion ring to send the completion event on. This should
29864 * be the NQ ID returned from the `nq_alloc` HWRM command.
29866 uint16_t cmpl_ring;
29868 * The sequence ID is used by the driver for tracking multiple
29869 * commands. This ID is treated as opaque data by the firmware and
29870 * the value is returned in the `hwrm_resp_hdr` upon completion.
29874 * The target ID of the command:
29875 * * 0x0-0xFFF8 - The function ID
29876 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29877 * * 0xFFFD - Reserved for user-space HWRM interface
29880 uint16_t target_id;
29882 * A physical address pointer pointing to a host buffer that the
29883 * command's response data will be written. This can be either a host
29884 * physical address (HPA) or a guest physical address (GPA) and must
29885 * point to a physically contiguous block of memory.
29887 uint64_t resp_addr;
29889 /* Counter PBL indirect levels. */
29890 uint8_t page_level;
29891 /* PBL pointer is physical start address. */
29892 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29893 /* PBL pointer points to PTE table. */
29894 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29895 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29896 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29897 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
29898 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
29901 /* 4KB page size. */
29902 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29903 /* 8KB page size. */
29904 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29905 /* 64KB page size. */
29906 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29907 /* 256KB page size. */
29908 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29909 /* 1MB page size. */
29910 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29911 /* 2MB page size. */
29912 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29913 /* 4MB page size. */
29914 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29915 /* 1GB page size. */
29916 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29917 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
29918 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
29920 /* Pointer to the PBL, or PDL depending on number of levels */
29922 } __attribute__((packed));
29924 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
29925 struct hwrm_cfa_ctx_mem_rgtr_output {
29926 /* The specific error status for the command. */
29927 uint16_t error_code;
29928 /* The HWRM command request type. */
29930 /* The sequence ID from the original command. */
29932 /* The length of the response data in number of bytes. */
29935 * Id/Handle to the recently register context memory. This handle is passed
29936 * to the CFA feature.
29939 uint8_t unused_0[5];
29941 * This field is used in Output records to indicate that the output
29942 * is completely written to RAM. This field should be read as '1'
29943 * to indicate that the output has been completely written.
29944 * When writing a command completion or response to an internal processor,
29945 * the order of writes has to be such that this field is written last.
29948 } __attribute__((packed));
29950 /***************************
29951 * hwrm_cfa_ctx_mem_unrgtr *
29952 ***************************/
29955 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
29956 struct hwrm_cfa_ctx_mem_unrgtr_input {
29957 /* The HWRM command request type. */
29960 * The completion ring to send the completion event on. This should
29961 * be the NQ ID returned from the `nq_alloc` HWRM command.
29963 uint16_t cmpl_ring;
29965 * The sequence ID is used by the driver for tracking multiple
29966 * commands. This ID is treated as opaque data by the firmware and
29967 * the value is returned in the `hwrm_resp_hdr` upon completion.
29971 * The target ID of the command:
29972 * * 0x0-0xFFF8 - The function ID
29973 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29974 * * 0xFFFD - Reserved for user-space HWRM interface
29977 uint16_t target_id;
29979 * A physical address pointer pointing to a host buffer that the
29980 * command's response data will be written. This can be either a host
29981 * physical address (HPA) or a guest physical address (GPA) and must
29982 * point to a physically contiguous block of memory.
29984 uint64_t resp_addr;
29986 * Id/Handle to the recently register context memory. This handle is passed
29987 * to the CFA feature.
29990 uint8_t unused_0[6];
29991 } __attribute__((packed));
29993 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
29994 struct hwrm_cfa_ctx_mem_unrgtr_output {
29995 /* The specific error status for the command. */
29996 uint16_t error_code;
29997 /* The HWRM command request type. */
29999 /* The sequence ID from the original command. */
30001 /* The length of the response data in number of bytes. */
30003 uint8_t unused_0[7];
30005 * This field is used in Output records to indicate that the output
30006 * is completely written to RAM. This field should be read as '1'
30007 * to indicate that the output has been completely written.
30008 * When writing a command completion or response to an internal processor,
30009 * the order of writes has to be such that this field is written last.
30012 } __attribute__((packed));
30014 /*************************
30015 * hwrm_cfa_ctx_mem_qctx *
30016 *************************/
30019 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
30020 struct hwrm_cfa_ctx_mem_qctx_input {
30021 /* The HWRM command request type. */
30024 * The completion ring to send the completion event on. This should
30025 * be the NQ ID returned from the `nq_alloc` HWRM command.
30027 uint16_t cmpl_ring;
30029 * The sequence ID is used by the driver for tracking multiple
30030 * commands. This ID is treated as opaque data by the firmware and
30031 * the value is returned in the `hwrm_resp_hdr` upon completion.
30035 * The target ID of the command:
30036 * * 0x0-0xFFF8 - The function ID
30037 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30038 * * 0xFFFD - Reserved for user-space HWRM interface
30041 uint16_t target_id;
30043 * A physical address pointer pointing to a host buffer that the
30044 * command's response data will be written. This can be either a host
30045 * physical address (HPA) or a guest physical address (GPA) and must
30046 * point to a physically contiguous block of memory.
30048 uint64_t resp_addr;
30050 * Id/Handle to the recently register context memory. This handle is passed
30051 * to the CFA feature.
30054 uint8_t unused_0[6];
30055 } __attribute__((packed));
30057 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
30058 struct hwrm_cfa_ctx_mem_qctx_output {
30059 /* The specific error status for the command. */
30060 uint16_t error_code;
30061 /* The HWRM command request type. */
30063 /* The sequence ID from the original command. */
30065 /* The length of the response data in number of bytes. */
30068 /* Counter PBL indirect levels. */
30069 uint8_t page_level;
30070 /* PBL pointer is physical start address. */
30071 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
30072 /* PBL pointer points to PTE table. */
30073 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
30074 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
30075 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
30076 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
30077 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
30080 /* 4KB page size. */
30081 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
30082 /* 8KB page size. */
30083 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
30084 /* 64KB page size. */
30085 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
30086 /* 256KB page size. */
30087 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
30088 /* 1MB page size. */
30089 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
30090 /* 2MB page size. */
30091 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
30092 /* 4MB page size. */
30093 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
30094 /* 1GB page size. */
30095 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
30096 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
30097 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
30098 uint8_t unused_0[4];
30099 /* Pointer to the PBL, or PDL depending on number of levels */
30101 uint8_t unused_1[7];
30103 * This field is used in Output records to indicate that the output
30104 * is completely written to RAM. This field should be read as '1'
30105 * to indicate that the output has been completely written.
30106 * When writing a command completion or response to an internal processor,
30107 * the order of writes has to be such that this field is written last.
30110 } __attribute__((packed));
30112 /**************************
30113 * hwrm_cfa_ctx_mem_qcaps *
30114 **************************/
30117 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
30118 struct hwrm_cfa_ctx_mem_qcaps_input {
30119 /* The HWRM command request type. */
30122 * The completion ring to send the completion event on. This should
30123 * be the NQ ID returned from the `nq_alloc` HWRM command.
30125 uint16_t cmpl_ring;
30127 * The sequence ID is used by the driver for tracking multiple
30128 * commands. This ID is treated as opaque data by the firmware and
30129 * the value is returned in the `hwrm_resp_hdr` upon completion.
30133 * The target ID of the command:
30134 * * 0x0-0xFFF8 - The function ID
30135 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30136 * * 0xFFFD - Reserved for user-space HWRM interface
30139 uint16_t target_id;
30141 * A physical address pointer pointing to a host buffer that the
30142 * command's response data will be written. This can be either a host
30143 * physical address (HPA) or a guest physical address (GPA) and must
30144 * point to a physically contiguous block of memory.
30146 uint64_t resp_addr;
30147 } __attribute__((packed));
30149 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
30150 struct hwrm_cfa_ctx_mem_qcaps_output {
30151 /* The specific error status for the command. */
30152 uint16_t error_code;
30153 /* The HWRM command request type. */
30155 /* The sequence ID from the original command. */
30157 /* The length of the response data in number of bytes. */
30159 /* Indicates the maximum number of context memory which can be registered. */
30160 uint16_t max_entries;
30161 uint8_t unused_0[5];
30163 * This field is used in Output records to indicate that the output
30164 * is completely written to RAM. This field should be read as '1'
30165 * to indicate that the output has been completely written.
30166 * When writing a command completion or response to an internal processor,
30167 * the order of writes has to be such that this field is written last.
30170 } __attribute__((packed));
30172 /**********************
30173 * hwrm_cfa_eem_qcaps *
30174 **********************/
30177 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
30178 struct hwrm_cfa_eem_qcaps_input {
30179 /* The HWRM command request type. */
30182 * The completion ring to send the completion event on. This should
30183 * be the NQ ID returned from the `nq_alloc` HWRM command.
30185 uint16_t cmpl_ring;
30187 * The sequence ID is used by the driver for tracking multiple
30188 * commands. This ID is treated as opaque data by the firmware and
30189 * the value is returned in the `hwrm_resp_hdr` upon completion.
30193 * The target ID of the command:
30194 * * 0x0-0xFFF8 - The function ID
30195 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30196 * * 0xFFFD - Reserved for user-space HWRM interface
30199 uint16_t target_id;
30201 * A physical address pointer pointing to a host buffer that the
30202 * command's response data will be written. This can be either a host
30203 * physical address (HPA) or a guest physical address (GPA) and must
30204 * point to a physically contiguous block of memory.
30206 uint64_t resp_addr;
30209 * When set to 1, indicates the configuration will apply to TX flows
30210 * which are to be offloaded.
30211 * Note if this bit is set then the path_rx bit can't be set.
30213 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
30216 * When set to 1, indicates the configuration will apply to RX flows
30217 * which are to be offloaded.
30218 * Note if this bit is set then the path_tx bit can't be set.
30220 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
30222 /* When set to 1, all offloaded flows will be sent to EEM. */
30223 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
30226 } __attribute__((packed));
30228 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
30229 struct hwrm_cfa_eem_qcaps_output {
30230 /* The specific error status for the command. */
30231 uint16_t error_code;
30232 /* The HWRM command request type. */
30234 /* The sequence ID from the original command. */
30236 /* The length of the response data in number of bytes. */
30240 * When set to 1, indicates the configuration will apply to TX flows
30241 * which are to be offloaded.
30242 * Note if this bit is set then the path_rx bit can't be set.
30244 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
30247 * When set to 1, indicates the configuration will apply to RX flows
30248 * which are to be offloaded.
30249 * Note if this bit is set then the path_tx bit can't be set.
30251 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
30254 * When set to 1, indicates the the FW supports the Centralized
30255 * Memory Model. The concept designates one entity for the
30256 * memory allocation while all others ‘subscribe’ to it.
30258 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30261 * When set to 1, indicates the the FW supports the Detached
30262 * Centralized Memory Model. The memory is allocated and managed
30263 * as a separate entity. All PFs and VFs will be granted direct
30264 * or semi-direct access to the allocated memory while none of
30265 * which can interfere with the management of the memory.
30267 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30270 uint32_t supported;
30272 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
30273 * If set to 0, EEM KEY0 table is not supported.
30275 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
30278 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
30279 * If set to 0, EEM KEY1 table is not supported.
30281 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
30284 * If set to 1, then EEM External Record table is supported.
30285 * If set to 0, EEM External Record table is not supported.
30286 * (This table includes action record, EFC pointers, encap pointers)
30288 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
30291 * If set to 1, then EEM External Flow Counters table is supported.
30292 * If set to 0, EEM External Flow Counters table is not supported.
30294 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
30297 * If set to 1, then FID table used for implicit flow flush is supported.
30298 * If set to 0, then FID table used for implicit flow flush is not supported.
30300 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
30303 * The maximum number of entries supported by EEM. When configuring the host memory
30304 * the number of numbers of entries that can supported are -
30305 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
30306 * Any value that are not these values, the FW will round down to the closest support
30307 * number of entries.
30309 uint32_t max_entries_supported;
30310 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
30311 uint16_t key_entry_size;
30312 /* The entry size in bytes of each entry in the EEM RECORD tables. */
30313 uint16_t record_entry_size;
30314 /* The entry size in bytes of each entry in the EEM EFC tables. */
30315 uint16_t efc_entry_size;
30316 /* The FID size in bytes of each entry in the EEM FID tables. */
30317 uint16_t fid_entry_size;
30318 uint8_t unused_1[7];
30320 * This field is used in Output records to indicate that the output
30321 * is completely written to RAM. This field should be read as '1'
30322 * to indicate that the output has been completely written.
30323 * When writing a command completion or response to an internal processor,
30324 * the order of writes has to be such that this field is written last.
30327 } __attribute__((packed));
30329 /********************
30330 * hwrm_cfa_eem_cfg *
30331 ********************/
30334 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
30335 struct hwrm_cfa_eem_cfg_input {
30336 /* The HWRM command request type. */
30339 * The completion ring to send the completion event on. This should
30340 * be the NQ ID returned from the `nq_alloc` HWRM command.
30342 uint16_t cmpl_ring;
30344 * The sequence ID is used by the driver for tracking multiple
30345 * commands. This ID is treated as opaque data by the firmware and
30346 * the value is returned in the `hwrm_resp_hdr` upon completion.
30350 * The target ID of the command:
30351 * * 0x0-0xFFF8 - The function ID
30352 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30353 * * 0xFFFD - Reserved for user-space HWRM interface
30356 uint16_t target_id;
30358 * A physical address pointer pointing to a host buffer that the
30359 * command's response data will be written. This can be either a host
30360 * physical address (HPA) or a guest physical address (GPA) and must
30361 * point to a physically contiguous block of memory.
30363 uint64_t resp_addr;
30366 * When set to 1, indicates the configuration will apply to TX flows
30367 * which are to be offloaded.
30368 * Note if this bit is set then the path_rx bit can't be set.
30370 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
30373 * When set to 1, indicates the configuration will apply to RX flows
30374 * which are to be offloaded.
30375 * Note if this bit is set then the path_tx bit can't be set.
30377 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
30379 /* When set to 1, all offloaded flows will be sent to EEM. */
30380 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
30382 /* When set to 1, secondary, 0 means primary. */
30383 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
30386 * Group_id which used by Firmware to identify memory pools belonging
30387 * to certain group.
30392 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
30393 * RECORD, EFC all have the same number of entries and all tables will be configured
30394 * using this value. Current minimum value is 32k. Current maximum value is 128M.
30396 uint32_t num_entries;
30398 /* Configured EEM with the given context if for KEY0 table. */
30399 uint16_t key0_ctx_id;
30400 /* Configured EEM with the given context if for KEY1 table. */
30401 uint16_t key1_ctx_id;
30402 /* Configured EEM with the given context if for RECORD table. */
30403 uint16_t record_ctx_id;
30404 /* Configured EEM with the given context if for EFC table. */
30405 uint16_t efc_ctx_id;
30406 /* Configured EEM with the given context if for EFC table. */
30407 uint16_t fid_ctx_id;
30410 } __attribute__((packed));
30412 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
30413 struct hwrm_cfa_eem_cfg_output {
30414 /* The specific error status for the command. */
30415 uint16_t error_code;
30416 /* The HWRM command request type. */
30418 /* The sequence ID from the original command. */
30420 /* The length of the response data in number of bytes. */
30422 uint8_t unused_0[7];
30424 * This field is used in Output records to indicate that the output
30425 * is completely written to RAM. This field should be read as '1'
30426 * to indicate that the output has been completely written.
30427 * When writing a command completion or response to an internal processor,
30428 * the order of writes has to be such that this field is written last.
30431 } __attribute__((packed));
30433 /*********************
30434 * hwrm_cfa_eem_qcfg *
30435 *********************/
30438 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
30439 struct hwrm_cfa_eem_qcfg_input {
30440 /* The HWRM command request type. */
30443 * The completion ring to send the completion event on. This should
30444 * be the NQ ID returned from the `nq_alloc` HWRM command.
30446 uint16_t cmpl_ring;
30448 * The sequence ID is used by the driver for tracking multiple
30449 * commands. This ID is treated as opaque data by the firmware and
30450 * the value is returned in the `hwrm_resp_hdr` upon completion.
30454 * The target ID of the command:
30455 * * 0x0-0xFFF8 - The function ID
30456 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30457 * * 0xFFFD - Reserved for user-space HWRM interface
30460 uint16_t target_id;
30462 * A physical address pointer pointing to a host buffer that the
30463 * command's response data will be written. This can be either a host
30464 * physical address (HPA) or a guest physical address (GPA) and must
30465 * point to a physically contiguous block of memory.
30467 uint64_t resp_addr;
30469 /* When set to 1, indicates the configuration is the TX flow. */
30470 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30471 /* When set to 1, indicates the configuration is the RX flow. */
30472 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30474 } __attribute__((packed));
30476 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
30477 struct hwrm_cfa_eem_qcfg_output {
30478 /* The specific error status for the command. */
30479 uint16_t error_code;
30480 /* The HWRM command request type. */
30482 /* The sequence ID from the original command. */
30484 /* The length of the response data in number of bytes. */
30487 /* When set to 1, indicates the configuration is the TX flow. */
30488 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
30490 /* When set to 1, indicates the configuration is the RX flow. */
30491 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
30493 /* When set to 1, all offloaded flows will be sent to EEM. */
30494 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
30496 /* The number of entries the FW has configured for EEM. */
30497 uint32_t num_entries;
30498 /* Configured EEM with the given context if for KEY0 table. */
30499 uint16_t key0_ctx_id;
30500 /* Configured EEM with the given context if for KEY1 table. */
30501 uint16_t key1_ctx_id;
30502 /* Configured EEM with the given context if for RECORD table. */
30503 uint16_t record_ctx_id;
30504 /* Configured EEM with the given context if for EFC table. */
30505 uint16_t efc_ctx_id;
30506 /* Configured EEM with the given context if for EFC table. */
30507 uint16_t fid_ctx_id;
30508 uint8_t unused_2[5];
30510 * This field is used in Output records to indicate that the output
30511 * is completely written to RAM. This field should be read as '1'
30512 * to indicate that the output has been completely written.
30513 * When writing a command completion or response to an internal processor,
30514 * the order of writes has to be such that this field is written last.
30517 } __attribute__((packed));
30519 /*******************
30520 * hwrm_cfa_eem_op *
30521 *******************/
30524 /* hwrm_cfa_eem_op_input (size:192b/24B) */
30525 struct hwrm_cfa_eem_op_input {
30526 /* The HWRM command request type. */
30529 * The completion ring to send the completion event on. This should
30530 * be the NQ ID returned from the `nq_alloc` HWRM command.
30532 uint16_t cmpl_ring;
30534 * The sequence ID is used by the driver for tracking multiple
30535 * commands. This ID is treated as opaque data by the firmware and
30536 * the value is returned in the `hwrm_resp_hdr` upon completion.
30540 * The target ID of the command:
30541 * * 0x0-0xFFF8 - The function ID
30542 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30543 * * 0xFFFD - Reserved for user-space HWRM interface
30546 uint16_t target_id;
30548 * A physical address pointer pointing to a host buffer that the
30549 * command's response data will be written. This can be either a host
30550 * physical address (HPA) or a guest physical address (GPA) and must
30551 * point to a physically contiguous block of memory.
30553 uint64_t resp_addr;
30556 * When set to 1, indicates the host memory which is passed will be
30557 * used for the TX flow offload function specified in fid.
30558 * Note if this bit is set then the path_rx bit can't be set.
30560 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30562 * When set to 1, indicates the host memory which is passed will be
30563 * used for the RX flow offload function specified in fid.
30564 * Note if this bit is set then the path_tx bit can't be set.
30566 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30568 /* The number of EEM key table entries to be configured. */
30570 /* This value is reserved and should not be used. */
30571 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
30573 * To properly stop EEM and ensure there are no DMA's, the caller
30574 * must disable EEM for the given PF, using this call. This will
30575 * safely disable EEM and ensure that all DMA'ed to the
30576 * keys/records/efc have been completed.
30578 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
30580 * Once the EEM host memory has been configured, EEM options have
30581 * been configured. Then the caller should enable EEM for the given
30582 * PF. Note once this call has been made, then the EEM mechanism
30583 * will be active and DMA's will occur as packets are processed.
30585 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
30587 * Clear EEM settings for the given PF so that the register values
30588 * are reset back to there initial state.
30590 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
30591 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
30592 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
30593 } __attribute__((packed));
30595 /* hwrm_cfa_eem_op_output (size:128b/16B) */
30596 struct hwrm_cfa_eem_op_output {
30597 /* The specific error status for the command. */
30598 uint16_t error_code;
30599 /* The HWRM command request type. */
30601 /* The sequence ID from the original command. */
30603 /* The length of the response data in number of bytes. */
30605 uint8_t unused_0[7];
30607 * This field is used in Output records to indicate that the output
30608 * is completely written to RAM. This field should be read as '1'
30609 * to indicate that the output has been completely written.
30610 * When writing a command completion or response to an internal processor,
30611 * the order of writes has to be such that this field is written last.
30614 } __attribute__((packed));
30616 /********************************
30617 * hwrm_cfa_adv_flow_mgnt_qcaps *
30618 ********************************/
30621 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
30622 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
30623 /* The HWRM command request type. */
30626 * The completion ring to send the completion event on. This should
30627 * be the NQ ID returned from the `nq_alloc` HWRM command.
30629 uint16_t cmpl_ring;
30631 * The sequence ID is used by the driver for tracking multiple
30632 * commands. This ID is treated as opaque data by the firmware and
30633 * the value is returned in the `hwrm_resp_hdr` upon completion.
30637 * The target ID of the command:
30638 * * 0x0-0xFFF8 - The function ID
30639 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30640 * * 0xFFFD - Reserved for user-space HWRM interface
30643 uint16_t target_id;
30645 * A physical address pointer pointing to a host buffer that the
30646 * command's response data will be written. This can be either a host
30647 * physical address (HPA) or a guest physical address (GPA) and must
30648 * point to a physically contiguous block of memory.
30650 uint64_t resp_addr;
30651 uint32_t unused_0[4];
30652 } __attribute__((packed));
30654 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
30655 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
30656 /* The specific error status for the command. */
30657 uint16_t error_code;
30658 /* The HWRM command request type. */
30660 /* The sequence ID from the original command. */
30662 /* The length of the response data in number of bytes. */
30666 * Value of 1 to indicate firmware support 16-bit flow handle.
30667 * Value of 0 to indicate firmware not support 16-bit flow handle.
30669 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
30672 * Value of 1 to indicate firmware support 64-bit flow handle.
30673 * Value of 0 to indicate firmware not support 64-bit flow handle.
30675 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
30678 * Value of 1 to indicate firmware support flow batch delete operation through
30679 * HWRM_CFA_FLOW_FLUSH command.
30680 * Value of 0 to indicate that the firmware does not support flow batch delete
30683 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
30686 * Value of 1 to indicate that the firmware support flow reset all operation through
30687 * HWRM_CFA_FLOW_FLUSH command.
30688 * Value of 0 indicates firmware does not support flow reset all operation.
30690 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
30693 * Value of 1 to indicate that firmware supports use of FID as dest_id in
30694 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
30695 * Value of 0 indicates firmware does not support use of FID as dest_id.
30697 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
30700 * Value of 1 to indicate that firmware supports TX EEM flows.
30701 * Value of 0 indicates firmware does not support TX EEM flows.
30703 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
30706 * Value of 1 to indicate that firmware supports RX EEM flows.
30707 * Value of 0 indicates firmware does not support RX EEM flows.
30709 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
30712 * Value of 1 to indicate that firmware supports the dynamic allocation of an
30713 * on-chip flow counter which can be used for EEM flows.
30714 * Value of 0 indicates firmware does not support the dynamic allocation of an
30715 * on-chip flow counter.
30717 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
30720 * Value of 1 to indicate that firmware supports setting of
30721 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
30722 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
30724 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
30727 * Value of 1 to indicate that firmware supports untagged matching
30728 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
30729 * indicates firmware does not support untagged matching.
30731 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
30734 * Value of 1 to indicate that firmware supports XDP filter. Value
30735 * of 0 indicates firmware does not support XDP filter.
30737 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
30740 * Value of 1 to indicate that the firmware support L2 header source
30741 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
30742 * Value of 0 indicates firmware does not support L2 header source
30745 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
30747 uint8_t unused_0[3];
30749 * This field is used in Output records to indicate that the output
30750 * is completely written to RAM. This field should be read as '1'
30751 * to indicate that the output has been completely written.
30752 * When writing a command completion or response to an internal processor,
30753 * the order of writes has to be such that this field is written last.
30756 } __attribute__((packed));
30758 /******************
30760 ******************/
30763 /* hwrm_cfa_tflib_input (size:1024b/128B) */
30764 struct hwrm_cfa_tflib_input {
30765 /* The HWRM command request type. */
30768 * The completion ring to send the completion event on. This should
30769 * be the NQ ID returned from the `nq_alloc` HWRM command.
30771 uint16_t cmpl_ring;
30773 * The sequence ID is used by the driver for tracking multiple
30774 * commands. This ID is treated as opaque data by the firmware and
30775 * the value is returned in the `hwrm_resp_hdr` upon completion.
30779 * The target ID of the command:
30780 * * 0x0-0xFFF8 - The function ID
30781 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30782 * * 0xFFFD - Reserved for user-space HWRM interface
30785 uint16_t target_id;
30787 * A physical address pointer pointing to a host buffer that the
30788 * command's response data will be written. This can be either a host
30789 * physical address (HPA) or a guest physical address (GPA) and must
30790 * point to a physically contiguous block of memory.
30792 uint64_t resp_addr;
30793 /* TFLIB message type. */
30795 /* TFLIB message subtype. */
30796 uint16_t tf_subtype;
30798 uint8_t unused0[4];
30799 /* TFLIB request data. */
30800 uint32_t tf_req[26];
30801 } __attribute__((packed));
30803 /* hwrm_cfa_tflib_output (size:5632b/704B) */
30804 struct hwrm_cfa_tflib_output {
30805 /* The specific error status for the command. */
30806 uint16_t error_code;
30807 /* The HWRM command request type. */
30809 /* The sequence ID from the original command. */
30811 /* The length of the response data in number of bytes. */
30813 /* TFLIB message type. */
30815 /* TFLIB message subtype. */
30816 uint16_t tf_subtype;
30817 /* TFLIB response code */
30818 uint32_t tf_resp_code;
30819 /* TFLIB response data. */
30820 uint32_t tf_resp[170];
30822 uint8_t unused1[7];
30824 * This field is used in Output records to indicate that the output
30825 * is completely written to RAM. This field should be read as '1'
30826 * to indicate that the output has been completely written.
30827 * When writing a command completion or response to an internal processor,
30828 * the order of writes has to be such that this field is written last.
30831 } __attribute__((packed));
30833 /******************************
30834 * hwrm_tunnel_dst_port_query *
30835 ******************************/
30838 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
30839 struct hwrm_tunnel_dst_port_query_input {
30840 /* The HWRM command request type. */
30843 * The completion ring to send the completion event on. This should
30844 * be the NQ ID returned from the `nq_alloc` HWRM command.
30846 uint16_t cmpl_ring;
30848 * The sequence ID is used by the driver for tracking multiple
30849 * commands. This ID is treated as opaque data by the firmware and
30850 * the value is returned in the `hwrm_resp_hdr` upon completion.
30854 * The target ID of the command:
30855 * * 0x0-0xFFF8 - The function ID
30856 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30857 * * 0xFFFD - Reserved for user-space HWRM interface
30860 uint16_t target_id;
30862 * A physical address pointer pointing to a host buffer that the
30863 * command's response data will be written. This can be either a host
30864 * physical address (HPA) or a guest physical address (GPA) and must
30865 * point to a physically contiguous block of memory.
30867 uint64_t resp_addr;
30869 uint8_t tunnel_type;
30870 /* Virtual eXtensible Local Area Network (VXLAN) */
30871 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
30873 /* Generic Network Virtualization Encapsulation (Geneve) */
30874 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
30876 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30877 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30879 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30880 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30882 /* Use fixed layer 2 ether type of 0xFFFF */
30883 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
30885 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30886 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30888 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
30889 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30890 uint8_t unused_0[7];
30891 } __attribute__((packed));
30893 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
30894 struct hwrm_tunnel_dst_port_query_output {
30895 /* The specific error status for the command. */
30896 uint16_t error_code;
30897 /* The HWRM command request type. */
30899 /* The sequence ID from the original command. */
30901 /* The length of the response data in number of bytes. */
30904 * This field represents the identifier of L4 destination port
30905 * used for the given tunnel type. This field is valid for
30906 * specific tunnel types that use layer 4 (e.g. UDP)
30907 * transports for tunneling.
30909 uint16_t tunnel_dst_port_id;
30911 * This field represents the value of L4 destination port
30912 * identified by tunnel_dst_port_id. This field is valid for
30913 * specific tunnel types that use layer 4 (e.g. UDP)
30914 * transports for tunneling.
30915 * This field is in network byte order.
30917 * A value of 0 means that the destination port is not
30920 uint16_t tunnel_dst_port_val;
30921 uint8_t unused_0[3];
30923 * This field is used in Output records to indicate that the output
30924 * is completely written to RAM. This field should be read as '1'
30925 * to indicate that the output has been completely written.
30926 * When writing a command completion or response to an internal processor,
30927 * the order of writes has to be such that this field is written last.
30930 } __attribute__((packed));
30932 /******************************
30933 * hwrm_tunnel_dst_port_alloc *
30934 ******************************/
30937 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
30938 struct hwrm_tunnel_dst_port_alloc_input {
30939 /* The HWRM command request type. */
30942 * The completion ring to send the completion event on. This should
30943 * be the NQ ID returned from the `nq_alloc` HWRM command.
30945 uint16_t cmpl_ring;
30947 * The sequence ID is used by the driver for tracking multiple
30948 * commands. This ID is treated as opaque data by the firmware and
30949 * the value is returned in the `hwrm_resp_hdr` upon completion.
30953 * The target ID of the command:
30954 * * 0x0-0xFFF8 - The function ID
30955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30956 * * 0xFFFD - Reserved for user-space HWRM interface
30959 uint16_t target_id;
30961 * A physical address pointer pointing to a host buffer that the
30962 * command's response data will be written. This can be either a host
30963 * physical address (HPA) or a guest physical address (GPA) and must
30964 * point to a physically contiguous block of memory.
30966 uint64_t resp_addr;
30968 uint8_t tunnel_type;
30969 /* Virtual eXtensible Local Area Network (VXLAN) */
30970 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30972 /* Generic Network Virtualization Encapsulation (Geneve) */
30973 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30975 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30976 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30978 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30979 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30981 /* Use fixed layer 2 ether type of 0xFFFF */
30982 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30984 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30985 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30987 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30988 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30991 * This field represents the value of L4 destination port used
30992 * for the given tunnel type. This field is valid for
30993 * specific tunnel types that use layer 4 (e.g. UDP)
30994 * transports for tunneling.
30996 * This field is in network byte order.
30998 * A value of 0 shall fail the command.
31000 uint16_t tunnel_dst_port_val;
31001 uint8_t unused_1[4];
31002 } __attribute__((packed));
31004 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
31005 struct hwrm_tunnel_dst_port_alloc_output {
31006 /* The specific error status for the command. */
31007 uint16_t error_code;
31008 /* The HWRM command request type. */
31010 /* The sequence ID from the original command. */
31012 /* The length of the response data in number of bytes. */
31015 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
31016 * types that has l4 destination port parameters.
31018 uint16_t tunnel_dst_port_id;
31019 uint8_t unused_0[5];
31021 * This field is used in Output records to indicate that the output
31022 * is completely written to RAM. This field should be read as '1'
31023 * to indicate that the output has been completely written.
31024 * When writing a command completion or response to an internal processor,
31025 * the order of writes has to be such that this field is written last.
31028 } __attribute__((packed));
31030 /*****************************
31031 * hwrm_tunnel_dst_port_free *
31032 *****************************/
31035 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
31036 struct hwrm_tunnel_dst_port_free_input {
31037 /* The HWRM command request type. */
31040 * The completion ring to send the completion event on. This should
31041 * be the NQ ID returned from the `nq_alloc` HWRM command.
31043 uint16_t cmpl_ring;
31045 * The sequence ID is used by the driver for tracking multiple
31046 * commands. This ID is treated as opaque data by the firmware and
31047 * the value is returned in the `hwrm_resp_hdr` upon completion.
31051 * The target ID of the command:
31052 * * 0x0-0xFFF8 - The function ID
31053 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31054 * * 0xFFFD - Reserved for user-space HWRM interface
31057 uint16_t target_id;
31059 * A physical address pointer pointing to a host buffer that the
31060 * command's response data will be written. This can be either a host
31061 * physical address (HPA) or a guest physical address (GPA) and must
31062 * point to a physically contiguous block of memory.
31064 uint64_t resp_addr;
31066 uint8_t tunnel_type;
31067 /* Virtual eXtensible Local Area Network (VXLAN) */
31068 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
31070 /* Generic Network Virtualization Encapsulation (Geneve) */
31071 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
31073 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31074 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31076 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31077 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31079 /* Use fixed layer 2 ether type of 0xFFFF */
31080 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
31082 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31083 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31085 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
31086 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
31089 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
31090 * types that has l4 destination port parameters.
31092 uint16_t tunnel_dst_port_id;
31093 uint8_t unused_1[4];
31094 } __attribute__((packed));
31096 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
31097 struct hwrm_tunnel_dst_port_free_output {
31098 /* The specific error status for the command. */
31099 uint16_t error_code;
31100 /* The HWRM command request type. */
31102 /* The sequence ID from the original command. */
31104 /* The length of the response data in number of bytes. */
31106 uint8_t unused_1[7];
31108 * This field is used in Output records to indicate that the output
31109 * is completely written to RAM. This field should be read as '1'
31110 * to indicate that the output has been completely written.
31111 * When writing a command completion or response to an internal processor,
31112 * the order of writes has to be such that this field is written last.
31115 } __attribute__((packed));
31117 /* Periodic statistics context DMA to host. */
31118 /* ctx_hw_stats (size:1280b/160B) */
31119 struct ctx_hw_stats {
31120 /* Number of received unicast packets */
31121 uint64_t rx_ucast_pkts;
31122 /* Number of received multicast packets */
31123 uint64_t rx_mcast_pkts;
31124 /* Number of received broadcast packets */
31125 uint64_t rx_bcast_pkts;
31126 /* Number of discarded packets on received path */
31127 uint64_t rx_discard_pkts;
31128 /* Number of dropped packets on received path */
31129 uint64_t rx_drop_pkts;
31130 /* Number of received bytes for unicast traffic */
31131 uint64_t rx_ucast_bytes;
31132 /* Number of received bytes for multicast traffic */
31133 uint64_t rx_mcast_bytes;
31134 /* Number of received bytes for broadcast traffic */
31135 uint64_t rx_bcast_bytes;
31136 /* Number of transmitted unicast packets */
31137 uint64_t tx_ucast_pkts;
31138 /* Number of transmitted multicast packets */
31139 uint64_t tx_mcast_pkts;
31140 /* Number of transmitted broadcast packets */
31141 uint64_t tx_bcast_pkts;
31142 /* Number of discarded packets on transmit path */
31143 uint64_t tx_discard_pkts;
31144 /* Number of dropped packets on transmit path */
31145 uint64_t tx_drop_pkts;
31146 /* Number of transmitted bytes for unicast traffic */
31147 uint64_t tx_ucast_bytes;
31148 /* Number of transmitted bytes for multicast traffic */
31149 uint64_t tx_mcast_bytes;
31150 /* Number of transmitted bytes for broadcast traffic */
31151 uint64_t tx_bcast_bytes;
31152 /* Number of TPA packets */
31154 /* Number of TPA bytes */
31155 uint64_t tpa_bytes;
31156 /* Number of TPA events */
31157 uint64_t tpa_events;
31158 /* Number of TPA aborts */
31159 uint64_t tpa_aborts;
31160 } __attribute__((packed));
31162 /* Periodic statistics context DMA to host. */
31163 /* ctx_hw_stats_ext (size:1344b/168B) */
31164 struct ctx_hw_stats_ext {
31165 /* Number of received unicast packets */
31166 uint64_t rx_ucast_pkts;
31167 /* Number of received multicast packets */
31168 uint64_t rx_mcast_pkts;
31169 /* Number of received broadcast packets */
31170 uint64_t rx_bcast_pkts;
31171 /* Number of discarded packets on received path */
31172 uint64_t rx_discard_pkts;
31173 /* Number of dropped packets on received path */
31174 uint64_t rx_drop_pkts;
31175 /* Number of received bytes for unicast traffic */
31176 uint64_t rx_ucast_bytes;
31177 /* Number of received bytes for multicast traffic */
31178 uint64_t rx_mcast_bytes;
31179 /* Number of received bytes for broadcast traffic */
31180 uint64_t rx_bcast_bytes;
31181 /* Number of transmitted unicast packets */
31182 uint64_t tx_ucast_pkts;
31183 /* Number of transmitted multicast packets */
31184 uint64_t tx_mcast_pkts;
31185 /* Number of transmitted broadcast packets */
31186 uint64_t tx_bcast_pkts;
31187 /* Number of discarded packets on transmit path */
31188 uint64_t tx_discard_pkts;
31189 /* Number of dropped packets on transmit path */
31190 uint64_t tx_drop_pkts;
31191 /* Number of transmitted bytes for unicast traffic */
31192 uint64_t tx_ucast_bytes;
31193 /* Number of transmitted bytes for multicast traffic */
31194 uint64_t tx_mcast_bytes;
31195 /* Number of transmitted bytes for broadcast traffic */
31196 uint64_t tx_bcast_bytes;
31197 /* Number of TPA eligible packets */
31198 uint64_t rx_tpa_eligible_pkt;
31199 /* Number of TPA eligible bytes */
31200 uint64_t rx_tpa_eligible_bytes;
31201 /* Number of TPA packets */
31202 uint64_t rx_tpa_pkt;
31203 /* Number of TPA bytes */
31204 uint64_t rx_tpa_bytes;
31205 /* Number of TPA errors */
31206 uint64_t rx_tpa_errors;
31207 } __attribute__((packed));
31209 /* Periodic Engine statistics context DMA to host. */
31210 /* ctx_eng_stats (size:512b/64B) */
31211 struct ctx_eng_stats {
31213 * Count of data bytes into the Engine.
31214 * This includes any user supplied prefix,
31215 * but does not include any predefined
31218 uint64_t eng_bytes_in;
31219 /* Count of data bytes out of the Engine. */
31220 uint64_t eng_bytes_out;
31222 * Count, in 4-byte (dword) units, of bytes
31223 * that are input as auxiliary data.
31224 * This includes the aux_cmd data.
31226 uint64_t aux_bytes_in;
31228 * Count, in 4-byte (dword) units, of bytes
31229 * that are output as auxiliary data.
31230 * This count is the buffer space for aux_data
31231 * output provided in the RQE, not the actual
31234 uint64_t aux_bytes_out;
31235 /* Count of number of commands executed. */
31238 * Count of number of error commands.
31239 * These are the commands with a
31240 * non-zero status value.
31242 uint64_t error_commands;
31244 * Compression/Encryption Engine usage,
31245 * the unit is count of clock cycles
31247 uint64_t cce_engine_usage;
31249 * De-Compression/De-cryption Engine usage,
31250 * the unit is count of clock cycles
31252 uint64_t cdd_engine_usage;
31253 } __attribute__((packed));
31255 /***********************
31256 * hwrm_stat_ctx_alloc *
31257 ***********************/
31260 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
31261 struct hwrm_stat_ctx_alloc_input {
31262 /* The HWRM command request type. */
31265 * The completion ring to send the completion event on. This should
31266 * be the NQ ID returned from the `nq_alloc` HWRM command.
31268 uint16_t cmpl_ring;
31270 * The sequence ID is used by the driver for tracking multiple
31271 * commands. This ID is treated as opaque data by the firmware and
31272 * the value is returned in the `hwrm_resp_hdr` upon completion.
31276 * The target ID of the command:
31277 * * 0x0-0xFFF8 - The function ID
31278 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31279 * * 0xFFFD - Reserved for user-space HWRM interface
31282 uint16_t target_id;
31284 * A physical address pointer pointing to a host buffer that the
31285 * command's response data will be written. This can be either a host
31286 * physical address (HPA) or a guest physical address (GPA) and must
31287 * point to a physically contiguous block of memory.
31289 uint64_t resp_addr;
31291 * This is the address for statistic block.
31292 * > For new versions of the chip, this address should be 128B
31295 uint64_t stats_dma_addr;
31297 * The statistic block update period in ms.
31298 * e.g. 250ms, 500ms, 750ms, 1000ms.
31299 * If update_period_ms is 0, then the stats update
31300 * shall be never done and the DMA address shall not be used.
31301 * In this case, the stat block can only be read by
31302 * hwrm_stat_ctx_query command.
31303 * On Ethernet/L2 based devices:
31304 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
31305 * ctx_hw_stats_ext is used for DMA,
31307 * ctx_hw_stats is used for DMA.
31309 uint32_t update_period_ms;
31311 * This field is used to specify statistics context specific
31312 * configuration flags.
31314 uint8_t stat_ctx_flags;
31316 * When this bit is set to '1', the statistics context shall be
31317 * allocated for RoCE traffic only. In this case, traffic other
31318 * than offloaded RoCE traffic shall not be included in this
31319 * statistic context.
31320 * When this bit is set to '0', the statistics context shall be
31321 * used for network traffic or engine traffic.
31323 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
31326 * This is the size of the structure (ctx_hw_stats or
31327 * ctx_hw_stats_ext) that the driver has allocated to be used
31328 * for the periodic DMA updates.
31330 uint16_t stats_dma_length;
31331 } __attribute__((packed));
31333 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
31334 struct hwrm_stat_ctx_alloc_output {
31335 /* The specific error status for the command. */
31336 uint16_t error_code;
31337 /* The HWRM command request type. */
31339 /* The sequence ID from the original command. */
31341 /* The length of the response data in number of bytes. */
31343 /* This is the statistics context ID value. */
31344 uint32_t stat_ctx_id;
31345 uint8_t unused_0[3];
31347 * This field is used in Output records to indicate that the output
31348 * is completely written to RAM. This field should be read as '1'
31349 * to indicate that the output has been completely written.
31350 * When writing a command completion or response to an internal processor,
31351 * the order of writes has to be such that this field is written last.
31354 } __attribute__((packed));
31356 /**********************
31357 * hwrm_stat_ctx_free *
31358 **********************/
31361 /* hwrm_stat_ctx_free_input (size:192b/24B) */
31362 struct hwrm_stat_ctx_free_input {
31363 /* The HWRM command request type. */
31366 * The completion ring to send the completion event on. This should
31367 * be the NQ ID returned from the `nq_alloc` HWRM command.
31369 uint16_t cmpl_ring;
31371 * The sequence ID is used by the driver for tracking multiple
31372 * commands. This ID is treated as opaque data by the firmware and
31373 * the value is returned in the `hwrm_resp_hdr` upon completion.
31377 * The target ID of the command:
31378 * * 0x0-0xFFF8 - The function ID
31379 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31380 * * 0xFFFD - Reserved for user-space HWRM interface
31383 uint16_t target_id;
31385 * A physical address pointer pointing to a host buffer that the
31386 * command's response data will be written. This can be either a host
31387 * physical address (HPA) or a guest physical address (GPA) and must
31388 * point to a physically contiguous block of memory.
31390 uint64_t resp_addr;
31391 /* ID of the statistics context that is being queried. */
31392 uint32_t stat_ctx_id;
31393 uint8_t unused_0[4];
31394 } __attribute__((packed));
31396 /* hwrm_stat_ctx_free_output (size:128b/16B) */
31397 struct hwrm_stat_ctx_free_output {
31398 /* The specific error status for the command. */
31399 uint16_t error_code;
31400 /* The HWRM command request type. */
31402 /* The sequence ID from the original command. */
31404 /* The length of the response data in number of bytes. */
31406 /* This is the statistics context ID value. */
31407 uint32_t stat_ctx_id;
31408 uint8_t unused_0[3];
31410 * This field is used in Output records to indicate that the output
31411 * is completely written to RAM. This field should be read as '1'
31412 * to indicate that the output has been completely written.
31413 * When writing a command completion or response to an internal processor,
31414 * the order of writes has to be such that this field is written last.
31417 } __attribute__((packed));
31419 /***********************
31420 * hwrm_stat_ctx_query *
31421 ***********************/
31424 /* hwrm_stat_ctx_query_input (size:192b/24B) */
31425 struct hwrm_stat_ctx_query_input {
31426 /* The HWRM command request type. */
31429 * The completion ring to send the completion event on. This should
31430 * be the NQ ID returned from the `nq_alloc` HWRM command.
31432 uint16_t cmpl_ring;
31434 * The sequence ID is used by the driver for tracking multiple
31435 * commands. This ID is treated as opaque data by the firmware and
31436 * the value is returned in the `hwrm_resp_hdr` upon completion.
31440 * The target ID of the command:
31441 * * 0x0-0xFFF8 - The function ID
31442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31443 * * 0xFFFD - Reserved for user-space HWRM interface
31446 uint16_t target_id;
31448 * A physical address pointer pointing to a host buffer that the
31449 * command's response data will be written. This can be either a host
31450 * physical address (HPA) or a guest physical address (GPA) and must
31451 * point to a physically contiguous block of memory.
31453 uint64_t resp_addr;
31454 /* ID of the statistics context that is being queried. */
31455 uint32_t stat_ctx_id;
31456 uint8_t unused_0[4];
31457 } __attribute__((packed));
31459 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
31460 struct hwrm_stat_ctx_query_output {
31461 /* The specific error status for the command. */
31462 uint16_t error_code;
31463 /* The HWRM command request type. */
31465 /* The sequence ID from the original command. */
31467 /* The length of the response data in number of bytes. */
31469 /* Number of transmitted unicast packets */
31470 uint64_t tx_ucast_pkts;
31471 /* Number of transmitted multicast packets */
31472 uint64_t tx_mcast_pkts;
31473 /* Number of transmitted broadcast packets */
31474 uint64_t tx_bcast_pkts;
31475 /* Number of transmitted packets with error */
31476 uint64_t tx_err_pkts;
31477 /* Number of dropped packets on transmit path */
31478 uint64_t tx_drop_pkts;
31479 /* Number of transmitted bytes for unicast traffic */
31480 uint64_t tx_ucast_bytes;
31481 /* Number of transmitted bytes for multicast traffic */
31482 uint64_t tx_mcast_bytes;
31483 /* Number of transmitted bytes for broadcast traffic */
31484 uint64_t tx_bcast_bytes;
31485 /* Number of received unicast packets */
31486 uint64_t rx_ucast_pkts;
31487 /* Number of received multicast packets */
31488 uint64_t rx_mcast_pkts;
31489 /* Number of received broadcast packets */
31490 uint64_t rx_bcast_pkts;
31491 /* Number of received packets with error */
31492 uint64_t rx_err_pkts;
31493 /* Number of dropped packets on received path */
31494 uint64_t rx_drop_pkts;
31495 /* Number of received bytes for unicast traffic */
31496 uint64_t rx_ucast_bytes;
31497 /* Number of received bytes for multicast traffic */
31498 uint64_t rx_mcast_bytes;
31499 /* Number of received bytes for broadcast traffic */
31500 uint64_t rx_bcast_bytes;
31501 /* Number of aggregated unicast packets */
31502 uint64_t rx_agg_pkts;
31503 /* Number of aggregated unicast bytes */
31504 uint64_t rx_agg_bytes;
31505 /* Number of aggregation events */
31506 uint64_t rx_agg_events;
31507 /* Number of aborted aggregations */
31508 uint64_t rx_agg_aborts;
31509 uint8_t unused_0[7];
31511 * This field is used in Output records to indicate that the output
31512 * is completely written to RAM. This field should be read as '1'
31513 * to indicate that the output has been completely written.
31514 * When writing a command completion or response to an internal processor,
31515 * the order of writes has to be such that this field is written last.
31518 } __attribute__((packed));
31520 /***************************
31521 * hwrm_stat_ctx_eng_query *
31522 ***************************/
31525 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
31526 struct hwrm_stat_ctx_eng_query_input {
31527 /* The HWRM command request type. */
31530 * The completion ring to send the completion event on. This should
31531 * be the NQ ID returned from the `nq_alloc` HWRM command.
31533 uint16_t cmpl_ring;
31535 * The sequence ID is used by the driver for tracking multiple
31536 * commands. This ID is treated as opaque data by the firmware and
31537 * the value is returned in the `hwrm_resp_hdr` upon completion.
31541 * The target ID of the command:
31542 * * 0x0-0xFFF8 - The function ID
31543 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31544 * * 0xFFFD - Reserved for user-space HWRM interface
31547 uint16_t target_id;
31549 * A physical address pointer pointing to a host buffer that the
31550 * command's response data will be written. This can be either a host
31551 * physical address (HPA) or a guest physical address (GPA) and must
31552 * point to a physically contiguous block of memory.
31554 uint64_t resp_addr;
31555 /* ID of the statistics context that is being queried. */
31556 uint32_t stat_ctx_id;
31557 uint8_t unused_0[4];
31558 } __attribute__((packed));
31560 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
31561 struct hwrm_stat_ctx_eng_query_output {
31562 /* The specific error status for the command. */
31563 uint16_t error_code;
31564 /* The HWRM command request type. */
31566 /* The sequence ID from the original command. */
31568 /* The length of the response data in number of bytes. */
31571 * Count of data bytes into the Engine.
31572 * This includes any user supplied prefix,
31573 * but does not include any predefined
31576 uint64_t eng_bytes_in;
31577 /* Count of data bytes out of the Engine. */
31578 uint64_t eng_bytes_out;
31580 * Count, in 4-byte (dword) units, of bytes
31581 * that are input as auxiliary data.
31582 * This includes the aux_cmd data.
31584 uint64_t aux_bytes_in;
31586 * Count, in 4-byte (dword) units, of bytes
31587 * that are output as auxiliary data.
31588 * This count is the buffer space for aux_data
31589 * output provided in the RQE, not the actual
31592 uint64_t aux_bytes_out;
31593 /* Count of number of commands executed. */
31596 * Count of number of error commands.
31597 * These are the commands with a
31598 * non-zero status value.
31600 uint64_t error_commands;
31602 * Compression/Encryption Engine usage,
31603 * the unit is count of clock cycles
31605 uint64_t cce_engine_usage;
31607 * De-Compression/De-cryption Engine usage,
31608 * the unit is count of clock cycles
31610 uint64_t cdd_engine_usage;
31611 uint8_t unused_0[7];
31613 * This field is used in Output records to indicate that the output
31614 * is completely written to RAM. This field should be read as '1'
31615 * to indicate that the output has been completely written.
31616 * When writing a command completion or response to an internal processor,
31617 * the order of writes has to be such that this field is written last.
31620 } __attribute__((packed));
31622 /***************************
31623 * hwrm_stat_ctx_clr_stats *
31624 ***************************/
31627 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
31628 struct hwrm_stat_ctx_clr_stats_input {
31629 /* The HWRM command request type. */
31632 * The completion ring to send the completion event on. This should
31633 * be the NQ ID returned from the `nq_alloc` HWRM command.
31635 uint16_t cmpl_ring;
31637 * The sequence ID is used by the driver for tracking multiple
31638 * commands. This ID is treated as opaque data by the firmware and
31639 * the value is returned in the `hwrm_resp_hdr` upon completion.
31643 * The target ID of the command:
31644 * * 0x0-0xFFF8 - The function ID
31645 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31646 * * 0xFFFD - Reserved for user-space HWRM interface
31649 uint16_t target_id;
31651 * A physical address pointer pointing to a host buffer that the
31652 * command's response data will be written. This can be either a host
31653 * physical address (HPA) or a guest physical address (GPA) and must
31654 * point to a physically contiguous block of memory.
31656 uint64_t resp_addr;
31657 /* ID of the statistics context that is being queried. */
31658 uint32_t stat_ctx_id;
31659 uint8_t unused_0[4];
31660 } __attribute__((packed));
31662 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
31663 struct hwrm_stat_ctx_clr_stats_output {
31664 /* The specific error status for the command. */
31665 uint16_t error_code;
31666 /* The HWRM command request type. */
31668 /* The sequence ID from the original command. */
31670 /* The length of the response data in number of bytes. */
31672 uint8_t unused_0[7];
31674 * This field is used in Output records to indicate that the output
31675 * is completely written to RAM. This field should be read as '1'
31676 * to indicate that the output has been completely written.
31677 * When writing a command completion or response to an internal processor,
31678 * the order of writes has to be such that this field is written last.
31681 } __attribute__((packed));
31683 /********************
31684 * hwrm_pcie_qstats *
31685 ********************/
31688 /* hwrm_pcie_qstats_input (size:256b/32B) */
31689 struct hwrm_pcie_qstats_input {
31690 /* The HWRM command request type. */
31693 * The completion ring to send the completion event on. This should
31694 * be the NQ ID returned from the `nq_alloc` HWRM command.
31696 uint16_t cmpl_ring;
31698 * The sequence ID is used by the driver for tracking multiple
31699 * commands. This ID is treated as opaque data by the firmware and
31700 * the value is returned in the `hwrm_resp_hdr` upon completion.
31704 * The target ID of the command:
31705 * * 0x0-0xFFF8 - The function ID
31706 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31707 * * 0xFFFD - Reserved for user-space HWRM interface
31710 uint16_t target_id;
31712 * A physical address pointer pointing to a host buffer that the
31713 * command's response data will be written. This can be either a host
31714 * physical address (HPA) or a guest physical address (GPA) and must
31715 * point to a physically contiguous block of memory.
31717 uint64_t resp_addr;
31719 * The size of PCIe statistics block in bytes.
31720 * Firmware will DMA the PCIe statistics to
31721 * the host with this field size in the response.
31723 uint16_t pcie_stat_size;
31724 uint8_t unused_0[6];
31726 * This is the host address where
31727 * PCIe statistics will be stored
31729 uint64_t pcie_stat_host_addr;
31730 } __attribute__((packed));
31732 /* hwrm_pcie_qstats_output (size:128b/16B) */
31733 struct hwrm_pcie_qstats_output {
31734 /* The specific error status for the command. */
31735 uint16_t error_code;
31736 /* The HWRM command request type. */
31738 /* The sequence ID from the original command. */
31740 /* The length of the response data in number of bytes. */
31742 /* The size of PCIe statistics block in bytes. */
31743 uint16_t pcie_stat_size;
31744 uint8_t unused_0[5];
31746 * This field is used in Output records to indicate that the output
31747 * is completely written to RAM. This field should be read as '1'
31748 * to indicate that the output has been completely written.
31749 * When writing a command completion or response to an internal processor,
31750 * the order of writes has to be such that this field is written last.
31753 } __attribute__((packed));
31755 /* PCIe Statistics Formats */
31756 /* pcie_ctx_hw_stats (size:768b/96B) */
31757 struct pcie_ctx_hw_stats {
31758 /* Number of physical layer receiver errors */
31759 uint64_t pcie_pl_signal_integrity;
31760 /* Number of DLLP CRC errors detected by Data Link Layer */
31761 uint64_t pcie_dl_signal_integrity;
31763 * Number of TLP LCRC and sequence number errors detected
31764 * by Data Link Layer
31766 uint64_t pcie_tl_signal_integrity;
31767 /* Number of times LTSSM entered Recovery state */
31768 uint64_t pcie_link_integrity;
31769 /* Number of TLP bytes that have been trasmitted */
31770 uint64_t pcie_tx_traffic_rate;
31771 /* Number of TLP bytes that have been received */
31772 uint64_t pcie_rx_traffic_rate;
31773 /* Number of DLLP bytes that have been trasmitted */
31774 uint64_t pcie_tx_dllp_statistics;
31775 /* Number of DLLP bytes that have been received */
31776 uint64_t pcie_rx_dllp_statistics;
31778 * Number of times spent in each phase of gen3
31781 uint64_t pcie_equalization_time;
31782 /* Records the last 16 transitions of the LTSSM */
31783 uint32_t pcie_ltssm_histogram[4];
31785 * Record the last 8 reasons on why LTSSM transitioned
31788 uint64_t pcie_recovery_histogram;
31789 } __attribute__((packed));
31791 /**********************
31792 * hwrm_exec_fwd_resp *
31793 **********************/
31796 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
31797 struct hwrm_exec_fwd_resp_input {
31798 /* The HWRM command request type. */
31801 * The completion ring to send the completion event on. This should
31802 * be the NQ ID returned from the `nq_alloc` HWRM command.
31804 uint16_t cmpl_ring;
31806 * The sequence ID is used by the driver for tracking multiple
31807 * commands. This ID is treated as opaque data by the firmware and
31808 * the value is returned in the `hwrm_resp_hdr` upon completion.
31812 * The target ID of the command:
31813 * * 0x0-0xFFF8 - The function ID
31814 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31815 * * 0xFFFD - Reserved for user-space HWRM interface
31818 uint16_t target_id;
31820 * A physical address pointer pointing to a host buffer that the
31821 * command's response data will be written. This can be either a host
31822 * physical address (HPA) or a guest physical address (GPA) and must
31823 * point to a physically contiguous block of memory.
31825 uint64_t resp_addr;
31827 * This is an encapsulated request. This request should
31828 * be executed by the HWRM and the response should be
31829 * provided in the response buffer inside the encapsulated
31832 uint32_t encap_request[26];
31834 * This value indicates the target id of the response to
31835 * the encapsulated request.
31836 * 0x0 - 0xFFF8 - Used for function ids
31837 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31840 uint16_t encap_resp_target_id;
31841 uint8_t unused_0[6];
31842 } __attribute__((packed));
31844 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
31845 struct hwrm_exec_fwd_resp_output {
31846 /* The specific error status for the command. */
31847 uint16_t error_code;
31848 /* The HWRM command request type. */
31850 /* The sequence ID from the original command. */
31852 /* The length of the response data in number of bytes. */
31854 uint8_t unused_0[7];
31856 * This field is used in Output records to indicate that the output
31857 * is completely written to RAM. This field should be read as '1'
31858 * to indicate that the output has been completely written.
31859 * When writing a command completion or response to an internal processor,
31860 * the order of writes has to be such that this field is written last.
31863 } __attribute__((packed));
31865 /************************
31866 * hwrm_reject_fwd_resp *
31867 ************************/
31870 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
31871 struct hwrm_reject_fwd_resp_input {
31872 /* The HWRM command request type. */
31875 * The completion ring to send the completion event on. This should
31876 * be the NQ ID returned from the `nq_alloc` HWRM command.
31878 uint16_t cmpl_ring;
31880 * The sequence ID is used by the driver for tracking multiple
31881 * commands. This ID is treated as opaque data by the firmware and
31882 * the value is returned in the `hwrm_resp_hdr` upon completion.
31886 * The target ID of the command:
31887 * * 0x0-0xFFF8 - The function ID
31888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31889 * * 0xFFFD - Reserved for user-space HWRM interface
31892 uint16_t target_id;
31894 * A physical address pointer pointing to a host buffer that the
31895 * command's response data will be written. This can be either a host
31896 * physical address (HPA) or a guest physical address (GPA) and must
31897 * point to a physically contiguous block of memory.
31899 uint64_t resp_addr;
31901 * This is an encapsulated request. This request should
31902 * be rejected by the HWRM and the error response should be
31903 * provided in the response buffer inside the encapsulated
31906 uint32_t encap_request[26];
31908 * This value indicates the target id of the response to
31909 * the encapsulated request.
31910 * 0x0 - 0xFFF8 - Used for function ids
31911 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31914 uint16_t encap_resp_target_id;
31915 uint8_t unused_0[6];
31916 } __attribute__((packed));
31918 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
31919 struct hwrm_reject_fwd_resp_output {
31920 /* The specific error status for the command. */
31921 uint16_t error_code;
31922 /* The HWRM command request type. */
31924 /* The sequence ID from the original command. */
31926 /* The length of the response data in number of bytes. */
31928 uint8_t unused_0[7];
31930 * This field is used in Output records to indicate that the output
31931 * is completely written to RAM. This field should be read as '1'
31932 * to indicate that the output has been completely written.
31933 * When writing a command completion or response to an internal processor,
31934 * the order of writes has to be such that this field is written last.
31937 } __attribute__((packed));
31944 /* hwrm_fwd_resp_input (size:1024b/128B) */
31945 struct hwrm_fwd_resp_input {
31946 /* The HWRM command request type. */
31949 * The completion ring to send the completion event on. This should
31950 * be the NQ ID returned from the `nq_alloc` HWRM command.
31952 uint16_t cmpl_ring;
31954 * The sequence ID is used by the driver for tracking multiple
31955 * commands. This ID is treated as opaque data by the firmware and
31956 * the value is returned in the `hwrm_resp_hdr` upon completion.
31960 * The target ID of the command:
31961 * * 0x0-0xFFF8 - The function ID
31962 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31963 * * 0xFFFD - Reserved for user-space HWRM interface
31966 uint16_t target_id;
31968 * A physical address pointer pointing to a host buffer that the
31969 * command's response data will be written. This can be either a host
31970 * physical address (HPA) or a guest physical address (GPA) and must
31971 * point to a physically contiguous block of memory.
31973 uint64_t resp_addr;
31975 * This value indicates the target id of the encapsulated
31977 * 0x0 - 0xFFF8 - Used for function ids
31978 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31981 uint16_t encap_resp_target_id;
31983 * This value indicates the completion ring the encapsulated
31984 * response will be optionally completed on. If the value is
31985 * -1, then no CR completion shall be generated for the
31986 * encapsulated response. Any other value must be a
31987 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
31988 * is provided, then a CR completion shall be generated for
31989 * the encapsulated response.
31991 uint16_t encap_resp_cmpl_ring;
31992 /* This field indicates the length of encapsulated response. */
31993 uint16_t encap_resp_len;
31997 * This is the host address where the encapsulated response
31999 * This area must be 16B aligned and must be cleared to zero
32000 * before the original request is made.
32002 uint64_t encap_resp_addr;
32003 /* This is an encapsulated response. */
32004 uint32_t encap_resp[24];
32005 } __attribute__((packed));
32007 /* hwrm_fwd_resp_output (size:128b/16B) */
32008 struct hwrm_fwd_resp_output {
32009 /* The specific error status for the command. */
32010 uint16_t error_code;
32011 /* The HWRM command request type. */
32013 /* The sequence ID from the original command. */
32015 /* The length of the response data in number of bytes. */
32017 uint8_t unused_0[7];
32019 * This field is used in Output records to indicate that the output
32020 * is completely written to RAM. This field should be read as '1'
32021 * to indicate that the output has been completely written.
32022 * When writing a command completion or response to an internal processor,
32023 * the order of writes has to be such that this field is written last.
32026 } __attribute__((packed));
32028 /*****************************
32029 * hwrm_fwd_async_event_cmpl *
32030 *****************************/
32033 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
32034 struct hwrm_fwd_async_event_cmpl_input {
32035 /* The HWRM command request type. */
32038 * The completion ring to send the completion event on. This should
32039 * be the NQ ID returned from the `nq_alloc` HWRM command.
32041 uint16_t cmpl_ring;
32043 * The sequence ID is used by the driver for tracking multiple
32044 * commands. This ID is treated as opaque data by the firmware and
32045 * the value is returned in the `hwrm_resp_hdr` upon completion.
32049 * The target ID of the command:
32050 * * 0x0-0xFFF8 - The function ID
32051 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32052 * * 0xFFFD - Reserved for user-space HWRM interface
32055 uint16_t target_id;
32057 * A physical address pointer pointing to a host buffer that the
32058 * command's response data will be written. This can be either a host
32059 * physical address (HPA) or a guest physical address (GPA) and must
32060 * point to a physically contiguous block of memory.
32062 uint64_t resp_addr;
32064 * This value indicates the target id of the encapsulated
32065 * asynchronous event.
32066 * 0x0 - 0xFFF8 - Used for function ids
32067 * 0xFFF8 - 0xFFFE - Reserved for internal processors
32068 * 0xFFFF - Broadcast to all children VFs (only applicable when
32069 * a PF is the requester)
32071 uint16_t encap_async_event_target_id;
32072 uint8_t unused_0[6];
32073 /* This is an encapsulated asynchronous event completion. */
32074 uint32_t encap_async_event_cmpl[4];
32075 } __attribute__((packed));
32077 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
32078 struct hwrm_fwd_async_event_cmpl_output {
32079 /* The specific error status for the command. */
32080 uint16_t error_code;
32081 /* The HWRM command request type. */
32083 /* The sequence ID from the original command. */
32085 /* The length of the response data in number of bytes. */
32087 uint8_t unused_0[7];
32089 * This field is used in Output records to indicate that the output
32090 * is completely written to RAM. This field should be read as '1'
32091 * to indicate that the output has been completely written.
32092 * When writing a command completion or response to an internal processor,
32093 * the order of writes has to be such that this field is written last.
32096 } __attribute__((packed));
32098 /**************************
32099 * hwrm_nvm_raw_write_blk *
32100 **************************/
32103 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
32104 struct hwrm_nvm_raw_write_blk_input {
32105 /* The HWRM command request type. */
32108 * The completion ring to send the completion event on. This should
32109 * be the NQ ID returned from the `nq_alloc` HWRM command.
32111 uint16_t cmpl_ring;
32113 * The sequence ID is used by the driver for tracking multiple
32114 * commands. This ID is treated as opaque data by the firmware and
32115 * the value is returned in the `hwrm_resp_hdr` upon completion.
32119 * The target ID of the command:
32120 * * 0x0-0xFFF8 - The function ID
32121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32122 * * 0xFFFD - Reserved for user-space HWRM interface
32125 uint16_t target_id;
32127 * A physical address pointer pointing to a host buffer that the
32128 * command's response data will be written. This can be either a host
32129 * physical address (HPA) or a guest physical address (GPA) and must
32130 * point to a physically contiguous block of memory.
32132 uint64_t resp_addr;
32134 * 64-bit Host Source Address.
32135 * This is the loation of the source data to be written.
32137 uint64_t host_src_addr;
32139 * 32-bit Destination Address.
32140 * This is the NVRAM byte-offset where the source data will be written to.
32142 uint32_t dest_addr;
32143 /* Length of data to be written, in bytes. */
32145 } __attribute__((packed));
32147 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
32148 struct hwrm_nvm_raw_write_blk_output {
32149 /* The specific error status for the command. */
32150 uint16_t error_code;
32151 /* The HWRM command request type. */
32153 /* The sequence ID from the original command. */
32155 /* The length of the response data in number of bytes. */
32157 uint8_t unused_0[7];
32159 * This field is used in Output records to indicate that the output
32160 * is completely written to RAM. This field should be read as '1'
32161 * to indicate that the output has been completely written.
32162 * When writing a command completion or response to an internal processor,
32163 * the order of writes has to be such that this field is written last.
32166 } __attribute__((packed));
32173 /* hwrm_nvm_read_input (size:320b/40B) */
32174 struct hwrm_nvm_read_input {
32175 /* The HWRM command request type. */
32178 * The completion ring to send the completion event on. This should
32179 * be the NQ ID returned from the `nq_alloc` HWRM command.
32181 uint16_t cmpl_ring;
32183 * The sequence ID is used by the driver for tracking multiple
32184 * commands. This ID is treated as opaque data by the firmware and
32185 * the value is returned in the `hwrm_resp_hdr` upon completion.
32189 * The target ID of the command:
32190 * * 0x0-0xFFF8 - The function ID
32191 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32192 * * 0xFFFD - Reserved for user-space HWRM interface
32195 uint16_t target_id;
32197 * A physical address pointer pointing to a host buffer that the
32198 * command's response data will be written. This can be either a host
32199 * physical address (HPA) or a guest physical address (GPA) and must
32200 * point to a physically contiguous block of memory.
32202 uint64_t resp_addr;
32204 * 64-bit Host Destination Address.
32205 * This is the host address where the data will be written to.
32207 uint64_t host_dest_addr;
32208 /* The 0-based index of the directory entry. */
32210 uint8_t unused_0[2];
32211 /* The NVRAM byte-offset to read from. */
32213 /* The length of the data to be read, in bytes. */
32215 uint8_t unused_1[4];
32216 } __attribute__((packed));
32218 /* hwrm_nvm_read_output (size:128b/16B) */
32219 struct hwrm_nvm_read_output {
32220 /* The specific error status for the command. */
32221 uint16_t error_code;
32222 /* The HWRM command request type. */
32224 /* The sequence ID from the original command. */
32226 /* The length of the response data in number of bytes. */
32228 uint8_t unused_0[7];
32230 * This field is used in Output records to indicate that the output
32231 * is completely written to RAM. This field should be read as '1'
32232 * to indicate that the output has been completely written.
32233 * When writing a command completion or response to an internal processor,
32234 * the order of writes has to be such that this field is written last.
32237 } __attribute__((packed));
32239 /*********************
32240 * hwrm_nvm_raw_dump *
32241 *********************/
32244 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
32245 struct hwrm_nvm_raw_dump_input {
32246 /* The HWRM command request type. */
32249 * The completion ring to send the completion event on. This should
32250 * be the NQ ID returned from the `nq_alloc` HWRM command.
32252 uint16_t cmpl_ring;
32254 * The sequence ID is used by the driver for tracking multiple
32255 * commands. This ID is treated as opaque data by the firmware and
32256 * the value is returned in the `hwrm_resp_hdr` upon completion.
32260 * The target ID of the command:
32261 * * 0x0-0xFFF8 - The function ID
32262 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32263 * * 0xFFFD - Reserved for user-space HWRM interface
32266 uint16_t target_id;
32268 * A physical address pointer pointing to a host buffer that the
32269 * command's response data will be written. This can be either a host
32270 * physical address (HPA) or a guest physical address (GPA) and must
32271 * point to a physically contiguous block of memory.
32273 uint64_t resp_addr;
32275 * 64-bit Host Destination Address.
32276 * This is the host address where the data will be written to.
32278 uint64_t host_dest_addr;
32279 /* 32-bit NVRAM byte-offset to read from. */
32281 /* Total length of NVRAM contents to be read, in bytes. */
32283 } __attribute__((packed));
32285 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
32286 struct hwrm_nvm_raw_dump_output {
32287 /* The specific error status for the command. */
32288 uint16_t error_code;
32289 /* The HWRM command request type. */
32291 /* The sequence ID from the original command. */
32293 /* The length of the response data in number of bytes. */
32295 uint8_t unused_0[7];
32297 * This field is used in Output records to indicate that the output
32298 * is completely written to RAM. This field should be read as '1'
32299 * to indicate that the output has been completely written.
32300 * When writing a command completion or response to an internal processor,
32301 * the order of writes has to be such that this field is written last.
32304 } __attribute__((packed));
32306 /****************************
32307 * hwrm_nvm_get_dir_entries *
32308 ****************************/
32311 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
32312 struct hwrm_nvm_get_dir_entries_input {
32313 /* The HWRM command request type. */
32316 * The completion ring to send the completion event on. This should
32317 * be the NQ ID returned from the `nq_alloc` HWRM command.
32319 uint16_t cmpl_ring;
32321 * The sequence ID is used by the driver for tracking multiple
32322 * commands. This ID is treated as opaque data by the firmware and
32323 * the value is returned in the `hwrm_resp_hdr` upon completion.
32327 * The target ID of the command:
32328 * * 0x0-0xFFF8 - The function ID
32329 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32330 * * 0xFFFD - Reserved for user-space HWRM interface
32333 uint16_t target_id;
32335 * A physical address pointer pointing to a host buffer that the
32336 * command's response data will be written. This can be either a host
32337 * physical address (HPA) or a guest physical address (GPA) and must
32338 * point to a physically contiguous block of memory.
32340 uint64_t resp_addr;
32342 * 64-bit Host Destination Address.
32343 * This is the host address where the directory will be written.
32345 uint64_t host_dest_addr;
32346 } __attribute__((packed));
32348 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
32349 struct hwrm_nvm_get_dir_entries_output {
32350 /* The specific error status for the command. */
32351 uint16_t error_code;
32352 /* The HWRM command request type. */
32354 /* The sequence ID from the original command. */
32356 /* The length of the response data in number of bytes. */
32358 uint8_t unused_0[7];
32360 * This field is used in Output records to indicate that the output
32361 * is completely written to RAM. This field should be read as '1'
32362 * to indicate that the output has been completely written.
32363 * When writing a command completion or response to an internal processor,
32364 * the order of writes has to be such that this field is written last.
32367 } __attribute__((packed));
32369 /*************************
32370 * hwrm_nvm_get_dir_info *
32371 *************************/
32374 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
32375 struct hwrm_nvm_get_dir_info_input {
32376 /* The HWRM command request type. */
32379 * The completion ring to send the completion event on. This should
32380 * be the NQ ID returned from the `nq_alloc` HWRM command.
32382 uint16_t cmpl_ring;
32384 * The sequence ID is used by the driver for tracking multiple
32385 * commands. This ID is treated as opaque data by the firmware and
32386 * the value is returned in the `hwrm_resp_hdr` upon completion.
32390 * The target ID of the command:
32391 * * 0x0-0xFFF8 - The function ID
32392 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32393 * * 0xFFFD - Reserved for user-space HWRM interface
32396 uint16_t target_id;
32398 * A physical address pointer pointing to a host buffer that the
32399 * command's response data will be written. This can be either a host
32400 * physical address (HPA) or a guest physical address (GPA) and must
32401 * point to a physically contiguous block of memory.
32403 uint64_t resp_addr;
32404 } __attribute__((packed));
32406 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
32407 struct hwrm_nvm_get_dir_info_output {
32408 /* The specific error status for the command. */
32409 uint16_t error_code;
32410 /* The HWRM command request type. */
32412 /* The sequence ID from the original command. */
32414 /* The length of the response data in number of bytes. */
32416 /* Number of directory entries in the directory. */
32418 /* Size of each directory entry, in bytes. */
32419 uint32_t entry_length;
32420 uint8_t unused_0[7];
32422 * This field is used in Output records to indicate that the output
32423 * is completely written to RAM. This field should be read as '1'
32424 * to indicate that the output has been completely written.
32425 * When writing a command completion or response to an internal processor,
32426 * the order of writes has to be such that this field is written last.
32429 } __attribute__((packed));
32431 /******************
32433 ******************/
32436 /* hwrm_nvm_write_input (size:384b/48B) */
32437 struct hwrm_nvm_write_input {
32438 /* The HWRM command request type. */
32441 * The completion ring to send the completion event on. This should
32442 * be the NQ ID returned from the `nq_alloc` HWRM command.
32444 uint16_t cmpl_ring;
32446 * The sequence ID is used by the driver for tracking multiple
32447 * commands. This ID is treated as opaque data by the firmware and
32448 * the value is returned in the `hwrm_resp_hdr` upon completion.
32452 * The target ID of the command:
32453 * * 0x0-0xFFF8 - The function ID
32454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32455 * * 0xFFFD - Reserved for user-space HWRM interface
32458 uint16_t target_id;
32460 * A physical address pointer pointing to a host buffer that the
32461 * command's response data will be written. This can be either a host
32462 * physical address (HPA) or a guest physical address (GPA) and must
32463 * point to a physically contiguous block of memory.
32465 uint64_t resp_addr;
32467 * 64-bit Host Source Address.
32468 * This is where the source data is.
32470 uint64_t host_src_addr;
32471 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
32474 * Directory ordinal.
32475 * The 0-based instance of the combined Directory Entry Type and Extension.
32477 uint16_t dir_ordinal;
32478 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
32480 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
32483 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
32484 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
32486 uint32_t dir_data_length;
32491 * When this bit is '1', the original active image
32492 * will not be removed. TBD: what purpose is this?
32494 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
32497 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
32498 * If this value is less than the specified data length, it will be ignored.
32499 * The response will contain the actual allocated item length, which may be greater than the requested item length.
32500 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
32501 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
32503 uint32_t dir_item_length;
32505 } __attribute__((packed));
32507 /* hwrm_nvm_write_output (size:128b/16B) */
32508 struct hwrm_nvm_write_output {
32509 /* The specific error status for the command. */
32510 uint16_t error_code;
32511 /* The HWRM command request type. */
32513 /* The sequence ID from the original command. */
32515 /* The length of the response data in number of bytes. */
32518 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
32519 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
32521 uint32_t dir_item_length;
32522 /* The directory index of the created or modified item. */
32526 * This field is used in Output records to indicate that the output
32527 * is completely written to RAM. This field should be read as '1'
32528 * to indicate that the output has been completely written.
32529 * When writing a command completion or response to an internal processor,
32530 * the order of writes has to be such that this field is written last.
32533 } __attribute__((packed));
32535 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
32536 struct hwrm_nvm_write_cmd_err {
32538 * command specific error codes that goes to
32539 * the cmd_err field in Common HWRM Error Response.
32542 /* Unknown error */
32543 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32544 /* Unable to complete operation due to fragmentation */
32545 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
32546 /* nvm is completely full. */
32547 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
32548 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
32549 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
32550 uint8_t unused_0[7];
32551 } __attribute__((packed));
32553 /*******************
32554 * hwrm_nvm_modify *
32555 *******************/
32558 /* hwrm_nvm_modify_input (size:320b/40B) */
32559 struct hwrm_nvm_modify_input {
32560 /* The HWRM command request type. */
32563 * The completion ring to send the completion event on. This should
32564 * be the NQ ID returned from the `nq_alloc` HWRM command.
32566 uint16_t cmpl_ring;
32568 * The sequence ID is used by the driver for tracking multiple
32569 * commands. This ID is treated as opaque data by the firmware and
32570 * the value is returned in the `hwrm_resp_hdr` upon completion.
32574 * The target ID of the command:
32575 * * 0x0-0xFFF8 - The function ID
32576 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32577 * * 0xFFFD - Reserved for user-space HWRM interface
32580 uint16_t target_id;
32582 * A physical address pointer pointing to a host buffer that the
32583 * command's response data will be written. This can be either a host
32584 * physical address (HPA) or a guest physical address (GPA) and must
32585 * point to a physically contiguous block of memory.
32587 uint64_t resp_addr;
32589 * 64-bit Host Source Address.
32590 * This is where the modified data is.
32592 uint64_t host_src_addr;
32593 /* 16-bit directory entry index. */
32595 uint8_t unused_0[2];
32596 /* 32-bit NVRAM byte-offset to modify content from. */
32599 * Length of data to be modified, in bytes. The length shall
32603 uint8_t unused_1[4];
32604 } __attribute__((packed));
32606 /* hwrm_nvm_modify_output (size:128b/16B) */
32607 struct hwrm_nvm_modify_output {
32608 /* The specific error status for the command. */
32609 uint16_t error_code;
32610 /* The HWRM command request type. */
32612 /* The sequence ID from the original command. */
32614 /* The length of the response data in number of bytes. */
32616 uint8_t unused_0[7];
32618 * This field is used in Output records to indicate that the output
32619 * is completely written to RAM. This field should be read as '1'
32620 * to indicate that the output has been completely written.
32621 * When writing a command completion or response to an internal processor,
32622 * the order of writes has to be such that this field is written last.
32625 } __attribute__((packed));
32627 /***************************
32628 * hwrm_nvm_find_dir_entry *
32629 ***************************/
32632 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
32633 struct hwrm_nvm_find_dir_entry_input {
32634 /* The HWRM command request type. */
32637 * The completion ring to send the completion event on. This should
32638 * be the NQ ID returned from the `nq_alloc` HWRM command.
32640 uint16_t cmpl_ring;
32642 * The sequence ID is used by the driver for tracking multiple
32643 * commands. This ID is treated as opaque data by the firmware and
32644 * the value is returned in the `hwrm_resp_hdr` upon completion.
32648 * The target ID of the command:
32649 * * 0x0-0xFFF8 - The function ID
32650 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32651 * * 0xFFFD - Reserved for user-space HWRM interface
32654 uint16_t target_id;
32656 * A physical address pointer pointing to a host buffer that the
32657 * command's response data will be written. This can be either a host
32658 * physical address (HPA) or a guest physical address (GPA) and must
32659 * point to a physically contiguous block of memory.
32661 uint64_t resp_addr;
32664 * This bit must be '1' for the dir_idx_valid field to be
32667 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
32669 /* Directory Entry Index */
32671 /* Directory Entry (Image) Type */
32674 * Directory ordinal.
32675 * The instance of this Directory Type
32677 uint16_t dir_ordinal;
32678 /* The Directory Entry Extension flags. */
32680 /* This value indicates the search option using dir_ordinal. */
32681 uint8_t opt_ordinal;
32682 /* This value indicates the search option using dir_ordinal. */
32683 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
32684 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
32685 /* Equal to specified ordinal value. */
32686 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
32687 /* Greater than or equal to specified ordinal value */
32688 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
32689 /* Greater than specified ordinal value */
32690 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
32691 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
32692 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
32693 uint8_t unused_0[3];
32694 } __attribute__((packed));
32696 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
32697 struct hwrm_nvm_find_dir_entry_output {
32698 /* The specific error status for the command. */
32699 uint16_t error_code;
32700 /* The HWRM command request type. */
32702 /* The sequence ID from the original command. */
32704 /* The length of the response data in number of bytes. */
32706 /* Allocated NVRAM for this directory entry, in bytes. */
32707 uint32_t dir_item_length;
32708 /* Size of the stored data for this directory entry, in bytes. */
32709 uint32_t dir_data_length;
32711 * Firmware version.
32712 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
32715 /* Directory ordinal. */
32716 uint16_t dir_ordinal;
32717 /* Directory Entry Index */
32719 uint8_t unused_0[7];
32721 * This field is used in Output records to indicate that the output
32722 * is completely written to RAM. This field should be read as '1'
32723 * to indicate that the output has been completely written.
32724 * When writing a command completion or response to an internal processor,
32725 * the order of writes has to be such that this field is written last.
32728 } __attribute__((packed));
32730 /****************************
32731 * hwrm_nvm_erase_dir_entry *
32732 ****************************/
32735 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
32736 struct hwrm_nvm_erase_dir_entry_input {
32737 /* The HWRM command request type. */
32740 * The completion ring to send the completion event on. This should
32741 * be the NQ ID returned from the `nq_alloc` HWRM command.
32743 uint16_t cmpl_ring;
32745 * The sequence ID is used by the driver for tracking multiple
32746 * commands. This ID is treated as opaque data by the firmware and
32747 * the value is returned in the `hwrm_resp_hdr` upon completion.
32751 * The target ID of the command:
32752 * * 0x0-0xFFF8 - The function ID
32753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32754 * * 0xFFFD - Reserved for user-space HWRM interface
32757 uint16_t target_id;
32759 * A physical address pointer pointing to a host buffer that the
32760 * command's response data will be written. This can be either a host
32761 * physical address (HPA) or a guest physical address (GPA) and must
32762 * point to a physically contiguous block of memory.
32764 uint64_t resp_addr;
32765 /* Directory Entry Index */
32767 uint8_t unused_0[6];
32768 } __attribute__((packed));
32770 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
32771 struct hwrm_nvm_erase_dir_entry_output {
32772 /* The specific error status for the command. */
32773 uint16_t error_code;
32774 /* The HWRM command request type. */
32776 /* The sequence ID from the original command. */
32778 /* The length of the response data in number of bytes. */
32780 uint8_t unused_0[7];
32782 * This field is used in Output records to indicate that the output
32783 * is completely written to RAM. This field should be read as '1'
32784 * to indicate that the output has been completely written.
32785 * When writing a command completion or response to an internal processor,
32786 * the order of writes has to be such that this field is written last.
32789 } __attribute__((packed));
32791 /*************************
32792 * hwrm_nvm_get_dev_info *
32793 *************************/
32796 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
32797 struct hwrm_nvm_get_dev_info_input {
32798 /* The HWRM command request type. */
32801 * The completion ring to send the completion event on. This should
32802 * be the NQ ID returned from the `nq_alloc` HWRM command.
32804 uint16_t cmpl_ring;
32806 * The sequence ID is used by the driver for tracking multiple
32807 * commands. This ID is treated as opaque data by the firmware and
32808 * the value is returned in the `hwrm_resp_hdr` upon completion.
32812 * The target ID of the command:
32813 * * 0x0-0xFFF8 - The function ID
32814 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32815 * * 0xFFFD - Reserved for user-space HWRM interface
32818 uint16_t target_id;
32820 * A physical address pointer pointing to a host buffer that the
32821 * command's response data will be written. This can be either a host
32822 * physical address (HPA) or a guest physical address (GPA) and must
32823 * point to a physically contiguous block of memory.
32825 uint64_t resp_addr;
32826 } __attribute__((packed));
32828 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
32829 struct hwrm_nvm_get_dev_info_output {
32830 /* The specific error status for the command. */
32831 uint16_t error_code;
32832 /* The HWRM command request type. */
32834 /* The sequence ID from the original command. */
32836 /* The length of the response data in number of bytes. */
32838 /* Manufacturer ID. */
32839 uint16_t manufacturer_id;
32841 uint16_t device_id;
32842 /* Sector size of the NVRAM device. */
32843 uint32_t sector_size;
32844 /* Total size, in bytes of the NVRAM device. */
32845 uint32_t nvram_size;
32846 uint32_t reserved_size;
32847 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
32848 uint32_t available_size;
32849 /* This field represents the major version of NVM cfg */
32850 uint8_t nvm_cfg_ver_maj;
32851 /* This field represents the minor version of NVM cfg */
32852 uint8_t nvm_cfg_ver_min;
32853 /* This field represents the update version of NVM cfg */
32854 uint8_t nvm_cfg_ver_upd;
32856 * This field is used in Output records to indicate that the output
32857 * is completely written to RAM. This field should be read as '1'
32858 * to indicate that the output has been completely written.
32859 * When writing a command completion or response to an internal processor,
32860 * the order of writes has to be such that this field is written last.
32863 } __attribute__((packed));
32865 /**************************
32866 * hwrm_nvm_mod_dir_entry *
32867 **************************/
32870 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
32871 struct hwrm_nvm_mod_dir_entry_input {
32872 /* The HWRM command request type. */
32875 * The completion ring to send the completion event on. This should
32876 * be the NQ ID returned from the `nq_alloc` HWRM command.
32878 uint16_t cmpl_ring;
32880 * The sequence ID is used by the driver for tracking multiple
32881 * commands. This ID is treated as opaque data by the firmware and
32882 * the value is returned in the `hwrm_resp_hdr` upon completion.
32886 * The target ID of the command:
32887 * * 0x0-0xFFF8 - The function ID
32888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32889 * * 0xFFFD - Reserved for user-space HWRM interface
32892 uint16_t target_id;
32894 * A physical address pointer pointing to a host buffer that the
32895 * command's response data will be written. This can be either a host
32896 * physical address (HPA) or a guest physical address (GPA) and must
32897 * point to a physically contiguous block of memory.
32899 uint64_t resp_addr;
32902 * This bit must be '1' for the checksum field to be
32905 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
32906 /* Directory Entry Index */
32909 * Directory ordinal.
32910 * The (0-based) instance of this Directory Type.
32912 uint16_t dir_ordinal;
32913 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
32915 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
32918 * If valid, then this field updates the checksum
32919 * value of the content in the directory entry.
32922 } __attribute__((packed));
32924 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
32925 struct hwrm_nvm_mod_dir_entry_output {
32926 /* The specific error status for the command. */
32927 uint16_t error_code;
32928 /* The HWRM command request type. */
32930 /* The sequence ID from the original command. */
32932 /* The length of the response data in number of bytes. */
32934 uint8_t unused_0[7];
32936 * This field is used in Output records to indicate that the output
32937 * is completely written to RAM. This field should be read as '1'
32938 * to indicate that the output has been completely written.
32939 * When writing a command completion or response to an internal processor,
32940 * the order of writes has to be such that this field is written last.
32943 } __attribute__((packed));
32945 /**************************
32946 * hwrm_nvm_verify_update *
32947 **************************/
32950 /* hwrm_nvm_verify_update_input (size:192b/24B) */
32951 struct hwrm_nvm_verify_update_input {
32952 /* The HWRM command request type. */
32955 * The completion ring to send the completion event on. This should
32956 * be the NQ ID returned from the `nq_alloc` HWRM command.
32958 uint16_t cmpl_ring;
32960 * The sequence ID is used by the driver for tracking multiple
32961 * commands. This ID is treated as opaque data by the firmware and
32962 * the value is returned in the `hwrm_resp_hdr` upon completion.
32966 * The target ID of the command:
32967 * * 0x0-0xFFF8 - The function ID
32968 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32969 * * 0xFFFD - Reserved for user-space HWRM interface
32972 uint16_t target_id;
32974 * A physical address pointer pointing to a host buffer that the
32975 * command's response data will be written. This can be either a host
32976 * physical address (HPA) or a guest physical address (GPA) and must
32977 * point to a physically contiguous block of memory.
32979 uint64_t resp_addr;
32980 /* Directory Entry Type, to be verified. */
32983 * Directory ordinal.
32984 * The instance of the Directory Type to be verified.
32986 uint16_t dir_ordinal;
32988 * The Directory Entry Extension flags.
32989 * The "UPDATE" extension flag must be set in this value.
32990 * A corresponding directory entry with the same type and ordinal values but *without*
32991 * the "UPDATE" extension flag must also exist. The other flags of the extension must
32992 * be identical between the active and update entries.
32995 uint8_t unused_0[2];
32996 } __attribute__((packed));
32998 /* hwrm_nvm_verify_update_output (size:128b/16B) */
32999 struct hwrm_nvm_verify_update_output {
33000 /* The specific error status for the command. */
33001 uint16_t error_code;
33002 /* The HWRM command request type. */
33004 /* The sequence ID from the original command. */
33006 /* The length of the response data in number of bytes. */
33008 uint8_t unused_0[7];
33010 * This field is used in Output records to indicate that the output
33011 * is completely written to RAM. This field should be read as '1'
33012 * to indicate that the output has been completely written.
33013 * When writing a command completion or response to an internal processor,
33014 * the order of writes has to be such that this field is written last.
33017 } __attribute__((packed));
33019 /***************************
33020 * hwrm_nvm_install_update *
33021 ***************************/
33024 /* hwrm_nvm_install_update_input (size:192b/24B) */
33025 struct hwrm_nvm_install_update_input {
33026 /* The HWRM command request type. */
33029 * The completion ring to send the completion event on. This should
33030 * be the NQ ID returned from the `nq_alloc` HWRM command.
33032 uint16_t cmpl_ring;
33034 * The sequence ID is used by the driver for tracking multiple
33035 * commands. This ID is treated as opaque data by the firmware and
33036 * the value is returned in the `hwrm_resp_hdr` upon completion.
33040 * The target ID of the command:
33041 * * 0x0-0xFFF8 - The function ID
33042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33043 * * 0xFFFD - Reserved for user-space HWRM interface
33046 uint16_t target_id;
33048 * A physical address pointer pointing to a host buffer that the
33049 * command's response data will be written. This can be either a host
33050 * physical address (HPA) or a guest physical address (GPA) and must
33051 * point to a physically contiguous block of memory.
33053 uint64_t resp_addr;
33055 * Installation type. If the value 3 through 0xffff is used,
33056 * only packaged items with that type value will be installed and
33057 * conditional installation directives for those packaged items
33058 * will be over-ridden (i.e. 'create' or 'replace' will be treated
33061 uint32_t install_type;
33063 * Perform a normal package installation. Conditional installation
33064 * directives (e.g. 'create' and 'replace') of packaged items
33065 * will be followed.
33067 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
33069 * Install all packaged items regardless of installation directive
33070 * (i.e. treat all packaged items as though they have an installation
33071 * directive of 'install').
33073 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
33074 UINT32_C(0xffffffff)
33075 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
33076 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
33078 /* If set to 1, then securely erase all unused locations in persistent storage. */
33079 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
33082 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
33083 * When combined with erase_unused_space then unspecified images will be securely erased.
33085 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
33088 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
33089 * Allow additional time for this command to complete if this bit is set to 1.
33091 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
33093 uint8_t unused_0[2];
33094 } __attribute__((packed));
33096 /* hwrm_nvm_install_update_output (size:192b/24B) */
33097 struct hwrm_nvm_install_update_output {
33098 /* The specific error status for the command. */
33099 uint16_t error_code;
33100 /* The HWRM command request type. */
33102 /* The sequence ID from the original command. */
33104 /* The length of the response data in number of bytes. */
33107 * Bit-mask of successfully installed items.
33108 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
33109 * A value of 0 indicates that no items were successfully installed.
33111 uint64_t installed_items;
33112 /* result is 8 b */
33114 /* There was no problem with the package installation. */
33115 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
33116 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
33117 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
33118 /* problem_item is 8 b */
33119 uint8_t problem_item;
33120 /* There was no problem with any packaged items. */
33121 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
33123 /* There was a problem with the NVM package itself. */
33124 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
33126 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
33127 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
33128 /* reset_required is 8 b */
33129 uint8_t reset_required;
33131 * No reset is required for installed/updated firmware or
33132 * microcode to take effect.
33134 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
33137 * A PCIe reset (e.g. system reboot) is
33138 * required for newly installed/updated firmware or
33139 * microcode to take effect.
33141 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
33144 * A controller power reset (e.g. system power-cycle) is
33145 * required for newly installed/updated firmware or
33146 * microcode to take effect. Some newly installed/updated
33147 * firmware or microcode may still take effect upon the
33150 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
33152 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
33153 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
33154 uint8_t unused_0[4];
33156 * This field is used in Output records to indicate that the output
33157 * is completely written to RAM. This field should be read as '1'
33158 * to indicate that the output has been completely written.
33159 * When writing a command completion or response to an internal processor,
33160 * the order of writes has to be such that this field is written last.
33163 } __attribute__((packed));
33165 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
33166 struct hwrm_nvm_install_update_cmd_err {
33168 * command specific error codes that goes to
33169 * the cmd_err field in Common HWRM Error Response.
33172 /* Unknown error */
33173 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33174 /* Unable to complete operation due to fragmentation */
33175 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
33176 /* nvm is completely full. */
33177 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
33178 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
33179 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
33180 uint8_t unused_0[7];
33181 } __attribute__((packed));
33183 /******************
33185 ******************/
33188 /* hwrm_nvm_flush_input (size:128b/16B) */
33189 struct hwrm_nvm_flush_input {
33190 /* The HWRM command request type. */
33193 * The completion ring to send the completion event on. This should
33194 * be the NQ ID returned from the `nq_alloc` HWRM command.
33196 uint16_t cmpl_ring;
33198 * The sequence ID is used by the driver for tracking multiple
33199 * commands. This ID is treated as opaque data by the firmware and
33200 * the value is returned in the `hwrm_resp_hdr` upon completion.
33204 * The target ID of the command:
33205 * * 0x0-0xFFF8 - The function ID
33206 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33207 * * 0xFFFD - Reserved for user-space HWRM interface
33210 uint16_t target_id;
33212 * A physical address pointer pointing to a host buffer that the
33213 * command's response data will be written. This can be either a host
33214 * physical address (HPA) or a guest physical address (GPA) and must
33215 * point to a physically contiguous block of memory.
33217 uint64_t resp_addr;
33218 } __attribute__((packed));
33220 /* hwrm_nvm_flush_output (size:128b/16B) */
33221 struct hwrm_nvm_flush_output {
33222 /* The specific error status for the command. */
33223 uint16_t error_code;
33224 /* The HWRM command request type. */
33226 /* The sequence ID from the original command. */
33228 /* The length of the response data in number of bytes. */
33230 uint8_t unused_0[7];
33232 * This field is used in Output records to indicate that the output
33233 * is completely written to RAM. This field should be read as '1'
33234 * to indicate that the output has been completely written.
33235 * When writing a command completion or response to an internal processor,
33236 * the order of writes has to be such that this field is written last.
33239 } __attribute__((packed));
33241 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
33242 struct hwrm_nvm_flush_cmd_err {
33244 * command specific error codes that goes to
33245 * the cmd_err field in Common HWRM Error Response.
33248 /* Unknown error */
33249 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33250 /* flush could not be performed */
33251 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
33252 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
33253 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
33254 uint8_t unused_0[7];
33255 } __attribute__((packed));
33257 /*************************
33258 * hwrm_nvm_get_variable *
33259 *************************/
33262 /* hwrm_nvm_get_variable_input (size:320b/40B) */
33263 struct hwrm_nvm_get_variable_input {
33264 /* The HWRM command request type. */
33267 * The completion ring to send the completion event on. This should
33268 * be the NQ ID returned from the `nq_alloc` HWRM command.
33270 uint16_t cmpl_ring;
33272 * The sequence ID is used by the driver for tracking multiple
33273 * commands. This ID is treated as opaque data by the firmware and
33274 * the value is returned in the `hwrm_resp_hdr` upon completion.
33278 * The target ID of the command:
33279 * * 0x0-0xFFF8 - The function ID
33280 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33281 * * 0xFFFD - Reserved for user-space HWRM interface
33284 uint16_t target_id;
33286 * A physical address pointer pointing to a host buffer that the
33287 * command's response data will be written. This can be either a host
33288 * physical address (HPA) or a guest physical address (GPA) and must
33289 * point to a physically contiguous block of memory.
33291 uint64_t resp_addr;
33293 * This is the host address where
33294 * nvm variable will be stored
33296 uint64_t dest_data_addr;
33297 /* size of data in bits */
33299 /* nvm cfg option number */
33300 uint16_t option_num;
33302 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33304 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33306 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
33307 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33309 * Number of dimensions for this nvm configuration variable.
33310 * This value indicates how many of the indexN values to use.
33311 * A value of 0 means that none of the indexN values are valid.
33312 * A value of 1 requires at index0 is valued, a value of 2
33313 * requires that index0 and index1 are valid, and so forth
33315 uint16_t dimensions;
33316 /* index for the 1st dimensions */
33318 /* index for the 2nd dimensions */
33320 /* index for the 3rd dimensions */
33322 /* index for the 4th dimensions */
33326 * When this bit is set to 1, the factory default value will be returned,
33327 * 0 returns the operational value.
33329 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
33332 } __attribute__((packed));
33334 /* hwrm_nvm_get_variable_output (size:128b/16B) */
33335 struct hwrm_nvm_get_variable_output {
33336 /* The specific error status for the command. */
33337 uint16_t error_code;
33338 /* The HWRM command request type. */
33340 /* The sequence ID from the original command. */
33342 /* The length of the response data in number of bytes. */
33344 /* size of data of the actual variable retrieved in bits */
33347 * option_num is the option number for the data retrieved. It is possible in the
33348 * future that the option number returned would be different than requested. This
33349 * condition could occur if an option is deprecated and a new option id is defined
33350 * with similar characteristics, but has a slightly different definition. This
33351 * also makes it convenient for the caller to identify the variable result with
33352 * the option id from the response.
33354 uint16_t option_num;
33356 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33358 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
33360 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
33361 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
33362 uint8_t unused_0[3];
33364 * This field is used in Output records to indicate that the output
33365 * is completely written to RAM. This field should be read as '1'
33366 * to indicate that the output has been completely written.
33367 * When writing a command completion or response to an internal processor,
33368 * the order of writes has to be such that this field is written last.
33371 } __attribute__((packed));
33373 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
33374 struct hwrm_nvm_get_variable_cmd_err {
33376 * command specific error codes that goes to
33377 * the cmd_err field in Common HWRM Error Response.
33380 /* Unknown error */
33381 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33382 /* variable does not exist */
33383 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33384 /* configuration is corrupted and the variable cannot be saved */
33385 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33386 /* length specified is too small */
33387 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
33388 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
33389 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
33390 uint8_t unused_0[7];
33391 } __attribute__((packed));
33393 /*************************
33394 * hwrm_nvm_set_variable *
33395 *************************/
33398 /* hwrm_nvm_set_variable_input (size:320b/40B) */
33399 struct hwrm_nvm_set_variable_input {
33400 /* The HWRM command request type. */
33403 * The completion ring to send the completion event on. This should
33404 * be the NQ ID returned from the `nq_alloc` HWRM command.
33406 uint16_t cmpl_ring;
33408 * The sequence ID is used by the driver for tracking multiple
33409 * commands. This ID is treated as opaque data by the firmware and
33410 * the value is returned in the `hwrm_resp_hdr` upon completion.
33414 * The target ID of the command:
33415 * * 0x0-0xFFF8 - The function ID
33416 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33417 * * 0xFFFD - Reserved for user-space HWRM interface
33420 uint16_t target_id;
33422 * A physical address pointer pointing to a host buffer that the
33423 * command's response data will be written. This can be either a host
33424 * physical address (HPA) or a guest physical address (GPA) and must
33425 * point to a physically contiguous block of memory.
33427 uint64_t resp_addr;
33429 * This is the host address where
33430 * nvm variable will be copied from
33432 uint64_t src_data_addr;
33433 /* size of data in bits */
33435 /* nvm cfg option number */
33436 uint16_t option_num;
33438 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33440 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33442 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
33443 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33445 * Number of dimensions for this nvm configuration variable.
33446 * This value indicates how many of the indexN values to use.
33447 * A value of 0 means that none of the indexN values are valid.
33448 * A value of 1 requires at index0 is valued, a value of 2
33449 * requires that index0 and index1 are valid, and so forth
33451 uint16_t dimensions;
33452 /* index for the 1st dimensions */
33454 /* index for the 2nd dimensions */
33456 /* index for the 3rd dimensions */
33458 /* index for the 4th dimensions */
33461 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
33462 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
33464 /* encryption method */
33465 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
33467 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
33468 /* No encryption. */
33469 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
33470 (UINT32_C(0x0) << 1)
33471 /* one-way encryption. */
33472 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
33473 (UINT32_C(0x1) << 1)
33474 /* symmetric AES256 encryption. */
33475 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
33476 (UINT32_C(0x2) << 1)
33477 /* SHA1 digest appended to plaintext contents, for authentication */
33478 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
33479 (UINT32_C(0x3) << 1)
33480 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
33481 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
33482 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
33484 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
33485 /* When this bit is 1, update the factory default region */
33486 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
33489 } __attribute__((packed));
33491 /* hwrm_nvm_set_variable_output (size:128b/16B) */
33492 struct hwrm_nvm_set_variable_output {
33493 /* The specific error status for the command. */
33494 uint16_t error_code;
33495 /* The HWRM command request type. */
33497 /* The sequence ID from the original command. */
33499 /* The length of the response data in number of bytes. */
33501 uint8_t unused_0[7];
33503 * This field is used in Output records to indicate that the output
33504 * is completely written to RAM. This field should be read as '1'
33505 * to indicate that the output has been completely written.
33506 * When writing a command completion or response to an internal processor,
33507 * the order of writes has to be such that this field is written last.
33510 } __attribute__((packed));
33512 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
33513 struct hwrm_nvm_set_variable_cmd_err {
33515 * command specific error codes that goes to
33516 * the cmd_err field in Common HWRM Error Response.
33519 /* Unknown error */
33520 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33521 /* variable does not exist */
33522 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33523 /* configuration is corrupted and the variable cannot be saved */
33524 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33525 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
33526 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
33527 uint8_t unused_0[7];
33528 } __attribute__((packed));
33530 /****************************
33531 * hwrm_nvm_validate_option *
33532 ****************************/
33535 /* hwrm_nvm_validate_option_input (size:320b/40B) */
33536 struct hwrm_nvm_validate_option_input {
33537 /* The HWRM command request type. */
33540 * The completion ring to send the completion event on. This should
33541 * be the NQ ID returned from the `nq_alloc` HWRM command.
33543 uint16_t cmpl_ring;
33545 * The sequence ID is used by the driver for tracking multiple
33546 * commands. This ID is treated as opaque data by the firmware and
33547 * the value is returned in the `hwrm_resp_hdr` upon completion.
33551 * The target ID of the command:
33552 * * 0x0-0xFFF8 - The function ID
33553 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33554 * * 0xFFFD - Reserved for user-space HWRM interface
33557 uint16_t target_id;
33559 * A physical address pointer pointing to a host buffer that the
33560 * command's response data will be written. This can be either a host
33561 * physical address (HPA) or a guest physical address (GPA) and must
33562 * point to a physically contiguous block of memory.
33564 uint64_t resp_addr;
33566 * This is the host address where
33567 * nvm variable will be copied from
33569 uint64_t src_data_addr;
33570 /* size of data in bits */
33572 /* nvm cfg option number */
33573 uint16_t option_num;
33575 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
33578 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
33580 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
33581 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
33583 * Number of dimensions for this nvm configuration variable.
33584 * This value indicates how many of the indexN values to use.
33585 * A value of 0 means that none of the indexN values are valid.
33586 * A value of 1 requires at index0 is valued, a value of 2
33587 * requires that index0 and index1 are valid, and so forth
33589 uint16_t dimensions;
33590 /* index for the 1st dimensions */
33592 /* index for the 2nd dimensions */
33594 /* index for the 3rd dimensions */
33596 /* index for the 4th dimensions */
33598 uint8_t unused_0[2];
33599 } __attribute__((packed));
33601 /* hwrm_nvm_validate_option_output (size:128b/16B) */
33602 struct hwrm_nvm_validate_option_output {
33603 /* The specific error status for the command. */
33604 uint16_t error_code;
33605 /* The HWRM command request type. */
33607 /* The sequence ID from the original command. */
33609 /* The length of the response data in number of bytes. */
33612 /* indicates that the value provided for the option is not matching with the saved data. */
33613 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
33614 /* indicates that the value provided for the option is matching the saved data. */
33615 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
33616 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
33617 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
33618 uint8_t unused_0[6];
33620 * This field is used in Output records to indicate that the output
33621 * is completely written to RAM. This field should be read as '1'
33622 * to indicate that the output has been completely written.
33623 * When writing a command completion or response to an internal processor,
33624 * the order of writes has to be such that this field is written last.
33627 } __attribute__((packed));
33629 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
33630 struct hwrm_nvm_validate_option_cmd_err {
33632 * command specific error codes that goes to
33633 * the cmd_err field in Common HWRM Error Response.
33636 /* Unknown error */
33637 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33638 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
33639 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
33640 uint8_t unused_0[7];
33641 } __attribute__((packed));
33645 ******************/
33648 /* hwrm_fw_reset_input (size:192b/24B) */
33649 struct hwrm_fw_reset_input {
33650 /* The HWRM command request type. */
33653 * The completion ring to send the completion event on. This should
33654 * be the NQ ID returned from the `nq_alloc` HWRM command.
33656 uint16_t cmpl_ring;
33658 * The sequence ID is used by the driver for tracking multiple
33659 * commands. This ID is treated as opaque data by the firmware and
33660 * the value is returned in the `hwrm_resp_hdr` upon completion.
33664 * The target ID of the command:
33665 * * 0x0-0xFFF8 - The function ID
33666 * * 0xFFF8-0xFFFE - Reserved for internal processors
33669 uint16_t target_id;
33671 * A physical address pointer pointing to a host buffer that the
33672 * command's response data will be written. This can be either a host
33673 * physical address (HPA) or a guest physical address (GPA) and must
33674 * point to a physically contiguous block of memory.
33676 uint64_t resp_addr;
33677 /* Type of embedded processor. */
33678 uint8_t embedded_proc_type;
33679 /* Boot Processor */
33680 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
33682 /* Management Processor */
33683 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
33685 /* Network control processor */
33686 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
33688 /* RoCE control processor */
33689 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
33692 * Host (in multi-host environment): This is only valid if requester is IPC.
33693 * Reinit host hardware resources and PCIe.
33695 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
33697 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
33698 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
33700 /* Reset all blocks of the chip (including all processors) */
33701 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
33704 * Host (in multi-host environment): This is only valid if requester is IPC.
33705 * Reinit host hardware resources.
33707 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
33709 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
33710 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
33711 /* Type of self reset. */
33712 uint8_t selfrst_status;
33713 /* No Self Reset */
33714 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
33716 /* Self Reset as soon as possible to do so safely */
33717 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
33719 /* Self Reset on PCIe Reset */
33720 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
33722 /* Self Reset immediately after notification to all clients. */
33723 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
33725 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
33726 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
33728 * Indicate which host is being reset. 0 means first host.
33729 * Only valid when embedded_proc_type is host in multihost
33735 * When this bit is '1', then the core firmware initiates
33736 * the reset only after graceful shut down of all registered instances.
33737 * If not, the device will continue with the existing firmware.
33739 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
33740 uint8_t unused_0[4];
33741 } __attribute__((packed));
33743 /* hwrm_fw_reset_output (size:128b/16B) */
33744 struct hwrm_fw_reset_output {
33745 /* The specific error status for the command. */
33746 uint16_t error_code;
33747 /* The HWRM command request type. */
33749 /* The sequence ID from the original command. */
33751 /* The length of the response data in number of bytes. */
33753 /* Type of self reset. */
33754 uint8_t selfrst_status;
33755 /* No Self Reset */
33756 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
33758 /* Self Reset as soon as possible to do so safely */
33759 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
33761 /* Self Reset on PCIe Reset */
33762 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
33764 /* Self Reset immediately after notification to all clients. */
33765 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
33767 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
33768 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
33769 uint8_t unused_0[6];
33771 * This field is used in Output records to indicate that the output
33772 * is completely written to RAM. This field should be read as '1'
33773 * to indicate that the output has been completely written.
33774 * When writing a command completion or response to an internal processor,
33775 * the order of writes has to be such that this field is written last.
33778 } __attribute__((packed));
33780 /**********************
33781 * hwrm_port_ts_query *
33782 ***********************/
33785 /* hwrm_port_ts_query_input (size:192b/24B) */
33786 struct hwrm_port_ts_query_input {
33787 /* The HWRM command request type. */
33790 * The completion ring to send the completion event on. This should
33791 * be the NQ ID returned from the `nq_alloc` HWRM command.
33793 uint16_t cmpl_ring;
33795 * The sequence ID is used by the driver for tracking multiple
33796 * commands. This ID is treated as opaque data by the firmware and
33797 * the value is returned in the `hwrm_resp_hdr` upon completion.
33801 * The target ID of the command:
33802 * * 0x0-0xFFF8 - The function ID
33803 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33804 * * 0xFFFD - Reserved for user-space HWRM interface
33807 uint16_t target_id;
33809 * A physical address pointer pointing to a host buffer that the
33810 * command's response data will be written. This can be either a host
33811 * physical address (HPA) or a guest physical address (GPA) and must
33812 * point to a physically contiguous block of memory.
33814 uint64_t resp_addr;
33817 * Enumeration denoting the RX, TX type of the resource.
33818 * This enumeration is used for resources that are similar for both
33819 * TX and RX paths of the chip.
33821 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
33823 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
33825 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
33826 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
33827 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
33829 * If set, the response includes the current value of the free
33832 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
33833 /* Port ID of port that is being queried. */
33835 uint8_t unused_0[2];
33836 } __attribute__((packed));
33838 /* hwrm_port_ts_query_output (size:192b/24B) */
33839 struct hwrm_port_ts_query_output {
33840 /* The specific error status for the command. */
33841 uint16_t error_code;
33842 /* The HWRM command request type. */
33844 /* The sequence ID from the original command. */
33846 /* The length of the response data in number of bytes. */
33849 * Timestamp value of PTP message captured, or current value of
33850 * free running timer.
33852 uint32_t ptp_msg_ts[2];
33853 /* Sequence ID of the PTP message captured. */
33854 uint16_t ptp_msg_seqid;
33855 uint8_t unused_0[5];
33857 * This field is used in Output records to indicate that the output
33858 * is completely written to RAM. This field should be read as '1'
33859 * to indicate that the output has been completely written.
33860 * When writing a command completion or response to an internal processor,
33861 * the order of writes has to be such that this field is written last.
33864 } __attribute__((packed));
33866 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */