1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* RoCE slow path command to query CC Gen1 support. */
71 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
72 /* RoCE slow path command to modify CC Gen1 support. */
73 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
74 /* Engine CKV - The device's serial number. */
75 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
76 /* Engine CKV - Per-function random nonce data. */
77 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
78 /* Engine CKV - Initialization vector. */
79 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
80 /* Engine CKV - Authentication tag. */
81 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
82 /* Engine CKV - The encrypted data. */
83 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
84 /* Engine CKV - Supported algorithms. */
85 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
86 /* Engine CKV - The EC curve name and ECC public key information. */
87 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
88 /* Engine CKV - The ECDSA signature. */
89 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
90 #define TLV_TYPE_LAST \
91 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
94 /* tlv (size:64b/8B) */
97 * The command discriminator is used to differentiate between various
98 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
99 * command messages as well as newer TLV encapsulated HWRM commands.
101 * For TLV encapsulated messages this field must be 0x8000.
107 * Indicates the presence of additional TLV encapsulated data
110 #define TLV_FLAGS_MORE UINT32_C(0x1)
111 /* Last TLV in a sequence of TLVs. */
112 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
113 /* More TLVs follow this TLV. */
114 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
116 * When an HWRM receiver detects a TLV type that it does not
117 * support with the TLV required flag set, the receiver must
118 * reject the HWRM message with an error code indicating an
119 * unsupported TLV type.
121 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
123 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
125 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
126 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
128 * This field defines the TLV type value which is divided into
129 * two ranges to differentiate between global and local TLV types.
130 * Global TLV types must be unique across all defined TLV types.
131 * Local TLV types are valid only for extensions to a given
132 * HWRM message and may be repeated across different HWRM message
133 * types. There is a direct correlation of each HWRM message type
134 * to a single global TLV type value.
136 * Global TLV range: `0 - (63k-1)`
138 * Local TLV range: `63k - (64k-1)`
142 * Length of the message data encapsulated by this TLV in bytes.
143 * This length does not include the size of the TLV header itself
144 * and it must be an integer multiple of 8B.
147 } __attribute__((packed));
150 /* input (size:128b/16B) */
153 * This value indicates what type of request this is. The format
154 * for the rest of the command is determined by this field.
158 * This value indicates the what completion ring the request will
159 * be optionally completed on. If the value is -1, then no
160 * CR completion will be generated. Any other value must be a
161 * valid CR ring_id value for this function.
164 /* This value indicates the command sequence number. */
167 * Target ID of this command.
169 * 0x0 - 0xFFF8 - Used for function ids
170 * 0xFFF8 - 0xFFFE - Reserved for internal processors
175 * This is the host address where the response will be written
176 * when the request is complete. This area must be 16B aligned
177 * and must be cleared to zero before the request is made.
180 } __attribute__((packed));
183 /* output (size:64b/8B) */
186 * Pass/Fail or error type
188 * Note: receiver to verify the in parameters, and fail the call
189 * with an error when appropriate
192 /* This field returns the type of original request. */
194 /* This field provides original sequence number of the command. */
197 * This field is the length of the response in bytes. The
198 * last byte of the response is a valid flag that will read
199 * as '1' when the command has been completely written to
203 } __attribute__((packed));
205 /* Short Command Structure */
206 /* hwrm_short_input (size:128b/16B) */
207 struct hwrm_short_input {
209 * This field indicates the type of request in the request buffer.
210 * The format for the rest of the command (request) is determined
215 * This field indicates a signature that is used to identify short
216 * form of the command listed here. This field shall be set to
220 /* Signature indicating this is a short form of HWRM command */
221 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
222 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
223 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
224 /* Reserved for future use. */
226 /* This value indicates the length of the request. */
229 * This is the host address where the request was written.
230 * This area must be 16B aligned.
233 } __attribute__((packed));
237 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
238 * # So only structure definition is provided here.
240 /* cmd_nums (size:64b/8B) */
243 * This version of the specification defines the commands listed in
244 * the table below. The following are general implementation
245 * requirements for these commands:
247 * # All commands listed below that are marked neither
248 * reserved nor experimental shall be implemented by the HWRM.
249 * # A HWRM client compliant to this specification should not use
250 * commands outside of the list below.
251 * # A HWRM client compliant to this specification should not use
252 * command numbers marked reserved below.
253 * # A command marked experimental below may not be implemented
255 * # A command marked experimental may change in the
256 * future version of the HWRM specification.
257 * # A command not listed below may be implemented by the HWRM.
258 * The behavior of commands that are not listed below is outside
259 * the scope of this specification.
262 #define HWRM_VER_GET UINT32_C(0x0)
263 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
264 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
265 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
266 /* Reserved for future use. */
267 #define HWRM_RESERVED1 UINT32_C(0x10)
268 #define HWRM_FUNC_RESET UINT32_C(0x11)
269 #define HWRM_FUNC_GETFID UINT32_C(0x12)
270 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
271 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
272 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
273 #define HWRM_FUNC_QCFG UINT32_C(0x16)
274 #define HWRM_FUNC_CFG UINT32_C(0x17)
275 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
276 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
277 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
278 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
279 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
280 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
281 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
282 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
283 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
284 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
286 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
287 #define HWRM_PORT_QSTATS UINT32_C(0x23)
288 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
290 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
292 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
293 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
294 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
296 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
297 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
298 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
299 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
300 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
301 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
302 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
303 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
304 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
305 #define HWRM_QUEUE_CFG UINT32_C(0x32)
306 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
307 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
308 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
309 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
310 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
311 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
312 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
313 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
315 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
317 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
319 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
320 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
321 #define HWRM_VNIC_FREE UINT32_C(0x41)
322 #define HWRM_VNIC_CFG UINT32_C(0x42)
323 #define HWRM_VNIC_QCFG UINT32_C(0x43)
324 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
326 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
327 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
328 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
329 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
330 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
331 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
332 #define HWRM_RING_ALLOC UINT32_C(0x50)
333 #define HWRM_RING_FREE UINT32_C(0x51)
334 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
335 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
336 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
337 #define HWRM_RING_RESET UINT32_C(0x5e)
338 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
339 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
340 /* Reserved for future use. */
341 #define HWRM_RESERVED5 UINT32_C(0x64)
342 /* Reserved for future use. */
343 #define HWRM_RESERVED6 UINT32_C(0x65)
344 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
345 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
346 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
347 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
348 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
349 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
350 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
351 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
352 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
354 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
356 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
357 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
358 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
359 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
361 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
363 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
365 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
366 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
367 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
368 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
369 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
370 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
371 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
372 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
373 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
374 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
375 #define HWRM_FW_RESET UINT32_C(0xc0)
376 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
377 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
378 #define HWRM_FW_SYNC UINT32_C(0xc3)
380 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
382 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
384 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
386 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
388 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
389 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
390 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
391 #define HWRM_FWD_RESP UINT32_C(0xd2)
392 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
393 #define HWRM_OEM_CMD UINT32_C(0xd4)
394 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
395 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
396 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
397 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
398 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
400 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
402 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
404 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
406 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
408 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
410 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
412 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
414 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
416 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
418 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
420 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
422 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
424 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
426 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
428 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
430 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
432 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
433 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
434 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
435 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
437 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
439 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
441 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
443 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
444 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
445 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
447 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
449 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
451 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
453 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
454 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
455 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
456 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
457 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
458 /* Engine CKV - Add a new CKEK used to encrypt keys. */
459 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
460 /* Engine CKV - Delete a previously added CKEK. */
461 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
462 /* Engine CKV - Add a new key to the key vault. */
463 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
464 /* Engine CKV - Delete a key from the key vault. */
465 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
466 /* Engine CKV - Delete all keys from the key vault. */
467 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
468 /* Engine CKV - Get random data. */
469 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
470 /* Engine CKV - Generate and encrypt a new AES key. */
471 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
472 /* Engine - Query the available queue groups configuration. */
473 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
474 /* Engine - Query the queue groups assigned to a function. */
475 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
476 /* Engine - Query the available queue group meter profile configuration. */
477 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
478 /* Engine - Query the configuration of a queue group meter profile. */
479 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
480 /* Engine - Allocate a queue group meter profile. */
481 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
482 /* Engine - Free a queue group meter profile. */
483 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
484 /* Engine - Query the meters assigned to a queue group. */
485 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
486 /* Engine - Bind a queue group meter profile to a queue group. */
487 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
488 /* Engine - Unbind a queue group meter profile from a queue group. */
489 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
490 /* Engine - Bind a queue group to a function. */
491 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
492 /* Engine - Query the scheduling group configuration. */
493 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
494 /* Engine - Query the queue groups assigned to a scheduling group. */
495 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
496 /* Engine - Query the configuration of a scheduling group's meter profiles. */
497 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
498 /* Engine - Configure a scheduling group's meter profiles. */
499 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
500 /* Engine - Bind a queue group to a scheduling group. */
501 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
502 /* Engine - Unbind a queue group from its scheduling group. */
503 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
504 /* Engine - Query the Engine configuration. */
505 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
506 /* Engine - Configure the statistics accumulator for an Engine. */
507 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
508 /* Engine - Clear the statistics accumulator for an Engine. */
509 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
510 /* Engine - Query the statistics accumulator for an Engine. */
511 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
512 /* Engine - Allocate an Engine RQ. */
513 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
514 /* Engine - Free an Engine RQ. */
515 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
516 /* Engine - Allocate an Engine CQ. */
517 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
518 /* Engine - Free an Engine CQ. */
519 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
520 /* Engine - Allocate an NQ. */
521 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
522 /* Engine - Free an NQ. */
523 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
524 /* Engine - Set the on-die RQE credit update location. */
525 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
527 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
529 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
531 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
533 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
535 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
536 /* Configures the BW of any VF */
537 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
538 /* Queries the BW of any VF */
539 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
541 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
543 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
545 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
547 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
549 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
551 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
553 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
555 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
557 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
558 #define HWRM_DBG_DUMP UINT32_C(0xff14)
560 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
562 #define HWRM_DBG_CFG UINT32_C(0xff16)
564 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
566 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
568 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
570 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
572 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
574 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
576 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
577 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
578 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
579 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
580 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
581 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
582 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
583 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
584 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
585 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
586 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
587 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
588 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
589 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
590 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
591 #define HWRM_NVM_READ UINT32_C(0xfffd)
592 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
593 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
594 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
595 uint16_t unused_0[3];
596 } __attribute__((packed));
599 /* ret_codes (size:64b/8B) */
602 /* Request was successfully executed by the HWRM. */
603 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
604 /* The HWRM failed to execute the request. */
605 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
607 * The request contains invalid argument(s) or input
610 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
612 * The requester is not allowed to access the requested
613 * resource. This error code shall be provided in a
614 * response to a request to query or modify an existing
615 * resource that is not accessible by the requester.
617 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
619 * The HWRM is unable to allocate the requested resource.
620 * This code only applies to requests for HWRM resource
623 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
625 * Invalid combination of flags is specified in the
628 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
630 * Invalid combination of enables fields is specified in
633 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
635 * Request contains a required TLV that is not supported by
636 * the installed version of firmware.
638 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
640 * No firmware buffer available to accept the request. Driver
641 * should retry the request.
643 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
645 * This error code is only reported by firmware when some
646 * sub-option of a supported HWRM command is unsupported.
648 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
650 * This error code is only reported by firmware when the specific
651 * request is not able to process when the HOT reset in progress.
653 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
655 * This error code is only reported by firmware when the registered
656 * driver instances are not capable of hot reset.
658 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
660 * Generic HWRM execution error that represents an
663 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
665 * This value indicates that the HWRM response is in TLV format and
666 * should be interpreted as one or more TLVs starting with the
667 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
668 * by itself, just an indicatation that the response should be parsed
669 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
671 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
673 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
674 /* Unsupported or invalid command */
675 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
676 #define HWRM_ERR_CODE_LAST \
677 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
678 uint16_t unused_0[3];
679 } __attribute__((packed));
682 /* hwrm_err_output (size:128b/16B) */
683 struct hwrm_err_output {
685 * Pass/Fail or error type
687 * Note: receiver to verify the in parameters, and fail the call
688 * with an error when appropriate
691 /* This field returns the type of original request. */
693 /* This field provides original sequence number of the command. */
696 * This field is the length of the response in bytes. The
697 * last byte of the response is a valid flag that will read
698 * as '1' when the command has been completely written to
702 /* debug info for this error response. */
704 /* debug info for this error response. */
707 * In the case of an error response, command specific error
708 * code is returned in this field.
712 * This field is used in Output records to indicate that the output
713 * is completely written to RAM. This field should be read as '1'
714 * to indicate that the output has been completely written.
715 * When writing a command completion or response to an internal processor,
716 * the order of writes has to be such that this field is written last.
719 } __attribute__((packed));
721 * Following is the signature for HWRM message field that indicates not
722 * applicable (All F's). Need to cast it the size of the field if needed.
724 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
725 /* hwrm_func_buf_rgtr */
726 #define HWRM_MAX_REQ_LEN 128
727 /* hwrm_selftest_qlist */
728 #define HWRM_MAX_RESP_LEN 280
729 /* 7 bit indirection table index. */
730 #define HW_HASH_INDEX_SIZE 0x80
731 #define HW_HASH_KEY_SIZE 40
732 /* valid key for HWRM response */
733 #define HWRM_RESP_VALID_KEY 1
734 #define HWRM_VERSION_MAJOR 1
735 #define HWRM_VERSION_MINOR 10
736 #define HWRM_VERSION_UPDATE 0
737 /* non-zero means beta version */
738 #define HWRM_VERSION_RSVD 19
739 #define HWRM_VERSION_STR "1.10.0.19"
746 /* hwrm_ver_get_input (size:192b/24B) */
747 struct hwrm_ver_get_input {
748 /* The HWRM command request type. */
751 * The completion ring to send the completion event on. This should
752 * be the NQ ID returned from the `nq_alloc` HWRM command.
756 * The sequence ID is used by the driver for tracking multiple
757 * commands. This ID is treated as opaque data by the firmware and
758 * the value is returned in the `hwrm_resp_hdr` upon completion.
762 * The target ID of the command:
763 * * 0x0-0xFFF8 - The function ID
764 * * 0xFFF8-0xFFFE - Reserved for internal processors
769 * A physical address pointer pointing to a host buffer that the
770 * command's response data will be written. This can be either a host
771 * physical address (HPA) or a guest physical address (GPA) and must
772 * point to a physically contiguous block of memory.
776 * This field represents the major version of HWRM interface
777 * specification supported by the driver HWRM implementation.
778 * The interface major version is intended to change only when
779 * non backward compatible changes are made to the HWRM
780 * interface specification.
782 uint8_t hwrm_intf_maj;
784 * This field represents the minor version of HWRM interface
785 * specification supported by the driver HWRM implementation.
786 * A change in interface minor version is used to reflect
787 * significant backward compatible modification to HWRM
788 * interface specification.
789 * This can be due to addition or removal of functionality.
790 * HWRM interface specifications with the same major version
791 * but different minor versions are compatible.
793 uint8_t hwrm_intf_min;
795 * This field represents the update version of HWRM interface
796 * specification supported by the driver HWRM implementation.
797 * The interface update version is used to reflect minor
798 * changes or bug fixes to a released HWRM interface
801 uint8_t hwrm_intf_upd;
803 } __attribute__((packed));
805 /* hwrm_ver_get_output (size:1408b/176B) */
806 struct hwrm_ver_get_output {
807 /* The specific error status for the command. */
809 /* The HWRM command request type. */
811 /* The sequence ID from the original command. */
813 /* The length of the response data in number of bytes. */
816 * This field represents the major version of HWRM interface
817 * specification supported by the HWRM implementation.
818 * The interface major version is intended to change only when
819 * non backward compatible changes are made to the HWRM
820 * interface specification.
821 * A HWRM implementation that is compliant with this
822 * specification shall provide value of 1 in this field.
824 uint8_t hwrm_intf_maj_8b;
826 * This field represents the minor version of HWRM interface
827 * specification supported by the HWRM implementation.
828 * A change in interface minor version is used to reflect
829 * significant backward compatible modification to HWRM
830 * interface specification.
831 * This can be due to addition or removal of functionality.
832 * HWRM interface specifications with the same major version
833 * but different minor versions are compatible.
834 * A HWRM implementation that is compliant with this
835 * specification shall provide value of 2 in this field.
837 uint8_t hwrm_intf_min_8b;
839 * This field represents the update version of HWRM interface
840 * specification supported by the HWRM implementation.
841 * The interface update version is used to reflect minor
842 * changes or bug fixes to a released HWRM interface
844 * A HWRM implementation that is compliant with this
845 * specification shall provide value of 2 in this field.
847 uint8_t hwrm_intf_upd_8b;
848 uint8_t hwrm_intf_rsvd_8b;
850 * This field represents the major version of HWRM firmware.
851 * A change in firmware major version represents a major
854 uint8_t hwrm_fw_maj_8b;
856 * This field represents the minor version of HWRM firmware.
857 * A change in firmware minor version represents significant
858 * firmware functionality changes.
860 uint8_t hwrm_fw_min_8b;
862 * This field represents the build version of HWRM firmware.
863 * A change in firmware build version represents bug fixes
864 * to a released firmware.
866 uint8_t hwrm_fw_bld_8b;
868 * This field is a reserved field. This field can be used to
869 * represent firmware branches or customer specific releases
870 * tied to a specific (major,minor,update) version of the
873 uint8_t hwrm_fw_rsvd_8b;
875 * This field represents the major version of mgmt firmware.
876 * A change in major version represents a major release.
878 uint8_t mgmt_fw_maj_8b;
880 * This field represents the minor version of mgmt firmware.
881 * A change in minor version represents significant
882 * functionality changes.
884 uint8_t mgmt_fw_min_8b;
886 * This field represents the build version of mgmt firmware.
887 * A change in update version represents bug fixes.
889 uint8_t mgmt_fw_bld_8b;
891 * This field is a reserved field. This field can be used to
892 * represent firmware branches or customer specific releases
893 * tied to a specific (major,minor,update) version
895 uint8_t mgmt_fw_rsvd_8b;
897 * This field represents the major version of network
899 * A change in major version represents a major release.
901 uint8_t netctrl_fw_maj_8b;
903 * This field represents the minor version of network
905 * A change in minor version represents significant
906 * functionality changes.
908 uint8_t netctrl_fw_min_8b;
910 * This field represents the build version of network
912 * A change in update version represents bug fixes.
914 uint8_t netctrl_fw_bld_8b;
916 * This field is a reserved field. This field can be used to
917 * represent firmware branches or customer specific releases
918 * tied to a specific (major,minor,update) version
920 uint8_t netctrl_fw_rsvd_8b;
922 * This field is used to indicate device's capabilities and
925 uint32_t dev_caps_cfg;
927 * If set to 1, then secure firmware update behavior
929 * If set to 0, then secure firmware update behavior is
932 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
935 * If set to 1, then firmware based DCBX agent is supported.
936 * If set to 0, then firmware based DCBX agent capability
937 * is not supported on this device.
939 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
942 * If set to 1, then HWRM short command format is supported.
943 * If set to 0, then HWRM short command format is not supported.
945 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
948 * If set to 1, then HWRM short command format is required.
949 * If set to 0, then HWRM short command format is not required.
951 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
954 * If set to 1, then the KONG host mailbox channel is supported.
955 * If set to 0, then the KONG host mailbox channel is not supported.
956 * By default, this flag should be 0 for older version of core firmware.
958 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
961 * If set to 1, then the 64bit flow handle is supported in addition to the
962 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
963 * supported. By default, this flag should be 0 for older version of core firmware.
965 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
968 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
969 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
970 * If set to 0, then filter types not supported.
971 * By default, this flag should be 0 for older version of core firmware.
973 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
976 * If set to 1, firmware is capable to support virtio vSwitch offload model.
977 * If set to 0, firmware can't supported virtio vSwitch offload model.
978 * By default, this flag should be 0 for older version of core firmware.
980 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
983 * If set to 1, firmware is capable to support trusted VF.
984 * If set to 0, firmware is not capable to support trusted VF.
985 * By default, this flag should be 0 for older version of core firmware.
987 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
990 * If set to 1, firmware is capable to support flow aging.
991 * If set to 0, firmware is not capable to support flow aging.
992 * By default, this flag should be 0 for older version of core firmware.
994 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
997 * This field represents the major version of RoCE firmware.
998 * A change in major version represents a major release.
1000 uint8_t roce_fw_maj_8b;
1002 * This field represents the minor version of RoCE firmware.
1003 * A change in minor version represents significant
1004 * functionality changes.
1006 uint8_t roce_fw_min_8b;
1008 * This field represents the build version of RoCE firmware.
1009 * A change in update version represents bug fixes.
1011 uint8_t roce_fw_bld_8b;
1013 * This field is a reserved field. This field can be used to
1014 * represent firmware branches or customer specific releases
1015 * tied to a specific (major,minor,update) version
1017 uint8_t roce_fw_rsvd_8b;
1019 * This field represents the name of HWRM FW (ASCII chars
1020 * with NULL at the end).
1022 char hwrm_fw_name[16];
1024 * This field represents the name of mgmt FW (ASCII chars
1025 * with NULL at the end).
1027 char mgmt_fw_name[16];
1029 * This field represents the name of network control
1030 * firmware (ASCII chars with NULL at the end).
1032 char netctrl_fw_name[16];
1034 * This field is reserved for future use.
1035 * The responder should set it to 0.
1036 * The requester should ignore this field.
1038 uint8_t reserved2[16];
1040 * This field represents the name of RoCE FW (ASCII chars
1041 * with NULL at the end).
1043 char roce_fw_name[16];
1044 /* This field returns the chip number. */
1046 /* This field returns the revision of chip. */
1048 /* This field returns the chip metal number. */
1050 /* This field returns the bond id of the chip. */
1051 uint8_t chip_bond_id;
1052 /* This value indicates the type of platform used for chip implementation. */
1053 uint8_t chip_platform_type;
1055 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1056 /* FPGA platform of the chip. */
1057 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1058 /* Palladium platform of the chip. */
1059 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1060 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1061 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1063 * This field returns the maximum value of request window that
1064 * is supported by the HWRM. The request window is mapped
1065 * into device address space using MMIO.
1067 uint16_t max_req_win_len;
1069 * This field returns the maximum value of response buffer in
1072 uint16_t max_resp_len;
1074 * This field returns the default request timeout value in
1077 uint16_t def_req_timeout;
1079 * This field will indicate if any subsystems is not fully
1084 * If set to 1, device is not ready.
1085 * If set to 0, device is ready to accept all HWRM commands.
1087 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1089 * If set to 1, external version present.
1090 * If set to 0, external version not present.
1092 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1093 uint8_t unused_0[2];
1095 * For backward compatibility this field must be set to 1.
1096 * Older drivers might look for this field to be 1 before
1097 * processing the message.
1101 * This field represents the major version of HWRM interface
1102 * specification supported by the HWRM implementation.
1103 * The interface major version is intended to change only when
1104 * non backward compatible changes are made to the HWRM
1105 * interface specification. A HWRM implementation that is
1106 * compliant with this specification shall provide value of 1
1109 uint16_t hwrm_intf_major;
1111 * This field represents the minor version of HWRM interface
1112 * specification supported by the HWRM implementation.
1113 * A change in interface minor version is used to reflect
1114 * significant backward compatible modification to HWRM
1115 * interface specification. This can be due to addition or
1116 * removal of functionality. HWRM interface specifications
1117 * with the same major version but different minor versions are
1118 * compatible. A HWRM implementation that is compliant with
1119 * this specification shall provide value of 2 in this field.
1121 uint16_t hwrm_intf_minor;
1123 * This field represents the update version of HWRM interface
1124 * specification supported by the HWRM implementation. The
1125 * interface update version is used to reflect minor changes or
1126 * bug fixes to a released HWRM interface specification.
1127 * A HWRM implementation that is compliant with this
1128 * specification shall provide value of 2 in this field.
1130 uint16_t hwrm_intf_build;
1132 * This field represents the patch version of HWRM interface
1133 * specification supported by the HWRM implementation.
1135 uint16_t hwrm_intf_patch;
1137 * This field represents the major version of HWRM firmware.
1138 * A change in firmware major version represents a major
1141 uint16_t hwrm_fw_major;
1143 * This field represents the minor version of HWRM firmware.
1144 * A change in firmware minor version represents significant
1145 * firmware functionality changes.
1147 uint16_t hwrm_fw_minor;
1149 * This field represents the build version of HWRM firmware.
1150 * A change in firmware build version represents bug fixes to
1151 * a released firmware.
1153 uint16_t hwrm_fw_build;
1155 * This field is a reserved field.
1156 * This field can be used to represent firmware branches or customer
1157 * specific releases tied to a specific (major,minor,update) version
1158 * of the HWRM firmware.
1160 uint16_t hwrm_fw_patch;
1162 * This field represents the major version of mgmt firmware.
1163 * A change in major version represents a major release.
1165 uint16_t mgmt_fw_major;
1167 * This field represents the minor version of HWRM firmware.
1168 * A change in firmware minor version represents significant
1169 * firmware functionality changes.
1171 uint16_t mgmt_fw_minor;
1173 * This field represents the build version of mgmt firmware.
1174 * A change in update version represents bug fixes.
1176 uint16_t mgmt_fw_build;
1178 * This field is a reserved field. This field can be used to
1179 * represent firmware branches or customer specific releases
1180 * tied to a specific (major,minor,update) version.
1182 uint16_t mgmt_fw_patch;
1184 * This field represents the major version of network control
1185 * firmware. A change in major version represents
1188 uint16_t netctrl_fw_major;
1190 * This field represents the minor version of network control
1191 * firmware. A change in minor version represents significant
1192 * functionality changes.
1194 uint16_t netctrl_fw_minor;
1196 * This field represents the build version of network control
1197 * firmware. A change in update version represents bug fixes.
1199 uint16_t netctrl_fw_build;
1201 * This field is a reserved field. This field can be used to
1202 * represent firmware branches or customer specific releases
1203 * tied to a specific (major,minor,update) version
1205 uint16_t netctrl_fw_patch;
1207 * This field represents the major version of RoCE firmware.
1208 * A change in major version represents a major release.
1210 uint16_t roce_fw_major;
1212 * This field represents the minor version of RoCE firmware.
1213 * A change in minor version represents significant
1214 * functionality changes.
1216 uint16_t roce_fw_minor;
1218 * This field represents the build version of RoCE firmware.
1219 * A change in update version represents bug fixes.
1221 uint16_t roce_fw_build;
1223 * This field is a reserved field. This field can be used to
1224 * represent firmware branches or customer specific releases
1225 * tied to a specific (major,minor,update) version
1227 uint16_t roce_fw_patch;
1229 * This field returns the maximum extended request length acceptable
1230 * by the device which allows requests greater than mailbox size when
1231 * used with the short cmd request format.
1233 uint16_t max_ext_req_len;
1234 uint8_t unused_1[5];
1236 * This field is used in Output records to indicate that the output
1237 * is completely written to RAM. This field should be read as '1'
1238 * to indicate that the output has been completely written.
1239 * When writing a command completion or response to an internal processor,
1240 * the order of writes has to be such that this field is written last.
1243 } __attribute__((packed));
1245 /* bd_base (size:64b/8B) */
1248 /* This value identifies the type of buffer descriptor. */
1249 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1250 #define BD_BASE_TYPE_SFT 0
1252 * Indicates that this BD is 16B long and is used for
1253 * normal L2 packet transmission.
1255 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1257 * Indicates that this BD is 1BB long and is an empty
1258 * TX BD. Not valid for use by the driver.
1260 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1262 * Indicates that this BD is 16B long and is an RX Producer
1263 * (ie. empty) buffer descriptor.
1265 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1267 * Indicates that this BD is 16B long and is an RX
1268 * Producer Buffer BD.
1270 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1272 * Indicates that this BD is 16B long and is an
1273 * RX Producer Assembly Buffer Descriptor.
1275 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1277 * Indicates that this BD is 32B long and is used for
1278 * normal L2 packet transmission.
1280 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1282 * Indicates that this BD is 32B long and is used for
1283 * L2 packet transmission for small packets that require
1286 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1287 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1288 uint8_t unused_1[7];
1289 } __attribute__((packed));
1291 /* tx_bd_short (size:128b/16B) */
1292 struct tx_bd_short {
1294 * All bits in this field must be valid on the first BD of a packet.
1295 * Only the packet_end bit must be valid for the remaining BDs
1298 uint16_t flags_type;
1299 /* This value identifies the type of buffer descriptor. */
1300 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1301 #define TX_BD_SHORT_TYPE_SFT 0
1303 * Indicates that this BD is 16B long and is used for
1304 * normal L2 packet transmission.
1306 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1307 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1309 * All bits in this field must be valid on the first BD of a packet.
1310 * Only the packet_end bit must be valid for the remaining BDs
1313 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1314 #define TX_BD_SHORT_FLAGS_SFT 6
1316 * If set to 1, the packet ends with the data in the buffer
1317 * pointed to by this descriptor. This flag must be
1318 * valid on every BD.
1320 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1322 * If set to 1, the device will not generate a completion for
1323 * this transmit packet unless there is an error in it's
1326 * is set to 0, then the packet will be completed normally.
1328 * This bit must be valid only on the first BD of a packet.
1330 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1332 * This value indicates how many 16B BD locations are consumed
1333 * in the ring by this packet.
1334 * A value of 1 indicates that this BD is the only BD (and that
1335 * the it is a short BD). A value
1336 * of 3 indicates either 3 short BDs or 1 long BD and one short
1337 * BD in the packet. A value of 0 indicates
1338 * that there are 32 BD locations in the packet (the maximum).
1340 * This field is valid only on the first BD of a packet.
1342 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1343 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1345 * This value is a hint for the length of the entire packet.
1346 * It is used by the chip to optimize internal processing.
1348 * The packet will be dropped if the hint is too short.
1350 * This field is valid only on the first BD of a packet.
1352 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1353 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1354 /* indicates packet length < 512B */
1355 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1356 /* indicates 512 <= packet length < 1KB */
1357 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1358 /* indicates 1KB <= packet length < 2KB */
1359 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1360 /* indicates packet length >= 2KB */
1361 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1362 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1363 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1365 * If set to 1, the device immediately updates the Send Consumer
1366 * Index after the buffer associated with this descriptor has
1367 * been transferred via DMA to NIC memory from host memory. An
1368 * interrupt may or may not be generated according to the state
1369 * of the interrupt avoidance mechanisms. If this bit
1370 * is set to 0, then the Consumer Index is only updated as soon
1371 * as one of the host interrupt coalescing conditions has been met.
1373 * This bit must be valid on the first BD of a packet.
1375 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1377 * This is the length of the host physical buffer this BD describes
1380 * This field must be valid on all BDs of a packet.
1384 * The opaque data field is pass through to the completion and can be
1385 * used for any data that the driver wants to associate with the
1388 * This field must be valid on the first BD of a packet.
1392 * This is the host physical address for the portion of the packet
1393 * described by this TX BD.
1395 * This value must be valid on all BDs of a packet.
1398 } __attribute__((packed));
1400 /* tx_bd_long (size:128b/16B) */
1402 /* This value identifies the type of buffer descriptor. */
1403 uint16_t flags_type;
1405 * This value indicates the type of buffer descriptor.
1408 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1409 #define TX_BD_LONG_TYPE_SFT 0
1411 * Indicates that this BD is 32B long and is used for
1412 * normal L2 packet transmission.
1414 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1415 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1417 * All bits in this field must be valid on the first BD of a packet.
1418 * Only the packet_end bit must be valid for the remaining BDs
1421 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1422 #define TX_BD_LONG_FLAGS_SFT 6
1424 * If set to 1, the packet ends with the data in the buffer
1425 * pointed to by this descriptor. This flag must be
1426 * valid on every BD.
1428 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1430 * If set to 1, the device will not generate a completion for
1431 * this transmit packet unless there is an error in it's
1434 * is set to 0, then the packet will be completed normally.
1436 * This bit must be valid only on the first BD of a packet.
1438 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1440 * This value indicates how many 16B BD locations are consumed
1441 * in the ring by this packet.
1442 * A value of 1 indicates that this BD is the only BD (and that
1443 * the it is a short BD). A value
1444 * of 3 indicates either 3 short BDs or 1 long BD and one short
1445 * BD in the packet. A value of 0 indicates
1446 * that there are 32 BD locations in the packet (the maximum).
1448 * This field is valid only on the first BD of a packet.
1450 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1451 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1453 * This value is a hint for the length of the entire packet.
1454 * It is used by the chip to optimize internal processing.
1456 * The packet will be dropped if the hint is too short.
1458 * This field is valid only on the first BD of a packet.
1460 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1461 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1462 /* indicates packet length < 512B */
1463 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1464 /* indicates 512 <= packet length < 1KB */
1465 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1466 /* indicates 1KB <= packet length < 2KB */
1467 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1468 /* indicates packet length >= 2KB */
1469 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1470 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1472 * If set to 1, the device immediately updates the Send Consumer
1473 * Index after the buffer associated with this descriptor has
1474 * been transferred via DMA to NIC memory from host memory. An
1475 * interrupt may or may not be generated according to the state
1476 * of the interrupt avoidance mechanisms. If this bit
1477 * is set to 0, then the Consumer Index is only updated as soon
1478 * as one of the host interrupt coalescing conditions has been met.
1480 * This bit must be valid on the first BD of a packet.
1482 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1484 * This is the length of the host physical buffer this BD describes
1487 * This field must be valid on all BDs of a packet.
1491 * The opaque data field is pass through to the completion and can be
1492 * used for any data that the driver wants to associate with the
1495 * This field must be valid on the first BD of a packet.
1499 * This is the host physical address for the portion of the packet
1500 * described by this TX BD.
1502 * This value must be valid on all BDs of a packet.
1505 } __attribute__((packed));
1507 /* Last 16 bytes of tx_bd_long. */
1508 /* tx_bd_long_hi (size:128b/16B) */
1509 struct tx_bd_long_hi {
1511 * All bits in this field must be valid on the first BD of a packet.
1512 * Their value on other BDs of the packet will be ignored.
1516 * If set to 1, the controller replaces the TCP/UPD checksum
1517 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1518 * checksum field of the encapsulated TCP/UDP packets with the
1519 * hardware calculated TCP/UDP checksum for the packet associated
1520 * with this descriptor. The flag is ignored if the LSO flag is set.
1522 * This bit must be valid on the first BD of a packet.
1524 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1526 * If set to 1, the controller replaces the IP checksum of the
1527 * normal packets, or the inner IP checksum of the encapsulated
1528 * packets with the hardware calculated IP checksum for the
1529 * packet associated with this descriptor.
1531 * This bit must be valid on the first BD of a packet.
1533 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1535 * If set to 1, the controller will not append an Ethernet CRC
1536 * to the end of the frame.
1538 * This bit must be valid on the first BD of a packet.
1540 * Packet must be 64B or longer when this flag is set. It is not
1541 * useful to use this bit with any form of TX offload such as
1542 * CSO or LSO. The intent is that the packet from the host already
1543 * has a valid Ethernet CRC on the packet.
1545 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1547 * If set to 1, the device will record the time at which the packet
1548 * was actually transmitted at the TX MAC.
1550 * This bit must be valid on the first BD of a packet.
1552 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1554 * If set to 1, The controller replaces the tunnel IP checksum
1555 * field with hardware calculated IP checksum for the IP header
1556 * of the packet associated with this descriptor.
1558 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1559 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1560 * bit is set, outer UDP checksum will be calculated for the following
1562 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1563 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1564 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1565 * checksum will not be calculated.
1566 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1567 * as part of LSO operation.
1569 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1571 * If set to 1, the device will treat this packet with LSO(Large
1572 * Send Offload) processing for both normal or encapsulated
1573 * packets, which is a form of TCP segmentation. When this bit
1574 * is 1, the hdr_size and mss fields must be valid. The driver
1575 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1576 * flags since the controller will replace the appropriate
1577 * checksum fields for segmented packets.
1579 * When this bit is 1, the hdr_size and mss fields must be valid.
1581 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1583 * If set to zero when LSO is '1', then the IPID will be treated
1584 * as a 16b number and will be wrapped if it exceeds a value of
1587 * If set to one when LSO is '1', then the IPID will be treated
1588 * as a 15b number and will be wrapped if it exceeds a value 0f
1591 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1593 * If set to zero when LSO is '1', then the IPID of the tunnel
1594 * IP header will not be modified during LSO operations.
1596 * If set to one when LSO is '1', then the IPID of the tunnel
1597 * IP header will be incremented for each subsequent segment of an
1600 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1603 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1605 * If set to '1', then the RoCE ICRC will be appended to the
1606 * packet. Packet must be a valid RoCE format packet.
1608 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1610 * If set to '1', then the FCoE CRC will be appended to the
1611 * packet. Packet must be a valid FCoE format packet.
1613 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1616 * When LSO is '1', this field must contain the offset of the
1617 * TCP payload from the beginning of the packet in as
1618 * 16b words. In case of encapsulated/tunneling packet, this field
1619 * contains the offset of the inner TCP payload from beginning of the
1620 * packet as 16-bit words.
1622 * This value must be valid on the first BD of a packet.
1624 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1625 #define TX_BD_LONG_HDR_SIZE_SFT 0
1628 * This is the MSS value that will be used to do the LSO processing.
1629 * The value is the length in bytes of the TCP payload for each
1630 * segment generated by the LSO operation.
1632 * This value must be valid on the first BD of a packet.
1634 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1635 #define TX_BD_LONG_MSS_SFT 0
1638 * This value selects a CFA action to perform on the packet.
1639 * Set this value to zero if no CFA action is desired.
1641 * This value must be valid on the first BD of a packet.
1643 uint16_t cfa_action;
1645 * This value is action meta-data that defines CFA edit operations
1646 * that are done in addition to any action editing.
1649 /* When key=1, This is the VLAN tag VID value. */
1650 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1651 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1652 /* When key=1, This is the VLAN tag DE value. */
1653 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1654 /* When key=1, This is the VLAN tag PRI value. */
1655 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1656 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1657 /* When key=1, This is the VLAN tag TPID select value. */
1658 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1659 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1661 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1663 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1665 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1667 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1669 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1670 /* Value programmed in CFA VLANTPID register. */
1671 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1672 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1673 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1674 /* When key=1, This is the VLAN tag TPID select value. */
1675 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1676 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1678 * This field identifies the type of edit to be performed
1681 * This value must be valid on the first BD of a packet.
1683 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1684 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1686 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1688 * - meta[17:16] - TPID select value (0 = 0x8100).
1689 * - meta[15:12] - PRI/DE value.
1690 * - meta[11:0] - VID value.
1692 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1693 #define TX_BD_LONG_CFA_META_KEY_LAST \
1694 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1695 } __attribute__((packed));
1698 * This structure is used to inform the NIC of packet data that needs to be
1699 * transmitted with additional processing that requires extra data such as
1700 * VLAN insertion plus attached inline data. This BD type may be used to
1701 * improve latency for small packets needing the additional extended features
1702 * supported by long BDs.
1704 /* tx_bd_long_inline (size:256b/32B) */
1705 struct tx_bd_long_inline {
1706 uint16_t flags_type;
1707 /* This value identifies the type of buffer descriptor. */
1708 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1709 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1711 * This type of BD is 32B long and is used for inline L2 packet
1714 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1715 #define TX_BD_LONG_INLINE_TYPE_LAST \
1716 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1718 * All bits in this field may be set on the first BD of a packet.
1719 * Only the packet_end bit may be set in non-first BDs.
1721 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1722 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1724 * If set to 1, the packet ends with the data in the buffer
1725 * pointed to by this descriptor. This flag must be
1726 * valid on every BD.
1728 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1730 * If set to 1, the device will not generate a completion for
1731 * this transmit packet unless there is an error in its processing.
1732 * If this bit is set to 0, then the packet will be completed
1735 * This bit may be set only on the first BD of a packet.
1737 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1739 * This value indicates how many 16B BD locations are consumed
1740 * in the ring by this packet, including the BD and inline
1743 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1744 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1745 /* This field is deprecated. */
1746 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1747 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1749 * If set to 1, the device immediately updates the Send Consumer
1750 * Index after the buffer associated with this descriptor has
1751 * been transferred via DMA to NIC memory from host memory. An
1752 * interrupt may or may not be generated according to the state
1753 * of the interrupt avoidance mechanisms. If this bit
1754 * is set to 0, then the Consumer Index is only updated as soon
1755 * as one of the host interrupt coalescing conditions has been met.
1757 * This bit must be valid on the first BD of a packet.
1759 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1761 * This is the length of the inline data, not including BD length, in
1763 * The maximum value is 480.
1765 * This field must be valid on all BDs of a packet.
1769 * The opaque data field is passed through to the completion and can be
1770 * used for any data that the driver wants to associate with the transmit
1773 * This field must be valid on the first BD of a packet.
1778 * All bits in this field must be valid on the first BD of a packet.
1779 * Their value on other BDs of the packet is ignored.
1783 * If set to 1, the controller replaces the TCP/UPD checksum
1784 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1785 * checksum field of the encapsulated TCP/UDP packets with the
1786 * hardware calculated TCP/UDP checksum for the packet associated
1787 * with this descriptor. The flag is ignored if the LSO flag is set.
1789 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1791 * If set to 1, the controller replaces the IP checksum of the
1792 * normal packets, or the inner IP checksum of the encapsulated
1793 * packets with the hardware calculated IP checksum for the
1794 * packet associated with this descriptor.
1796 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1798 * If set to 1, the controller will not append an Ethernet CRC
1799 * to the end of the frame.
1801 * Packet must be 64B or longer when this flag is set. It is not
1802 * useful to use this bit with any form of TX offload such as
1803 * CSO or LSO. The intent is that the packet from the host already
1804 * has a valid Ethernet CRC on the packet.
1806 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1808 * If set to 1, the device will record the time at which the packet
1809 * was actually transmitted at the TX MAC.
1811 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1813 * If set to 1, the controller replaces the tunnel IP checksum
1814 * field with hardware calculated IP checksum for the IP header
1815 * of the packet associated with this descriptor. The hardware
1816 * updates an outer UDP checksum if it is non-zero.
1818 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1820 * This bit must be 0 for BDs of this type. LSO is not supported with
1823 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1824 /* Since LSO is not supported with inline BDs, this bit is not used. */
1825 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1826 /* Since LSO is not supported with inline BDs, this bit is not used. */
1827 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1829 * If set to '1', then the RoCE ICRC will be appended to the
1830 * packet. Packet must be a valid RoCE format packet.
1832 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1834 * If set to '1', then the FCoE CRC will be appended to the
1835 * packet. Packet must be a valid FCoE format packet.
1837 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1842 * This value selects a CFA action to perform on the packet.
1843 * Set this value to zero if no CFA action is desired.
1845 * This value must be valid on the first BD of a packet.
1847 uint16_t cfa_action;
1849 * This value is action meta-data that defines CFA edit operations
1850 * that are done in addition to any action editing.
1853 /* When key = 1, this is the VLAN tag VID value. */
1854 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1855 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1856 /* When key = 1, this is the VLAN tag DE value. */
1857 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1858 /* When key = 1, this is the VLAN tag PRI value. */
1859 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1860 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
1861 /* When key = 1, this is the VLAN tag TPID select value. */
1862 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1863 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
1865 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
1866 (UINT32_C(0x0) << 16)
1868 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
1869 (UINT32_C(0x1) << 16)
1871 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
1872 (UINT32_C(0x2) << 16)
1874 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
1875 (UINT32_C(0x3) << 16)
1877 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
1878 (UINT32_C(0x4) << 16)
1879 /* Value programmed in CFA VLANTPID register. */
1880 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
1881 (UINT32_C(0x5) << 16)
1882 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
1883 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
1884 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
1886 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
1888 * This field identifies the type of edit to be performed
1891 * This value must be valid on the first BD of a packet.
1893 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
1894 UINT32_C(0xf0000000)
1895 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
1897 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
1898 (UINT32_C(0x0) << 28)
1900 * - meta[17:16] - TPID select value (0 = 0x8100).
1901 * - meta[15:12] - PRI/DE value.
1902 * - meta[11:0] - VID value.
1904 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
1905 (UINT32_C(0x1) << 28)
1906 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
1907 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
1908 } __attribute__((packed));
1910 /* tx_bd_empty (size:128b/16B) */
1911 struct tx_bd_empty {
1912 /* This value identifies the type of buffer descriptor. */
1914 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1915 #define TX_BD_EMPTY_TYPE_SFT 0
1917 * Indicates that this BD is 1BB long and is an empty
1918 * TX BD. Not valid for use by the driver.
1920 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1921 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1922 uint8_t unused_1[3];
1924 uint8_t unused_3[3];
1925 uint8_t unused_4[8];
1926 } __attribute__((packed));
1928 /* rx_prod_pkt_bd (size:128b/16B) */
1929 struct rx_prod_pkt_bd {
1930 /* This value identifies the type of buffer descriptor. */
1931 uint16_t flags_type;
1932 /* This value identifies the type of buffer descriptor. */
1933 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
1934 #define RX_PROD_PKT_BD_TYPE_SFT 0
1936 * Indicates that this BD is 16B long and is an RX Producer
1937 * (ie. empty) buffer descriptor.
1939 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
1940 #define RX_PROD_PKT_BD_TYPE_LAST \
1941 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
1942 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
1943 #define RX_PROD_PKT_BD_FLAGS_SFT 6
1945 * If set to 1, the packet will be placed at the address plus
1946 * 2B. The 2 Bytes of padding will be written as zero.
1948 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
1950 * If set to 1, the packet write will be padded out to the
1951 * nearest cache-line with zero value padding.
1953 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
1955 * This value is the number of additional buffers in the ring that
1956 * describe the buffer space to be consumed for the this packet.
1957 * If the value is zero, then the packet must fit within the
1958 * space described by this BD. If this value is 1 or more, it
1959 * indicates how many additional "buffer" BDs are in the ring
1960 * immediately following this BD to be used for the same
1963 * Even if the packet to be placed does not need all the
1964 * additional buffers, they will be consumed anyway.
1966 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
1967 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
1969 * This is the length in Bytes of the host physical buffer where
1970 * data for the packet may be placed in host memory.
1974 * The opaque data field is pass through to the completion and can be
1975 * used for any data that the driver wants to associate with this
1976 * receive buffer set.
1980 * This is the host physical address where data for the packet may
1981 * by placed in host memory.
1984 } __attribute__((packed));
1986 /* rx_prod_bfr_bd (size:128b/16B) */
1987 struct rx_prod_bfr_bd {
1988 /* This value identifies the type of buffer descriptor. */
1989 uint16_t flags_type;
1990 /* This value identifies the type of buffer descriptor. */
1991 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
1992 #define RX_PROD_BFR_BD_TYPE_SFT 0
1994 * Indicates that this BD is 16B long and is an RX
1995 * Producer Buffer BD.
1997 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
1998 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
1999 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2000 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2002 * This is the length in Bytes of the host physical buffer where
2003 * data for the packet may be placed in host memory.
2006 /* This field is not used. */
2009 * This is the host physical address where data for the packet may
2010 * by placed in host memory.
2013 } __attribute__((packed));
2015 /* rx_prod_agg_bd (size:128b/16B) */
2016 struct rx_prod_agg_bd {
2017 /* This value identifies the type of buffer descriptor. */
2018 uint16_t flags_type;
2019 /* This value identifies the type of buffer descriptor. */
2020 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2021 #define RX_PROD_AGG_BD_TYPE_SFT 0
2023 * Indicates that this BD is 16B long and is an
2024 * RX Producer Assembly Buffer Descriptor.
2026 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2027 #define RX_PROD_AGG_BD_TYPE_LAST \
2028 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2029 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2030 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2032 * If set to 1, the packet write will be padded out to the
2033 * nearest cache-line with zero value padding.
2035 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2037 * This is the length in Bytes of the host physical buffer where
2038 * data for the packet may be placed in host memory.
2042 * The opaque data field is pass through to the completion and can be
2043 * used for any data that the driver wants to associate with this
2044 * receive assembly buffer.
2048 * This is the host physical address where data for the packet may
2049 * by placed in host memory.
2052 } __attribute__((packed));
2054 /* cmpl_base (size:128b/16B) */
2058 * This field indicates the exact type of the completion.
2059 * By convention, the LSB identifies the length of the
2060 * record in 16B units. Even values indicate 16B
2061 * records. Odd values indicate 32B
2064 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2065 #define CMPL_BASE_TYPE_SFT 0
2068 * Completion of TX packet. Length = 16B
2070 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2073 * Completion of and L2 RX packet. Length = 32B
2075 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2077 * RX Aggregation Buffer completion :
2078 * Completion of an L2 aggregation buffer in support of
2079 * TPA, HDS, or Jumbo packet completion. Length = 16B
2081 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2083 * RX L2 TPA Start Completion:
2084 * Completion at the beginning of a TPA operation.
2087 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2089 * RX L2 TPA End Completion:
2090 * Completion at the end of a TPA operation.
2093 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2095 * Statistics Ejection Completion:
2096 * Completion of statistics data ejection buffer.
2099 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2101 * HWRM Command Completion:
2102 * Completion of an HWRM command.
2104 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2105 /* Forwarded HWRM Request */
2106 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2107 /* Forwarded HWRM Response */
2108 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2109 /* HWRM Asynchronous Event Information */
2110 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2111 /* CQ Notification */
2112 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2113 /* SRQ Threshold Event */
2114 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2115 /* DBQ Threshold Event */
2116 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2117 /* QP Async Notification */
2118 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2119 /* Function Async Notification */
2120 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2121 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2127 * This value is written by the NIC such that it will be different
2128 * for each pass through the completion queue. The even passes
2129 * will write 1. The odd passes will write 0.
2132 #define CMPL_BASE_V UINT32_C(0x1)
2133 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2134 #define CMPL_BASE_INFO3_SFT 1
2137 } __attribute__((packed));
2139 /* tx_cmpl (size:128b/16B) */
2141 uint16_t flags_type;
2143 * This field indicates the exact type of the completion.
2144 * By convention, the LSB identifies the length of the
2145 * record in 16B units. Even values indicate 16B
2146 * records. Odd values indicate 32B
2149 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2150 #define TX_CMPL_TYPE_SFT 0
2153 * Completion of TX packet. Length = 16B
2155 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2156 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2157 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2158 #define TX_CMPL_FLAGS_SFT 6
2160 * When this bit is '1', it indicates a packet that has an
2161 * error of some type. Type of error is indicated in
2164 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2166 * When this bit is '1', it indicates that the packet completed
2167 * was transmitted using the push acceleration data provided
2168 * by the driver. When this bit is '0', it indicates that the
2169 * packet had not push acceleration data written or was executed
2170 * as a normal packet even though push data was provided.
2172 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2173 /* unused1 is 16 b */
2176 * This is a copy of the opaque field from the first TX BD of this
2177 * transmitted packet.
2182 * This value is written by the NIC such that it will be different
2183 * for each pass through the completion queue. The even passes
2184 * will write 1. The odd passes will write 0.
2186 #define TX_CMPL_V UINT32_C(0x1)
2187 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2188 #define TX_CMPL_ERRORS_SFT 1
2190 * This error indicates that there was some sort of problem
2191 * with the BDs for the packet.
2193 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2194 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2196 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2199 * BDs were not formatted correctly.
2201 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2202 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2203 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2205 * When this bit is '1', it indicates that the length of
2206 * the packet was zero. No packet was transmitted.
2208 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2210 * When this bit is '1', it indicates that the packet
2211 * was longer than the programmed limit in TDI. No
2212 * packet was transmitted.
2214 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2216 * When this bit is '1', it indicates that one or more of the
2217 * BDs associated with this packet generated a PCI error.
2218 * This probably means the address was not valid.
2220 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2222 * When this bit is '1', it indicates that the packet was longer
2223 * than indicated by the hint. No packet was transmitted.
2225 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2227 * When this bit is '1', it indicates that the packet was
2228 * dropped due to Poison TLP error on one or more of the
2229 * TLPs in the PXP completion.
2231 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2232 /* unused2 is 16 b */
2234 /* unused3 is 32 b */
2236 } __attribute__((packed));
2238 /* rx_pkt_cmpl (size:128b/16B) */
2239 struct rx_pkt_cmpl {
2240 uint16_t flags_type;
2242 * This field indicates the exact type of the completion.
2243 * By convention, the LSB identifies the length of the
2244 * record in 16B units. Even values indicate 16B
2245 * records. Odd values indicate 32B
2248 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2249 #define RX_PKT_CMPL_TYPE_SFT 0
2252 * Completion of and L2 RX packet. Length = 32B
2254 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2255 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2256 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2257 #define RX_PKT_CMPL_FLAGS_SFT 6
2259 * When this bit is '1', it indicates a packet that has an
2260 * error of some type. Type of error is indicated in
2263 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2264 /* This field indicates how the packet was placed in the buffer. */
2265 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2266 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2269 * Packet was placed using normal algorithm.
2271 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2274 * Packet was placed using jumbo algorithm.
2276 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2278 * Header/Data Separation:
2279 * Packet was placed using Header/Data separation algorithm.
2280 * The separation location is indicated by the itype field.
2282 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2283 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2284 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2285 /* This bit is '1' if the RSS field in this completion is valid. */
2286 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2288 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2290 * This value indicates what the inner packet determined for the
2293 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2294 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2297 * Indicates that the packet type was not known.
2299 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2300 (UINT32_C(0x0) << 12)
2303 * Indicates that the packet was an IP packet, but further
2304 * classification was not possible.
2306 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2307 (UINT32_C(0x1) << 12)
2310 * Indicates that the packet was IP and TCP.
2311 * This indicates that the payload_offset field is valid.
2313 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2314 (UINT32_C(0x2) << 12)
2317 * Indicates that the packet was IP and UDP.
2318 * This indicates that the payload_offset field is valid.
2320 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2321 (UINT32_C(0x3) << 12)
2324 * Indicates that the packet was recognized as a FCoE.
2325 * This also indicates that the payload_offset field is valid.
2327 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2328 (UINT32_C(0x4) << 12)
2331 * Indicates that the packet was recognized as a RoCE.
2332 * This also indicates that the payload_offset field is valid.
2334 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2335 (UINT32_C(0x5) << 12)
2338 * Indicates that the packet was recognized as ICMP.
2339 * This indicates that the payload_offset field is valid.
2341 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2342 (UINT32_C(0x7) << 12)
2344 * PtP packet wo/timestamp:
2345 * Indicates that the packet was recognized as a PtP
2348 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2349 (UINT32_C(0x8) << 12)
2351 * PtP packet w/timestamp:
2352 * Indicates that the packet was recognized as a PtP
2353 * packet and that a timestamp was taken for the packet.
2355 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2356 (UINT32_C(0x9) << 12)
2357 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2358 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2360 * This is the length of the data for the packet stored in the
2361 * buffer(s) identified by the opaque value. This includes
2362 * the packet BD and any associated buffer BDs. This does not include
2363 * the the length of any data places in aggregation BDs.
2367 * This is a copy of the opaque field from the RX BD this completion
2371 uint8_t agg_bufs_v1;
2373 * This value is written by the NIC such that it will be different
2374 * for each pass through the completion queue. The even passes
2375 * will write 1. The odd passes will write 0.
2377 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2379 * This value is the number of aggregation buffers that follow this
2380 * entry in the completion ring that are a part of this packet.
2381 * If the value is zero, then the packet is completely contained
2382 * in the buffer space provided for the packet in the RX ring.
2384 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2385 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2386 /* unused1 is 2 b */
2387 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2388 #define RX_PKT_CMPL_UNUSED1_SFT 6
2390 * This is the RSS hash type for the packet. The value is packed
2391 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2393 * The value of tuple_extrac_op provides the information about
2394 * what fields the hash was computed on.
2395 * * 0: The RSS hash was computed over source IP address,
2396 * destination IP address, source port, and destination port of inner
2397 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2398 * the packet headers are considered inner packet headers for the RSS
2399 * hash computation purpose.
2400 * * 1: The RSS hash was computed over source IP address and destination
2401 * IP address of inner IP header. Note: For non-tunneled packets,
2402 * the packet headers are considered inner packet headers for the RSS
2403 * hash computation purpose.
2404 * * 2: The RSS hash was computed over source IP address,
2405 * destination IP address, source port, and destination port of
2406 * IP and TCP or UDP headers of outer tunnel headers.
2407 * Note: For non-tunneled packets, this value is not applicable.
2408 * * 3: The RSS hash was computed over source IP address and
2409 * destination IP address of IP header of outer tunnel headers.
2410 * Note: For non-tunneled packets, this value is not applicable.
2412 * Note that 4-tuples values listed above are applicable
2413 * for layer 4 protocols supported and enabled for RSS in the hardware,
2414 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2415 * enabled for TCP traffic only, then the values of tuple_extract_op
2416 * corresponding to 4-tuples are only valid for TCP traffic.
2418 uint8_t rss_hash_type;
2420 * This value indicates the offset in bytes from the beginning of the packet
2421 * where the inner payload starts. This value is valid for TCP, UDP,
2422 * FCoE, and RoCE packets.
2424 * A value of zero indicates that header is 256B into the packet.
2426 uint8_t payload_offset;
2427 /* unused2 is 8 b */
2430 * This value is the RSS hash value calculated for the packet
2431 * based on the mode bits and key value in the VNIC.
2434 } __attribute__((packed));
2436 /* Last 16 bytes of rx_pkt_cmpl. */
2437 /* rx_pkt_cmpl_hi (size:128b/16B) */
2438 struct rx_pkt_cmpl_hi {
2441 * This indicates that the ip checksum was calculated for the
2442 * inner packet and that the ip_cs_error field indicates if there
2445 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2447 * This indicates that the TCP, UDP or ICMP checksum was
2448 * calculated for the inner packet and that the l4_cs_error field
2449 * indicates if there was an error.
2451 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2453 * This indicates that the ip checksum was calculated for the
2454 * tunnel header and that the t_ip_cs_error field indicates if there
2457 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2459 * This indicates that the UDP checksum was
2460 * calculated for the tunnel packet and that the t_l4_cs_error field
2461 * indicates if there was an error.
2463 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2464 /* This value indicates what format the metadata field is. */
2465 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2466 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2467 /* No metadata informtaion. Value is zero. */
2468 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2469 (UINT32_C(0x0) << 4)
2471 * The metadata field contains the VLAN tag and TPID value.
2472 * - metadata[11:0] contains the vlan VID value.
2473 * - metadata[12] contains the vlan DE value.
2474 * - metadata[15:13] contains the vlan PRI value.
2475 * - metadata[31:16] contains the vlan TPID value.
2477 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2478 (UINT32_C(0x1) << 4)
2480 * If ext_meta_format is equal to 1, the metadata field
2481 * contains the lower 16b of the tunnel ID value, justified
2483 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2484 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2485 * - NVGRE = TNI[23:0] -> Tenant Network ID
2486 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2487 * - IPV4 = 0 (not populated)
2488 * - IPV6 = Flow Label[19:0]
2489 * - PPPoE = sessionID[15:0]
2490 * - MPLs = Outer label[19:0]
2491 * - UPAR = Selected[31:0] with bit mask
2493 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2494 (UINT32_C(0x2) << 4)
2496 * if ext_meta_format is equal to 1, metadata field contains
2497 * 16b metadata from the prepended header (chdr_data).
2499 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2500 (UINT32_C(0x3) << 4)
2502 * If ext_meta_format is equal to 1, the metadata field contains
2503 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2505 * - metadata[8:0] contains the outer_l3_offset.
2506 * - metadata[17:9] contains the inner_l2_offset.
2507 * - metadata[26:18] contains the inner_l3_offset.
2508 * - metadata[31:27] contains the inner_l4_size.
2510 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2511 (UINT32_C(0x4) << 4)
2512 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2513 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2515 * This field indicates the IP type for the inner-most IP header.
2516 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2517 * This value is only valid if itype indicates a packet
2518 * with an IP header.
2520 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2522 * This indicates that the complete 1's complement checksum was
2523 * calculated for the packet.
2525 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2527 * The combination of this value and meta_format indicated what
2528 * format the metadata field is.
2530 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2531 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2533 * This value is the complete 1's complement checksum calculated from
2534 * the start of the outer L3 header to the end of the packet (not
2535 * including the ethernet crc). It is valid when the
2536 * 'complete_checksum_calc' flag is set.
2538 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2539 UINT32_C(0xffff0000)
2540 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2542 * This is data from the CFA block as indicated by the meta_format
2546 /* When meta_format=1, this value is the VLAN VID. */
2547 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2548 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2549 /* When meta_format=1, this value is the VLAN DE. */
2550 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2551 /* When meta_format=1, this value is the VLAN PRI. */
2552 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2553 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2554 /* When meta_format=1, this value is the VLAN TPID. */
2555 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2556 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2559 * This value is written by the NIC such that it will be different
2560 * for each pass through the completion queue. The even passes
2561 * will write 1. The odd passes will write 0.
2563 #define RX_PKT_CMPL_V2 \
2565 #define RX_PKT_CMPL_ERRORS_MASK \
2567 #define RX_PKT_CMPL_ERRORS_SFT 1
2569 * This error indicates that there was some sort of problem with
2570 * the BDs for the packet that was found after part of the
2571 * packet was already placed. The packet should be treated as
2574 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2576 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2577 /* No buffer error */
2578 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2579 (UINT32_C(0x0) << 1)
2582 * Packet did not fit into packet buffer provided.
2583 * For regular placement, this means the packet did not fit
2584 * in the buffer provided. For HDS and jumbo placement, this
2585 * means that the packet could not be placed into 7 physical
2588 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2589 (UINT32_C(0x1) << 1)
2592 * All BDs needed for the packet were not on-chip when
2593 * the packet arrived.
2595 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2596 (UINT32_C(0x2) << 1)
2599 * BDs were not formatted correctly.
2601 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2602 (UINT32_C(0x3) << 1)
2605 * There was a bad_format error on the previous operation
2607 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2608 (UINT32_C(0x5) << 1)
2609 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2610 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2612 * This indicates that there was an error in the IP header
2615 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2618 * This indicates that there was an error in the TCP, UDP
2621 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2624 * This indicates that there was an error in the tunnel
2625 * IP header checksum.
2627 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2630 * This indicates that there was an error in the tunnel
2633 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2636 * This indicates that there was a CRC error on either an FCoE
2637 * or RoCE packet. The itype indicates the packet type.
2639 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2642 * This indicates that there was an error in the tunnel
2643 * portion of the packet when this
2644 * field is non-zero.
2646 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2648 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2650 * No additional error occurred on the tunnel portion
2651 * or the packet of the packet does not have a tunnel.
2653 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2654 (UINT32_C(0x0) << 9)
2656 * Indicates that IP header version does not match
2657 * expectation from L2 Ethertype for IPv4 and IPv6
2658 * in the tunnel header.
2660 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2661 (UINT32_C(0x1) << 9)
2663 * Indicates that header length is out of range in the
2664 * tunnel header. Valid for
2667 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2668 (UINT32_C(0x2) << 9)
2670 * Indicates that the physical packet is shorter than that
2671 * claimed by the PPPoE header length for a tunnel PPPoE
2674 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2675 (UINT32_C(0x3) << 9)
2677 * Indicates that physical packet is shorter than that claimed
2678 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2679 * tunnel packet packets.
2681 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2682 (UINT32_C(0x4) << 9)
2684 * Indicates that the physical packet is shorter than that
2685 * claimed by the tunnel UDP header length for a tunnel
2686 * UDP packet that is not fragmented.
2688 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2689 (UINT32_C(0x5) << 9)
2691 * indicates that the IPv4 TTL or IPv6 hop limit check
2692 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2693 * for IPv4, and IPv6.
2695 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2696 (UINT32_C(0x6) << 9)
2697 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2698 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2700 * This indicates that there was an error in the inner
2701 * portion of the packet when this
2702 * field is non-zero.
2704 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2706 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2708 * No additional error occurred on the tunnel portion
2709 * or the packet of the packet does not have a tunnel.
2711 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2712 (UINT32_C(0x0) << 12)
2714 * Indicates that IP header version does not match
2715 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2716 * option other than VFT was parsed on
2719 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2720 (UINT32_C(0x1) << 12)
2722 * indicates that header length is out of range. Valid for
2725 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2726 (UINT32_C(0x2) << 12)
2728 * indicates that the IPv4 TTL or IPv6 hop limit check
2729 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2731 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2732 (UINT32_C(0x3) << 12)
2734 * Indicates that physical packet is shorter than that
2735 * claimed by the l3 header length. Valid for IPv4,
2736 * IPv6 packet or RoCE packets.
2738 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2739 (UINT32_C(0x4) << 12)
2741 * Indicates that the physical packet is shorter than that
2742 * claimed by the UDP header length for a UDP packet that is
2745 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2746 (UINT32_C(0x5) << 12)
2748 * Indicates that TCP header length > IP payload. Valid for
2751 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2752 (UINT32_C(0x6) << 12)
2753 /* Indicates that TCP header length < 5. Valid for TCP. */
2754 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2755 (UINT32_C(0x7) << 12)
2757 * Indicates that TCP option headers result in a TCP header
2758 * size that does not match data offset in TCP header. Valid
2761 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2762 (UINT32_C(0x8) << 12)
2763 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2764 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2766 * This field identifies the CFA action rule that was used for this
2772 * This value holds the reordering sequence number for the packet.
2773 * If the reordering sequence is not valid, then this value is zero.
2774 * The reordering domain for the packet is in the bottom 8 to 10b of
2775 * the rss_hash value. The bottom 20b of this value contain the
2776 * ordering domain value for the packet.
2778 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2779 #define RX_PKT_CMPL_REORDER_SFT 0
2780 } __attribute__((packed));
2782 /* rx_tpa_start_cmpl (size:128b/16B) */
2783 struct rx_tpa_start_cmpl {
2784 uint16_t flags_type;
2786 * This field indicates the exact type of the completion.
2787 * By convention, the LSB identifies the length of the
2788 * record in 16B units. Even values indicate 16B
2789 * records. Odd values indicate 32B
2792 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2793 #define RX_TPA_START_CMPL_TYPE_SFT 0
2795 * RX L2 TPA Start Completion:
2796 * Completion at the beginning of a TPA operation.
2799 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2800 #define RX_TPA_START_CMPL_TYPE_LAST \
2801 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2802 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2803 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2804 /* This bit will always be '0' for TPA start completions. */
2805 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2806 /* This field indicates how the packet was placed in the buffer. */
2807 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2808 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2811 * TPA Packet was placed using jumbo algorithm. This means
2812 * that the first buffer will be filled with data before
2813 * moving to aggregation buffers. Each aggregation buffer
2814 * will be filled before moving to the next aggregation
2817 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2818 (UINT32_C(0x1) << 7)
2820 * Header/Data Separation:
2821 * Packet was placed using Header/Data separation algorithm.
2822 * The separation location is indicated by the itype field.
2824 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2825 (UINT32_C(0x2) << 7)
2828 * Packet will be placed using GRO/Jumbo where the first
2829 * packet is filled with data. Subsequent packets will be
2830 * placed such that any one packet does not span two
2831 * aggregation buffers unless it starts at the beginning of
2832 * an aggregation buffer.
2834 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2835 (UINT32_C(0x5) << 7)
2837 * GRO/Header-Data Separation:
2838 * Packet will be placed using GRO/HDS where the header
2839 * is in the first packet.
2840 * Payload of each packet will be
2841 * placed such that any one packet does not span two
2842 * aggregation buffers unless it starts at the beginning of
2843 * an aggregation buffer.
2845 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2846 (UINT32_C(0x6) << 7)
2847 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2848 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2849 /* This bit is '1' if the RSS field in this completion is valid. */
2850 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2852 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2854 * This value indicates what the inner packet determined for the
2857 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2858 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2861 * Indicates that the packet was IP and TCP.
2863 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2864 (UINT32_C(0x2) << 12)
2865 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2866 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2868 * This value indicates the amount of packet data written to the
2869 * buffer the opaque field in this completion corresponds to.
2873 * This is a copy of the opaque field from the RX BD this completion
2878 * This value is written by the NIC such that it will be different
2879 * for each pass through the completion queue. The even passes
2880 * will write 1. The odd passes will write 0.
2884 * This value is written by the NIC such that it will be different
2885 * for each pass through the completion queue. The even passes
2886 * will write 1. The odd passes will write 0.
2888 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2889 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2891 * This is the RSS hash type for the packet. The value is packed
2892 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2894 * The value of tuple_extrac_op provides the information about
2895 * what fields the hash was computed on.
2896 * * 0: The RSS hash was computed over source IP address,
2897 * destination IP address, source port, and destination port of inner
2898 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2899 * the packet headers are considered inner packet headers for the RSS
2900 * hash computation purpose.
2901 * * 1: The RSS hash was computed over source IP address and destination
2902 * IP address of inner IP header. Note: For non-tunneled packets,
2903 * the packet headers are considered inner packet headers for the RSS
2904 * hash computation purpose.
2905 * * 2: The RSS hash was computed over source IP address,
2906 * destination IP address, source port, and destination port of
2907 * IP and TCP or UDP headers of outer tunnel headers.
2908 * Note: For non-tunneled packets, this value is not applicable.
2909 * * 3: The RSS hash was computed over source IP address and
2910 * destination IP address of IP header of outer tunnel headers.
2911 * Note: For non-tunneled packets, this value is not applicable.
2913 * Note that 4-tuples values listed above are applicable
2914 * for layer 4 protocols supported and enabled for RSS in the hardware,
2915 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2916 * enabled for TCP traffic only, then the values of tuple_extract_op
2917 * corresponding to 4-tuples are only valid for TCP traffic.
2919 uint8_t rss_hash_type;
2921 * This is the aggregation ID that the completion is associated
2922 * with. Use this number to correlate the TPA start completion
2923 * with the TPA end completion.
2926 /* unused2 is 9 b */
2927 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2928 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2930 * This is the aggregation ID that the completion is associated
2931 * with. Use this number to correlate the TPA start completion
2932 * with the TPA end completion.
2934 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
2935 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
2937 * This value is the RSS hash value calculated for the packet
2938 * based on the mode bits and key value in the VNIC.
2941 } __attribute__((packed));
2943 /* Last 16 bytes of rx_tpq_start_cmpl. */
2944 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
2945 struct rx_tpa_start_cmpl_hi {
2948 * This indicates that the ip checksum was calculated for the
2949 * inner packet and that the sum passed for all segments
2950 * included in the aggregation.
2952 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
2955 * This indicates that the TCP, UDP or ICMP checksum was
2956 * calculated for the inner packet and that the sum passed
2957 * for all segments included in the aggregation.
2959 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
2962 * This indicates that the ip checksum was calculated for the
2963 * tunnel header and that the sum passed for all segments
2964 * included in the aggregation.
2966 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
2969 * This indicates that the UDP checksum was
2970 * calculated for the tunnel packet and that the sum passed for
2971 * all segments included in the aggregation.
2973 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
2975 /* This value indicates what format the metadata field is. */
2976 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
2978 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
2979 /* No metadata informtaion. Value is zero. */
2980 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
2981 (UINT32_C(0x0) << 4)
2983 * The metadata field contains the VLAN tag and TPID value.
2984 * - metadata[11:0] contains the vlan VID value.
2985 * - metadata[12] contains the vlan DE value.
2986 * - metadata[15:13] contains the vlan PRI value.
2987 * - metadata[31:16] contains the vlan TPID value.
2989 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
2990 (UINT32_C(0x1) << 4)
2992 * If ext_meta_format is equal to 1, the metadata field
2993 * contains the lower 16b of the tunnel ID value, justified
2995 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2996 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2997 * - NVGRE = TNI[23:0] -> Tenant Network ID
2998 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2999 * - IPV4 = 0 (not populated)
3000 * - IPV6 = Flow Label[19:0]
3001 * - PPPoE = sessionID[15:0]
3002 * - MPLs = Outer label[19:0]
3003 * - UPAR = Selected[31:0] with bit mask
3005 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3006 (UINT32_C(0x2) << 4)
3008 * if ext_meta_format is equal to 1, metadata field contains
3009 * 16b metadata from the prepended header (chdr_data).
3011 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3012 (UINT32_C(0x3) << 4)
3014 * If ext_meta_format is equal to 1, the metadata field contains
3015 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3017 * - metadata[8:0] contains the outer_l3_offset.
3018 * - metadata[17:9] contains the inner_l2_offset.
3019 * - metadata[26:18] contains the inner_l3_offset.
3020 * - metadata[31:27] contains the inner_l4_size.
3022 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3023 (UINT32_C(0x4) << 4)
3024 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3025 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3027 * This field indicates the IP type for the inner-most IP header.
3028 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3030 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
3033 * This indicates that the complete 1's complement checksum was
3034 * calculated for the packet.
3036 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3039 * The combination of this value and meta_format indicated what
3040 * format the metadata field is.
3042 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3044 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3046 * This value is the complete 1's complement checksum calculated from
3047 * the start of the outer L3 header to the end of the packet (not
3048 * including the ethernet crc). It is valid when the
3049 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3050 * the complete checksum is calculated for the first packet in the
3053 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3054 UINT32_C(0xffff0000)
3055 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3057 * This is data from the CFA block as indicated by the meta_format
3061 /* When meta_format=1, this value is the VLAN VID. */
3062 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3063 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3064 /* When meta_format=1, this value is the VLAN DE. */
3065 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3066 /* When meta_format=1, this value is the VLAN PRI. */
3067 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3068 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3069 /* When meta_format=1, this value is the VLAN TPID. */
3070 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3071 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3074 * This value is written by the NIC such that it will be different
3075 * for each pass through the completion queue. The even passes
3076 * will write 1. The odd passes will write 0.
3078 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3079 #define RX_TPA_START_CMPL_ERRORS_MASK \
3081 #define RX_TPA_START_CMPL_ERRORS_SFT 1
3083 * This error indicates that there was some sort of problem with
3084 * the BDs for the packet that was found after part of the
3085 * packet was already placed. The packet should be treated as
3088 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3089 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3090 /* No buffer error */
3091 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3092 (UINT32_C(0x0) << 1)
3095 * BDs were not formatted correctly.
3097 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3098 (UINT32_C(0x3) << 1)
3101 * There was a bad_format error on the previous operation
3103 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3104 (UINT32_C(0x5) << 1)
3105 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3106 RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3108 * This field identifies the CFA action rule that was used for this
3113 * This is the size in bytes of the inner most L4 header.
3114 * This can be subtracted from the payload_offset to determine
3115 * the start of the inner most L4 header.
3117 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3119 * This is the offset from the beginning of the packet in bytes for
3120 * the outer L3 header. If there is no outer L3 header, then this
3123 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3124 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3126 * This is the offset from the beginning of the packet in bytes for
3127 * the inner most L2 header.
3129 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3130 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3132 * This is the offset from the beginning of the packet in bytes for
3133 * the inner most L3 header.
3135 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3136 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3138 * This is the size in bytes of the inner most L4 header.
3139 * This can be subtracted from the payload_offset to determine
3140 * the start of the inner most L4 header.
3142 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3143 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3144 } __attribute__((packed));
3146 /* rx_tpa_end_cmpl (size:128b/16B) */
3147 struct rx_tpa_end_cmpl {
3148 uint16_t flags_type;
3150 * This field indicates the exact type of the completion.
3151 * By convention, the LSB identifies the length of the
3152 * record in 16B units. Even values indicate 16B
3153 * records. Odd values indicate 32B
3156 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3157 #define RX_TPA_END_CMPL_TYPE_SFT 0
3159 * RX L2 TPA End Completion:
3160 * Completion at the end of a TPA operation.
3163 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3164 #define RX_TPA_END_CMPL_TYPE_LAST \
3165 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3166 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3167 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3169 * When this bit is '1', it indicates a packet that has an
3170 * error of some type. Type of error is indicated in
3173 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3174 /* This field indicates how the packet was placed in the buffer. */
3175 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3176 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3179 * TPA Packet was placed using jumbo algorithm. This means
3180 * that the first buffer will be filled with data before
3181 * moving to aggregation buffers. Each aggregation buffer
3182 * will be filled before moving to the next aggregation
3185 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3186 (UINT32_C(0x1) << 7)
3188 * Header/Data Separation:
3189 * Packet was placed using Header/Data separation algorithm.
3190 * The separation location is indicated by the itype field.
3192 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3193 (UINT32_C(0x2) << 7)
3196 * Packet will be placed using GRO/Jumbo where the first
3197 * packet is filled with data. Subsequent packets will be
3198 * placed such that any one packet does not span two
3199 * aggregation buffers unless it starts at the beginning of
3200 * an aggregation buffer.
3202 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3203 (UINT32_C(0x5) << 7)
3205 * GRO/Header-Data Separation:
3206 * Packet will be placed using GRO/HDS where the header
3207 * is in the first packet.
3208 * Payload of each packet will be
3209 * placed such that any one packet does not span two
3210 * aggregation buffers unless it starts at the beginning of
3211 * an aggregation buffer.
3213 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3214 (UINT32_C(0x6) << 7)
3215 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3216 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3218 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3219 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3221 * This value indicates what the inner packet determined for the
3224 * Indicates that the packet was IP and TCP. This indicates
3225 * that the ip_cs field is valid and that the tcp_udp_cs
3226 * field is valid and contains the TCP checksum.
3227 * This also indicates that the payload_offset field is valid.
3229 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3230 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3232 * This value is zero for TPA End completions.
3233 * There is no data in the buffer that corresponds to the opaque
3234 * value in this completion.
3238 * This is a copy of the opaque field from the RX BD this completion
3243 * This value is written by the NIC such that it will be different
3244 * for each pass through the completion queue. The even passes
3245 * will write 1. The odd passes will write 0.
3247 uint8_t agg_bufs_v1;
3249 * This value is written by the NIC such that it will be different
3250 * for each pass through the completion queue. The even passes
3251 * will write 1. The odd passes will write 0.
3253 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3255 * This value is the number of aggregation buffers that follow this
3256 * entry in the completion ring that are a part of this aggregation
3258 * If the value is zero, then the packet is completely contained
3259 * in the buffer space provided in the aggregation start completion.
3261 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3262 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3263 /* This value is the number of segments in the TPA operation. */
3266 * This value indicates the offset in bytes from the beginning of the packet
3267 * where the inner payload starts. This value is valid for TCP, UDP,
3268 * FCoE, and RoCE packets.
3270 * A value of zero indicates an offset of 256 bytes.
3272 uint8_t payload_offset;
3274 /* unused2 is 1 b */
3275 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3277 * This is the aggregation ID that the completion is associated
3278 * with. Use this number to correlate the TPA start completion
3279 * with the TPA end completion.
3281 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3282 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3284 * For non-GRO packets, this value is the
3285 * timestamp delta between earliest and latest timestamp values for
3286 * TPA packet. If packets were not time stamped, then delta will be
3289 * For GRO packets, this field is zero except for the following
3292 * Timestamp present indication. When '0', no Timestamp
3293 * option is in the packet. When '1', then a Timestamp
3294 * option is present in the packet.
3297 } __attribute__((packed));
3299 /* Last 16 bytes of rx_tpa_end_cmpl. */
3300 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3301 struct rx_tpa_end_cmpl_hi {
3303 * This value is the number of duplicate ACKs that have been
3304 * received as part of the TPA operation.
3306 uint16_t tpa_dup_acks;
3308 * This value is the number of duplicate ACKs that have been
3309 * received as part of the TPA operation.
3311 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3312 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3314 * This value indicated the offset in bytes from the beginning of
3315 * the packet where the inner payload starts. This value is valid
3316 * for TCP, UDP, FCoE and RoCE packets
3318 uint8_t payload_offset;
3320 * The value is the total number of aggregation buffers that were
3321 * used in the TPA operation. All TPA aggregation buffer completions
3322 * precede the TPA End completion. If the value is zero, then the
3323 * aggregation is completely contained in the buffer space provided
3324 * in the aggregation start completion.
3325 * Note that the field is simply provided as a cross check.
3327 uint8_t tpa_agg_bufs;
3329 * This value is the valid when TPA completion is active. It
3330 * indicates the length of the longest segment of the TPA operation
3331 * for LRO mode and the length of the first segment in GRO mode.
3333 * This value may be used by GRO software to re-construct the original
3334 * packet stream from the TPA packet. This is the length of all
3335 * but the last segment for GRO. In LRO mode this value may be used
3336 * to indicate MSS size to the stack.
3338 uint16_t tpa_seg_len;
3339 /* unused4 is 16 b */
3343 * This value is written by the NIC such that it will be different
3344 * for each pass through the completion queue. The even passes
3345 * will write 1. The odd passes will write 0.
3347 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3348 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3349 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3351 * This error indicates that there was some sort of problem with
3352 * the BDs for the packet that was found after part of the
3353 * packet was already placed. The packet should be treated as
3356 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3357 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3358 /* No buffer error */
3359 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3360 (UINT32_C(0x0) << 1)
3362 * This error occurs when there is a fatal HW problem in
3363 * the chip only. It indicates that there were not
3364 * BDs on chip but that there was adequate reservation.
3365 * provided by the TPA block.
3367 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3368 (UINT32_C(0x2) << 1)
3371 * BDs were not formatted correctly.
3373 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3374 (UINT32_C(0x3) << 1)
3376 * This error occurs when TPA block was not configured to
3377 * reserve adequate BDs for TPA operations on this RX
3378 * ring. All data for the TPA operation was not placed.
3380 * This error can also be generated when the number of
3381 * segments is not programmed correctly in TPA and the
3382 * 33 total aggregation buffers allowed for the TPA
3383 * operation has been exceeded.
3385 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3386 (UINT32_C(0x4) << 1)
3389 * There was a bad_format error on the previous operation
3391 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3392 (UINT32_C(0x5) << 1)
3393 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3394 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3395 /* unused5 is 16 b */
3398 * This is the opaque value that was completed for the TPA start
3399 * completion that corresponds to this TPA end completion.
3401 uint32_t start_opaque;
3402 } __attribute__((packed));
3404 /* rx_abuf_cmpl (size:128b/16B) */
3405 struct rx_abuf_cmpl {
3408 * This field indicates the exact type of the completion.
3409 * By convention, the LSB identifies the length of the
3410 * record in 16B units. Even values indicate 16B
3411 * records. Odd values indicate 32B
3414 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
3415 #define RX_ABUF_CMPL_TYPE_SFT 0
3417 * RX Aggregation Buffer completion :
3418 * Completion of an L2 aggregation buffer in support of
3419 * TPA, HDS, or Jumbo packet completion. Length = 16B
3421 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
3422 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
3424 * This is the length of the data for the packet stored in this
3425 * aggregation buffer identified by the opaque value. This does not
3426 * include the length of any
3427 * data placed in other aggregation BDs or in the packet or buffer
3428 * BDs. This length does not include any space added due to
3429 * hdr_offset register during HDS placement mode.
3433 * This is a copy of the opaque field from the RX BD this aggregation
3434 * buffer corresponds to.
3439 * This value is written by the NIC such that it will be different
3440 * for each pass through the completion queue. The even passes
3441 * will write 1. The odd passes will write 0.
3443 #define RX_ABUF_CMPL_V UINT32_C(0x1)
3444 /* unused3 is 32 b */
3446 } __attribute__((packed));
3448 /* eject_cmpl (size:128b/16B) */
3452 * This field indicates the exact type of the completion.
3453 * By convention, the LSB identifies the length of the
3454 * record in 16B units. Even values indicate 16B
3455 * records. Odd values indicate 32B
3458 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
3459 #define EJECT_CMPL_TYPE_SFT 0
3461 * Statistics Ejection Completion:
3462 * Completion of statistics data ejection buffer.
3465 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
3466 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
3467 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3468 #define EJECT_CMPL_FLAGS_SFT 6
3470 * When this bit is '1', it indicates a packet that has an
3471 * error of some type. Type of error is indicated in
3474 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
3476 * This is the length of the statistics data stored in this
3481 * This is a copy of the opaque field from the RX BD this ejection
3482 * buffer corresponds to.
3487 * This value is written by the NIC such that it will be different
3488 * for each pass through the completion queue. The even passes
3489 * will write 1. The odd passes will write 0.
3491 #define EJECT_CMPL_V UINT32_C(0x1)
3492 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3493 #define EJECT_CMPL_ERRORS_SFT 1
3495 * This error indicates that there was some sort of problem with
3496 * the BDs for statistics ejection. The statistics ejection should
3497 * be treated as invalid
3499 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3500 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3501 /* No buffer error */
3502 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3503 (UINT32_C(0x0) << 1)
3506 * Statistics did not fit into aggregation buffer provided.
3508 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3509 (UINT32_C(0x1) << 1)
3512 * BDs were not formatted correctly.
3514 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3515 (UINT32_C(0x3) << 1)
3518 * There was a bad_format error on the previous operation
3520 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3521 (UINT32_C(0x5) << 1)
3522 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3523 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3524 /* reserved16 is 16 b */
3525 uint16_t reserved16;
3526 /* unused3 is 32 b */
3528 } __attribute__((packed));
3530 /* hwrm_cmpl (size:128b/16B) */
3534 * This field indicates the exact type of the completion.
3535 * By convention, the LSB identifies the length of the
3536 * record in 16B units. Even values indicate 16B
3537 * records. Odd values indicate 32B
3540 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3541 #define HWRM_CMPL_TYPE_SFT 0
3543 * HWRM Command Completion:
3544 * Completion of an HWRM command.
3546 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3547 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3548 /* This is the sequence_id of the HWRM command that has completed. */
3549 uint16_t sequence_id;
3550 /* unused2 is 32 b */
3554 * This value is written by the NIC such that it will be different
3555 * for each pass through the completion queue. The even passes
3556 * will write 1. The odd passes will write 0.
3558 #define HWRM_CMPL_V UINT32_C(0x1)
3559 /* unused4 is 32 b */
3561 } __attribute__((packed));
3563 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3564 struct hwrm_fwd_req_cmpl {
3566 * This field indicates the exact type of the completion.
3567 * By convention, the LSB identifies the length of the
3568 * record in 16B units. Even values indicate 16B
3569 * records. Odd values indicate 32B
3572 uint16_t req_len_type;
3574 * This field indicates the exact type of the completion.
3575 * By convention, the LSB identifies the length of the
3576 * record in 16B units. Even values indicate 16B
3577 * records. Odd values indicate 32B
3580 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3581 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3582 /* Forwarded HWRM Request */
3583 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3584 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3585 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3586 /* Length of forwarded request in bytes. */
3587 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3588 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3590 * Source ID of this request.
3591 * Typically used in forwarding requests and responses.
3592 * 0x0 - 0xFFF8 - Used for function ids
3593 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3597 /* unused1 is 32 b */
3599 /* Address of forwarded request. */
3600 uint32_t req_buf_addr_v[2];
3602 * This value is written by the NIC such that it will be different
3603 * for each pass through the completion queue. The even passes
3604 * will write 1. The odd passes will write 0.
3606 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3607 /* Address of forwarded request. */
3608 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3609 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3610 } __attribute__((packed));
3612 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3613 struct hwrm_fwd_resp_cmpl {
3616 * This field indicates the exact type of the completion.
3617 * By convention, the LSB identifies the length of the
3618 * record in 16B units. Even values indicate 16B
3619 * records. Odd values indicate 32B
3622 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3623 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3624 /* Forwarded HWRM Response */
3625 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3626 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3627 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3629 * Source ID of this response.
3630 * Typically used in forwarding requests and responses.
3631 * 0x0 - 0xFFF8 - Used for function ids
3632 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3636 /* Length of forwarded response in bytes. */
3638 /* unused2 is 16 b */
3640 /* Address of forwarded request. */
3641 uint32_t resp_buf_addr_v[2];
3643 * This value is written by the NIC such that it will be different
3644 * for each pass through the completion queue. The even passes
3645 * will write 1. The odd passes will write 0.
3647 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3648 /* Address of forwarded request. */
3649 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3650 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3651 } __attribute__((packed));
3653 /* hwrm_async_event_cmpl (size:128b/16B) */
3654 struct hwrm_async_event_cmpl {
3657 * This field indicates the exact type of the completion.
3658 * By convention, the LSB identifies the length of the
3659 * record in 16B units. Even values indicate 16B
3660 * records. Odd values indicate 32B
3663 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3664 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3665 /* HWRM Asynchronous Event Information */
3666 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3667 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3668 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3669 /* Identifiers of events. */
3671 /* Link status changed */
3672 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3674 /* Link MTU changed */
3675 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3677 /* Link speed changed */
3678 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3680 /* DCB Configuration changed */
3681 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3683 /* Port connection not allowed */
3684 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3686 /* Link speed configuration was not allowed */
3687 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3689 /* Link speed configuration change */
3690 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3692 /* Port PHY configuration change */
3693 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3695 /* Reset notification to clients */
3696 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
3698 /* Function driver unloaded */
3699 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3701 /* Function driver loaded */
3702 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3704 /* Function FLR related processing has completed */
3705 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3707 /* PF driver unloaded */
3708 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3710 /* PF driver loaded */
3711 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3713 /* VF Function Level Reset (FLR) */
3714 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3716 /* VF MAC Address Change */
3717 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3719 /* PF-VF communication channel status change. */
3720 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3722 /* VF Configuration Change */
3723 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3725 /* LLFC/PFC Configuration Change */
3726 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3728 /* Default VNIC Configuration Change */
3729 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
3732 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
3735 * A debug notification being posted to the driver. These
3736 * notifications are purely for diagnostic purpose and should not be
3737 * used for functional purpose. The driver is not supposed to act
3738 * on these messages except to log/record it.
3740 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
3743 * A trace log message. This contains firmware trace logs string
3744 * embedded in the asynchronous message. This is an experimental
3745 * event, not meant for production use at this time.
3747 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
3750 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3752 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3753 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3754 /* Event specific data */
3755 uint32_t event_data2;
3758 * This value is written by the NIC such that it will be different
3759 * for each pass through the completion queue. The even passes
3760 * will write 1. The odd passes will write 0.
3762 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3764 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3765 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3766 /* 8-lsb timestamp from POR (100-msec resolution) */
3767 uint8_t timestamp_lo;
3768 /* 16-lsb timestamp from POR (100-msec resolution) */
3769 uint16_t timestamp_hi;
3770 /* Event specific data */
3771 uint32_t event_data1;
3772 } __attribute__((packed));
3774 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3775 struct hwrm_async_event_cmpl_link_status_change {
3778 * This field indicates the exact type of the completion.
3779 * By convention, the LSB identifies the length of the
3780 * record in 16B units. Even values indicate 16B
3781 * records. Odd values indicate 32B
3784 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3786 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3787 /* HWRM Asynchronous Event Information */
3788 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3790 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3791 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3792 /* Identifiers of events. */
3794 /* Link status changed */
3795 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3797 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3798 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3799 /* Event specific data */
3800 uint32_t event_data2;
3803 * This value is written by the NIC such that it will be different
3804 * for each pass through the completion queue. The even passes
3805 * will write 1. The odd passes will write 0.
3807 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3810 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3812 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3813 /* 8-lsb timestamp from POR (100-msec resolution) */
3814 uint8_t timestamp_lo;
3815 /* 16-lsb timestamp from POR (100-msec resolution) */
3816 uint16_t timestamp_hi;
3817 /* Event specific data */
3818 uint32_t event_data1;
3819 /* Indicates link status change */
3820 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3823 * If this bit set to 0, then it indicates that the link
3824 * was up and it went down.
3826 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3829 * If this bit is set to 1, then it indicates that the link
3830 * was down and it went up.
3832 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3834 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3835 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3836 /* Indicates the physical port this link status change occur */
3837 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3839 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3842 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3844 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3846 /* Indicates the physical function this event occurred on. */
3847 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
3849 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
3851 } __attribute__((packed));
3853 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
3854 struct hwrm_async_event_cmpl_link_mtu_change {
3857 * This field indicates the exact type of the completion.
3858 * By convention, the LSB identifies the length of the
3859 * record in 16B units. Even values indicate 16B
3860 * records. Odd values indicate 32B
3863 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
3865 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
3866 /* HWRM Asynchronous Event Information */
3867 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3869 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
3870 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
3871 /* Identifiers of events. */
3873 /* Link MTU changed */
3874 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
3876 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
3877 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
3878 /* Event specific data */
3879 uint32_t event_data2;
3882 * This value is written by the NIC such that it will be different
3883 * for each pass through the completion queue. The even passes
3884 * will write 1. The odd passes will write 0.
3886 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
3888 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
3890 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
3891 /* 8-lsb timestamp from POR (100-msec resolution) */
3892 uint8_t timestamp_lo;
3893 /* 16-lsb timestamp from POR (100-msec resolution) */
3894 uint16_t timestamp_hi;
3895 /* Event specific data */
3896 uint32_t event_data1;
3897 /* The new MTU of the link in bytes. */
3898 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
3900 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
3901 } __attribute__((packed));
3903 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
3904 struct hwrm_async_event_cmpl_link_speed_change {
3907 * This field indicates the exact type of the completion.
3908 * By convention, the LSB identifies the length of the
3909 * record in 16B units. Even values indicate 16B
3910 * records. Odd values indicate 32B
3913 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
3915 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
3916 /* HWRM Asynchronous Event Information */
3917 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3919 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
3920 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
3921 /* Identifiers of events. */
3923 /* Link speed changed */
3924 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
3926 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
3927 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
3928 /* Event specific data */
3929 uint32_t event_data2;
3932 * This value is written by the NIC such that it will be different
3933 * for each pass through the completion queue. The even passes
3934 * will write 1. The odd passes will write 0.
3936 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
3939 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
3941 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
3942 /* 8-lsb timestamp from POR (100-msec resolution) */
3943 uint8_t timestamp_lo;
3944 /* 16-lsb timestamp from POR (100-msec resolution) */
3945 uint16_t timestamp_hi;
3946 /* Event specific data */
3947 uint32_t event_data1;
3949 * When this bit is '1', the link was forced to the
3950 * force_link_speed value.
3952 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
3954 /* The new link speed in 100 Mbps units. */
3955 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
3957 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
3959 /* 100Mb link speed */
3960 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
3961 (UINT32_C(0x1) << 1)
3962 /* 1Gb link speed */
3963 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
3964 (UINT32_C(0xa) << 1)
3965 /* 2Gb link speed */
3966 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
3967 (UINT32_C(0x14) << 1)
3968 /* 25Gb link speed */
3969 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
3970 (UINT32_C(0x19) << 1)
3971 /* 10Gb link speed */
3972 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
3973 (UINT32_C(0x64) << 1)
3974 /* 20Mb link speed */
3975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
3976 (UINT32_C(0xc8) << 1)
3977 /* 25Gb link speed */
3978 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
3979 (UINT32_C(0xfa) << 1)
3980 /* 40Gb link speed */
3981 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
3982 (UINT32_C(0x190) << 1)
3983 /* 50Gb link speed */
3984 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
3985 (UINT32_C(0x1f4) << 1)
3986 /* 100Gb link speed */
3987 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
3988 (UINT32_C(0x3e8) << 1)
3989 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
3990 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
3992 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3993 UINT32_C(0xffff0000)
3994 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3996 } __attribute__((packed));
3998 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
3999 struct hwrm_async_event_cmpl_dcb_config_change {
4002 * This field indicates the exact type of the completion.
4003 * By convention, the LSB identifies the length of the
4004 * record in 16B units. Even values indicate 16B
4005 * records. Odd values indicate 32B
4008 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4010 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4011 /* HWRM Asynchronous Event Information */
4012 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4014 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4015 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4016 /* Identifiers of events. */
4018 /* DCB Configuration changed */
4019 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4021 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4022 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4023 /* Event specific data */
4024 uint32_t event_data2;
4025 /* ETS configuration change */
4026 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4028 /* PFC configuration change */
4029 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4031 /* APP configuration change */
4032 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4036 * This value is written by the NIC such that it will be different
4037 * for each pass through the completion queue. The even passes
4038 * will write 1. The odd passes will write 0.
4040 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4043 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4045 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4046 /* 8-lsb timestamp from POR (100-msec resolution) */
4047 uint8_t timestamp_lo;
4048 /* 16-lsb timestamp from POR (100-msec resolution) */
4049 uint16_t timestamp_hi;
4050 /* Event specific data */
4051 uint32_t event_data1;
4053 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4055 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4057 /* Priority recommended for RoCE traffic */
4058 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4060 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4063 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4064 (UINT32_C(0xff) << 16)
4065 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4066 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4067 /* Priority recommended for L2 traffic */
4068 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4069 UINT32_C(0xff000000)
4070 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4073 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4074 (UINT32_C(0xff) << 24)
4075 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4076 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4077 } __attribute__((packed));
4079 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4080 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4083 * This field indicates the exact type of the completion.
4084 * By convention, the LSB identifies the length of the
4085 * record in 16B units. Even values indicate 16B
4086 * records. Odd values indicate 32B
4089 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4091 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4093 /* HWRM Asynchronous Event Information */
4094 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4096 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4097 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4098 /* Identifiers of events. */
4100 /* Port connection not allowed */
4101 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4103 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4104 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4105 /* Event specific data */
4106 uint32_t event_data2;
4109 * This value is written by the NIC such that it will be different
4110 * for each pass through the completion queue. The even passes
4111 * will write 1. The odd passes will write 0.
4113 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4116 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4118 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4119 /* 8-lsb timestamp from POR (100-msec resolution) */
4120 uint8_t timestamp_lo;
4121 /* 16-lsb timestamp from POR (100-msec resolution) */
4122 uint16_t timestamp_hi;
4123 /* Event specific data */
4124 uint32_t event_data1;
4126 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4128 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4131 * This value indicates the current port level enforcement policy
4132 * for the optics module when there is an optical module mismatch
4133 * and port is not connected.
4135 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4137 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4139 /* No enforcement */
4140 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4141 (UINT32_C(0x0) << 16)
4142 /* Disable Transmit side Laser. */
4143 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4144 (UINT32_C(0x1) << 16)
4145 /* Raise a warning message. */
4146 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4147 (UINT32_C(0x2) << 16)
4148 /* Power down the module. */
4149 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4150 (UINT32_C(0x3) << 16)
4151 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4152 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4153 } __attribute__((packed));
4155 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4156 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4159 * This field indicates the exact type of the completion.
4160 * By convention, the LSB identifies the length of the
4161 * record in 16B units. Even values indicate 16B
4162 * records. Odd values indicate 32B
4165 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4167 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4169 /* HWRM Asynchronous Event Information */
4170 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4172 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4173 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4174 /* Identifiers of events. */
4176 /* Link speed configuration was not allowed */
4177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4180 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4181 /* Event specific data */
4182 uint32_t event_data2;
4185 * This value is written by the NIC such that it will be different
4186 * for each pass through the completion queue. The even passes
4187 * will write 1. The odd passes will write 0.
4189 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4195 /* 8-lsb timestamp from POR (100-msec resolution) */
4196 uint8_t timestamp_lo;
4197 /* 16-lsb timestamp from POR (100-msec resolution) */
4198 uint16_t timestamp_hi;
4199 /* Event specific data */
4200 uint32_t event_data1;
4202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4206 } __attribute__((packed));
4208 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4209 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4212 * This field indicates the exact type of the completion.
4213 * By convention, the LSB identifies the length of the
4214 * record in 16B units. Even values indicate 16B
4215 * records. Odd values indicate 32B
4218 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4220 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4222 /* HWRM Asynchronous Event Information */
4223 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4225 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4226 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4227 /* Identifiers of events. */
4229 /* Link speed configuration change */
4230 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4232 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4233 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4234 /* Event specific data */
4235 uint32_t event_data2;
4238 * This value is written by the NIC such that it will be different
4239 * for each pass through the completion queue. The even passes
4240 * will write 1. The odd passes will write 0.
4242 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
4245 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
4247 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
4248 /* 8-lsb timestamp from POR (100-msec resolution) */
4249 uint8_t timestamp_lo;
4250 /* 16-lsb timestamp from POR (100-msec resolution) */
4251 uint16_t timestamp_hi;
4252 /* Event specific data */
4253 uint32_t event_data1;
4255 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4257 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4260 * If set to 1, it indicates that the supported link speeds
4261 * configuration on the port has changed.
4262 * If set to 0, then there is no change in supported link speeds
4265 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
4268 * If set to 1, it indicates that the link speed configuration
4269 * on the port has become illegal or invalid.
4270 * If set to 0, then the link speed configuration on the port is
4273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
4275 } __attribute__((packed));
4277 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
4278 struct hwrm_async_event_cmpl_port_phy_cfg_change {
4281 * This field indicates the exact type of the completion.
4282 * By convention, the LSB identifies the length of the
4283 * record in 16B units. Even values indicate 16B
4284 * records. Odd values indicate 32B
4287 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
4289 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
4291 /* HWRM Asynchronous Event Information */
4292 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4294 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
4295 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4296 /* Identifiers of events. */
4298 /* Port PHY configuration change */
4299 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
4301 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
4302 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
4303 /* Event specific data */
4304 uint32_t event_data2;
4307 * This value is written by the NIC such that it will be different
4308 * for each pass through the completion queue. The even passes
4309 * will write 1. The odd passes will write 0.
4311 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
4314 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
4316 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
4317 /* 8-lsb timestamp from POR (100-msec resolution) */
4318 uint8_t timestamp_lo;
4319 /* 16-lsb timestamp from POR (100-msec resolution) */
4320 uint16_t timestamp_hi;
4321 /* Event specific data */
4322 uint32_t event_data1;
4324 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4326 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4329 * If set to 1, it indicates that the FEC
4330 * configuration on the port has changed.
4331 * If set to 0, then there is no change in FEC configuration.
4333 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
4336 * If set to 1, it indicates that the EEE configuration
4337 * on the port has changed.
4338 * If set to 0, then there is no change in EEE configuration
4341 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
4344 * If set to 1, it indicates that the pause configuration
4345 * on the PHY has changed.
4346 * If set to 0, then there is no change in the pause
4347 * configuration on the PHY.
4349 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
4351 } __attribute__((packed));
4353 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
4354 struct hwrm_async_event_cmpl_reset_notify {
4357 * This field indicates the exact type of the completion.
4358 * By convention, the LSB identifies the length of the
4359 * record in 16B units. Even values indicate 16B
4360 * records. Odd values indicate 32B
4363 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
4365 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
4366 /* HWRM Asynchronous Event Information */
4367 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
4369 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
4370 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
4371 /* Identifiers of events. */
4373 /* Notify clients of imminent reset. */
4374 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
4376 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
4377 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
4378 /* Event specific data */
4379 uint32_t event_data2;
4382 * This value is written by the NIC such that it will be different
4383 * for each pass through the completion queue. The even passes
4384 * will write 1. The odd passes will write 0.
4386 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
4388 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
4389 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
4391 * 8-lsb timestamp (100-msec resolution)
4392 * The Minimum time required for the Firmware readiness after sending this
4393 * notification to the driver instances.
4395 uint8_t timestamp_lo;
4397 * 16-lsb timestamp (100-msec resolution)
4398 * The Maximum Firmware Reset bail out value in the order of 100
4399 * milli seconds. The driver instances will use this value to re-initiate the
4400 * registration process again if the core firmware didn’t set the ready
4403 uint16_t timestamp_hi;
4404 /* Event specific data */
4405 uint32_t event_data1;
4406 /* Indicates driver action requested */
4407 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
4409 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
4412 * If set to 1, it indicates that the l2 client should
4413 * stop sending in band traffic to Nitro.
4414 * if set to 0, there is no change in L2 client behavior.
4416 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
4419 * If set to 1, it indicates that the L2 client should
4420 * bring down the interface.
4421 * If set to 0, then there is no change in L2 client behavior.
4423 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
4425 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
4426 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
4427 /* Indicates reason for reset. */
4428 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
4430 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
4432 /* A management client has requested reset. */
4433 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
4434 (UINT32_C(0x1) << 8)
4435 /* A fatal firmware exception has occurred. */
4436 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
4437 (UINT32_C(0x2) << 8)
4438 /* A non-fatal firmware exception has occurred. */
4439 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
4440 (UINT32_C(0x3) << 8)
4441 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
4442 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
4444 * Minimum time before driver should attempt access - units 100ms ticks.
4447 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
4448 UINT32_C(0xffff0000)
4449 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
4451 } __attribute__((packed));
4453 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
4454 struct hwrm_async_event_cmpl_func_drvr_unload {
4457 * This field indicates the exact type of the completion.
4458 * By convention, the LSB identifies the length of the
4459 * record in 16B units. Even values indicate 16B
4460 * records. Odd values indicate 32B
4463 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
4465 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
4466 /* HWRM Asynchronous Event Information */
4467 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4469 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
4470 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4471 /* Identifiers of events. */
4473 /* Function driver unloaded */
4474 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
4476 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
4477 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
4478 /* Event specific data */
4479 uint32_t event_data2;
4482 * This value is written by the NIC such that it will be different
4483 * for each pass through the completion queue. The even passes
4484 * will write 1. The odd passes will write 0.
4486 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
4488 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
4490 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
4491 /* 8-lsb timestamp from POR (100-msec resolution) */
4492 uint8_t timestamp_lo;
4493 /* 16-lsb timestamp from POR (100-msec resolution) */
4494 uint16_t timestamp_hi;
4495 /* Event specific data */
4496 uint32_t event_data1;
4498 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4500 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
4502 } __attribute__((packed));
4504 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
4505 struct hwrm_async_event_cmpl_func_drvr_load {
4508 * This field indicates the exact type of the completion.
4509 * By convention, the LSB identifies the length of the
4510 * record in 16B units. Even values indicate 16B
4511 * records. Odd values indicate 32B
4514 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
4516 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
4517 /* HWRM Asynchronous Event Information */
4518 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4520 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
4521 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4522 /* Identifiers of events. */
4524 /* Function driver loaded */
4525 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
4527 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
4528 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
4529 /* Event specific data */
4530 uint32_t event_data2;
4533 * This value is written by the NIC such that it will be different
4534 * for each pass through the completion queue. The even passes
4535 * will write 1. The odd passes will write 0.
4537 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
4539 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4540 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
4541 /* 8-lsb timestamp from POR (100-msec resolution) */
4542 uint8_t timestamp_lo;
4543 /* 16-lsb timestamp from POR (100-msec resolution) */
4544 uint16_t timestamp_hi;
4545 /* Event specific data */
4546 uint32_t event_data1;
4548 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4550 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4551 } __attribute__((packed));
4553 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
4554 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
4557 * This field indicates the exact type of the completion.
4558 * By convention, the LSB identifies the length of the
4559 * record in 16B units. Even values indicate 16B
4560 * records. Odd values indicate 32B
4563 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
4565 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
4567 /* HWRM Asynchronous Event Information */
4568 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
4570 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
4571 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
4572 /* Identifiers of events. */
4574 /* Function FLR related processing has completed */
4575 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4577 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
4578 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
4579 /* Event specific data */
4580 uint32_t event_data2;
4583 * This value is written by the NIC such that it will be different
4584 * for each pass through the completion queue. The even passes
4585 * will write 1. The odd passes will write 0.
4587 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
4590 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
4592 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
4593 /* 8-lsb timestamp from POR (100-msec resolution) */
4594 uint8_t timestamp_lo;
4595 /* 16-lsb timestamp from POR (100-msec resolution) */
4596 uint16_t timestamp_hi;
4597 /* Event specific data */
4598 uint32_t event_data1;
4600 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
4602 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
4604 } __attribute__((packed));
4606 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
4607 struct hwrm_async_event_cmpl_pf_drvr_unload {
4610 * This field indicates the exact type of the completion.
4611 * By convention, the LSB identifies the length of the
4612 * record in 16B units. Even values indicate 16B
4613 * records. Odd values indicate 32B
4616 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
4618 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
4619 /* HWRM Asynchronous Event Information */
4620 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4622 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
4623 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4624 /* Identifiers of events. */
4626 /* PF driver unloaded */
4627 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
4629 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
4630 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
4631 /* Event specific data */
4632 uint32_t event_data2;
4635 * This value is written by the NIC such that it will be different
4636 * for each pass through the completion queue. The even passes
4637 * will write 1. The odd passes will write 0.
4639 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
4641 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
4642 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
4643 /* 8-lsb timestamp from POR (100-msec resolution) */
4644 uint8_t timestamp_lo;
4645 /* 16-lsb timestamp from POR (100-msec resolution) */
4646 uint16_t timestamp_hi;
4647 /* Event specific data */
4648 uint32_t event_data1;
4650 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4652 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
4653 /* Indicates the physical port this pf belongs to */
4654 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
4656 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
4657 } __attribute__((packed));
4659 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
4660 struct hwrm_async_event_cmpl_pf_drvr_load {
4663 * This field indicates the exact type of the completion.
4664 * By convention, the LSB identifies the length of the
4665 * record in 16B units. Even values indicate 16B
4666 * records. Odd values indicate 32B
4669 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4671 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4672 /* HWRM Asynchronous Event Information */
4673 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4675 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4676 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4677 /* Identifiers of events. */
4679 /* PF driver loaded */
4680 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4682 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4683 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4684 /* Event specific data */
4685 uint32_t event_data2;
4688 * This value is written by the NIC such that it will be different
4689 * for each pass through the completion queue. The even passes
4690 * will write 1. The odd passes will write 0.
4692 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4694 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4695 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4696 /* 8-lsb timestamp from POR (100-msec resolution) */
4697 uint8_t timestamp_lo;
4698 /* 16-lsb timestamp from POR (100-msec resolution) */
4699 uint16_t timestamp_hi;
4700 /* Event specific data */
4701 uint32_t event_data1;
4703 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4705 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4706 /* Indicates the physical port this pf belongs to */
4707 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4709 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4710 } __attribute__((packed));
4712 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4713 struct hwrm_async_event_cmpl_vf_flr {
4716 * This field indicates the exact type of the completion.
4717 * By convention, the LSB identifies the length of the
4718 * record in 16B units. Even values indicate 16B
4719 * records. Odd values indicate 32B
4722 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4724 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4725 /* HWRM Asynchronous Event Information */
4726 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4728 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4729 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4730 /* Identifiers of events. */
4732 /* VF Function Level Reset (FLR) */
4733 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4734 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4735 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4736 /* Event specific data */
4737 uint32_t event_data2;
4740 * This value is written by the NIC such that it will be different
4741 * for each pass through the completion queue. The even passes
4742 * will write 1. The odd passes will write 0.
4744 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4746 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4747 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4748 /* 8-lsb timestamp from POR (100-msec resolution) */
4749 uint8_t timestamp_lo;
4750 /* 16-lsb timestamp from POR (100-msec resolution) */
4751 uint16_t timestamp_hi;
4752 /* Event specific data */
4753 uint32_t event_data1;
4755 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4757 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
4758 /* Indicates the physical function this event occurred on. */
4759 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
4761 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
4762 } __attribute__((packed));
4764 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
4765 struct hwrm_async_event_cmpl_vf_mac_addr_change {
4768 * This field indicates the exact type of the completion.
4769 * By convention, the LSB identifies the length of the
4770 * record in 16B units. Even values indicate 16B
4771 * records. Odd values indicate 32B
4774 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
4776 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
4777 /* HWRM Asynchronous Event Information */
4778 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4780 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
4781 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
4782 /* Identifiers of events. */
4784 /* VF MAC Address Change */
4785 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
4787 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
4788 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
4789 /* Event specific data */
4790 uint32_t event_data2;
4793 * This value is written by the NIC such that it will be different
4794 * for each pass through the completion queue. The even passes
4795 * will write 1. The odd passes will write 0.
4797 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
4800 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
4802 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
4803 /* 8-lsb timestamp from POR (100-msec resolution) */
4804 uint8_t timestamp_lo;
4805 /* 16-lsb timestamp from POR (100-msec resolution) */
4806 uint16_t timestamp_hi;
4807 /* Event specific data */
4808 uint32_t event_data1;
4810 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
4812 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
4814 } __attribute__((packed));
4816 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
4817 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
4820 * This field indicates the exact type of the completion.
4821 * By convention, the LSB identifies the length of the
4822 * record in 16B units. Even values indicate 16B
4823 * records. Odd values indicate 32B
4826 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
4828 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
4830 /* HWRM Asynchronous Event Information */
4831 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4833 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
4834 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4835 /* Identifiers of events. */
4837 /* PF-VF communication channel status change. */
4838 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4840 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
4841 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
4842 /* Event specific data */
4843 uint32_t event_data2;
4846 * This value is written by the NIC such that it will be different
4847 * for each pass through the completion queue. The even passes
4848 * will write 1. The odd passes will write 0.
4850 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
4853 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
4855 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
4856 /* 8-lsb timestamp from POR (100-msec resolution) */
4857 uint8_t timestamp_lo;
4858 /* 16-lsb timestamp from POR (100-msec resolution) */
4859 uint16_t timestamp_hi;
4860 /* Event specific data */
4861 uint32_t event_data1;
4863 * If this bit is set to 1, then it indicates that the PF-VF
4864 * communication was lost and it is established.
4865 * If this bit set to 0, then it indicates that the PF-VF
4866 * communication was established and it is lost.
4868 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
4870 } __attribute__((packed));
4872 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
4873 struct hwrm_async_event_cmpl_vf_cfg_change {
4876 * This field indicates the exact type of the completion.
4877 * By convention, the LSB identifies the length of the
4878 * record in 16B units. Even values indicate 16B
4879 * records. Odd values indicate 32B
4882 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
4884 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
4885 /* HWRM Asynchronous Event Information */
4886 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4888 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
4889 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4890 /* Identifiers of events. */
4892 /* VF Configuration Change */
4893 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
4895 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
4896 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
4897 /* Event specific data */
4898 uint32_t event_data2;
4901 * This value is written by the NIC such that it will be different
4902 * for each pass through the completion queue. The even passes
4903 * will write 1. The odd passes will write 0.
4905 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
4907 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
4908 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
4909 /* 8-lsb timestamp from POR (100-msec resolution) */
4910 uint8_t timestamp_lo;
4911 /* 16-lsb timestamp from POR (100-msec resolution) */
4912 uint16_t timestamp_hi;
4914 * Each flag provided in this field indicates a specific VF
4915 * configuration change. At least one of these flags shall be set to 1
4916 * when an asynchronous event completion of this type is provided
4919 uint32_t event_data1;
4921 * If this bit is set to 1, then the value of MTU
4922 * was changed on this VF.
4923 * If set to 0, then this bit should be ignored.
4925 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
4928 * If this bit is set to 1, then the value of MRU
4929 * was changed on this VF.
4930 * If set to 0, then this bit should be ignored.
4932 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
4935 * If this bit is set to 1, then the value of default MAC
4936 * address was changed on this VF.
4937 * If set to 0, then this bit should be ignored.
4939 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
4942 * If this bit is set to 1, then the value of default VLAN
4943 * was changed on this VF.
4944 * If set to 0, then this bit should be ignored.
4946 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
4949 * If this bit is set to 1, then the value of trusted VF enable
4950 * was changed on this VF.
4951 * If set to 0, then this bit should be ignored.
4953 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
4955 } __attribute__((packed));
4957 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
4958 struct hwrm_async_event_cmpl_llfc_pfc_change {
4961 * This field indicates the exact type of the completion.
4962 * By convention, the LSB identifies the length of the
4963 * record in 16B units. Even values indicate 16B
4964 * records. Odd values indicate 32B
4967 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
4969 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
4970 /* HWRM Asynchronous Event Information */
4971 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4973 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
4974 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4975 /* unused1 is 10 b */
4976 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
4978 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
4979 /* Identifiers of events. */
4981 /* LLFC/PFC Configuration Change */
4982 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
4984 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
4985 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
4986 /* Event specific data */
4987 uint32_t event_data2;
4990 * This value is written by the NIC such that it will be different
4991 * for each pass through the completion queue. The even passes
4992 * will write 1. The odd passes will write 0.
4994 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
4996 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
4998 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
4999 /* 8-lsb timestamp from POR (100-msec resolution) */
5000 uint8_t timestamp_lo;
5001 /* 16-lsb timestamp from POR (100-msec resolution) */
5002 uint16_t timestamp_hi;
5003 /* Event specific data */
5004 uint32_t event_data1;
5005 /* Indicates llfc pfc status change */
5006 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5008 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5011 * If this field set to 1, then it indicates that llfc is
5014 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5017 * If this field is set to 2, then it indicates that pfc
5020 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5022 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5023 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5024 /* Indicates the physical port this llfc pfc change occur */
5025 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5027 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5030 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5032 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5034 } __attribute__((packed));
5036 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5037 struct hwrm_async_event_cmpl_default_vnic_change {
5040 * This field indicates the exact type of the completion.
5041 * By convention, the LSB identifies the length of the
5042 * record in 16B units. Even values indicate 16B
5043 * records. Odd values indicate 32B
5046 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5048 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5050 /* HWRM Asynchronous Event Information */
5051 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5053 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5054 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5055 /* unused1 is 10 b */
5056 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5058 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5060 /* Identifiers of events. */
5062 /* Notification of a default vnic allocaiton or free */
5063 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5065 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5066 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5067 /* Event specific data */
5068 uint32_t event_data2;
5071 * This value is written by the NIC such that it will be different
5072 * for each pass through the completion queue. The even passes
5073 * will write 1. The odd passes will write 0.
5075 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5078 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5080 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5081 /* 8-lsb timestamp from POR (100-msec resolution) */
5082 uint8_t timestamp_lo;
5083 /* 16-lsb timestamp from POR (100-msec resolution) */
5084 uint16_t timestamp_hi;
5085 /* Event specific data */
5086 uint32_t event_data1;
5087 /* Indicates default vnic configuration change */
5088 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5090 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5093 * If this field is set to 1, then it indicates that
5094 * a default VNIC has been allocate.
5096 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5099 * If this field is set to 2, then it indicates that
5100 * a default VNIC has been freed.
5102 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5104 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5105 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5106 /* Indicates the physical function this event occurred on. */
5107 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5109 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5111 /* Indicates the virtual function this event occurred on */
5112 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5114 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5116 } __attribute__((packed));
5118 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5119 struct hwrm_async_event_cmpl_hw_flow_aged {
5122 * This field indicates the exact type of the completion.
5123 * By convention, the LSB identifies the length of the
5124 * record in 16B units. Even values indicate 16B
5125 * records. Odd values indicate 32B
5128 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5130 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5131 /* HWRM Asynchronous Event Information */
5132 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5134 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5135 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5136 /* Identifiers of events. */
5138 /* Notification of a hw flow aged */
5139 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5141 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5142 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5143 /* Event specific data */
5144 uint32_t event_data2;
5147 * This value is written by the NIC such that it will be different
5148 * for each pass through the completion queue. The even passes
5149 * will write 1. The odd passes will write 0.
5151 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5153 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5154 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5155 /* 8-lsb timestamp from POR (100-msec resolution) */
5156 uint8_t timestamp_lo;
5157 /* 16-lsb timestamp from POR (100-msec resolution) */
5158 uint16_t timestamp_hi;
5159 /* Event specific data */
5160 uint32_t event_data1;
5161 /* Indicates flow ID this event occurred on. */
5162 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5163 UINT32_C(0x7fffffff)
5164 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5166 /* Indicates flow direction this event occurred on. */
5167 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5168 UINT32_C(0x80000000)
5170 * If this bit set to 0, then it indicates that the aged
5171 * event was rx flow.
5173 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
5174 (UINT32_C(0x0) << 31)
5176 * If this bit is set to 1, then it indicates that the aged
5177 * event was tx flow.
5179 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
5180 (UINT32_C(0x1) << 31)
5181 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
5182 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
5183 } __attribute__((packed));
5185 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
5186 struct hwrm_async_event_cmpl_hwrm_error {
5189 * This field indicates the exact type of the completion.
5190 * By convention, the LSB identifies the length of the
5191 * record in 16B units. Even values indicate 16B
5192 * records. Odd values indicate 32B
5195 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
5197 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
5198 /* HWRM Asynchronous Event Information */
5199 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
5201 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
5202 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
5203 /* Identifiers of events. */
5206 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
5208 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
5209 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
5210 /* Event specific data */
5211 uint32_t event_data2;
5212 /* Severity of HWRM Error */
5213 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
5215 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
5217 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
5219 /* Non-fatal Error */
5220 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
5223 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
5225 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
5226 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
5229 * This value is written by the NIC such that it will be different
5230 * for each pass through the completion queue. The even passes
5231 * will write 1. The odd passes will write 0.
5233 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
5235 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
5236 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
5237 /* 8-lsb timestamp from POR (100-msec resolution) */
5238 uint8_t timestamp_lo;
5239 /* 16-lsb timestamp from POR (100-msec resolution) */
5240 uint16_t timestamp_hi;
5241 /* Event specific data */
5242 uint32_t event_data1;
5243 /* Time stamp for error event */
5244 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
5246 } __attribute__((packed));
5248 /*******************
5250 *******************/
5253 /* hwrm_func_reset_input (size:192b/24B) */
5254 struct hwrm_func_reset_input {
5255 /* The HWRM command request type. */
5258 * The completion ring to send the completion event on. This should
5259 * be the NQ ID returned from the `nq_alloc` HWRM command.
5263 * The sequence ID is used by the driver for tracking multiple
5264 * commands. This ID is treated as opaque data by the firmware and
5265 * the value is returned in the `hwrm_resp_hdr` upon completion.
5269 * The target ID of the command:
5270 * * 0x0-0xFFF8 - The function ID
5271 * * 0xFFF8-0xFFFE - Reserved for internal processors
5276 * A physical address pointer pointing to a host buffer that the
5277 * command's response data will be written. This can be either a host
5278 * physical address (HPA) or a guest physical address (GPA) and must
5279 * point to a physically contiguous block of memory.
5284 * This bit must be '1' for the vf_id_valid field to be
5287 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
5289 * The ID of the VF that this PF is trying to reset.
5290 * Only the parent PF shall be allowed to reset a child VF.
5292 * A parent PF driver shall use this field only when a specific child VF
5293 * is requested to be reset.
5296 /* This value indicates the level of a function reset. */
5297 uint8_t func_reset_level;
5299 * Reset the caller function and its children VFs (if any). If no
5300 * children functions exist, then reset the caller function only.
5302 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
5304 /* Reset the caller function only */
5305 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
5308 * Reset all children VFs of the caller function driver if the
5309 * caller is a PF driver.
5310 * It is an error to specify this level by a VF driver.
5311 * It is an error to specify this level by a PF driver with
5314 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
5317 * Reset a specific VF of the caller function driver if the caller
5318 * is the parent PF driver.
5319 * It is an error to specify this level by a VF driver.
5320 * It is an error to specify this level by a PF driver that is not
5321 * the parent of the VF that is being requested to reset.
5323 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
5325 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
5326 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
5328 } __attribute__((packed));
5330 /* hwrm_func_reset_output (size:128b/16B) */
5331 struct hwrm_func_reset_output {
5332 /* The specific error status for the command. */
5333 uint16_t error_code;
5334 /* The HWRM command request type. */
5336 /* The sequence ID from the original command. */
5338 /* The length of the response data in number of bytes. */
5340 uint8_t unused_0[7];
5342 * This field is used in Output records to indicate that the output
5343 * is completely written to RAM. This field should be read as '1'
5344 * to indicate that the output has been completely written.
5345 * When writing a command completion or response to an internal processor,
5346 * the order of writes has to be such that this field is written last.
5349 } __attribute__((packed));
5351 /********************
5352 * hwrm_func_getfid *
5353 ********************/
5356 /* hwrm_func_getfid_input (size:192b/24B) */
5357 struct hwrm_func_getfid_input {
5358 /* The HWRM command request type. */
5361 * The completion ring to send the completion event on. This should
5362 * be the NQ ID returned from the `nq_alloc` HWRM command.
5366 * The sequence ID is used by the driver for tracking multiple
5367 * commands. This ID is treated as opaque data by the firmware and
5368 * the value is returned in the `hwrm_resp_hdr` upon completion.
5372 * The target ID of the command:
5373 * * 0x0-0xFFF8 - The function ID
5374 * * 0xFFF8-0xFFFE - Reserved for internal processors
5379 * A physical address pointer pointing to a host buffer that the
5380 * command's response data will be written. This can be either a host
5381 * physical address (HPA) or a guest physical address (GPA) and must
5382 * point to a physically contiguous block of memory.
5387 * This bit must be '1' for the pci_id field to be
5390 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
5392 * This value is the PCI ID of the queried function.
5393 * If ARI is enabled, then it is
5394 * Bus Number (8b):Function Number(8b). Otherwise, it is
5395 * Bus Number (8b):Device Number (5b):Function Number(3b).
5398 uint8_t unused_0[2];
5399 } __attribute__((packed));
5401 /* hwrm_func_getfid_output (size:128b/16B) */
5402 struct hwrm_func_getfid_output {
5403 /* The specific error status for the command. */
5404 uint16_t error_code;
5405 /* The HWRM command request type. */
5407 /* The sequence ID from the original command. */
5409 /* The length of the response data in number of bytes. */
5412 * FID value. This value is used to identify operations on the PCI
5413 * bus as belonging to a particular PCI function.
5416 uint8_t unused_0[5];
5418 * This field is used in Output records to indicate that the output
5419 * is completely written to RAM. This field should be read as '1'
5420 * to indicate that the output has been completely written.
5421 * When writing a command completion or response to an internal processor,
5422 * the order of writes has to be such that this field is written last.
5425 } __attribute__((packed));
5427 /**********************
5428 * hwrm_func_vf_alloc *
5429 **********************/
5432 /* hwrm_func_vf_alloc_input (size:192b/24B) */
5433 struct hwrm_func_vf_alloc_input {
5434 /* The HWRM command request type. */
5437 * The completion ring to send the completion event on. This should
5438 * be the NQ ID returned from the `nq_alloc` HWRM command.
5442 * The sequence ID is used by the driver for tracking multiple
5443 * commands. This ID is treated as opaque data by the firmware and
5444 * the value is returned in the `hwrm_resp_hdr` upon completion.
5448 * The target ID of the command:
5449 * * 0x0-0xFFF8 - The function ID
5450 * * 0xFFF8-0xFFFE - Reserved for internal processors
5455 * A physical address pointer pointing to a host buffer that the
5456 * command's response data will be written. This can be either a host
5457 * physical address (HPA) or a guest physical address (GPA) and must
5458 * point to a physically contiguous block of memory.
5463 * This bit must be '1' for the first_vf_id field to be
5466 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
5468 * This value is used to identify a Virtual Function (VF).
5469 * The scope of VF ID is local within a PF.
5471 uint16_t first_vf_id;
5472 /* The number of virtual functions requested. */
5474 } __attribute__((packed));
5476 /* hwrm_func_vf_alloc_output (size:128b/16B) */
5477 struct hwrm_func_vf_alloc_output {
5478 /* The specific error status for the command. */
5479 uint16_t error_code;
5480 /* The HWRM command request type. */
5482 /* The sequence ID from the original command. */
5484 /* The length of the response data in number of bytes. */
5486 /* The ID of the first VF allocated. */
5487 uint16_t first_vf_id;
5488 uint8_t unused_0[5];
5490 * This field is used in Output records to indicate that the output
5491 * is completely written to RAM. This field should be read as '1'
5492 * to indicate that the output has been completely written.
5493 * When writing a command completion or response to an internal processor,
5494 * the order of writes has to be such that this field is written last.
5497 } __attribute__((packed));
5499 /*********************
5500 * hwrm_func_vf_free *
5501 *********************/
5504 /* hwrm_func_vf_free_input (size:192b/24B) */
5505 struct hwrm_func_vf_free_input {
5506 /* The HWRM command request type. */
5509 * The completion ring to send the completion event on. This should
5510 * be the NQ ID returned from the `nq_alloc` HWRM command.
5514 * The sequence ID is used by the driver for tracking multiple
5515 * commands. This ID is treated as opaque data by the firmware and
5516 * the value is returned in the `hwrm_resp_hdr` upon completion.
5520 * The target ID of the command:
5521 * * 0x0-0xFFF8 - The function ID
5522 * * 0xFFF8-0xFFFE - Reserved for internal processors
5527 * A physical address pointer pointing to a host buffer that the
5528 * command's response data will be written. This can be either a host
5529 * physical address (HPA) or a guest physical address (GPA) and must
5530 * point to a physically contiguous block of memory.
5535 * This bit must be '1' for the first_vf_id field to be
5538 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
5540 * This value is used to identify a Virtual Function (VF).
5541 * The scope of VF ID is local within a PF.
5543 uint16_t first_vf_id;
5545 * The number of virtual functions requested.
5546 * 0xFFFF - Cleanup all children of this PF.
5549 } __attribute__((packed));
5551 /* hwrm_func_vf_free_output (size:128b/16B) */
5552 struct hwrm_func_vf_free_output {
5553 /* The specific error status for the command. */
5554 uint16_t error_code;
5555 /* The HWRM command request type. */
5557 /* The sequence ID from the original command. */
5559 /* The length of the response data in number of bytes. */
5561 uint8_t unused_0[7];
5563 * This field is used in Output records to indicate that the output
5564 * is completely written to RAM. This field should be read as '1'
5565 * to indicate that the output has been completely written.
5566 * When writing a command completion or response to an internal processor,
5567 * the order of writes has to be such that this field is written last.
5570 } __attribute__((packed));
5572 /********************
5573 * hwrm_func_vf_cfg *
5574 ********************/
5577 /* hwrm_func_vf_cfg_input (size:448b/56B) */
5578 struct hwrm_func_vf_cfg_input {
5579 /* The HWRM command request type. */
5582 * The completion ring to send the completion event on. This should
5583 * be the NQ ID returned from the `nq_alloc` HWRM command.
5587 * The sequence ID is used by the driver for tracking multiple
5588 * commands. This ID is treated as opaque data by the firmware and
5589 * the value is returned in the `hwrm_resp_hdr` upon completion.
5593 * The target ID of the command:
5594 * * 0x0-0xFFF8 - The function ID
5595 * * 0xFFF8-0xFFFE - Reserved for internal processors
5600 * A physical address pointer pointing to a host buffer that the
5601 * command's response data will be written. This can be either a host
5602 * physical address (HPA) or a guest physical address (GPA) and must
5603 * point to a physically contiguous block of memory.
5608 * This bit must be '1' for the mtu field to be
5611 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
5614 * This bit must be '1' for the guest_vlan field to be
5617 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
5620 * This bit must be '1' for the async_event_cr field to be
5623 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
5626 * This bit must be '1' for the dflt_mac_addr field to be
5629 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
5632 * This bit must be '1' for the num_rsscos_ctxs field to be
5635 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
5638 * This bit must be '1' for the num_cmpl_rings field to be
5641 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
5644 * This bit must be '1' for the num_tx_rings field to be
5647 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
5650 * This bit must be '1' for the num_rx_rings field to be
5653 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
5656 * This bit must be '1' for the num_l2_ctxs field to be
5659 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
5662 * This bit must be '1' for the num_vnics field to be
5665 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
5668 * This bit must be '1' for the num_stat_ctxs field to be
5671 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
5674 * This bit must be '1' for the num_hw_ring_grps field to be
5677 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
5680 * The maximum transmission unit requested on the function.
5681 * The HWRM should make sure that the mtu of
5682 * the function does not exceed the mtu of the physical
5683 * port that this function is associated with.
5685 * In addition to requesting mtu per function, it is
5686 * possible to configure mtu per transmit ring.
5687 * By default, the mtu of each transmit ring associated
5688 * with a function is equal to the mtu of the function.
5689 * The HWRM should make sure that the mtu of each transmit
5690 * ring that is assigned to a function has a valid mtu.
5694 * The guest VLAN for the function being configured.
5695 * This field's format is same as 802.1Q Tag's
5696 * Tag Control Information (TCI) format that includes both
5697 * Priority Code Point (PCP) and VLAN Identifier (VID).
5699 uint16_t guest_vlan;
5701 * ID of the target completion ring for receiving asynchronous
5702 * event completions. If this field is not valid, then the
5703 * HWRM shall use the default completion ring of the function
5704 * that is being configured as the target completion ring for
5705 * providing any asynchronous event completions for that
5707 * If this field is valid, then the HWRM shall use the
5708 * completion ring identified by this ID as the target
5709 * completion ring for providing any asynchronous event
5710 * completions for the function that is being configured.
5712 uint16_t async_event_cr;
5714 * This value is the current MAC address requested by the VF
5715 * driver to be configured on this VF. A value of
5716 * 00-00-00-00-00-00 indicates no MAC address configuration
5717 * is requested by the VF driver.
5718 * The parent PF driver may reject or overwrite this
5721 uint8_t dflt_mac_addr[6];
5724 * This bit requests that the firmware test to see if all the assets
5725 * requested in this command (i.e. number of TX rings) are available.
5726 * The firmware will return an error if the requested assets are
5727 * not available. The firwmare will NOT reserve the assets if they
5730 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
5733 * This bit requests that the firmware test to see if all the assets
5734 * requested in this command (i.e. number of RX rings) are available.
5735 * The firmware will return an error if the requested assets are
5736 * not available. The firwmare will NOT reserve the assets if they
5739 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
5742 * This bit requests that the firmware test to see if all the assets
5743 * requested in this command (i.e. number of CMPL rings) are available.
5744 * The firmware will return an error if the requested assets are
5745 * not available. The firwmare will NOT reserve the assets if they
5748 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
5751 * This bit requests that the firmware test to see if all the assets
5752 * requested in this command (i.e. number of RSS ctx) are available.
5753 * The firmware will return an error if the requested assets are
5754 * not available. The firwmare will NOT reserve the assets if they
5757 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
5760 * This bit requests that the firmware test to see if all the assets
5761 * requested in this command (i.e. number of ring groups) are available.
5762 * The firmware will return an error if the requested assets are
5763 * not available. The firwmare will NOT reserve the assets if they
5766 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
5769 * This bit requests that the firmware test to see if all the assets
5770 * requested in this command (i.e. number of stat ctx) are available.
5771 * The firmware will return an error if the requested assets are
5772 * not available. The firwmare will NOT reserve the assets if they
5775 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
5778 * This bit requests that the firmware test to see if all the assets
5779 * requested in this command (i.e. number of VNICs) are available.
5780 * The firmware will return an error if the requested assets are
5781 * not available. The firwmare will NOT reserve the assets if they
5784 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
5787 * This bit requests that the firmware test to see if all the assets
5788 * requested in this command (i.e. number of L2 ctx) are available.
5789 * The firmware will return an error if the requested assets are
5790 * not available. The firwmare will NOT reserve the assets if they
5793 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
5795 /* The number of RSS/COS contexts requested for the VF. */
5796 uint16_t num_rsscos_ctxs;
5797 /* The number of completion rings requested for the VF. */
5798 uint16_t num_cmpl_rings;
5799 /* The number of transmit rings requested for the VF. */
5800 uint16_t num_tx_rings;
5801 /* The number of receive rings requested for the VF. */
5802 uint16_t num_rx_rings;
5803 /* The number of L2 contexts requested for the VF. */
5804 uint16_t num_l2_ctxs;
5805 /* The number of vnics requested for the VF. */
5807 /* The number of statistic contexts requested for the VF. */
5808 uint16_t num_stat_ctxs;
5809 /* The number of HW ring groups requested for the VF. */
5810 uint16_t num_hw_ring_grps;
5811 uint8_t unused_0[4];
5812 } __attribute__((packed));
5814 /* hwrm_func_vf_cfg_output (size:128b/16B) */
5815 struct hwrm_func_vf_cfg_output {
5816 /* The specific error status for the command. */
5817 uint16_t error_code;
5818 /* The HWRM command request type. */
5820 /* The sequence ID from the original command. */
5822 /* The length of the response data in number of bytes. */
5824 uint8_t unused_0[7];
5826 * This field is used in Output records to indicate that the output
5827 * is completely written to RAM. This field should be read as '1'
5828 * to indicate that the output has been completely written.
5829 * When writing a command completion or response to an internal processor,
5830 * the order of writes has to be such that this field is written last.
5833 } __attribute__((packed));
5835 /*******************
5837 *******************/
5840 /* hwrm_func_qcaps_input (size:192b/24B) */
5841 struct hwrm_func_qcaps_input {
5842 /* The HWRM command request type. */
5845 * The completion ring to send the completion event on. This should
5846 * be the NQ ID returned from the `nq_alloc` HWRM command.
5850 * The sequence ID is used by the driver for tracking multiple
5851 * commands. This ID is treated as opaque data by the firmware and
5852 * the value is returned in the `hwrm_resp_hdr` upon completion.
5856 * The target ID of the command:
5857 * * 0x0-0xFFF8 - The function ID
5858 * * 0xFFF8-0xFFFE - Reserved for internal processors
5863 * A physical address pointer pointing to a host buffer that the
5864 * command's response data will be written. This can be either a host
5865 * physical address (HPA) or a guest physical address (GPA) and must
5866 * point to a physically contiguous block of memory.
5870 * Function ID of the function that is being queried.
5871 * 0xFF... (All Fs) if the query is for the requesting
5875 uint8_t unused_0[6];
5876 } __attribute__((packed));
5878 /* hwrm_func_qcaps_output (size:640b/80B) */
5879 struct hwrm_func_qcaps_output {
5880 /* The specific error status for the command. */
5881 uint16_t error_code;
5882 /* The HWRM command request type. */
5884 /* The sequence ID from the original command. */
5886 /* The length of the response data in number of bytes. */
5889 * FID value. This value is used to identify operations on the PCI
5890 * bus as belonging to a particular PCI function.
5894 * Port ID of port that this function is associated with.
5895 * Valid only for the PF.
5896 * 0xFF... (All Fs) if this function is not associated with
5898 * 0xFF... (All Fs) if this function is called from a VF.
5902 /* If 1, then Push mode is supported on this function. */
5903 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
5906 * If 1, then the global MSI-X auto-masking is enabled for the
5909 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
5912 * If 1, then the Precision Time Protocol (PTP) processing
5913 * is supported on this function.
5914 * The HWRM should enable PTP on only a single Physical
5915 * Function (PF) per port.
5917 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
5920 * If 1, then RDMA over Converged Ethernet (RoCE) v1
5921 * is supported on this function.
5923 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
5926 * If 1, then RDMA over Converged Ethernet (RoCE) v2
5927 * is supported on this function.
5929 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
5932 * If 1, then control and configuration of WoL magic packet
5933 * are supported on this function.
5935 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
5938 * If 1, then control and configuration of bitmap pattern
5939 * packet are supported on this function.
5941 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
5944 * If set to 1, then the control and configuration of rate limit
5945 * of an allocated TX ring on the queried function is supported.
5947 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
5950 * If 1, then control and configuration of minimum and
5951 * maximum bandwidths are supported on the queried function.
5953 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
5956 * If the query is for a VF, then this flag shall be ignored.
5957 * If this query is for a PF and this flag is set to 1,
5958 * then the PF has the capability to set the rate limits
5959 * on the TX rings of its children VFs.
5960 * If this query is for a PF and this flag is set to 0, then
5961 * the PF does not have the capability to set the rate limits
5962 * on the TX rings of its children VFs.
5964 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
5967 * If the query is for a VF, then this flag shall be ignored.
5968 * If this query is for a PF and this flag is set to 1,
5969 * then the PF has the capability to set the minimum and/or
5970 * maximum bandwidths for its children VFs.
5971 * If this query is for a PF and this flag is set to 0, then
5972 * the PF does not have the capability to set the minimum or
5973 * maximum bandwidths for its children VFs.
5975 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
5978 * Standard TX Ring mode is used for the allocation of TX ring
5979 * and underlying scheduling resources that allow bandwidth
5980 * reservation and limit settings on the queried function.
5981 * If set to 1, then standard TX ring mode is supported
5982 * on the queried function.
5983 * If set to 0, then standard TX ring mode is not available
5984 * on the queried function.
5986 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
5989 * If the query is for a VF, then this flag shall be ignored,
5990 * If this query is for a PF and this flag is set to 1,
5991 * then the PF has the capability to detect GENEVE tunnel
5994 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
5997 * If the query is for a VF, then this flag shall be ignored,
5998 * If this query is for a PF and this flag is set to 1,
5999 * then the PF has the capability to detect NVGRE tunnel
6002 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
6005 * If the query is for a VF, then this flag shall be ignored,
6006 * If this query is for a PF and this flag is set to 1,
6007 * then the PF has the capability to detect GRE tunnel
6010 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
6013 * If the query is for a VF, then this flag shall be ignored,
6014 * If this query is for a PF and this flag is set to 1,
6015 * then the PF has the capability to detect MPLS tunnel
6018 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
6021 * If the query is for a VF, then this flag shall be ignored,
6022 * If this query is for a PF and this flag is set to 1,
6023 * then the PF has the capability to support pcie stats.
6025 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
6028 * If the query is for a VF, then this flag shall be ignored,
6029 * If this query is for a PF and this flag is set to 1,
6030 * then the PF has the capability to adopt the VF's belonging
6033 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
6036 * If the query is for a VF, then this flag shall be ignored,
6037 * If this query is for a PF and this flag is set to 1,
6038 * then the PF has the administrative privilege to configure another PF
6040 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
6043 * If the query is for a VF, then this flag shall be ignored.
6044 * If this query is for a PF and this flag is set to 1, then
6045 * the PF will know that the firmware has the capability to track
6046 * the virtual link status.
6048 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
6051 * If 1, then this function supports the push mode that uses
6052 * write combine buffers and the long inline tx buffer descriptor.
6054 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
6057 * If 1, then FW has capability to allocate TX rings dynamically
6058 * in ring alloc even if PF reserved pool is zero.
6059 * This bit will be used only for PFs.
6061 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
6064 * When this bit is '1', it indicates that core firmware is
6065 * capable of Hot Reset.
6067 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
6070 * This value is current MAC address configured for this
6071 * function. A value of 00-00-00-00-00-00 indicates no
6072 * MAC address is currently configured.
6074 uint8_t mac_address[6];
6076 * The maximum number of RSS/COS contexts that can be
6077 * allocated to the function.
6079 uint16_t max_rsscos_ctx;
6081 * The maximum number of completion rings that can be
6082 * allocated to the function.
6084 uint16_t max_cmpl_rings;
6086 * The maximum number of transmit rings that can be
6087 * allocated to the function.
6089 uint16_t max_tx_rings;
6091 * The maximum number of receive rings that can be
6092 * allocated to the function.
6094 uint16_t max_rx_rings;
6096 * The maximum number of L2 contexts that can be
6097 * allocated to the function.
6099 uint16_t max_l2_ctxs;
6101 * The maximum number of VNICs that can be
6102 * allocated to the function.
6106 * The identifier for the first VF enabled on a PF. This
6107 * is valid only on the PF with SR-IOV enabled.
6108 * 0xFF... (All Fs) if this command is called on a PF with
6109 * SR-IOV disabled or on a VF.
6111 uint16_t first_vf_id;
6113 * The maximum number of VFs that can be
6114 * allocated to the function. This is valid only on the
6115 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
6116 * command is called on a PF with SR-IOV disabled or
6121 * The maximum number of statistic contexts that can be
6122 * allocated to the function.
6124 uint16_t max_stat_ctx;
6126 * The maximum number of Encapsulation records that can be
6127 * offloaded by this function.
6129 uint32_t max_encap_records;
6131 * The maximum number of decapsulation records that can
6132 * be offloaded by this function.
6134 uint32_t max_decap_records;
6136 * The maximum number of Exact Match (EM) flows that can be
6137 * offloaded by this function on the TX side.
6139 uint32_t max_tx_em_flows;
6141 * The maximum number of Wildcard Match (WM) flows that can
6142 * be offloaded by this function on the TX side.
6144 uint32_t max_tx_wm_flows;
6146 * The maximum number of Exact Match (EM) flows that can be
6147 * offloaded by this function on the RX side.
6149 uint32_t max_rx_em_flows;
6151 * The maximum number of Wildcard Match (WM) flows that can
6152 * be offloaded by this function on the RX side.
6154 uint32_t max_rx_wm_flows;
6156 * The maximum number of multicast filters that can
6157 * be supported by this function on the RX side.
6159 uint32_t max_mcast_filters;
6161 * The maximum value of flow_id that can be supported
6162 * in completion records.
6164 uint32_t max_flow_id;
6166 * The maximum number of HW ring groups that can be
6167 * supported on this function.
6169 uint32_t max_hw_ring_grps;
6171 * The maximum number of strict priority transmit rings
6172 * that can be allocated to the function.
6173 * This number indicates the maximum number of TX rings
6174 * that can be assigned strict priorities out of the
6175 * maximum number of TX rings that can be allocated
6176 * (max_tx_rings) to the function.
6178 uint16_t max_sp_tx_rings;
6181 * This field is used in Output records to indicate that the output
6182 * is completely written to RAM. This field should be read as '1'
6183 * to indicate that the output has been completely written.
6184 * When writing a command completion or response to an internal processor,
6185 * the order of writes has to be such that this field is written last.
6188 } __attribute__((packed));
6195 /* hwrm_func_qcfg_input (size:192b/24B) */
6196 struct hwrm_func_qcfg_input {
6197 /* The HWRM command request type. */
6200 * The completion ring to send the completion event on. This should
6201 * be the NQ ID returned from the `nq_alloc` HWRM command.
6205 * The sequence ID is used by the driver for tracking multiple
6206 * commands. This ID is treated as opaque data by the firmware and
6207 * the value is returned in the `hwrm_resp_hdr` upon completion.
6211 * The target ID of the command:
6212 * * 0x0-0xFFF8 - The function ID
6213 * * 0xFFF8-0xFFFE - Reserved for internal processors
6218 * A physical address pointer pointing to a host buffer that the
6219 * command's response data will be written. This can be either a host
6220 * physical address (HPA) or a guest physical address (GPA) and must
6221 * point to a physically contiguous block of memory.
6225 * Function ID of the function that is being queried.
6226 * 0xFF... (All Fs) if the query is for the requesting
6230 uint8_t unused_0[6];
6231 } __attribute__((packed));
6233 /* hwrm_func_qcfg_output (size:704b/88B) */
6234 struct hwrm_func_qcfg_output {
6235 /* The specific error status for the command. */
6236 uint16_t error_code;
6237 /* The HWRM command request type. */
6239 /* The sequence ID from the original command. */
6241 /* The length of the response data in number of bytes. */
6244 * FID value. This value is used to identify operations on the PCI
6245 * bus as belonging to a particular PCI function.
6249 * Port ID of port that this function is associated with.
6250 * 0xFF... (All Fs) if this function is not associated with
6255 * This value is the current VLAN setting for this
6256 * function. The value of 0 for this field indicates
6257 * no priority tagging or VLAN is used.
6258 * This field's format is same as 802.1Q Tag's
6259 * Tag Control Information (TCI) format that includes both
6260 * Priority Code Point (PCP) and VLAN Identifier (VID).
6265 * If 1, then magic packet based Out-Of-Box WoL is enabled on
6266 * the port associated with this function.
6268 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
6271 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
6272 * on the port associated with this function.
6274 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
6277 * If set to 1, then FW based DCBX agent is enabled and running on
6278 * the port associated with this function.
6279 * If set to 0, then DCBX agent is not running in the firmware.
6281 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
6284 * Standard TX Ring mode is used for the allocation of TX ring
6285 * and underlying scheduling resources that allow bandwidth
6286 * reservation and limit settings on the queried function.
6287 * If set to 1, then standard TX ring mode is enabled
6288 * on the queried function.
6289 * If set to 0, then the standard TX ring mode is disabled
6290 * on the queried function. In this extended TX ring resource
6291 * mode, the minimum and maximum bandwidth settings are not
6292 * supported to allow the allocation of TX rings to span multiple
6295 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
6298 * If set to 1 then FW based LLDP agent is enabled and running on
6299 * the port associated with this function.
6300 * If set to 0 then the LLDP agent is not running in the firmware.
6302 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
6305 * If set to 1, then multi-host mode is active for this function.
6306 * If set to 0, then multi-host mode is inactive for this function
6307 * or not applicable for this device.
6309 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
6312 * If the function that is being queried is a PF, then the HWRM shall
6313 * set this field to 0 and the HWRM client shall ignore this field.
6314 * If the function that is being queried is a VF, then the HWRM shall
6315 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
6316 * shall set this field to 0.
6318 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
6321 * If set to 1, then secure mode is enabled for this function or device.
6322 * If set to 0, then secure mode is disabled (or normal mode) for this
6323 * function or device.
6325 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
6328 * This value is current MAC address configured for this
6329 * function. A value of 00-00-00-00-00-00 indicates no
6330 * MAC address is currently configured.
6332 uint8_t mac_address[6];
6334 * This value is current PCI ID of this
6335 * function. If ARI is enabled, then it is
6336 * Bus Number (8b):Function Number(8b). Otherwise, it is
6337 * Bus Number (8b):Device Number (4b):Function Number(4b).
6338 * If multi-host mode is active, the 4 lsb will indicate
6339 * the PF index for this function.
6343 * The number of RSS/COS contexts currently
6344 * allocated to the function.
6346 uint16_t alloc_rsscos_ctx;
6348 * The number of completion rings currently allocated to
6349 * the function. This does not include the rings allocated
6350 * to any children functions if any.
6352 uint16_t alloc_cmpl_rings;
6354 * The number of transmit rings currently allocated to
6355 * the function. This does not include the rings allocated
6356 * to any children functions if any.
6358 uint16_t alloc_tx_rings;
6360 * The number of receive rings currently allocated to
6361 * the function. This does not include the rings allocated
6362 * to any children functions if any.
6364 uint16_t alloc_rx_rings;
6365 /* The allocated number of L2 contexts to the function. */
6366 uint16_t alloc_l2_ctx;
6367 /* The allocated number of vnics to the function. */
6368 uint16_t alloc_vnics;
6370 * The maximum transmission unit of the function.
6371 * If the reported mtu value is non-zero then it will used for the
6372 * rings allocated on this function. otherwise the default
6373 * value is used if ring MTU is not specified.
6377 * The maximum receive unit of the function.
6378 * For vnics allocated on this function, this default
6379 * value is used if vnic MRU is not specified.
6382 /* The statistics context assigned to a function. */
6383 uint16_t stat_ctx_id;
6385 * The HWRM shall return Unknown value for this field
6386 * when this command is used to query VF's configuration.
6388 uint8_t port_partition_type;
6389 /* Single physical function */
6390 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
6391 /* Multiple physical functions */
6392 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
6393 /* Network Partitioning 1.0 */
6394 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
6395 /* Network Partitioning 1.5 */
6396 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
6397 /* Network Partitioning 2.0 */
6398 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
6400 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
6402 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
6403 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
6405 * This field will indicate number of physical functions on this port_partition.
6406 * HWRM shall return unavail (i.e. value of 0) for this field
6407 * when this command is used to query VF's configuration or
6408 * from older firmware that doesn't support this field.
6410 uint8_t port_pf_cnt;
6411 /* number of PFs is not available */
6412 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
6413 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
6414 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
6416 * The default VNIC ID assigned to a function that is
6419 uint16_t dflt_vnic_id;
6420 uint16_t max_mtu_configured;
6422 * Minimum BW allocated for this function.
6423 * The HWRM will translate this value into byte counter and
6424 * time interval used for the scheduler inside the device.
6425 * A value of 0 indicates the minimum bandwidth is not
6429 /* The bandwidth value. */
6430 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
6432 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
6433 /* The granularity of the value (bits or bytes). */
6434 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
6435 UINT32_C(0x10000000)
6436 /* Value is in bits. */
6437 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
6438 (UINT32_C(0x0) << 28)
6439 /* Value is in bytes. */
6440 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
6441 (UINT32_C(0x1) << 28)
6442 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
6443 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
6444 /* bw_value_unit is 3 b */
6445 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
6446 UINT32_C(0xe0000000)
6447 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6448 /* Value is in Mb or MB (base 10). */
6449 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
6450 (UINT32_C(0x0) << 29)
6451 /* Value is in Kb or KB (base 10). */
6452 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
6453 (UINT32_C(0x2) << 29)
6454 /* Value is in bits or bytes. */
6455 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
6456 (UINT32_C(0x4) << 29)
6457 /* Value is in Gb or GB (base 10). */
6458 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
6459 (UINT32_C(0x6) << 29)
6460 /* Value is in 1/100th of a percentage of total bandwidth. */
6461 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
6462 (UINT32_C(0x1) << 29)
6464 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
6465 (UINT32_C(0x7) << 29)
6466 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
6467 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6469 * Maximum BW allocated for this function.
6470 * The HWRM will translate this value into byte counter and
6471 * time interval used for the scheduler inside the device.
6472 * A value of 0 indicates that the maximum bandwidth is not
6476 /* The bandwidth value. */
6477 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
6479 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
6480 /* The granularity of the value (bits or bytes). */
6481 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
6482 UINT32_C(0x10000000)
6483 /* Value is in bits. */
6484 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
6485 (UINT32_C(0x0) << 28)
6486 /* Value is in bytes. */
6487 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
6488 (UINT32_C(0x1) << 28)
6489 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
6490 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
6491 /* bw_value_unit is 3 b */
6492 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
6493 UINT32_C(0xe0000000)
6494 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6495 /* Value is in Mb or MB (base 10). */
6496 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
6497 (UINT32_C(0x0) << 29)
6498 /* Value is in Kb or KB (base 10). */
6499 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
6500 (UINT32_C(0x2) << 29)
6501 /* Value is in bits or bytes. */
6502 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
6503 (UINT32_C(0x4) << 29)
6504 /* Value is in Gb or GB (base 10). */
6505 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
6506 (UINT32_C(0x6) << 29)
6507 /* Value is in 1/100th of a percentage of total bandwidth. */
6508 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
6509 (UINT32_C(0x1) << 29)
6511 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
6512 (UINT32_C(0x7) << 29)
6513 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
6514 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6516 * This value indicates the Edge virtual bridge mode for the
6517 * domain that this function belongs to.
6520 /* No Edge Virtual Bridging (EVB) */
6521 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6522 /* Virtual Ethernet Bridge (VEB) */
6523 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
6524 /* Virtual Ethernet Port Aggregator (VEPA) */
6525 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
6526 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
6527 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
6530 * This value indicates the PCIE device cache line size.
6531 * The cache line size allows the DMA writes to terminate and
6532 * start at the cache boundary.
6534 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
6536 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
6537 /* Cache Line Size 64 bytes */
6538 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
6540 /* Cache Line Size 128 bytes */
6541 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
6543 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
6544 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
6545 /* This value is the virtual link admin state setting. */
6546 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
6548 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
6549 /* Admin link state is in forced down mode. */
6550 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
6551 (UINT32_C(0x0) << 2)
6552 /* Admin link state is in forced up mode. */
6553 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
6554 (UINT32_C(0x1) << 2)
6555 /* Admin link state is in auto mode - follows the physical link state. */
6556 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
6557 (UINT32_C(0x2) << 2)
6558 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
6559 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
6560 /* Reserved for future. */
6561 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
6563 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
6565 * The number of VFs that are allocated to the function.
6566 * This is valid only on the PF with SR-IOV enabled.
6567 * 0xFF... (All Fs) if this command is called on a PF with
6568 * SR-IOV disabled or on a VF.
6572 * The number of allocated multicast filters for this
6573 * function on the RX side.
6575 uint32_t alloc_mcast_filters;
6577 * The number of allocated HW ring groups for this
6580 uint32_t alloc_hw_ring_grps;
6582 * The number of strict priority transmit rings out of
6583 * currently allocated TX rings to the function
6586 uint16_t alloc_sp_tx_rings;
6588 * The number of statistics contexts
6589 * currently reserved for the function.
6591 uint16_t alloc_stat_ctx;
6593 * This field specifies how many NQs are reserved for the PF.
6594 * Remaining NQs that belong to the PF are available for VFs.
6595 * Once a PF has created VFs, it cannot change how many NQs are
6596 * reserved for itself (since the NQs must be contiguous in HW).
6598 uint16_t alloc_msix;
6600 * The number of registered VF’s associated with the PF. This field
6601 * should be ignored when the request received on the VF interface.
6602 * This field will be updated on the PF interface to initiate
6603 * the unregister request on PF in the HOT Reset Process.
6605 uint16_t registered_vfs;
6606 uint8_t unused_1[3];
6608 * For backward compatibility this field must be set to 1.
6609 * Older drivers might look for this field to be 1 before
6610 * processing the message.
6614 * This GRC address location is used by the Host driver interfaces to poll
6615 * the adapter ready state to re-initiate the registration process again
6616 * after receiving the RESET Notify event.
6618 uint32_t reset_addr_poll;
6619 uint8_t unused_2[3];
6621 * This field is used in Output records to indicate that the output
6622 * is completely written to RAM. This field should be read as '1'
6623 * to indicate that the output has been completely written.
6624 * When writing a command completion or response to an internal processor,
6625 * the order of writes has to be such that this field is written last.
6628 } __attribute__((packed));
6635 /* hwrm_func_cfg_input (size:704b/88B) */
6636 struct hwrm_func_cfg_input {
6637 /* The HWRM command request type. */
6640 * The completion ring to send the completion event on. This should
6641 * be the NQ ID returned from the `nq_alloc` HWRM command.
6645 * The sequence ID is used by the driver for tracking multiple
6646 * commands. This ID is treated as opaque data by the firmware and
6647 * the value is returned in the `hwrm_resp_hdr` upon completion.
6651 * The target ID of the command:
6652 * * 0x0-0xFFF8 - The function ID
6653 * * 0xFFF8-0xFFFE - Reserved for internal processors
6658 * A physical address pointer pointing to a host buffer that the
6659 * command's response data will be written. This can be either a host
6660 * physical address (HPA) or a guest physical address (GPA) and must
6661 * point to a physically contiguous block of memory.
6665 * Function ID of the function that is being
6667 * If set to 0xFF... (All Fs), then the the configuration is
6668 * for the requesting function.
6672 * This field specifies how many NQs will be reserved for the PF.
6673 * Remaining NQs that belong to the PF become available for VFs.
6674 * Once a PF has created VFs, it cannot change how many NQs are
6675 * reserved for itself (since the NQs must be contiguous in HW).
6680 * When this bit is '1', the function is disabled with
6681 * source MAC address check.
6682 * This is an anti-spoofing check. If this flag is set,
6683 * then the function shall be configured to disallow
6684 * transmission of frames with the source MAC address that
6685 * is configured for this function.
6687 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
6690 * When this bit is '1', the function is enabled with
6691 * source MAC address check.
6692 * This is an anti-spoofing check. If this flag is set,
6693 * then the function shall be configured to allow
6694 * transmission of frames with the source MAC address that
6695 * is configured for this function.
6697 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
6700 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
6702 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
6704 * Standard TX Ring mode is used for the allocation of TX ring
6705 * and underlying scheduling resources that allow bandwidth
6706 * reservation and limit settings on the queried function.
6707 * If set to 1, then standard TX ring mode is requested to be
6708 * enabled on the function being configured.
6710 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
6713 * Standard TX Ring mode is used for the allocation of TX ring
6714 * and underlying scheduling resources that allow bandwidth
6715 * reservation and limit settings on the queried function.
6716 * If set to 1, then the standard TX ring mode is requested to
6717 * be disabled on the function being configured. In this extended
6718 * TX ring resource mode, the minimum and maximum bandwidth settings
6719 * are not supported to allow the allocation of TX rings to
6720 * span multiple scheduler nodes.
6722 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
6725 * If this bit is set, virtual mac address configured
6726 * in this command will be persistent over warm boot.
6728 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
6731 * This bit only applies to the VF. If this bit is set, the statistic
6732 * context counters will not be cleared when the statistic context is freed
6733 * or a function reset is called on VF. This bit will be cleared when the PF
6734 * is unloaded or a function reset is called on the PF.
6736 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
6739 * This bit requests that the firmware test to see if all the assets
6740 * requested in this command (i.e. number of TX rings) are available.
6741 * The firmware will return an error if the requested assets are
6742 * not available. The firwmare will NOT reserve the assets if they
6745 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6748 * This bit requests that the firmware test to see if all the assets
6749 * requested in this command (i.e. number of RX rings) are available.
6750 * The firmware will return an error if the requested assets are
6751 * not available. The firwmare will NOT reserve the assets if they
6754 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6757 * This bit requests that the firmware test to see if all the assets
6758 * requested in this command (i.e. number of CMPL rings) are available.
6759 * The firmware will return an error if the requested assets are
6760 * not available. The firwmare will NOT reserve the assets if they
6763 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6766 * This bit requests that the firmware test to see if all the assets
6767 * requested in this command (i.e. number of RSS ctx) are available.
6768 * The firmware will return an error if the requested assets are
6769 * not available. The firwmare will NOT reserve the assets if they
6772 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6775 * This bit requests that the firmware test to see if all the assets
6776 * requested in this command (i.e. number of ring groups) are available.
6777 * The firmware will return an error if the requested assets are
6778 * not available. The firwmare will NOT reserve the assets if they
6781 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6784 * This bit requests that the firmware test to see if all the assets
6785 * requested in this command (i.e. number of stat ctx) are available.
6786 * The firmware will return an error if the requested assets are
6787 * not available. The firwmare will NOT reserve the assets if they
6790 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6793 * This bit requests that the firmware test to see if all the assets
6794 * requested in this command (i.e. number of VNICs) are available.
6795 * The firmware will return an error if the requested assets are
6796 * not available. The firwmare will NOT reserve the assets if they
6799 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6802 * This bit requests that the firmware test to see if all the assets
6803 * requested in this command (i.e. number of L2 ctx) are available.
6804 * The firmware will return an error if the requested assets are
6805 * not available. The firwmare will NOT reserve the assets if they
6808 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6811 * This configuration change can be initiated by a PF driver. This
6812 * configuration request shall be targeted to a VF. From local host
6813 * resident HWRM clients, only the parent PF driver shall be allowed
6814 * to initiate this change on one of its children VFs. If this bit is
6815 * set to 1, then the VF that is being configured is requested to be
6816 * trusted. If this bit is set to 0, then the VF that is being configured
6817 * is requested to be not trusted.
6819 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
6822 * When this bit it set, even if PF reserved pool size is zero,
6823 * FW will allow driver to create TX rings in ring alloc,
6824 * by reserving TX ring, S3 node dynamically.
6826 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
6830 * This bit must be '1' for the mtu field to be
6833 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
6836 * This bit must be '1' for the mru field to be
6839 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
6842 * This bit must be '1' for the num_rsscos_ctxs field to be
6845 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6848 * This bit must be '1' for the num_cmpl_rings field to be
6851 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6854 * This bit must be '1' for the num_tx_rings field to be
6857 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6860 * This bit must be '1' for the num_rx_rings field to be
6863 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6866 * This bit must be '1' for the num_l2_ctxs field to be
6869 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6872 * This bit must be '1' for the num_vnics field to be
6875 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
6878 * This bit must be '1' for the num_stat_ctxs field to be
6881 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6884 * This bit must be '1' for the dflt_mac_addr field to be
6887 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6890 * This bit must be '1' for the dflt_vlan field to be
6893 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
6896 * This bit must be '1' for the dflt_ip_addr field to be
6899 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
6902 * This bit must be '1' for the min_bw field to be
6905 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
6908 * This bit must be '1' for the max_bw field to be
6911 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
6914 * This bit must be '1' for the async_event_cr field to be
6917 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6920 * This bit must be '1' for the vlan_antispoof_mode field to be
6923 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
6926 * This bit must be '1' for the allowed_vlan_pris field to be
6929 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
6932 * This bit must be '1' for the evb_mode field to be
6935 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
6938 * This bit must be '1' for the num_mcast_filters field to be
6941 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
6944 * This bit must be '1' for the num_hw_ring_grps field to be
6947 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6950 * This bit must be '1' for the cache_linesize field to be
6953 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
6956 * This bit must be '1' for the num_msix field to be
6959 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
6962 * This bit must be '1' for the link admin state field to be
6965 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
6968 * The maximum transmission unit of the function.
6969 * The HWRM should make sure that the mtu of
6970 * the function does not exceed the mtu of the physical
6971 * port that this function is associated with.
6973 * In addition to configuring mtu per function, it is
6974 * possible to configure mtu per transmit ring.
6975 * By default, the mtu of each transmit ring associated
6976 * with a function is equal to the mtu of the function.
6977 * The HWRM should make sure that the mtu of each transmit
6978 * ring that is assigned to a function has a valid mtu.
6982 * The maximum receive unit of the function.
6983 * The HWRM should make sure that the mru of
6984 * the function does not exceed the mru of the physical
6985 * port that this function is associated with.
6987 * In addition to configuring mru per function, it is
6988 * possible to configure mru per vnic.
6989 * By default, the mru of each vnic associated
6990 * with a function is equal to the mru of the function.
6991 * The HWRM should make sure that the mru of each vnic
6992 * that is assigned to a function has a valid mru.
6996 * The number of RSS/COS contexts requested for the
6999 uint16_t num_rsscos_ctxs;
7001 * The number of completion rings requested for the
7002 * function. This does not include the rings allocated
7003 * to any children functions if any.
7005 uint16_t num_cmpl_rings;
7007 * The number of transmit rings requested for the function.
7008 * This does not include the rings allocated to any
7009 * children functions if any.
7011 uint16_t num_tx_rings;
7013 * The number of receive rings requested for the function.
7014 * This does not include the rings allocated
7015 * to any children functions if any.
7017 uint16_t num_rx_rings;
7018 /* The requested number of L2 contexts for the function. */
7019 uint16_t num_l2_ctxs;
7020 /* The requested number of vnics for the function. */
7022 /* The requested number of statistic contexts for the function. */
7023 uint16_t num_stat_ctxs;
7025 * The number of HW ring groups that should
7026 * be reserved for this function.
7028 uint16_t num_hw_ring_grps;
7029 /* The default MAC address for the function being configured. */
7030 uint8_t dflt_mac_addr[6];
7032 * The default VLAN for the function being configured.
7033 * This field's format is same as 802.1Q Tag's
7034 * Tag Control Information (TCI) format that includes both
7035 * Priority Code Point (PCP) and VLAN Identifier (VID).
7039 * The default IP address for the function being configured.
7040 * This address is only used in enabling source property check.
7042 uint32_t dflt_ip_addr[4];
7044 * Minimum BW allocated for this function.
7045 * The HWRM will translate this value into byte counter and
7046 * time interval used for the scheduler inside the device.
7049 /* The bandwidth value. */
7050 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
7052 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
7053 /* The granularity of the value (bits or bytes). */
7054 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
7055 UINT32_C(0x10000000)
7056 /* Value is in bits. */
7057 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
7058 (UINT32_C(0x0) << 28)
7059 /* Value is in bytes. */
7060 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
7061 (UINT32_C(0x1) << 28)
7062 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
7063 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
7064 /* bw_value_unit is 3 b */
7065 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7066 UINT32_C(0xe0000000)
7067 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7068 /* Value is in Mb or MB (base 10). */
7069 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7070 (UINT32_C(0x0) << 29)
7071 /* Value is in Kb or KB (base 10). */
7072 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7073 (UINT32_C(0x2) << 29)
7074 /* Value is in bits or bytes. */
7075 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7076 (UINT32_C(0x4) << 29)
7077 /* Value is in Gb or GB (base 10). */
7078 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7079 (UINT32_C(0x6) << 29)
7080 /* Value is in 1/100th of a percentage of total bandwidth. */
7081 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7082 (UINT32_C(0x1) << 29)
7084 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7085 (UINT32_C(0x7) << 29)
7086 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7087 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7089 * Maximum BW allocated for this function.
7090 * The HWRM will translate this value into byte counter and
7091 * time interval used for the scheduler inside the device.
7094 /* The bandwidth value. */
7095 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
7097 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
7098 /* The granularity of the value (bits or bytes). */
7099 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
7100 UINT32_C(0x10000000)
7101 /* Value is in bits. */
7102 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
7103 (UINT32_C(0x0) << 28)
7104 /* Value is in bytes. */
7105 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
7106 (UINT32_C(0x1) << 28)
7107 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
7108 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
7109 /* bw_value_unit is 3 b */
7110 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7111 UINT32_C(0xe0000000)
7112 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7113 /* Value is in Mb or MB (base 10). */
7114 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7115 (UINT32_C(0x0) << 29)
7116 /* Value is in Kb or KB (base 10). */
7117 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7118 (UINT32_C(0x2) << 29)
7119 /* Value is in bits or bytes. */
7120 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7121 (UINT32_C(0x4) << 29)
7122 /* Value is in Gb or GB (base 10). */
7123 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7124 (UINT32_C(0x6) << 29)
7125 /* Value is in 1/100th of a percentage of total bandwidth. */
7126 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7127 (UINT32_C(0x1) << 29)
7129 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7130 (UINT32_C(0x7) << 29)
7131 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7132 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7134 * ID of the target completion ring for receiving asynchronous
7135 * event completions. If this field is not valid, then the
7136 * HWRM shall use the default completion ring of the function
7137 * that is being configured as the target completion ring for
7138 * providing any asynchronous event completions for that
7140 * If this field is valid, then the HWRM shall use the
7141 * completion ring identified by this ID as the target
7142 * completion ring for providing any asynchronous event
7143 * completions for the function that is being configured.
7145 uint16_t async_event_cr;
7146 /* VLAN Anti-spoofing mode. */
7147 uint8_t vlan_antispoof_mode;
7148 /* No VLAN anti-spoofing checks are enabled */
7149 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
7151 /* Validate VLAN against the configured VLAN(s) */
7152 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
7154 /* Insert VLAN if it does not exist, otherwise discard */
7155 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
7157 /* Insert VLAN if it does not exist, override VLAN if it exists */
7158 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
7160 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
7161 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
7163 * This bit field defines VLAN PRIs that are allowed on
7165 * If nth bit is set, then VLAN PRI n is allowed on this
7168 uint8_t allowed_vlan_pris;
7170 * The HWRM shall allow a PF driver to change EVB mode for the
7171 * partition it belongs to.
7172 * The HWRM shall not allow a VF driver to change the EVB mode.
7173 * The HWRM shall take into account the switching of EVB mode
7174 * from one to another and reconfigure hardware resources as
7176 * The switching from VEB to VEPA mode requires
7177 * the disabling of the loopback traffic. Additionally,
7178 * source knock outs are handled differently in VEB and VEPA
7182 /* No Edge Virtual Bridging (EVB) */
7183 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7184 /* Virtual Ethernet Bridge (VEB) */
7185 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
7186 /* Virtual Ethernet Port Aggregator (VEPA) */
7187 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
7188 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
7189 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
7192 * This value indicates the PCIE device cache line size.
7193 * The cache line size allows the DMA writes to terminate and
7194 * start at the cache boundary.
7196 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
7198 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7199 /* Cache Line Size 64 bytes */
7200 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7202 /* Cache Line Size 128 bytes */
7203 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7205 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
7206 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7207 /* This value is the virtual link admin state setting. */
7208 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7210 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7211 /* Admin state is forced down. */
7212 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7213 (UINT32_C(0x0) << 2)
7214 /* Admin state is forced up. */
7215 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7216 (UINT32_C(0x1) << 2)
7217 /* Admin state is in auto mode - is to follow the physical link state. */
7218 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7219 (UINT32_C(0x2) << 2)
7220 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7221 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7222 /* Reserved for future. */
7223 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
7225 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
7227 * The number of multicast filters that should
7228 * be reserved for this function on the RX side.
7230 uint16_t num_mcast_filters;
7231 } __attribute__((packed));
7233 /* hwrm_func_cfg_output (size:128b/16B) */
7234 struct hwrm_func_cfg_output {
7235 /* The specific error status for the command. */
7236 uint16_t error_code;
7237 /* The HWRM command request type. */
7239 /* The sequence ID from the original command. */
7241 /* The length of the response data in number of bytes. */
7243 uint8_t unused_0[7];
7245 * This field is used in Output records to indicate that the output
7246 * is completely written to RAM. This field should be read as '1'
7247 * to indicate that the output has been completely written.
7248 * When writing a command completion or response to an internal processor,
7249 * the order of writes has to be such that this field is written last.
7252 } __attribute__((packed));
7254 /********************
7255 * hwrm_func_qstats *
7256 ********************/
7259 /* hwrm_func_qstats_input (size:192b/24B) */
7260 struct hwrm_func_qstats_input {
7261 /* The HWRM command request type. */
7264 * The completion ring to send the completion event on. This should
7265 * be the NQ ID returned from the `nq_alloc` HWRM command.
7269 * The sequence ID is used by the driver for tracking multiple
7270 * commands. This ID is treated as opaque data by the firmware and
7271 * the value is returned in the `hwrm_resp_hdr` upon completion.
7275 * The target ID of the command:
7276 * * 0x0-0xFFF8 - The function ID
7277 * * 0xFFF8-0xFFFE - Reserved for internal processors
7282 * A physical address pointer pointing to a host buffer that the
7283 * command's response data will be written. This can be either a host
7284 * physical address (HPA) or a guest physical address (GPA) and must
7285 * point to a physically contiguous block of memory.
7289 * Function ID of the function that is being queried.
7290 * 0xFF... (All Fs) if the query is for the requesting
7294 uint8_t unused_0[6];
7295 } __attribute__((packed));
7297 /* hwrm_func_qstats_output (size:1408b/176B) */
7298 struct hwrm_func_qstats_output {
7299 /* The specific error status for the command. */
7300 uint16_t error_code;
7301 /* The HWRM command request type. */
7303 /* The sequence ID from the original command. */
7305 /* The length of the response data in number of bytes. */
7307 /* Number of transmitted unicast packets on the function. */
7308 uint64_t tx_ucast_pkts;
7309 /* Number of transmitted multicast packets on the function. */
7310 uint64_t tx_mcast_pkts;
7311 /* Number of transmitted broadcast packets on the function. */
7312 uint64_t tx_bcast_pkts;
7314 * Number of transmitted packets that were discarded due to
7315 * internal NIC resource problems. For transmit, this
7316 * can only happen if TMP is configured to allow dropping
7317 * in HOL blocking conditions, which is not a normal
7320 uint64_t tx_discard_pkts;
7322 * Number of dropped packets on transmit path on the function.
7323 * These are packets that have been marked for drop by
7324 * the TE CFA block or are packets that exceeded the
7325 * transmit MTU limit for the function.
7327 uint64_t tx_drop_pkts;
7328 /* Number of transmitted bytes for unicast traffic on the function. */
7329 uint64_t tx_ucast_bytes;
7330 /* Number of transmitted bytes for multicast traffic on the function. */
7331 uint64_t tx_mcast_bytes;
7332 /* Number of transmitted bytes for broadcast traffic on the function. */
7333 uint64_t tx_bcast_bytes;
7334 /* Number of received unicast packets on the function. */
7335 uint64_t rx_ucast_pkts;
7336 /* Number of received multicast packets on the function. */
7337 uint64_t rx_mcast_pkts;
7338 /* Number of received broadcast packets on the function. */
7339 uint64_t rx_bcast_pkts;
7341 * Number of received packets that were discarded on the function
7342 * due to resource limitations. This can happen for 3 reasons.
7343 * # The BD used for the packet has a bad format.
7344 * # There were no BDs available in the ring for the packet.
7345 * # There were no BDs available on-chip for the packet.
7347 uint64_t rx_discard_pkts;
7349 * Number of dropped packets on received path on the function.
7350 * These are packets that have been marked for drop by the
7353 uint64_t rx_drop_pkts;
7354 /* Number of received bytes for unicast traffic on the function. */
7355 uint64_t rx_ucast_bytes;
7356 /* Number of received bytes for multicast traffic on the function. */
7357 uint64_t rx_mcast_bytes;
7358 /* Number of received bytes for broadcast traffic on the function. */
7359 uint64_t rx_bcast_bytes;
7360 /* Number of aggregated unicast packets on the function. */
7361 uint64_t rx_agg_pkts;
7362 /* Number of aggregated unicast bytes on the function. */
7363 uint64_t rx_agg_bytes;
7364 /* Number of aggregation events on the function. */
7365 uint64_t rx_agg_events;
7366 /* Number of aborted aggregations on the function. */
7367 uint64_t rx_agg_aborts;
7368 uint8_t unused_0[7];
7370 * This field is used in Output records to indicate that the output
7371 * is completely written to RAM. This field should be read as '1'
7372 * to indicate that the output has been completely written.
7373 * When writing a command completion or response to an internal processor,
7374 * the order of writes has to be such that this field is written last.
7377 } __attribute__((packed));
7379 /***********************
7380 * hwrm_func_clr_stats *
7381 ***********************/
7384 /* hwrm_func_clr_stats_input (size:192b/24B) */
7385 struct hwrm_func_clr_stats_input {
7386 /* The HWRM command request type. */
7389 * The completion ring to send the completion event on. This should
7390 * be the NQ ID returned from the `nq_alloc` HWRM command.
7394 * The sequence ID is used by the driver for tracking multiple
7395 * commands. This ID is treated as opaque data by the firmware and
7396 * the value is returned in the `hwrm_resp_hdr` upon completion.
7400 * The target ID of the command:
7401 * * 0x0-0xFFF8 - The function ID
7402 * * 0xFFF8-0xFFFE - Reserved for internal processors
7407 * A physical address pointer pointing to a host buffer that the
7408 * command's response data will be written. This can be either a host
7409 * physical address (HPA) or a guest physical address (GPA) and must
7410 * point to a physically contiguous block of memory.
7414 * Function ID of the function.
7415 * 0xFF... (All Fs) if the query is for the requesting
7419 uint8_t unused_0[6];
7420 } __attribute__((packed));
7422 /* hwrm_func_clr_stats_output (size:128b/16B) */
7423 struct hwrm_func_clr_stats_output {
7424 /* The specific error status for the command. */
7425 uint16_t error_code;
7426 /* The HWRM command request type. */
7428 /* The sequence ID from the original command. */
7430 /* The length of the response data in number of bytes. */
7432 uint8_t unused_0[7];
7434 * This field is used in Output records to indicate that the output
7435 * is completely written to RAM. This field should be read as '1'
7436 * to indicate that the output has been completely written.
7437 * When writing a command completion or response to an internal processor,
7438 * the order of writes has to be such that this field is written last.
7441 } __attribute__((packed));
7443 /**************************
7444 * hwrm_func_vf_resc_free *
7445 **************************/
7448 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
7449 struct hwrm_func_vf_resc_free_input {
7450 /* The HWRM command request type. */
7453 * The completion ring to send the completion event on. This should
7454 * be the NQ ID returned from the `nq_alloc` HWRM command.
7458 * The sequence ID is used by the driver for tracking multiple
7459 * commands. This ID is treated as opaque data by the firmware and
7460 * the value is returned in the `hwrm_resp_hdr` upon completion.
7464 * The target ID of the command:
7465 * * 0x0-0xFFF8 - The function ID
7466 * * 0xFFF8-0xFFFE - Reserved for internal processors
7471 * A physical address pointer pointing to a host buffer that the
7472 * command's response data will be written. This can be either a host
7473 * physical address (HPA) or a guest physical address (GPA) and must
7474 * point to a physically contiguous block of memory.
7478 * This value is used to identify a Virtual Function (VF).
7479 * The scope of VF ID is local within a PF.
7482 uint8_t unused_0[6];
7483 } __attribute__((packed));
7485 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
7486 struct hwrm_func_vf_resc_free_output {
7487 /* The specific error status for the command. */
7488 uint16_t error_code;
7489 /* The HWRM command request type. */
7491 /* The sequence ID from the original command. */
7493 /* The length of the response data in number of bytes. */
7495 uint8_t unused_0[7];
7497 * This field is used in Output records to indicate that the output
7498 * is completely written to RAM. This field should be read as '1'
7499 * to indicate that the output has been completely written.
7500 * When writing a command completion or response to an internal processor,
7501 * the order of writes has to be such that this field is written last.
7504 } __attribute__((packed));
7506 /**********************
7507 * hwrm_func_drv_rgtr *
7508 **********************/
7511 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
7512 struct hwrm_func_drv_rgtr_input {
7513 /* The HWRM command request type. */
7516 * The completion ring to send the completion event on. This should
7517 * be the NQ ID returned from the `nq_alloc` HWRM command.
7521 * The sequence ID is used by the driver for tracking multiple
7522 * commands. This ID is treated as opaque data by the firmware and
7523 * the value is returned in the `hwrm_resp_hdr` upon completion.
7527 * The target ID of the command:
7528 * * 0x0-0xFFF8 - The function ID
7529 * * 0xFFF8-0xFFFE - Reserved for internal processors
7534 * A physical address pointer pointing to a host buffer that the
7535 * command's response data will be written. This can be either a host
7536 * physical address (HPA) or a guest physical address (GPA) and must
7537 * point to a physically contiguous block of memory.
7542 * When this bit is '1', the function driver is requesting
7543 * all requests from its children VF drivers to be
7544 * forwarded to itself.
7545 * This flag can only be set by the PF driver.
7546 * If a VF driver sets this flag, it should be ignored
7549 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
7552 * When this bit is '1', the function is requesting none of
7553 * the requests from its children VF drivers to be
7554 * forwarded to itself.
7555 * This flag can only be set by the PF driver.
7556 * If a VF driver sets this flag, it should be ignored
7559 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
7562 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
7563 * fields shall be ignored and ver_maj, ver_min, ver_upd
7564 * and ver_patch shall be used for the driver version information.
7565 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
7566 * fields shall be used for the driver version information and
7567 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
7569 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
7572 * When this bit is '1', the function is indicating support of
7573 * 64bit flow handle. The firmware that only supports 64bit flow
7574 * handle should check this bit before allowing processing of
7575 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
7576 * with 64bit flow handle support can only be compatible with drivers
7577 * that support 64bit flow handle. The legacy drivers that don't support
7578 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
7579 * running with new firmware that only supports 64bit flow handle. The new
7580 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
7581 * status to the legacy driver when encounters these commands.
7583 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
7586 * When this bit is '1', the function is indicating support of
7587 * Hot Reset. The driver interface will destroy the resources,
7588 * unregister the function and register again up on receiving
7589 * the RESET_NOTIFY Async notification from the core firmware.
7590 * The core firmware will this use flag and trigger the Hot Reset
7591 * process only if all the registered driver instances are capable
7594 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
7598 * This bit must be '1' for the os_type field to be
7601 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
7604 * This bit must be '1' for the ver field to be
7607 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
7610 * This bit must be '1' for the timestamp field to be
7613 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
7616 * This bit must be '1' for the vf_req_fwd field to be
7619 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
7622 * This bit must be '1' for the async_event_fwd field to be
7625 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
7627 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7630 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7631 /* Other OS not listed below. */
7632 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
7634 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7636 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7638 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7640 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
7642 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7643 /* VMware ESXi OS. */
7644 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
7645 /* Microsoft Windows 8 64-bit OS. */
7646 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7647 /* Microsoft Windows Server 2012 R2 OS. */
7648 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7650 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7651 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
7652 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
7653 /* This is the 8bit major version of the driver. */
7655 /* This is the 8bit minor version of the driver. */
7657 /* This is the 8bit update version of the driver. */
7659 uint8_t unused_0[3];
7661 * This is a 32-bit timestamp provided by the driver for
7663 * The timestamp is in multiples of 1ms.
7666 uint8_t unused_1[4];
7668 * This is a 256-bit bit mask provided by the PF driver for
7669 * letting the HWRM know what commands issued by the VF driver
7670 * to the HWRM should be forwarded to the PF driver.
7671 * Nth bit refers to the Nth req_type.
7673 * Setting Nth bit to 1 indicates that requests from the
7674 * VF driver with req_type equal to N shall be forwarded to
7675 * the parent PF driver.
7677 * This field is not valid for the VF driver.
7679 uint32_t vf_req_fwd[8];
7681 * This is a 256-bit bit mask provided by the function driver
7682 * (PF or VF driver) to indicate the list of asynchronous event
7683 * completions to be forwarded.
7685 * Nth bit refers to the Nth event_id.
7687 * Setting Nth bit to 1 by the function driver shall result in
7688 * the HWRM forwarding asynchronous event completion with
7689 * event_id equal to N.
7691 * If all bits are set to 0 (value of 0), then the HWRM shall
7692 * not forward any asynchronous event completion to this
7695 uint32_t async_event_fwd[8];
7696 /* This is the 16bit major version of the driver. */
7698 /* This is the 16bit minor version of the driver. */
7700 /* This is the 16bit update version of the driver. */
7702 /* This is the 16bit patch version of the driver. */
7704 } __attribute__((packed));
7706 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
7707 struct hwrm_func_drv_rgtr_output {
7708 /* The specific error status for the command. */
7709 uint16_t error_code;
7710 /* The HWRM command request type. */
7712 /* The sequence ID from the original command. */
7714 /* The length of the response data in number of bytes. */
7718 * When this bit is '1', it indicates that the
7719 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
7721 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
7723 uint8_t unused_0[3];
7725 * This field is used in Output records to indicate that the output
7726 * is completely written to RAM. This field should be read as '1'
7727 * to indicate that the output has been completely written.
7728 * When writing a command completion or response to an internal processor,
7729 * the order of writes has to be such that this field is written last.
7732 } __attribute__((packed));
7734 /************************
7735 * hwrm_func_drv_unrgtr *
7736 ************************/
7739 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
7740 struct hwrm_func_drv_unrgtr_input {
7741 /* The HWRM command request type. */
7744 * The completion ring to send the completion event on. This should
7745 * be the NQ ID returned from the `nq_alloc` HWRM command.
7749 * The sequence ID is used by the driver for tracking multiple
7750 * commands. This ID is treated as opaque data by the firmware and
7751 * the value is returned in the `hwrm_resp_hdr` upon completion.
7755 * The target ID of the command:
7756 * * 0x0-0xFFF8 - The function ID
7757 * * 0xFFF8-0xFFFE - Reserved for internal processors
7762 * A physical address pointer pointing to a host buffer that the
7763 * command's response data will be written. This can be either a host
7764 * physical address (HPA) or a guest physical address (GPA) and must
7765 * point to a physically contiguous block of memory.
7770 * When this bit is '1', the function driver is notifying
7771 * the HWRM to prepare for the shutdown.
7773 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
7775 uint8_t unused_0[4];
7776 } __attribute__((packed));
7778 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
7779 struct hwrm_func_drv_unrgtr_output {
7780 /* The specific error status for the command. */
7781 uint16_t error_code;
7782 /* The HWRM command request type. */
7784 /* The sequence ID from the original command. */
7786 /* The length of the response data in number of bytes. */
7788 uint8_t unused_0[7];
7790 * This field is used in Output records to indicate that the output
7791 * is completely written to RAM. This field should be read as '1'
7792 * to indicate that the output has been completely written.
7793 * When writing a command completion or response to an internal processor,
7794 * the order of writes has to be such that this field is written last.
7797 } __attribute__((packed));
7799 /**********************
7800 * hwrm_func_buf_rgtr *
7801 **********************/
7804 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
7805 struct hwrm_func_buf_rgtr_input {
7806 /* The HWRM command request type. */
7809 * The completion ring to send the completion event on. This should
7810 * be the NQ ID returned from the `nq_alloc` HWRM command.
7814 * The sequence ID is used by the driver for tracking multiple
7815 * commands. This ID is treated as opaque data by the firmware and
7816 * the value is returned in the `hwrm_resp_hdr` upon completion.
7820 * The target ID of the command:
7821 * * 0x0-0xFFF8 - The function ID
7822 * * 0xFFF8-0xFFFE - Reserved for internal processors
7827 * A physical address pointer pointing to a host buffer that the
7828 * command's response data will be written. This can be either a host
7829 * physical address (HPA) or a guest physical address (GPA) and must
7830 * point to a physically contiguous block of memory.
7835 * This bit must be '1' for the vf_id field to be
7838 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7840 * This bit must be '1' for the err_buf_addr field to be
7843 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
7845 * This value is used to identify a Virtual Function (VF).
7846 * The scope of VF ID is local within a PF.
7850 * This field represents the number of pages used for request
7853 uint16_t req_buf_num_pages;
7855 * This field represents the page size used for request
7858 uint16_t req_buf_page_size;
7860 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
7862 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
7864 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
7866 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
7868 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
7870 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
7872 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
7873 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
7874 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
7875 /* The length of the request buffer per VF in bytes. */
7876 uint16_t req_buf_len;
7877 /* The length of the response buffer in bytes. */
7878 uint16_t resp_buf_len;
7879 uint8_t unused_0[2];
7880 /* This field represents the page address of page #0. */
7881 uint64_t req_buf_page_addr0;
7882 /* This field represents the page address of page #1. */
7883 uint64_t req_buf_page_addr1;
7884 /* This field represents the page address of page #2. */
7885 uint64_t req_buf_page_addr2;
7886 /* This field represents the page address of page #3. */
7887 uint64_t req_buf_page_addr3;
7888 /* This field represents the page address of page #4. */
7889 uint64_t req_buf_page_addr4;
7890 /* This field represents the page address of page #5. */
7891 uint64_t req_buf_page_addr5;
7892 /* This field represents the page address of page #6. */
7893 uint64_t req_buf_page_addr6;
7894 /* This field represents the page address of page #7. */
7895 uint64_t req_buf_page_addr7;
7896 /* This field represents the page address of page #8. */
7897 uint64_t req_buf_page_addr8;
7898 /* This field represents the page address of page #9. */
7899 uint64_t req_buf_page_addr9;
7901 * This field is used to receive the error reporting from
7902 * the chipset. Only applicable for PFs.
7904 uint64_t error_buf_addr;
7906 * This field is used to receive the response forwarded by the
7909 uint64_t resp_buf_addr;
7910 } __attribute__((packed));
7912 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
7913 struct hwrm_func_buf_rgtr_output {
7914 /* The specific error status for the command. */
7915 uint16_t error_code;
7916 /* The HWRM command request type. */
7918 /* The sequence ID from the original command. */
7920 /* The length of the response data in number of bytes. */
7922 uint8_t unused_0[7];
7924 * This field is used in Output records to indicate that the output
7925 * is completely written to RAM. This field should be read as '1'
7926 * to indicate that the output has been completely written.
7927 * When writing a command completion or response to an internal processor,
7928 * the order of writes has to be such that this field is written last.
7931 } __attribute__((packed));
7933 /************************
7934 * hwrm_func_buf_unrgtr *
7935 ************************/
7938 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
7939 struct hwrm_func_buf_unrgtr_input {
7940 /* The HWRM command request type. */
7943 * The completion ring to send the completion event on. This should
7944 * be the NQ ID returned from the `nq_alloc` HWRM command.
7948 * The sequence ID is used by the driver for tracking multiple
7949 * commands. This ID is treated as opaque data by the firmware and
7950 * the value is returned in the `hwrm_resp_hdr` upon completion.
7954 * The target ID of the command:
7955 * * 0x0-0xFFF8 - The function ID
7956 * * 0xFFF8-0xFFFE - Reserved for internal processors
7961 * A physical address pointer pointing to a host buffer that the
7962 * command's response data will be written. This can be either a host
7963 * physical address (HPA) or a guest physical address (GPA) and must
7964 * point to a physically contiguous block of memory.
7969 * This bit must be '1' for the vf_id field to be
7972 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7974 * This value is used to identify a Virtual Function (VF).
7975 * The scope of VF ID is local within a PF.
7978 uint8_t unused_0[2];
7979 } __attribute__((packed));
7981 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
7982 struct hwrm_func_buf_unrgtr_output {
7983 /* The specific error status for the command. */
7984 uint16_t error_code;
7985 /* The HWRM command request type. */
7987 /* The sequence ID from the original command. */
7989 /* The length of the response data in number of bytes. */
7991 uint8_t unused_0[7];
7993 * This field is used in Output records to indicate that the output
7994 * is completely written to RAM. This field should be read as '1'
7995 * to indicate that the output has been completely written.
7996 * When writing a command completion or response to an internal processor,
7997 * the order of writes has to be such that this field is written last.
8000 } __attribute__((packed));
8002 /**********************
8003 * hwrm_func_drv_qver *
8004 **********************/
8007 /* hwrm_func_drv_qver_input (size:192b/24B) */
8008 struct hwrm_func_drv_qver_input {
8009 /* The HWRM command request type. */
8012 * The completion ring to send the completion event on. This should
8013 * be the NQ ID returned from the `nq_alloc` HWRM command.
8017 * The sequence ID is used by the driver for tracking multiple
8018 * commands. This ID is treated as opaque data by the firmware and
8019 * the value is returned in the `hwrm_resp_hdr` upon completion.
8023 * The target ID of the command:
8024 * * 0x0-0xFFF8 - The function ID
8025 * * 0xFFF8-0xFFFE - Reserved for internal processors
8030 * A physical address pointer pointing to a host buffer that the
8031 * command's response data will be written. This can be either a host
8032 * physical address (HPA) or a guest physical address (GPA) and must
8033 * point to a physically contiguous block of memory.
8036 /* Reserved for future use. */
8039 * Function ID of the function that is being queried.
8040 * 0xFF... (All Fs) if the query is for the requesting
8044 uint8_t unused_0[2];
8045 } __attribute__((packed));
8047 /* hwrm_func_drv_qver_output (size:256b/32B) */
8048 struct hwrm_func_drv_qver_output {
8049 /* The specific error status for the command. */
8050 uint16_t error_code;
8051 /* The HWRM command request type. */
8053 /* The sequence ID from the original command. */
8055 /* The length of the response data in number of bytes. */
8057 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8060 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8061 /* Other OS not listed below. */
8062 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
8064 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8066 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8068 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8070 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
8072 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8073 /* VMware ESXi OS. */
8074 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
8075 /* Microsoft Windows 8 64-bit OS. */
8076 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8077 /* Microsoft Windows Server 2012 R2 OS. */
8078 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8080 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8081 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
8082 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
8083 /* This is the 8bit major version of the driver. */
8085 /* This is the 8bit minor version of the driver. */
8087 /* This is the 8bit update version of the driver. */
8089 uint8_t unused_0[3];
8090 /* This is the 16bit major version of the driver. */
8092 /* This is the 16bit minor version of the driver. */
8094 /* This is the 16bit update version of the driver. */
8096 /* This is the 16bit patch version of the driver. */
8098 uint8_t unused_1[7];
8100 * This field is used in Output records to indicate that the output
8101 * is completely written to RAM. This field should be read as '1'
8102 * to indicate that the output has been completely written.
8103 * When writing a command completion or response to an internal processor,
8104 * the order of writes has to be such that this field is written last.
8107 } __attribute__((packed));
8109 /****************************
8110 * hwrm_func_resource_qcaps *
8111 ****************************/
8114 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
8115 struct hwrm_func_resource_qcaps_input {
8116 /* The HWRM command request type. */
8119 * The completion ring to send the completion event on. This should
8120 * be the NQ ID returned from the `nq_alloc` HWRM command.
8124 * The sequence ID is used by the driver for tracking multiple
8125 * commands. This ID is treated as opaque data by the firmware and
8126 * the value is returned in the `hwrm_resp_hdr` upon completion.
8130 * The target ID of the command:
8131 * * 0x0-0xFFF8 - The function ID
8132 * * 0xFFF8-0xFFFE - Reserved for internal processors
8137 * A physical address pointer pointing to a host buffer that the
8138 * command's response data will be written. This can be either a host
8139 * physical address (HPA) or a guest physical address (GPA) and must
8140 * point to a physically contiguous block of memory.
8144 * Function ID of the function that is being queried.
8145 * 0xFF... (All Fs) if the query is for the requesting
8149 uint8_t unused_0[6];
8150 } __attribute__((packed));
8152 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
8153 struct hwrm_func_resource_qcaps_output {
8154 /* The specific error status for the command. */
8155 uint16_t error_code;
8156 /* The HWRM command request type. */
8158 /* The sequence ID from the original command. */
8160 /* The length of the response data in number of bytes. */
8162 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
8164 /* Maximum guaranteed number of MSI-X vectors supported by function */
8166 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
8167 uint16_t vf_reservation_strategy;
8168 /* The PF driver should evenly divide its remaining resources among all VFs. */
8169 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
8171 /* The PF driver should only reserve minimal resources for each VF. */
8172 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
8175 * The PF driver should not reserve any resources for each VF until the
8176 * the VF interface is brought up.
8178 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
8180 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
8181 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
8182 /* Minimum guaranteed number of RSS/COS contexts */
8183 uint16_t min_rsscos_ctx;
8184 /* Maximum non-guaranteed number of RSS/COS contexts */
8185 uint16_t max_rsscos_ctx;
8186 /* Minimum guaranteed number of completion rings */
8187 uint16_t min_cmpl_rings;
8188 /* Maximum non-guaranteed number of completion rings */
8189 uint16_t max_cmpl_rings;
8190 /* Minimum guaranteed number of transmit rings */
8191 uint16_t min_tx_rings;
8192 /* Maximum non-guaranteed number of transmit rings */
8193 uint16_t max_tx_rings;
8194 /* Minimum guaranteed number of receive rings */
8195 uint16_t min_rx_rings;
8196 /* Maximum non-guaranteed number of receive rings */
8197 uint16_t max_rx_rings;
8198 /* Minimum guaranteed number of L2 contexts */
8199 uint16_t min_l2_ctxs;
8200 /* Maximum non-guaranteed number of L2 contexts */
8201 uint16_t max_l2_ctxs;
8202 /* Minimum guaranteed number of VNICs */
8204 /* Maximum non-guaranteed number of VNICs */
8206 /* Minimum guaranteed number of statistic contexts */
8207 uint16_t min_stat_ctx;
8208 /* Maximum non-guaranteed number of statistic contexts */
8209 uint16_t max_stat_ctx;
8210 /* Minimum guaranteed number of ring groups */
8211 uint16_t min_hw_ring_grps;
8212 /* Maximum non-guaranteed number of ring groups */
8213 uint16_t max_hw_ring_grps;
8215 * Maximum number of inputs into the transmit scheduler for this function.
8216 * The number of TX rings assigned to the function cannot exceed this value.
8218 uint16_t max_tx_scheduler_inputs;
8221 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
8222 * feature to reserve all minimum resources when minimum >= 1, otherwise
8225 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
8227 uint8_t unused_0[5];
8229 * This field is used in Output records to indicate that the output
8230 * is completely written to RAM. This field should be read as '1'
8231 * to indicate that the output has been completely written.
8232 * When writing a command completion or response to an internal processor,
8233 * the order of writes has to be such that this field is written last.
8236 } __attribute__((packed));
8238 /*********************************
8239 * hwrm_func_backing_store_qcaps *
8240 *********************************/
8243 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
8244 struct hwrm_func_backing_store_qcaps_input {
8245 /* The HWRM command request type. */
8248 * The completion ring to send the completion event on. This should
8249 * be the NQ ID returned from the `nq_alloc` HWRM command.
8253 * The sequence ID is used by the driver for tracking multiple
8254 * commands. This ID is treated as opaque data by the firmware and
8255 * the value is returned in the `hwrm_resp_hdr` upon completion.
8259 * The target ID of the command:
8260 * * 0x0-0xFFF8 - The function ID
8261 * * 0xFFF8-0xFFFE - Reserved for internal processors
8266 * A physical address pointer pointing to a host buffer that the
8267 * command's response data will be written. This can be either a host
8268 * physical address (HPA) or a guest physical address (GPA) and must
8269 * point to a physically contiguous block of memory.
8272 } __attribute__((packed));
8274 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
8275 struct hwrm_func_backing_store_qcaps_output {
8276 /* The specific error status for the command. */
8277 uint16_t error_code;
8278 /* The HWRM command request type. */
8280 /* The sequence ID from the original command. */
8282 /* The length of the response data in number of bytes. */
8284 /* Maximum number of QP context entries supported for this function. */
8285 uint32_t qp_max_entries;
8287 * Minimum number of QP context entries that are needed to be reserved
8288 * for QP1 for the PF and its VFs. PF drivers must allocate at least
8289 * this many QP context entries, even if RoCE will not be used.
8291 uint16_t qp_min_qp1_entries;
8292 /* Maximum number of QP context entries that can be used for L2. */
8293 uint16_t qp_max_l2_entries;
8294 /* Number of bytes that must be allocated for each context entry. */
8295 uint16_t qp_entry_size;
8296 /* Maximum number of SRQ context entries that can be used for L2. */
8297 uint16_t srq_max_l2_entries;
8298 /* Maximum number of SRQ context entries supported for this function. */
8299 uint32_t srq_max_entries;
8300 /* Number of bytes that must be allocated for each context entry. */
8301 uint16_t srq_entry_size;
8302 /* Maximum number of CQ context entries that can be used for L2. */
8303 uint16_t cq_max_l2_entries;
8304 /* Maximum number of CQ context entries supported for this function. */
8305 uint32_t cq_max_entries;
8306 /* Number of bytes that must be allocated for each context entry. */
8307 uint16_t cq_entry_size;
8308 /* Maximum number of VNIC context entries supported for this function. */
8309 uint16_t vnic_max_vnic_entries;
8310 /* Maximum number of Ring table context entries supported for this function. */
8311 uint16_t vnic_max_ring_table_entries;
8312 /* Number of bytes that must be allocated for each context entry. */
8313 uint16_t vnic_entry_size;
8314 /* Maximum number of statistic context entries supported for this function. */
8315 uint32_t stat_max_entries;
8316 /* Number of bytes that must be allocated for each context entry. */
8317 uint16_t stat_entry_size;
8318 /* Number of bytes that must be allocated for each context entry. */
8319 uint16_t tqm_entry_size;
8320 /* Minimum number of TQM context entries required per ring. */
8321 uint32_t tqm_min_entries_per_ring;
8323 * Maximum number of TQM context entries supported per ring. This is
8324 * actually a recommended TQM queue size based on worst case usage of
8327 * TQM fastpath rings should be sized large enough to accommodate the
8328 * maximum number of QPs (either L2 or RoCE, or both if shared)
8329 * that can be enqueued to the TQM ring.
8331 * TQM slowpath rings should be sized as follows:
8333 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
8336 * num_vnics is the number of VNICs allocated in the VNIC backing store
8337 * num_l2_tx_rings is the number of L2 rings in the QP backing store
8338 * num_roce_qps is the number of RoCE QPs in the QP backing store
8339 * tqm_min_size is tqm_min_entries_per_ring reported by
8340 * HWRM_FUNC_BACKING_STORE_QCAPS
8342 * Note that TQM ring sizes cannot be extended while the system is
8343 * operational. If a PF driver needs to extend a TQM ring, it needs
8344 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8345 * the backing store.
8347 uint32_t tqm_max_entries_per_ring;
8348 /* Maximum number of MR/AV context entries supported for this function. */
8349 uint32_t mrav_max_entries;
8350 /* Number of bytes that must be allocated for each context entry. */
8351 uint16_t mrav_entry_size;
8352 /* Number of bytes that must be allocated for each context entry. */
8353 uint16_t tim_entry_size;
8354 /* Maximum number of Timer context entries supported for this function. */
8355 uint32_t tim_max_entries;
8356 uint8_t unused_0[2];
8358 * The number of entries specified for any TQM ring must be a
8359 * multiple of this value to prevent any resource allocation
8362 uint8_t tqm_entries_multiple;
8364 * This field is used in Output records to indicate that the output
8365 * is completely written to RAM. This field should be read as '1'
8366 * to indicate that the output has been completely written.
8367 * When writing a command completion or response to an internal processor,
8368 * the order of writes has to be such that this field is written last.
8371 } __attribute__((packed));
8373 /*******************************
8374 * hwrm_func_backing_store_cfg *
8375 *******************************/
8378 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
8379 struct hwrm_func_backing_store_cfg_input {
8380 /* The HWRM command request type. */
8383 * The completion ring to send the completion event on. This should
8384 * be the NQ ID returned from the `nq_alloc` HWRM command.
8388 * The sequence ID is used by the driver for tracking multiple
8389 * commands. This ID is treated as opaque data by the firmware and
8390 * the value is returned in the `hwrm_resp_hdr` upon completion.
8394 * The target ID of the command:
8395 * * 0x0-0xFFF8 - The function ID
8396 * * 0xFFF8-0xFFFE - Reserved for internal processors
8401 * A physical address pointer pointing to a host buffer that the
8402 * command's response data will be written. This can be either a host
8403 * physical address (HPA) or a guest physical address (GPA) and must
8404 * point to a physically contiguous block of memory.
8409 * When set, the firmware only uses on-chip resources and does not
8410 * expect any backing store to be provided by the host driver. This
8411 * mode provides minimal L2 functionality (e.g. limited L2 resources,
8414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
8418 * This bit must be '1' for the qp fields to be
8421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
8424 * This bit must be '1' for the srq fields to be
8427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
8430 * This bit must be '1' for the cq fields to be
8433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
8436 * This bit must be '1' for the vnic fields to be
8439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
8442 * This bit must be '1' for the stat fields to be
8445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
8448 * This bit must be '1' for the tqm_sp fields to be
8451 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
8454 * This bit must be '1' for the tqm_ring0 fields to be
8457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
8460 * This bit must be '1' for the tqm_ring1 fields to be
8463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
8466 * This bit must be '1' for the tqm_ring2 fields to be
8469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
8472 * This bit must be '1' for the tqm_ring3 fields to be
8475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
8478 * This bit must be '1' for the tqm_ring4 fields to be
8481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
8484 * This bit must be '1' for the tqm_ring5 fields to be
8487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
8490 * This bit must be '1' for the tqm_ring6 fields to be
8493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
8496 * This bit must be '1' for the tqm_ring7 fields to be
8499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
8502 * This bit must be '1' for the mrav fields to be
8505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
8508 * This bit must be '1' for the tim fields to be
8511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
8513 /* QPC page size and level. */
8514 uint8_t qpc_pg_size_qpc_lvl;
8515 /* QPC PBL indirect levels. */
8516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
8518 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
8519 /* PBL pointer is physical start address. */
8520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
8522 /* PBL pointer points to PTE table. */
8523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
8525 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
8528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
8529 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
8530 /* QPC page size. */
8531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
8533 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
8535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
8536 (UINT32_C(0x0) << 4)
8538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
8539 (UINT32_C(0x1) << 4)
8541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
8542 (UINT32_C(0x2) << 4)
8544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
8545 (UINT32_C(0x3) << 4)
8547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
8548 (UINT32_C(0x4) << 4)
8550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
8551 (UINT32_C(0x5) << 4)
8552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
8553 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
8554 /* SRQ page size and level. */
8555 uint8_t srq_pg_size_srq_lvl;
8556 /* SRQ PBL indirect levels. */
8557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
8559 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
8560 /* PBL pointer is physical start address. */
8561 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
8563 /* PBL pointer points to PTE table. */
8564 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
8566 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
8569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
8570 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
8571 /* SRQ page size. */
8572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
8574 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
8576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
8577 (UINT32_C(0x0) << 4)
8579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
8580 (UINT32_C(0x1) << 4)
8582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
8583 (UINT32_C(0x2) << 4)
8585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
8586 (UINT32_C(0x3) << 4)
8588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
8589 (UINT32_C(0x4) << 4)
8591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
8592 (UINT32_C(0x5) << 4)
8593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
8594 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
8595 /* CQ page size and level. */
8596 uint8_t cq_pg_size_cq_lvl;
8597 /* CQ PBL indirect levels. */
8598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
8600 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
8601 /* PBL pointer is physical start address. */
8602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
8604 /* PBL pointer points to PTE table. */
8605 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
8607 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
8610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
8611 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
8613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
8615 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
8617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
8618 (UINT32_C(0x0) << 4)
8620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
8621 (UINT32_C(0x1) << 4)
8623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
8624 (UINT32_C(0x2) << 4)
8626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
8627 (UINT32_C(0x3) << 4)
8629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
8630 (UINT32_C(0x4) << 4)
8632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
8633 (UINT32_C(0x5) << 4)
8634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
8635 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
8636 /* VNIC page size and level. */
8637 uint8_t vnic_pg_size_vnic_lvl;
8638 /* VNIC PBL indirect levels. */
8639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
8641 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
8642 /* PBL pointer is physical start address. */
8643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
8645 /* PBL pointer points to PTE table. */
8646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
8648 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
8651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
8652 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
8653 /* VNIC page size. */
8654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
8656 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
8658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
8659 (UINT32_C(0x0) << 4)
8661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
8662 (UINT32_C(0x1) << 4)
8664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
8665 (UINT32_C(0x2) << 4)
8667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
8668 (UINT32_C(0x3) << 4)
8670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
8671 (UINT32_C(0x4) << 4)
8673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
8674 (UINT32_C(0x5) << 4)
8675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
8676 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
8677 /* Stat page size and level. */
8678 uint8_t stat_pg_size_stat_lvl;
8679 /* Stat PBL indirect levels. */
8680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
8682 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
8683 /* PBL pointer is physical start address. */
8684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
8686 /* PBL pointer points to PTE table. */
8687 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
8689 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
8692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
8693 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
8694 /* Stat page size. */
8695 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
8697 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
8699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
8700 (UINT32_C(0x0) << 4)
8702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
8703 (UINT32_C(0x1) << 4)
8705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
8706 (UINT32_C(0x2) << 4)
8708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
8709 (UINT32_C(0x3) << 4)
8711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
8712 (UINT32_C(0x4) << 4)
8714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
8715 (UINT32_C(0x5) << 4)
8716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
8717 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
8718 /* TQM slow path page size and level. */
8719 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
8720 /* TQM slow path PBL indirect levels. */
8721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
8723 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
8724 /* PBL pointer is physical start address. */
8725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
8727 /* PBL pointer points to PTE table. */
8728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
8730 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
8733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
8734 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
8735 /* TQM slow path page size. */
8736 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
8738 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
8740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
8741 (UINT32_C(0x0) << 4)
8743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
8744 (UINT32_C(0x1) << 4)
8746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
8747 (UINT32_C(0x2) << 4)
8749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
8750 (UINT32_C(0x3) << 4)
8752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
8753 (UINT32_C(0x4) << 4)
8755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
8756 (UINT32_C(0x5) << 4)
8757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
8758 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
8759 /* TQM ring 0 page size and level. */
8760 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
8761 /* TQM ring 0 PBL indirect levels. */
8762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
8764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
8765 /* PBL pointer is physical start address. */
8766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
8768 /* PBL pointer points to PTE table. */
8769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
8771 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
8774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
8775 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
8776 /* TQM ring 0 page size. */
8777 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
8779 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
8781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
8782 (UINT32_C(0x0) << 4)
8784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
8785 (UINT32_C(0x1) << 4)
8787 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
8788 (UINT32_C(0x2) << 4)
8790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
8791 (UINT32_C(0x3) << 4)
8793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
8794 (UINT32_C(0x4) << 4)
8796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
8797 (UINT32_C(0x5) << 4)
8798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
8799 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
8800 /* TQM ring 1 page size and level. */
8801 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
8802 /* TQM ring 1 PBL indirect levels. */
8803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
8805 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
8806 /* PBL pointer is physical start address. */
8807 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
8809 /* PBL pointer points to PTE table. */
8810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
8812 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
8815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
8816 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
8817 /* TQM ring 1 page size. */
8818 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
8820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
8822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
8823 (UINT32_C(0x0) << 4)
8825 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
8826 (UINT32_C(0x1) << 4)
8828 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
8829 (UINT32_C(0x2) << 4)
8831 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
8832 (UINT32_C(0x3) << 4)
8834 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
8835 (UINT32_C(0x4) << 4)
8837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
8838 (UINT32_C(0x5) << 4)
8839 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
8840 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
8841 /* TQM ring 2 page size and level. */
8842 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
8843 /* TQM ring 2 PBL indirect levels. */
8844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
8846 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
8847 /* PBL pointer is physical start address. */
8848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
8850 /* PBL pointer points to PTE table. */
8851 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
8853 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
8856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
8857 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
8858 /* TQM ring 2 page size. */
8859 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
8861 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
8863 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
8864 (UINT32_C(0x0) << 4)
8866 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
8867 (UINT32_C(0x1) << 4)
8869 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
8870 (UINT32_C(0x2) << 4)
8872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
8873 (UINT32_C(0x3) << 4)
8875 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
8876 (UINT32_C(0x4) << 4)
8878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
8879 (UINT32_C(0x5) << 4)
8880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
8881 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
8882 /* TQM ring 3 page size and level. */
8883 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
8884 /* TQM ring 3 PBL indirect levels. */
8885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
8887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
8888 /* PBL pointer is physical start address. */
8889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
8891 /* PBL pointer points to PTE table. */
8892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
8894 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
8897 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
8898 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
8899 /* TQM ring 3 page size. */
8900 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
8902 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
8904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
8905 (UINT32_C(0x0) << 4)
8907 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
8908 (UINT32_C(0x1) << 4)
8910 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
8911 (UINT32_C(0x2) << 4)
8913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
8914 (UINT32_C(0x3) << 4)
8916 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
8917 (UINT32_C(0x4) << 4)
8919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
8920 (UINT32_C(0x5) << 4)
8921 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
8922 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
8923 /* TQM ring 4 page size and level. */
8924 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
8925 /* TQM ring 4 PBL indirect levels. */
8926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
8928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
8929 /* PBL pointer is physical start address. */
8930 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
8932 /* PBL pointer points to PTE table. */
8933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
8935 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
8938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
8939 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
8940 /* TQM ring 4 page size. */
8941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
8943 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
8945 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
8946 (UINT32_C(0x0) << 4)
8948 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
8949 (UINT32_C(0x1) << 4)
8951 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
8952 (UINT32_C(0x2) << 4)
8954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
8955 (UINT32_C(0x3) << 4)
8957 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
8958 (UINT32_C(0x4) << 4)
8960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
8961 (UINT32_C(0x5) << 4)
8962 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
8963 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
8964 /* TQM ring 5 page size and level. */
8965 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
8966 /* TQM ring 5 PBL indirect levels. */
8967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
8969 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
8970 /* PBL pointer is physical start address. */
8971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
8973 /* PBL pointer points to PTE table. */
8974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
8976 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
8979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
8980 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
8981 /* TQM ring 5 page size. */
8982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
8984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
8986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
8987 (UINT32_C(0x0) << 4)
8989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
8990 (UINT32_C(0x1) << 4)
8992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
8993 (UINT32_C(0x2) << 4)
8995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
8996 (UINT32_C(0x3) << 4)
8998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
8999 (UINT32_C(0x4) << 4)
9001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
9002 (UINT32_C(0x5) << 4)
9003 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
9004 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
9005 /* TQM ring 6 page size and level. */
9006 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9007 /* TQM ring 6 PBL indirect levels. */
9008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
9010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
9011 /* PBL pointer is physical start address. */
9012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
9014 /* PBL pointer points to PTE table. */
9015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
9017 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
9020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
9021 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
9022 /* TQM ring 6 page size. */
9023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
9025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
9027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
9028 (UINT32_C(0x0) << 4)
9030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
9031 (UINT32_C(0x1) << 4)
9033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
9034 (UINT32_C(0x2) << 4)
9036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
9037 (UINT32_C(0x3) << 4)
9039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
9040 (UINT32_C(0x4) << 4)
9042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
9043 (UINT32_C(0x5) << 4)
9044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
9045 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
9046 /* TQM ring 7 page size and level. */
9047 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9048 /* TQM ring 7 PBL indirect levels. */
9049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
9051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
9052 /* PBL pointer is physical start address. */
9053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
9055 /* PBL pointer points to PTE table. */
9056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
9058 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
9061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
9062 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
9063 /* TQM ring 7 page size. */
9064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
9066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
9068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
9069 (UINT32_C(0x0) << 4)
9071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
9072 (UINT32_C(0x1) << 4)
9074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
9075 (UINT32_C(0x2) << 4)
9077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
9078 (UINT32_C(0x3) << 4)
9080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
9081 (UINT32_C(0x4) << 4)
9083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
9084 (UINT32_C(0x5) << 4)
9085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
9086 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
9087 /* MR/AV page size and level. */
9088 uint8_t mrav_pg_size_mrav_lvl;
9089 /* MR/AV PBL indirect levels. */
9090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
9092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
9093 /* PBL pointer is physical start address. */
9094 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
9096 /* PBL pointer points to PTE table. */
9097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
9099 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
9102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
9103 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
9104 /* MR/AV page size. */
9105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
9107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
9109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
9110 (UINT32_C(0x0) << 4)
9112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
9113 (UINT32_C(0x1) << 4)
9115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
9116 (UINT32_C(0x2) << 4)
9118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
9119 (UINT32_C(0x3) << 4)
9121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
9122 (UINT32_C(0x4) << 4)
9124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
9125 (UINT32_C(0x5) << 4)
9126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
9127 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
9128 /* Timer page size and level. */
9129 uint8_t tim_pg_size_tim_lvl;
9130 /* Timer PBL indirect levels. */
9131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
9133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
9134 /* PBL pointer is physical start address. */
9135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
9137 /* PBL pointer points to PTE table. */
9138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
9140 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
9143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
9144 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
9145 /* Timer page size. */
9146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
9148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
9150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
9151 (UINT32_C(0x0) << 4)
9153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
9154 (UINT32_C(0x1) << 4)
9156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
9157 (UINT32_C(0x2) << 4)
9159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
9160 (UINT32_C(0x3) << 4)
9162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
9163 (UINT32_C(0x4) << 4)
9165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
9166 (UINT32_C(0x5) << 4)
9167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
9168 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
9169 /* QP page directory. */
9170 uint64_t qpc_page_dir;
9171 /* SRQ page directory. */
9172 uint64_t srq_page_dir;
9173 /* CQ page directory. */
9174 uint64_t cq_page_dir;
9175 /* VNIC page directory. */
9176 uint64_t vnic_page_dir;
9177 /* Stat page directory. */
9178 uint64_t stat_page_dir;
9179 /* TQM slowpath page directory. */
9180 uint64_t tqm_sp_page_dir;
9181 /* TQM ring 0 page directory. */
9182 uint64_t tqm_ring0_page_dir;
9183 /* TQM ring 1 page directory. */
9184 uint64_t tqm_ring1_page_dir;
9185 /* TQM ring 2 page directory. */
9186 uint64_t tqm_ring2_page_dir;
9187 /* TQM ring 3 page directory. */
9188 uint64_t tqm_ring3_page_dir;
9189 /* TQM ring 4 page directory. */
9190 uint64_t tqm_ring4_page_dir;
9191 /* TQM ring 5 page directory. */
9192 uint64_t tqm_ring5_page_dir;
9193 /* TQM ring 6 page directory. */
9194 uint64_t tqm_ring6_page_dir;
9195 /* TQM ring 7 page directory. */
9196 uint64_t tqm_ring7_page_dir;
9197 /* MR/AV page directory. */
9198 uint64_t mrav_page_dir;
9199 /* Timer page directory. */
9200 uint64_t tim_page_dir;
9201 /* Number of QPs. */
9202 uint32_t qp_num_entries;
9203 /* Number of SRQs. */
9204 uint32_t srq_num_entries;
9205 /* Number of CQs. */
9206 uint32_t cq_num_entries;
9207 /* Number of Stats. */
9208 uint32_t stat_num_entries;
9210 * Number of TQM slowpath entries.
9212 * TQM slowpath rings should be sized as follows:
9214 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9217 * num_vnics is the number of VNICs allocated in the VNIC backing store
9218 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9219 * num_roce_qps is the number of RoCE QPs in the QP backing store
9220 * tqm_min_size is tqm_min_entries_per_ring reported by
9221 * HWRM_FUNC_BACKING_STORE_QCAPS
9223 * Note that TQM ring sizes cannot be extended while the system is
9224 * operational. If a PF driver needs to extend a TQM ring, it needs
9225 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9226 * the backing store.
9228 uint32_t tqm_sp_num_entries;
9230 * Number of TQM ring 0 entries.
9232 * TQM fastpath rings should be sized large enough to accommodate the
9233 * maximum number of QPs (either L2 or RoCE, or both if shared)
9234 * that can be enqueued to the TQM ring.
9236 * Note that TQM ring sizes cannot be extended while the system is
9237 * operational. If a PF driver needs to extend a TQM ring, it needs
9238 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9239 * the backing store.
9241 uint32_t tqm_ring0_num_entries;
9243 * Number of TQM ring 1 entries.
9245 * TQM fastpath rings should be sized large enough to accommodate the
9246 * maximum number of QPs (either L2 or RoCE, or both if shared)
9247 * that can be enqueued to the TQM ring.
9249 * Note that TQM ring sizes cannot be extended while the system is
9250 * operational. If a PF driver needs to extend a TQM ring, it needs
9251 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9252 * the backing store.
9254 uint32_t tqm_ring1_num_entries;
9256 * Number of TQM ring 2 entries.
9258 * TQM fastpath rings should be sized large enough to accommodate the
9259 * maximum number of QPs (either L2 or RoCE, or both if shared)
9260 * that can be enqueued to the TQM ring.
9262 * Note that TQM ring sizes cannot be extended while the system is
9263 * operational. If a PF driver needs to extend a TQM ring, it needs
9264 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9265 * the backing store.
9267 uint32_t tqm_ring2_num_entries;
9269 * Number of TQM ring 3 entries.
9271 * TQM fastpath rings should be sized large enough to accommodate the
9272 * maximum number of QPs (either L2 or RoCE, or both if shared)
9273 * that can be enqueued to the TQM ring.
9275 * Note that TQM ring sizes cannot be extended while the system is
9276 * operational. If a PF driver needs to extend a TQM ring, it needs
9277 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9278 * the backing store.
9280 uint32_t tqm_ring3_num_entries;
9282 * Number of TQM ring 4 entries.
9284 * TQM fastpath rings should be sized large enough to accommodate the
9285 * maximum number of QPs (either L2 or RoCE, or both if shared)
9286 * that can be enqueued to the TQM ring.
9288 * Note that TQM ring sizes cannot be extended while the system is
9289 * operational. If a PF driver needs to extend a TQM ring, it needs
9290 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9291 * the backing store.
9293 uint32_t tqm_ring4_num_entries;
9295 * Number of TQM ring 5 entries.
9297 * TQM fastpath rings should be sized large enough to accommodate the
9298 * maximum number of QPs (either L2 or RoCE, or both if shared)
9299 * that can be enqueued to the TQM ring.
9301 * Note that TQM ring sizes cannot be extended while the system is
9302 * operational. If a PF driver needs to extend a TQM ring, it needs
9303 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9304 * the backing store.
9306 uint32_t tqm_ring5_num_entries;
9308 * Number of TQM ring 6 entries.
9310 * TQM fastpath rings should be sized large enough to accommodate the
9311 * maximum number of QPs (either L2 or RoCE, or both if shared)
9312 * that can be enqueued to the TQM ring.
9314 * Note that TQM ring sizes cannot be extended while the system is
9315 * operational. If a PF driver needs to extend a TQM ring, it needs
9316 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9317 * the backing store.
9319 uint32_t tqm_ring6_num_entries;
9321 * Number of TQM ring 7 entries.
9323 * TQM fastpath rings should be sized large enough to accommodate the
9324 * maximum number of QPs (either L2 or RoCE, or both if shared)
9325 * that can be enqueued to the TQM ring.
9327 * Note that TQM ring sizes cannot be extended while the system is
9328 * operational. If a PF driver needs to extend a TQM ring, it needs
9329 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9330 * the backing store.
9332 uint32_t tqm_ring7_num_entries;
9333 /* Number of MR/AV entries. */
9334 uint32_t mrav_num_entries;
9335 /* Number of Timer entries. */
9336 uint32_t tim_num_entries;
9337 /* Number of entries to reserve for QP1 */
9338 uint16_t qp_num_qp1_entries;
9339 /* Number of entries to reserve for L2 */
9340 uint16_t qp_num_l2_entries;
9341 /* Number of bytes that have been allocated for each context entry. */
9342 uint16_t qp_entry_size;
9343 /* Number of entries to reserve for L2 */
9344 uint16_t srq_num_l2_entries;
9345 /* Number of bytes that have been allocated for each context entry. */
9346 uint16_t srq_entry_size;
9347 /* Number of entries to reserve for L2 */
9348 uint16_t cq_num_l2_entries;
9349 /* Number of bytes that have been allocated for each context entry. */
9350 uint16_t cq_entry_size;
9351 /* Number of entries to reserve for VNIC entries */
9352 uint16_t vnic_num_vnic_entries;
9353 /* Number of entries to reserve for Ring table entries */
9354 uint16_t vnic_num_ring_table_entries;
9355 /* Number of bytes that have been allocated for each context entry. */
9356 uint16_t vnic_entry_size;
9357 /* Number of bytes that have been allocated for each context entry. */
9358 uint16_t stat_entry_size;
9359 /* Number of bytes that have been allocated for each context entry. */
9360 uint16_t tqm_entry_size;
9361 /* Number of bytes that have been allocated for each context entry. */
9362 uint16_t mrav_entry_size;
9363 /* Number of bytes that have been allocated for each context entry. */
9364 uint16_t tim_entry_size;
9365 } __attribute__((packed));
9367 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
9368 struct hwrm_func_backing_store_cfg_output {
9369 /* The specific error status for the command. */
9370 uint16_t error_code;
9371 /* The HWRM command request type. */
9373 /* The sequence ID from the original command. */
9375 /* The length of the response data in number of bytes. */
9377 uint8_t unused_0[7];
9379 * This field is used in Output records to indicate that the output
9380 * is completely written to RAM. This field should be read as '1'
9381 * to indicate that the output has been completely written.
9382 * When writing a command completion or response to an internal processor,
9383 * the order of writes has to be such that this field is written last.
9386 } __attribute__((packed));
9388 /********************************
9389 * hwrm_func_backing_store_qcfg *
9390 ********************************/
9393 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
9394 struct hwrm_func_backing_store_qcfg_input {
9395 /* The HWRM command request type. */
9398 * The completion ring to send the completion event on. This should
9399 * be the NQ ID returned from the `nq_alloc` HWRM command.
9403 * The sequence ID is used by the driver for tracking multiple
9404 * commands. This ID is treated as opaque data by the firmware and
9405 * the value is returned in the `hwrm_resp_hdr` upon completion.
9409 * The target ID of the command:
9410 * * 0x0-0xFFF8 - The function ID
9411 * * 0xFFF8-0xFFFE - Reserved for internal processors
9416 * A physical address pointer pointing to a host buffer that the
9417 * command's response data will be written. This can be either a host
9418 * physical address (HPA) or a guest physical address (GPA) and must
9419 * point to a physically contiguous block of memory.
9422 } __attribute__((packed));
9424 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
9425 struct hwrm_func_backing_store_qcfg_output {
9426 /* The specific error status for the command. */
9427 uint16_t error_code;
9428 /* The HWRM command request type. */
9430 /* The sequence ID from the original command. */
9432 /* The length of the response data in number of bytes. */
9436 * When set, the firmware only uses on-chip resources and does not
9437 * expect any backing store to be provided by the host driver. This
9438 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
9443 uint8_t unused_0[4];
9445 * This bit must be '1' for the qp fields to be
9448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
9451 * This bit must be '1' for the srq fields to be
9454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
9457 * This bit must be '1' for the cq fields to be
9460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
9463 * This bit must be '1' for the vnic fields to be
9466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
9469 * This bit must be '1' for the stat fields to be
9472 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
9475 * This bit must be '1' for the tqm_sp fields to be
9478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
9481 * This bit must be '1' for the tqm_ring0 fields to be
9484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
9487 * This bit must be '1' for the tqm_ring1 fields to be
9490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
9493 * This bit must be '1' for the tqm_ring2 fields to be
9496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
9499 * This bit must be '1' for the tqm_ring3 fields to be
9502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
9505 * This bit must be '1' for the tqm_ring4 fields to be
9508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
9511 * This bit must be '1' for the tqm_ring5 fields to be
9514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
9517 * This bit must be '1' for the tqm_ring6 fields to be
9520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
9523 * This bit must be '1' for the tqm_ring7 fields to be
9526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
9529 * This bit must be '1' for the mrav fields to be
9532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
9535 * This bit must be '1' for the tim fields to be
9538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
9540 /* QPC page size and level. */
9541 uint8_t qpc_pg_size_qpc_lvl;
9542 /* QPC PBL indirect levels. */
9543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
9545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
9546 /* PBL pointer is physical start address. */
9547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
9549 /* PBL pointer points to PTE table. */
9550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
9552 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
9555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
9556 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
9557 /* QPC page size. */
9558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
9560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
9562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
9563 (UINT32_C(0x0) << 4)
9565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
9566 (UINT32_C(0x1) << 4)
9568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
9569 (UINT32_C(0x2) << 4)
9571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
9572 (UINT32_C(0x3) << 4)
9574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
9575 (UINT32_C(0x4) << 4)
9577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
9578 (UINT32_C(0x5) << 4)
9579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
9580 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
9581 /* SRQ page size and level. */
9582 uint8_t srq_pg_size_srq_lvl;
9583 /* SRQ PBL indirect levels. */
9584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
9586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
9587 /* PBL pointer is physical start address. */
9588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
9590 /* PBL pointer points to PTE table. */
9591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
9593 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
9596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
9597 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
9598 /* SRQ page size. */
9599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
9601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
9603 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
9604 (UINT32_C(0x0) << 4)
9606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
9607 (UINT32_C(0x1) << 4)
9609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
9610 (UINT32_C(0x2) << 4)
9612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
9613 (UINT32_C(0x3) << 4)
9615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
9616 (UINT32_C(0x4) << 4)
9618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
9619 (UINT32_C(0x5) << 4)
9620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
9621 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
9622 /* CQ page size and level. */
9623 uint8_t cq_pg_size_cq_lvl;
9624 /* CQ PBL indirect levels. */
9625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
9627 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
9628 /* PBL pointer is physical start address. */
9629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
9631 /* PBL pointer points to PTE table. */
9632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
9634 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
9637 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
9638 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
9640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
9642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
9644 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
9645 (UINT32_C(0x0) << 4)
9647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
9648 (UINT32_C(0x1) << 4)
9650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
9651 (UINT32_C(0x2) << 4)
9653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
9654 (UINT32_C(0x3) << 4)
9656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
9657 (UINT32_C(0x4) << 4)
9659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
9660 (UINT32_C(0x5) << 4)
9661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
9662 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
9663 /* VNIC page size and level. */
9664 uint8_t vnic_pg_size_vnic_lvl;
9665 /* VNIC PBL indirect levels. */
9666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
9668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
9669 /* PBL pointer is physical start address. */
9670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
9672 /* PBL pointer points to PTE table. */
9673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
9675 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
9678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
9679 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
9680 /* VNIC page size. */
9681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
9683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
9685 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
9686 (UINT32_C(0x0) << 4)
9688 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
9689 (UINT32_C(0x1) << 4)
9691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
9692 (UINT32_C(0x2) << 4)
9694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
9695 (UINT32_C(0x3) << 4)
9697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
9698 (UINT32_C(0x4) << 4)
9700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
9701 (UINT32_C(0x5) << 4)
9702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
9703 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
9704 /* Stat page size and level. */
9705 uint8_t stat_pg_size_stat_lvl;
9706 /* Stat PBL indirect levels. */
9707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
9709 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
9710 /* PBL pointer is physical start address. */
9711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
9713 /* PBL pointer points to PTE table. */
9714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
9716 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
9719 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
9720 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
9721 /* Stat page size. */
9722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
9724 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
9726 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
9727 (UINT32_C(0x0) << 4)
9729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
9730 (UINT32_C(0x1) << 4)
9732 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
9733 (UINT32_C(0x2) << 4)
9735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
9736 (UINT32_C(0x3) << 4)
9738 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
9739 (UINT32_C(0x4) << 4)
9741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
9742 (UINT32_C(0x5) << 4)
9743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
9744 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
9745 /* TQM slow path page size and level. */
9746 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
9747 /* TQM slow path PBL indirect levels. */
9748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
9750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
9751 /* PBL pointer is physical start address. */
9752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
9754 /* PBL pointer points to PTE table. */
9755 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
9757 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
9760 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
9761 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
9762 /* TQM slow path page size. */
9763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
9765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
9767 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
9768 (UINT32_C(0x0) << 4)
9770 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
9771 (UINT32_C(0x1) << 4)
9773 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
9774 (UINT32_C(0x2) << 4)
9776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
9777 (UINT32_C(0x3) << 4)
9779 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
9780 (UINT32_C(0x4) << 4)
9782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
9783 (UINT32_C(0x5) << 4)
9784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
9785 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
9786 /* TQM ring 0 page size and level. */
9787 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9788 /* TQM ring 0 PBL indirect levels. */
9789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
9791 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
9792 /* PBL pointer is physical start address. */
9793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
9795 /* PBL pointer points to PTE table. */
9796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
9798 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
9801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
9802 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
9803 /* TQM ring 0 page size. */
9804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
9806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
9808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
9809 (UINT32_C(0x0) << 4)
9811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
9812 (UINT32_C(0x1) << 4)
9814 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
9815 (UINT32_C(0x2) << 4)
9817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
9818 (UINT32_C(0x3) << 4)
9820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
9821 (UINT32_C(0x4) << 4)
9823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
9824 (UINT32_C(0x5) << 4)
9825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
9826 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
9827 /* TQM ring 1 page size and level. */
9828 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9829 /* TQM ring 1 PBL indirect levels. */
9830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
9832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
9833 /* PBL pointer is physical start address. */
9834 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
9836 /* PBL pointer points to PTE table. */
9837 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
9839 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
9842 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
9843 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
9844 /* TQM ring 1 page size. */
9845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
9847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
9849 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
9850 (UINT32_C(0x0) << 4)
9852 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
9853 (UINT32_C(0x1) << 4)
9855 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
9856 (UINT32_C(0x2) << 4)
9858 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
9859 (UINT32_C(0x3) << 4)
9861 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
9862 (UINT32_C(0x4) << 4)
9864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
9865 (UINT32_C(0x5) << 4)
9866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
9867 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
9868 /* TQM ring 2 page size and level. */
9869 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9870 /* TQM ring 2 PBL indirect levels. */
9871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
9873 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
9874 /* PBL pointer is physical start address. */
9875 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
9877 /* PBL pointer points to PTE table. */
9878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
9880 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9881 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
9883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
9884 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
9885 /* TQM ring 2 page size. */
9886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
9888 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
9890 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
9891 (UINT32_C(0x0) << 4)
9893 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
9894 (UINT32_C(0x1) << 4)
9896 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
9897 (UINT32_C(0x2) << 4)
9899 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
9900 (UINT32_C(0x3) << 4)
9902 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
9903 (UINT32_C(0x4) << 4)
9905 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
9906 (UINT32_C(0x5) << 4)
9907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
9908 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
9909 /* TQM ring 3 page size and level. */
9910 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9911 /* TQM ring 3 PBL indirect levels. */
9912 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
9914 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
9915 /* PBL pointer is physical start address. */
9916 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
9918 /* PBL pointer points to PTE table. */
9919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
9921 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9922 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
9924 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
9925 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
9926 /* TQM ring 3 page size. */
9927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
9929 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
9931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
9932 (UINT32_C(0x0) << 4)
9934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
9935 (UINT32_C(0x1) << 4)
9937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
9938 (UINT32_C(0x2) << 4)
9940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
9941 (UINT32_C(0x3) << 4)
9943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
9944 (UINT32_C(0x4) << 4)
9946 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
9947 (UINT32_C(0x5) << 4)
9948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
9949 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
9950 /* TQM ring 4 page size and level. */
9951 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9952 /* TQM ring 4 PBL indirect levels. */
9953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
9955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
9956 /* PBL pointer is physical start address. */
9957 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
9959 /* PBL pointer points to PTE table. */
9960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
9962 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
9965 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
9966 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
9967 /* TQM ring 4 page size. */
9968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
9970 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
9972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
9973 (UINT32_C(0x0) << 4)
9975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
9976 (UINT32_C(0x1) << 4)
9978 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
9979 (UINT32_C(0x2) << 4)
9981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
9982 (UINT32_C(0x3) << 4)
9984 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
9985 (UINT32_C(0x4) << 4)
9987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
9988 (UINT32_C(0x5) << 4)
9989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
9990 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
9991 /* TQM ring 5 page size and level. */
9992 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9993 /* TQM ring 5 PBL indirect levels. */
9994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
9996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
9997 /* PBL pointer is physical start address. */
9998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
10000 /* PBL pointer points to PTE table. */
10001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
10003 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
10006 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
10007 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
10008 /* TQM ring 5 page size. */
10009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
10011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
10013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
10014 (UINT32_C(0x0) << 4)
10016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
10017 (UINT32_C(0x1) << 4)
10019 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
10020 (UINT32_C(0x2) << 4)
10022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
10023 (UINT32_C(0x3) << 4)
10025 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
10026 (UINT32_C(0x4) << 4)
10028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
10029 (UINT32_C(0x5) << 4)
10030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
10031 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
10032 /* TQM ring 6 page size and level. */
10033 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10034 /* TQM ring 6 PBL indirect levels. */
10035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
10037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
10038 /* PBL pointer is physical start address. */
10039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
10041 /* PBL pointer points to PTE table. */
10042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
10044 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
10047 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
10048 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
10049 /* TQM ring 6 page size. */
10050 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
10052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
10054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
10055 (UINT32_C(0x0) << 4)
10057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
10058 (UINT32_C(0x1) << 4)
10060 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
10061 (UINT32_C(0x2) << 4)
10063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
10064 (UINT32_C(0x3) << 4)
10066 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
10067 (UINT32_C(0x4) << 4)
10069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
10070 (UINT32_C(0x5) << 4)
10071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
10072 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
10073 /* TQM ring 7 page size and level. */
10074 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10075 /* TQM ring 7 PBL indirect levels. */
10076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
10078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
10079 /* PBL pointer is physical start address. */
10080 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
10082 /* PBL pointer points to PTE table. */
10083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
10085 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
10088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
10089 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
10090 /* TQM ring 7 page size. */
10091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
10093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
10095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
10096 (UINT32_C(0x0) << 4)
10098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
10099 (UINT32_C(0x1) << 4)
10101 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
10102 (UINT32_C(0x2) << 4)
10104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
10105 (UINT32_C(0x3) << 4)
10107 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
10108 (UINT32_C(0x4) << 4)
10110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
10111 (UINT32_C(0x5) << 4)
10112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
10113 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
10114 /* MR/AV page size and level. */
10115 uint8_t mrav_pg_size_mrav_lvl;
10116 /* MR/AV PBL indirect levels. */
10117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
10119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
10120 /* PBL pointer is physical start address. */
10121 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
10123 /* PBL pointer points to PTE table. */
10124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
10126 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
10129 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
10130 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
10131 /* MR/AV page size. */
10132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
10134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
10136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
10137 (UINT32_C(0x0) << 4)
10139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
10140 (UINT32_C(0x1) << 4)
10142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
10143 (UINT32_C(0x2) << 4)
10145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
10146 (UINT32_C(0x3) << 4)
10148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
10149 (UINT32_C(0x4) << 4)
10151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
10152 (UINT32_C(0x5) << 4)
10153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
10154 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
10155 /* Timer page size and level. */
10156 uint8_t tim_pg_size_tim_lvl;
10157 /* Timer PBL indirect levels. */
10158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
10160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
10161 /* PBL pointer is physical start address. */
10162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
10164 /* PBL pointer points to PTE table. */
10165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
10167 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
10170 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
10171 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
10172 /* Timer page size. */
10173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
10175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
10177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
10178 (UINT32_C(0x0) << 4)
10180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
10181 (UINT32_C(0x1) << 4)
10183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
10184 (UINT32_C(0x2) << 4)
10186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
10187 (UINT32_C(0x3) << 4)
10189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
10190 (UINT32_C(0x4) << 4)
10192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
10193 (UINT32_C(0x5) << 4)
10194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
10195 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
10196 /* QP page directory. */
10197 uint64_t qpc_page_dir;
10198 /* SRQ page directory. */
10199 uint64_t srq_page_dir;
10200 /* CQ page directory. */
10201 uint64_t cq_page_dir;
10202 /* VNIC page directory. */
10203 uint64_t vnic_page_dir;
10204 /* Stat page directory. */
10205 uint64_t stat_page_dir;
10206 /* TQM slowpath page directory. */
10207 uint64_t tqm_sp_page_dir;
10208 /* TQM ring 0 page directory. */
10209 uint64_t tqm_ring0_page_dir;
10210 /* TQM ring 1 page directory. */
10211 uint64_t tqm_ring1_page_dir;
10212 /* TQM ring 2 page directory. */
10213 uint64_t tqm_ring2_page_dir;
10214 /* TQM ring 3 page directory. */
10215 uint64_t tqm_ring3_page_dir;
10216 /* TQM ring 4 page directory. */
10217 uint64_t tqm_ring4_page_dir;
10218 /* TQM ring 5 page directory. */
10219 uint64_t tqm_ring5_page_dir;
10220 /* TQM ring 6 page directory. */
10221 uint64_t tqm_ring6_page_dir;
10222 /* TQM ring 7 page directory. */
10223 uint64_t tqm_ring7_page_dir;
10224 /* MR/AV page directory. */
10225 uint64_t mrav_page_dir;
10226 /* Timer page directory. */
10227 uint64_t tim_page_dir;
10228 /* Number of entries to reserve for QP1 */
10229 uint16_t qp_num_qp1_entries;
10230 /* Number of entries to reserve for L2 */
10231 uint16_t qp_num_l2_entries;
10232 /* Number of QPs. */
10233 uint32_t qp_num_entries;
10234 /* Number of SRQs. */
10235 uint32_t srq_num_entries;
10236 /* Number of entries to reserve for L2 */
10237 uint16_t srq_num_l2_entries;
10238 /* Number of entries to reserve for L2 */
10239 uint16_t cq_num_l2_entries;
10240 /* Number of CQs. */
10241 uint32_t cq_num_entries;
10242 /* Number of entries to reserve for VNIC entries */
10243 uint16_t vnic_num_vnic_entries;
10244 /* Number of entries to reserve for Ring table entries */
10245 uint16_t vnic_num_ring_table_entries;
10246 /* Number of Stats. */
10247 uint32_t stat_num_entries;
10248 /* Number of TQM slowpath entries. */
10249 uint32_t tqm_sp_num_entries;
10250 /* Number of TQM ring 0 entries. */
10251 uint32_t tqm_ring0_num_entries;
10252 /* Number of TQM ring 1 entries. */
10253 uint32_t tqm_ring1_num_entries;
10254 /* Number of TQM ring 2 entries. */
10255 uint32_t tqm_ring2_num_entries;
10256 /* Number of TQM ring 3 entries. */
10257 uint32_t tqm_ring3_num_entries;
10258 /* Number of TQM ring 4 entries. */
10259 uint32_t tqm_ring4_num_entries;
10260 /* Number of TQM ring 5 entries. */
10261 uint32_t tqm_ring5_num_entries;
10262 /* Number of TQM ring 6 entries. */
10263 uint32_t tqm_ring6_num_entries;
10264 /* Number of TQM ring 7 entries. */
10265 uint32_t tqm_ring7_num_entries;
10266 /* Number of MR/AV entries. */
10267 uint32_t mrav_num_entries;
10268 /* Number of Timer entries. */
10269 uint32_t tim_num_entries;
10270 uint8_t unused_1[7];
10272 * This field is used in Output records to indicate that the output
10273 * is completely written to RAM. This field should be read as '1'
10274 * to indicate that the output has been completely written.
10275 * When writing a command completion or response to an internal processor,
10276 * the order of writes has to be such that this field is written last.
10279 } __attribute__((packed));
10281 /***********************
10282 * hwrm_func_vlan_qcfg *
10283 ***********************/
10286 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
10287 struct hwrm_func_vlan_qcfg_input {
10288 /* The HWRM command request type. */
10291 * The completion ring to send the completion event on. This should
10292 * be the NQ ID returned from the `nq_alloc` HWRM command.
10294 uint16_t cmpl_ring;
10296 * The sequence ID is used by the driver for tracking multiple
10297 * commands. This ID is treated as opaque data by the firmware and
10298 * the value is returned in the `hwrm_resp_hdr` upon completion.
10302 * The target ID of the command:
10303 * * 0x0-0xFFF8 - The function ID
10304 * * 0xFFF8-0xFFFE - Reserved for internal processors
10307 uint16_t target_id;
10309 * A physical address pointer pointing to a host buffer that the
10310 * command's response data will be written. This can be either a host
10311 * physical address (HPA) or a guest physical address (GPA) and must
10312 * point to a physically contiguous block of memory.
10314 uint64_t resp_addr;
10316 * Function ID of the function that is being
10318 * If set to 0xFF... (All Fs), then the configuration is
10319 * for the requesting function.
10322 uint8_t unused_0[6];
10323 } __attribute__((packed));
10325 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
10326 struct hwrm_func_vlan_qcfg_output {
10327 /* The specific error status for the command. */
10328 uint16_t error_code;
10329 /* The HWRM command request type. */
10331 /* The sequence ID from the original command. */
10333 /* The length of the response data in number of bytes. */
10336 /* S-TAG VLAN identifier configured for the function. */
10338 /* S-TAG PCP value configured for the function. */
10342 * S-TAG TPID value configured for the function. This field is specified in
10343 * network byte order.
10345 uint16_t stag_tpid;
10346 /* C-TAG VLAN identifier configured for the function. */
10348 /* C-TAG PCP value configured for the function. */
10352 * C-TAG TPID value configured for the function. This field is specified in
10353 * network byte order.
10355 uint16_t ctag_tpid;
10360 uint8_t unused_3[3];
10362 * This field is used in Output records to indicate that the output
10363 * is completely written to RAM. This field should be read as '1'
10364 * to indicate that the output has been completely written.
10365 * When writing a command completion or response to an internal processor,
10366 * the order of writes has to be such that this field is written last.
10369 } __attribute__((packed));
10371 /**********************
10372 * hwrm_func_vlan_cfg *
10373 **********************/
10376 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
10377 struct hwrm_func_vlan_cfg_input {
10378 /* The HWRM command request type. */
10381 * The completion ring to send the completion event on. This should
10382 * be the NQ ID returned from the `nq_alloc` HWRM command.
10384 uint16_t cmpl_ring;
10386 * The sequence ID is used by the driver for tracking multiple
10387 * commands. This ID is treated as opaque data by the firmware and
10388 * the value is returned in the `hwrm_resp_hdr` upon completion.
10392 * The target ID of the command:
10393 * * 0x0-0xFFF8 - The function ID
10394 * * 0xFFF8-0xFFFE - Reserved for internal processors
10397 uint16_t target_id;
10399 * A physical address pointer pointing to a host buffer that the
10400 * command's response data will be written. This can be either a host
10401 * physical address (HPA) or a guest physical address (GPA) and must
10402 * point to a physically contiguous block of memory.
10404 uint64_t resp_addr;
10406 * Function ID of the function that is being
10408 * If set to 0xFF... (All Fs), then the configuration is
10409 * for the requesting function.
10412 uint8_t unused_0[2];
10415 * This bit must be '1' for the stag_vid field to be
10418 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
10420 * This bit must be '1' for the ctag_vid field to be
10423 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
10425 * This bit must be '1' for the stag_pcp field to be
10428 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
10430 * This bit must be '1' for the ctag_pcp field to be
10433 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
10435 * This bit must be '1' for the stag_tpid field to be
10438 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
10440 * This bit must be '1' for the ctag_tpid field to be
10443 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
10444 /* S-TAG VLAN identifier configured for the function. */
10446 /* S-TAG PCP value configured for the function. */
10450 * S-TAG TPID value configured for the function. This field is specified in
10451 * network byte order.
10453 uint16_t stag_tpid;
10454 /* C-TAG VLAN identifier configured for the function. */
10456 /* C-TAG PCP value configured for the function. */
10460 * C-TAG TPID value configured for the function. This field is specified in
10461 * network byte order.
10463 uint16_t ctag_tpid;
10468 uint8_t unused_3[4];
10469 } __attribute__((packed));
10471 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
10472 struct hwrm_func_vlan_cfg_output {
10473 /* The specific error status for the command. */
10474 uint16_t error_code;
10475 /* The HWRM command request type. */
10477 /* The sequence ID from the original command. */
10479 /* The length of the response data in number of bytes. */
10481 uint8_t unused_0[7];
10483 * This field is used in Output records to indicate that the output
10484 * is completely written to RAM. This field should be read as '1'
10485 * to indicate that the output has been completely written.
10486 * When writing a command completion or response to an internal processor,
10487 * the order of writes has to be such that this field is written last.
10490 } __attribute__((packed));
10492 /*******************************
10493 * hwrm_func_vf_vnic_ids_query *
10494 *******************************/
10497 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
10498 struct hwrm_func_vf_vnic_ids_query_input {
10499 /* The HWRM command request type. */
10502 * The completion ring to send the completion event on. This should
10503 * be the NQ ID returned from the `nq_alloc` HWRM command.
10505 uint16_t cmpl_ring;
10507 * The sequence ID is used by the driver for tracking multiple
10508 * commands. This ID is treated as opaque data by the firmware and
10509 * the value is returned in the `hwrm_resp_hdr` upon completion.
10513 * The target ID of the command:
10514 * * 0x0-0xFFF8 - The function ID
10515 * * 0xFFF8-0xFFFE - Reserved for internal processors
10518 uint16_t target_id;
10520 * A physical address pointer pointing to a host buffer that the
10521 * command's response data will be written. This can be either a host
10522 * physical address (HPA) or a guest physical address (GPA) and must
10523 * point to a physically contiguous block of memory.
10525 uint64_t resp_addr;
10527 * This value is used to identify a Virtual Function (VF).
10528 * The scope of VF ID is local within a PF.
10531 uint8_t unused_0[2];
10532 /* Max number of vnic ids in vnic id table */
10533 uint32_t max_vnic_id_cnt;
10534 /* This is the address for VF VNIC ID table */
10535 uint64_t vnic_id_tbl_addr;
10536 } __attribute__((packed));
10538 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
10539 struct hwrm_func_vf_vnic_ids_query_output {
10540 /* The specific error status for the command. */
10541 uint16_t error_code;
10542 /* The HWRM command request type. */
10544 /* The sequence ID from the original command. */
10546 /* The length of the response data in number of bytes. */
10549 * Actual number of vnic ids
10551 * Each VNIC ID is written as a 32-bit number.
10553 uint32_t vnic_id_cnt;
10554 uint8_t unused_0[3];
10556 * This field is used in Output records to indicate that the output
10557 * is completely written to RAM. This field should be read as '1'
10558 * to indicate that the output has been completely written.
10559 * When writing a command completion or response to an internal processor,
10560 * the order of writes has to be such that this field is written last.
10563 } __attribute__((packed));
10565 /***********************
10566 * hwrm_func_vf_bw_cfg *
10567 ***********************/
10570 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
10571 struct hwrm_func_vf_bw_cfg_input {
10572 /* The HWRM command request type. */
10575 * The completion ring to send the completion event on. This should
10576 * be the NQ ID returned from the `nq_alloc` HWRM command.
10578 uint16_t cmpl_ring;
10580 * The sequence ID is used by the driver for tracking multiple
10581 * commands. This ID is treated as opaque data by the firmware and
10582 * the value is returned in the `hwrm_resp_hdr` upon completion.
10586 * The target ID of the command:
10587 * * 0x0-0xFFF8 - The function ID
10588 * * 0xFFF8-0xFFFE - Reserved for internal processors
10591 uint16_t target_id;
10593 * A physical address pointer pointing to a host buffer that the
10594 * command's response data will be written. This can be either a host
10595 * physical address (HPA) or a guest physical address (GPA) and must
10596 * point to a physically contiguous block of memory.
10598 uint64_t resp_addr;
10600 * The number of VF functions that are being configured.
10601 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
10604 uint16_t unused[3];
10605 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
10607 /* The physical VF id the adjustment will be made to. */
10608 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
10609 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
10611 * This field configures the rate scale percentage of the VF as specified
10612 * by the physical VF id.
10614 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
10615 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
10616 /* 0% of the max tx rate */
10617 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
10618 (UINT32_C(0x0) << 12)
10619 /* 6.66% of the max tx rate */
10620 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
10621 (UINT32_C(0x1) << 12)
10622 /* 13.33% of the max tx rate */
10623 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
10624 (UINT32_C(0x2) << 12)
10625 /* 20% of the max tx rate */
10626 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
10627 (UINT32_C(0x3) << 12)
10628 /* 26.66% of the max tx rate */
10629 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
10630 (UINT32_C(0x4) << 12)
10631 /* 33% of the max tx rate */
10632 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
10633 (UINT32_C(0x5) << 12)
10634 /* 40% of the max tx rate */
10635 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
10636 (UINT32_C(0x6) << 12)
10637 /* 46.66% of the max tx rate */
10638 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
10639 (UINT32_C(0x7) << 12)
10640 /* 53.33% of the max tx rate */
10641 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
10642 (UINT32_C(0x8) << 12)
10643 /* 60% of the max tx rate */
10644 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
10645 (UINT32_C(0x9) << 12)
10646 /* 66.66% of the max tx rate */
10647 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
10648 (UINT32_C(0xa) << 12)
10649 /* 53.33% of the max tx rate */
10650 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
10651 (UINT32_C(0xb) << 12)
10652 /* 80% of the max tx rate */
10653 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
10654 (UINT32_C(0xc) << 12)
10655 /* 86.66% of the max tx rate */
10656 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
10657 (UINT32_C(0xd) << 12)
10658 /* 93.33% of the max tx rate */
10659 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
10660 (UINT32_C(0xe) << 12)
10661 /* 100% of the max tx rate */
10662 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
10663 (UINT32_C(0xf) << 12)
10664 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
10665 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
10666 } __attribute__((packed));
10668 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
10669 struct hwrm_func_vf_bw_cfg_output {
10670 /* The specific error status for the command. */
10671 uint16_t error_code;
10672 /* The HWRM command request type. */
10674 /* The sequence ID from the original command. */
10676 /* The length of the response data in number of bytes. */
10678 uint8_t unused_0[7];
10680 * This field is used in Output records to indicate that the output
10681 * is completely written to RAM. This field should be read as '1'
10682 * to indicate that the output has been completely written.
10683 * When writing a command completion or response to an internal processor,
10684 * the order of writes has to be such that this field is written last.
10687 } __attribute__((packed));
10689 /************************
10690 * hwrm_func_vf_bw_qcfg *
10691 ************************/
10694 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
10695 struct hwrm_func_vf_bw_qcfg_input {
10696 /* The HWRM command request type. */
10699 * The completion ring to send the completion event on. This should
10700 * be the NQ ID returned from the `nq_alloc` HWRM command.
10702 uint16_t cmpl_ring;
10704 * The sequence ID is used by the driver for tracking multiple
10705 * commands. This ID is treated as opaque data by the firmware and
10706 * the value is returned in the `hwrm_resp_hdr` upon completion.
10710 * The target ID of the command:
10711 * * 0x0-0xFFF8 - The function ID
10712 * * 0xFFF8-0xFFFE - Reserved for internal processors
10715 uint16_t target_id;
10717 * A physical address pointer pointing to a host buffer that the
10718 * command's response data will be written. This can be either a host
10719 * physical address (HPA) or a guest physical address (GPA) and must
10720 * point to a physically contiguous block of memory.
10722 uint64_t resp_addr;
10724 * The number of VF functions that are being queried.
10725 * The inline response space allows the host to query up to 50 VFs'
10726 * rate scale percentage
10729 uint16_t unused[3];
10730 /* These 16-bit fields contain the VF fid */
10732 /* The physical VF id of interest */
10733 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
10734 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
10735 } __attribute__((packed));
10737 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
10738 struct hwrm_func_vf_bw_qcfg_output {
10739 /* The specific error status for the command. */
10740 uint16_t error_code;
10741 /* The HWRM command request type. */
10743 /* The sequence ID from the original command. */
10745 /* The length of the response data in number of bytes. */
10748 * The number of VF functions that are being queried.
10749 * The inline response space allows the host to query up to 50 VFs' rate
10753 uint16_t unused[3];
10754 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
10756 /* The physical VF id the adjustment will be made to. */
10757 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
10758 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
10760 * This field configures the rate scale percentage of the VF as specified
10761 * by the physical VF id.
10763 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
10764 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
10765 /* 0% of the max tx rate */
10766 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
10767 (UINT32_C(0x0) << 12)
10768 /* 6.66% of the max tx rate */
10769 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
10770 (UINT32_C(0x1) << 12)
10771 /* 13.33% of the max tx rate */
10772 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
10773 (UINT32_C(0x2) << 12)
10774 /* 20% of the max tx rate */
10775 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
10776 (UINT32_C(0x3) << 12)
10777 /* 26.66% of the max tx rate */
10778 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
10779 (UINT32_C(0x4) << 12)
10780 /* 33% of the max tx rate */
10781 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
10782 (UINT32_C(0x5) << 12)
10783 /* 40% of the max tx rate */
10784 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
10785 (UINT32_C(0x6) << 12)
10786 /* 46.66% of the max tx rate */
10787 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
10788 (UINT32_C(0x7) << 12)
10789 /* 53.33% of the max tx rate */
10790 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
10791 (UINT32_C(0x8) << 12)
10792 /* 60% of the max tx rate */
10793 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
10794 (UINT32_C(0x9) << 12)
10795 /* 66.66% of the max tx rate */
10796 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
10797 (UINT32_C(0xa) << 12)
10798 /* 53.33% of the max tx rate */
10799 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
10800 (UINT32_C(0xb) << 12)
10801 /* 80% of the max tx rate */
10802 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
10803 (UINT32_C(0xc) << 12)
10804 /* 86.66% of the max tx rate */
10805 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
10806 (UINT32_C(0xd) << 12)
10807 /* 93.33% of the max tx rate */
10808 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
10809 (UINT32_C(0xe) << 12)
10810 /* 100% of the max tx rate */
10811 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
10812 (UINT32_C(0xf) << 12)
10813 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
10814 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
10815 uint8_t unused_0[7];
10817 * This field is used in Output records to indicate that the output
10818 * is completely written to RAM. This field should be read as '1'
10819 * to indicate that the output has been completely written.
10820 * When writing a command completion or response to an internal processor,
10821 * the order of writes has to be such that this field is written last.
10824 } __attribute__((packed));
10826 /***************************
10827 * hwrm_func_drv_if_change *
10828 ***************************/
10831 /* hwrm_func_drv_if_change_input (size:192b/24B) */
10832 struct hwrm_func_drv_if_change_input {
10833 /* The HWRM command request type. */
10836 * The completion ring to send the completion event on. This should
10837 * be the NQ ID returned from the `nq_alloc` HWRM command.
10839 uint16_t cmpl_ring;
10841 * The sequence ID is used by the driver for tracking multiple
10842 * commands. This ID is treated as opaque data by the firmware and
10843 * the value is returned in the `hwrm_resp_hdr` upon completion.
10847 * The target ID of the command:
10848 * * 0x0-0xFFF8 - The function ID
10849 * * 0xFFF8-0xFFFE - Reserved for internal processors
10852 uint16_t target_id;
10854 * A physical address pointer pointing to a host buffer that the
10855 * command's response data will be written. This can be either a host
10856 * physical address (HPA) or a guest physical address (GPA) and must
10857 * point to a physically contiguous block of memory.
10859 uint64_t resp_addr;
10862 * When this bit is '1', the function driver is indicating
10863 * that the IF state is changing to UP state. The call should
10864 * be made at the beginning of the driver's open call before
10865 * resources are allocated. After making the call, the driver
10866 * should check the response to see if any resources may have
10867 * changed (see the response below). If the driver fails
10868 * the open call, the driver should make this call again with
10869 * this bit cleared to indicate that the IF state is not UP.
10870 * During the driver's close call when the IF state is changing
10871 * to DOWN, the driver should make this call with the bit cleared
10872 * after all resources have been freed.
10874 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
10876 } __attribute__((packed));
10878 /* hwrm_func_drv_if_change_output (size:128b/16B) */
10879 struct hwrm_func_drv_if_change_output {
10880 /* The specific error status for the command. */
10881 uint16_t error_code;
10882 /* The HWRM command request type. */
10884 /* The sequence ID from the original command. */
10886 /* The length of the response data in number of bytes. */
10890 * When this bit is '1', it indicates that the resources reserved
10891 * for this function may have changed. The driver should check
10892 * resource capabilities and reserve resources again before
10893 * allocating resources.
10895 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
10897 uint8_t unused_0[3];
10899 * This field is used in Output records to indicate that the output
10900 * is completely written to RAM. This field should be read as '1'
10901 * to indicate that the output has been completely written.
10902 * When writing a command completion or response to an internal processor,
10903 * the order of writes has to be such that this field is written last.
10906 } __attribute__((packed));
10908 /*********************
10909 * hwrm_port_phy_cfg *
10910 *********************/
10913 /* hwrm_port_phy_cfg_input (size:448b/56B) */
10914 struct hwrm_port_phy_cfg_input {
10915 /* The HWRM command request type. */
10918 * The completion ring to send the completion event on. This should
10919 * be the NQ ID returned from the `nq_alloc` HWRM command.
10921 uint16_t cmpl_ring;
10923 * The sequence ID is used by the driver for tracking multiple
10924 * commands. This ID is treated as opaque data by the firmware and
10925 * the value is returned in the `hwrm_resp_hdr` upon completion.
10929 * The target ID of the command:
10930 * * 0x0-0xFFF8 - The function ID
10931 * * 0xFFF8-0xFFFE - Reserved for internal processors
10934 uint16_t target_id;
10936 * A physical address pointer pointing to a host buffer that the
10937 * command's response data will be written. This can be either a host
10938 * physical address (HPA) or a guest physical address (GPA) and must
10939 * point to a physically contiguous block of memory.
10941 uint64_t resp_addr;
10944 * When this bit is set to '1', the PHY for the port shall
10947 * # If this bit is set to 1, then the HWRM shall reset the
10948 * PHY after applying PHY configuration changes specified
10950 * # In order to guarantee that PHY configuration changes
10951 * specified in this command take effect, the HWRM
10952 * client should set this flag to 1.
10953 * # If this bit is not set to 1, then the HWRM may reset
10954 * the PHY depending on the current PHY configuration and
10955 * settings specified in this command.
10957 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
10959 /* deprecated bit. Do not use!!! */
10960 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
10963 * When this bit is set to '1', the link shall be forced to
10964 * the force_link_speed value.
10966 * When this bit is set to '1', the HWRM client should
10967 * not enable any of the auto negotiation related
10968 * fields represented by auto_XXX fields in this command.
10969 * When this bit is set to '1' and the HWRM client has
10970 * enabled a auto_XXX field in this command, then the
10971 * HWRM shall ignore the enabled auto_XXX field.
10973 * When this bit is set to zero, the link
10974 * shall be allowed to autoneg.
10976 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
10979 * When this bit is set to '1', the auto-negotiation process
10980 * shall be restarted on the link.
10982 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
10985 * When this bit is set to '1', Energy Efficient Ethernet
10986 * (EEE) is requested to be enabled on this link.
10987 * If EEE is not supported on this port, then this flag
10988 * shall be ignored by the HWRM.
10990 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
10993 * When this bit is set to '1', Energy Efficient Ethernet
10994 * (EEE) is requested to be disabled on this link.
10995 * If EEE is not supported on this port, then this flag
10996 * shall be ignored by the HWRM.
10998 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
11001 * When this bit is set to '1' and EEE is enabled on this
11002 * link, then TX LPI is requested to be enabled on the link.
11003 * If EEE is not supported on this port, then this flag
11004 * shall be ignored by the HWRM.
11005 * If EEE is disabled on this port, then this flag shall be
11006 * ignored by the HWRM.
11008 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
11011 * When this bit is set to '1' and EEE is enabled on this
11012 * link, then TX LPI is requested to be disabled on the link.
11013 * If EEE is not supported on this port, then this flag
11014 * shall be ignored by the HWRM.
11015 * If EEE is disabled on this port, then this flag shall be
11016 * ignored by the HWRM.
11018 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
11021 * When set to 1, then the HWRM shall enable FEC autonegotitation
11022 * on this port if supported.
11023 * When set to 0, then this flag shall be ignored.
11024 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
11027 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
11030 * When set to 1, then the HWRM shall disable FEC autonegotiation
11031 * on this port if supported.
11032 * When set to 0, then this flag shall be ignored.
11033 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
11036 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
11039 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
11040 * on this port if supported.
11041 * When set to 0, then this flag shall be ignored.
11042 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
11045 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
11048 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
11049 * on this port if supported.
11050 * When set to 0, then this flag shall be ignored.
11051 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
11054 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
11057 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
11058 * on this port if supported.
11059 * When set to 0, then this flag shall be ignored.
11060 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
11063 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
11066 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
11067 * on this port if supported.
11068 * When set to 0, then this flag shall be ignored.
11069 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
11072 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
11075 * When this bit is set to '1', the link shall be forced to
11078 * # When this bit is set to '1", all other
11079 * command input settings related to the link speed shall
11081 * Once the link state is forced down, it can be
11082 * explicitly cleared from that state by setting this flag
11084 * # If this flag is set to '0', then the link shall be
11085 * cleared from forced down state if the link is in forced
11087 * There may be conditions (e.g. out-of-band or sideband
11088 * configuration changes for the link) outside the scope
11089 * of the HWRM implementation that may clear forced down
11092 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
11096 * This bit must be '1' for the auto_mode field to be
11099 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
11102 * This bit must be '1' for the auto_duplex field to be
11105 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
11108 * This bit must be '1' for the auto_pause field to be
11111 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
11114 * This bit must be '1' for the auto_link_speed field to be
11117 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
11120 * This bit must be '1' for the auto_link_speed_mask field to be
11123 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
11126 * This bit must be '1' for the wirespeed field to be
11129 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
11132 * This bit must be '1' for the lpbk field to be
11135 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
11138 * This bit must be '1' for the preemphasis field to be
11141 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
11144 * This bit must be '1' for the force_pause field to be
11147 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
11150 * This bit must be '1' for the eee_link_speed_mask field to be
11153 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
11156 * This bit must be '1' for the tx_lpi_timer field to be
11159 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
11161 /* Port ID of port that is to be configured. */
11164 * This is the speed that will be used if the force
11165 * bit is '1'. If unsupported speed is selected, an error
11166 * will be generated.
11168 uint16_t force_link_speed;
11169 /* 100Mb link speed */
11170 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
11171 /* 1Gb link speed */
11172 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
11173 /* 2Gb link speed */
11174 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
11175 /* 25Gb link speed */
11176 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
11177 /* 10Gb link speed */
11178 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
11179 /* 20Mb link speed */
11180 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
11181 /* 25Gb link speed */
11182 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
11183 /* 40Gb link speed */
11184 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
11185 /* 50Gb link speed */
11186 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
11187 /* 100Gb link speed */
11188 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
11189 /* 200Gb link speed */
11190 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
11191 /* 10Mb link speed */
11192 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
11193 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
11194 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
11196 * This value is used to identify what autoneg mode is
11197 * used when the link speed is not being forced.
11200 /* Disable autoneg or autoneg disabled. No speeds are selected. */
11201 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
11202 /* Select all possible speeds for autoneg mode. */
11203 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
11205 * Select only the auto_link_speed speed for autoneg mode. This mode has
11206 * been DEPRECATED. An HWRM client should not use this mode.
11208 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
11210 * Select the auto_link_speed or any speed below that speed for autoneg.
11211 * This mode has been DEPRECATED. An HWRM client should not use this mode.
11213 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
11215 * Select the speeds based on the corresponding link speed mask value
11216 * that is provided.
11218 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
11219 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
11220 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
11222 * This is the duplex setting that will be used if the autoneg_mode
11223 * is "one_speed" or "one_or_below".
11225 uint8_t auto_duplex;
11226 /* Half Duplex will be requested. */
11227 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
11228 /* Full duplex will be requested. */
11229 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
11230 /* Both Half and Full dupex will be requested. */
11231 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
11232 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
11233 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
11235 * This value is used to configure the pause that will be
11236 * used for autonegotiation.
11237 * Add text on the usage of auto_pause and force_pause.
11239 uint8_t auto_pause;
11241 * When this bit is '1', Generation of tx pause messages
11242 * has been requested. Disabled otherwise.
11244 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
11247 * When this bit is '1', Reception of rx pause messages
11248 * has been requested. Disabled otherwise.
11250 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
11253 * When set to 1, the advertisement of pause is enabled.
11255 * # When the auto_mode is not set to none and this flag is
11256 * set to 1, then the auto_pause bits on this port are being
11257 * advertised and autoneg pause results are being interpreted.
11258 * # When the auto_mode is not set to none and this
11259 * flag is set to 0, the pause is forced as indicated in
11260 * force_pause, and also advertised as auto_pause bits, but
11261 * the autoneg results are not interpreted since the pause
11262 * configuration is being forced.
11263 * # When the auto_mode is set to none and this flag is set to
11264 * 1, auto_pause bits should be ignored and should be set to 0.
11266 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
11270 * This is the speed that will be used if the autoneg_mode
11271 * is "one_speed" or "one_or_below". If an unsupported speed
11272 * is selected, an error will be generated.
11274 uint16_t auto_link_speed;
11275 /* 100Mb link speed */
11276 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
11277 /* 1Gb link speed */
11278 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
11279 /* 2Gb link speed */
11280 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
11281 /* 25Gb link speed */
11282 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
11283 /* 10Gb link speed */
11284 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
11285 /* 20Mb link speed */
11286 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
11287 /* 25Gb link speed */
11288 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
11289 /* 40Gb link speed */
11290 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
11291 /* 50Gb link speed */
11292 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
11293 /* 100Gb link speed */
11294 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
11295 /* 200Gb link speed */
11296 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
11297 /* 10Mb link speed */
11298 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
11299 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
11300 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
11302 * This is a mask of link speeds that will be used if
11303 * autoneg_mode is "mask". If unsupported speed is enabled
11304 * an error will be generated.
11306 uint16_t auto_link_speed_mask;
11307 /* 100Mb link speed (Half-duplex) */
11308 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
11310 /* 100Mb link speed (Full-duplex) */
11311 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
11313 /* 1Gb link speed (Half-duplex) */
11314 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
11316 /* 1Gb link speed (Full-duplex) */
11317 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
11319 /* 2Gb link speed */
11320 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
11322 /* 25Gb link speed */
11323 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
11325 /* 10Gb link speed */
11326 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
11328 /* 20Gb link speed */
11329 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
11331 /* 25Gb link speed */
11332 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
11334 /* 40Gb link speed */
11335 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
11337 /* 50Gb link speed */
11338 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
11340 /* 100Gb link speed */
11341 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
11343 /* 10Mb link speed (Half-duplex) */
11344 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
11346 /* 10Mb link speed (Full-duplex) */
11347 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
11349 /* 200Gb link speed */
11350 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
11352 /* This value controls the wirespeed feature. */
11354 /* Wirespeed feature is disabled. */
11355 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
11356 /* Wirespeed feature is enabled. */
11357 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
11358 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
11359 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
11360 /* This value controls the loopback setting for the PHY. */
11362 /* No loopback is selected. Normal operation. */
11363 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
11365 * The HW will be configured with local loopback such that
11366 * host data is sent back to the host without modification.
11368 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
11370 * The HW will be configured with remote loopback such that
11371 * port logic will send packets back out the transmitter that
11374 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
11376 * The HW will be configured with external loopback such that
11377 * host data is sent on the trasmitter and based on the external
11378 * loopback connection the data will be received without modification.
11380 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
11381 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
11382 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
11384 * This value is used to configure the pause that will be
11385 * used for force mode.
11387 uint8_t force_pause;
11389 * When this bit is '1', Generation of tx pause messages
11390 * is supported. Disabled otherwise.
11392 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
11394 * When this bit is '1', Reception of rx pause messages
11395 * is supported. Disabled otherwise.
11397 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
11400 * This value controls the pre-emphasis to be used for the
11401 * link. Driver should not set this value (use
11402 * enable.preemphasis = 0) unless driver is sure of setting.
11403 * Normally HWRM FW will determine proper pre-emphasis.
11405 uint32_t preemphasis;
11407 * Setting for link speed mask that is used to
11408 * advertise speeds during autonegotiation when EEE is enabled.
11409 * This field is valid only when EEE is enabled.
11410 * The speeds specified in this field shall be a subset of
11411 * speeds specified in auto_link_speed_mask.
11412 * If EEE is enabled,then at least one speed shall be provided
11415 uint16_t eee_link_speed_mask;
11417 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
11419 /* 100Mb link speed (Full-duplex) */
11420 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
11423 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
11425 /* 1Gb link speed (Full-duplex) */
11426 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
11429 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
11432 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
11434 /* 10Gb link speed */
11435 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
11437 uint8_t unused_2[2];
11439 * Reuested setting of TX LPI timer in microseconds.
11440 * This field is valid only when EEE is enabled and TX LPI is
11443 uint32_t tx_lpi_timer;
11444 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
11445 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
11447 } __attribute__((packed));
11449 /* hwrm_port_phy_cfg_output (size:128b/16B) */
11450 struct hwrm_port_phy_cfg_output {
11451 /* The specific error status for the command. */
11452 uint16_t error_code;
11453 /* The HWRM command request type. */
11455 /* The sequence ID from the original command. */
11457 /* The length of the response data in number of bytes. */
11459 uint8_t unused_0[7];
11461 * This field is used in Output records to indicate that the output
11462 * is completely written to RAM. This field should be read as '1'
11463 * to indicate that the output has been completely written.
11464 * When writing a command completion or response to an internal processor,
11465 * the order of writes has to be such that this field is written last.
11468 } __attribute__((packed));
11470 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
11471 struct hwrm_port_phy_cfg_cmd_err {
11473 * command specific error codes that goes to
11474 * the cmd_err field in Common HWRM Error Response.
11477 /* Unknown error */
11478 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
11479 /* Unable to complete operation due to invalid speed */
11480 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
11482 * retry the command since the phy is not ready.
11483 * retry count is returned in opaque_0.
11484 * This is only valid for the first command and
11485 * this value will not change for successive calls.
11486 * but if a 0 is returned at any time then this should
11487 * be treated as an un recoverable failure,
11489 * retry interval in milli seconds is returned in opaque_1.
11490 * This specifies the time that user should wait before
11491 * issuing the next port_phy_cfg command.
11493 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
11494 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
11495 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
11496 uint8_t unused_0[7];
11497 } __attribute__((packed));
11499 /**********************
11500 * hwrm_port_phy_qcfg *
11501 **********************/
11504 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
11505 struct hwrm_port_phy_qcfg_input {
11506 /* The HWRM command request type. */
11509 * The completion ring to send the completion event on. This should
11510 * be the NQ ID returned from the `nq_alloc` HWRM command.
11512 uint16_t cmpl_ring;
11514 * The sequence ID is used by the driver for tracking multiple
11515 * commands. This ID is treated as opaque data by the firmware and
11516 * the value is returned in the `hwrm_resp_hdr` upon completion.
11520 * The target ID of the command:
11521 * * 0x0-0xFFF8 - The function ID
11522 * * 0xFFF8-0xFFFE - Reserved for internal processors
11525 uint16_t target_id;
11527 * A physical address pointer pointing to a host buffer that the
11528 * command's response data will be written. This can be either a host
11529 * physical address (HPA) or a guest physical address (GPA) and must
11530 * point to a physically contiguous block of memory.
11532 uint64_t resp_addr;
11533 /* Port ID of port that is to be queried. */
11535 uint8_t unused_0[6];
11536 } __attribute__((packed));
11538 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
11539 struct hwrm_port_phy_qcfg_output {
11540 /* The specific error status for the command. */
11541 uint16_t error_code;
11542 /* The HWRM command request type. */
11544 /* The sequence ID from the original command. */
11546 /* The length of the response data in number of bytes. */
11548 /* This value indicates the current link status. */
11550 /* There is no link or cable detected. */
11551 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
11552 /* There is no link, but a cable has been detected. */
11553 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
11554 /* There is a link. */
11555 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
11556 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
11557 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
11559 /* This value indicates the current link speed of the connection. */
11560 uint16_t link_speed;
11561 /* 100Mb link speed */
11562 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
11563 /* 1Gb link speed */
11564 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
11565 /* 2Gb link speed */
11566 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
11567 /* 25Gb link speed */
11568 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
11569 /* 10Gb link speed */
11570 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
11571 /* 20Mb link speed */
11572 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
11573 /* 25Gb link speed */
11574 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
11575 /* 40Gb link speed */
11576 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
11577 /* 50Gb link speed */
11578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
11579 /* 100Gb link speed */
11580 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
11581 /* 200Gb link speed */
11582 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
11583 /* 10Mb link speed */
11584 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
11585 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
11586 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
11588 * This value is indicates the duplex of the current
11591 uint8_t duplex_cfg;
11592 /* Half Duplex connection. */
11593 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
11594 /* Full duplex connection. */
11595 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
11596 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
11597 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
11599 * This value is used to indicate the current
11600 * pause configuration. When autoneg is enabled, this value
11601 * represents the autoneg results of pause configuration.
11605 * When this bit is '1', Generation of tx pause messages
11606 * is supported. Disabled otherwise.
11608 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
11610 * When this bit is '1', Reception of rx pause messages
11611 * is supported. Disabled otherwise.
11613 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
11615 * The supported speeds for the port. This is a bit mask.
11616 * For each speed that is supported, the corrresponding
11617 * bit will be set to '1'.
11619 uint16_t support_speeds;
11620 /* 100Mb link speed (Half-duplex) */
11621 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
11623 /* 100Mb link speed (Full-duplex) */
11624 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
11626 /* 1Gb link speed (Half-duplex) */
11627 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
11629 /* 1Gb link speed (Full-duplex) */
11630 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
11632 /* 2Gb link speed */
11633 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
11635 /* 25Gb link speed */
11636 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
11638 /* 10Gb link speed */
11639 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
11641 /* 20Gb link speed */
11642 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
11644 /* 25Gb link speed */
11645 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
11647 /* 40Gb link speed */
11648 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
11650 /* 50Gb link speed */
11651 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
11653 /* 100Gb link speed */
11654 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
11656 /* 10Mb link speed (Half-duplex) */
11657 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
11659 /* 10Mb link speed (Full-duplex) */
11660 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
11662 /* 200Gb link speed */
11663 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
11666 * Current setting of forced link speed.
11667 * When the link speed is not being forced, this
11668 * value shall be set to 0.
11670 uint16_t force_link_speed;
11671 /* 100Mb link speed */
11672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
11673 /* 1Gb link speed */
11674 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
11675 /* 2Gb link speed */
11676 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
11677 /* 25Gb link speed */
11678 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
11679 /* 10Gb link speed */
11680 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
11681 /* 20Mb link speed */
11682 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
11683 /* 25Gb link speed */
11684 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
11685 /* 40Gb link speed */
11686 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
11688 /* 50Gb link speed */
11689 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
11691 /* 100Gb link speed */
11692 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
11694 /* 200Gb link speed */
11695 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
11697 /* 10Mb link speed */
11698 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
11700 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
11701 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
11702 /* Current setting of auto negotiation mode. */
11704 /* Disable autoneg or autoneg disabled. No speeds are selected. */
11705 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
11706 /* Select all possible speeds for autoneg mode. */
11707 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
11709 * Select only the auto_link_speed speed for autoneg mode. This mode has
11710 * been DEPRECATED. An HWRM client should not use this mode.
11712 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
11714 * Select the auto_link_speed or any speed below that speed for autoneg.
11715 * This mode has been DEPRECATED. An HWRM client should not use this mode.
11717 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
11719 * Select the speeds based on the corresponding link speed mask value
11720 * that is provided.
11722 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
11723 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
11724 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
11726 * Current setting of pause autonegotiation.
11727 * Move autoneg_pause flag here.
11729 uint8_t auto_pause;
11731 * When this bit is '1', Generation of tx pause messages
11732 * has been requested. Disabled otherwise.
11734 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
11737 * When this bit is '1', Reception of rx pause messages
11738 * has been requested. Disabled otherwise.
11740 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
11743 * When set to 1, the advertisement of pause is enabled.
11745 * # When the auto_mode is not set to none and this flag is
11746 * set to 1, then the auto_pause bits on this port are being
11747 * advertised and autoneg pause results are being interpreted.
11748 * # When the auto_mode is not set to none and this
11749 * flag is set to 0, the pause is forced as indicated in
11750 * force_pause, and also advertised as auto_pause bits, but
11751 * the autoneg results are not interpreted since the pause
11752 * configuration is being forced.
11753 * # When the auto_mode is set to none and this flag is set to
11754 * 1, auto_pause bits should be ignored and should be set to 0.
11756 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
11759 * Current setting for auto_link_speed. This field is only
11760 * valid when auto_mode is set to "one_speed" or "one_or_below".
11762 uint16_t auto_link_speed;
11763 /* 100Mb link speed */
11764 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
11765 /* 1Gb link speed */
11766 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
11767 /* 2Gb link speed */
11768 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
11769 /* 25Gb link speed */
11770 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
11771 /* 10Gb link speed */
11772 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
11773 /* 20Mb link speed */
11774 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
11775 /* 25Gb link speed */
11776 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
11777 /* 40Gb link speed */
11778 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
11779 /* 50Gb link speed */
11780 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
11781 /* 100Gb link speed */
11782 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
11783 /* 200Gb link speed */
11784 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
11785 /* 10Mb link speed */
11786 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
11788 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
11789 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
11791 * Current setting for auto_link_speed_mask that is used to
11792 * advertise speeds during autonegotiation.
11793 * This field is only valid when auto_mode is set to "mask".
11794 * The speeds specified in this field shall be a subset of
11795 * supported speeds on this port.
11797 uint16_t auto_link_speed_mask;
11798 /* 100Mb link speed (Half-duplex) */
11799 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
11801 /* 100Mb link speed (Full-duplex) */
11802 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
11804 /* 1Gb link speed (Half-duplex) */
11805 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
11807 /* 1Gb link speed (Full-duplex) */
11808 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
11810 /* 2Gb link speed */
11811 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
11813 /* 25Gb link speed */
11814 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
11816 /* 10Gb link speed */
11817 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
11819 /* 20Gb link speed */
11820 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
11822 /* 25Gb link speed */
11823 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
11825 /* 40Gb link speed */
11826 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
11828 /* 50Gb link speed */
11829 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
11831 /* 100Gb link speed */
11832 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
11834 /* 10Mb link speed (Half-duplex) */
11835 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
11837 /* 10Mb link speed (Full-duplex) */
11838 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
11840 /* 200Gb link speed */
11841 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
11843 /* Current setting for wirespeed. */
11845 /* Wirespeed feature is disabled. */
11846 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
11847 /* Wirespeed feature is enabled. */
11848 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
11849 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
11850 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
11851 /* Current setting for loopback. */
11853 /* No loopback is selected. Normal operation. */
11854 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11856 * The HW will be configured with local loopback such that
11857 * host data is sent back to the host without modification.
11859 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11861 * The HW will be configured with remote loopback such that
11862 * port logic will send packets back out the transmitter that
11865 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11867 * The HW will be configured with external loopback such that
11868 * host data is sent on the trasmitter and based on the external
11869 * loopback connection the data will be received without modification.
11871 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
11872 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
11873 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
11875 * Current setting of forced pause.
11876 * When the pause configuration is not being forced, then
11877 * this value shall be set to 0.
11879 uint8_t force_pause;
11881 * When this bit is '1', Generation of tx pause messages
11882 * is supported. Disabled otherwise.
11884 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
11886 * When this bit is '1', Reception of rx pause messages
11887 * is supported. Disabled otherwise.
11889 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
11891 * This value indicates the current status of the optics module on
11894 uint8_t module_status;
11895 /* Module is inserted and accepted */
11896 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
11898 /* Module is rejected and transmit side Laser is disabled. */
11899 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
11901 /* Module mismatch warning. */
11902 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
11904 /* Module is rejected and powered down. */
11905 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
11907 /* Module is not inserted. */
11908 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
11910 /* Module status is not applicable. */
11911 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
11913 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
11914 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
11915 /* Current setting for preemphasis. */
11916 uint32_t preemphasis;
11917 /* This field represents the major version of the PHY. */
11919 /* This field represents the minor version of the PHY. */
11921 /* This field represents the build version of the PHY. */
11923 /* This value represents a PHY type. */
11926 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
11929 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
11931 /* BASE-KR4 (Deprecated) */
11932 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
11935 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
11938 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
11940 /* BASE-KR2 (Deprecated) */
11941 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
11944 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
11947 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
11950 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
11952 /* EEE capable BASE-T */
11953 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
11955 /* SGMII connected external PHY */
11956 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
11958 /* 25G_BASECR_CA_L */
11959 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
11961 /* 25G_BASECR_CA_S */
11962 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
11964 /* 25G_BASECR_CA_N */
11965 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
11968 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
11971 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
11974 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
11977 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
11980 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
11982 /* 100G_BASESR10 */
11983 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
11986 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
11989 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
11992 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
11995 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
11997 /* 40G_ACTIVE_CABLE */
11998 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
12001 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
12004 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
12007 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
12010 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
12013 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
12016 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
12019 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
12021 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
12022 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
12023 /* This value represents a media type. */
12024 uint8_t media_type;
12026 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
12028 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
12029 /* Direct Attached Copper */
12030 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
12032 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
12033 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
12034 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
12035 /* This value represents a transceiver type. */
12036 uint8_t xcvr_pkg_type;
12037 /* PHY and MAC are in the same package */
12038 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
12040 /* PHY and MAC are in different packages */
12041 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
12043 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
12044 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
12045 uint8_t eee_config_phy_addr;
12046 /* This field represents PHY address. */
12047 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
12049 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
12051 * This field represents flags related to EEE configuration.
12052 * These EEE configuration flags are valid only when the
12053 * auto_mode is not set to none (in other words autonegotiation
12056 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
12058 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
12060 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
12061 * Speeds for autoneg with EEE mode enabled
12062 * are based on eee_link_speed_mask.
12064 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
12067 * This flag is valid only when eee_enabled is set to 1.
12069 * # If eee_enabled is set to 0, then EEE mode is disabled
12070 * and this flag shall be ignored.
12071 * # If eee_enabled is set to 1 and this flag is set to 1,
12072 * then Energy Efficient Ethernet (EEE) mode is enabled
12074 * # If eee_enabled is set to 1 and this flag is set to 0,
12075 * then Energy Efficient Ethernet (EEE) mode is enabled
12076 * but is currently not in use.
12078 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
12081 * This flag is valid only when eee_enabled is set to 1.
12083 * # If eee_enabled is set to 0, then EEE mode is disabled
12084 * and this flag shall be ignored.
12085 * # If eee_enabled is set to 1 and this flag is set to 1,
12086 * then Energy Efficient Ethernet (EEE) mode is enabled
12087 * and TX LPI is enabled.
12088 * # If eee_enabled is set to 1 and this flag is set to 0,
12089 * then Energy Efficient Ethernet (EEE) mode is enabled
12090 * but TX LPI is disabled.
12092 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
12095 * When set to 1, the parallel detection is used to determine
12096 * the speed of the link partner.
12098 * Parallel detection is used when a autonegotiation capable
12099 * device is connected to a link parter that is not capable
12100 * of autonegotiation.
12102 uint8_t parallel_detect;
12104 * When set to 1, the parallel detection is used to determine
12105 * the speed of the link partner.
12107 * Parallel detection is used when a autonegotiation capable
12108 * device is connected to a link parter that is not capable
12109 * of autonegotiation.
12111 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
12113 * The advertised speeds for the port by the link partner.
12114 * Each advertised speed will be set to '1'.
12116 uint16_t link_partner_adv_speeds;
12117 /* 100Mb link speed (Half-duplex) */
12118 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
12120 /* 100Mb link speed (Full-duplex) */
12121 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
12123 /* 1Gb link speed (Half-duplex) */
12124 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
12126 /* 1Gb link speed (Full-duplex) */
12127 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
12129 /* 2Gb link speed */
12130 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
12132 /* 25Gb link speed */
12133 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
12135 /* 10Gb link speed */
12136 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
12138 /* 20Gb link speed */
12139 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
12141 /* 25Gb link speed */
12142 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
12144 /* 40Gb link speed */
12145 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
12147 /* 50Gb link speed */
12148 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
12150 /* 100Gb link speed */
12151 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
12153 /* 10Mb link speed (Half-duplex) */
12154 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
12156 /* 10Mb link speed (Full-duplex) */
12157 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
12160 * The advertised autoneg for the port by the link partner.
12161 * This field is deprecated and should be set to 0.
12163 uint8_t link_partner_adv_auto_mode;
12164 /* Disable autoneg or autoneg disabled. No speeds are selected. */
12165 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
12167 /* Select all possible speeds for autoneg mode. */
12168 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
12171 * Select only the auto_link_speed speed for autoneg mode. This mode has
12172 * been DEPRECATED. An HWRM client should not use this mode.
12174 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
12177 * Select the auto_link_speed or any speed below that speed for autoneg.
12178 * This mode has been DEPRECATED. An HWRM client should not use this mode.
12180 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
12183 * Select the speeds based on the corresponding link speed mask value
12184 * that is provided.
12186 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
12188 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
12189 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
12190 /* The advertised pause settings on the port by the link partner. */
12191 uint8_t link_partner_adv_pause;
12193 * When this bit is '1', Generation of tx pause messages
12194 * is supported. Disabled otherwise.
12196 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
12199 * When this bit is '1', Reception of rx pause messages
12200 * is supported. Disabled otherwise.
12202 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
12205 * Current setting for link speed mask that is used to
12206 * advertise speeds during autonegotiation when EEE is enabled.
12207 * This field is valid only when eee_enabled flags is set to 1.
12208 * The speeds specified in this field shall be a subset of
12209 * speeds specified in auto_link_speed_mask.
12211 uint16_t adv_eee_link_speed_mask;
12213 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
12215 /* 100Mb link speed (Full-duplex) */
12216 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
12219 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
12221 /* 1Gb link speed (Full-duplex) */
12222 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
12225 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
12228 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
12230 /* 10Gb link speed */
12231 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
12234 * Current setting for link speed mask that is advertised by
12235 * the link partner when EEE is enabled.
12236 * This field is valid only when eee_enabled flags is set to 1.
12238 uint16_t link_partner_adv_eee_link_speed_mask;
12240 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
12242 /* 100Mb link speed (Full-duplex) */
12243 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
12246 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
12248 /* 1Gb link speed (Full-duplex) */
12249 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
12252 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
12255 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
12257 /* 10Gb link speed */
12258 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
12260 uint32_t xcvr_identifier_type_tx_lpi_timer;
12262 * Current setting of TX LPI timer in microseconds.
12263 * This field is valid only when_eee_enabled flag is set to 1
12264 * and tx_lpi_enabled is set to 1.
12266 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
12268 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
12269 /* This value represents transceiver identifier type. */
12270 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
12271 UINT32_C(0xff000000)
12272 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
12274 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
12275 (UINT32_C(0x0) << 24)
12276 /* SFP/SFP+/SFP28 */
12277 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
12278 (UINT32_C(0x3) << 24)
12280 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
12281 (UINT32_C(0xc) << 24)
12283 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
12284 (UINT32_C(0xd) << 24)
12286 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
12287 (UINT32_C(0x11) << 24)
12288 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
12289 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
12291 * This value represents the current configuration of
12292 * Forward Error Correction (FEC) on the port.
12296 * When set to 1, then FEC is not supported on this port. If this flag
12297 * is set to 1, then all other FEC configuration flags shall be ignored.
12298 * When set to 0, then FEC is supported as indicated by other
12299 * configuration flags.
12300 * If no cable is attached and the HWRM does not yet know the FEC
12301 * capability, then the HWRM shall set this flag to 1 when reporting
12304 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
12307 * When set to 1, then FEC autonegotiation is supported on this port.
12308 * When set to 0, then FEC autonegotiation is not supported on this port.
12310 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
12313 * When set to 1, then FEC autonegotiation is enabled on this port.
12314 * When set to 0, then FEC autonegotiation is disabled if supported.
12315 * This flag should be ignored if FEC autonegotiation is not supported on this port.
12317 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
12320 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
12321 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
12323 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
12326 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
12327 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
12328 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
12330 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
12333 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
12334 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
12336 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
12339 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
12340 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
12341 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
12343 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
12346 * This value is indicates the duplex of the current
12347 * connection state.
12349 uint8_t duplex_state;
12350 /* Half Duplex connection. */
12351 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
12352 /* Full duplex connection. */
12353 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
12354 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
12355 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
12356 /* Option flags fields. */
12357 uint8_t option_flags;
12358 /* When this bit is '1', Media auto detect is enabled. */
12359 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
12362 * Up to 16 bytes of null padded ASCII string representing
12364 * If the string is set to null, then the vendor name is not
12367 char phy_vendor_name[16];
12369 * Up to 16 bytes of null padded ASCII string that
12370 * identifies vendor specific part number of the PHY.
12371 * If the string is set to null, then the vendor specific
12372 * part number is not available.
12374 char phy_vendor_partnumber[16];
12375 uint8_t unused_2[7];
12377 * This field is used in Output records to indicate that the output
12378 * is completely written to RAM. This field should be read as '1'
12379 * to indicate that the output has been completely written.
12380 * When writing a command completion or response to an internal processor,
12381 * the order of writes has to be such that this field is written last.
12384 } __attribute__((packed));
12386 /*********************
12387 * hwrm_port_mac_cfg *
12388 *********************/
12391 /* hwrm_port_mac_cfg_input (size:320b/40B) */
12392 struct hwrm_port_mac_cfg_input {
12393 /* The HWRM command request type. */
12396 * The completion ring to send the completion event on. This should
12397 * be the NQ ID returned from the `nq_alloc` HWRM command.
12399 uint16_t cmpl_ring;
12401 * The sequence ID is used by the driver for tracking multiple
12402 * commands. This ID is treated as opaque data by the firmware and
12403 * the value is returned in the `hwrm_resp_hdr` upon completion.
12407 * The target ID of the command:
12408 * * 0x0-0xFFF8 - The function ID
12409 * * 0xFFF8-0xFFFE - Reserved for internal processors
12412 uint16_t target_id;
12414 * A physical address pointer pointing to a host buffer that the
12415 * command's response data will be written. This can be either a host
12416 * physical address (HPA) or a guest physical address (GPA) and must
12417 * point to a physically contiguous block of memory.
12419 uint64_t resp_addr;
12421 * In this field, there are a number of CoS mappings related flags
12422 * that are used to configure CoS mappings and their corresponding
12423 * priorities in the hardware.
12424 * For the priorities of CoS mappings, the HWRM uses the following
12425 * priority order (high to low) by default:
12428 * # tunnel_vlan_pri
12431 * A subset of CoS mappings can be enabled.
12432 * If a priority is not specified for an enabled CoS mapping, the
12433 * priority will be assigned in the above order for the enabled CoS
12434 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
12435 * enabled and their priorities are not specified, the following
12436 * priority order (high to low) will be used by the HWRM:
12441 * vlan_pri CoS mapping together with default CoS with lower priority
12442 * are enabled by default by the HWRM.
12446 * When this bit is '1', this command will configure
12447 * the MAC to match the current link state of the PHY.
12448 * If the link is not established on the PHY, then this
12449 * bit has no effect.
12451 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
12454 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12455 * is requested to be enabled.
12457 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
12460 * When this bit is set to '1', tunnel VLAN PRI field to
12461 * CoS mapping is requested to be enabled.
12463 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
12466 * When this bit is set to '1', the IP DSCP to CoS mapping is
12467 * requested to be enabled.
12469 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
12472 * When this bit is '1', the HWRM is requested to
12473 * enable timestamp capture capability on the receive side
12476 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
12479 * When this bit is '1', the HWRM is requested to
12480 * disable timestamp capture capability on the receive side
12483 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
12486 * When this bit is '1', the HWRM is requested to
12487 * enable timestamp capture capability on the transmit side
12490 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
12493 * When this bit is '1', the HWRM is requested to
12494 * disable timestamp capture capability on the transmit side
12497 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
12500 * When this bit is '1', the Out-Of-Box WoL is requested to
12501 * be enabled on this port.
12503 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
12506 * When this bit is '1', the the Out-Of-Box WoL is requested to
12507 * be disabled on this port.
12509 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
12512 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12513 * is requested to be disabled.
12515 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
12518 * When this bit is set to '1', tunnel VLAN PRI field to
12519 * CoS mapping is requested to be disabled.
12521 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
12524 * When this bit is set to '1', the IP DSCP to CoS mapping is
12525 * requested to be disabled.
12527 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
12531 * This bit must be '1' for the ipg field to be
12534 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
12537 * This bit must be '1' for the lpbk field to be
12540 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
12543 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
12546 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
12549 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
12552 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
12555 * This bit must be '1' for the dscp2cos_map_pri field to be
12558 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
12561 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
12564 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
12567 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
12570 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
12573 * This bit must be '1' for the cos_field_cfg field to be
12576 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
12578 /* Port ID of port that is to be configured. */
12581 * This value is used to configure the minimum IPG that will
12582 * be sent between packets by this port.
12585 /* This value controls the loopback setting for the MAC. */
12587 /* No loopback is selected. Normal operation. */
12588 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
12590 * The HW will be configured with local loopback such that
12591 * host data is sent back to the host without modification.
12593 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
12595 * The HW will be configured with remote loopback such that
12596 * port logic will send packets back out the transmitter that
12599 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
12600 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
12601 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
12603 * This value controls the priority setting of VLAN PRI to CoS
12604 * mapping based on VLAN Tags of inner packet headers of
12605 * tunneled packets or packet headers of non-tunneled packets.
12607 * # Each XXX_pri variable shall have a unique priority value
12608 * when it is being specified.
12609 * # When comparing priorities of mappings, higher value
12610 * indicates higher priority.
12611 * For example, a value of 0-3 is returned where 0 is being
12612 * the lowest priority and 3 is being the highest priority.
12614 uint8_t vlan_pri2cos_map_pri;
12615 /* Reserved field. */
12618 * This value controls the priority setting of VLAN PRI to CoS
12619 * mapping based on VLAN Tags of tunneled header.
12620 * This mapping only applies when tunneled headers
12623 * # Each XXX_pri variable shall have a unique priority value
12624 * when it is being specified.
12625 * # When comparing priorities of mappings, higher value
12626 * indicates higher priority.
12627 * For example, a value of 0-3 is returned where 0 is being
12628 * the lowest priority and 3 is being the highest priority.
12630 uint8_t tunnel_pri2cos_map_pri;
12632 * This value controls the priority setting of IP DSCP to CoS
12633 * mapping based on inner IP header of tunneled packets or
12634 * IP header of non-tunneled packets.
12636 * # Each XXX_pri variable shall have a unique priority value
12637 * when it is being specified.
12638 * # When comparing priorities of mappings, higher value
12639 * indicates higher priority.
12640 * For example, a value of 0-3 is returned where 0 is being
12641 * the lowest priority and 3 is being the highest priority.
12643 uint8_t dscp2pri_map_pri;
12645 * This is a 16-bit bit mask that is used to request a
12646 * specific configuration of time stamp capture of PTP messages
12647 * on the receive side of this port.
12648 * This field shall be ignored if the ptp_rx_ts_capture_enable
12649 * flag is not set in this command.
12650 * Otherwise, if bit 'i' is set, then the HWRM is being
12651 * requested to configure the receive side of the port to
12652 * capture the time stamp of every received PTP message
12653 * with messageType field value set to i.
12655 uint16_t rx_ts_capture_ptp_msg_type;
12657 * This is a 16-bit bit mask that is used to request a
12658 * specific configuration of time stamp capture of PTP messages
12659 * on the transmit side of this port.
12660 * This field shall be ignored if the ptp_tx_ts_capture_enable
12661 * flag is not set in this command.
12662 * Otherwise, if bit 'i' is set, then the HWRM is being
12663 * requested to configure the transmit sied of the port to
12664 * capture the time stamp of every transmitted PTP message
12665 * with messageType field value set to i.
12667 uint16_t tx_ts_capture_ptp_msg_type;
12668 /* Configuration of CoS fields. */
12669 uint8_t cos_field_cfg;
12671 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
12674 * This field is used to specify selection of VLAN PRI value
12675 * based on whether one or two VLAN Tags are present in
12676 * the inner packet headers of tunneled packets or
12677 * non-tunneled packets.
12678 * This field is valid only if inner VLAN PRI to CoS mapping
12680 * If VLAN PRI to CoS mapping is not enabled, then this
12681 * field shall be ignored.
12683 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
12685 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
12688 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12689 * present in the inner packet headers
12691 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
12692 (UINT32_C(0x0) << 1)
12694 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12695 * present in the inner packet headers.
12696 * No VLAN PRI shall be selected for this configuration
12697 * if only one VLAN Tag is present in the inner
12700 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
12701 (UINT32_C(0x1) << 1)
12703 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12704 * are present in the inner packet headers
12706 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
12707 (UINT32_C(0x2) << 1)
12709 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
12710 (UINT32_C(0x3) << 1)
12711 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
12712 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
12714 * This field is used to specify selection of tunnel VLAN
12715 * PRI value based on whether one or two VLAN Tags are
12716 * present in tunnel headers.
12717 * This field is valid only if tunnel VLAN PRI to CoS mapping
12719 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
12720 * field shall be ignored.
12722 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
12724 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
12727 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12728 * present in the tunnel packet headers
12730 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
12731 (UINT32_C(0x0) << 3)
12733 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12734 * present in the tunnel packet headers.
12735 * No tunnel VLAN PRI shall be selected for this
12736 * configuration if only one VLAN Tag is present in
12737 * the tunnel packet headers.
12739 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
12740 (UINT32_C(0x1) << 3)
12742 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12743 * are present in the tunnel packet headers
12745 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
12746 (UINT32_C(0x2) << 3)
12748 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
12749 (UINT32_C(0x3) << 3)
12750 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
12751 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
12753 * This field shall be used to provide default CoS value
12754 * that has been configured on this port.
12755 * This field is valid only if default CoS mapping
12757 * If default CoS mapping is not enabled, then this
12758 * field shall be ignored.
12760 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
12762 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
12764 uint8_t unused_0[3];
12765 } __attribute__((packed));
12767 /* hwrm_port_mac_cfg_output (size:128b/16B) */
12768 struct hwrm_port_mac_cfg_output {
12769 /* The specific error status for the command. */
12770 uint16_t error_code;
12771 /* The HWRM command request type. */
12773 /* The sequence ID from the original command. */
12775 /* The length of the response data in number of bytes. */
12778 * This is the configured maximum length of Ethernet packet
12779 * payload that is allowed to be received on the port.
12780 * This value does not include the number of bytes used by
12781 * Ethernet header and trailer (CRC).
12785 * This is the configured maximum length of Ethernet packet
12786 * payload that is allowed to be transmitted on the port.
12787 * This value does not include the number of bytes used by
12788 * Ethernet header and trailer (CRC).
12791 /* Current configuration of the IPG value. */
12793 /* Current value of the loopback value. */
12795 /* No loopback is selected. Normal operation. */
12796 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
12798 * The HW will be configured with local loopback such that
12799 * host data is sent back to the host without modification.
12801 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
12803 * The HW will be configured with remote loopback such that
12804 * port logic will send packets back out the transmitter that
12807 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
12808 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
12809 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
12812 * This field is used in Output records to indicate that the output
12813 * is completely written to RAM. This field should be read as '1'
12814 * to indicate that the output has been completely written.
12815 * When writing a command completion or response to an internal processor,
12816 * the order of writes has to be such that this field is written last.
12819 } __attribute__((packed));
12821 /**********************
12822 * hwrm_port_mac_qcfg *
12823 **********************/
12826 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
12827 struct hwrm_port_mac_qcfg_input {
12828 /* The HWRM command request type. */
12831 * The completion ring to send the completion event on. This should
12832 * be the NQ ID returned from the `nq_alloc` HWRM command.
12834 uint16_t cmpl_ring;
12836 * The sequence ID is used by the driver for tracking multiple
12837 * commands. This ID is treated as opaque data by the firmware and
12838 * the value is returned in the `hwrm_resp_hdr` upon completion.
12842 * The target ID of the command:
12843 * * 0x0-0xFFF8 - The function ID
12844 * * 0xFFF8-0xFFFE - Reserved for internal processors
12847 uint16_t target_id;
12849 * A physical address pointer pointing to a host buffer that the
12850 * command's response data will be written. This can be either a host
12851 * physical address (HPA) or a guest physical address (GPA) and must
12852 * point to a physically contiguous block of memory.
12854 uint64_t resp_addr;
12855 /* Port ID of port that is to be configured. */
12857 uint8_t unused_0[6];
12858 } __attribute__((packed));
12860 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
12861 struct hwrm_port_mac_qcfg_output {
12862 /* The specific error status for the command. */
12863 uint16_t error_code;
12864 /* The HWRM command request type. */
12866 /* The sequence ID from the original command. */
12868 /* The length of the response data in number of bytes. */
12871 * This is the configured maximum length of Ethernet packet
12872 * payload that is allowed to be received on the port.
12873 * This value does not include the number of bytes used by the
12874 * Ethernet header and trailer (CRC).
12878 * This is the configured maximum length of Ethernet packet
12879 * payload that is allowed to be transmitted on the port.
12880 * This value does not include the number of bytes used by the
12881 * Ethernet header and trailer (CRC).
12885 * The minimum IPG that will
12886 * be sent between packets by this port.
12889 /* The loopback setting for the MAC. */
12891 /* No loopback is selected. Normal operation. */
12892 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
12894 * The HW will be configured with local loopback such that
12895 * host data is sent back to the host without modification.
12897 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
12899 * The HW will be configured with remote loopback such that
12900 * port logic will send packets back out the transmitter that
12903 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
12904 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
12905 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
12907 * Priority setting for VLAN PRI to CoS mapping.
12908 * # Each XXX_pri variable shall have a unique priority value
12909 * when it is being used.
12910 * # When comparing priorities of mappings, higher value
12911 * indicates higher priority.
12912 * For example, a value of 0-3 is returned where 0 is being
12913 * the lowest priority and 3 is being the highest priority.
12914 * # If the correspoding CoS mapping is not enabled, then this
12915 * field should be ignored.
12916 * # This value indicates the normalized priority value retained
12919 uint8_t vlan_pri2cos_map_pri;
12921 * In this field, a number of CoS mappings related flags
12922 * are used to indicate configured CoS mappings.
12926 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12929 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
12932 * When this bit is set to '1', tunnel VLAN PRI field to
12933 * CoS mapping is enabled.
12935 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
12938 * When this bit is set to '1', the IP DSCP to CoS mapping is
12941 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
12944 * When this bit is '1', the Out-Of-Box WoL is enabled on this
12947 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
12949 /* When this bit is '1', PTP is enabled for RX on this port. */
12950 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
12952 /* When this bit is '1', PTP is enabled for TX on this port. */
12953 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
12956 * Priority setting for tunnel VLAN PRI to CoS mapping.
12957 * # Each XXX_pri variable shall have a unique priority value
12958 * when it is being used.
12959 * # When comparing priorities of mappings, higher value
12960 * indicates higher priority.
12961 * For example, a value of 0-3 is returned where 0 is being
12962 * the lowest priority and 3 is being the highest priority.
12963 * # If the correspoding CoS mapping is not enabled, then this
12964 * field should be ignored.
12965 * # This value indicates the normalized priority value retained
12968 uint8_t tunnel_pri2cos_map_pri;
12970 * Priority setting for DSCP to PRI mapping.
12971 * # Each XXX_pri variable shall have a unique priority value
12972 * when it is being used.
12973 * # When comparing priorities of mappings, higher value
12974 * indicates higher priority.
12975 * For example, a value of 0-3 is returned where 0 is being
12976 * the lowest priority and 3 is being the highest priority.
12977 * # If the correspoding CoS mapping is not enabled, then this
12978 * field should be ignored.
12979 * # This value indicates the normalized priority value retained
12982 uint8_t dscp2pri_map_pri;
12984 * This is a 16-bit bit mask that represents the
12985 * current configuration of time stamp capture of PTP messages
12986 * on the receive side of this port.
12987 * If bit 'i' is set, then the receive side of the port
12988 * is configured to capture the time stamp of every
12989 * received PTP message with messageType field value set
12991 * If all bits are set to 0 (i.e. field value set 0),
12992 * then the receive side of the port is not configured
12993 * to capture timestamp for PTP messages.
12994 * If all bits are set to 1, then the receive side of the
12995 * port is configured to capture timestamp for all PTP
12998 uint16_t rx_ts_capture_ptp_msg_type;
13000 * This is a 16-bit bit mask that represents the
13001 * current configuration of time stamp capture of PTP messages
13002 * on the transmit side of this port.
13003 * If bit 'i' is set, then the transmit side of the port
13004 * is configured to capture the time stamp of every
13005 * received PTP message with messageType field value set
13007 * If all bits are set to 0 (i.e. field value set 0),
13008 * then the transmit side of the port is not configured
13009 * to capture timestamp for PTP messages.
13010 * If all bits are set to 1, then the transmit side of the
13011 * port is configured to capture timestamp for all PTP
13014 uint16_t tx_ts_capture_ptp_msg_type;
13015 /* Configuration of CoS fields. */
13016 uint8_t cos_field_cfg;
13018 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
13021 * This field is used for selecting VLAN PRI value
13022 * based on whether one or two VLAN Tags are present in
13023 * the inner packet headers of tunneled packets or
13024 * non-tunneled packets.
13026 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
13028 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
13031 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13032 * present in the inner packet headers
13034 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
13035 (UINT32_C(0x0) << 1)
13037 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13038 * present in the inner packet headers.
13039 * No VLAN PRI is selected for this configuration
13040 * if only one VLAN Tag is present in the inner
13043 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
13044 (UINT32_C(0x1) << 1)
13046 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13047 * are present in the inner packet headers
13049 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
13050 (UINT32_C(0x2) << 1)
13052 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
13053 (UINT32_C(0x3) << 1)
13054 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
13055 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
13057 * This field is used for selecting tunnel VLAN PRI value
13058 * based on whether one or two VLAN Tags are present in
13059 * the tunnel headers of tunneled packets. This selection
13060 * does not apply to non-tunneled packets.
13062 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
13064 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
13067 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13068 * present in the tunnel packet headers
13070 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
13071 (UINT32_C(0x0) << 3)
13073 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13074 * present in the tunnel packet headers.
13075 * No VLAN PRI is selected for this configuration
13076 * if only one VLAN Tag is present in the tunnel
13079 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
13080 (UINT32_C(0x1) << 3)
13082 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13083 * are present in the tunnel packet headers
13085 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
13086 (UINT32_C(0x2) << 3)
13088 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
13089 (UINT32_C(0x3) << 3)
13090 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
13091 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
13093 * This field is used to provide default CoS value that
13094 * has been configured on this port.
13096 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
13098 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
13101 * This field is used in Output records to indicate that the output
13102 * is completely written to RAM. This field should be read as '1'
13103 * to indicate that the output has been completely written.
13104 * When writing a command completion or response to an internal processor,
13105 * the order of writes has to be such that this field is written last.
13108 } __attribute__((packed));
13110 /**************************
13111 * hwrm_port_mac_ptp_qcfg *
13112 **************************/
13115 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
13116 struct hwrm_port_mac_ptp_qcfg_input {
13117 /* The HWRM command request type. */
13120 * The completion ring to send the completion event on. This should
13121 * be the NQ ID returned from the `nq_alloc` HWRM command.
13123 uint16_t cmpl_ring;
13125 * The sequence ID is used by the driver for tracking multiple
13126 * commands. This ID is treated as opaque data by the firmware and
13127 * the value is returned in the `hwrm_resp_hdr` upon completion.
13131 * The target ID of the command:
13132 * * 0x0-0xFFF8 - The function ID
13133 * * 0xFFF8-0xFFFE - Reserved for internal processors
13136 uint16_t target_id;
13138 * A physical address pointer pointing to a host buffer that the
13139 * command's response data will be written. This can be either a host
13140 * physical address (HPA) or a guest physical address (GPA) and must
13141 * point to a physically contiguous block of memory.
13143 uint64_t resp_addr;
13144 /* Port ID of port that is being queried. */
13146 uint8_t unused_0[6];
13147 } __attribute__((packed));
13149 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
13150 struct hwrm_port_mac_ptp_qcfg_output {
13151 /* The specific error status for the command. */
13152 uint16_t error_code;
13153 /* The HWRM command request type. */
13155 /* The sequence ID from the original command. */
13157 /* The length of the response data in number of bytes. */
13160 * In this field, a number of PTP related flags
13161 * are used to indicate configured PTP capabilities.
13165 * When this bit is set to '1', the PTP related registers are
13166 * directly accessible by the host.
13168 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
13171 * When this bit is set to '1', the PTP information is accessible
13172 * via HWRM commands.
13174 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
13176 uint8_t unused_0[3];
13177 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
13178 uint32_t rx_ts_reg_off_lower;
13179 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
13180 uint32_t rx_ts_reg_off_upper;
13181 /* Offset of the PTP register for the sequence ID for RX. */
13182 uint32_t rx_ts_reg_off_seq_id;
13183 /* Offset of the first PTP source ID for RX. */
13184 uint32_t rx_ts_reg_off_src_id_0;
13185 /* Offset of the second PTP source ID for RX. */
13186 uint32_t rx_ts_reg_off_src_id_1;
13187 /* Offset of the third PTP source ID for RX. */
13188 uint32_t rx_ts_reg_off_src_id_2;
13189 /* Offset of the domain ID for RX. */
13190 uint32_t rx_ts_reg_off_domain_id;
13191 /* Offset of the PTP FIFO register for RX. */
13192 uint32_t rx_ts_reg_off_fifo;
13193 /* Offset of the PTP advance FIFO register for RX. */
13194 uint32_t rx_ts_reg_off_fifo_adv;
13195 /* PTP timestamp granularity for RX. */
13196 uint32_t rx_ts_reg_off_granularity;
13197 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
13198 uint32_t tx_ts_reg_off_lower;
13199 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
13200 uint32_t tx_ts_reg_off_upper;
13201 /* Offset of the PTP register for the sequence ID for TX. */
13202 uint32_t tx_ts_reg_off_seq_id;
13203 /* Offset of the PTP FIFO register for TX. */
13204 uint32_t tx_ts_reg_off_fifo;
13205 /* PTP timestamp granularity for TX. */
13206 uint32_t tx_ts_reg_off_granularity;
13207 uint8_t unused_1[7];
13209 * This field is used in Output records to indicate that the output
13210 * is completely written to RAM. This field should be read as '1'
13211 * to indicate that the output has been completely written.
13212 * When writing a command completion or response to an internal processor,
13213 * the order of writes has to be such that this field is written last.
13216 } __attribute__((packed));
13218 /* Port Tx Statistics Formats */
13219 /* tx_port_stats (size:3264b/408B) */
13220 struct tx_port_stats {
13221 /* Total Number of 64 Bytes frames transmitted */
13222 uint64_t tx_64b_frames;
13223 /* Total Number of 65-127 Bytes frames transmitted */
13224 uint64_t tx_65b_127b_frames;
13225 /* Total Number of 128-255 Bytes frames transmitted */
13226 uint64_t tx_128b_255b_frames;
13227 /* Total Number of 256-511 Bytes frames transmitted */
13228 uint64_t tx_256b_511b_frames;
13229 /* Total Number of 512-1023 Bytes frames transmitted */
13230 uint64_t tx_512b_1023b_frames;
13231 /* Total Number of 1024-1518 Bytes frames transmitted */
13232 uint64_t tx_1024b_1518b_frames;
13234 * Total Number of each good VLAN (exludes FCS errors)
13235 * frame transmitted which is 1519 to 1522 bytes in length
13236 * inclusive (excluding framing bits but including FCS bytes).
13238 uint64_t tx_good_vlan_frames;
13239 /* Total Number of 1519-2047 Bytes frames transmitted */
13240 uint64_t tx_1519b_2047b_frames;
13241 /* Total Number of 2048-4095 Bytes frames transmitted */
13242 uint64_t tx_2048b_4095b_frames;
13243 /* Total Number of 4096-9216 Bytes frames transmitted */
13244 uint64_t tx_4096b_9216b_frames;
13245 /* Total Number of 9217-16383 Bytes frames transmitted */
13246 uint64_t tx_9217b_16383b_frames;
13247 /* Total Number of good frames transmitted */
13248 uint64_t tx_good_frames;
13249 /* Total Number of frames transmitted */
13250 uint64_t tx_total_frames;
13251 /* Total number of unicast frames transmitted */
13252 uint64_t tx_ucast_frames;
13253 /* Total number of multicast frames transmitted */
13254 uint64_t tx_mcast_frames;
13255 /* Total number of broadcast frames transmitted */
13256 uint64_t tx_bcast_frames;
13257 /* Total number of PAUSE control frames transmitted */
13258 uint64_t tx_pause_frames;
13260 * Total number of PFC/per-priority PAUSE
13261 * control frames transmitted
13263 uint64_t tx_pfc_frames;
13264 /* Total number of jabber frames transmitted */
13265 uint64_t tx_jabber_frames;
13266 /* Total number of frames transmitted with FCS error */
13267 uint64_t tx_fcs_err_frames;
13268 /* Total number of control frames transmitted */
13269 uint64_t tx_control_frames;
13270 /* Total number of over-sized frames transmitted */
13271 uint64_t tx_oversz_frames;
13272 /* Total number of frames with single deferral */
13273 uint64_t tx_single_dfrl_frames;
13274 /* Total number of frames with multiple deferrals */
13275 uint64_t tx_multi_dfrl_frames;
13276 /* Total number of frames with single collision */
13277 uint64_t tx_single_coll_frames;
13278 /* Total number of frames with multiple collisions */
13279 uint64_t tx_multi_coll_frames;
13280 /* Total number of frames with late collisions */
13281 uint64_t tx_late_coll_frames;
13282 /* Total number of frames with excessive collisions */
13283 uint64_t tx_excessive_coll_frames;
13284 /* Total number of fragmented frames transmitted */
13285 uint64_t tx_frag_frames;
13286 /* Total number of transmit errors */
13288 /* Total number of single VLAN tagged frames transmitted */
13289 uint64_t tx_tagged_frames;
13290 /* Total number of double VLAN tagged frames transmitted */
13291 uint64_t tx_dbl_tagged_frames;
13292 /* Total number of runt frames transmitted */
13293 uint64_t tx_runt_frames;
13294 /* Total number of TX FIFO under runs */
13295 uint64_t tx_fifo_underruns;
13297 * Total number of PFC frames with PFC enabled bit for
13298 * Pri 0 transmitted
13300 uint64_t tx_pfc_ena_frames_pri0;
13302 * Total number of PFC frames with PFC enabled bit for
13303 * Pri 1 transmitted
13305 uint64_t tx_pfc_ena_frames_pri1;
13307 * Total number of PFC frames with PFC enabled bit for
13308 * Pri 2 transmitted
13310 uint64_t tx_pfc_ena_frames_pri2;
13312 * Total number of PFC frames with PFC enabled bit for
13313 * Pri 3 transmitted
13315 uint64_t tx_pfc_ena_frames_pri3;
13317 * Total number of PFC frames with PFC enabled bit for
13318 * Pri 4 transmitted
13320 uint64_t tx_pfc_ena_frames_pri4;
13322 * Total number of PFC frames with PFC enabled bit for
13323 * Pri 5 transmitted
13325 uint64_t tx_pfc_ena_frames_pri5;
13327 * Total number of PFC frames with PFC enabled bit for
13328 * Pri 6 transmitted
13330 uint64_t tx_pfc_ena_frames_pri6;
13332 * Total number of PFC frames with PFC enabled bit for
13333 * Pri 7 transmitted
13335 uint64_t tx_pfc_ena_frames_pri7;
13336 /* Total number of EEE LPI Events on TX */
13337 uint64_t tx_eee_lpi_events;
13338 /* EEE LPI Duration Counter on TX */
13339 uint64_t tx_eee_lpi_duration;
13341 * Total number of Link Level Flow Control (LLFC) messages
13344 uint64_t tx_llfc_logical_msgs;
13345 /* Total number of HCFC messages transmitted */
13346 uint64_t tx_hcfc_msgs;
13347 /* Total number of TX collisions */
13348 uint64_t tx_total_collisions;
13349 /* Total number of transmitted bytes */
13351 /* Total number of end-to-end HOL frames */
13352 uint64_t tx_xthol_frames;
13353 /* Total Tx Drops per Port reported by STATS block */
13354 uint64_t tx_stat_discard;
13355 /* Total Tx Error Drops per Port reported by STATS block */
13356 uint64_t tx_stat_error;
13357 } __attribute__((packed));
13359 /* Port Rx Statistics Formats */
13360 /* rx_port_stats (size:4224b/528B) */
13361 struct rx_port_stats {
13362 /* Total Number of 64 Bytes frames received */
13363 uint64_t rx_64b_frames;
13364 /* Total Number of 65-127 Bytes frames received */
13365 uint64_t rx_65b_127b_frames;
13366 /* Total Number of 128-255 Bytes frames received */
13367 uint64_t rx_128b_255b_frames;
13368 /* Total Number of 256-511 Bytes frames received */
13369 uint64_t rx_256b_511b_frames;
13370 /* Total Number of 512-1023 Bytes frames received */
13371 uint64_t rx_512b_1023b_frames;
13372 /* Total Number of 1024-1518 Bytes frames received */
13373 uint64_t rx_1024b_1518b_frames;
13375 * Total Number of each good VLAN (exludes FCS errors)
13376 * frame received which is 1519 to 1522 bytes in length
13377 * inclusive (excluding framing bits but including FCS bytes).
13379 uint64_t rx_good_vlan_frames;
13380 /* Total Number of 1519-2047 Bytes frames received */
13381 uint64_t rx_1519b_2047b_frames;
13382 /* Total Number of 2048-4095 Bytes frames received */
13383 uint64_t rx_2048b_4095b_frames;
13384 /* Total Number of 4096-9216 Bytes frames received */
13385 uint64_t rx_4096b_9216b_frames;
13386 /* Total Number of 9217-16383 Bytes frames received */
13387 uint64_t rx_9217b_16383b_frames;
13388 /* Total number of frames received */
13389 uint64_t rx_total_frames;
13390 /* Total number of unicast frames received */
13391 uint64_t rx_ucast_frames;
13392 /* Total number of multicast frames received */
13393 uint64_t rx_mcast_frames;
13394 /* Total number of broadcast frames received */
13395 uint64_t rx_bcast_frames;
13396 /* Total number of received frames with FCS error */
13397 uint64_t rx_fcs_err_frames;
13398 /* Total number of control frames received */
13399 uint64_t rx_ctrl_frames;
13400 /* Total number of PAUSE frames received */
13401 uint64_t rx_pause_frames;
13402 /* Total number of PFC frames received */
13403 uint64_t rx_pfc_frames;
13405 * Total number of frames received with an unsupported
13408 uint64_t rx_unsupported_opcode_frames;
13410 * Total number of frames received with an unsupported
13411 * DA for pause and PFC
13413 uint64_t rx_unsupported_da_pausepfc_frames;
13414 /* Total number of frames received with an unsupported SA */
13415 uint64_t rx_wrong_sa_frames;
13416 /* Total number of received packets with alignment error */
13417 uint64_t rx_align_err_frames;
13418 /* Total number of received frames with out-of-range length */
13419 uint64_t rx_oor_len_frames;
13420 /* Total number of received frames with error termination */
13421 uint64_t rx_code_err_frames;
13423 * Total number of received frames with a false carrier is
13424 * detected during idle, as defined by RX_ER samples active
13425 * and RXD is 0xE. The event is reported along with the
13426 * statistics generated on the next received frame. Only
13427 * one false carrier condition can be detected and logged
13430 * Carrier event, valid for 10M/100M speed modes only.
13432 uint64_t rx_false_carrier_frames;
13433 /* Total number of over-sized frames received */
13434 uint64_t rx_ovrsz_frames;
13435 /* Total number of jabber packets received */
13436 uint64_t rx_jbr_frames;
13437 /* Total number of received frames with MTU error */
13438 uint64_t rx_mtu_err_frames;
13439 /* Total number of received frames with CRC match */
13440 uint64_t rx_match_crc_frames;
13441 /* Total number of frames received promiscuously */
13442 uint64_t rx_promiscuous_frames;
13444 * Total number of received frames with one or two VLAN
13447 uint64_t rx_tagged_frames;
13448 /* Total number of received frames with two VLAN tags */
13449 uint64_t rx_double_tagged_frames;
13450 /* Total number of truncated frames received */
13451 uint64_t rx_trunc_frames;
13452 /* Total number of good frames (without errors) received */
13453 uint64_t rx_good_frames;
13455 * Total number of received PFC frames with transition from
13456 * XON to XOFF on Pri 0
13458 uint64_t rx_pfc_xon2xoff_frames_pri0;
13460 * Total number of received PFC frames with transition from
13461 * XON to XOFF on Pri 1
13463 uint64_t rx_pfc_xon2xoff_frames_pri1;
13465 * Total number of received PFC frames with transition from
13466 * XON to XOFF on Pri 2
13468 uint64_t rx_pfc_xon2xoff_frames_pri2;
13470 * Total number of received PFC frames with transition from
13471 * XON to XOFF on Pri 3
13473 uint64_t rx_pfc_xon2xoff_frames_pri3;
13475 * Total number of received PFC frames with transition from
13476 * XON to XOFF on Pri 4
13478 uint64_t rx_pfc_xon2xoff_frames_pri4;
13480 * Total number of received PFC frames with transition from
13481 * XON to XOFF on Pri 5
13483 uint64_t rx_pfc_xon2xoff_frames_pri5;
13485 * Total number of received PFC frames with transition from
13486 * XON to XOFF on Pri 6
13488 uint64_t rx_pfc_xon2xoff_frames_pri6;
13490 * Total number of received PFC frames with transition from
13491 * XON to XOFF on Pri 7
13493 uint64_t rx_pfc_xon2xoff_frames_pri7;
13495 * Total number of received PFC frames with PFC enabled
13498 uint64_t rx_pfc_ena_frames_pri0;
13500 * Total number of received PFC frames with PFC enabled
13503 uint64_t rx_pfc_ena_frames_pri1;
13505 * Total number of received PFC frames with PFC enabled
13508 uint64_t rx_pfc_ena_frames_pri2;
13510 * Total number of received PFC frames with PFC enabled
13513 uint64_t rx_pfc_ena_frames_pri3;
13515 * Total number of received PFC frames with PFC enabled
13518 uint64_t rx_pfc_ena_frames_pri4;
13520 * Total number of received PFC frames with PFC enabled
13523 uint64_t rx_pfc_ena_frames_pri5;
13525 * Total number of received PFC frames with PFC enabled
13528 uint64_t rx_pfc_ena_frames_pri6;
13530 * Total number of received PFC frames with PFC enabled
13533 uint64_t rx_pfc_ena_frames_pri7;
13534 /* Total Number of frames received with SCH CRC error */
13535 uint64_t rx_sch_crc_err_frames;
13536 /* Total Number of under-sized frames received */
13537 uint64_t rx_undrsz_frames;
13538 /* Total Number of fragmented frames received */
13539 uint64_t rx_frag_frames;
13540 /* Total number of RX EEE LPI Events */
13541 uint64_t rx_eee_lpi_events;
13542 /* EEE LPI Duration Counter on RX */
13543 uint64_t rx_eee_lpi_duration;
13545 * Total number of physical type Link Level Flow Control
13546 * (LLFC) messages received
13548 uint64_t rx_llfc_physical_msgs;
13550 * Total number of logical type Link Level Flow Control
13551 * (LLFC) messages received
13553 uint64_t rx_llfc_logical_msgs;
13555 * Total number of logical type Link Level Flow Control
13556 * (LLFC) messages received with CRC error
13558 uint64_t rx_llfc_msgs_with_crc_err;
13559 /* Total number of HCFC messages received */
13560 uint64_t rx_hcfc_msgs;
13561 /* Total number of HCFC messages received with CRC error */
13562 uint64_t rx_hcfc_msgs_with_crc_err;
13563 /* Total number of received bytes */
13565 /* Total number of bytes received in runt frames */
13566 uint64_t rx_runt_bytes;
13567 /* Total number of runt frames received */
13568 uint64_t rx_runt_frames;
13569 /* Total Rx Discards per Port reported by STATS block */
13570 uint64_t rx_stat_discard;
13571 uint64_t rx_stat_err;
13572 } __attribute__((packed));
13574 /********************
13575 * hwrm_port_qstats *
13576 ********************/
13579 /* hwrm_port_qstats_input (size:320b/40B) */
13580 struct hwrm_port_qstats_input {
13581 /* The HWRM command request type. */
13584 * The completion ring to send the completion event on. This should
13585 * be the NQ ID returned from the `nq_alloc` HWRM command.
13587 uint16_t cmpl_ring;
13589 * The sequence ID is used by the driver for tracking multiple
13590 * commands. This ID is treated as opaque data by the firmware and
13591 * the value is returned in the `hwrm_resp_hdr` upon completion.
13595 * The target ID of the command:
13596 * * 0x0-0xFFF8 - The function ID
13597 * * 0xFFF8-0xFFFE - Reserved for internal processors
13600 uint16_t target_id;
13602 * A physical address pointer pointing to a host buffer that the
13603 * command's response data will be written. This can be either a host
13604 * physical address (HPA) or a guest physical address (GPA) and must
13605 * point to a physically contiguous block of memory.
13607 uint64_t resp_addr;
13608 /* Port ID of port that is being queried. */
13610 uint8_t unused_0[6];
13612 * This is the host address where
13613 * Tx port statistics will be stored
13615 uint64_t tx_stat_host_addr;
13617 * This is the host address where
13618 * Rx port statistics will be stored
13620 uint64_t rx_stat_host_addr;
13621 } __attribute__((packed));
13623 /* hwrm_port_qstats_output (size:128b/16B) */
13624 struct hwrm_port_qstats_output {
13625 /* The specific error status for the command. */
13626 uint16_t error_code;
13627 /* The HWRM command request type. */
13629 /* The sequence ID from the original command. */
13631 /* The length of the response data in number of bytes. */
13633 /* The size of TX port statistics block in bytes. */
13634 uint16_t tx_stat_size;
13635 /* The size of RX port statistics block in bytes. */
13636 uint16_t rx_stat_size;
13637 uint8_t unused_0[3];
13639 * This field is used in Output records to indicate that the output
13640 * is completely written to RAM. This field should be read as '1'
13641 * to indicate that the output has been completely written.
13642 * When writing a command completion or response to an internal processor,
13643 * the order of writes has to be such that this field is written last.
13646 } __attribute__((packed));
13648 /* Port Tx Statistics extended Formats */
13649 /* tx_port_stats_ext (size:2048b/256B) */
13650 struct tx_port_stats_ext {
13651 /* Total number of tx bytes count on cos queue 0 */
13652 uint64_t tx_bytes_cos0;
13653 /* Total number of tx bytes count on cos queue 1 */
13654 uint64_t tx_bytes_cos1;
13655 /* Total number of tx bytes count on cos queue 2 */
13656 uint64_t tx_bytes_cos2;
13657 /* Total number of tx bytes count on cos queue 3 */
13658 uint64_t tx_bytes_cos3;
13659 /* Total number of tx bytes count on cos queue 4 */
13660 uint64_t tx_bytes_cos4;
13661 /* Total number of tx bytes count on cos queue 5 */
13662 uint64_t tx_bytes_cos5;
13663 /* Total number of tx bytes count on cos queue 6 */
13664 uint64_t tx_bytes_cos6;
13665 /* Total number of tx bytes count on cos queue 7 */
13666 uint64_t tx_bytes_cos7;
13667 /* Total number of tx packets count on cos queue 0 */
13668 uint64_t tx_packets_cos0;
13669 /* Total number of tx packets count on cos queue 1 */
13670 uint64_t tx_packets_cos1;
13671 /* Total number of tx packets count on cos queue 2 */
13672 uint64_t tx_packets_cos2;
13673 /* Total number of tx packets count on cos queue 3 */
13674 uint64_t tx_packets_cos3;
13675 /* Total number of tx packets count on cos queue 4 */
13676 uint64_t tx_packets_cos4;
13677 /* Total number of tx packets count on cos queue 5 */
13678 uint64_t tx_packets_cos5;
13679 /* Total number of tx packets count on cos queue 6 */
13680 uint64_t tx_packets_cos6;
13681 /* Total number of tx packets count on cos queue 7 */
13682 uint64_t tx_packets_cos7;
13683 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
13684 uint64_t pfc_pri0_tx_duration_us;
13685 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
13686 uint64_t pfc_pri0_tx_transitions;
13687 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
13688 uint64_t pfc_pri1_tx_duration_us;
13689 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
13690 uint64_t pfc_pri1_tx_transitions;
13691 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
13692 uint64_t pfc_pri2_tx_duration_us;
13693 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
13694 uint64_t pfc_pri2_tx_transitions;
13695 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
13696 uint64_t pfc_pri3_tx_duration_us;
13697 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
13698 uint64_t pfc_pri3_tx_transitions;
13699 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
13700 uint64_t pfc_pri4_tx_duration_us;
13701 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
13702 uint64_t pfc_pri4_tx_transitions;
13703 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
13704 uint64_t pfc_pri5_tx_duration_us;
13705 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
13706 uint64_t pfc_pri5_tx_transitions;
13707 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
13708 uint64_t pfc_pri6_tx_duration_us;
13709 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
13710 uint64_t pfc_pri6_tx_transitions;
13711 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
13712 uint64_t pfc_pri7_tx_duration_us;
13713 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
13714 uint64_t pfc_pri7_tx_transitions;
13715 } __attribute__((packed));
13717 /* Port Rx Statistics extended Formats */
13718 /* rx_port_stats_ext (size:2368b/296B) */
13719 struct rx_port_stats_ext {
13720 /* Number of times link state changed to down */
13721 uint64_t link_down_events;
13722 /* Number of times the idle rings with pause bit are found */
13723 uint64_t continuous_pause_events;
13724 /* Number of times the active rings pause bit resumed back */
13725 uint64_t resume_pause_events;
13726 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
13727 uint64_t continuous_roce_pause_events;
13728 /* Number of times, the ROCE cos queue PFC is enabled back */
13729 uint64_t resume_roce_pause_events;
13730 /* Total number of rx bytes count on cos queue 0 */
13731 uint64_t rx_bytes_cos0;
13732 /* Total number of rx bytes count on cos queue 1 */
13733 uint64_t rx_bytes_cos1;
13734 /* Total number of rx bytes count on cos queue 2 */
13735 uint64_t rx_bytes_cos2;
13736 /* Total number of rx bytes count on cos queue 3 */
13737 uint64_t rx_bytes_cos3;
13738 /* Total number of rx bytes count on cos queue 4 */
13739 uint64_t rx_bytes_cos4;
13740 /* Total number of rx bytes count on cos queue 5 */
13741 uint64_t rx_bytes_cos5;
13742 /* Total number of rx bytes count on cos queue 6 */
13743 uint64_t rx_bytes_cos6;
13744 /* Total number of rx bytes count on cos queue 7 */
13745 uint64_t rx_bytes_cos7;
13746 /* Total number of rx packets count on cos queue 0 */
13747 uint64_t rx_packets_cos0;
13748 /* Total number of rx packets count on cos queue 1 */
13749 uint64_t rx_packets_cos1;
13750 /* Total number of rx packets count on cos queue 2 */
13751 uint64_t rx_packets_cos2;
13752 /* Total number of rx packets count on cos queue 3 */
13753 uint64_t rx_packets_cos3;
13754 /* Total number of rx packets count on cos queue 4 */
13755 uint64_t rx_packets_cos4;
13756 /* Total number of rx packets count on cos queue 5 */
13757 uint64_t rx_packets_cos5;
13758 /* Total number of rx packets count on cos queue 6 */
13759 uint64_t rx_packets_cos6;
13760 /* Total number of rx packets count on cos queue 7 */
13761 uint64_t rx_packets_cos7;
13762 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
13763 uint64_t pfc_pri0_rx_duration_us;
13764 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
13765 uint64_t pfc_pri0_rx_transitions;
13766 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
13767 uint64_t pfc_pri1_rx_duration_us;
13768 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
13769 uint64_t pfc_pri1_rx_transitions;
13770 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
13771 uint64_t pfc_pri2_rx_duration_us;
13772 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
13773 uint64_t pfc_pri2_rx_transitions;
13774 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
13775 uint64_t pfc_pri3_rx_duration_us;
13776 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
13777 uint64_t pfc_pri3_rx_transitions;
13778 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
13779 uint64_t pfc_pri4_rx_duration_us;
13780 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
13781 uint64_t pfc_pri4_rx_transitions;
13782 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
13783 uint64_t pfc_pri5_rx_duration_us;
13784 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
13785 uint64_t pfc_pri5_rx_transitions;
13786 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
13787 uint64_t pfc_pri6_rx_duration_us;
13788 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
13789 uint64_t pfc_pri6_rx_transitions;
13790 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
13791 uint64_t pfc_pri7_rx_duration_us;
13792 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
13793 uint64_t pfc_pri7_rx_transitions;
13794 } __attribute__((packed));
13796 /************************
13797 * hwrm_port_qstats_ext *
13798 ************************/
13801 /* hwrm_port_qstats_ext_input (size:320b/40B) */
13802 struct hwrm_port_qstats_ext_input {
13803 /* The HWRM command request type. */
13806 * The completion ring to send the completion event on. This should
13807 * be the NQ ID returned from the `nq_alloc` HWRM command.
13809 uint16_t cmpl_ring;
13811 * The sequence ID is used by the driver for tracking multiple
13812 * commands. This ID is treated as opaque data by the firmware and
13813 * the value is returned in the `hwrm_resp_hdr` upon completion.
13817 * The target ID of the command:
13818 * * 0x0-0xFFF8 - The function ID
13819 * * 0xFFF8-0xFFFE - Reserved for internal processors
13822 uint16_t target_id;
13824 * A physical address pointer pointing to a host buffer that the
13825 * command's response data will be written. This can be either a host
13826 * physical address (HPA) or a guest physical address (GPA) and must
13827 * point to a physically contiguous block of memory.
13829 uint64_t resp_addr;
13830 /* Port ID of port that is being queried. */
13833 * The size of TX port extended
13834 * statistics block in bytes.
13836 uint16_t tx_stat_size;
13838 * The size of RX port extended
13839 * statistics block in bytes
13841 uint16_t rx_stat_size;
13842 uint8_t unused_0[2];
13844 * This is the host address where
13845 * Tx port statistics will be stored
13847 uint64_t tx_stat_host_addr;
13849 * This is the host address where
13850 * Rx port statistics will be stored
13852 uint64_t rx_stat_host_addr;
13853 } __attribute__((packed));
13855 /* hwrm_port_qstats_ext_output (size:128b/16B) */
13856 struct hwrm_port_qstats_ext_output {
13857 /* The specific error status for the command. */
13858 uint16_t error_code;
13859 /* The HWRM command request type. */
13861 /* The sequence ID from the original command. */
13863 /* The length of the response data in number of bytes. */
13865 /* The size of TX port statistics block in bytes. */
13866 uint16_t tx_stat_size;
13867 /* The size of RX port statistics block in bytes. */
13868 uint16_t rx_stat_size;
13869 /* Total number of active cos queues available. */
13870 uint16_t total_active_cos_queues;
13873 * If set to 1, then this field indicates that clear
13874 * roce specific counters is supported.
13876 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
13879 * This field is used in Output records to indicate that the output
13880 * is completely written to RAM. This field should be read as '1'
13881 * to indicate that the output has been completely written.
13882 * When writing a command completion or response to an internal processor,
13883 * the order of writes has to be such that this field is written last.
13886 } __attribute__((packed));
13888 /*************************
13889 * hwrm_port_lpbk_qstats *
13890 *************************/
13893 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
13894 struct hwrm_port_lpbk_qstats_input {
13895 /* The HWRM command request type. */
13898 * The completion ring to send the completion event on. This should
13899 * be the NQ ID returned from the `nq_alloc` HWRM command.
13901 uint16_t cmpl_ring;
13903 * The sequence ID is used by the driver for tracking multiple
13904 * commands. This ID is treated as opaque data by the firmware and
13905 * the value is returned in the `hwrm_resp_hdr` upon completion.
13909 * The target ID of the command:
13910 * * 0x0-0xFFF8 - The function ID
13911 * * 0xFFF8-0xFFFE - Reserved for internal processors
13914 uint16_t target_id;
13916 * A physical address pointer pointing to a host buffer that the
13917 * command's response data will be written. This can be either a host
13918 * physical address (HPA) or a guest physical address (GPA) and must
13919 * point to a physically contiguous block of memory.
13921 uint64_t resp_addr;
13922 } __attribute__((packed));
13924 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
13925 struct hwrm_port_lpbk_qstats_output {
13926 /* The specific error status for the command. */
13927 uint16_t error_code;
13928 /* The HWRM command request type. */
13930 /* The sequence ID from the original command. */
13932 /* The length of the response data in number of bytes. */
13934 /* Number of transmitted unicast frames */
13935 uint64_t lpbk_ucast_frames;
13936 /* Number of transmitted multicast frames */
13937 uint64_t lpbk_mcast_frames;
13938 /* Number of transmitted broadcast frames */
13939 uint64_t lpbk_bcast_frames;
13940 /* Number of transmitted bytes for unicast traffic */
13941 uint64_t lpbk_ucast_bytes;
13942 /* Number of transmitted bytes for multicast traffic */
13943 uint64_t lpbk_mcast_bytes;
13944 /* Number of transmitted bytes for broadcast traffic */
13945 uint64_t lpbk_bcast_bytes;
13946 /* Total Tx Drops for loopback traffic reported by STATS block */
13947 uint64_t tx_stat_discard;
13948 /* Total Tx Error Drops for loopback traffic reported by STATS block */
13949 uint64_t tx_stat_error;
13950 /* Total Rx Drops for loopback traffic reported by STATS block */
13951 uint64_t rx_stat_discard;
13952 /* Total Rx Error Drops for loopback traffic reported by STATS block */
13953 uint64_t rx_stat_error;
13954 uint8_t unused_0[7];
13956 * This field is used in Output records to indicate that the output
13957 * is completely written to RAM. This field should be read as '1'
13958 * to indicate that the output has been completely written.
13959 * When writing a command completion or response to an internal processor,
13960 * the order of writes has to be such that this field is written last.
13963 } __attribute__((packed));
13965 /***********************
13966 * hwrm_port_clr_stats *
13967 ***********************/
13970 /* hwrm_port_clr_stats_input (size:192b/24B) */
13971 struct hwrm_port_clr_stats_input {
13972 /* The HWRM command request type. */
13975 * The completion ring to send the completion event on. This should
13976 * be the NQ ID returned from the `nq_alloc` HWRM command.
13978 uint16_t cmpl_ring;
13980 * The sequence ID is used by the driver for tracking multiple
13981 * commands. This ID is treated as opaque data by the firmware and
13982 * the value is returned in the `hwrm_resp_hdr` upon completion.
13986 * The target ID of the command:
13987 * * 0x0-0xFFF8 - The function ID
13988 * * 0xFFF8-0xFFFE - Reserved for internal processors
13991 uint16_t target_id;
13993 * A physical address pointer pointing to a host buffer that the
13994 * command's response data will be written. This can be either a host
13995 * physical address (HPA) or a guest physical address (GPA) and must
13996 * point to a physically contiguous block of memory.
13998 uint64_t resp_addr;
13999 /* Port ID of port that is being queried. */
14003 * If set to 1, then this field indicates clear the following RoCE
14004 * specific counters.
14005 * RoCE associated TX/RX cos counters
14006 * CNP associated TX/RX cos counters
14007 * RoCE/CNP specific TX/RX flow counters
14008 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
14009 * This flag is honored only when RoCE is enabled on that port.
14011 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
14012 uint8_t unused_0[5];
14013 } __attribute__((packed));
14015 /* hwrm_port_clr_stats_output (size:128b/16B) */
14016 struct hwrm_port_clr_stats_output {
14017 /* The specific error status for the command. */
14018 uint16_t error_code;
14019 /* The HWRM command request type. */
14021 /* The sequence ID from the original command. */
14023 /* The length of the response data in number of bytes. */
14025 uint8_t unused_0[7];
14027 * This field is used in Output records to indicate that the output
14028 * is completely written to RAM. This field should be read as '1'
14029 * to indicate that the output has been completely written.
14030 * When writing a command completion or response to an internal processor,
14031 * the order of writes has to be such that this field is written last.
14034 } __attribute__((packed));
14036 /***********************
14037 * hwrm_port_phy_qcaps *
14038 ***********************/
14041 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
14042 struct hwrm_port_phy_qcaps_input {
14043 /* The HWRM command request type. */
14046 * The completion ring to send the completion event on. This should
14047 * be the NQ ID returned from the `nq_alloc` HWRM command.
14049 uint16_t cmpl_ring;
14051 * The sequence ID is used by the driver for tracking multiple
14052 * commands. This ID is treated as opaque data by the firmware and
14053 * the value is returned in the `hwrm_resp_hdr` upon completion.
14057 * The target ID of the command:
14058 * * 0x0-0xFFF8 - The function ID
14059 * * 0xFFF8-0xFFFE - Reserved for internal processors
14062 uint16_t target_id;
14064 * A physical address pointer pointing to a host buffer that the
14065 * command's response data will be written. This can be either a host
14066 * physical address (HPA) or a guest physical address (GPA) and must
14067 * point to a physically contiguous block of memory.
14069 uint64_t resp_addr;
14070 /* Port ID of port that is being queried. */
14072 uint8_t unused_0[6];
14073 } __attribute__((packed));
14075 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
14076 struct hwrm_port_phy_qcaps_output {
14077 /* The specific error status for the command. */
14078 uint16_t error_code;
14079 /* The HWRM command request type. */
14081 /* The sequence ID from the original command. */
14083 /* The length of the response data in number of bytes. */
14085 /* PHY capability flags */
14088 * If set to 1, then this field indicates that the
14089 * link is capable of supporting EEE.
14091 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
14094 * If set to 1, then this field indicates that the
14095 * PHY is capable of supporting external loopback.
14097 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
14100 * Reserved field. The HWRM shall set this field to 0.
14101 * An HWRM client shall ignore this field.
14103 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
14105 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
14106 /* Number of front panel ports for this device. */
14108 /* Not supported or unknown */
14109 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
14110 /* single port device */
14111 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
14112 /* 2-port device */
14113 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
14114 /* 3-port device */
14115 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
14116 /* 4-port device */
14117 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
14118 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
14119 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
14121 * This is a bit mask to indicate what speeds are supported
14122 * as forced speeds on this link.
14123 * For each speed that can be forced on this link, the
14124 * corresponding mask bit shall be set to '1'.
14126 uint16_t supported_speeds_force_mode;
14127 /* 100Mb link speed (Half-duplex) */
14128 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
14130 /* 100Mb link speed (Full-duplex) */
14131 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
14133 /* 1Gb link speed (Half-duplex) */
14134 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
14136 /* 1Gb link speed (Full-duplex) */
14137 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
14139 /* 2Gb link speed */
14140 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
14142 /* 25Gb link speed */
14143 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
14145 /* 10Gb link speed */
14146 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
14148 /* 20Gb link speed */
14149 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
14151 /* 25Gb link speed */
14152 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
14154 /* 40Gb link speed */
14155 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
14157 /* 50Gb link speed */
14158 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
14160 /* 100Gb link speed */
14161 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
14163 /* 10Mb link speed (Half-duplex) */
14164 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
14166 /* 10Mb link speed (Full-duplex) */
14167 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
14170 * This is a bit mask to indicate what speeds are supported
14171 * for autonegotiation on this link.
14172 * For each speed that can be autonegotiated on this link, the
14173 * corresponding mask bit shall be set to '1'.
14175 uint16_t supported_speeds_auto_mode;
14176 /* 100Mb link speed (Half-duplex) */
14177 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
14179 /* 100Mb link speed (Full-duplex) */
14180 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
14182 /* 1Gb link speed (Half-duplex) */
14183 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
14185 /* 1Gb link speed (Full-duplex) */
14186 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
14188 /* 2Gb link speed */
14189 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
14191 /* 25Gb link speed */
14192 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
14194 /* 10Gb link speed */
14195 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
14197 /* 20Gb link speed */
14198 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
14200 /* 25Gb link speed */
14201 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
14203 /* 40Gb link speed */
14204 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
14206 /* 50Gb link speed */
14207 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
14209 /* 100Gb link speed */
14210 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
14212 /* 10Mb link speed (Half-duplex) */
14213 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
14215 /* 10Mb link speed (Full-duplex) */
14216 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
14219 * This is a bit mask to indicate what speeds are supported
14220 * for EEE on this link.
14221 * For each speed that can be autonegotiated when EEE is enabled
14222 * on this link, the corresponding mask bit shall be set to '1'.
14223 * This field is only valid when the eee_suppotred is set to '1'.
14225 uint16_t supported_speeds_eee_mode;
14227 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
14229 /* 100Mb link speed (Full-duplex) */
14230 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
14233 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
14235 /* 1Gb link speed (Full-duplex) */
14236 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
14239 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
14242 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
14244 /* 10Gb link speed */
14245 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
14247 uint32_t tx_lpi_timer_low;
14249 * The lowest value of TX LPI timer that can be set on this link
14250 * when EEE is enabled. This value is in microseconds.
14251 * This field is valid only when_eee_supported is set to '1'.
14253 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
14255 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
14257 * Reserved field. The HWRM shall set this field to 0.
14258 * An HWRM client shall ignore this field.
14260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
14261 UINT32_C(0xff000000)
14262 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
14263 uint32_t valid_tx_lpi_timer_high;
14265 * The highest value of TX LPI timer that can be set on this link
14266 * when EEE is enabled. This value is in microseconds.
14267 * This field is valid only when_eee_supported is set to '1'.
14269 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
14271 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
14273 * This field is used in Output records to indicate that the output
14274 * is completely written to RAM. This field should be read as '1'
14275 * to indicate that the output has been completely written.
14276 * When writing a command completion or response to an internal processor,
14277 * the order of writes has to be such that this field is written last.
14279 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
14280 UINT32_C(0xff000000)
14281 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
14282 } __attribute__((packed));
14284 /*********************
14285 * hwrm_port_led_cfg *
14286 *********************/
14289 /* hwrm_port_led_cfg_input (size:512b/64B) */
14290 struct hwrm_port_led_cfg_input {
14291 /* The HWRM command request type. */
14294 * The completion ring to send the completion event on. This should
14295 * be the NQ ID returned from the `nq_alloc` HWRM command.
14297 uint16_t cmpl_ring;
14299 * The sequence ID is used by the driver for tracking multiple
14300 * commands. This ID is treated as opaque data by the firmware and
14301 * the value is returned in the `hwrm_resp_hdr` upon completion.
14305 * The target ID of the command:
14306 * * 0x0-0xFFF8 - The function ID
14307 * * 0xFFF8-0xFFFE - Reserved for internal processors
14310 uint16_t target_id;
14312 * A physical address pointer pointing to a host buffer that the
14313 * command's response data will be written. This can be either a host
14314 * physical address (HPA) or a guest physical address (GPA) and must
14315 * point to a physically contiguous block of memory.
14317 uint64_t resp_addr;
14320 * This bit must be '1' for the led0_id field to be
14323 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
14326 * This bit must be '1' for the led0_state field to be
14329 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
14332 * This bit must be '1' for the led0_color field to be
14335 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
14338 * This bit must be '1' for the led0_blink_on field to be
14341 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
14344 * This bit must be '1' for the led0_blink_off field to be
14347 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
14350 * This bit must be '1' for the led0_group_id field to be
14353 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
14356 * This bit must be '1' for the led1_id field to be
14359 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
14362 * This bit must be '1' for the led1_state field to be
14365 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
14368 * This bit must be '1' for the led1_color field to be
14371 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
14374 * This bit must be '1' for the led1_blink_on field to be
14377 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
14380 * This bit must be '1' for the led1_blink_off field to be
14383 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
14386 * This bit must be '1' for the led1_group_id field to be
14389 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
14392 * This bit must be '1' for the led2_id field to be
14395 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
14398 * This bit must be '1' for the led2_state field to be
14401 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
14404 * This bit must be '1' for the led2_color field to be
14407 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
14410 * This bit must be '1' for the led2_blink_on field to be
14413 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
14416 * This bit must be '1' for the led2_blink_off field to be
14419 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
14422 * This bit must be '1' for the led2_group_id field to be
14425 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
14428 * This bit must be '1' for the led3_id field to be
14431 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
14434 * This bit must be '1' for the led3_state field to be
14437 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
14440 * This bit must be '1' for the led3_color field to be
14443 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
14446 * This bit must be '1' for the led3_blink_on field to be
14449 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
14452 * This bit must be '1' for the led3_blink_off field to be
14455 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
14458 * This bit must be '1' for the led3_group_id field to be
14461 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
14463 /* Port ID of port whose LEDs are configured. */
14466 * The number of LEDs that are being configured.
14467 * Up to 4 LEDs can be configured with this command.
14470 /* Reserved field. */
14472 /* An identifier for the LED #0. */
14474 /* The requested state of the LED #0. */
14475 uint8_t led0_state;
14476 /* Default state of the LED */
14477 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
14479 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
14481 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
14483 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
14484 /* Blink Alternately */
14485 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
14486 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
14487 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
14488 /* The requested color of LED #0. */
14489 uint8_t led0_color;
14491 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
14493 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
14495 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
14496 /* Green or Amber */
14497 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
14498 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
14499 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
14502 * If the LED #0 state is "blink" or "blinkalt", then
14503 * this field represents the requested time in milliseconds
14504 * to keep LED on between cycles.
14506 uint16_t led0_blink_on;
14508 * If the LED #0 state is "blink" or "blinkalt", then
14509 * this field represents the requested time in milliseconds
14510 * to keep LED off between cycles.
14512 uint16_t led0_blink_off;
14514 * An identifier for the group of LEDs that LED #0 belongs
14516 * If set to 0, then the LED #0 shall not be grouped and
14517 * shall be treated as an individual resource.
14518 * For all other non-zero values of this field, LED #0 shall
14519 * be grouped together with the LEDs with the same group ID
14522 uint8_t led0_group_id;
14523 /* Reserved field. */
14525 /* An identifier for the LED #1. */
14527 /* The requested state of the LED #1. */
14528 uint8_t led1_state;
14529 /* Default state of the LED */
14530 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
14532 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
14534 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
14536 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
14537 /* Blink Alternately */
14538 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
14539 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
14540 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
14541 /* The requested color of LED #1. */
14542 uint8_t led1_color;
14544 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
14546 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
14548 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
14549 /* Green or Amber */
14550 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
14551 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
14552 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
14555 * If the LED #1 state is "blink" or "blinkalt", then
14556 * this field represents the requested time in milliseconds
14557 * to keep LED on between cycles.
14559 uint16_t led1_blink_on;
14561 * If the LED #1 state is "blink" or "blinkalt", then
14562 * this field represents the requested time in milliseconds
14563 * to keep LED off between cycles.
14565 uint16_t led1_blink_off;
14567 * An identifier for the group of LEDs that LED #1 belongs
14569 * If set to 0, then the LED #1 shall not be grouped and
14570 * shall be treated as an individual resource.
14571 * For all other non-zero values of this field, LED #1 shall
14572 * be grouped together with the LEDs with the same group ID
14575 uint8_t led1_group_id;
14576 /* Reserved field. */
14578 /* An identifier for the LED #2. */
14580 /* The requested state of the LED #2. */
14581 uint8_t led2_state;
14582 /* Default state of the LED */
14583 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
14585 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
14587 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
14589 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
14590 /* Blink Alternately */
14591 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
14592 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
14593 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
14594 /* The requested color of LED #2. */
14595 uint8_t led2_color;
14597 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
14599 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
14601 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
14602 /* Green or Amber */
14603 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
14604 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
14605 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
14608 * If the LED #2 state is "blink" or "blinkalt", then
14609 * this field represents the requested time in milliseconds
14610 * to keep LED on between cycles.
14612 uint16_t led2_blink_on;
14614 * If the LED #2 state is "blink" or "blinkalt", then
14615 * this field represents the requested time in milliseconds
14616 * to keep LED off between cycles.
14618 uint16_t led2_blink_off;
14620 * An identifier for the group of LEDs that LED #2 belongs
14622 * If set to 0, then the LED #2 shall not be grouped and
14623 * shall be treated as an individual resource.
14624 * For all other non-zero values of this field, LED #2 shall
14625 * be grouped together with the LEDs with the same group ID
14628 uint8_t led2_group_id;
14629 /* Reserved field. */
14631 /* An identifier for the LED #3. */
14633 /* The requested state of the LED #3. */
14634 uint8_t led3_state;
14635 /* Default state of the LED */
14636 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
14638 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
14640 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
14642 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
14643 /* Blink Alternately */
14644 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
14645 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
14646 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
14647 /* The requested color of LED #3. */
14648 uint8_t led3_color;
14650 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
14652 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
14654 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
14655 /* Green or Amber */
14656 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
14657 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
14658 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
14661 * If the LED #3 state is "blink" or "blinkalt", then
14662 * this field represents the requested time in milliseconds
14663 * to keep LED on between cycles.
14665 uint16_t led3_blink_on;
14667 * If the LED #3 state is "blink" or "blinkalt", then
14668 * this field represents the requested time in milliseconds
14669 * to keep LED off between cycles.
14671 uint16_t led3_blink_off;
14673 * An identifier for the group of LEDs that LED #3 belongs
14675 * If set to 0, then the LED #3 shall not be grouped and
14676 * shall be treated as an individual resource.
14677 * For all other non-zero values of this field, LED #3 shall
14678 * be grouped together with the LEDs with the same group ID
14681 uint8_t led3_group_id;
14682 /* Reserved field. */
14684 } __attribute__((packed));
14686 /* hwrm_port_led_cfg_output (size:128b/16B) */
14687 struct hwrm_port_led_cfg_output {
14688 /* The specific error status for the command. */
14689 uint16_t error_code;
14690 /* The HWRM command request type. */
14692 /* The sequence ID from the original command. */
14694 /* The length of the response data in number of bytes. */
14696 uint8_t unused_0[7];
14698 * This field is used in Output records to indicate that the output
14699 * is completely written to RAM. This field should be read as '1'
14700 * to indicate that the output has been completely written.
14701 * When writing a command completion or response to an internal processor,
14702 * the order of writes has to be such that this field is written last.
14705 } __attribute__((packed));
14707 /**********************
14708 * hwrm_port_led_qcfg *
14709 **********************/
14712 /* hwrm_port_led_qcfg_input (size:192b/24B) */
14713 struct hwrm_port_led_qcfg_input {
14714 /* The HWRM command request type. */
14717 * The completion ring to send the completion event on. This should
14718 * be the NQ ID returned from the `nq_alloc` HWRM command.
14720 uint16_t cmpl_ring;
14722 * The sequence ID is used by the driver for tracking multiple
14723 * commands. This ID is treated as opaque data by the firmware and
14724 * the value is returned in the `hwrm_resp_hdr` upon completion.
14728 * The target ID of the command:
14729 * * 0x0-0xFFF8 - The function ID
14730 * * 0xFFF8-0xFFFE - Reserved for internal processors
14733 uint16_t target_id;
14735 * A physical address pointer pointing to a host buffer that the
14736 * command's response data will be written. This can be either a host
14737 * physical address (HPA) or a guest physical address (GPA) and must
14738 * point to a physically contiguous block of memory.
14740 uint64_t resp_addr;
14741 /* Port ID of port whose LED configuration is being queried. */
14743 uint8_t unused_0[6];
14744 } __attribute__((packed));
14746 /* hwrm_port_led_qcfg_output (size:448b/56B) */
14747 struct hwrm_port_led_qcfg_output {
14748 /* The specific error status for the command. */
14749 uint16_t error_code;
14750 /* The HWRM command request type. */
14752 /* The sequence ID from the original command. */
14754 /* The length of the response data in number of bytes. */
14757 * The number of LEDs that are configured on this port.
14758 * Up to 4 LEDs can be returned in the response.
14761 /* An identifier for the LED #0. */
14763 /* The type of LED #0. */
14766 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
14768 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
14770 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
14771 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
14772 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
14773 /* The current state of the LED #0. */
14774 uint8_t led0_state;
14775 /* Default state of the LED */
14776 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
14778 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
14780 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
14782 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
14783 /* Blink Alternately */
14784 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
14785 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
14786 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
14787 /* The color of LED #0. */
14788 uint8_t led0_color;
14790 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
14792 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
14794 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
14795 /* Green or Amber */
14796 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
14797 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
14798 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
14801 * If the LED #0 state is "blink" or "blinkalt", then
14802 * this field represents the requested time in milliseconds
14803 * to keep LED on between cycles.
14805 uint16_t led0_blink_on;
14807 * If the LED #0 state is "blink" or "blinkalt", then
14808 * this field represents the requested time in milliseconds
14809 * to keep LED off between cycles.
14811 uint16_t led0_blink_off;
14813 * An identifier for the group of LEDs that LED #0 belongs
14815 * If set to 0, then the LED #0 is not grouped.
14816 * For all other non-zero values of this field, LED #0 is
14817 * grouped together with the LEDs with the same group ID
14820 uint8_t led0_group_id;
14821 /* An identifier for the LED #1. */
14823 /* The type of LED #1. */
14826 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
14828 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
14830 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
14831 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
14832 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
14833 /* The current state of the LED #1. */
14834 uint8_t led1_state;
14835 /* Default state of the LED */
14836 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
14838 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
14840 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
14842 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
14843 /* Blink Alternately */
14844 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
14845 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
14846 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
14847 /* The color of LED #1. */
14848 uint8_t led1_color;
14850 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
14852 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
14854 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
14855 /* Green or Amber */
14856 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
14857 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
14858 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
14861 * If the LED #1 state is "blink" or "blinkalt", then
14862 * this field represents the requested time in milliseconds
14863 * to keep LED on between cycles.
14865 uint16_t led1_blink_on;
14867 * If the LED #1 state is "blink" or "blinkalt", then
14868 * this field represents the requested time in milliseconds
14869 * to keep LED off between cycles.
14871 uint16_t led1_blink_off;
14873 * An identifier for the group of LEDs that LED #1 belongs
14875 * If set to 0, then the LED #1 is not grouped.
14876 * For all other non-zero values of this field, LED #1 is
14877 * grouped together with the LEDs with the same group ID
14880 uint8_t led1_group_id;
14881 /* An identifier for the LED #2. */
14883 /* The type of LED #2. */
14886 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
14888 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
14890 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
14891 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
14892 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
14893 /* The current state of the LED #2. */
14894 uint8_t led2_state;
14895 /* Default state of the LED */
14896 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
14898 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
14900 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
14902 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
14903 /* Blink Alternately */
14904 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
14905 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
14906 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
14907 /* The color of LED #2. */
14908 uint8_t led2_color;
14910 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
14912 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
14914 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
14915 /* Green or Amber */
14916 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
14917 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
14918 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
14921 * If the LED #2 state is "blink" or "blinkalt", then
14922 * this field represents the requested time in milliseconds
14923 * to keep LED on between cycles.
14925 uint16_t led2_blink_on;
14927 * If the LED #2 state is "blink" or "blinkalt", then
14928 * this field represents the requested time in milliseconds
14929 * to keep LED off between cycles.
14931 uint16_t led2_blink_off;
14933 * An identifier for the group of LEDs that LED #2 belongs
14935 * If set to 0, then the LED #2 is not grouped.
14936 * For all other non-zero values of this field, LED #2 is
14937 * grouped together with the LEDs with the same group ID
14940 uint8_t led2_group_id;
14941 /* An identifier for the LED #3. */
14943 /* The type of LED #3. */
14946 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
14948 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
14950 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
14951 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
14952 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
14953 /* The current state of the LED #3. */
14954 uint8_t led3_state;
14955 /* Default state of the LED */
14956 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
14958 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
14960 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
14962 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
14963 /* Blink Alternately */
14964 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
14965 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
14966 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
14967 /* The color of LED #3. */
14968 uint8_t led3_color;
14970 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
14972 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
14974 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
14975 /* Green or Amber */
14976 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
14977 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
14978 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
14981 * If the LED #3 state is "blink" or "blinkalt", then
14982 * this field represents the requested time in milliseconds
14983 * to keep LED on between cycles.
14985 uint16_t led3_blink_on;
14987 * If the LED #3 state is "blink" or "blinkalt", then
14988 * this field represents the requested time in milliseconds
14989 * to keep LED off between cycles.
14991 uint16_t led3_blink_off;
14993 * An identifier for the group of LEDs that LED #3 belongs
14995 * If set to 0, then the LED #3 is not grouped.
14996 * For all other non-zero values of this field, LED #3 is
14997 * grouped together with the LEDs with the same group ID
15000 uint8_t led3_group_id;
15001 uint8_t unused_4[6];
15003 * This field is used in Output records to indicate that the output
15004 * is completely written to RAM. This field should be read as '1'
15005 * to indicate that the output has been completely written.
15006 * When writing a command completion or response to an internal processor,
15007 * the order of writes has to be such that this field is written last.
15010 } __attribute__((packed));
15012 /***********************
15013 * hwrm_port_led_qcaps *
15014 ***********************/
15017 /* hwrm_port_led_qcaps_input (size:192b/24B) */
15018 struct hwrm_port_led_qcaps_input {
15019 /* The HWRM command request type. */
15022 * The completion ring to send the completion event on. This should
15023 * be the NQ ID returned from the `nq_alloc` HWRM command.
15025 uint16_t cmpl_ring;
15027 * The sequence ID is used by the driver for tracking multiple
15028 * commands. This ID is treated as opaque data by the firmware and
15029 * the value is returned in the `hwrm_resp_hdr` upon completion.
15033 * The target ID of the command:
15034 * * 0x0-0xFFF8 - The function ID
15035 * * 0xFFF8-0xFFFE - Reserved for internal processors
15038 uint16_t target_id;
15040 * A physical address pointer pointing to a host buffer that the
15041 * command's response data will be written. This can be either a host
15042 * physical address (HPA) or a guest physical address (GPA) and must
15043 * point to a physically contiguous block of memory.
15045 uint64_t resp_addr;
15046 /* Port ID of port whose LED configuration is being queried. */
15048 uint8_t unused_0[6];
15049 } __attribute__((packed));
15051 /* hwrm_port_led_qcaps_output (size:384b/48B) */
15052 struct hwrm_port_led_qcaps_output {
15053 /* The specific error status for the command. */
15054 uint16_t error_code;
15055 /* The HWRM command request type. */
15057 /* The sequence ID from the original command. */
15059 /* The length of the response data in number of bytes. */
15062 * The number of LEDs that are configured on this port.
15063 * Up to 4 LEDs can be returned in the response.
15066 /* Reserved for future use. */
15068 /* An identifier for the LED #0. */
15070 /* The type of LED #0. */
15073 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
15075 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
15077 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
15078 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
15079 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
15081 * An identifier for the group of LEDs that LED #0 belongs
15083 * If set to 0, then the LED #0 cannot be grouped.
15084 * For all other non-zero values of this field, LED #0 is
15085 * grouped together with the LEDs with the same group ID
15088 uint8_t led0_group_id;
15090 /* The states supported by LED #0. */
15091 uint16_t led0_state_caps;
15093 * If set to 1, this LED is enabled.
15094 * If set to 0, this LED is disabled.
15096 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
15099 * If set to 1, off state is supported on this LED.
15100 * If set to 0, off state is not supported on this LED.
15102 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
15105 * If set to 1, on state is supported on this LED.
15106 * If set to 0, on state is not supported on this LED.
15108 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
15111 * If set to 1, blink state is supported on this LED.
15112 * If set to 0, blink state is not supported on this LED.
15114 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
15117 * If set to 1, blink_alt state is supported on this LED.
15118 * If set to 0, blink_alt state is not supported on this LED.
15120 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
15122 /* The colors supported by LED #0. */
15123 uint16_t led0_color_caps;
15125 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
15128 * If set to 1, Amber color is supported on this LED.
15129 * If set to 0, Amber color is not supported on this LED.
15131 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
15134 * If set to 1, Green color is supported on this LED.
15135 * If set to 0, Green color is not supported on this LED.
15137 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
15139 /* An identifier for the LED #1. */
15141 /* The type of LED #1. */
15144 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
15146 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
15148 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
15149 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
15150 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
15152 * An identifier for the group of LEDs that LED #1 belongs
15154 * If set to 0, then the LED #0 cannot be grouped.
15155 * For all other non-zero values of this field, LED #0 is
15156 * grouped together with the LEDs with the same group ID
15159 uint8_t led1_group_id;
15161 /* The states supported by LED #1. */
15162 uint16_t led1_state_caps;
15164 * If set to 1, this LED is enabled.
15165 * If set to 0, this LED is disabled.
15167 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
15170 * If set to 1, off state is supported on this LED.
15171 * If set to 0, off state is not supported on this LED.
15173 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
15176 * If set to 1, on state is supported on this LED.
15177 * If set to 0, on state is not supported on this LED.
15179 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
15182 * If set to 1, blink state is supported on this LED.
15183 * If set to 0, blink state is not supported on this LED.
15185 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
15188 * If set to 1, blink_alt state is supported on this LED.
15189 * If set to 0, blink_alt state is not supported on this LED.
15191 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
15193 /* The colors supported by LED #1. */
15194 uint16_t led1_color_caps;
15196 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
15199 * If set to 1, Amber color is supported on this LED.
15200 * If set to 0, Amber color is not supported on this LED.
15202 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
15205 * If set to 1, Green color is supported on this LED.
15206 * If set to 0, Green color is not supported on this LED.
15208 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
15210 /* An identifier for the LED #2. */
15212 /* The type of LED #2. */
15215 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
15217 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
15219 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
15220 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
15221 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
15223 * An identifier for the group of LEDs that LED #0 belongs
15225 * If set to 0, then the LED #0 cannot be grouped.
15226 * For all other non-zero values of this field, LED #0 is
15227 * grouped together with the LEDs with the same group ID
15230 uint8_t led2_group_id;
15232 /* The states supported by LED #2. */
15233 uint16_t led2_state_caps;
15235 * If set to 1, this LED is enabled.
15236 * If set to 0, this LED is disabled.
15238 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
15241 * If set to 1, off state is supported on this LED.
15242 * If set to 0, off state is not supported on this LED.
15244 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
15247 * If set to 1, on state is supported on this LED.
15248 * If set to 0, on state is not supported on this LED.
15250 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
15253 * If set to 1, blink state is supported on this LED.
15254 * If set to 0, blink state is not supported on this LED.
15256 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
15259 * If set to 1, blink_alt state is supported on this LED.
15260 * If set to 0, blink_alt state is not supported on this LED.
15262 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
15264 /* The colors supported by LED #2. */
15265 uint16_t led2_color_caps;
15267 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
15270 * If set to 1, Amber color is supported on this LED.
15271 * If set to 0, Amber color is not supported on this LED.
15273 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
15276 * If set to 1, Green color is supported on this LED.
15277 * If set to 0, Green color is not supported on this LED.
15279 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
15281 /* An identifier for the LED #3. */
15283 /* The type of LED #3. */
15286 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
15288 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
15290 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
15291 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
15292 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
15294 * An identifier for the group of LEDs that LED #3 belongs
15296 * If set to 0, then the LED #0 cannot be grouped.
15297 * For all other non-zero values of this field, LED #0 is
15298 * grouped together with the LEDs with the same group ID
15301 uint8_t led3_group_id;
15303 /* The states supported by LED #3. */
15304 uint16_t led3_state_caps;
15306 * If set to 1, this LED is enabled.
15307 * If set to 0, this LED is disabled.
15309 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
15312 * If set to 1, off state is supported on this LED.
15313 * If set to 0, off state is not supported on this LED.
15315 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
15318 * If set to 1, on state is supported on this LED.
15319 * If set to 0, on state is not supported on this LED.
15321 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
15324 * If set to 1, blink state is supported on this LED.
15325 * If set to 0, blink state is not supported on this LED.
15327 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
15330 * If set to 1, blink_alt state is supported on this LED.
15331 * If set to 0, blink_alt state is not supported on this LED.
15333 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
15335 /* The colors supported by LED #3. */
15336 uint16_t led3_color_caps;
15338 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
15341 * If set to 1, Amber color is supported on this LED.
15342 * If set to 0, Amber color is not supported on this LED.
15344 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
15347 * If set to 1, Green color is supported on this LED.
15348 * If set to 0, Green color is not supported on this LED.
15350 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
15352 uint8_t unused_4[3];
15354 * This field is used in Output records to indicate that the output
15355 * is completely written to RAM. This field should be read as '1'
15356 * to indicate that the output has been completely written.
15357 * When writing a command completion or response to an internal processor,
15358 * the order of writes has to be such that this field is written last.
15361 } __attribute__((packed));
15363 /***********************
15364 * hwrm_queue_qportcfg *
15365 ***********************/
15368 /* hwrm_queue_qportcfg_input (size:192b/24B) */
15369 struct hwrm_queue_qportcfg_input {
15370 /* The HWRM command request type. */
15373 * The completion ring to send the completion event on. This should
15374 * be the NQ ID returned from the `nq_alloc` HWRM command.
15376 uint16_t cmpl_ring;
15378 * The sequence ID is used by the driver for tracking multiple
15379 * commands. This ID is treated as opaque data by the firmware and
15380 * the value is returned in the `hwrm_resp_hdr` upon completion.
15384 * The target ID of the command:
15385 * * 0x0-0xFFF8 - The function ID
15386 * * 0xFFF8-0xFFFE - Reserved for internal processors
15389 uint16_t target_id;
15391 * A physical address pointer pointing to a host buffer that the
15392 * command's response data will be written. This can be either a host
15393 * physical address (HPA) or a guest physical address (GPA) and must
15394 * point to a physically contiguous block of memory.
15396 uint64_t resp_addr;
15399 * Enumeration denoting the RX, TX type of the resource.
15400 * This enumeration is used for resources that are similar for both
15401 * TX and RX paths of the chip.
15403 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
15405 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15407 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15408 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
15409 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
15411 * Port ID of port for which the queue configuration is being
15412 * queried. This field is only required when sent by IPC.
15416 * Drivers will set this capability when it can use
15417 * queue_idx_service_profile to map the queues to application.
15419 uint8_t drv_qmap_cap;
15421 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
15423 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
15424 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
15425 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
15427 } __attribute__((packed));
15429 /* hwrm_queue_qportcfg_output (size:256b/32B) */
15430 struct hwrm_queue_qportcfg_output {
15431 /* The specific error status for the command. */
15432 uint16_t error_code;
15433 /* The HWRM command request type. */
15435 /* The sequence ID from the original command. */
15437 /* The length of the response data in number of bytes. */
15440 * The maximum number of queues that can be configured on this
15442 * Valid values range from 1 through 8.
15444 uint8_t max_configurable_queues;
15446 * The maximum number of lossless queues that can be configured
15448 * Valid values range from 0 through 8.
15450 uint8_t max_configurable_lossless_queues;
15452 * Bitmask indicating which queues can be configured by the
15453 * hwrm_queue_cfg command.
15455 * Each bit represents a specific queue where bit 0 represents
15456 * queue 0 and bit 7 represents queue 7.
15457 * # A value of 0 indicates that the queue is not configurable
15458 * by the hwrm_queue_cfg command.
15459 * # A value of 1 indicates that the queue is configurable.
15460 * # A hwrm_queue_cfg command shall return error when trying to
15461 * configure a queue not configurable.
15463 uint8_t queue_cfg_allowed;
15464 /* Information about queue configuration. */
15465 uint8_t queue_cfg_info;
15467 * If this flag is set to '1', then the queues are
15468 * configured asymmetrically on TX and RX sides.
15469 * If this flag is set to '0', then the queues are
15470 * configured symmetrically on TX and RX sides. For
15471 * symmetric configuration, the queue configuration
15472 * including queue ids and service profiles on the
15473 * TX side is the same as the corresponding queue
15474 * configuration on the RX side.
15476 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
15479 * Bitmask indicating which queues can be configured by the
15480 * hwrm_queue_pfcenable_cfg command.
15482 * Each bit represents a specific priority where bit 0 represents
15483 * priority 0 and bit 7 represents priority 7.
15484 * # A value of 0 indicates that the priority is not configurable by
15485 * the hwrm_queue_pfcenable_cfg command.
15486 * # A value of 1 indicates that the priority is configurable.
15487 * # A hwrm_queue_pfcenable_cfg command shall return error when
15488 * trying to configure a priority that is not configurable.
15490 uint8_t queue_pfcenable_cfg_allowed;
15492 * Bitmask indicating which queues can be configured by the
15493 * hwrm_queue_pri2cos_cfg command.
15495 * Each bit represents a specific queue where bit 0 represents
15496 * queue 0 and bit 7 represents queue 7.
15497 * # A value of 0 indicates that the queue is not configurable
15498 * by the hwrm_queue_pri2cos_cfg command.
15499 * # A value of 1 indicates that the queue is configurable.
15500 * # A hwrm_queue_pri2cos_cfg command shall return error when
15501 * trying to configure a queue that is not configurable.
15503 uint8_t queue_pri2cos_cfg_allowed;
15505 * Bitmask indicating which queues can be configured by the
15506 * hwrm_queue_pri2cos_cfg command.
15508 * Each bit represents a specific queue where bit 0 represents
15509 * queue 0 and bit 7 represents queue 7.
15510 * # A value of 0 indicates that the queue is not configurable
15511 * by the hwrm_queue_pri2cos_cfg command.
15512 * # A value of 1 indicates that the queue is configurable.
15513 * # A hwrm_queue_pri2cos_cfg command shall return error when
15514 * trying to configure a queue not configurable.
15516 uint8_t queue_cos2bw_cfg_allowed;
15518 * ID of CoS Queue 0.
15521 * # This ID can be used on any subsequent call to an hwrm command
15522 * that takes a queue id.
15523 * # IDs must always be queried by this command before any use
15524 * by the driver or software.
15525 * # Any driver or software should not make any assumptions about
15527 * # A value of 0xff indicates that the queue is not available.
15528 * # Available queues may not be in sequential order.
15531 /* This value is applicable to CoS queues only. */
15532 uint8_t queue_id0_service_profile;
15533 /* Lossy (best-effort) */
15534 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
15536 /* Lossless (legacy) */
15537 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
15539 /* Lossless RoCE */
15540 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
15542 /* Lossy RoCE CNP */
15543 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15546 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
15548 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15549 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
15551 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
15552 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
15554 * ID of CoS Queue 1.
15557 * # This ID can be used on any subsequent call to an hwrm command
15558 * that takes a queue id.
15559 * # IDs must always be queried by this command before any use
15560 * by the driver or software.
15561 * # Any driver or software should not make any assumptions about
15563 * # A value of 0xff indicates that the queue is not available.
15564 * # Available queues may not be in sequential order.
15567 /* This value is applicable to CoS queues only. */
15568 uint8_t queue_id1_service_profile;
15569 /* Lossy (best-effort) */
15570 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
15572 /* Lossless (legacy) */
15573 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
15575 /* Lossless RoCE */
15576 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
15578 /* Lossy RoCE CNP */
15579 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15582 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
15584 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15585 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
15587 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
15588 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
15590 * ID of CoS Queue 2.
15593 * # This ID can be used on any subsequent call to an hwrm command
15594 * that takes a queue id.
15595 * # IDs must always be queried by this command before any use
15596 * by the driver or software.
15597 * # Any driver or software should not make any assumptions about
15599 * # A value of 0xff indicates that the queue is not available.
15600 * # Available queues may not be in sequential order.
15603 /* This value is applicable to CoS queues only. */
15604 uint8_t queue_id2_service_profile;
15605 /* Lossy (best-effort) */
15606 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
15608 /* Lossless (legacy) */
15609 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
15611 /* Lossless RoCE */
15612 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
15614 /* Lossy RoCE CNP */
15615 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15618 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
15620 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15621 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
15623 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
15624 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
15626 * ID of CoS Queue 3.
15629 * # This ID can be used on any subsequent call to an hwrm command
15630 * that takes a queue id.
15631 * # IDs must always be queried by this command before any use
15632 * by the driver or software.
15633 * # Any driver or software should not make any assumptions about
15635 * # A value of 0xff indicates that the queue is not available.
15636 * # Available queues may not be in sequential order.
15639 /* This value is applicable to CoS queues only. */
15640 uint8_t queue_id3_service_profile;
15641 /* Lossy (best-effort) */
15642 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
15644 /* Lossless (legacy) */
15645 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
15647 /* Lossless RoCE */
15648 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
15650 /* Lossy RoCE CNP */
15651 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15654 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
15656 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15657 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
15659 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
15660 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
15662 * ID of CoS Queue 4.
15665 * # This ID can be used on any subsequent call to an hwrm command
15666 * that takes a queue id.
15667 * # IDs must always be queried by this command before any use
15668 * by the driver or software.
15669 * # Any driver or software should not make any assumptions about
15671 * # A value of 0xff indicates that the queue is not available.
15672 * # Available queues may not be in sequential order.
15675 /* This value is applicable to CoS queues only. */
15676 uint8_t queue_id4_service_profile;
15677 /* Lossy (best-effort) */
15678 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
15680 /* Lossless (legacy) */
15681 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
15683 /* Lossless RoCE */
15684 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
15686 /* Lossy RoCE CNP */
15687 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15690 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
15692 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15693 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
15695 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
15696 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
15698 * ID of CoS Queue 5.
15701 * # This ID can be used on any subsequent call to an hwrm command
15702 * that takes a queue id.
15703 * # IDs must always be queried by this command before any use
15704 * by the driver or software.
15705 * # Any driver or software should not make any assumptions about
15707 * # A value of 0xff indicates that the queue is not available.
15708 * # Available queues may not be in sequential order.
15711 /* This value is applicable to CoS queues only. */
15712 uint8_t queue_id5_service_profile;
15713 /* Lossy (best-effort) */
15714 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
15716 /* Lossless (legacy) */
15717 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
15719 /* Lossless RoCE */
15720 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
15722 /* Lossy RoCE CNP */
15723 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15726 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
15728 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15729 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
15731 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
15732 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
15734 * ID of CoS Queue 6.
15737 * # This ID can be used on any subsequent call to an hwrm command
15738 * that takes a queue id.
15739 * # IDs must always be queried by this command before any use
15740 * by the driver or software.
15741 * # Any driver or software should not make any assumptions about
15743 * # A value of 0xff indicates that the queue is not available.
15744 * # Available queues may not be in sequential order.
15747 /* This value is applicable to CoS queues only. */
15748 uint8_t queue_id6_service_profile;
15749 /* Lossy (best-effort) */
15750 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
15752 /* Lossless (legacy) */
15753 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
15755 /* Lossless RoCE */
15756 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
15758 /* Lossy RoCE CNP */
15759 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15762 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
15764 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15765 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
15767 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
15768 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
15770 * ID of CoS Queue 7.
15773 * # This ID can be used on any subsequent call to an hwrm command
15774 * that takes a queue id.
15775 * # IDs must always be queried by this command before any use
15776 * by the driver or software.
15777 * # Any driver or software should not make any assumptions about
15779 * # A value of 0xff indicates that the queue is not available.
15780 * # Available queues may not be in sequential order.
15783 /* This value is applicable to CoS queues only. */
15784 uint8_t queue_id7_service_profile;
15785 /* Lossy (best-effort) */
15786 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
15788 /* Lossless (legacy) */
15789 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
15791 /* Lossless RoCE */
15792 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
15794 /* Lossy RoCE CNP */
15795 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15798 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
15800 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15801 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
15803 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
15804 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
15806 * This field is used in Output records to indicate that the output
15807 * is completely written to RAM. This field should be read as '1'
15808 * to indicate that the output has been completely written.
15809 * When writing a command completion or response to an internal processor,
15810 * the order of writes has to be such that this field is written last.
15813 } __attribute__((packed));
15815 /*******************
15816 * hwrm_queue_qcfg *
15817 *******************/
15820 /* hwrm_queue_qcfg_input (size:192b/24B) */
15821 struct hwrm_queue_qcfg_input {
15822 /* The HWRM command request type. */
15825 * The completion ring to send the completion event on. This should
15826 * be the NQ ID returned from the `nq_alloc` HWRM command.
15828 uint16_t cmpl_ring;
15830 * The sequence ID is used by the driver for tracking multiple
15831 * commands. This ID is treated as opaque data by the firmware and
15832 * the value is returned in the `hwrm_resp_hdr` upon completion.
15836 * The target ID of the command:
15837 * * 0x0-0xFFF8 - The function ID
15838 * * 0xFFF8-0xFFFE - Reserved for internal processors
15841 uint16_t target_id;
15843 * A physical address pointer pointing to a host buffer that the
15844 * command's response data will be written. This can be either a host
15845 * physical address (HPA) or a guest physical address (GPA) and must
15846 * point to a physically contiguous block of memory.
15848 uint64_t resp_addr;
15851 * Enumeration denoting the RX, TX type of the resource.
15852 * This enumeration is used for resources that are similar for both
15853 * TX and RX paths of the chip.
15855 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
15857 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15859 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15860 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
15861 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
15862 /* Queue ID of the queue. */
15864 } __attribute__((packed));
15866 /* hwrm_queue_qcfg_output (size:128b/16B) */
15867 struct hwrm_queue_qcfg_output {
15868 /* The specific error status for the command. */
15869 uint16_t error_code;
15870 /* The HWRM command request type. */
15872 /* The sequence ID from the original command. */
15874 /* The length of the response data in number of bytes. */
15877 * This value is a the estimate packet length used in the
15880 uint32_t queue_len;
15881 /* This value is applicable to CoS queues only. */
15882 uint8_t service_profile;
15883 /* Lossy (best-effort) */
15884 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
15886 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
15887 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15888 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
15889 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
15890 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
15891 /* Information about queue configuration. */
15892 uint8_t queue_cfg_info;
15894 * If this flag is set to '1', then the queue is
15895 * configured asymmetrically on TX and RX sides.
15896 * If this flag is set to '0', then this queue is
15897 * configured symmetrically on TX and RX sides.
15899 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
15903 * This field is used in Output records to indicate that the output
15904 * is completely written to RAM. This field should be read as '1'
15905 * to indicate that the output has been completely written.
15906 * When writing a command completion or response to an internal processor,
15907 * the order of writes has to be such that this field is written last.
15910 } __attribute__((packed));
15912 /******************
15914 ******************/
15917 /* hwrm_queue_cfg_input (size:320b/40B) */
15918 struct hwrm_queue_cfg_input {
15919 /* The HWRM command request type. */
15922 * The completion ring to send the completion event on. This should
15923 * be the NQ ID returned from the `nq_alloc` HWRM command.
15925 uint16_t cmpl_ring;
15927 * The sequence ID is used by the driver for tracking multiple
15928 * commands. This ID is treated as opaque data by the firmware and
15929 * the value is returned in the `hwrm_resp_hdr` upon completion.
15933 * The target ID of the command:
15934 * * 0x0-0xFFF8 - The function ID
15935 * * 0xFFF8-0xFFFE - Reserved for internal processors
15938 uint16_t target_id;
15940 * A physical address pointer pointing to a host buffer that the
15941 * command's response data will be written. This can be either a host
15942 * physical address (HPA) or a guest physical address (GPA) and must
15943 * point to a physically contiguous block of memory.
15945 uint64_t resp_addr;
15948 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
15949 * This enumeration is used for resources that are similar for both
15950 * TX and RX paths of the chip.
15952 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
15953 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
15955 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15957 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15958 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
15959 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
15960 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
15961 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
15964 * This bit must be '1' for the dflt_len field to be
15967 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
15969 * This bit must be '1' for the service_profile field to be
15972 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
15973 /* Queue ID of queue that is to be configured by this function. */
15976 * This value is a the estimate packet length used in the
15978 * Set to 0xFF... (All Fs) to not adjust this value.
15981 /* This value is applicable to CoS queues only. */
15982 uint8_t service_profile;
15983 /* Lossy (best-effort) */
15984 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
15986 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
15987 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15988 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
15989 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
15990 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
15991 uint8_t unused_0[7];
15992 } __attribute__((packed));
15994 /* hwrm_queue_cfg_output (size:128b/16B) */
15995 struct hwrm_queue_cfg_output {
15996 /* The specific error status for the command. */
15997 uint16_t error_code;
15998 /* The HWRM command request type. */
16000 /* The sequence ID from the original command. */
16002 /* The length of the response data in number of bytes. */
16004 uint8_t unused_0[7];
16006 * This field is used in Output records to indicate that the output
16007 * is completely written to RAM. This field should be read as '1'
16008 * to indicate that the output has been completely written.
16009 * When writing a command completion or response to an internal processor,
16010 * the order of writes has to be such that this field is written last.
16013 } __attribute__((packed));
16015 /*****************************
16016 * hwrm_queue_pfcenable_qcfg *
16017 *****************************/
16020 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
16021 struct hwrm_queue_pfcenable_qcfg_input {
16022 /* The HWRM command request type. */
16025 * The completion ring to send the completion event on. This should
16026 * be the NQ ID returned from the `nq_alloc` HWRM command.
16028 uint16_t cmpl_ring;
16030 * The sequence ID is used by the driver for tracking multiple
16031 * commands. This ID is treated as opaque data by the firmware and
16032 * the value is returned in the `hwrm_resp_hdr` upon completion.
16036 * The target ID of the command:
16037 * * 0x0-0xFFF8 - The function ID
16038 * * 0xFFF8-0xFFFE - Reserved for internal processors
16041 uint16_t target_id;
16043 * A physical address pointer pointing to a host buffer that the
16044 * command's response data will be written. This can be either a host
16045 * physical address (HPA) or a guest physical address (GPA) and must
16046 * point to a physically contiguous block of memory.
16048 uint64_t resp_addr;
16050 * Port ID of port for which the table is being configured.
16051 * The HWRM needs to check whether this function is allowed
16052 * to configure pri2cos mapping on this port.
16055 uint8_t unused_0[6];
16056 } __attribute__((packed));
16058 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
16059 struct hwrm_queue_pfcenable_qcfg_output {
16060 /* The specific error status for the command. */
16061 uint16_t error_code;
16062 /* The HWRM command request type. */
16064 /* The sequence ID from the original command. */
16066 /* The length of the response data in number of bytes. */
16069 /* If set to 1, then PFC is enabled on PRI 0. */
16070 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
16072 /* If set to 1, then PFC is enabled on PRI 1. */
16073 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
16075 /* If set to 1, then PFC is enabled on PRI 2. */
16076 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
16078 /* If set to 1, then PFC is enabled on PRI 3. */
16079 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
16081 /* If set to 1, then PFC is enabled on PRI 4. */
16082 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
16084 /* If set to 1, then PFC is enabled on PRI 5. */
16085 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
16087 /* If set to 1, then PFC is enabled on PRI 6. */
16088 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
16090 /* If set to 1, then PFC is enabled on PRI 7. */
16091 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
16093 uint8_t unused_0[3];
16095 * This field is used in Output records to indicate that the output
16096 * is completely written to RAM. This field should be read as '1'
16097 * to indicate that the output has been completely written.
16098 * When writing a command completion or response to an internal processor,
16099 * the order of writes has to be such that this field is written last.
16102 } __attribute__((packed));
16104 /****************************
16105 * hwrm_queue_pfcenable_cfg *
16106 ****************************/
16109 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
16110 struct hwrm_queue_pfcenable_cfg_input {
16111 /* The HWRM command request type. */
16114 * The completion ring to send the completion event on. This should
16115 * be the NQ ID returned from the `nq_alloc` HWRM command.
16117 uint16_t cmpl_ring;
16119 * The sequence ID is used by the driver for tracking multiple
16120 * commands. This ID is treated as opaque data by the firmware and
16121 * the value is returned in the `hwrm_resp_hdr` upon completion.
16125 * The target ID of the command:
16126 * * 0x0-0xFFF8 - The function ID
16127 * * 0xFFF8-0xFFFE - Reserved for internal processors
16130 uint16_t target_id;
16132 * A physical address pointer pointing to a host buffer that the
16133 * command's response data will be written. This can be either a host
16134 * physical address (HPA) or a guest physical address (GPA) and must
16135 * point to a physically contiguous block of memory.
16137 uint64_t resp_addr;
16139 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
16140 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
16142 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
16143 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
16145 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
16146 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
16148 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
16149 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
16151 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
16152 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
16154 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
16155 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
16157 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
16158 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
16160 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
16161 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
16164 * Port ID of port for which the table is being configured.
16165 * The HWRM needs to check whether this function is allowed
16166 * to configure pri2cos mapping on this port.
16169 uint8_t unused_0[2];
16170 } __attribute__((packed));
16172 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
16173 struct hwrm_queue_pfcenable_cfg_output {
16174 /* The specific error status for the command. */
16175 uint16_t error_code;
16176 /* The HWRM command request type. */
16178 /* The sequence ID from the original command. */
16180 /* The length of the response data in number of bytes. */
16182 uint8_t unused_0[7];
16184 * This field is used in Output records to indicate that the output
16185 * is completely written to RAM. This field should be read as '1'
16186 * to indicate that the output has been completely written.
16187 * When writing a command completion or response to an internal processor,
16188 * the order of writes has to be such that this field is written last.
16191 } __attribute__((packed));
16193 /***************************
16194 * hwrm_queue_pri2cos_qcfg *
16195 ***************************/
16198 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
16199 struct hwrm_queue_pri2cos_qcfg_input {
16200 /* The HWRM command request type. */
16203 * The completion ring to send the completion event on. This should
16204 * be the NQ ID returned from the `nq_alloc` HWRM command.
16206 uint16_t cmpl_ring;
16208 * The sequence ID is used by the driver for tracking multiple
16209 * commands. This ID is treated as opaque data by the firmware and
16210 * the value is returned in the `hwrm_resp_hdr` upon completion.
16214 * The target ID of the command:
16215 * * 0x0-0xFFF8 - The function ID
16216 * * 0xFFF8-0xFFFE - Reserved for internal processors
16219 uint16_t target_id;
16221 * A physical address pointer pointing to a host buffer that the
16222 * command's response data will be written. This can be either a host
16223 * physical address (HPA) or a guest physical address (GPA) and must
16224 * point to a physically contiguous block of memory.
16226 uint64_t resp_addr;
16229 * Enumeration denoting the RX, TX type of the resource.
16230 * This enumeration is used for resources that are similar for both
16231 * TX and RX paths of the chip.
16233 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
16235 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
16237 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
16238 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
16239 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
16241 * When this bit is set to '0', the query is
16242 * for VLAN PRI field in tunnel headers.
16243 * When this bit is set to '1', the query is
16244 * for VLAN PRI field in inner packet headers.
16246 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
16248 * Port ID of port for which the table is being configured.
16249 * The HWRM needs to check whether this function is allowed
16250 * to configure pri2cos mapping on this port.
16253 uint8_t unused_0[3];
16254 } __attribute__((packed));
16256 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
16257 struct hwrm_queue_pri2cos_qcfg_output {
16258 /* The specific error status for the command. */
16259 uint16_t error_code;
16260 /* The HWRM command request type. */
16262 /* The sequence ID from the original command. */
16264 /* The length of the response data in number of bytes. */
16267 * CoS Queue assigned to priority 0. This value can only
16268 * be changed before traffic has started.
16269 * A value of 0xff indicates that no CoS queue is assigned to the
16270 * specified priority.
16272 uint8_t pri0_cos_queue_id;
16274 * CoS Queue assigned to priority 1. This value can only
16275 * be changed before traffic has started.
16276 * A value of 0xff indicates that no CoS queue is assigned to the
16277 * specified priority.
16279 uint8_t pri1_cos_queue_id;
16281 * CoS Queue assigned to priority 2 This value can only
16282 * be changed before traffic has started.
16283 * A value of 0xff indicates that no CoS queue is assigned to the
16284 * specified priority.
16286 uint8_t pri2_cos_queue_id;
16288 * CoS Queue assigned to priority 3. This value can only
16289 * be changed before traffic has started.
16290 * A value of 0xff indicates that no CoS queue is assigned to the
16291 * specified priority.
16293 uint8_t pri3_cos_queue_id;
16295 * CoS Queue assigned to priority 4. This value can only
16296 * be changed before traffic has started.
16297 * A value of 0xff indicates that no CoS queue is assigned to the
16298 * specified priority.
16300 uint8_t pri4_cos_queue_id;
16302 * CoS Queue assigned to priority 5. This value can only
16303 * be changed before traffic has started.
16304 * A value of 0xff indicates that no CoS queue is assigned to the
16305 * specified priority.
16307 uint8_t pri5_cos_queue_id;
16309 * CoS Queue assigned to priority 6. This value can only
16310 * be changed before traffic has started.
16311 * A value of 0xff indicates that no CoS queue is assigned to the
16312 * specified priority.
16314 uint8_t pri6_cos_queue_id;
16316 * CoS Queue assigned to priority 7. This value can only
16317 * be changed before traffic has started.
16318 * A value of 0xff indicates that no CoS queue is assigned to the
16319 * specified priority.
16321 uint8_t pri7_cos_queue_id;
16322 /* Information about queue configuration. */
16323 uint8_t queue_cfg_info;
16325 * If this flag is set to '1', then the PRI to CoS
16326 * configuration is asymmetric on TX and RX sides.
16327 * If this flag is set to '0', then PRI to CoS configuration
16328 * is symmetric on TX and RX sides.
16330 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
16332 uint8_t unused_0[6];
16334 * This field is used in Output records to indicate that the output
16335 * is completely written to RAM. This field should be read as '1'
16336 * to indicate that the output has been completely written.
16337 * When writing a command completion or response to an internal processor,
16338 * the order of writes has to be such that this field is written last.
16341 } __attribute__((packed));
16343 /**************************
16344 * hwrm_queue_pri2cos_cfg *
16345 **************************/
16348 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
16349 struct hwrm_queue_pri2cos_cfg_input {
16350 /* The HWRM command request type. */
16353 * The completion ring to send the completion event on. This should
16354 * be the NQ ID returned from the `nq_alloc` HWRM command.
16356 uint16_t cmpl_ring;
16358 * The sequence ID is used by the driver for tracking multiple
16359 * commands. This ID is treated as opaque data by the firmware and
16360 * the value is returned in the `hwrm_resp_hdr` upon completion.
16364 * The target ID of the command:
16365 * * 0x0-0xFFF8 - The function ID
16366 * * 0xFFF8-0xFFFE - Reserved for internal processors
16369 uint16_t target_id;
16371 * A physical address pointer pointing to a host buffer that the
16372 * command's response data will be written. This can be either a host
16373 * physical address (HPA) or a guest physical address (GPA) and must
16374 * point to a physically contiguous block of memory.
16376 uint64_t resp_addr;
16379 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
16380 * This enumeration is used for resources that are similar for both
16381 * TX and RX paths of the chip.
16383 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
16384 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
16386 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
16388 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
16389 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
16390 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
16391 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
16392 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
16394 * When this bit is set to '0', the mapping is requested
16395 * for VLAN PRI field in tunnel headers.
16396 * When this bit is set to '1', the mapping is requested
16397 * for VLAN PRI field in inner packet headers.
16399 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
16402 * This bit must be '1' for the pri0_cos_queue_id field to be
16405 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
16408 * This bit must be '1' for the pri1_cos_queue_id field to be
16411 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
16414 * This bit must be '1' for the pri2_cos_queue_id field to be
16417 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
16420 * This bit must be '1' for the pri3_cos_queue_id field to be
16423 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
16426 * This bit must be '1' for the pri4_cos_queue_id field to be
16429 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
16432 * This bit must be '1' for the pri5_cos_queue_id field to be
16435 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
16438 * This bit must be '1' for the pri6_cos_queue_id field to be
16441 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
16444 * This bit must be '1' for the pri7_cos_queue_id field to be
16447 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
16450 * Port ID of port for which the table is being configured.
16451 * The HWRM needs to check whether this function is allowed
16452 * to configure pri2cos mapping on this port.
16456 * CoS Queue assigned to priority 0. This value can only
16457 * be changed before traffic has started.
16459 uint8_t pri0_cos_queue_id;
16461 * CoS Queue assigned to priority 1. This value can only
16462 * be changed before traffic has started.
16464 uint8_t pri1_cos_queue_id;
16466 * CoS Queue assigned to priority 2 This value can only
16467 * be changed before traffic has started.
16469 uint8_t pri2_cos_queue_id;
16471 * CoS Queue assigned to priority 3. This value can only
16472 * be changed before traffic has started.
16474 uint8_t pri3_cos_queue_id;
16476 * CoS Queue assigned to priority 4. This value can only
16477 * be changed before traffic has started.
16479 uint8_t pri4_cos_queue_id;
16481 * CoS Queue assigned to priority 5. This value can only
16482 * be changed before traffic has started.
16484 uint8_t pri5_cos_queue_id;
16486 * CoS Queue assigned to priority 6. This value can only
16487 * be changed before traffic has started.
16489 uint8_t pri6_cos_queue_id;
16491 * CoS Queue assigned to priority 7. This value can only
16492 * be changed before traffic has started.
16494 uint8_t pri7_cos_queue_id;
16495 uint8_t unused_0[7];
16496 } __attribute__((packed));
16498 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
16499 struct hwrm_queue_pri2cos_cfg_output {
16500 /* The specific error status for the command. */
16501 uint16_t error_code;
16502 /* The HWRM command request type. */
16504 /* The sequence ID from the original command. */
16506 /* The length of the response data in number of bytes. */
16508 uint8_t unused_0[7];
16510 * This field is used in Output records to indicate that the output
16511 * is completely written to RAM. This field should be read as '1'
16512 * to indicate that the output has been completely written.
16513 * When writing a command completion or response to an internal processor,
16514 * the order of writes has to be such that this field is written last.
16517 } __attribute__((packed));
16519 /**************************
16520 * hwrm_queue_cos2bw_qcfg *
16521 **************************/
16524 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
16525 struct hwrm_queue_cos2bw_qcfg_input {
16526 /* The HWRM command request type. */
16529 * The completion ring to send the completion event on. This should
16530 * be the NQ ID returned from the `nq_alloc` HWRM command.
16532 uint16_t cmpl_ring;
16534 * The sequence ID is used by the driver for tracking multiple
16535 * commands. This ID is treated as opaque data by the firmware and
16536 * the value is returned in the `hwrm_resp_hdr` upon completion.
16540 * The target ID of the command:
16541 * * 0x0-0xFFF8 - The function ID
16542 * * 0xFFF8-0xFFFE - Reserved for internal processors
16545 uint16_t target_id;
16547 * A physical address pointer pointing to a host buffer that the
16548 * command's response data will be written. This can be either a host
16549 * physical address (HPA) or a guest physical address (GPA) and must
16550 * point to a physically contiguous block of memory.
16552 uint64_t resp_addr;
16554 * Port ID of port for which the table is being configured.
16555 * The HWRM needs to check whether this function is allowed
16556 * to configure TC BW assignment on this port.
16559 uint8_t unused_0[6];
16560 } __attribute__((packed));
16562 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
16563 struct hwrm_queue_cos2bw_qcfg_output {
16564 /* The specific error status for the command. */
16565 uint16_t error_code;
16566 /* The HWRM command request type. */
16568 /* The sequence ID from the original command. */
16570 /* The length of the response data in number of bytes. */
16572 /* ID of CoS Queue 0. */
16577 * Minimum BW allocated to CoS Queue.
16578 * The HWRM will translate this value into byte counter and
16579 * time interval used for this COS inside the device.
16581 uint32_t queue_id0_min_bw;
16582 /* The bandwidth value. */
16583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
16584 UINT32_C(0xfffffff)
16585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
16587 /* The granularity of the value (bits or bytes). */
16588 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
16589 UINT32_C(0x10000000)
16590 /* Value is in bits. */
16591 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
16592 (UINT32_C(0x0) << 28)
16593 /* Value is in bytes. */
16594 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
16595 (UINT32_C(0x1) << 28)
16596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
16597 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
16598 /* bw_value_unit is 3 b */
16599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
16600 UINT32_C(0xe0000000)
16601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
16603 /* Value is in Mb or MB (base 10). */
16604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
16605 (UINT32_C(0x0) << 29)
16606 /* Value is in Kb or KB (base 10). */
16607 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
16608 (UINT32_C(0x2) << 29)
16609 /* Value is in bits or bytes. */
16610 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
16611 (UINT32_C(0x4) << 29)
16612 /* Value is in Gb or GB (base 10). */
16613 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
16614 (UINT32_C(0x6) << 29)
16615 /* Value is in 1/100th of a percentage of total bandwidth. */
16616 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16617 (UINT32_C(0x1) << 29)
16619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
16620 (UINT32_C(0x7) << 29)
16621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
16622 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
16624 * Maximum BW allocated to CoS Queue.
16625 * The HWRM will translate this value into byte counter and
16626 * time interval used for this COS inside the device.
16628 uint32_t queue_id0_max_bw;
16629 /* The bandwidth value. */
16630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
16631 UINT32_C(0xfffffff)
16632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
16634 /* The granularity of the value (bits or bytes). */
16635 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
16636 UINT32_C(0x10000000)
16637 /* Value is in bits. */
16638 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
16639 (UINT32_C(0x0) << 28)
16640 /* Value is in bytes. */
16641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
16642 (UINT32_C(0x1) << 28)
16643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
16644 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
16645 /* bw_value_unit is 3 b */
16646 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
16647 UINT32_C(0xe0000000)
16648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
16650 /* Value is in Mb or MB (base 10). */
16651 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
16652 (UINT32_C(0x0) << 29)
16653 /* Value is in Kb or KB (base 10). */
16654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
16655 (UINT32_C(0x2) << 29)
16656 /* Value is in bits or bytes. */
16657 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
16658 (UINT32_C(0x4) << 29)
16659 /* Value is in Gb or GB (base 10). */
16660 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
16661 (UINT32_C(0x6) << 29)
16662 /* Value is in 1/100th of a percentage of total bandwidth. */
16663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16664 (UINT32_C(0x1) << 29)
16666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
16667 (UINT32_C(0x7) << 29)
16668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
16669 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
16670 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16671 uint8_t queue_id0_tsa_assign;
16672 /* Strict Priority */
16673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
16675 /* Enhanced Transmission Selection */
16676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
16679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
16682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
16685 * Priority level for strict priority. Valid only when the
16686 * tsa_assign is 0 - Strict Priority (SP)
16687 * 0..7 - Valid values.
16688 * 8..255 - Reserved.
16690 uint8_t queue_id0_pri_lvl;
16692 * Weight used to allocate remaining BW for this COS after
16693 * servicing guaranteed bandwidths for all COS.
16695 uint8_t queue_id0_bw_weight;
16696 /* ID of CoS Queue 1. */
16699 * Minimum BW allocated to CoS Queue.
16700 * The HWRM will translate this value into byte counter and
16701 * time interval used for this COS inside the device.
16703 uint32_t queue_id1_min_bw;
16704 /* The bandwidth value. */
16705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
16706 UINT32_C(0xfffffff)
16707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
16709 /* The granularity of the value (bits or bytes). */
16710 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
16711 UINT32_C(0x10000000)
16712 /* Value is in bits. */
16713 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
16714 (UINT32_C(0x0) << 28)
16715 /* Value is in bytes. */
16716 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
16717 (UINT32_C(0x1) << 28)
16718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
16719 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
16720 /* bw_value_unit is 3 b */
16721 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
16722 UINT32_C(0xe0000000)
16723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
16725 /* Value is in Mb or MB (base 10). */
16726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
16727 (UINT32_C(0x0) << 29)
16728 /* Value is in Kb or KB (base 10). */
16729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
16730 (UINT32_C(0x2) << 29)
16731 /* Value is in bits or bytes. */
16732 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
16733 (UINT32_C(0x4) << 29)
16734 /* Value is in Gb or GB (base 10). */
16735 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
16736 (UINT32_C(0x6) << 29)
16737 /* Value is in 1/100th of a percentage of total bandwidth. */
16738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16739 (UINT32_C(0x1) << 29)
16741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
16742 (UINT32_C(0x7) << 29)
16743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
16744 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
16746 * Maximum BW allocated to CoS queue.
16747 * The HWRM will translate this value into byte counter and
16748 * time interval used for this COS inside the device.
16750 uint32_t queue_id1_max_bw;
16751 /* The bandwidth value. */
16752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
16753 UINT32_C(0xfffffff)
16754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
16756 /* The granularity of the value (bits or bytes). */
16757 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
16758 UINT32_C(0x10000000)
16759 /* Value is in bits. */
16760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
16761 (UINT32_C(0x0) << 28)
16762 /* Value is in bytes. */
16763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
16764 (UINT32_C(0x1) << 28)
16765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
16766 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
16767 /* bw_value_unit is 3 b */
16768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
16769 UINT32_C(0xe0000000)
16770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
16772 /* Value is in Mb or MB (base 10). */
16773 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
16774 (UINT32_C(0x0) << 29)
16775 /* Value is in Kb or KB (base 10). */
16776 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
16777 (UINT32_C(0x2) << 29)
16778 /* Value is in bits or bytes. */
16779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
16780 (UINT32_C(0x4) << 29)
16781 /* Value is in Gb or GB (base 10). */
16782 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
16783 (UINT32_C(0x6) << 29)
16784 /* Value is in 1/100th of a percentage of total bandwidth. */
16785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16786 (UINT32_C(0x1) << 29)
16788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
16789 (UINT32_C(0x7) << 29)
16790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
16791 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
16792 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16793 uint8_t queue_id1_tsa_assign;
16794 /* Strict Priority */
16795 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
16797 /* Enhanced Transmission Selection */
16798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
16801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
16804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
16807 * Priority level for strict priority. Valid only when the
16808 * tsa_assign is 0 - Strict Priority (SP)
16809 * 0..7 - Valid values.
16810 * 8..255 - Reserved.
16812 uint8_t queue_id1_pri_lvl;
16814 * Weight used to allocate remaining BW for this COS after
16815 * servicing guaranteed bandwidths for all COS.
16817 uint8_t queue_id1_bw_weight;
16818 /* ID of CoS Queue 2. */
16821 * Minimum BW allocated to CoS Queue.
16822 * The HWRM will translate this value into byte counter and
16823 * time interval used for this COS inside the device.
16825 uint32_t queue_id2_min_bw;
16826 /* The bandwidth value. */
16827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
16828 UINT32_C(0xfffffff)
16829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
16831 /* The granularity of the value (bits or bytes). */
16832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
16833 UINT32_C(0x10000000)
16834 /* Value is in bits. */
16835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
16836 (UINT32_C(0x0) << 28)
16837 /* Value is in bytes. */
16838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
16839 (UINT32_C(0x1) << 28)
16840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
16841 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
16842 /* bw_value_unit is 3 b */
16843 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
16844 UINT32_C(0xe0000000)
16845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
16847 /* Value is in Mb or MB (base 10). */
16848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
16849 (UINT32_C(0x0) << 29)
16850 /* Value is in Kb or KB (base 10). */
16851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
16852 (UINT32_C(0x2) << 29)
16853 /* Value is in bits or bytes. */
16854 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
16855 (UINT32_C(0x4) << 29)
16856 /* Value is in Gb or GB (base 10). */
16857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
16858 (UINT32_C(0x6) << 29)
16859 /* Value is in 1/100th of a percentage of total bandwidth. */
16860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16861 (UINT32_C(0x1) << 29)
16863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
16864 (UINT32_C(0x7) << 29)
16865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
16866 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
16868 * Maximum BW allocated to CoS queue.
16869 * The HWRM will translate this value into byte counter and
16870 * time interval used for this COS inside the device.
16872 uint32_t queue_id2_max_bw;
16873 /* The bandwidth value. */
16874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
16875 UINT32_C(0xfffffff)
16876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
16878 /* The granularity of the value (bits or bytes). */
16879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
16880 UINT32_C(0x10000000)
16881 /* Value is in bits. */
16882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
16883 (UINT32_C(0x0) << 28)
16884 /* Value is in bytes. */
16885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
16886 (UINT32_C(0x1) << 28)
16887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
16888 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
16889 /* bw_value_unit is 3 b */
16890 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
16891 UINT32_C(0xe0000000)
16892 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
16894 /* Value is in Mb or MB (base 10). */
16895 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
16896 (UINT32_C(0x0) << 29)
16897 /* Value is in Kb or KB (base 10). */
16898 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
16899 (UINT32_C(0x2) << 29)
16900 /* Value is in bits or bytes. */
16901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
16902 (UINT32_C(0x4) << 29)
16903 /* Value is in Gb or GB (base 10). */
16904 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
16905 (UINT32_C(0x6) << 29)
16906 /* Value is in 1/100th of a percentage of total bandwidth. */
16907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16908 (UINT32_C(0x1) << 29)
16910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
16911 (UINT32_C(0x7) << 29)
16912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
16913 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
16914 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16915 uint8_t queue_id2_tsa_assign;
16916 /* Strict Priority */
16917 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
16919 /* Enhanced Transmission Selection */
16920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
16923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
16926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
16929 * Priority level for strict priority. Valid only when the
16930 * tsa_assign is 0 - Strict Priority (SP)
16931 * 0..7 - Valid values.
16932 * 8..255 - Reserved.
16934 uint8_t queue_id2_pri_lvl;
16936 * Weight used to allocate remaining BW for this COS after
16937 * servicing guaranteed bandwidths for all COS.
16939 uint8_t queue_id2_bw_weight;
16940 /* ID of CoS Queue 3. */
16943 * Minimum BW allocated to CoS Queue.
16944 * The HWRM will translate this value into byte counter and
16945 * time interval used for this COS inside the device.
16947 uint32_t queue_id3_min_bw;
16948 /* The bandwidth value. */
16949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
16950 UINT32_C(0xfffffff)
16951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
16953 /* The granularity of the value (bits or bytes). */
16954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
16955 UINT32_C(0x10000000)
16956 /* Value is in bits. */
16957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
16958 (UINT32_C(0x0) << 28)
16959 /* Value is in bytes. */
16960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
16961 (UINT32_C(0x1) << 28)
16962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
16963 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
16964 /* bw_value_unit is 3 b */
16965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
16966 UINT32_C(0xe0000000)
16967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
16969 /* Value is in Mb or MB (base 10). */
16970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
16971 (UINT32_C(0x0) << 29)
16972 /* Value is in Kb or KB (base 10). */
16973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
16974 (UINT32_C(0x2) << 29)
16975 /* Value is in bits or bytes. */
16976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
16977 (UINT32_C(0x4) << 29)
16978 /* Value is in Gb or GB (base 10). */
16979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
16980 (UINT32_C(0x6) << 29)
16981 /* Value is in 1/100th of a percentage of total bandwidth. */
16982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16983 (UINT32_C(0x1) << 29)
16985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
16986 (UINT32_C(0x7) << 29)
16987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
16988 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
16990 * Maximum BW allocated to CoS queue.
16991 * The HWRM will translate this value into byte counter and
16992 * time interval used for this COS inside the device.
16994 uint32_t queue_id3_max_bw;
16995 /* The bandwidth value. */
16996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
16997 UINT32_C(0xfffffff)
16998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
17000 /* The granularity of the value (bits or bytes). */
17001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
17002 UINT32_C(0x10000000)
17003 /* Value is in bits. */
17004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
17005 (UINT32_C(0x0) << 28)
17006 /* Value is in bytes. */
17007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
17008 (UINT32_C(0x1) << 28)
17009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
17010 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
17011 /* bw_value_unit is 3 b */
17012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
17013 UINT32_C(0xe0000000)
17014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
17016 /* Value is in Mb or MB (base 10). */
17017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
17018 (UINT32_C(0x0) << 29)
17019 /* Value is in Kb or KB (base 10). */
17020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
17021 (UINT32_C(0x2) << 29)
17022 /* Value is in bits or bytes. */
17023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
17024 (UINT32_C(0x4) << 29)
17025 /* Value is in Gb or GB (base 10). */
17026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
17027 (UINT32_C(0x6) << 29)
17028 /* Value is in 1/100th of a percentage of total bandwidth. */
17029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17030 (UINT32_C(0x1) << 29)
17032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
17033 (UINT32_C(0x7) << 29)
17034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
17035 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
17036 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17037 uint8_t queue_id3_tsa_assign;
17038 /* Strict Priority */
17039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
17041 /* Enhanced Transmission Selection */
17042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
17045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
17048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
17051 * Priority level for strict priority. Valid only when the
17052 * tsa_assign is 0 - Strict Priority (SP)
17053 * 0..7 - Valid values.
17054 * 8..255 - Reserved.
17056 uint8_t queue_id3_pri_lvl;
17058 * Weight used to allocate remaining BW for this COS after
17059 * servicing guaranteed bandwidths for all COS.
17061 uint8_t queue_id3_bw_weight;
17062 /* ID of CoS Queue 4. */
17065 * Minimum BW allocated to CoS Queue.
17066 * The HWRM will translate this value into byte counter and
17067 * time interval used for this COS inside the device.
17069 uint32_t queue_id4_min_bw;
17070 /* The bandwidth value. */
17071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
17072 UINT32_C(0xfffffff)
17073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
17075 /* The granularity of the value (bits or bytes). */
17076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
17077 UINT32_C(0x10000000)
17078 /* Value is in bits. */
17079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
17080 (UINT32_C(0x0) << 28)
17081 /* Value is in bytes. */
17082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
17083 (UINT32_C(0x1) << 28)
17084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
17085 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
17086 /* bw_value_unit is 3 b */
17087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
17088 UINT32_C(0xe0000000)
17089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
17091 /* Value is in Mb or MB (base 10). */
17092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
17093 (UINT32_C(0x0) << 29)
17094 /* Value is in Kb or KB (base 10). */
17095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
17096 (UINT32_C(0x2) << 29)
17097 /* Value is in bits or bytes. */
17098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
17099 (UINT32_C(0x4) << 29)
17100 /* Value is in Gb or GB (base 10). */
17101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
17102 (UINT32_C(0x6) << 29)
17103 /* Value is in 1/100th of a percentage of total bandwidth. */
17104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17105 (UINT32_C(0x1) << 29)
17107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
17108 (UINT32_C(0x7) << 29)
17109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
17110 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
17112 * Maximum BW allocated to CoS queue.
17113 * The HWRM will translate this value into byte counter and
17114 * time interval used for this COS inside the device.
17116 uint32_t queue_id4_max_bw;
17117 /* The bandwidth value. */
17118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
17119 UINT32_C(0xfffffff)
17120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
17122 /* The granularity of the value (bits or bytes). */
17123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
17124 UINT32_C(0x10000000)
17125 /* Value is in bits. */
17126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
17127 (UINT32_C(0x0) << 28)
17128 /* Value is in bytes. */
17129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
17130 (UINT32_C(0x1) << 28)
17131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
17132 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
17133 /* bw_value_unit is 3 b */
17134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
17135 UINT32_C(0xe0000000)
17136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
17138 /* Value is in Mb or MB (base 10). */
17139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
17140 (UINT32_C(0x0) << 29)
17141 /* Value is in Kb or KB (base 10). */
17142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
17143 (UINT32_C(0x2) << 29)
17144 /* Value is in bits or bytes. */
17145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
17146 (UINT32_C(0x4) << 29)
17147 /* Value is in Gb or GB (base 10). */
17148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
17149 (UINT32_C(0x6) << 29)
17150 /* Value is in 1/100th of a percentage of total bandwidth. */
17151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17152 (UINT32_C(0x1) << 29)
17154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
17155 (UINT32_C(0x7) << 29)
17156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
17157 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
17158 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17159 uint8_t queue_id4_tsa_assign;
17160 /* Strict Priority */
17161 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
17163 /* Enhanced Transmission Selection */
17164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
17167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
17170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
17173 * Priority level for strict priority. Valid only when the
17174 * tsa_assign is 0 - Strict Priority (SP)
17175 * 0..7 - Valid values.
17176 * 8..255 - Reserved.
17178 uint8_t queue_id4_pri_lvl;
17180 * Weight used to allocate remaining BW for this COS after
17181 * servicing guaranteed bandwidths for all COS.
17183 uint8_t queue_id4_bw_weight;
17184 /* ID of CoS Queue 5. */
17187 * Minimum BW allocated to CoS Queue.
17188 * The HWRM will translate this value into byte counter and
17189 * time interval used for this COS inside the device.
17191 uint32_t queue_id5_min_bw;
17192 /* The bandwidth value. */
17193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
17194 UINT32_C(0xfffffff)
17195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
17197 /* The granularity of the value (bits or bytes). */
17198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
17199 UINT32_C(0x10000000)
17200 /* Value is in bits. */
17201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
17202 (UINT32_C(0x0) << 28)
17203 /* Value is in bytes. */
17204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
17205 (UINT32_C(0x1) << 28)
17206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
17207 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
17208 /* bw_value_unit is 3 b */
17209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
17210 UINT32_C(0xe0000000)
17211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
17213 /* Value is in Mb or MB (base 10). */
17214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
17215 (UINT32_C(0x0) << 29)
17216 /* Value is in Kb or KB (base 10). */
17217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
17218 (UINT32_C(0x2) << 29)
17219 /* Value is in bits or bytes. */
17220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
17221 (UINT32_C(0x4) << 29)
17222 /* Value is in Gb or GB (base 10). */
17223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
17224 (UINT32_C(0x6) << 29)
17225 /* Value is in 1/100th of a percentage of total bandwidth. */
17226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17227 (UINT32_C(0x1) << 29)
17229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
17230 (UINT32_C(0x7) << 29)
17231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
17232 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
17234 * Maximum BW allocated to CoS queue.
17235 * The HWRM will translate this value into byte counter and
17236 * time interval used for this COS inside the device.
17238 uint32_t queue_id5_max_bw;
17239 /* The bandwidth value. */
17240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
17241 UINT32_C(0xfffffff)
17242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
17244 /* The granularity of the value (bits or bytes). */
17245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
17246 UINT32_C(0x10000000)
17247 /* Value is in bits. */
17248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
17249 (UINT32_C(0x0) << 28)
17250 /* Value is in bytes. */
17251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
17252 (UINT32_C(0x1) << 28)
17253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
17254 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
17255 /* bw_value_unit is 3 b */
17256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
17257 UINT32_C(0xe0000000)
17258 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
17260 /* Value is in Mb or MB (base 10). */
17261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
17262 (UINT32_C(0x0) << 29)
17263 /* Value is in Kb or KB (base 10). */
17264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
17265 (UINT32_C(0x2) << 29)
17266 /* Value is in bits or bytes. */
17267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
17268 (UINT32_C(0x4) << 29)
17269 /* Value is in Gb or GB (base 10). */
17270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
17271 (UINT32_C(0x6) << 29)
17272 /* Value is in 1/100th of a percentage of total bandwidth. */
17273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17274 (UINT32_C(0x1) << 29)
17276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
17277 (UINT32_C(0x7) << 29)
17278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
17279 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
17280 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17281 uint8_t queue_id5_tsa_assign;
17282 /* Strict Priority */
17283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
17285 /* Enhanced Transmission Selection */
17286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
17289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
17292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
17295 * Priority level for strict priority. Valid only when the
17296 * tsa_assign is 0 - Strict Priority (SP)
17297 * 0..7 - Valid values.
17298 * 8..255 - Reserved.
17300 uint8_t queue_id5_pri_lvl;
17302 * Weight used to allocate remaining BW for this COS after
17303 * servicing guaranteed bandwidths for all COS.
17305 uint8_t queue_id5_bw_weight;
17306 /* ID of CoS Queue 6. */
17309 * Minimum BW allocated to CoS Queue.
17310 * The HWRM will translate this value into byte counter and
17311 * time interval used for this COS inside the device.
17313 uint32_t queue_id6_min_bw;
17314 /* The bandwidth value. */
17315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
17316 UINT32_C(0xfffffff)
17317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
17319 /* The granularity of the value (bits or bytes). */
17320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
17321 UINT32_C(0x10000000)
17322 /* Value is in bits. */
17323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
17324 (UINT32_C(0x0) << 28)
17325 /* Value is in bytes. */
17326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
17327 (UINT32_C(0x1) << 28)
17328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
17329 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
17330 /* bw_value_unit is 3 b */
17331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
17332 UINT32_C(0xe0000000)
17333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
17335 /* Value is in Mb or MB (base 10). */
17336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
17337 (UINT32_C(0x0) << 29)
17338 /* Value is in Kb or KB (base 10). */
17339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
17340 (UINT32_C(0x2) << 29)
17341 /* Value is in bits or bytes. */
17342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
17343 (UINT32_C(0x4) << 29)
17344 /* Value is in Gb or GB (base 10). */
17345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
17346 (UINT32_C(0x6) << 29)
17347 /* Value is in 1/100th of a percentage of total bandwidth. */
17348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17349 (UINT32_C(0x1) << 29)
17351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
17352 (UINT32_C(0x7) << 29)
17353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
17354 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
17356 * Maximum BW allocated to CoS queue.
17357 * The HWRM will translate this value into byte counter and
17358 * time interval used for this COS inside the device.
17360 uint32_t queue_id6_max_bw;
17361 /* The bandwidth value. */
17362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
17363 UINT32_C(0xfffffff)
17364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
17366 /* The granularity of the value (bits or bytes). */
17367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
17368 UINT32_C(0x10000000)
17369 /* Value is in bits. */
17370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
17371 (UINT32_C(0x0) << 28)
17372 /* Value is in bytes. */
17373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
17374 (UINT32_C(0x1) << 28)
17375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
17376 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
17377 /* bw_value_unit is 3 b */
17378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
17379 UINT32_C(0xe0000000)
17380 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
17382 /* Value is in Mb or MB (base 10). */
17383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
17384 (UINT32_C(0x0) << 29)
17385 /* Value is in Kb or KB (base 10). */
17386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
17387 (UINT32_C(0x2) << 29)
17388 /* Value is in bits or bytes. */
17389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
17390 (UINT32_C(0x4) << 29)
17391 /* Value is in Gb or GB (base 10). */
17392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
17393 (UINT32_C(0x6) << 29)
17394 /* Value is in 1/100th of a percentage of total bandwidth. */
17395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17396 (UINT32_C(0x1) << 29)
17398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
17399 (UINT32_C(0x7) << 29)
17400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
17401 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
17402 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17403 uint8_t queue_id6_tsa_assign;
17404 /* Strict Priority */
17405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
17407 /* Enhanced Transmission Selection */
17408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
17411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
17414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
17417 * Priority level for strict priority. Valid only when the
17418 * tsa_assign is 0 - Strict Priority (SP)
17419 * 0..7 - Valid values.
17420 * 8..255 - Reserved.
17422 uint8_t queue_id6_pri_lvl;
17424 * Weight used to allocate remaining BW for this COS after
17425 * servicing guaranteed bandwidths for all COS.
17427 uint8_t queue_id6_bw_weight;
17428 /* ID of CoS Queue 7. */
17431 * Minimum BW allocated to CoS Queue.
17432 * The HWRM will translate this value into byte counter and
17433 * time interval used for this COS inside the device.
17435 uint32_t queue_id7_min_bw;
17436 /* The bandwidth value. */
17437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
17438 UINT32_C(0xfffffff)
17439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
17441 /* The granularity of the value (bits or bytes). */
17442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
17443 UINT32_C(0x10000000)
17444 /* Value is in bits. */
17445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
17446 (UINT32_C(0x0) << 28)
17447 /* Value is in bytes. */
17448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
17449 (UINT32_C(0x1) << 28)
17450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
17451 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
17452 /* bw_value_unit is 3 b */
17453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
17454 UINT32_C(0xe0000000)
17455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
17457 /* Value is in Mb or MB (base 10). */
17458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
17459 (UINT32_C(0x0) << 29)
17460 /* Value is in Kb or KB (base 10). */
17461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
17462 (UINT32_C(0x2) << 29)
17463 /* Value is in bits or bytes. */
17464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
17465 (UINT32_C(0x4) << 29)
17466 /* Value is in Gb or GB (base 10). */
17467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
17468 (UINT32_C(0x6) << 29)
17469 /* Value is in 1/100th of a percentage of total bandwidth. */
17470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17471 (UINT32_C(0x1) << 29)
17473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
17474 (UINT32_C(0x7) << 29)
17475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
17476 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
17478 * Maximum BW allocated to CoS queue.
17479 * The HWRM will translate this value into byte counter and
17480 * time interval used for this COS inside the device.
17482 uint32_t queue_id7_max_bw;
17483 /* The bandwidth value. */
17484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
17485 UINT32_C(0xfffffff)
17486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
17488 /* The granularity of the value (bits or bytes). */
17489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
17490 UINT32_C(0x10000000)
17491 /* Value is in bits. */
17492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
17493 (UINT32_C(0x0) << 28)
17494 /* Value is in bytes. */
17495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
17496 (UINT32_C(0x1) << 28)
17497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
17498 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
17499 /* bw_value_unit is 3 b */
17500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
17501 UINT32_C(0xe0000000)
17502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
17504 /* Value is in Mb or MB (base 10). */
17505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
17506 (UINT32_C(0x0) << 29)
17507 /* Value is in Kb or KB (base 10). */
17508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
17509 (UINT32_C(0x2) << 29)
17510 /* Value is in bits or bytes. */
17511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
17512 (UINT32_C(0x4) << 29)
17513 /* Value is in Gb or GB (base 10). */
17514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
17515 (UINT32_C(0x6) << 29)
17516 /* Value is in 1/100th of a percentage of total bandwidth. */
17517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17518 (UINT32_C(0x1) << 29)
17520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
17521 (UINT32_C(0x7) << 29)
17522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
17523 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
17524 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17525 uint8_t queue_id7_tsa_assign;
17526 /* Strict Priority */
17527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
17529 /* Enhanced Transmission Selection */
17530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
17533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
17536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
17539 * Priority level for strict priority. Valid only when the
17540 * tsa_assign is 0 - Strict Priority (SP)
17541 * 0..7 - Valid values.
17542 * 8..255 - Reserved.
17544 uint8_t queue_id7_pri_lvl;
17546 * Weight used to allocate remaining BW for this COS after
17547 * servicing guaranteed bandwidths for all COS.
17549 uint8_t queue_id7_bw_weight;
17550 uint8_t unused_2[4];
17552 * This field is used in Output records to indicate that the output
17553 * is completely written to RAM. This field should be read as '1'
17554 * to indicate that the output has been completely written.
17555 * When writing a command completion or response to an internal processor,
17556 * the order of writes has to be such that this field is written last.
17559 } __attribute__((packed));
17561 /*************************
17562 * hwrm_queue_cos2bw_cfg *
17563 *************************/
17566 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
17567 struct hwrm_queue_cos2bw_cfg_input {
17568 /* The HWRM command request type. */
17571 * The completion ring to send the completion event on. This should
17572 * be the NQ ID returned from the `nq_alloc` HWRM command.
17574 uint16_t cmpl_ring;
17576 * The sequence ID is used by the driver for tracking multiple
17577 * commands. This ID is treated as opaque data by the firmware and
17578 * the value is returned in the `hwrm_resp_hdr` upon completion.
17582 * The target ID of the command:
17583 * * 0x0-0xFFF8 - The function ID
17584 * * 0xFFF8-0xFFFE - Reserved for internal processors
17587 uint16_t target_id;
17589 * A physical address pointer pointing to a host buffer that the
17590 * command's response data will be written. This can be either a host
17591 * physical address (HPA) or a guest physical address (GPA) and must
17592 * point to a physically contiguous block of memory.
17594 uint64_t resp_addr;
17598 * If this bit is set to 1, then all queue_id0 related
17599 * parameters in this command are valid.
17601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
17604 * If this bit is set to 1, then all queue_id1 related
17605 * parameters in this command are valid.
17607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
17610 * If this bit is set to 1, then all queue_id2 related
17611 * parameters in this command are valid.
17613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
17616 * If this bit is set to 1, then all queue_id3 related
17617 * parameters in this command are valid.
17619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
17622 * If this bit is set to 1, then all queue_id4 related
17623 * parameters in this command are valid.
17625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
17628 * If this bit is set to 1, then all queue_id5 related
17629 * parameters in this command are valid.
17631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
17634 * If this bit is set to 1, then all queue_id6 related
17635 * parameters in this command are valid.
17637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
17640 * If this bit is set to 1, then all queue_id7 related
17641 * parameters in this command are valid.
17643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
17646 * Port ID of port for which the table is being configured.
17647 * The HWRM needs to check whether this function is allowed
17648 * to configure TC BW assignment on this port.
17651 /* ID of CoS Queue 0. */
17655 * Minimum BW allocated to CoS Queue.
17656 * The HWRM will translate this value into byte counter and
17657 * time interval used for this COS inside the device.
17659 uint32_t queue_id0_min_bw;
17660 /* The bandwidth value. */
17661 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
17662 UINT32_C(0xfffffff)
17663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
17665 /* The granularity of the value (bits or bytes). */
17666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
17667 UINT32_C(0x10000000)
17668 /* Value is in bits. */
17669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
17670 (UINT32_C(0x0) << 28)
17671 /* Value is in bytes. */
17672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
17673 (UINT32_C(0x1) << 28)
17674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
17675 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
17676 /* bw_value_unit is 3 b */
17677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
17678 UINT32_C(0xe0000000)
17679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
17681 /* Value is in Mb or MB (base 10). */
17682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
17683 (UINT32_C(0x0) << 29)
17684 /* Value is in Kb or KB (base 10). */
17685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
17686 (UINT32_C(0x2) << 29)
17687 /* Value is in bits or bytes. */
17688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
17689 (UINT32_C(0x4) << 29)
17690 /* Value is in Gb or GB (base 10). */
17691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
17692 (UINT32_C(0x6) << 29)
17693 /* Value is in 1/100th of a percentage of total bandwidth. */
17694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17695 (UINT32_C(0x1) << 29)
17697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
17698 (UINT32_C(0x7) << 29)
17699 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
17700 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
17702 * Maximum BW allocated to CoS Queue.
17703 * The HWRM will translate this value into byte counter and
17704 * time interval used for this COS inside the device.
17706 uint32_t queue_id0_max_bw;
17707 /* The bandwidth value. */
17708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
17709 UINT32_C(0xfffffff)
17710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
17712 /* The granularity of the value (bits or bytes). */
17713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
17714 UINT32_C(0x10000000)
17715 /* Value is in bits. */
17716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
17717 (UINT32_C(0x0) << 28)
17718 /* Value is in bytes. */
17719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
17720 (UINT32_C(0x1) << 28)
17721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
17722 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
17723 /* bw_value_unit is 3 b */
17724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
17725 UINT32_C(0xe0000000)
17726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
17728 /* Value is in Mb or MB (base 10). */
17729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
17730 (UINT32_C(0x0) << 29)
17731 /* Value is in Kb or KB (base 10). */
17732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
17733 (UINT32_C(0x2) << 29)
17734 /* Value is in bits or bytes. */
17735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
17736 (UINT32_C(0x4) << 29)
17737 /* Value is in Gb or GB (base 10). */
17738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
17739 (UINT32_C(0x6) << 29)
17740 /* Value is in 1/100th of a percentage of total bandwidth. */
17741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17742 (UINT32_C(0x1) << 29)
17744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
17745 (UINT32_C(0x7) << 29)
17746 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
17747 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
17748 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17749 uint8_t queue_id0_tsa_assign;
17750 /* Strict Priority */
17751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
17753 /* Enhanced Transmission Selection */
17754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
17757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
17760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
17763 * Priority level for strict priority. Valid only when the
17764 * tsa_assign is 0 - Strict Priority (SP)
17765 * 0..7 - Valid values.
17766 * 8..255 - Reserved.
17768 uint8_t queue_id0_pri_lvl;
17770 * Weight used to allocate remaining BW for this COS after
17771 * servicing guaranteed bandwidths for all COS.
17773 uint8_t queue_id0_bw_weight;
17774 /* ID of CoS Queue 1. */
17777 * Minimum BW allocated to CoS Queue.
17778 * The HWRM will translate this value into byte counter and
17779 * time interval used for this COS inside the device.
17781 uint32_t queue_id1_min_bw;
17782 /* The bandwidth value. */
17783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
17784 UINT32_C(0xfffffff)
17785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
17787 /* The granularity of the value (bits or bytes). */
17788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
17789 UINT32_C(0x10000000)
17790 /* Value is in bits. */
17791 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
17792 (UINT32_C(0x0) << 28)
17793 /* Value is in bytes. */
17794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
17795 (UINT32_C(0x1) << 28)
17796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
17797 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
17798 /* bw_value_unit is 3 b */
17799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
17800 UINT32_C(0xe0000000)
17801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
17803 /* Value is in Mb or MB (base 10). */
17804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
17805 (UINT32_C(0x0) << 29)
17806 /* Value is in Kb or KB (base 10). */
17807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
17808 (UINT32_C(0x2) << 29)
17809 /* Value is in bits or bytes. */
17810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
17811 (UINT32_C(0x4) << 29)
17812 /* Value is in Gb or GB (base 10). */
17813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
17814 (UINT32_C(0x6) << 29)
17815 /* Value is in 1/100th of a percentage of total bandwidth. */
17816 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17817 (UINT32_C(0x1) << 29)
17819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
17820 (UINT32_C(0x7) << 29)
17821 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
17822 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
17824 * Maximum BW allocated to CoS queue.
17825 * The HWRM will translate this value into byte counter and
17826 * time interval used for this COS inside the device.
17828 uint32_t queue_id1_max_bw;
17829 /* The bandwidth value. */
17830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
17831 UINT32_C(0xfffffff)
17832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
17834 /* The granularity of the value (bits or bytes). */
17835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
17836 UINT32_C(0x10000000)
17837 /* Value is in bits. */
17838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
17839 (UINT32_C(0x0) << 28)
17840 /* Value is in bytes. */
17841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
17842 (UINT32_C(0x1) << 28)
17843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
17844 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
17845 /* bw_value_unit is 3 b */
17846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
17847 UINT32_C(0xe0000000)
17848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
17850 /* Value is in Mb or MB (base 10). */
17851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
17852 (UINT32_C(0x0) << 29)
17853 /* Value is in Kb or KB (base 10). */
17854 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
17855 (UINT32_C(0x2) << 29)
17856 /* Value is in bits or bytes. */
17857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
17858 (UINT32_C(0x4) << 29)
17859 /* Value is in Gb or GB (base 10). */
17860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
17861 (UINT32_C(0x6) << 29)
17862 /* Value is in 1/100th of a percentage of total bandwidth. */
17863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17864 (UINT32_C(0x1) << 29)
17866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
17867 (UINT32_C(0x7) << 29)
17868 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
17869 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
17870 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17871 uint8_t queue_id1_tsa_assign;
17872 /* Strict Priority */
17873 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
17875 /* Enhanced Transmission Selection */
17876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
17879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
17882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
17885 * Priority level for strict priority. Valid only when the
17886 * tsa_assign is 0 - Strict Priority (SP)
17887 * 0..7 - Valid values.
17888 * 8..255 - Reserved.
17890 uint8_t queue_id1_pri_lvl;
17892 * Weight used to allocate remaining BW for this COS after
17893 * servicing guaranteed bandwidths for all COS.
17895 uint8_t queue_id1_bw_weight;
17896 /* ID of CoS Queue 2. */
17899 * Minimum BW allocated to CoS Queue.
17900 * The HWRM will translate this value into byte counter and
17901 * time interval used for this COS inside the device.
17903 uint32_t queue_id2_min_bw;
17904 /* The bandwidth value. */
17905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
17906 UINT32_C(0xfffffff)
17907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
17909 /* The granularity of the value (bits or bytes). */
17910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
17911 UINT32_C(0x10000000)
17912 /* Value is in bits. */
17913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
17914 (UINT32_C(0x0) << 28)
17915 /* Value is in bytes. */
17916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
17917 (UINT32_C(0x1) << 28)
17918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
17919 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
17920 /* bw_value_unit is 3 b */
17921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
17922 UINT32_C(0xe0000000)
17923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
17925 /* Value is in Mb or MB (base 10). */
17926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
17927 (UINT32_C(0x0) << 29)
17928 /* Value is in Kb or KB (base 10). */
17929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
17930 (UINT32_C(0x2) << 29)
17931 /* Value is in bits or bytes. */
17932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
17933 (UINT32_C(0x4) << 29)
17934 /* Value is in Gb or GB (base 10). */
17935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
17936 (UINT32_C(0x6) << 29)
17937 /* Value is in 1/100th of a percentage of total bandwidth. */
17938 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17939 (UINT32_C(0x1) << 29)
17941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
17942 (UINT32_C(0x7) << 29)
17943 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
17944 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
17946 * Maximum BW allocated to CoS queue.
17947 * The HWRM will translate this value into byte counter and
17948 * time interval used for this COS inside the device.
17950 uint32_t queue_id2_max_bw;
17951 /* The bandwidth value. */
17952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
17953 UINT32_C(0xfffffff)
17954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
17956 /* The granularity of the value (bits or bytes). */
17957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
17958 UINT32_C(0x10000000)
17959 /* Value is in bits. */
17960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
17961 (UINT32_C(0x0) << 28)
17962 /* Value is in bytes. */
17963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
17964 (UINT32_C(0x1) << 28)
17965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
17966 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
17967 /* bw_value_unit is 3 b */
17968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
17969 UINT32_C(0xe0000000)
17970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
17972 /* Value is in Mb or MB (base 10). */
17973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
17974 (UINT32_C(0x0) << 29)
17975 /* Value is in Kb or KB (base 10). */
17976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
17977 (UINT32_C(0x2) << 29)
17978 /* Value is in bits or bytes. */
17979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
17980 (UINT32_C(0x4) << 29)
17981 /* Value is in Gb or GB (base 10). */
17982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
17983 (UINT32_C(0x6) << 29)
17984 /* Value is in 1/100th of a percentage of total bandwidth. */
17985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17986 (UINT32_C(0x1) << 29)
17988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
17989 (UINT32_C(0x7) << 29)
17990 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
17991 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
17992 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17993 uint8_t queue_id2_tsa_assign;
17994 /* Strict Priority */
17995 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
17997 /* Enhanced Transmission Selection */
17998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
18001 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
18004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
18007 * Priority level for strict priority. Valid only when the
18008 * tsa_assign is 0 - Strict Priority (SP)
18009 * 0..7 - Valid values.
18010 * 8..255 - Reserved.
18012 uint8_t queue_id2_pri_lvl;
18014 * Weight used to allocate remaining BW for this COS after
18015 * servicing guaranteed bandwidths for all COS.
18017 uint8_t queue_id2_bw_weight;
18018 /* ID of CoS Queue 3. */
18021 * Minimum BW allocated to CoS Queue.
18022 * The HWRM will translate this value into byte counter and
18023 * time interval used for this COS inside the device.
18025 uint32_t queue_id3_min_bw;
18026 /* The bandwidth value. */
18027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
18028 UINT32_C(0xfffffff)
18029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
18031 /* The granularity of the value (bits or bytes). */
18032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
18033 UINT32_C(0x10000000)
18034 /* Value is in bits. */
18035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
18036 (UINT32_C(0x0) << 28)
18037 /* Value is in bytes. */
18038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
18039 (UINT32_C(0x1) << 28)
18040 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
18041 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
18042 /* bw_value_unit is 3 b */
18043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
18044 UINT32_C(0xe0000000)
18045 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
18047 /* Value is in Mb or MB (base 10). */
18048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
18049 (UINT32_C(0x0) << 29)
18050 /* Value is in Kb or KB (base 10). */
18051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
18052 (UINT32_C(0x2) << 29)
18053 /* Value is in bits or bytes. */
18054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
18055 (UINT32_C(0x4) << 29)
18056 /* Value is in Gb or GB (base 10). */
18057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
18058 (UINT32_C(0x6) << 29)
18059 /* Value is in 1/100th of a percentage of total bandwidth. */
18060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18061 (UINT32_C(0x1) << 29)
18063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
18064 (UINT32_C(0x7) << 29)
18065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
18066 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
18068 * Maximum BW allocated to CoS queue.
18069 * The HWRM will translate this value into byte counter and
18070 * time interval used for this COS inside the device.
18072 uint32_t queue_id3_max_bw;
18073 /* The bandwidth value. */
18074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
18075 UINT32_C(0xfffffff)
18076 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
18078 /* The granularity of the value (bits or bytes). */
18079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
18080 UINT32_C(0x10000000)
18081 /* Value is in bits. */
18082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
18083 (UINT32_C(0x0) << 28)
18084 /* Value is in bytes. */
18085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
18086 (UINT32_C(0x1) << 28)
18087 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
18088 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
18089 /* bw_value_unit is 3 b */
18090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
18091 UINT32_C(0xe0000000)
18092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
18094 /* Value is in Mb or MB (base 10). */
18095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
18096 (UINT32_C(0x0) << 29)
18097 /* Value is in Kb or KB (base 10). */
18098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
18099 (UINT32_C(0x2) << 29)
18100 /* Value is in bits or bytes. */
18101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
18102 (UINT32_C(0x4) << 29)
18103 /* Value is in Gb or GB (base 10). */
18104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
18105 (UINT32_C(0x6) << 29)
18106 /* Value is in 1/100th of a percentage of total bandwidth. */
18107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18108 (UINT32_C(0x1) << 29)
18110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
18111 (UINT32_C(0x7) << 29)
18112 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
18113 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
18114 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18115 uint8_t queue_id3_tsa_assign;
18116 /* Strict Priority */
18117 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
18119 /* Enhanced Transmission Selection */
18120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
18123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
18126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
18129 * Priority level for strict priority. Valid only when the
18130 * tsa_assign is 0 - Strict Priority (SP)
18131 * 0..7 - Valid values.
18132 * 8..255 - Reserved.
18134 uint8_t queue_id3_pri_lvl;
18136 * Weight used to allocate remaining BW for this COS after
18137 * servicing guaranteed bandwidths for all COS.
18139 uint8_t queue_id3_bw_weight;
18140 /* ID of CoS Queue 4. */
18143 * Minimum BW allocated to CoS Queue.
18144 * The HWRM will translate this value into byte counter and
18145 * time interval used for this COS inside the device.
18147 uint32_t queue_id4_min_bw;
18148 /* The bandwidth value. */
18149 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
18150 UINT32_C(0xfffffff)
18151 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
18153 /* The granularity of the value (bits or bytes). */
18154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
18155 UINT32_C(0x10000000)
18156 /* Value is in bits. */
18157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
18158 (UINT32_C(0x0) << 28)
18159 /* Value is in bytes. */
18160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
18161 (UINT32_C(0x1) << 28)
18162 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
18163 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
18164 /* bw_value_unit is 3 b */
18165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
18166 UINT32_C(0xe0000000)
18167 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
18169 /* Value is in Mb or MB (base 10). */
18170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
18171 (UINT32_C(0x0) << 29)
18172 /* Value is in Kb or KB (base 10). */
18173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
18174 (UINT32_C(0x2) << 29)
18175 /* Value is in bits or bytes. */
18176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
18177 (UINT32_C(0x4) << 29)
18178 /* Value is in Gb or GB (base 10). */
18179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
18180 (UINT32_C(0x6) << 29)
18181 /* Value is in 1/100th of a percentage of total bandwidth. */
18182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18183 (UINT32_C(0x1) << 29)
18185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
18186 (UINT32_C(0x7) << 29)
18187 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
18188 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
18190 * Maximum BW allocated to CoS queue.
18191 * The HWRM will translate this value into byte counter and
18192 * time interval used for this COS inside the device.
18194 uint32_t queue_id4_max_bw;
18195 /* The bandwidth value. */
18196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
18197 UINT32_C(0xfffffff)
18198 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
18200 /* The granularity of the value (bits or bytes). */
18201 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
18202 UINT32_C(0x10000000)
18203 /* Value is in bits. */
18204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
18205 (UINT32_C(0x0) << 28)
18206 /* Value is in bytes. */
18207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
18208 (UINT32_C(0x1) << 28)
18209 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
18210 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
18211 /* bw_value_unit is 3 b */
18212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
18213 UINT32_C(0xe0000000)
18214 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
18216 /* Value is in Mb or MB (base 10). */
18217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
18218 (UINT32_C(0x0) << 29)
18219 /* Value is in Kb or KB (base 10). */
18220 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
18221 (UINT32_C(0x2) << 29)
18222 /* Value is in bits or bytes. */
18223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
18224 (UINT32_C(0x4) << 29)
18225 /* Value is in Gb or GB (base 10). */
18226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
18227 (UINT32_C(0x6) << 29)
18228 /* Value is in 1/100th of a percentage of total bandwidth. */
18229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18230 (UINT32_C(0x1) << 29)
18232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
18233 (UINT32_C(0x7) << 29)
18234 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
18235 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
18236 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18237 uint8_t queue_id4_tsa_assign;
18238 /* Strict Priority */
18239 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
18241 /* Enhanced Transmission Selection */
18242 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
18245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
18248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
18251 * Priority level for strict priority. Valid only when the
18252 * tsa_assign is 0 - Strict Priority (SP)
18253 * 0..7 - Valid values.
18254 * 8..255 - Reserved.
18256 uint8_t queue_id4_pri_lvl;
18258 * Weight used to allocate remaining BW for this COS after
18259 * servicing guaranteed bandwidths for all COS.
18261 uint8_t queue_id4_bw_weight;
18262 /* ID of CoS Queue 5. */
18265 * Minimum BW allocated to CoS Queue.
18266 * The HWRM will translate this value into byte counter and
18267 * time interval used for this COS inside the device.
18269 uint32_t queue_id5_min_bw;
18270 /* The bandwidth value. */
18271 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
18272 UINT32_C(0xfffffff)
18273 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
18275 /* The granularity of the value (bits or bytes). */
18276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
18277 UINT32_C(0x10000000)
18278 /* Value is in bits. */
18279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
18280 (UINT32_C(0x0) << 28)
18281 /* Value is in bytes. */
18282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
18283 (UINT32_C(0x1) << 28)
18284 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
18285 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
18286 /* bw_value_unit is 3 b */
18287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
18288 UINT32_C(0xe0000000)
18289 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
18291 /* Value is in Mb or MB (base 10). */
18292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
18293 (UINT32_C(0x0) << 29)
18294 /* Value is in Kb or KB (base 10). */
18295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
18296 (UINT32_C(0x2) << 29)
18297 /* Value is in bits or bytes. */
18298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
18299 (UINT32_C(0x4) << 29)
18300 /* Value is in Gb or GB (base 10). */
18301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
18302 (UINT32_C(0x6) << 29)
18303 /* Value is in 1/100th of a percentage of total bandwidth. */
18304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18305 (UINT32_C(0x1) << 29)
18307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
18308 (UINT32_C(0x7) << 29)
18309 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
18310 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
18312 * Maximum BW allocated to CoS queue.
18313 * The HWRM will translate this value into byte counter and
18314 * time interval used for this COS inside the device.
18316 uint32_t queue_id5_max_bw;
18317 /* The bandwidth value. */
18318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
18319 UINT32_C(0xfffffff)
18320 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
18322 /* The granularity of the value (bits or bytes). */
18323 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
18324 UINT32_C(0x10000000)
18325 /* Value is in bits. */
18326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
18327 (UINT32_C(0x0) << 28)
18328 /* Value is in bytes. */
18329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
18330 (UINT32_C(0x1) << 28)
18331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
18332 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
18333 /* bw_value_unit is 3 b */
18334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
18335 UINT32_C(0xe0000000)
18336 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
18338 /* Value is in Mb or MB (base 10). */
18339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
18340 (UINT32_C(0x0) << 29)
18341 /* Value is in Kb or KB (base 10). */
18342 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
18343 (UINT32_C(0x2) << 29)
18344 /* Value is in bits or bytes. */
18345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
18346 (UINT32_C(0x4) << 29)
18347 /* Value is in Gb or GB (base 10). */
18348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
18349 (UINT32_C(0x6) << 29)
18350 /* Value is in 1/100th of a percentage of total bandwidth. */
18351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18352 (UINT32_C(0x1) << 29)
18354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
18355 (UINT32_C(0x7) << 29)
18356 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
18357 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
18358 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18359 uint8_t queue_id5_tsa_assign;
18360 /* Strict Priority */
18361 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
18363 /* Enhanced Transmission Selection */
18364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
18367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
18370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
18373 * Priority level for strict priority. Valid only when the
18374 * tsa_assign is 0 - Strict Priority (SP)
18375 * 0..7 - Valid values.
18376 * 8..255 - Reserved.
18378 uint8_t queue_id5_pri_lvl;
18380 * Weight used to allocate remaining BW for this COS after
18381 * servicing guaranteed bandwidths for all COS.
18383 uint8_t queue_id5_bw_weight;
18384 /* ID of CoS Queue 6. */
18387 * Minimum BW allocated to CoS Queue.
18388 * The HWRM will translate this value into byte counter and
18389 * time interval used for this COS inside the device.
18391 uint32_t queue_id6_min_bw;
18392 /* The bandwidth value. */
18393 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
18394 UINT32_C(0xfffffff)
18395 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
18397 /* The granularity of the value (bits or bytes). */
18398 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
18399 UINT32_C(0x10000000)
18400 /* Value is in bits. */
18401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
18402 (UINT32_C(0x0) << 28)
18403 /* Value is in bytes. */
18404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
18405 (UINT32_C(0x1) << 28)
18406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
18407 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
18408 /* bw_value_unit is 3 b */
18409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
18410 UINT32_C(0xe0000000)
18411 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
18413 /* Value is in Mb or MB (base 10). */
18414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
18415 (UINT32_C(0x0) << 29)
18416 /* Value is in Kb or KB (base 10). */
18417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
18418 (UINT32_C(0x2) << 29)
18419 /* Value is in bits or bytes. */
18420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
18421 (UINT32_C(0x4) << 29)
18422 /* Value is in Gb or GB (base 10). */
18423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
18424 (UINT32_C(0x6) << 29)
18425 /* Value is in 1/100th of a percentage of total bandwidth. */
18426 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18427 (UINT32_C(0x1) << 29)
18429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
18430 (UINT32_C(0x7) << 29)
18431 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
18432 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
18434 * Maximum BW allocated to CoS queue.
18435 * The HWRM will translate this value into byte counter and
18436 * time interval used for this COS inside the device.
18438 uint32_t queue_id6_max_bw;
18439 /* The bandwidth value. */
18440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
18441 UINT32_C(0xfffffff)
18442 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
18444 /* The granularity of the value (bits or bytes). */
18445 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
18446 UINT32_C(0x10000000)
18447 /* Value is in bits. */
18448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
18449 (UINT32_C(0x0) << 28)
18450 /* Value is in bytes. */
18451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
18452 (UINT32_C(0x1) << 28)
18453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
18454 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
18455 /* bw_value_unit is 3 b */
18456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
18457 UINT32_C(0xe0000000)
18458 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
18460 /* Value is in Mb or MB (base 10). */
18461 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
18462 (UINT32_C(0x0) << 29)
18463 /* Value is in Kb or KB (base 10). */
18464 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
18465 (UINT32_C(0x2) << 29)
18466 /* Value is in bits or bytes. */
18467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
18468 (UINT32_C(0x4) << 29)
18469 /* Value is in Gb or GB (base 10). */
18470 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
18471 (UINT32_C(0x6) << 29)
18472 /* Value is in 1/100th of a percentage of total bandwidth. */
18473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18474 (UINT32_C(0x1) << 29)
18476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
18477 (UINT32_C(0x7) << 29)
18478 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
18479 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
18480 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18481 uint8_t queue_id6_tsa_assign;
18482 /* Strict Priority */
18483 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
18485 /* Enhanced Transmission Selection */
18486 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
18489 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
18492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
18495 * Priority level for strict priority. Valid only when the
18496 * tsa_assign is 0 - Strict Priority (SP)
18497 * 0..7 - Valid values.
18498 * 8..255 - Reserved.
18500 uint8_t queue_id6_pri_lvl;
18502 * Weight used to allocate remaining BW for this COS after
18503 * servicing guaranteed bandwidths for all COS.
18505 uint8_t queue_id6_bw_weight;
18506 /* ID of CoS Queue 7. */
18509 * Minimum BW allocated to CoS Queue.
18510 * The HWRM will translate this value into byte counter and
18511 * time interval used for this COS inside the device.
18513 uint32_t queue_id7_min_bw;
18514 /* The bandwidth value. */
18515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
18516 UINT32_C(0xfffffff)
18517 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
18519 /* The granularity of the value (bits or bytes). */
18520 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
18521 UINT32_C(0x10000000)
18522 /* Value is in bits. */
18523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
18524 (UINT32_C(0x0) << 28)
18525 /* Value is in bytes. */
18526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
18527 (UINT32_C(0x1) << 28)
18528 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
18529 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
18530 /* bw_value_unit is 3 b */
18531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
18532 UINT32_C(0xe0000000)
18533 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
18535 /* Value is in Mb or MB (base 10). */
18536 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
18537 (UINT32_C(0x0) << 29)
18538 /* Value is in Kb or KB (base 10). */
18539 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
18540 (UINT32_C(0x2) << 29)
18541 /* Value is in bits or bytes. */
18542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
18543 (UINT32_C(0x4) << 29)
18544 /* Value is in Gb or GB (base 10). */
18545 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
18546 (UINT32_C(0x6) << 29)
18547 /* Value is in 1/100th of a percentage of total bandwidth. */
18548 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18549 (UINT32_C(0x1) << 29)
18551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
18552 (UINT32_C(0x7) << 29)
18553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
18554 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
18556 * Maximum BW allocated to CoS queue.
18557 * The HWRM will translate this value into byte counter and
18558 * time interval used for this COS inside the device.
18560 uint32_t queue_id7_max_bw;
18561 /* The bandwidth value. */
18562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
18563 UINT32_C(0xfffffff)
18564 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
18566 /* The granularity of the value (bits or bytes). */
18567 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
18568 UINT32_C(0x10000000)
18569 /* Value is in bits. */
18570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
18571 (UINT32_C(0x0) << 28)
18572 /* Value is in bytes. */
18573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
18574 (UINT32_C(0x1) << 28)
18575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
18576 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
18577 /* bw_value_unit is 3 b */
18578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
18579 UINT32_C(0xe0000000)
18580 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
18582 /* Value is in Mb or MB (base 10). */
18583 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
18584 (UINT32_C(0x0) << 29)
18585 /* Value is in Kb or KB (base 10). */
18586 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
18587 (UINT32_C(0x2) << 29)
18588 /* Value is in bits or bytes. */
18589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
18590 (UINT32_C(0x4) << 29)
18591 /* Value is in Gb or GB (base 10). */
18592 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
18593 (UINT32_C(0x6) << 29)
18594 /* Value is in 1/100th of a percentage of total bandwidth. */
18595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18596 (UINT32_C(0x1) << 29)
18598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
18599 (UINT32_C(0x7) << 29)
18600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
18601 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
18602 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18603 uint8_t queue_id7_tsa_assign;
18604 /* Strict Priority */
18605 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
18607 /* Enhanced Transmission Selection */
18608 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
18611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
18614 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
18617 * Priority level for strict priority. Valid only when the
18618 * tsa_assign is 0 - Strict Priority (SP)
18619 * 0..7 - Valid values.
18620 * 8..255 - Reserved.
18622 uint8_t queue_id7_pri_lvl;
18624 * Weight used to allocate remaining BW for this COS after
18625 * servicing guaranteed bandwidths for all COS.
18627 uint8_t queue_id7_bw_weight;
18628 uint8_t unused_1[5];
18629 } __attribute__((packed));
18631 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
18632 struct hwrm_queue_cos2bw_cfg_output {
18633 /* The specific error status for the command. */
18634 uint16_t error_code;
18635 /* The HWRM command request type. */
18637 /* The sequence ID from the original command. */
18639 /* The length of the response data in number of bytes. */
18641 uint8_t unused_0[7];
18643 * This field is used in Output records to indicate that the output
18644 * is completely written to RAM. This field should be read as '1'
18645 * to indicate that the output has been completely written.
18646 * When writing a command completion or response to an internal processor,
18647 * the order of writes has to be such that this field is written last.
18650 } __attribute__((packed));
18652 /*******************
18653 * hwrm_vnic_alloc *
18654 *******************/
18657 /* hwrm_vnic_alloc_input (size:192b/24B) */
18658 struct hwrm_vnic_alloc_input {
18659 /* The HWRM command request type. */
18662 * The completion ring to send the completion event on. This should
18663 * be the NQ ID returned from the `nq_alloc` HWRM command.
18665 uint16_t cmpl_ring;
18667 * The sequence ID is used by the driver for tracking multiple
18668 * commands. This ID is treated as opaque data by the firmware and
18669 * the value is returned in the `hwrm_resp_hdr` upon completion.
18673 * The target ID of the command:
18674 * * 0x0-0xFFF8 - The function ID
18675 * * 0xFFF8-0xFFFE - Reserved for internal processors
18678 uint16_t target_id;
18680 * A physical address pointer pointing to a host buffer that the
18681 * command's response data will be written. This can be either a host
18682 * physical address (HPA) or a guest physical address (GPA) and must
18683 * point to a physically contiguous block of memory.
18685 uint64_t resp_addr;
18688 * When this bit is '1', this VNIC is requested to
18689 * be the default VNIC for this function.
18691 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
18692 uint8_t unused_0[4];
18693 } __attribute__((packed));
18695 /* hwrm_vnic_alloc_output (size:128b/16B) */
18696 struct hwrm_vnic_alloc_output {
18697 /* The specific error status for the command. */
18698 uint16_t error_code;
18699 /* The HWRM command request type. */
18701 /* The sequence ID from the original command. */
18703 /* The length of the response data in number of bytes. */
18705 /* Logical vnic ID */
18707 uint8_t unused_0[3];
18709 * This field is used in Output records to indicate that the output
18710 * is completely written to RAM. This field should be read as '1'
18711 * to indicate that the output has been completely written.
18712 * When writing a command completion or response to an internal processor,
18713 * the order of writes has to be such that this field is written last.
18716 } __attribute__((packed));
18718 /******************
18720 ******************/
18723 /* hwrm_vnic_free_input (size:192b/24B) */
18724 struct hwrm_vnic_free_input {
18725 /* The HWRM command request type. */
18728 * The completion ring to send the completion event on. This should
18729 * be the NQ ID returned from the `nq_alloc` HWRM command.
18731 uint16_t cmpl_ring;
18733 * The sequence ID is used by the driver for tracking multiple
18734 * commands. This ID is treated as opaque data by the firmware and
18735 * the value is returned in the `hwrm_resp_hdr` upon completion.
18739 * The target ID of the command:
18740 * * 0x0-0xFFF8 - The function ID
18741 * * 0xFFF8-0xFFFE - Reserved for internal processors
18744 uint16_t target_id;
18746 * A physical address pointer pointing to a host buffer that the
18747 * command's response data will be written. This can be either a host
18748 * physical address (HPA) or a guest physical address (GPA) and must
18749 * point to a physically contiguous block of memory.
18751 uint64_t resp_addr;
18752 /* Logical vnic ID */
18754 uint8_t unused_0[4];
18755 } __attribute__((packed));
18757 /* hwrm_vnic_free_output (size:128b/16B) */
18758 struct hwrm_vnic_free_output {
18759 /* The specific error status for the command. */
18760 uint16_t error_code;
18761 /* The HWRM command request type. */
18763 /* The sequence ID from the original command. */
18765 /* The length of the response data in number of bytes. */
18767 uint8_t unused_0[7];
18769 * This field is used in Output records to indicate that the output
18770 * is completely written to RAM. This field should be read as '1'
18771 * to indicate that the output has been completely written.
18772 * When writing a command completion or response to an internal processor,
18773 * the order of writes has to be such that this field is written last.
18776 } __attribute__((packed));
18783 /* hwrm_vnic_cfg_input (size:320b/40B) */
18784 struct hwrm_vnic_cfg_input {
18785 /* The HWRM command request type. */
18788 * The completion ring to send the completion event on. This should
18789 * be the NQ ID returned from the `nq_alloc` HWRM command.
18791 uint16_t cmpl_ring;
18793 * The sequence ID is used by the driver for tracking multiple
18794 * commands. This ID is treated as opaque data by the firmware and
18795 * the value is returned in the `hwrm_resp_hdr` upon completion.
18799 * The target ID of the command:
18800 * * 0x0-0xFFF8 - The function ID
18801 * * 0xFFF8-0xFFFE - Reserved for internal processors
18804 uint16_t target_id;
18806 * A physical address pointer pointing to a host buffer that the
18807 * command's response data will be written. This can be either a host
18808 * physical address (HPA) or a guest physical address (GPA) and must
18809 * point to a physically contiguous block of memory.
18811 uint64_t resp_addr;
18814 * When this bit is '1', the VNIC is requested to
18815 * be the default VNIC for the function.
18817 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
18820 * When this bit is '1', the VNIC is being configured to
18821 * strip VLAN in the RX path.
18822 * If set to '0', then VLAN stripping is disabled on
18825 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
18828 * When this bit is '1', the VNIC is being configured to
18829 * buffer receive packets in the hardware until the host
18830 * posts new receive buffers.
18831 * If set to '0', then bd_stall is being configured to be
18832 * disabled on this VNIC.
18834 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
18837 * When this bit is '1', the VNIC is being configured to
18838 * receive both RoCE and non-RoCE traffic.
18839 * If set to '0', then this VNIC is not configured to be
18840 * operating in dual VNIC mode.
18842 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
18845 * When this flag is set to '1', the VNIC is requested to
18846 * be configured to receive only RoCE traffic.
18847 * If this flag is set to '0', then this flag shall be
18848 * ignored by the HWRM.
18849 * If roce_dual_vnic_mode flag is set to '1'
18850 * or roce_mirroring_capable_vnic_mode flag to 1,
18851 * then the HWRM client shall not set this flag to '1'.
18853 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
18856 * When a VNIC uses one destination ring group for certain
18857 * application (e.g. Receive Flow Steering) where
18858 * exact match is used to direct packets to a VNIC with one
18859 * destination ring group only, there is no need to configure
18860 * RSS indirection table for that VNIC as only one destination
18861 * ring group is used.
18863 * This flag is used to enable a mode where
18864 * RSS is enabled in the VNIC using a RSS context
18865 * for computing RSS hash but the RSS indirection table is
18866 * not configured using hwrm_vnic_rss_cfg.
18868 * If this mode is enabled, then the driver should not program
18869 * RSS indirection table for the RSS context that is used for
18870 * computing RSS hash only.
18872 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
18875 * When this bit is '1', the VNIC is being configured to
18876 * receive both RoCE and non-RoCE traffic, but forward only the
18877 * RoCE traffic further. Also, RoCE traffic can be mirrored to
18880 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
18884 * This bit must be '1' for the dflt_ring_grp field to be
18887 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
18890 * This bit must be '1' for the rss_rule field to be
18893 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
18896 * This bit must be '1' for the cos_rule field to be
18899 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
18902 * This bit must be '1' for the lb_rule field to be
18905 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
18908 * This bit must be '1' for the mru field to be
18911 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
18914 * This bit must be '1' for the default_rx_ring_id field to be
18917 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
18920 * This bit must be '1' for the default_cmpl_ring_id field to be
18923 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
18925 /* Logical vnic ID */
18928 * Default Completion ring for the VNIC. This ring will
18929 * be chosen if packet does not match any RSS rules and if
18930 * there is no COS rule.
18932 uint16_t dflt_ring_grp;
18934 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
18935 * there is no RSS rule.
18939 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
18940 * there is no COS rule.
18944 * RSS ID for load balancing rule/table structure.
18945 * 0xFF... (All Fs) if there is no LB rule.
18949 * The maximum receive unit of the vnic.
18950 * Each vnic is associated with a function.
18951 * The vnic mru value overwrites the mru setting of the
18952 * associated function.
18953 * The HWRM shall make sure that vnic mru does not exceed
18954 * the mru of the port the function is associated with.
18958 * Default Rx ring for the VNIC. This ring will
18959 * be chosen if packet does not match any RSS rules.
18960 * The aggregation ring associated with the Rx ring is
18961 * implied based on the Rx ring specified when the
18962 * aggregation ring was allocated.
18964 uint16_t default_rx_ring_id;
18966 * Default completion ring for the VNIC. This ring will
18967 * be chosen if packet does not match any RSS rules.
18969 uint16_t default_cmpl_ring_id;
18970 } __attribute__((packed));
18972 /* hwrm_vnic_cfg_output (size:128b/16B) */
18973 struct hwrm_vnic_cfg_output {
18974 /* The specific error status for the command. */
18975 uint16_t error_code;
18976 /* The HWRM command request type. */
18978 /* The sequence ID from the original command. */
18980 /* The length of the response data in number of bytes. */
18982 uint8_t unused_0[7];
18984 * This field is used in Output records to indicate that the output
18985 * is completely written to RAM. This field should be read as '1'
18986 * to indicate that the output has been completely written.
18987 * When writing a command completion or response to an internal processor,
18988 * the order of writes has to be such that this field is written last.
18991 } __attribute__((packed));
18993 /******************
18995 ******************/
18998 /* hwrm_vnic_qcfg_input (size:256b/32B) */
18999 struct hwrm_vnic_qcfg_input {
19000 /* The HWRM command request type. */
19003 * The completion ring to send the completion event on. This should
19004 * be the NQ ID returned from the `nq_alloc` HWRM command.
19006 uint16_t cmpl_ring;
19008 * The sequence ID is used by the driver for tracking multiple
19009 * commands. This ID is treated as opaque data by the firmware and
19010 * the value is returned in the `hwrm_resp_hdr` upon completion.
19014 * The target ID of the command:
19015 * * 0x0-0xFFF8 - The function ID
19016 * * 0xFFF8-0xFFFE - Reserved for internal processors
19019 uint16_t target_id;
19021 * A physical address pointer pointing to a host buffer that the
19022 * command's response data will be written. This can be either a host
19023 * physical address (HPA) or a guest physical address (GPA) and must
19024 * point to a physically contiguous block of memory.
19026 uint64_t resp_addr;
19029 * This bit must be '1' for the vf_id_valid field to be
19032 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
19033 /* Logical vnic ID */
19035 /* ID of Virtual Function whose VNIC resource is being queried. */
19037 uint8_t unused_0[6];
19038 } __attribute__((packed));
19040 /* hwrm_vnic_qcfg_output (size:256b/32B) */
19041 struct hwrm_vnic_qcfg_output {
19042 /* The specific error status for the command. */
19043 uint16_t error_code;
19044 /* The HWRM command request type. */
19046 /* The sequence ID from the original command. */
19048 /* The length of the response data in number of bytes. */
19050 /* Default Completion ring for the VNIC. */
19051 uint16_t dflt_ring_grp;
19053 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
19054 * there is no RSS rule.
19058 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
19059 * there is no COS rule.
19063 * RSS ID for load balancing rule/table structure.
19064 * 0xFF... (All Fs) if there is no LB rule.
19067 /* The maximum receive unit of the vnic. */
19069 uint8_t unused_0[2];
19072 * When this bit is '1', the VNIC is the default VNIC for
19075 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
19078 * When this bit is '1', the VNIC is configured to
19079 * strip VLAN in the RX path.
19080 * If set to '0', then VLAN stripping is disabled on
19083 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
19086 * When this bit is '1', the VNIC is configured to
19087 * buffer receive packets in the hardware until the host
19088 * posts new receive buffers.
19089 * If set to '0', then bd_stall is disabled on
19092 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
19095 * When this bit is '1', the VNIC is configured to
19096 * receive both RoCE and non-RoCE traffic.
19097 * If set to '0', then this VNIC is not configured to
19098 * operate in dual VNIC mode.
19100 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
19103 * When this flag is set to '1', the VNIC is configured to
19104 * receive only RoCE traffic.
19105 * When this flag is set to '0', the VNIC is not configured
19106 * to receive only RoCE traffic.
19107 * If roce_dual_vnic_mode flag and this flag both are set
19108 * to '1', then it is an invalid configuration of the
19109 * VNIC. The HWRM should not allow that type of
19110 * mis-configuration by HWRM clients.
19112 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
19115 * When a VNIC uses one destination ring group for certain
19116 * application (e.g. Receive Flow Steering) where
19117 * exact match is used to direct packets to a VNIC with one
19118 * destination ring group only, there is no need to configure
19119 * RSS indirection table for that VNIC as only one destination
19120 * ring group is used.
19122 * When this bit is set to '1', then the VNIC is enabled in a
19123 * mode where RSS is enabled in the VNIC using a RSS context
19124 * for computing RSS hash but the RSS indirection table is
19127 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
19130 * When this bit is '1', the VNIC is configured to
19131 * receive both RoCE and non-RoCE traffic, but forward only
19132 * RoCE traffic further. Also RoCE traffic can be mirrored to
19135 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
19137 uint8_t unused_1[7];
19139 * This field is used in Output records to indicate that the output
19140 * is completely written to RAM. This field should be read as '1'
19141 * to indicate that the output has been completely written.
19142 * When writing a command completion or response to an internal processor,
19143 * the order of writes has to be such that this field is written last.
19146 } __attribute__((packed));
19148 /*******************
19149 * hwrm_vnic_qcaps *
19150 *******************/
19153 /* hwrm_vnic_qcaps_input (size:192b/24B) */
19154 struct hwrm_vnic_qcaps_input {
19155 /* The HWRM command request type. */
19158 * The completion ring to send the completion event on. This should
19159 * be the NQ ID returned from the `nq_alloc` HWRM command.
19161 uint16_t cmpl_ring;
19163 * The sequence ID is used by the driver for tracking multiple
19164 * commands. This ID is treated as opaque data by the firmware and
19165 * the value is returned in the `hwrm_resp_hdr` upon completion.
19169 * The target ID of the command:
19170 * * 0x0-0xFFF8 - The function ID
19171 * * 0xFFF8-0xFFFE - Reserved for internal processors
19174 uint16_t target_id;
19176 * A physical address pointer pointing to a host buffer that the
19177 * command's response data will be written. This can be either a host
19178 * physical address (HPA) or a guest physical address (GPA) and must
19179 * point to a physically contiguous block of memory.
19181 uint64_t resp_addr;
19183 uint8_t unused_0[4];
19184 } __attribute__((packed));
19186 /* hwrm_vnic_qcaps_output (size:192b/24B) */
19187 struct hwrm_vnic_qcaps_output {
19188 /* The specific error status for the command. */
19189 uint16_t error_code;
19190 /* The HWRM command request type. */
19192 /* The sequence ID from the original command. */
19194 /* The length of the response data in number of bytes. */
19196 /* The maximum receive unit that is settable on a vnic. */
19198 uint8_t unused_0[2];
19201 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
19204 * When this bit is '1', the capability of stripping VLAN in
19205 * the RX path is supported on VNIC(s).
19206 * If set to '0', then VLAN stripping capability is
19207 * not supported on VNIC(s).
19209 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
19212 * When this bit is '1', the capability to buffer receive
19213 * packets in the hardware until the host posts new receive buffers
19214 * is supported on VNIC(s).
19215 * If set to '0', then bd_stall capability is not supported
19218 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
19221 * When this bit is '1', the capability to
19222 * receive both RoCE and non-RoCE traffic on VNIC(s) is
19224 * If set to '0', then the capability to receive
19225 * both RoCE and non-RoCE traffic on VNIC(s) is
19228 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
19231 * When this bit is set to '1', the capability to configure
19232 * a VNIC to receive only RoCE traffic is supported.
19233 * When this flag is set to '0', the VNIC capability to
19234 * configure to receive only RoCE traffic is not supported.
19236 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
19239 * When this bit is set to '1', then the capability to enable
19240 * a VNIC in a mode where RSS context without configuring
19241 * RSS indirection table is supported (for RSS hash computation).
19242 * When this bit is set to '0', then a VNIC can not be configured
19243 * with a mode to enable RSS context without configuring RSS
19244 * indirection table.
19246 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
19249 * When this bit is '1', the capability to
19250 * mirror the the RoCE traffic is supported.
19251 * If set to '0', then the capability to mirror the
19252 * RoCE traffic is not supported.
19254 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
19257 * When this bit is '1', the outermost RSS hashing capability
19258 * is supported. If set to '0', then the outermost RSS hashing
19259 * capability is not supported.
19261 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
19263 uint8_t unused_1[7];
19265 * This field is used in Output records to indicate that the output
19266 * is completely written to RAM. This field should be read as '1'
19267 * to indicate that the output has been completely written.
19268 * When writing a command completion or response to an internal processor,
19269 * the order of writes has to be such that this field is written last.
19272 } __attribute__((packed));
19274 /*********************
19275 * hwrm_vnic_tpa_cfg *
19276 *********************/
19279 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
19280 struct hwrm_vnic_tpa_cfg_input {
19281 /* The HWRM command request type. */
19284 * The completion ring to send the completion event on. This should
19285 * be the NQ ID returned from the `nq_alloc` HWRM command.
19287 uint16_t cmpl_ring;
19289 * The sequence ID is used by the driver for tracking multiple
19290 * commands. This ID is treated as opaque data by the firmware and
19291 * the value is returned in the `hwrm_resp_hdr` upon completion.
19295 * The target ID of the command:
19296 * * 0x0-0xFFF8 - The function ID
19297 * * 0xFFF8-0xFFFE - Reserved for internal processors
19300 uint16_t target_id;
19302 * A physical address pointer pointing to a host buffer that the
19303 * command's response data will be written. This can be either a host
19304 * physical address (HPA) or a guest physical address (GPA) and must
19305 * point to a physically contiguous block of memory.
19307 uint64_t resp_addr;
19310 * When this bit is '1', the VNIC shall be configured to
19311 * perform transparent packet aggregation (TPA) of
19312 * non-tunneled TCP packets.
19314 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
19317 * When this bit is '1', the VNIC shall be configured to
19318 * perform transparent packet aggregation (TPA) of
19319 * tunneled TCP packets.
19321 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
19324 * When this bit is '1', the VNIC shall be configured to
19325 * perform transparent packet aggregation (TPA) according
19326 * to Windows Receive Segment Coalescing (RSC) rules.
19328 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
19331 * When this bit is '1', the VNIC shall be configured to
19332 * perform transparent packet aggregation (TPA) according
19333 * to Linux Generic Receive Offload (GRO) rules.
19335 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
19338 * When this bit is '1', the VNIC shall be configured to
19339 * perform transparent packet aggregation (TPA) for TCP
19340 * packets with IP ECN set to non-zero.
19342 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
19345 * When this bit is '1', the VNIC shall be configured to
19346 * perform transparent packet aggregation (TPA) for
19347 * GRE tunneled TCP packets only if all packets have the
19348 * same GRE sequence.
19350 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
19353 * When this bit is '1' and the GRO mode is enabled,
19354 * the VNIC shall be configured to
19355 * perform transparent packet aggregation (TPA) for
19356 * TCP/IPv4 packets with consecutively increasing IPIDs.
19357 * In other words, the last packet that is being
19358 * aggregated to an already existing aggregation context
19359 * shall have IPID 1 more than the IPID of the last packet
19360 * that was aggregated in that aggregation context.
19362 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
19365 * When this bit is '1' and the GRO mode is enabled,
19366 * the VNIC shall be configured to
19367 * perform transparent packet aggregation (TPA) for
19368 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
19371 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
19375 * This bit must be '1' for the max_agg_segs field to be
19378 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
19380 * This bit must be '1' for the max_aggs field to be
19383 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
19385 * This bit must be '1' for the max_agg_timer field to be
19388 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
19390 * This bit must be '1' for the min_agg_len field to be
19393 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
19394 /* Logical vnic ID */
19397 * This is the maximum number of TCP segments that can
19398 * be aggregated (unit is Log2). Max value is 31.
19400 uint16_t max_agg_segs;
19402 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
19404 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
19406 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
19408 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
19409 /* Any segment size larger than this is not valid */
19410 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
19411 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
19412 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
19414 * This is the maximum number of aggregations this VNIC is
19415 * allowed (unit is Log2). Max value is 7
19418 /* 1 aggregation */
19419 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
19420 /* 2 aggregations */
19421 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
19422 /* 4 aggregations */
19423 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
19424 /* 8 aggregations */
19425 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
19426 /* 16 aggregations */
19427 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
19428 /* Any aggregation size larger than this is not valid */
19429 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
19430 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
19431 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
19432 uint8_t unused_0[2];
19434 * This is the maximum amount of time allowed for
19435 * an aggregation context to complete after it was initiated.
19437 uint32_t max_agg_timer;
19439 * This is the minimum amount of payload length required to
19440 * start an aggregation context.
19442 uint32_t min_agg_len;
19443 } __attribute__((packed));
19445 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
19446 struct hwrm_vnic_tpa_cfg_output {
19447 /* The specific error status for the command. */
19448 uint16_t error_code;
19449 /* The HWRM command request type. */
19451 /* The sequence ID from the original command. */
19453 /* The length of the response data in number of bytes. */
19455 uint8_t unused_0[7];
19457 * This field is used in Output records to indicate that the output
19458 * is completely written to RAM. This field should be read as '1'
19459 * to indicate that the output has been completely written.
19460 * When writing a command completion or response to an internal processor,
19461 * the order of writes has to be such that this field is written last.
19464 } __attribute__((packed));
19466 /*********************
19467 * hwrm_vnic_rss_cfg *
19468 *********************/
19471 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
19472 struct hwrm_vnic_rss_cfg_input {
19473 /* The HWRM command request type. */
19476 * The completion ring to send the completion event on. This should
19477 * be the NQ ID returned from the `nq_alloc` HWRM command.
19479 uint16_t cmpl_ring;
19481 * The sequence ID is used by the driver for tracking multiple
19482 * commands. This ID is treated as opaque data by the firmware and
19483 * the value is returned in the `hwrm_resp_hdr` upon completion.
19487 * The target ID of the command:
19488 * * 0x0-0xFFF8 - The function ID
19489 * * 0xFFF8-0xFFFE - Reserved for internal processors
19492 uint16_t target_id;
19494 * A physical address pointer pointing to a host buffer that the
19495 * command's response data will be written. This can be either a host
19496 * physical address (HPA) or a guest physical address (GPA) and must
19497 * point to a physically contiguous block of memory.
19499 uint64_t resp_addr;
19500 uint32_t hash_type;
19502 * When this bit is '1', the RSS hash shall be computed
19503 * over source and destination IPv4 addresses of IPv4
19506 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19508 * When this bit is '1', the RSS hash shall be computed
19509 * over source/destination IPv4 addresses and
19510 * source/destination ports of TCP/IPv4 packets.
19512 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19514 * When this bit is '1', the RSS hash shall be computed
19515 * over source/destination IPv4 addresses and
19516 * source/destination ports of UDP/IPv4 packets.
19518 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19520 * When this bit is '1', the RSS hash shall be computed
19521 * over source and destination IPv4 addresses of IPv6
19524 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19526 * When this bit is '1', the RSS hash shall be computed
19527 * over source/destination IPv6 addresses and
19528 * source/destination ports of TCP/IPv6 packets.
19530 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19532 * When this bit is '1', the RSS hash shall be computed
19533 * over source/destination IPv6 addresses and
19534 * source/destination ports of UDP/IPv6 packets.
19536 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19537 /* VNIC ID of VNIC associated with RSS table being configured. */
19540 * Specifies which VNIC ring table pair to configure.
19541 * Valid values range from 0 to 7.
19543 uint8_t ring_table_pair_index;
19544 /* Flags to specify different RSS hash modes. */
19545 uint8_t hash_mode_flags;
19547 * When this bit is '1', it indicates using current RSS
19548 * hash mode setting configured in the device.
19550 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
19553 * When this bit is '1', it indicates requesting support of
19554 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19555 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19556 * packets, the RSS hash is computed over the normal
19557 * src/dest l3 and src/dest l4 headers.
19559 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19562 * When this bit is '1', it indicates requesting support of
19563 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19564 * tunnel packets. For none-tunnel packets, the RSS hash is
19565 * computed over the normal src/dest l3 headers.
19567 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19570 * When this bit is '1', it indicates requesting support of
19571 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19572 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19573 * packets, the RSS hash is computed over the normal
19574 * src/dest l3 and src/dest l4 headers.
19576 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19579 * When this bit is '1', it indicates requesting support of
19580 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19581 * tunnel packets. For none-tunnel packets, the RSS hash is
19582 * computed over the normal src/dest l3 headers.
19584 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19586 /* This is the address for rss ring group table */
19587 uint64_t ring_grp_tbl_addr;
19588 /* This is the address for rss hash key table */
19589 uint64_t hash_key_tbl_addr;
19590 /* Index to the rss indirection table. */
19591 uint16_t rss_ctx_idx;
19592 uint8_t unused_1[6];
19593 } __attribute__((packed));
19595 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
19596 struct hwrm_vnic_rss_cfg_output {
19597 /* The specific error status for the command. */
19598 uint16_t error_code;
19599 /* The HWRM command request type. */
19601 /* The sequence ID from the original command. */
19603 /* The length of the response data in number of bytes. */
19605 uint8_t unused_0[7];
19607 * This field is used in Output records to indicate that the output
19608 * is completely written to RAM. This field should be read as '1'
19609 * to indicate that the output has been completely written.
19610 * When writing a command completion or response to an internal processor,
19611 * the order of writes has to be such that this field is written last.
19614 } __attribute__((packed));
19616 /**********************
19617 * hwrm_vnic_rss_qcfg *
19618 **********************/
19621 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
19622 struct hwrm_vnic_rss_qcfg_input {
19623 /* The HWRM command request type. */
19626 * The completion ring to send the completion event on. This should
19627 * be the NQ ID returned from the `nq_alloc` HWRM command.
19629 uint16_t cmpl_ring;
19631 * The sequence ID is used by the driver for tracking multiple
19632 * commands. This ID is treated as opaque data by the firmware and
19633 * the value is returned in the `hwrm_resp_hdr` upon completion.
19637 * The target ID of the command:
19638 * * 0x0-0xFFF8 - The function ID
19639 * * 0xFFF8-0xFFFE - Reserved for internal processors
19642 uint16_t target_id;
19644 * A physical address pointer pointing to a host buffer that the
19645 * command's response data will be written. This can be either a host
19646 * physical address (HPA) or a guest physical address (GPA) and must
19647 * point to a physically contiguous block of memory.
19649 uint64_t resp_addr;
19650 /* Index to the rss indirection table. */
19651 uint16_t rss_ctx_idx;
19652 uint8_t unused_0[6];
19653 } __attribute__((packed));
19655 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
19656 struct hwrm_vnic_rss_qcfg_output {
19657 /* The specific error status for the command. */
19658 uint16_t error_code;
19659 /* The HWRM command request type. */
19661 /* The sequence ID from the original command. */
19663 /* The length of the response data in number of bytes. */
19665 uint32_t hash_type;
19667 * When this bit is '1', the RSS hash shall be computed
19668 * over source and destination IPv4 addresses of IPv4
19671 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19673 * When this bit is '1', the RSS hash shall be computed
19674 * over source/destination IPv4 addresses and
19675 * source/destination ports of TCP/IPv4 packets.
19677 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19679 * When this bit is '1', the RSS hash shall be computed
19680 * over source/destination IPv4 addresses and
19681 * source/destination ports of UDP/IPv4 packets.
19683 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19685 * When this bit is '1', the RSS hash shall be computed
19686 * over source and destination IPv4 addresses of IPv6
19689 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19691 * When this bit is '1', the RSS hash shall be computed
19692 * over source/destination IPv6 addresses and
19693 * source/destination ports of TCP/IPv6 packets.
19695 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19697 * When this bit is '1', the RSS hash shall be computed
19698 * over source/destination IPv6 addresses and
19699 * source/destination ports of UDP/IPv6 packets.
19701 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19702 uint8_t unused_0[4];
19703 /* This is the value of rss hash key */
19704 uint32_t hash_key[10];
19705 /* Flags to specify different RSS hash modes. */
19706 uint8_t hash_mode_flags;
19708 * When this bit is '1', it indicates using current RSS
19709 * hash mode setting configured in the device.
19711 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
19714 * When this bit is '1', it indicates requesting support of
19715 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19716 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19717 * packets, the RSS hash is computed over the normal
19718 * src/dest l3 and src/dest l4 headers.
19720 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19723 * When this bit is '1', it indicates requesting support of
19724 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19725 * tunnel packets. For none-tunnel packets, the RSS hash is
19726 * computed over the normal src/dest l3 headers.
19728 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19731 * When this bit is '1', it indicates requesting support of
19732 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19733 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19734 * packets, the RSS hash is computed over the normal
19735 * src/dest l3 and src/dest l4 headers.
19737 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19740 * When this bit is '1', it indicates requesting support of
19741 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19742 * tunnel packets. For none-tunnel packets, the RSS hash is
19743 * computed over the normal src/dest l3 headers.
19745 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19747 uint8_t unused_1[6];
19749 * This field is used in Output records to indicate that the output
19750 * is completely written to RAM. This field should be read as '1'
19751 * to indicate that the output has been completely written.
19752 * When writing a command completion or response to an internal processor,
19753 * the order of writes has to be such that this field is written last.
19756 } __attribute__((packed));
19758 /**************************
19759 * hwrm_vnic_plcmodes_cfg *
19760 **************************/
19763 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
19764 struct hwrm_vnic_plcmodes_cfg_input {
19765 /* The HWRM command request type. */
19768 * The completion ring to send the completion event on. This should
19769 * be the NQ ID returned from the `nq_alloc` HWRM command.
19771 uint16_t cmpl_ring;
19773 * The sequence ID is used by the driver for tracking multiple
19774 * commands. This ID is treated as opaque data by the firmware and
19775 * the value is returned in the `hwrm_resp_hdr` upon completion.
19779 * The target ID of the command:
19780 * * 0x0-0xFFF8 - The function ID
19781 * * 0xFFF8-0xFFFE - Reserved for internal processors
19784 uint16_t target_id;
19786 * A physical address pointer pointing to a host buffer that the
19787 * command's response data will be written. This can be either a host
19788 * physical address (HPA) or a guest physical address (GPA) and must
19789 * point to a physically contiguous block of memory.
19791 uint64_t resp_addr;
19794 * When this bit is '1', the VNIC shall be configured to
19795 * use regular placement algorithm.
19796 * By default, the regular placement algorithm shall be
19797 * enabled on the VNIC.
19799 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
19802 * When this bit is '1', the VNIC shall be configured
19803 * use the jumbo placement algorithm.
19805 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
19808 * When this bit is '1', the VNIC shall be configured
19809 * to enable Header-Data split for IPv4 packets according
19810 * to the following rules:
19811 * # If the packet is identified as TCP/IPv4, then the
19812 * packet is split at the beginning of the TCP payload.
19813 * # If the packet is identified as UDP/IPv4, then the
19814 * packet is split at the beginning of UDP payload.
19815 * # If the packet is identified as non-TCP and non-UDP
19816 * IPv4 packet, then the packet is split at the beginning
19817 * of the upper layer protocol header carried in the IPv4
19820 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
19823 * When this bit is '1', the VNIC shall be configured
19824 * to enable Header-Data split for IPv6 packets according
19825 * to the following rules:
19826 * # If the packet is identified as TCP/IPv6, then the
19827 * packet is split at the beginning of the TCP payload.
19828 * # If the packet is identified as UDP/IPv6, then the
19829 * packet is split at the beginning of UDP payload.
19830 * # If the packet is identified as non-TCP and non-UDP
19831 * IPv6 packet, then the packet is split at the beginning
19832 * of the upper layer protocol header carried in the IPv6
19835 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
19838 * When this bit is '1', the VNIC shall be configured
19839 * to enable Header-Data split for FCoE packets at the
19840 * beginning of FC payload.
19842 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
19845 * When this bit is '1', the VNIC shall be configured
19846 * to enable Header-Data split for RoCE packets at the
19847 * beginning of RoCE payload (after BTH/GRH headers).
19849 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
19853 * This bit must be '1' for the jumbo_thresh_valid field to be
19856 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
19859 * This bit must be '1' for the hds_offset_valid field to be
19862 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
19865 * This bit must be '1' for the hds_threshold_valid field to be
19868 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
19870 /* Logical vnic ID */
19873 * When jumbo placement algorithm is enabled, this value
19874 * is used to determine the threshold for jumbo placement.
19875 * Packets with length larger than this value will be
19876 * placed according to the jumbo placement algorithm.
19878 uint16_t jumbo_thresh;
19880 * This value is used to determine the offset into
19881 * packet buffer where the split data (payload) will be
19882 * placed according to one of of HDS placement algorithm.
19884 * The lengths of packet buffers provided for split data
19885 * shall be larger than this value.
19887 uint16_t hds_offset;
19889 * When one of the HDS placement algorithm is enabled, this
19890 * value is used to determine the threshold for HDS
19892 * Packets with length larger than this value will be
19893 * placed according to the HDS placement algorithm.
19894 * This value shall be in multiple of 4 bytes.
19896 uint16_t hds_threshold;
19897 uint8_t unused_0[6];
19898 } __attribute__((packed));
19900 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
19901 struct hwrm_vnic_plcmodes_cfg_output {
19902 /* The specific error status for the command. */
19903 uint16_t error_code;
19904 /* The HWRM command request type. */
19906 /* The sequence ID from the original command. */
19908 /* The length of the response data in number of bytes. */
19910 uint8_t unused_0[7];
19912 * This field is used in Output records to indicate that the output
19913 * is completely written to RAM. This field should be read as '1'
19914 * to indicate that the output has been completely written.
19915 * When writing a command completion or response to an internal processor,
19916 * the order of writes has to be such that this field is written last.
19919 } __attribute__((packed));
19921 /***************************
19922 * hwrm_vnic_plcmodes_qcfg *
19923 ***************************/
19926 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
19927 struct hwrm_vnic_plcmodes_qcfg_input {
19928 /* The HWRM command request type. */
19931 * The completion ring to send the completion event on. This should
19932 * be the NQ ID returned from the `nq_alloc` HWRM command.
19934 uint16_t cmpl_ring;
19936 * The sequence ID is used by the driver for tracking multiple
19937 * commands. This ID is treated as opaque data by the firmware and
19938 * the value is returned in the `hwrm_resp_hdr` upon completion.
19942 * The target ID of the command:
19943 * * 0x0-0xFFF8 - The function ID
19944 * * 0xFFF8-0xFFFE - Reserved for internal processors
19947 uint16_t target_id;
19949 * A physical address pointer pointing to a host buffer that the
19950 * command's response data will be written. This can be either a host
19951 * physical address (HPA) or a guest physical address (GPA) and must
19952 * point to a physically contiguous block of memory.
19954 uint64_t resp_addr;
19955 /* Logical vnic ID */
19957 uint8_t unused_0[4];
19958 } __attribute__((packed));
19960 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
19961 struct hwrm_vnic_plcmodes_qcfg_output {
19962 /* The specific error status for the command. */
19963 uint16_t error_code;
19964 /* The HWRM command request type. */
19966 /* The sequence ID from the original command. */
19968 /* The length of the response data in number of bytes. */
19972 * When this bit is '1', the VNIC is configured to
19973 * use regular placement algorithm.
19975 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
19978 * When this bit is '1', the VNIC is configured to
19979 * use the jumbo placement algorithm.
19981 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
19984 * When this bit is '1', the VNIC is configured
19985 * to enable Header-Data split for IPv4 packets.
19987 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
19990 * When this bit is '1', the VNIC is configured
19991 * to enable Header-Data split for IPv6 packets.
19993 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
19996 * When this bit is '1', the VNIC is configured
19997 * to enable Header-Data split for FCoE packets.
19999 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
20002 * When this bit is '1', the VNIC is configured
20003 * to enable Header-Data split for RoCE packets.
20005 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
20008 * When this bit is '1', the VNIC is configured
20009 * to be the default VNIC of the requesting function.
20011 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
20014 * When jumbo placement algorithm is enabled, this value
20015 * is used to determine the threshold for jumbo placement.
20016 * Packets with length larger than this value will be
20017 * placed according to the jumbo placement algorithm.
20019 uint16_t jumbo_thresh;
20021 * This value is used to determine the offset into
20022 * packet buffer where the split data (payload) will be
20023 * placed according to one of of HDS placement algorithm.
20025 * The lengths of packet buffers provided for split data
20026 * shall be larger than this value.
20028 uint16_t hds_offset;
20030 * When one of the HDS placement algorithm is enabled, this
20031 * value is used to determine the threshold for HDS
20033 * Packets with length larger than this value will be
20034 * placed according to the HDS placement algorithm.
20035 * This value shall be in multiple of 4 bytes.
20037 uint16_t hds_threshold;
20038 uint8_t unused_0[5];
20040 * This field is used in Output records to indicate that the output
20041 * is completely written to RAM. This field should be read as '1'
20042 * to indicate that the output has been completely written.
20043 * When writing a command completion or response to an internal processor,
20044 * the order of writes has to be such that this field is written last.
20047 } __attribute__((packed));
20049 /**********************************
20050 * hwrm_vnic_rss_cos_lb_ctx_alloc *
20051 **********************************/
20054 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
20055 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
20056 /* The HWRM command request type. */
20059 * The completion ring to send the completion event on. This should
20060 * be the NQ ID returned from the `nq_alloc` HWRM command.
20062 uint16_t cmpl_ring;
20064 * The sequence ID is used by the driver for tracking multiple
20065 * commands. This ID is treated as opaque data by the firmware and
20066 * the value is returned in the `hwrm_resp_hdr` upon completion.
20070 * The target ID of the command:
20071 * * 0x0-0xFFF8 - The function ID
20072 * * 0xFFF8-0xFFFE - Reserved for internal processors
20075 uint16_t target_id;
20077 * A physical address pointer pointing to a host buffer that the
20078 * command's response data will be written. This can be either a host
20079 * physical address (HPA) or a guest physical address (GPA) and must
20080 * point to a physically contiguous block of memory.
20082 uint64_t resp_addr;
20083 } __attribute__((packed));
20085 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
20086 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
20087 /* The specific error status for the command. */
20088 uint16_t error_code;
20089 /* The HWRM command request type. */
20091 /* The sequence ID from the original command. */
20093 /* The length of the response data in number of bytes. */
20095 /* rss_cos_lb_ctx_id is 16 b */
20096 uint16_t rss_cos_lb_ctx_id;
20097 uint8_t unused_0[5];
20099 * This field is used in Output records to indicate that the output
20100 * is completely written to RAM. This field should be read as '1'
20101 * to indicate that the output has been completely written.
20102 * When writing a command completion or response to an internal processor,
20103 * the order of writes has to be such that this field is written last.
20106 } __attribute__((packed));
20108 /*********************************
20109 * hwrm_vnic_rss_cos_lb_ctx_free *
20110 *********************************/
20113 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
20114 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
20115 /* The HWRM command request type. */
20118 * The completion ring to send the completion event on. This should
20119 * be the NQ ID returned from the `nq_alloc` HWRM command.
20121 uint16_t cmpl_ring;
20123 * The sequence ID is used by the driver for tracking multiple
20124 * commands. This ID is treated as opaque data by the firmware and
20125 * the value is returned in the `hwrm_resp_hdr` upon completion.
20129 * The target ID of the command:
20130 * * 0x0-0xFFF8 - The function ID
20131 * * 0xFFF8-0xFFFE - Reserved for internal processors
20134 uint16_t target_id;
20136 * A physical address pointer pointing to a host buffer that the
20137 * command's response data will be written. This can be either a host
20138 * physical address (HPA) or a guest physical address (GPA) and must
20139 * point to a physically contiguous block of memory.
20141 uint64_t resp_addr;
20142 /* rss_cos_lb_ctx_id is 16 b */
20143 uint16_t rss_cos_lb_ctx_id;
20144 uint8_t unused_0[6];
20145 } __attribute__((packed));
20147 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
20148 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
20149 /* The specific error status for the command. */
20150 uint16_t error_code;
20151 /* The HWRM command request type. */
20153 /* The sequence ID from the original command. */
20155 /* The length of the response data in number of bytes. */
20157 uint8_t unused_0[7];
20159 * This field is used in Output records to indicate that the output
20160 * is completely written to RAM. This field should be read as '1'
20161 * to indicate that the output has been completely written.
20162 * When writing a command completion or response to an internal processor,
20163 * the order of writes has to be such that this field is written last.
20166 } __attribute__((packed));
20168 /*******************
20169 * hwrm_ring_alloc *
20170 *******************/
20173 /* hwrm_ring_alloc_input (size:704b/88B) */
20174 struct hwrm_ring_alloc_input {
20175 /* The HWRM command request type. */
20178 * The completion ring to send the completion event on. This should
20179 * be the NQ ID returned from the `nq_alloc` HWRM command.
20181 uint16_t cmpl_ring;
20183 * The sequence ID is used by the driver for tracking multiple
20184 * commands. This ID is treated as opaque data by the firmware and
20185 * the value is returned in the `hwrm_resp_hdr` upon completion.
20189 * The target ID of the command:
20190 * * 0x0-0xFFF8 - The function ID
20191 * * 0xFFF8-0xFFFE - Reserved for internal processors
20194 uint16_t target_id;
20196 * A physical address pointer pointing to a host buffer that the
20197 * command's response data will be written. This can be either a host
20198 * physical address (HPA) or a guest physical address (GPA) and must
20199 * point to a physically contiguous block of memory.
20201 uint64_t resp_addr;
20204 * This bit must be '1' for the ring_arb_cfg field to be
20207 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
20210 * This bit must be '1' for the stat_ctx_id_valid field to be
20213 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
20216 * This bit must be '1' for the max_bw_valid field to be
20219 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
20222 * This bit must be '1' for the rx_ring_id field to be
20225 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
20228 * This bit must be '1' for the nq_ring_id field to be
20231 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
20234 * This bit must be '1' for the rx_buf_size field to be
20237 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
20241 /* L2 Completion Ring (CR) */
20242 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
20244 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
20246 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
20247 /* RoCE Notification Completion Ring (ROCE_CR) */
20248 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
20249 /* RX Aggregation Ring */
20250 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
20251 /* Notification Queue */
20252 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
20253 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
20254 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
20256 /* Ring allocation flags. */
20259 * For Rx rings, the incoming packet data can be placed at either
20260 * a 0B or 2B offset from the start of the Rx packet buffer. When
20261 * '1', the received packet will be padded with 2B of zeros at the
20262 * front of the packet. Note that this flag is only used for
20263 * Rx rings and is ignored for all other rings included Rx
20264 * Aggregation rings.
20266 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
20268 * This value is a pointer to the page table for the
20271 uint64_t page_tbl_addr;
20272 /* First Byte Offset of the first entry in the first page. */
20275 * Actual page size in 2^page_size. The supported range is increments
20276 * in powers of 2 from 16 bytes to 1GB.
20278 * Page size is 16 B.
20280 * Page size is 4 KB.
20282 * Page size is 8 KB.
20284 * Page size is 64 KB.
20286 * Page size is 2 MB.
20288 * Page size is 4 MB.
20290 * Page size is 1 GB.
20294 * This value indicates the depth of page table.
20295 * For this version of the specification, value other than 0 or
20296 * 1 shall be considered as an invalid value.
20297 * When the page_tbl_depth = 0, then it is treated as a
20298 * special case with the following.
20299 * 1. FBO and page size fields are not valid.
20300 * 2. page_tbl_addr is the physical address of the first
20301 * element of the ring.
20303 uint8_t page_tbl_depth;
20304 uint8_t unused_1[2];
20306 * Number of 16B units in the ring. Minimum size for
20307 * a ring is 16 16B entries.
20311 * Logical ring number for the ring to be allocated.
20312 * This value determines the position in the doorbell
20313 * area where the update to the ring will be made.
20315 * For completion rings, this value is also the MSI-X
20316 * vector number for the function the completion ring is
20319 uint16_t logical_id;
20321 * This field is used only when ring_type is a TX ring.
20322 * This value indicates what completion ring the TX ring
20323 * is associated with.
20325 uint16_t cmpl_ring_id;
20327 * This field is used only when ring_type is a TX ring.
20328 * This value indicates what CoS queue the TX ring
20329 * is associated with.
20333 * When allocating a Rx ring or Rx aggregation ring, this field
20334 * specifies the size of the buffer descriptors posted to the ring.
20336 uint16_t rx_buf_size;
20338 * When allocating an Rx aggregation ring, this field
20339 * specifies the associated Rx ring ID.
20341 uint16_t rx_ring_id;
20343 * When allocating a completion ring, this field
20344 * specifies the associated NQ ring ID.
20346 uint16_t nq_ring_id;
20348 * This field is used only when ring_type is a TX ring.
20349 * This field is used to configure arbitration related
20350 * parameters for a TX ring.
20352 uint16_t ring_arb_cfg;
20353 /* Arbitration policy used for the ring. */
20354 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
20356 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
20358 * Use strict priority for the TX ring.
20359 * Priority value is specified in arb_policy_param
20361 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
20364 * Use weighted fair queue arbitration for the TX ring.
20365 * Weight is specified in arb_policy_param
20367 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
20369 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
20370 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
20371 /* Reserved field. */
20372 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
20374 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
20376 * Arbitration policy specific parameter.
20377 * # For strict priority arbitration policy, this field
20378 * represents a priority value. If set to 0, then the priority
20379 * is not specified and the HWRM is allowed to select
20380 * any priority for this TX ring.
20381 * # For weighted fair queue arbitration policy, this field
20382 * represents a weight value. If set to 0, then the weight
20383 * is not specified and the HWRM is allowed to select
20384 * any weight for this TX ring.
20386 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
20388 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
20391 * This field is reserved for the future use.
20392 * It shall be set to 0.
20394 uint32_t reserved3;
20396 * This field is used only when ring_type is a TX ring.
20397 * This input indicates what statistics context this ring
20398 * should be associated with.
20400 uint32_t stat_ctx_id;
20402 * This field is reserved for the future use.
20403 * It shall be set to 0.
20405 uint32_t reserved4;
20407 * This field is used only when ring_type is a TX ring
20408 * to specify maximum BW allocated to the TX ring.
20409 * The HWRM will translate this value into byte counter and
20410 * time interval used for this ring inside the device.
20413 /* The bandwidth value. */
20414 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
20415 UINT32_C(0xfffffff)
20416 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
20417 /* The granularity of the value (bits or bytes). */
20418 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
20419 UINT32_C(0x10000000)
20420 /* Value is in bits. */
20421 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
20422 (UINT32_C(0x0) << 28)
20423 /* Value is in bytes. */
20424 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
20425 (UINT32_C(0x1) << 28)
20426 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
20427 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
20428 /* bw_value_unit is 3 b */
20429 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
20430 UINT32_C(0xe0000000)
20431 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
20432 /* Value is in Mb or MB (base 10). */
20433 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
20434 (UINT32_C(0x0) << 29)
20435 /* Value is in Kb or KB (base 10). */
20436 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
20437 (UINT32_C(0x2) << 29)
20438 /* Value is in bits or bytes. */
20439 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
20440 (UINT32_C(0x4) << 29)
20441 /* Value is in Gb or GB (base 10). */
20442 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
20443 (UINT32_C(0x6) << 29)
20444 /* Value is in 1/100th of a percentage of total bandwidth. */
20445 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20446 (UINT32_C(0x1) << 29)
20448 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
20449 (UINT32_C(0x7) << 29)
20450 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
20451 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
20453 * This field is used only when ring_type is a Completion ring.
20454 * This value indicates what interrupt mode should be used
20455 * on this completion ring.
20456 * Note: In the legacy interrupt mode, no more than 16
20457 * completion rings are allowed.
20461 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
20463 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
20465 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
20466 /* No Interrupt - Polled mode */
20467 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
20468 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
20469 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
20470 uint8_t unused_4[3];
20472 * The cq_handle is specified when allocating a completion ring. For
20473 * devices that support NQs, this cq_handle will be included in the
20474 * NQE to specify which CQ should be read to retrieve the completion
20477 uint64_t cq_handle;
20478 } __attribute__((packed));
20480 /* hwrm_ring_alloc_output (size:128b/16B) */
20481 struct hwrm_ring_alloc_output {
20482 /* The specific error status for the command. */
20483 uint16_t error_code;
20484 /* The HWRM command request type. */
20486 /* The sequence ID from the original command. */
20488 /* The length of the response data in number of bytes. */
20491 * Physical number of ring allocated.
20492 * This value shall be unique for a ring type.
20495 /* Logical number of ring allocated. */
20496 uint16_t logical_ring_id;
20497 uint8_t unused_0[3];
20499 * This field is used in Output records to indicate that the output
20500 * is completely written to RAM. This field should be read as '1'
20501 * to indicate that the output has been completely written.
20502 * When writing a command completion or response to an internal processor,
20503 * the order of writes has to be such that this field is written last.
20506 } __attribute__((packed));
20508 /******************
20510 ******************/
20513 /* hwrm_ring_free_input (size:192b/24B) */
20514 struct hwrm_ring_free_input {
20515 /* The HWRM command request type. */
20518 * The completion ring to send the completion event on. This should
20519 * be the NQ ID returned from the `nq_alloc` HWRM command.
20521 uint16_t cmpl_ring;
20523 * The sequence ID is used by the driver for tracking multiple
20524 * commands. This ID is treated as opaque data by the firmware and
20525 * the value is returned in the `hwrm_resp_hdr` upon completion.
20529 * The target ID of the command:
20530 * * 0x0-0xFFF8 - The function ID
20531 * * 0xFFF8-0xFFFE - Reserved for internal processors
20534 uint16_t target_id;
20536 * A physical address pointer pointing to a host buffer that the
20537 * command's response data will be written. This can be either a host
20538 * physical address (HPA) or a guest physical address (GPA) and must
20539 * point to a physically contiguous block of memory.
20541 uint64_t resp_addr;
20544 /* L2 Completion Ring (CR) */
20545 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
20547 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
20549 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
20550 /* RoCE Notification Completion Ring (ROCE_CR) */
20551 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
20552 /* RX Aggregation Ring */
20553 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
20554 /* Notification Queue */
20555 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
20556 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
20557 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
20559 /* Physical number of ring allocated. */
20561 uint8_t unused_1[4];
20562 } __attribute__((packed));
20564 /* hwrm_ring_free_output (size:128b/16B) */
20565 struct hwrm_ring_free_output {
20566 /* The specific error status for the command. */
20567 uint16_t error_code;
20568 /* The HWRM command request type. */
20570 /* The sequence ID from the original command. */
20572 /* The length of the response data in number of bytes. */
20574 uint8_t unused_0[7];
20576 * This field is used in Output records to indicate that the output
20577 * is completely written to RAM. This field should be read as '1'
20578 * to indicate that the output has been completely written.
20579 * When writing a command completion or response to an internal processor,
20580 * the order of writes has to be such that this field is written last.
20583 } __attribute__((packed));
20585 /*******************
20586 * hwrm_ring_reset *
20587 *******************/
20590 /* hwrm_ring_reset_input (size:192b/24B) */
20591 struct hwrm_ring_reset_input {
20592 /* The HWRM command request type. */
20595 * The completion ring to send the completion event on. This should
20596 * be the NQ ID returned from the `nq_alloc` HWRM command.
20598 uint16_t cmpl_ring;
20600 * The sequence ID is used by the driver for tracking multiple
20601 * commands. This ID is treated as opaque data by the firmware and
20602 * the value is returned in the `hwrm_resp_hdr` upon completion.
20606 * The target ID of the command:
20607 * * 0x0-0xFFF8 - The function ID
20608 * * 0xFFF8-0xFFFE - Reserved for internal processors
20611 uint16_t target_id;
20613 * A physical address pointer pointing to a host buffer that the
20614 * command's response data will be written. This can be either a host
20615 * physical address (HPA) or a guest physical address (GPA) and must
20616 * point to a physically contiguous block of memory.
20618 uint64_t resp_addr;
20621 /* L2 Completion Ring (CR) */
20622 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
20624 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
20626 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
20627 /* RoCE Notification Completion Ring (ROCE_CR) */
20628 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
20629 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
20630 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
20632 /* Physical number of the ring. */
20634 uint8_t unused_1[4];
20635 } __attribute__((packed));
20637 /* hwrm_ring_reset_output (size:128b/16B) */
20638 struct hwrm_ring_reset_output {
20639 /* The specific error status for the command. */
20640 uint16_t error_code;
20641 /* The HWRM command request type. */
20643 /* The sequence ID from the original command. */
20645 /* The length of the response data in number of bytes. */
20647 uint8_t unused_0[7];
20649 * This field is used in Output records to indicate that the output
20650 * is completely written to RAM. This field should be read as '1'
20651 * to indicate that the output has been completely written.
20652 * When writing a command completion or response to an internal processor,
20653 * the order of writes has to be such that this field is written last.
20656 } __attribute__((packed));
20658 /**************************
20659 * hwrm_ring_aggint_qcaps *
20660 **************************/
20663 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
20664 struct hwrm_ring_aggint_qcaps_input {
20665 /* The HWRM command request type. */
20668 * The completion ring to send the completion event on. This should
20669 * be the NQ ID returned from the `nq_alloc` HWRM command.
20671 uint16_t cmpl_ring;
20673 * The sequence ID is used by the driver for tracking multiple
20674 * commands. This ID is treated as opaque data by the firmware and
20675 * the value is returned in the `hwrm_resp_hdr` upon completion.
20679 * The target ID of the command:
20680 * * 0x0-0xFFF8 - The function ID
20681 * * 0xFFF8-0xFFFE - Reserved for internal processors
20684 uint16_t target_id;
20686 * A physical address pointer pointing to a host buffer that the
20687 * command's response data will be written. This can be either a host
20688 * physical address (HPA) or a guest physical address (GPA) and must
20689 * point to a physically contiguous block of memory.
20691 uint64_t resp_addr;
20692 } __attribute__((packed));
20694 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
20695 struct hwrm_ring_aggint_qcaps_output {
20696 /* The specific error status for the command. */
20697 uint16_t error_code;
20698 /* The HWRM command request type. */
20700 /* The sequence ID from the original command. */
20702 /* The length of the response data in number of bytes. */
20704 uint32_t cmpl_params;
20706 * When this bit is set to '1', int_lat_tmr_min can be configured
20707 * on completion rings.
20709 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
20712 * When this bit is set to '1', int_lat_tmr_max can be configured
20713 * on completion rings.
20715 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
20718 * When this bit is set to '1', timer_reset can be enabled
20719 * on completion rings.
20721 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
20724 * When this bit is set to '1', ring_idle can be enabled
20725 * on completion rings.
20727 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
20730 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
20731 * on completion rings.
20733 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
20736 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
20737 * on completion rings.
20739 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
20742 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
20743 * on completion rings.
20745 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
20748 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
20749 * on completion rings.
20751 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
20754 * When this bit is set to '1', num_cmpl_aggr_int can be configured
20755 * on completion rings.
20757 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
20759 uint32_t nq_params;
20761 * When this bit is set to '1', int_lat_tmr_min can be configured
20762 * on notification queues.
20764 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
20766 /* Minimum value for num_cmpl_dma_aggr */
20767 uint16_t num_cmpl_dma_aggr_min;
20768 /* Maximum value for num_cmpl_dma_aggr */
20769 uint16_t num_cmpl_dma_aggr_max;
20770 /* Minimum value for num_cmpl_dma_aggr_during_int */
20771 uint16_t num_cmpl_dma_aggr_during_int_min;
20772 /* Maximum value for num_cmpl_dma_aggr_during_int */
20773 uint16_t num_cmpl_dma_aggr_during_int_max;
20774 /* Minimum value for cmpl_aggr_dma_tmr */
20775 uint16_t cmpl_aggr_dma_tmr_min;
20776 /* Maximum value for cmpl_aggr_dma_tmr */
20777 uint16_t cmpl_aggr_dma_tmr_max;
20778 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
20779 uint16_t cmpl_aggr_dma_tmr_during_int_min;
20780 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
20781 uint16_t cmpl_aggr_dma_tmr_during_int_max;
20782 /* Minimum value for int_lat_tmr_min */
20783 uint16_t int_lat_tmr_min_min;
20784 /* Maximum value for int_lat_tmr_min */
20785 uint16_t int_lat_tmr_min_max;
20786 /* Minimum value for int_lat_tmr_max */
20787 uint16_t int_lat_tmr_max_min;
20788 /* Maximum value for int_lat_tmr_max */
20789 uint16_t int_lat_tmr_max_max;
20790 /* Minimum value for num_cmpl_aggr_int */
20791 uint16_t num_cmpl_aggr_int_min;
20792 /* Maximum value for num_cmpl_aggr_int */
20793 uint16_t num_cmpl_aggr_int_max;
20794 /* The units for timer parameters, in nanoseconds. */
20795 uint16_t timer_units;
20796 uint8_t unused_0[1];
20798 * This field is used in Output records to indicate that the output
20799 * is completely written to RAM. This field should be read as '1'
20800 * to indicate that the output has been completely written.
20801 * When writing a command completion or response to an internal processor,
20802 * the order of writes has to be such that this field is written last.
20805 } __attribute__((packed));
20807 /**************************************
20808 * hwrm_ring_cmpl_ring_qaggint_params *
20809 **************************************/
20812 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
20813 struct hwrm_ring_cmpl_ring_qaggint_params_input {
20814 /* The HWRM command request type. */
20817 * The completion ring to send the completion event on. This should
20818 * be the NQ ID returned from the `nq_alloc` HWRM command.
20820 uint16_t cmpl_ring;
20822 * The sequence ID is used by the driver for tracking multiple
20823 * commands. This ID is treated as opaque data by the firmware and
20824 * the value is returned in the `hwrm_resp_hdr` upon completion.
20828 * The target ID of the command:
20829 * * 0x0-0xFFF8 - The function ID
20830 * * 0xFFF8-0xFFFE - Reserved for internal processors
20833 uint16_t target_id;
20835 * A physical address pointer pointing to a host buffer that the
20836 * command's response data will be written. This can be either a host
20837 * physical address (HPA) or a guest physical address (GPA) and must
20838 * point to a physically contiguous block of memory.
20840 uint64_t resp_addr;
20841 /* Physical number of completion ring. */
20843 uint8_t unused_0[6];
20844 } __attribute__((packed));
20846 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
20847 struct hwrm_ring_cmpl_ring_qaggint_params_output {
20848 /* The specific error status for the command. */
20849 uint16_t error_code;
20850 /* The HWRM command request type. */
20852 /* The sequence ID from the original command. */
20854 /* The length of the response data in number of bytes. */
20858 * When this bit is set to '1', interrupt max
20859 * timer is reset whenever a completion is received.
20861 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
20864 * When this bit is set to '1', ring idle mode
20865 * aggregation will be enabled.
20867 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
20870 * Number of completions to aggregate before DMA
20871 * during the normal mode.
20873 uint16_t num_cmpl_dma_aggr;
20875 * Number of completions to aggregate before DMA
20876 * during the interrupt mode.
20878 uint16_t num_cmpl_dma_aggr_during_int;
20880 * Timer in unit of 80-nsec used to aggregate completions before
20881 * DMA during the normal mode (not in interrupt mode).
20883 uint16_t cmpl_aggr_dma_tmr;
20885 * Timer in unit of 80-nsec used to aggregate completions before
20886 * DMA during the interrupt mode.
20888 uint16_t cmpl_aggr_dma_tmr_during_int;
20889 /* Minimum time (in unit of 80-nsec) between two interrupts. */
20890 uint16_t int_lat_tmr_min;
20892 * Maximum wait time (in unit of 80-nsec) spent aggregating
20893 * completions before signaling the interrupt after the
20894 * interrupt is enabled.
20896 uint16_t int_lat_tmr_max;
20898 * Minimum number of completions aggregated before signaling
20901 uint16_t num_cmpl_aggr_int;
20902 uint8_t unused_0[7];
20904 * This field is used in Output records to indicate that the output
20905 * is completely written to RAM. This field should be read as '1'
20906 * to indicate that the output has been completely written.
20907 * When writing a command completion or response to an internal processor,
20908 * the order of writes has to be such that this field is written last.
20911 } __attribute__((packed));
20913 /*****************************************
20914 * hwrm_ring_cmpl_ring_cfg_aggint_params *
20915 *****************************************/
20918 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
20919 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
20920 /* The HWRM command request type. */
20923 * The completion ring to send the completion event on. This should
20924 * be the NQ ID returned from the `nq_alloc` HWRM command.
20926 uint16_t cmpl_ring;
20928 * The sequence ID is used by the driver for tracking multiple
20929 * commands. This ID is treated as opaque data by the firmware and
20930 * the value is returned in the `hwrm_resp_hdr` upon completion.
20934 * The target ID of the command:
20935 * * 0x0-0xFFF8 - The function ID
20936 * * 0xFFF8-0xFFFE - Reserved for internal processors
20939 uint16_t target_id;
20941 * A physical address pointer pointing to a host buffer that the
20942 * command's response data will be written. This can be either a host
20943 * physical address (HPA) or a guest physical address (GPA) and must
20944 * point to a physically contiguous block of memory.
20946 uint64_t resp_addr;
20947 /* Physical number of completion ring. */
20951 * When this bit is set to '1', interrupt latency max
20952 * timer is reset whenever a completion is received.
20954 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
20957 * When this bit is set to '1', ring idle mode
20958 * aggregation will be enabled.
20960 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
20963 * Set this flag to 1 when configuring parameters on a
20964 * notification queue. Set this flag to 0 when configuring
20965 * parameters on a completion queue.
20967 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
20970 * Number of completions to aggregate before DMA
20971 * during the normal mode.
20973 uint16_t num_cmpl_dma_aggr;
20975 * Number of completions to aggregate before DMA
20976 * during the interrupt mode.
20978 uint16_t num_cmpl_dma_aggr_during_int;
20980 * Timer in unit of 80-nsec used to aggregate completions before
20981 * DMA during the normal mode (not in interrupt mode).
20983 uint16_t cmpl_aggr_dma_tmr;
20985 * Timer in unit of 80-nsec used to aggregate completions before
20986 * DMA during the interrupt mode.
20988 uint16_t cmpl_aggr_dma_tmr_during_int;
20989 /* Minimum time (in unit of 80-nsec) between two interrupts. */
20990 uint16_t int_lat_tmr_min;
20992 * Maximum wait time (in unit of 80-nsec) spent aggregating
20993 * cmpls before signaling the interrupt after the
20994 * interrupt is enabled.
20996 uint16_t int_lat_tmr_max;
20998 * Minimum number of completions aggregated before signaling
21001 uint16_t num_cmpl_aggr_int;
21003 * Bitfield that indicates which parameters are to be applied. Only
21004 * required when configuring devices with notification queues, and
21005 * used in that case to set certain parameters on completion queues
21006 * and others on notification queues.
21010 * This bit must be '1' for the num_cmpl_dma_aggr field to be
21013 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
21016 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
21019 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
21022 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
21025 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
21028 * This bit must be '1' for the int_lat_tmr_min field to be
21031 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
21034 * This bit must be '1' for the int_lat_tmr_max field to be
21037 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
21040 * This bit must be '1' for the num_cmpl_aggr_int field to be
21043 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
21045 uint8_t unused_0[4];
21046 } __attribute__((packed));
21048 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
21049 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
21050 /* The specific error status for the command. */
21051 uint16_t error_code;
21052 /* The HWRM command request type. */
21054 /* The sequence ID from the original command. */
21056 /* The length of the response data in number of bytes. */
21058 uint8_t unused_0[7];
21060 * This field is used in Output records to indicate that the output
21061 * is completely written to RAM. This field should be read as '1'
21062 * to indicate that the output has been completely written.
21063 * When writing a command completion or response to an internal processor,
21064 * the order of writes has to be such that this field is written last.
21067 } __attribute__((packed));
21069 /***********************
21070 * hwrm_ring_grp_alloc *
21071 ***********************/
21074 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
21075 struct hwrm_ring_grp_alloc_input {
21076 /* The HWRM command request type. */
21079 * The completion ring to send the completion event on. This should
21080 * be the NQ ID returned from the `nq_alloc` HWRM command.
21082 uint16_t cmpl_ring;
21084 * The sequence ID is used by the driver for tracking multiple
21085 * commands. This ID is treated as opaque data by the firmware and
21086 * the value is returned in the `hwrm_resp_hdr` upon completion.
21090 * The target ID of the command:
21091 * * 0x0-0xFFF8 - The function ID
21092 * * 0xFFF8-0xFFFE - Reserved for internal processors
21095 uint16_t target_id;
21097 * A physical address pointer pointing to a host buffer that the
21098 * command's response data will be written. This can be either a host
21099 * physical address (HPA) or a guest physical address (GPA) and must
21100 * point to a physically contiguous block of memory.
21102 uint64_t resp_addr;
21104 * This value identifies the CR associated with the ring
21109 * This value identifies the main RR associated with the ring
21114 * This value identifies the aggregation RR associated with
21115 * the ring group. If this value is 0xFF... (All Fs), then no
21116 * Aggregation ring will be set.
21120 * This value identifies the statistics context associated
21121 * with the ring group.
21124 } __attribute__((packed));
21126 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
21127 struct hwrm_ring_grp_alloc_output {
21128 /* The specific error status for the command. */
21129 uint16_t error_code;
21130 /* The HWRM command request type. */
21132 /* The sequence ID from the original command. */
21134 /* The length of the response data in number of bytes. */
21137 * This is the ring group ID value. Use this value to program
21138 * the default ring group for the VNIC or as table entries
21139 * in an RSS/COS context.
21141 uint32_t ring_group_id;
21142 uint8_t unused_0[3];
21144 * This field is used in Output records to indicate that the output
21145 * is completely written to RAM. This field should be read as '1'
21146 * to indicate that the output has been completely written.
21147 * When writing a command completion or response to an internal processor,
21148 * the order of writes has to be such that this field is written last.
21151 } __attribute__((packed));
21153 /**********************
21154 * hwrm_ring_grp_free *
21155 **********************/
21158 /* hwrm_ring_grp_free_input (size:192b/24B) */
21159 struct hwrm_ring_grp_free_input {
21160 /* The HWRM command request type. */
21163 * The completion ring to send the completion event on. This should
21164 * be the NQ ID returned from the `nq_alloc` HWRM command.
21166 uint16_t cmpl_ring;
21168 * The sequence ID is used by the driver for tracking multiple
21169 * commands. This ID is treated as opaque data by the firmware and
21170 * the value is returned in the `hwrm_resp_hdr` upon completion.
21174 * The target ID of the command:
21175 * * 0x0-0xFFF8 - The function ID
21176 * * 0xFFF8-0xFFFE - Reserved for internal processors
21179 uint16_t target_id;
21181 * A physical address pointer pointing to a host buffer that the
21182 * command's response data will be written. This can be either a host
21183 * physical address (HPA) or a guest physical address (GPA) and must
21184 * point to a physically contiguous block of memory.
21186 uint64_t resp_addr;
21187 /* This is the ring group ID value. */
21188 uint32_t ring_group_id;
21189 uint8_t unused_0[4];
21190 } __attribute__((packed));
21192 /* hwrm_ring_grp_free_output (size:128b/16B) */
21193 struct hwrm_ring_grp_free_output {
21194 /* The specific error status for the command. */
21195 uint16_t error_code;
21196 /* The HWRM command request type. */
21198 /* The sequence ID from the original command. */
21200 /* The length of the response data in number of bytes. */
21202 uint8_t unused_0[7];
21204 * This field is used in Output records to indicate that the output
21205 * is completely written to RAM. This field should be read as '1'
21206 * to indicate that the output has been completely written.
21207 * When writing a command completion or response to an internal processor,
21208 * the order of writes has to be such that this field is written last.
21211 } __attribute__((packed));
21213 /****************************
21214 * hwrm_cfa_l2_filter_alloc *
21215 ****************************/
21218 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
21219 struct hwrm_cfa_l2_filter_alloc_input {
21220 /* The HWRM command request type. */
21223 * The completion ring to send the completion event on. This should
21224 * be the NQ ID returned from the `nq_alloc` HWRM command.
21226 uint16_t cmpl_ring;
21228 * The sequence ID is used by the driver for tracking multiple
21229 * commands. This ID is treated as opaque data by the firmware and
21230 * the value is returned in the `hwrm_resp_hdr` upon completion.
21234 * The target ID of the command:
21235 * * 0x0-0xFFF8 - The function ID
21236 * * 0xFFF8-0xFFFE - Reserved for internal processors
21239 uint16_t target_id;
21241 * A physical address pointer pointing to a host buffer that the
21242 * command's response data will be written. This can be either a host
21243 * physical address (HPA) or a guest physical address (GPA) and must
21244 * point to a physically contiguous block of memory.
21246 uint64_t resp_addr;
21249 * Enumeration denoting the RX, TX type of the resource.
21250 * This enumeration is used for resources that are similar for both
21251 * TX and RX paths of the chip.
21253 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
21256 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
21259 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
21261 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
21262 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
21263 /* Setting of this flag indicates the applicability to the loopback path. */
21264 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
21267 * Setting of this flag indicates drop action. If this flag is not set,
21268 * then it should be considered accept action.
21270 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
21273 * If this flag is set, all t_l2_* fields are invalid
21274 * and they should not be specified.
21275 * If this flag is set, then l2_* fields refer to
21276 * fields of outermost L2 header.
21278 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
21281 * Enumeration denoting NO_ROCE_L2 to support old drivers.
21282 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
21284 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
21286 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
21287 /* To support old drivers */
21288 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
21289 (UINT32_C(0x0) << 4)
21290 /* Only L2 traffic */
21291 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
21292 (UINT32_C(0x1) << 4)
21293 /* Roce & L2 traffic */
21294 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
21295 (UINT32_C(0x2) << 4)
21296 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
21297 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
21300 * This bit must be '1' for the l2_addr field to be
21303 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
21306 * This bit must be '1' for the l2_addr_mask field to be
21309 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
21312 * This bit must be '1' for the l2_ovlan field to be
21315 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
21318 * This bit must be '1' for the l2_ovlan_mask field to be
21321 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
21324 * This bit must be '1' for the l2_ivlan field to be
21327 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
21330 * This bit must be '1' for the l2_ivlan_mask field to be
21333 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
21336 * This bit must be '1' for the t_l2_addr field to be
21339 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
21342 * This bit must be '1' for the t_l2_addr_mask field to be
21345 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
21348 * This bit must be '1' for the t_l2_ovlan field to be
21351 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
21354 * This bit must be '1' for the t_l2_ovlan_mask field to be
21357 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
21360 * This bit must be '1' for the t_l2_ivlan field to be
21363 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
21366 * This bit must be '1' for the t_l2_ivlan_mask field to be
21369 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
21372 * This bit must be '1' for the src_type field to be
21375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
21378 * This bit must be '1' for the src_id field to be
21381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
21384 * This bit must be '1' for the tunnel_type field to be
21387 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
21390 * This bit must be '1' for the dst_id field to be
21393 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
21396 * This bit must be '1' for the mirror_vnic_id field to be
21399 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
21402 * This value sets the match value for the L2 MAC address.
21403 * Destination MAC address for RX path.
21404 * Source MAC address for TX path.
21406 uint8_t l2_addr[6];
21407 uint8_t unused_0[2];
21409 * This value sets the mask value for the L2 address.
21410 * A value of 0 will mask the corresponding bit from
21413 uint8_t l2_addr_mask[6];
21414 /* This value sets VLAN ID value for outer VLAN. */
21417 * This value sets the mask value for the ovlan id.
21418 * A value of 0 will mask the corresponding bit from
21421 uint16_t l2_ovlan_mask;
21422 /* This value sets VLAN ID value for inner VLAN. */
21425 * This value sets the mask value for the ivlan id.
21426 * A value of 0 will mask the corresponding bit from
21429 uint16_t l2_ivlan_mask;
21430 uint8_t unused_1[2];
21432 * This value sets the match value for the tunnel
21434 * Destination MAC address for RX path.
21435 * Source MAC address for TX path.
21437 uint8_t t_l2_addr[6];
21438 uint8_t unused_2[2];
21440 * This value sets the mask value for the tunnel L2
21442 * A value of 0 will mask the corresponding bit from
21445 uint8_t t_l2_addr_mask[6];
21446 /* This value sets VLAN ID value for tunnel outer VLAN. */
21447 uint16_t t_l2_ovlan;
21449 * This value sets the mask value for the tunnel ovlan id.
21450 * A value of 0 will mask the corresponding bit from
21453 uint16_t t_l2_ovlan_mask;
21454 /* This value sets VLAN ID value for tunnel inner VLAN. */
21455 uint16_t t_l2_ivlan;
21457 * This value sets the mask value for the tunnel ivlan id.
21458 * A value of 0 will mask the corresponding bit from
21461 uint16_t t_l2_ivlan_mask;
21462 /* This value identifies the type of source of the packet. */
21465 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
21466 /* Physical function */
21467 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
21468 /* Virtual function */
21469 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
21470 /* Virtual NIC of a function */
21471 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
21472 /* Embedded processor for CFA management */
21473 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
21474 /* Embedded processor for OOB management */
21475 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
21476 /* Embedded processor for RoCE */
21477 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
21478 /* Embedded processor for network proxy functions */
21479 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
21480 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
21481 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
21484 * This value is the id of the source.
21485 * For a network port, it represents port_id.
21486 * For a physical function, it represents fid.
21487 * For a virtual function, it represents vf_id.
21488 * For a vnic, it represents vnic_id.
21489 * For embedded processors, this id is not valid.
21492 * 1. The function ID is implied if it src_id is
21493 * not provided for a src_type that is either
21497 uint8_t tunnel_type;
21499 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21501 /* Virtual eXtensible Local Area Network (VXLAN) */
21502 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21504 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21505 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21507 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21508 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21511 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21513 /* Generic Network Virtualization Encapsulation (Geneve) */
21514 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21516 /* Multi-Protocol Lable Switching (MPLS) */
21517 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21519 /* Stateless Transport Tunnel (STT) */
21520 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21522 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21523 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21525 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21526 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21528 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21529 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21531 /* Use fixed layer 2 ether type of 0xFFFF */
21532 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
21534 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
21535 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
21537 /* Any tunneled traffic */
21538 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21540 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21541 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21544 * If set, this value shall represent the
21545 * Logical VNIC ID of the destination VNIC for the RX
21546 * path and network port id of the destination port for
21551 * Logical VNIC ID of the VNIC where traffic is
21554 uint16_t mirror_vnic_id;
21556 * This hint is provided to help in placing
21557 * the filter in the filter table.
21560 /* No preference */
21561 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
21563 /* Above the given filter */
21564 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
21566 /* Below the given filter */
21567 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
21569 /* As high as possible */
21570 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
21572 /* As low as possible */
21573 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
21575 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
21576 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
21580 * This is the ID of the filter that goes along with
21583 * This field is valid only for the following values.
21584 * 1 - Above the given filter
21585 * 2 - Below the given filter
21587 uint64_t l2_filter_id_hint;
21588 } __attribute__((packed));
21590 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
21591 struct hwrm_cfa_l2_filter_alloc_output {
21592 /* The specific error status for the command. */
21593 uint16_t error_code;
21594 /* The HWRM command request type. */
21596 /* The sequence ID from the original command. */
21598 /* The length of the response data in number of bytes. */
21601 * This value identifies a set of CFA data structures used for an L2
21604 uint64_t l2_filter_id;
21606 * This is the ID of the flow associated with this
21608 * This value shall be used to match and associate the
21609 * flow identifier returned in completion records.
21610 * A value of 0xFFFFFFFF shall indicate no flow id.
21613 uint8_t unused_0[3];
21615 * This field is used in Output records to indicate that the output
21616 * is completely written to RAM. This field should be read as '1'
21617 * to indicate that the output has been completely written.
21618 * When writing a command completion or response to an internal processor,
21619 * the order of writes has to be such that this field is written last.
21622 } __attribute__((packed));
21624 /***************************
21625 * hwrm_cfa_l2_filter_free *
21626 ***************************/
21629 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
21630 struct hwrm_cfa_l2_filter_free_input {
21631 /* The HWRM command request type. */
21634 * The completion ring to send the completion event on. This should
21635 * be the NQ ID returned from the `nq_alloc` HWRM command.
21637 uint16_t cmpl_ring;
21639 * The sequence ID is used by the driver for tracking multiple
21640 * commands. This ID is treated as opaque data by the firmware and
21641 * the value is returned in the `hwrm_resp_hdr` upon completion.
21645 * The target ID of the command:
21646 * * 0x0-0xFFF8 - The function ID
21647 * * 0xFFF8-0xFFFE - Reserved for internal processors
21650 uint16_t target_id;
21652 * A physical address pointer pointing to a host buffer that the
21653 * command's response data will be written. This can be either a host
21654 * physical address (HPA) or a guest physical address (GPA) and must
21655 * point to a physically contiguous block of memory.
21657 uint64_t resp_addr;
21659 * This value identifies a set of CFA data structures used for an L2
21662 uint64_t l2_filter_id;
21663 } __attribute__((packed));
21665 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
21666 struct hwrm_cfa_l2_filter_free_output {
21667 /* The specific error status for the command. */
21668 uint16_t error_code;
21669 /* The HWRM command request type. */
21671 /* The sequence ID from the original command. */
21673 /* The length of the response data in number of bytes. */
21675 uint8_t unused_0[7];
21677 * This field is used in Output records to indicate that the output
21678 * is completely written to RAM. This field should be read as '1'
21679 * to indicate that the output has been completely written.
21680 * When writing a command completion or response to an internal processor,
21681 * the order of writes has to be such that this field is written last.
21684 } __attribute__((packed));
21686 /**************************
21687 * hwrm_cfa_l2_filter_cfg *
21688 **************************/
21691 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
21692 struct hwrm_cfa_l2_filter_cfg_input {
21693 /* The HWRM command request type. */
21696 * The completion ring to send the completion event on. This should
21697 * be the NQ ID returned from the `nq_alloc` HWRM command.
21699 uint16_t cmpl_ring;
21701 * The sequence ID is used by the driver for tracking multiple
21702 * commands. This ID is treated as opaque data by the firmware and
21703 * the value is returned in the `hwrm_resp_hdr` upon completion.
21707 * The target ID of the command:
21708 * * 0x0-0xFFF8 - The function ID
21709 * * 0xFFF8-0xFFFE - Reserved for internal processors
21712 uint16_t target_id;
21714 * A physical address pointer pointing to a host buffer that the
21715 * command's response data will be written. This can be either a host
21716 * physical address (HPA) or a guest physical address (GPA) and must
21717 * point to a physically contiguous block of memory.
21719 uint64_t resp_addr;
21722 * Enumeration denoting the RX, TX type of the resource.
21723 * This enumeration is used for resources that are similar for both
21724 * TX and RX paths of the chip.
21726 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
21729 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
21732 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
21734 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
21735 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
21737 * Setting of this flag indicates drop action. If this flag is not set,
21738 * then it should be considered accept action.
21740 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
21743 * Enumeration denoting NO_ROCE_L2 to support old drivers.
21744 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
21746 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
21748 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
21749 /* To support old drivers */
21750 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
21751 (UINT32_C(0x0) << 2)
21752 /* Only L2 traffic */
21753 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
21754 (UINT32_C(0x1) << 2)
21755 /* Roce & L2 traffic */
21756 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
21757 (UINT32_C(0x2) << 2)
21758 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
21759 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
21762 * This bit must be '1' for the dst_id field to be
21765 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
21768 * This bit must be '1' for the new_mirror_vnic_id field to be
21771 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
21774 * This value identifies a set of CFA data structures used for an L2
21777 uint64_t l2_filter_id;
21779 * If set, this value shall represent the
21780 * Logical VNIC ID of the destination VNIC for the RX
21781 * path and network port id of the destination port for
21786 * New Logical VNIC ID of the VNIC where traffic is
21789 uint32_t new_mirror_vnic_id;
21790 } __attribute__((packed));
21792 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
21793 struct hwrm_cfa_l2_filter_cfg_output {
21794 /* The specific error status for the command. */
21795 uint16_t error_code;
21796 /* The HWRM command request type. */
21798 /* The sequence ID from the original command. */
21800 /* The length of the response data in number of bytes. */
21802 uint8_t unused_0[7];
21804 * This field is used in Output records to indicate that the output
21805 * is completely written to RAM. This field should be read as '1'
21806 * to indicate that the output has been completely written.
21807 * When writing a command completion or response to an internal processor,
21808 * the order of writes has to be such that this field is written last.
21811 } __attribute__((packed));
21813 /***************************
21814 * hwrm_cfa_l2_set_rx_mask *
21815 ***************************/
21818 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
21819 struct hwrm_cfa_l2_set_rx_mask_input {
21820 /* The HWRM command request type. */
21823 * The completion ring to send the completion event on. This should
21824 * be the NQ ID returned from the `nq_alloc` HWRM command.
21826 uint16_t cmpl_ring;
21828 * The sequence ID is used by the driver for tracking multiple
21829 * commands. This ID is treated as opaque data by the firmware and
21830 * the value is returned in the `hwrm_resp_hdr` upon completion.
21834 * The target ID of the command:
21835 * * 0x0-0xFFF8 - The function ID
21836 * * 0xFFF8-0xFFFE - Reserved for internal processors
21839 uint16_t target_id;
21841 * A physical address pointer pointing to a host buffer that the
21842 * command's response data will be written. This can be either a host
21843 * physical address (HPA) or a guest physical address (GPA) and must
21844 * point to a physically contiguous block of memory.
21846 uint64_t resp_addr;
21851 * When this bit is '1', the function is requested to accept
21852 * multi-cast packets specified by the multicast addr table.
21854 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
21857 * When this bit is '1', the function is requested to accept
21858 * all multi-cast packets.
21860 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
21863 * When this bit is '1', the function is requested to accept
21864 * broadcast packets.
21866 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
21869 * When this bit is '1', the function is requested to be
21870 * put in the promiscuous mode.
21872 * The HWRM should accept any function to set up
21873 * promiscuous mode.
21875 * The HWRM shall follow the semantics below for the
21876 * promiscuous mode support.
21877 * # When partitioning is not enabled on a port
21878 * (i.e. single PF on the port), then the PF shall
21879 * be allowed to be in the promiscuous mode. When the
21880 * PF is in the promiscuous mode, then it shall
21881 * receive all host bound traffic on that port.
21882 * # When partitioning is enabled on a port
21883 * (i.e. multiple PFs per port) and a PF on that
21884 * port is in the promiscuous mode, then the PF
21885 * receives all traffic within that partition as
21886 * identified by a unique identifier for the
21887 * PF (e.g. S-Tag). If a unique outer VLAN
21888 * for the PF is specified, then the setting of
21889 * promiscuous mode on that PF shall result in the
21890 * PF receiving all host bound traffic with matching
21892 * # A VF shall can be set in the promiscuous mode.
21893 * In the promiscuous mode, the VF does not receive any
21894 * traffic unless a unique outer VLAN for the
21895 * VF is specified. If a unique outer VLAN
21896 * for the VF is specified, then the setting of
21897 * promiscuous mode on that VF shall result in the
21898 * VF receiving all host bound traffic with the
21899 * matching outer VLAN.
21900 * # The HWRM shall allow the setting of promiscuous
21901 * mode on a function independently from the
21902 * promiscuous mode settings on other functions.
21904 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
21907 * If this flag is set, the corresponding RX
21908 * filters shall be set up to cover multicast/broadcast
21909 * filters for the outermost Layer 2 destination MAC
21912 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
21915 * If this flag is set, the corresponding RX
21916 * filters shall be set up to cover multicast/broadcast
21917 * filters for the VLAN-tagged packets that match the
21918 * TPID and VID fields of VLAN tags in the VLAN tag
21919 * table specified in this command.
21921 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
21924 * If this flag is set, the corresponding RX
21925 * filters shall be set up to cover multicast/broadcast
21926 * filters for non-VLAN tagged packets and VLAN-tagged
21927 * packets that match the TPID and VID fields of VLAN
21928 * tags in the VLAN tag table specified in this command.
21930 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
21933 * If this flag is set, the corresponding RX
21934 * filters shall be set up to cover multicast/broadcast
21935 * filters for non-VLAN tagged packets and VLAN-tagged
21936 * packets matching any VLAN tag.
21938 * If this flag is set, then the HWRM shall ignore
21939 * VLAN tags specified in vlan_tag_tbl.
21941 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
21942 * flags is set, then the HWRM shall ignore
21943 * VLAN tags specified in vlan_tag_tbl.
21945 * The HWRM client shall set at most one flag out of
21946 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
21948 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
21950 /* This is the address for mcast address tbl. */
21951 uint64_t mc_tbl_addr;
21953 * This value indicates how many entries in mc_tbl are valid.
21954 * Each entry is 6 bytes.
21956 uint32_t num_mc_entries;
21957 uint8_t unused_0[4];
21959 * This is the address for VLAN tag table.
21960 * Each VLAN entry in the table is 4 bytes of a VLAN tag
21961 * including TPID, PCP, DEI, and VID fields in network byte
21964 uint64_t vlan_tag_tbl_addr;
21966 * This value indicates how many entries in vlan_tag_tbl are
21967 * valid. Each entry is 4 bytes.
21969 uint32_t num_vlan_tags;
21970 uint8_t unused_1[4];
21971 } __attribute__((packed));
21973 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
21974 struct hwrm_cfa_l2_set_rx_mask_output {
21975 /* The specific error status for the command. */
21976 uint16_t error_code;
21977 /* The HWRM command request type. */
21979 /* The sequence ID from the original command. */
21981 /* The length of the response data in number of bytes. */
21983 uint8_t unused_0[7];
21985 * This field is used in Output records to indicate that the output
21986 * is completely written to RAM. This field should be read as '1'
21987 * to indicate that the output has been completely written.
21988 * When writing a command completion or response to an internal processor,
21989 * the order of writes has to be such that this field is written last.
21992 } __attribute__((packed));
21994 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
21995 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
21997 * command specific error codes that goes to
21998 * the cmd_err field in Common HWRM Error Response.
22001 /* Unknown error */
22002 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
22004 /* Unable to complete operation due to conflict with Ntuple Filter */
22005 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
22007 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
22008 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
22009 uint8_t unused_0[7];
22010 } __attribute__((packed));
22012 /*******************************
22013 * hwrm_cfa_vlan_antispoof_cfg *
22014 *******************************/
22017 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
22018 struct hwrm_cfa_vlan_antispoof_cfg_input {
22019 /* The HWRM command request type. */
22022 * The completion ring to send the completion event on. This should
22023 * be the NQ ID returned from the `nq_alloc` HWRM command.
22025 uint16_t cmpl_ring;
22027 * The sequence ID is used by the driver for tracking multiple
22028 * commands. This ID is treated as opaque data by the firmware and
22029 * the value is returned in the `hwrm_resp_hdr` upon completion.
22033 * The target ID of the command:
22034 * * 0x0-0xFFF8 - The function ID
22035 * * 0xFFF8-0xFFFE - Reserved for internal processors
22038 uint16_t target_id;
22040 * A physical address pointer pointing to a host buffer that the
22041 * command's response data will be written. This can be either a host
22042 * physical address (HPA) or a guest physical address (GPA) and must
22043 * point to a physically contiguous block of memory.
22045 uint64_t resp_addr;
22047 * Function ID of the function that is being configured.
22048 * Only valid for a VF FID configured by the PF.
22051 uint8_t unused_0[2];
22052 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
22053 uint32_t num_vlan_entries;
22055 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
22056 * antispoof table. Each table entry contains the 16-bit TPID
22057 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
22058 * all in network order to match hwrm_cfa_l2_set_rx_mask.
22059 * For an individual VLAN entry, the mask value should be 0xfff
22060 * for the 12-bit VLAN ID.
22062 uint64_t vlan_tag_mask_tbl_addr;
22063 } __attribute__((packed));
22065 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
22066 struct hwrm_cfa_vlan_antispoof_cfg_output {
22067 /* The specific error status for the command. */
22068 uint16_t error_code;
22069 /* The HWRM command request type. */
22071 /* The sequence ID from the original command. */
22073 /* The length of the response data in number of bytes. */
22075 uint8_t unused_0[7];
22077 * This field is used in Output records to indicate that the output
22078 * is completely written to RAM. This field should be read as '1'
22079 * to indicate that the output has been completely written.
22080 * When writing a command completion or response to an internal processor,
22081 * the order of writes has to be such that this field is written last.
22084 } __attribute__((packed));
22086 /********************************
22087 * hwrm_cfa_vlan_antispoof_qcfg *
22088 ********************************/
22091 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
22092 struct hwrm_cfa_vlan_antispoof_qcfg_input {
22093 /* The HWRM command request type. */
22096 * The completion ring to send the completion event on. This should
22097 * be the NQ ID returned from the `nq_alloc` HWRM command.
22099 uint16_t cmpl_ring;
22101 * The sequence ID is used by the driver for tracking multiple
22102 * commands. This ID is treated as opaque data by the firmware and
22103 * the value is returned in the `hwrm_resp_hdr` upon completion.
22107 * The target ID of the command:
22108 * * 0x0-0xFFF8 - The function ID
22109 * * 0xFFF8-0xFFFE - Reserved for internal processors
22112 uint16_t target_id;
22114 * A physical address pointer pointing to a host buffer that the
22115 * command's response data will be written. This can be either a host
22116 * physical address (HPA) or a guest physical address (GPA) and must
22117 * point to a physically contiguous block of memory.
22119 uint64_t resp_addr;
22121 * Function ID of the function that is being queried.
22122 * Only valid for a VF FID queried by the PF.
22125 uint8_t unused_0[2];
22127 * Maximum number of VLAN entries the firmware is allowed to DMA
22128 * to vlan_tag_mask_tbl.
22130 uint32_t max_vlan_entries;
22132 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
22133 * antispoof table to which firmware will DMA to. Each table
22134 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
22135 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
22136 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
22137 * the mask value should be 0xfff for the 12-bit VLAN ID.
22139 uint64_t vlan_tag_mask_tbl_addr;
22140 } __attribute__((packed));
22142 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
22143 struct hwrm_cfa_vlan_antispoof_qcfg_output {
22144 /* The specific error status for the command. */
22145 uint16_t error_code;
22146 /* The HWRM command request type. */
22148 /* The sequence ID from the original command. */
22150 /* The length of the response data in number of bytes. */
22152 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
22153 uint32_t num_vlan_entries;
22154 uint8_t unused_0[3];
22156 * This field is used in Output records to indicate that the output
22157 * is completely written to RAM. This field should be read as '1'
22158 * to indicate that the output has been completely written.
22159 * When writing a command completion or response to an internal processor,
22160 * the order of writes has to be such that this field is written last.
22163 } __attribute__((packed));
22165 /********************************
22166 * hwrm_cfa_tunnel_filter_alloc *
22167 ********************************/
22170 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
22171 struct hwrm_cfa_tunnel_filter_alloc_input {
22172 /* The HWRM command request type. */
22175 * The completion ring to send the completion event on. This should
22176 * be the NQ ID returned from the `nq_alloc` HWRM command.
22178 uint16_t cmpl_ring;
22180 * The sequence ID is used by the driver for tracking multiple
22181 * commands. This ID is treated as opaque data by the firmware and
22182 * the value is returned in the `hwrm_resp_hdr` upon completion.
22186 * The target ID of the command:
22187 * * 0x0-0xFFF8 - The function ID
22188 * * 0xFFF8-0xFFFE - Reserved for internal processors
22191 uint16_t target_id;
22193 * A physical address pointer pointing to a host buffer that the
22194 * command's response data will be written. This can be either a host
22195 * physical address (HPA) or a guest physical address (GPA) and must
22196 * point to a physically contiguous block of memory.
22198 uint64_t resp_addr;
22200 /* Setting of this flag indicates the applicability to the loopback path. */
22201 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
22205 * This bit must be '1' for the l2_filter_id field to be
22208 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
22211 * This bit must be '1' for the l2_addr field to be
22214 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
22217 * This bit must be '1' for the l2_ivlan field to be
22220 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
22223 * This bit must be '1' for the l3_addr field to be
22226 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
22229 * This bit must be '1' for the l3_addr_type field to be
22232 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
22235 * This bit must be '1' for the t_l3_addr_type field to be
22238 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
22241 * This bit must be '1' for the t_l3_addr field to be
22244 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
22247 * This bit must be '1' for the tunnel_type field to be
22250 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
22253 * This bit must be '1' for the vni field to be
22256 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
22259 * This bit must be '1' for the dst_vnic_id field to be
22262 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
22265 * This bit must be '1' for the mirror_vnic_id field to be
22268 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
22271 * This value identifies a set of CFA data structures used for an L2
22274 uint64_t l2_filter_id;
22276 * This value sets the match value for the inner L2
22278 * Destination MAC address for RX path.
22279 * Source MAC address for TX path.
22281 uint8_t l2_addr[6];
22283 * This value sets VLAN ID value for inner VLAN.
22284 * Only 12-bits of VLAN ID are used in setting the filter.
22288 * The value of inner destination IP address to be used in filtering.
22289 * For IPv4, first four bytes represent the IP address.
22291 uint32_t l3_addr[4];
22293 * The value of tunnel destination IP address to be used in filtering.
22294 * For IPv4, first four bytes represent the IP address.
22296 uint32_t t_l3_addr[4];
22298 * This value indicates the type of inner IP address.
22301 * All others are invalid.
22303 uint8_t l3_addr_type;
22305 * This value indicates the type of tunnel IP address.
22308 * All others are invalid.
22310 uint8_t t_l3_addr_type;
22312 uint8_t tunnel_type;
22314 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22316 /* Virtual eXtensible Local Area Network (VXLAN) */
22317 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22319 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22320 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22322 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22323 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22326 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22328 /* Generic Network Virtualization Encapsulation (Geneve) */
22329 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22331 /* Multi-Protocol Lable Switching (MPLS) */
22332 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22334 /* Stateless Transport Tunnel (STT) */
22335 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
22337 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22338 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22340 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22341 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22343 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22344 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22346 /* Use fixed layer 2 ether type of 0xFFFF */
22347 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
22349 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
22350 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
22352 /* Any tunneled traffic */
22353 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22355 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22356 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22358 * tunnel_flags allows the user to indicate the tunnel tag detection
22359 * for the tunnel type specified in tunnel_type.
22361 uint8_t tunnel_flags;
22363 * If the tunnel_type is geneve, then this bit indicates if we
22364 * need to match the geneve OAM packet.
22365 * If the tunnel_type is nvgre or gre, then this bit indicates if
22366 * we need to detect checksum present bit in geneve header.
22367 * If the tunnel_type is mpls, then this bit indicates if we need
22368 * to match mpls packet with explicit IPV4/IPV6 null header.
22370 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
22373 * If the tunnel_type is geneve, then this bit indicates if we
22374 * need to detect the critical option bit set in the oam packet.
22375 * If the tunnel_type is nvgre or gre, then this bit indicates
22376 * if we need to match nvgre packets with key present bit set in
22378 * If the tunnel_type is mpls, then this bit indicates if we
22379 * need to match mpls packet with S bit from inner/second label.
22381 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
22384 * If the tunnel_type is geneve, then this bit indicates if we
22385 * need to match geneve packet with extended header bit set in
22387 * If the tunnel_type is nvgre or gre, then this bit indicates
22388 * if we need to match nvgre packets with sequence number
22389 * present bit set in gre header.
22390 * If the tunnel_type is mpls, then this bit indicates if we
22391 * need to match mpls packet with S bit from out/first label.
22393 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
22396 * Virtual Network Identifier (VNI). Only valid with
22397 * tunnel_types VXLAN, NVGRE, and Geneve.
22398 * Only lower 24-bits of VNI field are used
22399 * in setting up the filter.
22402 /* Logical VNIC ID of the destination VNIC. */
22403 uint32_t dst_vnic_id;
22405 * Logical VNIC ID of the VNIC where traffic is
22408 uint32_t mirror_vnic_id;
22409 } __attribute__((packed));
22411 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
22412 struct hwrm_cfa_tunnel_filter_alloc_output {
22413 /* The specific error status for the command. */
22414 uint16_t error_code;
22415 /* The HWRM command request type. */
22417 /* The sequence ID from the original command. */
22419 /* The length of the response data in number of bytes. */
22421 /* This value is an opaque id into CFA data structures. */
22422 uint64_t tunnel_filter_id;
22424 * This is the ID of the flow associated with this
22426 * This value shall be used to match and associate the
22427 * flow identifier returned in completion records.
22428 * A value of 0xFFFFFFFF shall indicate no flow id.
22431 uint8_t unused_0[3];
22433 * This field is used in Output records to indicate that the output
22434 * is completely written to RAM. This field should be read as '1'
22435 * to indicate that the output has been completely written.
22436 * When writing a command completion or response to an internal processor,
22437 * the order of writes has to be such that this field is written last.
22440 } __attribute__((packed));
22442 /*******************************
22443 * hwrm_cfa_tunnel_filter_free *
22444 *******************************/
22447 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
22448 struct hwrm_cfa_tunnel_filter_free_input {
22449 /* The HWRM command request type. */
22452 * The completion ring to send the completion event on. This should
22453 * be the NQ ID returned from the `nq_alloc` HWRM command.
22455 uint16_t cmpl_ring;
22457 * The sequence ID is used by the driver for tracking multiple
22458 * commands. This ID is treated as opaque data by the firmware and
22459 * the value is returned in the `hwrm_resp_hdr` upon completion.
22463 * The target ID of the command:
22464 * * 0x0-0xFFF8 - The function ID
22465 * * 0xFFF8-0xFFFE - Reserved for internal processors
22468 uint16_t target_id;
22470 * A physical address pointer pointing to a host buffer that the
22471 * command's response data will be written. This can be either a host
22472 * physical address (HPA) or a guest physical address (GPA) and must
22473 * point to a physically contiguous block of memory.
22475 uint64_t resp_addr;
22476 /* This value is an opaque id into CFA data structures. */
22477 uint64_t tunnel_filter_id;
22478 } __attribute__((packed));
22480 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
22481 struct hwrm_cfa_tunnel_filter_free_output {
22482 /* The specific error status for the command. */
22483 uint16_t error_code;
22484 /* The HWRM command request type. */
22486 /* The sequence ID from the original command. */
22488 /* The length of the response data in number of bytes. */
22490 uint8_t unused_0[7];
22492 * This field is used in Output records to indicate that the output
22493 * is completely written to RAM. This field should be read as '1'
22494 * to indicate that the output has been completely written.
22495 * When writing a command completion or response to an internal processor,
22496 * the order of writes has to be such that this field is written last.
22499 } __attribute__((packed));
22501 /***************************************
22502 * hwrm_cfa_redirect_tunnel_type_alloc *
22503 ***************************************/
22506 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
22507 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
22508 /* The HWRM command request type. */
22511 * The completion ring to send the completion event on. This should
22512 * be the NQ ID returned from the `nq_alloc` HWRM command.
22514 uint16_t cmpl_ring;
22516 * The sequence ID is used by the driver for tracking multiple
22517 * commands. This ID is treated as opaque data by the firmware and
22518 * the value is returned in the `hwrm_resp_hdr` upon completion.
22522 * The target ID of the command:
22523 * * 0x0-0xFFF8 - The function ID
22524 * * 0xFFF8-0xFFFE - Reserved for internal processors
22527 uint16_t target_id;
22529 * A physical address pointer pointing to a host buffer that the
22530 * command's response data will be written. This can be either a host
22531 * physical address (HPA) or a guest physical address (GPA) and must
22532 * point to a physically contiguous block of memory.
22534 uint64_t resp_addr;
22535 /* The destination function id, to whom the traffic is redirected. */
22538 uint8_t tunnel_type;
22540 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22542 /* Virtual eXtensible Local Area Network (VXLAN) */
22543 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22545 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22546 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22548 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22549 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22552 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22554 /* Generic Network Virtualization Encapsulation (Geneve) */
22555 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22557 /* Multi-Protocol Lable Switching (MPLS) */
22558 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22560 /* Stateless Transport Tunnel (STT) */
22561 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
22563 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22564 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22566 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22567 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22569 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22570 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22572 /* Use fixed layer 2 ether type of 0xFFFF */
22573 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
22575 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
22576 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
22578 /* Any tunneled traffic */
22579 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22581 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22582 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22583 /* Tunnel alloc flags. */
22585 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
22586 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
22588 uint8_t unused_0[4];
22589 } __attribute__((packed));
22591 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
22592 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
22593 /* The specific error status for the command. */
22594 uint16_t error_code;
22595 /* The HWRM command request type. */
22597 /* The sequence ID from the original command. */
22599 /* The length of the response data in number of bytes. */
22601 uint8_t unused_0[7];
22603 * This field is used in Output records to indicate that the output
22604 * is completely written to RAM. This field should be read as '1'
22605 * to indicate that the output has been completely written.
22606 * When writing a command completion or response to an internal processor,
22607 * the order of writes has to be such that this field is written last.
22610 } __attribute__((packed));
22612 /**************************************
22613 * hwrm_cfa_redirect_tunnel_type_free *
22614 **************************************/
22617 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
22618 struct hwrm_cfa_redirect_tunnel_type_free_input {
22619 /* The HWRM command request type. */
22622 * The completion ring to send the completion event on. This should
22623 * be the NQ ID returned from the `nq_alloc` HWRM command.
22625 uint16_t cmpl_ring;
22627 * The sequence ID is used by the driver for tracking multiple
22628 * commands. This ID is treated as opaque data by the firmware and
22629 * the value is returned in the `hwrm_resp_hdr` upon completion.
22633 * The target ID of the command:
22634 * * 0x0-0xFFF8 - The function ID
22635 * * 0xFFF8-0xFFFE - Reserved for internal processors
22638 uint16_t target_id;
22640 * A physical address pointer pointing to a host buffer that the
22641 * command's response data will be written. This can be either a host
22642 * physical address (HPA) or a guest physical address (GPA) and must
22643 * point to a physically contiguous block of memory.
22645 uint64_t resp_addr;
22646 /* The destination function id, to whom the traffic is redirected. */
22649 uint8_t tunnel_type;
22651 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
22653 /* Virtual eXtensible Local Area Network (VXLAN) */
22654 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
22656 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22657 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
22659 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22660 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
22663 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
22665 /* Generic Network Virtualization Encapsulation (Geneve) */
22666 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
22668 /* Multi-Protocol Lable Switching (MPLS) */
22669 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
22671 /* Stateless Transport Tunnel (STT) */
22672 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
22674 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22675 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
22677 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22678 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22680 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22681 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22683 /* Use fixed layer 2 ether type of 0xFFFF */
22684 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
22686 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
22687 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
22689 /* Any tunneled traffic */
22690 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22692 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
22693 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
22694 uint8_t unused_0[5];
22695 } __attribute__((packed));
22697 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
22698 struct hwrm_cfa_redirect_tunnel_type_free_output {
22699 /* The specific error status for the command. */
22700 uint16_t error_code;
22701 /* The HWRM command request type. */
22703 /* The sequence ID from the original command. */
22705 /* The length of the response data in number of bytes. */
22707 uint8_t unused_0[7];
22709 * This field is used in Output records to indicate that the output
22710 * is completely written to RAM. This field should be read as '1'
22711 * to indicate that the output has been completely written.
22712 * When writing a command completion or response to an internal processor,
22713 * the order of writes has to be such that this field is written last.
22716 } __attribute__((packed));
22718 /**************************************
22719 * hwrm_cfa_redirect_tunnel_type_info *
22720 **************************************/
22723 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
22724 struct hwrm_cfa_redirect_tunnel_type_info_input {
22725 /* The HWRM command request type. */
22728 * The completion ring to send the completion event on. This should
22729 * be the NQ ID returned from the `nq_alloc` HWRM command.
22731 uint16_t cmpl_ring;
22733 * The sequence ID is used by the driver for tracking multiple
22734 * commands. This ID is treated as opaque data by the firmware and
22735 * the value is returned in the `hwrm_resp_hdr` upon completion.
22739 * The target ID of the command:
22740 * * 0x0-0xFFF8 - The function ID
22741 * * 0xFFF8-0xFFFE - Reserved for internal processors
22744 uint16_t target_id;
22746 * A physical address pointer pointing to a host buffer that the
22747 * command's response data will be written. This can be either a host
22748 * physical address (HPA) or a guest physical address (GPA) and must
22749 * point to a physically contiguous block of memory.
22751 uint64_t resp_addr;
22752 /* The source function id. */
22755 uint8_t tunnel_type;
22757 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
22759 /* Virtual eXtensible Local Area Network (VXLAN) */
22760 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
22762 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22763 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
22765 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22766 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
22769 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
22771 /* Generic Network Virtualization Encapsulation (Geneve) */
22772 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
22774 /* Multi-Protocol Lable Switching (MPLS) */
22775 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
22777 /* Stateless Transport Tunnel (STT) */
22778 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
22780 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22781 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
22783 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22784 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22786 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22787 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22789 /* Use fixed layer 2 ether type of 0xFFFF */
22790 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
22792 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
22793 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
22795 /* Any tunneled traffic */
22796 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22798 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
22799 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
22800 uint8_t unused_0[5];
22801 } __attribute__((packed));
22803 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
22804 struct hwrm_cfa_redirect_tunnel_type_info_output {
22805 /* The specific error status for the command. */
22806 uint16_t error_code;
22807 /* The HWRM command request type. */
22809 /* The sequence ID from the original command. */
22811 /* The length of the response data in number of bytes. */
22813 /* The destination function id, to whom the traffic is redirected. */
22815 uint8_t unused_0[5];
22817 * This field is used in Output records to indicate that the output
22818 * is completely written to RAM. This field should be read as '1'
22819 * to indicate that the output has been completely written.
22820 * When writing a command completion or response to an internal processor,
22821 * the order of writes has to be such that this field is written last.
22824 } __attribute__((packed));
22826 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
22827 struct hwrm_vxlan_ipv4_hdr {
22828 /* IPv4 version and header length. */
22830 /* IPv4 header length */
22831 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
22832 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
22834 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
22835 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
22836 /* IPv4 type of service. */
22838 /* IPv4 identification. */
22840 /* IPv4 flags and offset. */
22841 uint16_t flags_frag_offset;
22844 /* IPv4 protocol. */
22846 /* IPv4 source address. */
22847 uint32_t src_ip_addr;
22848 /* IPv4 destination address. */
22849 uint32_t dest_ip_addr;
22850 } __attribute__((packed));
22852 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
22853 struct hwrm_vxlan_ipv6_hdr {
22854 /* IPv6 version, traffic class and flow label. */
22855 uint32_t ver_tc_flow_label;
22856 /* IPv6 version shift */
22857 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
22859 /* IPv6 version mask */
22860 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
22861 UINT32_C(0xf0000000)
22862 /* IPv6 TC shift */
22863 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
22866 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
22867 UINT32_C(0xff00000)
22868 /* IPv6 flow label shift */
22869 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
22871 /* IPv6 flow label mask */
22872 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
22874 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
22875 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
22876 /* IPv6 payload length. */
22877 uint16_t payload_len;
22878 /* IPv6 next header. */
22882 /* IPv6 source address. */
22883 uint32_t src_ip_addr[4];
22884 /* IPv6 destination address. */
22885 uint32_t dest_ip_addr[4];
22886 } __attribute__((packed));
22888 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
22889 struct hwrm_cfa_encap_data_vxlan {
22890 /* Source MAC address. */
22891 uint8_t src_mac_addr[6];
22894 /* Destination MAC address. */
22895 uint8_t dst_mac_addr[6];
22896 /* Number of VLAN tags. */
22897 uint8_t num_vlan_tags;
22900 /* Outer VLAN TPID. */
22901 uint16_t ovlan_tpid;
22902 /* Outer VLAN TCI. */
22903 uint16_t ovlan_tci;
22904 /* Inner VLAN TPID. */
22905 uint16_t ivlan_tpid;
22906 /* Inner VLAN TCI. */
22907 uint16_t ivlan_tci;
22908 /* L3 header fields. */
22910 /* IP version mask. */
22911 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
22912 /* IP version 4. */
22913 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
22914 /* IP version 6. */
22915 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
22916 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
22917 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
22918 /* UDP source port. */
22920 /* UDP destination port. */
22922 /* VXLAN Network Identifier. */
22924 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
22925 uint8_t hdr_rsvd0[3];
22926 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
22928 /* VXLAN header flags field. */
22931 } __attribute__((packed));
22933 /*******************************
22934 * hwrm_cfa_encap_record_alloc *
22935 *******************************/
22938 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
22939 struct hwrm_cfa_encap_record_alloc_input {
22940 /* The HWRM command request type. */
22943 * The completion ring to send the completion event on. This should
22944 * be the NQ ID returned from the `nq_alloc` HWRM command.
22946 uint16_t cmpl_ring;
22948 * The sequence ID is used by the driver for tracking multiple
22949 * commands. This ID is treated as opaque data by the firmware and
22950 * the value is returned in the `hwrm_resp_hdr` upon completion.
22954 * The target ID of the command:
22955 * * 0x0-0xFFF8 - The function ID
22956 * * 0xFFF8-0xFFFE - Reserved for internal processors
22959 uint16_t target_id;
22961 * A physical address pointer pointing to a host buffer that the
22962 * command's response data will be written. This can be either a host
22963 * physical address (HPA) or a guest physical address (GPA) and must
22964 * point to a physically contiguous block of memory.
22966 uint64_t resp_addr;
22968 /* Setting of this flag indicates the applicability to the loopback path. */
22969 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
22971 /* Encapsulation Type. */
22972 uint8_t encap_type;
22973 /* Virtual eXtensible Local Area Network (VXLAN) */
22974 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
22976 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22977 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
22979 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
22980 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
22983 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
22985 /* Generic Network Virtualization Encapsulation (Geneve) */
22986 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
22988 /* Multi-Protocol Lable Switching (MPLS) */
22989 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
22992 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
22994 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22995 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
22997 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22998 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
23000 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23001 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
23003 /* Use fixed layer 2 ether type of 0xFFFF */
23004 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
23006 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
23007 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
23008 uint8_t unused_0[3];
23009 /* This value is encap data used for the given encap type. */
23010 uint32_t encap_data[20];
23011 } __attribute__((packed));
23013 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
23014 struct hwrm_cfa_encap_record_alloc_output {
23015 /* The specific error status for the command. */
23016 uint16_t error_code;
23017 /* The HWRM command request type. */
23019 /* The sequence ID from the original command. */
23021 /* The length of the response data in number of bytes. */
23023 /* This value is an opaque id into CFA data structures. */
23024 uint32_t encap_record_id;
23025 uint8_t unused_0[3];
23027 * This field is used in Output records to indicate that the output
23028 * is completely written to RAM. This field should be read as '1'
23029 * to indicate that the output has been completely written.
23030 * When writing a command completion or response to an internal processor,
23031 * the order of writes has to be such that this field is written last.
23034 } __attribute__((packed));
23036 /******************************
23037 * hwrm_cfa_encap_record_free *
23038 ******************************/
23041 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
23042 struct hwrm_cfa_encap_record_free_input {
23043 /* The HWRM command request type. */
23046 * The completion ring to send the completion event on. This should
23047 * be the NQ ID returned from the `nq_alloc` HWRM command.
23049 uint16_t cmpl_ring;
23051 * The sequence ID is used by the driver for tracking multiple
23052 * commands. This ID is treated as opaque data by the firmware and
23053 * the value is returned in the `hwrm_resp_hdr` upon completion.
23057 * The target ID of the command:
23058 * * 0x0-0xFFF8 - The function ID
23059 * * 0xFFF8-0xFFFE - Reserved for internal processors
23062 uint16_t target_id;
23064 * A physical address pointer pointing to a host buffer that the
23065 * command's response data will be written. This can be either a host
23066 * physical address (HPA) or a guest physical address (GPA) and must
23067 * point to a physically contiguous block of memory.
23069 uint64_t resp_addr;
23070 /* This value is an opaque id into CFA data structures. */
23071 uint32_t encap_record_id;
23072 uint8_t unused_0[4];
23073 } __attribute__((packed));
23075 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
23076 struct hwrm_cfa_encap_record_free_output {
23077 /* The specific error status for the command. */
23078 uint16_t error_code;
23079 /* The HWRM command request type. */
23081 /* The sequence ID from the original command. */
23083 /* The length of the response data in number of bytes. */
23085 uint8_t unused_0[7];
23087 * This field is used in Output records to indicate that the output
23088 * is completely written to RAM. This field should be read as '1'
23089 * to indicate that the output has been completely written.
23090 * When writing a command completion or response to an internal processor,
23091 * the order of writes has to be such that this field is written last.
23094 } __attribute__((packed));
23096 /********************************
23097 * hwrm_cfa_ntuple_filter_alloc *
23098 ********************************/
23101 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
23102 struct hwrm_cfa_ntuple_filter_alloc_input {
23103 /* The HWRM command request type. */
23106 * The completion ring to send the completion event on. This should
23107 * be the NQ ID returned from the `nq_alloc` HWRM command.
23109 uint16_t cmpl_ring;
23111 * The sequence ID is used by the driver for tracking multiple
23112 * commands. This ID is treated as opaque data by the firmware and
23113 * the value is returned in the `hwrm_resp_hdr` upon completion.
23117 * The target ID of the command:
23118 * * 0x0-0xFFF8 - The function ID
23119 * * 0xFFF8-0xFFFE - Reserved for internal processors
23122 uint16_t target_id;
23124 * A physical address pointer pointing to a host buffer that the
23125 * command's response data will be written. This can be either a host
23126 * physical address (HPA) or a guest physical address (GPA) and must
23127 * point to a physically contiguous block of memory.
23129 uint64_t resp_addr;
23131 /* Setting of this flag indicates the applicability to the loopback path. */
23132 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23135 * Setting of this flag indicates drop action. If this flag is not set,
23136 * then it should be considered accept action.
23138 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
23141 * Setting of this flag indicates that a meter is expected to be attached
23142 * to this flow. This hint can be used when choosing the action record
23143 * format required for the flow.
23145 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
23149 * This bit must be '1' for the l2_filter_id field to be
23152 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
23155 * This bit must be '1' for the ethertype field to be
23158 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
23161 * This bit must be '1' for the tunnel_type field to be
23164 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23167 * This bit must be '1' for the src_macaddr field to be
23170 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23173 * This bit must be '1' for the ipaddr_type field to be
23176 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23179 * This bit must be '1' for the src_ipaddr field to be
23182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23185 * This bit must be '1' for the src_ipaddr_mask field to be
23188 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
23191 * This bit must be '1' for the dst_ipaddr field to be
23194 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
23197 * This bit must be '1' for the dst_ipaddr_mask field to be
23200 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
23203 * This bit must be '1' for the ip_protocol field to be
23206 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23209 * This bit must be '1' for the src_port field to be
23212 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
23215 * This bit must be '1' for the src_port_mask field to be
23218 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
23221 * This bit must be '1' for the dst_port field to be
23224 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
23227 * This bit must be '1' for the dst_port_mask field to be
23230 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
23233 * This bit must be '1' for the pri_hint field to be
23236 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
23239 * This bit must be '1' for the ntuple_filter_id field to be
23242 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
23245 * This bit must be '1' for the dst_id field to be
23248 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23251 * This bit must be '1' for the mirror_vnic_id field to be
23254 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23257 * This bit must be '1' for the dst_macaddr field to be
23260 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
23263 * This value identifies a set of CFA data structures used for an L2
23266 uint64_t l2_filter_id;
23268 * This value indicates the source MAC address in
23269 * the Ethernet header.
23271 uint8_t src_macaddr[6];
23272 /* This value indicates the ethertype in the Ethernet header. */
23273 uint16_t ethertype;
23275 * This value indicates the type of IP address.
23278 * All others are invalid.
23280 uint8_t ip_addr_type;
23282 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
23285 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
23288 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
23290 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23291 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23293 * The value of protocol filed in IP header.
23294 * Applies to UDP and TCP traffic.
23298 uint8_t ip_protocol;
23300 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
23303 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
23306 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
23308 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
23309 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
23311 * If set, this value shall represent the
23312 * Logical VNIC ID of the destination VNIC for the RX
23313 * path and network port id of the destination port for
23318 * Logical VNIC ID of the VNIC where traffic is
23321 uint16_t mirror_vnic_id;
23323 * This value indicates the tunnel type for this filter.
23324 * If this field is not specified, then the filter shall
23325 * apply to both non-tunneled and tunneled packets.
23326 * If this field conflicts with the tunnel_type specified
23327 * in the l2_filter_id, then the HWRM shall return an
23328 * error for this command.
23330 uint8_t tunnel_type;
23332 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23334 /* Virtual eXtensible Local Area Network (VXLAN) */
23335 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23337 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23338 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23340 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23341 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23344 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23346 /* Generic Network Virtualization Encapsulation (Geneve) */
23347 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23349 /* Multi-Protocol Lable Switching (MPLS) */
23350 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23352 /* Stateless Transport Tunnel (STT) */
23353 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23355 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23356 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23358 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23359 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23361 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23362 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23364 /* Use fixed layer 2 ether type of 0xFFFF */
23365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23367 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23368 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23370 /* Any tunneled traffic */
23371 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23373 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23374 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23376 * This hint is provided to help in placing
23377 * the filter in the filter table.
23380 /* No preference */
23381 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
23383 /* Above the given filter */
23384 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
23386 /* Below the given filter */
23387 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
23389 /* As high as possible */
23390 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
23392 /* As low as possible */
23393 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
23395 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
23396 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
23398 * The value of source IP address to be used in filtering.
23399 * For IPv4, first four bytes represent the IP address.
23401 uint32_t src_ipaddr[4];
23403 * The value of source IP address mask to be used in
23405 * For IPv4, first four bytes represent the IP address mask.
23407 uint32_t src_ipaddr_mask[4];
23409 * The value of destination IP address to be used in filtering.
23410 * For IPv4, first four bytes represent the IP address.
23412 uint32_t dst_ipaddr[4];
23414 * The value of destination IP address mask to be used in
23416 * For IPv4, first four bytes represent the IP address mask.
23418 uint32_t dst_ipaddr_mask[4];
23420 * The value of source port to be used in filtering.
23421 * Applies to UDP and TCP traffic.
23425 * The value of source port mask to be used in filtering.
23426 * Applies to UDP and TCP traffic.
23428 uint16_t src_port_mask;
23430 * The value of destination port to be used in filtering.
23431 * Applies to UDP and TCP traffic.
23435 * The value of destination port mask to be used in
23437 * Applies to UDP and TCP traffic.
23439 uint16_t dst_port_mask;
23441 * This is the ID of the filter that goes along with
23444 uint64_t ntuple_filter_id_hint;
23445 } __attribute__((packed));
23447 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
23448 struct hwrm_cfa_ntuple_filter_alloc_output {
23449 /* The specific error status for the command. */
23450 uint16_t error_code;
23451 /* The HWRM command request type. */
23453 /* The sequence ID from the original command. */
23455 /* The length of the response data in number of bytes. */
23457 /* This value is an opaque id into CFA data structures. */
23458 uint64_t ntuple_filter_id;
23460 * This is the ID of the flow associated with this
23462 * This value shall be used to match and associate the
23463 * flow identifier returned in completion records.
23464 * A value of 0xFFFFFFFF shall indicate no flow id.
23467 uint8_t unused_0[3];
23469 * This field is used in Output records to indicate that the output
23470 * is completely written to RAM. This field should be read as '1'
23471 * to indicate that the output has been completely written.
23472 * When writing a command completion or response to an internal processor,
23473 * the order of writes has to be such that this field is written last.
23476 } __attribute__((packed));
23478 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
23479 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
23481 * command specific error codes that goes to
23482 * the cmd_err field in Common HWRM Error Response.
23485 /* Unknown error */
23486 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
23488 /* Unable to complete operation due to conflict with Rx Mask VLAN */
23489 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
23491 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
23492 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
23493 uint8_t unused_0[7];
23494 } __attribute__((packed));
23496 /*******************************
23497 * hwrm_cfa_ntuple_filter_free *
23498 *******************************/
23501 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
23502 struct hwrm_cfa_ntuple_filter_free_input {
23503 /* The HWRM command request type. */
23506 * The completion ring to send the completion event on. This should
23507 * be the NQ ID returned from the `nq_alloc` HWRM command.
23509 uint16_t cmpl_ring;
23511 * The sequence ID is used by the driver for tracking multiple
23512 * commands. This ID is treated as opaque data by the firmware and
23513 * the value is returned in the `hwrm_resp_hdr` upon completion.
23517 * The target ID of the command:
23518 * * 0x0-0xFFF8 - The function ID
23519 * * 0xFFF8-0xFFFE - Reserved for internal processors
23522 uint16_t target_id;
23524 * A physical address pointer pointing to a host buffer that the
23525 * command's response data will be written. This can be either a host
23526 * physical address (HPA) or a guest physical address (GPA) and must
23527 * point to a physically contiguous block of memory.
23529 uint64_t resp_addr;
23530 /* This value is an opaque id into CFA data structures. */
23531 uint64_t ntuple_filter_id;
23532 } __attribute__((packed));
23534 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
23535 struct hwrm_cfa_ntuple_filter_free_output {
23536 /* The specific error status for the command. */
23537 uint16_t error_code;
23538 /* The HWRM command request type. */
23540 /* The sequence ID from the original command. */
23542 /* The length of the response data in number of bytes. */
23544 uint8_t unused_0[7];
23546 * This field is used in Output records to indicate that the output
23547 * is completely written to RAM. This field should be read as '1'
23548 * to indicate that the output has been completely written.
23549 * When writing a command completion or response to an internal processor,
23550 * the order of writes has to be such that this field is written last.
23553 } __attribute__((packed));
23555 /******************************
23556 * hwrm_cfa_ntuple_filter_cfg *
23557 ******************************/
23560 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
23561 struct hwrm_cfa_ntuple_filter_cfg_input {
23562 /* The HWRM command request type. */
23565 * The completion ring to send the completion event on. This should
23566 * be the NQ ID returned from the `nq_alloc` HWRM command.
23568 uint16_t cmpl_ring;
23570 * The sequence ID is used by the driver for tracking multiple
23571 * commands. This ID is treated as opaque data by the firmware and
23572 * the value is returned in the `hwrm_resp_hdr` upon completion.
23576 * The target ID of the command:
23577 * * 0x0-0xFFF8 - The function ID
23578 * * 0xFFF8-0xFFFE - Reserved for internal processors
23581 uint16_t target_id;
23583 * A physical address pointer pointing to a host buffer that the
23584 * command's response data will be written. This can be either a host
23585 * physical address (HPA) or a guest physical address (GPA) and must
23586 * point to a physically contiguous block of memory.
23588 uint64_t resp_addr;
23591 * This bit must be '1' for the new_dst_id field to be
23594 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
23597 * This bit must be '1' for the new_mirror_vnic_id field to be
23600 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
23603 * This bit must be '1' for the new_meter_instance_id field to be
23606 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
23608 uint8_t unused_0[4];
23609 /* This value is an opaque id into CFA data structures. */
23610 uint64_t ntuple_filter_id;
23612 * If set, this value shall represent the new
23613 * Logical VNIC ID of the destination VNIC for the RX
23614 * path and new network port id of the destination port for
23617 uint32_t new_dst_id;
23619 * New Logical VNIC ID of the VNIC where traffic is
23622 uint32_t new_mirror_vnic_id;
23624 * New meter to attach to the flow. Specifying the
23625 * invalid instance ID is used to remove any existing
23626 * meter from the flow.
23628 uint16_t new_meter_instance_id;
23630 * A value of 0xfff is considered invalid and implies the
23631 * instance is not configured.
23633 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
23635 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
23636 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
23637 uint8_t unused_1[6];
23638 } __attribute__((packed));
23640 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
23641 struct hwrm_cfa_ntuple_filter_cfg_output {
23642 /* The specific error status for the command. */
23643 uint16_t error_code;
23644 /* The HWRM command request type. */
23646 /* The sequence ID from the original command. */
23648 /* The length of the response data in number of bytes. */
23650 uint8_t unused_0[7];
23652 * This field is used in Output records to indicate that the output
23653 * is completely written to RAM. This field should be read as '1'
23654 * to indicate that the output has been completely written.
23655 * When writing a command completion or response to an internal processor,
23656 * the order of writes has to be such that this field is written last.
23659 } __attribute__((packed));
23661 /**************************
23662 * hwrm_cfa_em_flow_alloc *
23663 **************************/
23666 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
23667 struct hwrm_cfa_em_flow_alloc_input {
23668 /* The HWRM command request type. */
23671 * The completion ring to send the completion event on. This should
23672 * be the NQ ID returned from the `nq_alloc` HWRM command.
23674 uint16_t cmpl_ring;
23676 * The sequence ID is used by the driver for tracking multiple
23677 * commands. This ID is treated as opaque data by the firmware and
23678 * the value is returned in the `hwrm_resp_hdr` upon completion.
23682 * The target ID of the command:
23683 * * 0x0-0xFFF8 - The function ID
23684 * * 0xFFF8-0xFFFE - Reserved for internal processors
23687 uint16_t target_id;
23689 * A physical address pointer pointing to a host buffer that the
23690 * command's response data will be written. This can be either a host
23691 * physical address (HPA) or a guest physical address (GPA) and must
23692 * point to a physically contiguous block of memory.
23694 uint64_t resp_addr;
23697 * Enumeration denoting the RX, TX type of the resource.
23698 * This enumeration is used for resources that are similar for both
23699 * TX and RX paths of the chip.
23701 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
23703 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
23705 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
23706 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
23707 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
23709 * Setting of this flag indicates enabling of a byte counter for a given
23712 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
23714 * Setting of this flag indicates enabling of a packet counter for a given
23717 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
23718 /* Setting of this flag indicates de-capsulation action for the given flow. */
23719 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
23720 /* Setting of this flag indicates encapsulation action for the given flow. */
23721 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
23723 * Setting of this flag indicates drop action. If this flag is not set,
23724 * then it should be considered accept action.
23726 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
23728 * Setting of this flag indicates that a meter is expected to be attached
23729 * to this flow. This hint can be used when choosing the action record
23730 * format required for the flow.
23732 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
23735 * This bit must be '1' for the l2_filter_id field to be
23738 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
23741 * This bit must be '1' for the tunnel_type field to be
23744 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23747 * This bit must be '1' for the tunnel_id field to be
23750 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
23753 * This bit must be '1' for the src_macaddr field to be
23756 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23759 * This bit must be '1' for the dst_macaddr field to be
23762 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
23765 * This bit must be '1' for the ovlan_vid field to be
23768 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
23771 * This bit must be '1' for the ivlan_vid field to be
23774 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
23777 * This bit must be '1' for the ethertype field to be
23780 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
23783 * This bit must be '1' for the src_ipaddr field to be
23786 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23789 * This bit must be '1' for the dst_ipaddr field to be
23792 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
23795 * This bit must be '1' for the ipaddr_type field to be
23798 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23801 * This bit must be '1' for the ip_protocol field to be
23804 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23807 * This bit must be '1' for the src_port field to be
23810 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
23813 * This bit must be '1' for the dst_port field to be
23816 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
23819 * This bit must be '1' for the dst_id field to be
23822 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
23825 * This bit must be '1' for the mirror_vnic_id field to be
23828 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23831 * This bit must be '1' for the encap_record_id field to be
23834 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
23837 * This bit must be '1' for the meter_instance_id field to be
23840 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
23843 * This value identifies a set of CFA data structures used for an L2
23846 uint64_t l2_filter_id;
23848 uint8_t tunnel_type;
23850 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23852 /* Virtual eXtensible Local Area Network (VXLAN) */
23853 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23855 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23856 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23858 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23859 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23862 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23864 /* Generic Network Virtualization Encapsulation (Geneve) */
23865 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23867 /* Multi-Protocol Lable Switching (MPLS) */
23868 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23870 /* Stateless Transport Tunnel (STT) */
23871 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
23873 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23874 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23876 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23877 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23879 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23880 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23882 /* Use fixed layer 2 ether type of 0xFFFF */
23883 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23885 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23886 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23888 /* Any tunneled traffic */
23889 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23891 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23892 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23893 uint8_t unused_0[3];
23895 * Tunnel identifier.
23896 * Virtual Network Identifier (VNI). Only valid with
23897 * tunnel_types VXLAN, NVGRE, and Geneve.
23898 * Only lower 24-bits of VNI field are used
23899 * in setting up the filter.
23901 uint32_t tunnel_id;
23903 * This value indicates the source MAC address in
23904 * the Ethernet header.
23906 uint8_t src_macaddr[6];
23907 /* The meter instance to attach to the flow. */
23908 uint16_t meter_instance_id;
23910 * A value of 0xfff is considered invalid and implies the
23911 * instance is not configured.
23913 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
23915 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
23916 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
23918 * This value indicates the destination MAC address in
23919 * the Ethernet header.
23921 uint8_t dst_macaddr[6];
23923 * This value indicates the VLAN ID of the outer VLAN tag
23924 * in the Ethernet header.
23926 uint16_t ovlan_vid;
23928 * This value indicates the VLAN ID of the inner VLAN tag
23929 * in the Ethernet header.
23931 uint16_t ivlan_vid;
23932 /* This value indicates the ethertype in the Ethernet header. */
23933 uint16_t ethertype;
23935 * This value indicates the type of IP address.
23938 * All others are invalid.
23940 uint8_t ip_addr_type;
23942 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
23944 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
23946 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
23947 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23950 * The value of protocol filed in IP header.
23951 * Applies to UDP and TCP traffic.
23955 uint8_t ip_protocol;
23957 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
23959 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
23961 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
23962 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
23963 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
23964 uint8_t unused_1[2];
23966 * The value of source IP address to be used in filtering.
23967 * For IPv4, first four bytes represent the IP address.
23969 uint32_t src_ipaddr[4];
23971 * big_endian = True
23972 * The value of destination IP address to be used in filtering.
23973 * For IPv4, first four bytes represent the IP address.
23975 uint32_t dst_ipaddr[4];
23977 * The value of source port to be used in filtering.
23978 * Applies to UDP and TCP traffic.
23982 * The value of destination port to be used in filtering.
23983 * Applies to UDP and TCP traffic.
23987 * If set, this value shall represent the
23988 * Logical VNIC ID of the destination VNIC for the RX
23989 * path and network port id of the destination port for
23994 * Logical VNIC ID of the VNIC where traffic is
23997 uint16_t mirror_vnic_id;
23998 /* Logical ID of the encapsulation record. */
23999 uint32_t encap_record_id;
24000 uint8_t unused_2[4];
24001 } __attribute__((packed));
24003 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
24004 struct hwrm_cfa_em_flow_alloc_output {
24005 /* The specific error status for the command. */
24006 uint16_t error_code;
24007 /* The HWRM command request type. */
24009 /* The sequence ID from the original command. */
24011 /* The length of the response data in number of bytes. */
24013 /* This value is an opaque id into CFA data structures. */
24014 uint64_t em_filter_id;
24016 * This is the ID of the flow associated with this
24018 * This value shall be used to match and associate the
24019 * flow identifier returned in completion records.
24020 * A value of 0xFFFFFFFF shall indicate no flow id.
24023 uint8_t unused_0[3];
24025 * This field is used in Output records to indicate that the output
24026 * is completely written to RAM. This field should be read as '1'
24027 * to indicate that the output has been completely written.
24028 * When writing a command completion or response to an internal processor,
24029 * the order of writes has to be such that this field is written last.
24032 } __attribute__((packed));
24034 /*************************
24035 * hwrm_cfa_em_flow_free *
24036 *************************/
24039 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
24040 struct hwrm_cfa_em_flow_free_input {
24041 /* The HWRM command request type. */
24044 * The completion ring to send the completion event on. This should
24045 * be the NQ ID returned from the `nq_alloc` HWRM command.
24047 uint16_t cmpl_ring;
24049 * The sequence ID is used by the driver for tracking multiple
24050 * commands. This ID is treated as opaque data by the firmware and
24051 * the value is returned in the `hwrm_resp_hdr` upon completion.
24055 * The target ID of the command:
24056 * * 0x0-0xFFF8 - The function ID
24057 * * 0xFFF8-0xFFFE - Reserved for internal processors
24060 uint16_t target_id;
24062 * A physical address pointer pointing to a host buffer that the
24063 * command's response data will be written. This can be either a host
24064 * physical address (HPA) or a guest physical address (GPA) and must
24065 * point to a physically contiguous block of memory.
24067 uint64_t resp_addr;
24068 /* This value is an opaque id into CFA data structures. */
24069 uint64_t em_filter_id;
24070 } __attribute__((packed));
24072 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
24073 struct hwrm_cfa_em_flow_free_output {
24074 /* The specific error status for the command. */
24075 uint16_t error_code;
24076 /* The HWRM command request type. */
24078 /* The sequence ID from the original command. */
24080 /* The length of the response data in number of bytes. */
24082 uint8_t unused_0[7];
24084 * This field is used in Output records to indicate that the output
24085 * is completely written to RAM. This field should be read as '1'
24086 * to indicate that the output has been completely written.
24087 * When writing a command completion or response to an internal processor,
24088 * the order of writes has to be such that this field is written last.
24091 } __attribute__((packed));
24093 /********************************
24094 * hwrm_cfa_meter_profile_alloc *
24095 ********************************/
24098 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
24099 struct hwrm_cfa_meter_profile_alloc_input {
24100 /* The HWRM command request type. */
24103 * The completion ring to send the completion event on. This should
24104 * be the NQ ID returned from the `nq_alloc` HWRM command.
24106 uint16_t cmpl_ring;
24108 * The sequence ID is used by the driver for tracking multiple
24109 * commands. This ID is treated as opaque data by the firmware and
24110 * the value is returned in the `hwrm_resp_hdr` upon completion.
24114 * The target ID of the command:
24115 * * 0x0-0xFFF8 - The function ID
24116 * * 0xFFF8-0xFFFE - Reserved for internal processors
24119 uint16_t target_id;
24121 * A physical address pointer pointing to a host buffer that the
24122 * command's response data will be written. This can be either a host
24123 * physical address (HPA) or a guest physical address (GPA) and must
24124 * point to a physically contiguous block of memory.
24126 uint64_t resp_addr;
24129 * Enumeration denoting the RX, TX type of the resource.
24130 * This enumeration is used for resources that are similar for both
24131 * TX and RX paths of the chip.
24133 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
24135 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
24138 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
24140 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
24141 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
24142 /* The meter algorithm type. */
24143 uint8_t meter_type;
24144 /* RFC 2697 (srTCM) */
24145 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
24147 /* RFC 2698 (trTCM) */
24148 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
24150 /* RFC 4115 (trTCM) */
24151 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
24153 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
24154 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
24156 * This field is reserved for the future use.
24157 * It shall be set to 0.
24159 uint16_t reserved1;
24161 * This field is reserved for the future use.
24162 * It shall be set to 0.
24164 uint32_t reserved2;
24165 /* A meter rate specified in bytes-per-second. */
24166 uint32_t commit_rate;
24167 /* The bandwidth value. */
24168 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
24169 UINT32_C(0xfffffff)
24170 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
24172 /* The granularity of the value (bits or bytes). */
24173 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
24174 UINT32_C(0x10000000)
24175 /* Value is in bits. */
24176 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
24177 (UINT32_C(0x0) << 28)
24178 /* Value is in bytes. */
24179 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
24180 (UINT32_C(0x1) << 28)
24181 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
24182 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
24183 /* bw_value_unit is 3 b */
24184 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
24185 UINT32_C(0xe0000000)
24186 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
24188 /* Value is in Mb or MB (base 10). */
24189 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
24190 (UINT32_C(0x0) << 29)
24191 /* Value is in Kb or KB (base 10). */
24192 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
24193 (UINT32_C(0x2) << 29)
24194 /* Value is in bits or bytes. */
24195 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
24196 (UINT32_C(0x4) << 29)
24197 /* Value is in Gb or GB (base 10). */
24198 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
24199 (UINT32_C(0x6) << 29)
24200 /* Value is in 1/100th of a percentage of total bandwidth. */
24201 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
24202 (UINT32_C(0x1) << 29)
24204 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
24205 (UINT32_C(0x7) << 29)
24206 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
24207 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
24208 /* A meter burst size specified in bytes. */
24209 uint32_t commit_burst;
24210 /* The bandwidth value. */
24211 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
24212 UINT32_C(0xfffffff)
24213 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
24215 /* The granularity of the value (bits or bytes). */
24216 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
24217 UINT32_C(0x10000000)
24218 /* Value is in bits. */
24219 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
24220 (UINT32_C(0x0) << 28)
24221 /* Value is in bytes. */
24222 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
24223 (UINT32_C(0x1) << 28)
24224 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
24225 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
24226 /* bw_value_unit is 3 b */
24227 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
24228 UINT32_C(0xe0000000)
24229 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
24231 /* Value is in Mb or MB (base 10). */
24232 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
24233 (UINT32_C(0x0) << 29)
24234 /* Value is in Kb or KB (base 10). */
24235 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
24236 (UINT32_C(0x2) << 29)
24237 /* Value is in bits or bytes. */
24238 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
24239 (UINT32_C(0x4) << 29)
24240 /* Value is in Gb or GB (base 10). */
24241 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
24242 (UINT32_C(0x6) << 29)
24243 /* Value is in 1/100th of a percentage of total bandwidth. */
24244 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
24245 (UINT32_C(0x1) << 29)
24247 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
24248 (UINT32_C(0x7) << 29)
24249 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
24250 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
24251 /* A meter rate specified in bytes-per-second. */
24252 uint32_t excess_peak_rate;
24253 /* The bandwidth value. */
24254 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
24255 UINT32_C(0xfffffff)
24256 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
24258 /* The granularity of the value (bits or bytes). */
24259 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
24260 UINT32_C(0x10000000)
24261 /* Value is in bits. */
24262 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
24263 (UINT32_C(0x0) << 28)
24264 /* Value is in bytes. */
24265 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
24266 (UINT32_C(0x1) << 28)
24267 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
24268 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
24269 /* bw_value_unit is 3 b */
24270 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
24271 UINT32_C(0xe0000000)
24272 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
24274 /* Value is in Mb or MB (base 10). */
24275 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
24276 (UINT32_C(0x0) << 29)
24277 /* Value is in Kb or KB (base 10). */
24278 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
24279 (UINT32_C(0x2) << 29)
24280 /* Value is in bits or bytes. */
24281 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
24282 (UINT32_C(0x4) << 29)
24283 /* Value is in Gb or GB (base 10). */
24284 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
24285 (UINT32_C(0x6) << 29)
24286 /* Value is in 1/100th of a percentage of total bandwidth. */
24287 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
24288 (UINT32_C(0x1) << 29)
24290 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
24291 (UINT32_C(0x7) << 29)
24292 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
24293 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
24294 /* A meter burst size specified in bytes. */
24295 uint32_t excess_peak_burst;
24296 /* The bandwidth value. */
24297 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
24298 UINT32_C(0xfffffff)
24299 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
24301 /* The granularity of the value (bits or bytes). */
24302 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
24303 UINT32_C(0x10000000)
24304 /* Value is in bits. */
24305 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
24306 (UINT32_C(0x0) << 28)
24307 /* Value is in bytes. */
24308 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
24309 (UINT32_C(0x1) << 28)
24310 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
24311 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
24312 /* bw_value_unit is 3 b */
24313 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
24314 UINT32_C(0xe0000000)
24315 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
24317 /* Value is in Mb or MB (base 10). */
24318 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
24319 (UINT32_C(0x0) << 29)
24320 /* Value is in Kb or KB (base 10). */
24321 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
24322 (UINT32_C(0x2) << 29)
24323 /* Value is in bits or bytes. */
24324 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
24325 (UINT32_C(0x4) << 29)
24326 /* Value is in Gb or GB (base 10). */
24327 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
24328 (UINT32_C(0x6) << 29)
24329 /* Value is in 1/100th of a percentage of total bandwidth. */
24330 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
24331 (UINT32_C(0x1) << 29)
24333 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
24334 (UINT32_C(0x7) << 29)
24335 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
24336 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
24337 } __attribute__((packed));
24339 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
24340 struct hwrm_cfa_meter_profile_alloc_output {
24341 /* The specific error status for the command. */
24342 uint16_t error_code;
24343 /* The HWRM command request type. */
24345 /* The sequence ID from the original command. */
24347 /* The length of the response data in number of bytes. */
24349 /* This value identifies a meter profile in CFA. */
24350 uint16_t meter_profile_id;
24352 * A value of 0xfff is considered invalid and implies the
24353 * profile is not configured.
24355 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
24357 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
24358 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
24359 uint8_t unused_0[5];
24361 * This field is used in Output records to indicate that the output
24362 * is completely written to RAM. This field should be read as '1'
24363 * to indicate that the output has been completely written.
24364 * When writing a command completion or response to an internal processor,
24365 * the order of writes has to be such that this field is written last.
24368 } __attribute__((packed));
24370 /*******************************
24371 * hwrm_cfa_meter_profile_free *
24372 *******************************/
24375 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
24376 struct hwrm_cfa_meter_profile_free_input {
24377 /* The HWRM command request type. */
24380 * The completion ring to send the completion event on. This should
24381 * be the NQ ID returned from the `nq_alloc` HWRM command.
24383 uint16_t cmpl_ring;
24385 * The sequence ID is used by the driver for tracking multiple
24386 * commands. This ID is treated as opaque data by the firmware and
24387 * the value is returned in the `hwrm_resp_hdr` upon completion.
24391 * The target ID of the command:
24392 * * 0x0-0xFFF8 - The function ID
24393 * * 0xFFF8-0xFFFE - Reserved for internal processors
24396 uint16_t target_id;
24398 * A physical address pointer pointing to a host buffer that the
24399 * command's response data will be written. This can be either a host
24400 * physical address (HPA) or a guest physical address (GPA) and must
24401 * point to a physically contiguous block of memory.
24403 uint64_t resp_addr;
24406 * Enumeration denoting the RX, TX type of the resource.
24407 * This enumeration is used for resources that are similar for both
24408 * TX and RX paths of the chip.
24410 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
24412 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
24415 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
24417 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
24418 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
24420 /* This value identifies a meter profile in CFA. */
24421 uint16_t meter_profile_id;
24423 * A value of 0xfff is considered invalid and implies the
24424 * profile is not configured.
24426 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
24428 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
24429 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
24430 uint8_t unused_1[4];
24431 } __attribute__((packed));
24433 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
24434 struct hwrm_cfa_meter_profile_free_output {
24435 /* The specific error status for the command. */
24436 uint16_t error_code;
24437 /* The HWRM command request type. */
24439 /* The sequence ID from the original command. */
24441 /* The length of the response data in number of bytes. */
24443 uint8_t unused_0[7];
24445 * This field is used in Output records to indicate that the output
24446 * is completely written to RAM. This field should be read as '1'
24447 * to indicate that the output has been completely written.
24448 * When writing a command completion or response to an internal processor,
24449 * the order of writes has to be such that this field is written last.
24452 } __attribute__((packed));
24454 /******************************
24455 * hwrm_cfa_meter_profile_cfg *
24456 ******************************/
24459 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
24460 struct hwrm_cfa_meter_profile_cfg_input {
24461 /* The HWRM command request type. */
24464 * The completion ring to send the completion event on. This should
24465 * be the NQ ID returned from the `nq_alloc` HWRM command.
24467 uint16_t cmpl_ring;
24469 * The sequence ID is used by the driver for tracking multiple
24470 * commands. This ID is treated as opaque data by the firmware and
24471 * the value is returned in the `hwrm_resp_hdr` upon completion.
24475 * The target ID of the command:
24476 * * 0x0-0xFFF8 - The function ID
24477 * * 0xFFF8-0xFFFE - Reserved for internal processors
24480 uint16_t target_id;
24482 * A physical address pointer pointing to a host buffer that the
24483 * command's response data will be written. This can be either a host
24484 * physical address (HPA) or a guest physical address (GPA) and must
24485 * point to a physically contiguous block of memory.
24487 uint64_t resp_addr;
24490 * Enumeration denoting the RX, TX type of the resource.
24491 * This enumeration is used for resources that are similar for both
24492 * TX and RX paths of the chip.
24494 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
24496 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24498 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24499 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
24500 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
24501 /* The meter algorithm type. */
24502 uint8_t meter_type;
24503 /* RFC 2697 (srTCM) */
24504 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
24506 /* RFC 2698 (trTCM) */
24507 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
24509 /* RFC 4115 (trTCM) */
24510 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
24512 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
24513 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
24514 /* This value identifies a meter profile in CFA. */
24515 uint16_t meter_profile_id;
24517 * A value of 0xfff is considered invalid and implies the
24518 * profile is not configured.
24520 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
24522 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
24523 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
24525 * This field is reserved for the future use.
24526 * It shall be set to 0.
24529 /* A meter rate specified in bytes-per-second. */
24530 uint32_t commit_rate;
24531 /* The bandwidth value. */
24532 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
24533 UINT32_C(0xfffffff)
24534 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
24536 /* The granularity of the value (bits or bytes). */
24537 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
24538 UINT32_C(0x10000000)
24539 /* Value is in bits. */
24540 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
24541 (UINT32_C(0x0) << 28)
24542 /* Value is in bytes. */
24543 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
24544 (UINT32_C(0x1) << 28)
24545 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
24546 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
24547 /* bw_value_unit is 3 b */
24548 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
24549 UINT32_C(0xe0000000)
24550 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
24552 /* Value is in Mb or MB (base 10). */
24553 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
24554 (UINT32_C(0x0) << 29)
24555 /* Value is in Kb or KB (base 10). */
24556 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
24557 (UINT32_C(0x2) << 29)
24558 /* Value is in bits or bytes. */
24559 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
24560 (UINT32_C(0x4) << 29)
24561 /* Value is in Gb or GB (base 10). */
24562 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
24563 (UINT32_C(0x6) << 29)
24564 /* Value is in 1/100th of a percentage of total bandwidth. */
24565 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
24566 (UINT32_C(0x1) << 29)
24568 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
24569 (UINT32_C(0x7) << 29)
24570 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
24571 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
24572 /* A meter burst size specified in bytes. */
24573 uint32_t commit_burst;
24574 /* The bandwidth value. */
24575 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
24576 UINT32_C(0xfffffff)
24577 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
24579 /* The granularity of the value (bits or bytes). */
24580 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
24581 UINT32_C(0x10000000)
24582 /* Value is in bits. */
24583 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
24584 (UINT32_C(0x0) << 28)
24585 /* Value is in bytes. */
24586 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
24587 (UINT32_C(0x1) << 28)
24588 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
24589 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
24590 /* bw_value_unit is 3 b */
24591 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
24592 UINT32_C(0xe0000000)
24593 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
24595 /* Value is in Mb or MB (base 10). */
24596 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
24597 (UINT32_C(0x0) << 29)
24598 /* Value is in Kb or KB (base 10). */
24599 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
24600 (UINT32_C(0x2) << 29)
24601 /* Value is in bits or bytes. */
24602 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
24603 (UINT32_C(0x4) << 29)
24604 /* Value is in Gb or GB (base 10). */
24605 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
24606 (UINT32_C(0x6) << 29)
24607 /* Value is in 1/100th of a percentage of total bandwidth. */
24608 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
24609 (UINT32_C(0x1) << 29)
24611 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
24612 (UINT32_C(0x7) << 29)
24613 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
24614 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
24615 /* A meter rate specified in bytes-per-second. */
24616 uint32_t excess_peak_rate;
24617 /* The bandwidth value. */
24618 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
24619 UINT32_C(0xfffffff)
24620 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
24622 /* The granularity of the value (bits or bytes). */
24623 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
24624 UINT32_C(0x10000000)
24625 /* Value is in bits. */
24626 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
24627 (UINT32_C(0x0) << 28)
24628 /* Value is in bytes. */
24629 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
24630 (UINT32_C(0x1) << 28)
24631 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
24632 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
24633 /* bw_value_unit is 3 b */
24634 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
24635 UINT32_C(0xe0000000)
24636 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
24638 /* Value is in Mb or MB (base 10). */
24639 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
24640 (UINT32_C(0x0) << 29)
24641 /* Value is in Kb or KB (base 10). */
24642 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
24643 (UINT32_C(0x2) << 29)
24644 /* Value is in bits or bytes. */
24645 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
24646 (UINT32_C(0x4) << 29)
24647 /* Value is in Gb or GB (base 10). */
24648 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
24649 (UINT32_C(0x6) << 29)
24650 /* Value is in 1/100th of a percentage of total bandwidth. */
24651 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
24652 (UINT32_C(0x1) << 29)
24654 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
24655 (UINT32_C(0x7) << 29)
24656 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
24657 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
24658 /* A meter burst size specified in bytes. */
24659 uint32_t excess_peak_burst;
24660 /* The bandwidth value. */
24661 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
24662 UINT32_C(0xfffffff)
24663 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
24665 /* The granularity of the value (bits or bytes). */
24666 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
24667 UINT32_C(0x10000000)
24668 /* Value is in bits. */
24669 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
24670 (UINT32_C(0x0) << 28)
24671 /* Value is in bytes. */
24672 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
24673 (UINT32_C(0x1) << 28)
24674 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
24675 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
24676 /* bw_value_unit is 3 b */
24677 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
24678 UINT32_C(0xe0000000)
24679 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
24681 /* Value is in Mb or MB (base 10). */
24682 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
24683 (UINT32_C(0x0) << 29)
24684 /* Value is in Kb or KB (base 10). */
24685 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
24686 (UINT32_C(0x2) << 29)
24687 /* Value is in bits or bytes. */
24688 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
24689 (UINT32_C(0x4) << 29)
24690 /* Value is in Gb or GB (base 10). */
24691 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
24692 (UINT32_C(0x6) << 29)
24693 /* Value is in 1/100th of a percentage of total bandwidth. */
24694 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
24695 (UINT32_C(0x1) << 29)
24697 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
24698 (UINT32_C(0x7) << 29)
24699 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
24700 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
24701 } __attribute__((packed));
24703 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
24704 struct hwrm_cfa_meter_profile_cfg_output {
24705 /* The specific error status for the command. */
24706 uint16_t error_code;
24707 /* The HWRM command request type. */
24709 /* The sequence ID from the original command. */
24711 /* The length of the response data in number of bytes. */
24713 uint8_t unused_0[7];
24715 * This field is used in Output records to indicate that the output
24716 * is completely written to RAM. This field should be read as '1'
24717 * to indicate that the output has been completely written.
24718 * When writing a command completion or response to an internal processor,
24719 * the order of writes has to be such that this field is written last.
24722 } __attribute__((packed));
24724 /*********************************
24725 * hwrm_cfa_meter_instance_alloc *
24726 *********************************/
24729 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
24730 struct hwrm_cfa_meter_instance_alloc_input {
24731 /* The HWRM command request type. */
24734 * The completion ring to send the completion event on. This should
24735 * be the NQ ID returned from the `nq_alloc` HWRM command.
24737 uint16_t cmpl_ring;
24739 * The sequence ID is used by the driver for tracking multiple
24740 * commands. This ID is treated as opaque data by the firmware and
24741 * the value is returned in the `hwrm_resp_hdr` upon completion.
24745 * The target ID of the command:
24746 * * 0x0-0xFFF8 - The function ID
24747 * * 0xFFF8-0xFFFE - Reserved for internal processors
24750 uint16_t target_id;
24752 * A physical address pointer pointing to a host buffer that the
24753 * command's response data will be written. This can be either a host
24754 * physical address (HPA) or a guest physical address (GPA) and must
24755 * point to a physically contiguous block of memory.
24757 uint64_t resp_addr;
24760 * Enumeration denoting the RX, TX type of the resource.
24761 * This enumeration is used for resources that are similar for both
24762 * TX and RX paths of the chip.
24764 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
24767 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
24770 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
24772 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
24773 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
24775 /* This value identifies a meter profile in CFA. */
24776 uint16_t meter_profile_id;
24778 * A value of 0xfff is considered invalid and implies the
24779 * profile is not configured.
24781 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
24783 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
24784 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
24785 uint8_t unused_1[4];
24786 } __attribute__((packed));
24788 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
24789 struct hwrm_cfa_meter_instance_alloc_output {
24790 /* The specific error status for the command. */
24791 uint16_t error_code;
24792 /* The HWRM command request type. */
24794 /* The sequence ID from the original command. */
24796 /* The length of the response data in number of bytes. */
24798 /* This value identifies a meter instance in CFA. */
24799 uint16_t meter_instance_id;
24801 * A value of 0xfff is considered invalid and implies the
24802 * instance is not configured.
24804 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
24806 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
24807 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
24808 uint8_t unused_0[5];
24810 * This field is used in Output records to indicate that the output
24811 * is completely written to RAM. This field should be read as '1'
24812 * to indicate that the output has been completely written.
24813 * When writing a command completion or response to an internal processor,
24814 * the order of writes has to be such that this field is written last.
24817 } __attribute__((packed));
24819 /********************************
24820 * hwrm_cfa_meter_instance_free *
24821 ********************************/
24824 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
24825 struct hwrm_cfa_meter_instance_free_input {
24826 /* The HWRM command request type. */
24829 * The completion ring to send the completion event on. This should
24830 * be the NQ ID returned from the `nq_alloc` HWRM command.
24832 uint16_t cmpl_ring;
24834 * The sequence ID is used by the driver for tracking multiple
24835 * commands. This ID is treated as opaque data by the firmware and
24836 * the value is returned in the `hwrm_resp_hdr` upon completion.
24840 * The target ID of the command:
24841 * * 0x0-0xFFF8 - The function ID
24842 * * 0xFFF8-0xFFFE - Reserved for internal processors
24845 uint16_t target_id;
24847 * A physical address pointer pointing to a host buffer that the
24848 * command's response data will be written. This can be either a host
24849 * physical address (HPA) or a guest physical address (GPA) and must
24850 * point to a physically contiguous block of memory.
24852 uint64_t resp_addr;
24855 * Enumeration denoting the RX, TX type of the resource.
24856 * This enumeration is used for resources that are similar for both
24857 * TX and RX paths of the chip.
24859 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
24861 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
24864 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
24866 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
24867 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
24869 /* This value identifies a meter instance in CFA. */
24870 uint16_t meter_instance_id;
24872 * A value of 0xfff is considered invalid and implies the
24873 * instance is not configured.
24875 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
24877 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
24878 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
24879 uint8_t unused_1[4];
24880 } __attribute__((packed));
24882 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
24883 struct hwrm_cfa_meter_instance_free_output {
24884 /* The specific error status for the command. */
24885 uint16_t error_code;
24886 /* The HWRM command request type. */
24888 /* The sequence ID from the original command. */
24890 /* The length of the response data in number of bytes. */
24892 uint8_t unused_0[7];
24894 * This field is used in Output records to indicate that the output
24895 * is completely written to RAM. This field should be read as '1'
24896 * to indicate that the output has been completely written.
24897 * When writing a command completion or response to an internal processor,
24898 * the order of writes has to be such that this field is written last.
24901 } __attribute__((packed));
24903 /*******************************
24904 * hwrm_cfa_decap_filter_alloc *
24905 *******************************/
24908 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
24909 struct hwrm_cfa_decap_filter_alloc_input {
24910 /* The HWRM command request type. */
24913 * The completion ring to send the completion event on. This should
24914 * be the NQ ID returned from the `nq_alloc` HWRM command.
24916 uint16_t cmpl_ring;
24918 * The sequence ID is used by the driver for tracking multiple
24919 * commands. This ID is treated as opaque data by the firmware and
24920 * the value is returned in the `hwrm_resp_hdr` upon completion.
24924 * The target ID of the command:
24925 * * 0x0-0xFFF8 - The function ID
24926 * * 0xFFF8-0xFFFE - Reserved for internal processors
24929 uint16_t target_id;
24931 * A physical address pointer pointing to a host buffer that the
24932 * command's response data will be written. This can be either a host
24933 * physical address (HPA) or a guest physical address (GPA) and must
24934 * point to a physically contiguous block of memory.
24936 uint64_t resp_addr;
24938 /* ovs_tunnel is 1 b */
24939 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
24943 * This bit must be '1' for the tunnel_type field to be
24946 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24949 * This bit must be '1' for the tunnel_id field to be
24952 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
24955 * This bit must be '1' for the src_macaddr field to be
24958 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
24961 * This bit must be '1' for the dst_macaddr field to be
24964 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
24967 * This bit must be '1' for the ovlan_vid field to be
24970 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
24973 * This bit must be '1' for the ivlan_vid field to be
24976 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
24979 * This bit must be '1' for the t_ovlan_vid field to be
24982 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
24985 * This bit must be '1' for the t_ivlan_vid field to be
24988 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
24991 * This bit must be '1' for the ethertype field to be
24994 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
24997 * This bit must be '1' for the src_ipaddr field to be
25000 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
25003 * This bit must be '1' for the dst_ipaddr field to be
25006 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
25009 * This bit must be '1' for the ipaddr_type field to be
25012 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25015 * This bit must be '1' for the ip_protocol field to be
25018 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25021 * This bit must be '1' for the src_port field to be
25024 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
25027 * This bit must be '1' for the dst_port field to be
25030 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
25033 * This bit must be '1' for the dst_id field to be
25036 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
25039 * This bit must be '1' for the mirror_vnic_id field to be
25042 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25045 * Tunnel identifier.
25046 * Virtual Network Identifier (VNI). Only valid with
25047 * tunnel_types VXLAN, NVGRE, and Geneve.
25048 * Only lower 24-bits of VNI field are used
25049 * in setting up the filter.
25051 uint32_t tunnel_id;
25053 uint8_t tunnel_type;
25055 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25057 /* Virtual eXtensible Local Area Network (VXLAN) */
25058 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25060 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25061 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25063 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25064 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25067 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25069 /* Generic Network Virtualization Encapsulation (Geneve) */
25070 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25072 /* Multi-Protocol Lable Switching (MPLS) */
25073 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25075 /* Stateless Transport Tunnel (STT) */
25076 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25078 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25079 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25081 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25082 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25084 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25085 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25087 /* Use fixed layer 2 ether type of 0xFFFF */
25088 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25090 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25091 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25093 /* Any tunneled traffic */
25094 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25096 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25097 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25101 * This value indicates the source MAC address in
25102 * the Ethernet header.
25104 uint8_t src_macaddr[6];
25105 uint8_t unused_2[2];
25107 * This value indicates the destination MAC address in
25108 * the Ethernet header.
25110 uint8_t dst_macaddr[6];
25112 * This value indicates the VLAN ID of the outer VLAN tag
25113 * in the Ethernet header.
25115 uint16_t ovlan_vid;
25117 * This value indicates the VLAN ID of the inner VLAN tag
25118 * in the Ethernet header.
25120 uint16_t ivlan_vid;
25122 * This value indicates the VLAN ID of the outer VLAN tag
25123 * in the tunnel Ethernet header.
25125 uint16_t t_ovlan_vid;
25127 * This value indicates the VLAN ID of the inner VLAN tag
25128 * in the tunnel Ethernet header.
25130 uint16_t t_ivlan_vid;
25131 /* This value indicates the ethertype in the Ethernet header. */
25132 uint16_t ethertype;
25134 * This value indicates the type of IP address.
25137 * All others are invalid.
25139 uint8_t ip_addr_type;
25141 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
25144 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
25147 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
25149 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25150 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25152 * The value of protocol filed in IP header.
25153 * Applies to UDP and TCP traffic.
25157 uint8_t ip_protocol;
25159 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
25162 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
25165 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
25167 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
25168 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
25172 * The value of source IP address to be used in filtering.
25173 * For IPv4, first four bytes represent the IP address.
25175 uint32_t src_ipaddr[4];
25177 * The value of destination IP address to be used in filtering.
25178 * For IPv4, first four bytes represent the IP address.
25180 uint32_t dst_ipaddr[4];
25182 * The value of source port to be used in filtering.
25183 * Applies to UDP and TCP traffic.
25187 * The value of destination port to be used in filtering.
25188 * Applies to UDP and TCP traffic.
25192 * If set, this value shall represent the
25193 * Logical VNIC ID of the destination VNIC for the RX
25198 * If set, this value shall represent the L2 context that matches the L2
25199 * information of the decap filter.
25201 uint16_t l2_ctxt_ref_id;
25202 } __attribute__((packed));
25204 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
25205 struct hwrm_cfa_decap_filter_alloc_output {
25206 /* The specific error status for the command. */
25207 uint16_t error_code;
25208 /* The HWRM command request type. */
25210 /* The sequence ID from the original command. */
25212 /* The length of the response data in number of bytes. */
25214 /* This value is an opaque id into CFA data structures. */
25215 uint32_t decap_filter_id;
25216 uint8_t unused_0[3];
25218 * This field is used in Output records to indicate that the output
25219 * is completely written to RAM. This field should be read as '1'
25220 * to indicate that the output has been completely written.
25221 * When writing a command completion or response to an internal processor,
25222 * the order of writes has to be such that this field is written last.
25225 } __attribute__((packed));
25227 /******************************
25228 * hwrm_cfa_decap_filter_free *
25229 ******************************/
25232 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
25233 struct hwrm_cfa_decap_filter_free_input {
25234 /* The HWRM command request type. */
25237 * The completion ring to send the completion event on. This should
25238 * be the NQ ID returned from the `nq_alloc` HWRM command.
25240 uint16_t cmpl_ring;
25242 * The sequence ID is used by the driver for tracking multiple
25243 * commands. This ID is treated as opaque data by the firmware and
25244 * the value is returned in the `hwrm_resp_hdr` upon completion.
25248 * The target ID of the command:
25249 * * 0x0-0xFFF8 - The function ID
25250 * * 0xFFF8-0xFFFE - Reserved for internal processors
25253 uint16_t target_id;
25255 * A physical address pointer pointing to a host buffer that the
25256 * command's response data will be written. This can be either a host
25257 * physical address (HPA) or a guest physical address (GPA) and must
25258 * point to a physically contiguous block of memory.
25260 uint64_t resp_addr;
25261 /* This value is an opaque id into CFA data structures. */
25262 uint32_t decap_filter_id;
25263 uint8_t unused_0[4];
25264 } __attribute__((packed));
25266 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
25267 struct hwrm_cfa_decap_filter_free_output {
25268 /* The specific error status for the command. */
25269 uint16_t error_code;
25270 /* The HWRM command request type. */
25272 /* The sequence ID from the original command. */
25274 /* The length of the response data in number of bytes. */
25276 uint8_t unused_0[7];
25278 * This field is used in Output records to indicate that the output
25279 * is completely written to RAM. This field should be read as '1'
25280 * to indicate that the output has been completely written.
25281 * When writing a command completion or response to an internal processor,
25282 * the order of writes has to be such that this field is written last.
25285 } __attribute__((packed));
25287 /***********************
25288 * hwrm_cfa_flow_alloc *
25289 ***********************/
25292 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
25293 struct hwrm_cfa_flow_alloc_input {
25294 /* The HWRM command request type. */
25297 * The completion ring to send the completion event on. This should
25298 * be the NQ ID returned from the `nq_alloc` HWRM command.
25300 uint16_t cmpl_ring;
25302 * The sequence ID is used by the driver for tracking multiple
25303 * commands. This ID is treated as opaque data by the firmware and
25304 * the value is returned in the `hwrm_resp_hdr` upon completion.
25308 * The target ID of the command:
25309 * * 0x0-0xFFF8 - The function ID
25310 * * 0xFFF8-0xFFFE - Reserved for internal processors
25313 uint16_t target_id;
25315 * A physical address pointer pointing to a host buffer that the
25316 * command's response data will be written. This can be either a host
25317 * physical address (HPA) or a guest physical address (GPA) and must
25318 * point to a physically contiguous block of memory.
25320 uint64_t resp_addr;
25322 /* tunnel is 1 b */
25323 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
25325 /* num_vlan is 2 b */
25326 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
25328 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
25330 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
25331 (UINT32_C(0x0) << 1)
25333 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
25334 (UINT32_C(0x1) << 1)
25336 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
25337 (UINT32_C(0x2) << 1)
25338 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
25339 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
25340 /* Enumeration denoting the Flow Type. */
25341 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
25343 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
25345 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
25346 (UINT32_C(0x0) << 3)
25348 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
25349 (UINT32_C(0x1) << 3)
25351 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
25352 (UINT32_C(0x2) << 3)
25353 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
25354 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
25356 * when set to 1, indicates TX flow offload for function specified in src_fid and
25357 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
25358 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
25359 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
25360 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
25361 * belong to the children VFs of the same PF to indicate VM to VM flow.
25363 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
25366 * when set to 1, indicates RX flow offload for function specified in dst_fid and
25367 * the src_fid should be set to invalid value.
25369 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
25372 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
25373 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
25374 * This flag is only valid when the flow direction is RX.
25376 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
25383 /* Tunnel handle valid when tunnel flag is set. */
25384 uint32_t tunnel_handle;
25385 uint16_t action_flags;
25387 * Setting of this flag indicates drop action. If this flag is not set,
25388 * then it should be considered accept action.
25390 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
25392 /* recycle is 1 b */
25393 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
25396 * Setting of this flag indicates drop action. If this flag is not set,
25397 * then it should be considered accept action.
25399 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
25402 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
25404 /* tunnel is 1 b */
25405 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
25407 /* nat_src is 1 b */
25408 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
25410 /* nat_dest is 1 b */
25411 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
25413 /* nat_ipv4_address is 1 b */
25414 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
25416 /* l2_header_rewrite is 1 b */
25417 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
25419 /* ttl_decrement is 1 b */
25420 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
25423 * If set to 1 and flow direction is TX, it indicates decap of L2 header
25424 * and encap of tunnel header. If set to 1 and flow direction is RX, it
25425 * indicates decap of tunnel header and encap L2 header. The type of tunnel
25426 * is specified in the tunnel_type field.
25428 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
25430 /* If set to 1, flow aging is enabled for this flow. */
25431 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
25434 * Tx Flow: pf or vf fid.
25438 /* VLAN tpid, valid when push_vlan flag is set. */
25439 uint16_t l2_rewrite_vlan_tpid;
25440 /* VLAN tci, valid when push_vlan flag is set. */
25441 uint16_t l2_rewrite_vlan_tci;
25442 /* Meter id, valid when meter flag is set. */
25443 uint16_t act_meter_id;
25444 /* Flow with the same l2 context tcam key. */
25445 uint16_t ref_flow_handle;
25446 /* This value sets the match value for the ethertype. */
25447 uint16_t ethertype;
25448 /* valid when num tags is 1 or 2. */
25449 uint16_t outer_vlan_tci;
25450 /* This value sets the match value for the Destination MAC address. */
25452 /* valid when num tags is 2. */
25453 uint16_t inner_vlan_tci;
25454 /* This value sets the match value for the Source MAC address. */
25456 /* The bit length of destination IP address mask. */
25457 uint8_t ip_dst_mask_len;
25458 /* The bit length of source IP address mask. */
25459 uint8_t ip_src_mask_len;
25460 /* The value of destination IPv4/IPv6 address. */
25461 uint32_t ip_dst[4];
25462 /* The source IPv4/IPv6 address. */
25463 uint32_t ip_src[4];
25465 * The value of source port.
25466 * Applies to UDP and TCP traffic.
25468 uint16_t l4_src_port;
25470 * The value of source port mask.
25471 * Applies to UDP and TCP traffic.
25473 uint16_t l4_src_port_mask;
25475 * The value of destination port.
25476 * Applies to UDP and TCP traffic.
25478 uint16_t l4_dst_port;
25480 * The value of destination port mask.
25481 * Applies to UDP and TCP traffic.
25483 uint16_t l4_dst_port_mask;
25485 * NAT IPv4/6 address based on address type flag.
25486 * 0 values are ignored.
25488 uint32_t nat_ip_address[4];
25489 /* L2 header re-write Destination MAC address. */
25490 uint16_t l2_rewrite_dmac[3];
25492 * The NAT source/destination port based on direction flag.
25493 * Applies to UDP and TCP traffic.
25494 * 0 values are ignored.
25497 /* L2 header re-write Source MAC address. */
25498 uint16_t l2_rewrite_smac[3];
25499 /* The value of ip protocol. */
25502 uint8_t tunnel_type;
25504 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25506 /* Virtual eXtensible Local Area Network (VXLAN) */
25507 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25509 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25510 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25512 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25513 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25516 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25518 /* Generic Network Virtualization Encapsulation (Geneve) */
25519 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25521 /* Multi-Protocol Lable Switching (MPLS) */
25522 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25524 /* Stateless Transport Tunnel (STT) */
25525 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
25527 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25528 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25530 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25531 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25533 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25534 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25536 /* Use fixed layer 2 ether type of 0xFFFF */
25537 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25539 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25540 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25542 /* Any tunneled traffic */
25543 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25545 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25546 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25547 } __attribute__((packed));
25549 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
25550 struct hwrm_cfa_flow_alloc_output {
25551 /* The specific error status for the command. */
25552 uint16_t error_code;
25553 /* The HWRM command request type. */
25555 /* The sequence ID from the original command. */
25557 /* The length of the response data in number of bytes. */
25559 /* Flow record index. */
25560 uint16_t flow_handle;
25561 uint8_t unused_0[2];
25563 * This is the ID of the flow associated with this
25565 * This value shall be used to match and associate the
25566 * flow identifier returned in completion records.
25567 * A value of 0xFFFFFFFF shall indicate no flow id.
25570 /* This value identifies a set of CFA data structures used for a flow. */
25571 uint64_t ext_flow_handle;
25572 uint8_t unused_1[7];
25574 * This field is used in Output records to indicate that the output
25575 * is completely written to RAM. This field should be read as '1'
25576 * to indicate that the output has been completely written.
25577 * When writing a command completion or response to an internal processor,
25578 * the order of writes has to be such that this field is written last.
25581 } __attribute__((packed));
25583 /**********************
25584 * hwrm_cfa_flow_free *
25585 **********************/
25588 /* hwrm_cfa_flow_free_input (size:256b/32B) */
25589 struct hwrm_cfa_flow_free_input {
25590 /* The HWRM command request type. */
25593 * The completion ring to send the completion event on. This should
25594 * be the NQ ID returned from the `nq_alloc` HWRM command.
25596 uint16_t cmpl_ring;
25598 * The sequence ID is used by the driver for tracking multiple
25599 * commands. This ID is treated as opaque data by the firmware and
25600 * the value is returned in the `hwrm_resp_hdr` upon completion.
25604 * The target ID of the command:
25605 * * 0x0-0xFFF8 - The function ID
25606 * * 0xFFF8-0xFFFE - Reserved for internal processors
25609 uint16_t target_id;
25611 * A physical address pointer pointing to a host buffer that the
25612 * command's response data will be written. This can be either a host
25613 * physical address (HPA) or a guest physical address (GPA) and must
25614 * point to a physically contiguous block of memory.
25616 uint64_t resp_addr;
25617 /* Flow record index. */
25618 uint16_t flow_handle;
25619 uint8_t unused_0[6];
25620 /* This value identifies a set of CFA data structures used for a flow. */
25621 uint64_t ext_flow_handle;
25622 } __attribute__((packed));
25624 /* hwrm_cfa_flow_free_output (size:256b/32B) */
25625 struct hwrm_cfa_flow_free_output {
25626 /* The specific error status for the command. */
25627 uint16_t error_code;
25628 /* The HWRM command request type. */
25630 /* The sequence ID from the original command. */
25632 /* The length of the response data in number of bytes. */
25634 /* packet is 64 b */
25638 uint8_t unused_0[7];
25640 * This field is used in Output records to indicate that the output
25641 * is completely written to RAM. This field should be read as '1'
25642 * to indicate that the output has been completely written.
25643 * When writing a command completion or response to an internal processor,
25644 * the order of writes has to be such that this field is written last.
25647 } __attribute__((packed));
25649 /**********************
25650 * hwrm_cfa_flow_info *
25651 **********************/
25654 /* hwrm_cfa_flow_info_input (size:256b/32B) */
25655 struct hwrm_cfa_flow_info_input {
25656 /* The HWRM command request type. */
25659 * The completion ring to send the completion event on. This should
25660 * be the NQ ID returned from the `nq_alloc` HWRM command.
25662 uint16_t cmpl_ring;
25664 * The sequence ID is used by the driver for tracking multiple
25665 * commands. This ID is treated as opaque data by the firmware and
25666 * the value is returned in the `hwrm_resp_hdr` upon completion.
25670 * The target ID of the command:
25671 * * 0x0-0xFFF8 - The function ID
25672 * * 0xFFF8-0xFFFE - Reserved for internal processors
25675 uint16_t target_id;
25677 * A physical address pointer pointing to a host buffer that the
25678 * command's response data will be written. This can be either a host
25679 * physical address (HPA) or a guest physical address (GPA) and must
25680 * point to a physically contiguous block of memory.
25682 uint64_t resp_addr;
25683 /* Flow record index. */
25684 uint16_t flow_handle;
25685 /* Max flow handle */
25686 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
25688 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
25689 /* CNP flow handle */
25690 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
25692 /* RoCEv1 flow handle */
25693 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
25695 /* RoCEv2 flow handle */
25696 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
25698 /* Direction rx = 1 */
25699 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
25701 uint8_t unused_0[6];
25702 /* This value identifies a set of CFA data structures used for a flow. */
25703 uint64_t ext_flow_handle;
25704 } __attribute__((packed));
25706 /* hwrm_cfa_flow_info_output (size:448b/56B) */
25707 struct hwrm_cfa_flow_info_output {
25708 /* The specific error status for the command. */
25709 uint16_t error_code;
25710 /* The HWRM command request type. */
25712 /* The sequence ID from the original command. */
25714 /* The length of the response data in number of bytes. */
25718 /* profile is 8 b */
25720 /* src_fid is 16 b */
25722 /* dst_fid is 16 b */
25724 /* l2_ctxt_id is 16 b */
25725 uint16_t l2_ctxt_id;
25726 /* em_info is 64 b */
25728 /* tcam_info is 64 b */
25729 uint64_t tcam_info;
25730 /* vfp_tcam_info is 64 b */
25731 uint64_t vfp_tcam_info;
25732 /* ar_id is 16 b */
25734 /* flow_handle is 16 b */
25735 uint16_t flow_handle;
25736 /* tunnel_handle is 32 b */
25737 uint32_t tunnel_handle;
25738 /* The flow aging timer for the flow, the unit is 100 milliseconds */
25739 uint16_t flow_timer;
25740 uint8_t unused_0[5];
25742 * This field is used in Output records to indicate that the output
25743 * is completely written to RAM. This field should be read as '1'
25744 * to indicate that the output has been completely written.
25745 * When writing a command completion or response to an internal processor,
25746 * the order of writes has to be such that this field is written last.
25749 } __attribute__((packed));
25751 /***********************
25752 * hwrm_cfa_flow_flush *
25753 ***********************/
25756 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
25757 struct hwrm_cfa_flow_flush_input {
25758 /* The HWRM command request type. */
25761 * The completion ring to send the completion event on. This should
25762 * be the NQ ID returned from the `nq_alloc` HWRM command.
25764 uint16_t cmpl_ring;
25766 * The sequence ID is used by the driver for tracking multiple
25767 * commands. This ID is treated as opaque data by the firmware and
25768 * the value is returned in the `hwrm_resp_hdr` upon completion.
25772 * The target ID of the command:
25773 * * 0x0-0xFFF8 - The function ID
25774 * * 0xFFF8-0xFFFE - Reserved for internal processors
25777 uint16_t target_id;
25779 * A physical address pointer pointing to a host buffer that the
25780 * command's response data will be written. This can be either a host
25781 * physical address (HPA) or a guest physical address (GPA) and must
25782 * point to a physically contiguous block of memory.
25784 uint64_t resp_addr;
25786 uint8_t unused_0[4];
25787 } __attribute__((packed));
25789 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
25790 struct hwrm_cfa_flow_flush_output {
25791 /* The specific error status for the command. */
25792 uint16_t error_code;
25793 /* The HWRM command request type. */
25795 /* The sequence ID from the original command. */
25797 /* The length of the response data in number of bytes. */
25799 uint8_t unused_0[7];
25801 * This field is used in Output records to indicate that the output
25802 * is completely written to RAM. This field should be read as '1'
25803 * to indicate that the output has been completely written.
25804 * When writing a command completion or response to an internal processor,
25805 * the order of writes has to be such that this field is written last.
25808 } __attribute__((packed));
25810 /***********************
25811 * hwrm_cfa_flow_stats *
25812 ***********************/
25815 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
25816 struct hwrm_cfa_flow_stats_input {
25817 /* The HWRM command request type. */
25820 * The completion ring to send the completion event on. This should
25821 * be the NQ ID returned from the `nq_alloc` HWRM command.
25823 uint16_t cmpl_ring;
25825 * The sequence ID is used by the driver for tracking multiple
25826 * commands. This ID is treated as opaque data by the firmware and
25827 * the value is returned in the `hwrm_resp_hdr` upon completion.
25831 * The target ID of the command:
25832 * * 0x0-0xFFF8 - The function ID
25833 * * 0xFFF8-0xFFFE - Reserved for internal processors
25836 uint16_t target_id;
25838 * A physical address pointer pointing to a host buffer that the
25839 * command's response data will be written. This can be either a host
25840 * physical address (HPA) or a guest physical address (GPA) and must
25841 * point to a physically contiguous block of memory.
25843 uint64_t resp_addr;
25845 uint16_t num_flows;
25847 uint16_t flow_handle_0;
25849 uint16_t flow_handle_1;
25851 uint16_t flow_handle_2;
25853 uint16_t flow_handle_3;
25855 uint16_t flow_handle_4;
25857 uint16_t flow_handle_5;
25859 uint16_t flow_handle_6;
25861 uint16_t flow_handle_7;
25863 uint16_t flow_handle_8;
25865 uint16_t flow_handle_9;
25866 uint8_t unused_0[2];
25867 /* Flow ID of a flow. */
25868 uint32_t flow_id_0;
25869 /* Flow ID of a flow. */
25870 uint32_t flow_id_1;
25871 /* Flow ID of a flow. */
25872 uint32_t flow_id_2;
25873 /* Flow ID of a flow. */
25874 uint32_t flow_id_3;
25875 /* Flow ID of a flow. */
25876 uint32_t flow_id_4;
25877 /* Flow ID of a flow. */
25878 uint32_t flow_id_5;
25879 /* Flow ID of a flow. */
25880 uint32_t flow_id_6;
25881 /* Flow ID of a flow. */
25882 uint32_t flow_id_7;
25883 /* Flow ID of a flow. */
25884 uint32_t flow_id_8;
25885 /* Flow ID of a flow. */
25886 uint32_t flow_id_9;
25887 } __attribute__((packed));
25889 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
25890 struct hwrm_cfa_flow_stats_output {
25891 /* The specific error status for the command. */
25892 uint16_t error_code;
25893 /* The HWRM command request type. */
25895 /* The sequence ID from the original command. */
25897 /* The length of the response data in number of bytes. */
25899 /* packet_0 is 64 b */
25901 /* packet_1 is 64 b */
25903 /* packet_2 is 64 b */
25905 /* packet_3 is 64 b */
25907 /* packet_4 is 64 b */
25909 /* packet_5 is 64 b */
25911 /* packet_6 is 64 b */
25913 /* packet_7 is 64 b */
25915 /* packet_8 is 64 b */
25917 /* packet_9 is 64 b */
25919 /* byte_0 is 64 b */
25921 /* byte_1 is 64 b */
25923 /* byte_2 is 64 b */
25925 /* byte_3 is 64 b */
25927 /* byte_4 is 64 b */
25929 /* byte_5 is 64 b */
25931 /* byte_6 is 64 b */
25933 /* byte_7 is 64 b */
25935 /* byte_8 is 64 b */
25937 /* byte_9 is 64 b */
25939 uint8_t unused_0[7];
25941 * This field is used in Output records to indicate that the output
25942 * is completely written to RAM. This field should be read as '1'
25943 * to indicate that the output has been completely written.
25944 * When writing a command completion or response to an internal processor,
25945 * the order of writes has to be such that this field is written last.
25948 } __attribute__((packed));
25950 /***********************************
25951 * hwrm_cfa_flow_aging_timer_reset *
25952 ***********************************/
25955 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
25956 struct hwrm_cfa_flow_aging_timer_reset_input {
25957 /* The HWRM command request type. */
25960 * The completion ring to send the completion event on. This should
25961 * be the NQ ID returned from the `nq_alloc` HWRM command.
25963 uint16_t cmpl_ring;
25965 * The sequence ID is used by the driver for tracking multiple
25966 * commands. This ID is treated as opaque data by the firmware and
25967 * the value is returned in the `hwrm_resp_hdr` upon completion.
25971 * The target ID of the command:
25972 * * 0x0-0xFFF8 - The function ID
25973 * * 0xFFF8-0xFFFE - Reserved for internal processors
25976 uint16_t target_id;
25978 * A physical address pointer pointing to a host buffer that the
25979 * command's response data will be written. This can be either a host
25980 * physical address (HPA) or a guest physical address (GPA) and must
25981 * point to a physically contiguous block of memory.
25983 uint64_t resp_addr;
25984 /* Flow record index. */
25985 uint16_t flow_handle;
25986 uint8_t unused_0[6];
25987 /* This value identifies a set of CFA data structures used for a flow. */
25988 uint64_t ext_flow_handle;
25989 } __attribute__((packed));
25991 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
25992 struct hwrm_cfa_flow_aging_timer_reset_output {
25993 /* The specific error status for the command. */
25994 uint16_t error_code;
25995 /* The HWRM command request type. */
25997 /* The sequence ID from the original command. */
25999 /* The length of the response data in number of bytes. */
26001 uint8_t unused_0[7];
26003 * This field is used in Output records to indicate that the output
26004 * is completely written to RAM. This field should be read as '1'
26005 * to indicate that the output has been completely written.
26006 * When writing a command completion or response to an internal processor,
26007 * the order of writes has to be such that this field is written last.
26010 } __attribute__((packed));
26012 /***************************
26013 * hwrm_cfa_flow_aging_cfg *
26014 ***************************/
26017 /* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
26018 struct hwrm_cfa_flow_aging_cfg_input {
26019 /* The HWRM command request type. */
26022 * The completion ring to send the completion event on. This should
26023 * be the NQ ID returned from the `nq_alloc` HWRM command.
26025 uint16_t cmpl_ring;
26027 * The sequence ID is used by the driver for tracking multiple
26028 * commands. This ID is treated as opaque data by the firmware and
26029 * the value is returned in the `hwrm_resp_hdr` upon completion.
26033 * The target ID of the command:
26034 * * 0x0-0xFFF8 - The function ID
26035 * * 0xFFF8-0xFFFE - Reserved for internal processors
26038 uint16_t target_id;
26040 * A physical address pointer pointing to a host buffer that the
26041 * command's response data will be written. This can be either a host
26042 * physical address (HPA) or a guest physical address (GPA) and must
26043 * point to a physically contiguous block of memory.
26045 uint64_t resp_addr;
26046 /* The bit field to enable per flow aging configuration. */
26048 /* This bit must be '1' for the tcp flow timer field to be configured */
26049 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
26051 /* This bit must be '1' for the tcp finish timer field to be configured */
26052 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
26054 /* This bit must be '1' for the udp flow timer field to be configured */
26055 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
26057 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
26059 /* Enumeration denoting the RX, TX type of the resource. */
26060 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26062 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26064 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26065 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
26066 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
26068 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
26069 uint32_t tcp_flow_timer;
26070 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
26071 uint32_t tcp_fin_timer;
26072 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
26073 uint32_t udp_flow_timer;
26074 } __attribute__((packed));
26076 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
26077 struct hwrm_cfa_flow_aging_cfg_output {
26078 /* The specific error status for the command. */
26079 uint16_t error_code;
26080 /* The HWRM command request type. */
26082 /* The sequence ID from the original command. */
26084 /* The length of the response data in number of bytes. */
26086 uint8_t unused_0[7];
26088 * This field is used in Output records to indicate that the output
26089 * is completely written to RAM. This field should be read as '1'
26090 * to indicate that the output has been completely written.
26091 * When writing a command completion or response to an internal processor,
26092 * the order of writes has to be such that this field is written last.
26095 } __attribute__((packed));
26097 /****************************
26098 * hwrm_cfa_flow_aging_qcfg *
26099 ****************************/
26102 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
26103 struct hwrm_cfa_flow_aging_qcfg_input {
26104 /* The HWRM command request type. */
26107 * The completion ring to send the completion event on. This should
26108 * be the NQ ID returned from the `nq_alloc` HWRM command.
26110 uint16_t cmpl_ring;
26112 * The sequence ID is used by the driver for tracking multiple
26113 * commands. This ID is treated as opaque data by the firmware and
26114 * the value is returned in the `hwrm_resp_hdr` upon completion.
26118 * The target ID of the command:
26119 * * 0x0-0xFFF8 - The function ID
26120 * * 0xFFF8-0xFFFE - Reserved for internal processors
26123 uint16_t target_id;
26125 * A physical address pointer pointing to a host buffer that the
26126 * command's response data will be written. This can be either a host
26127 * physical address (HPA) or a guest physical address (GPA) and must
26128 * point to a physically contiguous block of memory.
26130 uint64_t resp_addr;
26131 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
26133 /* Enumeration denoting the RX, TX type of the resource. */
26134 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26136 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26138 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26139 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
26140 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
26141 uint8_t unused_0[7];
26142 } __attribute__((packed));
26144 /* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
26145 struct hwrm_cfa_flow_aging_qcfg_output {
26146 /* The specific error status for the command. */
26147 uint16_t error_code;
26148 /* The HWRM command request type. */
26150 /* The sequence ID from the original command. */
26152 /* The length of the response data in number of bytes. */
26154 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
26155 uint32_t tcp_flow_timer;
26156 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
26157 uint32_t tcp_fin_timer;
26158 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
26159 uint32_t udp_flow_timer;
26160 uint8_t unused_0[3];
26162 * This field is used in Output records to indicate that the output
26163 * is completely written to RAM. This field should be read as '1'
26164 * to indicate that the output has been completely written.
26165 * When writing a command completion or response to an internal processor,
26166 * the order of writes has to be such that this field is written last.
26169 } __attribute__((packed));
26171 /*****************************
26172 * hwrm_cfa_flow_aging_qcaps *
26173 *****************************/
26176 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
26177 struct hwrm_cfa_flow_aging_qcaps_input {
26178 /* The HWRM command request type. */
26181 * The completion ring to send the completion event on. This should
26182 * be the NQ ID returned from the `nq_alloc` HWRM command.
26184 uint16_t cmpl_ring;
26186 * The sequence ID is used by the driver for tracking multiple
26187 * commands. This ID is treated as opaque data by the firmware and
26188 * the value is returned in the `hwrm_resp_hdr` upon completion.
26192 * The target ID of the command:
26193 * * 0x0-0xFFF8 - The function ID
26194 * * 0xFFF8-0xFFFE - Reserved for internal processors
26197 uint16_t target_id;
26199 * A physical address pointer pointing to a host buffer that the
26200 * command's response data will be written. This can be either a host
26201 * physical address (HPA) or a guest physical address (GPA) and must
26202 * point to a physically contiguous block of memory.
26204 uint64_t resp_addr;
26205 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
26207 /* Enumeration denoting the RX, TX type of the resource. */
26208 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
26210 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26212 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26213 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
26214 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
26215 uint8_t unused_0[7];
26216 } __attribute__((packed));
26218 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
26219 struct hwrm_cfa_flow_aging_qcaps_output {
26220 /* The specific error status for the command. */
26221 uint16_t error_code;
26222 /* The HWRM command request type. */
26224 /* The sequence ID from the original command. */
26226 /* The length of the response data in number of bytes. */
26228 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
26229 uint32_t max_tcp_flow_timer;
26230 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
26231 uint32_t max_tcp_fin_timer;
26232 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
26233 uint32_t max_udp_flow_timer;
26234 /* The maximum aging flows that HW can support. */
26235 uint32_t max_aging_flows;
26236 uint8_t unused_0[7];
26238 * This field is used in Output records to indicate that the output
26239 * is completely written to RAM. This field should be read as '1'
26240 * to indicate that the output has been completely written.
26241 * When writing a command completion or response to an internal processor,
26242 * the order of writes has to be such that this field is written last.
26245 } __attribute__((packed));
26247 /**********************
26248 * hwrm_cfa_pair_info *
26249 **********************/
26252 /* hwrm_cfa_pair_info_input (size:448b/56B) */
26253 struct hwrm_cfa_pair_info_input {
26254 /* The HWRM command request type. */
26257 * The completion ring to send the completion event on. This should
26258 * be the NQ ID returned from the `nq_alloc` HWRM command.
26260 uint16_t cmpl_ring;
26262 * The sequence ID is used by the driver for tracking multiple
26263 * commands. This ID is treated as opaque data by the firmware and
26264 * the value is returned in the `hwrm_resp_hdr` upon completion.
26268 * The target ID of the command:
26269 * * 0x0-0xFFF8 - The function ID
26270 * * 0xFFF8-0xFFFE - Reserved for internal processors
26273 uint16_t target_id;
26275 * A physical address pointer pointing to a host buffer that the
26276 * command's response data will be written. This can be either a host
26277 * physical address (HPA) or a guest physical address (GPA) and must
26278 * point to a physically contiguous block of memory.
26280 uint64_t resp_addr;
26282 /* If this flag is set, lookup by name else lookup by index. */
26283 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
26284 /* If this flag is set, lookup by PF id and VF id. */
26285 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
26286 /* Pair table index. */
26287 uint16_t pair_index;
26288 /* Pair pf index. */
26290 /* Pair vf index. */
26292 /* Pair name (32 byte string). */
26293 char pair_name[32];
26294 } __attribute__((packed));
26296 /* hwrm_cfa_pair_info_output (size:576b/72B) */
26297 struct hwrm_cfa_pair_info_output {
26298 /* The specific error status for the command. */
26299 uint16_t error_code;
26300 /* The HWRM command request type. */
26302 /* The sequence ID from the original command. */
26304 /* The length of the response data in number of bytes. */
26306 /* Pair table index. */
26307 uint16_t next_pair_index;
26308 /* Pair member a's fid. */
26310 /* Logical host number. */
26311 uint8_t host_a_index;
26312 /* Logical PF number. */
26313 uint8_t pf_a_index;
26314 /* Pair member a's Linux logical VF number. */
26315 uint16_t vf_a_index;
26317 uint16_t rx_cfa_code_a;
26318 /* Tx CFA action. */
26319 uint16_t tx_cfa_action_a;
26320 /* Pair member b's fid. */
26322 /* Logical host number. */
26323 uint8_t host_b_index;
26324 /* Logical PF number. */
26325 uint8_t pf_b_index;
26326 /* Pair member a's Linux logical VF number. */
26327 uint16_t vf_b_index;
26329 uint16_t rx_cfa_code_b;
26330 /* Tx CFA action. */
26331 uint16_t tx_cfa_action_b;
26332 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
26334 /* Pair between VF on local host with PF or VF on specified host. */
26335 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
26336 /* Pair between REP on local host with PF or VF on specified host. */
26337 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
26338 /* Pair between REP on local host with REP on specified host. */
26339 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
26340 /* Pair for the proxy interface. */
26341 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
26342 /* Pair for the PF interface. */
26343 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
26344 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
26345 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
26347 uint8_t pair_state;
26348 /* Pair has been allocated */
26349 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
26350 /* Both pair members are active */
26351 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
26352 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
26353 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
26354 /* Pair name (32 byte string). */
26355 char pair_name[32];
26356 uint8_t unused_0[7];
26358 * This field is used in Output records to indicate that the output
26359 * is completely written to RAM. This field should be read as '1'
26360 * to indicate that the output has been completely written.
26361 * When writing a command completion or response to an internal processor,
26362 * the order of writes has to be such that this field is written last.
26365 } __attribute__((packed));
26367 /***************************************
26368 * hwrm_cfa_redirect_query_tunnel_type *
26369 ***************************************/
26372 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
26373 struct hwrm_cfa_redirect_query_tunnel_type_input {
26374 /* The HWRM command request type. */
26377 * The completion ring to send the completion event on. This should
26378 * be the NQ ID returned from the `nq_alloc` HWRM command.
26380 uint16_t cmpl_ring;
26382 * The sequence ID is used by the driver for tracking multiple
26383 * commands. This ID is treated as opaque data by the firmware and
26384 * the value is returned in the `hwrm_resp_hdr` upon completion.
26388 * The target ID of the command:
26389 * * 0x0-0xFFF8 - The function ID
26390 * * 0xFFF8-0xFFFE - Reserved for internal processors
26393 uint16_t target_id;
26395 * A physical address pointer pointing to a host buffer that the
26396 * command's response data will be written. This can be either a host
26397 * physical address (HPA) or a guest physical address (GPA) and must
26398 * point to a physically contiguous block of memory.
26400 uint64_t resp_addr;
26401 /* The source function id. */
26403 uint8_t unused_0[6];
26404 } __attribute__((packed));
26406 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
26407 struct hwrm_cfa_redirect_query_tunnel_type_output {
26408 /* The specific error status for the command. */
26409 uint16_t error_code;
26410 /* The HWRM command request type. */
26412 /* The sequence ID from the original command. */
26414 /* The length of the response data in number of bytes. */
26417 uint32_t tunnel_mask;
26419 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
26421 /* Virtual eXtensible Local Area Network (VXLAN) */
26422 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
26424 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26425 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
26427 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26428 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
26431 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
26433 /* Generic Network Virtualization Encapsulation (Geneve) */
26434 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
26436 /* Multi-Protocol Lable Switching (MPLS) */
26437 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
26439 /* Stateless Transport Tunnel (STT) */
26440 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
26442 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26443 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
26445 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26446 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
26448 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26449 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
26451 /* Any tunneled traffic */
26452 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
26454 /* Use fixed layer 2 ether type of 0xFFFF */
26455 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
26457 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26458 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
26460 uint8_t unused_0[3];
26462 * This field is used in Output records to indicate that the output
26463 * is completely written to RAM. This field should be read as '1'
26464 * to indicate that the output has been completely written.
26465 * When writing a command completion or response to an internal processor,
26466 * the order of writes has to be such that this field is written last.
26469 } __attribute__((packed));
26471 /******************************
26472 * hwrm_tunnel_dst_port_query *
26473 ******************************/
26476 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
26477 struct hwrm_tunnel_dst_port_query_input {
26478 /* The HWRM command request type. */
26481 * The completion ring to send the completion event on. This should
26482 * be the NQ ID returned from the `nq_alloc` HWRM command.
26484 uint16_t cmpl_ring;
26486 * The sequence ID is used by the driver for tracking multiple
26487 * commands. This ID is treated as opaque data by the firmware and
26488 * the value is returned in the `hwrm_resp_hdr` upon completion.
26492 * The target ID of the command:
26493 * * 0x0-0xFFF8 - The function ID
26494 * * 0xFFF8-0xFFFE - Reserved for internal processors
26497 uint16_t target_id;
26499 * A physical address pointer pointing to a host buffer that the
26500 * command's response data will be written. This can be either a host
26501 * physical address (HPA) or a guest physical address (GPA) and must
26502 * point to a physically contiguous block of memory.
26504 uint64_t resp_addr;
26506 uint8_t tunnel_type;
26507 /* Virtual eXtensible Local Area Network (VXLAN) */
26508 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
26510 /* Generic Network Virtualization Encapsulation (Geneve) */
26511 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
26513 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26514 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26516 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26517 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26519 /* Use fixed layer 2 ether type of 0xFFFF */
26520 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
26522 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26523 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26525 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
26526 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
26527 uint8_t unused_0[7];
26528 } __attribute__((packed));
26530 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
26531 struct hwrm_tunnel_dst_port_query_output {
26532 /* The specific error status for the command. */
26533 uint16_t error_code;
26534 /* The HWRM command request type. */
26536 /* The sequence ID from the original command. */
26538 /* The length of the response data in number of bytes. */
26541 * This field represents the identifier of L4 destination port
26542 * used for the given tunnel type. This field is valid for
26543 * specific tunnel types that use layer 4 (e.g. UDP)
26544 * transports for tunneling.
26546 uint16_t tunnel_dst_port_id;
26548 * This field represents the value of L4 destination port
26549 * identified by tunnel_dst_port_id. This field is valid for
26550 * specific tunnel types that use layer 4 (e.g. UDP)
26551 * transports for tunneling.
26552 * This field is in network byte order.
26554 * A value of 0 means that the destination port is not
26557 uint16_t tunnel_dst_port_val;
26558 uint8_t unused_0[3];
26560 * This field is used in Output records to indicate that the output
26561 * is completely written to RAM. This field should be read as '1'
26562 * to indicate that the output has been completely written.
26563 * When writing a command completion or response to an internal processor,
26564 * the order of writes has to be such that this field is written last.
26567 } __attribute__((packed));
26569 /******************************
26570 * hwrm_tunnel_dst_port_alloc *
26571 ******************************/
26574 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
26575 struct hwrm_tunnel_dst_port_alloc_input {
26576 /* The HWRM command request type. */
26579 * The completion ring to send the completion event on. This should
26580 * be the NQ ID returned from the `nq_alloc` HWRM command.
26582 uint16_t cmpl_ring;
26584 * The sequence ID is used by the driver for tracking multiple
26585 * commands. This ID is treated as opaque data by the firmware and
26586 * the value is returned in the `hwrm_resp_hdr` upon completion.
26590 * The target ID of the command:
26591 * * 0x0-0xFFF8 - The function ID
26592 * * 0xFFF8-0xFFFE - Reserved for internal processors
26595 uint16_t target_id;
26597 * A physical address pointer pointing to a host buffer that the
26598 * command's response data will be written. This can be either a host
26599 * physical address (HPA) or a guest physical address (GPA) and must
26600 * point to a physically contiguous block of memory.
26602 uint64_t resp_addr;
26604 uint8_t tunnel_type;
26605 /* Virtual eXtensible Local Area Network (VXLAN) */
26606 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26608 /* Generic Network Virtualization Encapsulation (Geneve) */
26609 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26611 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26612 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26614 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26615 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26617 /* Use fixed layer 2 ether type of 0xFFFF */
26618 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26620 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26621 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26623 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26624 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
26627 * This field represents the value of L4 destination port used
26628 * for the given tunnel type. This field is valid for
26629 * specific tunnel types that use layer 4 (e.g. UDP)
26630 * transports for tunneling.
26632 * This field is in network byte order.
26634 * A value of 0 shall fail the command.
26636 uint16_t tunnel_dst_port_val;
26637 uint8_t unused_1[4];
26638 } __attribute__((packed));
26640 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
26641 struct hwrm_tunnel_dst_port_alloc_output {
26642 /* The specific error status for the command. */
26643 uint16_t error_code;
26644 /* The HWRM command request type. */
26646 /* The sequence ID from the original command. */
26648 /* The length of the response data in number of bytes. */
26651 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
26652 * types that has l4 destination port parameters.
26654 uint16_t tunnel_dst_port_id;
26655 uint8_t unused_0[5];
26657 * This field is used in Output records to indicate that the output
26658 * is completely written to RAM. This field should be read as '1'
26659 * to indicate that the output has been completely written.
26660 * When writing a command completion or response to an internal processor,
26661 * the order of writes has to be such that this field is written last.
26664 } __attribute__((packed));
26666 /*****************************
26667 * hwrm_tunnel_dst_port_free *
26668 *****************************/
26671 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
26672 struct hwrm_tunnel_dst_port_free_input {
26673 /* The HWRM command request type. */
26676 * The completion ring to send the completion event on. This should
26677 * be the NQ ID returned from the `nq_alloc` HWRM command.
26679 uint16_t cmpl_ring;
26681 * The sequence ID is used by the driver for tracking multiple
26682 * commands. This ID is treated as opaque data by the firmware and
26683 * the value is returned in the `hwrm_resp_hdr` upon completion.
26687 * The target ID of the command:
26688 * * 0x0-0xFFF8 - The function ID
26689 * * 0xFFF8-0xFFFE - Reserved for internal processors
26692 uint16_t target_id;
26694 * A physical address pointer pointing to a host buffer that the
26695 * command's response data will be written. This can be either a host
26696 * physical address (HPA) or a guest physical address (GPA) and must
26697 * point to a physically contiguous block of memory.
26699 uint64_t resp_addr;
26701 uint8_t tunnel_type;
26702 /* Virtual eXtensible Local Area Network (VXLAN) */
26703 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
26705 /* Generic Network Virtualization Encapsulation (Geneve) */
26706 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
26708 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26709 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26711 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26712 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26714 /* Use fixed layer 2 ether type of 0xFFFF */
26715 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
26717 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26718 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26720 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
26721 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
26724 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
26725 * types that has l4 destination port parameters.
26727 uint16_t tunnel_dst_port_id;
26728 uint8_t unused_1[4];
26729 } __attribute__((packed));
26731 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
26732 struct hwrm_tunnel_dst_port_free_output {
26733 /* The specific error status for the command. */
26734 uint16_t error_code;
26735 /* The HWRM command request type. */
26737 /* The sequence ID from the original command. */
26739 /* The length of the response data in number of bytes. */
26741 uint8_t unused_1[7];
26743 * This field is used in Output records to indicate that the output
26744 * is completely written to RAM. This field should be read as '1'
26745 * to indicate that the output has been completely written.
26746 * When writing a command completion or response to an internal processor,
26747 * the order of writes has to be such that this field is written last.
26750 } __attribute__((packed));
26752 /* Periodic statistics context DMA to host. */
26753 /* ctx_hw_stats (size:1280b/160B) */
26754 struct ctx_hw_stats {
26755 /* Number of received unicast packets */
26756 uint64_t rx_ucast_pkts;
26757 /* Number of received multicast packets */
26758 uint64_t rx_mcast_pkts;
26759 /* Number of received broadcast packets */
26760 uint64_t rx_bcast_pkts;
26761 /* Number of discarded packets on received path */
26762 uint64_t rx_discard_pkts;
26763 /* Number of dropped packets on received path */
26764 uint64_t rx_drop_pkts;
26765 /* Number of received bytes for unicast traffic */
26766 uint64_t rx_ucast_bytes;
26767 /* Number of received bytes for multicast traffic */
26768 uint64_t rx_mcast_bytes;
26769 /* Number of received bytes for broadcast traffic */
26770 uint64_t rx_bcast_bytes;
26771 /* Number of transmitted unicast packets */
26772 uint64_t tx_ucast_pkts;
26773 /* Number of transmitted multicast packets */
26774 uint64_t tx_mcast_pkts;
26775 /* Number of transmitted broadcast packets */
26776 uint64_t tx_bcast_pkts;
26777 /* Number of discarded packets on transmit path */
26778 uint64_t tx_discard_pkts;
26779 /* Number of dropped packets on transmit path */
26780 uint64_t tx_drop_pkts;
26781 /* Number of transmitted bytes for unicast traffic */
26782 uint64_t tx_ucast_bytes;
26783 /* Number of transmitted bytes for multicast traffic */
26784 uint64_t tx_mcast_bytes;
26785 /* Number of transmitted bytes for broadcast traffic */
26786 uint64_t tx_bcast_bytes;
26787 /* Number of TPA packets */
26789 /* Number of TPA bytes */
26790 uint64_t tpa_bytes;
26791 /* Number of TPA events */
26792 uint64_t tpa_events;
26793 /* Number of TPA aborts */
26794 uint64_t tpa_aborts;
26795 } __attribute__((packed));
26797 /* Periodic Engine statistics context DMA to host. */
26798 /* ctx_eng_stats (size:512b/64B) */
26799 struct ctx_eng_stats {
26801 * Count of data bytes into the Engine.
26802 * This includes any user supplied prefix,
26803 * but does not include any predefined
26806 uint64_t eng_bytes_in;
26807 /* Count of data bytes out of the Engine. */
26808 uint64_t eng_bytes_out;
26810 * Count, in 4-byte (dword) units, of bytes
26811 * that are input as auxiliary data.
26812 * This includes the aux_cmd data.
26814 uint64_t aux_bytes_in;
26816 * Count, in 4-byte (dword) units, of bytes
26817 * that are output as auxiliary data.
26818 * This count is the buffer space for aux_data
26819 * output provided in the RQE, not the actual
26822 uint64_t aux_bytes_out;
26823 /* Count of number of commands executed. */
26826 * Count of number of error commands.
26827 * These are the commands with a
26828 * non-zero status value.
26830 uint64_t error_commands;
26832 * Compression/Encryption Engine usage,
26833 * the unit is count of clock cycles
26835 uint64_t cce_engine_usage;
26837 * De-Compression/De-cryption Engine usage,
26838 * the unit is count of clock cycles
26840 uint64_t cdd_engine_usage;
26841 } __attribute__((packed));
26843 /***********************
26844 * hwrm_stat_ctx_alloc *
26845 ***********************/
26848 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
26849 struct hwrm_stat_ctx_alloc_input {
26850 /* The HWRM command request type. */
26853 * The completion ring to send the completion event on. This should
26854 * be the NQ ID returned from the `nq_alloc` HWRM command.
26856 uint16_t cmpl_ring;
26858 * The sequence ID is used by the driver for tracking multiple
26859 * commands. This ID is treated as opaque data by the firmware and
26860 * the value is returned in the `hwrm_resp_hdr` upon completion.
26864 * The target ID of the command:
26865 * * 0x0-0xFFF8 - The function ID
26866 * * 0xFFF8-0xFFFE - Reserved for internal processors
26869 uint16_t target_id;
26871 * A physical address pointer pointing to a host buffer that the
26872 * command's response data will be written. This can be either a host
26873 * physical address (HPA) or a guest physical address (GPA) and must
26874 * point to a physically contiguous block of memory.
26876 uint64_t resp_addr;
26877 /* This is the address for statistic block. */
26878 uint64_t stats_dma_addr;
26880 * The statistic block update period in ms.
26881 * e.g. 250ms, 500ms, 750ms, 1000ms.
26882 * If update_period_ms is 0, then the stats update
26883 * shall be never done and the DMA address shall not be used.
26884 * In this case, the stat block can only be read by
26885 * hwrm_stat_ctx_query command.
26887 uint32_t update_period_ms;
26889 * This field is used to specify statistics context specific
26890 * configuration flags.
26892 uint8_t stat_ctx_flags;
26894 * When this bit is set to '1', the statistics context shall be
26895 * allocated for RoCE traffic only. In this case, traffic other
26896 * than offloaded RoCE traffic shall not be included in this
26897 * statistic context.
26898 * When this bit is set to '0', the statistics context shall be
26899 * used for network traffic or engine traffic.
26901 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
26902 uint8_t unused_0[3];
26903 } __attribute__((packed));
26905 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
26906 struct hwrm_stat_ctx_alloc_output {
26907 /* The specific error status for the command. */
26908 uint16_t error_code;
26909 /* The HWRM command request type. */
26911 /* The sequence ID from the original command. */
26913 /* The length of the response data in number of bytes. */
26915 /* This is the statistics context ID value. */
26916 uint32_t stat_ctx_id;
26917 uint8_t unused_0[3];
26919 * This field is used in Output records to indicate that the output
26920 * is completely written to RAM. This field should be read as '1'
26921 * to indicate that the output has been completely written.
26922 * When writing a command completion or response to an internal processor,
26923 * the order of writes has to be such that this field is written last.
26926 } __attribute__((packed));
26928 /**********************
26929 * hwrm_stat_ctx_free *
26930 **********************/
26933 /* hwrm_stat_ctx_free_input (size:192b/24B) */
26934 struct hwrm_stat_ctx_free_input {
26935 /* The HWRM command request type. */
26938 * The completion ring to send the completion event on. This should
26939 * be the NQ ID returned from the `nq_alloc` HWRM command.
26941 uint16_t cmpl_ring;
26943 * The sequence ID is used by the driver for tracking multiple
26944 * commands. This ID is treated as opaque data by the firmware and
26945 * the value is returned in the `hwrm_resp_hdr` upon completion.
26949 * The target ID of the command:
26950 * * 0x0-0xFFF8 - The function ID
26951 * * 0xFFF8-0xFFFE - Reserved for internal processors
26954 uint16_t target_id;
26956 * A physical address pointer pointing to a host buffer that the
26957 * command's response data will be written. This can be either a host
26958 * physical address (HPA) or a guest physical address (GPA) and must
26959 * point to a physically contiguous block of memory.
26961 uint64_t resp_addr;
26962 /* ID of the statistics context that is being queried. */
26963 uint32_t stat_ctx_id;
26964 uint8_t unused_0[4];
26965 } __attribute__((packed));
26967 /* hwrm_stat_ctx_free_output (size:128b/16B) */
26968 struct hwrm_stat_ctx_free_output {
26969 /* The specific error status for the command. */
26970 uint16_t error_code;
26971 /* The HWRM command request type. */
26973 /* The sequence ID from the original command. */
26975 /* The length of the response data in number of bytes. */
26977 /* This is the statistics context ID value. */
26978 uint32_t stat_ctx_id;
26979 uint8_t unused_0[3];
26981 * This field is used in Output records to indicate that the output
26982 * is completely written to RAM. This field should be read as '1'
26983 * to indicate that the output has been completely written.
26984 * When writing a command completion or response to an internal processor,
26985 * the order of writes has to be such that this field is written last.
26988 } __attribute__((packed));
26990 /***********************
26991 * hwrm_stat_ctx_query *
26992 ***********************/
26995 /* hwrm_stat_ctx_query_input (size:192b/24B) */
26996 struct hwrm_stat_ctx_query_input {
26997 /* The HWRM command request type. */
27000 * The completion ring to send the completion event on. This should
27001 * be the NQ ID returned from the `nq_alloc` HWRM command.
27003 uint16_t cmpl_ring;
27005 * The sequence ID is used by the driver for tracking multiple
27006 * commands. This ID is treated as opaque data by the firmware and
27007 * the value is returned in the `hwrm_resp_hdr` upon completion.
27011 * The target ID of the command:
27012 * * 0x0-0xFFF8 - The function ID
27013 * * 0xFFF8-0xFFFE - Reserved for internal processors
27016 uint16_t target_id;
27018 * A physical address pointer pointing to a host buffer that the
27019 * command's response data will be written. This can be either a host
27020 * physical address (HPA) or a guest physical address (GPA) and must
27021 * point to a physically contiguous block of memory.
27023 uint64_t resp_addr;
27024 /* ID of the statistics context that is being queried. */
27025 uint32_t stat_ctx_id;
27026 uint8_t unused_0[4];
27027 } __attribute__((packed));
27029 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
27030 struct hwrm_stat_ctx_query_output {
27031 /* The specific error status for the command. */
27032 uint16_t error_code;
27033 /* The HWRM command request type. */
27035 /* The sequence ID from the original command. */
27037 /* The length of the response data in number of bytes. */
27039 /* Number of transmitted unicast packets */
27040 uint64_t tx_ucast_pkts;
27041 /* Number of transmitted multicast packets */
27042 uint64_t tx_mcast_pkts;
27043 /* Number of transmitted broadcast packets */
27044 uint64_t tx_bcast_pkts;
27045 /* Number of transmitted packets with error */
27046 uint64_t tx_err_pkts;
27047 /* Number of dropped packets on transmit path */
27048 uint64_t tx_drop_pkts;
27049 /* Number of transmitted bytes for unicast traffic */
27050 uint64_t tx_ucast_bytes;
27051 /* Number of transmitted bytes for multicast traffic */
27052 uint64_t tx_mcast_bytes;
27053 /* Number of transmitted bytes for broadcast traffic */
27054 uint64_t tx_bcast_bytes;
27055 /* Number of received unicast packets */
27056 uint64_t rx_ucast_pkts;
27057 /* Number of received multicast packets */
27058 uint64_t rx_mcast_pkts;
27059 /* Number of received broadcast packets */
27060 uint64_t rx_bcast_pkts;
27061 /* Number of received packets with error */
27062 uint64_t rx_err_pkts;
27063 /* Number of dropped packets on received path */
27064 uint64_t rx_drop_pkts;
27065 /* Number of received bytes for unicast traffic */
27066 uint64_t rx_ucast_bytes;
27067 /* Number of received bytes for multicast traffic */
27068 uint64_t rx_mcast_bytes;
27069 /* Number of received bytes for broadcast traffic */
27070 uint64_t rx_bcast_bytes;
27071 /* Number of aggregated unicast packets */
27072 uint64_t rx_agg_pkts;
27073 /* Number of aggregated unicast bytes */
27074 uint64_t rx_agg_bytes;
27075 /* Number of aggregation events */
27076 uint64_t rx_agg_events;
27077 /* Number of aborted aggregations */
27078 uint64_t rx_agg_aborts;
27079 uint8_t unused_0[7];
27081 * This field is used in Output records to indicate that the output
27082 * is completely written to RAM. This field should be read as '1'
27083 * to indicate that the output has been completely written.
27084 * When writing a command completion or response to an internal processor,
27085 * the order of writes has to be such that this field is written last.
27088 } __attribute__((packed));
27090 /***************************
27091 * hwrm_stat_ctx_eng_query *
27092 ***************************/
27095 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
27096 struct hwrm_stat_ctx_eng_query_input {
27097 /* The HWRM command request type. */
27100 * The completion ring to send the completion event on. This should
27101 * be the NQ ID returned from the `nq_alloc` HWRM command.
27103 uint16_t cmpl_ring;
27105 * The sequence ID is used by the driver for tracking multiple
27106 * commands. This ID is treated as opaque data by the firmware and
27107 * the value is returned in the `hwrm_resp_hdr` upon completion.
27111 * The target ID of the command:
27112 * * 0x0-0xFFF8 - The function ID
27113 * * 0xFFF8-0xFFFE - Reserved for internal processors
27116 uint16_t target_id;
27118 * A physical address pointer pointing to a host buffer that the
27119 * command's response data will be written. This can be either a host
27120 * physical address (HPA) or a guest physical address (GPA) and must
27121 * point to a physically contiguous block of memory.
27123 uint64_t resp_addr;
27124 /* ID of the statistics context that is being queried. */
27125 uint32_t stat_ctx_id;
27126 uint8_t unused_0[4];
27127 } __attribute__((packed));
27129 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
27130 struct hwrm_stat_ctx_eng_query_output {
27131 /* The specific error status for the command. */
27132 uint16_t error_code;
27133 /* The HWRM command request type. */
27135 /* The sequence ID from the original command. */
27137 /* The length of the response data in number of bytes. */
27140 * Count of data bytes into the Engine.
27141 * This includes any user supplied prefix,
27142 * but does not include any predefined
27145 uint64_t eng_bytes_in;
27146 /* Count of data bytes out of the Engine. */
27147 uint64_t eng_bytes_out;
27149 * Count, in 4-byte (dword) units, of bytes
27150 * that are input as auxiliary data.
27151 * This includes the aux_cmd data.
27153 uint64_t aux_bytes_in;
27155 * Count, in 4-byte (dword) units, of bytes
27156 * that are output as auxiliary data.
27157 * This count is the buffer space for aux_data
27158 * output provided in the RQE, not the actual
27161 uint64_t aux_bytes_out;
27162 /* Count of number of commands executed. */
27165 * Count of number of error commands.
27166 * These are the commands with a
27167 * non-zero status value.
27169 uint64_t error_commands;
27171 * Compression/Encryption Engine usage,
27172 * the unit is count of clock cycles
27174 uint64_t cce_engine_usage;
27176 * De-Compression/De-cryption Engine usage,
27177 * the unit is count of clock cycles
27179 uint64_t cdd_engine_usage;
27180 uint8_t unused_0[7];
27182 * This field is used in Output records to indicate that the output
27183 * is completely written to RAM. This field should be read as '1'
27184 * to indicate that the output has been completely written.
27185 * When writing a command completion or response to an internal processor,
27186 * the order of writes has to be such that this field is written last.
27189 } __attribute__((packed));
27191 /***************************
27192 * hwrm_stat_ctx_clr_stats *
27193 ***************************/
27196 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
27197 struct hwrm_stat_ctx_clr_stats_input {
27198 /* The HWRM command request type. */
27201 * The completion ring to send the completion event on. This should
27202 * be the NQ ID returned from the `nq_alloc` HWRM command.
27204 uint16_t cmpl_ring;
27206 * The sequence ID is used by the driver for tracking multiple
27207 * commands. This ID is treated as opaque data by the firmware and
27208 * the value is returned in the `hwrm_resp_hdr` upon completion.
27212 * The target ID of the command:
27213 * * 0x0-0xFFF8 - The function ID
27214 * * 0xFFF8-0xFFFE - Reserved for internal processors
27217 uint16_t target_id;
27219 * A physical address pointer pointing to a host buffer that the
27220 * command's response data will be written. This can be either a host
27221 * physical address (HPA) or a guest physical address (GPA) and must
27222 * point to a physically contiguous block of memory.
27224 uint64_t resp_addr;
27225 /* ID of the statistics context that is being queried. */
27226 uint32_t stat_ctx_id;
27227 uint8_t unused_0[4];
27228 } __attribute__((packed));
27230 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
27231 struct hwrm_stat_ctx_clr_stats_output {
27232 /* The specific error status for the command. */
27233 uint16_t error_code;
27234 /* The HWRM command request type. */
27236 /* The sequence ID from the original command. */
27238 /* The length of the response data in number of bytes. */
27240 uint8_t unused_0[7];
27242 * This field is used in Output records to indicate that the output
27243 * is completely written to RAM. This field should be read as '1'
27244 * to indicate that the output has been completely written.
27245 * When writing a command completion or response to an internal processor,
27246 * the order of writes has to be such that this field is written last.
27249 } __attribute__((packed));
27251 /********************
27252 * hwrm_pcie_qstats *
27253 ********************/
27256 /* hwrm_pcie_qstats_input (size:256b/32B) */
27257 struct hwrm_pcie_qstats_input {
27258 /* The HWRM command request type. */
27261 * The completion ring to send the completion event on. This should
27262 * be the NQ ID returned from the `nq_alloc` HWRM command.
27264 uint16_t cmpl_ring;
27266 * The sequence ID is used by the driver for tracking multiple
27267 * commands. This ID is treated as opaque data by the firmware and
27268 * the value is returned in the `hwrm_resp_hdr` upon completion.
27272 * The target ID of the command:
27273 * * 0x0-0xFFF8 - The function ID
27274 * * 0xFFF8-0xFFFE - Reserved for internal processors
27277 uint16_t target_id;
27279 * A physical address pointer pointing to a host buffer that the
27280 * command's response data will be written. This can be either a host
27281 * physical address (HPA) or a guest physical address (GPA) and must
27282 * point to a physically contiguous block of memory.
27284 uint64_t resp_addr;
27286 * The size of PCIe statistics block in bytes.
27287 * Firmware will DMA the PCIe statistics to
27288 * the host with this field size in the response.
27290 uint16_t pcie_stat_size;
27291 uint8_t unused_0[6];
27293 * This is the host address where
27294 * PCIe statistics will be stored
27296 uint64_t pcie_stat_host_addr;
27297 } __attribute__((packed));
27299 /* hwrm_pcie_qstats_output (size:128b/16B) */
27300 struct hwrm_pcie_qstats_output {
27301 /* The specific error status for the command. */
27302 uint16_t error_code;
27303 /* The HWRM command request type. */
27305 /* The sequence ID from the original command. */
27307 /* The length of the response data in number of bytes. */
27309 /* The size of PCIe statistics block in bytes. */
27310 uint16_t pcie_stat_size;
27311 uint8_t unused_0[5];
27313 * This field is used in Output records to indicate that the output
27314 * is completely written to RAM. This field should be read as '1'
27315 * to indicate that the output has been completely written.
27316 * When writing a command completion or response to an internal processor,
27317 * the order of writes has to be such that this field is written last.
27320 } __attribute__((packed));
27322 /* PCIe Statistics Formats */
27323 /* pcie_ctx_hw_stats (size:768b/96B) */
27324 struct pcie_ctx_hw_stats {
27325 /* Number of physical layer receiver errors */
27326 uint64_t pcie_pl_signal_integrity;
27327 /* Number of DLLP CRC errors detected by Data Link Layer */
27328 uint64_t pcie_dl_signal_integrity;
27330 * Number of TLP LCRC and sequence number errors detected
27331 * by Data Link Layer
27333 uint64_t pcie_tl_signal_integrity;
27334 /* Number of times LTSSM entered Recovery state */
27335 uint64_t pcie_link_integrity;
27336 /* Number of TLP bytes that have been trasmitted */
27337 uint64_t pcie_tx_traffic_rate;
27338 /* Number of TLP bytes that have been received */
27339 uint64_t pcie_rx_traffic_rate;
27340 /* Number of DLLP bytes that have been trasmitted */
27341 uint64_t pcie_tx_dllp_statistics;
27342 /* Number of DLLP bytes that have been received */
27343 uint64_t pcie_rx_dllp_statistics;
27345 * Number of times spent in each phase of gen3
27348 uint64_t pcie_equalization_time;
27349 /* Records the last 16 transitions of the LTSSM */
27350 uint32_t pcie_ltssm_histogram[4];
27352 * Record the last 8 reasons on why LTSSM transitioned
27355 uint64_t pcie_recovery_histogram;
27356 } __attribute__((packed));
27358 /**********************
27359 * hwrm_exec_fwd_resp *
27360 **********************/
27363 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
27364 struct hwrm_exec_fwd_resp_input {
27365 /* The HWRM command request type. */
27368 * The completion ring to send the completion event on. This should
27369 * be the NQ ID returned from the `nq_alloc` HWRM command.
27371 uint16_t cmpl_ring;
27373 * The sequence ID is used by the driver for tracking multiple
27374 * commands. This ID is treated as opaque data by the firmware and
27375 * the value is returned in the `hwrm_resp_hdr` upon completion.
27379 * The target ID of the command:
27380 * * 0x0-0xFFF8 - The function ID
27381 * * 0xFFF8-0xFFFE - Reserved for internal processors
27384 uint16_t target_id;
27386 * A physical address pointer pointing to a host buffer that the
27387 * command's response data will be written. This can be either a host
27388 * physical address (HPA) or a guest physical address (GPA) and must
27389 * point to a physically contiguous block of memory.
27391 uint64_t resp_addr;
27393 * This is an encapsulated request. This request should
27394 * be executed by the HWRM and the response should be
27395 * provided in the response buffer inside the encapsulated
27398 uint32_t encap_request[26];
27400 * This value indicates the target id of the response to
27401 * the encapsulated request.
27402 * 0x0 - 0xFFF8 - Used for function ids
27403 * 0xFFF8 - 0xFFFE - Reserved for internal processors
27406 uint16_t encap_resp_target_id;
27407 uint8_t unused_0[6];
27408 } __attribute__((packed));
27410 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
27411 struct hwrm_exec_fwd_resp_output {
27412 /* The specific error status for the command. */
27413 uint16_t error_code;
27414 /* The HWRM command request type. */
27416 /* The sequence ID from the original command. */
27418 /* The length of the response data in number of bytes. */
27420 uint8_t unused_0[7];
27422 * This field is used in Output records to indicate that the output
27423 * is completely written to RAM. This field should be read as '1'
27424 * to indicate that the output has been completely written.
27425 * When writing a command completion or response to an internal processor,
27426 * the order of writes has to be such that this field is written last.
27429 } __attribute__((packed));
27431 /************************
27432 * hwrm_reject_fwd_resp *
27433 ************************/
27436 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
27437 struct hwrm_reject_fwd_resp_input {
27438 /* The HWRM command request type. */
27441 * The completion ring to send the completion event on. This should
27442 * be the NQ ID returned from the `nq_alloc` HWRM command.
27444 uint16_t cmpl_ring;
27446 * The sequence ID is used by the driver for tracking multiple
27447 * commands. This ID is treated as opaque data by the firmware and
27448 * the value is returned in the `hwrm_resp_hdr` upon completion.
27452 * The target ID of the command:
27453 * * 0x0-0xFFF8 - The function ID
27454 * * 0xFFF8-0xFFFE - Reserved for internal processors
27457 uint16_t target_id;
27459 * A physical address pointer pointing to a host buffer that the
27460 * command's response data will be written. This can be either a host
27461 * physical address (HPA) or a guest physical address (GPA) and must
27462 * point to a physically contiguous block of memory.
27464 uint64_t resp_addr;
27466 * This is an encapsulated request. This request should
27467 * be rejected by the HWRM and the error response should be
27468 * provided in the response buffer inside the encapsulated
27471 uint32_t encap_request[26];
27473 * This value indicates the target id of the response to
27474 * the encapsulated request.
27475 * 0x0 - 0xFFF8 - Used for function ids
27476 * 0xFFF8 - 0xFFFE - Reserved for internal processors
27479 uint16_t encap_resp_target_id;
27480 uint8_t unused_0[6];
27481 } __attribute__((packed));
27483 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
27484 struct hwrm_reject_fwd_resp_output {
27485 /* The specific error status for the command. */
27486 uint16_t error_code;
27487 /* The HWRM command request type. */
27489 /* The sequence ID from the original command. */
27491 /* The length of the response data in number of bytes. */
27493 uint8_t unused_0[7];
27495 * This field is used in Output records to indicate that the output
27496 * is completely written to RAM. This field should be read as '1'
27497 * to indicate that the output has been completely written.
27498 * When writing a command completion or response to an internal processor,
27499 * the order of writes has to be such that this field is written last.
27502 } __attribute__((packed));
27509 /* hwrm_fwd_resp_input (size:1024b/128B) */
27510 struct hwrm_fwd_resp_input {
27511 /* The HWRM command request type. */
27514 * The completion ring to send the completion event on. This should
27515 * be the NQ ID returned from the `nq_alloc` HWRM command.
27517 uint16_t cmpl_ring;
27519 * The sequence ID is used by the driver for tracking multiple
27520 * commands. This ID is treated as opaque data by the firmware and
27521 * the value is returned in the `hwrm_resp_hdr` upon completion.
27525 * The target ID of the command:
27526 * * 0x0-0xFFF8 - The function ID
27527 * * 0xFFF8-0xFFFE - Reserved for internal processors
27530 uint16_t target_id;
27532 * A physical address pointer pointing to a host buffer that the
27533 * command's response data will be written. This can be either a host
27534 * physical address (HPA) or a guest physical address (GPA) and must
27535 * point to a physically contiguous block of memory.
27537 uint64_t resp_addr;
27539 * This value indicates the target id of the encapsulated
27541 * 0x0 - 0xFFF8 - Used for function ids
27542 * 0xFFF8 - 0xFFFE - Reserved for internal processors
27545 uint16_t encap_resp_target_id;
27547 * This value indicates the completion ring the encapsulated
27548 * response will be optionally completed on. If the value is
27549 * -1, then no CR completion shall be generated for the
27550 * encapsulated response. Any other value must be a
27551 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
27552 * is provided, then a CR completion shall be generated for
27553 * the encapsulated response.
27555 uint16_t encap_resp_cmpl_ring;
27556 /* This field indicates the length of encapsulated response. */
27557 uint16_t encap_resp_len;
27561 * This is the host address where the encapsulated response
27563 * This area must be 16B aligned and must be cleared to zero
27564 * before the original request is made.
27566 uint64_t encap_resp_addr;
27567 /* This is an encapsulated response. */
27568 uint32_t encap_resp[24];
27569 } __attribute__((packed));
27571 /* hwrm_fwd_resp_output (size:128b/16B) */
27572 struct hwrm_fwd_resp_output {
27573 /* The specific error status for the command. */
27574 uint16_t error_code;
27575 /* The HWRM command request type. */
27577 /* The sequence ID from the original command. */
27579 /* The length of the response data in number of bytes. */
27581 uint8_t unused_0[7];
27583 * This field is used in Output records to indicate that the output
27584 * is completely written to RAM. This field should be read as '1'
27585 * to indicate that the output has been completely written.
27586 * When writing a command completion or response to an internal processor,
27587 * the order of writes has to be such that this field is written last.
27590 } __attribute__((packed));
27592 /*****************************
27593 * hwrm_fwd_async_event_cmpl *
27594 *****************************/
27597 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
27598 struct hwrm_fwd_async_event_cmpl_input {
27599 /* The HWRM command request type. */
27602 * The completion ring to send the completion event on. This should
27603 * be the NQ ID returned from the `nq_alloc` HWRM command.
27605 uint16_t cmpl_ring;
27607 * The sequence ID is used by the driver for tracking multiple
27608 * commands. This ID is treated as opaque data by the firmware and
27609 * the value is returned in the `hwrm_resp_hdr` upon completion.
27613 * The target ID of the command:
27614 * * 0x0-0xFFF8 - The function ID
27615 * * 0xFFF8-0xFFFE - Reserved for internal processors
27618 uint16_t target_id;
27620 * A physical address pointer pointing to a host buffer that the
27621 * command's response data will be written. This can be either a host
27622 * physical address (HPA) or a guest physical address (GPA) and must
27623 * point to a physically contiguous block of memory.
27625 uint64_t resp_addr;
27627 * This value indicates the target id of the encapsulated
27628 * asynchronous event.
27629 * 0x0 - 0xFFF8 - Used for function ids
27630 * 0xFFF8 - 0xFFFE - Reserved for internal processors
27631 * 0xFFFF - Broadcast to all children VFs (only applicable when
27632 * a PF is the requester)
27634 uint16_t encap_async_event_target_id;
27635 uint8_t unused_0[6];
27636 /* This is an encapsulated asynchronous event completion. */
27637 uint32_t encap_async_event_cmpl[4];
27638 } __attribute__((packed));
27640 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
27641 struct hwrm_fwd_async_event_cmpl_output {
27642 /* The specific error status for the command. */
27643 uint16_t error_code;
27644 /* The HWRM command request type. */
27646 /* The sequence ID from the original command. */
27648 /* The length of the response data in number of bytes. */
27650 uint8_t unused_0[7];
27652 * This field is used in Output records to indicate that the output
27653 * is completely written to RAM. This field should be read as '1'
27654 * to indicate that the output has been completely written.
27655 * When writing a command completion or response to an internal processor,
27656 * the order of writes has to be such that this field is written last.
27659 } __attribute__((packed));
27661 /**************************
27662 * hwrm_nvm_raw_write_blk *
27663 **************************/
27666 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
27667 struct hwrm_nvm_raw_write_blk_input {
27668 /* The HWRM command request type. */
27671 * The completion ring to send the completion event on. This should
27672 * be the NQ ID returned from the `nq_alloc` HWRM command.
27674 uint16_t cmpl_ring;
27676 * The sequence ID is used by the driver for tracking multiple
27677 * commands. This ID is treated as opaque data by the firmware and
27678 * the value is returned in the `hwrm_resp_hdr` upon completion.
27682 * The target ID of the command:
27683 * * 0x0-0xFFF8 - The function ID
27684 * * 0xFFF8-0xFFFE - Reserved for internal processors
27687 uint16_t target_id;
27689 * A physical address pointer pointing to a host buffer that the
27690 * command's response data will be written. This can be either a host
27691 * physical address (HPA) or a guest physical address (GPA) and must
27692 * point to a physically contiguous block of memory.
27694 uint64_t resp_addr;
27696 * 64-bit Host Source Address.
27697 * This is the loation of the source data to be written.
27699 uint64_t host_src_addr;
27701 * 32-bit Destination Address.
27702 * This is the NVRAM byte-offset where the source data will be written to.
27704 uint32_t dest_addr;
27705 /* Length of data to be written, in bytes. */
27707 } __attribute__((packed));
27709 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
27710 struct hwrm_nvm_raw_write_blk_output {
27711 /* The specific error status for the command. */
27712 uint16_t error_code;
27713 /* The HWRM command request type. */
27715 /* The sequence ID from the original command. */
27717 /* The length of the response data in number of bytes. */
27719 uint8_t unused_0[7];
27721 * This field is used in Output records to indicate that the output
27722 * is completely written to RAM. This field should be read as '1'
27723 * to indicate that the output has been completely written.
27724 * When writing a command completion or response to an internal processor,
27725 * the order of writes has to be such that this field is written last.
27728 } __attribute__((packed));
27735 /* hwrm_nvm_read_input (size:320b/40B) */
27736 struct hwrm_nvm_read_input {
27737 /* The HWRM command request type. */
27740 * The completion ring to send the completion event on. This should
27741 * be the NQ ID returned from the `nq_alloc` HWRM command.
27743 uint16_t cmpl_ring;
27745 * The sequence ID is used by the driver for tracking multiple
27746 * commands. This ID is treated as opaque data by the firmware and
27747 * the value is returned in the `hwrm_resp_hdr` upon completion.
27751 * The target ID of the command:
27752 * * 0x0-0xFFF8 - The function ID
27753 * * 0xFFF8-0xFFFE - Reserved for internal processors
27756 uint16_t target_id;
27758 * A physical address pointer pointing to a host buffer that the
27759 * command's response data will be written. This can be either a host
27760 * physical address (HPA) or a guest physical address (GPA) and must
27761 * point to a physically contiguous block of memory.
27763 uint64_t resp_addr;
27765 * 64-bit Host Destination Address.
27766 * This is the host address where the data will be written to.
27768 uint64_t host_dest_addr;
27769 /* The 0-based index of the directory entry. */
27771 uint8_t unused_0[2];
27772 /* The NVRAM byte-offset to read from. */
27774 /* The length of the data to be read, in bytes. */
27776 uint8_t unused_1[4];
27777 } __attribute__((packed));
27779 /* hwrm_nvm_read_output (size:128b/16B) */
27780 struct hwrm_nvm_read_output {
27781 /* The specific error status for the command. */
27782 uint16_t error_code;
27783 /* The HWRM command request type. */
27785 /* The sequence ID from the original command. */
27787 /* The length of the response data in number of bytes. */
27789 uint8_t unused_0[7];
27791 * This field is used in Output records to indicate that the output
27792 * is completely written to RAM. This field should be read as '1'
27793 * to indicate that the output has been completely written.
27794 * When writing a command completion or response to an internal processor,
27795 * the order of writes has to be such that this field is written last.
27798 } __attribute__((packed));
27800 /*********************
27801 * hwrm_nvm_raw_dump *
27802 *********************/
27805 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
27806 struct hwrm_nvm_raw_dump_input {
27807 /* The HWRM command request type. */
27810 * The completion ring to send the completion event on. This should
27811 * be the NQ ID returned from the `nq_alloc` HWRM command.
27813 uint16_t cmpl_ring;
27815 * The sequence ID is used by the driver for tracking multiple
27816 * commands. This ID is treated as opaque data by the firmware and
27817 * the value is returned in the `hwrm_resp_hdr` upon completion.
27821 * The target ID of the command:
27822 * * 0x0-0xFFF8 - The function ID
27823 * * 0xFFF8-0xFFFE - Reserved for internal processors
27826 uint16_t target_id;
27828 * A physical address pointer pointing to a host buffer that the
27829 * command's response data will be written. This can be either a host
27830 * physical address (HPA) or a guest physical address (GPA) and must
27831 * point to a physically contiguous block of memory.
27833 uint64_t resp_addr;
27835 * 64-bit Host Destination Address.
27836 * This is the host address where the data will be written to.
27838 uint64_t host_dest_addr;
27839 /* 32-bit NVRAM byte-offset to read from. */
27841 /* Total length of NVRAM contents to be read, in bytes. */
27843 } __attribute__((packed));
27845 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
27846 struct hwrm_nvm_raw_dump_output {
27847 /* The specific error status for the command. */
27848 uint16_t error_code;
27849 /* The HWRM command request type. */
27851 /* The sequence ID from the original command. */
27853 /* The length of the response data in number of bytes. */
27855 uint8_t unused_0[7];
27857 * This field is used in Output records to indicate that the output
27858 * is completely written to RAM. This field should be read as '1'
27859 * to indicate that the output has been completely written.
27860 * When writing a command completion or response to an internal processor,
27861 * the order of writes has to be such that this field is written last.
27864 } __attribute__((packed));
27866 /****************************
27867 * hwrm_nvm_get_dir_entries *
27868 ****************************/
27871 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
27872 struct hwrm_nvm_get_dir_entries_input {
27873 /* The HWRM command request type. */
27876 * The completion ring to send the completion event on. This should
27877 * be the NQ ID returned from the `nq_alloc` HWRM command.
27879 uint16_t cmpl_ring;
27881 * The sequence ID is used by the driver for tracking multiple
27882 * commands. This ID is treated as opaque data by the firmware and
27883 * the value is returned in the `hwrm_resp_hdr` upon completion.
27887 * The target ID of the command:
27888 * * 0x0-0xFFF8 - The function ID
27889 * * 0xFFF8-0xFFFE - Reserved for internal processors
27892 uint16_t target_id;
27894 * A physical address pointer pointing to a host buffer that the
27895 * command's response data will be written. This can be either a host
27896 * physical address (HPA) or a guest physical address (GPA) and must
27897 * point to a physically contiguous block of memory.
27899 uint64_t resp_addr;
27901 * 64-bit Host Destination Address.
27902 * This is the host address where the directory will be written.
27904 uint64_t host_dest_addr;
27905 } __attribute__((packed));
27907 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
27908 struct hwrm_nvm_get_dir_entries_output {
27909 /* The specific error status for the command. */
27910 uint16_t error_code;
27911 /* The HWRM command request type. */
27913 /* The sequence ID from the original command. */
27915 /* The length of the response data in number of bytes. */
27917 uint8_t unused_0[7];
27919 * This field is used in Output records to indicate that the output
27920 * is completely written to RAM. This field should be read as '1'
27921 * to indicate that the output has been completely written.
27922 * When writing a command completion or response to an internal processor,
27923 * the order of writes has to be such that this field is written last.
27926 } __attribute__((packed));
27928 /*************************
27929 * hwrm_nvm_get_dir_info *
27930 *************************/
27933 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
27934 struct hwrm_nvm_get_dir_info_input {
27935 /* The HWRM command request type. */
27938 * The completion ring to send the completion event on. This should
27939 * be the NQ ID returned from the `nq_alloc` HWRM command.
27941 uint16_t cmpl_ring;
27943 * The sequence ID is used by the driver for tracking multiple
27944 * commands. This ID is treated as opaque data by the firmware and
27945 * the value is returned in the `hwrm_resp_hdr` upon completion.
27949 * The target ID of the command:
27950 * * 0x0-0xFFF8 - The function ID
27951 * * 0xFFF8-0xFFFE - Reserved for internal processors
27954 uint16_t target_id;
27956 * A physical address pointer pointing to a host buffer that the
27957 * command's response data will be written. This can be either a host
27958 * physical address (HPA) or a guest physical address (GPA) and must
27959 * point to a physically contiguous block of memory.
27961 uint64_t resp_addr;
27962 } __attribute__((packed));
27964 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
27965 struct hwrm_nvm_get_dir_info_output {
27966 /* The specific error status for the command. */
27967 uint16_t error_code;
27968 /* The HWRM command request type. */
27970 /* The sequence ID from the original command. */
27972 /* The length of the response data in number of bytes. */
27974 /* Number of directory entries in the directory. */
27976 /* Size of each directory entry, in bytes. */
27977 uint32_t entry_length;
27978 uint8_t unused_0[7];
27980 * This field is used in Output records to indicate that the output
27981 * is completely written to RAM. This field should be read as '1'
27982 * to indicate that the output has been completely written.
27983 * When writing a command completion or response to an internal processor,
27984 * the order of writes has to be such that this field is written last.
27987 } __attribute__((packed));
27989 /******************
27991 ******************/
27994 /* hwrm_nvm_write_input (size:384b/48B) */
27995 struct hwrm_nvm_write_input {
27996 /* The HWRM command request type. */
27999 * The completion ring to send the completion event on. This should
28000 * be the NQ ID returned from the `nq_alloc` HWRM command.
28002 uint16_t cmpl_ring;
28004 * The sequence ID is used by the driver for tracking multiple
28005 * commands. This ID is treated as opaque data by the firmware and
28006 * the value is returned in the `hwrm_resp_hdr` upon completion.
28010 * The target ID of the command:
28011 * * 0x0-0xFFF8 - The function ID
28012 * * 0xFFF8-0xFFFE - Reserved for internal processors
28015 uint16_t target_id;
28017 * A physical address pointer pointing to a host buffer that the
28018 * command's response data will be written. This can be either a host
28019 * physical address (HPA) or a guest physical address (GPA) and must
28020 * point to a physically contiguous block of memory.
28022 uint64_t resp_addr;
28024 * 64-bit Host Source Address.
28025 * This is where the source data is.
28027 uint64_t host_src_addr;
28028 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
28031 * Directory ordinal.
28032 * The 0-based instance of the combined Directory Entry Type and Extension.
28034 uint16_t dir_ordinal;
28035 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
28037 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
28040 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
28041 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
28043 uint32_t dir_data_length;
28048 * When this bit is '1', the original active image
28049 * will not be removed. TBD: what purpose is this?
28051 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
28054 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
28055 * If this value is less than the specified data length, it will be ignored.
28056 * The response will contain the actual allocated item length, which may be greater than the requested item length.
28057 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
28058 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
28060 uint32_t dir_item_length;
28062 } __attribute__((packed));
28064 /* hwrm_nvm_write_output (size:128b/16B) */
28065 struct hwrm_nvm_write_output {
28066 /* The specific error status for the command. */
28067 uint16_t error_code;
28068 /* The HWRM command request type. */
28070 /* The sequence ID from the original command. */
28072 /* The length of the response data in number of bytes. */
28075 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
28076 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
28078 uint32_t dir_item_length;
28079 /* The directory index of the created or modified item. */
28083 * This field is used in Output records to indicate that the output
28084 * is completely written to RAM. This field should be read as '1'
28085 * to indicate that the output has been completely written.
28086 * When writing a command completion or response to an internal processor,
28087 * the order of writes has to be such that this field is written last.
28090 } __attribute__((packed));
28092 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
28093 struct hwrm_nvm_write_cmd_err {
28095 * command specific error codes that goes to
28096 * the cmd_err field in Common HWRM Error Response.
28099 /* Unknown error */
28100 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28101 /* Unable to complete operation due to fragmentation */
28102 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
28103 /* nvm is completely full. */
28104 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
28105 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
28106 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
28107 uint8_t unused_0[7];
28108 } __attribute__((packed));
28110 /*******************
28111 * hwrm_nvm_modify *
28112 *******************/
28115 /* hwrm_nvm_modify_input (size:320b/40B) */
28116 struct hwrm_nvm_modify_input {
28117 /* The HWRM command request type. */
28120 * The completion ring to send the completion event on. This should
28121 * be the NQ ID returned from the `nq_alloc` HWRM command.
28123 uint16_t cmpl_ring;
28125 * The sequence ID is used by the driver for tracking multiple
28126 * commands. This ID is treated as opaque data by the firmware and
28127 * the value is returned in the `hwrm_resp_hdr` upon completion.
28131 * The target ID of the command:
28132 * * 0x0-0xFFF8 - The function ID
28133 * * 0xFFF8-0xFFFE - Reserved for internal processors
28136 uint16_t target_id;
28138 * A physical address pointer pointing to a host buffer that the
28139 * command's response data will be written. This can be either a host
28140 * physical address (HPA) or a guest physical address (GPA) and must
28141 * point to a physically contiguous block of memory.
28143 uint64_t resp_addr;
28145 * 64-bit Host Source Address.
28146 * This is where the modified data is.
28148 uint64_t host_src_addr;
28149 /* 16-bit directory entry index. */
28151 uint8_t unused_0[2];
28152 /* 32-bit NVRAM byte-offset to modify content from. */
28155 * Length of data to be modified, in bytes. The length shall
28159 uint8_t unused_1[4];
28160 } __attribute__((packed));
28162 /* hwrm_nvm_modify_output (size:128b/16B) */
28163 struct hwrm_nvm_modify_output {
28164 /* The specific error status for the command. */
28165 uint16_t error_code;
28166 /* The HWRM command request type. */
28168 /* The sequence ID from the original command. */
28170 /* The length of the response data in number of bytes. */
28172 uint8_t unused_0[7];
28174 * This field is used in Output records to indicate that the output
28175 * is completely written to RAM. This field should be read as '1'
28176 * to indicate that the output has been completely written.
28177 * When writing a command completion or response to an internal processor,
28178 * the order of writes has to be such that this field is written last.
28181 } __attribute__((packed));
28183 /***************************
28184 * hwrm_nvm_find_dir_entry *
28185 ***************************/
28188 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
28189 struct hwrm_nvm_find_dir_entry_input {
28190 /* The HWRM command request type. */
28193 * The completion ring to send the completion event on. This should
28194 * be the NQ ID returned from the `nq_alloc` HWRM command.
28196 uint16_t cmpl_ring;
28198 * The sequence ID is used by the driver for tracking multiple
28199 * commands. This ID is treated as opaque data by the firmware and
28200 * the value is returned in the `hwrm_resp_hdr` upon completion.
28204 * The target ID of the command:
28205 * * 0x0-0xFFF8 - The function ID
28206 * * 0xFFF8-0xFFFE - Reserved for internal processors
28209 uint16_t target_id;
28211 * A physical address pointer pointing to a host buffer that the
28212 * command's response data will be written. This can be either a host
28213 * physical address (HPA) or a guest physical address (GPA) and must
28214 * point to a physically contiguous block of memory.
28216 uint64_t resp_addr;
28219 * This bit must be '1' for the dir_idx_valid field to be
28222 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
28224 /* Directory Entry Index */
28226 /* Directory Entry (Image) Type */
28229 * Directory ordinal.
28230 * The instance of this Directory Type
28232 uint16_t dir_ordinal;
28233 /* The Directory Entry Extension flags. */
28235 /* This value indicates the search option using dir_ordinal. */
28236 uint8_t opt_ordinal;
28237 /* This value indicates the search option using dir_ordinal. */
28238 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
28239 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
28240 /* Equal to specified ordinal value. */
28241 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
28242 /* Greater than or equal to specified ordinal value */
28243 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
28244 /* Greater than specified ordinal value */
28245 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
28246 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
28247 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
28248 uint8_t unused_0[3];
28249 } __attribute__((packed));
28251 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
28252 struct hwrm_nvm_find_dir_entry_output {
28253 /* The specific error status for the command. */
28254 uint16_t error_code;
28255 /* The HWRM command request type. */
28257 /* The sequence ID from the original command. */
28259 /* The length of the response data in number of bytes. */
28261 /* Allocated NVRAM for this directory entry, in bytes. */
28262 uint32_t dir_item_length;
28263 /* Size of the stored data for this directory entry, in bytes. */
28264 uint32_t dir_data_length;
28266 * Firmware version.
28267 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
28270 /* Directory ordinal. */
28271 uint16_t dir_ordinal;
28272 /* Directory Entry Index */
28274 uint8_t unused_0[7];
28276 * This field is used in Output records to indicate that the output
28277 * is completely written to RAM. This field should be read as '1'
28278 * to indicate that the output has been completely written.
28279 * When writing a command completion or response to an internal processor,
28280 * the order of writes has to be such that this field is written last.
28283 } __attribute__((packed));
28285 /****************************
28286 * hwrm_nvm_erase_dir_entry *
28287 ****************************/
28290 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
28291 struct hwrm_nvm_erase_dir_entry_input {
28292 /* The HWRM command request type. */
28295 * The completion ring to send the completion event on. This should
28296 * be the NQ ID returned from the `nq_alloc` HWRM command.
28298 uint16_t cmpl_ring;
28300 * The sequence ID is used by the driver for tracking multiple
28301 * commands. This ID is treated as opaque data by the firmware and
28302 * the value is returned in the `hwrm_resp_hdr` upon completion.
28306 * The target ID of the command:
28307 * * 0x0-0xFFF8 - The function ID
28308 * * 0xFFF8-0xFFFE - Reserved for internal processors
28311 uint16_t target_id;
28313 * A physical address pointer pointing to a host buffer that the
28314 * command's response data will be written. This can be either a host
28315 * physical address (HPA) or a guest physical address (GPA) and must
28316 * point to a physically contiguous block of memory.
28318 uint64_t resp_addr;
28319 /* Directory Entry Index */
28321 uint8_t unused_0[6];
28322 } __attribute__((packed));
28324 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
28325 struct hwrm_nvm_erase_dir_entry_output {
28326 /* The specific error status for the command. */
28327 uint16_t error_code;
28328 /* The HWRM command request type. */
28330 /* The sequence ID from the original command. */
28332 /* The length of the response data in number of bytes. */
28334 uint8_t unused_0[7];
28336 * This field is used in Output records to indicate that the output
28337 * is completely written to RAM. This field should be read as '1'
28338 * to indicate that the output has been completely written.
28339 * When writing a command completion or response to an internal processor,
28340 * the order of writes has to be such that this field is written last.
28343 } __attribute__((packed));
28345 /*************************
28346 * hwrm_nvm_get_dev_info *
28347 *************************/
28350 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
28351 struct hwrm_nvm_get_dev_info_input {
28352 /* The HWRM command request type. */
28355 * The completion ring to send the completion event on. This should
28356 * be the NQ ID returned from the `nq_alloc` HWRM command.
28358 uint16_t cmpl_ring;
28360 * The sequence ID is used by the driver for tracking multiple
28361 * commands. This ID is treated as opaque data by the firmware and
28362 * the value is returned in the `hwrm_resp_hdr` upon completion.
28366 * The target ID of the command:
28367 * * 0x0-0xFFF8 - The function ID
28368 * * 0xFFF8-0xFFFE - Reserved for internal processors
28371 uint16_t target_id;
28373 * A physical address pointer pointing to a host buffer that the
28374 * command's response data will be written. This can be either a host
28375 * physical address (HPA) or a guest physical address (GPA) and must
28376 * point to a physically contiguous block of memory.
28378 uint64_t resp_addr;
28379 } __attribute__((packed));
28381 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
28382 struct hwrm_nvm_get_dev_info_output {
28383 /* The specific error status for the command. */
28384 uint16_t error_code;
28385 /* The HWRM command request type. */
28387 /* The sequence ID from the original command. */
28389 /* The length of the response data in number of bytes. */
28391 /* Manufacturer ID. */
28392 uint16_t manufacturer_id;
28394 uint16_t device_id;
28395 /* Sector size of the NVRAM device. */
28396 uint32_t sector_size;
28397 /* Total size, in bytes of the NVRAM device. */
28398 uint32_t nvram_size;
28399 uint32_t reserved_size;
28400 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
28401 uint32_t available_size;
28402 uint8_t unused_0[3];
28404 * This field is used in Output records to indicate that the output
28405 * is completely written to RAM. This field should be read as '1'
28406 * to indicate that the output has been completely written.
28407 * When writing a command completion or response to an internal processor,
28408 * the order of writes has to be such that this field is written last.
28411 } __attribute__((packed));
28413 /**************************
28414 * hwrm_nvm_mod_dir_entry *
28415 **************************/
28418 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
28419 struct hwrm_nvm_mod_dir_entry_input {
28420 /* The HWRM command request type. */
28423 * The completion ring to send the completion event on. This should
28424 * be the NQ ID returned from the `nq_alloc` HWRM command.
28426 uint16_t cmpl_ring;
28428 * The sequence ID is used by the driver for tracking multiple
28429 * commands. This ID is treated as opaque data by the firmware and
28430 * the value is returned in the `hwrm_resp_hdr` upon completion.
28434 * The target ID of the command:
28435 * * 0x0-0xFFF8 - The function ID
28436 * * 0xFFF8-0xFFFE - Reserved for internal processors
28439 uint16_t target_id;
28441 * A physical address pointer pointing to a host buffer that the
28442 * command's response data will be written. This can be either a host
28443 * physical address (HPA) or a guest physical address (GPA) and must
28444 * point to a physically contiguous block of memory.
28446 uint64_t resp_addr;
28449 * This bit must be '1' for the checksum field to be
28452 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
28453 /* Directory Entry Index */
28456 * Directory ordinal.
28457 * The (0-based) instance of this Directory Type.
28459 uint16_t dir_ordinal;
28460 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
28462 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
28465 * If valid, then this field updates the checksum
28466 * value of the content in the directory entry.
28469 } __attribute__((packed));
28471 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
28472 struct hwrm_nvm_mod_dir_entry_output {
28473 /* The specific error status for the command. */
28474 uint16_t error_code;
28475 /* The HWRM command request type. */
28477 /* The sequence ID from the original command. */
28479 /* The length of the response data in number of bytes. */
28481 uint8_t unused_0[7];
28483 * This field is used in Output records to indicate that the output
28484 * is completely written to RAM. This field should be read as '1'
28485 * to indicate that the output has been completely written.
28486 * When writing a command completion or response to an internal processor,
28487 * the order of writes has to be such that this field is written last.
28490 } __attribute__((packed));
28492 /**************************
28493 * hwrm_nvm_verify_update *
28494 **************************/
28497 /* hwrm_nvm_verify_update_input (size:192b/24B) */
28498 struct hwrm_nvm_verify_update_input {
28499 /* The HWRM command request type. */
28502 * The completion ring to send the completion event on. This should
28503 * be the NQ ID returned from the `nq_alloc` HWRM command.
28505 uint16_t cmpl_ring;
28507 * The sequence ID is used by the driver for tracking multiple
28508 * commands. This ID is treated as opaque data by the firmware and
28509 * the value is returned in the `hwrm_resp_hdr` upon completion.
28513 * The target ID of the command:
28514 * * 0x0-0xFFF8 - The function ID
28515 * * 0xFFF8-0xFFFE - Reserved for internal processors
28518 uint16_t target_id;
28520 * A physical address pointer pointing to a host buffer that the
28521 * command's response data will be written. This can be either a host
28522 * physical address (HPA) or a guest physical address (GPA) and must
28523 * point to a physically contiguous block of memory.
28525 uint64_t resp_addr;
28526 /* Directory Entry Type, to be verified. */
28529 * Directory ordinal.
28530 * The instance of the Directory Type to be verified.
28532 uint16_t dir_ordinal;
28534 * The Directory Entry Extension flags.
28535 * The "UPDATE" extension flag must be set in this value.
28536 * A corresponding directory entry with the same type and ordinal values but *without*
28537 * the "UPDATE" extension flag must also exist. The other flags of the extension must
28538 * be identical between the active and update entries.
28541 uint8_t unused_0[2];
28542 } __attribute__((packed));
28544 /* hwrm_nvm_verify_update_output (size:128b/16B) */
28545 struct hwrm_nvm_verify_update_output {
28546 /* The specific error status for the command. */
28547 uint16_t error_code;
28548 /* The HWRM command request type. */
28550 /* The sequence ID from the original command. */
28552 /* The length of the response data in number of bytes. */
28554 uint8_t unused_0[7];
28556 * This field is used in Output records to indicate that the output
28557 * is completely written to RAM. This field should be read as '1'
28558 * to indicate that the output has been completely written.
28559 * When writing a command completion or response to an internal processor,
28560 * the order of writes has to be such that this field is written last.
28563 } __attribute__((packed));
28565 /***************************
28566 * hwrm_nvm_install_update *
28567 ***************************/
28570 /* hwrm_nvm_install_update_input (size:192b/24B) */
28571 struct hwrm_nvm_install_update_input {
28572 /* The HWRM command request type. */
28575 * The completion ring to send the completion event on. This should
28576 * be the NQ ID returned from the `nq_alloc` HWRM command.
28578 uint16_t cmpl_ring;
28580 * The sequence ID is used by the driver for tracking multiple
28581 * commands. This ID is treated as opaque data by the firmware and
28582 * the value is returned in the `hwrm_resp_hdr` upon completion.
28586 * The target ID of the command:
28587 * * 0x0-0xFFF8 - The function ID
28588 * * 0xFFF8-0xFFFE - Reserved for internal processors
28591 uint16_t target_id;
28593 * A physical address pointer pointing to a host buffer that the
28594 * command's response data will be written. This can be either a host
28595 * physical address (HPA) or a guest physical address (GPA) and must
28596 * point to a physically contiguous block of memory.
28598 uint64_t resp_addr;
28600 * Installation type. If the value 3 through 0xffff is used,
28601 * only packaged items with that type value will be installed and
28602 * conditional installation directives for those packaged items
28603 * will be over-ridden (i.e. 'create' or 'replace' will be treated
28606 uint32_t install_type;
28608 * Perform a normal package installation. Conditional installation
28609 * directives (e.g. 'create' and 'replace') of packaged items
28610 * will be followed.
28612 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
28614 * Install all packaged items regardless of installation directive
28615 * (i.e. treat all packaged items as though they have an installation
28616 * directive of 'install').
28618 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
28619 UINT32_C(0xffffffff)
28620 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
28621 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
28623 /* If set to 1, then securely erase all unused locations in persistent storage. */
28624 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
28627 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
28628 * When combined with erase_unused_space then unspecified images will be securely erased.
28630 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
28633 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
28634 * Allow additional time for this command to complete if this bit is set to 1.
28636 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
28638 uint8_t unused_0[2];
28639 } __attribute__((packed));
28641 /* hwrm_nvm_install_update_output (size:192b/24B) */
28642 struct hwrm_nvm_install_update_output {
28643 /* The specific error status for the command. */
28644 uint16_t error_code;
28645 /* The HWRM command request type. */
28647 /* The sequence ID from the original command. */
28649 /* The length of the response data in number of bytes. */
28652 * Bit-mask of successfully installed items.
28653 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
28654 * A value of 0 indicates that no items were successfully installed.
28656 uint64_t installed_items;
28657 /* result is 8 b */
28659 /* There was no problem with the package installation. */
28660 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
28661 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
28662 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
28663 /* problem_item is 8 b */
28664 uint8_t problem_item;
28665 /* There was no problem with any packaged items. */
28666 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
28668 /* There was a problem with the NVM package itself. */
28669 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
28671 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
28672 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
28673 /* reset_required is 8 b */
28674 uint8_t reset_required;
28676 * No reset is required for installed/updated firmware or
28677 * microcode to take effect.
28679 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
28682 * A PCIe reset (e.g. system reboot) is
28683 * required for newly installed/updated firmware or
28684 * microcode to take effect.
28686 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
28689 * A controller power reset (e.g. system power-cycle) is
28690 * required for newly installed/updated firmware or
28691 * microcode to take effect. Some newly installed/updated
28692 * firmware or microcode may still take effect upon the
28695 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
28697 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
28698 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
28699 uint8_t unused_0[4];
28701 * This field is used in Output records to indicate that the output
28702 * is completely written to RAM. This field should be read as '1'
28703 * to indicate that the output has been completely written.
28704 * When writing a command completion or response to an internal processor,
28705 * the order of writes has to be such that this field is written last.
28708 } __attribute__((packed));
28710 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
28711 struct hwrm_nvm_install_update_cmd_err {
28713 * command specific error codes that goes to
28714 * the cmd_err field in Common HWRM Error Response.
28717 /* Unknown error */
28718 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28719 /* Unable to complete operation due to fragmentation */
28720 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
28721 /* nvm is completely full. */
28722 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
28723 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
28724 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
28725 uint8_t unused_0[7];
28726 } __attribute__((packed));
28728 /******************
28730 ******************/
28733 /* hwrm_nvm_flush_input (size:128b/16B) */
28734 struct hwrm_nvm_flush_input {
28735 /* The HWRM command request type. */
28738 * The completion ring to send the completion event on. This should
28739 * be the NQ ID returned from the `nq_alloc` HWRM command.
28741 uint16_t cmpl_ring;
28743 * The sequence ID is used by the driver for tracking multiple
28744 * commands. This ID is treated as opaque data by the firmware and
28745 * the value is returned in the `hwrm_resp_hdr` upon completion.
28749 * The target ID of the command:
28750 * * 0x0-0xFFF8 - The function ID
28751 * * 0xFFF8-0xFFFE - Reserved for internal processors
28754 uint16_t target_id;
28756 * A physical address pointer pointing to a host buffer that the
28757 * command's response data will be written. This can be either a host
28758 * physical address (HPA) or a guest physical address (GPA) and must
28759 * point to a physically contiguous block of memory.
28761 uint64_t resp_addr;
28762 } __attribute__((packed));
28764 /* hwrm_nvm_flush_output (size:128b/16B) */
28765 struct hwrm_nvm_flush_output {
28766 /* The specific error status for the command. */
28767 uint16_t error_code;
28768 /* The HWRM command request type. */
28770 /* The sequence ID from the original command. */
28772 /* The length of the response data in number of bytes. */
28774 uint8_t unused_0[7];
28776 * This field is used in Output records to indicate that the output
28777 * is completely written to RAM. This field should be read as '1'
28778 * to indicate that the output has been completely written.
28779 * When writing a command completion or response to an internal processor,
28780 * the order of writes has to be such that this field is written last.
28783 } __attribute__((packed));
28785 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
28786 struct hwrm_nvm_flush_cmd_err {
28788 * command specific error codes that goes to
28789 * the cmd_err field in Common HWRM Error Response.
28792 /* Unknown error */
28793 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28794 /* flush could not be performed */
28795 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
28796 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
28797 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
28798 uint8_t unused_0[7];
28799 } __attribute__((packed));
28801 /*************************
28802 * hwrm_nvm_get_variable *
28803 *************************/
28806 /* hwrm_nvm_get_variable_input (size:320b/40B) */
28807 struct hwrm_nvm_get_variable_input {
28808 /* The HWRM command request type. */
28811 * The completion ring to send the completion event on. This should
28812 * be the NQ ID returned from the `nq_alloc` HWRM command.
28814 uint16_t cmpl_ring;
28816 * The sequence ID is used by the driver for tracking multiple
28817 * commands. This ID is treated as opaque data by the firmware and
28818 * the value is returned in the `hwrm_resp_hdr` upon completion.
28822 * The target ID of the command:
28823 * * 0x0-0xFFF8 - The function ID
28824 * * 0xFFF8-0xFFFE - Reserved for internal processors
28827 uint16_t target_id;
28829 * A physical address pointer pointing to a host buffer that the
28830 * command's response data will be written. This can be either a host
28831 * physical address (HPA) or a guest physical address (GPA) and must
28832 * point to a physically contiguous block of memory.
28834 uint64_t resp_addr;
28836 * This is the host address where
28837 * nvm variable will be stored
28839 uint64_t dest_data_addr;
28840 /* size of data in bits */
28842 /* nvm cfg option number */
28843 uint16_t option_num;
28845 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
28847 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
28849 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
28850 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
28852 * Number of dimensions for this nvm configuration variable.
28853 * This value indicates how many of the indexN values to use.
28854 * A value of 0 means that none of the indexN values are valid.
28855 * A value of 1 requires at index0 is valued, a value of 2
28856 * requires that index0 and index1 are valid, and so forth
28858 uint16_t dimensions;
28859 /* index for the 1st dimensions */
28861 /* index for the 2nd dimensions */
28863 /* index for the 3rd dimensions */
28865 /* index for the 4th dimensions */
28869 * When this bit is set to 1, the factory default value will be returned,
28870 * 0 returns the operational value.
28872 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
28875 } __attribute__((packed));
28877 /* hwrm_nvm_get_variable_output (size:128b/16B) */
28878 struct hwrm_nvm_get_variable_output {
28879 /* The specific error status for the command. */
28880 uint16_t error_code;
28881 /* The HWRM command request type. */
28883 /* The sequence ID from the original command. */
28885 /* The length of the response data in number of bytes. */
28887 /* size of data of the actual variable retrieved in bits */
28890 * option_num is the option number for the data retrieved. It is possible in the
28891 * future that the option number returned would be different than requested. This
28892 * condition could occur if an option is deprecated and a new option id is defined
28893 * with similar characteristics, but has a slightly different definition. This
28894 * also makes it convenient for the caller to identify the variable result with
28895 * the option id from the response.
28897 uint16_t option_num;
28899 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
28901 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
28903 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
28904 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
28905 uint8_t unused_0[3];
28907 * This field is used in Output records to indicate that the output
28908 * is completely written to RAM. This field should be read as '1'
28909 * to indicate that the output has been completely written.
28910 * When writing a command completion or response to an internal processor,
28911 * the order of writes has to be such that this field is written last.
28914 } __attribute__((packed));
28916 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
28917 struct hwrm_nvm_get_variable_cmd_err {
28919 * command specific error codes that goes to
28920 * the cmd_err field in Common HWRM Error Response.
28923 /* Unknown error */
28924 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28925 /* variable does not exist */
28926 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
28927 /* configuration is corrupted and the variable cannot be saved */
28928 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
28929 /* length specified is too small */
28930 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
28931 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
28932 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
28933 uint8_t unused_0[7];
28934 } __attribute__((packed));
28936 /*************************
28937 * hwrm_nvm_set_variable *
28938 *************************/
28941 /* hwrm_nvm_set_variable_input (size:320b/40B) */
28942 struct hwrm_nvm_set_variable_input {
28943 /* The HWRM command request type. */
28946 * The completion ring to send the completion event on. This should
28947 * be the NQ ID returned from the `nq_alloc` HWRM command.
28949 uint16_t cmpl_ring;
28951 * The sequence ID is used by the driver for tracking multiple
28952 * commands. This ID is treated as opaque data by the firmware and
28953 * the value is returned in the `hwrm_resp_hdr` upon completion.
28957 * The target ID of the command:
28958 * * 0x0-0xFFF8 - The function ID
28959 * * 0xFFF8-0xFFFE - Reserved for internal processors
28962 uint16_t target_id;
28964 * A physical address pointer pointing to a host buffer that the
28965 * command's response data will be written. This can be either a host
28966 * physical address (HPA) or a guest physical address (GPA) and must
28967 * point to a physically contiguous block of memory.
28969 uint64_t resp_addr;
28971 * This is the host address where
28972 * nvm variable will be copied from
28974 uint64_t src_data_addr;
28975 /* size of data in bits */
28977 /* nvm cfg option number */
28978 uint16_t option_num;
28980 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
28982 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
28984 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
28985 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
28987 * Number of dimensions for this nvm configuration variable.
28988 * This value indicates how many of the indexN values to use.
28989 * A value of 0 means that none of the indexN values are valid.
28990 * A value of 1 requires at index0 is valued, a value of 2
28991 * requires that index0 and index1 are valid, and so forth
28993 uint16_t dimensions;
28994 /* index for the 1st dimensions */
28996 /* index for the 2nd dimensions */
28998 /* index for the 3rd dimensions */
29000 /* index for the 4th dimensions */
29003 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
29004 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
29006 /* encryption method */
29007 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
29009 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
29010 /* No encryption. */
29011 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
29012 (UINT32_C(0x0) << 1)
29013 /* one-way encryption. */
29014 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
29015 (UINT32_C(0x1) << 1)
29016 /* symmetric AES256 encryption. */
29017 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
29018 (UINT32_C(0x2) << 1)
29019 /* SHA1 digest appended to plaintext contents, for authentication */
29020 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
29021 (UINT32_C(0x3) << 1)
29022 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
29023 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
29025 } __attribute__((packed));
29027 /* hwrm_nvm_set_variable_output (size:128b/16B) */
29028 struct hwrm_nvm_set_variable_output {
29029 /* The specific error status for the command. */
29030 uint16_t error_code;
29031 /* The HWRM command request type. */
29033 /* The sequence ID from the original command. */
29035 /* The length of the response data in number of bytes. */
29037 uint8_t unused_0[7];
29039 * This field is used in Output records to indicate that the output
29040 * is completely written to RAM. This field should be read as '1'
29041 * to indicate that the output has been completely written.
29042 * When writing a command completion or response to an internal processor,
29043 * the order of writes has to be such that this field is written last.
29046 } __attribute__((packed));
29048 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
29049 struct hwrm_nvm_set_variable_cmd_err {
29051 * command specific error codes that goes to
29052 * the cmd_err field in Common HWRM Error Response.
29055 /* Unknown error */
29056 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
29057 /* variable does not exist */
29058 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
29059 /* configuration is corrupted and the variable cannot be saved */
29060 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
29061 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
29062 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
29063 uint8_t unused_0[7];
29064 } __attribute__((packed));
29066 /****************************
29067 * hwrm_nvm_validate_option *
29068 ****************************/
29071 /* hwrm_nvm_validate_option_input (size:320b/40B) */
29072 struct hwrm_nvm_validate_option_input {
29073 /* The HWRM command request type. */
29076 * The completion ring to send the completion event on. This should
29077 * be the NQ ID returned from the `nq_alloc` HWRM command.
29079 uint16_t cmpl_ring;
29081 * The sequence ID is used by the driver for tracking multiple
29082 * commands. This ID is treated as opaque data by the firmware and
29083 * the value is returned in the `hwrm_resp_hdr` upon completion.
29087 * The target ID of the command:
29088 * * 0x0-0xFFF8 - The function ID
29089 * * 0xFFF8-0xFFFE - Reserved for internal processors
29092 uint16_t target_id;
29094 * A physical address pointer pointing to a host buffer that the
29095 * command's response data will be written. This can be either a host
29096 * physical address (HPA) or a guest physical address (GPA) and must
29097 * point to a physically contiguous block of memory.
29099 uint64_t resp_addr;
29101 * This is the host address where
29102 * nvm variable will be copied from
29104 uint64_t src_data_addr;
29105 /* size of data in bits */
29107 /* nvm cfg option number */
29108 uint16_t option_num;
29110 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
29113 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
29115 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
29116 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
29118 * Number of dimensions for this nvm configuration variable.
29119 * This value indicates how many of the indexN values to use.
29120 * A value of 0 means that none of the indexN values are valid.
29121 * A value of 1 requires at index0 is valued, a value of 2
29122 * requires that index0 and index1 are valid, and so forth
29124 uint16_t dimensions;
29125 /* index for the 1st dimensions */
29127 /* index for the 2nd dimensions */
29129 /* index for the 3rd dimensions */
29131 /* index for the 4th dimensions */
29133 uint8_t unused_0[2];
29134 } __attribute__((packed));
29136 /* hwrm_nvm_validate_option_output (size:128b/16B) */
29137 struct hwrm_nvm_validate_option_output {
29138 /* The specific error status for the command. */
29139 uint16_t error_code;
29140 /* The HWRM command request type. */
29142 /* The sequence ID from the original command. */
29144 /* The length of the response data in number of bytes. */
29147 /* indicates that the value provided for the option is not matching with the saved data. */
29148 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
29149 /* indicates that the value provided for the option is matching the saved data. */
29150 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
29151 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
29152 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
29153 uint8_t unused_0[6];
29155 * This field is used in Output records to indicate that the output
29156 * is completely written to RAM. This field should be read as '1'
29157 * to indicate that the output has been completely written.
29158 * When writing a command completion or response to an internal processor,
29159 * the order of writes has to be such that this field is written last.
29162 } __attribute__((packed));
29164 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
29165 struct hwrm_nvm_validate_option_cmd_err {
29167 * command specific error codes that goes to
29168 * the cmd_err field in Common HWRM Error Response.
29171 /* Unknown error */
29172 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
29173 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
29174 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
29175 uint8_t unused_0[7];
29176 } __attribute__((packed));
29178 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */