1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2022 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
273 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
274 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
275 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
276 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
277 /* Reserved for future use. */
278 #define HWRM_RESERVED1 UINT32_C(0x10)
279 #define HWRM_FUNC_RESET UINT32_C(0x11)
280 #define HWRM_FUNC_GETFID UINT32_C(0x12)
281 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
282 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
283 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
284 #define HWRM_FUNC_QCFG UINT32_C(0x16)
285 #define HWRM_FUNC_CFG UINT32_C(0x17)
286 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
287 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
288 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
289 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
290 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
291 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
292 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
293 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
294 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
295 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
297 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
298 #define HWRM_PORT_QSTATS UINT32_C(0x23)
299 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
301 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
303 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
304 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
305 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
307 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
308 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
309 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
310 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
311 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
312 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
313 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
314 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
315 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
316 #define HWRM_QUEUE_CFG UINT32_C(0x32)
317 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
318 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
319 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
320 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
321 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
322 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
323 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
324 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
325 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
326 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 /* Updates specific fields in RX VNIC structure */
341 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
342 #define HWRM_RING_ALLOC UINT32_C(0x50)
343 #define HWRM_RING_FREE UINT32_C(0x51)
344 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
345 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
346 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
347 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
348 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
349 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
350 #define HWRM_RING_RESET UINT32_C(0x5e)
351 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
352 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
353 #define HWRM_RING_CFG UINT32_C(0x62)
354 #define HWRM_RING_QCFG UINT32_C(0x63)
355 /* Reserved for future use. */
356 #define HWRM_RESERVED5 UINT32_C(0x64)
357 /* Reserved for future use. */
358 #define HWRM_RESERVED6 UINT32_C(0x65)
359 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
360 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
361 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
362 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
363 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
364 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
365 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
366 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
367 #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
368 #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
369 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
370 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
371 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
372 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
373 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
374 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
375 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
377 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
379 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
380 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
381 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
382 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
384 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
386 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
388 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
389 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
390 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
391 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
392 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
393 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
394 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
395 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
396 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
397 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
398 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
399 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
400 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
401 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
402 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
404 #define HWRM_RESERVED7 UINT32_C(0xba)
405 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
406 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
407 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
408 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
409 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
410 #define HWRM_FW_RESET UINT32_C(0xc0)
411 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
412 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
413 #define HWRM_FW_SYNC UINT32_C(0xc3)
414 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
415 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
416 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
417 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
419 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
421 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
423 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
425 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
427 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
428 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
429 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
430 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
431 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
432 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
433 #define HWRM_FWD_RESP UINT32_C(0xd2)
434 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
435 #define HWRM_OEM_CMD UINT32_C(0xd4)
436 /* Tells the fw to run PRBS test on a given port and lane. */
437 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
438 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
439 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
440 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
441 /* Tells the fw to collect dsc dump on a given port and lane. */
442 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
443 #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
444 #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
445 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
446 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
447 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
448 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
449 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
450 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
451 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
452 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
454 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
456 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
458 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
460 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
462 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
464 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
466 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
468 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
470 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
472 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
474 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
476 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
478 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
480 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
482 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
484 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
486 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
488 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
490 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
491 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
492 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
493 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
495 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
497 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
499 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
501 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
502 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
503 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
505 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
507 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
509 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
511 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
513 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
515 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
517 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
519 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
521 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
523 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
525 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
527 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
529 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
531 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
533 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
535 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
537 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
539 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
540 /* Experimental - DEPRECATED */
541 #define HWRM_CFA_TFLIB UINT32_C(0x125)
543 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
545 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
547 #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128)
549 #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129)
550 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
551 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
552 /* Engine CKV - Add a new CKEK used to encrypt keys. */
553 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
554 /* Engine CKV - Delete a previously added CKEK. */
555 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
556 /* Engine CKV - Add a new key to the key vault. */
557 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
558 /* Engine CKV - Delete a key from the key vault. */
559 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
560 /* Engine CKV - Delete all keys from the key vault. */
561 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
562 /* Engine CKV - Get random data. */
563 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
564 /* Engine CKV - Generate and encrypt a new AES key. */
565 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
566 /* Engine CKV - Configure a label index with a label value. */
567 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
568 /* Engine CKV - Query a label */
569 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
570 /* Engine - Query the available queue groups configuration. */
571 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
572 /* Engine - Query the queue groups assigned to a function. */
573 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
574 /* Engine - Query the available queue group meter profile configuration. */
575 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
576 /* Engine - Query the configuration of a queue group meter profile. */
577 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
578 /* Engine - Allocate a queue group meter profile. */
579 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
580 /* Engine - Free a queue group meter profile. */
581 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
582 /* Engine - Query the meters assigned to a queue group. */
583 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
584 /* Engine - Bind a queue group meter profile to a queue group. */
585 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
586 /* Engine - Unbind a queue group meter profile from a queue group. */
587 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
588 /* Engine - Bind a queue group to a function. */
589 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
590 /* Engine - Query the scheduling group configuration. */
591 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
592 /* Engine - Query the queue groups assigned to a scheduling group. */
593 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
594 /* Engine - Query the configuration of a scheduling group's meter profiles. */
595 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
596 /* Engine - Configure a scheduling group's meter profiles. */
597 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
598 /* Engine - Bind a queue group to a scheduling group. */
599 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
600 /* Engine - Unbind a queue group from its scheduling group. */
601 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
602 /* Engine - Query the Engine configuration. */
603 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
604 /* Engine - Configure the statistics accumulator for an Engine. */
605 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
606 /* Engine - Clear the statistics accumulator for an Engine. */
607 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
608 /* Engine - Query the statistics accumulator for an Engine. */
609 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
610 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
611 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
612 /* Engine - Allocate an Engine RQ. */
613 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
614 /* Engine - Free an Engine RQ. */
615 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
616 /* Engine - Allocate an Engine CQ. */
617 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
618 /* Engine - Free an Engine CQ. */
619 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
620 /* Engine - Allocate an NQ. */
621 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
622 /* Engine - Free an NQ. */
623 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
624 /* Engine - Set the on-die RQE credit update location. */
625 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
626 /* Engine - Query the engine function configuration. */
627 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
629 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
631 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
633 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
635 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
637 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
638 /* Configures the BW of any VF */
639 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
640 /* Queries the BW of any VF */
641 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
642 /* Queries pf ids belong to specified host(s) */
643 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
644 /* Queries extended stats per function */
645 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
646 /* Queries extended statistics context */
647 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
648 /* Configure SoC packet DMA settings */
649 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
650 /* Query SoC packet DMA settings */
651 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
652 /* PTP - Queries configuration of timesync IO pins. */
653 #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
654 /* PTP - Configuration of timesync IO pins. */
655 #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
656 /* PTP - Configuration for disciplining PHC. */
657 #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
658 /* PTP - Queries for PHC timestamps. */
659 #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
660 /* PTP - Extended PTP configuration. */
661 #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
662 /* PTP - Query extended PTP configuration. */
663 #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
664 /* The command is used to allocate KTLS or QUIC key contexts. */
665 #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
666 /* The is the new API to configure backing stores. */
667 #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
668 /* The is the new API to query backing store configurations. */
669 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
670 /* To support doorbell pacing configuration. */
671 #define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5)
672 /* To query doorbell pacing configuration. */
673 #define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6)
675 * To broadcast the doorbell event to the drivers to
676 * initiate pacing of doorbells.
678 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
679 /* The is the new API to query backing store capabilities. */
680 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
682 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
684 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
686 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
688 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
690 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
692 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
693 /* Returns the current value of a free running counter from the device. */
694 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
696 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
698 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
700 * Tells the fw to run the DMA read from the host and DMA write
703 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
704 /* Tells the fw to program the fru memory */
705 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
706 /* Tells the fw to read the fru memory */
707 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
708 /* Used to provision SoC software images */
709 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
710 /* Retrieves the SoC status and image provisioning information */
711 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
712 /* Tells the fw to program the seeprom memory */
713 #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
714 /* Tells the fw to read the seeprom memory */
715 #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
716 /* Tells the fw to get the health of seeprom data */
717 #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
719 * The command is used for certificate provisioning to export a
720 * Certificate Signing Request (CSR) from the device.
722 #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
724 * The command is used for certificate provisioning to import a
725 * CA-signed certificate chain to the device.
727 #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
729 * The command is used for certificate provisioning to query the
732 #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
734 * The command is used to get the hash of the NVM configuration that is
735 * calculated during firmware boot.
737 #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
738 /* Retrieves the PSOC status and provisioning information. */
739 #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
741 * This command allows manufacturing tool to determine which selftests
742 * are available to be run.
744 #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
746 * This command allows manufacturing tool to request which selftests
749 #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
751 #define HWRM_TF UINT32_C(0x2bc)
753 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
755 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
757 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
759 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
761 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
763 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
765 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
767 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
769 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
771 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
773 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
775 #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
777 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
779 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
781 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
783 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
785 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
787 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
789 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
791 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
793 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
795 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
797 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
799 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
801 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
803 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
805 #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
807 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
809 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
811 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
813 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
815 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
817 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
819 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
821 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
823 #define HWRM_SV UINT32_C(0x400)
825 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
827 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
829 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
831 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
832 #define HWRM_DBG_DUMP UINT32_C(0xff14)
834 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
836 #define HWRM_DBG_CFG UINT32_C(0xff16)
838 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
840 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
842 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
844 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
846 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
848 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
850 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
852 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
853 /* Send driver debug information to firmware */
854 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
855 /* Query debug capabilities of firmware */
856 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
857 /* Retrieve debug settings of firmware */
858 #define HWRM_DBG_QCFG UINT32_C(0xff21)
859 /* Set destination parameters for crashdump medium */
860 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
862 #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
864 #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
866 #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
868 #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
870 #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
872 #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
874 #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
876 #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
878 #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
879 #define HWRM_NVM_DEFRAG UINT32_C(0xffec)
880 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
882 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
883 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
884 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
885 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
886 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
887 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
888 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
889 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
890 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
891 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
892 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
893 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
894 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
895 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
896 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
897 #define HWRM_NVM_READ UINT32_C(0xfffd)
898 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
899 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
900 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
901 uint16_t unused_0[3];
905 /* ret_codes (size:64b/8B) */
908 /* Request was successfully executed by the HWRM. */
909 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
910 /* The HWRM failed to execute the request. */
911 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
913 * The request contains invalid argument(s) or input
916 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
918 * The requester is not allowed to access the requested
919 * resource. This error code shall be provided in a
920 * response to a request to query or modify an existing
921 * resource that is not accessible by the requester.
923 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
925 * The HWRM is unable to allocate the requested resource.
926 * This code only applies to requests for HWRM resource
929 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
931 * Invalid combination of flags is specified in the
934 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
936 * Invalid combination of enables fields is specified in
939 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
941 * Request contains a required TLV that is not supported by
942 * the installed version of firmware.
944 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
946 * No firmware buffer available to accept the request. Driver
947 * should retry the request.
949 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
951 * This error code is only reported by firmware when some
952 * sub-option of a supported HWRM command is unsupported.
954 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
956 * This error code is only reported by firmware when the specific
957 * request is not able to process when the HOT reset in progress.
959 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
961 * This error code is only reported by firmware when the registered
962 * driver instances are not capable of hot reset.
964 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
966 * This error code is only reported by the firmware when during
967 * flow allocation when a request for a flow counter fails because
968 * the number of flow counters are exhausted.
970 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
972 * This error code is only reported by firmware when the registered
973 * driver instances requested to offloaded a flow but was unable to because
974 * the requested key's hash collides with the installed keys.
976 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
978 * This error code is only reported by firmware when the registered
979 * driver instances requested to offloaded a flow but was unable to because
980 * the same key has already been installed.
982 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
984 * Generic HWRM execution error that represents an
987 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
989 * Firmware is unable to service the request at the present time. Caller
990 * may try again later.
992 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
994 * This error code is reported by Firmware when an operation requested
995 * by the host is not allowed due to a secure lock violation.
997 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
999 * This error code is reported by Firmware when an operation requested
1000 * by a VF cannot be forwarded to the parent PF as required, either
1001 * because the PF is down or otherwise doesn't have an appropriate
1002 * async completion ring or associated forwarding buffers configured.
1004 #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
1006 * This value indicates that the HWRM response is in TLV format and
1007 * should be interpreted as one or more TLVs starting with the
1008 * hwrm_resp_hdr TLV. This value is not an indication of any error
1009 * by itself, just an indication that the response should be parsed
1010 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
1012 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
1014 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
1015 /* Unsupported or invalid command */
1016 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
1017 #define HWRM_ERR_CODE_LAST \
1018 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
1019 uint16_t unused_0[3];
1023 /* hwrm_err_output (size:128b/16B) */
1024 struct hwrm_err_output {
1026 * Pass/Fail or error type
1028 * Note: receiver to verify the in parameters, and fail the call
1029 * with an error when appropriate
1031 uint16_t error_code;
1032 /* This field returns the type of original request. */
1034 /* This field provides original sequence number of the command. */
1037 * This field is the length of the response in bytes. The
1038 * last byte of the response is a valid flag that will read
1039 * as '1' when the command has been completely written to
1043 /* debug info for this error response. */
1045 /* debug info for this error response. */
1048 * In the case of an error response, command specific error
1049 * code is returned in this field.
1053 * This field is used in Output records to indicate that the output
1054 * is completely written to RAM. This field should be read as '1'
1055 * to indicate that the output has been completely written.
1056 * When writing a command completion or response to an internal processor,
1057 * the order of writes has to be such that this field is written last.
1062 * Following is the signature for HWRM message field that indicates not
1063 * applicable (All F's). Need to cast it the size of the field if needed.
1065 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
1066 /* hwrm_func_buf_rgtr */
1067 #define HWRM_MAX_REQ_LEN 128
1068 /* hwrm_cfa_flow_info */
1069 #define HWRM_MAX_RESP_LEN 704
1070 /* 7 bit indirection table index. */
1071 #define HW_HASH_INDEX_SIZE 0x80
1072 #define HW_HASH_KEY_SIZE 40
1073 /* valid key for HWRM response */
1074 #define HWRM_RESP_VALID_KEY 1
1075 /* Reserved for BONO processor */
1076 #define HWRM_TARGET_ID_BONO 0xFFF8
1077 /* Reserved for KONG processor */
1078 #define HWRM_TARGET_ID_KONG 0xFFF9
1079 /* Reserved for APE processor */
1080 #define HWRM_TARGET_ID_APE 0xFFFA
1082 * This value will be used by tools for User-space HWRM Interface.
1083 * When tool execute any HWRM command with this target_id, firmware
1084 * will copy the response and/or data payload via register space instead
1087 #define HWRM_TARGET_ID_TOOLS 0xFFFD
1088 #define HWRM_VERSION_MAJOR 1
1089 #define HWRM_VERSION_MINOR 10
1090 #define HWRM_VERSION_UPDATE 2
1091 /* non-zero means beta version */
1092 #define HWRM_VERSION_RSVD 83
1093 #define HWRM_VERSION_STR "1.10.2.83"
1100 /* hwrm_ver_get_input (size:192b/24B) */
1101 struct hwrm_ver_get_input {
1102 /* The HWRM command request type. */
1105 * The completion ring to send the completion event on. This should
1106 * be the NQ ID returned from the `nq_alloc` HWRM command.
1110 * The sequence ID is used by the driver for tracking multiple
1111 * commands. This ID is treated as opaque data by the firmware and
1112 * the value is returned in the `hwrm_resp_hdr` upon completion.
1116 * The target ID of the command:
1117 * * 0x0-0xFFF8 - The function ID
1118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1119 * * 0xFFFD - Reserved for user-space HWRM interface
1124 * A physical address pointer pointing to a host buffer that the
1125 * command's response data will be written. This can be either a host
1126 * physical address (HPA) or a guest physical address (GPA) and must
1127 * point to a physically contiguous block of memory.
1131 * This field represents the major version of HWRM interface
1132 * specification supported by the driver HWRM implementation.
1133 * The interface major version is intended to change only when
1134 * non backward compatible changes are made to the HWRM
1135 * interface specification.
1137 uint8_t hwrm_intf_maj;
1139 * This field represents the minor version of HWRM interface
1140 * specification supported by the driver HWRM implementation.
1141 * A change in interface minor version is used to reflect
1142 * significant backward compatible modification to HWRM
1143 * interface specification.
1144 * This can be due to addition or removal of functionality.
1145 * HWRM interface specifications with the same major version
1146 * but different minor versions are compatible.
1148 uint8_t hwrm_intf_min;
1150 * This field represents the update version of HWRM interface
1151 * specification supported by the driver HWRM implementation.
1152 * The interface update version is used to reflect minor
1153 * changes or bug fixes to a released HWRM interface
1156 uint8_t hwrm_intf_upd;
1157 uint8_t unused_0[5];
1160 /* hwrm_ver_get_output (size:1408b/176B) */
1161 struct hwrm_ver_get_output {
1162 /* The specific error status for the command. */
1163 uint16_t error_code;
1164 /* The HWRM command request type. */
1166 /* The sequence ID from the original command. */
1168 /* The length of the response data in number of bytes. */
1171 * This field represents the major version of HWRM interface
1172 * specification supported by the HWRM implementation.
1173 * The interface major version is intended to change only when
1174 * non backward compatible changes are made to the HWRM
1175 * interface specification.
1176 * A HWRM implementation that is compliant with this
1177 * specification shall provide value of 1 in this field.
1179 uint8_t hwrm_intf_maj_8b;
1181 * This field represents the minor version of HWRM interface
1182 * specification supported by the HWRM implementation.
1183 * A change in interface minor version is used to reflect
1184 * significant backward compatible modification to HWRM
1185 * interface specification.
1186 * This can be due to addition or removal of functionality.
1187 * HWRM interface specifications with the same major version
1188 * but different minor versions are compatible.
1189 * A HWRM implementation that is compliant with this
1190 * specification shall provide value of 2 in this field.
1192 uint8_t hwrm_intf_min_8b;
1194 * This field represents the update version of HWRM interface
1195 * specification supported by the HWRM implementation.
1196 * The interface update version is used to reflect minor
1197 * changes or bug fixes to a released HWRM interface
1199 * A HWRM implementation that is compliant with this
1200 * specification shall provide value of 2 in this field.
1202 uint8_t hwrm_intf_upd_8b;
1203 uint8_t hwrm_intf_rsvd_8b;
1205 * This field represents the major version of HWRM firmware.
1206 * A change in firmware major version represents a major
1209 uint8_t hwrm_fw_maj_8b;
1211 * This field represents the minor version of HWRM firmware.
1212 * A change in firmware minor version represents significant
1213 * firmware functionality changes.
1215 uint8_t hwrm_fw_min_8b;
1217 * This field represents the build version of HWRM firmware.
1218 * A change in firmware build version represents bug fixes
1219 * to a released firmware.
1221 uint8_t hwrm_fw_bld_8b;
1223 * This field is a reserved field. This field can be used to
1224 * represent firmware branches or customer specific releases
1225 * tied to a specific (major,minor,update) version of the
1228 uint8_t hwrm_fw_rsvd_8b;
1230 * This field represents the major version of mgmt firmware.
1231 * A change in major version represents a major release.
1233 uint8_t mgmt_fw_maj_8b;
1235 * This field represents the minor version of mgmt firmware.
1236 * A change in minor version represents significant
1237 * functionality changes.
1239 uint8_t mgmt_fw_min_8b;
1241 * This field represents the build version of mgmt firmware.
1242 * A change in update version represents bug fixes.
1244 uint8_t mgmt_fw_bld_8b;
1246 * This field is a reserved field. This field can be used to
1247 * represent firmware branches or customer specific releases
1248 * tied to a specific (major,minor,update) version
1250 uint8_t mgmt_fw_rsvd_8b;
1252 * This field represents the major version of network
1254 * A change in major version represents a major release.
1256 uint8_t netctrl_fw_maj_8b;
1258 * This field represents the minor version of network
1260 * A change in minor version represents significant
1261 * functionality changes.
1263 uint8_t netctrl_fw_min_8b;
1265 * This field represents the build version of network
1267 * A change in update version represents bug fixes.
1269 uint8_t netctrl_fw_bld_8b;
1271 * This field is a reserved field. This field can be used to
1272 * represent firmware branches or customer specific releases
1273 * tied to a specific (major,minor,update) version
1275 uint8_t netctrl_fw_rsvd_8b;
1277 * This field is used to indicate device's capabilities and
1280 uint32_t dev_caps_cfg;
1282 * If set to 1, then secure firmware update behavior
1284 * If set to 0, then secure firmware update behavior is
1287 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1290 * If set to 1, then firmware based DCBX agent is supported.
1291 * If set to 0, then firmware based DCBX agent capability
1292 * is not supported on this device.
1294 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1297 * If set to 1, then HWRM short command format is supported.
1298 * If set to 0, then HWRM short command format is not supported.
1300 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1303 * If set to 1, then HWRM short command format is required.
1304 * If set to 0, then HWRM short command format is not required.
1306 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1309 * If set to 1, then the KONG host mailbox channel is supported.
1310 * If set to 0, then the KONG host mailbox channel is not supported.
1311 * By default, this flag should be 0 for older version of core firmware.
1313 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1316 * If set to 1, then the 64bit flow handle is supported in addition to the
1317 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1318 * supported. By default, this flag should be 0 for older version of core firmware.
1320 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1323 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1324 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1325 * If set to 0, then filter types not supported.
1326 * By default, this flag should be 0 for older version of core firmware.
1328 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1331 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1332 * If set to 0, firmware can't supported virtio vSwitch offload model.
1333 * By default, this flag should be 0 for older version of core firmware.
1335 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1338 * If set to 1, firmware is capable to support trusted VF.
1339 * If set to 0, firmware is not capable to support trusted VF.
1340 * By default, this flag should be 0 for older version of core firmware.
1342 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1345 * If set to 1, firmware is capable to support flow aging.
1346 * If set to 0, firmware is not capable to support flow aging.
1347 * By default, this flag should be 0 for older version of core firmware.
1349 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1352 * If set to 1, firmware is capable to support advanced flow counters like,
1353 * Meter drop counters and EEM counters.
1354 * If set to 0, firmware is not capable to support advanced flow counters.
1355 * By default, this flag should be 0 for older version of core firmware.
1357 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1360 * If set to 1, the firmware is able to support the use of the CFA
1361 * Extended Exact Match(EEM) feature.
1362 * If set to 0, firmware is not capable to support the use of the
1364 * By default, this flag should be 0 for older version of core firmware.
1366 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1369 * If set to 1, the firmware is able to support advance CFA flow management
1370 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1371 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1373 * By default, this flag should be 0 for older version of core firmware.
1375 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1378 * Deprecated and replaced with cfa_truflow_supported.
1379 * If set to 1, the firmware is able to support TFLIB features.
1380 * If set to 0, then the firmware doesn’t support TFLIB features.
1381 * By default, this flag should be 0 for older version of core firmware.
1383 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1386 * If set to 1, the firmware is able to support TruFlow features.
1387 * If set to 0, then the firmware doesn’t support TruFlow features.
1388 * By default, this flag should be 0 for older version of
1391 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1394 * If set to 1, then firmware supports secure boot.
1395 * If set to 0, then firmware doesn't support secure boot.
1397 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \
1400 * This field represents the major version of RoCE firmware.
1401 * A change in major version represents a major release.
1403 uint8_t roce_fw_maj_8b;
1405 * This field represents the minor version of RoCE firmware.
1406 * A change in minor version represents significant
1407 * functionality changes.
1409 uint8_t roce_fw_min_8b;
1411 * This field represents the build version of RoCE firmware.
1412 * A change in update version represents bug fixes.
1414 uint8_t roce_fw_bld_8b;
1416 * This field is a reserved field. This field can be used to
1417 * represent firmware branches or customer specific releases
1418 * tied to a specific (major,minor,update) version
1420 uint8_t roce_fw_rsvd_8b;
1422 * This field represents the name of HWRM FW (ASCII chars
1423 * with NULL at the end).
1425 char hwrm_fw_name[16];
1427 * This field represents the name of mgmt FW (ASCII chars
1428 * with NULL at the end).
1430 char mgmt_fw_name[16];
1432 * This field represents the name of network control
1433 * firmware (ASCII chars with NULL at the end).
1435 char netctrl_fw_name[16];
1436 /* This field represents the active board package name. */
1437 char active_pkg_name[16];
1439 * This field represents the name of RoCE FW (ASCII chars
1440 * with NULL at the end).
1442 char roce_fw_name[16];
1443 /* This field returns the chip number. */
1445 /* This field returns the revision of chip. */
1447 /* This field returns the chip metal number. */
1449 /* This field returns the bond id of the chip. */
1450 uint8_t chip_bond_id;
1451 /* This value indicates the type of platform used for chip implementation. */
1452 uint8_t chip_platform_type;
1454 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1455 /* FPGA platform of the chip. */
1456 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1457 /* Palladium platform of the chip. */
1458 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1459 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1460 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1462 * This field returns the maximum value of request window that
1463 * is supported by the HWRM. The request window is mapped
1464 * into device address space using MMIO.
1466 uint16_t max_req_win_len;
1468 * This field returns the maximum value of response buffer in
1471 uint16_t max_resp_len;
1473 * This field returns the default request timeout value in
1476 uint16_t def_req_timeout;
1478 * This field will indicate if any subsystems is not fully
1483 * If set to 1, it will indicate to host drivers that firmware is
1484 * not ready to start full blown HWRM commands. Host drivers should
1485 * re-try HWRM_VER_GET with some timeout period. The timeout period
1486 * can be selected up to 5 seconds. Host drivers should also check
1487 * for dev_not_rdy_backing_store to identify if flag is set due to
1488 * backing store not been available.
1489 * For Example, PCIe hot-plug:
1490 * Hot plug timing is system dependent. It generally takes up to
1491 * 600 milliseconds for firmware to clear DEV_NOT_RDY flag.
1492 * If set to 0, device is ready to accept all HWRM commands.
1494 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
1497 * If set to 1, external version present.
1498 * If set to 0, external version not present.
1500 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
1503 * Firmware sets this flag along with dev_not_rdy flag to indicate
1504 * host drivers that it has not completed resource initialization
1505 * required for data path operations. Host drivers should not send
1506 * any HWRM command that requires data path resources. Firmware will
1507 * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
1508 * those commands once both the flags are cleared.
1509 * If this flag and dev_not_rdy flag are set to 0, device is ready
1510 * to accept all HWRM commands.
1512 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
1514 uint8_t unused_0[2];
1516 * For backward compatibility this field must be set to 1.
1517 * Older drivers might look for this field to be 1 before
1518 * processing the message.
1522 * This field represents the major version of HWRM interface
1523 * specification supported by the HWRM implementation.
1524 * The interface major version is intended to change only when
1525 * non backward compatible changes are made to the HWRM
1526 * interface specification. A HWRM implementation that is
1527 * compliant with this specification shall provide value of 1
1530 uint16_t hwrm_intf_major;
1532 * This field represents the minor version of HWRM interface
1533 * specification supported by the HWRM implementation.
1534 * A change in interface minor version is used to reflect
1535 * significant backward compatible modification to HWRM
1536 * interface specification. This can be due to addition or
1537 * removal of functionality. HWRM interface specifications
1538 * with the same major version but different minor versions are
1539 * compatible. A HWRM implementation that is compliant with
1540 * this specification shall provide value of 2 in this field.
1542 uint16_t hwrm_intf_minor;
1544 * This field represents the update version of HWRM interface
1545 * specification supported by the HWRM implementation. The
1546 * interface update version is used to reflect minor changes or
1547 * bug fixes to a released HWRM interface specification.
1548 * A HWRM implementation that is compliant with this
1549 * specification shall provide value of 2 in this field.
1551 uint16_t hwrm_intf_build;
1553 * This field represents the patch version of HWRM interface
1554 * specification supported by the HWRM implementation.
1556 uint16_t hwrm_intf_patch;
1558 * This field represents the major version of HWRM firmware.
1559 * A change in firmware major version represents a major
1562 uint16_t hwrm_fw_major;
1564 * This field represents the minor version of HWRM firmware.
1565 * A change in firmware minor version represents significant
1566 * firmware functionality changes.
1568 uint16_t hwrm_fw_minor;
1570 * This field represents the build version of HWRM firmware.
1571 * A change in firmware build version represents bug fixes to
1572 * a released firmware.
1574 uint16_t hwrm_fw_build;
1576 * This field is a reserved field.
1577 * This field can be used to represent firmware branches or customer
1578 * specific releases tied to a specific (major,minor,update) version
1579 * of the HWRM firmware.
1581 uint16_t hwrm_fw_patch;
1583 * This field represents the major version of mgmt firmware.
1584 * A change in major version represents a major release.
1586 uint16_t mgmt_fw_major;
1588 * This field represents the minor version of HWRM firmware.
1589 * A change in firmware minor version represents significant
1590 * firmware functionality changes.
1592 uint16_t mgmt_fw_minor;
1594 * This field represents the build version of mgmt firmware.
1595 * A change in update version represents bug fixes.
1597 uint16_t mgmt_fw_build;
1599 * This field is a reserved field. This field can be used to
1600 * represent firmware branches or customer specific releases
1601 * tied to a specific (major,minor,update) version.
1603 uint16_t mgmt_fw_patch;
1605 * This field represents the major version of network control
1606 * firmware. A change in major version represents
1609 uint16_t netctrl_fw_major;
1611 * This field represents the minor version of network control
1612 * firmware. A change in minor version represents significant
1613 * functionality changes.
1615 uint16_t netctrl_fw_minor;
1617 * This field represents the build version of network control
1618 * firmware. A change in update version represents bug fixes.
1620 uint16_t netctrl_fw_build;
1622 * This field is a reserved field. This field can be used to
1623 * represent firmware branches or customer specific releases
1624 * tied to a specific (major,minor,update) version
1626 uint16_t netctrl_fw_patch;
1628 * This field represents the major version of RoCE firmware.
1629 * A change in major version represents a major release.
1631 uint16_t roce_fw_major;
1633 * This field represents the minor version of RoCE firmware.
1634 * A change in minor version represents significant
1635 * functionality changes.
1637 uint16_t roce_fw_minor;
1639 * This field represents the build version of RoCE firmware.
1640 * A change in update version represents bug fixes.
1642 uint16_t roce_fw_build;
1644 * This field is a reserved field. This field can be used to
1645 * represent firmware branches or customer specific releases
1646 * tied to a specific (major,minor,update) version
1648 uint16_t roce_fw_patch;
1650 * This field returns the maximum extended request length acceptable
1651 * by the device which allows requests greater than mailbox size when
1652 * used with the short cmd request format.
1654 uint16_t max_ext_req_len;
1656 * This field returns the maximum request timeout value in seconds.
1657 * For backward compatibility, a value of zero should be interpreted
1658 * as the default value of 40 seconds. Drivers should always honor the
1659 * maximum timeout, but are permitted to warn if a longer duration than
1660 * this default is advertised. Values larger than 40 seconds should
1661 * only be used as a stopgap measure to address a device limitation or
1662 * for the purposes of test and debugging. The long term goal is for
1663 * firmware to significantly reduce this value in the passage of time.
1665 uint16_t max_req_timeout;
1666 uint8_t unused_1[3];
1668 * This field is used in Output records to indicate that the output
1669 * is completely written to RAM. This field should be read as '1'
1670 * to indicate that the output has been completely written.
1671 * When writing a command completion or response to an internal processor,
1672 * the order of writes has to be such that this field is written last.
1677 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1678 struct cfa_bds_read_cmd_data_msg {
1679 /* This value selects the format for the mid-path command for the CFA. */
1682 * This is read command. From 32 to 128B can be read from a table
1683 * using this command.
1685 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1686 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1687 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1688 /* This value selects the table type to be acted upon. */
1690 /* This value selects the table type to be acted upon. */
1691 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1692 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1693 /* This command acts on the action table of the specified scope. */
1694 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1695 /* This command acts on the exact match table of the specified scope. */
1696 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1697 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1698 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1699 /* This value selects which table scope will be accessed. */
1700 uint8_t table_scope;
1701 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1702 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1704 * This value identifies the number of 32B units will be accessed. A
1705 * value of zero is invalid. Maximum value is 4.
1708 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1709 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1710 /* This is the 32B index into the selected table to access. */
1711 uint32_t table_index;
1712 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1713 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1715 * This is the 64b host address where you want the data returned to. The
1716 * data will be written to the same function as the one that owns the SQ
1717 * this command is read from. The bottom two bits of this value must be
1718 * zero. The size of the write is controlled by the data_size field.
1720 uint64_t host_address;
1723 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1724 struct cfa_bds_write_cmd_data_msg {
1725 /* This value selects the format for the mid-path command for the CFA. */
1728 * This is write command. From 32 to 128B can be written to a table
1729 * using this command.
1731 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1732 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1733 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1734 /* This value selects the table type to be acted upon. */
1735 uint8_t write_thru_table_type;
1736 /* This value selects the table type to be acted upon. */
1737 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1738 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1739 /* This command acts on the action table of the specified scope. */
1740 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1741 /* This command acts on the exact match table of the specified scope. */
1742 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1743 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1744 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1746 * Indicates write-through control. Indicates write-through when set,
1747 * or write back when cleared.
1749 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1750 /* This value selects which table scope will be accessed. */
1751 uint8_t table_scope;
1752 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1753 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1755 * This value identifies the number of 32B units will be accessed. A
1756 * value of zero is invalid. Maximum value is 4.
1759 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1760 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1761 /* This is the 32B index into the selected table to access. */
1762 uint32_t table_index;
1763 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1764 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1768 * This is the data to be written. Data length is determined by the
1769 * data_size field. The bd_cnt in the encapsulating BD must also be set
1770 * correctly to ensure that the BD is processed correctly and the full
1771 * WRITE_CMD message is extracted from the BD.
1776 /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
1777 struct cfa_bds_read_clr_cmd_data_msg {
1778 /* This value selects the format for the mid-path command for the CFA. */
1781 * This is read-clear command. 32B can be read from a table and
1782 * a 16b mask can be used to clear specific 16b units after the
1783 * read as an atomic operation.
1785 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1786 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1787 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1788 /* This value selects the table type to be acted upon. */
1790 /* This value selects the table type to be acted upon. */
1791 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1792 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1793 /* This command acts on the action table of the specified scope. */
1794 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1795 /* This command acts on the exact match table of the specified scope. */
1796 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1797 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1798 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1799 /* This value selects which table scope will be accessed. */
1800 uint8_t table_scope;
1801 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1802 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1804 * This value identifies the number of 32B units will be accessed.
1805 * Always set the value to 1.
1808 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1809 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
1810 /* This is the 32B index into the selected table to access. */
1811 uint32_t table_index;
1812 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1814 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1816 * This is the 64b host address where you want the data returned to. The
1817 * data will be written to the same function as the one that owns the SQ
1818 * this command is read from. The bottom two bits of this value must be
1819 * zero. The size of the write is controlled by the data_size field.
1821 uint64_t host_address;
1823 * This is active high clear mask for the 32B of data that this command
1824 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1825 * of data read when set to '1'.
1827 uint16_t clear_mask;
1828 uint16_t unused0[3];
1829 uint16_t unused1[4];
1832 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1833 struct cfa_bds_em_insert_cmd_data_msg {
1834 /* This value selects the format for the mid-path command for the CFA. */
1837 * An exact match table insert will be attempted into the table.
1838 * If there is a free location in the bucket, the payload will
1839 * be written to the bucket.
1841 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1842 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1843 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1845 * Indicates write-through control. Indicates write-through when set,
1846 * or write back when cleared.
1849 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1850 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1852 * Indicates write-through control. Indicates write-through when set,
1853 * or write back when cleared.
1855 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1856 /* This value selects which table scope will be accessed. */
1857 uint8_t table_scope;
1858 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1859 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1861 * This value identifies the number of 32B units will be accessed. A
1862 * value of zero is invalid. Maximum value is 4.
1865 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1866 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1867 /* This is the 32B index into the selected table to access. */
1868 uint32_t table_index;
1869 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1871 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1873 * This is the 64b host address where you want the data returned to. The
1874 * data will be written to the same function as the one that owns the SQ
1876 uint64_t host_address;
1878 * This is the Exact Match Lookup Record. Data length is determined by
1879 * the data_size field. The bd_cnt in the encapsulating BD must also be
1884 /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
1885 struct cfa_bds_em_delete_cmd_data_msg {
1886 /* This value selects the format for the mid-path command for the CFA. */
1888 /* An exact match table delete will be attempted. */
1889 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1890 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1891 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1893 * Indicates write-through control. Indicates write-through when set,
1894 * or write back when cleared.
1897 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1898 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1900 * Indicates write-through control. Indicates write-through when set,
1901 * or write back when cleared.
1903 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1904 /* This value selects which table scope will be accessed. */
1905 uint8_t table_scope;
1906 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1907 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1909 * This value identifies the number of 32B units will be accessed. A
1910 * value of zero is invalid. Maximum value is 4.
1913 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1914 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1917 * This is the 64b host address where you want the data returned to. The
1918 * data will be written to the same function as the one that owns the SQ
1920 uint64_t host_address;
1922 * This is the Exact Match Lookup Record. Data length is determined by
1923 * the data_size field. The bd_cnt in the encapsulating BD must also be
1926 uint32_t unused1[2];
1929 /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
1930 struct cfa_bds_invalidate_cmd_data_msg {
1931 /* This value selects the format for the mid-path command for the CFA. */
1934 * The specified table area will be invalidated. If it is needed.
1935 * again, it will be read from the backing store.
1937 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1938 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1939 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1940 /* This value selects the table type to be acted upon. */
1942 /* This value selects the table type to be acted upon. */
1943 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1944 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1945 /* This command acts on the action table of the specified scope. */
1946 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1948 /* This command acts on the exact match table of the specified scope. */
1949 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1951 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1952 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1953 /* This value selects which table scope will be accessed. */
1954 uint8_t table_scope;
1955 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1956 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1957 /* This value specifies the number of cache lines to invalidate. */
1959 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1960 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1961 /* This is the 32B index into the selected table to access. */
1962 uint32_t table_index;
1963 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1965 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1969 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1970 struct cfa_bds_event_collect_cmd_data_msg {
1971 /* This value selects the format for the mid-path command for the CFA. */
1973 /* Reads notification messages from the Host Notification Queue. */
1974 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1976 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1977 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1979 /* This value selects which table scope will be accessed. */
1980 uint8_t table_scope;
1981 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1983 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1985 * This value identifies the number of 32B units will be accessed. A
1986 * value of zero is invalid. Maximum value is 4.
1989 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1990 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1993 * This is the 64b host address where you want the data returned to. The
1994 * data will be written to the same function as the one that owns the SQ
1996 uint64_t host_address;
1999 /* ce_bds_add_data_msg (size:512b/64B) */
2000 struct ce_bds_add_data_msg {
2001 uint32_t version_algorithm_kid_opcode;
2003 * This value selects the operation for the mid-path command for the
2006 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2007 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
2009 * This is the add command. Using this opcode, Host Driver can add
2010 * information required for kTLS processing. The information is
2011 * updated in the CFCK context.
2013 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
2014 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
2015 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
2017 * This field is the Crypto Context ID. The KID is used to store
2018 * information used by the associated kTLS offloaded connection.
2020 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
2022 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
2024 * Currently only two algorithms are supported, AES_GCM_128 and
2025 * AES_GCM_256. Additional bits for future growth.
2027 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
2029 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
2030 /* AES_GCM_128 Algorithm */
2031 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
2033 /* AES_GCM_256 Algorithm */
2034 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
2037 * Version number of TLS connection. HW will provide registers that
2038 * converts the 4b encoded version number to 16b of actual version
2039 * number in the TLS Header. This field is initialized/updated by
2040 * this "KTLS crypto add" mid-path command.
2042 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
2043 UINT32_C(0xf0000000)
2044 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
2045 /* TLS1.2 Version */
2046 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
2047 (UINT32_C(0x0) << 28)
2048 /* TLS1.3 Version */
2049 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
2050 (UINT32_C(0x1) << 28)
2051 #define CE_BDS_ADD_DATA_MSG__LAST \
2052 CE_BDS_ADD_DATA_MSG__TLS1_3
2053 uint8_t cmd_type_ctx_kind;
2055 * Command Type in the TLS header. HW will provide registers that
2056 * converts the 3b encoded command type to 8b of actual command
2057 * type in the TLS Header. This field is initialized/updated by
2058 * this "KTLS crypto add" mid-path command.
2060 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
2061 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
2063 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
2064 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
2065 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
2066 /* This field selects the context kind for the request. */
2067 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8)
2068 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3
2069 /* Crypto key transmit context */
2070 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3)
2071 /* Crypto key receive context */
2072 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3)
2073 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \
2074 CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX
2077 * Salt is part of the nonce that is used as the Initial Vector (IV) in
2078 * AES-GCM cipher suites. These are exchanged as part of the handshake
2079 * process and is either the client_write_iv (when the client is
2080 * sending) or server_write_iv (when the server is sending). In
2081 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
2082 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
2083 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
2084 * the 12B of IV. This value is initialized by this mid-path command.
2089 * This field keeps track of the TCP sequence number that is expected as
2090 * the first byte in the next TCP packet. This field is calculated by HW
2091 * using the output of the parser. The field is initialized as part of
2092 * the Mid-path BD download/update of a kTLS connection. For every TCP
2093 * packet processed, TCE HW will update the value to Current packet TCP
2094 * sequence number + Current packet TCP Payload Length.
2096 uint32_t pkt_tcp_seq_num;
2098 * This field maintains the TCP sequence number of the first byte in the
2099 * header of the active TLS record. This field is initialized as part of
2100 * the Mid-path BD download/update of a kTLS connection. For every
2101 * record that is processed, TCE HW copies the value from the
2102 * next_tls_header_tcp_seq_num field.
2104 uint32_t tls_header_tcp_seq_num;
2106 * This is sequence number for the TLS record in a particular session.
2107 * In TLS1.2, record sequence number is part of the Associated Data (AD)
2108 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
2109 * the Initial Vector (IV). The field is initialized as part of the
2110 * mid-path BD download/update of a kTLS connection. TCE HW increments
2111 * the field after that for every record processed as it parses the TCP
2114 uint32_t record_seq_num[2];
2116 * Key used for encrypting or decrypting TLS records. The Key is
2117 * exchanged during the hand-shake protocol by the client-server and
2118 * provided to HW through this mid-path BD.
2120 uint32_t session_key[8];
2123 /* ce_bds_delete_data_msg (size:64b/8B) */
2124 struct ce_bds_delete_data_msg {
2125 uint32_t kid_opcode_ctx_kind;
2127 * This value selects the operation for the mid-path command for the
2130 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2131 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2133 * This is the delete command. Using this opcode, the host Driver
2134 * can remove a key context from the CFCK. If context is deleted
2135 * and packets with the same KID come through the pipeline, the
2136 * following actions are taken. For transmit packets, no crypto
2137 * operation will be performed, payload will be zero'ed out. For
2138 * receive packets, no crypto operation will be performed,
2139 * payload will be unmodified.
2141 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2142 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
2143 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
2145 * This field is the Crypto Context ID. The KID is used to store
2146 * information used by the associated kTLS offloaded connection.
2148 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2149 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
2150 /* This field selects the context kind for the request. */
2151 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000)
2152 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_SFT 24
2153 /* Crypto Key Transmit Context. */
2154 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24)
2155 /* Crypto Key Receive Context. */
2156 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24)
2157 /* QUIC Key Transmit Context. */
2158 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24)
2159 /* QUIC Key Receive Context. */
2160 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
2161 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \
2162 CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX
2166 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
2167 struct ce_bds_resync_resp_ack_msg {
2168 uint32_t resync_status_kid_opcode;
2170 * This value selects the operation for the mid-path command for the
2173 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2174 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2176 * This command is used by the driver as a response to the resync
2177 * request sent by the crypto engine.
2179 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2180 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
2181 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
2183 * This field is the Crypto Context ID. The KID is used to store
2184 * information used by the associated kTLS offloaded connection.
2186 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2187 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
2189 * This field indicates if the resync request resulted in a success or
2192 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2195 * An ACK indicates that the driver was able to find the TLS record
2196 * associated with TCP sequence number provided by the HW
2198 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2199 (UINT32_C(0x0) << 24)
2200 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2201 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2203 * This field is the echo of the TCP sequence number provided in the
2204 * resync request by the HW. If HW sent multiple resync requests, it
2205 * only tracks the latest TCP sequence number. When the response from
2206 * the Driver doesn't match the latest request, HW will drop the resync
2209 uint32_t resync_record_tcp_seq_num;
2211 * This field indicates the TLS record sequence number associated with
2212 * the resync request. HW will take this number and add the delta records
2213 * it has found since sending the resync request, update the context and
2214 * resume decrypting records.
2216 uint32_t resync_record_seq_num[2];
2219 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2220 struct ce_bds_resync_resp_nack_msg {
2221 uint32_t resync_status_kid_opcode;
2223 * This value selects the operation for the mid-path command for the
2226 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2227 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2229 * This command is used by the driver as a response to the resync
2230 * request sent by the crypto engine.
2232 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2233 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2234 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2236 * This field is the Crypto Context ID. The KID is used to store
2237 * information used by the associated kTLS offloaded connection.
2239 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2241 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2243 * This field indicates if the resync request resulted in a success or
2246 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2249 * An NAK indicates that the driver wasn't able to find the TLS
2250 * record associated with TCP sequence number provided by the HW
2252 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2253 (UINT32_C(0x1) << 24)
2254 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2255 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2257 * This field is the echo of the TCP sequence number provided in the
2258 * resync request by the HW. If HW sent multiple resync requests, it
2259 * only tracks the latest TCP sequence number. When the response from
2260 * the Driver doesn't match the latest request, HW will drop the resync
2263 uint32_t resync_record_tcp_seq_num;
2266 /* crypto_presync_bd_cmd (size:256b/32B) */
2267 struct crypto_presync_bd_cmd {
2270 * Typically, presync BDs are used for packet retransmissions. Source
2271 * port sends all the packets in order over the network to destination
2272 * port and packets get dropped in the network. The destination port
2273 * will request retranmission of dropped packets and source port driver
2274 * will send presync BD to setup the transmitter appropriately. It will
2275 * provide the start and end TCP sequence number of the data to be
2276 * transmitted. HW keeps two sets of context variable, one for in order
2277 * traffic and one for retransmission traffic. HW is designed to
2278 * transmit everything posted in the presync BD and return to in order
2279 * mode after that. No inorder context variables are updated in the
2280 * process. There is a special case where packets can be dropped
2281 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2282 * ex) and HW still needs to transmit rest of the traffic. In this
2283 * mode, driver will send a presync BD as if it is a retransmission but
2284 * at the end of the transmission, the in order variables need to be
2285 * updated. This flag is used by driver to indicate that in order
2286 * variables needs to be updated at the end of completing the task
2287 * associated with the presync BD.
2289 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2294 * This field maintains the TCP sequence number of the first byte in the
2295 * Header of the active TLS record. This field is set to 0 during
2296 * mid-path BD updates, but is set to correct value when a presync BD is
2297 * detected. For every record that is processed, the value from the
2298 * next_tls_header_tcp_seq_num field is copied.
2300 uint32_t header_tcp_seq_num;
2302 * When a retransmitted packet has a TLS authentication TAG present and
2303 * the data spans multiple TCP Packets, HW is required to read the entire
2304 * record to recalculate the TAG but only transmit what is required. This
2305 * field is the start TCP sequence number of the packet(s) that need to
2306 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2307 * add command and initialized to value provided by the driver when
2308 * Pre-sync BD is detected. This field is never updated unless another
2309 * Pre-sync BD signaling a new retransmission is scheduled.
2311 uint32_t start_tcp_seq_num;
2313 * When a retransmitted packet has a TLS authentication TAG present and
2314 * the data spans multiple TCP Packets, HW is required to read the
2315 * entire record to recalculate the TAG but only transmit what is
2316 * required. This field is the end TCP sequence number of the packet(s)
2317 * that need to be re-transmitted. This field is initialized to 0 during
2318 * Mid-path BD add command and initialized to value provided by the
2319 * driver when Pre-sync BD is detected. This field is never updated
2320 * unless another Pre-sync BD signaling a new retransmission is
2323 uint32_t end_tcp_seq_num;
2325 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2326 * with the SALT). For retrans packets, this field is extracted from the
2327 * TLS record, field right after the TLS Header and stored in the
2328 * context. This field needs to be stored in context as TCP segmentation
2329 * could have split the field into multiple TCP packets. This value is
2330 * initialized to 0 when presync BD is detected by taking the value from
2331 * the first TLS header. When subsequent TLS Headers are detected, the
2332 * value is extracted from packet.
2334 uint32_t explicit_nonce[2];
2336 * This is sequence number for the TLS record in a particular session. In
2337 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2338 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2339 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2340 * download. Is initialized to correct value when a pre-sync BD is
2341 * detected. TCE HW increments the field after that for every record
2342 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2343 * delivering more retransmission instruction will also update this
2346 uint32_t record_seq_num[2];
2349 /* bd_base (size:64b/8B) */
2352 /* This value identifies the type of buffer descriptor. */
2353 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2354 #define BD_BASE_TYPE_SFT 0
2356 * Indicates that this BD is 16B long and is used for
2357 * normal L2 packet transmission.
2359 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2361 * Indicates that this BD is 1BB long and is an empty
2362 * TX BD. Not valid for use by the driver.
2364 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2366 * Indicates that this BD is 16B long and is an RX Producer
2367 * (i.e. empty) buffer descriptor.
2369 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2371 * Indicates that this BD is 16B long and is an RX
2372 * Producer Buffer BD.
2374 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2376 * Indicates that this BD is 16B long and is an
2377 * RX Producer Assembly Buffer Descriptor.
2379 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2381 * Indicates that this BD is used to issue a command to one of
2382 * the mid-path destinations.
2384 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2386 * Indicates that this BD is used to issue a cryptographic pre-
2387 * sync command through the fast path and destined for TCE.
2389 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2391 * Indicates a timed transmit BD. This is a 16b BD that is inserted
2392 * into a packet BD chain immediately after the first BD. It is used
2393 * to control the flow in a timed transmit operation.
2395 #define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
2397 * Indicates that this BD is 32B long and is used for
2398 * normal L2 packet transmission.
2400 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2402 * Indicates that this BD is 32B long and is used for
2403 * L2 packet transmission for small packets that require
2406 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2407 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2408 uint8_t unused_1[7];
2411 /* tx_bd_short (size:128b/16B) */
2412 struct tx_bd_short {
2414 * All bits in this field must be valid on the first BD of a packet.
2415 * Only the packet_end bit must be valid for the remaining BDs
2418 uint16_t flags_type;
2419 /* This value identifies the type of buffer descriptor. */
2420 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2421 #define TX_BD_SHORT_TYPE_SFT 0
2423 * Indicates that this BD is 16B long and is used for
2424 * normal L2 packet transmission.
2426 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2427 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2429 * All bits in this field must be valid on the first BD of a packet.
2430 * Only the packet_end bit must be valid for the remaining BDs
2433 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2434 #define TX_BD_SHORT_FLAGS_SFT 6
2436 * If set to 1, the packet ends with the data in the buffer
2437 * pointed to by this descriptor. This flag must be
2438 * valid on every BD.
2440 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2442 * If set to 1, the device will not generate a completion for
2443 * this transmit packet unless there is an error in it's
2446 * is set to 0, then the packet will be completed normally.
2448 * This bit must be valid only on the first BD of a packet.
2450 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2452 * This value indicates how many 16B BD locations are consumed
2453 * in the ring by this packet.
2454 * A value of 1 indicates that this BD is the only BD (and that
2455 * it is a short BD). A value
2456 * of 3 indicates either 3 short BDs or 1 long BD and one short
2457 * BD in the packet. A value of 0 indicates
2458 * that there are 32 BD locations in the packet (the maximum).
2460 * This field is valid only on the first BD of a packet.
2462 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2463 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2465 * This value is a hint for the length of the entire packet.
2466 * It is used by the chip to optimize internal processing.
2468 * The packet will be dropped if the hint is too short.
2470 * This field is valid only on the first BD of a packet.
2472 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2473 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2474 /* indicates packet length < 512B */
2475 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2476 /* indicates 512 <= packet length < 1KB */
2477 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2478 /* indicates 1KB <= packet length < 2KB */
2479 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2480 /* indicates packet length >= 2KB */
2481 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2482 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2483 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2485 * If set to 1, the device immediately updates the Send Consumer
2486 * Index after the buffer associated with this descriptor has
2487 * been transferred via DMA to NIC memory from host memory. An
2488 * interrupt may or may not be generated according to the state
2489 * of the interrupt avoidance mechanisms. If this bit
2490 * is set to 0, then the Consumer Index is only updated as soon
2491 * as one of the host interrupt coalescing conditions has been met.
2493 * This bit must be valid on the first BD of a packet.
2495 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2497 * This is the length of the host physical buffer this BD describes
2500 * This field must be valid on all BDs of a packet.
2504 * The opaque data field is pass through to the completion and can be
2505 * used for any data that the driver wants to associate with the
2508 * This field must be valid on the first BD of a packet. If completion
2509 * coalescing is enabled on the TX ring, it is suggested that the driver
2510 * populate the opaque field to indicate the specific TX ring with which
2511 * the completion is associated, then utilize the opaque and sq_cons_idx
2512 * fields in the coalesced completion record to determine the specific
2513 * packets that are to be completed on that ring.
2517 * This is the host physical address for the portion of the packet
2518 * described by this TX BD.
2520 * This value must be valid on all BDs of a packet.
2525 /* tx_bd_long (size:128b/16B) */
2527 /* This value identifies the type of buffer descriptor. */
2528 uint16_t flags_type;
2530 * This value indicates the type of buffer descriptor.
2533 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2534 #define TX_BD_LONG_TYPE_SFT 0
2536 * Indicates that this BD is 32B long and is used for
2537 * normal L2 packet transmission.
2539 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2540 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2542 * All bits in this field must be valid on the first BD of a packet.
2543 * Only the packet_end bit must be valid for the remaining BDs
2546 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2547 #define TX_BD_LONG_FLAGS_SFT 6
2549 * If set to 1, the packet ends with the data in the buffer
2550 * pointed to by this descriptor. This flag must be
2551 * valid on every BD.
2553 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2555 * If set to 1, the device will not generate a completion for
2556 * this transmit packet unless there is an error in it's
2559 * is set to 0, then the packet will be completed normally.
2561 * This bit must be valid only on the first BD of a packet.
2563 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2565 * This value indicates how many 16B BD locations are consumed
2566 * in the ring by this packet.
2567 * A value of 1 indicates that this BD is the only BD (and that
2568 * it is a short BD). A value
2569 * of 3 indicates either 3 short BDs or 1 long BD and one short
2570 * BD in the packet. A value of 0 indicates
2571 * that there are 32 BD locations in the packet (the maximum).
2573 * This field is valid only on the first BD of a packet.
2575 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2576 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2578 * This value is a hint for the length of the entire packet.
2579 * It is used by the chip to optimize internal processing.
2581 * The packet will be dropped if the hint is too short.
2583 * This field is valid only on the first BD of a packet.
2585 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2586 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2587 /* indicates packet length < 512B */
2588 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2589 /* indicates 512 <= packet length < 1KB */
2590 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2591 /* indicates 1KB <= packet length < 2KB */
2592 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2593 /* indicates packet length >= 2KB */
2594 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2595 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2597 * If set to 1, the device immediately updates the Send Consumer
2598 * Index after the buffer associated with this descriptor has
2599 * been transferred via DMA to NIC memory from host memory. An
2600 * interrupt may or may not be generated according to the state
2601 * of the interrupt avoidance mechanisms. If this bit
2602 * is set to 0, then the Consumer Index is only updated as soon
2603 * as one of the host interrupt coalescing conditions has been met.
2605 * This bit must be valid on the first BD of a packet.
2607 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2609 * This is the length of the host physical buffer this BD describes
2612 * This field must be valid on all BDs of a packet.
2616 * The opaque data field is passed through to the completion and can be
2617 * used for any data that the driver wants to associate with the
2620 * This field must be valid on the first BD of a packet. If completion
2621 * coalescing is enabled on the TX ring, it is suggested that the driver
2622 * populate the opaque field to indicate the specific TX ring with which
2623 * the completion is associated, then utilize the opaque and sq_cons_idx
2624 * fields in the coalesced completion record to determine the specific
2625 * packets that are to be completed on that ring.
2629 * This is the host physical address for the portion of the packet
2630 * described by this TX BD.
2632 * This value must be valid on all BDs of a packet.
2637 /* Last 16 bytes of tx_bd_long. */
2638 /* tx_bd_long_hi (size:128b/16B) */
2639 struct tx_bd_long_hi {
2641 * All bits in this field must be valid on the first BD of a packet.
2642 * Their value on other BDs of the packet will be ignored.
2646 * If set to 1, the controller replaces the TCP/UPD checksum
2647 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2648 * checksum field of the encapsulated TCP/UDP packets with the
2649 * hardware calculated TCP/UDP checksum for the packet associated
2650 * with this descriptor. The flag is ignored if the LSO flag is set.
2652 * This bit must be valid on the first BD of a packet.
2654 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2656 * If set to 1, the controller replaces the IP checksum of the
2657 * normal packets, or the inner IP checksum of the encapsulated
2658 * packets with the hardware calculated IP checksum for the
2659 * packet associated with this descriptor.
2661 * This bit must be valid on the first BD of a packet.
2663 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2665 * If set to 1, the controller will not append an Ethernet CRC
2666 * to the end of the frame.
2668 * This bit must be valid on the first BD of a packet.
2670 * Packet must be 64B or longer when this flag is set. It is not
2671 * useful to use this bit with any form of TX offload such as
2672 * CSO or LSO. The intent is that the packet from the host already
2673 * has a valid Ethernet CRC on the packet.
2675 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2677 * This bit, in conjunction with the stamp_1step bit, controls whether
2678 * a TX packet timestamp is collected and the type of timestamp that
2681 * This bit must be valid on the first BD of a packet.
2683 * Enumerations of the concatenation { stamp, stamp_1step } are
2686 * - 2'b00: ts_none - no timestamp
2687 * - 2'b01: ts_ptp_1step - 1-step PTP
2688 * - 2'b10: ts_2cmpl - 2-step PTP timestamp or PA timestamp
2689 * - 2'b11: ts_rsvd - reserved, same behavior as ts_none
2690 * For the ts_2cmpl enumeration, an additional completion is returned.
2691 * This additional completion may carry a 2-step PTP timestamp or a PA
2692 * timestamp, depending on parsing of the transmitted packet.
2694 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2696 * If set to 1, The controller replaces the tunnel IP checksum
2697 * field with hardware calculated IP checksum for the IP header
2698 * of the packet associated with this descriptor.
2700 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2701 * needs to be enabled. If the global outer UDP checksum TE_NIC
2702 * register bit is set, outer UDP checksum will be calculated for
2703 * the following cases:
2704 * 1. Packets with tcp_udp_chksum flag set to offload checksum for
2705 * inner packet AND the inner packet is TCP/UDP. If the inner packet
2706 * is ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is
2707 * set, the outer UDP checksum will not be calculated.
2708 * 2. Packets with lso flag set which implies inner TCP checksum
2709 * calculation as part of LSO operation.
2711 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2713 * If set to 1, the device will treat this packet with LSO(Large
2714 * Send Offload) processing for both normal or encapsulated
2715 * packets, which is a form of TCP segmentation. When this bit
2716 * is 1, the hdr_size and mss fields must be valid. The driver
2717 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2718 * tcp_udp_chksum flags since the controller will replace the
2719 * appropriate checksum fields for segmented packets.
2721 * When this bit is 1, the hdr_size and mss fields must be valid.
2723 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2725 * If set to zero when LSO is '1', then the IPID will be treated
2726 * as a 16b number and will be wrapped if it exceeds a value of
2729 * If set to one when LSO is '1', then the IPID will be treated
2730 * as a 15b number and will be wrapped if it exceeds a value 0f
2733 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2735 * If set to zero when LSO is '1', then the IPID of the tunnel
2736 * IP header will not be modified during LSO operations.
2738 * If set to one when LSO is '1', then the IPID of the tunnel
2739 * IP header will be incremented for each subsequent segment of an
2742 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2745 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2747 * If set to '1', then the RoCE ICRC will be appended to the
2748 * packet. Packet must be a valid RoCE format packet.
2750 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2752 * If set to '1', then the FCoE CRC will be appended to the
2753 * packet. Packet must be a valid FCoE format packet.
2755 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2757 * If set to '1', then the timestamp from the BD is used. If cleared
2758 * to 0, then TWE provides the timestamp.
2760 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2762 * If set to '1', this operation will cause a trace capture in each
2763 * block it passes through.
2765 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2767 * This bit, in conjunction with the stamp bit, controls whether a
2768 * TX packet timestamp is collected and the type of timestamp that
2771 * See the stamp field for a description of the valid combinations of
2772 * stamp and stamp_1step.
2774 * This bit must be valid on the first BD of a packet.
2776 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2778 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2779 * field with hardware calculated IP checksum for the IP header of the
2780 * packet associated with this descriptor. For outer UDP checksum, it
2781 * will be the following behavior for all cases independent of
2782 * settings of inner LSO and checksum offload BD flags.
2783 * If outer UDP checksum is 0, then do not update it.
2784 * If outer UDP checksum is non zero, then the hardware should
2785 * compute and update it.
2787 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2789 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel
2790 * IP header will not be modified during LSO operations. If set to one
2791 * when LSO is '1', then the IPID of the Outer-tunnel IP header will
2792 * be incremented for each subsequent segment of an LSO operation. The
2793 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2796 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2798 * If set to '1', When set to 1, KTLS encryption will be enabled for
2801 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2802 uint16_t kid_or_ts_low_hdr_size;
2804 * When LSO is '1', this field must contain the offset of the
2805 * TCP payload from the beginning of the packet in as
2806 * 16b words. In case of encapsulated/tunneling packet, this field
2807 * contains the offset of the inner TCP payload from beginning of the
2808 * packet as 16-bit words.
2810 * This value must be valid on the first BD of a packet.
2812 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2813 #define TX_BD_LONG_HDR_SIZE_SFT 0
2815 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2816 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
2819 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2820 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2821 uint32_t kid_or_ts_high_mss;
2823 * This is the MSS value that will be used to do the LSO processing.
2824 * The value is the length in bytes of the TCP payload for each
2825 * segment generated by the LSO operation.
2827 * This value must be valid on the first BD of a packet.
2829 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2830 #define TX_BD_LONG_MSS_SFT 0
2832 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2833 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2834 * of this field contain the upper 13 bits of the 20-bit KID.
2836 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2837 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2839 * This value selects bits 25:16 of the CFA action to perform on the
2840 * packet. See the cfa_action field for more information.
2842 uint16_t cfa_action_high;
2843 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2844 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2846 * This value selects a CFA action to perform on the packet.
2847 * Set this value to zero if no CFA action is desired.
2849 * This value must be valid on the first BD of a packet.
2851 uint16_t cfa_action;
2853 * This value is action meta-data that defines CFA edit operations
2854 * that are done in addition to any action editing.
2857 /* When key=1, This is the VLAN tag VID value. */
2858 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2859 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2860 /* When key=1, This is the VLAN tag DE value. */
2861 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2862 /* When key=1, This is the VLAN tag PRI value. */
2863 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2864 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2865 /* When key=1, This is the VLAN tag TPID select value. */
2866 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2867 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2869 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
2870 (UINT32_C(0x0) << 16)
2872 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
2873 (UINT32_C(0x1) << 16)
2875 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
2876 (UINT32_C(0x2) << 16)
2878 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
2879 (UINT32_C(0x3) << 16)
2881 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
2882 (UINT32_C(0x4) << 16)
2883 /* Value programmed in CFA VLANTPID register. */
2884 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
2885 (UINT32_C(0x5) << 16)
2886 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2887 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2888 /* When key=1, This is the VLAN tag TPID select value. */
2889 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2890 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2892 * This field identifies the type of edit to be performed
2895 * This value must be valid on the first BD of a packet.
2897 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2898 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2900 #define TX_BD_LONG_CFA_META_KEY_NONE \
2901 (UINT32_C(0x0) << 28)
2903 * - meta[17:16] - TPID select value (0 = 0x8100).
2904 * - meta[15:12] - PRI/DE value.
2905 * - meta[11:0] - VID value.
2907 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
2908 (UINT32_C(0x1) << 28)
2911 * - Wh+/SR - this option is not supported.
2912 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
2913 * is set in the Lookup Table.
2914 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
2915 * en_bd_meta is set in the Lookup Table.
2917 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
2918 (UINT32_C(0x2) << 28)
2919 #define TX_BD_LONG_CFA_META_KEY_LAST \
2920 TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
2924 * This structure is used to inform the NIC of packet data that needs to
2925 * be transmitted with additional processing that requires extra data
2926 * such as VLAN insertion plus attached inline data.
2927 * This BD type may be used to improve latency for small packets needing
2928 * the additional extended features supported by long BDs.
2930 /* tx_bd_long_inline (size:256b/32B) */
2931 struct tx_bd_long_inline {
2932 uint16_t flags_type;
2933 /* This value identifies the type of buffer descriptor. */
2934 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2935 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2937 * This type of BD is 32B long and is used for inline L2 packet
2940 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2941 #define TX_BD_LONG_INLINE_TYPE_LAST \
2942 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2944 * All bits in this field may be set on the first BD of a packet.
2945 * Only the packet_end bit may be set in non-first BDs.
2947 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2948 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2950 * If set to 1, the packet ends with the data in the buffer
2951 * pointed to by this descriptor. This flag must be
2952 * valid on every BD.
2954 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2956 * If set to 1, the device will not generate a completion for
2957 * this transmit packet unless there is an error in its processing.
2958 * If this bit is set to 0, then the packet will be completed
2961 * This bit may be set only on the first BD of a packet.
2963 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2965 * This value indicates how many 16B BD locations are consumed
2966 * in the ring by this packet, including the BD and inline
2969 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2970 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2971 /* This field is deprecated. */
2972 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2973 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2975 * If set to 1, the device immediately updates the Send Consumer
2976 * Index after the buffer associated with this descriptor has
2977 * been transferred via DMA to NIC memory from host memory. An
2978 * interrupt may or may not be generated according to the state
2979 * of the interrupt avoidance mechanisms. If this bit
2980 * is set to 0, then the Consumer Index is only updated as soon
2981 * as one of the host interrupt coalescing conditions has been met.
2983 * This bit must be valid on the first BD of a packet.
2985 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2987 * This is the length of the inline data, not including BD length, in
2989 * The maximum value is 480.
2991 * This field must be valid on all BDs of a packet.
2995 * The opaque data field is passed through to the completion and can be
2996 * used for any data that the driver wants to associate with the
2997 * transmit BD. This field must be valid on the first BD of a packet.
2998 * If completion coalescing is enabled on the TX ring, it is suggested
2999 * that the driver populate the opaque field to indicate the specific
3000 * TX ring with which the completion is associated, then utilize the
3001 * opaque and sq_cons_idx fields in the coalesced completion record to
3002 * determine the specific packets that are to be completed on that ring.
3004 * This field must be valid on the first BD of a packet.
3009 * All bits in this field must be valid on the first BD of a packet.
3010 * Their value on other BDs of the packet is ignored.
3014 * If set to 1, the controller replaces the TCP/UPD checksum
3015 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
3016 * checksum field of the encapsulated TCP/UDP packets with the
3017 * hardware calculated TCP/UDP checksum for the packet associated
3018 * with this descriptor. The flag is ignored if the LSO flag is set.
3020 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
3022 * If set to 1, the controller replaces the IP checksum of the
3023 * normal packets, or the inner IP checksum of the encapsulated
3024 * packets with the hardware calculated IP checksum for the
3025 * packet associated with this descriptor.
3027 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
3029 * If set to 1, the controller will not append an Ethernet CRC
3030 * to the end of the frame.
3032 * Packet must be 64B or longer when this flag is set. It is not
3033 * useful to use this bit with any form of TX offload such as
3034 * CSO or LSO. The intent is that the packet from the host already
3035 * has a valid Ethernet CRC on the packet.
3037 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
3039 * If set to 1, the device will record the time at which the packet
3040 * was actually transmitted at the TX MAC for 2-step time sync. This
3041 * bit must be valid on the first BD of a packet.
3043 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
3045 * If set to 1, the controller replaces the tunnel IP checksum
3046 * field with hardware calculated IP checksum for the IP header
3047 * of the packet associated with this descriptor. The hardware
3048 * updates an outer UDP checksum if it is non-zero.
3050 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
3052 * This bit must be 0 for BDs of this type. LSO is not supported with
3055 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
3056 /* Since LSO is not supported with inline BDs, this bit is not used. */
3057 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
3058 /* Since LSO is not supported with inline BDs, this bit is not used. */
3059 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
3061 * If set to '1', then the RoCE ICRC will be appended to the
3062 * packet. Packet must be a valid RoCE format packet.
3064 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
3066 * If set to '1', then the FCoE CRC will be appended to the
3067 * packet. Packet must be a valid FCoE format packet.
3069 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
3071 * If set to '1', then the timestamp from the BD is used. If cleared
3072 * to 0, then TWE provides the timestamp.
3074 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
3076 * If set to '1', this operation will cause a trace capture in each
3077 * block it passes through.
3079 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
3081 * If set to '1', the device will record the time at which the packet
3082 * was actually transmitted at the TX MAC for 1-step time sync. This
3083 * bit must be valid on the first BD of a packet.
3085 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
3087 * If set to '1', the controller replaces the Outer-tunnel IP checksum
3088 * field with hardware calculated IP checksum for the IP header of the
3089 * packet associated with this descriptor. For outer UDP checksum, it
3090 * will be the following behavior for all cases independent of settings
3091 * of inner LSO and checksum offload BD flags. If outer UDP checksum
3092 * is 0, then do not update it. If outer UDP checksum is non zero, then
3093 * the hardware should compute and update it.
3095 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
3097 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
3098 * header will not be modified during LSO operations. If set to one
3099 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
3100 * incremented for each subsequent segment of an LSO operation. The
3101 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
3104 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
3106 * If set to '1', When set to 1, KTLS encryption will be enabled for
3109 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
3111 uint8_t kid_or_ts_low;
3112 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
3114 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
3115 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
3118 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
3119 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
3120 uint32_t kid_or_ts_high;
3121 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
3122 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
3124 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
3125 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
3126 * of this field contain the upper 13 bits of the 20-bit KID.
3128 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3129 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
3131 * This value selects bits 25:16 of the CFA action to perform on the
3132 * packet. See the cfa_action field for more information.
3134 uint16_t cfa_action_high;
3135 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3136 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
3138 * This value selects a CFA action to perform on the packet.
3139 * Set this value to zero if no CFA action is desired.
3141 * This value must be valid on the first BD of a packet.
3143 uint16_t cfa_action;
3145 * This value is action meta-data that defines CFA edit operations
3146 * that are done in addition to any action editing.
3149 /* When key = 1, this is the VLAN tag VID value. */
3150 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3151 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
3152 /* When key = 1, this is the VLAN tag DE value. */
3153 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
3155 /* When key = 1, this is the VLAN tag PRI value. */
3156 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
3158 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
3159 /* When key = 1, this is the VLAN tag TPID select value. */
3160 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
3162 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
3164 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
3165 (UINT32_C(0x0) << 16)
3167 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
3168 (UINT32_C(0x1) << 16)
3170 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
3171 (UINT32_C(0x2) << 16)
3173 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
3174 (UINT32_C(0x3) << 16)
3176 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
3177 (UINT32_C(0x4) << 16)
3178 /* Value programmed in CFA VLANTPID register. */
3179 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
3180 (UINT32_C(0x5) << 16)
3181 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
3182 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
3183 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
3185 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
3187 * This field identifies the type of edit to be performed
3190 * This value must be valid on the first BD of a packet.
3192 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
3193 UINT32_C(0xf0000000)
3194 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
3196 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
3197 (UINT32_C(0x0) << 28)
3199 * - meta[17:16] - TPID select value (0 = 0x8100).
3200 * - meta[15:12] - PRI/DE value.
3201 * - meta[11:0] - VID value.
3203 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
3204 (UINT32_C(0x1) << 28)
3207 * - Wh+/SR - this option is not supported.
3208 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3209 * is set in the Lookup Table.
3210 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
3211 * en_bd_meta is set in the Lookup Table.
3213 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
3214 (UINT32_C(0x2) << 28)
3215 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
3216 TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
3219 /* tx_bd_empty (size:128b/16B) */
3220 struct tx_bd_empty {
3221 /* This value identifies the type of buffer descriptor. */
3223 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
3224 #define TX_BD_EMPTY_TYPE_SFT 0
3226 * Indicates that this BD is 1BB long and is an empty
3227 * TX BD. Not valid for use by the driver.
3229 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3230 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
3231 uint8_t unused_1[3];
3233 uint8_t unused_3[3];
3234 uint8_t unused_4[8];
3237 /* tx_bd_mp_cmd (size:128b/16B) */
3238 struct tx_bd_mp_cmd {
3239 /* Unless otherwise stated, sub-fields of this field are always valid. */
3240 uint16_t flags_type;
3241 /* This value identifies the type of buffer descriptor. */
3242 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
3243 #define TX_BD_MP_CMD_TYPE_SFT 0
3245 * Indicates that this BD is used to issue a command to one of
3246 * the mid-path destinations.
3248 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3249 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3250 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3251 #define TX_BD_MP_CMD_FLAGS_SFT 6
3253 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3254 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3256 * This value indicates the number of 16B BD locations (slots)
3257 * consumed in the ring by this mid-path command BD, including the
3258 * BD header and the command field.
3260 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3261 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3263 * This value defines the length of command field in bytes. The maximum
3264 * value shall be 496.
3268 * The opaque data field is pass through to the completion and can be
3269 * used for any data that the driver wants to associate with this
3270 * Tx mid-path command.
3276 /* tx_bd_presync_cmd (size:128b/16B) */
3277 struct tx_bd_presync_cmd {
3278 /* Unless otherwise stated, sub-fields of this field are always valid. */
3279 uint16_t flags_type;
3280 /* This value identifies the type of buffer descriptor. */
3281 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3282 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3284 * Indicates that this BD is used to issue a cryptographic pre-
3285 * sync command through the fast path and destined for TCE.
3287 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3288 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3289 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3290 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3291 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3293 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3294 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3296 * This value indicates the number of 16B BD locations (slots)
3297 * consumed in the ring by this pre-sync command BD, including the
3298 * BD header and the command field.
3300 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3301 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3303 * This value defines the length of command field in bytes. The maximum
3304 * value shall be 496.
3308 * The opaque data field is pass through to TCE and can be used for
3313 * This field is the Crypto Context ID to which the retransmit packet is
3314 * applied. The KID references the context fields used by the
3315 * associated kTLS offloaded connection.
3319 * The KID value of all-ones is reserved for non-KTLS packets, which
3320 * only implies that this value must not be used when filling this
3321 * field for crypto packets.
3323 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3324 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3328 /* rx_prod_pkt_bd (size:128b/16B) */
3329 struct rx_prod_pkt_bd {
3330 /* This value identifies the type of buffer descriptor. */
3331 uint16_t flags_type;
3332 /* This value identifies the type of buffer descriptor. */
3333 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3334 #define RX_PROD_PKT_BD_TYPE_SFT 0
3336 * Indicates that this BD is 16B long and is an RX Producer
3337 * (i.e. empty) buffer descriptor.
3339 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3340 #define RX_PROD_PKT_BD_TYPE_LAST \
3341 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3342 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3343 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3345 * If set to 1, the packet will be placed at the address plus
3346 * 2B. The 2 Bytes of padding will be written as zero.
3348 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3350 * If set to 1, the packet write will be padded out to the
3351 * nearest cache-line with zero value padding.
3353 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3355 * This field has been deprecated. There can be no additional
3356 * BDs for this packet from this ring.
3359 * This value is the number of additional buffers in the ring that
3360 * describe the buffer space to be consumed for this packet.
3361 * If the value is zero, then the packet must fit within the
3362 * space described by this BD. If this value is 1 or more, it
3363 * indicates how many additional "buffer" BDs are in the ring
3364 * immediately following this BD to be used for the same
3365 * network packet. Even if the packet to be placed does not need
3366 * all the additional buffers, they will be consumed anyway.
3368 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3369 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3371 * This is the length in Bytes of the host physical buffer where
3372 * data for the packet may be placed in host memory.
3376 * The opaque data field is pass through to the completion and can be
3377 * used for any data that the driver wants to associate with this
3378 * receive buffer set.
3382 * This is the host physical address where data for the packet may
3383 * be placed in host memory.
3388 /* rx_prod_bfr_bd (size:128b/16B) */
3389 struct rx_prod_bfr_bd {
3390 /* This value identifies the type of buffer descriptor. */
3391 uint16_t flags_type;
3392 /* This value identifies the type of buffer descriptor. */
3393 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3394 #define RX_PROD_BFR_BD_TYPE_SFT 0
3396 * Indicates that this BD is 16B long and is an RX
3397 * Producer Buffer BD.
3399 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3400 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3401 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3402 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3404 * This is the length in Bytes of the host physical buffer where
3405 * data for the packet may be placed in host memory.
3408 /* This field is not used. */
3411 * This is the host physical address where data for the packet may
3412 * be placed in host memory.
3417 /* rx_prod_agg_bd (size:128b/16B) */
3418 struct rx_prod_agg_bd {
3419 /* This value identifies the type of buffer descriptor. */
3420 uint16_t flags_type;
3421 /* This value identifies the type of buffer descriptor. */
3422 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3423 #define RX_PROD_AGG_BD_TYPE_SFT 0
3425 * Indicates that this BD is 16B long and is an
3426 * RX Producer Assembly Buffer Descriptor.
3428 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3429 #define RX_PROD_AGG_BD_TYPE_LAST \
3430 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3431 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3432 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3434 * If set to 1, the packet write will be padded out to the
3435 * nearest cache-line with zero value padding.
3437 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3439 * This is the length in Bytes of the host physical buffer where
3440 * data for the packet may be placed in host memory.
3444 * The opaque data field is pass through to the completion and can be
3445 * used for any data that the driver wants to associate with this
3446 * receive assembly buffer.
3450 * This is the host physical address where data for the packet may
3451 * be placed in host memory.
3456 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3457 struct cfa_cmpls_cmp_data_msg {
3458 uint32_t mp_client_dma_length_opcode_status_type;
3460 * This field represents the Mid-Path client that generated the
3463 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3464 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3465 /* Mid Path Short Completion with length = 16B. */
3466 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3468 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3469 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3470 /* This value indicates the status for the command. */
3471 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3472 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3473 /* Completed without error. */
3474 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3475 (UINT32_C(0x0) << 6)
3476 /* Indicates an unsupported CFA opcode in the command. */
3477 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3478 (UINT32_C(0x1) << 6)
3480 * Indicates a CFA command formatting error. This error can occur on
3481 * any of the supported CFA commands.
3483 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3484 (UINT32_C(0x2) << 6)
3486 * Indicates an SVIF-Table scope error. This error can occur on any
3487 * of the supported CFA commands.
3489 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3490 (UINT32_C(0x3) << 6)
3492 * Indicates that the table_index is either outside of the
3493 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3494 * the static bucket range. This error can occur on EM Insert
3495 * commands. It can also occur on Read, Read Clear, Write, and
3496 * Invalidate commands if the table_type is EM.
3498 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3499 (UINT32_C(0x4) << 6)
3501 * Cache operation responded with an error. This error can occur on
3502 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3504 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3505 (UINT32_C(0x5) << 6)
3507 * Indicates failure on EM Insert or EM Delete Command. Hash index
3508 * and hash msb are returned in table_index and hash_msb fields.
3509 * Dma_length is set to 1 if the bucket is also returned (as dma
3512 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3513 (UINT32_C(0x6) << 6)
3515 * Indicates no notifications were available on an Event Collection
3518 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3519 (UINT32_C(0x7) << 6)
3520 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3521 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3522 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3523 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3524 /* This is the opcode from the command. */
3525 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3527 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3529 * This is read command. From 32 to 128B can be read from a table
3530 * using this command.
3532 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3533 (UINT32_C(0x0) << 12)
3535 * This is write command. From 32 to 128B can be written to a table
3536 * using this command.
3538 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3539 (UINT32_C(0x1) << 12)
3541 * This is read-clear command. 32B can be read from a table and a 16b
3542 * mask can be used to clear specific 16b units after the read as an
3545 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3546 (UINT32_C(0x2) << 12)
3548 * An exact match table insert will be attempted into the table. If
3549 * there is a free location in the bucket, the payload will be
3550 * written to the bucket.
3552 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3553 (UINT32_C(0x3) << 12)
3554 /* An exact match table delete will be attempted. */
3555 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3556 (UINT32_C(0x4) << 12)
3558 * The specified table area will be invalidated. If it is needed
3559 * again, it will be read from the backing store.
3561 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3562 (UINT32_C(0x5) << 12)
3563 /* Reads notification messages from the Host Notification Queue. */
3564 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3565 (UINT32_C(0x6) << 12)
3566 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3567 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3569 * This field indicates the length of the DMA that accompanies the
3570 * completion. Specified in units of DWords (32b). Valid values are
3571 * between 0 and 128. A value of zero indicates that there is no DMA
3572 * that accompanies the completion.
3574 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3576 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3578 * This field represents the Mid-Path client that generated the
3581 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3582 UINT32_C(0xf0000000)
3583 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3584 /* TX configurable flow processing block. */
3585 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3586 (UINT32_C(0x2) << 28)
3587 /* RX configurable flow processing block. */
3588 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3589 (UINT32_C(0x3) << 28)
3590 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3591 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3593 * This is a copy of the opaque field from the mid path BD of this
3597 uint16_t hash_msb_v;
3599 * This value is written by the NIC such that it will be different for
3600 * each pass through the completion queue. The even passes will
3601 * write 1. The odd passes will write 0.
3603 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3604 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3605 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3607 * This is the upper 12b of the hash, returned on Exact Match
3608 * Insertion/Deletion Commands.
3610 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3611 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3612 /* This is the table type from the command. */
3614 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3615 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3616 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3617 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3618 /* This command acts on the action table of the specified scope. */
3619 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3620 /* This command acts on the exact match table of the specified scope. */
3621 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3622 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3623 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3624 uint8_t table_scope;
3625 /* This is the table scope from the command. */
3626 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3627 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3628 uint32_t table_index;
3630 * This is the table index from the command (if it exists). However, if
3631 * an Exact Match Insertion/Deletion command failed, then this is the
3632 * table index of the calculated static hash bucket.
3634 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3635 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3638 /* CFA Mid-Path 32B DMA Message */
3639 /* cfa_dma32b_data_msg (size:256b/32B) */
3640 struct cfa_dma32b_data_msg {
3641 /* DMA data value. */
3645 /* CFA Mid-Path 64B DMA Message */
3646 /* cfa_dma64b_data_msg (size:512b/64B) */
3647 struct cfa_dma64b_data_msg {
3648 /* DMA data value. */
3652 /* CFA Mid-Path 96B DMA Message */
3653 /* cfa_dma96b_data_msg (size:768b/96B) */
3654 struct cfa_dma96b_data_msg {
3655 /* DMA data value. */
3659 /* CFA Mid-Path 128B DMA Message */
3660 /* cfa_dma128b_data_msg (size:1024b/128B) */
3661 struct cfa_dma128b_data_msg {
3662 /* DMA data value. */
3666 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3667 struct ce_cmpls_cmp_data_msg {
3668 uint16_t status_subtype_type;
3670 * This field indicates the exact type of the completion. By
3671 * convention, the LSB identifies the length of the record in 16B
3672 * units. Even values indicate 16B records. Odd values indicate 32B
3675 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3676 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3677 /* Completion of a Mid Path Command. Length = 16B */
3678 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3679 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3680 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3682 * This value indicates the CE sub-type operation that is being
3685 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3686 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3687 /* Completion Response for a Solicited Command. */
3688 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3689 /* Error Completion (Unsolicited). */
3690 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3691 /* Re-Sync Completion (Unsolicited) */
3692 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3693 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3694 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3695 /* This value indicates the status for the command. */
3696 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3697 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3698 /* Completed without error. */
3699 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3700 (UINT32_C(0x0) << 10)
3701 /* CFCK load error. */
3702 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3703 (UINT32_C(0x1) << 10)
3704 /* FID check error. */
3705 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3706 (UINT32_C(0x2) << 10)
3707 /* Context kind / MP version mismatch error. */
3708 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \
3709 (UINT32_C(0x3) << 10)
3710 /* Unsupported Destination Connection ID Length. */
3711 #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \
3712 (UINT32_C(0x4) << 10)
3714 * Invalid MP Command [anything other than ADD or DELETE
3715 * triggers this for QUIC].
3717 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \
3718 (UINT32_C(0x5) << 10)
3719 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3720 CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR
3723 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3724 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3726 * This field represents the Mid-Path client that generated the
3729 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3730 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3731 /* TX crypto engine block. */
3732 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3733 /* RX crypto engine block. */
3734 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3735 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3736 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3738 * This is a copy of the opaque field from the mid path BD of this
3745 * This value is written by the NIC such that it will be different
3746 * for each pass through the completion queue. The even passes will
3747 * write 1. The odd passes will write 0.
3749 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3751 * This field is the Crypto Context ID. The KID is used to store
3752 * information used by the associated kTLS offloaded connection.
3754 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3755 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3759 /* cmpl_base (size:128b/16B) */
3763 * This field indicates the exact type of the completion.
3764 * By convention, the LSB identifies the length of the
3765 * record in 16B units. Even values indicate 16B
3766 * records. Odd values indicate 32B
3769 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3770 #define CMPL_BASE_TYPE_SFT 0
3773 * Completion of TX packet. Length = 16B
3775 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3778 * Completion of NO-OP. Length = 16B
3780 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3782 * TX L2 coalesced completion:
3783 * Completion of coalesced TX packet. Length = 16B
3785 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3787 * TX L2 PTP completion:
3788 * Completion of PTP TX packet. Length = 32B
3790 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3792 * TX L2 Packet Timestamp completion:
3793 * Completion of an L2 Packet Timestamp Packet. Length = 16B
3795 #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4)
3797 * RX L2 TPA Start V2 Completion:
3798 * Completion of and L2 RX packet. Length = 32B
3799 * This is the new version of the RX_TPA_START completion used
3800 * in SR2 and later chips.
3802 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3804 * RX L2 V2 completion:
3805 * Completion of and L2 RX packet. Length = 32B
3806 * This is the new version of the RX_L2 completion used in SR2
3809 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3812 * This is the compressed version of Rx Completion for performance
3813 * applications. Length = 16B
3815 #define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
3818 * Completion of and L2 RX packet. Length = 32B
3820 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3822 * RX Aggregation Buffer completion:
3823 * Completion of an L2 aggregation buffer in support of
3824 * TPA, HDS, or Jumbo packet completion. Length = 16B
3826 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3828 * RX L2 TPA Start Completion:
3829 * Completion at the beginning of a TPA operation.
3832 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3834 * RX L2 TPA End Completion:
3835 * Completion at the end of a TPA operation.
3838 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3840 * RX TPA Aggregation Buffer Completion:
3841 * Completion of an L2 aggregation buffer in support of TPA packet
3845 #define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16)
3847 * RX L2 completion: Completion of and L2 RX packet.
3850 #define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17)
3852 * RX L2 TPA Start completion: Completion at the beginning of a TPA
3856 #define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
3858 * Statistics Ejection Completion:
3859 * Completion of statistics data ejection buffer.
3862 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3864 * VEE Flush Completion:
3865 * This completion is inserted manually by
3866 * the Primate and processed by the VEE hardware to ensure that
3867 * all completions on a VEE function have been processed by the
3868 * VEE hardware before FLR process is completed.
3870 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3872 * Mid Path Short Completion :
3873 * Completion of a Mid Path Command. Length = 16B
3875 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3877 * Mid Path Long Completion :
3878 * Completion of a Mid Path Command. Length = 32B
3880 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3882 * HWRM Command Completion:
3883 * Completion of an HWRM command.
3885 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3886 /* Forwarded HWRM Request */
3887 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3888 /* Forwarded HWRM Response */
3889 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3890 /* HWRM Asynchronous Event Information */
3891 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3892 /* CQ Notification */
3893 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3894 /* SRQ Threshold Event */
3895 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3896 /* DBQ Threshold Event */
3897 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3898 /* QP Async Notification */
3899 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3900 /* Function Async Notification */
3901 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3902 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3908 * This value is written by the NIC such that it will be different
3909 * for each pass through the completion queue. The even passes
3910 * will write 1. The odd passes will write 0.
3913 #define CMPL_BASE_V UINT32_C(0x1)
3914 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3915 #define CMPL_BASE_INFO3_SFT 1
3920 /* tx_cmpl (size:128b/16B) */
3922 uint16_t flags_type;
3924 * This field indicates the exact type of the completion.
3925 * By convention, the LSB identifies the length of the
3926 * record in 16B units. Even values indicate 16B
3927 * records. Odd values indicate 32B
3930 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3931 #define TX_CMPL_TYPE_SFT 0
3934 * Completion of TX packet. Length = 16B
3936 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3937 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3938 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3939 #define TX_CMPL_FLAGS_SFT 6
3941 * When this bit is '1', it indicates a packet that has an
3942 * error of some type. Type of error is indicated in
3945 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3947 * When this bit is '1', it indicates that the packet completed
3948 * was transmitted using the push acceleration data provided
3949 * by the driver. When this bit is '0', it indicates that the
3950 * packet had not push acceleration data written or was executed
3951 * as a normal packet even though push data was provided.
3953 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3954 /* unused1 is 16 b */
3957 * This is a copy of the opaque field from the first TX BD of this
3958 * transmitted packet. Note that, if the packet was described by a short
3959 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3960 * short CSO BD will appear in the bottom 16 bits of this field.
3965 * This value is written by the NIC such that it will be different
3966 * for each pass through the completion queue. The even passes
3967 * will write 1. The odd passes will write 0.
3969 #define TX_CMPL_V UINT32_C(0x1)
3970 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3971 #define TX_CMPL_ERRORS_SFT 1
3973 * This error indicates that there was some sort of problem
3974 * with the BDs for the packet.
3976 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3977 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3979 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3980 (UINT32_C(0x0) << 1)
3983 * BDs were not formatted correctly.
3985 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3986 (UINT32_C(0x2) << 1)
3987 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3988 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3990 * When this bit is '1', it indicates that the length of
3991 * the packet was zero. No packet was transmitted.
3993 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3995 * When this bit is '1', it indicates that the packet
3996 * was longer than the programmed limit in TDI. No
3997 * packet was transmitted.
3999 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4001 * When this bit is '1', it indicates that one or more of the
4002 * BDs associated with this packet generated a PCI error.
4003 * This probably means the address was not valid.
4005 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
4007 * When this bit is '1', it indicates that the packet was longer
4008 * than indicated by the hint. No packet was transmitted.
4010 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4012 * When this bit is '1', it indicates that the packet was
4013 * dropped due to Poison TLP error on one or more of the
4014 * TLPs in the PXP completion.
4016 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4018 * When this bit is '1', it indicates that the packet was dropped
4019 * due to a transient internal error in TDC. The packet or LSO can
4020 * be retried and may transmit successfully on a subsequent attempt.
4022 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4024 * When this bit is '1', it was not possible to collect a timestamp
4025 * for a PTP completion, in which case the timestamp_hi and
4026 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4027 * completion, the timestamp_hi and timestamp_lo fields are valid.
4028 * RJRN will copy the value of this bit into the field of the same
4029 * name in all TX completions, regardless of whether such completions
4030 * are PTP completions or other TX completions.
4032 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4033 /* unused2 is 16 b */
4035 /* unused3 is 32 b */
4039 /* tx_cmpl_coal (size:128b/16B) */
4040 struct tx_cmpl_coal {
4041 uint16_t flags_type;
4043 * This field indicates the exact type of the completion.
4044 * By convention, the LSB identifies the length of the
4045 * record in 16B units. Even values indicate 16B
4046 * records. Odd values indicate 32B
4049 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
4050 #define TX_CMPL_COAL_TYPE_SFT 0
4052 * TX L2 coalesced completion:
4053 * Completion of TX packet. Length = 16B
4055 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
4056 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
4057 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
4058 #define TX_CMPL_COAL_FLAGS_SFT 6
4060 * When this bit is '1', it indicates a packet that has an
4061 * error of some type. Type of error is indicated in
4064 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
4066 * When this bit is '1', it indicates that the packet completed
4067 * was transmitted using the push acceleration data provided
4068 * by the driver. When this bit is '0', it indicates that the
4069 * packet had not push acceleration data written or was executed
4070 * as a normal packet even though push data was provided.
4072 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
4073 /* unused1 is 16 b */
4076 * This is a copy of the opaque field from the first TX BD of the packet
4077 * which corresponds with the reported sq_cons_idx. Note that, with
4078 * coalesced completions, completions are generated for only some of the
4079 * packets. The driver will see the opaque field for only those packets.
4080 * Note that, if the packet was described by a short CSO or short CSO
4081 * inline BD, then the 16-bit opaque field from the short CSO BD will
4082 * appear in the bottom 16 bits of this field. For TX rings with
4083 * completion coalescing enabled (which would use the coalesced
4084 * completion record), it is suggested that the driver populate the
4085 * opaque field to indicate the specific TX ring with which the
4086 * completion is associated, then utilize the opaque and sq_cons_idx
4087 * fields in the coalesced completion record to determine the specific
4088 * packets that are to be completed on that ring.
4093 * This value is written by the NIC such that it will be different
4094 * for each pass through the completion queue. The even passes
4095 * will write 1. The odd passes will write 0.
4097 #define TX_CMPL_COAL_V UINT32_C(0x1)
4098 #define TX_CMPL_COAL_ERRORS_MASK \
4100 #define TX_CMPL_COAL_ERRORS_SFT 1
4102 * This error indicates that there was some sort of problem
4103 * with the BDs for the packet.
4105 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4106 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
4108 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
4109 (UINT32_C(0x0) << 1)
4112 * BDs were not formatted correctly.
4114 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
4115 (UINT32_C(0x2) << 1)
4116 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
4117 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
4119 * When this bit is '1', it indicates that the length of
4120 * the packet was zero. No packet was transmitted.
4122 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4124 * When this bit is '1', it indicates that the packet
4125 * was longer than the programmed limit in TDI. No
4126 * packet was transmitted.
4128 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4130 * When this bit is '1', it indicates that one or more of the
4131 * BDs associated with this packet generated a PCI error.
4132 * This probably means the address was not valid.
4134 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
4136 * When this bit is '1', it indicates that the packet was longer
4137 * than indicated by the hint. No packet was transmitted.
4139 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4141 * When this bit is '1', it indicates that the packet was
4142 * dropped due to Poison TLP error on one or more of the
4143 * TLPs in the PXP completion.
4145 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
4148 * When this bit is '1', it indicates that the packet was dropped
4149 * due to a transient internal error in TDC. The packet or LSO can
4150 * be retried and may transmit successfully on a subsequent attempt.
4152 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
4155 * When this bit is '1', it was not possible to collect a a timestamp
4156 * for a PTP completion, in which case the timestamp_hi and
4157 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4158 * completion, the timestamp_hi and timestamp_lo fields are valid.
4159 * RJRN will copy the value of this bit into the field of the same
4160 * name in all TX completions, regardless of whether such
4161 * completions are PTP completions or other TX completions.
4163 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
4165 /* unused2 is 16 b */
4167 uint32_t sq_cons_idx;
4169 * This value is SQ index for the start of the packet following the
4170 * last completed packet.
4172 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
4173 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
4176 /* tx_cmpl_ptp (size:128b/16B) */
4177 struct tx_cmpl_ptp {
4178 uint16_t flags_type;
4180 * This field indicates the exact type of the completion.
4181 * By convention, the LSB identifies the length of the
4182 * record in 16B units. Even values indicate 16B
4183 * records. Odd values indicate 32B
4186 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
4187 #define TX_CMPL_PTP_TYPE_SFT 0
4189 * TX L2 PTP completion:
4190 * Completion of TX packet. Length = 32B
4192 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
4193 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
4194 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
4195 #define TX_CMPL_PTP_FLAGS_SFT 6
4197 * When this bit is '1', it indicates a packet that has an
4198 * error of some type. Type of error is indicated in
4201 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
4203 * When this bit is '1', it indicates that the packet completed
4204 * was transmitted using the push acceleration data provided
4205 * by the driver. When this bit is '0', it indicates that the
4206 * packet had not push acceleration data written or was executed
4207 * as a normal packet even though push data was provided.
4209 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
4210 /* unused1 is 16 b */
4213 * This is a copy of the opaque field from the first TX BD of this
4214 * transmitted packet. Note that, if the packet was described by a short
4215 * CSO or short CSO inline BD, then the 16-bit opaque field from the
4216 * short CSO BD will appear in the bottom 16 bits of this field.
4221 * This value is written by the NIC such that it will be different
4222 * for each pass through the completion queue. The even passes
4223 * will write 1. The odd passes will write 0.
4225 #define TX_CMPL_PTP_V UINT32_C(0x1)
4226 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
4227 #define TX_CMPL_PTP_ERRORS_SFT 1
4229 * This error indicates that there was some sort of problem
4230 * with the BDs for the packet.
4232 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4233 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
4235 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
4236 (UINT32_C(0x0) << 1)
4239 * BDs were not formatted correctly.
4241 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
4242 (UINT32_C(0x2) << 1)
4243 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
4244 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
4246 * When this bit is '1', it indicates that the length of
4247 * the packet was zero. No packet was transmitted.
4249 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4251 * When this bit is '1', it indicates that the packet
4252 * was longer than the programmed limit in TDI. No
4253 * packet was transmitted.
4255 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4257 * When this bit is '1', it indicates that one or more of the
4258 * BDs associated with this packet generated a PCI error.
4259 * This probably means the address was not valid.
4261 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
4263 * When this bit is '1', it indicates that the packet was longer
4264 * than indicated by the hint. No packet was transmitted.
4266 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4268 * When this bit is '1', it indicates that the packet was
4269 * dropped due to Poison TLP error on one or more of the
4270 * TLPs in the PXP completion.
4272 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4274 * When this bit is '1', it indicates that the packet was dropped due
4275 * to a transient internal error in TDC. The packet or LSO can be
4276 * retried and may transmit successfully on a subsequent attempt.
4278 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4280 * When this bit is '1', it was not possible to collect a a timestamp
4281 * for a PTP completion, in which case the timestamp_hi and
4282 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4283 * completion, the timestamp_hi and timestamp_lo fields are valid.
4284 * RJRN will copy the value of this bit into the field of the same
4285 * name in all TX completions, regardless of whether such
4286 * completions are PTP completions or other TX completions.
4288 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4289 /* unused2 is 16 b */
4292 * This is timestamp value (lower 32bits) read from PM for the PTP
4293 * timestamp enabled packet.
4295 uint32_t timestamp_lo;
4298 /* tx_cmpl_ptp_hi (size:128b/16B) */
4299 struct tx_cmpl_ptp_hi {
4301 * This is timestamp value (lower 32bits) read from PM for the PTP
4302 * timestamp enabled packet.
4304 uint16_t timestamp_hi[3];
4305 uint16_t reserved16;
4308 * This value is written by the NIC such that it will be different for
4309 * each pass through the completion queue.
4310 * The even passes will write 1.
4311 * The odd passes will write 0.
4313 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4316 /* rx_pkt_cmpl (size:128b/16B) */
4317 struct rx_pkt_cmpl {
4318 uint16_t flags_type;
4320 * This field indicates the exact type of the completion.
4321 * By convention, the LSB identifies the length of the
4322 * record in 16B units. Even values indicate 16B
4323 * records. Odd values indicate 32B
4326 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4327 #define RX_PKT_CMPL_TYPE_SFT 0
4330 * Completion of and L2 RX packet. Length = 32B
4332 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4333 #define RX_PKT_CMPL_TYPE_LAST \
4334 RX_PKT_CMPL_TYPE_RX_L2
4335 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4336 #define RX_PKT_CMPL_FLAGS_SFT 6
4338 * When this bit is '1', it indicates a packet that has an
4339 * error of some type. Type of error is indicated in
4342 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4343 /* This field indicates how the packet was placed in the buffer. */
4344 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4345 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4348 * Packet was placed using normal algorithm.
4350 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL \
4351 (UINT32_C(0x0) << 7)
4354 * Packet was placed using jumbo algorithm.
4356 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO \
4357 (UINT32_C(0x1) << 7)
4359 * Header/Data Separation:
4360 * Packet was placed using Header/Data separation algorithm.
4361 * The separation location is indicated by the itype field.
4363 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS \
4364 (UINT32_C(0x2) << 7)
4365 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4366 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4367 /* This bit is '1' if the RSS field in this completion is valid. */
4368 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4370 * This bit is '1' if metadata has been added to the end of the
4371 * packet in host memory.
4373 #define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4375 * This value indicates what the inner packet determined for the
4378 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4379 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4382 * Indicates that the packet type was not known.
4384 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4385 (UINT32_C(0x0) << 12)
4388 * Indicates that the packet was an IP packet, but further
4389 * classification was not possible.
4391 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4392 (UINT32_C(0x1) << 12)
4395 * Indicates that the packet was IP and TCP.
4396 * This indicates that the payload_offset field is valid.
4398 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4399 (UINT32_C(0x2) << 12)
4402 * Indicates that the packet was IP and UDP.
4403 * This indicates that the payload_offset field is valid.
4405 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4406 (UINT32_C(0x3) << 12)
4409 * Indicates that the packet was recognized as a FCoE.
4410 * This also indicates that the payload_offset field is valid.
4412 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4413 (UINT32_C(0x4) << 12)
4416 * Indicates that the packet was recognized as a RoCE.
4417 * This also indicates that the payload_offset field is valid.
4419 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4420 (UINT32_C(0x5) << 12)
4423 * Indicates that the packet was recognized as ICMP.
4424 * This indicates that the payload_offset field is valid.
4426 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4427 (UINT32_C(0x7) << 12)
4429 * PTP packet wo/timestamp:
4430 * Indicates that the packet was recognized as a PTP
4433 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4434 (UINT32_C(0x8) << 12)
4436 * PTP packet w/timestamp:
4437 * Indicates that the packet was recognized as a PTP
4438 * packet and that a timestamp was taken for the packet.
4440 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4441 (UINT32_C(0x9) << 12)
4442 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4443 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4445 * This is the length of the data for the packet stored in the
4446 * buffer(s) identified by the opaque value. This includes
4447 * the packet BD and any associated buffer BDs. This does not include
4448 * the length of any data places in aggregation BDs.
4452 * This is a copy of the opaque field from the RX BD this completion
4456 uint8_t agg_bufs_v1;
4458 * This value is written by the NIC such that it will be different
4459 * for each pass through the completion queue. The even passes
4460 * will write 1. The odd passes will write 0.
4462 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4464 * This value is the number of aggregation buffers that follow this
4465 * entry in the completion ring that are a part of this packet.
4466 * If the value is zero, then the packet is completely contained
4467 * in the buffer space provided for the packet in the RX ring.
4469 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4470 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4471 /* unused1 is 2 b */
4472 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4473 #define RX_PKT_CMPL_UNUSED1_SFT 6
4475 * This is the RSS hash type for the packet. The value is packed
4476 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4477 * The value of tuple_extrac_op provides the information about
4478 * what fields the hash was computed on.
4479 * Note that 4-tuples values listed below are applicable
4480 * for layer 4 protocols supported and enabled for RSS in the hardware,
4481 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4482 * enabled for TCP traffic only, then the values of tuple_extract_op
4483 * corresponding to 4-tuples are only valid for TCP traffic.
4485 uint8_t rss_hash_type;
4487 * The RSS hash was computed over source IP address,
4488 * destination IP address, source port, and destination port of inner
4489 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4490 * the packet headers are considered inner packet headers for the RSS
4491 * hash computation purpose.
4493 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
4495 * The RSS hash was computed over source IP address and destination
4496 * IP address of inner IP header. Note: For non-tunneled packets,
4497 * the packet headers are considered inner packet headers for the RSS
4498 * hash computation purpose.
4500 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
4502 * The RSS hash was computed over source IP address,
4503 * destination IP address, source port, and destination port of
4504 * IP and TCP or UDP headers of outer tunnel headers.
4505 * Note: For non-tunneled packets, this value is not applicable.
4507 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
4509 * The RSS hash was computed over source IP address and
4510 * destination IP address of IP header of outer tunnel headers.
4511 * Note: For non-tunneled packets, this value is not applicable.
4513 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
4514 #define RX_PKT_CMPL_RSS_HASH_TYPE_LAST \
4515 RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3
4517 * This value indicates the offset in bytes from the beginning of the
4518 * packet where the inner payload starts. This value is valid for TCP,
4519 * UDP, FCoE, and RoCE packets.
4521 * A value of zero indicates that header is 256B into the packet.
4523 uint8_t payload_offset;
4524 /* unused2 is 8 b */
4527 * This value is the RSS hash value calculated for the packet
4528 * based on the mode bits and key value in the VNIC.
4533 /* Last 16 bytes of rx_pkt_cmpl. */
4534 /* rx_pkt_cmpl_hi (size:128b/16B) */
4535 struct rx_pkt_cmpl_hi {
4538 * This indicates that the ip checksum was calculated for the
4539 * inner packet and that the ip_cs_error field indicates if there
4542 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4544 * This indicates that the TCP, UDP or ICMP checksum was
4545 * calculated for the inner packet and that the l4_cs_error field
4546 * indicates if there was an error.
4548 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4550 * This indicates that the ip checksum was calculated for the
4551 * tunnel header and that the t_ip_cs_error field indicates if there
4554 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4556 * This indicates that the UDP checksum was
4557 * calculated for the tunnel packet and that the t_l4_cs_error field
4558 * indicates if there was an error.
4560 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4561 /* This value indicates what format the metadata field is. */
4562 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4563 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4564 /* No metadata information. Value is zero. */
4565 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4566 (UINT32_C(0x0) << 4)
4568 * The metadata field contains the VLAN tag and TPID value.
4569 * - metadata[11:0] contains the vlan VID value.
4570 * - metadata[12] contains the vlan DE value.
4571 * - metadata[15:13] contains the vlan PRI value.
4572 * - metadata[31:16] contains the vlan TPID value.
4574 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4575 (UINT32_C(0x1) << 4)
4577 * If ext_meta_format is equal to 1, the metadata field
4578 * contains the lower 16b of the tunnel ID value, justified
4580 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4581 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4582 * - NVGRE = TNI[23:0] -> Tenant Network ID
4583 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4584 * - IPV4 = 0 (not populated)
4585 * - IPV6 = Flow Label[19:0]
4586 * - PPPoE = sessionID[15:0]
4587 * - MPLs = Outer label[19:0]
4588 * - UPAR = Selected[31:0] with bit mask
4590 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4591 (UINT32_C(0x2) << 4)
4593 * if ext_meta_format is equal to 1, metadata field contains
4594 * 16b metadata from the prepended header (chdr_data).
4596 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4597 (UINT32_C(0x3) << 4)
4599 * If ext_meta_format is equal to 1, the metadata field contains
4600 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4602 * - metadata[8:0] contains the outer_l3_offset.
4603 * - metadata[17:9] contains the inner_l2_offset.
4604 * - metadata[26:18] contains the inner_l3_offset.
4605 * - metadata[31:27] contains the inner_l4_size.
4607 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4608 (UINT32_C(0x4) << 4)
4609 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4610 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4612 * This field indicates the IP type for the inner-most IP header.
4613 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4614 * This value is only valid if itype indicates a packet
4615 * with an IP header.
4617 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4619 * This indicates that the complete 1's complement checksum was
4620 * calculated for the packet.
4622 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4624 * The combination of this value and meta_format indicated what
4625 * format the metadata field is.
4627 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4628 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4630 * This value is the complete 1's complement checksum calculated from
4631 * the start of the outer L3 header to the end of the packet (not
4632 * including the ethernet crc). It is valid when the
4633 * 'complete_checksum_calc' flag is set.
4635 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4636 UINT32_C(0xffff0000)
4637 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4639 * This is data from the CFA block as indicated by the meta_format
4643 /* When meta_format=1, this value is the VLAN VID. */
4644 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4645 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4646 /* When meta_format=1, this value is the VLAN DE. */
4647 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4648 /* When meta_format=1, this value is the VLAN PRI. */
4649 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4650 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4651 /* When meta_format=1, this value is the VLAN TPID. */
4652 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4653 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4656 * This value is written by the NIC such that it will be different
4657 * for each pass through the completion queue. The even passes
4658 * will write 1. The odd passes will write 0.
4660 #define RX_PKT_CMPL_V2 \
4662 #define RX_PKT_CMPL_ERRORS_MASK \
4664 #define RX_PKT_CMPL_ERRORS_SFT 1
4666 * This error indicates that there was some sort of problem with
4667 * the BDs for the packet that was found after part of the
4668 * packet was already placed. The packet should be treated as
4671 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4673 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4674 /* No buffer error */
4675 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4676 (UINT32_C(0x0) << 1)
4679 * Packet did not fit into packet buffer provided.
4680 * For regular placement, this means the packet did not fit
4681 * in the buffer provided. For HDS and jumbo placement, this
4682 * means that the packet could not be placed into 7 physical
4685 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4686 (UINT32_C(0x1) << 1)
4689 * All BDs needed for the packet were not on-chip when
4690 * the packet arrived.
4692 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4693 (UINT32_C(0x2) << 1)
4696 * BDs were not formatted correctly.
4698 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4699 (UINT32_C(0x3) << 1)
4702 * There was a bad_format error on the previous operation
4704 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4705 (UINT32_C(0x5) << 1)
4706 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4707 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4709 * This indicates that there was an error in the IP header
4712 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4715 * This indicates that there was an error in the TCP, UDP
4718 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4721 * This indicates that there was an error in the tunnel
4722 * IP header checksum.
4724 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4727 * This indicates that there was an error in the tunnel
4730 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4733 * This indicates that there was a CRC error on either an FCoE
4734 * or RoCE packet. The itype indicates the packet type.
4736 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4739 * This indicates that there was an error in the tunnel
4740 * portion of the packet when this
4741 * field is non-zero.
4743 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4745 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4747 * No additional error occurred on the tunnel portion
4748 * or the packet of the packet does not have a tunnel.
4750 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4751 (UINT32_C(0x0) << 9)
4753 * Indicates that IP header version does not match
4754 * expectation from L2 Ethertype for IPv4 and IPv6
4755 * in the tunnel header.
4757 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4758 (UINT32_C(0x1) << 9)
4760 * Indicates that header length is out of range in the
4761 * tunnel header. Valid for
4764 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4765 (UINT32_C(0x2) << 9)
4767 * Indicates that the physical packet is shorter than that
4768 * claimed by the PPPoE header length for a tunnel PPPoE
4771 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4772 (UINT32_C(0x3) << 9)
4774 * Indicates that physical packet is shorter than that claimed
4775 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4776 * tunnel packet packets.
4778 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4779 (UINT32_C(0x4) << 9)
4781 * Indicates that the physical packet is shorter than that
4782 * claimed by the tunnel UDP header length for a tunnel
4783 * UDP packet that is not fragmented.
4785 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4786 (UINT32_C(0x5) << 9)
4788 * indicates that the IPv4 TTL or IPv6 hop limit check
4789 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4790 * for IPv4, and IPv6.
4792 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4793 (UINT32_C(0x6) << 9)
4794 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4795 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4797 * This indicates that there was an error in the inner
4798 * portion of the packet when this
4799 * field is non-zero.
4801 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4803 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4805 * No additional error occurred on the tunnel portion
4806 * or the packet of the packet does not have a tunnel.
4808 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4809 (UINT32_C(0x0) << 12)
4811 * Indicates that IP header version does not match
4812 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4813 * option other than VFT was parsed on
4816 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4817 (UINT32_C(0x1) << 12)
4819 * indicates that header length is out of range. Valid for
4822 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4823 (UINT32_C(0x2) << 12)
4825 * indicates that the IPv4 TTL or IPv6 hop limit check
4826 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4828 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4829 (UINT32_C(0x3) << 12)
4831 * Indicates that physical packet is shorter than that
4832 * claimed by the l3 header length. Valid for IPv4,
4833 * IPv6 packet or RoCE packets.
4835 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4836 (UINT32_C(0x4) << 12)
4838 * Indicates that the physical packet is shorter than that
4839 * claimed by the UDP header length for a UDP packet that is
4842 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4843 (UINT32_C(0x5) << 12)
4845 * Indicates that TCP header length > IP payload. Valid for
4848 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4849 (UINT32_C(0x6) << 12)
4850 /* Indicates that TCP header length < 5. Valid for TCP. */
4851 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4852 (UINT32_C(0x7) << 12)
4854 * Indicates that TCP option headers result in a TCP header
4855 * size that does not match data offset in TCP header. Valid
4858 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4859 (UINT32_C(0x8) << 12)
4860 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4861 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4863 * This field identifies the CFA action rule that was used for this
4869 * This value holds the reordering sequence number for the packet.
4870 * If the reordering sequence is not valid, then this value is zero.
4871 * The reordering domain for the packet is in the bottom 8 to 10b of
4872 * the rss_hash value. The bottom 20b of this value contain the
4873 * ordering domain value for the packet.
4875 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4876 #define RX_PKT_CMPL_REORDER_SFT 0
4879 /* rx_pkt_v2_cmpl (size:128b/16B) */
4880 struct rx_pkt_v2_cmpl {
4881 uint16_t flags_type;
4883 * This field indicates the exact type of the completion.
4884 * By convention, the LSB identifies the length of the
4885 * record in 16B units. Even values indicate 16B
4886 * records. Odd values indicate 32B
4889 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4890 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4892 * RX L2 V2 completion:
4893 * Completion of and L2 RX packet. Length = 32B
4894 * This is the new version of the RX_L2 completion used in SR2
4897 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4898 #define RX_PKT_V2_CMPL_TYPE_LAST \
4899 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4900 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4901 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4903 * When this bit is '1', it indicates a packet that has an
4904 * error of some type. Type of error is indicated in
4907 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4908 /* This field indicates how the packet was placed in the buffer. */
4909 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4910 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4913 * Packet was placed using normal algorithm.
4915 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4916 (UINT32_C(0x0) << 7)
4919 * Packet was placed using jumbo algorithm.
4921 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4922 (UINT32_C(0x1) << 7)
4924 * Header/Data Separation:
4925 * Packet was placed using Header/Data separation algorithm.
4926 * The separation location is indicated by the itype field.
4928 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4929 (UINT32_C(0x2) << 7)
4932 * Packet was placed using truncation algorithm. The
4933 * placed (truncated) length is indicated in the payload_offset
4934 * field. The original length is indicated in the len field.
4936 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4937 (UINT32_C(0x3) << 7)
4938 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4939 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4940 /* This bit is '1' if the RSS field in this completion is valid. */
4941 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4943 * This bit is '1' if metadata has been added to the end of the
4944 * packet in host memory. Metadata starts at the first 32B boundary
4945 * after the end of the packet for regular and jumbo placement.
4946 * It starts at the first 32B boundary after the end of the header
4947 * for HDS placement. The length of the metadata is indicated in the
4950 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4952 * This value indicates what the inner packet determined for the
4955 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4956 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4959 * Indicates that the packet type was not known.
4961 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4962 (UINT32_C(0x0) << 12)
4965 * Indicates that the packet was an IP packet, but further
4966 * classification was not possible.
4968 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4969 (UINT32_C(0x1) << 12)
4972 * Indicates that the packet was IP and TCP.
4973 * This indicates that the payload_offset field is valid.
4975 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4976 (UINT32_C(0x2) << 12)
4979 * Indicates that the packet was IP and UDP.
4980 * This indicates that the payload_offset field is valid.
4982 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4983 (UINT32_C(0x3) << 12)
4986 * Indicates that the packet was recognized as a FCoE.
4987 * This also indicates that the payload_offset field is valid.
4989 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4990 (UINT32_C(0x4) << 12)
4993 * Indicates that the packet was recognized as a RoCE.
4994 * This also indicates that the payload_offset field is valid.
4996 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4997 (UINT32_C(0x5) << 12)
5000 * Indicates that the packet was recognized as ICMP.
5001 * This indicates that the payload_offset field is valid.
5003 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
5004 (UINT32_C(0x7) << 12)
5006 * PTP packet wo/timestamp:
5007 * Indicates that the packet was recognized as a PTP
5010 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
5011 (UINT32_C(0x8) << 12)
5013 * PTP packet w/timestamp:
5014 * Indicates that the packet was recognized as a PTP
5015 * packet and that a timestamp was taken for the packet.
5017 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
5018 (UINT32_C(0x9) << 12)
5019 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
5020 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
5022 * This is the length of the data for the packet stored in the
5023 * buffer(s) identified by the opaque value. This includes
5024 * the packet BD and any associated buffer BDs. This does not include
5025 * the length of any data places in aggregation BDs.
5029 * This is a copy of the opaque field from the RX BD this completion
5033 uint8_t agg_bufs_v1;
5035 * This value is written by the NIC such that it will be different
5036 * for each pass through the completion queue. The even passes
5037 * will write 1. The odd passes will write 0.
5039 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
5041 * This value is the number of aggregation buffers that follow this
5042 * entry in the completion ring that are a part of this packet.
5043 * If the value is zero, then the packet is completely contained
5044 * in the buffer space provided for the packet in the RX ring.
5046 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5047 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
5048 /* unused1 is 2 b */
5049 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
5050 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
5052 * This is the RSS hash type for the packet. The value is packed
5053 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5054 * The value of tuple_extrac_op provides the information about
5055 * what fields the hash was computed on.
5056 * Note that 4-tuples values listed below are applicable
5057 * for layer 4 protocols supported and enabled for RSS in the hardware,
5058 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5059 * enabled for TCP traffic only, then the values of tuple_extract_op
5060 * corresponding to 4-tuples are only valid for TCP traffic.
5062 uint8_t rss_hash_type;
5064 * The RSS hash was computed over source IP address,
5065 * destination IP address, source port, and destination port of inner
5066 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5067 * the packet headers are considered inner packet headers for the RSS
5068 * hash computation purpose.
5070 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
5072 * The RSS hash was computed over source IP address and destination
5073 * IP address of inner IP header. Note: For non-tunneled packets,
5074 * the packet headers are considered inner packet headers for the RSS
5075 * hash computation purpose.
5077 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
5079 * The RSS hash was computed over source IP address,
5080 * destination IP address, source port, and destination port of
5081 * IP and TCP or UDP headers of outer tunnel headers.
5082 * Note: For non-tunneled packets, this value is not applicable.
5084 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
5086 * The RSS hash was computed over source IP address and
5087 * destination IP address of IP header of outer tunnel headers.
5088 * Note: For non-tunneled packets, this value is not applicable.
5090 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
5091 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_LAST \
5092 RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3
5093 uint16_t metadata1_payload_offset;
5095 * This is data from the CFA as indicated by the meta_format field.
5096 * If truncation placement is not used, this value indicates the offset
5097 * in bytes from the beginning of the packet where the inner payload
5098 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
5099 * truncation placement is used, this value represents the placed
5100 * (truncated) length of the packet.
5102 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
5103 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
5104 /* This is data from the CFA as indicated by the meta_format field. */
5105 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
5106 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
5107 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5108 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
5109 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5111 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5112 (UINT32_C(0x0) << 12)
5114 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5115 (UINT32_C(0x1) << 12)
5117 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5118 (UINT32_C(0x2) << 12)
5120 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5121 (UINT32_C(0x3) << 12)
5123 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5124 (UINT32_C(0x4) << 12)
5125 /* Value programmed in CFA VLANTPID register. */
5126 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5127 (UINT32_C(0x5) << 12)
5128 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
5129 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5130 /* When meta_format != 0, this value is the VLAN valid. */
5131 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
5133 * This value is the RSS hash value calculated for the packet
5134 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
5135 * is set in VNIC context, this is the lower 32b of the host address
5136 * from the first BD used to place the packet.
5141 /* Last 16 bytes of RX Packet V2 Completion Record */
5142 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
5143 struct rx_pkt_v2_cmpl_hi {
5146 * When this bit is '0', the cs_ok field has the following definition:-
5147 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5148 * in the delivered packet, counted from the outer-most header group to
5149 * the inner-most header group, stopping at the first error. -
5150 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5151 * in the delivered packet, counted from the outer-most header group to
5152 * the inner-most header group, stopping at the first error. When this
5153 * bit is '1', the cs_ok field has the following definition: -
5154 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5155 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5156 * will be '1' if all the parsed header groups with an IP checksum are
5157 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5158 * header groups with an L4 checksum are valid.
5160 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
5162 /* This value indicates what format the metadata field is. */
5163 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
5165 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
5166 /* There is no metadata information. Values are zero. */
5167 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
5168 (UINT32_C(0x0) << 4)
5170 * The {metadata1, metadata0} fields contain the vtag
5171 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5172 * de, vid[11:0]} The metadata2 field contains the table scope
5173 * and action record pointer. - metadata2[25:0] contains the
5174 * action record pointer. - metadata2[31:26] contains the table
5177 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
5178 (UINT32_C(0x1) << 4)
5180 * The {metadata1, metadata0} fields contain the vtag
5182 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5183 * The metadata2 field contains the Tunnel ID
5184 * value, justified to LSB.
5185 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5186 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5187 * - NVGRE = TNI[23:0] -> Tenant Network ID
5188 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5189 * - IPv4 = 0 (not populated)
5190 * - IPv6 = Flow Label[19:0]
5191 * - PPPoE = sessionID[15:0]
5192 * - MPLs = Outer label[19:0]
5193 * - UPAR = Selected[31:0] with bit mask
5195 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
5196 (UINT32_C(0x2) << 4)
5198 * The {metadata1, metadata0} fields contain the vtag
5200 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5201 * The metadata2 field contains the 32b metadata from the prepended
5202 * header (chdr_data).
5204 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
5205 (UINT32_C(0x3) << 4)
5207 * The {metadata1, metadata0} fields contain the vtag
5209 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5210 * The metadata2 field contains the outer_l3_offset,
5211 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5212 * - metadata2[8:0] contains the outer_l3_offset.
5213 * - metadata2[17:9] contains the inner_l2_offset.
5214 * - metadata2[26:18] contains the inner_l3_offset.
5215 * - metadata2[31:27] contains the inner_l4_size.
5217 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
5218 (UINT32_C(0x4) << 4)
5219 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
5220 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
5222 * This field indicates the IP type for the inner-most IP header.
5223 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5224 * This value is only valid if itype indicates a packet
5225 * with an IP header.
5227 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
5230 * This indicates that the complete 1's complement checksum was
5231 * calculated for the packet.
5233 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
5236 * This field indicates the status of IP and L4 CS calculations done
5237 * by the chip. The format of this field is indicated by the
5238 * cs_all_ok_mode bit.
5240 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
5242 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
5244 * This value is the complete 1's complement checksum calculated from
5245 * the start of the outer L3 header to the end of the packet (not
5246 * including the ethernet crc). It is valid when the
5247 * 'complete_checksum_calc' flag is set.
5249 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5250 UINT32_C(0xffff0000)
5251 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5253 * This is data from the CFA block as indicated by the meta_format
5255 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5256 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5257 * act_rec_ptr[25:0]}
5258 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5259 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5260 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5261 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5262 * of the host address from the first BD used to place the packet.
5267 * This value is written by the NIC such that it will be different
5268 * for each pass through the completion queue. The even passes
5269 * will write 1. The odd passes will write 0.
5271 #define RX_PKT_V2_CMPL_HI_V2 \
5273 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
5275 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
5277 * This error indicates that there was some sort of problem with
5278 * the BDs for the packet that was found after part of the
5279 * packet was already placed. The packet should be treated as
5282 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
5284 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
5285 /* No buffer error */
5286 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
5287 (UINT32_C(0x0) << 1)
5289 * Did Not Fit: Packet did not fit into packet buffer provided.
5290 * For regular placement, this means the packet did not fit in
5291 * the buffer provided. For HDS and jumbo placement, this means
5292 * that the packet could not be placed into 8 physical buffers
5293 * (if fixed-size buffers are used), or that the packet could
5294 * not be placed in the number of physical buffers configured
5295 * for the VNIC (if variable-size buffers are used)
5297 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5298 (UINT32_C(0x1) << 1)
5300 * Not On Chip: All BDs needed for the packet were not on-chip
5301 * when the packet arrived. For regular placement, this error is
5302 * not valid. For HDS and jumbo placement, this means that not
5303 * enough agg BDs were posted to place the packet.
5305 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5306 (UINT32_C(0x2) << 1)
5309 * BDs were not formatted correctly.
5311 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5312 (UINT32_C(0x3) << 1)
5315 * There was a bad_format error on the previous operation
5317 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
5318 (UINT32_C(0x5) << 1)
5319 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
5320 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5322 * This indicates that there was an error in the outer tunnel
5323 * portion of the packet when this field is non-zero.
5325 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5327 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5329 * No additional error occurred on the outer tunnel portion
5330 * of the packet or the packet does not have a outer tunnel.
5332 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5333 (UINT32_C(0x0) << 4)
5335 * Indicates that IP header version does not match expectation
5336 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5338 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5339 (UINT32_C(0x1) << 4)
5341 * Indicates that header length is out of range in the outer
5342 * tunnel header. Valid for IPv4.
5344 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5345 (UINT32_C(0x2) << 4)
5347 * Indicates that physical packet is shorter than that claimed
5348 * by the outer tunnel l3 header length. Valid for IPv4, or
5349 * IPv6 outer tunnel packets.
5351 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5352 (UINT32_C(0x3) << 4)
5354 * Indicates that the physical packet is shorter than that
5355 * claimed by the outer tunnel UDP header length for a outer
5356 * tunnel UDP packet that is not fragmented.
5358 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5359 (UINT32_C(0x4) << 4)
5361 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5362 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5365 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5366 (UINT32_C(0x5) << 4)
5368 * Indicates that the IP checksum failed its check in the outer
5371 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5372 (UINT32_C(0x6) << 4)
5374 * Indicates that the L4 checksum failed its check in the outer
5377 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5378 (UINT32_C(0x7) << 4)
5379 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5380 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5382 * This indicates that there was a CRC error on either an FCoE
5383 * or RoCE packet. The itype indicates the packet type.
5385 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5388 * This indicates that there was an error in the tunnel portion
5389 * of the packet when this field is non-zero.
5391 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5393 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5395 * No additional error occurred on the tunnel portion
5396 * of the packet or the packet does not have a tunnel.
5398 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5399 (UINT32_C(0x0) << 9)
5401 * Indicates that IP header version does not match expectation
5402 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5404 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5405 (UINT32_C(0x1) << 9)
5407 * Indicates that header length is out of range in the tunnel
5408 * header. Valid for IPv4.
5410 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5411 (UINT32_C(0x2) << 9)
5413 * Indicates that physical packet is shorter than that claimed
5414 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5417 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5418 (UINT32_C(0x3) << 9)
5420 * Indicates that the physical packet is shorter than that claimed
5421 * by the tunnel UDP header length for a tunnel UDP packet that is
5424 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5425 (UINT32_C(0x4) << 9)
5427 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5428 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5430 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5431 (UINT32_C(0x5) << 9)
5433 * Indicates that the IP checksum failed its check in the tunnel
5436 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5437 (UINT32_C(0x6) << 9)
5439 * Indicates that the L4 checksum failed its check in the tunnel
5442 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5443 (UINT32_C(0x7) << 9)
5444 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5445 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5447 * This indicates that there was an error in the inner
5448 * portion of the packet when this
5449 * field is non-zero.
5451 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5453 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5455 * No additional error occurred on the tunnel portion
5456 * or the packet of the packet does not have a tunnel.
5458 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5459 (UINT32_C(0x0) << 12)
5461 * Indicates that IP header version does not match
5462 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5463 * option other than VFT was parsed on
5466 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5467 (UINT32_C(0x1) << 12)
5469 * indicates that header length is out of range. Valid for
5472 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5473 (UINT32_C(0x2) << 12)
5475 * indicates that the IPv4 TTL or IPv6 hop limit check
5476 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5478 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5479 (UINT32_C(0x3) << 12)
5481 * Indicates that physical packet is shorter than that
5482 * claimed by the l3 header length. Valid for IPv4,
5483 * IPv6 packet or RoCE packets.
5485 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5486 (UINT32_C(0x4) << 12)
5488 * Indicates that the physical packet is shorter than that
5489 * claimed by the UDP header length for a UDP packet that is
5492 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5493 (UINT32_C(0x5) << 12)
5495 * Indicates that TCP header length > IP payload. Valid for
5498 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5499 (UINT32_C(0x6) << 12)
5500 /* Indicates that TCP header length < 5. Valid for TCP. */
5501 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5502 (UINT32_C(0x7) << 12)
5504 * Indicates that TCP option headers result in a TCP header
5505 * size that does not match data offset in TCP header. Valid
5508 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5509 (UINT32_C(0x8) << 12)
5511 * Indicates that the IP checksum failed its check in the
5514 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5515 (UINT32_C(0x9) << 12)
5517 * Indicates that the L4 checksum failed its check in the
5520 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5521 (UINT32_C(0xa) << 12)
5522 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5523 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5525 * This is data from the CFA block as indicated by the meta_format
5529 /* When meta_format=1, this value is the VLAN VID. */
5530 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5531 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5532 /* When meta_format=1, this value is the VLAN DE. */
5533 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5534 /* When meta_format=1, this value is the VLAN PRI. */
5535 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5536 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5538 * The timestamp field contains the 32b timestamp for the packet from
5544 /* rx_pkt_v3_cmpl (size:128b/16B) */
5545 struct rx_pkt_v3_cmpl {
5546 uint16_t flags_type;
5548 * This field indicates the exact type of the completion.
5549 * By convention, the LSB identifies the length of the
5550 * record in 16B units. Even values indicate 16B
5551 * records. Odd values indicate 32B
5554 #define RX_PKT_V3_CMPL_TYPE_MASK UINT32_C(0x3f)
5555 #define RX_PKT_V3_CMPL_TYPE_SFT 0
5557 * RX L2 V3 completion:
5558 * Completion of and L2 RX packet. Length = 32B
5559 * This is the new version of the RX_L2 completion used in Thor2
5562 #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 UINT32_C(0x17)
5563 #define RX_PKT_V3_CMPL_TYPE_LAST \
5564 RX_PKT_V3_CMPL_TYPE_RX_L2_V3
5565 #define RX_PKT_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5566 #define RX_PKT_V3_CMPL_FLAGS_SFT 6
5568 * When this bit is '1', it indicates a packet that has an
5569 * error of some type. Type of error is indicated in
5572 #define RX_PKT_V3_CMPL_FLAGS_ERROR UINT32_C(0x40)
5573 /* This field indicates how the packet was placed in the buffer. */
5574 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5575 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_SFT 7
5578 * Packet was placed using normal algorithm.
5580 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL \
5581 (UINT32_C(0x0) << 7)
5584 * Packet was placed using jumbo algorithm.
5586 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO \
5587 (UINT32_C(0x1) << 7)
5589 * Header/Data Separation:
5590 * Packet was placed using Header/Data separation algorithm.
5591 * The separation location is indicated by the itype field.
5593 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS \
5594 (UINT32_C(0x2) << 7)
5597 * Packet was placed using truncation algorithm. The
5598 * placed (truncated) length is indicated in the payload_offset
5599 * field. The original length is indicated in the len field.
5601 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION \
5602 (UINT32_C(0x3) << 7)
5603 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_LAST \
5604 RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION
5605 /* This bit is '1' if the RSS field in this completion is valid. */
5606 #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5608 * This bit is '1' if metadata has been added to the end of the
5609 * packet in host memory. Metadata starts at the first 32B boundary
5610 * after the end of the packet for regular and jumbo placement.
5611 * It starts at the first 32B boundary after the end of the header
5612 * for HDS placement. The length of the metadata is indicated in the
5615 #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
5617 * This value indicates what the inner packet determined for the
5620 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5621 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_SFT 12
5624 * Indicates that the packet type was not known.
5626 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN \
5627 (UINT32_C(0x0) << 12)
5630 * Indicates that the packet was an IP packet, but further
5631 * classification was not possible.
5633 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP \
5634 (UINT32_C(0x1) << 12)
5637 * Indicates that the packet was IP and TCP.
5638 * This indicates that the payload_offset field is valid.
5640 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP \
5641 (UINT32_C(0x2) << 12)
5644 * Indicates that the packet was IP and UDP.
5645 * This indicates that the payload_offset field is valid.
5647 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP \
5648 (UINT32_C(0x3) << 12)
5651 * Indicates that the packet was recognized as a FCoE.
5652 * This also indicates that the payload_offset field is valid.
5654 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE \
5655 (UINT32_C(0x4) << 12)
5658 * Indicates that the packet was recognized as a RoCE.
5659 * This also indicates that the payload_offset field is valid.
5661 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE \
5662 (UINT32_C(0x5) << 12)
5665 * Indicates that the packet was recognized as ICMP.
5666 * This indicates that the payload_offset field is valid.
5668 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP \
5669 (UINT32_C(0x7) << 12)
5671 * PTP packet wo/timestamp:
5672 * Indicates that the packet was recognized as a PTP
5675 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
5676 (UINT32_C(0x8) << 12)
5678 * PTP packet w/timestamp:
5679 * Indicates that the packet was recognized as a PTP
5680 * packet and that a timestamp was taken for the packet.
5681 * The 4b sub-nanosecond portion of the timestamp is in
5682 * the payload_offset field.
5684 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
5685 (UINT32_C(0x9) << 12)
5686 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_LAST \
5687 RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
5689 * This is the length of the data for the packet stored in the
5690 * buffer(s) identified by the opaque value. This includes
5691 * the packet BD and any associated buffer BDs. This does not include
5692 * the length of any data places in aggregation BDs.
5696 * This is a copy of the opaque field from the RX BD this completion
5700 uint16_t rss_hash_type_agg_bufs_v1;
5702 * This value is written by the NIC such that it will be different
5703 * for each pass through the completion queue. The even passes
5704 * will write 1. The odd passes will write 0.
5706 #define RX_PKT_V3_CMPL_V1 UINT32_C(0x1)
5708 * This value is the number of aggregation buffers that follow this
5709 * entry in the completion ring that are a part of this packet.
5710 * If the value is zero, then the packet is completely contained
5711 * in the buffer space provided for the packet in the RX ring.
5713 #define RX_PKT_V3_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5714 #define RX_PKT_V3_CMPL_AGG_BUFS_SFT 1
5715 /* unused1 is 1 b */
5716 #define RX_PKT_V3_CMPL_UNUSED1 UINT32_C(0x40)
5718 * This is the RSS hash type for the packet. The value is packed
5719 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5720 * The value of tuple_extrac_op provides the information about
5721 * what fields the hash was computed on.
5722 * Note that 4-tuples values listed below are applicable
5723 * for layer 4 protocols supported and enabled for RSS in the
5724 * hardware, HWRM firmware, and drivers. For example, if RSS hash
5725 * is supported and enabled for TCP traffic only, then the values of
5726 * tuple_extract_op corresponding to 4-tuples are only valid for
5729 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
5730 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_SFT 7
5732 * The RSS hash was computed over source IP address,
5733 * destination IP address, source port, and destination port of
5734 * inner IP and TCP or UDP headers.
5736 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (UINT32_C(0x0) << 7)
5738 * The RSS hash was computed over source IP address and
5739 * destination IP address of inner IP header.
5741 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (UINT32_C(0x1) << 7)
5743 * The RSS hash was computed over source IP address,
5744 * destination IP address, source port, and destination port of
5745 * IP and TCP or UDP headers of outer tunnel headers.
5746 * Note: For non-tunneled packets, this value is not applicable.
5748 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2 (UINT32_C(0x2) << 7)
5750 * The RSS hash was computed over source IP address and
5751 * destination IP address of IP header of outer tunnel headers.
5752 * Note: For non-tunneled packets, this value is not applicable.
5754 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (UINT32_C(0x3) << 7)
5756 * The RSS hash was computed over source IP address of the inner
5759 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (UINT32_C(0x4) << 7)
5761 * The RSS hash was computed over destination IP address of the
5764 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (UINT32_C(0x5) << 7)
5766 * The RSS hash was computed over source IP address of the outer
5768 * Note: For non-tunneled packets, this value is not applicable.
5770 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (UINT32_C(0x6) << 7)
5772 * The RSS hash was computed over destination IP address of the
5774 * Note: For non-tunneled packets, this value is not applicable.
5776 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (UINT32_C(0x7) << 7)
5778 * The RSS hash was computed over source IP address, destination
5779 * IP address, and flow label of the inner IP header.
5780 * Note: For packets without an inner IPv6 header, this value is not
5781 * this value is not applicable.
5783 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (UINT32_C(0x8) << 7)
5785 * The RSS hash was computed over the flow label of the inner
5787 * Note: For packets without an inner IPv6 header, this value
5788 * is not applicable.
5790 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (UINT32_C(0x9) << 7)
5792 * The RSS hash was computed over source IP address, destination
5793 * IP address, and flow label of the outer IP header.
5794 * Note: For packets without an outer IPv6 header, this value is not
5797 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (UINT32_C(0xa) << 7)
5799 * The RSS hash was computed over the flow label of the outer
5801 * Note: For packets without an outer IPv6 header, this value
5802 * is not applicable.
5804 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7)
5805 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST \
5806 RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11
5807 uint16_t metadata1_payload_offset;
5809 * If truncation placement is not used, this value indicates the offset
5810 * in bytes from the beginning of the packet where the inner payload
5811 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets.
5812 * For PTP packets with timestamp (as indicated by the flags_itype
5813 * field), this field contains the 4b sub-nanosecond portion of the
5816 * If truncation placement is used, this value represents the placed
5817 * (truncated) length of the packet.
5819 #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
5820 #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0
5821 /* This is data from the CFA as indicated by the meta_format field. */
5822 #define RX_PKT_V3_CMPL_METADATA1_MASK UINT32_C(0xf000)
5823 #define RX_PKT_V3_CMPL_METADATA1_SFT 12
5824 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5825 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
5826 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_SFT 12
5828 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5829 (UINT32_C(0x0) << 12)
5831 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \
5832 (UINT32_C(0x1) << 12)
5834 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \
5835 (UINT32_C(0x2) << 12)
5837 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \
5838 (UINT32_C(0x3) << 12)
5840 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \
5841 (UINT32_C(0x4) << 12)
5842 /* Value programmed in CFA VLANTPID register. */
5843 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5844 (UINT32_C(0x5) << 12)
5845 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_LAST \
5846 RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG
5847 /* When meta_format != 0, this value is the VLAN valid. */
5848 #define RX_PKT_V3_CMPL_METADATA1_VALID UINT32_C(0x8000)
5850 * This value is the RSS hash value calculated for the packet
5851 * based on the mode bits and key value in the VNIC. When hairpin_en
5852 * is set in VNIC context, this is the lower 32b of the host address
5853 * from the first BD used to place the packet.
5858 /* Last 16 bytes of RX Packet V3 Completion Record */
5859 /* rx_pkt_v3_cmpl_hi (size:128b/16B) */
5860 struct rx_pkt_v3_cmpl_hi {
5863 * This indicates that the ip checksum was calculated for the inner
5864 * packet and that the ip_cs_error field indicates if there was an
5867 #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC \
5870 * This indicates that the TCP, UDP or ICMP checksum was calculated
5871 * for the inner packet and that the l4_cs_error field indicates if
5872 * there was an error.
5874 #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC \
5877 * This indicates that the ip checksum was calculated for the tunnel
5878 * header and that the t_ip_cs_error field indicates if there was an
5881 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC \
5884 * This indicates that the UDP checksum was calculated for the tunnel
5885 * packet and that the t_l4_cs_error field indicates if there was an
5888 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC \
5890 /* This value indicates what format the metadata field is. */
5891 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK \
5893 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
5894 /* There is no metadata information. Values are zero. */
5895 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE \
5896 (UINT32_C(0x0) << 4)
5898 * The {metadata1, metadata0} fields contain the vtag
5899 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5900 * de, vid[11:0]} The metadata2 field contains the table scope
5901 * and action record pointer. - metadata2[25:0] contains the
5902 * action record pointer. - metadata2[31:26] contains the table
5905 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
5906 (UINT32_C(0x1) << 4)
5908 * The {metadata1, metadata0} fields contain the vtag
5910 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5911 * The metadata2 field contains the Tunnel ID
5912 * value, justified to LSB.
5913 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5914 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5915 * - NVGRE = TNI[23:0] -> Tenant Network ID
5916 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5917 * - IPv4 = 0 (not populated)
5918 * - IPv6 = Flow Label[19:0]
5919 * - PPPoE = sessionID[15:0]
5920 * - MPLs = Outer label[19:0]
5921 * - UPAR = Selected[31:0] with bit mask
5923 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
5924 (UINT32_C(0x2) << 4)
5926 * The {metadata1, metadata0} fields contain the vtag
5928 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5929 * The metadata2 field contains the 32b metadata from the prepended
5930 * header (chdr_data).
5932 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
5933 (UINT32_C(0x3) << 4)
5935 * The {metadata1, metadata0} fields contain the vtag
5937 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5938 * The metadata2 field contains the outer_l3_offset,
5939 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5940 * - metadata2[8:0] contains the outer_l3_offset.
5941 * - metadata2[17:9] contains the inner_l2_offset.
5942 * - metadata2[26:18] contains the inner_l3_offset.
5943 * - metadata2[31:27] contains the inner_l4_size.
5945 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
5946 (UINT32_C(0x4) << 4)
5947 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_LAST \
5948 RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
5950 * This field indicates the IP type for the inner-most IP header.
5951 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5952 * This value is only valid if itype indicates a packet
5953 * with an IP header.
5955 #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE \
5958 * This indicates that the complete 1's complement checksum was
5959 * calculated for the packet.
5961 #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
5964 * This field indicates the status of IP and L4 CS calculations done
5965 * by the chip. The format of this field is indicated by the
5966 * cs_all_ok_mode bit.
5968 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE \
5970 /* Indicates that the Tunnel IP type was IPv4 */
5971 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 \
5972 (UINT32_C(0x0) << 10)
5973 /* Indicates that the Tunnel IP type was IPv6 */
5974 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 \
5975 (UINT32_C(0x1) << 10)
5976 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_LAST \
5977 RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6
5979 * This value is the complete 1's complement checksum calculated from
5980 * the start of the outer L3 header to the end of the packet (not
5981 * including the ethernet crc). It is valid when the
5982 * 'complete_checksum_calc' flag is set.
5984 #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5985 UINT32_C(0xffff0000)
5986 #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5988 * This is data from the CFA block as indicated by the meta_format
5990 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5991 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5992 * act_rec_ptr[25:0]}
5993 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5994 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5995 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6000 * This value is written by the NIC such that it will be different
6001 * for each pass through the completion queue. The even passes
6002 * will write 1. The odd passes will write 0.
6004 #define RX_PKT_V3_CMPL_HI_V2 \
6006 #define RX_PKT_V3_CMPL_HI_ERRORS_MASK \
6008 #define RX_PKT_V3_CMPL_HI_ERRORS_SFT 1
6010 * This error indicates that there was some sort of problem with
6011 * the BDs for the packet that was found after part of the
6012 * packet was already placed. The packet should be treated as
6015 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
6017 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
6018 /* No buffer error */
6019 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
6020 (UINT32_C(0x0) << 1)
6022 * Did Not Fit: Packet did not fit into packet buffer provided.
6023 * For regular placement, this means the packet did not fit in
6024 * the buffer provided. For HDS and jumbo placement, this means
6025 * that the packet could not be placed into 8 physical buffers.
6027 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
6028 (UINT32_C(0x1) << 1)
6030 * Not On Chip: All BDs needed for the packet were not on-chip
6031 * when the packet arrived. For regular placement, this error is
6032 * not valid. For HDS and jumbo placement, this means that not
6033 * enough agg BDs were posted to place the packet.
6035 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6036 (UINT32_C(0x2) << 1)
6039 * BDs were not formatted correctly.
6041 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6042 (UINT32_C(0x3) << 1)
6045 * There was a bad_format error on the previous operation
6047 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
6048 (UINT32_C(0x5) << 1)
6049 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
6050 RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
6051 /* This indicates that there was an error in the IP header checksum. */
6052 #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR \
6055 * This indicates that there was an error in the TCP, UDP or ICMP
6058 #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR \
6061 * This indicates that there was an error in the tunnel IP header
6064 #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR \
6066 /* This indicates that there was an error in the tunnel UDP checksum. */
6067 #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR \
6070 * This indicates that there was a CRC error on either an FCoE
6071 * or RoCE packet. The itype indicates the packet type.
6073 #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR \
6076 * This indicates that there was an error in the tunnel portion
6077 * of the packet when this field is non-zero.
6079 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
6081 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
6083 * No additional error occurred on the tunnel portion
6084 * of the packet or the packet does not have a tunnel.
6086 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
6087 (UINT32_C(0x0) << 9)
6089 * Indicates that IP header version does not match expectation
6090 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
6092 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
6093 (UINT32_C(0x1) << 9)
6095 * Indicates that header length is out of range in the tunnel
6096 * header. Valid for IPv4.
6098 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
6099 (UINT32_C(0x2) << 9)
6101 * Indicates that physical packet is shorter than that claimed
6102 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
6105 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
6106 (UINT32_C(0x3) << 9)
6108 * Indicates that the physical packet is shorter than that claimed
6109 * by the tunnel UDP header length for a tunnel UDP packet that is
6112 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
6113 (UINT32_C(0x4) << 9)
6115 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
6116 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6118 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
6119 (UINT32_C(0x5) << 9)
6121 * Indicates that the IP checksum failed its check in the tunnel
6124 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
6125 (UINT32_C(0x6) << 9)
6127 * Indicates that the L4 checksum failed its check in the tunnel
6130 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
6131 (UINT32_C(0x7) << 9)
6132 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
6133 RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
6135 * This indicates that there was an error in the inner
6136 * portion of the packet when this
6137 * field is non-zero.
6139 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK \
6141 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
6143 * No additional error occurred on the tunnel portion
6144 * or the packet of the packet does not have a tunnel.
6146 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
6147 (UINT32_C(0x0) << 12)
6149 * Indicates that IP header version does not match
6150 * expectation from L2 Ethertype for IPv4 and IPv6 or that
6151 * option other than VFT was parsed on
6154 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
6155 (UINT32_C(0x1) << 12)
6157 * indicates that header length is out of range. Valid for
6160 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
6161 (UINT32_C(0x2) << 12)
6163 * indicates that the IPv4 TTL or IPv6 hop limit check
6164 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6166 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
6167 (UINT32_C(0x3) << 12)
6169 * Indicates that physical packet is shorter than that
6170 * claimed by the l3 header length. Valid for IPv4,
6171 * IPv6 packet or RoCE packets.
6173 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
6174 (UINT32_C(0x4) << 12)
6176 * Indicates that the physical packet is shorter than that
6177 * claimed by the UDP header length for a UDP packet that is
6180 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
6181 (UINT32_C(0x5) << 12)
6183 * Indicates that TCP header length > IP payload. Valid for
6186 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
6187 (UINT32_C(0x6) << 12)
6188 /* Indicates that TCP header length < 5. Valid for TCP. */
6189 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
6190 (UINT32_C(0x7) << 12)
6192 * Indicates that TCP option headers result in a TCP header
6193 * size that does not match data offset in TCP header. Valid
6196 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
6197 (UINT32_C(0x8) << 12)
6199 * Indicates that the IP checksum failed its check in the
6202 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
6203 (UINT32_C(0x9) << 12)
6205 * Indicates that the L4 checksum failed its check in the
6208 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
6209 (UINT32_C(0xa) << 12)
6210 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST \
6211 RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
6213 * This is data from the CFA block as indicated by the meta_format
6217 /* When meta_format=1, this value is the VLAN VID. */
6218 #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
6219 #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0
6220 /* When meta_format=1, this value is the VLAN DE. */
6221 #define RX_PKT_V3_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
6222 /* When meta_format=1, this value is the VLAN PRI. */
6223 #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
6224 #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_SFT 13
6226 * The timestamp field contains the 32b timestamp for the packet from
6229 * When hairpin_en is set in VNIC context, this is the upper 32b of the
6230 * host address from the first BD used to place the packet.
6235 /* rx_pkt_compress_cmpl (size:128b/16B) */
6236 struct rx_pkt_compress_cmpl {
6237 uint16_t flags_type;
6239 * This field indicates the exact type of the completion.
6240 * By convention, the LSB identifies the length of the
6241 * record in 16B units. Even values indicate 16B
6242 * records. Odd values indicate 32B
6245 #define RX_PKT_COMPRESS_CMPL_TYPE_MASK UINT32_C(0x3f)
6246 #define RX_PKT_COMPRESS_CMPL_TYPE_SFT 0
6249 * This is the compressed version of Rx Completion for performance
6250 * applications. Length = 16B
6251 * This version of the completion record is used in Thor2 and later
6254 #define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS \
6256 #define RX_PKT_COMPRESS_CMPL_TYPE_LAST \
6257 RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS
6258 #define RX_PKT_COMPRESS_CMPL_FLAGS_MASK \
6260 #define RX_PKT_COMPRESS_CMPL_FLAGS_SFT 6
6262 * When this bit is '1', it indicates a packet that has an
6263 * error of some type. Type of error is indicated in
6266 #define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR \
6269 * This field indicates the status of IP and L4 CS calculations done
6270 * by the chip. The format of this field is indicated by the
6271 * cs_all_ok_mode bit.
6273 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE \
6275 /* Indicates that the Tunnel IP type was IPv4 */
6276 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4 \
6277 (UINT32_C(0x0) << 8)
6278 /* Indicates that the Tunnel IP type was IPv6 */
6279 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 \
6280 (UINT32_C(0x1) << 8)
6281 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_LAST \
6282 RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6
6284 * This field indicates the IP type for the inner-most IP header.
6285 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6286 * This value is only valid if itype indicates a packet
6287 * with an IP header.
6289 #define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE \
6291 /* This bit is '1' if the RSS field in this completion is valid. */
6292 #define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID \
6295 * This value indicates what the inner packet determined for the
6298 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK \
6300 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_SFT 12
6303 * Indicates that the packet type was not known.
6305 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN \
6306 (UINT32_C(0x0) << 12)
6309 * Indicates that the packet was an IP packet, but further
6310 * classification was not possible.
6312 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP \
6313 (UINT32_C(0x1) << 12)
6316 * Indicates that the packet was IP and TCP.
6317 * This indicates that the payload_offset field is valid.
6319 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP \
6320 (UINT32_C(0x2) << 12)
6323 * Indicates that the packet was IP and UDP.
6324 * This indicates that the payload_offset field is valid.
6326 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP \
6327 (UINT32_C(0x3) << 12)
6330 * Indicates that the packet was recognized as a FCoE.
6331 * This also indicates that the payload_offset field is valid.
6333 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE \
6334 (UINT32_C(0x4) << 12)
6337 * Indicates that the packet was recognized as a RoCE.
6338 * This also indicates that the payload_offset field is valid.
6340 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE \
6341 (UINT32_C(0x5) << 12)
6344 * Indicates that the packet was recognized as ICMP.
6345 * This indicates that the payload_offset field is valid.
6347 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP \
6348 (UINT32_C(0x7) << 12)
6350 * PTP packet wo/timestamp:
6351 * Indicates that the packet was recognized as a PTP
6354 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
6355 (UINT32_C(0x8) << 12)
6357 * PTP packet w/timestamp:
6358 * Indicates that the packet was recognized as a PTP
6359 * packet and that a timestamp was taken for the packet.
6360 * The 4b sub-nanosecond portion of the timestamp is in
6361 * the payload_offset field.
6363 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
6364 (UINT32_C(0x9) << 12)
6365 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_LAST \
6366 RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
6368 * This is the length of the data for the packet stored in the
6369 * buffer(s) identified by the opaque value. This includes
6370 * the packet BD and any associated buffer BDs. This does not include
6371 * the length of any data places in aggregation BDs.
6375 * This value is the RSS hash value calculated for the packet
6376 * based on the mode bits and key value in the VNIC. When hairpin_en
6377 * is set in VNIC context, this is the lower 32b of the host address
6378 * from the first BD used to place the packet.
6381 uint16_t metadata1_cs_error_calc_v1;
6383 * This value is written by the NIC such that it will be different
6384 * for each pass through the completion queue. The even passes
6385 * will write 1. The odd passes will write 0.
6387 #define RX_PKT_COMPRESS_CMPL_V1 \
6390 #define RX_PKT_COMPRESS_CMPL_UNUSED_MASK \
6392 #define RX_PKT_COMPRESS_CMPL_UNUSED_SFT 1
6393 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK \
6395 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_SFT 4
6396 /* This indicates that there was an error in the IP header checksum. */
6397 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR \
6400 * This indicates that there was an error in the TCP, UDP or ICMP
6403 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR \
6406 * This indicates that there was an error in the tunnel IP header
6409 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR \
6411 /* This indicates that there was an error in the tunnel UDP checksum. */
6412 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR \
6415 * This indicates that the ip checksum was calculated for the inner
6416 * packet and that the ip_cs_error field indicates if there was an
6419 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC \
6422 * This indicates that the TCP, UDP or ICMP checksum was calculated
6423 * for the inner packet and that the l4_cs_error field indicates if
6424 * there was an error.
6426 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC \
6429 * This indicates that the ip checksum was calculated for the tunnel
6430 * header and that the t_ip_cs_error field indicates if there was an
6433 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC \
6436 * This indicates that the UDP checksum was calculated for the tunnel
6437 * packet and that the t_l4_cs_error field indicates if there was an
6440 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC \
6442 /* This is data from the CFA as indicated by the meta_format field. */
6443 #define RX_PKT_COMPRESS_CMPL_METADATA1_MASK \
6445 #define RX_PKT_COMPRESS_CMPL_METADATA1_SFT 12
6446 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
6447 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK \
6449 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_SFT 12
6451 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8 \
6452 (UINT32_C(0x0) << 12)
6454 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100 \
6455 (UINT32_C(0x1) << 12)
6457 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100 \
6458 (UINT32_C(0x2) << 12)
6460 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200 \
6461 (UINT32_C(0x3) << 12)
6463 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300 \
6464 (UINT32_C(0x4) << 12)
6465 /* Value programmed in CFA VLANTPID register. */
6466 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG \
6467 (UINT32_C(0x5) << 12)
6468 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_LAST \
6469 RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG
6470 /* When meta_format != 0, this value is the VLAN valid. */
6471 #define RX_PKT_COMPRESS_CMPL_METADATA1_VALID \
6473 /* This is data from the CFA as indicated by the meta_format field. */
6474 uint16_t vlanc_tcid;
6475 /* When meta_format!=0, this value is the VLAN VID. */
6476 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff)
6477 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_SFT 0
6478 /* When meta_format!=0, this value is the VLAN DE. */
6479 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE UINT32_C(0x1000)
6480 /* When meta_format!=0, this value is the VLAN PRI. */
6481 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000)
6482 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_SFT 13
6483 uint32_t errors_agg_bufs_opaque;
6484 /* Lower 16bits of the Opaque field provided in the Rx BD. */
6485 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK \
6487 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_SFT \
6490 * This value is the number of aggregation buffers that follow this
6491 * entry in the completion ring that are a part of this packet.
6492 * If the value is zero, then the packet is completely contained
6493 * in the buffer space provided for the packet in the RX ring.
6495 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK \
6497 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_SFT \
6499 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK \
6500 UINT32_C(0x1fe00000)
6501 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_SFT \
6504 * This indicates that there was an error in the inner
6505 * portion of the packet when this
6506 * field is non-zero.
6508 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK \
6510 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_SFT \
6513 * No additional error occurred on the tunnel portion
6514 * or the packet of the packet does not have a tunnel.
6516 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR \
6517 (UINT32_C(0x0) << 21)
6519 * Indicates that IP header version does not match
6520 * expectation from L2 Ethertype for IPv4 and IPv6 or that
6521 * option other than VFT was parsed on
6524 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION \
6525 (UINT32_C(0x1) << 21)
6527 * indicates that header length is out of range. Valid for
6530 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
6531 (UINT32_C(0x2) << 21)
6533 * indicates that the IPv4 TTL or IPv6 hop limit check
6534 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6536 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL \
6537 (UINT32_C(0x3) << 21)
6539 * Indicates that physical packet is shorter than that
6540 * claimed by the l3 header length. Valid for IPv4,
6541 * IPv6 packet or RoCE packets.
6543 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
6544 (UINT32_C(0x4) << 21)
6546 * Indicates that the physical packet is shorter than that
6547 * claimed by the UDP header length for a UDP packet that is
6550 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
6551 (UINT32_C(0x5) << 21)
6553 * Indicates that TCP header length > IP payload. Valid for
6556 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
6557 (UINT32_C(0x6) << 21)
6558 /* Indicates that TCP header length < 5. Valid for TCP. */
6559 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
6560 (UINT32_C(0x7) << 21)
6562 * Indicates that TCP option headers result in a TCP header
6563 * size that does not match data offset in TCP header. Valid
6566 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
6567 (UINT32_C(0x8) << 21)
6568 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_LAST \
6569 RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
6571 * This indicates that there was an error in the tunnel portion
6572 * of the packet when this field is non-zero.
6574 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK \
6576 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_SFT \
6579 * No additional error occurred on the tunnel portion
6580 * of the packet or the packet does not have a tunnel.
6582 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR \
6583 (UINT32_C(0x0) << 25)
6585 * Indicates that IP header version does not match expectation
6586 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
6588 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
6589 (UINT32_C(0x1) << 25)
6591 * Indicates that header length is out of range in the tunnel
6592 * header. Valid for IPv4.
6594 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
6595 (UINT32_C(0x2) << 25)
6597 * Indicates that physical packet is shorter than that claimed
6598 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
6601 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
6602 (UINT32_C(0x3) << 25)
6604 * Indicates that the physical packet is shorter than that claimed
6605 * by the tunnel UDP header length for a tunnel UDP packet that is
6608 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
6609 (UINT32_C(0x4) << 25)
6611 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
6612 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6614 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
6615 (UINT32_C(0x5) << 25)
6617 * Indicates that the IP checksum failed its check in the tunnel
6620 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
6621 (UINT32_C(0x6) << 25)
6623 * Indicates that the L4 checksum failed its check in the tunnel
6626 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
6627 (UINT32_C(0x7) << 25)
6628 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_LAST \
6629 RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
6631 * This indicates that there was a CRC error on either an FCoE
6632 * or RoCE packet. The itype indicates the packet type.
6634 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR \
6635 UINT32_C(0x10000000)
6636 /* unused1 is 3 b */
6637 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK \
6638 UINT32_C(0xe0000000)
6639 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_SFT \
6644 * This TPA completion structure is used on devices where the
6645 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6647 /* rx_tpa_start_cmpl (size:128b/16B) */
6648 struct rx_tpa_start_cmpl {
6649 uint16_t flags_type;
6651 * This field indicates the exact type of the completion.
6652 * By convention, the LSB identifies the length of the
6653 * record in 16B units. Even values indicate 16B
6654 * records. Odd values indicate 32B
6657 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
6658 #define RX_TPA_START_CMPL_TYPE_SFT 0
6660 * RX L2 TPA Start Completion:
6661 * Completion at the beginning of a TPA operation.
6664 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
6665 #define RX_TPA_START_CMPL_TYPE_LAST \
6666 RX_TPA_START_CMPL_TYPE_RX_TPA_START
6667 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6668 #define RX_TPA_START_CMPL_FLAGS_SFT 6
6669 /* This bit will always be '0' for TPA start completions. */
6670 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
6671 /* This field indicates how the packet was placed in the buffer. */
6672 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6673 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
6676 * TPA Packet was placed using jumbo algorithm. This means
6677 * that the first buffer will be filled with data before
6678 * moving to aggregation buffers. Each aggregation buffer
6679 * will be filled before moving to the next aggregation
6682 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6683 (UINT32_C(0x1) << 7)
6685 * Header/Data Separation:
6686 * Packet was placed using Header/Data separation algorithm.
6687 * The separation location is indicated by the itype field.
6689 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
6690 (UINT32_C(0x2) << 7)
6693 * Packet will be placed using GRO/Jumbo where the first
6694 * packet is filled with data. Subsequent packets will be
6695 * placed such that any one packet does not span two
6696 * aggregation buffers unless it starts at the beginning of
6697 * an aggregation buffer.
6699 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6700 (UINT32_C(0x5) << 7)
6702 * GRO/Header-Data Separation:
6703 * Packet will be placed using GRO/HDS where the header
6704 * is in the first packet.
6705 * Payload of each packet will be
6706 * placed such that any one packet does not span two
6707 * aggregation buffers unless it starts at the beginning of
6708 * an aggregation buffer.
6710 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6711 (UINT32_C(0x6) << 7)
6712 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
6713 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6714 /* This bit is '1' if the RSS field in this completion is valid. */
6715 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
6717 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
6719 * This value indicates what the inner packet determined for the
6722 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
6723 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
6726 * Indicates that the packet was IP and TCP.
6728 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
6729 (UINT32_C(0x2) << 12)
6730 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
6731 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
6733 * This value indicates the amount of packet data written to the
6734 * buffer the opaque field in this completion corresponds to.
6738 * This is a copy of the opaque field from the RX BD this completion
6743 * This value is written by the NIC such that it will be different
6744 * for each pass through the completion queue. The even passes
6745 * will write 1. The odd passes will write 0.
6749 * This value is written by the NIC such that it will be different
6750 * for each pass through the completion queue. The even passes
6751 * will write 1. The odd passes will write 0.
6753 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
6754 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
6756 * This is the RSS hash type for the packet. The value is packed
6757 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6759 * The value of tuple_extrac_op provides the information about
6760 * what fields the hash was computed on.
6761 * * 0: The RSS hash was computed over source IP address,
6762 * destination IP address, source port, and destination port of inner
6763 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6764 * the packet headers are considered inner packet headers for the RSS
6765 * hash computation purpose.
6766 * * 1: The RSS hash was computed over source IP address and destination
6767 * IP address of inner IP header. Note: For non-tunneled packets,
6768 * the packet headers are considered inner packet headers for the RSS
6769 * hash computation purpose.
6770 * * 2: The RSS hash was computed over source IP address,
6771 * destination IP address, source port, and destination port of
6772 * IP and TCP or UDP headers of outer tunnel headers.
6773 * Note: For non-tunneled packets, this value is not applicable.
6774 * * 3: The RSS hash was computed over source IP address and
6775 * destination IP address of IP header of outer tunnel headers.
6776 * Note: For non-tunneled packets, this value is not applicable.
6778 * Note that 4-tuples values listed above are applicable
6779 * for layer 4 protocols supported and enabled for RSS in the hardware,
6780 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6781 * enabled for TCP traffic only, then the values of tuple_extract_op
6782 * corresponding to 4-tuples are only valid for TCP traffic.
6784 uint8_t rss_hash_type;
6786 * This is the aggregation ID that the completion is associated
6787 * with. Use this number to correlate the TPA start completion
6788 * with the TPA end completion.
6791 /* unused2 is 9 b */
6792 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
6793 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
6795 * This is the aggregation ID that the completion is associated
6796 * with. Use this number to correlate the TPA start completion
6797 * with the TPA end completion.
6799 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
6800 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
6802 * This value is the RSS hash value calculated for the packet
6803 * based on the mode bits and key value in the VNIC.
6809 * Last 16 bytes of rx_tpa_start_cmpl.
6811 * This TPA completion structure is used on devices where the
6812 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6814 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
6815 struct rx_tpa_start_cmpl_hi {
6818 * This indicates that the ip checksum was calculated for the
6819 * inner packet and that the sum passed for all segments
6820 * included in the aggregation.
6822 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
6824 * This indicates that the TCP, UDP or ICMP checksum was
6825 * calculated for the inner packet and that the sum passed
6826 * for all segments included in the aggregation.
6828 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
6830 * This indicates that the ip checksum was calculated for the
6831 * tunnel header and that the sum passed for all segments
6832 * included in the aggregation.
6834 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
6836 * This indicates that the UDP checksum was
6837 * calculated for the tunnel packet and that the sum passed for
6838 * all segments included in the aggregation.
6840 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
6841 /* This value indicates what format the metadata field is. */
6842 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
6843 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6844 /* No metadata information. Value is zero. */
6845 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
6846 (UINT32_C(0x0) << 4)
6848 * The metadata field contains the VLAN tag and TPID value.
6849 * - metadata[11:0] contains the vlan VID value.
6850 * - metadata[12] contains the vlan DE value.
6851 * - metadata[15:13] contains the vlan PRI value.
6852 * - metadata[31:16] contains the vlan TPID value.
6854 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6855 (UINT32_C(0x1) << 4)
6856 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
6857 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
6859 * This field indicates the IP type for the inner-most IP header.
6860 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6862 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
6864 * This is data from the CFA block as indicated by the meta_format
6868 /* When meta_format=1, this value is the VLAN VID. */
6869 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6870 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
6871 /* When meta_format=1, this value is the VLAN DE. */
6872 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
6873 /* When meta_format=1, this value is the VLAN PRI. */
6874 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6875 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
6876 /* When meta_format=1, this value is the VLAN TPID. */
6877 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6878 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
6881 * This value is written by the NIC such that it will be different
6882 * for each pass through the completion queue. The even passes
6883 * will write 1. The odd passes will write 0.
6885 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
6887 * This field identifies the CFA action rule that was used for this
6892 * This is the size in bytes of the inner most L4 header.
6893 * This can be subtracted from the payload_offset to determine
6894 * the start of the inner most L4 header.
6896 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6898 * This is the offset from the beginning of the packet in bytes for
6899 * the outer L3 header. If there is no outer L3 header, then this
6902 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6903 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
6905 * This is the offset from the beginning of the packet in bytes for
6906 * the inner most L2 header.
6908 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6909 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
6911 * This is the offset from the beginning of the packet in bytes for
6912 * the inner most L3 header.
6914 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6915 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
6917 * This is the size in bytes of the inner most L4 header.
6918 * This can be subtracted from the payload_offset to determine
6919 * the start of the inner most L4 header.
6921 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6922 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
6926 * This TPA completion structure is used on devices where the
6927 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6928 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
6931 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
6932 struct rx_tpa_start_v2_cmpl {
6933 uint16_t flags_type;
6935 * This field indicates the exact type of the completion.
6936 * By convention, the LSB identifies the length of the
6937 * record in 16B units. Even values indicate 16B
6938 * records. Odd values indicate 32B
6941 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
6943 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
6945 * RX L2 TPA Start V2 Completion:
6946 * Completion at the beginning of a TPA operation.
6948 * This is the new version of the RX_TPA_START completion used
6949 * in SR2 and later chips.
6951 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
6953 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
6954 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
6955 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
6957 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
6959 * When this bit is '1', it indicates a packet that has an error
6960 * of some type. Type of error is indicated in error_flags.
6962 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
6964 /* This field indicates how the packet was placed in the buffer. */
6965 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
6967 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
6970 * TPA Packet was placed using jumbo algorithm. This means
6971 * that the first buffer will be filled with data before
6972 * moving to aggregation buffers. Each aggregation buffer
6973 * will be filled before moving to the next aggregation
6976 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
6977 (UINT32_C(0x1) << 7)
6979 * Header/Data Separation:
6980 * Packet was placed using Header/Data separation algorithm.
6981 * The separation location is indicated by the itype field.
6983 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
6984 (UINT32_C(0x2) << 7)
6987 * Packet will be placed using In-Order Completion/Jumbo where
6988 * the first packet of the aggregation is placed using Jumbo
6989 * Placement. Subsequent packets will be placed such that each
6990 * packet starts at the beginning of an aggregation buffer.
6992 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6993 (UINT32_C(0x4) << 7)
6996 * Packet will be placed using GRO/Jumbo where the first
6997 * packet is filled with data. Subsequent packets will be
6998 * placed such that any one packet does not span two
6999 * aggregation buffers unless it starts at the beginning of
7000 * an aggregation buffer.
7002 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
7003 (UINT32_C(0x5) << 7)
7005 * GRO/Header-Data Separation:
7006 * Packet will be placed using GRO/HDS where the header
7007 * is in the first packet.
7008 * Payload of each packet will be
7009 * placed such that any one packet does not span two
7010 * aggregation buffers unless it starts at the beginning of
7011 * an aggregation buffer.
7013 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
7014 (UINT32_C(0x6) << 7)
7016 * IOC/Header-Data Separation:
7017 * Packet will be placed using In-Order Completion/HDS where
7018 * the header is in the first packet buffer. Payload of each
7019 * packet will be placed such that each packet starts at the
7020 * beginning of an aggregation buffer.
7022 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
7023 (UINT32_C(0x7) << 7)
7024 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
7025 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
7026 /* This bit is '1' if the RSS field in this completion is valid. */
7027 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
7030 * This bit is '1' if metadata has been added to the end of the
7031 * packet in host memory. Metadata starts at the first 32B boundary
7032 * after the end of the packet for regular and jumbo placement. It
7033 * starts at the first 32B boundary after the end of the header for
7034 * HDS placement. The length of the metadata is indicated in the
7037 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
7040 * This value indicates what the inner packet determined for the
7043 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
7045 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
7048 * Indicates that the packet was IP and TCP.
7050 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
7051 (UINT32_C(0x2) << 12)
7052 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
7053 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
7055 * This value indicates the amount of packet data written to the
7056 * buffer the opaque field in this completion corresponds to.
7060 * This is a copy of the opaque field from the RX BD this completion
7061 * corresponds to. If the VNIC is configured to not use an Rx BD for
7062 * the TPA Start completion, then this is a copy of the opaque field
7063 * from the first BD used to place the TPA Start packet.
7067 * This value is written by the NIC such that it will be different
7068 * for each pass through the completion queue. The even passes
7069 * will write 1. The odd passes will write 0.
7073 * This value is written by the NIC such that it will be different
7074 * for each pass through the completion queue. The even passes
7075 * will write 1. The odd passes will write 0.
7077 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
7078 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
7080 * This is the RSS hash type for the packet. The value is packed
7081 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7083 * The value of tuple_extrac_op provides the information about
7084 * what fields the hash was computed on.
7085 * * 0: The RSS hash was computed over source IP address,
7086 * destination IP address, source port, and destination port of inner
7087 * IP and TCP or UDP headers. Note: For non-tunneled packets,
7088 * the packet headers are considered inner packet headers for the RSS
7089 * hash computation purpose.
7090 * * 1: The RSS hash was computed over source IP address and destination
7091 * IP address of inner IP header. Note: For non-tunneled packets,
7092 * the packet headers are considered inner packet headers for the RSS
7093 * hash computation purpose.
7094 * * 2: The RSS hash was computed over source IP address,
7095 * destination IP address, source port, and destination port of
7096 * IP and TCP or UDP headers of outer tunnel headers.
7097 * Note: For non-tunneled packets, this value is not applicable.
7098 * * 3: The RSS hash was computed over source IP address and
7099 * destination IP address of IP header of outer tunnel headers.
7100 * Note: For non-tunneled packets, this value is not applicable.
7102 * Note that 4-tuples values listed above are applicable
7103 * for layer 4 protocols supported and enabled for RSS in the hardware,
7104 * HWRM firmware, and drivers. For example, if RSS hash is supported and
7105 * enabled for TCP traffic only, then the values of tuple_extract_op
7106 * corresponding to 4-tuples are only valid for TCP traffic.
7108 uint8_t rss_hash_type;
7110 * This is the aggregation ID that the completion is associated
7111 * with. Use this number to correlate the TPA start completion
7112 * with the TPA end completion.
7116 * This is the aggregation ID that the completion is associated
7117 * with. Use this number to correlate the TPA start completion
7118 * with the TPA end completion.
7120 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
7121 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
7122 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
7124 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
7125 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
7126 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
7128 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
7130 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
7131 (UINT32_C(0x0) << 12)
7133 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
7134 (UINT32_C(0x1) << 12)
7136 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
7137 (UINT32_C(0x2) << 12)
7139 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
7140 (UINT32_C(0x3) << 12)
7142 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
7143 (UINT32_C(0x4) << 12)
7144 /* Value programmed in CFA VLANTPID register. */
7145 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
7146 (UINT32_C(0x5) << 12)
7147 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
7148 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
7149 /* When meta_format != 0, this value is the VLAN valid. */
7150 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
7153 * This value is the RSS hash value calculated for the packet
7154 * based on the mode bits and key value in the VNIC.
7155 * When vee_cmpl_mode is set in VNIC context, this is the lower
7156 * 32b of the host address from the first BD used to place the packet.
7162 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
7164 * This TPA completion structure is used on devices where the
7165 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7167 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
7168 struct rx_tpa_start_v2_cmpl_hi {
7170 /* This indicates that the aggregation was done using GRO rules. */
7171 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
7174 * When this bit is '0', the cs_ok field has the following definition:-
7175 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
7176 * in the delivered packet, counted from the outer-most header group to
7177 * the inner-most header group, stopping at the first error. -
7178 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
7179 * in the delivered packet, counted from the outer-most header group to
7180 * the inner-most header group, stopping at the first error. When this
7181 * bit is '1', the cs_ok field has the following definition: -
7182 * hdr_cnt[2:0] = The number of header groups that were parsed by the
7183 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
7184 * will be '1' if all the parsed header groups with an IP checksum are
7185 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
7186 * header groups with an L4 checksum are valid.
7188 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
7190 /* This value indicates what format the metadata field is. */
7191 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
7193 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
7194 /* There is no metadata information. Values are zero. */
7195 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
7196 (UINT32_C(0x0) << 4)
7198 * The {metadata1, metadata0} fields contain the vtag
7199 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
7200 * de, vid[11:0]} The metadata2 field contains the table scope
7201 * and action record pointer. - metadata2[25:0] contains the
7202 * action record pointer. - metadata2[31:26] contains the table
7205 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
7206 (UINT32_C(0x1) << 4)
7208 * The {metadata1, metadata0} fields contain the vtag
7210 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7211 * The metadata2 field contains the Tunnel ID
7212 * value, justified to LSB.
7213 * - VXLAN = VNI[23:0] -> VXLAN Network ID
7214 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
7215 * - NVGRE = TNI[23:0] -> Tenant Network ID
7216 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
7217 * - IPv4 = 0 (not populated)
7218 * - IPv6 = Flow Label[19:0]
7219 * - PPPoE = sessionID[15:0]
7220 * - MPLs = Outer label[19:0]
7221 * - UPAR = Selected[31:0] with bit mask
7223 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
7224 (UINT32_C(0x2) << 4)
7226 * The {metadata1, metadata0} fields contain the vtag
7228 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
7229 * The metadata2 field contains the 32b metadata from the prepended
7230 * header (chdr_data).
7232 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
7233 (UINT32_C(0x3) << 4)
7235 * The {metadata1, metadata0} fields contain the vtag
7237 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7238 * The metadata2 field contains the outer_l3_offset,
7239 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
7240 * - metadata2[8:0] contains the outer_l3_offset.
7241 * - metadata2[17:9] contains the inner_l2_offset.
7242 * - metadata2[26:18] contains the inner_l3_offset.
7243 * - metadata2[31:27] contains the inner_l4_size.
7245 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
7246 (UINT32_C(0x4) << 4)
7247 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
7248 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
7250 * This field indicates the IP type for the inner-most IP header.
7251 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7252 * This value is only valid if itype indicates a packet
7253 * with an IP header.
7255 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
7258 * This indicates that the complete 1's complement checksum was
7259 * calculated for the packet in the affregation.
7261 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
7264 * This field indicates the status of IP and L4 CS calculations done
7265 * by the chip. The format of this field is indicated by the
7266 * cs_all_ok_mode bit.
7267 * CS status for TPA packets is always valid. This means that "all_ok"
7268 * status will always be set. The ok count status will be set
7269 * appropriately for the packet header, such that all existing CS
7272 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
7274 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
7276 * This value is the complete 1's complement checksum calculated from
7277 * the start of the outer L3 header to the end of the packet (not
7278 * including the ethernet crc). It is valid when the
7279 * 'complete_checksum_calc' flag is set. For TPA Start completions,
7280 * the complete checksum is calculated for the first packet in the
7283 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
7284 UINT32_C(0xffff0000)
7285 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
7287 * This is data from the CFA block as indicated by the meta_format
7289 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
7290 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
7291 * act_rec_ptr[25:0]}
7292 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
7293 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
7294 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
7295 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
7296 * of the host address from the first BD used to place the packet.
7301 * This value is written by the NIC such that it will be different
7302 * for each pass through the completion queue. The even passes
7303 * will write 1. The odd passes will write 0.
7305 #define RX_TPA_START_V2_CMPL_V2 \
7307 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
7309 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
7311 * This error indicates that there was some sort of problem with
7312 * the BDs for the packetThe packet should be treated as
7315 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
7317 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7318 /* No buffer error */
7319 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7320 (UINT32_C(0x0) << 1)
7323 * Packet did not fit into packet buffer provided. This means
7324 * that the TPA Start packet was too big to be placed into the
7325 * per-packet maximum number of physical buffers configured for
7326 * the VNIC, or that it was too big to be placed into the
7327 * per-aggregation maximum number of physical buffers configured
7328 * for the VNIC. This error only occurs when the VNIC is
7329 * configured for variable size receive buffers.
7331 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7332 (UINT32_C(0x1) << 1)
7335 * BDs were not formatted correctly.
7337 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7338 (UINT32_C(0x3) << 1)
7341 * There was a bad_format error on the previous operation
7343 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7344 (UINT32_C(0x5) << 1)
7345 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
7346 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7348 * This is data from the CFA block as indicated by the meta_format
7352 /* When meta_format != 0, this value is the VLAN VID. */
7353 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
7354 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
7355 /* When meta_format != 0, this value is the VLAN DE. */
7356 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
7357 /* When meta_format != 0, this value is the VLAN PRI. */
7358 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
7359 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
7361 * This field contains the outer_l3_offset, inner_l2_offset,
7362 * inner_l3_offset, and inner_l4_size.
7364 * hdr_offsets[8:0] contains the outer_l3_offset.
7365 * hdr_offsets[17:9] contains the inner_l2_offset.
7366 * hdr_offsets[26:18] contains the inner_l3_offset.
7367 * hdr_offsets[31:27] contains the inner_l4_size.
7369 uint32_t hdr_offsets;
7373 * This TPA completion structure is used on devices where the
7374 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7375 * RX L2 TPA Start V3 Completion Record (32 bytes split to 2 16-byte
7378 /* rx_tpa_start_v3_cmpl (size:128b/16B) */
7379 struct rx_tpa_start_v3_cmpl {
7380 uint16_t flags_type;
7382 * This field indicates the exact type of the completion.
7383 * By convention, the LSB identifies the length of the
7384 * record in 16B units. Even values indicate 16B
7385 * records. Odd values indicate 32B
7388 #define RX_TPA_START_V3_CMPL_TYPE_MASK \
7390 #define RX_TPA_START_V3_CMPL_TYPE_SFT 0
7392 * RX L2 TPA Start V3 completion:
7393 * Completion at the beginning of a TPA operation.
7395 * This is the new version of the RX_TPA_START completion used
7396 * in Thor2 and later chips.
7398 #define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 \
7400 #define RX_TPA_START_V3_CMPL_TYPE_LAST \
7401 RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3
7402 #define RX_TPA_START_V3_CMPL_FLAGS_MASK \
7404 #define RX_TPA_START_V3_CMPL_FLAGS_SFT 6
7406 * When this bit is '1', it indicates a packet that has an error
7407 * of some type. Type of error is indicated in error_flags.
7409 #define RX_TPA_START_V3_CMPL_FLAGS_ERROR \
7411 /* This field indicates how the packet was placed in the buffer. */
7412 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK \
7414 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_SFT 7
7417 * TPA Packet was placed using jumbo algorithm. This means
7418 * that the first buffer will be filled with data before
7419 * moving to aggregation buffers. Each aggregation buffer
7420 * will be filled before moving to the next aggregation
7423 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO \
7424 (UINT32_C(0x1) << 7)
7426 * Header/Data Separation:
7427 * Packet was placed using Header/Data separation algorithm.
7428 * The separation location is indicated by the itype field.
7430 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS \
7431 (UINT32_C(0x2) << 7)
7434 * Packet will be placed using In-Order Completion/Jumbo where
7435 * the first packet of the aggregation is placed using Jumbo
7436 * Placement. Subsequent packets will be placed such that each
7437 * packet starts at the beginning of an aggregation buffer.
7439 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
7440 (UINT32_C(0x4) << 7)
7443 * Packet will be placed using GRO/Jumbo where the first
7444 * packet is filled with data. Subsequent packets will be
7445 * placed such that any one packet does not span two
7446 * aggregation buffers unless it starts at the beginning of
7447 * an aggregation buffer.
7449 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
7450 (UINT32_C(0x5) << 7)
7452 * GRO/Header-Data Separation:
7453 * Packet will be placed using GRO/HDS where the header
7454 * is in the first packet.
7455 * Payload of each packet will be
7456 * placed such that any one packet does not span two
7457 * aggregation buffers unless it starts at the beginning of
7458 * an aggregation buffer.
7460 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS \
7461 (UINT32_C(0x6) << 7)
7463 * IOC/Header-Data Separation:
7464 * Packet will be placed using In-Order Completion/HDS where
7465 * the header is in the first packet buffer. Payload of each
7466 * packet will be placed such that each packet starts at the
7467 * beginning of an aggregation buffer.
7469 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS \
7470 (UINT32_C(0x7) << 7)
7471 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_LAST \
7472 RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS
7473 /* This bit is '1' if the RSS field in this completion is valid. */
7474 #define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID \
7477 * This bit is '1' if metadata has been added to the end of the
7478 * packet in host memory. Metadata starts at the first 32B boundary
7479 * after the end of the packet for regular and jumbo placement. It
7480 * starts at the first 32B boundary after the end of the header for
7481 * HDS placement. The length of the metadata is indicated in the
7484 #define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT \
7487 * This value indicates what the inner packet determined for the
7490 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK \
7492 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_SFT 12
7495 * Indicates that the packet was IP and TCP.
7497 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP \
7498 (UINT32_C(0x2) << 12)
7499 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_LAST \
7500 RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP
7502 * This value indicates the amount of packet data written to the
7503 * buffer the opaque field in this completion corresponds to.
7507 * This is a copy of the opaque field from the RX BD this completion
7508 * corresponds to. If the VNIC is configured to not use an Rx BD for
7509 * the TPA Start completion, then this is a copy of the opaque field
7510 * from the first BD used to place the TPA Start packet.
7513 uint16_t rss_hash_type_v1;
7515 * This value is written by the NIC such that it will be different
7516 * for each pass through the completion queue. The even passes
7517 * will write 1. The odd passes will write 0.
7519 #define RX_TPA_START_V3_CMPL_V1 UINT32_C(0x1)
7520 /* unused1 is 6 b. */
7521 #define RX_TPA_START_V3_CMPL_UNUSED1_MASK UINT32_C(0x7e)
7522 #define RX_TPA_START_V3_CMPL_UNUSED1_SFT 1
7524 * This is the RSS hash type for the packet. The value is packed
7525 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7527 * The value of tuple_extrac_op provides the information about
7528 * what fields the hash was computed on.
7529 * * 0: The RSS hash was computed over source IP address,
7530 * destination IP address, source port, and destination port of inner
7531 * IP and TCP or UDP headers.
7532 * * 1: The RSS hash was computed over source IP address and
7533 * destination IP address of inner IP header.
7534 * * 2: The RSS hash was computed over source IP address,
7535 * destination IP address, source port, and destination port of
7536 * IP and TCP or UDP headers of outer tunnel headers.
7537 * Note: For non-tunneled packets, this value is not applicable.
7538 * * 3: The RSS hash was computed over source IP address and
7539 * destination IP address of IP header of outer tunnel headers.
7540 * Note: For non-tunneled packets, this value is not applicable.
7541 * * 4: The RSS hash was computed over source IP address of the inner
7543 * * 5: The RSS hash was computed over destination IP address of the
7545 * * 6: The RSS hash was computed over source IP address of the outer
7546 * IP header. Note: For non-tunneled packets, this value is not
7548 * * 7: The RSS hash was computed over destination IP address of the
7550 * Note: For non-tunneled packets, this value is not applicable.
7551 * * 8: The RSS hash was computed over source IP address, destination
7552 * IP address, and flow label of the inner IP header.
7553 * Note: For packets without an inner IPv6 header, this value is not
7555 * * 9: The RSS hash was computed over the flow label of the inner
7557 * Note: For packets without an inner IPv6 header, this value
7558 * is not applicable.
7559 * * 10: The RSS hash was computed over source IP address, destination
7560 * IP address, and flow label of the outer IP header.
7561 * Note: For packets without an outer IPv6 header, this value is not
7563 * * 11: The RSS hash was computed over the flow label of the outer
7564 * IP header. Note: For packets without an outer IPv6 header, this
7565 * value is not applicable.
7567 * Note that 4-tuples values listed above are applicable
7568 * for layer 4 protocols supported and enabled for RSS in the hardware,
7569 * HWRM firmware, and drivers. For example, if RSS hash is supported
7570 * and enabled for TCP traffic only, then the values of
7571 * tuple_extract_op corresponding to 4-tuples are only valid for TCP
7574 #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
7575 #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_SFT 7
7577 * This is the aggregation ID that the completion is associated
7578 * with. Use this number to correlate the TPA start completion
7579 * with the TPA end completion.
7583 * This is the aggregation ID that the completion is associated
7584 * with. Use this number to correlate the TPA start completion
7585 * with the TPA end completion.
7587 #define RX_TPA_START_V3_CMPL_AGG_ID_MASK UINT32_C(0xfff)
7588 #define RX_TPA_START_V3_CMPL_AGG_ID_SFT 0
7589 #define RX_TPA_START_V3_CMPL_METADATA1_MASK \
7591 #define RX_TPA_START_V3_CMPL_METADATA1_SFT 12
7592 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
7593 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK \
7595 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_SFT 12
7597 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \
7598 (UINT32_C(0x0) << 12)
7600 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \
7601 (UINT32_C(0x1) << 12)
7603 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \
7604 (UINT32_C(0x2) << 12)
7606 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \
7607 (UINT32_C(0x3) << 12)
7609 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \
7610 (UINT32_C(0x4) << 12)
7611 /* Value programmed in CFA VLANTPID register. */
7612 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \
7613 (UINT32_C(0x5) << 12)
7614 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_LAST \
7615 RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG
7616 /* When meta_format != 0, this value is the VLAN valid. */
7617 #define RX_TPA_START_V3_CMPL_METADATA1_VALID \
7620 * This value is the RSS hash value calculated for the packet
7621 * based on the mode bits and key value in the VNIC.
7622 * When vee_cmpl_mode is set in VNIC context, this is the lower
7623 * 32b of the host address from the first BD used to place the packet.
7629 * Last 16 bytes of RX L2 TPA Start V3 Completion Record
7631 * This TPA completion structure is used on devices where the
7632 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7634 /* rx_tpa_start_v3_cmpl_hi (size:128b/16B) */
7635 struct rx_tpa_start_v3_cmpl_hi {
7638 * This indicates that the ip checksum was calculated for the inner
7639 * packet and that the ip_cs_error field indicates if there was an
7642 #define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC \
7645 * This indicates that the TCP, UDP or ICMP checksum was calculated
7646 * for the inner packet and that the l4_cs_error field indicates if
7647 * there was an error.
7649 #define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC \
7652 * This indicates that the ip checksum was calculated for the tunnel
7653 * header and that the t_ip_cs_error field indicates if there was an
7656 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC \
7659 * This indicates that the UDP checksum was calculated for the tunnel
7660 * packet and that the t_l4_cs_error field indicates if there was an
7663 #define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC \
7665 /* This value indicates what format the metadata field is. */
7666 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK \
7668 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_SFT 4
7669 /* There is no metadata information. Values are zero. */
7670 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE \
7671 (UINT32_C(0x0) << 4)
7673 * The {metadata1, metadata0} fields contain the vtag
7674 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
7675 * de, vid[11:0]} The metadata2 field contains the table scope
7676 * and action record pointer. - metadata2[25:0] contains the
7677 * action record pointer. - metadata2[31:26] contains the table
7680 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
7681 (UINT32_C(0x1) << 4)
7683 * The {metadata1, metadata0} fields contain the vtag
7685 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7686 * The metadata2 field contains the Tunnel ID
7687 * value, justified to LSB.
7688 * - VXLAN = VNI[23:0] -> VXLAN Network ID
7689 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
7690 * - NVGRE = TNI[23:0] -> Tenant Network ID
7691 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
7692 * - IPv4 = 0 (not populated)
7693 * - IPv6 = Flow Label[19:0]
7694 * - PPPoE = sessionID[15:0]
7695 * - MPLs = Outer label[19:0]
7696 * - UPAR = Selected[31:0] with bit mask
7698 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
7699 (UINT32_C(0x2) << 4)
7701 * The {metadata1, metadata0} fields contain the vtag
7703 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
7704 * The metadata2 field contains the 32b metadata from the prepended
7705 * header (chdr_data).
7707 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
7708 (UINT32_C(0x3) << 4)
7710 * The {metadata1, metadata0} fields contain the vtag
7712 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7713 * The metadata2 field contains the outer_l3_offset,
7714 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
7715 * - metadata2[8:0] contains the outer_l3_offset.
7716 * - metadata2[17:9] contains the inner_l2_offset.
7717 * - metadata2[26:18] contains the inner_l3_offset.
7718 * - metadata2[31:27] contains the inner_l4_size.
7720 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
7721 (UINT32_C(0x4) << 4)
7722 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_LAST \
7723 RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
7725 * This field indicates the IP type for the inner-most IP header.
7726 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7727 * This value is only valid if itype indicates a packet
7728 * with an IP header.
7730 #define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE \
7733 * This indicates that the complete 1's complement checksum was
7734 * calculated for the packet.
7736 #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
7739 * This field indicates the status of IP and L4 CS calculations done
7740 * by the chip. The format of this field is indicated by the
7741 * cs_all_ok_mode bit.
7743 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE \
7745 /* Indicates that the Tunnel IP type was IPv4 */
7746 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4 \
7747 (UINT32_C(0x0) << 10)
7748 /* Indicates that the Tunnel IP type was IPv6 */
7749 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 \
7750 (UINT32_C(0x1) << 10)
7751 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_LAST \
7752 RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6
7753 /* This indicates that the aggregation was done using GRO rules. */
7754 #define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO \
7757 * This value is the complete 1's complement checksum calculated from
7758 * the start of the outer L3 header to the end of the packet (not
7759 * including the ethernet crc). It is valid when the
7760 * 'complete_checksum_calc' flag is set. For TPA Start completions,
7761 * the complete checksum is calculated for the first packet in the
7764 #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
7765 UINT32_C(0xffff0000)
7766 #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
7768 * This is data from the CFA block as indicated by the meta_format
7770 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
7771 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
7772 * act_rec_ptr[25:0]}
7773 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
7774 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
7775 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
7776 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
7777 * of the host address from the first BD used to place the packet.
7782 * This value is written by the NIC such that it will be different
7783 * for each pass through the completion queue. The even passes
7784 * will write 1. The odd passes will write 0.
7786 #define RX_TPA_START_V3_CMPL_V2 \
7788 #define RX_TPA_START_V3_CMPL_ERRORS_MASK \
7790 #define RX_TPA_START_V3_CMPL_ERRORS_SFT 1
7792 * This error indicates that there was some sort of problem with
7793 * the BDs for the packetThe packet should be treated as
7796 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK \
7798 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7799 /* No buffer error */
7800 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7801 (UINT32_C(0x0) << 1)
7804 * Packet did not fit into packet buffer provided. This means
7805 * that the TPA Start packet was too big to be placed into the
7806 * per-packet maximum number of physical buffers configured for
7807 * the VNIC, or that it was too big to be placed into the
7808 * per-aggregation maximum number of physical buffers configured
7809 * for the VNIC. This error only occurs when the VNIC is
7810 * configured for variable size receive buffers.
7812 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7813 (UINT32_C(0x1) << 1)
7816 * BDs were not formatted correctly.
7818 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7819 (UINT32_C(0x3) << 1)
7822 * There was a bad_format error on the previous operation
7824 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7825 (UINT32_C(0x5) << 1)
7826 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_LAST \
7827 RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7829 * This is data from the CFA block as indicated by the meta_format
7833 /* When meta_format != 0, this value is the VLAN VID. */
7834 #define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
7835 #define RX_TPA_START_V3_CMPL_METADATA0_VID_SFT 0
7836 /* When meta_format != 0, this value is the VLAN DE. */
7837 #define RX_TPA_START_V3_CMPL_METADATA0_DE UINT32_C(0x1000)
7838 /* When meta_format != 0, this value is the VLAN PRI. */
7839 #define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
7840 #define RX_TPA_START_V3_CMPL_METADATA0_PRI_SFT 13
7842 * This field contains the outer_l3_offset, inner_l2_offset,
7843 * inner_l3_offset, and inner_l4_size.
7845 * hdr_offsets[8:0] contains the outer_l3_offset.
7846 * hdr_offsets[17:9] contains the inner_l2_offset.
7847 * hdr_offsets[26:18] contains the inner_l3_offset.
7848 * hdr_offsets[31:27] contains the inner_l4_size.
7850 uint32_t hdr_offsets;
7854 * This TPA completion structure is used on devices where the
7855 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7857 /* rx_tpa_end_cmpl (size:128b/16B) */
7858 struct rx_tpa_end_cmpl {
7859 uint16_t flags_type;
7861 * This field indicates the exact type of the completion.
7862 * By convention, the LSB identifies the length of the
7863 * record in 16B units. Even values indicate 16B
7864 * records. Odd values indicate 32B
7867 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
7868 #define RX_TPA_END_CMPL_TYPE_SFT 0
7870 * RX L2 TPA End Completion:
7871 * Completion at the end of a TPA operation.
7874 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
7875 #define RX_TPA_END_CMPL_TYPE_LAST \
7876 RX_TPA_END_CMPL_TYPE_RX_TPA_END
7877 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7878 #define RX_TPA_END_CMPL_FLAGS_SFT 6
7880 * When this bit is '1', it indicates a packet that has an
7881 * error of some type. Type of error is indicated in
7884 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
7885 /* This field indicates how the packet was placed in the buffer. */
7886 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
7887 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
7890 * TPA Packet was placed using jumbo algorithm. This means
7891 * that the first buffer will be filled with data before
7892 * moving to aggregation buffers. Each aggregation buffer
7893 * will be filled before moving to the next aggregation
7896 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
7897 (UINT32_C(0x1) << 7)
7899 * Header/Data Separation:
7900 * Packet was placed using Header/Data separation algorithm.
7901 * The separation location is indicated by the itype field.
7903 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
7904 (UINT32_C(0x2) << 7)
7907 * Packet will be placed using In-Order Completion/Jumbo where
7908 * the first packet of the aggregation is placed using Jumbo
7909 * Placement. Subsequent packets will be placed such that each
7910 * packet starts at the beginning of an aggregation buffer.
7912 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
7913 (UINT32_C(0x4) << 7)
7916 * Packet will be placed using GRO/Jumbo where the first
7917 * packet is filled with data. Subsequent packets will be
7918 * placed such that any one packet does not span two
7919 * aggregation buffers unless it starts at the beginning of
7920 * an aggregation buffer.
7922 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
7923 (UINT32_C(0x5) << 7)
7925 * GRO/Header-Data Separation:
7926 * Packet will be placed using GRO/HDS where the header
7927 * is in the first packet.
7928 * Payload of each packet will be
7929 * placed such that any one packet does not span two
7930 * aggregation buffers unless it starts at the beginning of
7931 * an aggregation buffer.
7933 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
7934 (UINT32_C(0x6) << 7)
7936 * IOC/Header-Data Separation:
7937 * Packet will be placed using In-Order Completion/HDS where
7938 * the header is in the first packet buffer. Payload of each
7939 * packet will be placed such that each packet starts at the
7940 * beginning of an aggregation buffer.
7942 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
7943 (UINT32_C(0x7) << 7)
7944 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
7945 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
7946 /* When set, this bit indicates that the timestamp field is valid. */
7947 #define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID UINT32_C(0x400)
7949 * This bit is '1' if metadata has been added to the end of the
7950 * packet in host memory. Metadata starts at the first 32B boundary
7951 * after the end of the packet for regular and jumbo placement.
7952 * It starts at the first 32B boundary after the end of the header
7953 * for HDS placement. The length of the metadata is indicated in the
7956 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
7958 * This value indicates what the inner packet determined for the
7961 * Indicates that the packet was IP and TCP. This indicates
7962 * that the ip_cs field is valid and that the tcp_udp_cs
7963 * field is valid and contains the TCP checksum.
7964 * This also indicates that the payload_offset field is valid.
7966 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
7968 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
7970 * This value is zero for TPA End completions.
7971 * There is no data in the buffer that corresponds to the opaque
7972 * value in this completion.
7976 * This is a copy of the opaque field from the RX BD this completion
7981 * This value is written by the NIC such that it will be different
7982 * for each pass through the completion queue. The even passes
7983 * will write 1. The odd passes will write 0.
7985 uint8_t agg_bufs_v1;
7987 * This value is written by the NIC such that it will be different
7988 * for each pass through the completion queue. The even passes
7989 * will write 1. The odd passes will write 0.
7991 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
7993 * This value is the number of aggregation buffers that follow this
7994 * entry in the completion ring that are a part of this aggregation
7996 * If the value is zero, then the packet is completely contained
7997 * in the buffer space provided in the aggregation start completion.
7999 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
8000 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
8001 /* This value is the number of segments in the TPA operation. */
8004 * This value indicates the offset in bytes from the beginning of the
8005 * packet where the inner payload starts. This value is valid for TCP,
8006 * UDP, FCoE, and RoCE packets.
8008 * A value of zero indicates an offset of 256 bytes.
8010 uint8_t payload_offset;
8012 /* unused2 is 1 b */
8013 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
8015 * This is the aggregation ID that the completion is associated
8016 * with. Use this number to correlate the TPA start completion
8017 * with the TPA end completion.
8019 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
8020 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
8022 * For non-GRO packets, this value is the
8023 * timestamp delta between earliest and latest timestamp values for
8024 * TPA packet. If packets were not time stamped, then delta will be
8027 * For GRO packets, this field is zero except for the following
8030 * Timestamp present indication. When '0', no Timestamp
8031 * option is in the packet. When '1', then a Timestamp
8032 * option is present in the packet.
8038 * Last 16 bytes of rx_tpa_end_cmpl.
8040 * This TPA completion structure is used on devices where the
8041 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8043 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
8044 struct rx_tpa_end_cmpl_hi {
8045 uint32_t tpa_dup_acks;
8047 * This value is the number of duplicate ACKs that have been
8048 * received as part of the TPA operation.
8050 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
8051 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
8053 * This value is the valid when TPA completion is active. It
8054 * indicates the length of the longest segment of the TPA operation
8055 * for LRO mode and the length of the first segment in GRO mode.
8057 * This value may be used by GRO software to re-construct the original
8058 * packet stream from the TPA packet. This is the length of all
8059 * but the last segment for GRO. In LRO mode this value may be used
8060 * to indicate MSS size to the stack.
8062 uint16_t tpa_seg_len;
8064 * The lower 16b of the timestamp of the last packet added to the
8065 * aggregation. Only valid when flags.timestamp_valid is set.
8067 uint16_t timestamp_lower;
8070 * This value is written by the NIC such that it will be different
8071 * for each pass through the completion queue. The even passes
8072 * will write 1. The odd passes will write 0.
8074 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
8075 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
8076 #define RX_TPA_END_CMPL_ERRORS_SFT 1
8078 * This error indicates that there was some sort of problem with
8079 * the BDs for the packet that was found after part of the
8080 * packet was already placed. The packet should be treated as
8083 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
8084 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
8086 * This error occurs when there is a fatal HW problem in
8087 * the chip only. It indicates that there were not
8088 * BDs on chip but that there was adequate reservation.
8089 * provided by the TPA block.
8091 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
8092 (UINT32_C(0x2) << 1)
8094 * This error occurs when TPA block was not configured to
8095 * reserve adequate BDs for TPA operations on this RX
8096 * ring. All data for the TPA operation was not placed.
8098 * This error can also be generated when the number of
8099 * segments is not programmed correctly in TPA and the
8100 * 33 total aggregation buffers allowed for the TPA
8101 * operation has been exceeded.
8103 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
8104 (UINT32_C(0x4) << 1)
8105 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
8106 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
8108 * The upper 16b of the timestamp of the last packet added to the
8109 * aggregation. Only valid when flags.timestamp_valid is set.
8111 uint16_t timestamp_upper;
8113 * This is the opaque value that was completed for the TPA start
8114 * completion that corresponds to this TPA end completion.
8116 uint32_t start_opaque;
8120 * This TPA completion structure is used on devices where the
8121 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8123 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
8124 struct rx_tpa_v2_start_cmpl {
8125 uint16_t flags_type;
8127 * This field indicates the exact type of the completion.
8128 * By convention, the LSB identifies the length of the
8129 * record in 16B units. Even values indicate 16B
8130 * records. Odd values indicate 32B
8133 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
8135 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
8137 * RX L2 TPA Start Completion:
8138 * Completion at the beginning of a TPA operation.
8141 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
8143 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
8144 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
8145 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
8147 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
8148 /* This bit will always be '0' for TPA start completions. */
8149 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
8151 /* This field indicates how the packet was placed in the buffer. */
8152 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
8154 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
8157 * TPA Packet was placed using jumbo algorithm. This means
8158 * that the first buffer will be filled with data before
8159 * moving to aggregation buffers. Each aggregation buffer
8160 * will be filled before moving to the next aggregation
8163 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
8164 (UINT32_C(0x1) << 7)
8166 * Header/Data Separation:
8167 * Packet was placed using Header/Data separation algorithm.
8168 * The separation location is indicated by the itype field.
8170 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
8171 (UINT32_C(0x2) << 7)
8174 * Packet will be placed using GRO/Jumbo where the first
8175 * packet is filled with data. Subsequent packets will be
8176 * placed such that any one packet does not span two
8177 * aggregation buffers unless it starts at the beginning of
8178 * an aggregation buffer.
8180 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
8181 (UINT32_C(0x5) << 7)
8183 * GRO/Header-Data Separation:
8184 * Packet will be placed using GRO/HDS where the header
8185 * is in the first packet.
8186 * Payload of each packet will be
8187 * placed such that any one packet does not span two
8188 * aggregation buffers unless it starts at the beginning of
8189 * an aggregation buffer.
8191 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
8192 (UINT32_C(0x6) << 7)
8193 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
8194 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
8195 /* This bit is '1' if the RSS field in this completion is valid. */
8196 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
8199 * For devices that support timestamps, when this bit is cleared the
8200 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
8201 * field contains the 32b timestamp for
8202 * the packet from the MAC. When this bit is set, the
8203 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
8204 * field contains the outer_l3_offset, inner_l2_offset,
8205 * inner_l3_offset, and inner_l4_size.
8207 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
8210 * This value indicates what the inner packet determined for the
8213 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
8215 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
8218 * Indicates that the packet was IP and TCP.
8220 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
8221 (UINT32_C(0x2) << 12)
8222 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
8223 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
8225 * This value indicates the amount of packet data written to the
8226 * buffer the opaque field in this completion corresponds to.
8230 * This is a copy of the opaque field from the RX BD this completion
8235 * This value is written by the NIC such that it will be different
8236 * for each pass through the completion queue. The even passes
8237 * will write 1. The odd passes will write 0.
8241 * This value is written by the NIC such that it will be different
8242 * for each pass through the completion queue. The even passes
8243 * will write 1. The odd passes will write 0.
8245 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
8246 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
8248 * This is the RSS hash type for the packet. The value is packed
8249 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
8251 * The value of tuple_extrac_op provides the information about
8252 * what fields the hash was computed on.
8253 * * 0: The RSS hash was computed over source IP address,
8254 * destination IP address, source port, and destination port of inner
8255 * IP and TCP or UDP headers. Note: For non-tunneled packets,
8256 * the packet headers are considered inner packet headers for the RSS
8257 * hash computation purpose.
8258 * * 1: The RSS hash was computed over source IP address and destination
8259 * IP address of inner IP header. Note: For non-tunneled packets,
8260 * the packet headers are considered inner packet headers for the RSS
8261 * hash computation purpose.
8262 * * 2: The RSS hash was computed over source IP address,
8263 * destination IP address, source port, and destination port of
8264 * IP and TCP or UDP headers of outer tunnel headers.
8265 * Note: For non-tunneled packets, this value is not applicable.
8266 * * 3: The RSS hash was computed over source IP address and
8267 * destination IP address of IP header of outer tunnel headers.
8268 * Note: For non-tunneled packets, this value is not applicable.
8270 * Note that 4-tuples values listed above are applicable
8271 * for layer 4 protocols supported and enabled for RSS in the hardware,
8272 * HWRM firmware, and drivers. For example, if RSS hash is supported and
8273 * enabled for TCP traffic only, then the values of tuple_extract_op
8274 * corresponding to 4-tuples are only valid for TCP traffic.
8276 uint8_t rss_hash_type;
8278 * This is the aggregation ID that the completion is associated
8279 * with. Use this number to correlate the TPA start completion
8280 * with the TPA end completion.
8284 * This value is the RSS hash value calculated for the packet
8285 * based on the mode bits and key value in the VNIC.
8291 * Last 16 bytes of rx_tpa_v2_start_cmpl.
8293 * This TPA completion structure is used on devices where the
8294 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8296 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
8297 struct rx_tpa_v2_start_cmpl_hi {
8300 * This indicates that the ip checksum was calculated for the
8301 * inner packet and that the sum passed for all segments
8302 * included in the aggregation.
8304 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
8307 * This indicates that the TCP, UDP or ICMP checksum was
8308 * calculated for the inner packet and that the sum passed
8309 * for all segments included in the aggregation.
8311 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
8314 * This indicates that the ip checksum was calculated for the
8315 * tunnel header and that the sum passed for all segments
8316 * included in the aggregation.
8318 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
8321 * This indicates that the UDP checksum was
8322 * calculated for the tunnel packet and that the sum passed for
8323 * all segments included in the aggregation.
8325 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
8327 /* This value indicates what format the metadata field is. */
8328 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
8330 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
8331 /* No metadata informtaion. Value is zero. */
8332 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
8333 (UINT32_C(0x0) << 4)
8335 * The metadata field contains the VLAN tag and TPID value.
8336 * - metadata[11:0] contains the vlan VID value.
8337 * - metadata[12] contains the vlan DE value.
8338 * - metadata[15:13] contains the vlan PRI value.
8339 * - metadata[31:16] contains the vlan TPID value.
8341 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
8342 (UINT32_C(0x1) << 4)
8344 * If ext_meta_format is equal to 1, the metadata field
8345 * contains the lower 16b of the tunnel ID value, justified
8347 * - VXLAN = VNI[23:0] -> VXLAN Network ID
8348 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
8349 * - NVGRE = TNI[23:0] -> Tenant Network ID
8350 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
8351 * - IPV4 = 0 (not populated)
8352 * - IPV6 = Flow Label[19:0]
8353 * - PPPoE = sessionID[15:0]
8354 * - MPLs = Outer label[19:0]
8355 * - UPAR = Selected[31:0] with bit mask
8357 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
8358 (UINT32_C(0x2) << 4)
8360 * if ext_meta_format is equal to 1, metadata field contains
8361 * 16b metadata from the prepended header (chdr_data).
8363 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
8364 (UINT32_C(0x3) << 4)
8366 * If ext_meta_format is equal to 1, the metadata field contains
8367 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
8369 * - metadata[8:0] contains the outer_l3_offset.
8370 * - metadata[17:9] contains the inner_l2_offset.
8371 * - metadata[26:18] contains the inner_l3_offset.
8372 * - metadata[31:27] contains the inner_l4_size.
8374 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
8375 (UINT32_C(0x4) << 4)
8376 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
8377 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
8379 * This field indicates the IP type for the inner-most IP header.
8380 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
8382 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
8385 * This indicates that the complete 1's complement checksum was
8386 * calculated for the packet.
8388 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
8391 * The combination of this value and meta_format indicated what
8392 * format the metadata field is.
8394 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
8396 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
8398 * This value is the complete 1's complement checksum calculated from
8399 * the start of the outer L3 header to the end of the packet (not
8400 * including the ethernet crc). It is valid when the
8401 * 'complete_checksum_calc' flag is set. For TPA Start completions,
8402 * the complete checksum is calculated for the first packet in the
8405 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
8406 UINT32_C(0xffff0000)
8407 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
8409 * This is data from the CFA block as indicated by the meta_format
8413 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
8414 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
8415 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
8416 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
8417 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
8418 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
8419 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
8420 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
8421 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
8422 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
8423 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
8426 * This value is written by the NIC such that it will be different
8427 * for each pass through the completion queue. The even passes
8428 * will write 1. The odd passes will write 0.
8430 #define RX_TPA_V2_START_CMPL_V2 \
8432 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
8434 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
8436 * This error indicates that there was some sort of problem with
8437 * the BDs for the packet that was found after part of the
8438 * packet was already placed. The packet should be treated as
8441 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
8443 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
8444 /* No buffer error */
8445 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
8446 (UINT32_C(0x0) << 1)
8449 * BDs were not formatted correctly.
8451 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
8452 (UINT32_C(0x3) << 1)
8455 * There was a bad_format error on the previous operation
8457 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
8458 (UINT32_C(0x5) << 1)
8459 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
8460 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
8462 * This field identifies the CFA action rule that was used for this
8467 * For devices that support timestamps this field is overridden
8468 * with the timestamp value. When `flags.timestamp_fld_format` is
8469 * cleared, this field contains the 32b timestamp for the packet from the
8472 * When `flags.timestamp_fld_format` is set, this field contains the
8473 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
8476 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
8478 * This is the offset from the beginning of the packet in bytes for
8479 * the outer L3 header. If there is no outer L3 header, then this
8482 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
8483 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
8485 * This is the offset from the beginning of the packet in bytes for
8486 * the inner most L2 header.
8488 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
8489 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
8491 * This is the offset from the beginning of the packet in bytes for
8492 * the inner most L3 header.
8494 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
8495 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
8497 * This is the size in bytes of the inner most L4 header.
8498 * This can be subtracted from the payload_offset to determine
8499 * the start of the inner most L4 header.
8501 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
8502 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
8506 * This TPA completion structure is used on devices where the
8507 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8509 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
8510 struct rx_tpa_v2_end_cmpl {
8511 uint16_t flags_type;
8513 * This field indicates the exact type of the completion.
8514 * By convention, the LSB identifies the length of the
8515 * record in 16B units. Even values indicate 16B
8516 * records. Odd values indicate 32B
8519 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
8521 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
8523 * RX L2 TPA End Completion:
8524 * Completion at the end of a TPA operation.
8527 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
8529 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
8530 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
8531 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
8533 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
8535 * When this bit is '1', it indicates a packet that has an
8536 * error of some type. Type of error is indicated in
8539 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
8541 /* This field indicates how the packet was placed in the buffer. */
8542 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
8544 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
8547 * TPA Packet was placed using jumbo algorithm. This means
8548 * that the first buffer will be filled with data before
8549 * moving to aggregation buffers. Each aggregation buffer
8550 * will be filled before moving to the next aggregation
8553 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
8554 (UINT32_C(0x1) << 7)
8556 * Header/Data Separation:
8557 * Packet was placed using Header/Data separation algorithm.
8558 * The separation location is indicated by the itype field.
8560 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
8561 (UINT32_C(0x2) << 7)
8564 * Packet will be placed using GRO/Jumbo where the first
8565 * packet is filled with data. Subsequent packets will be
8566 * placed such that any one packet does not span two
8567 * aggregation buffers unless it starts at the beginning of
8568 * an aggregation buffer.
8570 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
8571 (UINT32_C(0x5) << 7)
8573 * GRO/Header-Data Separation:
8574 * Packet will be placed using GRO/HDS where the header
8575 * is in the first packet.
8576 * Payload of each packet will be
8577 * placed such that any one packet does not span two
8578 * aggregation buffers unless it starts at the beginning of
8579 * an aggregation buffer.
8581 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
8582 (UINT32_C(0x6) << 7)
8584 * IOC/Header-Data Separation:
8585 * Packet will be placed using In-Order Completion/HDS where
8586 * the header is in the first packet buffer. Payload of each
8587 * packet will be placed such that each packet starts at the
8588 * beginning of an aggregation buffer.
8590 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
8591 (UINT32_C(0x7) << 7)
8592 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
8593 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
8595 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
8598 * This bit is '1' if metadata has been added to the end of the
8599 * packet in host memory. Metadata starts at the first 32B boundary
8600 * after the end of the packet for regular and jumbo placement.
8601 * It starts at the first 32B boundary after the end of the header
8602 * for HDS placement. The length of the metadata is indicated in the
8605 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
8608 * This value indicates what the inner packet determined for the
8611 * Indicates that the packet was IP and TCP. This indicates
8612 * that the ip_cs field is valid and that the tcp_udp_cs
8613 * field is valid and contains the TCP checksum.
8614 * This also indicates that the payload_offset field is valid.
8616 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
8618 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
8620 * This value is zero for TPA End completions.
8621 * There is no data in the buffer that corresponds to the opaque
8622 * value in this completion.
8626 * This is a copy of the opaque field from the RX BD this completion
8632 * This value is written by the NIC such that it will be different
8633 * for each pass through the completion queue. The even passes
8634 * will write 1. The odd passes will write 0.
8636 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
8637 /* This value is the number of segments in the TPA operation. */
8640 * This is the aggregation ID that the completion is associated
8641 * with. Use this number to correlate the TPA start completion
8642 * with the TPA end completion.
8646 * For non-GRO packets, this value is the
8647 * timestamp delta between earliest and latest timestamp values for
8648 * TPA packet. If packets were not time stamped, then delta will be
8651 * For GRO packets, this field is zero except for the following
8654 * Timestamp present indication. When '0', no Timestamp
8655 * option is in the packet. When '1', then a Timestamp
8656 * option is present in the packet.
8662 * Last 16 bytes of rx_tpa_v2_end_cmpl.
8664 * This TPA completion structure is used on devices where the
8665 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8667 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
8668 struct rx_tpa_v2_end_cmpl_hi {
8670 * This value is the number of duplicate ACKs that have been
8671 * received as part of the TPA operation.
8673 uint16_t tpa_dup_acks;
8675 * This value is the number of duplicate ACKs that have been
8676 * received as part of the TPA operation.
8678 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
8679 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
8681 * This value indicated the offset in bytes from the beginning of
8682 * the packet where the inner payload starts. This value is valid
8683 * for TCP, UDP, FCoE and RoCE packets
8685 uint8_t payload_offset;
8687 * The value is the total number of aggregation buffers that were
8688 * used in the TPA operation. All TPA aggregation buffer completions
8689 * precede the TPA End completion. If the value is zero, then the
8690 * aggregation is completely contained in the buffer space provided
8691 * in the aggregation start completion.
8692 * Note that the field is simply provided as a cross check.
8694 uint8_t tpa_agg_bufs;
8696 * This value is the valid when TPA completion is active. It
8697 * indicates the length of the longest segment of the TPA operation
8698 * for LRO mode and the length of the first segment in GRO mode.
8700 * This value may be used by GRO software to re-construct the original
8701 * packet stream from the TPA packet. This is the length of all
8702 * but the last segment for GRO. In LRO mode this value may be used
8703 * to indicate MSS size to the stack.
8705 uint16_t tpa_seg_len;
8709 * This value is written by the NIC such that it will be different
8710 * for each pass through the completion queue. The even passes
8711 * will write 1. The odd passes will write 0.
8713 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
8714 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
8716 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
8718 * This error indicates that there was some sort of problem with
8719 * the BDs for the packet that was found after part of the
8720 * packet was already placed. The packet should be treated as
8723 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
8725 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
8726 /* No buffer error */
8727 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
8728 (UINT32_C(0x0) << 1)
8730 * This error occurs when there is a fatal HW problem in
8731 * the chip only. It indicates that there were not
8732 * BDs on chip but that there was adequate reservation.
8733 * provided by the TPA block.
8735 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
8736 (UINT32_C(0x2) << 1)
8739 * BDs were not formatted correctly.
8741 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
8742 (UINT32_C(0x3) << 1)
8744 * This error occurs when TPA block was not configured to
8745 * reserve adequate BDs for TPA operations on this RX
8746 * ring. All data for the TPA operation was not placed.
8748 * This error can also be generated when the number of
8749 * segments is not programmed correctly in TPA and the
8750 * 33 total aggregation buffers allowed for the TPA
8751 * operation has been exceeded.
8753 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
8754 (UINT32_C(0x4) << 1)
8757 * There was a bad_format error on the previous operation
8759 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
8760 (UINT32_C(0x5) << 1)
8761 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
8762 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
8765 * This is the opaque value that was completed for the TPA start
8766 * completion that corresponds to this TPA end completion.
8768 uint32_t start_opaque;
8772 * This TPA completion structure is used on devices where the
8773 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8775 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
8776 struct rx_tpa_v2_abuf_cmpl {
8779 * This field indicates the exact type of the completion.
8780 * By convention, the LSB identifies the length of the
8781 * record in 16B units. Even values indicate 16B
8782 * records. Odd values indicate 32B
8785 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
8786 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
8788 * RX TPA Aggregation Buffer completion:
8789 * Completion of an L2 aggregation buffer in support of
8790 * TPA packet completion. Length = 16B
8792 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
8793 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
8794 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
8796 * This is the length of the data for the packet stored in this
8797 * aggregation buffer identified by the opaque value. This does not
8798 * include the length of any
8799 * data placed in other aggregation BDs or in the packet or buffer
8800 * BDs. This length does not include any space added due to
8801 * hdr_offset register during HDS placement mode.
8805 * This is a copy of the opaque field from the RX BD this aggregation
8806 * buffer corresponds to.
8811 * This value is written by the NIC such that it will be different
8812 * for each pass through the completion queue. The even passes
8813 * will write 1. The odd passes will write 0.
8815 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
8817 * This is the aggregation ID that the completion is associated with. Use
8818 * this number to correlate the TPA agg completion with the TPA start
8819 * completion and the TPA end completion.
8825 /* rx_abuf_cmpl (size:128b/16B) */
8826 struct rx_abuf_cmpl {
8829 * This field indicates the exact type of the completion.
8830 * By convention, the LSB identifies the length of the
8831 * record in 16B units. Even values indicate 16B
8832 * records. Odd values indicate 32B
8835 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
8836 #define RX_ABUF_CMPL_TYPE_SFT 0
8838 * RX Aggregation Buffer completion:
8839 * Completion of an L2 aggregation buffer in support of
8840 * TPA, HDS, or Jumbo packet completion. Length = 16B
8842 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
8843 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
8845 * This is the length of the data for the packet stored in this
8846 * aggregation buffer identified by the opaque value. This does not
8847 * include the length of any
8848 * data placed in other aggregation BDs or in the packet or buffer
8849 * BDs. This length does not include any space added due to
8850 * hdr_offset register during HDS placement mode.
8854 * This is a copy of the opaque field from the RX BD this aggregation
8855 * buffer corresponds to.
8860 * This value is written by the NIC such that it will be different
8861 * for each pass through the completion queue. The even passes
8862 * will write 1. The odd passes will write 0.
8864 #define RX_ABUF_CMPL_V UINT32_C(0x1)
8865 /* unused3 is 32 b */
8869 /* VEE FLUSH Completion Record (16 bytes) */
8870 /* vee_flush (size:128b/16B) */
8872 uint32_t downstream_path_type;
8874 * This field indicates the exact type of the completion.
8875 * By convention, the LSB identifies the length of the
8876 * record in 16B units. Even values indicate 16B
8877 * records. Odd values indicate 32B
8880 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
8881 #define VEE_FLUSH_TYPE_SFT 0
8883 * VEE Flush Completion:
8884 * This completion is inserted manually by the Primate and processed
8885 * by the VEE hardware to ensure that all completions on a VEE
8886 * function have been processed by the VEE hardware before FLR
8887 * process is completed.
8889 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
8890 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
8891 /* downstream_path is 1 b */
8892 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
8893 /* This completion is associated with VEE Transmit */
8894 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
8895 /* This completion is associated with VEE Receive */
8896 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
8897 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
8899 * This is an opaque value that is passed through the completion
8900 * to the VEE handler SW and is used to indicate what VEE VQ or
8901 * function has completed FLR processing.
8906 * This value is written by the NIC such that it will be different
8907 * for each pass through the completion queue. The even passes will
8908 * write 1. The odd passes will write 0.
8910 #define VEE_FLUSH_V UINT32_C(0x1)
8911 /* unused3 is 32 b */
8915 /* eject_cmpl (size:128b/16B) */
8919 * This field indicates the exact type of the completion.
8920 * By convention, the LSB identifies the length of the
8921 * record in 16B units. Even values indicate 16B
8922 * records. Odd values indicate 32B
8925 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
8926 #define EJECT_CMPL_TYPE_SFT 0
8928 * Statistics Ejection Completion:
8929 * Completion of statistics data ejection buffer.
8932 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
8933 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
8934 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
8935 #define EJECT_CMPL_FLAGS_SFT 6
8937 * When this bit is '1', it indicates a packet that has an
8938 * error of some type. Type of error is indicated in
8941 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
8943 * This is the length of the statistics data stored in this
8948 * This is a copy of the opaque field from the RX BD this ejection
8949 * buffer corresponds to.
8954 * This value is written by the NIC such that it will be different
8955 * for each pass through the completion queue. The even passes
8956 * will write 1. The odd passes will write 0.
8958 #define EJECT_CMPL_V UINT32_C(0x1)
8959 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
8960 #define EJECT_CMPL_ERRORS_SFT 1
8962 * This error indicates that there was some sort of problem with
8963 * the BDs for statistics ejection. The statistics ejection should
8964 * be treated as invalid
8966 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
8967 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
8968 /* No buffer error */
8969 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
8970 (UINT32_C(0x0) << 1)
8973 * Statistics did not fit into aggregation buffer provided.
8975 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
8976 (UINT32_C(0x1) << 1)
8979 * BDs were not formatted correctly.
8981 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
8982 (UINT32_C(0x3) << 1)
8985 * There was a bad_format error on the previous operation
8987 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
8988 (UINT32_C(0x5) << 1)
8989 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
8990 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
8991 /* reserved16 is 16 b */
8992 uint16_t reserved16;
8993 /* unused3 is 32 b */
8997 /* hwrm_cmpl (size:128b/16B) */
9001 * This field indicates the exact type of the completion.
9002 * By convention, the LSB identifies the length of the
9003 * record in 16B units. Even values indicate 16B
9004 * records. Odd values indicate 32B
9007 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
9008 #define HWRM_CMPL_TYPE_SFT 0
9010 * HWRM Command Completion:
9011 * Completion of an HWRM command.
9013 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
9014 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
9015 /* This is the sequence_id of the HWRM command that has completed. */
9016 uint16_t sequence_id;
9017 /* unused2 is 32 b */
9021 * This value is written by the NIC such that it will be different
9022 * for each pass through the completion queue. The even passes
9023 * will write 1. The odd passes will write 0.
9025 #define HWRM_CMPL_V UINT32_C(0x1)
9026 /* unused4 is 32 b */
9030 /* hwrm_fwd_req_cmpl (size:128b/16B) */
9031 struct hwrm_fwd_req_cmpl {
9033 * This field indicates the exact type of the completion.
9034 * By convention, the LSB identifies the length of the
9035 * record in 16B units. Even values indicate 16B
9036 * records. Odd values indicate 32B
9039 uint16_t req_len_type;
9041 * This field indicates the exact type of the completion.
9042 * By convention, the LSB identifies the length of the
9043 * record in 16B units. Even values indicate 16B
9044 * records. Odd values indicate 32B
9047 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
9048 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
9049 /* Forwarded HWRM Request */
9050 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
9051 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
9052 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
9053 /* Length of forwarded request in bytes. */
9054 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
9055 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
9057 * Source ID of this request.
9058 * Typically used in forwarding requests and responses.
9059 * 0x0 - 0xFFF8 - Used for function ids
9060 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9064 /* unused1 is 32 b */
9066 /* Address of forwarded request. */
9067 uint32_t req_buf_addr_v[2];
9069 * This value is written by the NIC such that it will be different
9070 * for each pass through the completion queue. The even passes
9071 * will write 1. The odd passes will write 0.
9073 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
9074 /* Address of forwarded request. */
9075 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9076 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
9079 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
9080 struct hwrm_fwd_resp_cmpl {
9083 * This field indicates the exact type of the completion.
9084 * By convention, the LSB identifies the length of the
9085 * record in 16B units. Even values indicate 16B
9086 * records. Odd values indicate 32B
9089 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
9090 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
9091 /* Forwarded HWRM Response */
9092 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
9093 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
9094 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
9096 * Source ID of this response.
9097 * Typically used in forwarding requests and responses.
9098 * 0x0 - 0xFFF8 - Used for function ids
9099 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9103 /* Length of forwarded response in bytes. */
9105 /* unused2 is 16 b */
9107 /* Address of forwarded request. */
9108 uint32_t resp_buf_addr_v[2];
9110 * This value is written by the NIC such that it will be different
9111 * for each pass through the completion queue. The even passes
9112 * will write 1. The odd passes will write 0.
9114 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
9115 /* Address of forwarded request. */
9116 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9117 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
9120 /* hwrm_async_event_cmpl (size:128b/16B) */
9121 struct hwrm_async_event_cmpl {
9124 * This field indicates the exact type of the completion.
9125 * By convention, the LSB identifies the length of the
9126 * record in 16B units. Even values indicate 16B
9127 * records. Odd values indicate 32B
9130 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
9131 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
9132 /* HWRM Asynchronous Event Information */
9133 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
9134 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
9135 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
9136 /* Identifiers of events. */
9138 /* Link status changed */
9139 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
9141 /* Link MTU changed */
9142 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
9144 /* Link speed changed */
9145 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
9147 /* DCB Configuration changed */
9148 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
9150 /* Port connection not allowed */
9151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
9153 /* Link speed configuration was not allowed */
9154 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
9156 /* Link speed configuration change */
9157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
9159 /* Port PHY configuration change */
9160 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
9162 /* Reset notification to clients */
9163 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
9165 /* Master function selection event */
9166 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
9169 * An event signifying that a ring has been disabled by
9172 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
9174 /* Function driver unloaded */
9175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
9177 /* Function driver loaded */
9178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
9180 /* Function FLR related processing has completed */
9181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
9183 /* PF driver unloaded */
9184 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
9186 /* PF driver loaded */
9187 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
9189 /* VF Function Level Reset (FLR) */
9190 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
9192 /* VF MAC Address Change */
9193 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
9195 /* PF-VF communication channel status change. */
9196 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
9198 /* VF Configuration Change */
9199 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
9201 /* LLFC/PFC Configuration Change */
9202 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
9204 /* Default VNIC Configuration Change */
9205 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
9208 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
9211 * A debug notification being posted to the driver. These
9212 * notifications are purely for diagnostic purpose and should not be
9213 * used for functional purpose. The driver is not supposed to act
9214 * on these messages except to log/record it.
9216 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
9219 * An EEM flow cached memory flush for all flows request event being
9220 * posted to the PF driver.
9222 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
9225 * An EEM flow cache memory flush completion event being posted to the
9226 * firmware by the PF driver. This is indication that host EEM flush
9227 * has completed by the PF.
9229 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9232 * A tcp flag action change event being posted to the PF or trusted VF
9233 * driver by the firmware. The PF or trusted VF driver should query
9234 * the firmware for the new TCP flag action update after receiving
9237 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9240 * An EEM flow active event being posted to the PF or trusted VF driver
9241 * by the firmware. The PF or trusted VF driver should update the
9242 * flow's aging timer after receiving this async event.
9244 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
9247 * A eem cfg change event being posted to the trusted VF driver by the
9248 * firmware if the parent PF EEM configuration changed.
9250 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
9254 * TFLIB unique default VNIC Configuration Change
9256 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
9260 * TFLIB unique link status changed
9262 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
9265 * An event signifying completion for HWRM_FW_STATE_QUIESCE
9266 * (completion, timeout, or error)
9268 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
9271 * An event signifying a HWRM command is in progress and its
9272 * response will be deferred. This event is used on crypto controllers
9275 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
9278 * An event signifying that a PFC WatchDog configuration
9279 * has changed on any port / cos.
9281 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9284 * An echo request from the firmware. An echo response is expected by
9287 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
9290 * An event from firmware indicating who has been selected as the
9291 * PHC Master or secondary. Also indicates the last time a failover
9292 * happens. Event will also be sent when PHC rolls over.
9294 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE \
9297 * An event from firmware showing the last PPS timestamp that has been
9300 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \
9303 * An event from firmware indicating that an error has occurred.
9304 * The driver should log the event so that an administrator can be
9305 * aware that a problem has occurred that may need attention.
9307 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \
9310 * An event from firmware indicating that the programmed pacing
9311 * threshold for the doorbell global FIFO has been crossed. The driver
9312 * needs to take appropriate action to pace the doorbells when this
9313 * event is received from the firmware.
9315 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \
9317 /* Maximum Registrable event id. */
9318 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
9321 * A trace log message. This contains firmware trace logs string
9322 * embedded in the asynchronous message. This is an experimental
9323 * event, not meant for production use at this time.
9325 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
9328 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
9330 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
9331 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
9332 /* Event specific data */
9333 uint32_t event_data2;
9336 * This value is written by the NIC such that it will be different
9337 * for each pass through the completion queue. The even passes
9338 * will write 1. The odd passes will write 0.
9340 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
9342 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
9343 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
9344 /* 8-lsb timestamp from POR (100-msec resolution) */
9345 uint8_t timestamp_lo;
9346 /* 16-lsb timestamp from POR (100-msec resolution) */
9347 uint16_t timestamp_hi;
9348 /* Event specific data */
9349 uint32_t event_data1;
9352 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
9353 struct hwrm_async_event_cmpl_link_status_change {
9356 * This field indicates the exact type of the completion.
9357 * By convention, the LSB identifies the length of the
9358 * record in 16B units. Even values indicate 16B
9359 * records. Odd values indicate 32B
9362 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
9364 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
9365 /* HWRM Asynchronous Event Information */
9366 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9368 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
9369 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
9370 /* Identifiers of events. */
9372 /* Link status changed */
9373 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
9375 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
9376 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
9377 /* Event specific data */
9378 uint32_t event_data2;
9381 * This value is written by the NIC such that it will be different
9382 * for each pass through the completion queue. The even passes
9383 * will write 1. The odd passes will write 0.
9385 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
9388 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
9390 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
9391 /* 8-lsb timestamp from POR (100-msec resolution) */
9392 uint8_t timestamp_lo;
9393 /* 16-lsb timestamp from POR (100-msec resolution) */
9394 uint16_t timestamp_hi;
9395 /* Event specific data */
9396 uint32_t event_data1;
9397 /* Indicates link status change */
9398 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
9401 * If this bit set to 0, then it indicates that the link
9402 * was up and it went down.
9404 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
9407 * If this bit is set to 1, then it indicates that the link
9408 * was down and it went up.
9410 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
9412 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
9413 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
9414 /* Indicates the physical port this link status change occur */
9415 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
9417 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
9420 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9422 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9424 /* Indicates the physical function this event occurred on. */
9425 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
9427 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
9431 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
9432 struct hwrm_async_event_cmpl_link_mtu_change {
9435 * This field indicates the exact type of the completion.
9436 * By convention, the LSB identifies the length of the
9437 * record in 16B units. Even values indicate 16B
9438 * records. Odd values indicate 32B
9441 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
9443 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
9444 /* HWRM Asynchronous Event Information */
9445 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9447 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
9448 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
9449 /* Identifiers of events. */
9451 /* Link MTU changed */
9452 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
9454 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
9455 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
9456 /* Event specific data */
9457 uint32_t event_data2;
9460 * This value is written by the NIC such that it will be different
9461 * for each pass through the completion queue. The even passes
9462 * will write 1. The odd passes will write 0.
9464 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
9466 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
9468 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
9469 /* 8-lsb timestamp from POR (100-msec resolution) */
9470 uint8_t timestamp_lo;
9471 /* 16-lsb timestamp from POR (100-msec resolution) */
9472 uint16_t timestamp_hi;
9473 /* Event specific data */
9474 uint32_t event_data1;
9475 /* The new MTU of the link in bytes. */
9476 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
9478 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
9481 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
9482 struct hwrm_async_event_cmpl_link_speed_change {
9485 * This field indicates the exact type of the completion.
9486 * By convention, the LSB identifies the length of the
9487 * record in 16B units. Even values indicate 16B
9488 * records. Odd values indicate 32B
9491 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
9493 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
9494 /* HWRM Asynchronous Event Information */
9495 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9497 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
9498 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
9499 /* Identifiers of events. */
9501 /* Link speed changed */
9502 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
9504 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
9505 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
9506 /* Event specific data */
9507 uint32_t event_data2;
9510 * This value is written by the NIC such that it will be different
9511 * for each pass through the completion queue. The even passes
9512 * will write 1. The odd passes will write 0.
9514 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
9517 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
9519 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
9520 /* 8-lsb timestamp from POR (100-msec resolution) */
9521 uint8_t timestamp_lo;
9522 /* 16-lsb timestamp from POR (100-msec resolution) */
9523 uint16_t timestamp_hi;
9524 /* Event specific data */
9525 uint32_t event_data1;
9527 * When this bit is '1', the link was forced to the
9528 * force_link_speed value.
9530 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
9532 /* The new link speed in 100 Mbps units. */
9533 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
9535 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
9537 /* 100Mb link speed */
9538 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
9539 (UINT32_C(0x1) << 1)
9540 /* 1Gb link speed */
9541 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
9542 (UINT32_C(0xa) << 1)
9543 /* 2Gb link speed */
9544 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
9545 (UINT32_C(0x14) << 1)
9546 /* 25Gb link speed */
9547 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
9548 (UINT32_C(0x19) << 1)
9549 /* 10Gb link speed */
9550 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
9551 (UINT32_C(0x64) << 1)
9552 /* 20Mb link speed */
9553 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
9554 (UINT32_C(0xc8) << 1)
9555 /* 25Gb link speed */
9556 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
9557 (UINT32_C(0xfa) << 1)
9558 /* 40Gb link speed */
9559 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
9560 (UINT32_C(0x190) << 1)
9561 /* 50Gb link speed */
9562 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
9563 (UINT32_C(0x1f4) << 1)
9564 /* 100Gb link speed */
9565 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
9566 (UINT32_C(0x3e8) << 1)
9567 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
9568 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
9570 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9571 UINT32_C(0xffff0000)
9572 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9576 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
9577 struct hwrm_async_event_cmpl_dcb_config_change {
9580 * This field indicates the exact type of the completion.
9581 * By convention, the LSB identifies the length of the
9582 * record in 16B units. Even values indicate 16B
9583 * records. Odd values indicate 32B
9586 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
9588 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
9589 /* HWRM Asynchronous Event Information */
9590 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9592 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
9593 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9594 /* Identifiers of events. */
9596 /* DCB Configuration changed */
9597 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
9599 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
9600 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
9601 /* Event specific data */
9602 uint32_t event_data2;
9603 /* ETS configuration change */
9604 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
9606 /* PFC configuration change */
9607 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
9609 /* APP configuration change */
9610 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
9612 /* DSCP configuration change */
9613 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \
9617 * This value is written by the NIC such that it will be different
9618 * for each pass through the completion queue. The even passes
9619 * will write 1. The odd passes will write 0.
9621 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
9624 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
9626 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
9627 /* 8-lsb timestamp from POR (100-msec resolution) */
9628 uint8_t timestamp_lo;
9629 /* 16-lsb timestamp from POR (100-msec resolution) */
9630 uint16_t timestamp_hi;
9631 /* Event specific data */
9632 uint32_t event_data1;
9634 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9636 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9638 /* Priority recommended for RoCE traffic */
9639 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
9641 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
9644 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
9645 (UINT32_C(0xff) << 16)
9646 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
9647 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
9648 /* Priority recommended for L2 traffic */
9649 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
9650 UINT32_C(0xff000000)
9651 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
9654 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
9655 (UINT32_C(0xff) << 24)
9656 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
9657 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
9660 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
9661 struct hwrm_async_event_cmpl_port_conn_not_allowed {
9664 * This field indicates the exact type of the completion.
9665 * By convention, the LSB identifies the length of the
9666 * record in 16B units. Even values indicate 16B
9667 * records. Odd values indicate 32B
9670 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
9672 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
9674 /* HWRM Asynchronous Event Information */
9675 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
9677 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
9678 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
9679 /* Identifiers of events. */
9681 /* Port connection not allowed */
9682 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
9684 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
9685 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
9686 /* Event specific data */
9687 uint32_t event_data2;
9690 * This value is written by the NIC such that it will be different
9691 * for each pass through the completion queue. The even passes
9692 * will write 1. The odd passes will write 0.
9694 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
9697 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
9699 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
9700 /* 8-lsb timestamp from POR (100-msec resolution) */
9701 uint8_t timestamp_lo;
9702 /* 16-lsb timestamp from POR (100-msec resolution) */
9703 uint16_t timestamp_hi;
9704 /* Event specific data */
9705 uint32_t event_data1;
9707 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
9709 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
9712 * This value indicates the current port level enforcement policy
9713 * for the optics module when there is an optical module mismatch
9714 * and port is not connected.
9716 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
9718 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
9720 /* No enforcement */
9721 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
9722 (UINT32_C(0x0) << 16)
9723 /* Disable Transmit side Laser. */
9724 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
9725 (UINT32_C(0x1) << 16)
9726 /* Raise a warning message. */
9727 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
9728 (UINT32_C(0x2) << 16)
9729 /* Power down the module. */
9730 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
9731 (UINT32_C(0x3) << 16)
9732 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
9733 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
9736 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
9737 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
9740 * This field indicates the exact type of the completion.
9741 * By convention, the LSB identifies the length of the
9742 * record in 16B units. Even values indicate 16B
9743 * records. Odd values indicate 32B
9746 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
9748 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
9750 /* HWRM Asynchronous Event Information */
9751 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
9753 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
9754 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
9755 /* Identifiers of events. */
9757 /* Link speed configuration was not allowed */
9758 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
9760 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
9761 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
9762 /* Event specific data */
9763 uint32_t event_data2;
9766 * This value is written by the NIC such that it will be different
9767 * for each pass through the completion queue. The even passes
9768 * will write 1. The odd passes will write 0.
9770 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
9773 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
9775 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
9776 /* 8-lsb timestamp from POR (100-msec resolution) */
9777 uint8_t timestamp_lo;
9778 /* 16-lsb timestamp from POR (100-msec resolution) */
9779 uint16_t timestamp_hi;
9780 /* Event specific data */
9781 uint32_t event_data1;
9783 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
9785 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
9789 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
9790 struct hwrm_async_event_cmpl_link_speed_cfg_change {
9793 * This field indicates the exact type of the completion.
9794 * By convention, the LSB identifies the length of the
9795 * record in 16B units. Even values indicate 16B
9796 * records. Odd values indicate 32B
9799 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
9801 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
9803 /* HWRM Asynchronous Event Information */
9804 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9806 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
9807 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9808 /* Identifiers of events. */
9810 /* Link speed configuration change */
9811 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
9813 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
9814 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
9815 /* Event specific data */
9816 uint32_t event_data2;
9819 * This value is written by the NIC such that it will be different
9820 * for each pass through the completion queue. The even passes
9821 * will write 1. The odd passes will write 0.
9823 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
9826 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
9828 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
9829 /* 8-lsb timestamp from POR (100-msec resolution) */
9830 uint8_t timestamp_lo;
9831 /* 16-lsb timestamp from POR (100-msec resolution) */
9832 uint16_t timestamp_hi;
9833 /* Event specific data */
9834 uint32_t event_data1;
9836 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9838 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9841 * If set to 1, it indicates that the supported link speeds
9842 * configuration on the port has changed.
9843 * If set to 0, then there is no change in supported link speeds
9846 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
9849 * If set to 1, it indicates that the link speed configuration
9850 * on the port has become illegal or invalid.
9851 * If set to 0, then the link speed configuration on the port is
9854 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
9858 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
9859 struct hwrm_async_event_cmpl_port_phy_cfg_change {
9862 * This field indicates the exact type of the completion.
9863 * By convention, the LSB identifies the length of the
9864 * record in 16B units. Even values indicate 16B
9865 * records. Odd values indicate 32B
9868 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
9870 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
9872 /* HWRM Asynchronous Event Information */
9873 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9875 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
9876 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9877 /* Identifiers of events. */
9879 /* Port PHY configuration change */
9880 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
9882 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
9883 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
9884 /* Event specific data */
9885 uint32_t event_data2;
9888 * This value is written by the NIC such that it will be different
9889 * for each pass through the completion queue. The even passes
9890 * will write 1. The odd passes will write 0.
9892 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
9895 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
9897 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
9898 /* 8-lsb timestamp from POR (100-msec resolution) */
9899 uint8_t timestamp_lo;
9900 /* 16-lsb timestamp from POR (100-msec resolution) */
9901 uint16_t timestamp_hi;
9902 /* Event specific data */
9903 uint32_t event_data1;
9905 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9907 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9910 * If set to 1, it indicates that the FEC
9911 * configuration on the port has changed.
9912 * If set to 0, then there is no change in FEC configuration.
9914 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
9917 * If set to 1, it indicates that the EEE configuration
9918 * on the port has changed.
9919 * If set to 0, then there is no change in EEE configuration
9922 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
9925 * If set to 1, it indicates that the pause configuration
9926 * on the PHY has changed.
9927 * If set to 0, then there is no change in the pause
9928 * configuration on the PHY.
9930 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
9934 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
9935 struct hwrm_async_event_cmpl_reset_notify {
9938 * This field indicates the exact type of the completion.
9939 * By convention, the LSB identifies the length of the
9940 * record in 16B units. Even values indicate 16B
9941 * records. Odd values indicate 32B
9944 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
9946 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
9947 /* HWRM Asynchronous Event Information */
9948 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
9950 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
9951 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
9952 /* Identifiers of events. */
9954 /* Notify clients of imminent reset. */
9955 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
9957 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
9958 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
9959 /* Event specific data. The data is for internal debug use only. */
9960 uint32_t event_data2;
9962 * These bits indicate the status as being reported by the firmware.
9963 * This value is exactly the same as status code in fw_status register.
9964 * If the status code is equal to 0x8000, then the reset is initiated
9965 * by the Host using the FW_RESET command when the FW is in a healthy
9966 * state. If the status code is not equal to 0x8000, then the reset is
9967 * initiated by the FW to recover from the error or FATAL state.
9969 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
9971 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
9975 * This value is written by the NIC such that it will be different
9976 * for each pass through the completion queue. The even passes
9977 * will write 1. The odd passes will write 0.
9979 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
9981 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
9982 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
9984 * 8-lsb timestamp (100-msec resolution)
9985 * The Minimum time required for the Firmware readiness after sending
9986 * this notification to the driver instances.
9988 uint8_t timestamp_lo;
9990 * 16-lsb timestamp (100-msec resolution)
9991 * The Maximum Firmware Reset bail out value in the order of 100
9992 * milliseconds. The driver instances will use this value to reinitiate
9993 * the registration process again if the core firmware didn’t set the
9996 uint16_t timestamp_hi;
9997 /* Event specific data */
9998 uint32_t event_data1;
9999 /* Indicates driver action requested */
10000 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
10002 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
10005 * If set to 1, it indicates that the l2 client should
10006 * stop sending in band traffic to Nitro.
10007 * if set to 0, there is no change in L2 client behavior.
10009 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
10012 * If set to 1, it indicates that the L2 client should
10013 * bring down the interface.
10014 * If set to 0, then there is no change in L2 client behavior.
10016 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
10018 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
10019 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
10020 /* Indicates reason for reset. */
10021 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
10023 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
10025 /* A management client has requested reset. */
10026 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
10027 (UINT32_C(0x1) << 8)
10028 /* A fatal firmware exception has occurred. */
10029 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
10030 (UINT32_C(0x2) << 8)
10031 /* A non-fatal firmware exception has occurred. */
10032 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
10033 (UINT32_C(0x3) << 8)
10035 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
10036 (UINT32_C(0x4) << 8)
10038 * Reset was a result of a firmware activation. That is, the
10039 * fw_activation flag was set in a FW_RESET operation.
10041 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \
10042 (UINT32_C(0x5) << 8)
10043 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
10044 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
10046 * Minimum time before driver should attempt access - units 100ms
10050 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
10051 UINT32_C(0xffff0000)
10052 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
10056 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
10057 struct hwrm_async_event_cmpl_error_recovery {
10060 * This field indicates the exact type of the completion.
10061 * By convention, the LSB identifies the length of the
10062 * record in 16B units. Even values indicate 16B
10063 * records. Odd values indicate 32B
10066 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
10068 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
10069 /* HWRM Asynchronous Event Information */
10070 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
10072 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
10073 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
10074 /* Identifiers of events. */
10077 * This async notification message can be used for selecting or
10078 * deselecting master function for error recovery,
10079 * and to communicate to all the functions whether error recovery
10080 * was enabled/disabled.
10082 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
10084 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
10085 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
10086 /* Event specific data */
10087 uint32_t event_data2;
10090 * This value is written by the NIC such that it will be different
10091 * for each pass through the completion queue. The even passes
10092 * will write 1. The odd passes will write 0.
10094 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
10095 /* opaque is 7 b */
10096 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
10097 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
10098 /* 8-lsb timestamp (100-msec resolution) */
10099 uint8_t timestamp_lo;
10100 /* 16-lsb timestamp (100-msec resolution) */
10101 uint16_t timestamp_hi;
10102 /* Event specific data */
10103 uint32_t event_data1;
10104 /* Indicates driver action requested */
10105 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
10107 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
10110 * If set to 1, this function is selected as Master function.
10111 * This function has responsibility to do 'chip reset' when it
10112 * detects a fatal error. If set to 0, master function functionality
10113 * is disabled on this function.
10115 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
10118 * If set to 1, error recovery is enabled.
10119 * If set to 0, error recovery is disabled.
10121 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
10125 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
10126 struct hwrm_async_event_cmpl_ring_monitor_msg {
10129 * This field indicates the exact type of the completion.
10130 * By convention, the LSB identifies the length of the
10131 * record in 16B units. Even values indicate 16B
10132 * records. Odd values indicate 32B
10135 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
10137 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
10138 /* HWRM Asynchronous Event Information */
10139 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
10141 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
10142 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
10143 /* Identifiers of events. */
10145 /* Ring Monitor Message. */
10146 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
10148 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
10149 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
10150 /* Event specific data */
10151 uint32_t event_data2;
10152 /* Type of Ring disabled. */
10153 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
10155 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
10157 /* tx ring disabled. */
10158 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
10160 /* rx ring disabled. */
10161 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
10163 /* cmpl ring disabled. */
10164 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
10166 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
10167 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
10170 * This value is written by the NIC such that it will be different
10171 * for each pass through the completion queue. The even passes
10172 * will write 1. The odd passes will write 0.
10174 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
10175 /* opaque is 7 b */
10176 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
10178 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
10179 /* 8-lsb timestamp from POR (100-msec resolution) */
10180 uint8_t timestamp_lo;
10181 /* 16-lsb timestamp from POR (100-msec resolution) */
10182 uint16_t timestamp_hi;
10184 * Event specific data. If ring_type_disabled indicates a tx, rx or cmpl
10185 * then this field will indicate the ring id.
10187 uint32_t event_data1;
10190 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
10191 struct hwrm_async_event_cmpl_func_drvr_unload {
10194 * This field indicates the exact type of the completion.
10195 * By convention, the LSB identifies the length of the
10196 * record in 16B units. Even values indicate 16B
10197 * records. Odd values indicate 32B
10200 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
10202 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
10203 /* HWRM Asynchronous Event Information */
10204 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
10206 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
10207 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
10208 /* Identifiers of events. */
10210 /* Function driver unloaded */
10211 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
10213 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
10214 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
10215 /* Event specific data */
10216 uint32_t event_data2;
10219 * This value is written by the NIC such that it will be different
10220 * for each pass through the completion queue. The even passes
10221 * will write 1. The odd passes will write 0.
10223 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
10224 /* opaque is 7 b */
10225 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
10227 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
10228 /* 8-lsb timestamp from POR (100-msec resolution) */
10229 uint8_t timestamp_lo;
10230 /* 16-lsb timestamp from POR (100-msec resolution) */
10231 uint16_t timestamp_hi;
10232 /* Event specific data */
10233 uint32_t event_data1;
10235 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
10237 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
10241 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
10242 struct hwrm_async_event_cmpl_func_drvr_load {
10245 * This field indicates the exact type of the completion.
10246 * By convention, the LSB identifies the length of the
10247 * record in 16B units. Even values indicate 16B
10248 * records. Odd values indicate 32B
10251 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
10253 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
10254 /* HWRM Asynchronous Event Information */
10255 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
10257 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
10258 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
10259 /* Identifiers of events. */
10261 /* Function driver loaded */
10262 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
10264 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
10265 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
10266 /* Event specific data */
10267 uint32_t event_data2;
10270 * This value is written by the NIC such that it will be different
10271 * for each pass through the completion queue. The even passes
10272 * will write 1. The odd passes will write 0.
10274 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
10275 /* opaque is 7 b */
10276 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10277 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
10278 /* 8-lsb timestamp from POR (100-msec resolution) */
10279 uint8_t timestamp_lo;
10280 /* 16-lsb timestamp from POR (100-msec resolution) */
10281 uint16_t timestamp_hi;
10282 /* Event specific data */
10283 uint32_t event_data1;
10285 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
10287 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10290 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
10291 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
10294 * This field indicates the exact type of the completion.
10295 * By convention, the LSB identifies the length of the
10296 * record in 16B units. Even values indicate 16B
10297 * records. Odd values indicate 32B
10300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
10302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
10304 /* HWRM Asynchronous Event Information */
10305 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
10307 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
10308 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
10309 /* Identifiers of events. */
10311 /* Function FLR related processing has completed */
10312 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
10314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
10315 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
10316 /* Event specific data */
10317 uint32_t event_data2;
10320 * This value is written by the NIC such that it will be different
10321 * for each pass through the completion queue. The even passes
10322 * will write 1. The odd passes will write 0.
10324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
10326 /* opaque is 7 b */
10327 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
10329 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
10330 /* 8-lsb timestamp from POR (100-msec resolution) */
10331 uint8_t timestamp_lo;
10332 /* 16-lsb timestamp from POR (100-msec resolution) */
10333 uint16_t timestamp_hi;
10334 /* Event specific data */
10335 uint32_t event_data1;
10337 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
10339 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
10343 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
10344 struct hwrm_async_event_cmpl_pf_drvr_unload {
10347 * This field indicates the exact type of the completion.
10348 * By convention, the LSB identifies the length of the
10349 * record in 16B units. Even values indicate 16B
10350 * records. Odd values indicate 32B
10353 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
10355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
10356 /* HWRM Asynchronous Event Information */
10357 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
10359 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
10360 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
10361 /* Identifiers of events. */
10363 /* PF driver unloaded */
10364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
10366 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
10367 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
10368 /* Event specific data */
10369 uint32_t event_data2;
10372 * This value is written by the NIC such that it will be different
10373 * for each pass through the completion queue. The even passes
10374 * will write 1. The odd passes will write 0.
10376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
10377 /* opaque is 7 b */
10378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
10379 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
10380 /* 8-lsb timestamp from POR (100-msec resolution) */
10381 uint8_t timestamp_lo;
10382 /* 16-lsb timestamp from POR (100-msec resolution) */
10383 uint16_t timestamp_hi;
10384 /* Event specific data */
10385 uint32_t event_data1;
10387 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
10389 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
10390 /* Indicates the physical port this pf belongs to */
10391 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
10393 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
10396 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
10397 struct hwrm_async_event_cmpl_pf_drvr_load {
10400 * This field indicates the exact type of the completion.
10401 * By convention, the LSB identifies the length of the
10402 * record in 16B units. Even values indicate 16B
10403 * records. Odd values indicate 32B
10406 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
10408 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
10409 /* HWRM Asynchronous Event Information */
10410 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
10412 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
10413 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
10414 /* Identifiers of events. */
10416 /* PF driver loaded */
10417 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
10419 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
10420 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
10421 /* Event specific data */
10422 uint32_t event_data2;
10425 * This value is written by the NIC such that it will be different
10426 * for each pass through the completion queue. The even passes
10427 * will write 1. The odd passes will write 0.
10429 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
10430 /* opaque is 7 b */
10431 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10432 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
10433 /* 8-lsb timestamp from POR (100-msec resolution) */
10434 uint8_t timestamp_lo;
10435 /* 16-lsb timestamp from POR (100-msec resolution) */
10436 uint16_t timestamp_hi;
10437 /* Event specific data */
10438 uint32_t event_data1;
10440 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
10442 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10443 /* Indicates the physical port this pf belongs to */
10444 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
10446 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
10449 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
10450 struct hwrm_async_event_cmpl_vf_flr {
10453 * This field indicates the exact type of the completion.
10454 * By convention, the LSB identifies the length of the
10455 * record in 16B units. Even values indicate 16B
10456 * records. Odd values indicate 32B
10459 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
10461 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
10462 /* HWRM Asynchronous Event Information */
10463 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
10465 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
10466 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
10467 /* Identifiers of events. */
10469 /* VF Function Level Reset (FLR) */
10470 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
10471 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
10472 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
10473 /* Event specific data */
10474 uint32_t event_data2;
10477 * This value is written by the NIC such that it will be different
10478 * for each pass through the completion queue. The even passes
10479 * will write 1. The odd passes will write 0.
10481 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
10482 /* opaque is 7 b */
10483 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
10484 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
10485 /* 8-lsb timestamp from POR (100-msec resolution) */
10486 uint8_t timestamp_lo;
10487 /* 16-lsb timestamp from POR (100-msec resolution) */
10488 uint16_t timestamp_hi;
10489 /* Event specific data */
10490 uint32_t event_data1;
10492 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
10494 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
10495 /* Indicates the physical function this event occurred on. */
10496 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
10498 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
10501 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
10502 struct hwrm_async_event_cmpl_vf_mac_addr_change {
10505 * This field indicates the exact type of the completion.
10506 * By convention, the LSB identifies the length of the
10507 * record in 16B units. Even values indicate 16B
10508 * records. Odd values indicate 32B
10511 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
10513 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
10514 /* HWRM Asynchronous Event Information */
10515 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
10517 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
10518 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
10519 /* Identifiers of events. */
10521 /* VF MAC Address Change */
10522 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
10524 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
10525 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
10526 /* Event specific data */
10527 uint32_t event_data2;
10530 * This value is written by the NIC such that it will be different
10531 * for each pass through the completion queue. The even passes
10532 * will write 1. The odd passes will write 0.
10534 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
10536 /* opaque is 7 b */
10537 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
10539 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
10540 /* 8-lsb timestamp from POR (100-msec resolution) */
10541 uint8_t timestamp_lo;
10542 /* 16-lsb timestamp from POR (100-msec resolution) */
10543 uint16_t timestamp_hi;
10544 /* Event specific data */
10545 uint32_t event_data1;
10547 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
10549 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
10553 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
10554 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
10557 * This field indicates the exact type of the completion.
10558 * By convention, the LSB identifies the length of the
10559 * record in 16B units. Even values indicate 16B
10560 * records. Odd values indicate 32B
10563 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
10565 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
10567 /* HWRM Asynchronous Event Information */
10568 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
10570 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
10571 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
10572 /* Identifiers of events. */
10574 /* PF-VF communication channel status change. */
10575 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
10577 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
10578 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
10579 /* Event specific data */
10580 uint32_t event_data2;
10583 * This value is written by the NIC such that it will be different
10584 * for each pass through the completion queue. The even passes
10585 * will write 1. The odd passes will write 0.
10587 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
10589 /* opaque is 7 b */
10590 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
10592 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
10593 /* 8-lsb timestamp from POR (100-msec resolution) */
10594 uint8_t timestamp_lo;
10595 /* 16-lsb timestamp from POR (100-msec resolution) */
10596 uint16_t timestamp_hi;
10597 /* Event specific data */
10598 uint32_t event_data1;
10600 * If this bit is set to 1, then it indicates that the PF-VF
10601 * communication was lost and it is established.
10602 * If this bit set to 0, then it indicates that the PF-VF
10603 * communication was established and it is lost.
10605 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
10609 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
10610 struct hwrm_async_event_cmpl_vf_cfg_change {
10613 * This field indicates the exact type of the completion.
10614 * By convention, the LSB identifies the length of the
10615 * record in 16B units. Even values indicate 16B
10616 * records. Odd values indicate 32B
10619 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
10621 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
10622 /* HWRM Asynchronous Event Information */
10623 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
10625 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
10626 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
10627 /* Identifiers of events. */
10629 /* VF Configuration Change */
10630 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
10632 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
10633 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
10634 /* Event specific data */
10635 uint32_t event_data2;
10637 * This value indicates the VF ID of the VF whose configuration
10638 * is changing if this async. event is sent to the parent PF.
10639 * The firmware supports sending this to the parent PF if the
10640 * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1.
10641 * This value is undefined when the async. event is sent to the
10644 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \
10646 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
10649 * This value is written by the NIC such that it will be different
10650 * for each pass through the completion queue. The even passes
10651 * will write 1. The odd passes will write 0.
10653 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
10654 /* opaque is 7 b */
10655 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10656 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
10657 /* 8-lsb timestamp from POR (100-msec resolution) */
10658 uint8_t timestamp_lo;
10659 /* 16-lsb timestamp from POR (100-msec resolution) */
10660 uint16_t timestamp_hi;
10662 * Each flag provided in this field indicates a specific VF
10663 * configuration change. At least one of these flags shall be set to 1
10664 * when an asynchronous event completion of this type is provided
10667 uint32_t event_data1;
10669 * If this bit is set to 1, then the value of MTU
10670 * was changed on this VF.
10671 * If set to 0, then this bit should be ignored.
10673 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
10676 * If this bit is set to 1, then the value of MRU
10677 * was changed on this VF.
10678 * If set to 0, then this bit should be ignored.
10680 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
10683 * If this bit is set to 1, then the value of default MAC
10684 * address was changed on this VF.
10685 * If set to 0, then this bit should be ignored.
10687 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
10690 * If this bit is set to 1, then the value of default VLAN
10691 * was changed on this VF.
10692 * If set to 0, then this bit should be ignored.
10694 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
10697 * If this bit is set to 1, then the value of trusted VF enable
10698 * was changed on this VF.
10699 * If set to 0, then this bit should be ignored.
10701 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
10705 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
10706 struct hwrm_async_event_cmpl_llfc_pfc_change {
10709 * This field indicates the exact type of the completion.
10710 * By convention, the LSB identifies the length of the
10711 * record in 16B units. Even values indicate 16B
10712 * records. Odd values indicate 32B
10715 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
10717 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
10718 /* HWRM Asynchronous Event Information */
10719 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
10721 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
10722 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
10723 /* unused1 is 10 b */
10724 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
10726 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
10727 /* Identifiers of events. */
10729 /* LLFC/PFC Configuration Change */
10730 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
10732 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
10733 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
10734 /* Event specific data */
10735 uint32_t event_data2;
10738 * This value is written by the NIC such that it will be different
10739 * for each pass through the completion queue. The even passes
10740 * will write 1. The odd passes will write 0.
10742 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
10743 /* opaque is 7 b */
10744 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
10746 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
10747 /* 8-lsb timestamp from POR (100-msec resolution) */
10748 uint8_t timestamp_lo;
10749 /* 16-lsb timestamp from POR (100-msec resolution) */
10750 uint16_t timestamp_hi;
10751 /* Event specific data */
10752 uint32_t event_data1;
10753 /* Indicates llfc pfc status change */
10754 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
10756 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
10759 * If this field set to 1, then it indicates that llfc is
10762 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
10765 * If this field is set to 2, then it indicates that pfc
10768 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
10770 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
10771 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
10772 /* Indicates the physical port this llfc pfc change occur */
10773 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
10775 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
10778 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
10780 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
10784 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
10785 struct hwrm_async_event_cmpl_default_vnic_change {
10788 * This field indicates the exact type of the completion.
10789 * By convention, the LSB identifies the length of the
10790 * record in 16B units. Even values indicate 16B
10791 * records. Odd values indicate 32B
10794 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
10796 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
10798 /* HWRM Asynchronous Event Information */
10799 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
10801 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
10802 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
10803 /* unused1 is 10 b */
10804 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
10806 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
10808 /* Identifiers of events. */
10810 /* Notification of a default vnic allocation or free */
10811 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
10813 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
10814 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
10815 /* Event specific data */
10816 uint32_t event_data2;
10819 * This value is written by the NIC such that it will be different
10820 * for each pass through the completion queue. The even passes
10821 * will write 1. The odd passes will write 0.
10823 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
10825 /* opaque is 7 b */
10826 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
10828 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
10829 /* 8-lsb timestamp from POR (100-msec resolution) */
10830 uint8_t timestamp_lo;
10831 /* 16-lsb timestamp from POR (100-msec resolution) */
10832 uint16_t timestamp_hi;
10833 /* Event specific data */
10834 uint32_t event_data1;
10835 /* Indicates default vnic configuration change */
10836 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
10838 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
10841 * If this field is set to 1, then it indicates that
10842 * a default VNIC has been allocate.
10844 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
10847 * If this field is set to 2, then it indicates that
10848 * a default VNIC has been freed.
10850 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
10852 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
10853 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
10854 /* Indicates the physical function this event occurred on. */
10855 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
10857 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
10859 /* Indicates the virtual function this event occurred on */
10860 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
10861 UINT32_C(0x3fffc00)
10862 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
10866 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
10867 struct hwrm_async_event_cmpl_hw_flow_aged {
10870 * This field indicates the exact type of the completion.
10871 * By convention, the LSB identifies the length of the
10872 * record in 16B units. Even values indicate 16B
10873 * records. Odd values indicate 32B
10876 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
10878 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
10879 /* HWRM Asynchronous Event Information */
10880 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
10882 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
10883 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
10884 /* Identifiers of events. */
10886 /* Notification of a hw flow aged */
10887 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
10889 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
10890 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
10891 /* Event specific data */
10892 uint32_t event_data2;
10895 * This value is written by the NIC such that it will be different
10896 * for each pass through the completion queue. The even passes
10897 * will write 1. The odd passes will write 0.
10899 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
10900 /* opaque is 7 b */
10901 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
10902 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
10903 /* 8-lsb timestamp from POR (100-msec resolution) */
10904 uint8_t timestamp_lo;
10905 /* 16-lsb timestamp from POR (100-msec resolution) */
10906 uint16_t timestamp_hi;
10907 /* Event specific data */
10908 uint32_t event_data1;
10909 /* Indicates flow ID this event occurred on. */
10910 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
10911 UINT32_C(0x7fffffff)
10912 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
10914 /* Indicates flow direction this event occurred on. */
10915 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
10916 UINT32_C(0x80000000)
10918 * If this bit set to 0, then it indicates that the aged
10919 * event was rx flow.
10921 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
10922 (UINT32_C(0x0) << 31)
10924 * If this bit is set to 1, then it indicates that the aged
10925 * event was tx flow.
10927 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
10928 (UINT32_C(0x1) << 31)
10929 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
10930 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
10933 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
10934 struct hwrm_async_event_cmpl_eem_cache_flush_req {
10937 * This field indicates the exact type of the completion.
10938 * By convention, the LSB identifies the length of the
10939 * record in 16B units. Even values indicate 16B
10940 * records. Odd values indicate 32B
10943 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
10945 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
10947 /* HWRM Asynchronous Event Information */
10948 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
10950 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
10951 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
10952 /* Identifiers of events. */
10954 /* Notification of a eem_cache_flush request */
10955 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
10957 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
10958 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
10959 /* Event specific data */
10960 uint32_t event_data2;
10963 * This value is written by the NIC such that it will be different
10964 * for each pass through the completion queue. The even passes
10965 * will write 1. The odd passes will write 0.
10967 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
10969 /* opaque is 7 b */
10970 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
10972 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
10973 /* 8-lsb timestamp from POR (100-msec resolution) */
10974 uint8_t timestamp_lo;
10975 /* 16-lsb timestamp from POR (100-msec resolution) */
10976 uint16_t timestamp_hi;
10977 /* Event specific data */
10978 uint32_t event_data1;
10981 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
10982 struct hwrm_async_event_cmpl_eem_cache_flush_done {
10985 * This field indicates the exact type of the completion.
10986 * By convention, the LSB identifies the length of the
10987 * record in 16B units. Even values indicate 16B
10988 * records. Odd values indicate 32B
10991 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
10993 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
10995 /* HWRM Asynchronous Event Information */
10996 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
10998 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
10999 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
11000 /* Identifiers of events. */
11003 * Notification of a host eem_cache_flush has completed. This event
11004 * is generated by the host driver.
11006 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
11008 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
11009 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
11010 /* Event specific data */
11011 uint32_t event_data2;
11014 * This value is written by the NIC such that it will be different
11015 * for each pass through the completion queue. The even passes
11016 * will write 1. The odd passes will write 0.
11018 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
11020 /* opaque is 7 b */
11021 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
11023 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
11024 /* 8-lsb timestamp from POR (100-msec resolution) */
11025 uint8_t timestamp_lo;
11026 /* 16-lsb timestamp from POR (100-msec resolution) */
11027 uint16_t timestamp_hi;
11028 /* Event specific data */
11029 uint32_t event_data1;
11030 /* Indicates function ID that this event occurred on. */
11031 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
11033 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
11037 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
11038 struct hwrm_async_event_cmpl_tcp_flag_action_change {
11041 * This field indicates the exact type of the completion.
11042 * By convention, the LSB identifies the length of the
11043 * record in 16B units. Even values indicate 16B
11044 * records. Odd values indicate 32B
11047 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
11049 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
11051 /* HWRM Asynchronous Event Information */
11052 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
11054 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
11055 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
11056 /* Identifiers of events. */
11058 /* Notification of tcp flag action change */
11059 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
11061 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
11062 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
11063 /* Event specific data */
11064 uint32_t event_data2;
11067 * This value is written by the NIC such that it will be different
11068 * for each pass through the completion queue. The even passes
11069 * will write 1. The odd passes will write 0.
11071 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
11073 /* opaque is 7 b */
11074 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
11076 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
11077 /* 8-lsb timestamp from POR (100-msec resolution) */
11078 uint8_t timestamp_lo;
11079 /* 16-lsb timestamp from POR (100-msec resolution) */
11080 uint16_t timestamp_hi;
11081 /* Event specific data */
11082 uint32_t event_data1;
11085 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
11086 struct hwrm_async_event_cmpl_eem_flow_active {
11089 * This field indicates the exact type of the completion.
11090 * By convention, the LSB identifies the length of the
11091 * record in 16B units. Even values indicate 16B
11092 * records. Odd values indicate 32B
11095 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
11097 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
11098 /* HWRM Asynchronous Event Information */
11099 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
11101 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
11102 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
11103 /* Identifiers of events. */
11105 /* Notification of an active eem flow */
11106 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
11108 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
11109 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
11110 /* Event specific data */
11111 uint32_t event_data2;
11112 /* Indicates the 2nd global id this event occurred on. */
11113 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
11114 UINT32_C(0x3fffffff)
11115 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
11118 * Indicates flow direction of the flow identified by
11121 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
11122 UINT32_C(0x40000000)
11123 /* If this bit is set to 0, then it indicates that this rx flow. */
11124 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
11125 (UINT32_C(0x0) << 30)
11126 /* If this bit is set to 1, then it indicates that this tx flow. */
11127 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
11128 (UINT32_C(0x1) << 30)
11129 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
11130 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
11133 * This value is written by the NIC such that it will be different
11134 * for each pass through the completion queue. The even passes
11135 * will write 1. The odd passes will write 0.
11137 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
11138 /* opaque is 7 b */
11139 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
11141 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
11142 /* 8-lsb timestamp from POR (100-msec resolution) */
11143 uint8_t timestamp_lo;
11144 /* 16-lsb timestamp from POR (100-msec resolution) */
11145 uint16_t timestamp_hi;
11146 /* Event specific data */
11147 uint32_t event_data1;
11148 /* Indicates the 1st global id this event occurred on. */
11149 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
11150 UINT32_C(0x3fffffff)
11151 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
11154 * Indicates flow direction of the flow identified by the
11157 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
11158 UINT32_C(0x40000000)
11159 /* If this bit is set to 0, then it indicates that this is rx flow. */
11160 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
11161 (UINT32_C(0x0) << 30)
11162 /* If this bit is set to 1, then it indicates that this is tx flow. */
11163 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
11164 (UINT32_C(0x1) << 30)
11165 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
11166 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
11168 * Indicates EEM flow aging mode this event occurred on. If
11169 * this bit is set to 0, the event_data1 is the EEM global
11170 * ID. If this bit is set to 1, the event_data1 is the number
11171 * of global ID in the context memory.
11173 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
11174 UINT32_C(0x80000000)
11175 /* EEM flow aging mode 0. */
11176 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
11177 (UINT32_C(0x0) << 31)
11178 /* EEM flow aging mode 1. */
11179 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
11180 (UINT32_C(0x1) << 31)
11181 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
11182 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
11185 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
11186 struct hwrm_async_event_cmpl_eem_cfg_change {
11189 * This field indicates the exact type of the completion.
11190 * By convention, the LSB identifies the length of the
11191 * record in 16B units. Even values indicate 16B
11192 * records. Odd values indicate 32B
11195 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
11197 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
11198 /* HWRM Asynchronous Event Information */
11199 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
11201 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
11202 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
11203 /* Identifiers of events. */
11205 /* Notification of EEM configuration change */
11206 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
11208 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
11209 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
11210 /* Event specific data */
11211 uint32_t event_data2;
11214 * This value is written by the NIC such that it will be different
11215 * for each pass through the completion queue. The even passes
11216 * will write 1. The odd passes will write 0.
11218 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
11219 /* opaque is 7 b */
11220 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11221 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
11222 /* 8-lsb timestamp from POR (100-msec resolution) */
11223 uint8_t timestamp_lo;
11224 /* 16-lsb timestamp from POR (100-msec resolution) */
11225 uint16_t timestamp_hi;
11226 /* Event specific data */
11227 uint32_t event_data1;
11229 * Value of 1 to indicate EEM TX configuration is enabled. Value of
11230 * 0 to indicate the EEM TX configuration is disabled.
11232 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
11235 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
11236 * to indicate the EEM RX configuration is disabled.
11238 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
11242 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
11243 struct hwrm_async_event_cmpl_quiesce_done {
11246 * This field indicates the exact type of the completion.
11247 * By convention, the LSB identifies the length of the
11248 * record in 16B units. Even values indicate 16B
11249 * records. Odd values indicate 32B
11252 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
11254 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
11255 /* HWRM Asynchronous Event Information */
11256 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
11258 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
11259 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
11260 /* Identifiers of events. */
11262 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
11263 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
11265 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
11266 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
11267 /* Event specific data */
11268 uint32_t event_data2;
11269 /* Status of HWRM_FW_STATE_QUIESCE completion */
11270 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
11272 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
11275 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
11276 * completed successfully.
11278 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
11281 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
11284 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
11287 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
11288 * encountered an error.
11290 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
11292 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
11293 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
11294 /* opaque is 8 b */
11295 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
11297 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
11300 * Additional information about internal hardware state related to
11301 * idle/quiesce state. QUIESCE may succeed per quiesce_status
11302 * regardless of idle_state_flags. If QUIESCE fails, the host may
11303 * inspect idle_state_flags to determine whether a retry is warranted.
11305 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
11307 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
11310 * Failure to quiesce is caused by host not updating the NQ consumer
11313 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
11315 /* Flag 1 indicating partial non-idle state. */
11316 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
11318 /* Flag 2 indicating partial non-idle state. */
11319 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
11321 /* Flag 3 indicating partial non-idle state. */
11322 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
11326 * This value is written by the NIC such that it will be different
11327 * for each pass through the completion queue. The even passes
11328 * will write 1. The odd passes will write 0.
11330 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
11331 /* opaque is 7 b */
11332 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
11333 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
11334 /* 8-lsb timestamp from POR (100-msec resolution) */
11335 uint8_t timestamp_lo;
11336 /* 16-lsb timestamp from POR (100-msec resolution) */
11337 uint16_t timestamp_hi;
11338 /* Event specific data */
11339 uint32_t event_data1;
11340 /* Time stamp for error event */
11341 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
11345 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
11346 struct hwrm_async_event_cmpl_deferred_response {
11349 * This field indicates the exact type of the completion.
11350 * By convention, the LSB identifies the length of the
11351 * record in 16B units. Even values indicate 16B
11352 * records. Odd values indicate 32B
11355 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
11357 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
11358 /* HWRM Asynchronous Event Information */
11359 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
11361 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
11362 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
11363 /* Identifiers of events. */
11366 * An event signifying a HWRM command is in progress and its
11367 * response will be deferred
11369 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
11371 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
11372 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
11373 /* Event specific data */
11374 uint32_t event_data2;
11376 * The PF's mailbox is clear to issue another command.
11377 * A command with this seq_id is still in progress
11378 * and will return a regular HWRM completion when done.
11379 * 'event_data1' field, if non-zero, contains the estimated
11380 * execution time for the command.
11382 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
11384 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
11388 * This value is written by the NIC such that it will be different
11389 * for each pass through the completion queue. The even passes
11390 * will write 1. The odd passes will write 0.
11392 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
11394 /* opaque is 7 b */
11395 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
11397 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
11398 /* 8-lsb timestamp from POR (100-msec resolution) */
11399 uint8_t timestamp_lo;
11400 /* 16-lsb timestamp from POR (100-msec resolution) */
11401 uint16_t timestamp_hi;
11402 /* Estimated remaining time of command execution in ms (if not zero) */
11403 uint32_t event_data1;
11406 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
11407 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
11410 * This field indicates the exact type of the completion.
11411 * By convention, the LSB identifies the length of the
11412 * record in 16B units. Even values indicate 16B
11413 * records. Odd values indicate 32B
11416 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
11418 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
11420 /* HWRM Asynchronous Event Information */
11421 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
11423 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
11424 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
11425 /* Identifiers of events. */
11427 /* PFC watchdog configuration change for given port/cos */
11428 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
11430 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
11431 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
11432 /* Event specific data */
11433 uint32_t event_data2;
11436 * This value is written by the NIC such that it will be different
11437 * for each pass through the completion queue. The even passes
11438 * will write 1. The odd passes will write 0.
11440 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
11442 /* opaque is 7 b */
11443 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
11445 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
11446 /* 8-lsb timestamp from POR (100-msec resolution) */
11447 uint8_t timestamp_lo;
11448 /* 16-lsb timestamp from POR (100-msec resolution) */
11449 uint16_t timestamp_hi;
11450 /* Event specific data */
11451 uint32_t event_data1;
11453 * 1 in bit position X indicates PFC watchdog should
11456 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
11458 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
11460 /* 1 means PFC WD for COS0 is on, 0 - off. */
11461 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
11463 /* 1 means PFC WD for COS1 is on, 0 - off. */
11464 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
11466 /* 1 means PFC WD for COS2 is on, 0 - off. */
11467 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
11469 /* 1 means PFC WD for COS3 is on, 0 - off. */
11470 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
11472 /* 1 means PFC WD for COS4 is on, 0 - off. */
11473 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
11475 /* 1 means PFC WD for COS5 is on, 0 - off. */
11476 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
11478 /* 1 means PFC WD for COS6 is on, 0 - off. */
11479 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
11481 /* 1 means PFC WD for COS7 is on, 0 - off. */
11482 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
11485 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
11487 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
11491 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
11492 struct hwrm_async_event_cmpl_echo_request {
11495 * This field indicates the exact type of the completion.
11496 * By convention, the LSB identifies the length of the
11497 * record in 16B units. Even values indicate 16B
11498 * records. Odd values indicate 32B
11501 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
11503 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
11504 /* HWRM Asynchronous Event Information */
11505 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
11507 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
11508 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
11509 /* Identifiers of events. */
11512 * An echo request from the firmware. An echo response is expected by
11515 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
11517 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
11518 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
11519 /* Event specific data that should be provided in the echo response */
11520 uint32_t event_data2;
11523 * This value is written by the NIC such that it will be different
11524 * for each pass through the completion queue. The even passes
11525 * will write 1. The odd passes will write 0.
11527 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
11528 /* opaque is 7 b */
11529 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
11530 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
11531 /* 8-lsb timestamp from POR (100-msec resolution) */
11532 uint8_t timestamp_lo;
11533 /* 16-lsb timestamp from POR (100-msec resolution) */
11534 uint16_t timestamp_hi;
11535 /* Event specific data that should be provided in the echo response */
11536 uint32_t event_data1;
11539 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
11540 struct hwrm_async_event_cmpl_phc_update {
11543 * This field indicates the exact type of the completion.
11544 * By convention, the LSB identifies the length of the
11545 * record in 16B units. Even values indicate 16B
11546 * records. Odd values indicate 32B
11549 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK \
11551 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
11552 /* HWRM Asynchronous Event Information */
11553 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT \
11555 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST \
11556 HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
11557 /* Identifiers of events. */
11560 * This async event is used to notify driver of changes
11561 * in PHC master. Only one master function can configure
11564 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE \
11566 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST \
11567 HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
11568 /* Event specific data */
11569 uint32_t event_data2;
11570 /* This field provides the current master function. */
11571 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK \
11573 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT \
11575 /* This field provides the current secondary function. */
11576 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK \
11577 UINT32_C(0xffff0000)
11578 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT \
11582 * This value is written by the NIC such that it will be different
11583 * for each pass through the completion queue. The even passes
11584 * will write 1. The odd passes will write 0.
11586 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V UINT32_C(0x1)
11587 /* opaque is 7 b */
11588 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
11589 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
11590 /* 8-lsb timestamp (100-msec resolution) */
11591 uint8_t timestamp_lo;
11592 /* 16-lsb timestamp (100-msec resolution) */
11593 uint16_t timestamp_hi;
11594 /* Event specific data */
11595 uint32_t event_data1;
11596 /* Indicates to the driver the type of PHC event. */
11597 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK \
11599 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT \
11602 * Indicates PHC Master selection event. The master fid is
11603 * specified in event_data2.phc_master_fid.
11605 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER \
11608 * Indicates PHC Secondary selection event. The secondary fid is
11609 * specified in event_data2.phc_sec_fid.
11611 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY \
11614 * Indicates PHC failover event. Failover happens from
11615 * event_data2.phc_master_fid to event_data2.phc_sec_fid.
11617 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER \
11620 * Indicates that the 64bit Real time clock upper 16bits
11621 * have been updated due to PHC rollover. The updated
11622 * upper 16bits is in event_data1.phc_time_msb
11624 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE \
11626 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST \
11627 HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
11629 * This field provides the upper 16bits of the 64bit real
11632 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK \
11634 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT \
11638 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
11639 struct hwrm_async_event_cmpl_pps_timestamp {
11642 * This field indicates the exact type of the completion.
11643 * By convention, the LSB identifies the length of the
11644 * record in 16B units. Even values indicate 16B
11645 * records. Odd values indicate 32B
11648 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \
11650 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
11651 /* HWRM Asynchronous Event Information */
11652 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \
11654 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \
11655 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
11656 /* Identifiers of events. */
11659 * This async notification message can be used to inform
11660 * driver of the latest PPS timestamp that has been latched.
11661 * When driver enables PPS event, Firmware will generate
11662 * PPS timestamps every second, Firmware informs driver
11663 * of this timestamp through the async event.
11665 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \
11667 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \
11668 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
11669 /* Event specific data */
11670 uint32_t event_data2;
11671 /* Indicates the PPS event type */
11672 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \
11674 /* This is an internal event. */
11675 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \
11677 /* This is an external event. */
11678 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \
11680 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \
11681 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
11683 * Indicates the pin number on which the event is
11686 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \
11688 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \
11691 * Contains bits[47:32] of the upper PPS timestamp.
11692 * Lower 32 bits are in event_data1. Together they
11693 * provide the 48 bit PPS timestamp.
11695 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \
11697 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \
11701 * This value is written by the NIC such that it will be different
11702 * for each pass through the completion queue. The even passes
11703 * will write 1. The odd passes will write 0.
11705 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
11706 /* opaque is 7 b */
11707 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
11708 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
11709 /* 8-lsb timestamp (100-msec resolution) */
11710 uint8_t timestamp_lo;
11711 /* 16-lsb timestamp (100-msec resolution) */
11712 uint16_t timestamp_hi;
11713 /* Contains the lower 32 bits of the PPS timestamp. */
11714 uint32_t event_data1;
11715 /* Contains the lower 32 bit PPS timestamp */
11716 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \
11717 UINT32_C(0xffffffff)
11718 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \
11722 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */
11723 struct hwrm_async_event_cmpl_error_report {
11726 * This field indicates the exact type of the completion.
11727 * By convention, the LSB identifies the length of the
11728 * record in 16B units. Even values indicate 16B
11729 * records. Odd values indicate 32B
11732 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \
11734 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
11735 /* HWRM Asynchronous Event Information */
11736 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \
11738 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \
11739 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
11740 /* Identifiers of events. */
11743 * This async notification message is used to inform
11744 * the driver that an error has occurred which may need
11745 * the attention of the administrator.
11747 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \
11749 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \
11750 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
11751 /* Event specific data. */
11752 uint32_t event_data2;
11755 * This value is written by the NIC such that it will be different
11756 * for each pass through the completion queue. The even passes
11757 * will write 1. The odd passes will write 0.
11759 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
11760 /* opaque is 7 b */
11761 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
11762 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
11763 /* 8-lsb timestamp (100-msec resolution) */
11764 uint8_t timestamp_lo;
11765 /* 16-lsb timestamp (100-msec resolution) */
11766 uint16_t timestamp_hi;
11767 /* Event specific data */
11768 uint32_t event_data1;
11770 * Indicates the type of error being reported. See section on Error
11771 * Report event error_types for details on each error.
11773 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \
11775 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
11778 /* hwrm_async_event_cmpl_doorbell_pacing_threshold (size:128b/16B) */
11779 struct hwrm_async_event_cmpl_doorbell_pacing_threshold {
11782 * This field indicates the exact type of the completion.
11783 * By convention, the LSB identifies the length of the
11784 * record in 16B units. Even values indicate 16B
11785 * records. Odd values indicate 32B
11788 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK \
11790 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_SFT \
11792 /* HWRM Asynchronous Event Information */
11793 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \
11795 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_LAST \
11796 HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
11797 /* Identifiers of events. */
11800 * This async notification message is used to inform the driver
11801 * that the programmable pacing threshold for the doorbell FIFO is
11802 * reached. The driver will take appropriate action to pace the
11803 * doorbells when this async event is received from the firmware.
11805 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD \
11807 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_LAST \
11808 HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD
11809 /* Event specific data. */
11810 uint32_t event_data2;
11813 * This value is written by the NIC such that it will be different
11814 * for each pass through the completion queue. The even passes
11815 * will write 1. The odd passes will write 0.
11817 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V \
11819 /* opaque is 7 b */
11820 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK \
11822 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_SFT 1
11823 /* 8-lsb timestamp (100-msec resolution) */
11824 uint8_t timestamp_lo;
11825 /* 16-lsb timestamp (100-msec resolution) */
11826 uint16_t timestamp_hi;
11827 /* Event specific data */
11828 uint32_t event_data1;
11831 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
11832 struct hwrm_async_event_cmpl_fw_trace_msg {
11835 * This field indicates the exact type of the completion.
11836 * By convention, the LSB identifies the length of the
11837 * record in 16B units. Even values indicate 16B
11838 * records. Odd values indicate 32B
11841 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
11843 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
11844 /* HWRM Asynchronous Event Information */
11845 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
11847 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
11848 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
11849 /* Identifiers of events. */
11851 /* Firmware trace log message */
11852 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
11854 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
11855 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
11856 /* Trace byte 0 to 3 */
11857 uint32_t event_data2;
11859 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
11861 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
11863 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
11865 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
11867 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
11869 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
11871 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
11872 UINT32_C(0xff000000)
11873 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
11876 * This value is written by the NIC such that it will be different
11877 * for each pass through the completion queue. The even passes
11878 * will write 1. The odd passes will write 0.
11880 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
11881 /* opaque is 7 b */
11882 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
11883 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
11885 uint8_t timestamp_lo;
11886 /* Indicates if the string is partial or complete. */
11887 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
11889 /* Complete string */
11890 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
11892 /* Partial string */
11893 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
11895 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
11896 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
11897 /* Indicates the firmware that sent the trace message. */
11898 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
11900 /* Primary firmware */
11901 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
11902 (UINT32_C(0x0) << 1)
11903 /* Secondary firmware */
11904 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
11905 (UINT32_C(0x1) << 1)
11906 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
11907 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
11908 /* Trace byte 4 to 5 */
11909 uint16_t timestamp_hi;
11911 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
11913 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
11915 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
11917 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
11918 /* Trace byte 6 to 9 */
11919 uint32_t event_data1;
11921 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
11923 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
11925 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
11927 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
11929 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
11931 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
11933 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
11934 UINT32_C(0xff000000)
11935 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
11938 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
11939 struct hwrm_async_event_cmpl_hwrm_error {
11942 * This field indicates the exact type of the completion.
11943 * By convention, the LSB identifies the length of the
11944 * record in 16B units. Even values indicate 16B
11945 * records. Odd values indicate 32B
11948 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
11950 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
11951 /* HWRM Asynchronous Event Information */
11952 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
11954 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
11955 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
11956 /* Identifiers of events. */
11959 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
11961 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
11962 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
11963 /* Event specific data */
11964 uint32_t event_data2;
11965 /* Severity of HWRM Error */
11966 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
11968 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
11970 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
11972 /* Non-fatal Error */
11973 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
11976 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
11978 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
11979 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
11982 * This value is written by the NIC such that it will be different
11983 * for each pass through the completion queue. The even passes
11984 * will write 1. The odd passes will write 0.
11986 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
11987 /* opaque is 7 b */
11988 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
11989 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
11990 /* 8-lsb timestamp from POR (100-msec resolution) */
11991 uint8_t timestamp_lo;
11992 /* 16-lsb timestamp from POR (100-msec resolution) */
11993 uint16_t timestamp_hi;
11994 /* Event specific data */
11995 uint32_t event_data1;
11996 /* Time stamp for error event */
11997 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
12001 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
12002 struct hwrm_async_event_cmpl_error_report_base {
12005 * This field indicates the exact type of the completion.
12006 * By convention, the LSB identifies the length of the
12007 * record in 16B units. Even values indicate 16B
12008 * records. Odd values indicate 32B
12011 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \
12013 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
12014 /* HWRM Asynchronous Event Information */
12015 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \
12017 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \
12018 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
12019 /* Identifiers of events. */
12022 * This async notification message is used to inform
12023 * the driver that an error has occurred which may need
12024 * the attention of the administrator.
12026 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \
12028 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \
12029 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
12030 /* Event specific data. */
12031 uint32_t event_data2;
12034 * This value is written by the NIC such that it will be different
12035 * for each pass through the completion queue. The even passes
12036 * will write 1. The odd passes will write 0.
12038 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \
12040 /* opaque is 7 b */
12041 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \
12043 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
12044 /* 8-lsb timestamp (100-msec resolution) */
12045 uint8_t timestamp_lo;
12046 /* 16-lsb timestamp (100-msec resolution) */
12047 uint16_t timestamp_hi;
12048 /* Event specific data */
12049 uint32_t event_data1;
12050 /* Indicates the type of error being reported. */
12051 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \
12053 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \
12056 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \
12059 * The NIC was subjected to an extended pause storm which caused it
12060 * to disable flow control in order to avoid stalling the Tx path.
12062 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
12065 * The NIC received an interrupt storm on a TSIO pin being used as
12066 * PPS_IN which caused it to disable the interrupt. The signal
12067 * should be fixed to be a proper 1 PPS signal before re-enabling
12068 * it. The pin number on which this signal was received is stored
12069 * in event_data2 as pin_id.
12071 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
12074 * There was a low level error with an NVM write or erase.
12075 * See nvm_err_type for more details.
12077 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \
12080 * This indicates doorbell drop threshold was hit. When this
12081 * threshold is crossed, it indicates one or more doorbells for
12082 * the function were dropped by hardware.
12084 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
12087 * Indicates the NIC's temperature has crossed one of the thermal
12090 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD \
12092 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \
12093 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD
12096 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
12097 struct hwrm_async_event_cmpl_error_report_pause_storm {
12100 * This field indicates the exact type of the completion.
12101 * By convention, the LSB identifies the length of the
12102 * record in 16B units. Even values indicate 16B
12103 * records. Odd values indicate 32B
12106 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \
12108 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \
12110 /* HWRM Asynchronous Event Information */
12111 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \
12113 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \
12114 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
12115 /* Identifiers of events. */
12118 * This async notification message is used to inform
12119 * the driver that an error has occurred which may need
12120 * the attention of the administrator.
12122 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \
12124 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \
12125 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
12126 /* Event specific data. */
12127 uint32_t event_data2;
12130 * This value is written by the NIC such that it will be different
12131 * for each pass through the completion queue. The even passes
12132 * will write 1. The odd passes will write 0.
12134 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \
12136 /* opaque is 7 b */
12137 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \
12139 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
12140 /* 8-lsb timestamp (100-msec resolution) */
12141 uint8_t timestamp_lo;
12142 /* 16-lsb timestamp (100-msec resolution) */
12143 uint16_t timestamp_hi;
12144 /* Event specific data */
12145 uint32_t event_data1;
12146 /* Indicates the type of error being reported. */
12147 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \
12149 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \
12152 * The NIC was subjected to an extended pause storm which caused it
12153 * to disable flow control in order to avoid stalling the Tx path.
12155 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
12157 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \
12158 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
12161 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
12162 struct hwrm_async_event_cmpl_error_report_invalid_signal {
12165 * This field indicates the exact type of the completion.
12166 * By convention, the LSB identifies the length of the
12167 * record in 16B units. Even values indicate 16B
12168 * records. Odd values indicate 32B
12171 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \
12173 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \
12175 /* HWRM Asynchronous Event Information */
12176 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \
12178 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \
12179 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
12180 /* Identifiers of events. */
12183 * This async notification message is used to inform
12184 * the driver that an error has occurred which may need
12185 * the attention of the administrator.
12187 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \
12189 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \
12190 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
12191 /* Event specific data. */
12192 uint32_t event_data2;
12193 /* Indicates the TSIO pin on which invalid signal is detected. */
12194 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \
12196 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \
12200 * This value is written by the NIC such that it will be different
12201 * for each pass through the completion queue. The even passes
12202 * will write 1. The odd passes will write 0.
12204 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \
12206 /* opaque is 7 b */
12207 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \
12209 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
12210 /* 8-lsb timestamp (100-msec resolution) */
12211 uint8_t timestamp_lo;
12212 /* 16-lsb timestamp (100-msec resolution) */
12213 uint16_t timestamp_hi;
12214 /* Event specific data */
12215 uint32_t event_data1;
12216 /* Indicates the type of error being reported. */
12217 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \
12219 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \
12222 * The NIC received an interrupt storm on a TSIO pin being used as
12223 * PPS_IN which caused it to disable the interrupt. The signal
12224 * should be fixed to be a proper 1 PPS signal before re-enabling
12225 * it. The pin number on which this signal was received is stored
12226 * in event_data2 as pin_id.
12228 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
12230 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \
12231 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
12234 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
12235 struct hwrm_async_event_cmpl_error_report_nvm {
12238 * This field indicates the exact type of the completion.
12239 * By convention, the LSB identifies the length of the
12240 * record in 16B units. Even values indicate 16B
12241 * records. Odd values indicate 32B
12244 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \
12246 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
12247 /* HWRM Asynchronous Event Information */
12248 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \
12250 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \
12251 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
12252 /* Identifiers of events. */
12255 * This async notification message is used to inform
12256 * the driver that an error has occurred which may need
12257 * the attention of the administrator.
12259 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \
12261 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \
12262 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
12263 /* Event specific data. */
12264 uint32_t event_data2;
12265 /* Indicates the address where error was detected */
12266 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \
12267 UINT32_C(0xffffffff)
12268 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \
12272 * This value is written by the NIC such that it will be different
12273 * for each pass through the completion queue. The even passes
12274 * will write 1. The odd passes will write 0.
12276 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
12277 /* opaque is 7 b */
12278 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \
12280 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
12281 /* 8-lsb timestamp (100-msec resolution) */
12282 uint8_t timestamp_lo;
12283 /* 16-lsb timestamp (100-msec resolution) */
12284 uint16_t timestamp_hi;
12285 /* Event specific data */
12286 uint32_t event_data1;
12287 /* Indicates the type of error being reported. */
12288 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \
12290 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \
12293 * There was a low level error with an NVM operation.
12294 * See nvm_err_type for more details.
12296 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \
12298 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \
12299 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
12300 /* The specific type of NVM error */
12301 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \
12303 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \
12306 * There was a low level error with an NVM write operation.
12307 * Verification of written data did not match.
12308 * event_data2 will be the failing address.
12310 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \
12311 (UINT32_C(0x1) << 8)
12313 * There was a low level error with an NVM erase operation.
12314 * All the bits were not erased.
12315 * event_data2 will be the failing address.
12317 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \
12318 (UINT32_C(0x2) << 8)
12319 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \
12320 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
12323 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
12324 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
12327 * This field indicates the exact type of the completion.
12328 * By convention, the LSB identifies the length of the
12329 * record in 16B units. Even values indicate 16B
12330 * records. Odd values indicate 32B
12333 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \
12335 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \
12337 /* HWRM Asynchronous Event Information */
12338 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \
12340 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \
12341 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
12342 /* Identifiers of events. */
12345 * This async notification message is used to inform
12346 * the driver that an error has occurred which may need
12347 * the attention of the administrator.
12349 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \
12351 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \
12352 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
12353 /* Event specific data. */
12354 uint32_t event_data2;
12357 * This value is written by the NIC such that it will be different
12358 * for each pass through the completion queue. The even passes
12359 * will write 1. The odd passes will write 0.
12361 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \
12363 /* opaque is 7 b */
12364 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \
12366 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \
12368 /* 8-lsb timestamp (100-msec resolution) */
12369 uint8_t timestamp_lo;
12370 /* 16-lsb timestamp (100-msec resolution) */
12371 uint16_t timestamp_hi;
12372 /* Event specific data */
12373 uint32_t event_data1;
12374 /* Indicates the type of error being reported. */
12375 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \
12377 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \
12380 * This indicates doorbell drop threshold was hit. When this
12381 * threshold is crossed, it indicates one or more doorbells for
12382 * the function were dropped by hardware.
12384 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
12386 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
12387 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
12390 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */
12391 struct hwrm_async_event_cmpl_error_report_thermal {
12394 * This field indicates the exact type of the completion.
12395 * By convention, the LSB identifies the length of the
12396 * record in 16B units. Even values indicate 16B
12397 * records. Odd values indicate 32B
12400 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK \
12402 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT \
12404 /* HWRM Asynchronous Event Information */
12405 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT \
12407 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST \
12408 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT
12409 /* Identifiers of events. */
12412 * This async notification message is used to inform
12413 * the driver that an error has occurred which may need
12414 * the attention of the administrator.
12416 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT \
12418 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST \
12419 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT
12420 /* Event specific data. */
12421 uint32_t event_data2;
12422 /* Current temperature. In Celsius */
12423 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK \
12425 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT \
12428 * The temperature setting of the threshold that was just crossed.
12431 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK \
12433 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT \
12437 * This value is written by the NIC such that it will be different
12438 * for each pass through the completion queue. The even passes
12439 * will write 1. The odd passes will write 0.
12441 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V \
12443 /* opaque is 7 b */
12444 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK \
12446 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1
12447 /* 8-lsb timestamp (100-msec resolution) */
12448 uint8_t timestamp_lo;
12449 /* 16-lsb timestamp (100-msec resolution) */
12450 uint16_t timestamp_hi;
12451 /* Event specific data */
12452 uint32_t event_data1;
12453 /* Indicates the type of error being reported. */
12454 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK \
12456 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT \
12459 * There was thermal event. The type will be specified in the
12460 * field threshold_type. event_data2 will contain the current
12461 * temperature and the configured value for the threshold that
12462 * was just crossed. The threshold values are lower thresholds,
12463 * so the event will trigger with an active flag when the
12464 * temperature is on an increasing trajectory.
12466 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT \
12468 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST \
12469 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT
12470 /* The specific type of thermal threshold error */
12471 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK \
12473 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT \
12475 /* Warning thermal threshold was crossed */
12476 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN \
12477 (UINT32_C(0x0) << 8)
12478 /* Critical thermal threshold was crossed */
12479 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL \
12480 (UINT32_C(0x1) << 8)
12481 /* Fatal thermal threshold was crossed */
12482 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL \
12483 (UINT32_C(0x2) << 8)
12485 * Thermal shutdown threshold was crossed and a shutdown is
12486 * imminent. This event will not occur if self shutdown
12489 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN \
12490 (UINT32_C(0x3) << 8)
12491 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST \
12492 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN
12494 * Indicates if the thermal crossing occurs while the temperature is
12495 * increasing or decreasing.
12497 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR \
12499 /* Threshold is crossed while the temperature is falling. */
12500 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING \
12501 (UINT32_C(0x0) << 11)
12502 /* Threshold is crossed while the temperature is rising. */
12503 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING \
12504 (UINT32_C(0x1) << 11)
12505 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST \
12506 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING
12509 /* metadata_base_msg (size:64b/8B) */
12510 struct metadata_base_msg {
12511 uint16_t md_type_link;
12512 /* This field classifies the data present in the meta-data. */
12513 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
12514 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
12515 /* Meta data fields are not valid */
12516 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
12518 * This setting is used when packets are coming in-order. Depending on
12519 * the state of the receive context, the meta-data will carry different
12522 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
12524 * With this setting HW passes the TCP sequence number of the TLS
12525 * record that it is requesting a resync on in the meta data.
12527 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
12528 #define METADATA_BASE_MSG_MD_TYPE_LAST \
12529 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
12531 * This field indicates where the next metadata block starts. It is
12532 * counted in 16B units. A value of zero indicates that there is no
12535 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
12536 #define METADATA_BASE_MSG_LINK_SFT 5
12541 /* tls_metadata_base_msg (size:64b/8B) */
12542 struct tls_metadata_base_msg {
12543 uint32_t md_type_link_flags_kid_lo;
12544 /* This field classifies the data present in the meta-data. */
12545 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
12547 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
12549 * This setting is used when packets are coming in-order. Depending on
12550 * the state of the receive context, the meta-data will carry different
12553 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
12556 * With this setting HW passes the TCP sequence number of the TLS
12557 * record that it is requesting a resync on in the meta data.
12559 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
12561 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
12562 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
12564 * This field indicates where the next metadata block starts. It is
12565 * counted in 16B units. A value of zero indicates that there is no
12568 #define TLS_METADATA_BASE_MSG_LINK_MASK \
12570 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
12571 /* These are flags present in the metadata. */
12572 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
12573 UINT32_C(0x1fffe00)
12574 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
12576 * A value of 1 implies that the packet was decrypted by HW. Otherwise
12577 * the packet is passed on as it came in on the wire.
12579 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
12582 * This field indicates the state of the ghash field passed in the
12585 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
12587 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
12589 * This enumeration states that the ghash is not valid in the
12592 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
12593 (UINT32_C(0x0) << 10)
12595 * This enumeration indicates that this pkt contains the record's
12596 * tag and this pkt was received ooo, the partial_ghash field
12597 * contains the ghash.
12599 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
12600 (UINT32_C(0x1) << 10)
12602 * This enumeration indicates that the current record's tag wasn't
12603 * seen and the chip is moving on to the next record, the
12604 * partial_ghash field contains the ghash.
12606 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
12607 (UINT32_C(0x2) << 10)
12608 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
12609 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
12610 /* This field indicates the status of tag authentication. */
12611 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
12613 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
12615 * This enumeration is set when there is no tags present in the
12618 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
12619 (UINT32_C(0x0) << 12)
12621 * This enumeration states that there is at least one tag in the
12622 * packet and every tag is valid.
12624 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
12625 (UINT32_C(0x1) << 12)
12627 * This enumeration states that there is at least one tag in the
12628 * packet and at least one of the tag is invalid. The entire packet
12629 * is sent decrypted to the host.
12631 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
12632 (UINT32_C(0x2) << 12)
12633 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
12634 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
12636 * A value of 1 indicates that this packet contains a record that
12637 * starts in the packet and extends beyond the packet.
12639 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
12642 * This value indicates the lower 7-bit of the Crypto Key ID
12643 * associated with this operation.
12645 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
12646 UINT32_C(0xfe000000)
12647 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
12650 * This value indicates the upper 13-bit of the Crypto Key ID
12651 * associated with this operation.
12653 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
12654 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
12658 /* tls_metadata_insync_msg (size:192b/24B) */
12659 struct tls_metadata_insync_msg {
12660 uint32_t md_type_link_flags_kid_lo;
12661 /* This field classifies the data present in the meta-data. */
12662 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
12664 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
12666 * This setting is used when packets are coming in-order. Depending on
12667 * the state of the receive context, the meta-data will carry different
12670 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
12672 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
12673 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
12675 * This field indicates where the next metadata block starts. It is
12676 * counted in 16B units. A value of zero indicates that there is no
12679 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
12681 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
12682 /* These are flags present in the metadata. */
12683 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
12684 UINT32_C(0x1fffe00)
12685 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
12687 * A value of 1 implies that the packet was decrypted by HW. Otherwise
12688 * the packet is passed on as it came in on the wire.
12690 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
12693 * This field indicates the state of the ghash field passed in the
12696 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
12698 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
12700 * This enumeration states that the ghash is not valid in the
12703 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
12704 (UINT32_C(0x0) << 10)
12706 * This enumeration indicates that this pkt contains the record's
12707 * tag and this pkt was received ooo, the partial_ghash field
12708 * contains the ghash.
12710 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
12711 (UINT32_C(0x1) << 10)
12713 * This enumeration indicates that the current record's tag wasn't
12714 * seen and the chip is moving on to the next record, the
12715 * partial_ghash field contains the ghash.
12717 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
12718 (UINT32_C(0x2) << 10)
12719 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
12720 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
12721 /* This field indicates the status of tag authentication. */
12722 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
12724 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
12726 * This enumeration is set when there is no tags present in the
12729 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
12730 (UINT32_C(0x0) << 12)
12732 * This enumeration states that there is at least one tag in the
12733 * packet and every tag is valid.
12735 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
12736 (UINT32_C(0x1) << 12)
12738 * This enumeration states that there is at least one tag in the
12739 * packet and at least one of the tag is invalid. The entire packet
12740 * is sent decrypted to the host.
12742 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
12743 (UINT32_C(0x2) << 12)
12744 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
12745 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
12747 * A value of 1 indicates that this packet contains a record that
12748 * starts in the packet and extends beyond the packet.
12750 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
12753 * This value indicates the lower 7-bit of the Crypto Key ID
12754 * associated with this operation.
12756 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
12757 UINT32_C(0xfe000000)
12758 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
12761 * This value indicates the upper 13-bit of the Crypto Key ID
12762 * associated with this operation.
12764 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
12765 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
12767 * This field is only valid when md_type is set to tls_insync. This field
12768 * indicates the offset within the current TCP packet where the TLS header
12769 * starts. If there are multiple TLS headers in the packet, this provides
12770 * the offset of the last TLS header.
12772 * The field is calculated by subtracting TCP sequence number of the first
12773 * byte of the TCP payload of the packet from the TCP sequence number of
12774 * the last TLS header in the packet.
12776 uint16_t tls_header_offset;
12778 * This is the sequence Number of the record that was processed by the HW.
12779 * If there are multiple records in a packet, this would be the sequence
12780 * number of the last record.
12782 uint64_t record_seq_num;
12784 * This field contains cumulative partial GHASH value of all the packets
12785 * decrypted by the HW associated with a TLS record. This field is valid
12786 * on when packets belonging to have arrived out-of-order and HW could
12787 * not decrypt every packet and authenticate the record. Partial GHASH is
12788 * only sent out with packet having the TAG field.
12790 uint64_t partial_ghash;
12793 /* tls_metadata_resync_msg (size:256b/32B) */
12794 struct tls_metadata_resync_msg {
12795 uint32_t md_type_link_flags_kid_lo;
12796 /* This field classifies the data present in the meta-data. */
12797 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
12799 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
12801 * With this setting HW passes the TCP sequence number of the TLS
12802 * record that it is requesting a resync on in the meta data.
12804 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
12806 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
12807 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
12809 * This field indicates where the next metadata block starts. It is
12810 * counted in 16B units. A value of zero indicates that there is no
12813 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
12815 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
12816 /* These are flags present in the metadata. */
12817 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
12818 UINT32_C(0x1fffe00)
12819 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
12821 * A value of 1 implies that the packet was decrypted by HW. Otherwise
12822 * the packet is passed on as it came in on the wire.
12824 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
12827 * This field indicates the state of the ghash field passed in the
12830 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
12832 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
12834 * This enumeration states that the ghash is not valid in the
12837 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
12838 (UINT32_C(0x0) << 10)
12839 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
12840 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
12841 /* This field indicates the status of tag authentication. */
12842 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
12844 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
12846 * This enumeration is set when there is no tags present in the
12849 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
12850 (UINT32_C(0x0) << 12)
12851 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
12852 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
12854 * A value of 1 indicates that this packet contains a record that
12855 * starts in the packet and extends beyond the packet.
12857 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
12860 * This value indicates the lower 7-bit of the Crypto Key ID
12861 * associated with this operation.
12863 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
12864 UINT32_C(0xfe000000)
12865 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
12868 * This value indicates the upper 13-bit of the Crypto Key ID
12869 * associated with this operation.
12871 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
12872 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
12873 /* This field is unused in this context. */
12874 uint16_t metadata_0;
12876 * This field indicates the TCP sequence number of the TLS record that HW
12877 * is requesting a resync on from the Driver. HW will keep a count of the
12878 * TLS records it found after this record (delta_records). Driver will
12879 * provide the TLS Record Sequence Number associated with the record. HW
12880 * will add the delta_records to the Record Sequence Number provided by
12881 * the driver and get back on sync.
12883 uint32_t resync_record_tcp_seq_num;
12885 /* This field is unused in this context. */
12886 uint64_t metadata_2;
12887 /* This field is unused in this context. */
12888 uint64_t metadata_3;
12891 /*******************
12892 * hwrm_func_reset *
12893 *******************/
12896 /* hwrm_func_reset_input (size:192b/24B) */
12897 struct hwrm_func_reset_input {
12898 /* The HWRM command request type. */
12901 * The completion ring to send the completion event on. This should
12902 * be the NQ ID returned from the `nq_alloc` HWRM command.
12904 uint16_t cmpl_ring;
12906 * The sequence ID is used by the driver for tracking multiple
12907 * commands. This ID is treated as opaque data by the firmware and
12908 * the value is returned in the `hwrm_resp_hdr` upon completion.
12912 * The target ID of the command:
12913 * * 0x0-0xFFF8 - The function ID
12914 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12915 * * 0xFFFD - Reserved for user-space HWRM interface
12918 uint16_t target_id;
12920 * A physical address pointer pointing to a host buffer that the
12921 * command's response data will be written. This can be either a host
12922 * physical address (HPA) or a guest physical address (GPA) and must
12923 * point to a physically contiguous block of memory.
12925 uint64_t resp_addr;
12928 * This bit must be '1' for the vf_id_valid field to be
12931 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
12933 * The ID of the VF that this PF is trying to reset.
12934 * Only the parent PF shall be allowed to reset a child VF.
12936 * A parent PF driver shall use this field only when a specific child VF
12937 * is requested to be reset.
12940 /* This value indicates the level of a function reset. */
12941 uint8_t func_reset_level;
12943 * Reset the caller function and its children VFs (if any). If no
12944 * children functions exist, then reset the caller function only.
12946 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
12948 /* Reset the caller function only */
12949 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
12952 * Reset all children VFs of the caller function driver if the
12953 * caller is a PF driver.
12954 * It is an error to specify this level by a VF driver.
12955 * It is an error to specify this level by a PF driver with
12958 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
12961 * Reset a specific VF of the caller function driver if the caller
12962 * is the parent PF driver.
12963 * It is an error to specify this level by a VF driver.
12964 * It is an error to specify this level by a PF driver that is not
12965 * the parent of the VF that is being requested to reset.
12967 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
12969 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
12970 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
12974 /* hwrm_func_reset_output (size:128b/16B) */
12975 struct hwrm_func_reset_output {
12976 /* The specific error status for the command. */
12977 uint16_t error_code;
12978 /* The HWRM command request type. */
12980 /* The sequence ID from the original command. */
12982 /* The length of the response data in number of bytes. */
12984 uint8_t unused_0[7];
12986 * This field is used in Output records to indicate that the output
12987 * is completely written to RAM. This field should be read as '1'
12988 * to indicate that the output has been completely written.
12989 * When writing a command completion or response to an internal processor,
12990 * the order of writes has to be such that this field is written last.
12995 /********************
12996 * hwrm_func_getfid *
12997 ********************/
13000 /* hwrm_func_getfid_input (size:192b/24B) */
13001 struct hwrm_func_getfid_input {
13002 /* The HWRM command request type. */
13005 * The completion ring to send the completion event on. This should
13006 * be the NQ ID returned from the `nq_alloc` HWRM command.
13008 uint16_t cmpl_ring;
13010 * The sequence ID is used by the driver for tracking multiple
13011 * commands. This ID is treated as opaque data by the firmware and
13012 * the value is returned in the `hwrm_resp_hdr` upon completion.
13016 * The target ID of the command:
13017 * * 0x0-0xFFF8 - The function ID
13018 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13019 * * 0xFFFD - Reserved for user-space HWRM interface
13022 uint16_t target_id;
13024 * A physical address pointer pointing to a host buffer that the
13025 * command's response data will be written. This can be either a host
13026 * physical address (HPA) or a guest physical address (GPA) and must
13027 * point to a physically contiguous block of memory.
13029 uint64_t resp_addr;
13032 * This bit must be '1' for the pci_id field to be
13035 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
13037 * This value is the PCI ID of the queried function.
13038 * If ARI is enabled, then it is
13039 * Bus Number (8b):Function Number(8b). Otherwise, it is
13040 * Bus Number (8b):Device Number (5b):Function Number(3b).
13043 uint8_t unused_0[2];
13046 /* hwrm_func_getfid_output (size:128b/16B) */
13047 struct hwrm_func_getfid_output {
13048 /* The specific error status for the command. */
13049 uint16_t error_code;
13050 /* The HWRM command request type. */
13052 /* The sequence ID from the original command. */
13054 /* The length of the response data in number of bytes. */
13057 * FID value. This value is used to identify operations on the PCI
13058 * bus as belonging to a particular PCI function.
13061 uint8_t unused_0[5];
13063 * This field is used in Output records to indicate that the output
13064 * is completely written to RAM. This field should be read as '1'
13065 * to indicate that the output has been completely written.
13066 * When writing a command completion or response to an internal processor,
13067 * the order of writes has to be such that this field is written last.
13072 /**********************
13073 * hwrm_func_vf_alloc *
13074 **********************/
13077 /* hwrm_func_vf_alloc_input (size:192b/24B) */
13078 struct hwrm_func_vf_alloc_input {
13079 /* The HWRM command request type. */
13082 * The completion ring to send the completion event on. This should
13083 * be the NQ ID returned from the `nq_alloc` HWRM command.
13085 uint16_t cmpl_ring;
13087 * The sequence ID is used by the driver for tracking multiple
13088 * commands. This ID is treated as opaque data by the firmware and
13089 * the value is returned in the `hwrm_resp_hdr` upon completion.
13093 * The target ID of the command:
13094 * * 0x0-0xFFF8 - The function ID
13095 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13096 * * 0xFFFD - Reserved for user-space HWRM interface
13099 uint16_t target_id;
13101 * A physical address pointer pointing to a host buffer that the
13102 * command's response data will be written. This can be either a host
13103 * physical address (HPA) or a guest physical address (GPA) and must
13104 * point to a physically contiguous block of memory.
13106 uint64_t resp_addr;
13109 * This bit must be '1' for the first_vf_id field to be
13112 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
13114 * This value is used to identify a Virtual Function (VF).
13115 * The scope of VF ID is local within a PF.
13117 uint16_t first_vf_id;
13118 /* The number of virtual functions requested. */
13122 /* hwrm_func_vf_alloc_output (size:128b/16B) */
13123 struct hwrm_func_vf_alloc_output {
13124 /* The specific error status for the command. */
13125 uint16_t error_code;
13126 /* The HWRM command request type. */
13128 /* The sequence ID from the original command. */
13130 /* The length of the response data in number of bytes. */
13132 /* The ID of the first VF allocated. */
13133 uint16_t first_vf_id;
13134 uint8_t unused_0[5];
13136 * This field is used in Output records to indicate that the output
13137 * is completely written to RAM. This field should be read as '1'
13138 * to indicate that the output has been completely written.
13139 * When writing a command completion or response to an internal processor,
13140 * the order of writes has to be such that this field is written last.
13145 /*********************
13146 * hwrm_func_vf_free *
13147 *********************/
13150 /* hwrm_func_vf_free_input (size:192b/24B) */
13151 struct hwrm_func_vf_free_input {
13152 /* The HWRM command request type. */
13155 * The completion ring to send the completion event on. This should
13156 * be the NQ ID returned from the `nq_alloc` HWRM command.
13158 uint16_t cmpl_ring;
13160 * The sequence ID is used by the driver for tracking multiple
13161 * commands. This ID is treated as opaque data by the firmware and
13162 * the value is returned in the `hwrm_resp_hdr` upon completion.
13166 * The target ID of the command:
13167 * * 0x0-0xFFF8 - The function ID
13168 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13169 * * 0xFFFD - Reserved for user-space HWRM interface
13172 uint16_t target_id;
13174 * A physical address pointer pointing to a host buffer that the
13175 * command's response data will be written. This can be either a host
13176 * physical address (HPA) or a guest physical address (GPA) and must
13177 * point to a physically contiguous block of memory.
13179 uint64_t resp_addr;
13182 * This bit must be '1' for the first_vf_id field to be
13185 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
13187 * This value is used to identify a Virtual Function (VF).
13188 * The scope of VF ID is local within a PF.
13190 uint16_t first_vf_id;
13192 * The number of virtual functions requested.
13193 * 0xFFFF - Cleanup all children of this PF.
13198 /* hwrm_func_vf_free_output (size:128b/16B) */
13199 struct hwrm_func_vf_free_output {
13200 /* The specific error status for the command. */
13201 uint16_t error_code;
13202 /* The HWRM command request type. */
13204 /* The sequence ID from the original command. */
13206 /* The length of the response data in number of bytes. */
13208 uint8_t unused_0[7];
13210 * This field is used in Output records to indicate that the output
13211 * is completely written to RAM. This field should be read as '1'
13212 * to indicate that the output has been completely written.
13213 * When writing a command completion or response to an internal processor,
13214 * the order of writes has to be such that this field is written last.
13219 /********************
13220 * hwrm_func_vf_cfg *
13221 ********************/
13224 /* hwrm_func_vf_cfg_input (size:448b/56B) */
13225 struct hwrm_func_vf_cfg_input {
13226 /* The HWRM command request type. */
13229 * The completion ring to send the completion event on. This should
13230 * be the NQ ID returned from the `nq_alloc` HWRM command.
13232 uint16_t cmpl_ring;
13234 * The sequence ID is used by the driver for tracking multiple
13235 * commands. This ID is treated as opaque data by the firmware and
13236 * the value is returned in the `hwrm_resp_hdr` upon completion.
13240 * The target ID of the command:
13241 * * 0x0-0xFFF8 - The function ID
13242 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13243 * * 0xFFFD - Reserved for user-space HWRM interface
13246 uint16_t target_id;
13248 * A physical address pointer pointing to a host buffer that the
13249 * command's response data will be written. This can be either a host
13250 * physical address (HPA) or a guest physical address (GPA) and must
13251 * point to a physically contiguous block of memory.
13253 uint64_t resp_addr;
13256 * This bit must be '1' for the mtu field to be
13259 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
13262 * This bit must be '1' for the guest_vlan field to be
13265 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
13268 * This bit must be '1' for the async_event_cr field to be
13271 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
13274 * This bit must be '1' for the dflt_mac_addr field to be
13277 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
13280 * This bit must be '1' for the num_rsscos_ctxs field to be
13283 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
13286 * This bit must be '1' for the num_cmpl_rings field to be
13289 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
13292 * This bit must be '1' for the num_tx_rings field to be
13295 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
13298 * This bit must be '1' for the num_rx_rings field to be
13301 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
13304 * This bit must be '1' for the num_l2_ctxs field to be
13307 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
13310 * This bit must be '1' for the num_vnics field to be
13313 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
13316 * This bit must be '1' for the num_stat_ctxs field to be
13319 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
13322 * This bit must be '1' for the num_hw_ring_grps field to be
13325 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
13328 * This bit must be '1' for the num_tx_key_ctxs field to be
13331 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \
13334 * This bit must be '1' for the num_rx_key_ctxs field to be
13337 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \
13340 * The maximum transmission unit requested on the function.
13341 * The HWRM should make sure that the mtu of
13342 * the function does not exceed the mtu of the physical
13343 * port that this function is associated with.
13345 * In addition to requesting mtu per function, it is
13346 * possible to configure mtu per transmit ring.
13347 * By default, the mtu of each transmit ring associated
13348 * with a function is equal to the mtu of the function.
13349 * The HWRM should make sure that the mtu of each transmit
13350 * ring that is assigned to a function has a valid mtu.
13354 * The guest VLAN for the function being configured.
13355 * This field's format is same as 802.1Q Tag's
13356 * Tag Control Information (TCI) format that includes both
13357 * Priority Code Point (PCP) and VLAN Identifier (VID).
13359 uint16_t guest_vlan;
13361 * ID of the target completion ring for receiving asynchronous
13362 * event completions. If this field is not valid, then the
13363 * HWRM shall use the default completion ring of the function
13364 * that is being configured as the target completion ring for
13365 * providing any asynchronous event completions for that
13367 * If this field is valid, then the HWRM shall use the
13368 * completion ring identified by this ID as the target
13369 * completion ring for providing any asynchronous event
13370 * completions for the function that is being configured.
13372 uint16_t async_event_cr;
13374 * This value is the current MAC address requested by the VF
13375 * driver to be configured on this VF. A value of
13376 * 00-00-00-00-00-00 indicates no MAC address configuration
13377 * is requested by the VF driver.
13378 * The parent PF driver may reject or overwrite this
13381 uint8_t dflt_mac_addr[6];
13384 * This bit requests that the firmware test to see if all the assets
13385 * requested in this command (i.e. number of TX rings) are available.
13386 * The firmware will return an error if the requested assets are
13387 * not available. The firwmare will NOT reserve the assets if they
13390 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
13393 * This bit requests that the firmware test to see if all the assets
13394 * requested in this command (i.e. number of RX rings) are available.
13395 * The firmware will return an error if the requested assets are
13396 * not available. The firwmare will NOT reserve the assets if they
13399 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
13402 * This bit requests that the firmware test to see if all the assets
13403 * requested in this command (i.e. number of CMPL rings) are available.
13404 * The firmware will return an error if the requested assets are
13405 * not available. The firwmare will NOT reserve the assets if they
13408 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
13411 * This bit requests that the firmware test to see if all the assets
13412 * requested in this command (i.e. number of RSS ctx) are available.
13413 * The firmware will return an error if the requested assets are
13414 * not available. The firwmare will NOT reserve the assets if they
13417 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
13420 * This bit requests that the firmware test to see if all the assets
13421 * requested in this command (i.e. number of ring groups) are available.
13422 * The firmware will return an error if the requested assets are
13423 * not available. The firwmare will NOT reserve the assets if they
13426 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
13429 * This bit requests that the firmware test to see if all the assets
13430 * requested in this command (i.e. number of stat ctx) are available.
13431 * The firmware will return an error if the requested assets are
13432 * not available. The firwmare will NOT reserve the assets if they
13435 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
13438 * This bit requests that the firmware test to see if all the assets
13439 * requested in this command (i.e. number of VNICs) are available.
13440 * The firmware will return an error if the requested assets are
13441 * not available. The firwmare will NOT reserve the assets if they
13444 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
13447 * This bit requests that the firmware test to see if all the assets
13448 * requested in this command (i.e. number of L2 ctx) are available.
13449 * The firmware will return an error if the requested assets are
13450 * not available. The firwmare will NOT reserve the assets if they
13453 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
13456 * If this bit is set to 1, the VF driver is requesting FW to enable
13457 * PPP TX PUSH feature on all the TX rings specified in the
13458 * num_tx_rings field. By default, the PPP TX push feature is
13459 * disabled for all the TX rings of the VF. This flag is ignored if
13460 * the num_tx_rings field is not specified or the VF doesn't support
13461 * PPP tx push feature.
13463 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
13466 * If this bit is set to 1, the VF driver is requesting FW to disable
13467 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
13468 * ignored if the VF doesn't support PPP tx push feature.
13470 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
13472 /* The number of RSS/COS contexts requested for the VF. */
13473 uint16_t num_rsscos_ctxs;
13474 /* The number of completion rings requested for the VF. */
13475 uint16_t num_cmpl_rings;
13476 /* The number of transmit rings requested for the VF. */
13477 uint16_t num_tx_rings;
13478 /* The number of receive rings requested for the VF. */
13479 uint16_t num_rx_rings;
13480 /* The number of L2 contexts requested for the VF. */
13481 uint16_t num_l2_ctxs;
13482 /* The number of vnics requested for the VF. */
13483 uint16_t num_vnics;
13484 /* The number of statistic contexts requested for the VF. */
13485 uint16_t num_stat_ctxs;
13486 /* The number of HW ring groups requested for the VF. */
13487 uint16_t num_hw_ring_grps;
13488 /* Number of Tx Key Contexts requested. */
13489 uint16_t num_tx_key_ctxs;
13490 /* Number of Rx Key Contexts requested. */
13491 uint16_t num_rx_key_ctxs;
13494 /* hwrm_func_vf_cfg_output (size:128b/16B) */
13495 struct hwrm_func_vf_cfg_output {
13496 /* The specific error status for the command. */
13497 uint16_t error_code;
13498 /* The HWRM command request type. */
13500 /* The sequence ID from the original command. */
13502 /* The length of the response data in number of bytes. */
13504 uint8_t unused_0[7];
13506 * This field is used in Output records to indicate that the output
13507 * is completely written to RAM. This field should be read as '1'
13508 * to indicate that the output has been completely written.
13509 * When writing a command completion or response to an internal processor,
13510 * the order of writes has to be such that this field is written last.
13515 /*******************
13516 * hwrm_func_qcaps *
13517 *******************/
13520 /* hwrm_func_qcaps_input (size:192b/24B) */
13521 struct hwrm_func_qcaps_input {
13522 /* The HWRM command request type. */
13525 * The completion ring to send the completion event on. This should
13526 * be the NQ ID returned from the `nq_alloc` HWRM command.
13528 uint16_t cmpl_ring;
13530 * The sequence ID is used by the driver for tracking multiple
13531 * commands. This ID is treated as opaque data by the firmware and
13532 * the value is returned in the `hwrm_resp_hdr` upon completion.
13536 * The target ID of the command:
13537 * * 0x0-0xFFF8 - The function ID
13538 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13539 * * 0xFFFD - Reserved for user-space HWRM interface
13542 uint16_t target_id;
13544 * A physical address pointer pointing to a host buffer that the
13545 * command's response data will be written. This can be either a host
13546 * physical address (HPA) or a guest physical address (GPA) and must
13547 * point to a physically contiguous block of memory.
13549 uint64_t resp_addr;
13551 * Function ID of the function that is being queried.
13552 * 0xFF... (All Fs) if the query is for the requesting
13554 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
13555 * to be used by a trusted VF to query its parent PF.
13558 uint8_t unused_0[6];
13561 /* hwrm_func_qcaps_output (size:768b/96B) */
13562 struct hwrm_func_qcaps_output {
13563 /* The specific error status for the command. */
13564 uint16_t error_code;
13565 /* The HWRM command request type. */
13567 /* The sequence ID from the original command. */
13569 /* The length of the response data in number of bytes. */
13572 * FID value. This value is used to identify operations on the PCI
13573 * bus as belonging to a particular PCI function.
13577 * Port ID of port that this function is associated with.
13578 * Valid only for the PF.
13579 * 0xFF... (All Fs) if this function is not associated with
13581 * 0xFF... (All Fs) if this function is called from a VF.
13585 /* If 1, then Push mode is supported on this function. */
13586 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
13589 * If 1, then the global MSI-X auto-masking is enabled for the
13592 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
13595 * If 1, then the Precision Time Protocol (PTP) processing
13596 * is supported on this function.
13597 * The HWRM should enable PTP on only a single Physical
13598 * Function (PF) per port.
13600 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
13603 * If 1, then RDMA over Converged Ethernet (RoCE) v1
13604 * is supported on this function.
13606 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
13609 * If 1, then RDMA over Converged Ethernet (RoCE) v2
13610 * is supported on this function.
13612 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
13615 * If 1, then control and configuration of WoL magic packet
13616 * are supported on this function.
13618 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
13621 * If 1, then control and configuration of bitmap pattern
13622 * packet are supported on this function.
13624 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
13627 * If set to 1, then the control and configuration of rate limit
13628 * of an allocated TX ring on the queried function is supported.
13630 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
13633 * If 1, then control and configuration of minimum and
13634 * maximum bandwidths are supported on the queried function.
13636 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
13639 * If the query is for a VF, then this flag shall be ignored.
13640 * If this query is for a PF and this flag is set to 1,
13641 * then the PF has the capability to set the rate limits
13642 * on the TX rings of its children VFs.
13643 * If this query is for a PF and this flag is set to 0, then
13644 * the PF does not have the capability to set the rate limits
13645 * on the TX rings of its children VFs.
13647 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
13650 * If the query is for a VF, then this flag shall be ignored.
13651 * If this query is for a PF and this flag is set to 1,
13652 * then the PF has the capability to set the minimum and/or
13653 * maximum bandwidths for its children VFs.
13654 * If this query is for a PF and this flag is set to 0, then
13655 * the PF does not have the capability to set the minimum or
13656 * maximum bandwidths for its children VFs.
13658 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
13661 * Standard TX Ring mode is used for the allocation of TX ring
13662 * and underlying scheduling resources that allow bandwidth
13663 * reservation and limit settings on the queried function.
13664 * If set to 1, then standard TX ring mode is supported
13665 * on the queried function.
13666 * If set to 0, then standard TX ring mode is not available
13667 * on the queried function.
13669 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
13672 * If the query is for a VF, then this flag shall be ignored,
13673 * If this query is for a PF and this flag is set to 1,
13674 * then the PF has the capability to detect GENEVE tunnel
13677 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
13680 * If the query is for a VF, then this flag shall be ignored,
13681 * If this query is for a PF and this flag is set to 1,
13682 * then the PF has the capability to detect NVGRE tunnel
13685 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
13688 * If the query is for a VF, then this flag shall be ignored,
13689 * If this query is for a PF and this flag is set to 1,
13690 * then the PF has the capability to detect GRE tunnel
13693 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
13696 * If the query is for a VF, then this flag shall be ignored,
13697 * If this query is for a PF and this flag is set to 1,
13698 * then the PF has the capability to detect MPLS tunnel
13701 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
13704 * If the query is for a VF, then this flag shall be ignored,
13705 * If this query is for a PF and this flag is set to 1,
13706 * then the PF has the capability to support pcie stats.
13708 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
13711 * If the query is for a VF, then this flag shall be ignored,
13712 * If this query is for a PF and this flag is set to 1,
13713 * then the PF has the capability to adopt the VF's belonging
13716 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
13719 * If the query is for a VF, then this flag shall be ignored,
13720 * If this query is for a PF and this flag is set to 1,
13721 * then the PF has the administrative privilege to configure another PF
13723 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
13726 * If the query is for a VF, then this flag shall be ignored.
13727 * If this query is for a PF and this flag is set to 1, then
13728 * the PF will know that the firmware has the capability to track
13729 * the virtual link status.
13731 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
13734 * If 1, then this function supports the push mode that uses
13735 * write combine buffers and the long inline tx buffer descriptor.
13737 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
13740 * If 1, then FW has capability to allocate TX rings dynamically
13741 * in ring alloc even if PF reserved pool is zero.
13742 * This bit will be used only for PFs.
13744 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
13747 * When this bit is '1', it indicates that core firmware is
13748 * capable of Hot Reset.
13750 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
13753 * This flag will be set to 1 by the FW if FW supports adapter error
13756 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
13759 * If the query is for a VF, then this flag shall be ignored.
13760 * If this query is for a PF and this flag is set to 1, then
13761 * the PF has the capability to support extended stats.
13763 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
13764 UINT32_C(0x1000000)
13766 * If the query is for a VF, then this flag shall be ignored.
13767 * If this query is for a PF and this flag is set to 1, then host
13768 * must initiate reset or reload (or fastboot) the firmware image
13769 * upon detection of device shutdown state.
13771 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
13772 UINT32_C(0x2000000)
13774 * If the query is for a VF, then this flag (always set to 0) shall
13775 * be ignored. If this query is for a PF and this flag is set to 1,
13776 * host, when registered for the default vnic change async event,
13777 * receives async notification whenever a default vnic state is
13778 * changed for any of child or adopted VFs.
13780 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
13781 UINT32_C(0x4000000)
13782 /* If set to 1, then the vlan acceleration for TX is disabled. */
13783 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
13784 UINT32_C(0x8000000)
13786 * When this bit is '1', it indicates that core firmware supports
13787 * DBG_COREDUMP_XXX commands.
13789 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
13790 UINT32_C(0x10000000)
13792 * When this bit is '1', it indicates that core firmware supports
13793 * DBG_CRASHDUMP_XXX commands.
13795 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
13796 UINT32_C(0x20000000)
13798 * If the query is for a VF, then this flag should be ignored.
13799 * If the query is for a PF and this flag is set to 1, then
13800 * the PF has the capability to support retrieval of
13801 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
13802 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
13803 * If this flag is set to 1, only that (supported) command should
13804 * be used for retrieval of PFC related statistics (rather than
13805 * hwrm_port_qstats_ext command, which could previously be used).
13807 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
13808 UINT32_C(0x40000000)
13810 * When this bit is '1', it indicates that core firmware supports
13811 * DBG_QCAPS command
13813 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
13814 UINT32_C(0x80000000)
13816 * This value is current MAC address configured for this
13817 * function. A value of 00-00-00-00-00-00 indicates no
13818 * MAC address is currently configured.
13820 uint8_t mac_address[6];
13822 * The maximum number of RSS/COS contexts that can be
13823 * allocated to the function.
13825 uint16_t max_rsscos_ctx;
13827 * The maximum number of completion rings that can be
13828 * allocated to the function.
13830 uint16_t max_cmpl_rings;
13832 * The maximum number of transmit rings that can be
13833 * allocated to the function.
13835 uint16_t max_tx_rings;
13837 * The maximum number of receive rings that can be
13838 * allocated to the function.
13840 uint16_t max_rx_rings;
13842 * The maximum number of L2 contexts that can be
13843 * allocated to the function.
13845 uint16_t max_l2_ctxs;
13847 * The maximum number of VNICs that can be
13848 * allocated to the function.
13850 uint16_t max_vnics;
13852 * The identifier for the first VF enabled on a PF. This
13853 * is valid only on the PF with SR-IOV enabled.
13854 * 0xFF... (All Fs) if this command is called on a PF with
13855 * SR-IOV disabled or on a VF.
13857 uint16_t first_vf_id;
13859 * The maximum number of VFs that can be
13860 * allocated to the function. This is valid only on the
13861 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
13862 * command is called on a PF with SR-IOV disabled or
13867 * The maximum number of statistic contexts that can be
13868 * allocated to the function.
13870 uint16_t max_stat_ctx;
13872 * The maximum number of Encapsulation records that can be
13873 * offloaded by this function.
13875 uint32_t max_encap_records;
13877 * The maximum number of decapsulation records that can
13878 * be offloaded by this function.
13880 uint32_t max_decap_records;
13882 * The maximum number of Exact Match (EM) flows that can be
13883 * offloaded by this function on the TX side.
13885 uint32_t max_tx_em_flows;
13887 * The maximum number of Wildcard Match (WM) flows that can
13888 * be offloaded by this function on the TX side.
13890 uint32_t max_tx_wm_flows;
13892 * The maximum number of Exact Match (EM) flows that can be
13893 * offloaded by this function on the RX side.
13895 uint32_t max_rx_em_flows;
13897 * The maximum number of Wildcard Match (WM) flows that can
13898 * be offloaded by this function on the RX side.
13900 uint32_t max_rx_wm_flows;
13902 * The maximum number of multicast filters that can
13903 * be supported by this function on the RX side.
13905 uint32_t max_mcast_filters;
13907 * The maximum value of flow_id that can be supported
13908 * in completion records.
13910 uint32_t max_flow_id;
13912 * The maximum number of HW ring groups that can be
13913 * supported on this function.
13915 uint32_t max_hw_ring_grps;
13917 * The maximum number of strict priority transmit rings
13918 * that can be allocated to the function.
13919 * This number indicates the maximum number of TX rings
13920 * that can be assigned strict priorities out of the
13921 * maximum number of TX rings that can be allocated
13922 * (max_tx_rings) to the function.
13924 uint16_t max_sp_tx_rings;
13926 * The maximum number of MSI-X vectors that may be allocated across
13927 * all VFs for the function. This is valid only on the PF with SR-IOV
13928 * enabled. Returns zero if this command is called on a PF with
13929 * SR-IOV disabled or on a VF.
13931 uint16_t max_msix_vfs;
13932 uint32_t flags_ext;
13934 * If 1, the device can be configured to set the ECN bits in the
13935 * IP header of received packets if the receive queue length
13936 * exceeds a given threshold.
13938 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
13941 * If 1, the device can report the number of received packets
13942 * that it marked as having experienced congestion.
13944 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
13947 * If 1, the device can report extended hw statistics (including
13948 * additional tpa statistics).
13950 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
13953 * If set to 1, then the core firmware has support to enable/
13954 * disable hot reset support for interface dynamically through
13957 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
13959 /* If 1, the proxy mode is supported on this function */
13960 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
13963 * If 1, the tx rings source interface override feature is supported
13964 * on this function.
13966 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
13969 * If 1, the device supports scheduler queues. SCHQs can be managed
13970 * using RING_SCHQ_ALLOC/CFG/FREE commands.
13972 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
13975 * If set to 1, then this function supports the TX push mode that
13976 * uses ping-pong buffers from the push pages.
13978 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
13981 * If set to 1, then this function doesn't have the privilege to
13982 * configure the EVB mode of the port it uses.
13984 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
13987 * If set to 1, then the HW and FW support the SoC packet DMA
13988 * datapath between SoC and NIC. This function can act as the
13989 * HWRM communication transport agent on behalf of the SoC SPD
13990 * software module. This capability is only advertised to the
13993 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
13996 * If set to 1, then this function supports FW_LIVEPATCH for
13997 * firmware livepatch commands.
13999 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
14002 * When this bit is '1', it indicates that core firmware is
14003 * capable of fast Reset.
14005 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
14008 * When this bit is '1', it indicates that firmware and hardware
14009 * are capable of updating tx_metadata via hwrm_ring_cfg command.
14011 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
14014 * If set to 1, then the device can report the action
14015 * needed to activate set nvm options.
14017 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
14020 * When this bit is '1', it indicates that the BD metadata feature
14021 * is supported for this function.
14023 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
14026 * When this bit is '1', it indicates that the echo request feature
14027 * is supported for this function. If the driver registers for the
14028 * echo request asynchronous event, then the firmware can send an
14029 * unsolicited echo request to the driver and expect an echo
14032 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
14035 * When this bit is '1', it indicates that core firmware supports
14036 * NPAR 1.2 on this function.
14038 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \
14040 /* When this bit is '1', it indicates that PTM feature is supported. */
14041 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \
14043 /* When this bit is '1', it indicates that PPS feature is supported. */
14044 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \
14047 * When this bit is '1', it indicates that VF config. change
14048 * async event is supported on the parent PF if the async.
14049 * event is registered by the PF.
14051 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \
14054 * When this bit is '1', the NIC supports configuration of
14055 * partition_min_bw and partition_max_bw. Configuration of a
14056 * minimum guaranteed bandwidth is only supported if the
14057 * min_bw_supported flag is also set.
14059 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \
14062 * When this bit is '1', the FW supports configuration of
14063 * PCP and TPID values of the default VLAN.
14065 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \
14067 /* When this bit is '1', it indicates that HW and FW support KTLS. */
14068 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \
14071 * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG
14072 * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions
14073 * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive
14074 * rate control. Configuration of a minimum guaranteed bandwidth
14075 * is only supported if the min_bw_supported flag is also set.
14077 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \
14080 * When this bit is '1', the firmware supports enforcement of
14081 * minimum guaranteed bandwidth. A minimum guaranteed bandwidth
14082 * could be configured for a partition or for an endpoint. Firmware
14083 * only sets this flag if one or both of the ep_rate_control and
14084 * partition_bw_supported flags are set.
14086 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \
14087 UINT32_C(0x1000000)
14089 * When this bit is '1', HW supports TX coalesced completion
14092 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \
14093 UINT32_C(0x2000000)
14095 * When this bit is '1', it indicates the FW has full support
14096 * for all backing store types with the BACKING_STORE_CFG/QCFG
14099 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \
14100 UINT32_C(0x4000000)
14102 * When this bit is '1', it indicates the FW forces to use the
14103 * BACKING_STORE_CFG/QCFG V2 APIs.
14105 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \
14106 UINT32_C(0x8000000)
14108 * When this bit is '1', it indicates that FW will support a single
14109 * 64bit real time clock for PTP.
14111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED \
14112 UINT32_C(0x10000000)
14114 * When this bit is '1', it indicates the FW is capable of
14115 * supporting Doorbell Pacing.
14117 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED \
14118 UINT32_C(0x20000000)
14120 * When this bit is '1', it indicates the FW is capable of
14121 * supporting HW based doorbell drop recovery.
14123 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED \
14124 UINT32_C(0x40000000)
14126 * When this bit is '1', it indicates the driver can disable the CQ
14127 * overflow detection and can also skip the index updates for CQ.
14129 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED \
14130 UINT32_C(0x80000000)
14131 /* The maximum number of SCHQs supported by this device. */
14133 uint8_t mpc_chnls_cap;
14135 * When this bit is '1', it indicates that HW and firmware
14136 * supports the use of a MPC channel with destination set
14137 * to the TX crypto engine block.
14139 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
14141 * When this bit is '1', it indicates that HW and firmware
14142 * supports the use of a MPC channel with destination set
14143 * to the RX crypto engine block.
14145 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
14147 * When this bit is '1', it indicates that HW and firmware
14148 * supports the use of a MPC channel with destination set
14149 * to the TX configurable flow processing block.
14151 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
14153 * When this bit is '1', it indicates that HW and firmware
14154 * supports the use of a MPC channel with destination set
14155 * to the RX configurable flow processing block.
14157 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
14159 * When this bit is '1', it indicates that HW and firmware
14160 * supports the use of a MPC channel with destination set
14161 * to the primate processor block.
14163 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
14165 * Maximum number of Key Contexts supported per HWRM
14166 * function call for allocating Key Contexts.
14168 uint16_t max_key_ctxs_alloc;
14169 uint32_t flags_ext2;
14171 * When this bit is '1', it indicates that FW will support
14172 * timestamping on all RX packets, not just PTP type packets.
14174 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED \
14176 /* When this bit is '1', it indicates that HW and FW support QUIC. */
14177 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \
14179 uint16_t tunnel_disable_flag;
14181 * When this bit is '1', it indicates that the VXLAN parsing
14182 * is disabled in hardware
14184 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN \
14187 * When this bit is '1', it indicates that the NGE parsing
14188 * is disabled in hardware
14190 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE \
14193 * When this bit is '1', it indicates that the NVGRE parsing
14194 * is disabled in hardware
14196 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE \
14199 * When this bit is '1', it indicates that the L2GRE parsing
14200 * is disabled in hardware
14202 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE \
14205 * When this bit is '1', it indicates that the GRE parsing
14206 * is disabled in hardware
14208 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE \
14211 * When this bit is '1', it indicates that the IPINIP parsing
14212 * is disabled in hardware
14214 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP \
14217 * When this bit is '1', it indicates that the MPLS parsing
14218 * is disabled in hardware
14220 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS \
14223 * When this bit is '1', it indicates that the PPPOE parsing
14224 * is disabled in hardware
14226 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \
14230 * This field is used in Output records to indicate that the output
14231 * is completely written to RAM. This field should be read as '1'
14232 * to indicate that the output has been completely written.
14233 * When writing a command completion or response to an internal
14234 * processor, the order of writes has to be such that this field is
14240 /******************
14242 ******************/
14245 /* hwrm_func_qcfg_input (size:192b/24B) */
14246 struct hwrm_func_qcfg_input {
14247 /* The HWRM command request type. */
14250 * The completion ring to send the completion event on. This should
14251 * be the NQ ID returned from the `nq_alloc` HWRM command.
14253 uint16_t cmpl_ring;
14255 * The sequence ID is used by the driver for tracking multiple
14256 * commands. This ID is treated as opaque data by the firmware and
14257 * the value is returned in the `hwrm_resp_hdr` upon completion.
14261 * The target ID of the command:
14262 * * 0x0-0xFFF8 - The function ID
14263 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14264 * * 0xFFFD - Reserved for user-space HWRM interface
14267 uint16_t target_id;
14269 * A physical address pointer pointing to a host buffer that the
14270 * command's response data will be written. This can be either a host
14271 * physical address (HPA) or a guest physical address (GPA) and must
14272 * point to a physically contiguous block of memory.
14274 uint64_t resp_addr;
14276 * Function ID of the function that is being queried.
14277 * 0xFF... (All Fs) if the query is for the requesting
14279 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
14280 * to be used by a trusted VF to query its parent PF.
14283 uint8_t unused_0[6];
14286 /* hwrm_func_qcfg_output (size:896b/112B) */
14287 struct hwrm_func_qcfg_output {
14288 /* The specific error status for the command. */
14289 uint16_t error_code;
14290 /* The HWRM command request type. */
14292 /* The sequence ID from the original command. */
14294 /* The length of the response data in number of bytes. */
14297 * FID value. This value is used to identify operations on the PCI
14298 * bus as belonging to a particular PCI function.
14302 * Port ID of port that this function is associated with.
14303 * 0xFF... (All Fs) if this function is not associated with
14308 * This value is the current VLAN setting for this
14309 * function. The value of 0 for this field indicates
14310 * no priority tagging or VLAN is used.
14311 * This field's format is same as 802.1Q Tag's
14312 * Tag Control Information (TCI) format that includes both
14313 * Priority Code Point (PCP) and VLAN Identifier (VID).
14318 * If 1, then magic packet based Out-Of-Box WoL is enabled on
14319 * the port associated with this function.
14321 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
14324 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
14325 * on the port associated with this function.
14327 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
14330 * If set to 1, then FW based DCBX agent is enabled and running on
14331 * the port associated with this function.
14332 * If set to 0, then DCBX agent is not running in the firmware.
14334 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
14337 * Standard TX Ring mode is used for the allocation of TX ring
14338 * and underlying scheduling resources that allow bandwidth
14339 * reservation and limit settings on the queried function.
14340 * If set to 1, then standard TX ring mode is enabled
14341 * on the queried function.
14342 * If set to 0, then the standard TX ring mode is disabled
14343 * on the queried function. In this extended TX ring resource
14344 * mode, the minimum and maximum bandwidth settings are not
14345 * supported to allow the allocation of TX rings to span multiple
14348 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
14351 * If set to 1 then FW based LLDP agent is enabled and running on
14352 * the port associated with this function.
14353 * If set to 0 then the LLDP agent is not running in the firmware.
14355 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
14358 * If set to 1, then multi-host mode is active for this function.
14359 * The NIC is attached to two or more independent host systems
14360 * through two or more PCIe endpoints.
14361 * If set to 0, then multi-host mode is inactive for this function
14362 * or not applicable for this device.
14364 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
14367 * If the function that is being queried is a PF, then the HWRM shall
14368 * set this field to 0 and the HWRM client shall ignore this field.
14369 * If the function that is being queried is a VF, then the HWRM shall
14370 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
14371 * shall set this field to 0.
14373 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
14376 * If set to 1, then secure mode is enabled for this function or device.
14377 * If set to 0, then secure mode is disabled (or normal mode) for this
14378 * function or device.
14380 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
14383 * If set to 1, then this PF is enabled with a preboot driver that
14384 * requires access to the legacy L2 ring model and legacy 32b
14385 * doorbells. If set to 0, then this PF is not allowed to use
14386 * the legacy L2 rings. This feature is not allowed on VFs and
14387 * is only relevant for devices that require a context backing
14390 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
14393 * If set to 1, then the firmware and all currently registered driver
14394 * instances support hot reset. The hot reset support will be updated
14395 * dynamically based on the driver interface advertisement.
14396 * If set to 0, then the adapter is not currently able to initiate
14399 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
14402 * If set to 1, then the PPP tx push mode is enabled for all the
14403 * reserved TX rings of this function. If set to 0, then PPP tx push
14404 * mode is disabled for all the reserved TX rings of this function.
14406 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
14409 * If set to 1, then the firmware will notify driver using async
14410 * event when a ring is disabled due to a Hardware error.
14412 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
14415 * If set to 1, then the firmware and all currently registered driver
14416 * instances support fast reset. The fast reset support will be
14417 * updated dynamically based on the driver interface advertisement.
14418 * If set to 0, then the adapter is not currently able to initiate
14421 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
14424 * If set to 1, then multi-root mode is active for this function.
14425 * The NIC is attached to a single host with a single operating
14426 * system, but through two or more PCIe endpoints.
14427 * If set to 0, then multi-root mode is inactive for this function
14428 * or not applicable for this device.
14430 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
14433 * This flag indicates RDMA support for child VFS of
14434 * a physical function.
14435 * If set to 1, RoCE is supported on all child VFs.
14436 * If set to 0, RoCE is disabled on all child VFs.
14438 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \
14441 * This value is current MAC address configured for this
14442 * function. A value of 00-00-00-00-00-00 indicates no
14443 * MAC address is currently configured.
14445 uint8_t mac_address[6];
14447 * This value is current PCI ID of this
14448 * function. If ARI is enabled, then it is
14449 * Bus Number (8b):Function Number(8b). Otherwise, it is
14450 * Bus Number (8b):Device Number (4b):Function Number(4b).
14451 * If multi-host mode is active, the 4 lsb will indicate
14452 * the PF index for this function.
14456 * The number of RSS/COS contexts currently
14457 * allocated to the function.
14459 uint16_t alloc_rsscos_ctx;
14461 * The number of completion rings currently allocated to
14462 * the function. This does not include the rings allocated
14463 * to any children functions if any.
14465 uint16_t alloc_cmpl_rings;
14467 * The number of transmit rings currently allocated to
14468 * the function. This does not include the rings allocated
14469 * to any children functions if any.
14471 uint16_t alloc_tx_rings;
14473 * The number of receive rings currently allocated to
14474 * the function. This does not include the rings allocated
14475 * to any children functions if any.
14477 uint16_t alloc_rx_rings;
14478 /* The allocated number of L2 contexts to the function. */
14479 uint16_t alloc_l2_ctx;
14480 /* The allocated number of vnics to the function. */
14481 uint16_t alloc_vnics;
14483 * The maximum transmission unit of the function
14484 * configured by the admin pf.
14485 * If the reported mtu value is non-zero then it will be used for the
14486 * rings allocated on this function, otherwise the default
14487 * value is used if ring MTU is not specified.
14488 * The driver cannot use any MTU bigger than this value
14489 * if it is non-zero.
14491 uint16_t admin_mtu;
14493 * The maximum receive unit of the function.
14494 * For vnics allocated on this function, this default
14495 * value is used if vnic MRU is not specified.
14498 /* The statistics context assigned to a function. */
14499 uint16_t stat_ctx_id;
14501 * The HWRM shall return Unknown value for this field
14502 * when this command is used to query VF's configuration.
14504 uint8_t port_partition_type;
14505 /* Single physical function */
14506 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
14507 /* Multiple physical functions */
14508 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
14509 /* Network Partitioning 1.0 */
14510 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
14511 /* Network Partitioning 1.5 */
14512 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
14513 /* Network Partitioning 2.0 */
14514 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
14515 /* Network Partitioning 1.2 */
14516 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
14518 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
14520 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
14521 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
14523 * This field will indicate number of physical functions on this port_partition.
14524 * HWRM shall return unavail (i.e. value of 0) for this field
14525 * when this command is used to query VF's configuration or
14526 * from older firmware that doesn't support this field.
14528 uint8_t port_pf_cnt;
14529 /* number of PFs is not available */
14530 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
14531 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
14532 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
14534 * The default VNIC ID assigned to a function that is
14537 uint16_t dflt_vnic_id;
14538 uint16_t max_mtu_configured;
14540 * Minimum guaranteed transmit bandwidth for this function. When
14541 * specified for a PF, does not affect traffic from the PF's child VFs.
14542 * A value of 0 indicates the minimum bandwidth is not configured.
14545 /* The bandwidth value. */
14546 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
14547 UINT32_C(0xfffffff)
14548 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
14549 /* The granularity of the value (bits or bytes). */
14550 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
14551 UINT32_C(0x10000000)
14552 /* Value is in bits. */
14553 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
14554 (UINT32_C(0x0) << 28)
14555 /* Value is in bytes. */
14556 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
14557 (UINT32_C(0x1) << 28)
14558 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
14559 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
14560 /* bw_value_unit is 3 b */
14561 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
14562 UINT32_C(0xe0000000)
14563 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
14564 /* Value is in Mb or MB (base 10). */
14565 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
14566 (UINT32_C(0x0) << 29)
14567 /* Value is in Kb or KB (base 10). */
14568 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
14569 (UINT32_C(0x2) << 29)
14570 /* Value is in bits or bytes. */
14571 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
14572 (UINT32_C(0x4) << 29)
14573 /* Value is in Gb or GB (base 10). */
14574 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
14575 (UINT32_C(0x6) << 29)
14576 /* Value is in 1/100th of a percentage of link bandwidth. */
14577 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14578 (UINT32_C(0x1) << 29)
14580 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
14581 (UINT32_C(0x7) << 29)
14582 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
14583 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
14585 * Maximum transmit rate for this function. When specified for a PF,
14586 * does not affect traffic from the PF's child VFs.
14587 * A value of 0 indicates that the maximum bandwidth is not configured.
14590 /* The bandwidth value. */
14591 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
14592 UINT32_C(0xfffffff)
14593 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
14594 /* The granularity of the value (bits or bytes). */
14595 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
14596 UINT32_C(0x10000000)
14597 /* Value is in bits. */
14598 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
14599 (UINT32_C(0x0) << 28)
14600 /* Value is in bytes. */
14601 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
14602 (UINT32_C(0x1) << 28)
14603 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
14604 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
14605 /* bw_value_unit is 3 b */
14606 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
14607 UINT32_C(0xe0000000)
14608 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
14609 /* Value is in Mb or MB (base 10). */
14610 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
14611 (UINT32_C(0x0) << 29)
14612 /* Value is in Kb or KB (base 10). */
14613 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
14614 (UINT32_C(0x2) << 29)
14615 /* Value is in bits or bytes. */
14616 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
14617 (UINT32_C(0x4) << 29)
14618 /* Value is in Gb or GB (base 10). */
14619 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
14620 (UINT32_C(0x6) << 29)
14621 /* Value is in 1/100th of a percentage of link bandwidth. */
14622 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14623 (UINT32_C(0x1) << 29)
14625 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
14626 (UINT32_C(0x7) << 29)
14627 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
14628 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
14630 * This value indicates the Edge virtual bridge mode for the
14631 * domain that this function belongs to.
14634 /* No Edge Virtual Bridging (EVB) */
14635 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
14636 /* Virtual Ethernet Bridge (VEB) */
14637 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
14638 /* Virtual Ethernet Port Aggregator (VEPA) */
14639 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
14640 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
14641 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
14644 * This value indicates the PCIE device cache line size.
14645 * The cache line size allows the DMA writes to terminate and
14646 * start at the cache boundary.
14648 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
14650 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
14651 /* Cache Line Size 64 bytes */
14652 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
14654 /* Cache Line Size 128 bytes */
14655 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
14657 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
14658 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
14659 /* This value is the virtual link admin state setting. */
14660 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
14662 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
14663 /* Admin link state is in forced down mode. */
14664 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
14665 (UINT32_C(0x0) << 2)
14666 /* Admin link state is in forced up mode. */
14667 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
14668 (UINT32_C(0x1) << 2)
14669 /* Admin link state is in auto mode - follows the physical link state. */
14670 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
14671 (UINT32_C(0x2) << 2)
14672 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
14673 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
14674 /* Reserved for future. */
14675 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
14677 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
14679 * The number of VFs that are allocated to the function.
14680 * This is valid only on the PF with SR-IOV enabled.
14681 * 0xFF... (All Fs) if this command is called on a PF with
14682 * SR-IOV disabled or on a VF.
14684 uint16_t alloc_vfs;
14686 * The number of allocated multicast filters for this
14687 * function on the RX side.
14689 uint32_t alloc_mcast_filters;
14691 * The number of allocated HW ring groups for this
14694 uint32_t alloc_hw_ring_grps;
14696 * The number of strict priority transmit rings out of
14697 * currently allocated TX rings to the function
14698 * (alloc_tx_rings).
14700 uint16_t alloc_sp_tx_rings;
14702 * The number of statistics contexts
14703 * currently reserved for the function.
14705 uint16_t alloc_stat_ctx;
14707 * This field specifies how many NQs are reserved for the PF.
14708 * Remaining NQs that belong to the PF are available for VFs.
14709 * Once a PF has created VFs, it cannot change how many NQs are
14710 * reserved for itself (since the NQs must be contiguous in HW).
14712 uint16_t alloc_msix;
14714 * The number of registered VF’s associated with the PF. This field
14715 * should be ignored when the request received on the VF interface.
14716 * This field will be updated on the PF interface to initiate
14717 * the unregister request on PF in the HOT Reset Process.
14719 uint16_t registered_vfs;
14721 * The size of the doorbell BAR in KBytes reserved for L2 including
14722 * any area that is shared between L2 and RoCE. The L2 driver
14723 * should only map the L2 portion of the doorbell BAR. Any rounding
14724 * of the BAR size to the native CPU page size should be performed
14725 * by the driver. If the value is zero, no special partitioning
14726 * of the doorbell BAR between L2 and RoCE is required.
14728 uint16_t l2_doorbell_bar_size_kb;
14731 * For backward compatibility this field must be set to 1.
14732 * Older drivers might look for this field to be 1 before
14733 * processing the message.
14737 * This GRC address location is used by the Host driver interfaces to poll
14738 * the adapter ready state to re-initiate the registration process again
14739 * after receiving the RESET Notify event.
14741 uint32_t reset_addr_poll;
14743 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
14744 * this value to find out the doorbell page offset from the BAR.
14746 uint16_t legacy_l2_db_size_kb;
14747 uint16_t svif_info;
14749 * This field specifies the source virtual interface of the function being
14750 * queried. Drivers can use this to program svif field in the L2 context
14753 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
14754 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
14755 /* This field specifies whether svif is valid or not */
14756 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
14759 * When this bit is '1', it indicates that a MPC channel with
14760 * destination set to the TX crypto engine block is enabled.
14762 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
14765 * When this bit is '1', it indicates that a MPC channel with
14766 * destination set to the RX crypto engine block is enabled.
14768 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
14771 * When this bit is '1', it indicates that a MPC channel with
14772 * destination set to the TX configurable flow processing block is
14775 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
14778 * When this bit is '1', it indicates that a MPC channel with
14779 * destination set to the RX configurable flow processing block is
14782 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
14785 * When this bit is '1', it indicates that a MPC channel with
14786 * destination set to the primate processor block is enabled.
14788 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
14790 uint8_t unused_2[3];
14792 * Minimum guaranteed bandwidth for the network partition made up
14793 * of the caller physical function and all its child virtual
14794 * functions. The rate is specified as a percentage of the bandwidth
14795 * of the link the partition is associated with. A value of 0
14796 * indicates that no minimum bandwidth is configured.
14797 * The format of this field is defined to match min_bw, even though
14798 * the partition minimum rate is always specified as a percentage.
14800 uint32_t partition_min_bw;
14801 /* The bandwidth value. */
14802 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
14803 UINT32_C(0xfffffff)
14804 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
14807 * The granularity of the value (bits or bytes). Firmware never sets
14810 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \
14811 UINT32_C(0x10000000)
14812 /* Value is in bits. */
14813 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \
14814 (UINT32_C(0x0) << 28)
14815 /* Value is in bytes. */
14816 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \
14817 (UINT32_C(0x1) << 28)
14818 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \
14819 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES
14820 /* Always percentage of link bandwidth. */
14821 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
14822 UINT32_C(0xe0000000)
14823 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
14825 /* Bandwidth value is in hundredths of a percent of link bandwidth. */
14826 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14827 (UINT32_C(0x1) << 29)
14828 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
14829 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
14831 * The maximum bandwidth that may be used by the network partition
14832 * made up of the caller physical function and all its child virtual
14833 * functions. The rate is specified as a percentage of the bandwidth
14834 * of the link the partition is associated with. A value of 0
14835 * indicates that no maximum bandwidth is configured.
14836 * The format of this field is defined to match max_bw, even though
14837 * the partition bandwidth must be specified as a percentage.
14839 uint32_t partition_max_bw;
14840 /* The bandwidth value. */
14841 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
14842 UINT32_C(0xfffffff)
14843 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
14846 * The granularity of the value (bits or bytes). Firmware never sets
14849 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \
14850 UINT32_C(0x10000000)
14851 /* Value is in bits. */
14852 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \
14853 (UINT32_C(0x0) << 28)
14854 /* Value is in bytes. */
14855 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \
14856 (UINT32_C(0x1) << 28)
14857 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \
14858 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES
14859 /* Always a percentage of link bandwidth. */
14860 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
14861 UINT32_C(0xe0000000)
14862 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
14864 /* Value is in hundredths of a percent of link bandwidth. */
14865 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14866 (UINT32_C(0x1) << 29)
14867 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
14868 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
14870 * The maximum transmission unit of the function
14871 * configured by the host pf/vf.
14872 * If the reported mtu value is non-zero then it will be used for the
14873 * rings allocated on this function, otherwise the default
14874 * value is used if ring MTU is not specified.
14877 /* Number of Tx Key Contexts allocated. */
14878 uint16_t alloc_tx_key_ctxs;
14879 /* Number of Rx Key Contexts allocated. */
14880 uint16_t alloc_rx_key_ctxs;
14881 uint8_t unused_3[5];
14883 * This field is used in Output records to indicate that the output
14884 * is completely written to RAM. This field should be read as '1'
14885 * to indicate that the output has been completely written.
14886 * When writing a command completion or response to an internal processor,
14887 * the order of writes has to be such that this field is written last.
14897 /* hwrm_func_cfg_input (size:896b/112B) */
14898 struct hwrm_func_cfg_input {
14899 /* The HWRM command request type. */
14902 * The completion ring to send the completion event on. This should
14903 * be the NQ ID returned from the `nq_alloc` HWRM command.
14905 uint16_t cmpl_ring;
14907 * The sequence ID is used by the driver for tracking multiple
14908 * commands. This ID is treated as opaque data by the firmware and
14909 * the value is returned in the `hwrm_resp_hdr` upon completion.
14913 * The target ID of the command:
14914 * * 0x0-0xFFF8 - The function ID
14915 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14916 * * 0xFFFD - Reserved for user-space HWRM interface
14919 uint16_t target_id;
14921 * A physical address pointer pointing to a host buffer that the
14922 * command's response data will be written. This can be either a host
14923 * physical address (HPA) or a guest physical address (GPA) and must
14924 * point to a physically contiguous block of memory.
14926 uint64_t resp_addr;
14928 * Function ID of the function that is being
14930 * If set to 0xFF... (All Fs), then the configuration is
14931 * for the requesting function.
14935 * This field specifies how many NQs will be reserved for the PF.
14936 * Remaining NQs that belong to the PF become available for VFs.
14937 * Once a PF has created VFs, it cannot change how many NQs are
14938 * reserved for itself (since the NQs must be contiguous in HW).
14943 * When this bit is '1', the function is disabled with
14944 * source MAC address check.
14945 * This is an anti-spoofing check. If this flag is set,
14946 * then the function shall be configured to disallow
14947 * transmission of frames with the source MAC address that
14948 * is configured for this function.
14950 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
14953 * When this bit is '1', the function is enabled with
14954 * source MAC address check.
14955 * This is an anti-spoofing check. If this flag is set,
14956 * then the function shall be configured to allow
14957 * transmission of frames with the source MAC address that
14958 * is configured for this function.
14960 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
14963 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
14965 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
14967 * Standard TX Ring mode is used for the allocation of TX ring
14968 * and underlying scheduling resources that allow bandwidth
14969 * reservation and limit settings on the queried function.
14970 * If set to 1, then standard TX ring mode is requested to be
14971 * enabled on the function being configured.
14973 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
14976 * Standard TX Ring mode is used for the allocation of TX ring
14977 * and underlying scheduling resources that allow bandwidth
14978 * reservation and limit settings on the queried function.
14979 * If set to 1, then the standard TX ring mode is requested to
14980 * be disabled on the function being configured. In this extended
14981 * TX ring resource mode, the minimum and maximum bandwidth settings
14982 * are not supported to allow the allocation of TX rings to
14983 * span multiple scheduler nodes.
14985 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
14988 * If this bit is set, virtual mac address configured
14989 * in this command will be persistent over warm boot.
14991 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
14994 * This bit only applies to the VF. If this bit is set, the statistic
14995 * context counters will not be cleared when the statistic context is freed
14996 * or a function reset is called on VF. This bit will be cleared when the PF
14997 * is unloaded or a function reset is called on the PF.
14999 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
15002 * This bit requests that the firmware test to see if all the assets
15003 * requested in this command (i.e. number of TX rings) are available.
15004 * The firmware will return an error if the requested assets are
15005 * not available. The firwmare will NOT reserve the assets if they
15008 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
15011 * This bit requests that the firmware test to see if all the assets
15012 * requested in this command (i.e. number of RX rings) are available.
15013 * The firmware will return an error if the requested assets are
15014 * not available. The firwmare will NOT reserve the assets if they
15017 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
15020 * This bit requests that the firmware test to see if all the assets
15021 * requested in this command (i.e. number of CMPL rings) are available.
15022 * The firmware will return an error if the requested assets are
15023 * not available. The firwmare will NOT reserve the assets if they
15026 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
15029 * This bit requests that the firmware test to see if all the assets
15030 * requested in this command (i.e. number of RSS ctx) are available.
15031 * The firmware will return an error if the requested assets are
15032 * not available. The firwmare will NOT reserve the assets if they
15035 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
15038 * This bit requests that the firmware test to see if all the assets
15039 * requested in this command (i.e. number of ring groups) are available.
15040 * The firmware will return an error if the requested assets are
15041 * not available. The firwmare will NOT reserve the assets if they
15044 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
15047 * This bit requests that the firmware test to see if all the assets
15048 * requested in this command (i.e. number of stat ctx) are available.
15049 * The firmware will return an error if the requested assets are
15050 * not available. The firwmare will NOT reserve the assets if they
15053 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
15056 * This bit requests that the firmware test to see if all the assets
15057 * requested in this command (i.e. number of VNICs) are available.
15058 * The firmware will return an error if the requested assets are
15059 * not available. The firwmare will NOT reserve the assets if they
15062 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
15065 * This bit requests that the firmware test to see if all the assets
15066 * requested in this command (i.e. number of L2 ctx) are available.
15067 * The firmware will return an error if the requested assets are
15068 * not available. The firwmare will NOT reserve the assets if they
15071 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
15074 * This configuration change can be initiated by a PF driver. This
15075 * configuration request shall be targeted to a VF. From local host
15076 * resident HWRM clients, only the parent PF driver shall be allowed
15077 * to initiate this change on one of its children VFs. If this bit is
15078 * set to 1, then the VF that is being configured is requested to be
15081 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
15084 * When this bit it set, even if PF reserved pool size is zero,
15085 * FW will allow driver to create TX rings in ring alloc,
15086 * by reserving TX ring, S3 node dynamically.
15088 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
15091 * This bit requests that the firmware test to see if all the assets
15092 * requested in this command (i.e. number of NQ rings) are available.
15093 * The firmware will return an error if the requested assets are
15094 * not available. The firwmare will NOT reserve the assets if they
15097 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
15100 * This configuration change can be initiated by a PF driver. This
15101 * configuration request shall be targeted to a VF. From local host
15102 * resident HWRM clients, only the parent PF driver shall be allowed
15103 * to initiate this change on one of its children VFs. If this bit is
15104 * set to 1, then the VF that is being configured is requested to be
15107 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
15108 UINT32_C(0x1000000)
15110 * This bit is used by preboot drivers on a PF that require access
15111 * to the legacy L2 ring model and legacy 32b doorbells. This
15112 * feature is not allowed on VFs and is only relevant for devices
15113 * that require a context backing store.
15115 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
15116 UINT32_C(0x2000000)
15118 * If this bit is set to 0, then the interface does not support hot
15119 * reset capability which it advertised with the hot_reset_support
15120 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
15121 * flag to 0, adapter cannot do the hot reset. In this state, if the
15122 * firmware receives a hot reset request, firmware must fail the
15123 * request. If this bit is set to 1, then interface is renabling the
15124 * hot reset capability.
15126 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
15127 UINT32_C(0x4000000)
15129 * If this bit is set to 1, the PF driver is requesting FW
15130 * to enable PPP TX PUSH feature on all the TX rings specified in
15131 * the num_tx_rings field. By default, the PPP TX push feature is
15132 * disabled for all the TX rings of the function. This flag is
15133 * ignored if num_tx_rings field is not specified or the function
15134 * doesn't support PPP tx push feature.
15136 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
15137 UINT32_C(0x8000000)
15139 * If this bit is set to 1, the PF driver is requesting FW
15140 * to disable PPP TX PUSH feature on all the TX rings specified in
15141 * the num_tx_rings field. This flag is ignored if num_tx_rings
15142 * field is not specified or the function doesn't support PPP tx
15145 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
15146 UINT32_C(0x10000000)
15148 * If this bit is set to 1, the driver is requesting FW to enable
15149 * the BD_METADATA feature for this function. The FW returns error
15150 * on this request if the TX_METADATA is enabled for this function.
15152 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
15153 UINT32_C(0x20000000)
15155 * If this bit is set to 1, the driver is requesting FW to disable
15156 * the BD_METADATA feature for this function. The FW returns error
15157 * on this request if the TX_METADATA is enabled for this function.
15159 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
15160 UINT32_C(0x40000000)
15163 * This bit must be '1' for the admin_mtu field to be
15166 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \
15169 * This bit must be '1' for the mru field to be
15172 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
15175 * This bit must be '1' for the num_rsscos_ctxs field to be
15178 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
15181 * This bit must be '1' for the num_cmpl_rings field to be
15184 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
15187 * This bit must be '1' for the num_tx_rings field to be
15190 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
15193 * This bit must be '1' for the num_rx_rings field to be
15196 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
15199 * This bit must be '1' for the num_l2_ctxs field to be
15202 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
15205 * This bit must be '1' for the num_vnics field to be
15208 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
15211 * This bit must be '1' for the num_stat_ctxs field to be
15214 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
15217 * This bit must be '1' for the dflt_mac_addr field to be
15220 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
15223 * This bit must be '1' for the dflt_vlan field to be
15226 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
15229 * This bit must be '1' for the dflt_ip_addr field to be
15232 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
15235 * This bit must be '1' for the min_bw field to be
15238 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
15241 * This bit must be '1' for the max_bw field to be
15244 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
15247 * This bit must be '1' for the async_event_cr field to be
15250 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
15253 * This bit must be '1' for the vlan_antispoof_mode field to be
15256 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
15259 * This bit must be '1' for the allowed_vlan_pris field to be
15262 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
15265 * This bit must be '1' for the evb_mode field to be
15268 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
15271 * This bit must be '1' for the num_mcast_filters field to be
15274 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
15277 * This bit must be '1' for the num_hw_ring_grps field to be
15280 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
15283 * This bit must be '1' for the cache_linesize field to be
15286 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
15289 * This bit must be '1' for the num_msix field to be
15292 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
15295 * This bit must be '1' for the link admin state field to be
15298 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
15301 * This bit must be '1' for the hot_reset_if_en_dis field to be
15304 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
15307 * This bit must be '1' for the schq_id field to be
15310 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
15311 UINT32_C(0x1000000)
15313 * This bit must be '1' for the mpc_chnls field to be
15316 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
15317 UINT32_C(0x2000000)
15319 * This bit must be '1' for the partition_min_bw field to be
15322 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \
15323 UINT32_C(0x4000000)
15325 * This bit must be '1' for the partition_max_bw field to be
15328 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \
15329 UINT32_C(0x8000000)
15331 * This bit must be '1' for the tpid field to be
15332 * configured. This bit is only valid when dflt_vlan enable
15335 #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \
15336 UINT32_C(0x10000000)
15338 * This bit must be '1' for the host_mtu field to be
15341 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \
15342 UINT32_C(0x20000000)
15344 * This bit must be '1' for the number of Tx Key Contexts
15345 * field to be configured.
15347 #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \
15348 UINT32_C(0x40000000)
15350 * This bit must be '1' for the number of Rx Key Contexts
15351 * field to be configured.
15353 #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \
15354 UINT32_C(0x80000000)
15356 * This field can be used by the admin PF to configure
15357 * mtu of foster PFs.
15358 * The maximum transmission unit of the function.
15359 * The HWRM should make sure that the mtu of
15360 * the function does not exceed the mtu of the physical
15361 * port that this function is associated with.
15363 * In addition to configuring mtu per function, it is
15364 * possible to configure mtu per transmit ring.
15365 * By default, the mtu of each transmit ring associated
15366 * with a function is equal to the mtu of the function.
15367 * The HWRM should make sure that the mtu of each transmit
15368 * ring that is assigned to a function has a valid mtu.
15370 uint16_t admin_mtu;
15372 * The maximum receive unit of the function.
15373 * The HWRM should make sure that the mru of
15374 * the function does not exceed the mru of the physical
15375 * port that this function is associated with.
15377 * In addition to configuring mru per function, it is
15378 * possible to configure mru per vnic.
15379 * By default, the mru of each vnic associated
15380 * with a function is equal to the mru of the function.
15381 * The HWRM should make sure that the mru of each vnic
15382 * that is assigned to a function has a valid mru.
15386 * The number of RSS/COS contexts requested for the
15389 uint16_t num_rsscos_ctxs;
15391 * The number of completion rings requested for the
15392 * function. This does not include the rings allocated
15393 * to any children functions if any.
15395 uint16_t num_cmpl_rings;
15397 * The number of transmit rings requested for the function.
15398 * This does not include the rings allocated to any
15399 * children functions if any.
15401 uint16_t num_tx_rings;
15403 * The number of receive rings requested for the function.
15404 * This does not include the rings allocated
15405 * to any children functions if any.
15407 uint16_t num_rx_rings;
15408 /* The requested number of L2 contexts for the function. */
15409 uint16_t num_l2_ctxs;
15410 /* The requested number of vnics for the function. */
15411 uint16_t num_vnics;
15412 /* The requested number of statistic contexts for the function. */
15413 uint16_t num_stat_ctxs;
15415 * The number of HW ring groups that should
15416 * be reserved for this function.
15418 uint16_t num_hw_ring_grps;
15419 /* The default MAC address for the function being configured. */
15420 uint8_t dflt_mac_addr[6];
15422 * The default VLAN for the function being configured.
15423 * This field's format is same as 802.1Q Tag's
15424 * Tag Control Information (TCI) format that includes both
15425 * Priority Code Point (PCP) and VLAN Identifier (VID).
15427 uint16_t dflt_vlan;
15429 * The default IP address for the function being configured.
15430 * This address is only used in enabling source property check.
15432 uint32_t dflt_ip_addr[4];
15434 * Minimum guaranteed transmit bandwidth for this function. When
15435 * specified for a PF, does not affect traffic from the PF's child VFs.
15436 * A value of 0 indicates the minimum bandwidth is not configured.
15439 /* The bandwidth value. */
15440 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
15441 UINT32_C(0xfffffff)
15442 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
15443 /* The granularity of the value (bits or bytes). */
15444 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
15445 UINT32_C(0x10000000)
15446 /* Value is in bits. */
15447 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
15448 (UINT32_C(0x0) << 28)
15449 /* Value is in bytes. */
15450 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
15451 (UINT32_C(0x1) << 28)
15452 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
15453 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
15454 /* bw_value_unit is 3 b */
15455 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
15456 UINT32_C(0xe0000000)
15457 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
15458 /* Value is in Mb or MB (base 10). */
15459 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
15460 (UINT32_C(0x0) << 29)
15461 /* Value is in Kb or KB (base 10). */
15462 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
15463 (UINT32_C(0x2) << 29)
15464 /* Value is in bits or bytes. */
15465 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
15466 (UINT32_C(0x4) << 29)
15467 /* Value is in Gb or GB (base 10). */
15468 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
15469 (UINT32_C(0x6) << 29)
15470 /* Value is in 1/100th of a percentage of total bandwidth. */
15471 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15472 (UINT32_C(0x1) << 29)
15474 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
15475 (UINT32_C(0x7) << 29)
15476 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
15477 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
15479 * Maximum transmit rate for this function. When specified for a PF,
15480 * does not affect traffic from the PF's child VFs.
15481 * A value of 0 indicates that the maximum bandwidth is not configured.
15484 /* The bandwidth value. */
15485 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
15486 UINT32_C(0xfffffff)
15487 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
15488 /* The granularity of the value (bits or bytes). */
15489 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
15490 UINT32_C(0x10000000)
15491 /* Value is in bits. */
15492 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
15493 (UINT32_C(0x0) << 28)
15494 /* Value is in bytes. */
15495 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
15496 (UINT32_C(0x1) << 28)
15497 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
15498 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
15499 /* bw_value_unit is 3 b */
15500 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
15501 UINT32_C(0xe0000000)
15502 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
15503 /* Value is in Mb or MB (base 10). */
15504 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
15505 (UINT32_C(0x0) << 29)
15506 /* Value is in Kb or KB (base 10). */
15507 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
15508 (UINT32_C(0x2) << 29)
15509 /* Value is in bits or bytes. */
15510 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
15511 (UINT32_C(0x4) << 29)
15512 /* Value is in Gb or GB (base 10). */
15513 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
15514 (UINT32_C(0x6) << 29)
15515 /* Value is in 1/100th of a percentage of total bandwidth. */
15516 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15517 (UINT32_C(0x1) << 29)
15519 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
15520 (UINT32_C(0x7) << 29)
15521 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
15522 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
15524 * ID of the target completion ring for receiving asynchronous
15525 * event completions. If this field is not valid, then the
15526 * HWRM shall use the default completion ring of the function
15527 * that is being configured as the target completion ring for
15528 * providing any asynchronous event completions for that
15530 * If this field is valid, then the HWRM shall use the
15531 * completion ring identified by this ID as the target
15532 * completion ring for providing any asynchronous event
15533 * completions for the function that is being configured.
15535 uint16_t async_event_cr;
15536 /* VLAN Anti-spoofing mode. */
15537 uint8_t vlan_antispoof_mode;
15538 /* No VLAN anti-spoofing checks are enabled */
15539 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
15541 /* Validate VLAN against the configured VLAN(s) */
15542 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
15544 /* Insert VLAN if it does not exist, otherwise discard */
15545 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
15547 /* Insert VLAN if it does not exist, override VLAN if it exists */
15548 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
15550 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
15551 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
15553 * This bit field defines VLAN PRIs that are allowed on
15555 * If nth bit is set, then VLAN PRI n is allowed on this
15558 uint8_t allowed_vlan_pris;
15560 * The evb_mode is configured on a per port basis. The default evb_mode
15561 * is configured based on the NVM EVB mode setting upon firmware
15562 * initialization. The HWRM allows a PF driver to change EVB mode for a
15563 * port used by the PF only when one of the following conditions is
15565 * 1. The current operating mode is single function mode.
15566 * (ie. one PF per port)
15567 * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
15568 * EVB mode of the port used by the PAXC PF. None of the X86 PFs
15569 * should have privileges.
15570 * The HWRM doesn't permit any PFs to change the underlying EVB mode
15571 * when running as MHB or NPAR mode in performance NIC configuration.
15572 * The HWRM doesn't permit a VF driver to change the EVB mode.
15573 * Once the HWRM determines a function doesn't meet the conditions
15574 * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
15575 * flag in HWRM_FUNC_QCAPS command response for the function.
15576 * The HWRM takes into account the switching of EVB mode from one to
15577 * another and reconfigure hardware resources as reqiured. The
15578 * switching from VEB to VEPA mode requires the disabling of the
15579 * loopback traffic. Additionally, source knockouts are handled
15580 * differently in VEB and VEPA modes.
15583 /* No Edge Virtual Bridging (EVB) */
15584 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
15585 /* Virtual Ethernet Bridge (VEB) */
15586 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
15587 /* Virtual Ethernet Port Aggregator (VEPA) */
15588 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
15589 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
15590 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
15593 * This value indicates the PCIE device cache line size.
15594 * The cache line size allows the DMA writes to terminate and
15595 * start at the cache boundary.
15597 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
15599 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
15600 /* Cache Line Size 64 bytes */
15601 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
15603 /* Cache Line Size 128 bytes */
15604 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
15606 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
15607 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
15608 /* This value is the virtual link admin state setting. */
15609 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
15611 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
15612 /* Admin state is forced down. */
15613 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
15614 (UINT32_C(0x0) << 2)
15615 /* Admin state is forced up. */
15616 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
15617 (UINT32_C(0x1) << 2)
15618 /* Admin state is in auto mode - is to follow the physical link state. */
15619 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
15620 (UINT32_C(0x2) << 2)
15621 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
15622 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
15623 /* Reserved for future. */
15624 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
15626 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
15628 * The number of multicast filters that should
15629 * be reserved for this function on the RX side.
15631 uint16_t num_mcast_filters;
15632 /* Used by a PF driver to associate a SCHQ with a VF. */
15634 uint16_t mpc_chnls;
15636 * When this bit is '1', the caller requests to enable a MPC
15637 * channel with destination to the TX crypto engine block.
15638 * When this bit is ‘0’, this flag has no effect.
15640 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
15642 * When this bit is '1', the caller requests to disable a MPC
15643 * channel with destination to the TX crypto engine block.
15644 * When this bit is ‘0’, this flag has no effect.
15646 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
15648 * When this bit is '1', the caller requests to enable a MPC
15649 * channel with destination to the RX crypto engine block.
15650 * When this bit is ‘0’, this flag has no effect.
15652 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
15654 * When this bit is '1', the caller requests to disable a MPC
15655 * channel with destination to the RX crypto engine block.
15656 * When this bit is ‘0’, this flag has no effect.
15658 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
15660 * When this bit is '1', the caller requests to enable a MPC
15661 * channel with destination to the TX configurable flow processing
15662 * block. When this bit is ‘0’, this flag has no effect.
15664 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
15667 * When this bit is '1', the caller requests to disable a MPC
15668 * channel with destination to the TX configurable flow processing
15669 * block. When this bit is ‘0’, this flag has no effect.
15671 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
15674 * When this bit is '1', the caller requests to enable a MPC
15675 * channel with destination to the RX configurable flow processing
15676 * block. When this bit is ‘0’, this flag has no effect.
15678 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
15681 * When this bit is '1', the caller requests to disable a MPC
15682 * channel with destination to the RX configurable flow processing
15683 * block. When this bit is ‘0’, this flag has no effect.
15685 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
15688 * When this bit is '1', the caller requests to enable a MPC
15689 * channel with destination to the primate processor block.
15690 * When this bit is ‘0’, this flag has no effect.
15692 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
15695 * When this bit is '1', the caller requests to disable a MPC
15696 * channel with destination to the primate processor block.
15697 * When this bit is ‘0’, this flag has no effect.
15699 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
15702 * Minimum guaranteed bandwidth for the network partition made up
15703 * of the caller physical function and all its child virtual
15704 * functions. The rate is specified as a percentage of the bandwidth
15705 * of the link the partition is associated with. A value of 0
15706 * indicates that no minimum bandwidth is configured. The sum of the
15707 * minimum bandwidths for all partitions on a link must not exceed
15709 * The format of this field is defined to match min_bw, even though
15710 * it does not allow all the options for min_bw at this time.
15712 uint32_t partition_min_bw;
15713 /* The bandwidth value. */
15714 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
15715 UINT32_C(0xfffffff)
15716 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
15719 * The granularity of the value (bits or bytes). Firmware ignores
15722 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \
15723 UINT32_C(0x10000000)
15724 /* Value is in bits. */
15725 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \
15726 (UINT32_C(0x0) << 28)
15727 /* Value is in bytes. */
15728 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \
15729 (UINT32_C(0x1) << 28)
15730 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \
15731 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES
15732 /* Bandwidth units. Must be set to percent1_100. */
15733 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
15734 UINT32_C(0xe0000000)
15735 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
15737 /* Value is in hundredths of a percent of link bandwidth. */
15738 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15739 (UINT32_C(0x1) << 29)
15740 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
15741 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
15743 * The maximum bandwidth that may be used by the network partition
15744 * made up of the caller physical function and all its child virtual
15745 * functions. The rate is specified as a percentage of the bandwidth
15746 * of the link the partition is associated with. A value of 0
15747 * indicates that no maximum bandwidth is configured.
15748 * The format of this field is defined to match max_bw, even though it
15749 * does not allow all the options for max_bw at this time.
15751 uint32_t partition_max_bw;
15752 /* The bandwidth value. */
15753 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
15754 UINT32_C(0xfffffff)
15755 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
15758 * The granularity of the value (bits or bytes). Firmware ignores
15761 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \
15762 UINT32_C(0x10000000)
15763 /* Value is in bits. */
15764 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \
15765 (UINT32_C(0x0) << 28)
15766 /* Value is in bytes. */
15767 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \
15768 (UINT32_C(0x1) << 28)
15769 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \
15770 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES
15771 /* Bandwidth units. Must be set to percent1_100. */
15772 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
15773 UINT32_C(0xe0000000)
15774 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
15776 /* Value is in hundredths of a percent of link bandwidth. */
15777 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15778 (UINT32_C(0x1) << 29)
15779 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
15780 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
15782 * The TPID for the function for which default VLAN
15783 * is configured. If the dflt_vlan is not specified
15784 * with the TPID, FW returns error. If the TPID is
15785 * not specified with dflt_vlan, the default TPID of
15786 * 0x8100 will be used. This field is specified in
15787 * network byte order.
15791 * This field can be used by the host PF to configure
15793 * The maximum transmission unit of the function.
15794 * The HWRM should make sure that the mtu of
15795 * the function does not exceed the mtu of the physical
15796 * port that this function is associated with.
15798 * In addition to configuring mtu per function, it is
15799 * possible to configure mtu per transmit ring.
15800 * By default, the mtu of each transmit ring associated
15801 * with a function is equal to the mtu of the function.
15802 * The HWRM should make sure that the mtu of each transmit
15803 * ring that is assigned to a function has a valid mtu.
15806 /* Number of Tx Key Contexts requested. */
15807 uint16_t num_tx_key_ctxs;
15808 /* Number of Rx Key Contexts requested. */
15809 uint16_t num_rx_key_ctxs;
15810 uint8_t unused_0[4];
15813 /* hwrm_func_cfg_output (size:128b/16B) */
15814 struct hwrm_func_cfg_output {
15815 /* The specific error status for the command. */
15816 uint16_t error_code;
15817 /* The HWRM command request type. */
15819 /* The sequence ID from the original command. */
15821 /* The length of the response data in number of bytes. */
15823 uint8_t unused_0[7];
15825 * This field is used in Output records to indicate that the output
15826 * is completely written to RAM. This field should be read as '1'
15827 * to indicate that the output has been completely written.
15828 * When writing a command completion or response to an internal processor,
15829 * the order of writes has to be such that this field is written last.
15834 /* hwrm_func_cfg_cmd_err (size:64b/8B) */
15835 struct hwrm_func_cfg_cmd_err {
15836 /* command specific error codes for the cmd_err field in hwrm_err_output */
15838 /* Unknown error. */
15839 #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \
15841 /* The partition minimum bandwidth is out of range. */
15842 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \
15844 /* The minimum bandwidth is more than the maximum bandwidth. */
15845 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \
15848 * The NIC does not support enforcement of a minimum guaranteed
15849 * bandwidth for a partition.
15851 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \
15853 /* Partition bandwidths must be specified as a percentage. */
15854 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \
15856 #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \
15857 HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
15858 uint8_t unused_0[7];
15861 /********************
15862 * hwrm_func_qstats *
15863 ********************/
15866 /* hwrm_func_qstats_input (size:192b/24B) */
15867 struct hwrm_func_qstats_input {
15868 /* The HWRM command request type. */
15871 * The completion ring to send the completion event on. This should
15872 * be the NQ ID returned from the `nq_alloc` HWRM command.
15874 uint16_t cmpl_ring;
15876 * The sequence ID is used by the driver for tracking multiple
15877 * commands. This ID is treated as opaque data by the firmware and
15878 * the value is returned in the `hwrm_resp_hdr` upon completion.
15882 * The target ID of the command:
15883 * * 0x0-0xFFF8 - The function ID
15884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15885 * * 0xFFFD - Reserved for user-space HWRM interface
15888 uint16_t target_id;
15890 * A physical address pointer pointing to a host buffer that the
15891 * command's response data will be written. This can be either a host
15892 * physical address (HPA) or a guest physical address (GPA) and must
15893 * point to a physically contiguous block of memory.
15895 uint64_t resp_addr;
15897 * Function ID of the function that is being queried.
15898 * 0xFF... (All Fs) if the query is for the requesting
15900 * A privileged PF can query for other function's statistics.
15903 /* This flags indicates the type of statistics request. */
15905 /* This value is not used to avoid backward compatibility issues. */
15906 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
15908 * flags should be set to 1 when request is for only RoCE statistics.
15909 * This will be honored only if the caller_fid is a privileged PF.
15910 * In all other cases FID and caller_fid should be the same.
15912 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
15914 * flags should be set to 2 when request is for the counter mask,
15915 * representing the width of each of the stats counters, rather
15916 * than counters themselves.
15918 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
15919 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
15920 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
15921 uint8_t unused_0[5];
15924 /* hwrm_func_qstats_output (size:1408b/176B) */
15925 struct hwrm_func_qstats_output {
15926 /* The specific error status for the command. */
15927 uint16_t error_code;
15928 /* The HWRM command request type. */
15930 /* The sequence ID from the original command. */
15932 /* The length of the response data in number of bytes. */
15934 /* Number of transmitted unicast packets on the function. */
15935 uint64_t tx_ucast_pkts;
15936 /* Number of transmitted multicast packets on the function. */
15937 uint64_t tx_mcast_pkts;
15938 /* Number of transmitted broadcast packets on the function. */
15939 uint64_t tx_bcast_pkts;
15941 * Number of transmitted packets that were discarded due to
15942 * internal NIC resource problems. For transmit, this
15943 * can only happen if TMP is configured to allow dropping
15944 * in HOL blocking conditions, which is not a normal
15947 uint64_t tx_discard_pkts;
15949 * Number of dropped packets on transmit path on the function.
15950 * These are packets that have been marked for drop by
15951 * the TE CFA block or are packets that exceeded the
15952 * transmit MTU limit for the function.
15954 uint64_t tx_drop_pkts;
15955 /* Number of transmitted bytes for unicast traffic on the function. */
15956 uint64_t tx_ucast_bytes;
15957 /* Number of transmitted bytes for multicast traffic on the function. */
15958 uint64_t tx_mcast_bytes;
15959 /* Number of transmitted bytes for broadcast traffic on the function. */
15960 uint64_t tx_bcast_bytes;
15961 /* Number of received unicast packets on the function. */
15962 uint64_t rx_ucast_pkts;
15963 /* Number of received multicast packets on the function. */
15964 uint64_t rx_mcast_pkts;
15965 /* Number of received broadcast packets on the function. */
15966 uint64_t rx_bcast_pkts;
15968 * Number of received packets that were discarded on the function
15969 * due to resource limitations. This can happen for 3 reasons.
15970 * # The BD used for the packet has a bad format.
15971 * # There were no BDs available in the ring for the packet.
15972 * # There were no BDs available on-chip for the packet.
15974 uint64_t rx_discard_pkts;
15976 * Number of dropped packets on received path on the function.
15977 * These are packets that have been marked for drop by the
15980 uint64_t rx_drop_pkts;
15981 /* Number of received bytes for unicast traffic on the function. */
15982 uint64_t rx_ucast_bytes;
15983 /* Number of received bytes for multicast traffic on the function. */
15984 uint64_t rx_mcast_bytes;
15985 /* Number of received bytes for broadcast traffic on the function. */
15986 uint64_t rx_bcast_bytes;
15987 /* Number of aggregated unicast packets on the function. */
15988 uint64_t rx_agg_pkts;
15989 /* Number of aggregated unicast bytes on the function. */
15990 uint64_t rx_agg_bytes;
15991 /* Number of aggregation events on the function. */
15992 uint64_t rx_agg_events;
15993 /* Number of aborted aggregations on the function. */
15994 uint64_t rx_agg_aborts;
15995 uint8_t unused_0[7];
15997 * This field is used in Output records to indicate that the output
15998 * is completely written to RAM. This field should be read as '1'
15999 * to indicate that the output has been completely written.
16000 * When writing a command completion or response to an internal processor,
16001 * the order of writes has to be such that this field is written last.
16006 /************************
16007 * hwrm_func_qstats_ext *
16008 ************************/
16011 /* hwrm_func_qstats_ext_input (size:256b/32B) */
16012 struct hwrm_func_qstats_ext_input {
16013 /* The HWRM command request type. */
16016 * The completion ring to send the completion event on. This should
16017 * be the NQ ID returned from the `nq_alloc` HWRM command.
16019 uint16_t cmpl_ring;
16021 * The sequence ID is used by the driver for tracking multiple
16022 * commands. This ID is treated as opaque data by the firmware and
16023 * the value is returned in the `hwrm_resp_hdr` upon completion.
16027 * The target ID of the command:
16028 * * 0x0-0xFFF8 - The function ID
16029 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16030 * * 0xFFFD - Reserved for user-space HWRM interface
16033 uint16_t target_id;
16035 * A physical address pointer pointing to a host buffer that the
16036 * command's response data will be written. This can be either a host
16037 * physical address (HPA) or a guest physical address (GPA) and must
16038 * point to a physically contiguous block of memory.
16040 uint64_t resp_addr;
16042 * Function ID of the function that is being queried.
16043 * 0xFF... (All Fs) if the query is for the requesting
16045 * A privileged PF can query for other function's statistics.
16048 /* This flags indicates the type of statistics request. */
16050 /* This value is not used to avoid backward compatibility issues. */
16051 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
16053 * flags should be set to 1 when request is for only RoCE statistics.
16054 * This will be honored only if the caller_fid is a privileged PF.
16055 * In all other cases FID and caller_fid should be the same.
16057 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
16059 * flags should be set to 2 when request is for the counter mask
16060 * representing the width of each of the stats counters, rather
16061 * than counters themselves.
16063 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
16064 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
16065 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
16066 uint8_t unused_0[1];
16069 * This bit must be '1' for the schq_id and traffic_class fields to
16072 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
16073 /* Specifies the SCHQ for which to gather statistics */
16076 * Specifies the traffic class for which to gather statistics. Valid
16077 * values are 0 through (max_configurable_queues - 1), where
16078 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
16080 uint16_t traffic_class;
16081 uint8_t unused_1[4];
16084 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
16085 struct hwrm_func_qstats_ext_output {
16086 /* The specific error status for the command. */
16087 uint16_t error_code;
16088 /* The HWRM command request type. */
16090 /* The sequence ID from the original command. */
16092 /* The length of the response data in number of bytes. */
16094 /* Number of received unicast packets */
16095 uint64_t rx_ucast_pkts;
16096 /* Number of received multicast packets */
16097 uint64_t rx_mcast_pkts;
16098 /* Number of received broadcast packets */
16099 uint64_t rx_bcast_pkts;
16100 /* Number of discarded packets on received path */
16101 uint64_t rx_discard_pkts;
16102 /* Number of packets on receive path with error */
16103 uint64_t rx_error_pkts;
16104 /* Number of received bytes for unicast traffic */
16105 uint64_t rx_ucast_bytes;
16106 /* Number of received bytes for multicast traffic */
16107 uint64_t rx_mcast_bytes;
16108 /* Number of received bytes for broadcast traffic */
16109 uint64_t rx_bcast_bytes;
16110 /* Number of transmitted unicast packets */
16111 uint64_t tx_ucast_pkts;
16112 /* Number of transmitted multicast packets */
16113 uint64_t tx_mcast_pkts;
16114 /* Number of transmitted broadcast packets */
16115 uint64_t tx_bcast_pkts;
16116 /* Number of packets on transmit path with error */
16117 uint64_t tx_error_pkts;
16118 /* Number of discarded packets on transmit path */
16119 uint64_t tx_discard_pkts;
16120 /* Number of transmitted bytes for unicast traffic */
16121 uint64_t tx_ucast_bytes;
16122 /* Number of transmitted bytes for multicast traffic */
16123 uint64_t tx_mcast_bytes;
16124 /* Number of transmitted bytes for broadcast traffic */
16125 uint64_t tx_bcast_bytes;
16126 /* Number of TPA eligible packets */
16127 uint64_t rx_tpa_eligible_pkt;
16128 /* Number of TPA eligible bytes */
16129 uint64_t rx_tpa_eligible_bytes;
16130 /* Number of TPA packets */
16131 uint64_t rx_tpa_pkt;
16132 /* Number of TPA bytes */
16133 uint64_t rx_tpa_bytes;
16134 /* Number of TPA errors */
16135 uint64_t rx_tpa_errors;
16136 /* Number of TPA errors */
16137 uint64_t rx_tpa_events;
16138 uint8_t unused_0[7];
16140 * This field is used in Output records to indicate that the output
16141 * is completely written to RAM. This field should be read as '1'
16142 * to indicate that the output has been completely written.
16143 * When writing a command completion or response to an internal processor,
16144 * the order of writes has to be such that this field is written last.
16149 /***********************
16150 * hwrm_func_clr_stats *
16151 ***********************/
16154 /* hwrm_func_clr_stats_input (size:192b/24B) */
16155 struct hwrm_func_clr_stats_input {
16156 /* The HWRM command request type. */
16159 * The completion ring to send the completion event on. This should
16160 * be the NQ ID returned from the `nq_alloc` HWRM command.
16162 uint16_t cmpl_ring;
16164 * The sequence ID is used by the driver for tracking multiple
16165 * commands. This ID is treated as opaque data by the firmware and
16166 * the value is returned in the `hwrm_resp_hdr` upon completion.
16170 * The target ID of the command:
16171 * * 0x0-0xFFF8 - The function ID
16172 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16173 * * 0xFFFD - Reserved for user-space HWRM interface
16176 uint16_t target_id;
16178 * A physical address pointer pointing to a host buffer that the
16179 * command's response data will be written. This can be either a host
16180 * physical address (HPA) or a guest physical address (GPA) and must
16181 * point to a physically contiguous block of memory.
16183 uint64_t resp_addr;
16185 * Function ID of the function.
16186 * 0xFF... (All Fs) if the query is for the requesting
16190 uint8_t unused_0[6];
16193 /* hwrm_func_clr_stats_output (size:128b/16B) */
16194 struct hwrm_func_clr_stats_output {
16195 /* The specific error status for the command. */
16196 uint16_t error_code;
16197 /* The HWRM command request type. */
16199 /* The sequence ID from the original command. */
16201 /* The length of the response data in number of bytes. */
16203 uint8_t unused_0[7];
16205 * This field is used in Output records to indicate that the output
16206 * is completely written to RAM. This field should be read as '1'
16207 * to indicate that the output has been completely written.
16208 * When writing a command completion or response to an internal processor,
16209 * the order of writes has to be such that this field is written last.
16214 /**************************
16215 * hwrm_func_vf_resc_free *
16216 **************************/
16219 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
16220 struct hwrm_func_vf_resc_free_input {
16221 /* The HWRM command request type. */
16224 * The completion ring to send the completion event on. This should
16225 * be the NQ ID returned from the `nq_alloc` HWRM command.
16227 uint16_t cmpl_ring;
16229 * The sequence ID is used by the driver for tracking multiple
16230 * commands. This ID is treated as opaque data by the firmware and
16231 * the value is returned in the `hwrm_resp_hdr` upon completion.
16235 * The target ID of the command:
16236 * * 0x0-0xFFF8 - The function ID
16237 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16238 * * 0xFFFD - Reserved for user-space HWRM interface
16241 uint16_t target_id;
16243 * A physical address pointer pointing to a host buffer that the
16244 * command's response data will be written. This can be either a host
16245 * physical address (HPA) or a guest physical address (GPA) and must
16246 * point to a physically contiguous block of memory.
16248 uint64_t resp_addr;
16250 * This value is used to identify a Virtual Function (VF).
16251 * The scope of VF ID is local within a PF.
16254 uint8_t unused_0[6];
16257 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
16258 struct hwrm_func_vf_resc_free_output {
16259 /* The specific error status for the command. */
16260 uint16_t error_code;
16261 /* The HWRM command request type. */
16263 /* The sequence ID from the original command. */
16265 /* The length of the response data in number of bytes. */
16267 uint8_t unused_0[7];
16269 * This field is used in Output records to indicate that the output
16270 * is completely written to RAM. This field should be read as '1'
16271 * to indicate that the output has been completely written.
16272 * When writing a command completion or response to an internal processor,
16273 * the order of writes has to be such that this field is written last.
16278 /**********************
16279 * hwrm_func_drv_rgtr *
16280 **********************/
16283 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
16284 struct hwrm_func_drv_rgtr_input {
16285 /* The HWRM command request type. */
16288 * The completion ring to send the completion event on. This should
16289 * be the NQ ID returned from the `nq_alloc` HWRM command.
16291 uint16_t cmpl_ring;
16293 * The sequence ID is used by the driver for tracking multiple
16294 * commands. This ID is treated as opaque data by the firmware and
16295 * the value is returned in the `hwrm_resp_hdr` upon completion.
16299 * The target ID of the command:
16300 * * 0x0-0xFFF8 - The function ID
16301 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16302 * * 0xFFFD - Reserved for user-space HWRM interface
16305 uint16_t target_id;
16307 * A physical address pointer pointing to a host buffer that the
16308 * command's response data will be written. This can be either a host
16309 * physical address (HPA) or a guest physical address (GPA) and must
16310 * point to a physically contiguous block of memory.
16312 uint64_t resp_addr;
16315 * When this bit is '1', the function driver is requesting
16316 * all requests from its children VF drivers to be
16317 * forwarded to itself.
16318 * This flag can only be set by the PF driver.
16319 * If a VF driver sets this flag, it should be ignored
16322 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
16325 * When this bit is '1', the function is requesting none of
16326 * the requests from its children VF drivers to be
16327 * forwarded to itself.
16328 * This flag can only be set by the PF driver.
16329 * If a VF driver sets this flag, it should be ignored
16332 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
16335 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
16336 * fields shall be ignored and ver_maj, ver_min, ver_upd
16337 * and ver_patch shall be used for the driver version information.
16338 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
16339 * fields shall be used for the driver version information and
16340 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
16342 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
16345 * When this bit is '1', the function is indicating support of
16346 * 64bit flow handle. The firmware that only supports 64bit flow
16347 * handle should check this bit before allowing processing of
16348 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
16349 * with 64bit flow handle support can only be compatible with drivers
16350 * that support 64bit flow handle. The legacy drivers that don't support
16351 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
16352 * running with new firmware that only supports 64bit flow handle. The new
16353 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
16354 * status to the legacy driver when encounters these commands.
16356 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
16359 * When this bit is '1', the function is indicating support of
16360 * Hot Reset. The driver interface will destroy the resources,
16361 * unregister the function and register again up on receiving
16362 * the RESET_NOTIFY Async notification from the core firmware.
16363 * The core firmware will this use flag and trigger the Hot Reset
16364 * process only if all the registered driver instances are capable
16367 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
16370 * When this bit is 1, the function is indicating the support of the
16371 * error recovery capability. Error recovery support will be used by
16372 * firmware only if all the driver instances support error recovery
16373 * process. By setting this bit, driver is indicating support for
16374 * corresponding async event completion message. These will be
16375 * delivered to the driver even if they did not register for it.
16376 * If supported, after receiving reset notify async event with fatal
16377 * flag set in event data1, then all the drivers have to tear down
16378 * their resources without sending any HWRM commands to FW.
16380 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
16383 * When this bit is 1, the function is indicating the support of the
16384 * Master capability. The Firmware will use this capability to select the
16385 * Master function. The master function will be used to initiate
16386 * designated functionality like error recovery etc… If none of the
16387 * registered PF’s or trusted VF’s indicate this support, then
16388 * firmware will select the 1st registered PF as Master capable instance.
16390 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
16393 * When this bit is 1, the function is indicating the support of the
16394 * fast reset capability. Fast reset support will be used by
16395 * firmware only if all the driver instances support fast reset
16396 * process. By setting this bit, driver is indicating support for
16397 * corresponding async event completion message. These will be
16398 * delivered to the driver even if they did not register for it.
16399 * If supported, after receiving reset notify async event with fast
16400 * reset flag set in event data1, then all the drivers have to tear
16401 * down their resources without sending any HWRM commands to FW.
16403 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
16406 * When this bit is 1, the function's driver is indicating the
16407 * support of handling the vnic_rss_cfg's INVALID_PARAM error
16408 * returned by firmware. Firmware returns error, if host driver
16409 * configures the invalid hash_types bit combination for a given
16412 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \
16415 * When this bit is 1, the function's driver is indicating the
16416 * support of handling the NPAR 1.2 feature where the s-tag may be
16417 * a value other than 0x8100 or 0x88a8.
16419 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
16423 * This bit must be '1' for the os_type field to be
16426 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
16429 * This bit must be '1' for the ver field to be
16432 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
16435 * This bit must be '1' for the timestamp field to be
16438 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
16441 * This bit must be '1' for the vf_req_fwd field to be
16444 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
16447 * This bit must be '1' for the async_event_fwd field to be
16450 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
16452 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
16455 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
16456 /* Other OS not listed below. */
16457 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
16459 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
16461 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
16463 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
16465 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
16467 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
16468 /* VMware ESXi OS. */
16469 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
16470 /* Microsoft Windows 8 64-bit OS. */
16471 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
16472 /* Microsoft Windows Server 2012 R2 OS. */
16473 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
16475 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
16476 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
16477 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
16478 /* This is the 8bit major version of the driver. */
16479 uint8_t ver_maj_8b;
16480 /* This is the 8bit minor version of the driver. */
16481 uint8_t ver_min_8b;
16482 /* This is the 8bit update version of the driver. */
16483 uint8_t ver_upd_8b;
16484 uint8_t unused_0[3];
16486 * This is a 32-bit timestamp provided by the driver for
16488 * The timestamp is in multiples of 1ms.
16490 uint32_t timestamp;
16491 uint8_t unused_1[4];
16493 * This is a 256-bit bit mask provided by the PF driver for
16494 * letting the HWRM know what commands issued by the VF driver
16495 * to the HWRM should be forwarded to the PF driver.
16496 * Nth bit refers to the Nth req_type.
16498 * Setting Nth bit to 1 indicates that requests from the
16499 * VF driver with req_type equal to N shall be forwarded to
16500 * the parent PF driver.
16502 * This field is not valid for the VF driver.
16504 uint32_t vf_req_fwd[8];
16506 * This is a 256-bit bit mask provided by the function driver
16507 * (PF or VF driver) to indicate the list of asynchronous event
16508 * completions to be forwarded.
16510 * Nth bit refers to the Nth event_id.
16512 * Setting Nth bit to 1 by the function driver shall result in
16513 * the HWRM forwarding asynchronous event completion with
16514 * event_id equal to N.
16516 * If all bits are set to 0 (value of 0), then the HWRM shall
16517 * not forward any asynchronous event completion to this
16520 uint32_t async_event_fwd[8];
16521 /* This is the 16bit major version of the driver. */
16523 /* This is the 16bit minor version of the driver. */
16525 /* This is the 16bit update version of the driver. */
16527 /* This is the 16bit patch version of the driver. */
16528 uint16_t ver_patch;
16531 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
16532 struct hwrm_func_drv_rgtr_output {
16533 /* The specific error status for the command. */
16534 uint16_t error_code;
16535 /* The HWRM command request type. */
16537 /* The sequence ID from the original command. */
16539 /* The length of the response data in number of bytes. */
16543 * When this bit is '1', it indicates that the
16544 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
16546 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
16548 uint8_t unused_0[3];
16550 * This field is used in Output records to indicate that the output
16551 * is completely written to RAM. This field should be read as '1'
16552 * to indicate that the output has been completely written.
16553 * When writing a command completion or response to an internal processor,
16554 * the order of writes has to be such that this field is written last.
16559 /************************
16560 * hwrm_func_drv_unrgtr *
16561 ************************/
16564 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
16565 struct hwrm_func_drv_unrgtr_input {
16566 /* The HWRM command request type. */
16569 * The completion ring to send the completion event on. This should
16570 * be the NQ ID returned from the `nq_alloc` HWRM command.
16572 uint16_t cmpl_ring;
16574 * The sequence ID is used by the driver for tracking multiple
16575 * commands. This ID is treated as opaque data by the firmware and
16576 * the value is returned in the `hwrm_resp_hdr` upon completion.
16580 * The target ID of the command:
16581 * * 0x0-0xFFF8 - The function ID
16582 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16583 * * 0xFFFD - Reserved for user-space HWRM interface
16586 uint16_t target_id;
16588 * A physical address pointer pointing to a host buffer that the
16589 * command's response data will be written. This can be either a host
16590 * physical address (HPA) or a guest physical address (GPA) and must
16591 * point to a physically contiguous block of memory.
16593 uint64_t resp_addr;
16596 * When this bit is '1', the function driver is notifying
16597 * the HWRM to prepare for the shutdown.
16599 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
16601 uint8_t unused_0[4];
16604 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
16605 struct hwrm_func_drv_unrgtr_output {
16606 /* The specific error status for the command. */
16607 uint16_t error_code;
16608 /* The HWRM command request type. */
16610 /* The sequence ID from the original command. */
16612 /* The length of the response data in number of bytes. */
16614 uint8_t unused_0[7];
16616 * This field is used in Output records to indicate that the output
16617 * is completely written to RAM. This field should be read as '1'
16618 * to indicate that the output has been completely written.
16619 * When writing a command completion or response to an internal processor,
16620 * the order of writes has to be such that this field is written last.
16625 /**********************
16626 * hwrm_func_buf_rgtr *
16627 **********************/
16630 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
16631 struct hwrm_func_buf_rgtr_input {
16632 /* The HWRM command request type. */
16635 * The completion ring to send the completion event on. This should
16636 * be the NQ ID returned from the `nq_alloc` HWRM command.
16638 uint16_t cmpl_ring;
16640 * The sequence ID is used by the driver for tracking multiple
16641 * commands. This ID is treated as opaque data by the firmware and
16642 * the value is returned in the `hwrm_resp_hdr` upon completion.
16646 * The target ID of the command:
16647 * * 0x0-0xFFF8 - The function ID
16648 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16649 * * 0xFFFD - Reserved for user-space HWRM interface
16652 uint16_t target_id;
16654 * A physical address pointer pointing to a host buffer that the
16655 * command's response data will be written. This can be either a host
16656 * physical address (HPA) or a guest physical address (GPA) and must
16657 * point to a physically contiguous block of memory.
16659 uint64_t resp_addr;
16662 * This bit must be '1' for the vf_id field to be
16665 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
16667 * This bit must be '1' for the err_buf_addr field to be
16670 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
16672 * This value is used to identify a Virtual Function (VF).
16673 * The scope of VF ID is local within a PF.
16677 * This field represents the number of pages used for request
16680 uint16_t req_buf_num_pages;
16682 * This field represents the page size used for request
16685 uint16_t req_buf_page_size;
16687 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
16689 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
16691 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
16693 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
16695 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
16697 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
16699 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
16700 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
16701 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
16702 /* The length of the request buffer per VF in bytes. */
16703 uint16_t req_buf_len;
16704 /* The length of the response buffer in bytes. */
16705 uint16_t resp_buf_len;
16706 uint8_t unused_0[2];
16707 /* This field represents the page address of page #0. */
16708 uint64_t req_buf_page_addr0;
16709 /* This field represents the page address of page #1. */
16710 uint64_t req_buf_page_addr1;
16711 /* This field represents the page address of page #2. */
16712 uint64_t req_buf_page_addr2;
16713 /* This field represents the page address of page #3. */
16714 uint64_t req_buf_page_addr3;
16715 /* This field represents the page address of page #4. */
16716 uint64_t req_buf_page_addr4;
16717 /* This field represents the page address of page #5. */
16718 uint64_t req_buf_page_addr5;
16719 /* This field represents the page address of page #6. */
16720 uint64_t req_buf_page_addr6;
16721 /* This field represents the page address of page #7. */
16722 uint64_t req_buf_page_addr7;
16723 /* This field represents the page address of page #8. */
16724 uint64_t req_buf_page_addr8;
16725 /* This field represents the page address of page #9. */
16726 uint64_t req_buf_page_addr9;
16728 * This field is used to receive the error reporting from
16729 * the chipset. Only applicable for PFs.
16731 uint64_t error_buf_addr;
16733 * This field is used to receive the response forwarded by the
16736 uint64_t resp_buf_addr;
16739 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
16740 struct hwrm_func_buf_rgtr_output {
16741 /* The specific error status for the command. */
16742 uint16_t error_code;
16743 /* The HWRM command request type. */
16745 /* The sequence ID from the original command. */
16747 /* The length of the response data in number of bytes. */
16749 uint8_t unused_0[7];
16751 * This field is used in Output records to indicate that the output
16752 * is completely written to RAM. This field should be read as '1'
16753 * to indicate that the output has been completely written.
16754 * When writing a command completion or response to an internal processor,
16755 * the order of writes has to be such that this field is written last.
16760 /************************
16761 * hwrm_func_buf_unrgtr *
16762 ************************/
16765 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
16766 struct hwrm_func_buf_unrgtr_input {
16767 /* The HWRM command request type. */
16770 * The completion ring to send the completion event on. This should
16771 * be the NQ ID returned from the `nq_alloc` HWRM command.
16773 uint16_t cmpl_ring;
16775 * The sequence ID is used by the driver for tracking multiple
16776 * commands. This ID is treated as opaque data by the firmware and
16777 * the value is returned in the `hwrm_resp_hdr` upon completion.
16781 * The target ID of the command:
16782 * * 0x0-0xFFF8 - The function ID
16783 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16784 * * 0xFFFD - Reserved for user-space HWRM interface
16787 uint16_t target_id;
16789 * A physical address pointer pointing to a host buffer that the
16790 * command's response data will be written. This can be either a host
16791 * physical address (HPA) or a guest physical address (GPA) and must
16792 * point to a physically contiguous block of memory.
16794 uint64_t resp_addr;
16797 * This bit must be '1' for the vf_id field to be
16800 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
16802 * This value is used to identify a Virtual Function (VF).
16803 * The scope of VF ID is local within a PF.
16806 uint8_t unused_0[2];
16809 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
16810 struct hwrm_func_buf_unrgtr_output {
16811 /* The specific error status for the command. */
16812 uint16_t error_code;
16813 /* The HWRM command request type. */
16815 /* The sequence ID from the original command. */
16817 /* The length of the response data in number of bytes. */
16819 uint8_t unused_0[7];
16821 * This field is used in Output records to indicate that the output
16822 * is completely written to RAM. This field should be read as '1'
16823 * to indicate that the output has been completely written.
16824 * When writing a command completion or response to an internal processor,
16825 * the order of writes has to be such that this field is written last.
16830 /**********************
16831 * hwrm_func_drv_qver *
16832 **********************/
16835 /* hwrm_func_drv_qver_input (size:192b/24B) */
16836 struct hwrm_func_drv_qver_input {
16837 /* The HWRM command request type. */
16840 * The completion ring to send the completion event on. This should
16841 * be the NQ ID returned from the `nq_alloc` HWRM command.
16843 uint16_t cmpl_ring;
16845 * The sequence ID is used by the driver for tracking multiple
16846 * commands. This ID is treated as opaque data by the firmware and
16847 * the value is returned in the `hwrm_resp_hdr` upon completion.
16851 * The target ID of the command:
16852 * * 0x0-0xFFF8 - The function ID
16853 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16854 * * 0xFFFD - Reserved for user-space HWRM interface
16857 uint16_t target_id;
16859 * A physical address pointer pointing to a host buffer that the
16860 * command's response data will be written. This can be either a host
16861 * physical address (HPA) or a guest physical address (GPA) and must
16862 * point to a physically contiguous block of memory.
16864 uint64_t resp_addr;
16865 /* Reserved for future use. */
16868 * Function ID of the function that is being queried.
16869 * 0xFF... (All Fs) if the query is for the requesting
16873 uint8_t unused_0[2];
16876 /* hwrm_func_drv_qver_output (size:256b/32B) */
16877 struct hwrm_func_drv_qver_output {
16878 /* The specific error status for the command. */
16879 uint16_t error_code;
16880 /* The HWRM command request type. */
16882 /* The sequence ID from the original command. */
16884 /* The length of the response data in number of bytes. */
16886 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
16889 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
16890 /* Other OS not listed below. */
16891 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
16893 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
16895 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
16897 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
16899 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
16901 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
16902 /* VMware ESXi OS. */
16903 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
16904 /* Microsoft Windows 8 64-bit OS. */
16905 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
16906 /* Microsoft Windows Server 2012 R2 OS. */
16907 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
16909 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
16910 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
16911 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
16912 /* This is the 8bit major version of the driver. */
16913 uint8_t ver_maj_8b;
16914 /* This is the 8bit minor version of the driver. */
16915 uint8_t ver_min_8b;
16916 /* This is the 8bit update version of the driver. */
16917 uint8_t ver_upd_8b;
16918 uint8_t unused_0[3];
16919 /* This is the 16bit major version of the driver. */
16921 /* This is the 16bit minor version of the driver. */
16923 /* This is the 16bit update version of the driver. */
16925 /* This is the 16bit patch version of the driver. */
16926 uint16_t ver_patch;
16927 uint8_t unused_1[7];
16929 * This field is used in Output records to indicate that the output
16930 * is completely written to RAM. This field should be read as '1'
16931 * to indicate that the output has been completely written.
16932 * When writing a command completion or response to an internal processor,
16933 * the order of writes has to be such that this field is written last.
16938 /****************************
16939 * hwrm_func_resource_qcaps *
16940 ****************************/
16943 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
16944 struct hwrm_func_resource_qcaps_input {
16945 /* The HWRM command request type. */
16948 * The completion ring to send the completion event on. This should
16949 * be the NQ ID returned from the `nq_alloc` HWRM command.
16951 uint16_t cmpl_ring;
16953 * The sequence ID is used by the driver for tracking multiple
16954 * commands. This ID is treated as opaque data by the firmware and
16955 * the value is returned in the `hwrm_resp_hdr` upon completion.
16959 * The target ID of the command:
16960 * * 0x0-0xFFF8 - The function ID
16961 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16962 * * 0xFFFD - Reserved for user-space HWRM interface
16965 uint16_t target_id;
16967 * A physical address pointer pointing to a host buffer that the
16968 * command's response data will be written. This can be either a host
16969 * physical address (HPA) or a guest physical address (GPA) and must
16970 * point to a physically contiguous block of memory.
16972 uint64_t resp_addr;
16974 * Function ID of the function that is being queried.
16975 * 0xFF... (All Fs) if the query is for the requesting
16979 uint8_t unused_0[6];
16982 /* hwrm_func_resource_qcaps_output (size:512b/64B) */
16983 struct hwrm_func_resource_qcaps_output {
16984 /* The specific error status for the command. */
16985 uint16_t error_code;
16986 /* The HWRM command request type. */
16988 /* The sequence ID from the original command. */
16990 /* The length of the response data in number of bytes. */
16992 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
16994 /* Maximum guaranteed number of MSI-X vectors supported by function */
16996 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
16997 uint16_t vf_reservation_strategy;
16998 /* The PF driver should evenly divide its remaining resources among all VFs. */
16999 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
17001 /* The PF driver should only reserve minimal resources for each VF. */
17002 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
17005 * The PF driver should not reserve any resources for each VF until
17006 * the VF interface is brought up.
17008 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
17010 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
17011 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
17012 /* Minimum guaranteed number of RSS/COS contexts */
17013 uint16_t min_rsscos_ctx;
17014 /* Maximum non-guaranteed number of RSS/COS contexts */
17015 uint16_t max_rsscos_ctx;
17016 /* Minimum guaranteed number of completion rings */
17017 uint16_t min_cmpl_rings;
17018 /* Maximum non-guaranteed number of completion rings */
17019 uint16_t max_cmpl_rings;
17020 /* Minimum guaranteed number of transmit rings */
17021 uint16_t min_tx_rings;
17022 /* Maximum non-guaranteed number of transmit rings */
17023 uint16_t max_tx_rings;
17024 /* Minimum guaranteed number of receive rings */
17025 uint16_t min_rx_rings;
17026 /* Maximum non-guaranteed number of receive rings */
17027 uint16_t max_rx_rings;
17028 /* Minimum guaranteed number of L2 contexts */
17029 uint16_t min_l2_ctxs;
17030 /* Maximum non-guaranteed number of L2 contexts */
17031 uint16_t max_l2_ctxs;
17032 /* Minimum guaranteed number of VNICs */
17033 uint16_t min_vnics;
17034 /* Maximum non-guaranteed number of VNICs */
17035 uint16_t max_vnics;
17036 /* Minimum guaranteed number of statistic contexts */
17037 uint16_t min_stat_ctx;
17038 /* Maximum non-guaranteed number of statistic contexts */
17039 uint16_t max_stat_ctx;
17040 /* Minimum guaranteed number of ring groups */
17041 uint16_t min_hw_ring_grps;
17042 /* Maximum non-guaranteed number of ring groups */
17043 uint16_t max_hw_ring_grps;
17045 * Maximum number of inputs into the transmit scheduler for this function.
17046 * The number of TX rings assigned to the function cannot exceed this value.
17048 uint16_t max_tx_scheduler_inputs;
17051 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
17052 * feature to reserve all minimum resources when minimum >= 1, otherwise
17053 * returns an error.
17055 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
17057 /* Minimum guaranteed number of Tx Key Contexts */
17058 uint16_t min_tx_key_ctxs;
17059 /* Maximum non-guaranteed number of Tx Key Contexts */
17060 uint16_t max_tx_key_ctxs;
17061 /* Minimum guaranteed number of Rx Key Contexts */
17062 uint16_t min_rx_key_ctxs;
17063 /* Maximum non-guaranteed number of Rx Key Contexts */
17064 uint16_t max_rx_key_ctxs;
17065 uint8_t unused_0[5];
17067 * This field is used in Output records to indicate that the output
17068 * is completely written to RAM. This field should be read as '1'
17069 * to indicate that the output has been completely written.
17070 * When writing a command completion or response to an internal processor,
17071 * the order of writes has to be such that this field is written last.
17076 /*****************************
17077 * hwrm_func_vf_resource_cfg *
17078 *****************************/
17081 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
17082 struct hwrm_func_vf_resource_cfg_input {
17083 /* The HWRM command request type. */
17086 * The completion ring to send the completion event on. This should
17087 * be the NQ ID returned from the `nq_alloc` HWRM command.
17089 uint16_t cmpl_ring;
17091 * The sequence ID is used by the driver for tracking multiple
17092 * commands. This ID is treated as opaque data by the firmware and
17093 * the value is returned in the `hwrm_resp_hdr` upon completion.
17097 * The target ID of the command:
17098 * * 0x0-0xFFF8 - The function ID
17099 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17100 * * 0xFFFD - Reserved for user-space HWRM interface
17103 uint16_t target_id;
17105 * A physical address pointer pointing to a host buffer that the
17106 * command's response data will be written. This can be either a host
17107 * physical address (HPA) or a guest physical address (GPA) and must
17108 * point to a physically contiguous block of memory.
17110 uint64_t resp_addr;
17111 /* VF ID that is being configured by PF */
17113 /* Maximum guaranteed number of MSI-X vectors for the function */
17115 /* Minimum guaranteed number of RSS/COS contexts */
17116 uint16_t min_rsscos_ctx;
17117 /* Maximum non-guaranteed number of RSS/COS contexts */
17118 uint16_t max_rsscos_ctx;
17119 /* Minimum guaranteed number of completion rings */
17120 uint16_t min_cmpl_rings;
17121 /* Maximum non-guaranteed number of completion rings */
17122 uint16_t max_cmpl_rings;
17123 /* Minimum guaranteed number of transmit rings */
17124 uint16_t min_tx_rings;
17125 /* Maximum non-guaranteed number of transmit rings */
17126 uint16_t max_tx_rings;
17127 /* Minimum guaranteed number of receive rings */
17128 uint16_t min_rx_rings;
17129 /* Maximum non-guaranteed number of receive rings */
17130 uint16_t max_rx_rings;
17131 /* Minimum guaranteed number of L2 contexts */
17132 uint16_t min_l2_ctxs;
17133 /* Maximum non-guaranteed number of L2 contexts */
17134 uint16_t max_l2_ctxs;
17135 /* Minimum guaranteed number of VNICs */
17136 uint16_t min_vnics;
17137 /* Maximum non-guaranteed number of VNICs */
17138 uint16_t max_vnics;
17139 /* Minimum guaranteed number of statistic contexts */
17140 uint16_t min_stat_ctx;
17141 /* Maximum non-guaranteed number of statistic contexts */
17142 uint16_t max_stat_ctx;
17143 /* Minimum guaranteed number of ring groups */
17144 uint16_t min_hw_ring_grps;
17145 /* Maximum non-guaranteed number of ring groups */
17146 uint16_t max_hw_ring_grps;
17149 * If this bit is set, all minimum resources requested should be
17150 * reserved if minimum >= 1, otherwise return error. In case of
17151 * error, keep all existing reservations before the call.
17153 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
17155 /* Minimum guaranteed number of Tx Key Contexts */
17156 uint16_t min_tx_key_ctxs;
17157 /* Maximum non-guaranteed number of Tx Key Contexts */
17158 uint16_t max_tx_key_ctxs;
17159 /* Minimum guaranteed number of Rx Key Contexts */
17160 uint16_t min_rx_key_ctxs;
17161 /* Maximum non-guaranteed number of Rx Key Contexts */
17162 uint16_t max_rx_key_ctxs;
17163 uint8_t unused_0[2];
17166 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
17167 struct hwrm_func_vf_resource_cfg_output {
17168 /* The specific error status for the command. */
17169 uint16_t error_code;
17170 /* The HWRM command request type. */
17172 /* The sequence ID from the original command. */
17174 /* The length of the response data in number of bytes. */
17176 /* Reserved number of RSS/COS contexts */
17177 uint16_t reserved_rsscos_ctx;
17178 /* Reserved number of completion rings */
17179 uint16_t reserved_cmpl_rings;
17180 /* Reserved number of transmit rings */
17181 uint16_t reserved_tx_rings;
17182 /* Reserved number of receive rings */
17183 uint16_t reserved_rx_rings;
17184 /* Reserved number of L2 contexts */
17185 uint16_t reserved_l2_ctxs;
17186 /* Reserved number of VNICs */
17187 uint16_t reserved_vnics;
17188 /* Reserved number of statistic contexts */
17189 uint16_t reserved_stat_ctx;
17190 /* Reserved number of ring groups */
17191 uint16_t reserved_hw_ring_grps;
17192 /* Actual number of Tx Key Contexts reserved */
17193 uint16_t reserved_tx_key_ctxs;
17194 /* Actual number of Rx Key Contexts reserved */
17195 uint16_t reserved_rx_key_ctxs;
17196 uint8_t unused_0[3];
17198 * This field is used in Output records to indicate that the output
17199 * is completely written to RAM. This field should be read as '1'
17200 * to indicate that the output has been completely written.
17201 * When writing a command completion or response to an internal processor,
17202 * the order of writes has to be such that this field is written last.
17207 /*********************************
17208 * hwrm_func_backing_store_qcaps *
17209 *********************************/
17212 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
17213 struct hwrm_func_backing_store_qcaps_input {
17214 /* The HWRM command request type. */
17217 * The completion ring to send the completion event on. This should
17218 * be the NQ ID returned from the `nq_alloc` HWRM command.
17220 uint16_t cmpl_ring;
17222 * The sequence ID is used by the driver for tracking multiple
17223 * commands. This ID is treated as opaque data by the firmware and
17224 * the value is returned in the `hwrm_resp_hdr` upon completion.
17228 * The target ID of the command:
17229 * * 0x0-0xFFF8 - The function ID
17230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17231 * * 0xFFFD - Reserved for user-space HWRM interface
17234 uint16_t target_id;
17236 * A physical address pointer pointing to a host buffer that the
17237 * command's response data will be written. This can be either a host
17238 * physical address (HPA) or a guest physical address (GPA) and must
17239 * point to a physically contiguous block of memory.
17241 uint64_t resp_addr;
17244 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
17245 struct hwrm_func_backing_store_qcaps_output {
17246 /* The specific error status for the command. */
17247 uint16_t error_code;
17248 /* The HWRM command request type. */
17250 /* The sequence ID from the original command. */
17252 /* The length of the response data in number of bytes. */
17254 /* Maximum number of QP context entries supported for this function. */
17255 uint32_t qp_max_entries;
17257 * Minimum number of QP context entries that are needed to be reserved
17258 * for QP1 for the PF and its VFs. PF drivers must allocate at least
17259 * this many QP context entries, even if RoCE will not be used.
17261 uint16_t qp_min_qp1_entries;
17263 * Maximum number of QP context entries that can be used for L2 and
17266 uint16_t qp_max_l2_entries;
17267 /* Number of bytes that must be allocated for each context entry. */
17268 uint16_t qp_entry_size;
17269 /* Maximum number of SRQ context entries that can be used for L2. */
17270 uint16_t srq_max_l2_entries;
17271 /* Maximum number of SRQ context entries supported for this function. */
17272 uint32_t srq_max_entries;
17273 /* Number of bytes that must be allocated for each context entry. */
17274 uint16_t srq_entry_size;
17275 /* Maximum number of CQ context entries that can be used for L2. */
17276 uint16_t cq_max_l2_entries;
17277 /* Maximum number of CQ context entries supported for this function. */
17278 uint32_t cq_max_entries;
17279 /* Number of bytes that must be allocated for each context entry. */
17280 uint16_t cq_entry_size;
17281 /* Maximum number of VNIC context entries supported for this function. */
17282 uint16_t vnic_max_vnic_entries;
17283 /* Maximum number of Ring table context entries supported for this function. */
17284 uint16_t vnic_max_ring_table_entries;
17285 /* Number of bytes that must be allocated for each context entry. */
17286 uint16_t vnic_entry_size;
17287 /* Maximum number of statistic context entries supported for this function. */
17288 uint32_t stat_max_entries;
17289 /* Number of bytes that must be allocated for each context entry. */
17290 uint16_t stat_entry_size;
17291 /* Number of bytes that must be allocated for each context entry. */
17292 uint16_t tqm_entry_size;
17293 /* Minimum number of TQM context entries required per ring. */
17294 uint32_t tqm_min_entries_per_ring;
17296 * Maximum number of TQM context entries supported per ring. This is
17297 * actually a recommended TQM queue size based on worst case usage of
17300 * TQM fastpath rings should be sized large enough to accommodate the
17301 * maximum number of QPs (either L2 or RoCE, or both if shared)
17302 * that can be enqueued to the TQM ring.
17304 * TQM slowpath rings should be sized as follows:
17306 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
17309 * num_vnics is the number of VNICs allocated in the VNIC backing store
17310 * num_l2_tx_rings is the number of L2 rings in the QP backing store
17311 * num_roce_qps is the number of RoCE QPs in the QP backing store
17312 * tqm_min_size is tqm_min_entries_per_ring reported by
17313 * HWRM_FUNC_BACKING_STORE_QCAPS
17315 * Note that TQM ring sizes cannot be extended while the system is
17316 * operational. If a PF driver needs to extend a TQM ring, it needs
17317 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
17318 * the backing store.
17320 uint32_t tqm_max_entries_per_ring;
17322 * Maximum number of MR plus AV context entries supported for this
17325 uint32_t mrav_max_entries;
17326 /* Number of bytes that must be allocated for each context entry. */
17327 uint16_t mrav_entry_size;
17328 /* Number of bytes that must be allocated for each context entry. */
17329 uint16_t tim_entry_size;
17330 /* Maximum number of Timer context entries supported for this function. */
17331 uint32_t tim_max_entries;
17333 * When this field is zero, the 32b `mrav_num_entries` field in the
17334 * `backing_store_cfg` and `backing_store_qcfg` commands represents
17335 * the total number of MR plus AV entries allowed in the MR/AV backing
17338 * When this field is non-zero, the 32b `mrav_num_entries` field in
17339 * the `backing_store_cfg` and `backing_store_qcfg` commands is
17340 * logically divided into two 16b fields. Bits `[31:16]` represents
17341 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
17342 * Both of these values are represented in a unit granularity
17343 * specified by this field. For example, if this field is 16 and
17344 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
17345 * is 8192 and the number of AV entries is 4096.
17347 uint16_t mrav_num_entries_units;
17349 * The number of entries specified for any TQM ring must be a
17350 * multiple of this value to prevent any resource allocation
17353 uint8_t tqm_entries_multiple;
17355 * Initializer to be used by drivers
17356 * to initialize context memory to ensure
17357 * context subsystem flags an error for an attack
17358 * before the first time context load.
17360 uint8_t ctx_kind_initializer;
17362 * Specifies which context kinds need to be initialized with the
17363 * ctx_kind_initializer.
17365 uint16_t ctx_init_mask;
17367 * If this bit is '1' then this context type should be initialized
17368 * with the ctx_kind_initializer at the specified offset.
17370 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
17373 * If this bit is '1' then this context type should be initialized
17374 * with the ctx_kind_initializer at the specified offset.
17376 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
17379 * If this bit is '1' then this context type should be initialized
17380 * with the ctx_kind_initializer at the specified offset.
17382 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
17385 * If this bit is '1' then this context type should be initialized
17386 * with the ctx_kind_initializer at the specified offset.
17388 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
17391 * If this bit is '1' then this context type should be initialized
17392 * with the ctx_kind_initializer at the specified offset.
17394 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
17397 * If this bit is '1' then this context type should be initialized
17398 * with the ctx_kind_initializer at the specified offset.
17400 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
17403 * If this bit is '1' then the Tx KTLS context type should be
17404 * initialized with the ctx_kind_initializer at the specified offset.
17406 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \
17409 * If this bit is '1' then the Rx KTLS context type should be
17410 * initialized with the ctx_kind_initializer at the specified offset.
17412 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \
17415 * Specifies the doubleword offset of ctx_kind_initializer for this
17418 uint8_t qp_init_offset;
17420 * Specifies the doubleword offset of ctx_kind_initializer for this
17423 uint8_t srq_init_offset;
17425 * Specifies the doubleword offset of ctx_kind_initializer for this
17428 uint8_t cq_init_offset;
17430 * Specifies the doubleword offset of ctx_kind_initializer for this
17433 uint8_t vnic_init_offset;
17435 * Count of TQM fastpath rings to be used for allocating backing store.
17436 * Backing store configuration must be specified for each TQM ring from
17437 * this count in `backing_store_cfg`.
17438 * Only first 8 TQM FP rings will be advertised with this field.
17440 uint8_t tqm_fp_rings_count;
17442 * Specifies the doubleword offset of ctx_kind_initializer for this
17445 uint8_t stat_init_offset;
17447 * Specifies the doubleword offset of ctx_kind_initializer for this
17450 uint8_t mrav_init_offset;
17452 * Count of TQM extended fastpath rings to be used for allocating
17453 * backing store beyond 8 rings(rings 9,10,11)
17454 * Backing store configuration must be specified for each TQM ring from
17455 * this count in `backing_store_cfg`.
17457 uint8_t tqm_fp_rings_count_ext;
17459 * Specifies the doubleword offset of ctx_kind_initializer for Tx
17460 * KTLS context type.
17462 uint8_t tkc_init_offset;
17464 * Specifies the doubleword offset of ctx_kind_initializer for Rx
17465 * KTLS context type.
17467 uint8_t rkc_init_offset;
17468 /* Tx KTLS context entry size in bytes. */
17469 uint16_t tkc_entry_size;
17470 /* Rx KTLS context entry size in bytes. */
17471 uint16_t rkc_entry_size;
17473 * Maximum number of Tx KTLS context entries supported for this
17476 uint32_t tkc_max_entries;
17478 * Maximum number of Rx KTLS context entries supported for this
17481 uint32_t rkc_max_entries;
17482 /* Reserved for future. */
17485 * This field is used in Output records to indicate that the output
17486 * is completely written to RAM. This field should be read as '1'
17487 * to indicate that the output has been completely written.
17488 * When writing a command completion or response to an internal processor,
17489 * the order of writes has to be such that this field is written last.
17494 /* tqm_fp_ring_cfg (size:128b/16B) */
17495 struct tqm_fp_ring_cfg {
17496 /* TQM ring page size and level. */
17497 uint8_t tqm_ring_pg_size_tqm_ring_lvl;
17498 /* TQM ring PBL indirect levels. */
17499 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
17501 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
17502 /* PBL pointer is physical start address. */
17503 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
17505 /* PBL pointer points to PTE table. */
17506 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
17509 * PBL pointer points to PDE table with each entry pointing to
17512 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
17514 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
17515 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
17516 /* TQM ring page size. */
17517 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
17519 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
17521 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
17522 (UINT32_C(0x0) << 4)
17524 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
17525 (UINT32_C(0x1) << 4)
17527 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
17528 (UINT32_C(0x2) << 4)
17530 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
17531 (UINT32_C(0x3) << 4)
17533 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
17534 (UINT32_C(0x4) << 4)
17536 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
17537 (UINT32_C(0x5) << 4)
17538 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
17539 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
17541 /* Number of TQM ring entries. */
17542 uint32_t tqm_ring_num_entries;
17543 /* TQM ring page directory. */
17544 uint64_t tqm_ring_page_dir;
17547 /*******************************
17548 * hwrm_func_backing_store_cfg *
17549 *******************************/
17552 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
17553 struct hwrm_func_backing_store_cfg_input {
17554 /* The HWRM command request type. */
17557 * The completion ring to send the completion event on. This should
17558 * be the NQ ID returned from the `nq_alloc` HWRM command.
17560 uint16_t cmpl_ring;
17562 * The sequence ID is used by the driver for tracking multiple
17563 * commands. This ID is treated as opaque data by the firmware and
17564 * the value is returned in the `hwrm_resp_hdr` upon completion.
17568 * The target ID of the command:
17569 * * 0x0-0xFFF8 - The function ID
17570 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17571 * * 0xFFFD - Reserved for user-space HWRM interface
17574 uint16_t target_id;
17576 * A physical address pointer pointing to a host buffer that the
17577 * command's response data will be written. This can be either a host
17578 * physical address (HPA) or a guest physical address (GPA) and must
17579 * point to a physically contiguous block of memory.
17581 uint64_t resp_addr;
17584 * When set, the firmware only uses on-chip resources and does not
17585 * expect any backing store to be provided by the host driver. This
17586 * mode provides minimal L2 functionality (e.g. limited L2 resources,
17589 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
17592 * When set, the 32b `mrav_num_entries` field is logically divided
17593 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
17595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
17599 * This bit must be '1' for the qp fields to be
17602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
17605 * This bit must be '1' for the srq fields to be
17608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
17611 * This bit must be '1' for the cq fields to be
17614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
17617 * This bit must be '1' for the vnic fields to be
17620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
17623 * This bit must be '1' for the stat fields to be
17626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
17629 * This bit must be '1' for the tqm_sp fields to be
17632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
17635 * This bit must be '1' for the tqm_ring0 fields to be
17638 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
17641 * This bit must be '1' for the tqm_ring1 fields to be
17644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
17647 * This bit must be '1' for the tqm_ring2 fields to be
17650 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
17653 * This bit must be '1' for the tqm_ring3 fields to be
17656 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
17659 * This bit must be '1' for the tqm_ring4 fields to be
17662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
17665 * This bit must be '1' for the tqm_ring5 fields to be
17668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
17671 * This bit must be '1' for the tqm_ring6 fields to be
17674 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
17677 * This bit must be '1' for the tqm_ring7 fields to be
17680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
17683 * This bit must be '1' for the mrav fields to be
17686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
17689 * This bit must be '1' for the tim fields to be
17692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
17695 * This bit must be '1' for the tqm_ring8 fields to be
17698 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
17701 * This bit must be '1' for the tqm_ring9 fields to be
17704 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
17707 * This bit must be '1' for the tqm_ring10 fields to be
17710 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
17713 * This bit must be '1' for the Tx KTLS context
17714 * fields to be configured.
17716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \
17719 * This bit must be '1' for the Rx KTLS context
17720 * fields to be configured.
17722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \
17724 /* QPC page size and level. */
17725 uint8_t qpc_pg_size_qpc_lvl;
17726 /* QPC PBL indirect levels. */
17727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
17729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
17730 /* PBL pointer is physical start address. */
17731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
17733 /* PBL pointer points to PTE table. */
17734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
17736 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
17739 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
17740 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
17741 /* QPC page size. */
17742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
17744 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
17746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
17747 (UINT32_C(0x0) << 4)
17749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
17750 (UINT32_C(0x1) << 4)
17752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
17753 (UINT32_C(0x2) << 4)
17755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
17756 (UINT32_C(0x3) << 4)
17758 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
17759 (UINT32_C(0x4) << 4)
17761 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
17762 (UINT32_C(0x5) << 4)
17763 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
17764 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
17765 /* SRQ page size and level. */
17766 uint8_t srq_pg_size_srq_lvl;
17767 /* SRQ PBL indirect levels. */
17768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
17770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
17771 /* PBL pointer is physical start address. */
17772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
17774 /* PBL pointer points to PTE table. */
17775 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
17777 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17778 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
17780 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
17781 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
17782 /* SRQ page size. */
17783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
17785 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
17787 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
17788 (UINT32_C(0x0) << 4)
17790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
17791 (UINT32_C(0x1) << 4)
17793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
17794 (UINT32_C(0x2) << 4)
17796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
17797 (UINT32_C(0x3) << 4)
17799 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
17800 (UINT32_C(0x4) << 4)
17802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
17803 (UINT32_C(0x5) << 4)
17804 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
17805 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
17806 /* CQ page size and level. */
17807 uint8_t cq_pg_size_cq_lvl;
17808 /* CQ PBL indirect levels. */
17809 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
17811 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
17812 /* PBL pointer is physical start address. */
17813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
17815 /* PBL pointer points to PTE table. */
17816 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
17818 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
17821 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
17822 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
17823 /* CQ page size. */
17824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
17826 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
17828 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
17829 (UINT32_C(0x0) << 4)
17831 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
17832 (UINT32_C(0x1) << 4)
17834 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
17835 (UINT32_C(0x2) << 4)
17837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
17838 (UINT32_C(0x3) << 4)
17840 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
17841 (UINT32_C(0x4) << 4)
17843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
17844 (UINT32_C(0x5) << 4)
17845 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
17846 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
17847 /* VNIC page size and level. */
17848 uint8_t vnic_pg_size_vnic_lvl;
17849 /* VNIC PBL indirect levels. */
17850 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
17852 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
17853 /* PBL pointer is physical start address. */
17854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
17856 /* PBL pointer points to PTE table. */
17857 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
17859 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17860 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
17862 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
17863 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
17864 /* VNIC page size. */
17865 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
17867 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
17869 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
17870 (UINT32_C(0x0) << 4)
17872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
17873 (UINT32_C(0x1) << 4)
17875 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
17876 (UINT32_C(0x2) << 4)
17878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
17879 (UINT32_C(0x3) << 4)
17881 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
17882 (UINT32_C(0x4) << 4)
17884 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
17885 (UINT32_C(0x5) << 4)
17886 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
17887 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
17888 /* Stat page size and level. */
17889 uint8_t stat_pg_size_stat_lvl;
17890 /* Stat PBL indirect levels. */
17891 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
17893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
17894 /* PBL pointer is physical start address. */
17895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
17897 /* PBL pointer points to PTE table. */
17898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
17900 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17901 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
17903 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
17904 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
17905 /* Stat page size. */
17906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
17908 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
17910 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
17911 (UINT32_C(0x0) << 4)
17913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
17914 (UINT32_C(0x1) << 4)
17916 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
17917 (UINT32_C(0x2) << 4)
17919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
17920 (UINT32_C(0x3) << 4)
17922 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
17923 (UINT32_C(0x4) << 4)
17925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
17926 (UINT32_C(0x5) << 4)
17927 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
17928 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
17929 /* TQM slow path page size and level. */
17930 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
17931 /* TQM slow path PBL indirect levels. */
17932 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
17934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
17935 /* PBL pointer is physical start address. */
17936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
17938 /* PBL pointer points to PTE table. */
17939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
17941 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17942 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
17944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
17945 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
17946 /* TQM slow path page size. */
17947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
17949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
17951 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
17952 (UINT32_C(0x0) << 4)
17954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
17955 (UINT32_C(0x1) << 4)
17957 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
17958 (UINT32_C(0x2) << 4)
17960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
17961 (UINT32_C(0x3) << 4)
17963 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
17964 (UINT32_C(0x4) << 4)
17966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
17967 (UINT32_C(0x5) << 4)
17968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
17969 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
17970 /* TQM ring 0 page size and level. */
17971 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
17972 /* TQM ring 0 PBL indirect levels. */
17973 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
17975 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
17976 /* PBL pointer is physical start address. */
17977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
17979 /* PBL pointer points to PTE table. */
17980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
17982 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17983 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
17985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
17986 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
17987 /* TQM ring 0 page size. */
17988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
17990 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
17992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
17993 (UINT32_C(0x0) << 4)
17995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
17996 (UINT32_C(0x1) << 4)
17998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
17999 (UINT32_C(0x2) << 4)
18001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
18002 (UINT32_C(0x3) << 4)
18004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
18005 (UINT32_C(0x4) << 4)
18007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
18008 (UINT32_C(0x5) << 4)
18009 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
18010 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
18011 /* TQM ring 1 page size and level. */
18012 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
18013 /* TQM ring 1 PBL indirect levels. */
18014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
18016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
18017 /* PBL pointer is physical start address. */
18018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
18020 /* PBL pointer points to PTE table. */
18021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
18023 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18024 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
18026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
18027 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
18028 /* TQM ring 1 page size. */
18029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
18031 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
18033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
18034 (UINT32_C(0x0) << 4)
18036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
18037 (UINT32_C(0x1) << 4)
18039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
18040 (UINT32_C(0x2) << 4)
18042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
18043 (UINT32_C(0x3) << 4)
18045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
18046 (UINT32_C(0x4) << 4)
18048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
18049 (UINT32_C(0x5) << 4)
18050 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
18051 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
18052 /* TQM ring 2 page size and level. */
18053 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
18054 /* TQM ring 2 PBL indirect levels. */
18055 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
18057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
18058 /* PBL pointer is physical start address. */
18059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
18061 /* PBL pointer points to PTE table. */
18062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
18064 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
18067 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
18068 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
18069 /* TQM ring 2 page size. */
18070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
18072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
18074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
18075 (UINT32_C(0x0) << 4)
18077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
18078 (UINT32_C(0x1) << 4)
18080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
18081 (UINT32_C(0x2) << 4)
18083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
18084 (UINT32_C(0x3) << 4)
18086 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
18087 (UINT32_C(0x4) << 4)
18089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
18090 (UINT32_C(0x5) << 4)
18091 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
18092 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
18093 /* TQM ring 3 page size and level. */
18094 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
18095 /* TQM ring 3 PBL indirect levels. */
18096 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
18098 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
18099 /* PBL pointer is physical start address. */
18100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
18102 /* PBL pointer points to PTE table. */
18103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
18105 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
18108 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
18109 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
18110 /* TQM ring 3 page size. */
18111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
18113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
18115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
18116 (UINT32_C(0x0) << 4)
18118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
18119 (UINT32_C(0x1) << 4)
18121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
18122 (UINT32_C(0x2) << 4)
18124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
18125 (UINT32_C(0x3) << 4)
18127 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
18128 (UINT32_C(0x4) << 4)
18130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
18131 (UINT32_C(0x5) << 4)
18132 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
18133 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
18134 /* TQM ring 4 page size and level. */
18135 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
18136 /* TQM ring 4 PBL indirect levels. */
18137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
18139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
18140 /* PBL pointer is physical start address. */
18141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
18143 /* PBL pointer points to PTE table. */
18144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
18146 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
18149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
18150 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
18151 /* TQM ring 4 page size. */
18152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
18154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
18156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
18157 (UINT32_C(0x0) << 4)
18159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
18160 (UINT32_C(0x1) << 4)
18162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
18163 (UINT32_C(0x2) << 4)
18165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
18166 (UINT32_C(0x3) << 4)
18168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
18169 (UINT32_C(0x4) << 4)
18171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
18172 (UINT32_C(0x5) << 4)
18173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
18174 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
18175 /* TQM ring 5 page size and level. */
18176 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
18177 /* TQM ring 5 PBL indirect levels. */
18178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
18180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
18181 /* PBL pointer is physical start address. */
18182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
18184 /* PBL pointer points to PTE table. */
18185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
18187 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
18190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
18191 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
18192 /* TQM ring 5 page size. */
18193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
18195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
18197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
18198 (UINT32_C(0x0) << 4)
18200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
18201 (UINT32_C(0x1) << 4)
18203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
18204 (UINT32_C(0x2) << 4)
18206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
18207 (UINT32_C(0x3) << 4)
18209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
18210 (UINT32_C(0x4) << 4)
18212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
18213 (UINT32_C(0x5) << 4)
18214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
18215 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
18216 /* TQM ring 6 page size and level. */
18217 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
18218 /* TQM ring 6 PBL indirect levels. */
18219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
18221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
18222 /* PBL pointer is physical start address. */
18223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
18225 /* PBL pointer points to PTE table. */
18226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
18228 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
18231 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
18232 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
18233 /* TQM ring 6 page size. */
18234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
18236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
18238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
18239 (UINT32_C(0x0) << 4)
18241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
18242 (UINT32_C(0x1) << 4)
18244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
18245 (UINT32_C(0x2) << 4)
18247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
18248 (UINT32_C(0x3) << 4)
18250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
18251 (UINT32_C(0x4) << 4)
18253 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
18254 (UINT32_C(0x5) << 4)
18255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
18256 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
18257 /* TQM ring 7 page size and level. */
18258 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
18259 /* TQM ring 7 PBL indirect levels. */
18260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
18262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
18263 /* PBL pointer is physical start address. */
18264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
18266 /* PBL pointer points to PTE table. */
18267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
18269 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
18272 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
18273 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
18274 /* TQM ring 7 page size. */
18275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
18277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
18279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
18280 (UINT32_C(0x0) << 4)
18282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
18283 (UINT32_C(0x1) << 4)
18285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
18286 (UINT32_C(0x2) << 4)
18288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
18289 (UINT32_C(0x3) << 4)
18291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
18292 (UINT32_C(0x4) << 4)
18294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
18295 (UINT32_C(0x5) << 4)
18296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
18297 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
18298 /* MR/AV page size and level. */
18299 uint8_t mrav_pg_size_mrav_lvl;
18300 /* MR/AV PBL indirect levels. */
18301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
18303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
18304 /* PBL pointer is physical start address. */
18305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
18307 /* PBL pointer points to PTE table. */
18308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
18310 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
18313 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
18314 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
18315 /* MR/AV page size. */
18316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
18318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
18320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
18321 (UINT32_C(0x0) << 4)
18323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
18324 (UINT32_C(0x1) << 4)
18326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
18327 (UINT32_C(0x2) << 4)
18329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
18330 (UINT32_C(0x3) << 4)
18332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
18333 (UINT32_C(0x4) << 4)
18335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
18336 (UINT32_C(0x5) << 4)
18337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
18338 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
18339 /* Timer page size and level. */
18340 uint8_t tim_pg_size_tim_lvl;
18341 /* Timer PBL indirect levels. */
18342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
18344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
18345 /* PBL pointer is physical start address. */
18346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
18348 /* PBL pointer points to PTE table. */
18349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
18351 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
18354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
18355 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
18356 /* Timer page size. */
18357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
18359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
18361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
18362 (UINT32_C(0x0) << 4)
18364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
18365 (UINT32_C(0x1) << 4)
18367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
18368 (UINT32_C(0x2) << 4)
18370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
18371 (UINT32_C(0x3) << 4)
18373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
18374 (UINT32_C(0x4) << 4)
18376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
18377 (UINT32_C(0x5) << 4)
18378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
18379 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
18380 /* QP page directory. */
18381 uint64_t qpc_page_dir;
18382 /* SRQ page directory. */
18383 uint64_t srq_page_dir;
18384 /* CQ page directory. */
18385 uint64_t cq_page_dir;
18386 /* VNIC page directory. */
18387 uint64_t vnic_page_dir;
18388 /* Stat page directory. */
18389 uint64_t stat_page_dir;
18390 /* TQM slowpath page directory. */
18391 uint64_t tqm_sp_page_dir;
18392 /* TQM ring 0 page directory. */
18393 uint64_t tqm_ring0_page_dir;
18394 /* TQM ring 1 page directory. */
18395 uint64_t tqm_ring1_page_dir;
18396 /* TQM ring 2 page directory. */
18397 uint64_t tqm_ring2_page_dir;
18398 /* TQM ring 3 page directory. */
18399 uint64_t tqm_ring3_page_dir;
18400 /* TQM ring 4 page directory. */
18401 uint64_t tqm_ring4_page_dir;
18402 /* TQM ring 5 page directory. */
18403 uint64_t tqm_ring5_page_dir;
18404 /* TQM ring 6 page directory. */
18405 uint64_t tqm_ring6_page_dir;
18406 /* TQM ring 7 page directory. */
18407 uint64_t tqm_ring7_page_dir;
18408 /* MR/AV page directory. */
18409 uint64_t mrav_page_dir;
18410 /* Timer page directory. */
18411 uint64_t tim_page_dir;
18412 /* Number of QPs. */
18413 uint32_t qp_num_entries;
18414 /* Number of SRQs. */
18415 uint32_t srq_num_entries;
18416 /* Number of CQs. */
18417 uint32_t cq_num_entries;
18418 /* Number of Stats. */
18419 uint32_t stat_num_entries;
18421 * Number of TQM slowpath entries.
18423 * TQM slowpath rings should be sized as follows:
18425 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
18428 * num_vnics is the number of VNICs allocated in the VNIC backing store
18429 * num_l2_tx_rings is the number of L2 rings in the QP backing store
18430 * num_roce_qps is the number of RoCE QPs in the QP backing store
18431 * tqm_min_size is tqm_min_entries_per_ring reported by
18432 * HWRM_FUNC_BACKING_STORE_QCAPS
18434 * Note that TQM ring sizes cannot be extended while the system is
18435 * operational. If a PF driver needs to extend a TQM ring, it needs
18436 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18437 * the backing store.
18439 uint32_t tqm_sp_num_entries;
18441 * Number of TQM ring 0 entries.
18443 * TQM fastpath rings should be sized large enough to accommodate the
18444 * maximum number of QPs (either L2 or RoCE, or both if shared)
18445 * that can be enqueued to the TQM ring.
18447 * Note that TQM ring sizes cannot be extended while the system is
18448 * operational. If a PF driver needs to extend a TQM ring, it needs
18449 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18450 * the backing store.
18452 uint32_t tqm_ring0_num_entries;
18454 * Number of TQM ring 1 entries.
18456 * TQM fastpath rings should be sized large enough to accommodate the
18457 * maximum number of QPs (either L2 or RoCE, or both if shared)
18458 * that can be enqueued to the TQM ring.
18460 * Note that TQM ring sizes cannot be extended while the system is
18461 * operational. If a PF driver needs to extend a TQM ring, it needs
18462 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18463 * the backing store.
18465 uint32_t tqm_ring1_num_entries;
18467 * Number of TQM ring 2 entries.
18469 * TQM fastpath rings should be sized large enough to accommodate the
18470 * maximum number of QPs (either L2 or RoCE, or both if shared)
18471 * that can be enqueued to the TQM ring.
18473 * Note that TQM ring sizes cannot be extended while the system is
18474 * operational. If a PF driver needs to extend a TQM ring, it needs
18475 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18476 * the backing store.
18478 uint32_t tqm_ring2_num_entries;
18480 * Number of TQM ring 3 entries.
18482 * TQM fastpath rings should be sized large enough to accommodate the
18483 * maximum number of QPs (either L2 or RoCE, or both if shared)
18484 * that can be enqueued to the TQM ring.
18486 * Note that TQM ring sizes cannot be extended while the system is
18487 * operational. If a PF driver needs to extend a TQM ring, it needs
18488 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18489 * the backing store.
18491 uint32_t tqm_ring3_num_entries;
18493 * Number of TQM ring 4 entries.
18495 * TQM fastpath rings should be sized large enough to accommodate the
18496 * maximum number of QPs (either L2 or RoCE, or both if shared)
18497 * that can be enqueued to the TQM ring.
18499 * Note that TQM ring sizes cannot be extended while the system is
18500 * operational. If a PF driver needs to extend a TQM ring, it needs
18501 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18502 * the backing store.
18504 uint32_t tqm_ring4_num_entries;
18506 * Number of TQM ring 5 entries.
18508 * TQM fastpath rings should be sized large enough to accommodate the
18509 * maximum number of QPs (either L2 or RoCE, or both if shared)
18510 * that can be enqueued to the TQM ring.
18512 * Note that TQM ring sizes cannot be extended while the system is
18513 * operational. If a PF driver needs to extend a TQM ring, it needs
18514 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18515 * the backing store.
18517 uint32_t tqm_ring5_num_entries;
18519 * Number of TQM ring 6 entries.
18521 * TQM fastpath rings should be sized large enough to accommodate the
18522 * maximum number of QPs (either L2 or RoCE, or both if shared)
18523 * that can be enqueued to the TQM ring.
18525 * Note that TQM ring sizes cannot be extended while the system is
18526 * operational. If a PF driver needs to extend a TQM ring, it needs
18527 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18528 * the backing store.
18530 uint32_t tqm_ring6_num_entries;
18532 * Number of TQM ring 7 entries.
18534 * TQM fastpath rings should be sized large enough to accommodate the
18535 * maximum number of QPs (either L2 or RoCE, or both if shared)
18536 * that can be enqueued to the TQM ring.
18538 * Note that TQM ring sizes cannot be extended while the system is
18539 * operational. If a PF driver needs to extend a TQM ring, it needs
18540 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
18541 * the backing store.
18543 uint32_t tqm_ring7_num_entries;
18545 * If the MR/AV split reservation flag is not set, then this field
18546 * represents the total number of MR plus AV entries. For versions
18547 * of firmware that support the split reservation, when it is not
18548 * specified half of the entries will be reserved for MRs and the
18549 * other half for AVs.
18551 * If the MR/AV split reservation flag is set, then this
18552 * field is logically divided into two 16b fields. Bits `[31:16]`
18553 * represents the `mr_num_entries` and bits `[15:0]` represents
18554 * `av_num_entries`. The granularity of these values is defined by
18555 * the `mrav_num_entries_unit` field returned by the
18556 * `backing_store_qcaps` command.
18558 uint32_t mrav_num_entries;
18559 /* Number of Timer entries. */
18560 uint32_t tim_num_entries;
18561 /* Number of entries to reserve for QP1 */
18562 uint16_t qp_num_qp1_entries;
18563 /* Number of entries to reserve for L2 */
18564 uint16_t qp_num_l2_entries;
18565 /* Number of bytes that have been allocated for each context entry. */
18566 uint16_t qp_entry_size;
18567 /* Number of entries to reserve for L2 */
18568 uint16_t srq_num_l2_entries;
18569 /* Number of bytes that have been allocated for each context entry. */
18570 uint16_t srq_entry_size;
18571 /* Number of entries to reserve for L2 */
18572 uint16_t cq_num_l2_entries;
18573 /* Number of bytes that have been allocated for each context entry. */
18574 uint16_t cq_entry_size;
18575 /* Number of entries to reserve for VNIC entries */
18576 uint16_t vnic_num_vnic_entries;
18577 /* Number of entries to reserve for Ring table entries */
18578 uint16_t vnic_num_ring_table_entries;
18579 /* Number of bytes that have been allocated for each context entry. */
18580 uint16_t vnic_entry_size;
18581 /* Number of bytes that have been allocated for each context entry. */
18582 uint16_t stat_entry_size;
18583 /* Number of bytes that have been allocated for each context entry. */
18584 uint16_t tqm_entry_size;
18585 /* Number of bytes that have been allocated for each context entry. */
18586 uint16_t mrav_entry_size;
18587 /* Number of bytes that have been allocated for each context entry. */
18588 uint16_t tim_entry_size;
18589 /* TQM ring page size and level. */
18590 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
18591 /* TQM ring PBL indirect levels. */
18592 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
18594 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
18596 /* PBL pointer is physical start address. */
18597 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
18599 /* PBL pointer points to PTE table. */
18600 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
18603 * PBL pointer points to PDE table with each entry pointing to
18606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
18608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
18609 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
18610 /* TQM ring page size. */
18611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
18613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
18616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
18617 (UINT32_C(0x0) << 4)
18619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
18620 (UINT32_C(0x1) << 4)
18622 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
18623 (UINT32_C(0x2) << 4)
18625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
18626 (UINT32_C(0x3) << 4)
18628 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
18629 (UINT32_C(0x4) << 4)
18631 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
18632 (UINT32_C(0x5) << 4)
18633 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
18634 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
18635 uint8_t ring8_unused[3];
18636 /* Number of TQM ring entries. */
18637 uint32_t tqm_ring8_num_entries;
18638 /* TQM ring page directory. */
18639 uint64_t tqm_ring8_page_dir;
18640 /* TQM ring page size and level. */
18641 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
18642 /* TQM ring PBL indirect levels. */
18643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
18645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
18647 /* PBL pointer is physical start address. */
18648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
18650 /* PBL pointer points to PTE table. */
18651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
18654 * PBL pointer points to PDE table with each entry pointing to
18657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
18659 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
18660 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
18661 /* TQM ring page size. */
18662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
18664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
18667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
18668 (UINT32_C(0x0) << 4)
18670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
18671 (UINT32_C(0x1) << 4)
18673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
18674 (UINT32_C(0x2) << 4)
18676 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
18677 (UINT32_C(0x3) << 4)
18679 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
18680 (UINT32_C(0x4) << 4)
18682 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
18683 (UINT32_C(0x5) << 4)
18684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
18685 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
18686 uint8_t ring9_unused[3];
18687 /* Number of TQM ring entries. */
18688 uint32_t tqm_ring9_num_entries;
18689 /* TQM ring page directory. */
18690 uint64_t tqm_ring9_page_dir;
18691 /* TQM ring page size and level. */
18692 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
18693 /* TQM ring PBL indirect levels. */
18694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
18696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
18698 /* PBL pointer is physical start address. */
18699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
18701 /* PBL pointer points to PTE table. */
18702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
18705 * PBL pointer points to PDE table with each entry pointing to
18708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
18710 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
18711 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
18712 /* TQM ring page size. */
18713 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
18715 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
18718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
18719 (UINT32_C(0x0) << 4)
18721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
18722 (UINT32_C(0x1) << 4)
18724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
18725 (UINT32_C(0x2) << 4)
18727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
18728 (UINT32_C(0x3) << 4)
18730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
18731 (UINT32_C(0x4) << 4)
18733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
18734 (UINT32_C(0x5) << 4)
18735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
18736 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
18737 uint8_t ring10_unused[3];
18738 /* Number of TQM ring entries. */
18739 uint32_t tqm_ring10_num_entries;
18740 /* TQM ring page directory. */
18741 uint64_t tqm_ring10_page_dir;
18742 /* Number of Tx KTLS context entries allocated. */
18743 uint32_t tkc_num_entries;
18744 /* Number of Rx KTLS context entries allocated. */
18745 uint32_t rkc_num_entries;
18746 /* Tx KTLS context page directory. */
18747 uint64_t tkc_page_dir;
18748 /* Rx KTLS context page directory. */
18749 uint64_t rkc_page_dir;
18750 /* Number of bytes allocated for each Tx KTLS context entry. */
18751 uint16_t tkc_entry_size;
18752 /* Number of bytes allocated for each Rx KTLS context entry. */
18753 uint16_t rkc_entry_size;
18754 /* Tx KTLS context page size and level. */
18755 uint8_t tkc_pg_size_tkc_lvl;
18756 /* Tx KTLS context PBL indirect levels. */
18757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \
18759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0
18760 /* PBL pointer is physical start address. */
18761 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \
18763 /* PBL pointer points to PTE table. */
18764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \
18766 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
18767 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \
18769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \
18770 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2
18771 /* Tx KTLS context page size. */
18772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \
18774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4
18776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \
18777 (UINT32_C(0x0) << 4)
18779 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \
18780 (UINT32_C(0x1) << 4)
18782 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \
18783 (UINT32_C(0x2) << 4)
18785 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \
18786 (UINT32_C(0x3) << 4)
18788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \
18789 (UINT32_C(0x4) << 4)
18791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \
18792 (UINT32_C(0x5) << 4)
18793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \
18794 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G
18795 /* Rx KTLS context page size and level. */
18796 uint8_t rkc_pg_size_rkc_lvl;
18797 /* Rx KTLS context PBL indirect levels. */
18798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \
18800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0
18801 /* PBL pointer is physical start address. */
18802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \
18804 /* PBL pointer points to PTE table. */
18805 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \
18808 * PBL pointer points to PDE table with each entry pointing to
18811 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \
18813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \
18814 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2
18815 /* Rx KTLS context page size. */
18816 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \
18818 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4
18820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \
18821 (UINT32_C(0x0) << 4)
18823 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \
18824 (UINT32_C(0x1) << 4)
18826 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \
18827 (UINT32_C(0x2) << 4)
18829 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \
18830 (UINT32_C(0x3) << 4)
18832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \
18833 (UINT32_C(0x4) << 4)
18835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \
18836 (UINT32_C(0x5) << 4)
18837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \
18838 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G
18839 /* Reserved for future. */
18843 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
18844 struct hwrm_func_backing_store_cfg_output {
18845 /* The specific error status for the command. */
18846 uint16_t error_code;
18847 /* The HWRM command request type. */
18849 /* The sequence ID from the original command. */
18851 /* The length of the response data in number of bytes. */
18853 uint8_t unused_0[7];
18855 * This field is used in Output records to indicate that the output
18856 * is completely written to RAM. This field should be read as '1'
18857 * to indicate that the output has been completely written.
18858 * When writing a command completion or response to an internal processor,
18859 * the order of writes has to be such that this field is written last.
18864 /********************************
18865 * hwrm_func_backing_store_qcfg *
18866 ********************************/
18869 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
18870 struct hwrm_func_backing_store_qcfg_input {
18871 /* The HWRM command request type. */
18874 * The completion ring to send the completion event on. This should
18875 * be the NQ ID returned from the `nq_alloc` HWRM command.
18877 uint16_t cmpl_ring;
18879 * The sequence ID is used by the driver for tracking multiple
18880 * commands. This ID is treated as opaque data by the firmware and
18881 * the value is returned in the `hwrm_resp_hdr` upon completion.
18885 * The target ID of the command:
18886 * * 0x0-0xFFF8 - The function ID
18887 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18888 * * 0xFFFD - Reserved for user-space HWRM interface
18891 uint16_t target_id;
18893 * A physical address pointer pointing to a host buffer that the
18894 * command's response data will be written. This can be either a host
18895 * physical address (HPA) or a guest physical address (GPA) and must
18896 * point to a physically contiguous block of memory.
18898 uint64_t resp_addr;
18901 /* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */
18902 struct hwrm_func_backing_store_qcfg_output {
18903 /* The specific error status for the command. */
18904 uint16_t error_code;
18905 /* The HWRM command request type. */
18907 /* The sequence ID from the original command. */
18909 /* The length of the response data in number of bytes. */
18913 * When set, the firmware only uses on-chip resources and does not
18914 * expect any backing store to be provided by the host driver. This
18915 * mode provides minimal L2 functionality (e.g. limited L2 resources,
18918 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
18921 * When set, the 32b `mrav_num_entries` field is logically divided
18922 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
18924 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
18928 * This bit must be '1' for the qp fields to be
18931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
18934 * This bit must be '1' for the srq fields to be
18937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
18940 * This bit must be '1' for the cq fields to be
18943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
18946 * This bit must be '1' for the vnic fields to be
18949 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
18952 * This bit must be '1' for the stat fields to be
18955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
18958 * This bit must be '1' for the tqm_sp fields to be
18961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
18964 * This bit must be '1' for the tqm_ring0 fields to be
18967 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
18970 * This bit must be '1' for the tqm_ring1 fields to be
18973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
18976 * This bit must be '1' for the tqm_ring2 fields to be
18979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
18982 * This bit must be '1' for the tqm_ring3 fields to be
18985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
18988 * This bit must be '1' for the tqm_ring4 fields to be
18991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
18994 * This bit must be '1' for the tqm_ring5 fields to be
18997 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
19000 * This bit must be '1' for the tqm_ring6 fields to be
19003 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
19006 * This bit must be '1' for the tqm_ring7 fields to be
19009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
19012 * This bit must be '1' for the mrav fields to be
19015 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
19018 * This bit must be '1' for the tim fields to be
19021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
19024 * This bit must be '1' for the tqm_ring8 fields to be
19027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
19030 * This bit must be '1' for the tqm_ring9 fields to be
19033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
19036 * This bit must be '1' for the tqm_ring10 fields to be
19039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
19042 * This bit must be '1' for the Tx KTLS context
19043 * fields to be configured.
19045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \
19048 * This bit must be '1' for the Rx KTLS context
19049 * fields to be configured.
19051 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \
19053 /* QPC page size and level. */
19054 uint8_t qpc_pg_size_qpc_lvl;
19055 /* QPC PBL indirect levels. */
19056 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
19058 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
19059 /* PBL pointer is physical start address. */
19060 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
19062 /* PBL pointer points to PTE table. */
19063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
19065 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19066 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
19068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
19069 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
19070 /* QPC page size. */
19071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
19073 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
19075 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
19076 (UINT32_C(0x0) << 4)
19078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
19079 (UINT32_C(0x1) << 4)
19081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
19082 (UINT32_C(0x2) << 4)
19084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
19085 (UINT32_C(0x3) << 4)
19087 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
19088 (UINT32_C(0x4) << 4)
19090 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
19091 (UINT32_C(0x5) << 4)
19092 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
19093 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
19094 /* SRQ page size and level. */
19095 uint8_t srq_pg_size_srq_lvl;
19096 /* SRQ PBL indirect levels. */
19097 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
19099 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
19100 /* PBL pointer is physical start address. */
19101 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
19103 /* PBL pointer points to PTE table. */
19104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
19106 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19107 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
19109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
19110 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
19111 /* SRQ page size. */
19112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
19114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
19116 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
19117 (UINT32_C(0x0) << 4)
19119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
19120 (UINT32_C(0x1) << 4)
19122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
19123 (UINT32_C(0x2) << 4)
19125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
19126 (UINT32_C(0x3) << 4)
19128 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
19129 (UINT32_C(0x4) << 4)
19131 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
19132 (UINT32_C(0x5) << 4)
19133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
19134 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
19135 /* CQ page size and level. */
19136 uint8_t cq_pg_size_cq_lvl;
19137 /* CQ PBL indirect levels. */
19138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
19140 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
19141 /* PBL pointer is physical start address. */
19142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
19144 /* PBL pointer points to PTE table. */
19145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
19147 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
19150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
19151 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
19152 /* CQ page size. */
19153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
19155 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
19157 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
19158 (UINT32_C(0x0) << 4)
19160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
19161 (UINT32_C(0x1) << 4)
19163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
19164 (UINT32_C(0x2) << 4)
19166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
19167 (UINT32_C(0x3) << 4)
19169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
19170 (UINT32_C(0x4) << 4)
19172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
19173 (UINT32_C(0x5) << 4)
19174 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
19175 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
19176 /* VNIC page size and level. */
19177 uint8_t vnic_pg_size_vnic_lvl;
19178 /* VNIC PBL indirect levels. */
19179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
19181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
19182 /* PBL pointer is physical start address. */
19183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
19185 /* PBL pointer points to PTE table. */
19186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
19188 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
19191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
19192 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
19193 /* VNIC page size. */
19194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
19196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
19198 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
19199 (UINT32_C(0x0) << 4)
19201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
19202 (UINT32_C(0x1) << 4)
19204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
19205 (UINT32_C(0x2) << 4)
19207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
19208 (UINT32_C(0x3) << 4)
19210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
19211 (UINT32_C(0x4) << 4)
19213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
19214 (UINT32_C(0x5) << 4)
19215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
19216 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
19217 /* Stat page size and level. */
19218 uint8_t stat_pg_size_stat_lvl;
19219 /* Stat PBL indirect levels. */
19220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
19222 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
19223 /* PBL pointer is physical start address. */
19224 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
19226 /* PBL pointer points to PTE table. */
19227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
19229 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
19232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
19233 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
19234 /* Stat page size. */
19235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
19237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
19239 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
19240 (UINT32_C(0x0) << 4)
19242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
19243 (UINT32_C(0x1) << 4)
19245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
19246 (UINT32_C(0x2) << 4)
19248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
19249 (UINT32_C(0x3) << 4)
19251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
19252 (UINT32_C(0x4) << 4)
19254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
19255 (UINT32_C(0x5) << 4)
19256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
19257 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
19258 /* TQM slow path page size and level. */
19259 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
19260 /* TQM slow path PBL indirect levels. */
19261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
19263 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
19264 /* PBL pointer is physical start address. */
19265 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
19267 /* PBL pointer points to PTE table. */
19268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
19270 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
19273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
19274 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
19275 /* TQM slow path page size. */
19276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
19278 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
19280 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
19281 (UINT32_C(0x0) << 4)
19283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
19284 (UINT32_C(0x1) << 4)
19286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
19287 (UINT32_C(0x2) << 4)
19289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
19290 (UINT32_C(0x3) << 4)
19292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
19293 (UINT32_C(0x4) << 4)
19295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
19296 (UINT32_C(0x5) << 4)
19297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
19298 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
19299 /* TQM ring 0 page size and level. */
19300 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
19301 /* TQM ring 0 PBL indirect levels. */
19302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
19304 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
19305 /* PBL pointer is physical start address. */
19306 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
19308 /* PBL pointer points to PTE table. */
19309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
19311 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
19314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
19315 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
19316 /* TQM ring 0 page size. */
19317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
19319 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
19321 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
19322 (UINT32_C(0x0) << 4)
19324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
19325 (UINT32_C(0x1) << 4)
19327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
19328 (UINT32_C(0x2) << 4)
19330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
19331 (UINT32_C(0x3) << 4)
19333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
19334 (UINT32_C(0x4) << 4)
19336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
19337 (UINT32_C(0x5) << 4)
19338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
19339 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
19340 /* TQM ring 1 page size and level. */
19341 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
19342 /* TQM ring 1 PBL indirect levels. */
19343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
19345 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
19346 /* PBL pointer is physical start address. */
19347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
19349 /* PBL pointer points to PTE table. */
19350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
19352 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
19355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
19356 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
19357 /* TQM ring 1 page size. */
19358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
19360 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
19362 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
19363 (UINT32_C(0x0) << 4)
19365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
19366 (UINT32_C(0x1) << 4)
19368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
19369 (UINT32_C(0x2) << 4)
19371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
19372 (UINT32_C(0x3) << 4)
19374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
19375 (UINT32_C(0x4) << 4)
19377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
19378 (UINT32_C(0x5) << 4)
19379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
19380 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
19381 /* TQM ring 2 page size and level. */
19382 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
19383 /* TQM ring 2 PBL indirect levels. */
19384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
19386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
19387 /* PBL pointer is physical start address. */
19388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
19390 /* PBL pointer points to PTE table. */
19391 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
19393 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
19396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
19397 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
19398 /* TQM ring 2 page size. */
19399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
19401 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
19403 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
19404 (UINT32_C(0x0) << 4)
19406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
19407 (UINT32_C(0x1) << 4)
19409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
19410 (UINT32_C(0x2) << 4)
19412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
19413 (UINT32_C(0x3) << 4)
19415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
19416 (UINT32_C(0x4) << 4)
19418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
19419 (UINT32_C(0x5) << 4)
19420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
19421 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
19422 /* TQM ring 3 page size and level. */
19423 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
19424 /* TQM ring 3 PBL indirect levels. */
19425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
19427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
19428 /* PBL pointer is physical start address. */
19429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
19431 /* PBL pointer points to PTE table. */
19432 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
19434 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
19437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
19438 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
19439 /* TQM ring 3 page size. */
19440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
19442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
19444 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
19445 (UINT32_C(0x0) << 4)
19447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
19448 (UINT32_C(0x1) << 4)
19450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
19451 (UINT32_C(0x2) << 4)
19453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
19454 (UINT32_C(0x3) << 4)
19456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
19457 (UINT32_C(0x4) << 4)
19459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
19460 (UINT32_C(0x5) << 4)
19461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
19462 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
19463 /* TQM ring 4 page size and level. */
19464 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
19465 /* TQM ring 4 PBL indirect levels. */
19466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
19468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
19469 /* PBL pointer is physical start address. */
19470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
19472 /* PBL pointer points to PTE table. */
19473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
19475 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
19478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
19479 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
19480 /* TQM ring 4 page size. */
19481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
19483 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
19485 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
19486 (UINT32_C(0x0) << 4)
19488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
19489 (UINT32_C(0x1) << 4)
19491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
19492 (UINT32_C(0x2) << 4)
19494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
19495 (UINT32_C(0x3) << 4)
19497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
19498 (UINT32_C(0x4) << 4)
19500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
19501 (UINT32_C(0x5) << 4)
19502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
19503 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
19504 /* TQM ring 5 page size and level. */
19505 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
19506 /* TQM ring 5 PBL indirect levels. */
19507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
19509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
19510 /* PBL pointer is physical start address. */
19511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
19513 /* PBL pointer points to PTE table. */
19514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
19516 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
19519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
19520 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
19521 /* TQM ring 5 page size. */
19522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
19524 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
19526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
19527 (UINT32_C(0x0) << 4)
19529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
19530 (UINT32_C(0x1) << 4)
19532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
19533 (UINT32_C(0x2) << 4)
19535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
19536 (UINT32_C(0x3) << 4)
19538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
19539 (UINT32_C(0x4) << 4)
19541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
19542 (UINT32_C(0x5) << 4)
19543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
19544 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
19545 /* TQM ring 6 page size and level. */
19546 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
19547 /* TQM ring 6 PBL indirect levels. */
19548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
19550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
19551 /* PBL pointer is physical start address. */
19552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
19554 /* PBL pointer points to PTE table. */
19555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
19557 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
19560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
19561 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
19562 /* TQM ring 6 page size. */
19563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
19565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
19567 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
19568 (UINT32_C(0x0) << 4)
19570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
19571 (UINT32_C(0x1) << 4)
19573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
19574 (UINT32_C(0x2) << 4)
19576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
19577 (UINT32_C(0x3) << 4)
19579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
19580 (UINT32_C(0x4) << 4)
19582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
19583 (UINT32_C(0x5) << 4)
19584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
19585 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
19586 /* TQM ring 7 page size and level. */
19587 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
19588 /* TQM ring 7 PBL indirect levels. */
19589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
19591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
19592 /* PBL pointer is physical start address. */
19593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
19595 /* PBL pointer points to PTE table. */
19596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
19598 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
19601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
19602 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
19603 /* TQM ring 7 page size. */
19604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
19606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
19608 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
19609 (UINT32_C(0x0) << 4)
19611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
19612 (UINT32_C(0x1) << 4)
19614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
19615 (UINT32_C(0x2) << 4)
19617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
19618 (UINT32_C(0x3) << 4)
19620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
19621 (UINT32_C(0x4) << 4)
19623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
19624 (UINT32_C(0x5) << 4)
19625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
19626 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
19627 /* MR/AV page size and level. */
19628 uint8_t mrav_pg_size_mrav_lvl;
19629 /* MR/AV PBL indirect levels. */
19630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
19632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
19633 /* PBL pointer is physical start address. */
19634 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
19636 /* PBL pointer points to PTE table. */
19637 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
19639 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
19642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
19643 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
19644 /* MR/AV page size. */
19645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
19647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
19649 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
19650 (UINT32_C(0x0) << 4)
19652 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
19653 (UINT32_C(0x1) << 4)
19655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
19656 (UINT32_C(0x2) << 4)
19658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
19659 (UINT32_C(0x3) << 4)
19661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
19662 (UINT32_C(0x4) << 4)
19664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
19665 (UINT32_C(0x5) << 4)
19666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
19667 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
19668 /* Timer page size and level. */
19669 uint8_t tim_pg_size_tim_lvl;
19670 /* Timer PBL indirect levels. */
19671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
19673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
19674 /* PBL pointer is physical start address. */
19675 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
19677 /* PBL pointer points to PTE table. */
19678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
19680 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
19681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
19683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
19684 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
19685 /* Timer page size. */
19686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
19688 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
19690 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
19691 (UINT32_C(0x0) << 4)
19693 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
19694 (UINT32_C(0x1) << 4)
19696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
19697 (UINT32_C(0x2) << 4)
19699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
19700 (UINT32_C(0x3) << 4)
19702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
19703 (UINT32_C(0x4) << 4)
19705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
19706 (UINT32_C(0x5) << 4)
19707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
19708 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
19709 /* QP page directory. */
19710 uint64_t qpc_page_dir;
19711 /* SRQ page directory. */
19712 uint64_t srq_page_dir;
19713 /* CQ page directory. */
19714 uint64_t cq_page_dir;
19715 /* VNIC page directory. */
19716 uint64_t vnic_page_dir;
19717 /* Stat page directory. */
19718 uint64_t stat_page_dir;
19719 /* TQM slowpath page directory. */
19720 uint64_t tqm_sp_page_dir;
19721 /* TQM ring 0 page directory. */
19722 uint64_t tqm_ring0_page_dir;
19723 /* TQM ring 1 page directory. */
19724 uint64_t tqm_ring1_page_dir;
19725 /* TQM ring 2 page directory. */
19726 uint64_t tqm_ring2_page_dir;
19727 /* TQM ring 3 page directory. */
19728 uint64_t tqm_ring3_page_dir;
19729 /* TQM ring 4 page directory. */
19730 uint64_t tqm_ring4_page_dir;
19731 /* TQM ring 5 page directory. */
19732 uint64_t tqm_ring5_page_dir;
19733 /* TQM ring 6 page directory. */
19734 uint64_t tqm_ring6_page_dir;
19735 /* TQM ring 7 page directory. */
19736 uint64_t tqm_ring7_page_dir;
19737 /* MR/AV page directory. */
19738 uint64_t mrav_page_dir;
19739 /* Timer page directory. */
19740 uint64_t tim_page_dir;
19741 /* Number of entries to reserve for QP1 */
19742 uint16_t qp_num_qp1_entries;
19743 /* Number of entries to reserve for L2 */
19744 uint16_t qp_num_l2_entries;
19745 /* Number of QPs. */
19746 uint32_t qp_num_entries;
19747 /* Number of SRQs. */
19748 uint32_t srq_num_entries;
19749 /* Number of entries to reserve for L2 */
19750 uint16_t srq_num_l2_entries;
19751 /* Number of entries to reserve for L2 */
19752 uint16_t cq_num_l2_entries;
19753 /* Number of CQs. */
19754 uint32_t cq_num_entries;
19755 /* Number of entries to reserve for VNIC entries */
19756 uint16_t vnic_num_vnic_entries;
19757 /* Number of entries to reserve for Ring table entries */
19758 uint16_t vnic_num_ring_table_entries;
19759 /* Number of Stats. */
19760 uint32_t stat_num_entries;
19761 /* Number of TQM slowpath entries. */
19762 uint32_t tqm_sp_num_entries;
19763 /* Number of TQM ring 0 entries. */
19764 uint32_t tqm_ring0_num_entries;
19765 /* Number of TQM ring 1 entries. */
19766 uint32_t tqm_ring1_num_entries;
19767 /* Number of TQM ring 2 entries. */
19768 uint32_t tqm_ring2_num_entries;
19769 /* Number of TQM ring 3 entries. */
19770 uint32_t tqm_ring3_num_entries;
19771 /* Number of TQM ring 4 entries. */
19772 uint32_t tqm_ring4_num_entries;
19773 /* Number of TQM ring 5 entries. */
19774 uint32_t tqm_ring5_num_entries;
19775 /* Number of TQM ring 6 entries. */
19776 uint32_t tqm_ring6_num_entries;
19777 /* Number of TQM ring 7 entries. */
19778 uint32_t tqm_ring7_num_entries;
19780 * If the MR/AV split reservation flag is not set, then this field
19781 * represents the total number of MR plus AV entries. For versions
19782 * of firmware that support the split reservation, when it is not
19783 * specified half of the entries will be reserved for MRs and the
19784 * other half for AVs.
19786 * If the MR/AV split reservation flag is set, then this
19787 * field is logically divided into two 16b fields. Bits `[31:16]`
19788 * represents the `mr_num_entries` and bits `[15:0]` represents
19789 * `av_num_entries`. The granularity of these values is defined by
19790 * the `mrav_num_entries_unit` field returned by the
19791 * `backing_store_qcaps` command.
19793 uint32_t mrav_num_entries;
19794 /* Number of Timer entries. */
19795 uint32_t tim_num_entries;
19796 /* TQM ring page size and level. */
19797 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
19798 /* TQM ring PBL indirect levels. */
19799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
19801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
19803 /* PBL pointer is physical start address. */
19804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
19806 /* PBL pointer points to PTE table. */
19807 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
19810 * PBL pointer points to PDE table with each entry pointing to
19813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
19815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
19816 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
19817 /* TQM ring page size. */
19818 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
19820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
19823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
19824 (UINT32_C(0x0) << 4)
19826 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
19827 (UINT32_C(0x1) << 4)
19829 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
19830 (UINT32_C(0x2) << 4)
19832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
19833 (UINT32_C(0x3) << 4)
19835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
19836 (UINT32_C(0x4) << 4)
19838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
19839 (UINT32_C(0x5) << 4)
19840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
19841 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
19842 uint8_t ring8_unused[3];
19843 /* Number of TQM ring entries. */
19844 uint32_t tqm_ring8_num_entries;
19845 /* TQM ring page directory. */
19846 uint64_t tqm_ring8_page_dir;
19847 /* TQM ring page size and level. */
19848 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
19849 /* TQM ring PBL indirect levels. */
19850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
19852 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
19854 /* PBL pointer is physical start address. */
19855 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
19857 /* PBL pointer points to PTE table. */
19858 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
19861 * PBL pointer points to PDE table with each entry pointing to
19864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
19866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
19867 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
19868 /* TQM ring page size. */
19869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
19871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
19874 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
19875 (UINT32_C(0x0) << 4)
19877 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
19878 (UINT32_C(0x1) << 4)
19880 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
19881 (UINT32_C(0x2) << 4)
19883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
19884 (UINT32_C(0x3) << 4)
19886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
19887 (UINT32_C(0x4) << 4)
19889 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
19890 (UINT32_C(0x5) << 4)
19891 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
19892 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
19893 uint8_t ring9_unused[3];
19894 /* Number of TQM ring entries. */
19895 uint32_t tqm_ring9_num_entries;
19896 /* TQM ring page directory. */
19897 uint64_t tqm_ring9_page_dir;
19898 /* TQM ring page size and level. */
19899 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
19900 /* TQM ring PBL indirect levels. */
19901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
19903 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
19905 /* PBL pointer is physical start address. */
19906 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
19908 /* PBL pointer points to PTE table. */
19909 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
19912 * PBL pointer points to PDE table with each entry pointing to
19915 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
19917 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
19918 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
19919 /* TQM ring page size. */
19920 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
19922 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
19925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
19926 (UINT32_C(0x0) << 4)
19928 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
19929 (UINT32_C(0x1) << 4)
19931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
19932 (UINT32_C(0x2) << 4)
19934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
19935 (UINT32_C(0x3) << 4)
19937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
19938 (UINT32_C(0x4) << 4)
19940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
19941 (UINT32_C(0x5) << 4)
19942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
19943 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
19944 uint8_t ring10_unused[3];
19945 /* Number of TQM ring entries. */
19946 uint32_t tqm_ring10_num_entries;
19947 /* TQM ring page directory. */
19948 uint64_t tqm_ring10_page_dir;
19949 /* Number of Tx KTLS context entries. */
19950 uint32_t tkc_num_entries;
19951 /* Number of Rx KTLS context entries. */
19952 uint32_t rkc_num_entries;
19953 /* Tx KTLS context page directory. */
19954 uint64_t tkc_page_dir;
19955 /* Rx KTLS context page directory. */
19956 uint64_t rkc_page_dir;
19957 /* Tx KTLS context page size and level. */
19958 uint8_t tkc_pg_size_tkc_lvl;
19959 /* Tx KTLS context PBL indirect levels. */
19960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \
19962 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0
19963 /* PBL pointer is physical start address. */
19964 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \
19966 /* PBL pointer points to PTE table. */
19967 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \
19970 * PBL pointer points to PDE table with each entry pointing to
19973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \
19975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \
19976 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2
19977 /* Tx KTLS context page size. */
19978 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \
19980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4
19982 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \
19983 (UINT32_C(0x0) << 4)
19985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \
19986 (UINT32_C(0x1) << 4)
19988 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \
19989 (UINT32_C(0x2) << 4)
19991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \
19992 (UINT32_C(0x3) << 4)
19994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \
19995 (UINT32_C(0x4) << 4)
19997 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \
19998 (UINT32_C(0x5) << 4)
19999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \
20000 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G
20001 /* Rx KTLS context page size and level. */
20002 uint8_t rkc_pg_size_rkc_lvl;
20003 /* Rx KTLS context PBL indirect levels. */
20004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \
20006 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0
20007 /* PBL pointer is physical start address. */
20008 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \
20010 /* PBL pointer points to PTE table. */
20011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \
20014 * PBL pointer points to PDE table with each entry pointing to
20017 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \
20019 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \
20020 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2
20021 /* Rx KTLS context page size. */
20022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \
20024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4
20026 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \
20027 (UINT32_C(0x0) << 4)
20029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \
20030 (UINT32_C(0x1) << 4)
20032 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \
20033 (UINT32_C(0x2) << 4)
20035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \
20036 (UINT32_C(0x3) << 4)
20038 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \
20039 (UINT32_C(0x4) << 4)
20041 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \
20042 (UINT32_C(0x5) << 4)
20043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \
20044 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G
20045 uint8_t unused_1[5];
20047 * This field is used in Output records to indicate that the output
20048 * is completely written to RAM. This field should be read as 1
20049 * to indicate that the output has been completely written.
20050 * When writing a command completion or response to an internal
20051 * processor, the order of writes has to be such that this field
20057 /****************************
20058 * hwrm_error_recovery_qcfg *
20059 ****************************/
20062 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
20063 struct hwrm_error_recovery_qcfg_input {
20064 /* The HWRM command request type. */
20067 * The completion ring to send the completion event on. This should
20068 * be the NQ ID returned from the `nq_alloc` HWRM command.
20070 uint16_t cmpl_ring;
20072 * The sequence ID is used by the driver for tracking multiple
20073 * commands. This ID is treated as opaque data by the firmware and
20074 * the value is returned in the `hwrm_resp_hdr` upon completion.
20078 * The target ID of the command:
20079 * * 0x0-0xFFF8 - The function ID
20080 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20081 * * 0xFFFD - Reserved for user-space HWRM interface
20084 uint16_t target_id;
20086 * A physical address pointer pointing to a host buffer that the
20087 * command's response data will be written. This can be either a host
20088 * physical address (HPA) or a guest physical address (GPA) and must
20089 * point to a physically contiguous block of memory.
20091 uint64_t resp_addr;
20092 uint8_t unused_0[8];
20095 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
20096 struct hwrm_error_recovery_qcfg_output {
20097 /* The specific error status for the command. */
20098 uint16_t error_code;
20099 /* The HWRM command request type. */
20101 /* The sequence ID from the original command. */
20103 /* The length of the response data in number of bytes. */
20107 * When this flag is set to 1, error recovery will be initiated
20108 * through master function driver.
20110 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
20112 * When this flag is set to 1, error recovery will be performed
20113 * through Co processor.
20115 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
20117 * Driver Polling frequency. This value is in units of 100msec.
20118 * Typical value would be 10 to indicate 1sec.
20119 * Drivers can poll FW health status, Heartbeat, reset_counter with
20122 uint32_t driver_polling_freq;
20124 * This value is in units of 100msec.
20125 * Typical value would be 30 to indicate 3sec.
20126 * Master function wait period from detecting a fatal error to
20127 * initiating reset. In this time period Master PF expects every
20128 * active driver will detect fatal error.
20130 uint32_t master_func_wait_period;
20132 * This value is in units of 100msec.
20133 * Typical value would be 50 to indicate 5sec.
20134 * Normal function wait period from fatal error detection to
20135 * polling FW health status. In this time period, drivers should not
20136 * do any PCIe MMIO transaction and should not send any HWRM commands.
20138 uint32_t normal_func_wait_period;
20140 * This value is in units of 100msec.
20141 * Typical value would be 20 to indicate 2sec.
20142 * This field indicates that, master function wait period after chip
20143 * reset. After this time, master function should reinitialize with
20146 uint32_t master_func_wait_period_after_reset;
20148 * This value is in units of 100msec.
20149 * Typical value would be 60 to indicate 6sec.
20150 * This field is applicable to both master and normal functions.
20151 * Even after chip reset, if FW status not changed to ready,
20152 * then all the functions can poll for this much time and bailout.
20154 uint32_t max_bailout_time_after_reset;
20156 * FW health status register.
20157 * Lower 2 bits indicates address space location and upper 30 bits
20158 * indicates upper 30bits of the register address.
20159 * A value of 0xFFFF-FFFF indicates this register does not exist.
20161 uint32_t fw_health_status_reg;
20162 /* Lower 2 bits indicates address space location. */
20163 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
20165 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
20168 * If value is 0, this register is located in PCIe config space.
20169 * Drivers have to map appropriate window to access this
20172 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
20175 * If value is 1, this register is located in GRC address space.
20176 * Drivers have to map appropriate window to access this
20179 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
20182 * If value is 2, this register is located in first BAR address
20183 * space. Drivers have to map appropriate window to access this
20186 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
20189 * If value is 3, this register is located in second BAR address
20190 * space. Drivers have to map appropriate window to access this
20191 * Drivers have to map appropriate window to access this
20194 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
20196 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
20197 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
20198 /* Upper 30bits of the register address. */
20199 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
20200 UINT32_C(0xfffffffc)
20201 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
20204 * FW HeartBeat register.
20205 * Lower 2 bits indicates address space location and upper 30 bits
20206 * indicates actual address.
20207 * A value of 0xFFFF-FFFF indicates this register does not exist.
20209 uint32_t fw_heartbeat_reg;
20210 /* Lower 2 bits indicates address space location. */
20211 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
20213 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
20216 * If value is 0, this register is located in PCIe config space.
20217 * Drivers have to map appropriate window to access this
20220 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
20223 * If value is 1, this register is located in GRC address space.
20224 * Drivers have to map appropriate window to access this
20227 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
20230 * If value is 2, this register is located in first BAR address
20231 * space. Drivers have to map appropriate window to access this
20234 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
20237 * If value is 3, this register is located in second BAR address
20238 * space. Drivers have to map appropriate window to access this
20241 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
20243 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
20244 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
20245 /* Upper 30bits of the register address. */
20246 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
20247 UINT32_C(0xfffffffc)
20248 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
20251 * FW reset counter.
20252 * Lower 2 bits indicates address space location and upper 30 bits
20253 * indicates actual address.
20254 * A value of 0xFFFF-FFFF indicates this register does not exist.
20256 uint32_t fw_reset_cnt_reg;
20257 /* Lower 2 bits indicates address space location. */
20258 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
20260 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
20263 * If value is 0, this register is located in PCIe config space.
20264 * Drivers have to map appropriate window to access this
20267 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
20270 * If value is 1, this register is located in GRC address space.
20271 * Drivers have to map appropriate window to access this
20274 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
20277 * If value is 2, this register is located in first BAR address
20278 * space. Drivers have to map appropriate window to access this
20281 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
20284 * If value is 3, this register is located in second BAR address
20285 * space. Drivers have to map appropriate window to access this
20288 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
20290 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
20291 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
20292 /* Upper 30bits of the register address. */
20293 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
20294 UINT32_C(0xfffffffc)
20295 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
20298 * Reset Inprogress Register address for PFs.
20299 * Lower 2 bits indicates address space location and upper 30 bits
20300 * indicates actual address.
20301 * A value of 0xFFFF-FFFF indicates this register does not exist.
20303 uint32_t reset_inprogress_reg;
20304 /* Lower 2 bits indicates address space location. */
20305 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
20307 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
20310 * If value is 0, this register is located in PCIe config space.
20311 * Drivers have to map appropriate window to access this
20314 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
20317 * If value is 1, this register is located in GRC address space.
20318 * Drivers have to map appropriate window to access this
20321 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
20324 * If value is 2, this register is located in first BAR address
20325 * space. Drivers have to map appropriate window to access this
20328 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
20331 * If value is 3, this register is located in second BAR address
20332 * space. Drivers have to map appropriate window to access this
20335 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
20337 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
20338 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
20339 /* Upper 30bits of the register address. */
20340 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
20341 UINT32_C(0xfffffffc)
20342 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
20344 /* This field indicates the mask value for reset_inprogress_reg. */
20345 uint32_t reset_inprogress_reg_mask;
20346 uint8_t unused_0[3];
20348 * Array of registers and value count to reset the Chip
20349 * Each array count has reset_reg, reset_reg_val, delay_after_reset
20350 * in TLV format. Depending upon Chip type, number of reset registers
20351 * will vary. Drivers have to write reset_reg_val in the reset_reg
20352 * location in the same sequence in order to recover from a fatal
20355 uint8_t reg_array_cnt;
20358 * Lower 2 bits indicates address space location and upper 30 bits
20359 * indicates actual address.
20360 * A value of 0xFFFF-FFFF indicates this register does not exist.
20362 uint32_t reset_reg[16];
20363 /* Lower 2 bits indicates address space location. */
20364 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
20366 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
20368 * If value is 0, this register is located in PCIe config space.
20369 * Drivers have to map appropriate window to access this
20372 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
20375 * If value is 1, this register is located in GRC address space.
20376 * Drivers have to map appropriate window to access this
20379 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
20382 * If value is 2, this register is located in first BAR address
20383 * space. Drivers have to map appropriate window to access this
20386 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
20389 * If value is 3, this register is located in second BAR address
20390 * space. Drivers have to map appropriate window to access this
20393 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
20395 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
20396 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
20397 /* Upper 30bits of the register address. */
20398 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
20399 UINT32_C(0xfffffffc)
20400 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
20401 /* Value to be written in reset_reg to reset the controller. */
20402 uint32_t reset_reg_val[16];
20404 * This value is in units of 1msec.
20405 * Typical value would be 10 to indicate 10msec.
20406 * Some of the operations like Core reset require delay before
20407 * accessing PCIE MMIO register space.
20408 * If this value is non-zero, drivers have to wait for
20409 * this much time after writing reset_reg_val in reset_reg.
20411 uint8_t delay_after_reset[16];
20413 * Error recovery counter.
20414 * Lower 2 bits indicates address space location and upper 30 bits
20415 * indicates actual address.
20416 * A value of 0xFFFF-FFFF indicates this register does not exist.
20418 uint32_t err_recovery_cnt_reg;
20419 /* Lower 2 bits indicates address space location. */
20420 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
20422 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
20425 * If value is 0, this register is located in PCIe config space.
20426 * Drivers have to map appropriate window to access this
20429 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
20432 * If value is 1, this register is located in GRC address space.
20433 * Drivers have to map appropriate window to access this
20436 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
20439 * If value is 2, this register is located in first BAR address
20440 * space. Drivers have to map appropriate window to access this
20443 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
20446 * If value is 3, this register is located in second BAR address
20447 * space. Drivers have to map appropriate window to access this
20450 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
20452 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
20453 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
20454 /* Upper 30bits of the register address. */
20455 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
20456 UINT32_C(0xfffffffc)
20457 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
20459 uint8_t unused_1[3];
20461 * This field is used in Output records to indicate that the output
20462 * is completely written to RAM. This field should be read as '1'
20463 * to indicate that the output has been completely written.
20464 * When writing a command completion or response to an internal
20465 * processor, the order of writes has to be such that this field
20471 /***************************
20472 * hwrm_func_echo_response *
20473 ***************************/
20476 /* hwrm_func_echo_response_input (size:192b/24B) */
20477 struct hwrm_func_echo_response_input {
20478 /* The HWRM command request type. */
20481 * The completion ring to send the completion event on. This should
20482 * be the NQ ID returned from the `nq_alloc` HWRM command.
20484 uint16_t cmpl_ring;
20486 * The sequence ID is used by the driver for tracking multiple
20487 * commands. This ID is treated as opaque data by the firmware and
20488 * the value is returned in the `hwrm_resp_hdr` upon completion.
20492 * The target ID of the command:
20493 * * 0x0-0xFFF8 - The function ID
20494 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20495 * * 0xFFFD - Reserved for user-space HWRM interface
20498 uint16_t target_id;
20500 * A physical address pointer pointing to a host buffer that the
20501 * command's response data will be written. This can be either a host
20502 * physical address (HPA) or a guest physical address (GPA) and must
20503 * point to a physically contiguous block of memory.
20505 uint64_t resp_addr;
20506 uint32_t event_data1;
20507 uint32_t event_data2;
20510 /* hwrm_func_echo_response_output (size:128b/16B) */
20511 struct hwrm_func_echo_response_output {
20512 /* The specific error status for the command. */
20513 uint16_t error_code;
20514 /* The HWRM command request type. */
20516 /* The sequence ID from the original command. */
20518 /* The length of the response data in number of bytes. */
20520 uint8_t unused_0[7];
20522 * This field is used in Output records to indicate that the output
20523 * is completely written to RAM. This field should be read as '1'
20524 * to indicate that the output has been completely written.
20525 * When writing a command completion or response to an internal processor,
20526 * the order of writes has to be such that this field is written last.
20531 /**************************
20532 * hwrm_func_ptp_pin_qcfg *
20533 **************************/
20536 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
20537 struct hwrm_func_ptp_pin_qcfg_input {
20538 /* The HWRM command request type. */
20541 * The completion ring to send the completion event on. This should
20542 * be the NQ ID returned from the `nq_alloc` HWRM command.
20544 uint16_t cmpl_ring;
20546 * The sequence ID is used by the driver for tracking multiple
20547 * commands. This ID is treated as opaque data by the firmware and
20548 * the value is returned in the `hwrm_resp_hdr` upon completion.
20552 * The target ID of the command:
20553 * * 0x0-0xFFF8 - The function ID
20554 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20555 * * 0xFFFD - Reserved for user-space HWRM interface
20558 uint16_t target_id;
20560 * A physical address pointer pointing to a host buffer that the
20561 * command's response data will be written. This can be either a host
20562 * physical address (HPA) or a guest physical address (GPA) and must
20563 * point to a physically contiguous block of memory.
20565 uint64_t resp_addr;
20566 uint8_t unused_0[8];
20569 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
20570 struct hwrm_func_ptp_pin_qcfg_output {
20571 /* The specific error status for the command. */
20572 uint16_t error_code;
20573 /* The HWRM command request type. */
20575 /* The sequence ID from the original command. */
20577 /* The length of the response data in number of bytes. */
20580 * The number of TSIO pins that are configured on this board
20581 * Up to 4 pins can be returned in the response.
20587 * When this bit is '1', TSIO pin 0 is enabled.
20588 * When this bit is '0', TSIO pin 0 is disabled.
20590 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \
20593 * When this bit is '1', TSIO pin 1 is enabled.
20594 * When this bit is '0', TSIO pin 1 is disabled.
20596 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \
20599 * When this bit is '1', TSIO pin 2 is enabled.
20600 * When this bit is '0', TSIO pin 2 is disabled.
20602 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \
20605 * When this bit is '1', TSIO pin 3 is enabled.
20606 * When this bit is '0', TSIO pin 3 is disabled.
20608 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \
20610 /* Type of function for Pin #0. */
20611 uint8_t pin0_usage;
20612 /* No function is configured. */
20613 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
20614 /* PPS IN is configured. */
20615 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
20616 /* PPS OUT is configured. */
20617 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
20618 /* SYNC IN is configured. */
20619 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
20620 /* SYNC OUT is configured. */
20621 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
20622 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \
20623 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT
20624 /* Type of function for Pin #1. */
20625 uint8_t pin1_usage;
20626 /* No function is configured. */
20627 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
20628 /* PPS IN is configured. */
20629 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
20630 /* PPS OUT is configured. */
20631 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
20632 /* SYNC IN is configured. */
20633 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
20634 /* SYNC OUT is configured. */
20635 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
20636 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \
20637 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT
20638 /* Type of function for Pin #2. */
20639 uint8_t pin2_usage;
20640 /* No function is configured. */
20641 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
20642 /* PPS IN is configured. */
20643 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
20644 /* PPS OUT is configured. */
20645 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
20646 /* SYNC IN is configured. */
20647 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
20648 /* SYNC OUT is configured. */
20649 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
20650 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
20651 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
20652 /* Type of function for Pin #3. */
20653 uint8_t pin3_usage;
20654 /* No function is configured. */
20655 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
20656 /* PPS IN is configured. */
20657 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
20658 /* PPS OUT is configured. */
20659 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
20660 /* SYNC IN is configured. */
20661 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
20662 /* SYNC OUT is configured. */
20663 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
20664 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
20665 HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
20668 * This field is used in Output records to indicate that the output
20669 * is completely written to RAM. This field should be read as '1'
20670 * to indicate that the output has been completely written.
20671 * When writing a command completion or response to an internal processor,
20672 * the order of writes has to be such that this field is written last.
20677 /*************************
20678 * hwrm_func_ptp_pin_cfg *
20679 *************************/
20682 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
20683 struct hwrm_func_ptp_pin_cfg_input {
20684 /* The HWRM command request type. */
20687 * The completion ring to send the completion event on. This should
20688 * be the NQ ID returned from the `nq_alloc` HWRM command.
20690 uint16_t cmpl_ring;
20692 * The sequence ID is used by the driver for tracking multiple
20693 * commands. This ID is treated as opaque data by the firmware and
20694 * the value is returned in the `hwrm_resp_hdr` upon completion.
20698 * The target ID of the command:
20699 * * 0x0-0xFFF8 - The function ID
20700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20701 * * 0xFFFD - Reserved for user-space HWRM interface
20704 uint16_t target_id;
20706 * A physical address pointer pointing to a host buffer that the
20707 * command's response data will be written. This can be either a host
20708 * physical address (HPA) or a guest physical address (GPA) and must
20709 * point to a physically contiguous block of memory.
20711 uint64_t resp_addr;
20714 * This bit must be '1' for the pin0_state field to be
20717 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \
20720 * This bit must be '1' for the pin0_usage field to be
20723 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \
20726 * This bit must be '1' for the pin1_state field to be
20729 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \
20732 * This bit must be '1' for the pin1_usage field to be
20735 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \
20738 * This bit must be '1' for the pin2_state field to be
20741 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \
20744 * This bit must be '1' for the pin2_usage field to be
20747 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \
20750 * This bit must be '1' for the pin3_state field to be
20753 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \
20756 * This bit must be '1' for the pin3_usage field to be
20759 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \
20761 /* Enable or disable functionality of Pin #0. */
20762 uint8_t pin0_state;
20764 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
20766 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
20767 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \
20768 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED
20769 /* Configure function for TSIO pin#0. */
20770 uint8_t pin0_usage;
20771 /* No function is configured. */
20772 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
20773 /* PPS IN is configured. */
20774 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
20775 /* PPS OUT is configured. */
20776 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
20777 /* SYNC IN is configured. */
20778 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
20779 /* SYNC OUT is configured. */
20780 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
20781 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \
20782 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT
20783 /* Enable or disable functionality of Pin #1. */
20784 uint8_t pin1_state;
20786 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
20788 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
20789 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \
20790 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED
20791 /* Configure function for TSIO pin#1. */
20792 uint8_t pin1_usage;
20793 /* No function is configured. */
20794 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
20795 /* PPS IN is configured. */
20796 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
20797 /* PPS OUT is configured. */
20798 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
20799 /* SYNC IN is configured. */
20800 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
20801 /* SYNC OUT is configured. */
20802 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
20803 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \
20804 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT
20805 /* Enable or disable functionality of Pin #2. */
20806 uint8_t pin2_state;
20808 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
20810 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
20811 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \
20812 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED
20813 /* Configure function for TSIO pin#2. */
20814 uint8_t pin2_usage;
20815 /* No function is configured. */
20816 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
20817 /* PPS IN is configured. */
20818 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
20819 /* PPS OUT is configured. */
20820 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
20821 /* SYNC IN is configured. */
20822 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
20823 /* SYNC OUT is configured. */
20824 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
20825 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
20826 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
20827 /* Enable or disable functionality of Pin #3. */
20828 uint8_t pin3_state;
20830 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
20832 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
20833 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \
20834 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED
20835 /* Configure function for TSIO pin#3. */
20836 uint8_t pin3_usage;
20837 /* No function is configured. */
20838 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
20839 /* PPS IN is configured. */
20840 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
20841 /* PPS OUT is configured. */
20842 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
20843 /* SYNC IN is configured. */
20844 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
20845 /* SYNC OUT is configured. */
20846 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
20847 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
20848 HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
20849 uint8_t unused_0[4];
20852 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
20853 struct hwrm_func_ptp_pin_cfg_output {
20854 /* The specific error status for the command. */
20855 uint16_t error_code;
20856 /* The HWRM command request type. */
20858 /* The sequence ID from the original command. */
20860 /* The length of the response data in number of bytes. */
20862 uint8_t unused_0[7];
20864 * This field is used in Output records to indicate that the output
20865 * is completely written to RAM. This field should be read as '1'
20866 * to indicate that the output has been completely written.
20867 * When writing a command completion or response to an internal processor,
20868 * the order of writes has to be such that this field is written last.
20873 /*********************
20874 * hwrm_func_ptp_cfg *
20875 *********************/
20878 /* hwrm_func_ptp_cfg_input (size:384b/48B) */
20879 struct hwrm_func_ptp_cfg_input {
20880 /* The HWRM command request type. */
20883 * The completion ring to send the completion event on. This should
20884 * be the NQ ID returned from the `nq_alloc` HWRM command.
20886 uint16_t cmpl_ring;
20888 * The sequence ID is used by the driver for tracking multiple
20889 * commands. This ID is treated as opaque data by the firmware and
20890 * the value is returned in the `hwrm_resp_hdr` upon completion.
20894 * The target ID of the command:
20895 * * 0x0-0xFFF8 - The function ID
20896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20897 * * 0xFFFD - Reserved for user-space HWRM interface
20900 uint16_t target_id;
20902 * A physical address pointer pointing to a host buffer that the
20903 * command's response data will be written. This can be either a host
20904 * physical address (HPA) or a guest physical address (GPA) and must
20905 * point to a physically contiguous block of memory.
20907 uint64_t resp_addr;
20910 * This bit must be '1' for the ptp_pps_event field to be
20913 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \
20916 * This bit must be '1' for the ptp_freq_adj_dll_source field to be
20919 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \
20922 * This bit must be '1' for the ptp_freq_adj_dll_phase field to be
20925 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \
20928 * This bit must be '1' for the ptp_freq_adj_ext_period field to be
20931 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \
20934 * This bit must be '1' for the ptp_freq_adj_ext_up field to be
20937 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \
20940 * This bit must be '1' for the ptp_freq_adj_ext_phase field to be
20943 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \
20945 /* This bit must be '1' for ptp_set_time field to be configured. */
20946 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME \
20948 /* This field is used to enable interrupt for a specific PPS event. */
20949 uint8_t ptp_pps_event;
20951 * When this bit is set to '1', interrupt is enabled for internal
20952 * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does
20953 * not configure PPS_OUT on a TSIO pin, then firmware will allocate
20954 * PPS_OUT to an unallocated pin.
20956 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \
20959 * When this bit is set to '1', interrupt is enabled for external
20960 * PPS event. Latches timestamp on PPS_IN TSIO pin.
20962 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \
20965 * This field is used to set the source signal used to discipline
20966 * PHC (PTP Hardware Clock)
20968 uint8_t ptp_freq_adj_dll_source;
20969 /* No source is selected. Use servo to discipline PHC */
20970 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \
20972 /* TSIO Pin #0 is selected as source signal. */
20973 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \
20975 /* TSIO Pin #1 is selected as source signal. */
20976 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \
20978 /* TSIO Pin #2 is selected as source signal. */
20979 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \
20981 /* TSIO Pin #3 is selected as source signal. */
20982 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \
20984 /* Port #0 is selected as source signal. */
20985 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \
20987 /* Port #1 is selected as source signal. */
20988 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \
20990 /* Port #2 is selected as source signal. */
20991 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \
20993 /* Port #3 is selected as source signal. */
20994 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \
20996 /* Invalid signal. */
20997 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \
20999 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \
21000 HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
21002 * This field is used to provide phase adjustment for DLL
21003 * used to discipline PHC (PTP Hardware clock)
21005 uint8_t ptp_freq_adj_dll_phase;
21006 /* No Phase adjustment. */
21007 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \
21009 /* 4Khz sync in frequency. */
21010 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \
21012 /* 8Khz sync in frequency. */
21013 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \
21015 /* 10Mhz sync in frequency. */
21016 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \
21018 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \
21019 HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M
21020 uint8_t unused_0[3];
21022 * Period in nanoseconds (ns) for external signal
21025 uint32_t ptp_freq_adj_ext_period;
21027 * Up time in nanoseconds (ns) of the duty cycle
21028 * of the external signal. This value should be
21029 * less than ptp_freq_adj_ext_period.
21031 uint32_t ptp_freq_adj_ext_up;
21033 * Phase value is provided. This field provides the
21034 * least significant 32 bits of the phase input. The
21035 * most significant 16 bits come from
21036 * ptp_freq_adj_ext_phase_upper field. Setting this
21037 * field requires setting ptp_freq_adj_ext_period
21038 * field as well to identify the external signal
21041 uint32_t ptp_freq_adj_ext_phase_lower;
21043 * Phase value is provided. The lower 16 bits of this field is used
21044 * with the 32 bit value from ptp_freq_adj_ext_phase_lower
21045 * to provide a 48 bit value input for Phase.
21047 uint32_t ptp_freq_adj_ext_phase_upper;
21049 * Allows driver to set the full 64bit time in FW. The upper 16 bits
21050 * will be stored in FW and the lower 48bits will be programmed in
21051 * PHC. Firmware will send a broadcast async event to all functions
21052 * to indicate the programmed upper 16 bits.
21054 uint64_t ptp_set_time;
21057 /* hwrm_func_ptp_cfg_output (size:128b/16B) */
21058 struct hwrm_func_ptp_cfg_output {
21059 /* The specific error status for the command. */
21060 uint16_t error_code;
21061 /* The HWRM command request type. */
21063 /* The sequence ID from the original command. */
21065 /* The length of the response data in number of bytes. */
21067 uint8_t unused_0[7];
21069 * This field is used in Output records to indicate that the output
21070 * is completely written to RAM. This field should be read as '1'
21071 * to indicate that the output has been completely written.
21072 * When writing a command completion or response to an internal processor,
21073 * the order of writes has to be such that this field is written last.
21078 /**************************
21079 * hwrm_func_ptp_ts_query *
21080 **************************/
21083 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */
21084 struct hwrm_func_ptp_ts_query_input {
21085 /* The HWRM command request type. */
21088 * The completion ring to send the completion event on. This should
21089 * be the NQ ID returned from the `nq_alloc` HWRM command.
21091 uint16_t cmpl_ring;
21093 * The sequence ID is used by the driver for tracking multiple
21094 * commands. This ID is treated as opaque data by the firmware and
21095 * the value is returned in the `hwrm_resp_hdr` upon completion.
21099 * The target ID of the command:
21100 * * 0x0-0xFFF8 - The function ID
21101 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21102 * * 0xFFFD - Reserved for user-space HWRM interface
21105 uint16_t target_id;
21107 * A physical address pointer pointing to a host buffer that the
21108 * command's response data will be written. This can be either a host
21109 * physical address (HPA) or a guest physical address (GPA) and must
21110 * point to a physically contiguous block of memory.
21112 uint64_t resp_addr;
21114 /* If set, the response includes PPS event timestamps */
21115 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
21116 /* If set, the response includes PTM timestamps */
21117 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
21118 uint8_t unused_0[4];
21121 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */
21122 struct hwrm_func_ptp_ts_query_output {
21123 /* The specific error status for the command. */
21124 uint16_t error_code;
21125 /* The HWRM command request type. */
21127 /* The sequence ID from the original command. */
21129 /* The length of the response data in number of bytes. */
21131 /* Timestamp value of last PPS event latched. */
21132 uint64_t pps_event_ts;
21133 /* PTM local timestamp value. */
21134 uint64_t ptm_res_local_ts;
21135 /* PTM Master timestamp value. */
21136 uint64_t ptm_pmstr_ts;
21137 /* PTM Master propagation delay */
21138 uint32_t ptm_mstr_prop_dly;
21139 uint8_t unused_0[3];
21141 * This field is used in Output records to indicate that the output
21142 * is completely written to RAM. This field should be read as '1'
21143 * to indicate that the output has been completely written.
21144 * When writing a command completion or response to an internal processor,
21145 * the order of writes has to be such that this field is written last.
21150 /*************************
21151 * hwrm_func_ptp_ext_cfg *
21152 *************************/
21155 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
21156 struct hwrm_func_ptp_ext_cfg_input {
21157 /* The HWRM command request type. */
21160 * The completion ring to send the completion event on. This should
21161 * be the NQ ID returned from the `nq_alloc` HWRM command.
21163 uint16_t cmpl_ring;
21165 * The sequence ID is used by the driver for tracking multiple
21166 * commands. This ID is treated as opaque data by the firmware and
21167 * the value is returned in the `hwrm_resp_hdr` upon completion.
21171 * The target ID of the command:
21172 * * 0x0-0xFFF8 - The function ID
21173 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21174 * * 0xFFFD - Reserved for user-space HWRM interface
21177 uint16_t target_id;
21179 * A physical address pointer pointing to a host buffer that the
21180 * command's response data will be written. This can be either a host
21181 * physical address (HPA) or a guest physical address (GPA) and must
21182 * point to a physically contiguous block of memory.
21184 uint64_t resp_addr;
21187 * This bit must be '1' for the phc_master_fid field to be
21190 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \
21193 * This bit must be '1' for the phc_sec_fid field to be
21196 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \
21199 * This bit must be '1' for the phc_sec_mode field to be
21202 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \
21205 * This bit must be '1' for the failover_timer field to be
21208 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \
21211 * This field is used to configure the Master function. Only this
21212 * function can modify or condition the PHC. Only driver calls from
21213 * this function are allowed to adjust frequency of PHC or configure
21214 * PPS functionality.
21215 * If driver does not specify this FID, then firmware will auto select
21216 * the first function that makes the call to modify PHC as the Master.
21218 uint16_t phc_master_fid;
21220 * This field is used to configure the secondary function. This
21221 * function becomes the Master function in case of failover from
21223 * If driver does not specify this FID, firmware will auto select
21224 * the last non-master function to make a call to condition PHC as
21227 uint16_t phc_sec_fid;
21229 * This field is used to configure conditions under which a function
21230 * can become a secondary function.
21232 uint8_t phc_sec_mode;
21234 * Immediately failover to the current secondary function. If there
21235 * is no secondary function available, failover does not happen.
21237 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
21239 * All functions (PF and VF) can be used during auto selection
21240 * of a secondary function. This is not used in case of admin
21241 * configured secondary function.
21243 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
21245 * Only PF's can be selected as a secondary function during auto
21246 * selection. This is not used in case of admin configured secondary
21249 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
21250 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \
21251 HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY
21254 * This field indicates the failover time is milliseconds. If the
21255 * timeout expires, firmware will failover PTP configurability from
21256 * current master to secondary fid.
21257 * 0 - Failover timer is automatically selected based on the last
21258 * adjFreq() call. If adjFreq() is not called for 3 * (last interval)
21259 * the failover kicks in. For example, if last interval between
21260 * adjFreq() calls was 2 seconds and the next adjFreq() is not made for
21261 * at least 6 seconds, then secondary takes over as master to condition
21262 * PHC. Firmware rounds up the failover timer to be a multiple of 250
21263 * ms. Firmware checks every 250 ms to see if timer expired.
21264 * 0xFFFFFFFF - If driver specifies this value, then failover never
21265 * happens. Admin or auto selected Master will always be used for
21266 * conditioning PHC.
21267 * X - If driver specifies any other value, this is admin indicated
21268 * failover timeout. If no adjFreq() call is made within this timeout
21269 * value, then failover happens. This value should be a multiple of
21270 * 250 ms. Firmware checks every 250 ms to see if timer expired.
21272 uint32_t failover_timer;
21273 uint8_t unused_1[4];
21276 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
21277 struct hwrm_func_ptp_ext_cfg_output {
21278 /* The specific error status for the command. */
21279 uint16_t error_code;
21280 /* The HWRM command request type. */
21282 /* The sequence ID from the original command. */
21284 /* The length of the response data in number of bytes. */
21286 uint8_t unused_0[7];
21288 * This field is used in Output records to indicate that the output
21289 * is completely written to RAM. This field should be read as '1'
21290 * to indicate that the output has been completely written.
21291 * When writing a command completion or response to an internal processor,
21292 * the order of writes has to be such that this field is written last.
21297 /**************************
21298 * hwrm_func_ptp_ext_qcfg *
21299 **************************/
21302 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
21303 struct hwrm_func_ptp_ext_qcfg_input {
21304 /* The HWRM command request type. */
21307 * The completion ring to send the completion event on. This should
21308 * be the NQ ID returned from the `nq_alloc` HWRM command.
21310 uint16_t cmpl_ring;
21312 * The sequence ID is used by the driver for tracking multiple
21313 * commands. This ID is treated as opaque data by the firmware and
21314 * the value is returned in the `hwrm_resp_hdr` upon completion.
21318 * The target ID of the command:
21319 * * 0x0-0xFFF8 - The function ID
21320 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21321 * * 0xFFFD - Reserved for user-space HWRM interface
21324 uint16_t target_id;
21326 * A physical address pointer pointing to a host buffer that the
21327 * command's response data will be written. This can be either a host
21328 * physical address (HPA) or a guest physical address (GPA) and must
21329 * point to a physically contiguous block of memory.
21331 uint64_t resp_addr;
21332 uint8_t unused_0[8];
21335 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
21336 struct hwrm_func_ptp_ext_qcfg_output {
21337 /* The specific error status for the command. */
21338 uint16_t error_code;
21339 /* The HWRM command request type. */
21341 /* The sequence ID from the original command. */
21343 /* The length of the response data in number of bytes. */
21346 * Firmware returns the current PHC master function. This function
21347 * could either be admin selected or auto selected.
21349 uint16_t phc_master_fid;
21351 * Firmware returns the current PHC secondary function. This function
21352 * could either be admin selected or auto selected.
21354 uint16_t phc_sec_fid;
21356 * Firmware returns the last non-master/non-secondary function to
21357 * make a call to condition PHC.
21359 uint16_t phc_active_fid0;
21361 * Firmware returns the second last non-master/non-secondary function
21362 * to make a call to condition PHC.
21364 uint16_t phc_active_fid1;
21366 * Timestamp indicating the last time a failover happened. The master
21367 * and secondary functions in the failover event is indicated in the
21370 uint32_t last_failover_event;
21372 * Last failover happened from this function. This was the master
21373 * function at the time of failover.
21377 * Last failover happened to this function. This was the secondary
21378 * function at the time of failover.
21381 uint8_t unused_0[7];
21383 * This field is used in Output records to indicate that the output
21384 * is completely written to RAM. This field should be read as '1'
21385 * to indicate that the output has been completely written.
21386 * When writing a command completion or response to an internal processor,
21387 * the order of writes has to be such that this field is written last.
21392 /***************************
21393 * hwrm_func_key_ctx_alloc *
21394 ***************************/
21397 /* hwrm_func_key_ctx_alloc_input (size:320b/40B) */
21398 struct hwrm_func_key_ctx_alloc_input {
21399 /* The HWRM command request type. */
21402 * The completion ring to send the completion event on. This should
21403 * be the NQ ID returned from the `nq_alloc` HWRM command.
21405 uint16_t cmpl_ring;
21407 * The sequence ID is used by the driver for tracking multiple
21408 * commands. This ID is treated as opaque data by the firmware and
21409 * the value is returned in the `hwrm_resp_hdr` upon completion.
21413 * The target ID of the command:
21414 * * 0x0-0xFFF8 - The function ID
21415 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21416 * * 0xFFFD - Reserved for user-space HWRM interface
21419 uint16_t target_id;
21421 * A physical address pointer pointing to a host buffer that the
21422 * command's response data will be written. This can be either a host
21423 * physical address (HPA) or a guest physical address (GPA) and must
21424 * point to a physically contiguous block of memory.
21426 uint64_t resp_addr;
21429 /* Number of Key Contexts to be allocated. */
21430 uint16_t num_key_ctxs;
21431 /* DMA buffer size in bytes. */
21432 uint32_t dma_bufr_size_bytes;
21433 /* Key Context type. */
21434 uint8_t key_ctx_type;
21435 /* KTLS Tx Key Context type. */
21436 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX \
21438 /* KTLS Rx Key Context type. */
21439 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX \
21441 /* QUIC Tx Key Context type. */
21442 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX \
21444 /* QUIC Rx Key Context type. */
21445 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX \
21447 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \
21448 HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX
21449 uint8_t unused_0[7];
21450 /* Host DMA address to send back KTLS context IDs. */
21451 uint64_t host_dma_addr;
21454 /* hwrm_func_key_ctx_alloc_output (size:128b/16B) */
21455 struct hwrm_func_key_ctx_alloc_output {
21456 /* The specific error status for the command. */
21457 uint16_t error_code;
21458 /* The HWRM command request type. */
21460 /* The sequence ID from the original command. */
21462 /* The length of the response data in number of bytes. */
21464 /* Actual number of Key Contexts allocated. */
21465 uint16_t num_key_ctxs_allocated;
21466 uint8_t unused_0[5];
21468 * This field is used in Output records to indicate that the output
21469 * is completely written to RAM. This field should be read as '1'
21470 * to indicate that the output has been completely written.
21471 * When writing a command completion or response to an internal processor,
21472 * the order of writes has to be such that this field is written last.
21477 /**********************************
21478 * hwrm_func_backing_store_cfg_v2 *
21479 **********************************/
21482 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
21483 struct hwrm_func_backing_store_cfg_v2_input {
21484 /* The HWRM command request type. */
21487 * The completion ring to send the completion event on. This should
21488 * be the NQ ID returned from the `nq_alloc` HWRM command.
21490 uint16_t cmpl_ring;
21492 * The sequence ID is used by the driver for tracking multiple
21493 * commands. This ID is treated as opaque data by the firmware and
21494 * the value is returned in the `hwrm_resp_hdr` upon completion.
21498 * The target ID of the command:
21499 * * 0x0-0xFFF8 - The function ID
21500 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21501 * * 0xFFFD - Reserved for user-space HWRM interface
21504 uint16_t target_id;
21506 * A physical address pointer pointing to a host buffer that the
21507 * command's response data will be written. This can be either a host
21508 * physical address (HPA) or a guest physical address (GPA) and must
21509 * point to a physically contiguous block of memory.
21511 uint64_t resp_addr;
21512 /* Type of backing store to be configured. */
21515 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \
21517 /* Shared receive queue. */
21518 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \
21520 /* Completion queue. */
21521 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \
21524 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \
21526 /* Statistic context. */
21527 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \
21529 /* Slow-path TQM ring. */
21530 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \
21532 /* Fast-path TQM ring. */
21533 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \
21535 /* Memory Region and Memory Address Vector Context. */
21536 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \
21539 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \
21541 /* Tx key context. */
21542 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \
21544 /* Rx key context. */
21545 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \
21547 /* Mid-path TQM ring. */
21548 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \
21550 /* SQ Doorbell shadow region. */
21551 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW \
21553 /* RQ Doorbell shadow region. */
21554 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW \
21556 /* SRQ Doorbell shadow region. */
21557 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \
21559 /* CQ Doorbell shadow region. */
21560 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW \
21562 /* QUIC Tx key context. */
21563 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC \
21565 /* QUIC Rx key context. */
21566 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC \
21568 /* Invalid type. */
21569 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID \
21571 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \
21572 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID
21574 * Instance of the backing store type. It is zero-based,
21575 * which means "0" indicates the first instance. For backing
21576 * stores with single instance only, leave this field to 0.
21579 /* Control flags. */
21582 * When set, the firmware only uses on-chip resources and
21583 * does not expect any backing store to be provided by the
21584 * host driver. This mode provides minimal L2 functionality
21585 * (e.g. limited L2 resources, no RoCE).
21587 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \
21589 /* Page directory. */
21591 /* Number of entries */
21592 uint32_t num_entries;
21593 /* Number of bytes allocated for each entry */
21594 uint16_t entry_size;
21595 /* Page size and pbl level. */
21596 uint8_t page_size_pbl_level;
21597 /* PBL indirect levels. */
21598 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \
21600 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0
21601 /* PBL pointer is physical start address. */
21602 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \
21604 /* PBL pointer points to PTE table. */
21605 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \
21608 * PBL pointer points to PDE table with each entry pointing to
21611 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \
21613 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \
21614 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2
21616 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \
21618 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4
21620 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \
21621 (UINT32_C(0x0) << 4)
21623 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \
21624 (UINT32_C(0x1) << 4)
21626 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \
21627 (UINT32_C(0x2) << 4)
21629 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \
21630 (UINT32_C(0x3) << 4)
21632 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \
21633 (UINT32_C(0x4) << 4)
21635 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \
21636 (UINT32_C(0x5) << 4)
21637 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \
21638 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G
21640 * This field counts how many split entries contain valid data.
21641 * Below is the table that maps the count value:
21642 * | Count | Indication |
21643 * | ----- | -------------------------------------------------- |
21644 * | 0 | None of the split entries has valid data. |
21645 * | 1 | Only "split_entry_0" contains valid data. |
21646 * | 2 | Only "split_entry_0" and "1" have valid data. |
21647 * | 3 | Only "split_entry_0", "1" and "2" have valid data. |
21648 * | 4 | All four split entries have valid data. |
21650 uint8_t subtype_valid_cnt;
21652 * Split entry #0. Note that the four split entries (as a group)
21653 * must be cast to a type-specific data structure first before
21654 * accessing it! Below is the table that maps a backing store
21655 * type to the associated split entry casting data structure.
21656 * | Type | Split Entry Casting Data Structure |
21657 * | ---- | -------------------------------------------------- |
21658 * | QPC | qpc_split_entries |
21659 * | SRQ | srq_split_entries |
21660 * | CQ | cq_split_entries |
21661 * | VINC | vnic_split_entries |
21662 * | MRAV | marv_split_entries |
21664 uint32_t split_entry_0;
21665 /* Split entry #1. */
21666 uint32_t split_entry_1;
21667 /* Split entry #2. */
21668 uint32_t split_entry_2;
21669 /* Split entry #3. */
21670 uint32_t split_entry_3;
21673 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
21674 struct hwrm_func_backing_store_cfg_v2_output {
21675 /* The specific error status for the command. */
21676 uint16_t error_code;
21677 /* The HWRM command request type. */
21679 /* The sequence ID from the original command. */
21681 /* The length of the response data in number of bytes. */
21685 * This field is used in Output records to indicate that the
21686 * output is completely written to RAM. This field should be
21687 * read as '1' to indicate that the output has been completely
21688 * written. When writing a command completion or response to
21689 * an internal processor, the order of writes has to be such
21690 * that this field is written last.
21695 /***********************************
21696 * hwrm_func_backing_store_qcfg_v2 *
21697 ***********************************/
21700 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
21701 struct hwrm_func_backing_store_qcfg_v2_input {
21702 /* The HWRM command request type. */
21705 * The completion ring to send the completion event on. This should
21706 * be the NQ ID returned from the `nq_alloc` HWRM command.
21708 uint16_t cmpl_ring;
21710 * The sequence ID is used by the driver for tracking multiple
21711 * commands. This ID is treated as opaque data by the firmware and
21712 * the value is returned in the `hwrm_resp_hdr` upon completion.
21716 * The target ID of the command:
21717 * * 0x0-0xFFF8 - The function ID
21718 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21719 * * 0xFFFD - Reserved for user-space HWRM interface
21722 uint16_t target_id;
21724 * A physical address pointer pointing to a host buffer that the
21725 * command's response data will be written. This can be either a host
21726 * physical address (HPA) or a guest physical address (GPA) and must
21727 * point to a physically contiguous block of memory.
21729 uint64_t resp_addr;
21730 /* Type of backing store to be configured. */
21733 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \
21735 /* Shared receive queue. */
21736 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \
21738 /* Completion queue. */
21739 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \
21742 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \
21744 /* Statistic context. */
21745 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \
21747 /* Slow-path TQM ring. */
21748 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \
21750 /* Fast-path TQM ring. */
21751 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \
21753 /* Memory Region and Memory Address Vector Context. */
21754 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \
21757 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \
21759 /* Tx key context. */
21760 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \
21762 /* Rx key context. */
21763 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \
21765 /* Mid-path TQM ring. */
21766 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \
21768 /* SQ Doorbell shadow region. */
21769 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW \
21771 /* RQ Doorbell shadow region. */
21772 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW \
21774 /* SRQ Doorbell shadow region. */
21775 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \
21777 /* CQ Doorbell shadow region. */
21778 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW \
21780 /* QUIC Tx key context. */
21781 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC \
21783 /* QUIC Rx key context. */
21784 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC \
21786 /* Invalid type. */
21787 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID \
21789 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \
21790 HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID
21792 * Instance of the backing store type. It is zero-based,
21793 * which means "0" indicates the first instance. For backing
21794 * stores with single instance only, leave this field to 0.
21800 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
21801 struct hwrm_func_backing_store_qcfg_v2_output {
21802 /* The specific error status for the command. */
21803 uint16_t error_code;
21804 /* The HWRM command request type. */
21806 /* The sequence ID from the original command. */
21808 /* The length of the response data in number of bytes. */
21810 /* Type of backing store to be configured. */
21813 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \
21815 /* Shared receive queue. */
21816 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \
21818 /* Completion queue. */
21819 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \
21822 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \
21824 /* Statistic context. */
21825 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \
21827 /* Slow-path TQM ring. */
21828 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \
21830 /* Fast-path TQM ring. */
21831 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \
21833 /* Memory Region and Memory Address Vector Context. */
21834 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \
21837 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \
21839 /* Tx key context. */
21840 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \
21842 /* Rx key context. */
21843 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \
21845 /* Mid-path TQM ring. */
21846 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \
21848 /* QUIC Tx key context. */
21849 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC \
21851 /* QUIC Rx key context. */
21852 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC \
21854 /* Invalid type. */
21855 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID \
21857 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \
21858 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID
21860 * Instance of the backing store type. It is zero-based,
21861 * which means "0" indicates the first instance. For backing
21862 * stores with single instance only, leave this field to 0.
21865 /* Control flags. */
21867 /* Page directory. */
21869 /* Number of entries */
21870 uint32_t num_entries;
21871 /* Page size and pbl level. */
21872 uint8_t page_size_pbl_level;
21873 /* PBL indirect levels. */
21874 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \
21876 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0
21877 /* PBL pointer is physical start address. */
21878 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \
21880 /* PBL pointer points to PTE table. */
21881 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \
21884 * PBL pointer points to PDE table with each entry pointing to
21887 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \
21889 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \
21890 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2
21892 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \
21894 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4
21896 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \
21897 (UINT32_C(0x0) << 4)
21899 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \
21900 (UINT32_C(0x1) << 4)
21902 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \
21903 (UINT32_C(0x2) << 4)
21905 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \
21906 (UINT32_C(0x3) << 4)
21908 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \
21909 (UINT32_C(0x4) << 4)
21911 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \
21912 (UINT32_C(0x5) << 4)
21913 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \
21914 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G
21916 * This field counts how many split entries contain valid data.
21917 * Below is the table that maps the count value:
21918 * | count | Indication |
21919 * | ----- | -------------------------------------------------- |
21920 * | 0 | None of the split entries has valid data. |
21921 * | 1 | Only "split_entry_0" contains valid data. |
21922 * | 2 | Only "split_entry_0" and "1" have valid data. |
21923 * | 3 | Only "split_entry_0", "1" and "2" have valid data. |
21924 * | 4 | All four split entries have valid data. |
21926 uint8_t subtype_valid_cnt;
21929 * Split entry #0. Note that the four split entries (as a group)
21930 * must be cast to a type-specific data structure first before
21931 * accessing it! Below is the table that maps a backing store
21932 * type to the associated split entry casting data structure.
21933 * | Type | Split Entry Casting Data Structure |
21934 * | ---- | -------------------------------------------------- |
21935 * | QPC | qpc_split_entries |
21936 * | SRQ | srq_split_entries |
21937 * | CQ | cq_split_entries |
21938 * | VINC | vnic_split_entries |
21939 * | MRAV | marv_split_entries |
21941 uint32_t split_entry_0;
21942 /* Split entry #1. */
21943 uint32_t split_entry_1;
21944 /* Split entry #2. */
21945 uint32_t split_entry_2;
21946 /* Split entry #3. */
21947 uint32_t split_entry_3;
21950 * This field is used in Output records to indicate that the
21951 * output is completely written to RAM. This field should be
21952 * read as '1' to indicate that the output has been completely
21953 * written. When writing a command completion or response to
21954 * an internal processor, the order of writes has to be such
21955 * that this field is written last.
21960 /************************************
21961 * hwrm_func_backing_store_qcaps_v2 *
21962 ************************************/
21965 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
21966 struct hwrm_func_backing_store_qcaps_v2_input {
21967 /* The HWRM command request type. */
21970 * The completion ring to send the completion event on. This should
21971 * be the NQ ID returned from the `nq_alloc` HWRM command.
21973 uint16_t cmpl_ring;
21975 * The sequence ID is used by the driver for tracking multiple
21976 * commands. This ID is treated as opaque data by the firmware and
21977 * the value is returned in the `hwrm_resp_hdr` upon completion.
21981 * The target ID of the command:
21982 * * 0x0-0xFFF8 - The function ID
21983 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21984 * * 0xFFFD - Reserved for user-space HWRM interface
21987 uint16_t target_id;
21989 * A physical address pointer pointing to a host buffer that the
21990 * command's response data will be written. This can be either a host
21991 * physical address (HPA) or a guest physical address (GPA) and must
21992 * point to a physically contiguous block of memory.
21994 uint64_t resp_addr;
21995 /* Type of backing store to be queried. */
21998 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP \
22000 /* Shared receive queue. */
22001 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ \
22003 /* Completion queue. */
22004 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ \
22007 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC \
22009 /* Statistic context. */
22010 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT \
22012 /* Slow-path TQM ring. */
22013 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING \
22015 /* Fast-path TQM ring. */
22016 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING \
22018 /* Memory Region and Memory Address Vector Context. */
22019 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV \
22022 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM \
22024 /* Tx key context. */
22025 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC \
22027 /* Rx key context. */
22028 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC \
22030 /* Mid-path TQM ring. */
22031 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING \
22033 /* SQ Doorbell shadow region. */
22034 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW \
22036 /* RQ Doorbell shadow region. */
22037 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW \
22039 /* SRQ Doorbell shadow region. */
22040 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW \
22042 /* CQ Doorbell shadow region. */
22043 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW \
22045 /* QUIC Tx key context. */
22046 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC \
22048 /* QUIC Rx key context. */
22049 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC \
22051 /* Invalid type. */
22052 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID \
22054 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST \
22055 HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID
22059 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
22060 struct hwrm_func_backing_store_qcaps_v2_output {
22061 /* The specific error status for the command. */
22062 uint16_t error_code;
22063 /* The HWRM command request type. */
22065 /* The sequence ID from the original command. */
22067 /* The length of the response data in number of bytes. */
22069 /* Type of backing store to be queried. */
22072 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP \
22074 /* Shared receive queue. */
22075 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ \
22077 /* Completion queue. */
22078 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ \
22081 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC \
22083 /* Statistic context. */
22084 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT \
22086 /* Slow-path TQM ring. */
22087 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING \
22089 /* Fast-path TQM ring. */
22090 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING \
22092 /* Memory Region and Memory Address Vector Context. */
22093 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV \
22096 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM \
22098 /* KTLS Tx key context. */
22099 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC \
22101 /* KTLS Rx key context. */
22102 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC \
22104 /* Mid-path TQM ring. */
22105 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING \
22107 /* SQ Doorbell shadow region. */
22108 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW \
22110 /* RQ Doorbell shadow region. */
22111 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW \
22113 /* SRQ Doorbell shadow region. */
22114 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW \
22116 /* CQ Doorbell shadow region. */
22117 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW \
22119 /* QUIC Tx key context. */
22120 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC \
22122 /* QUIC Rx key context. */
22123 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC \
22125 /* Invalid type. */
22126 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID \
22128 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_LAST \
22129 HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID
22130 /* Number of bytes per backing store entry. */
22131 uint16_t entry_size;
22132 /* Control flags. */
22135 * When set, it indicates the context type should be initialized
22136 * with the “ctx_init_value” at the specified offset.
22138 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT \
22140 /* When set, it indicates the context type is valid. */
22141 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID \
22144 * When set, it indicates the region for this type is not a regular
22145 * context memory but a driver managed memory that is created,
22146 * initialized and managed by the driver.
22148 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY \
22151 * Bit map of the valid instances associated with the
22152 * backing store type.
22154 uint32_t instance_bit_map;
22156 * Initializer to be used by drivers to initialize context memory
22157 * to ensure context subsystem flags an error for an attack before
22158 * the first time context load.
22160 uint8_t ctx_init_value;
22162 * Specifies the doubleword offset of ctx_init_value for this
22165 uint8_t ctx_init_offset;
22167 * Some backing store types, e.g., TQM rings, require the number
22168 * of entries to be a multiple of this value to prevent any
22169 * resource allocation limitations. If not applicable, leave
22170 * this field with "0".
22172 uint8_t entry_multiple;
22174 /* Maximum number of backing store entries supported for this type. */
22175 uint32_t max_num_entries;
22177 * Minimum number of backing store entries required for this type.
22178 * This field is only valid for some backing store types, e.g.,
22179 * TQM rings. If not applicable, leave this field with "0".
22181 uint32_t min_num_entries;
22183 * Next valid backing store type. If current type queried is already
22184 * the last valid type, firmware must set this field to invalid type.
22186 uint16_t next_valid_type;
22188 * This field counts how many split entries contain valid data.
22189 * Below is the table that maps the count value:
22190 * | count | Indication |
22191 * | ----- | -------------------------------------------------- |
22192 * | 0 | None of the split entries has valid data. |
22193 * | 1 | Only "split_entry_0" contains valid data. |
22194 * | 2 | Only "split_entry_0" and "1" have valid data. |
22195 * | 3 | Only "split_entry_0", "1" and "2" have valid data. |
22196 * | 4 | All four split entries have valid data. |
22198 uint8_t subtype_valid_cnt;
22201 * Split entry #0. Note that the four split entries (as a group)
22202 * must be cast to a type-specific data structure first before
22203 * accessing it! Below is the table that maps a backing store
22204 * type to the associated split entry casting data structure.
22205 * | Type | Split Entry Casting Data Structure |
22206 * | ---- | -------------------------------------------------- |
22207 * | QPC | qpc_split_entries |
22208 * | SRQ | srq_split_entries |
22209 * | CQ | cq_split_entries |
22210 * | VINC | vnic_split_entries |
22211 * | MRAV | marv_split_entries |
22213 uint32_t split_entry_0;
22214 /* Split entry #1. */
22215 uint32_t split_entry_1;
22216 /* Split entry #2. */
22217 uint32_t split_entry_2;
22218 /* Split entry #3. */
22219 uint32_t split_entry_3;
22222 * This field is used in Output records to indicate that the
22223 * output is completely written to RAM. This field should be
22224 * read as '1' to indicate that the output has been completely
22225 * written. When writing a command completion or response to
22226 * an internal processor, the order of writes has to be such
22227 * that this field is written last.
22232 /****************************
22233 * hwrm_func_dbr_pacing_cfg *
22234 ****************************/
22237 /* hwrm_func_dbr_pacing_cfg_input (size:320b/40B) */
22238 struct hwrm_func_dbr_pacing_cfg_input {
22239 /* The HWRM command request type. */
22242 * The completion ring to send the completion event on. This should
22243 * be the NQ ID returned from the `nq_alloc` HWRM command.
22245 uint16_t cmpl_ring;
22247 * The sequence ID is used by the driver for tracking multiple
22248 * commands. This ID is treated as opaque data by the firmware and
22249 * the value is returned in the `hwrm_resp_hdr` upon completion.
22253 * The target ID of the command:
22254 * * 0x0-0xFFF8 - The function ID
22255 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22256 * * 0xFFFD - Reserved for user-space HWRM interface
22259 uint16_t target_id;
22261 * A physical address pointer pointing to a host buffer that the
22262 * command's response data will be written. This can be either a host
22263 * physical address (HPA) or a guest physical address (GPA) and must
22264 * point to a physically contiguous block of memory.
22266 uint64_t resp_addr;
22269 * This bit must be '1' to enable DBR NQ events. The NQ ID to
22270 * receive the events must be specified in the primary_nq_id
22273 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE \
22275 /* This bit must be '1' to disable DBR NQ events. */
22276 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE \
22278 uint8_t unused_0[7];
22281 * This bit must be '1' for the primary_nq_id field to be
22284 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID \
22287 * This bit must be '1' for the pacing_threshold field to be
22290 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID \
22293 * Specify primary function’s NQ ID to receive the doorbell pacing
22294 * threshold crossing events.
22296 uint32_t primary_nq_id;
22298 * Specify pacing threshold value, as a percentage of the max
22299 * doorbell FIFO depth. The range is 1 to 36.
22301 uint32_t pacing_threshold;
22302 uint8_t unused_1[4];
22305 /* hwrm_func_dbr_pacing_cfg_output (size:128b/16B) */
22306 struct hwrm_func_dbr_pacing_cfg_output {
22307 /* The specific error status for the command. */
22308 uint16_t error_code;
22309 /* The HWRM command request type. */
22311 /* The sequence ID from the original command. */
22313 /* The length of the response data in number of bytes. */
22315 uint8_t unused_0[7];
22317 * This field is used in Output records to indicate that the output
22318 * is completely written to RAM. This field should be read as '1'
22319 * to indicate that the output has been completely written.
22320 * When writing a command completion or response to an internal
22321 * processor, the order of writes has to be such that this field is
22327 /*****************************
22328 * hwrm_func_dbr_pacing_qcfg *
22329 *****************************/
22332 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */
22333 struct hwrm_func_dbr_pacing_qcfg_input {
22334 /* The HWRM command request type. */
22337 * The completion ring to send the completion event on. This should
22338 * be the NQ ID returned from the `nq_alloc` HWRM command.
22340 uint16_t cmpl_ring;
22342 * The sequence ID is used by the driver for tracking multiple
22343 * commands. This ID is treated as opaque data by the firmware and
22344 * the value is returned in the `hwrm_resp_hdr` upon completion.
22348 * The target ID of the command:
22349 * * 0x0-0xFFF8 - The function ID
22350 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22351 * * 0xFFFD - Reserved for user-space HWRM interface
22354 uint16_t target_id;
22356 * A physical address pointer pointing to a host buffer that the
22357 * command's response data will be written. This can be either a host
22358 * physical address (HPA) or a guest physical address (GPA) and must
22359 * point to a physically contiguous block of memory.
22361 uint64_t resp_addr;
22364 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */
22365 struct hwrm_func_dbr_pacing_qcfg_output {
22366 /* The specific error status for the command. */
22367 uint16_t error_code;
22368 /* The HWRM command request type. */
22370 /* The sequence ID from the original command. */
22372 /* The length of the response data in number of bytes. */
22375 /* When this bit is '1', it indicates DBR NQ events are enabled. */
22376 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED \
22378 uint8_t unused_0[7];
22380 * The Doorbell global FIFO occupancy register. This field should be
22381 * used by the driver and user library in the doorbell pacing
22382 * algorithm. Lower 2 bits indicates address space location and upper
22383 * 30 bits indicates upper 30bits of the register address. A value of
22384 * 0xFFFF-FFFF indicates this register does not exist.
22386 uint32_t dbr_stat_db_fifo_reg;
22387 /* Lower 2 bits indicates address space location. */
22388 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK \
22390 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT \
22393 * If value is 0, this register is located in PCIe config space.
22394 * Drivers have to map appropriate window to access this
22397 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG \
22400 * If value is 1, this register is located in GRC address space.
22401 * Drivers have to map appropriate window to access this
22404 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC \
22407 * If value is 2, this register is located in first BAR address
22408 * space. Drivers have to map appropriate window to access this
22411 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 \
22414 * If value is 3, this register is located in second BAR address
22415 * space. Drivers have to map appropriate window to access this
22416 * Drivers have to map appropriate window to access this
22419 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 \
22421 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST \
22422 HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1
22423 /* Upper 30bits of the register address. */
22424 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK \
22425 UINT32_C(0xfffffffc)
22426 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SFT \
22429 * This field indicates the mask value for dbr_stat_db_fifo_reg
22430 * to get the high watermark for doorbell FIFO.
22432 uint32_t dbr_stat_db_fifo_reg_watermark_mask;
22434 * This field indicates the shift value for dbr_stat_db_fifo_reg
22435 * to get the high watermark for doorbell FIFO.
22437 uint8_t dbr_stat_db_fifo_reg_watermark_shift;
22438 uint8_t unused_1[3];
22440 * This field indicates the mask value for dbr_stat_db_fifo_reg
22441 * to get the amount of room left for doorbell FIFO.
22443 uint32_t dbr_stat_db_fifo_reg_fifo_room_mask;
22445 * This field indicates the shift value for dbr_stat_db_fifo_reg
22446 * to get the amount of room left for doorbell FIFO.
22448 uint8_t dbr_stat_db_fifo_reg_fifo_room_shift;
22449 uint8_t unused_2[3];
22451 * DBR_REG_AEQ_ARM register. This field should be used by the driver
22452 * to rearm the interrupt for regeneration of a notification to the
22453 * host from the hardware when the global doorbell occupancy threshold
22454 * is above the threshold value. Lower 2 bits indicates address space
22455 * location and upper 30 bits indicates upper 30bits of the register
22456 * address. A value of 0xFFFF-FFFF indicates this register does not
22459 uint32_t dbr_throttling_aeq_arm_reg;
22460 /* Lower 2 bits indicates address space location. */
22461 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK \
22463 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT \
22466 * If value is 0, this register is located in PCIe config space.
22467 * Drivers have to map appropriate window to access this
22470 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG \
22473 * If value is 1, this register is located in GRC address space.
22474 * Drivers have to map appropriate window to access this
22477 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC \
22480 * If value is 2, this register is located in first BAR address
22481 * space. Drivers have to map appropriate window to access this
22484 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 \
22487 * If value is 3, this register is located in second BAR address
22488 * space. Drivers have to map appropriate window to access this
22489 * Drivers have to map appropriate window to access this
22492 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 \
22494 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST \
22495 HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1
22496 /* Upper 30bits of the register address. */
22497 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK \
22498 UINT32_C(0xfffffffc)
22499 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT \
22502 * This field indicates the value to be written for
22503 * dbr_throttling_aeq_arm_reg register.
22505 uint8_t dbr_throttling_aeq_arm_reg_val;
22506 uint8_t unused_3[7];
22508 * Specifies primary function’s NQ ID.
22509 * A value of 0xFFFF indicates NQ ID is invalid.
22511 uint32_t primary_nq_id;
22513 * Specifies the pacing threshold value, as a percentage of the
22514 * max doorbell FIFO depth. The range is 1 to 100.
22516 uint32_t pacing_threshold;
22517 uint8_t unused_4[7];
22519 * This field is used in Output records to indicate that the output
22520 * is completely written to RAM. This field should be read as '1'
22521 * to indicate that the output has been completely written.
22522 * When writing a command completion or response to an internal
22523 * processor, the order of writes has to be such that this field is
22529 /****************************************
22530 * hwrm_func_dbr_pacing_broadcast_event *
22531 ****************************************/
22534 /* hwrm_func_dbr_pacing_broadcast_event_input (size:128b/16B) */
22535 struct hwrm_func_dbr_pacing_broadcast_event_input {
22536 /* The HWRM command request type. */
22539 * The completion ring to send the completion event on. This should
22540 * be the NQ ID returned from the `nq_alloc` HWRM command.
22542 uint16_t cmpl_ring;
22544 * The sequence ID is used by the driver for tracking multiple
22545 * commands. This ID is treated as opaque data by the firmware and
22546 * the value is returned in the `hwrm_resp_hdr` upon completion.
22550 * The target ID of the command:
22551 * * 0x0-0xFFF8 - The function ID
22552 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22553 * * 0xFFFD - Reserved for user-space HWRM interface
22556 uint16_t target_id;
22558 * A physical address pointer pointing to a host buffer that the
22559 * command's response data will be written. This can be either a host
22560 * physical address (HPA) or a guest physical address (GPA) and must
22561 * point to a physically contiguous block of memory.
22563 uint64_t resp_addr;
22566 /* hwrm_func_dbr_pacing_broadcast_event_output (size:128b/16B) */
22567 struct hwrm_func_dbr_pacing_broadcast_event_output {
22568 /* The specific error status for the command. */
22569 uint16_t error_code;
22570 /* The HWRM command request type. */
22572 /* The sequence ID from the original command. */
22574 /* The length of the response data in number of bytes. */
22576 uint8_t unused_0[7];
22578 * This field is used in Output records to indicate that the output
22579 * is completely written to RAM. This field should be read as '1'
22580 * to indicate that the output has been completely written.
22581 * When writing a command completion or response to an internal
22582 * processor, the order of writes has to be such that this field is
22588 /***********************
22589 * hwrm_func_vlan_qcfg *
22590 ***********************/
22593 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
22594 struct hwrm_func_vlan_qcfg_input {
22595 /* The HWRM command request type. */
22598 * The completion ring to send the completion event on. This should
22599 * be the NQ ID returned from the `nq_alloc` HWRM command.
22601 uint16_t cmpl_ring;
22603 * The sequence ID is used by the driver for tracking multiple
22604 * commands. This ID is treated as opaque data by the firmware and
22605 * the value is returned in the `hwrm_resp_hdr` upon completion.
22609 * The target ID of the command:
22610 * * 0x0-0xFFF8 - The function ID
22611 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22612 * * 0xFFFD - Reserved for user-space HWRM interface
22615 uint16_t target_id;
22617 * A physical address pointer pointing to a host buffer that the
22618 * command's response data will be written. This can be either a host
22619 * physical address (HPA) or a guest physical address (GPA) and must
22620 * point to a physically contiguous block of memory.
22622 uint64_t resp_addr;
22624 * Function ID of the function that is being
22626 * If set to 0xFF... (All Fs), then the configuration is
22627 * for the requesting function.
22630 uint8_t unused_0[6];
22633 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
22634 struct hwrm_func_vlan_qcfg_output {
22635 /* The specific error status for the command. */
22636 uint16_t error_code;
22637 /* The HWRM command request type. */
22639 /* The sequence ID from the original command. */
22641 /* The length of the response data in number of bytes. */
22644 /* S-TAG VLAN identifier configured for the function. */
22646 /* S-TAG PCP value configured for the function. */
22650 * S-TAG TPID value configured for the function. This field is specified in
22651 * network byte order.
22653 uint16_t stag_tpid;
22654 /* C-TAG VLAN identifier configured for the function. */
22656 /* C-TAG PCP value configured for the function. */
22660 * C-TAG TPID value configured for the function. This field is specified in
22661 * network byte order.
22663 uint16_t ctag_tpid;
22668 uint8_t unused_3[3];
22670 * This field is used in Output records to indicate that the output
22671 * is completely written to RAM. This field should be read as '1'
22672 * to indicate that the output has been completely written.
22673 * When writing a command completion or response to an internal processor,
22674 * the order of writes has to be such that this field is written last.
22679 /**********************
22680 * hwrm_func_vlan_cfg *
22681 **********************/
22684 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
22685 struct hwrm_func_vlan_cfg_input {
22686 /* The HWRM command request type. */
22689 * The completion ring to send the completion event on. This should
22690 * be the NQ ID returned from the `nq_alloc` HWRM command.
22692 uint16_t cmpl_ring;
22694 * The sequence ID is used by the driver for tracking multiple
22695 * commands. This ID is treated as opaque data by the firmware and
22696 * the value is returned in the `hwrm_resp_hdr` upon completion.
22700 * The target ID of the command:
22701 * * 0x0-0xFFF8 - The function ID
22702 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22703 * * 0xFFFD - Reserved for user-space HWRM interface
22706 uint16_t target_id;
22708 * A physical address pointer pointing to a host buffer that the
22709 * command's response data will be written. This can be either a host
22710 * physical address (HPA) or a guest physical address (GPA) and must
22711 * point to a physically contiguous block of memory.
22713 uint64_t resp_addr;
22715 * Function ID of the function that is being
22717 * If set to 0xFF... (All Fs), then the configuration is
22718 * for the requesting function.
22721 uint8_t unused_0[2];
22724 * This bit must be '1' for the stag_vid field to be
22727 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
22729 * This bit must be '1' for the ctag_vid field to be
22732 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
22734 * This bit must be '1' for the stag_pcp field to be
22737 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
22739 * This bit must be '1' for the ctag_pcp field to be
22742 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
22744 * This bit must be '1' for the stag_tpid field to be
22747 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
22749 * This bit must be '1' for the ctag_tpid field to be
22752 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
22753 /* S-TAG VLAN identifier configured for the function. */
22755 /* S-TAG PCP value configured for the function. */
22759 * S-TAG TPID value configured for the function. This field is specified in
22760 * network byte order.
22762 uint16_t stag_tpid;
22763 /* C-TAG VLAN identifier configured for the function. */
22765 /* C-TAG PCP value configured for the function. */
22769 * C-TAG TPID value configured for the function. This field is specified in
22770 * network byte order.
22772 uint16_t ctag_tpid;
22777 uint8_t unused_3[4];
22780 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
22781 struct hwrm_func_vlan_cfg_output {
22782 /* The specific error status for the command. */
22783 uint16_t error_code;
22784 /* The HWRM command request type. */
22786 /* The sequence ID from the original command. */
22788 /* The length of the response data in number of bytes. */
22790 uint8_t unused_0[7];
22792 * This field is used in Output records to indicate that the output
22793 * is completely written to RAM. This field should be read as '1'
22794 * to indicate that the output has been completely written.
22795 * When writing a command completion or response to an internal processor,
22796 * the order of writes has to be such that this field is written last.
22801 /*******************************
22802 * hwrm_func_vf_vnic_ids_query *
22803 *******************************/
22806 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
22807 struct hwrm_func_vf_vnic_ids_query_input {
22808 /* The HWRM command request type. */
22811 * The completion ring to send the completion event on. This should
22812 * be the NQ ID returned from the `nq_alloc` HWRM command.
22814 uint16_t cmpl_ring;
22816 * The sequence ID is used by the driver for tracking multiple
22817 * commands. This ID is treated as opaque data by the firmware and
22818 * the value is returned in the `hwrm_resp_hdr` upon completion.
22822 * The target ID of the command:
22823 * * 0x0-0xFFF8 - The function ID
22824 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22825 * * 0xFFFD - Reserved for user-space HWRM interface
22828 uint16_t target_id;
22830 * A physical address pointer pointing to a host buffer that the
22831 * command's response data will be written. This can be either a host
22832 * physical address (HPA) or a guest physical address (GPA) and must
22833 * point to a physically contiguous block of memory.
22835 uint64_t resp_addr;
22837 * This value is used to identify a Virtual Function (VF).
22838 * The scope of VF ID is local within a PF.
22841 uint8_t unused_0[2];
22842 /* Max number of vnic ids in vnic id table */
22843 uint32_t max_vnic_id_cnt;
22844 /* This is the address for VF VNIC ID table */
22845 uint64_t vnic_id_tbl_addr;
22848 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
22849 struct hwrm_func_vf_vnic_ids_query_output {
22850 /* The specific error status for the command. */
22851 uint16_t error_code;
22852 /* The HWRM command request type. */
22854 /* The sequence ID from the original command. */
22856 /* The length of the response data in number of bytes. */
22859 * Actual number of vnic ids
22861 * Each VNIC ID is written as a 32-bit number.
22863 uint32_t vnic_id_cnt;
22864 uint8_t unused_0[3];
22866 * This field is used in Output records to indicate that the output
22867 * is completely written to RAM. This field should be read as '1'
22868 * to indicate that the output has been completely written.
22869 * When writing a command completion or response to an internal processor,
22870 * the order of writes has to be such that this field is written last.
22875 /***********************
22876 * hwrm_func_vf_bw_cfg *
22877 ***********************/
22880 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
22881 struct hwrm_func_vf_bw_cfg_input {
22882 /* The HWRM command request type. */
22885 * The completion ring to send the completion event on. This should
22886 * be the NQ ID returned from the `nq_alloc` HWRM command.
22888 uint16_t cmpl_ring;
22890 * The sequence ID is used by the driver for tracking multiple
22891 * commands. This ID is treated as opaque data by the firmware and
22892 * the value is returned in the `hwrm_resp_hdr` upon completion.
22896 * The target ID of the command:
22897 * * 0x0-0xFFF8 - The function ID
22898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22899 * * 0xFFFD - Reserved for user-space HWRM interface
22902 uint16_t target_id;
22904 * A physical address pointer pointing to a host buffer that the
22905 * command's response data will be written. This can be either a host
22906 * physical address (HPA) or a guest physical address (GPA) and must
22907 * point to a physically contiguous block of memory.
22909 uint64_t resp_addr;
22911 * The number of VF functions that are being configured.
22912 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
22915 uint16_t unused[3];
22916 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
22918 /* The physical VF id the adjustment will be made to. */
22919 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
22920 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
22922 * This field configures the rate scale percentage of the VF as specified
22923 * by the physical VF id.
22925 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
22926 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
22927 /* 0% of the max tx rate */
22928 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
22929 (UINT32_C(0x0) << 12)
22930 /* 6.66% of the max tx rate */
22931 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
22932 (UINT32_C(0x1) << 12)
22933 /* 13.33% of the max tx rate */
22934 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
22935 (UINT32_C(0x2) << 12)
22936 /* 20% of the max tx rate */
22937 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
22938 (UINT32_C(0x3) << 12)
22939 /* 26.66% of the max tx rate */
22940 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
22941 (UINT32_C(0x4) << 12)
22942 /* 33% of the max tx rate */
22943 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
22944 (UINT32_C(0x5) << 12)
22945 /* 40% of the max tx rate */
22946 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
22947 (UINT32_C(0x6) << 12)
22948 /* 46.66% of the max tx rate */
22949 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
22950 (UINT32_C(0x7) << 12)
22951 /* 53.33% of the max tx rate */
22952 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
22953 (UINT32_C(0x8) << 12)
22954 /* 60% of the max tx rate */
22955 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
22956 (UINT32_C(0x9) << 12)
22957 /* 66.66% of the max tx rate */
22958 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
22959 (UINT32_C(0xa) << 12)
22960 /* 53.33% of the max tx rate */
22961 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
22962 (UINT32_C(0xb) << 12)
22963 /* 80% of the max tx rate */
22964 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
22965 (UINT32_C(0xc) << 12)
22966 /* 86.66% of the max tx rate */
22967 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
22968 (UINT32_C(0xd) << 12)
22969 /* 93.33% of the max tx rate */
22970 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
22971 (UINT32_C(0xe) << 12)
22972 /* 100% of the max tx rate */
22973 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
22974 (UINT32_C(0xf) << 12)
22975 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
22976 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
22979 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
22980 struct hwrm_func_vf_bw_cfg_output {
22981 /* The specific error status for the command. */
22982 uint16_t error_code;
22983 /* The HWRM command request type. */
22985 /* The sequence ID from the original command. */
22987 /* The length of the response data in number of bytes. */
22989 uint8_t unused_0[7];
22991 * This field is used in Output records to indicate that the output
22992 * is completely written to RAM. This field should be read as '1'
22993 * to indicate that the output has been completely written.
22994 * When writing a command completion or response to an internal processor,
22995 * the order of writes has to be such that this field is written last.
23000 /************************
23001 * hwrm_func_vf_bw_qcfg *
23002 ************************/
23005 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
23006 struct hwrm_func_vf_bw_qcfg_input {
23007 /* The HWRM command request type. */
23010 * The completion ring to send the completion event on. This should
23011 * be the NQ ID returned from the `nq_alloc` HWRM command.
23013 uint16_t cmpl_ring;
23015 * The sequence ID is used by the driver for tracking multiple
23016 * commands. This ID is treated as opaque data by the firmware and
23017 * the value is returned in the `hwrm_resp_hdr` upon completion.
23021 * The target ID of the command:
23022 * * 0x0-0xFFF8 - The function ID
23023 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23024 * * 0xFFFD - Reserved for user-space HWRM interface
23027 uint16_t target_id;
23029 * A physical address pointer pointing to a host buffer that the
23030 * command's response data will be written. This can be either a host
23031 * physical address (HPA) or a guest physical address (GPA) and must
23032 * point to a physically contiguous block of memory.
23034 uint64_t resp_addr;
23036 * The number of VF functions that are being queried.
23037 * The inline response space allows the host to query up to 50 VFs'
23038 * rate scale percentage
23041 uint16_t unused[3];
23042 /* These 16-bit fields contain the VF fid */
23044 /* The physical VF id of interest */
23045 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
23046 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
23049 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
23050 struct hwrm_func_vf_bw_qcfg_output {
23051 /* The specific error status for the command. */
23052 uint16_t error_code;
23053 /* The HWRM command request type. */
23055 /* The sequence ID from the original command. */
23057 /* The length of the response data in number of bytes. */
23060 * The number of VF functions that are being queried.
23061 * The inline response space allows the host to query up to 50 VFs' rate
23065 uint16_t unused[3];
23066 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
23068 /* The physical VF id the adjustment will be made to. */
23069 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
23070 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
23072 * This field configures the rate scale percentage of the VF as specified
23073 * by the physical VF id.
23075 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
23076 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
23077 /* 0% of the max tx rate */
23078 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
23079 (UINT32_C(0x0) << 12)
23080 /* 6.66% of the max tx rate */
23081 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
23082 (UINT32_C(0x1) << 12)
23083 /* 13.33% of the max tx rate */
23084 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
23085 (UINT32_C(0x2) << 12)
23086 /* 20% of the max tx rate */
23087 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
23088 (UINT32_C(0x3) << 12)
23089 /* 26.66% of the max tx rate */
23090 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
23091 (UINT32_C(0x4) << 12)
23092 /* 33% of the max tx rate */
23093 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
23094 (UINT32_C(0x5) << 12)
23095 /* 40% of the max tx rate */
23096 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
23097 (UINT32_C(0x6) << 12)
23098 /* 46.66% of the max tx rate */
23099 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
23100 (UINT32_C(0x7) << 12)
23101 /* 53.33% of the max tx rate */
23102 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
23103 (UINT32_C(0x8) << 12)
23104 /* 60% of the max tx rate */
23105 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
23106 (UINT32_C(0x9) << 12)
23107 /* 66.66% of the max tx rate */
23108 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
23109 (UINT32_C(0xa) << 12)
23110 /* 53.33% of the max tx rate */
23111 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
23112 (UINT32_C(0xb) << 12)
23113 /* 80% of the max tx rate */
23114 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
23115 (UINT32_C(0xc) << 12)
23116 /* 86.66% of the max tx rate */
23117 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
23118 (UINT32_C(0xd) << 12)
23119 /* 93.33% of the max tx rate */
23120 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
23121 (UINT32_C(0xe) << 12)
23122 /* 100% of the max tx rate */
23123 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
23124 (UINT32_C(0xf) << 12)
23125 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
23126 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
23127 uint8_t unused_0[7];
23129 * This field is used in Output records to indicate that the output
23130 * is completely written to RAM. This field should be read as '1'
23131 * to indicate that the output has been completely written.
23132 * When writing a command completion or response to an internal processor,
23133 * the order of writes has to be such that this field is written last.
23138 /***************************
23139 * hwrm_func_drv_if_change *
23140 ***************************/
23143 /* hwrm_func_drv_if_change_input (size:192b/24B) */
23144 struct hwrm_func_drv_if_change_input {
23145 /* The HWRM command request type. */
23148 * The completion ring to send the completion event on. This should
23149 * be the NQ ID returned from the `nq_alloc` HWRM command.
23151 uint16_t cmpl_ring;
23153 * The sequence ID is used by the driver for tracking multiple
23154 * commands. This ID is treated as opaque data by the firmware and
23155 * the value is returned in the `hwrm_resp_hdr` upon completion.
23159 * The target ID of the command:
23160 * * 0x0-0xFFF8 - The function ID
23161 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23162 * * 0xFFFD - Reserved for user-space HWRM interface
23165 uint16_t target_id;
23167 * A physical address pointer pointing to a host buffer that the
23168 * command's response data will be written. This can be either a host
23169 * physical address (HPA) or a guest physical address (GPA) and must
23170 * point to a physically contiguous block of memory.
23172 uint64_t resp_addr;
23175 * When this bit is '1', the function driver is indicating
23176 * that the IF state is changing to UP state. The call should
23177 * be made at the beginning of the driver's open call before
23178 * resources are allocated. After making the call, the driver
23179 * should check the response to see if any resources may have
23180 * changed (see the response below). If the driver fails
23181 * the open call, the driver should make this call again with
23182 * this bit cleared to indicate that the IF state is not UP.
23183 * During the driver's close call when the IF state is changing
23184 * to DOWN, the driver should make this call with the bit cleared
23185 * after all resources have been freed.
23187 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
23191 /* hwrm_func_drv_if_change_output (size:128b/16B) */
23192 struct hwrm_func_drv_if_change_output {
23193 /* The specific error status for the command. */
23194 uint16_t error_code;
23195 /* The HWRM command request type. */
23197 /* The sequence ID from the original command. */
23199 /* The length of the response data in number of bytes. */
23203 * When this bit is '1', it indicates that the resources reserved
23204 * for this function may have changed. The driver should check
23205 * resource capabilities and reserve resources again before
23206 * allocating resources.
23208 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
23211 * When this bit is '1', it indicates that the firmware got changed / reset.
23212 * The driver should do complete re-initialization when that bit is set.
23214 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
23216 uint8_t unused_0[3];
23218 * This field is used in Output records to indicate that the output
23219 * is completely written to RAM. This field should be read as '1'
23220 * to indicate that the output has been completely written.
23221 * When writing a command completion or response to an internal processor,
23222 * the order of writes has to be such that this field is written last.
23227 /*******************************
23228 * hwrm_func_host_pf_ids_query *
23229 *******************************/
23232 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
23233 struct hwrm_func_host_pf_ids_query_input {
23234 /* The HWRM command request type. */
23237 * The completion ring to send the completion event on. This should
23238 * be the NQ ID returned from the `nq_alloc` HWRM command.
23240 uint16_t cmpl_ring;
23242 * The sequence ID is used by the driver for tracking multiple
23243 * commands. This ID is treated as opaque data by the firmware and
23244 * the value is returned in the `hwrm_resp_hdr` upon completion.
23248 * The target ID of the command:
23249 * * 0x0-0xFFF8 - The function ID
23250 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23251 * * 0xFFFD - Reserved for user-space HWRM interface
23254 uint16_t target_id;
23256 * A physical address pointer pointing to a host buffer that the
23257 * command's response data will be written. This can be either a host
23258 * physical address (HPA) or a guest physical address (GPA) and must
23259 * point to a physically contiguous block of memory.
23261 uint64_t resp_addr;
23264 * # If this bit is set to '1', the query will contain PF(s)
23265 * belongs to SOC host.
23267 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
23269 * # If this bit is set to '1', the query will contain PF(s)
23270 * belongs to EP0 host.
23272 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
23274 * # If this bit is set to '1', the query will contain PF(s)
23275 * belongs to EP1 host.
23277 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
23279 * # If this bit is set to '1', the query will contain PF(s)
23280 * belongs to EP2 host.
23282 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
23284 * # If this bit is set to '1', the query will contain PF(s)
23285 * belongs to EP3 host.
23287 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
23289 * This provides a filter of what PF(s) will be returned in the
23294 * all available PF(s) belong to the host(s) (defined in the
23295 * host field). This includes the hidden PFs.
23297 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
23299 * all available PF(s) belong to the host(s) (defined in the
23300 * host field) that is available for L2 traffic.
23302 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
23304 * all available PF(s) belong to the host(s) (defined in the
23305 * host field) that is available for ROCE traffic.
23307 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
23308 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
23309 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
23310 uint8_t unused_1[6];
23313 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
23314 struct hwrm_func_host_pf_ids_query_output {
23315 /* The specific error status for the command. */
23316 uint16_t error_code;
23317 /* The HWRM command request type. */
23319 /* The sequence ID from the original command. */
23321 /* The length of the response data in number of bytes. */
23323 /* This provides the first PF ID of the device. */
23324 uint16_t first_pf_id;
23325 uint16_t pf_ordinal_mask;
23327 * When this bit is '1', it indicates first PF belongs to one of
23328 * the hosts defined in the input request.
23330 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
23333 * When this bit is '1', it indicates 2nd PF belongs to one of the
23334 * hosts defined in the input request.
23336 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
23339 * When this bit is '1', it indicates 3rd PF belongs to one of the
23340 * hosts defined in the input request.
23342 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
23345 * When this bit is '1', it indicates 4th PF belongs to one of the
23346 * hosts defined in the input request.
23348 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
23351 * When this bit is '1', it indicates 5th PF belongs to one of the
23352 * hosts defined in the input request.
23354 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
23357 * When this bit is '1', it indicates 6th PF belongs to one of the
23358 * hosts defined in the input request.
23360 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
23363 * When this bit is '1', it indicates 7th PF belongs to one of the
23364 * hosts defined in the input request.
23366 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
23369 * When this bit is '1', it indicates 8th PF belongs to one of the
23370 * hosts defined in the input request.
23372 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
23375 * When this bit is '1', it indicates 9th PF belongs to one of the
23376 * hosts defined in the input request.
23378 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
23381 * When this bit is '1', it indicates 10th PF belongs to one of the
23382 * hosts defined in the input request.
23384 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
23387 * When this bit is '1', it indicates 11th PF belongs to one of the
23388 * hosts defined in the input request.
23390 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
23393 * When this bit is '1', it indicates 12th PF belongs to one of the
23394 * hosts defined in the input request.
23396 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
23399 * When this bit is '1', it indicates 13th PF belongs to one of the
23400 * hosts defined in the input request.
23402 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
23405 * When this bit is '1', it indicates 14th PF belongs to one of the
23406 * hosts defined in the input request.
23408 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
23411 * When this bit is '1', it indicates 15th PF belongs to one of the
23412 * hosts defined in the input request.
23414 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
23417 * When this bit is '1', it indicates 16th PF belongs to one of the
23418 * hosts defined in the input request.
23420 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
23422 uint8_t unused_1[3];
23424 * This field is used in Output records to indicate that the output
23425 * is completely written to RAM. This field should be read as '1'
23426 * to indicate that the output has been completely written.
23427 * When writing a command completion or response to an internal processor,
23428 * the order of writes has to be such that this field is written last.
23433 /*********************
23434 * hwrm_func_spd_cfg *
23435 *********************/
23438 /* hwrm_func_spd_cfg_input (size:384b/48B) */
23439 struct hwrm_func_spd_cfg_input {
23440 /* The HWRM command request type. */
23443 * The completion ring to send the completion event on. This should
23444 * be the NQ ID returned from the `nq_alloc` HWRM command.
23446 uint16_t cmpl_ring;
23448 * The sequence ID is used by the driver for tracking multiple
23449 * commands. This ID is treated as opaque data by the firmware and
23450 * the value is returned in the `hwrm_resp_hdr` upon completion.
23454 * The target ID of the command:
23455 * * 0x0-0xFFF8 - The function ID
23456 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23457 * * 0xFFFD - Reserved for user-space HWRM interface
23460 uint16_t target_id;
23462 * A physical address pointer pointing to a host buffer that the
23463 * command's response data will be written. This can be either a host
23464 * physical address (HPA) or a guest physical address (GPA) and must
23465 * point to a physically contiguous block of memory.
23467 uint64_t resp_addr;
23469 /* Set this bit is '1' to enable the SPD datapath forwarding. */
23470 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
23471 /* Set this bit is '1' to disable the SPD datapath forwarding. */
23472 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
23474 * Set this bit is '1' to enable the SPD datapath checksum
23477 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
23479 * Set this bit is '1' to disable the SPD datapath checksum
23482 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
23484 * Set this bit is '1' to enable the SPD datapath debug
23487 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
23489 * Set this bit is '1' to disable the SPD datapath debug
23492 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
23495 * This bit must be '1' for the ethertype field to be
23498 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
23501 * This bit must be '1' for the hash_mode_flags field to be
23504 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
23507 * This bit must be '1' for the hash_type field to be
23510 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
23513 * This bit must be '1' for the ring_tbl_addr field to be
23516 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
23519 * This bit must be '1' for the hash_key_tbl_addr field to be
23522 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
23525 * Ethertype value used in the encapsulated SPD packet header.
23526 * The user must choose a value that is not conflicting with
23527 * publicly defined ethertype values. By default, the ethertype
23528 * value of 0xffff is used if there is no user specified value.
23530 uint16_t ethertype;
23531 /* Flags to specify different RSS hash modes. */
23532 uint8_t hash_mode_flags;
23534 * When this bit is '1', it indicates using current RSS
23535 * hash mode setting configured in the device.
23537 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
23540 * When this bit is '1', it indicates requesting support of
23541 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
23542 * l4.src, l4.dest} for tunnel packets. For none-tunnel
23543 * packets, the RSS hash is computed over the normal
23544 * src/dest l3 and src/dest l4 headers.
23546 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
23549 * When this bit is '1', it indicates requesting support of
23550 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
23551 * tunnel packets. For none-tunnel packets, the RSS hash is
23552 * computed over the normal src/dest l3 headers.
23554 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
23557 * When this bit is '1', it indicates requesting support of
23558 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
23559 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
23560 * packets, the RSS hash is computed over the normal
23561 * src/dest l3 and src/dest l4 headers.
23563 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
23566 * When this bit is '1', it indicates requesting support of
23567 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
23568 * tunnel packets. For none-tunnel packets, the RSS hash is
23569 * computed over the normal src/dest l3 headers.
23571 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
23574 uint32_t hash_type;
23576 * When this bit is '1', the RSS hash shall be computed
23577 * over source and destination IPv4 addresses of IPv4
23580 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
23582 * When this bit is '1', the RSS hash shall be computed
23583 * over source/destination IPv4 addresses and
23584 * source/destination ports of TCP/IPv4 packets.
23586 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
23588 * When this bit is '1', the RSS hash shall be computed
23589 * over source/destination IPv4 addresses and
23590 * source/destination ports of UDP/IPv4 packets.
23592 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
23594 * When this bit is '1', the RSS hash shall be computed
23595 * over source and destination IPv4 addresses of IPv6
23598 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
23600 * When this bit is '1', the RSS hash shall be computed
23601 * over source/destination IPv6 addresses and
23602 * source/destination ports of TCP/IPv6 packets.
23604 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
23606 * When this bit is '1', the RSS hash shall be computed
23607 * over source/destination IPv6 addresses and
23608 * source/destination ports of UDP/IPv6 packets.
23610 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
23611 /* This is the address for rss ring group table */
23612 uint64_t ring_grp_tbl_addr;
23613 /* This is the address for rss hash key table */
23614 uint64_t hash_key_tbl_addr;
23617 /* hwrm_func_spd_cfg_output (size:128b/16B) */
23618 struct hwrm_func_spd_cfg_output {
23619 /* The specific error status for the command. */
23620 uint16_t error_code;
23621 /* The HWRM command request type. */
23623 /* The sequence ID from the original command. */
23625 /* The length of the response data in number of bytes. */
23627 uint8_t unused_0[7];
23629 * This field is used in Output records to indicate that the output
23630 * is completely written to RAM. This field should be read as '1'
23631 * to indicate that the output has been completely written.
23632 * When writing a command completion or response to an internal processor,
23633 * the order of writes has to be such that this field is written last.
23638 /**********************
23639 * hwrm_func_spd_qcfg *
23640 **********************/
23643 /* hwrm_func_spd_qcfg_input (size:128b/16B) */
23644 struct hwrm_func_spd_qcfg_input {
23645 /* The HWRM command request type. */
23648 * The completion ring to send the completion event on. This should
23649 * be the NQ ID returned from the `nq_alloc` HWRM command.
23651 uint16_t cmpl_ring;
23653 * The sequence ID is used by the driver for tracking multiple
23654 * commands. This ID is treated as opaque data by the firmware and
23655 * the value is returned in the `hwrm_resp_hdr` upon completion.
23659 * The target ID of the command:
23660 * * 0x0-0xFFF8 - The function ID
23661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23662 * * 0xFFFD - Reserved for user-space HWRM interface
23665 uint16_t target_id;
23667 * A physical address pointer pointing to a host buffer that the
23668 * command's response data will be written. This can be either a host
23669 * physical address (HPA) or a guest physical address (GPA) and must
23670 * point to a physically contiguous block of memory.
23672 uint64_t resp_addr;
23675 /* hwrm_func_spd_qcfg_output (size:512b/64B) */
23676 struct hwrm_func_spd_qcfg_output {
23677 /* The specific error status for the command. */
23678 uint16_t error_code;
23679 /* The HWRM command request type. */
23681 /* The sequence ID from the original command. */
23683 /* The length of the response data in number of bytes. */
23687 * The SPD datapath forwarding is currently enabled when this
23688 * flag is set to '1'.
23690 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
23692 * The SPD datapath checksum feature is currently enabled when
23693 * this flag is set to '1'.
23695 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
23697 * The SPD datapath debug feature is currently enabled when
23698 * this flag is set to '1'.
23700 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
23701 uint32_t hash_type;
23703 * When this bit is '1', the RSS hash shall be computed
23704 * over source and destination IPv4 addresses of IPv4
23707 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
23709 * When this bit is '1', the RSS hash shall be computed
23710 * over source/destination IPv4 addresses and
23711 * source/destination ports of TCP/IPv4 packets.
23713 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
23715 * When this bit is '1', the RSS hash shall be computed
23716 * over source/destination IPv4 addresses and
23717 * source/destination ports of UDP/IPv4 packets.
23719 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
23721 * When this bit is '1', the RSS hash shall be computed
23722 * over source and destination IPv4 addresses of IPv6
23725 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
23727 * When this bit is '1', the RSS hash shall be computed
23728 * over source/destination IPv6 addresses and
23729 * source/destination ports of TCP/IPv6 packets.
23731 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
23733 * When this bit is '1', the RSS hash shall be computed
23734 * over source/destination IPv6 addresses and
23735 * source/destination ports of UDP/IPv6 packets.
23737 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
23738 /* This is the value of rss hash key */
23739 uint32_t hash_key[10];
23740 /* Flags to specify different RSS hash modes. */
23741 uint8_t hash_mode_flags;
23743 * When this bit is '1', it indicates using current RSS
23744 * hash mode setting configured in the device.
23746 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
23749 * When this bit is '1', it indicates requesting support of
23750 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
23751 * l4.src, l4.dest} for tunnel packets. For none-tunnel
23752 * packets, the RSS hash is computed over the normal
23753 * src/dest l3 and src/dest l4 headers.
23755 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
23758 * When this bit is '1', it indicates requesting support of
23759 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
23760 * tunnel packets. For none-tunnel packets, the RSS hash is
23761 * computed over the normal src/dest l3 headers.
23763 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
23766 * When this bit is '1', it indicates requesting support of
23767 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
23768 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
23769 * packets, the RSS hash is computed over the normal
23770 * src/dest l3 and src/dest l4 headers.
23772 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
23775 * When this bit is '1', it indicates requesting support of
23776 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
23777 * tunnel packets. For none-tunnel packets, the RSS hash is
23778 * computed over the normal src/dest l3 headers.
23780 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
23784 * Ethertype value used in the encapsulated SPD packet header.
23785 * The user must choose a value that is not conflicting with
23786 * publicly defined ethertype values. By default, the ethertype
23787 * value of 0xffff is used if there is no user specified value.
23789 uint16_t ethertype;
23790 uint8_t unused_2[3];
23792 * This field is used in Output records to indicate that the output
23793 * is completely written to RAM. This field should be read as '1'
23794 * to indicate that the output has been completely written.
23795 * When writing a command completion or response to an internal processor,
23796 * the order of writes has to be such that this field is written last.
23801 /*********************
23802 * hwrm_port_phy_cfg *
23803 *********************/
23806 /* hwrm_port_phy_cfg_input (size:448b/56B) */
23807 struct hwrm_port_phy_cfg_input {
23808 /* The HWRM command request type. */
23811 * The completion ring to send the completion event on. This should
23812 * be the NQ ID returned from the `nq_alloc` HWRM command.
23814 uint16_t cmpl_ring;
23816 * The sequence ID is used by the driver for tracking multiple
23817 * commands. This ID is treated as opaque data by the firmware and
23818 * the value is returned in the `hwrm_resp_hdr` upon completion.
23822 * The target ID of the command:
23823 * * 0x0-0xFFF8 - The function ID
23824 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23825 * * 0xFFFD - Reserved for user-space HWRM interface
23828 uint16_t target_id;
23830 * A physical address pointer pointing to a host buffer that the
23831 * command's response data will be written. This can be either a host
23832 * physical address (HPA) or a guest physical address (GPA) and must
23833 * point to a physically contiguous block of memory.
23835 uint64_t resp_addr;
23838 * When this bit is set to '1', the PHY for the port shall
23841 * # If this bit is set to 1, then the HWRM shall reset the
23842 * PHY after applying PHY configuration changes specified
23844 * # In order to guarantee that PHY configuration changes
23845 * specified in this command take effect, the HWRM
23846 * client should set this flag to 1.
23847 * # If this bit is not set to 1, then the HWRM may reset
23848 * the PHY depending on the current PHY configuration and
23849 * settings specified in this command.
23851 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
23853 /* deprecated bit. Do not use!!! */
23854 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
23857 * When this bit is set to '1', and the force_pam4_link_speed
23858 * bit in the 'enables' field is '0', the link shall be forced
23859 * to the force_link_speed value.
23861 * When this bit is set to '1', and the force_pam4_link_speed
23862 * bit in the 'enables' field is '1', the link shall be forced
23863 * to the force_pam4_link_speed value.
23865 * When this bit is set to '1', the HWRM client should
23866 * not enable any of the auto negotiation related
23867 * fields represented by auto_XXX fields in this command.
23868 * When this bit is set to '1' and the HWRM client has
23869 * enabled a auto_XXX field in this command, then the
23870 * HWRM shall ignore the enabled auto_XXX field.
23872 * When this bit is set to zero, the link
23873 * shall be allowed to autoneg.
23875 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
23878 * When this bit is set to '1', the auto-negotiation process
23879 * shall be restarted on the link.
23881 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
23884 * When this bit is set to '1', Energy Efficient Ethernet
23885 * (EEE) is requested to be enabled on this link.
23886 * If EEE is not supported on this port, then this flag
23887 * shall be ignored by the HWRM.
23889 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
23892 * When this bit is set to '1', Energy Efficient Ethernet
23893 * (EEE) is requested to be disabled on this link.
23894 * If EEE is not supported on this port, then this flag
23895 * shall be ignored by the HWRM.
23897 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
23900 * When this bit is set to '1' and EEE is enabled on this
23901 * link, then TX LPI is requested to be enabled on the link.
23902 * If EEE is not supported on this port, then this flag
23903 * shall be ignored by the HWRM.
23904 * If EEE is disabled on this port, then this flag shall be
23905 * ignored by the HWRM.
23907 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
23910 * When this bit is set to '1' and EEE is enabled on this
23911 * link, then TX LPI is requested to be disabled on the link.
23912 * If EEE is not supported on this port, then this flag
23913 * shall be ignored by the HWRM.
23914 * If EEE is disabled on this port, then this flag shall be
23915 * ignored by the HWRM.
23917 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
23920 * When set to 1, then the HWRM shall enable FEC autonegotitation
23921 * on this port if supported. When enabled, at least one of the
23922 * FEC modes must be advertised by enabling the fec_clause_74_enable,
23923 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
23924 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
23925 * of the FEC mode is currently enabled, the HWRM shall choose
23926 * a default advertisement setting.
23927 * The default advertisement setting can be queried by calling
23928 * hwrm_port_phy_qcfg. Note that the link speed must be
23929 * in autonegotiation mode for FEC autonegotiation to take effect.
23930 * When set to 0, then this flag shall be ignored.
23931 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
23934 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
23937 * When set to 1, then the HWRM shall disable FEC autonegotiation
23938 * on this port and use forced FEC mode. In forced FEC mode, one
23939 * or more FEC forced settings under the same clause can be set.
23940 * When set to 0, then this flag shall be ignored.
23941 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
23944 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
23947 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
23948 * on this port if supported, by advertising FEC CLAUSE 74 if
23949 * FEC autonegotiation is enabled or force enabled otherwise.
23950 * When set to 0, then this flag shall be ignored.
23951 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
23954 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
23957 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
23958 * on this port if supported, by not advertising FEC CLAUSE 74 if
23959 * FEC autonegotiation is enabled or force disabled otherwise.
23960 * When set to 0, then this flag shall be ignored.
23961 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
23964 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
23967 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
23968 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
23969 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
23970 * or force enabled otherwise. In forced FEC mode, this flag
23971 * will only take effect if the speed is NRZ. Additional
23972 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
23973 * in forced FEC mode.
23974 * When set to 0, then this flag shall be ignored.
23975 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
23978 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
23981 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
23982 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
23983 * not advertising RS(528,514) if FEC autonegotiation is enabled or
23984 * force disabled otherwise. When set to 0, then this flag shall be
23985 * ignored. If FEC RS(528,514) is not supported, then the HWRM
23986 * shall ignore this flag.
23988 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
23991 * When this bit is set to '1', the link shall be forced to
23994 * # When this bit is set to '1", all other
23995 * command input settings related to the link speed shall
23997 * Once the link state is forced down, it can be
23998 * explicitly cleared from that state by setting this flag
24000 * # If this flag is set to '0', then the link shall be
24001 * cleared from forced down state if the link is in forced
24003 * There may be conditions (e.g. out-of-band or sideband
24004 * configuration changes for the link) outside the scope
24005 * of the HWRM implementation that may clear forced down
24008 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
24011 * When set to 1, then the HWRM shall enable FEC RS544_1XN
24012 * on this port if supported, by advertising FEC RS544_1XN if
24013 * FEC autonegotiation is enabled or force enabled otherwise.
24014 * In forced mode, this flag will only take effect if the speed is
24015 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
24016 * HWRM shall choose one of the RS544 modes.
24017 * When set to 0, then this flag shall be ignored.
24018 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
24021 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
24024 * When set to 1, then the HWRM shall disable FEC RS544_1XN
24025 * on this port if supported, by not advertising FEC RS544_1XN if
24026 * FEC autonegotiation is enabled or force disabled otherwise.
24027 * When set to 0, then this flag shall be ignored.
24028 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
24031 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
24034 * When set to 1, then the HWRM shall enable FEC RS(544,514)
24035 * on this port if supported, by advertising FEC RS(544,514) if
24036 * FEC autonegotiation is enabled or force enabled otherwise.
24037 * In forced mode, this flag will only take effect if the speed is
24038 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
24039 * HWRM shall choose one of the RS544 modes.
24040 * When set to 0, then this flag shall be ignored.
24041 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
24044 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
24047 * When set to 1, then the HWRM shall disable FEC RS(544,514)
24048 * on this port if supported, by not advertising FEC RS(544,514) if
24049 * FEC autonegotiation is enabled or force disabled otherwise.
24050 * When set to 0, then this flag shall be ignored.
24051 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
24054 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
24057 * When set to 1, then the HWRM shall enable FEC RS272_1XN
24058 * on this port if supported, by advertising FEC RS272_1XN if
24059 * FEC autonegotiation is enabled or force enabled otherwise.
24060 * In forced mode, this flag will only take effect if the speed is
24061 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
24062 * HWRM shall choose one of the RS272 modes. Note that RS272
24063 * and RS544 modes cannot be set at the same time in forced FEC mode.
24064 * When set to 0, then this flag shall be ignored.
24065 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
24068 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
24071 * When set to 1, then the HWRM shall disable FEC RS272_1XN
24072 * on this port if supported, by not advertising FEC RS272_1XN if
24073 * FEC autonegotiation is enabled or force disabled otherwise.
24074 * When set to 0, then this flag shall be ignored.
24075 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
24078 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
24081 * When set to 1, then the HWRM shall enable FEC RS(272,257)
24082 * on this port if supported, by advertising FEC RS(272,257) if
24083 * FEC autonegotiation is enabled or force enabled otherwise.
24084 * In forced mode, this flag will only take effect if the speed is
24085 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
24086 * HWRM shall choose one of the RS272 modes. Note that RS272
24087 * and RS544 modes cannot be set at the same time in forced FEC mode.
24088 * When set to 0, then this flag shall be ignored.
24089 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
24092 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
24095 * When set to 1, then the HWRM shall disable FEC RS(272,257)
24096 * on this port if supported, by not advertising FEC RS(272,257) if
24097 * FEC autonegotiation is enabled or force disabled otherwise.
24098 * When set to 0, then this flag shall be ignored.
24099 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
24102 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
24106 * This bit must be '1' for the auto_mode field to be
24109 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
24112 * This bit must be '1' for the auto_duplex field to be
24115 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
24118 * This bit must be '1' for the auto_pause field to be
24121 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
24124 * This bit must be '1' for the auto_link_speed field to be
24127 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
24130 * This bit must be '1' for the auto_link_speed_mask field to be
24133 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
24136 * This bit must be '1' for the wirespeed field to be
24139 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
24142 * This bit must be '1' for the lpbk field to be
24145 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
24148 * This bit must be '1' for the preemphasis field to be
24151 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
24154 * This bit must be '1' for the force_pause field to be
24157 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
24160 * This bit must be '1' for the eee_link_speed_mask field to be
24163 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
24166 * This bit must be '1' for the tx_lpi_timer field to be
24169 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
24172 * This bit must be '1' for the force_pam4_link_speed field to be
24175 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
24178 * This bit must be '1' for the auto_pam4_link_speed_mask field to
24181 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
24183 /* Port ID of port that is to be configured. */
24186 * This is the speed that will be used if the force
24187 * bit is '1'. If unsupported speed is selected, an error
24188 * will be generated.
24190 uint16_t force_link_speed;
24191 /* 100Mb link speed */
24192 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
24193 /* 1Gb link speed */
24194 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
24195 /* 2Gb link speed */
24196 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
24197 /* 25Gb link speed */
24198 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
24199 /* 10Gb link speed */
24200 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
24201 /* 20Mb link speed */
24202 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
24203 /* 25Gb link speed */
24204 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
24205 /* 40Gb link speed */
24206 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
24207 /* 50Gb link speed */
24208 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
24209 /* 100Gb link speed */
24210 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
24211 /* 10Mb link speed */
24212 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
24213 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
24214 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
24216 * This value is used to identify what autoneg mode is
24217 * used when the link speed is not being forced.
24220 /* Disable autoneg or autoneg disabled. No speeds are selected. */
24221 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
24222 /* Select all possible speeds for autoneg mode. */
24223 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
24225 * Select only the auto_link_speed speed for autoneg mode. This mode has
24226 * been DEPRECATED. An HWRM client should not use this mode.
24228 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
24230 * Select the auto_link_speed or any speed below that speed for autoneg.
24231 * This mode has been DEPRECATED. An HWRM client should not use this mode.
24233 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
24235 * Select the speeds based on the corresponding link speed mask values
24236 * that are provided. The included speeds are specified in the
24237 * auto_link_speed and auto_pam4_link_speed fields.
24239 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
24240 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
24241 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
24243 * This is the duplex setting that will be used if the autoneg_mode
24244 * is "one_speed" or "one_or_below".
24246 uint8_t auto_duplex;
24247 /* Half Duplex will be requested. */
24248 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
24249 /* Full duplex will be requested. */
24250 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
24251 /* Both Half and Full duplex will be requested. */
24252 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
24253 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
24254 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
24256 * This value is used to configure the pause that will be
24257 * used for autonegotiation.
24258 * Add text on the usage of auto_pause and force_pause.
24260 uint8_t auto_pause;
24262 * When this bit is '1', Generation of tx pause messages
24263 * has been requested. Disabled otherwise.
24265 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
24268 * When this bit is '1', Reception of rx pause messages
24269 * has been requested. Disabled otherwise.
24271 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
24274 * When set to 1, the advertisement of pause is enabled.
24276 * # When the auto_mode is not set to none and this flag is
24277 * set to 1, then the auto_pause bits on this port are being
24278 * advertised and autoneg pause results are being interpreted.
24279 * # When the auto_mode is not set to none and this
24280 * flag is set to 0, the pause is forced as indicated in
24281 * force_pause, and also advertised as auto_pause bits, but
24282 * the autoneg results are not interpreted since the pause
24283 * configuration is being forced.
24284 * # When the auto_mode is set to none and this flag is set to
24285 * 1, auto_pause bits should be ignored and should be set to 0.
24287 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
24291 * This is the speed that will be used if the autoneg_mode
24292 * is "one_speed" or "one_or_below". If an unsupported speed
24293 * is selected, an error will be generated.
24295 uint16_t auto_link_speed;
24296 /* 100Mb link speed */
24297 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
24298 /* 1Gb link speed */
24299 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
24300 /* 2Gb link speed */
24301 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
24302 /* 25Gb link speed */
24303 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
24304 /* 10Gb link speed */
24305 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
24306 /* 20Mb link speed */
24307 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
24308 /* 25Gb link speed */
24309 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
24310 /* 40Gb link speed */
24311 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
24312 /* 50Gb link speed */
24313 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
24314 /* 100Gb link speed */
24315 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
24316 /* 10Mb link speed */
24317 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
24318 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
24319 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
24321 * This is a mask of link speeds that will be used if
24322 * autoneg_mode is "mask". If unsupported speed is enabled
24323 * an error will be generated.
24325 uint16_t auto_link_speed_mask;
24326 /* 100Mb link speed (Half-duplex) */
24327 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
24329 /* 100Mb link speed (Full-duplex) */
24330 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
24332 /* 1Gb link speed (Half-duplex) */
24333 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
24335 /* 1Gb link speed (Full-duplex) */
24336 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
24338 /* 2Gb link speed */
24339 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
24341 /* 25Gb link speed */
24342 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
24344 /* 10Gb link speed */
24345 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
24347 /* 20Gb link speed */
24348 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
24350 /* 25Gb link speed */
24351 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
24353 /* 40Gb link speed */
24354 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
24356 /* 50Gb link speed */
24357 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
24359 /* 100Gb link speed */
24360 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
24362 /* 10Mb link speed (Half-duplex) */
24363 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
24365 /* 10Mb link speed (Full-duplex) */
24366 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
24368 /* This value controls the wirespeed feature. */
24370 /* Wirespeed feature is disabled. */
24371 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
24372 /* Wirespeed feature is enabled. */
24373 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
24374 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
24375 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
24376 /* This value controls the loopback setting for the PHY. */
24378 /* No loopback is selected. Normal operation. */
24379 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
24381 * The HW will be configured with local loopback such that
24382 * host data is sent back to the host without modification.
24384 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
24386 * The HW will be configured with remote loopback such that
24387 * port logic will send packets back out the transmitter that
24390 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
24392 * The HW will be configured with external loopback such that
24393 * host data is sent on the transmitter and based on the external
24394 * loopback connection the data will be received without modification.
24396 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
24397 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
24398 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
24400 * This value is used to configure the pause that will be
24401 * used for force mode.
24403 uint8_t force_pause;
24405 * When this bit is '1', Generation of tx pause messages
24406 * is supported. Disabled otherwise.
24408 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
24410 * When this bit is '1', Reception of rx pause messages
24411 * is supported. Disabled otherwise.
24413 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
24416 * This value controls the pre-emphasis to be used for the
24417 * link. Driver should not set this value (use
24418 * enable.preemphasis = 0) unless driver is sure of setting.
24419 * Normally HWRM FW will determine proper pre-emphasis.
24421 uint32_t preemphasis;
24423 * Setting for link speed mask that is used to
24424 * advertise speeds during autonegotiation when EEE is enabled.
24425 * This field is valid only when EEE is enabled.
24426 * The speeds specified in this field shall be a subset of
24427 * speeds specified in auto_link_speed_mask.
24428 * If EEE is enabled,then at least one speed shall be provided
24431 uint16_t eee_link_speed_mask;
24433 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
24435 /* 100Mb link speed (Full-duplex) */
24436 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
24439 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
24441 /* 1Gb link speed (Full-duplex) */
24442 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
24445 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
24448 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
24450 /* 10Gb link speed */
24451 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
24454 * This is the speed that will be used if the force and force_pam4
24455 * bits are '1'. If unsupported speed is selected, an error
24456 * will be generated.
24458 uint16_t force_pam4_link_speed;
24459 /* 50Gb link speed */
24460 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
24462 /* 100Gb link speed */
24463 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
24465 /* 200Gb link speed */
24466 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
24468 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
24469 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
24471 * Requested setting of TX LPI timer in microseconds.
24472 * This field is valid only when EEE is enabled and TX LPI is
24475 uint32_t tx_lpi_timer;
24476 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
24477 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
24478 /* This field specifies which PAM4 speeds are enabled for auto mode. */
24479 uint16_t auto_link_pam4_speed_mask;
24480 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
24482 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
24484 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
24486 uint8_t unused_2[2];
24489 /* hwrm_port_phy_cfg_output (size:128b/16B) */
24490 struct hwrm_port_phy_cfg_output {
24491 /* The specific error status for the command. */
24492 uint16_t error_code;
24493 /* The HWRM command request type. */
24495 /* The sequence ID from the original command. */
24497 /* The length of the response data in number of bytes. */
24499 uint8_t unused_0[7];
24501 * This field is used in Output records to indicate that the output
24502 * is completely written to RAM. This field should be read as '1'
24503 * to indicate that the output has been completely written.
24504 * When writing a command completion or response to an internal processor,
24505 * the order of writes has to be such that this field is written last.
24510 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
24511 struct hwrm_port_phy_cfg_cmd_err {
24513 * command specific error codes that goes to
24514 * the cmd_err field in Common HWRM Error Response.
24517 /* Unknown error */
24518 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24519 /* Unable to complete operation due to invalid speed */
24520 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
24522 * retry the command since the phy is not ready.
24523 * retry count is returned in opaque_0.
24524 * This is only valid for the first command and
24525 * this value will not change for successive calls.
24526 * but if a 0 is returned at any time then this should
24527 * be treated as an un recoverable failure,
24529 * retry interval in milli seconds is returned in opaque_1.
24530 * This specifies the time that user should wait before
24531 * issuing the next port_phy_cfg command.
24533 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
24534 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
24535 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
24536 uint8_t unused_0[7];
24539 /**********************
24540 * hwrm_port_phy_qcfg *
24541 **********************/
24544 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
24545 struct hwrm_port_phy_qcfg_input {
24546 /* The HWRM command request type. */
24549 * The completion ring to send the completion event on. This should
24550 * be the NQ ID returned from the `nq_alloc` HWRM command.
24552 uint16_t cmpl_ring;
24554 * The sequence ID is used by the driver for tracking multiple
24555 * commands. This ID is treated as opaque data by the firmware and
24556 * the value is returned in the `hwrm_resp_hdr` upon completion.
24560 * The target ID of the command:
24561 * * 0x0-0xFFF8 - The function ID
24562 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24563 * * 0xFFFD - Reserved for user-space HWRM interface
24566 uint16_t target_id;
24568 * A physical address pointer pointing to a host buffer that the
24569 * command's response data will be written. This can be either a host
24570 * physical address (HPA) or a guest physical address (GPA) and must
24571 * point to a physically contiguous block of memory.
24573 uint64_t resp_addr;
24574 /* Port ID of port that is to be queried. */
24576 uint8_t unused_0[6];
24579 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
24580 struct hwrm_port_phy_qcfg_output {
24581 /* The specific error status for the command. */
24582 uint16_t error_code;
24583 /* The HWRM command request type. */
24585 /* The sequence ID from the original command. */
24587 /* The length of the response data in number of bytes. */
24589 /* This value indicates the current link status. */
24591 /* There is no link or cable detected. */
24592 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
24593 /* There is no link, but a cable has been detected. */
24594 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
24595 /* There is a link. */
24596 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
24597 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
24598 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
24599 uint8_t active_fec_signal_mode;
24601 * This value indicates the current link signaling mode of the
24604 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
24606 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
24607 /* NRZ signaling */
24608 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
24610 /* PAM4 signaling */
24611 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
24613 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
24614 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
24615 /* This value indicates the current active FEC mode. */
24616 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
24618 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
24619 /* No active FEC */
24620 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
24621 (UINT32_C(0x0) << 4)
24622 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
24623 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
24624 (UINT32_C(0x1) << 4)
24625 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
24626 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
24627 (UINT32_C(0x2) << 4)
24628 /* FEC RS544_1XN active, autonegoatiated or forced. */
24629 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
24630 (UINT32_C(0x3) << 4)
24631 /* FEC RS(544,528) active, autonegoatiated or forced. */
24632 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
24633 (UINT32_C(0x4) << 4)
24634 /* FEC RS272_1XN active, autonegotiated or forced. */
24635 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
24636 (UINT32_C(0x5) << 4)
24637 /* FEC RS(272,257) active, autonegoatiated or forced. */
24638 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
24639 (UINT32_C(0x6) << 4)
24640 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
24641 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
24643 * This value indicates the current link speed of the connection.
24644 * The signal_mode field indicates if the link is using
24645 * NRZ or PAM4 signaling.
24647 uint16_t link_speed;
24648 /* 100Mb link speed */
24649 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
24650 /* 1Gb link speed */
24651 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
24652 /* 2Gb link speed */
24653 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
24654 /* 25Gb link speed */
24655 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
24656 /* 10Gb link speed */
24657 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
24658 /* 20Mb link speed */
24659 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
24660 /* 25Gb link speed */
24661 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
24662 /* 40Gb link speed */
24663 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
24664 /* 50Gb link speed */
24665 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
24666 /* 100Gb link speed */
24667 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
24668 /* 200Gb link speed */
24669 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
24670 /* 10Mb link speed */
24671 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
24672 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
24673 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
24675 * This value is indicates the duplex of the current
24678 uint8_t duplex_cfg;
24679 /* Half Duplex connection. */
24680 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
24681 /* Full duplex connection. */
24682 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
24683 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
24684 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
24686 * This value is used to indicate the current
24687 * pause configuration. When autoneg is enabled, this value
24688 * represents the autoneg results of pause configuration.
24692 * When this bit is '1', Generation of tx pause messages
24693 * is supported. Disabled otherwise.
24695 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
24697 * When this bit is '1', Reception of rx pause messages
24698 * is supported. Disabled otherwise.
24700 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
24702 * The supported speeds for the port. This is a bit mask.
24703 * For each speed that is supported, the corresponding
24704 * bit will be set to '1'.
24706 uint16_t support_speeds;
24707 /* 100Mb link speed (Half-duplex) */
24708 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
24710 /* 100Mb link speed (Full-duplex) */
24711 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
24713 /* 1Gb link speed (Half-duplex) */
24714 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
24716 /* 1Gb link speed (Full-duplex) */
24717 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
24719 /* 2Gb link speed */
24720 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
24722 /* 25Gb link speed */
24723 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
24725 /* 10Gb link speed */
24726 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
24728 /* 20Gb link speed */
24729 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
24731 /* 25Gb link speed */
24732 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
24734 /* 40Gb link speed */
24735 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
24737 /* 50Gb link speed */
24738 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
24740 /* 100Gb link speed */
24741 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
24743 /* 10Mb link speed (Half-duplex) */
24744 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
24746 /* 10Mb link speed (Full-duplex) */
24747 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
24750 * Current setting of forced link speed.
24751 * When the link speed is not being forced, this
24752 * value shall be set to 0.
24754 uint16_t force_link_speed;
24755 /* 100Mb link speed */
24756 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
24757 /* 1Gb link speed */
24758 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
24759 /* 2Gb link speed */
24760 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
24761 /* 25Gb link speed */
24762 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
24763 /* 10Gb link speed */
24764 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
24765 /* 20Mb link speed */
24766 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
24767 /* 25Gb link speed */
24768 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
24769 /* 40Gb link speed */
24770 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
24772 /* 50Gb link speed */
24773 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
24775 /* 100Gb link speed */
24776 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
24778 /* 10Mb link speed */
24779 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
24781 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
24782 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
24783 /* Current setting of auto negotiation mode. */
24785 /* Disable autoneg or autoneg disabled. No speeds are selected. */
24786 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
24787 /* Select all possible speeds for autoneg mode. */
24788 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
24790 * Select only the auto_link_speed speed for autoneg mode. This mode has
24791 * been DEPRECATED. An HWRM client should not use this mode.
24793 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
24795 * Select the auto_link_speed or any speed below that speed for autoneg.
24796 * This mode has been DEPRECATED. An HWRM client should not use this mode.
24798 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
24800 * Select the speeds based on the corresponding link speed mask value
24801 * that is provided.
24803 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
24804 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
24805 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
24807 * Current setting of pause autonegotiation.
24808 * Move autoneg_pause flag here.
24810 uint8_t auto_pause;
24812 * When this bit is '1', Generation of tx pause messages
24813 * has been requested. Disabled otherwise.
24815 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
24818 * When this bit is '1', Reception of rx pause messages
24819 * has been requested. Disabled otherwise.
24821 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
24824 * When set to 1, the advertisement of pause is enabled.
24826 * # When the auto_mode is not set to none and this flag is
24827 * set to 1, then the auto_pause bits on this port are being
24828 * advertised and autoneg pause results are being interpreted.
24829 * # When the auto_mode is not set to none and this
24830 * flag is set to 0, the pause is forced as indicated in
24831 * force_pause, and also advertised as auto_pause bits, but
24832 * the autoneg results are not interpreted since the pause
24833 * configuration is being forced.
24834 * # When the auto_mode is set to none and this flag is set to
24835 * 1, auto_pause bits should be ignored and should be set to 0.
24837 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
24840 * Current setting for auto_link_speed. This field is only
24841 * valid when auto_mode is set to "one_speed" or "one_or_below".
24843 uint16_t auto_link_speed;
24844 /* 100Mb link speed */
24845 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
24846 /* 1Gb link speed */
24847 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
24848 /* 2Gb link speed */
24849 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
24850 /* 25Gb link speed */
24851 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
24852 /* 10Gb link speed */
24853 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
24854 /* 20Mb link speed */
24855 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
24856 /* 25Gb link speed */
24857 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
24858 /* 40Gb link speed */
24859 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
24860 /* 50Gb link speed */
24861 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
24862 /* 100Gb link speed */
24863 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
24864 /* 10Mb link speed */
24865 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
24867 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
24868 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
24870 * Current setting for auto_link_speed_mask that is used to
24871 * advertise speeds during autonegotiation.
24872 * This field is only valid when auto_mode is set to "mask".
24873 * The speeds specified in this field shall be a subset of
24874 * supported speeds on this port.
24876 uint16_t auto_link_speed_mask;
24877 /* 100Mb link speed (Half-duplex) */
24878 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
24880 /* 100Mb link speed (Full-duplex) */
24881 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
24883 /* 1Gb link speed (Half-duplex) */
24884 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
24886 /* 1Gb link speed (Full-duplex) */
24887 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
24889 /* 2Gb link speed */
24890 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
24892 /* 25Gb link speed */
24893 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
24895 /* 10Gb link speed */
24896 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
24898 /* 20Gb link speed */
24899 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
24901 /* 25Gb link speed */
24902 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
24904 /* 40Gb link speed */
24905 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
24907 /* 50Gb link speed */
24908 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
24910 /* 100Gb link speed */
24911 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
24913 /* 10Mb link speed (Half-duplex) */
24914 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
24916 /* 10Mb link speed (Full-duplex) */
24917 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
24919 /* Current setting for wirespeed. */
24921 /* Wirespeed feature is disabled. */
24922 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
24923 /* Wirespeed feature is enabled. */
24924 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
24925 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
24926 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
24927 /* Current setting for loopback. */
24929 /* No loopback is selected. Normal operation. */
24930 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
24932 * The HW will be configured with local loopback such that
24933 * host data is sent back to the host without modification.
24935 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
24937 * The HW will be configured with remote loopback such that
24938 * port logic will send packets back out the transmitter that
24941 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
24943 * The HW will be configured with external loopback such that
24944 * host data is sent on the transmitter and based on the external
24945 * loopback connection the data will be received without modification.
24947 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
24948 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
24949 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
24951 * Current setting of forced pause.
24952 * When the pause configuration is not being forced, then
24953 * this value shall be set to 0.
24955 uint8_t force_pause;
24957 * When this bit is '1', Generation of tx pause messages
24958 * is supported. Disabled otherwise.
24960 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
24962 * When this bit is '1', Reception of rx pause messages
24963 * is supported. Disabled otherwise.
24965 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
24967 * This value indicates the current status of the optics module on
24970 uint8_t module_status;
24971 /* Module is inserted and accepted */
24972 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
24974 /* Module is rejected and transmit side Laser is disabled. */
24975 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
24977 /* Module mismatch warning. */
24978 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
24980 /* Module is rejected and powered down. */
24981 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
24983 /* Module is not inserted. */
24984 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
24986 /* Module is powered down because of over current fault. */
24987 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
24989 /* Module status is not applicable. */
24990 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
24992 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
24993 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
24994 /* Current setting for preemphasis. */
24995 uint32_t preemphasis;
24996 /* This field represents the major version of the PHY. */
24998 /* This field represents the minor version of the PHY. */
25000 /* This field represents the build version of the PHY. */
25002 /* This value represents a PHY type. */
25005 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
25008 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
25010 /* BASE-KR4 (Deprecated) */
25011 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
25014 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
25017 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
25019 /* BASE-KR2 (Deprecated) */
25020 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
25023 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
25026 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
25029 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
25031 /* EEE capable BASE-T */
25032 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
25034 /* SGMII connected external PHY */
25035 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
25037 /* 25G_BASECR_CA_L */
25038 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
25040 /* 25G_BASECR_CA_S */
25041 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
25043 /* 25G_BASECR_CA_N */
25044 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
25047 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
25050 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
25053 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
25056 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
25059 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
25061 /* 100G_BASESR10 */
25062 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
25065 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
25068 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
25071 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
25074 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
25076 /* 40G_ACTIVE_CABLE */
25077 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
25080 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
25083 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
25086 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
25089 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
25092 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
25095 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
25098 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
25101 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \
25104 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \
25107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \
25110 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \
25113 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \
25116 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \
25119 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \
25122 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \
25124 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
25125 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2
25126 /* This value represents a media type. */
25127 uint8_t media_type;
25129 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
25131 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
25132 /* Direct Attached Copper */
25133 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
25135 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
25136 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
25137 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
25138 /* This value represents a transceiver type. */
25139 uint8_t xcvr_pkg_type;
25140 /* PHY and MAC are in the same package */
25141 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
25143 /* PHY and MAC are in different packages */
25144 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
25146 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
25147 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
25148 uint8_t eee_config_phy_addr;
25149 /* This field represents PHY address. */
25150 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
25152 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
25154 * This field represents flags related to EEE configuration.
25155 * These EEE configuration flags are valid only when the
25156 * auto_mode is not set to none (in other words autonegotiation
25159 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
25161 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
25163 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
25164 * Speeds for autoneg with EEE mode enabled
25165 * are based on eee_link_speed_mask.
25167 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
25170 * This flag is valid only when eee_enabled is set to 1.
25172 * # If eee_enabled is set to 0, then EEE mode is disabled
25173 * and this flag shall be ignored.
25174 * # If eee_enabled is set to 1 and this flag is set to 1,
25175 * then Energy Efficient Ethernet (EEE) mode is enabled
25177 * # If eee_enabled is set to 1 and this flag is set to 0,
25178 * then Energy Efficient Ethernet (EEE) mode is enabled
25179 * but is currently not in use.
25181 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
25184 * This flag is valid only when eee_enabled is set to 1.
25186 * # If eee_enabled is set to 0, then EEE mode is disabled
25187 * and this flag shall be ignored.
25188 * # If eee_enabled is set to 1 and this flag is set to 1,
25189 * then Energy Efficient Ethernet (EEE) mode is enabled
25190 * and TX LPI is enabled.
25191 * # If eee_enabled is set to 1 and this flag is set to 0,
25192 * then Energy Efficient Ethernet (EEE) mode is enabled
25193 * but TX LPI is disabled.
25195 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
25198 * When set to 1, the parallel detection is used to determine
25199 * the speed of the link partner.
25201 * Parallel detection is used when a autonegotiation capable
25202 * device is connected to a link partner that is not capable
25203 * of autonegotiation.
25205 uint8_t parallel_detect;
25207 * When set to 1, the parallel detection is used to determine
25208 * the speed of the link partner.
25210 * Parallel detection is used when a autonegotiation capable
25211 * device is connected to a link partner that is not capable
25212 * of autonegotiation.
25214 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
25216 * The advertised speeds for the port by the link partner.
25217 * Each advertised speed will be set to '1'.
25219 uint16_t link_partner_adv_speeds;
25220 /* 100Mb link speed (Half-duplex) */
25221 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
25223 /* 100Mb link speed (Full-duplex) */
25224 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
25226 /* 1Gb link speed (Half-duplex) */
25227 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
25229 /* 1Gb link speed (Full-duplex) */
25230 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
25232 /* 2Gb link speed */
25233 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
25235 /* 25Gb link speed */
25236 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
25238 /* 10Gb link speed */
25239 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
25241 /* 20Gb link speed */
25242 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
25244 /* 25Gb link speed */
25245 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
25247 /* 40Gb link speed */
25248 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
25250 /* 50Gb link speed */
25251 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
25253 /* 100Gb link speed */
25254 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
25256 /* 10Mb link speed (Half-duplex) */
25257 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
25259 /* 10Mb link speed (Full-duplex) */
25260 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
25263 * The advertised autoneg for the port by the link partner.
25264 * This field is deprecated and should be set to 0.
25266 uint8_t link_partner_adv_auto_mode;
25267 /* Disable autoneg or autoneg disabled. No speeds are selected. */
25268 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
25270 /* Select all possible speeds for autoneg mode. */
25271 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
25274 * Select only the auto_link_speed speed for autoneg mode. This mode has
25275 * been DEPRECATED. An HWRM client should not use this mode.
25277 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
25280 * Select the auto_link_speed or any speed below that speed for autoneg.
25281 * This mode has been DEPRECATED. An HWRM client should not use this mode.
25283 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
25286 * Select the speeds based on the corresponding link speed mask value
25287 * that is provided.
25289 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
25291 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
25292 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
25293 /* The advertised pause settings on the port by the link partner. */
25294 uint8_t link_partner_adv_pause;
25296 * When this bit is '1', Generation of tx pause messages
25297 * is supported. Disabled otherwise.
25299 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
25302 * When this bit is '1', Reception of rx pause messages
25303 * is supported. Disabled otherwise.
25305 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
25308 * Current setting for link speed mask that is used to
25309 * advertise speeds during autonegotiation when EEE is enabled.
25310 * This field is valid only when eee_enabled flags is set to 1.
25311 * The speeds specified in this field shall be a subset of
25312 * speeds specified in auto_link_speed_mask.
25314 uint16_t adv_eee_link_speed_mask;
25316 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
25318 /* 100Mb link speed (Full-duplex) */
25319 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
25322 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
25324 /* 1Gb link speed (Full-duplex) */
25325 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
25328 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
25331 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
25333 /* 10Gb link speed */
25334 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
25337 * Current setting for link speed mask that is advertised by
25338 * the link partner when EEE is enabled.
25339 * This field is valid only when eee_enabled flags is set to 1.
25341 uint16_t link_partner_adv_eee_link_speed_mask;
25343 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
25345 /* 100Mb link speed (Full-duplex) */
25346 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
25349 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
25351 /* 1Gb link speed (Full-duplex) */
25352 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
25355 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
25358 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
25360 /* 10Gb link speed */
25361 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
25363 uint32_t xcvr_identifier_type_tx_lpi_timer;
25365 * Current setting of TX LPI timer in microseconds.
25366 * This field is valid only when_eee_enabled flag is set to 1
25367 * and tx_lpi_enabled is set to 1.
25369 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
25371 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
25372 /* This value represents transceiver identifier type. */
25373 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
25374 UINT32_C(0xff000000)
25375 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
25377 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
25378 (UINT32_C(0x0) << 24)
25379 /* SFP/SFP+/SFP28 */
25380 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
25381 (UINT32_C(0x3) << 24)
25383 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
25384 (UINT32_C(0xc) << 24)
25386 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
25387 (UINT32_C(0xd) << 24)
25389 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
25390 (UINT32_C(0x11) << 24)
25391 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
25392 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
25394 * This value represents the current configuration of
25395 * Forward Error Correction (FEC) on the port.
25399 * When set to 1, then FEC is not supported on this port. If this flag
25400 * is set to 1, then all other FEC configuration flags shall be ignored.
25401 * When set to 0, then FEC is supported as indicated by other
25402 * configuration flags.
25404 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
25407 * When set to 1, then FEC autonegotiation is supported on this port.
25408 * When set to 0, then FEC autonegotiation is not supported on this port.
25410 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
25413 * When set to 1, then FEC autonegotiation is enabled on this port.
25414 * When set to 0, then FEC autonegotiation is disabled if supported.
25415 * This flag should be ignored if FEC autonegotiation is not supported on this port.
25417 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
25420 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
25421 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
25423 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
25426 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
25427 * port. This means that FEC CLAUSE 74 is either advertised if
25428 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
25429 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
25430 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
25432 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
25435 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
25436 * NRZ) is supported on this port.
25437 * When set to 0, then FEC RS(528,418) is not supported on this port.
25439 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
25442 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
25443 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
25444 * either advertised if FEC autonegotiation is enabled or FEC
25445 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
25446 * is disabled if supported.
25447 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
25449 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
25452 * When set to 1, then FEC RS544_1XN is supported on this port.
25453 * When set to 0, then FEC RS544_1XN is not supported on this port.
25455 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
25458 * When set to 1, then RS544_1XN is enabled on this
25459 * port. This means that FEC RS544_1XN is either advertised if
25460 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
25461 * When set to 0, then FEC RS544_1XN is disabled if supported.
25462 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
25464 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
25467 * When set to 1, then FEC RS(544,514) is supported on this port.
25468 * When set to 0, then FEC RS(544,514) is not supported on this port.
25470 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
25473 * When set to 1, then RS(544,514) is enabled on this
25474 * port. This means that FEC RS(544,514) is either advertised if
25475 * FEC autonegotiation is enabled or FEC RS(544,514) is force
25476 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
25477 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
25479 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
25482 * When set to 1, then FEC RS272_1XN is supported on this port.
25483 * When set to 0, then FEC RS272_1XN is not supported on this port.
25485 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
25488 * When set to 1, then RS272_1XN is enabled on this
25489 * port. This means that FEC RS272_1XN is either advertised if
25490 * FEC autonegotiation is enabled or FEC RS272_1XN is force
25491 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
25492 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
25494 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
25497 * When set to 1, then FEC RS(272,514) is supported on this port.
25498 * When set to 0, then FEC RS(272,514) is not supported on this port.
25500 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
25503 * When set to 1, then RS(272,257) is enabled on this
25504 * port. This means that FEC RS(272,257) is either advertised if
25505 * FEC autonegotiation is enabled or FEC RS(272,257) is force
25506 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
25507 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
25509 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
25512 * This value is indicates the duplex of the current
25513 * connection state.
25515 uint8_t duplex_state;
25516 /* Half Duplex connection. */
25517 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
25518 /* Full duplex connection. */
25519 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
25520 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
25521 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
25522 /* Option flags fields. */
25523 uint8_t option_flags;
25524 /* When this bit is '1', Media auto detect is enabled. */
25525 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
25528 * When this bit is '1', active_fec_signal_mode can be
25531 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
25534 * Up to 16 bytes of null padded ASCII string representing
25536 * If the string is set to null, then the vendor name is not
25539 char phy_vendor_name[16];
25541 * Up to 16 bytes of null padded ASCII string that
25542 * identifies vendor specific part number of the PHY.
25543 * If the string is set to null, then the vendor specific
25544 * part number is not available.
25546 char phy_vendor_partnumber[16];
25548 * The supported PAM4 speeds for the port. This is a bit mask.
25549 * For each speed that is supported, the corresponding
25550 * bit will be set to '1'.
25552 uint16_t support_pam4_speeds;
25553 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
25555 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
25557 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
25560 * Current setting of forced PAM4 link speed.
25561 * When the link speed is not being forced, this
25562 * value shall be set to 0.
25564 uint16_t force_pam4_link_speed;
25565 /* 50Gb link speed */
25566 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
25568 /* 100Gb link speed */
25569 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
25571 /* 200Gb link speed */
25572 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
25574 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
25575 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
25577 * Current setting for auto_pam4_link_speed_mask that is used to
25578 * advertise speeds during autonegotiation.
25579 * This field is only valid when auto_mode is set to "mask".
25580 * The speeds specified in this field shall be a subset of
25581 * supported speeds on this port.
25583 uint16_t auto_pam4_link_speed_mask;
25584 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
25586 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
25588 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
25591 * The advertised PAM4 speeds for the port by the link partner.
25592 * Each advertised speed will be set to '1'.
25594 uint8_t link_partner_pam4_adv_speeds;
25595 /* 50Gb link speed */
25596 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
25598 /* 100Gb link speed */
25599 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
25601 /* 200Gb link speed */
25602 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
25605 * This field is used in Output records to indicate that the output
25606 * is completely written to RAM. This field should be read as '1'
25607 * to indicate that the output has been completely written.
25608 * When writing a command completion or response to an internal processor,
25609 * the order of writes has to be such that this field is written last.
25614 /*********************
25615 * hwrm_port_mac_cfg *
25616 *********************/
25619 /* hwrm_port_mac_cfg_input (size:448b/56B) */
25620 struct hwrm_port_mac_cfg_input {
25621 /* The HWRM command request type. */
25624 * The completion ring to send the completion event on. This should
25625 * be the NQ ID returned from the `nq_alloc` HWRM command.
25627 uint16_t cmpl_ring;
25629 * The sequence ID is used by the driver for tracking multiple
25630 * commands. This ID is treated as opaque data by the firmware and
25631 * the value is returned in the `hwrm_resp_hdr` upon completion.
25635 * The target ID of the command:
25636 * * 0x0-0xFFF8 - The function ID
25637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25638 * * 0xFFFD - Reserved for user-space HWRM interface
25641 uint16_t target_id;
25643 * A physical address pointer pointing to a host buffer that the
25644 * command's response data will be written. This can be either a host
25645 * physical address (HPA) or a guest physical address (GPA) and must
25646 * point to a physically contiguous block of memory.
25648 uint64_t resp_addr;
25650 * In this field, there are a number of CoS mappings related flags
25651 * that are used to configure CoS mappings and their corresponding
25652 * priorities in the hardware.
25653 * For the priorities of CoS mappings, the HWRM uses the following
25654 * priority order (high to low) by default:
25657 * # tunnel_vlan_pri
25660 * A subset of CoS mappings can be enabled.
25661 * If a priority is not specified for an enabled CoS mapping, the
25662 * priority will be assigned in the above order for the enabled CoS
25663 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
25664 * enabled and their priorities are not specified, the following
25665 * priority order (high to low) will be used by the HWRM:
25670 * vlan_pri CoS mapping together with default CoS with lower priority
25671 * are enabled by default by the HWRM.
25675 * When this bit is '1', this command will configure
25676 * the MAC to match the current link state of the PHY.
25677 * If the link is not established on the PHY, then this
25678 * bit has no effect.
25680 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
25683 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
25684 * is requested to be enabled.
25686 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
25689 * When this bit is set to '1', tunnel VLAN PRI field to
25690 * CoS mapping is requested to be enabled.
25692 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
25695 * When this bit is set to '1', the IP DSCP to CoS mapping is
25696 * requested to be enabled.
25698 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
25701 * When this bit is '1', the HWRM is requested to
25702 * enable timestamp capture capability on the receive side
25705 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
25708 * When this bit is '1', the HWRM is requested to
25709 * disable timestamp capture capability on the receive side
25712 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
25715 * When this bit is '1', the HWRM is requested to
25716 * enable timestamp capture capability on the transmit side
25719 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
25722 * When this bit is '1', the HWRM is requested to
25723 * disable timestamp capture capability on the transmit side
25726 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
25729 * When this bit is '1', the Out-Of-Box WoL is requested to
25730 * be enabled on this port.
25732 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
25735 * When this bit is '1', the Out-Of-Box WoL is requested to
25736 * be disabled on this port.
25738 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
25741 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
25742 * is requested to be disabled.
25744 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
25747 * When this bit is set to '1', tunnel VLAN PRI field to
25748 * CoS mapping is requested to be disabled.
25750 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
25753 * When this bit is set to '1', the IP DSCP to CoS mapping is
25754 * requested to be disabled.
25756 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
25759 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
25760 * bit is set, then the device uses one step Tx timestamping.
25761 * This bit is temporary and used for experimental purposes.
25763 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
25766 * When this bit is '1', the controller is requested to enable
25767 * timestamp capture capability on all packets (not just PTP)
25768 * of the receive side of this port.
25770 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE \
25773 * When this bit is '1', the controller is requested to disable
25774 * timestamp capture capability on all packets (not just PTP)
25775 * of the receive side of this port.
25777 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE \
25781 * This bit must be '1' for the ipg field to be
25784 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
25787 * This bit must be '1' for the lpbk field to be
25790 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
25793 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
25796 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
25799 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
25802 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
25805 * This bit must be '1' for the dscp2cos_map_pri field to be
25808 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
25811 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
25814 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
25817 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
25820 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
25823 * This bit must be '1' for the cos_field_cfg field to be
25826 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
25829 * This bit must be '1' for the ptp_freq_adj_ppb field to be
25832 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
25835 * This bit must be '1' for the ptp_adj_phase field to be
25838 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \
25840 /* Port ID of port that is to be configured. */
25843 * This value is used to configure the minimum IPG that will
25844 * be sent between packets by this port.
25847 /* This value controls the loopback setting for the MAC. */
25849 /* No loopback is selected. Normal operation. */
25850 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
25852 * The HW will be configured with local loopback such that
25853 * host data is sent back to the host without modification.
25855 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
25857 * The HW will be configured with remote loopback such that
25858 * port logic will send packets back out the transmitter that
25861 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
25862 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
25863 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
25865 * This value controls the priority setting of VLAN PRI to CoS
25866 * mapping based on VLAN Tags of inner packet headers of
25867 * tunneled packets or packet headers of non-tunneled packets.
25869 * # Each XXX_pri variable shall have a unique priority value
25870 * when it is being specified.
25871 * # When comparing priorities of mappings, higher value
25872 * indicates higher priority.
25873 * For example, a value of 0-3 is returned where 0 is being
25874 * the lowest priority and 3 is being the highest priority.
25876 uint8_t vlan_pri2cos_map_pri;
25877 /* Reserved field. */
25880 * This value controls the priority setting of VLAN PRI to CoS
25881 * mapping based on VLAN Tags of tunneled header.
25882 * This mapping only applies when tunneled headers
25885 * # Each XXX_pri variable shall have a unique priority value
25886 * when it is being specified.
25887 * # When comparing priorities of mappings, higher value
25888 * indicates higher priority.
25889 * For example, a value of 0-3 is returned where 0 is being
25890 * the lowest priority and 3 is being the highest priority.
25892 uint8_t tunnel_pri2cos_map_pri;
25894 * This value controls the priority setting of IP DSCP to CoS
25895 * mapping based on inner IP header of tunneled packets or
25896 * IP header of non-tunneled packets.
25898 * # Each XXX_pri variable shall have a unique priority value
25899 * when it is being specified.
25900 * # When comparing priorities of mappings, higher value
25901 * indicates higher priority.
25902 * For example, a value of 0-3 is returned where 0 is being
25903 * the lowest priority and 3 is being the highest priority.
25905 uint8_t dscp2pri_map_pri;
25907 * This is a 16-bit bit mask that is used to request a
25908 * specific configuration of time stamp capture of PTP messages
25909 * on the receive side of this port.
25910 * This field shall be ignored if the ptp_rx_ts_capture_enable
25911 * flag is not set in this command.
25912 * Otherwise, if bit 'i' is set, then the HWRM is being
25913 * requested to configure the receive side of the port to
25914 * capture the time stamp of every received PTP message
25915 * with messageType field value set to i.
25917 uint16_t rx_ts_capture_ptp_msg_type;
25919 * This is a 16-bit bit mask that is used to request a
25920 * specific configuration of time stamp capture of PTP messages
25921 * on the transmit side of this port.
25922 * This field shall be ignored if the ptp_tx_ts_capture_enable
25923 * flag is not set in this command.
25924 * Otherwise, if bit 'i' is set, then the HWRM is being
25925 * requested to configure the transmit side of the port to
25926 * capture the time stamp of every transmitted PTP message
25927 * with messageType field value set to i.
25929 uint16_t tx_ts_capture_ptp_msg_type;
25930 /* Configuration of CoS fields. */
25931 uint8_t cos_field_cfg;
25933 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
25936 * This field is used to specify selection of VLAN PRI value
25937 * based on whether one or two VLAN Tags are present in
25938 * the inner packet headers of tunneled packets or
25939 * non-tunneled packets.
25940 * This field is valid only if inner VLAN PRI to CoS mapping
25942 * If VLAN PRI to CoS mapping is not enabled, then this
25943 * field shall be ignored.
25945 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
25947 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
25950 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
25951 * present in the inner packet headers
25953 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
25954 (UINT32_C(0x0) << 1)
25956 * Select outer VLAN Tag PRI when 2 VLAN Tags are
25957 * present in the inner packet headers.
25958 * No VLAN PRI shall be selected for this configuration
25959 * if only one VLAN Tag is present in the inner
25962 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
25963 (UINT32_C(0x1) << 1)
25965 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
25966 * are present in the inner packet headers
25968 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
25969 (UINT32_C(0x2) << 1)
25971 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
25972 (UINT32_C(0x3) << 1)
25973 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
25974 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
25976 * This field is used to specify selection of tunnel VLAN
25977 * PRI value based on whether one or two VLAN Tags are
25978 * present in tunnel headers.
25979 * This field is valid only if tunnel VLAN PRI to CoS mapping
25981 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
25982 * field shall be ignored.
25984 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
25986 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
25989 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
25990 * present in the tunnel packet headers
25992 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
25993 (UINT32_C(0x0) << 3)
25995 * Select outer VLAN Tag PRI when 2 VLAN Tags are
25996 * present in the tunnel packet headers.
25997 * No tunnel VLAN PRI shall be selected for this
25998 * configuration if only one VLAN Tag is present in
25999 * the tunnel packet headers.
26001 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
26002 (UINT32_C(0x1) << 3)
26004 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
26005 * are present in the tunnel packet headers
26007 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
26008 (UINT32_C(0x2) << 3)
26010 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
26011 (UINT32_C(0x3) << 3)
26012 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
26013 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
26015 * This field shall be used to provide default CoS value
26016 * that has been configured on this port.
26017 * This field is valid only if default CoS mapping
26019 * If default CoS mapping is not enabled, then this
26020 * field shall be ignored.
26022 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
26024 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
26026 uint8_t unused_0[3];
26028 * This signed field specifies by how much to adjust the frequency
26029 * of sync timer updates (measured in parts per billion).
26031 int32_t ptp_freq_adj_ppb;
26032 uint8_t unused_1[4];
26034 * This unsigned field specifies the phase offset to be applied
26035 * to the PHC (PTP Hardware Clock). This field is specified in
26038 int64_t ptp_adj_phase;
26041 /* hwrm_port_mac_cfg_output (size:128b/16B) */
26042 struct hwrm_port_mac_cfg_output {
26043 /* The specific error status for the command. */
26044 uint16_t error_code;
26045 /* The HWRM command request type. */
26047 /* The sequence ID from the original command. */
26049 /* The length of the response data in number of bytes. */
26052 * This is the configured maximum length of Ethernet packet
26053 * payload that is allowed to be received on the port.
26054 * This value does not include the number of bytes used by
26055 * Ethernet header and trailer (CRC).
26059 * This is the configured maximum length of Ethernet packet
26060 * payload that is allowed to be transmitted on the port.
26061 * This value does not include the number of bytes used by
26062 * Ethernet header and trailer (CRC).
26065 /* Current configuration of the IPG value. */
26067 /* Current value of the loopback value. */
26069 /* No loopback is selected. Normal operation. */
26070 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
26072 * The HW will be configured with local loopback such that
26073 * host data is sent back to the host without modification.
26075 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
26077 * The HW will be configured with remote loopback such that
26078 * port logic will send packets back out the transmitter that
26081 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
26082 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
26083 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
26086 * This field is used in Output records to indicate that the output
26087 * is completely written to RAM. This field should be read as '1'
26088 * to indicate that the output has been completely written.
26089 * When writing a command completion or response to an internal processor,
26090 * the order of writes has to be such that this field is written last.
26095 /**********************
26096 * hwrm_port_mac_qcfg *
26097 **********************/
26100 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
26101 struct hwrm_port_mac_qcfg_input {
26102 /* The HWRM command request type. */
26105 * The completion ring to send the completion event on. This should
26106 * be the NQ ID returned from the `nq_alloc` HWRM command.
26108 uint16_t cmpl_ring;
26110 * The sequence ID is used by the driver for tracking multiple
26111 * commands. This ID is treated as opaque data by the firmware and
26112 * the value is returned in the `hwrm_resp_hdr` upon completion.
26116 * The target ID of the command:
26117 * * 0x0-0xFFF8 - The function ID
26118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26119 * * 0xFFFD - Reserved for user-space HWRM interface
26122 uint16_t target_id;
26124 * A physical address pointer pointing to a host buffer that the
26125 * command's response data will be written. This can be either a host
26126 * physical address (HPA) or a guest physical address (GPA) and must
26127 * point to a physically contiguous block of memory.
26129 uint64_t resp_addr;
26130 /* Port ID of port that is to be configured. */
26132 uint8_t unused_0[6];
26135 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
26136 struct hwrm_port_mac_qcfg_output {
26137 /* The specific error status for the command. */
26138 uint16_t error_code;
26139 /* The HWRM command request type. */
26141 /* The sequence ID from the original command. */
26143 /* The length of the response data in number of bytes. */
26146 * This is the configured maximum length of Ethernet packet
26147 * payload that is allowed to be received on the port.
26148 * This value does not include the number of bytes used by the
26149 * Ethernet header and trailer (CRC).
26153 * This is the configured maximum length of Ethernet packet
26154 * payload that is allowed to be transmitted on the port.
26155 * This value does not include the number of bytes used by the
26156 * Ethernet header and trailer (CRC).
26160 * The minimum IPG that will
26161 * be sent between packets by this port.
26164 /* The loopback setting for the MAC. */
26166 /* No loopback is selected. Normal operation. */
26167 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
26169 * The HW will be configured with local loopback such that
26170 * host data is sent back to the host without modification.
26172 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
26174 * The HW will be configured with remote loopback such that
26175 * port logic will send packets back out the transmitter that
26178 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
26179 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
26180 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
26182 * Priority setting for VLAN PRI to CoS mapping.
26183 * # Each XXX_pri variable shall have a unique priority value
26184 * when it is being used.
26185 * # When comparing priorities of mappings, higher value
26186 * indicates higher priority.
26187 * For example, a value of 0-3 is returned where 0 is being
26188 * the lowest priority and 3 is being the highest priority.
26189 * # If the corresponding CoS mapping is not enabled, then this
26190 * field should be ignored.
26191 * # This value indicates the normalized priority value retained
26194 uint8_t vlan_pri2cos_map_pri;
26196 * In this field, a number of CoS mappings related flags
26197 * are used to indicate configured CoS mappings.
26201 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
26204 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
26207 * When this bit is set to '1', tunnel VLAN PRI field to
26208 * CoS mapping is enabled.
26210 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
26213 * When this bit is set to '1', the IP DSCP to CoS mapping is
26216 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
26219 * When this bit is '1', the Out-Of-Box WoL is enabled on this
26222 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
26224 /* When this bit is '1', PTP is enabled for RX on this port. */
26225 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
26227 /* When this bit is '1', PTP is enabled for TX on this port. */
26228 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
26231 * Priority setting for tunnel VLAN PRI to CoS mapping.
26232 * # Each XXX_pri variable shall have a unique priority value
26233 * when it is being used.
26234 * # When comparing priorities of mappings, higher value
26235 * indicates higher priority.
26236 * For example, a value of 0-3 is returned where 0 is being
26237 * the lowest priority and 3 is being the highest priority.
26238 * # If the corresponding CoS mapping is not enabled, then this
26239 * field should be ignored.
26240 * # This value indicates the normalized priority value retained
26243 uint8_t tunnel_pri2cos_map_pri;
26245 * Priority setting for DSCP to PRI mapping.
26246 * # Each XXX_pri variable shall have a unique priority value
26247 * when it is being used.
26248 * # When comparing priorities of mappings, higher value
26249 * indicates higher priority.
26250 * For example, a value of 0-3 is returned where 0 is being
26251 * the lowest priority and 3 is being the highest priority.
26252 * # If the corresponding CoS mapping is not enabled, then this
26253 * field should be ignored.
26254 * # This value indicates the normalized priority value retained
26257 uint8_t dscp2pri_map_pri;
26259 * This is a 16-bit bit mask that represents the
26260 * current configuration of time stamp capture of PTP messages
26261 * on the receive side of this port.
26262 * If bit 'i' is set, then the receive side of the port
26263 * is configured to capture the time stamp of every
26264 * received PTP message with messageType field value set
26266 * If all bits are set to 0 (i.e. field value set 0),
26267 * then the receive side of the port is not configured
26268 * to capture timestamp for PTP messages.
26269 * If all bits are set to 1, then the receive side of the
26270 * port is configured to capture timestamp for all PTP
26273 uint16_t rx_ts_capture_ptp_msg_type;
26275 * This is a 16-bit bit mask that represents the
26276 * current configuration of time stamp capture of PTP messages
26277 * on the transmit side of this port.
26278 * If bit 'i' is set, then the transmit side of the port
26279 * is configured to capture the time stamp of every
26280 * received PTP message with messageType field value set
26282 * If all bits are set to 0 (i.e. field value set 0),
26283 * then the transmit side of the port is not configured
26284 * to capture timestamp for PTP messages.
26285 * If all bits are set to 1, then the transmit side of the
26286 * port is configured to capture timestamp for all PTP
26289 uint16_t tx_ts_capture_ptp_msg_type;
26290 /* Configuration of CoS fields. */
26291 uint8_t cos_field_cfg;
26293 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
26296 * This field is used for selecting VLAN PRI value
26297 * based on whether one or two VLAN Tags are present in
26298 * the inner packet headers of tunneled packets or
26299 * non-tunneled packets.
26301 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
26303 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
26306 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
26307 * present in the inner packet headers
26309 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
26310 (UINT32_C(0x0) << 1)
26312 * Select outer VLAN Tag PRI when 2 VLAN Tags are
26313 * present in the inner packet headers.
26314 * No VLAN PRI is selected for this configuration
26315 * if only one VLAN Tag is present in the inner
26318 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
26319 (UINT32_C(0x1) << 1)
26321 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
26322 * are present in the inner packet headers
26324 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
26325 (UINT32_C(0x2) << 1)
26327 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
26328 (UINT32_C(0x3) << 1)
26329 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
26330 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
26332 * This field is used for selecting tunnel VLAN PRI value
26333 * based on whether one or two VLAN Tags are present in
26334 * the tunnel headers of tunneled packets. This selection
26335 * does not apply to non-tunneled packets.
26337 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
26339 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
26342 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
26343 * present in the tunnel packet headers
26345 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
26346 (UINT32_C(0x0) << 3)
26348 * Select outer VLAN Tag PRI when 2 VLAN Tags are
26349 * present in the tunnel packet headers.
26350 * No VLAN PRI is selected for this configuration
26351 * if only one VLAN Tag is present in the tunnel
26354 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
26355 (UINT32_C(0x1) << 3)
26357 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
26358 * are present in the tunnel packet headers
26360 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
26361 (UINT32_C(0x2) << 3)
26363 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
26364 (UINT32_C(0x3) << 3)
26365 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
26366 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
26368 * This field is used to provide default CoS value that
26369 * has been configured on this port.
26371 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
26373 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
26376 uint16_t port_svif_info;
26378 * This field specifies the source virtual interface of the port being
26379 * queried. Drivers can use this to program port svif field in the
26382 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
26384 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
26385 /* This field specifies whether port_svif is valid or not */
26386 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
26388 uint8_t unused_2[5];
26390 * This field is used in Output records to indicate that the output
26391 * is completely written to RAM. This field should be read as '1'
26392 * to indicate that the output has been completely written.
26393 * When writing a command completion or response to an internal processor,
26394 * the order of writes has to be such that this field is written last.
26399 /**************************
26400 * hwrm_port_mac_ptp_qcfg *
26401 **************************/
26404 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
26405 struct hwrm_port_mac_ptp_qcfg_input {
26406 /* The HWRM command request type. */
26409 * The completion ring to send the completion event on. This should
26410 * be the NQ ID returned from the `nq_alloc` HWRM command.
26412 uint16_t cmpl_ring;
26414 * The sequence ID is used by the driver for tracking multiple
26415 * commands. This ID is treated as opaque data by the firmware and
26416 * the value is returned in the `hwrm_resp_hdr` upon completion.
26420 * The target ID of the command:
26421 * * 0x0-0xFFF8 - The function ID
26422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26423 * * 0xFFFD - Reserved for user-space HWRM interface
26426 uint16_t target_id;
26428 * A physical address pointer pointing to a host buffer that the
26429 * command's response data will be written. This can be either a host
26430 * physical address (HPA) or a guest physical address (GPA) and must
26431 * point to a physically contiguous block of memory.
26433 uint64_t resp_addr;
26434 /* Port ID of port that is being queried. */
26436 uint8_t unused_0[6];
26439 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
26440 struct hwrm_port_mac_ptp_qcfg_output {
26441 /* The specific error status for the command. */
26442 uint16_t error_code;
26443 /* The HWRM command request type. */
26445 /* The sequence ID from the original command. */
26447 /* The length of the response data in number of bytes. */
26450 * In this field, a number of PTP related flags
26451 * are used to indicate configured PTP capabilities.
26455 * When this bit is set to '1', the PTP related registers are
26456 * directly accessible by the host.
26458 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
26461 * When this bit is set to '1', the device supports one-step
26464 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
26467 * When this bit is set to '1', the PTP information is accessible
26468 * via HWRM commands.
26470 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
26473 * When this bit is set to '1', two specific registers for current
26474 * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are
26475 * directly accessible by the host.
26477 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \
26480 * When this bit is set to '1', it indicates that driver has
26481 * configured 64bit RTC.
26483 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED \
26485 uint8_t unused_0[3];
26487 * Offset of the PTP register for the lower 32 bits of timestamp
26490 uint32_t rx_ts_reg_off_lower;
26492 * Offset of the PTP register for the upper 32 bits of timestamp
26495 uint32_t rx_ts_reg_off_upper;
26496 /* Offset of the PTP register for the sequence ID for RX. */
26497 uint32_t rx_ts_reg_off_seq_id;
26498 /* Offset of the first PTP source ID for RX. */
26499 uint32_t rx_ts_reg_off_src_id_0;
26500 /* Offset of the second PTP source ID for RX. */
26501 uint32_t rx_ts_reg_off_src_id_1;
26502 /* Offset of the third PTP source ID for RX. */
26503 uint32_t rx_ts_reg_off_src_id_2;
26504 /* Offset of the domain ID for RX. */
26505 uint32_t rx_ts_reg_off_domain_id;
26506 /* Offset of the PTP FIFO register for RX. */
26507 uint32_t rx_ts_reg_off_fifo;
26508 /* Offset of the PTP advance FIFO register for RX. */
26509 uint32_t rx_ts_reg_off_fifo_adv;
26510 /* PTP timestamp granularity for RX. */
26511 uint32_t rx_ts_reg_off_granularity;
26513 * Offset of the PTP register for the lower 32 bits of timestamp
26516 uint32_t tx_ts_reg_off_lower;
26518 * Offset of the PTP register for the upper 32 bits of timestamp
26521 uint32_t tx_ts_reg_off_upper;
26522 /* Offset of the PTP register for the sequence ID for TX. */
26523 uint32_t tx_ts_reg_off_seq_id;
26524 /* Offset of the PTP FIFO register for TX. */
26525 uint32_t tx_ts_reg_off_fifo;
26526 /* PTP timestamp granularity for TX. */
26527 uint32_t tx_ts_reg_off_granularity;
26528 /* Offset of register to get lower 32 bits of current time. */
26529 uint32_t ts_ref_clock_reg_lower;
26530 /* Offset of register to get upper 32 bits of current time. */
26531 uint32_t ts_ref_clock_reg_upper;
26532 uint8_t unused_1[7];
26534 * This field is used in Output records to indicate that the output
26535 * is completely written to RAM. This field should be read as '1'
26536 * to indicate that the output has been completely written.
26537 * When writing a command completion or response to an internal processor,
26538 * the order of writes has to be such that this field is written last.
26543 /* Port Tx Statistics Format */
26544 /* tx_port_stats (size:3264b/408B) */
26545 struct tx_port_stats {
26546 /* Total Number of 64 Bytes frames transmitted */
26547 uint64_t tx_64b_frames;
26548 /* Total Number of 65-127 Bytes frames transmitted */
26549 uint64_t tx_65b_127b_frames;
26550 /* Total Number of 128-255 Bytes frames transmitted */
26551 uint64_t tx_128b_255b_frames;
26552 /* Total Number of 256-511 Bytes frames transmitted */
26553 uint64_t tx_256b_511b_frames;
26554 /* Total Number of 512-1023 Bytes frames transmitted */
26555 uint64_t tx_512b_1023b_frames;
26556 /* Total Number of 1024-1518 Bytes frames transmitted */
26557 uint64_t tx_1024b_1518b_frames;
26559 * Total Number of each good VLAN (excludes FCS errors)
26560 * frame transmitted which is 1519 to 1522 bytes in length
26561 * inclusive (excluding framing bits but including FCS bytes).
26563 uint64_t tx_good_vlan_frames;
26564 /* Total Number of 1519-2047 Bytes frames transmitted */
26565 uint64_t tx_1519b_2047b_frames;
26566 /* Total Number of 2048-4095 Bytes frames transmitted */
26567 uint64_t tx_2048b_4095b_frames;
26568 /* Total Number of 4096-9216 Bytes frames transmitted */
26569 uint64_t tx_4096b_9216b_frames;
26570 /* Total Number of 9217-16383 Bytes frames transmitted */
26571 uint64_t tx_9217b_16383b_frames;
26572 /* Total Number of good frames transmitted */
26573 uint64_t tx_good_frames;
26574 /* Total Number of frames transmitted */
26575 uint64_t tx_total_frames;
26576 /* Total number of unicast frames transmitted */
26577 uint64_t tx_ucast_frames;
26578 /* Total number of multicast frames transmitted */
26579 uint64_t tx_mcast_frames;
26580 /* Total number of broadcast frames transmitted */
26581 uint64_t tx_bcast_frames;
26582 /* Total number of PAUSE control frames transmitted */
26583 uint64_t tx_pause_frames;
26585 * Total number of PFC/per-priority PAUSE
26586 * control frames transmitted
26588 uint64_t tx_pfc_frames;
26589 /* Total number of jabber frames transmitted */
26590 uint64_t tx_jabber_frames;
26591 /* Total number of frames transmitted with FCS error */
26592 uint64_t tx_fcs_err_frames;
26593 /* Total number of control frames transmitted */
26594 uint64_t tx_control_frames;
26595 /* Total number of over-sized frames transmitted */
26596 uint64_t tx_oversz_frames;
26597 /* Total number of frames with single deferral */
26598 uint64_t tx_single_dfrl_frames;
26599 /* Total number of frames with multiple deferrals */
26600 uint64_t tx_multi_dfrl_frames;
26601 /* Total number of frames with single collision */
26602 uint64_t tx_single_coll_frames;
26603 /* Total number of frames with multiple collisions */
26604 uint64_t tx_multi_coll_frames;
26605 /* Total number of frames with late collisions */
26606 uint64_t tx_late_coll_frames;
26607 /* Total number of frames with excessive collisions */
26608 uint64_t tx_excessive_coll_frames;
26609 /* Total number of fragmented frames transmitted */
26610 uint64_t tx_frag_frames;
26611 /* Total number of transmit errors */
26613 /* Total number of single VLAN tagged frames transmitted */
26614 uint64_t tx_tagged_frames;
26615 /* Total number of double VLAN tagged frames transmitted */
26616 uint64_t tx_dbl_tagged_frames;
26617 /* Total number of runt frames transmitted */
26618 uint64_t tx_runt_frames;
26619 /* Total number of TX FIFO under runs */
26620 uint64_t tx_fifo_underruns;
26622 * Total number of PFC frames with PFC enabled bit for
26623 * Pri 0 transmitted
26625 uint64_t tx_pfc_ena_frames_pri0;
26627 * Total number of PFC frames with PFC enabled bit for
26628 * Pri 1 transmitted
26630 uint64_t tx_pfc_ena_frames_pri1;
26632 * Total number of PFC frames with PFC enabled bit for
26633 * Pri 2 transmitted
26635 uint64_t tx_pfc_ena_frames_pri2;
26637 * Total number of PFC frames with PFC enabled bit for
26638 * Pri 3 transmitted
26640 uint64_t tx_pfc_ena_frames_pri3;
26642 * Total number of PFC frames with PFC enabled bit for
26643 * Pri 4 transmitted
26645 uint64_t tx_pfc_ena_frames_pri4;
26647 * Total number of PFC frames with PFC enabled bit for
26648 * Pri 5 transmitted
26650 uint64_t tx_pfc_ena_frames_pri5;
26652 * Total number of PFC frames with PFC enabled bit for
26653 * Pri 6 transmitted
26655 uint64_t tx_pfc_ena_frames_pri6;
26657 * Total number of PFC frames with PFC enabled bit for
26658 * Pri 7 transmitted
26660 uint64_t tx_pfc_ena_frames_pri7;
26661 /* Total number of EEE LPI Events on TX */
26662 uint64_t tx_eee_lpi_events;
26663 /* EEE LPI Duration Counter on TX */
26664 uint64_t tx_eee_lpi_duration;
26666 * Total number of Link Level Flow Control (LLFC) messages
26669 uint64_t tx_llfc_logical_msgs;
26670 /* Total number of HCFC messages transmitted */
26671 uint64_t tx_hcfc_msgs;
26672 /* Total number of TX collisions */
26673 uint64_t tx_total_collisions;
26674 /* Total number of transmitted bytes */
26676 /* Total number of end-to-end HOL frames */
26677 uint64_t tx_xthol_frames;
26678 /* Total Tx Drops per Port reported by STATS block */
26679 uint64_t tx_stat_discard;
26680 /* Total Tx Error Drops per Port reported by STATS block */
26681 uint64_t tx_stat_error;
26684 /* Port Rx Statistics Format */
26685 /* rx_port_stats (size:4224b/528B) */
26686 struct rx_port_stats {
26687 /* Total Number of 64 Bytes frames received */
26688 uint64_t rx_64b_frames;
26689 /* Total Number of 65-127 Bytes frames received */
26690 uint64_t rx_65b_127b_frames;
26691 /* Total Number of 128-255 Bytes frames received */
26692 uint64_t rx_128b_255b_frames;
26693 /* Total Number of 256-511 Bytes frames received */
26694 uint64_t rx_256b_511b_frames;
26695 /* Total Number of 512-1023 Bytes frames received */
26696 uint64_t rx_512b_1023b_frames;
26697 /* Total Number of 1024-1518 Bytes frames received */
26698 uint64_t rx_1024b_1518b_frames;
26700 * Total Number of each good VLAN (excludes FCS errors)
26701 * frame received which is 1519 to 1522 bytes in length
26702 * inclusive (excluding framing bits but including FCS bytes).
26704 uint64_t rx_good_vlan_frames;
26705 /* Total Number of 1519-2047 Bytes frames received */
26706 uint64_t rx_1519b_2047b_frames;
26707 /* Total Number of 2048-4095 Bytes frames received */
26708 uint64_t rx_2048b_4095b_frames;
26709 /* Total Number of 4096-9216 Bytes frames received */
26710 uint64_t rx_4096b_9216b_frames;
26711 /* Total Number of 9217-16383 Bytes frames received */
26712 uint64_t rx_9217b_16383b_frames;
26713 /* Total number of frames received */
26714 uint64_t rx_total_frames;
26715 /* Total number of unicast frames received */
26716 uint64_t rx_ucast_frames;
26717 /* Total number of multicast frames received */
26718 uint64_t rx_mcast_frames;
26719 /* Total number of broadcast frames received */
26720 uint64_t rx_bcast_frames;
26721 /* Total number of received frames with FCS error */
26722 uint64_t rx_fcs_err_frames;
26723 /* Total number of control frames received */
26724 uint64_t rx_ctrl_frames;
26725 /* Total number of PAUSE frames received */
26726 uint64_t rx_pause_frames;
26727 /* Total number of PFC frames received */
26728 uint64_t rx_pfc_frames;
26730 * Total number of frames received with an unsupported
26733 uint64_t rx_unsupported_opcode_frames;
26735 * Total number of frames received with an unsupported
26736 * DA for pause and PFC
26738 uint64_t rx_unsupported_da_pausepfc_frames;
26739 /* Total number of frames received with an unsupported SA */
26740 uint64_t rx_wrong_sa_frames;
26741 /* Total number of received packets with alignment error */
26742 uint64_t rx_align_err_frames;
26743 /* Total number of received frames with out-of-range length */
26744 uint64_t rx_oor_len_frames;
26745 /* Total number of received frames with error termination */
26746 uint64_t rx_code_err_frames;
26748 * Total number of received frames with a false carrier is
26749 * detected during idle, as defined by RX_ER samples active
26750 * and RXD is 0xE. The event is reported along with the
26751 * statistics generated on the next received frame. Only
26752 * one false carrier condition can be detected and logged
26755 * Carrier event, valid for 10M/100M speed modes only.
26757 uint64_t rx_false_carrier_frames;
26758 /* Total number of over-sized frames received */
26759 uint64_t rx_ovrsz_frames;
26760 /* Total number of jabber packets received */
26761 uint64_t rx_jbr_frames;
26762 /* Total number of received frames with MTU error */
26763 uint64_t rx_mtu_err_frames;
26764 /* Total number of received frames with CRC match */
26765 uint64_t rx_match_crc_frames;
26766 /* Total number of frames received promiscuously */
26767 uint64_t rx_promiscuous_frames;
26769 * Total number of received frames with one or two VLAN
26772 uint64_t rx_tagged_frames;
26773 /* Total number of received frames with two VLAN tags */
26774 uint64_t rx_double_tagged_frames;
26775 /* Total number of truncated frames received */
26776 uint64_t rx_trunc_frames;
26777 /* Total number of good frames (without errors) received */
26778 uint64_t rx_good_frames;
26780 * Total number of received PFC frames with transition from
26781 * XON to XOFF on Pri 0
26783 uint64_t rx_pfc_xon2xoff_frames_pri0;
26785 * Total number of received PFC frames with transition from
26786 * XON to XOFF on Pri 1
26788 uint64_t rx_pfc_xon2xoff_frames_pri1;
26790 * Total number of received PFC frames with transition from
26791 * XON to XOFF on Pri 2
26793 uint64_t rx_pfc_xon2xoff_frames_pri2;
26795 * Total number of received PFC frames with transition from
26796 * XON to XOFF on Pri 3
26798 uint64_t rx_pfc_xon2xoff_frames_pri3;
26800 * Total number of received PFC frames with transition from
26801 * XON to XOFF on Pri 4
26803 uint64_t rx_pfc_xon2xoff_frames_pri4;
26805 * Total number of received PFC frames with transition from
26806 * XON to XOFF on Pri 5
26808 uint64_t rx_pfc_xon2xoff_frames_pri5;
26810 * Total number of received PFC frames with transition from
26811 * XON to XOFF on Pri 6
26813 uint64_t rx_pfc_xon2xoff_frames_pri6;
26815 * Total number of received PFC frames with transition from
26816 * XON to XOFF on Pri 7
26818 uint64_t rx_pfc_xon2xoff_frames_pri7;
26820 * Total number of received PFC frames with PFC enabled
26823 uint64_t rx_pfc_ena_frames_pri0;
26825 * Total number of received PFC frames with PFC enabled
26828 uint64_t rx_pfc_ena_frames_pri1;
26830 * Total number of received PFC frames with PFC enabled
26833 uint64_t rx_pfc_ena_frames_pri2;
26835 * Total number of received PFC frames with PFC enabled
26838 uint64_t rx_pfc_ena_frames_pri3;
26840 * Total number of received PFC frames with PFC enabled
26843 uint64_t rx_pfc_ena_frames_pri4;
26845 * Total number of received PFC frames with PFC enabled
26848 uint64_t rx_pfc_ena_frames_pri5;
26850 * Total number of received PFC frames with PFC enabled
26853 uint64_t rx_pfc_ena_frames_pri6;
26855 * Total number of received PFC frames with PFC enabled
26858 uint64_t rx_pfc_ena_frames_pri7;
26859 /* Total Number of frames received with SCH CRC error */
26860 uint64_t rx_sch_crc_err_frames;
26861 /* Total Number of under-sized frames received */
26862 uint64_t rx_undrsz_frames;
26863 /* Total Number of fragmented frames received */
26864 uint64_t rx_frag_frames;
26865 /* Total number of RX EEE LPI Events */
26866 uint64_t rx_eee_lpi_events;
26867 /* EEE LPI Duration Counter on RX */
26868 uint64_t rx_eee_lpi_duration;
26870 * Total number of physical type Link Level Flow Control
26871 * (LLFC) messages received
26873 uint64_t rx_llfc_physical_msgs;
26875 * Total number of logical type Link Level Flow Control
26876 * (LLFC) messages received
26878 uint64_t rx_llfc_logical_msgs;
26880 * Total number of logical type Link Level Flow Control
26881 * (LLFC) messages received with CRC error
26883 uint64_t rx_llfc_msgs_with_crc_err;
26884 /* Total number of HCFC messages received */
26885 uint64_t rx_hcfc_msgs;
26886 /* Total number of HCFC messages received with CRC error */
26887 uint64_t rx_hcfc_msgs_with_crc_err;
26888 /* Total number of received bytes */
26890 /* Total number of bytes received in runt frames */
26891 uint64_t rx_runt_bytes;
26892 /* Total number of runt frames received */
26893 uint64_t rx_runt_frames;
26894 /* Total Rx Discards per Port reported by STATS block */
26895 uint64_t rx_stat_discard;
26896 uint64_t rx_stat_err;
26899 /********************
26900 * hwrm_port_qstats *
26901 ********************/
26904 /* hwrm_port_qstats_input (size:320b/40B) */
26905 struct hwrm_port_qstats_input {
26906 /* The HWRM command request type. */
26909 * The completion ring to send the completion event on. This should
26910 * be the NQ ID returned from the `nq_alloc` HWRM command.
26912 uint16_t cmpl_ring;
26914 * The sequence ID is used by the driver for tracking multiple
26915 * commands. This ID is treated as opaque data by the firmware and
26916 * the value is returned in the `hwrm_resp_hdr` upon completion.
26920 * The target ID of the command:
26921 * * 0x0-0xFFF8 - The function ID
26922 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26923 * * 0xFFFD - Reserved for user-space HWRM interface
26926 uint16_t target_id;
26928 * A physical address pointer pointing to a host buffer that the
26929 * command's response data will be written. This can be either a host
26930 * physical address (HPA) or a guest physical address (GPA) and must
26931 * point to a physically contiguous block of memory.
26933 uint64_t resp_addr;
26934 /* Port ID of port that is being queried. */
26937 /* This value is not used to avoid backward compatibility issues. */
26938 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
26940 * This bit is set to 1 when request is for a counter mask,
26941 * representing the width of each of the stats counters, rather
26942 * than counters themselves.
26944 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
26945 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
26946 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
26947 uint8_t unused_0[5];
26949 * This is the host address where
26950 * Tx port statistics will be stored
26952 uint64_t tx_stat_host_addr;
26954 * This is the host address where
26955 * Rx port statistics will be stored
26957 uint64_t rx_stat_host_addr;
26960 /* hwrm_port_qstats_output (size:128b/16B) */
26961 struct hwrm_port_qstats_output {
26962 /* The specific error status for the command. */
26963 uint16_t error_code;
26964 /* The HWRM command request type. */
26966 /* The sequence ID from the original command. */
26968 /* The length of the response data in number of bytes. */
26970 /* The size of TX port statistics block in bytes. */
26971 uint16_t tx_stat_size;
26972 /* The size of RX port statistics block in bytes. */
26973 uint16_t rx_stat_size;
26974 uint8_t unused_0[3];
26976 * This field is used in Output records to indicate that the output
26977 * is completely written to RAM. This field should be read as '1'
26978 * to indicate that the output has been completely written.
26979 * When writing a command completion or response to an internal processor,
26980 * the order of writes has to be such that this field is written last.
26985 /* Port Tx Statistics extended Format */
26986 /* tx_port_stats_ext (size:2048b/256B) */
26987 struct tx_port_stats_ext {
26988 /* Total number of tx bytes count on cos queue 0 */
26989 uint64_t tx_bytes_cos0;
26990 /* Total number of tx bytes count on cos queue 1 */
26991 uint64_t tx_bytes_cos1;
26992 /* Total number of tx bytes count on cos queue 2 */
26993 uint64_t tx_bytes_cos2;
26994 /* Total number of tx bytes count on cos queue 3 */
26995 uint64_t tx_bytes_cos3;
26996 /* Total number of tx bytes count on cos queue 4 */
26997 uint64_t tx_bytes_cos4;
26998 /* Total number of tx bytes count on cos queue 5 */
26999 uint64_t tx_bytes_cos5;
27000 /* Total number of tx bytes count on cos queue 6 */
27001 uint64_t tx_bytes_cos6;
27002 /* Total number of tx bytes count on cos queue 7 */
27003 uint64_t tx_bytes_cos7;
27004 /* Total number of tx packets count on cos queue 0 */
27005 uint64_t tx_packets_cos0;
27006 /* Total number of tx packets count on cos queue 1 */
27007 uint64_t tx_packets_cos1;
27008 /* Total number of tx packets count on cos queue 2 */
27009 uint64_t tx_packets_cos2;
27010 /* Total number of tx packets count on cos queue 3 */
27011 uint64_t tx_packets_cos3;
27012 /* Total number of tx packets count on cos queue 4 */
27013 uint64_t tx_packets_cos4;
27014 /* Total number of tx packets count on cos queue 5 */
27015 uint64_t tx_packets_cos5;
27016 /* Total number of tx packets count on cos queue 6 */
27017 uint64_t tx_packets_cos6;
27018 /* Total number of tx packets count on cos queue 7 */
27019 uint64_t tx_packets_cos7;
27020 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
27021 uint64_t pfc_pri0_tx_duration_us;
27022 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
27023 uint64_t pfc_pri0_tx_transitions;
27024 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
27025 uint64_t pfc_pri1_tx_duration_us;
27026 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
27027 uint64_t pfc_pri1_tx_transitions;
27028 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
27029 uint64_t pfc_pri2_tx_duration_us;
27030 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
27031 uint64_t pfc_pri2_tx_transitions;
27032 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
27033 uint64_t pfc_pri3_tx_duration_us;
27034 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
27035 uint64_t pfc_pri3_tx_transitions;
27036 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
27037 uint64_t pfc_pri4_tx_duration_us;
27038 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
27039 uint64_t pfc_pri4_tx_transitions;
27040 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
27041 uint64_t pfc_pri5_tx_duration_us;
27042 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
27043 uint64_t pfc_pri5_tx_transitions;
27044 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
27045 uint64_t pfc_pri6_tx_duration_us;
27046 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
27047 uint64_t pfc_pri6_tx_transitions;
27048 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
27049 uint64_t pfc_pri7_tx_duration_us;
27050 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
27051 uint64_t pfc_pri7_tx_transitions;
27054 /* Port Rx Statistics extended Format */
27055 /* rx_port_stats_ext (size:3776b/472B) */
27056 struct rx_port_stats_ext {
27057 /* Number of times link state changed to down */
27058 uint64_t link_down_events;
27059 /* Number of times the idle rings with pause bit are found */
27060 uint64_t continuous_pause_events;
27061 /* Number of times the active rings pause bit resumed back */
27062 uint64_t resume_pause_events;
27063 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
27064 uint64_t continuous_roce_pause_events;
27065 /* Number of times, the ROCE cos queue PFC is enabled back */
27066 uint64_t resume_roce_pause_events;
27067 /* Total number of rx bytes count on cos queue 0 */
27068 uint64_t rx_bytes_cos0;
27069 /* Total number of rx bytes count on cos queue 1 */
27070 uint64_t rx_bytes_cos1;
27071 /* Total number of rx bytes count on cos queue 2 */
27072 uint64_t rx_bytes_cos2;
27073 /* Total number of rx bytes count on cos queue 3 */
27074 uint64_t rx_bytes_cos3;
27075 /* Total number of rx bytes count on cos queue 4 */
27076 uint64_t rx_bytes_cos4;
27077 /* Total number of rx bytes count on cos queue 5 */
27078 uint64_t rx_bytes_cos5;
27079 /* Total number of rx bytes count on cos queue 6 */
27080 uint64_t rx_bytes_cos6;
27081 /* Total number of rx bytes count on cos queue 7 */
27082 uint64_t rx_bytes_cos7;
27083 /* Total number of rx packets count on cos queue 0 */
27084 uint64_t rx_packets_cos0;
27085 /* Total number of rx packets count on cos queue 1 */
27086 uint64_t rx_packets_cos1;
27087 /* Total number of rx packets count on cos queue 2 */
27088 uint64_t rx_packets_cos2;
27089 /* Total number of rx packets count on cos queue 3 */
27090 uint64_t rx_packets_cos3;
27091 /* Total number of rx packets count on cos queue 4 */
27092 uint64_t rx_packets_cos4;
27093 /* Total number of rx packets count on cos queue 5 */
27094 uint64_t rx_packets_cos5;
27095 /* Total number of rx packets count on cos queue 6 */
27096 uint64_t rx_packets_cos6;
27097 /* Total number of rx packets count on cos queue 7 */
27098 uint64_t rx_packets_cos7;
27099 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
27100 uint64_t pfc_pri0_rx_duration_us;
27101 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
27102 uint64_t pfc_pri0_rx_transitions;
27103 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
27104 uint64_t pfc_pri1_rx_duration_us;
27105 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
27106 uint64_t pfc_pri1_rx_transitions;
27107 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
27108 uint64_t pfc_pri2_rx_duration_us;
27109 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
27110 uint64_t pfc_pri2_rx_transitions;
27111 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
27112 uint64_t pfc_pri3_rx_duration_us;
27113 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
27114 uint64_t pfc_pri3_rx_transitions;
27115 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
27116 uint64_t pfc_pri4_rx_duration_us;
27117 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
27118 uint64_t pfc_pri4_rx_transitions;
27119 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
27120 uint64_t pfc_pri5_rx_duration_us;
27121 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
27122 uint64_t pfc_pri5_rx_transitions;
27123 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
27124 uint64_t pfc_pri6_rx_duration_us;
27125 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
27126 uint64_t pfc_pri6_rx_transitions;
27127 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
27128 uint64_t pfc_pri7_rx_duration_us;
27129 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
27130 uint64_t pfc_pri7_rx_transitions;
27131 /* Total number of received bits */
27133 /* The number of events where the port receive buffer was over 85% full */
27134 uint64_t rx_buffer_passed_threshold;
27136 * The number of symbol errors that wasn't corrected by FEC correction
27139 uint64_t rx_pcs_symbol_err;
27140 /* The number of corrected bits on the port according to active FEC */
27141 uint64_t rx_corrected_bits;
27142 /* Total number of rx discard bytes count on cos queue 0 */
27143 uint64_t rx_discard_bytes_cos0;
27144 /* Total number of rx discard bytes count on cos queue 1 */
27145 uint64_t rx_discard_bytes_cos1;
27146 /* Total number of rx discard bytes count on cos queue 2 */
27147 uint64_t rx_discard_bytes_cos2;
27148 /* Total number of rx discard bytes count on cos queue 3 */
27149 uint64_t rx_discard_bytes_cos3;
27150 /* Total number of rx discard bytes count on cos queue 4 */
27151 uint64_t rx_discard_bytes_cos4;
27152 /* Total number of rx discard bytes count on cos queue 5 */
27153 uint64_t rx_discard_bytes_cos5;
27154 /* Total number of rx discard bytes count on cos queue 6 */
27155 uint64_t rx_discard_bytes_cos6;
27156 /* Total number of rx discard bytes count on cos queue 7 */
27157 uint64_t rx_discard_bytes_cos7;
27158 /* Total number of rx discard packets count on cos queue 0 */
27159 uint64_t rx_discard_packets_cos0;
27160 /* Total number of rx discard packets count on cos queue 1 */
27161 uint64_t rx_discard_packets_cos1;
27162 /* Total number of rx discard packets count on cos queue 2 */
27163 uint64_t rx_discard_packets_cos2;
27164 /* Total number of rx discard packets count on cos queue 3 */
27165 uint64_t rx_discard_packets_cos3;
27166 /* Total number of rx discard packets count on cos queue 4 */
27167 uint64_t rx_discard_packets_cos4;
27168 /* Total number of rx discard packets count on cos queue 5 */
27169 uint64_t rx_discard_packets_cos5;
27170 /* Total number of rx discard packets count on cos queue 6 */
27171 uint64_t rx_discard_packets_cos6;
27172 /* Total number of rx discard packets count on cos queue 7 */
27173 uint64_t rx_discard_packets_cos7;
27174 /* Total number of FEC blocks corrected by the FEC function in the PHY */
27175 uint64_t rx_fec_corrected_blocks;
27177 * Total number of FEC blocks determined to be uncorrectable by the
27178 * FEC function in the PHY
27180 uint64_t rx_fec_uncorrectable_blocks;
27184 * Port Rx Statistics extended PFC WatchDog Format.
27185 * StormDetect and StormRevert event determination is based
27186 * on an integration period and a percentage threshold.
27187 * StormDetect event - when percentage of XOFF frames received
27188 * within an integration period exceeds the configured threshold.
27189 * StormRevert event - when percentage of XON frames received
27190 * within an integration period exceeds the configured threshold.
27191 * Actual number of XOFF/XON frames for the events to be triggered
27192 * depends on both configured integration period and sampling rate.
27193 * The statistics in this structure represent counts of specified
27194 * events from the moment the feature (PFC WatchDog) is enabled via
27195 * hwrm_queue_pfc_enable_cfg call.
27197 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
27198 struct rx_port_stats_ext_pfc_wd {
27200 * Total number of PFC WatchDog StormDetect events detected
27203 uint64_t rx_pfc_watchdog_storms_detected_pri0;
27205 * Total number of PFC WatchDog StormDetect events detected
27208 uint64_t rx_pfc_watchdog_storms_detected_pri1;
27210 * Total number of PFC WatchDog StormDetect events detected
27213 uint64_t rx_pfc_watchdog_storms_detected_pri2;
27215 * Total number of PFC WatchDog StormDetect events detected
27218 uint64_t rx_pfc_watchdog_storms_detected_pri3;
27220 * Total number of PFC WatchDog StormDetect events detected
27223 uint64_t rx_pfc_watchdog_storms_detected_pri4;
27225 * Total number of PFC WatchDog StormDetect events detected
27228 uint64_t rx_pfc_watchdog_storms_detected_pri5;
27230 * Total number of PFC WatchDog StormDetect events detected
27233 uint64_t rx_pfc_watchdog_storms_detected_pri6;
27235 * Total number of PFC WatchDog StormDetect events detected
27238 uint64_t rx_pfc_watchdog_storms_detected_pri7;
27240 * Total number of PFC WatchDog StormRevert events detected
27243 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
27245 * Total number of PFC WatchDog StormRevert events detected
27248 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
27250 * Total number of PFC WatchDog StormRevert events detected
27253 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
27255 * Total number of PFC WatchDog StormRevert events detected
27258 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
27260 * Total number of PFC WatchDog StormRevert events detected
27263 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
27265 * Total number of PFC WatchDog StormRevert events detected
27268 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
27270 * Total number of PFC WatchDog StormRevert events detected
27273 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
27275 * Total number of PFC WatchDog StormRevert events detected
27278 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
27280 * Total number of packets received during PFC watchdog storm
27283 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
27285 * Total number of packets received during PFC watchdog storm
27288 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
27290 * Total number of packets received during PFC watchdog storm
27293 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
27295 * Total number of packets received during PFC watchdog storm
27298 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
27300 * Total number of packets received during PFC watchdog storm
27303 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
27305 * Total number of packets received during PFC watchdog storm
27308 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
27310 * Total number of packets received during PFC watchdog storm
27313 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
27315 * Total number of packets received during PFC watchdog storm
27318 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
27320 * Total number of bytes received during PFC watchdog storm
27323 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
27325 * Total number of bytes received during PFC watchdog storm
27328 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
27330 * Total number of bytes received during PFC watchdog storm
27333 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
27335 * Total number of bytes received during PFC watchdog storm
27338 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
27340 * Total number of bytes received during PFC watchdog storm
27343 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
27345 * Total number of bytes received during PFC watchdog storm
27348 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
27350 * Total number of bytes received during PFC watchdog storm
27353 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
27355 * Total number of bytes received during PFC watchdog storm
27358 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
27360 * Total number of packets dropped on rx during PFC watchdog storm
27363 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
27365 * Total number of packets dropped on rx during PFC watchdog storm
27368 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
27370 * Total number of packets dropped on rx during PFC watchdog storm
27373 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
27375 * Total number of packets dropped on rx during PFC watchdog storm
27378 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
27380 * Total number of packets dropped on rx during PFC watchdog storm
27383 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
27385 * Total number of packets dropped on rx during PFC watchdog storm
27388 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
27390 * Total number of packets dropped on rx during PFC watchdog storm
27393 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
27395 * Total number of packets dropped on rx during PFC watchdog storm
27398 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
27400 * Total number of bytes dropped on rx during PFC watchdog storm
27403 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
27405 * Total number of bytes dropped on rx during PFC watchdog storm
27408 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
27410 * Total number of bytes dropped on rx during PFC watchdog storm
27413 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
27415 * Total number of bytes dropped on rx during PFC watchdog storm
27418 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
27420 * Total number of bytes dropped on rx during PFC watchdog storm
27423 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
27425 * Total number of bytes dropped on rx during PFC watchdog storm
27428 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
27430 * Total number of bytes dropped on rx during PFC watchdog storm
27433 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
27435 * Total number of bytes dropped on rx during PFC watchdog storm
27438 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
27440 * Number of packets received during last PFC watchdog storm
27443 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
27445 * Number of packets received during last PFC watchdog storm
27448 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
27450 * Number of packets received during last PFC watchdog storm
27453 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
27455 * Number of packets received during last PFC watchdog storm
27458 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
27460 * Number of packets received during last PFC watchdog storm
27463 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
27465 * Number of packets received during last PFC watchdog storm
27468 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
27470 * Number of packets received during last PFC watchdog storm
27473 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
27475 * Number of packets received during last PFC watchdog storm
27478 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
27480 * Number of bytes received during last PFC watchdog storm
27483 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
27485 * Number of bytes received during last PFC watchdog storm
27488 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
27490 * Number of bytes received during last PFC watchdog storm
27493 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
27495 * Number of bytes received during last PFC watchdog storm
27498 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
27500 * Number of bytes received during last PFC watchdog storm
27503 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
27505 * Number of bytes received during last PFC watchdog storm
27508 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
27510 * Number of bytes received during last PFC watchdog storm
27513 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
27515 * Number of bytes received during last PFC watchdog storm
27518 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
27520 * Number of packets dropped on rx during last PFC watchdog storm
27523 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
27525 * Number of packets dropped on rx during last PFC watchdog storm
27528 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
27530 * Number of packets dropped on rx during last PFC watchdog storm
27533 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
27535 * Number of packets dropped on rx during last PFC watchdog storm
27538 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
27540 * Number of packets dropped on rx during last PFC watchdog storm
27543 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
27545 * Number of packets dropped on rx during last PFC watchdog storm
27548 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
27550 * Number of packets dropped on rx during last PFC watchdog storm
27553 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
27555 * Number of packets dropped on rx during last PFC watchdog storm
27558 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
27560 * Total number of bytes dropped on rx during PFC watchdog storm
27563 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
27565 * Number of bytes dropped on rx during last PFC watchdog storm
27568 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
27570 * Number of bytes dropped on rx during last PFC watchdog storm
27573 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
27575 * Number of bytes dropped on rx during last PFC watchdog storm
27578 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
27580 * Number of bytes dropped on rx during last PFC watchdog storm
27583 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
27585 * Number of bytes dropped on rx during last PFC watchdog storm
27588 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
27590 * Number of bytes dropped on rx during last PFC watchdog storm
27593 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
27595 * Number of bytes dropped on rx during last PFC watchdog storm
27598 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
27601 /************************
27602 * hwrm_port_qstats_ext *
27603 ************************/
27606 /* hwrm_port_qstats_ext_input (size:320b/40B) */
27607 struct hwrm_port_qstats_ext_input {
27608 /* The HWRM command request type. */
27611 * The completion ring to send the completion event on. This should
27612 * be the NQ ID returned from the `nq_alloc` HWRM command.
27614 uint16_t cmpl_ring;
27616 * The sequence ID is used by the driver for tracking multiple
27617 * commands. This ID is treated as opaque data by the firmware and
27618 * the value is returned in the `hwrm_resp_hdr` upon completion.
27622 * The target ID of the command:
27623 * * 0x0-0xFFF8 - The function ID
27624 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27625 * * 0xFFFD - Reserved for user-space HWRM interface
27628 uint16_t target_id;
27630 * A physical address pointer pointing to a host buffer that the
27631 * command's response data will be written. This can be either a host
27632 * physical address (HPA) or a guest physical address (GPA) and must
27633 * point to a physically contiguous block of memory.
27635 uint64_t resp_addr;
27636 /* Port ID of port that is being queried. */
27639 * The size of TX port extended
27640 * statistics block in bytes.
27642 uint16_t tx_stat_size;
27644 * The size of RX port extended
27645 * statistics block in bytes
27647 uint16_t rx_stat_size;
27649 /* This value is not used to avoid backward compatibility issues. */
27650 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
27652 * This bit is set to 1 when request is for the counter mask,
27653 * representing width of each of the stats counters, rather than
27654 * counters themselves.
27656 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
27657 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
27658 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
27661 * This is the host address where
27662 * Tx port statistics will be stored
27664 uint64_t tx_stat_host_addr;
27666 * This is the host address where
27667 * Rx port statistics will be stored
27669 uint64_t rx_stat_host_addr;
27672 /* hwrm_port_qstats_ext_output (size:128b/16B) */
27673 struct hwrm_port_qstats_ext_output {
27674 /* The specific error status for the command. */
27675 uint16_t error_code;
27676 /* The HWRM command request type. */
27678 /* The sequence ID from the original command. */
27680 /* The length of the response data in number of bytes. */
27682 /* The size of TX port statistics block in bytes. */
27683 uint16_t tx_stat_size;
27684 /* The size of RX port statistics block in bytes. */
27685 uint16_t rx_stat_size;
27686 /* Total number of active cos queues available. */
27687 uint16_t total_active_cos_queues;
27690 * If set to 1, then this field indicates that clear
27691 * roce specific counters is supported.
27693 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
27696 * This field is used in Output records to indicate that the output
27697 * is completely written to RAM. This field should be read as '1'
27698 * to indicate that the output has been completely written.
27699 * When writing a command completion or response to an internal processor,
27700 * the order of writes has to be such that this field is written last.
27705 /*******************************
27706 * hwrm_port_qstats_ext_pfc_wd *
27707 *******************************/
27710 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
27711 struct hwrm_port_qstats_ext_pfc_wd_input {
27712 /* The HWRM command request type. */
27715 * The completion ring to send the completion event on. This should
27716 * be the NQ ID returned from the `nq_alloc` HWRM command.
27718 uint16_t cmpl_ring;
27720 * The sequence ID is used by the driver for tracking multiple
27721 * commands. This ID is treated as opaque data by the firmware and
27722 * the value is returned in the `hwrm_resp_hdr` upon completion.
27726 * The target ID of the command:
27727 * * 0x0-0xFFF8 - The function ID
27728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27729 * * 0xFFFD - Reserved for user-space HWRM interface
27732 uint16_t target_id;
27734 * A physical address pointer pointing to a host buffer that the
27735 * command's response data will be written. This can be either a host
27736 * physical address (HPA) or a guest physical address (GPA) and must
27737 * point to a physically contiguous block of memory.
27739 uint64_t resp_addr;
27740 /* Port ID of port that is being queried. */
27743 * The size of rx_port_stats_ext_pfc_wd
27746 uint16_t pfc_wd_stat_size;
27747 uint8_t unused_0[4];
27749 * This is the host address where
27750 * rx_port_stats_ext_pfc_wd will be stored
27752 uint64_t pfc_wd_stat_host_addr;
27755 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
27756 struct hwrm_port_qstats_ext_pfc_wd_output {
27757 /* The specific error status for the command. */
27758 uint16_t error_code;
27759 /* The HWRM command request type. */
27761 /* The sequence ID from the original command. */
27763 /* The length of the response data in number of bytes. */
27766 * The size of rx_port_stats_ext_pfc_wd
27767 * statistics block in bytes.
27769 uint16_t pfc_wd_stat_size;
27772 * This field is used in Output records to indicate that the output
27773 * is completely written to RAM. This field should be read as '1'
27774 * to indicate that the output has been completely written.
27775 * When writing a command completion or response to an internal processor,
27776 * the order of writes has to be such that this field is written last.
27779 uint8_t unused_0[4];
27782 /*************************
27783 * hwrm_port_lpbk_qstats *
27784 *************************/
27787 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
27788 struct hwrm_port_lpbk_qstats_input {
27789 /* The HWRM command request type. */
27792 * The completion ring to send the completion event on. This should
27793 * be the NQ ID returned from the `nq_alloc` HWRM command.
27795 uint16_t cmpl_ring;
27797 * The sequence ID is used by the driver for tracking multiple
27798 * commands. This ID is treated as opaque data by the firmware and
27799 * the value is returned in the `hwrm_resp_hdr` upon completion.
27803 * The target ID of the command:
27804 * * 0x0-0xFFF8 - The function ID
27805 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27806 * * 0xFFFD - Reserved for user-space HWRM interface
27809 uint16_t target_id;
27811 * A physical address pointer pointing to a host buffer that the
27812 * command's response data will be written. This can be either a host
27813 * physical address (HPA) or a guest physical address (GPA) and must
27814 * point to a physically contiguous block of memory.
27816 uint64_t resp_addr;
27819 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
27820 struct hwrm_port_lpbk_qstats_output {
27821 /* The specific error status for the command. */
27822 uint16_t error_code;
27823 /* The HWRM command request type. */
27825 /* The sequence ID from the original command. */
27827 /* The length of the response data in number of bytes. */
27829 /* Number of transmitted unicast frames */
27830 uint64_t lpbk_ucast_frames;
27831 /* Number of transmitted multicast frames */
27832 uint64_t lpbk_mcast_frames;
27833 /* Number of transmitted broadcast frames */
27834 uint64_t lpbk_bcast_frames;
27835 /* Number of transmitted bytes for unicast traffic */
27836 uint64_t lpbk_ucast_bytes;
27837 /* Number of transmitted bytes for multicast traffic */
27838 uint64_t lpbk_mcast_bytes;
27839 /* Number of transmitted bytes for broadcast traffic */
27840 uint64_t lpbk_bcast_bytes;
27841 /* Total Tx Drops for loopback traffic reported by STATS block */
27842 uint64_t tx_stat_discard;
27843 /* Total Tx Error Drops for loopback traffic reported by STATS block */
27844 uint64_t tx_stat_error;
27845 /* Total Rx Drops for loopback traffic reported by STATS block */
27846 uint64_t rx_stat_discard;
27847 /* Total Rx Error Drops for loopback traffic reported by STATS block */
27848 uint64_t rx_stat_error;
27849 uint8_t unused_0[7];
27851 * This field is used in Output records to indicate that the output
27852 * is completely written to RAM. This field should be read as '1'
27853 * to indicate that the output has been completely written.
27854 * When writing a command completion or response to an internal processor,
27855 * the order of writes has to be such that this field is written last.
27860 /************************
27861 * hwrm_port_ecn_qstats *
27862 ************************/
27865 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
27866 struct hwrm_port_ecn_qstats_input {
27867 /* The HWRM command request type. */
27870 * The completion ring to send the completion event on. This should
27871 * be the NQ ID returned from the `nq_alloc` HWRM command.
27873 uint16_t cmpl_ring;
27875 * The sequence ID is used by the driver for tracking multiple
27876 * commands. This ID is treated as opaque data by the firmware and
27877 * the value is returned in the `hwrm_resp_hdr` upon completion.
27881 * The target ID of the command:
27882 * * 0x0-0xFFF8 - The function ID
27883 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27884 * * 0xFFFD - Reserved for user-space HWRM interface
27887 uint16_t target_id;
27889 * A physical address pointer pointing to a host buffer that the
27890 * command's response data will be written. This can be either a host
27891 * physical address (HPA) or a guest physical address (GPA) and must
27892 * point to a physically contiguous block of memory.
27894 uint64_t resp_addr;
27896 * Port ID of port that is being queried. Unused if NIC is in
27901 * Size of the DMA buffer the caller has allocated for the firmware to
27904 uint16_t ecn_stat_buf_size;
27906 /* This value is not used to avoid backward compatibility issues. */
27907 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
27909 * This bit is set to 1 when request is for a counter mask,
27910 * representing the width of each of the stats counters, rather
27911 * than counters themselves.
27913 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
27914 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
27915 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
27916 uint8_t unused_0[3];
27918 * This is the host address where
27919 * ECN port statistics will be stored
27921 uint64_t ecn_stat_host_addr;
27924 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
27925 struct hwrm_port_ecn_qstats_output {
27926 /* The specific error status for the command. */
27927 uint16_t error_code;
27928 /* The HWRM command request type. */
27930 /* The sequence ID from the original command. */
27932 /* The length of the response data in number of bytes. */
27934 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
27935 uint16_t ecn_stat_buf_size;
27937 * Bitmask that indicates which CoS queues have ECN marking enabled.
27938 * Bit i corresponds to CoS queue i.
27941 uint8_t unused_0[4];
27943 * This field is used in Output records to indicate that the output
27944 * is completely written to RAM. This field should be read as '1'
27945 * to indicate that the output has been completely written.
27946 * When writing a command completion or response to an internal processor,
27947 * the order of writes has to be such that this field is written last.
27952 /* ECN mark statistics format */
27953 /* port_stats_ecn (size:512b/64B) */
27954 struct port_stats_ecn {
27956 * Number of packets marked in CoS queue 0.
27957 * Or, if the driver requested counter masks, a mask to indicate the size
27960 uint64_t mark_cnt_cos0;
27962 * Number of packets marked in CoS queue 1.
27963 * Or, if the driver requested counter masks, a mask to indicate the size
27966 uint64_t mark_cnt_cos1;
27968 * Number of packets marked in CoS queue 2.
27969 * Or, if the driver requested counter masks, a mask to indicate the size
27972 uint64_t mark_cnt_cos2;
27974 * Number of packets marked in CoS queue 3.
27975 * Or, if the driver requested counter masks, a mask to indicate the size
27978 uint64_t mark_cnt_cos3;
27980 * Number of packets marked in CoS queue 4.
27981 * Or, if the driver requested counter masks, a mask to indicate the size
27984 uint64_t mark_cnt_cos4;
27986 * Number of packets marked in CoS queue 5.
27987 * Or, if the driver requested counter masks, a mask to indicate the size
27990 uint64_t mark_cnt_cos5;
27992 * Number of packets marked in CoS queue 6.
27993 * Or, if the driver requested counter masks, a mask to indicate the size
27996 uint64_t mark_cnt_cos6;
27998 * Number of packets marked in CoS queue 7.
27999 * Or, if the driver requested counter masks, a mask to indicate the size
28002 uint64_t mark_cnt_cos7;
28005 /***********************
28006 * hwrm_port_clr_stats *
28007 ***********************/
28010 /* hwrm_port_clr_stats_input (size:192b/24B) */
28011 struct hwrm_port_clr_stats_input {
28012 /* The HWRM command request type. */
28015 * The completion ring to send the completion event on. This should
28016 * be the NQ ID returned from the `nq_alloc` HWRM command.
28018 uint16_t cmpl_ring;
28020 * The sequence ID is used by the driver for tracking multiple
28021 * commands. This ID is treated as opaque data by the firmware and
28022 * the value is returned in the `hwrm_resp_hdr` upon completion.
28026 * The target ID of the command:
28027 * * 0x0-0xFFF8 - The function ID
28028 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28029 * * 0xFFFD - Reserved for user-space HWRM interface
28032 uint16_t target_id;
28034 * A physical address pointer pointing to a host buffer that the
28035 * command's response data will be written. This can be either a host
28036 * physical address (HPA) or a guest physical address (GPA) and must
28037 * point to a physically contiguous block of memory.
28039 uint64_t resp_addr;
28040 /* Port ID of port that is being queried. */
28044 * If set to 1, then this field indicates clear the following RoCE
28045 * specific counters.
28046 * RoCE associated TX/RX cos counters
28047 * CNP associated TX/RX cos counters
28048 * RoCE/CNP specific TX/RX flow counters
28049 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
28050 * This flag is honored only when RoCE is enabled on that port.
28052 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
28053 uint8_t unused_0[5];
28056 /* hwrm_port_clr_stats_output (size:128b/16B) */
28057 struct hwrm_port_clr_stats_output {
28058 /* The specific error status for the command. */
28059 uint16_t error_code;
28060 /* The HWRM command request type. */
28062 /* The sequence ID from the original command. */
28064 /* The length of the response data in number of bytes. */
28066 uint8_t unused_0[7];
28068 * This field is used in Output records to indicate that the output
28069 * is completely written to RAM. This field should be read as '1'
28070 * to indicate that the output has been completely written.
28071 * When writing a command completion or response to an internal processor,
28072 * the order of writes has to be such that this field is written last.
28077 /***********************
28078 * hwrm_port_phy_qcaps *
28079 ***********************/
28082 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
28083 struct hwrm_port_phy_qcaps_input {
28084 /* The HWRM command request type. */
28087 * The completion ring to send the completion event on. This should
28088 * be the NQ ID returned from the `nq_alloc` HWRM command.
28090 uint16_t cmpl_ring;
28092 * The sequence ID is used by the driver for tracking multiple
28093 * commands. This ID is treated as opaque data by the firmware and
28094 * the value is returned in the `hwrm_resp_hdr` upon completion.
28098 * The target ID of the command:
28099 * * 0x0-0xFFF8 - The function ID
28100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28101 * * 0xFFFD - Reserved for user-space HWRM interface
28104 uint16_t target_id;
28106 * A physical address pointer pointing to a host buffer that the
28107 * command's response data will be written. This can be either a host
28108 * physical address (HPA) or a guest physical address (GPA) and must
28109 * point to a physically contiguous block of memory.
28111 uint64_t resp_addr;
28112 /* Port ID of port that is being queried. */
28114 uint8_t unused_0[6];
28117 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
28118 struct hwrm_port_phy_qcaps_output {
28119 /* The specific error status for the command. */
28120 uint16_t error_code;
28121 /* The HWRM command request type. */
28123 /* The sequence ID from the original command. */
28125 /* The length of the response data in number of bytes. */
28127 /* PHY capability flags */
28130 * If set to 1, then this field indicates that the
28131 * link is capable of supporting EEE.
28133 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
28136 * If set to 1, then this field indicates that the
28137 * PHY is capable of supporting external loopback.
28139 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
28142 * If set to 1, then this field indicates that the
28143 * PHY is capable of supporting loopback in autoneg mode.
28145 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
28148 * Indicates if the configuration of shared PHY settings is supported.
28149 * In cases where a physical port is shared by multiple functions
28150 * (e.g. NPAR, multihost, etc), the configuration of PHY
28151 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
28152 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
28154 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
28157 * If set to 1, it indicates that the port counters and extended
28158 * port counters will not reset when the firmware shuts down or
28159 * resets the PHY. These counters will only be reset during power
28160 * cycle or by calling HWRM_PORT_CLR_STATS.
28161 * If set to 0, the state of the counters is unspecified when
28162 * firmware shuts down or resets the PHY.
28164 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
28167 * If set to 1, then this field indicates that the
28168 * local loopback is not supported on this controller.
28170 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
28173 * If set to 1, then this field indicates that the
28174 * PHY/Link down policy during PF shutdown is totally
28175 * controlled by the firmware. It can shutdown the link
28176 * even when there are active VFs associated with the PF.
28177 * Host PF driver can send HWRM_PHY_CFG command to bring
28178 * down the PHY even when the port is shared between VFs
28181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
28184 * If set to 1, this field indicates that the FCS may
28185 * be disabled for a given packet via the transmit
28186 * buffer descriptor.
28188 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
28190 /* Number of front panel ports for this device. */
28192 /* Not supported or unknown */
28193 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
28194 /* single port device */
28195 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
28196 /* 2-port device */
28197 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
28198 /* 3-port device */
28199 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
28200 /* 4-port device */
28201 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
28202 /* 12-port device */
28203 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc)
28204 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
28205 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12
28207 * This is a bit mask to indicate what speeds are supported
28208 * as forced speeds on this link.
28209 * For each speed that can be forced on this link, the
28210 * corresponding mask bit shall be set to '1'.
28212 uint16_t supported_speeds_force_mode;
28213 /* 100Mb link speed (Half-duplex) */
28214 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
28216 /* 100Mb link speed (Full-duplex) */
28217 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
28219 /* 1Gb link speed (Half-duplex) */
28220 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
28222 /* 1Gb link speed (Full-duplex) */
28223 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
28225 /* 2Gb link speed */
28226 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
28228 /* 25Gb link speed */
28229 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
28231 /* 10Gb link speed */
28232 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
28234 /* 20Gb link speed */
28235 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
28237 /* 25Gb link speed */
28238 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
28240 /* 40Gb link speed */
28241 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
28243 /* 50Gb link speed */
28244 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
28246 /* 100Gb link speed */
28247 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
28249 /* 10Mb link speed (Half-duplex) */
28250 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
28252 /* 10Mb link speed (Full-duplex) */
28253 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
28256 * This is a bit mask to indicate what speeds are supported
28257 * for autonegotiation on this link.
28258 * For each speed that can be autonegotiated on this link, the
28259 * corresponding mask bit shall be set to '1'.
28261 uint16_t supported_speeds_auto_mode;
28262 /* 100Mb link speed (Half-duplex) */
28263 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
28265 /* 100Mb link speed (Full-duplex) */
28266 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
28268 /* 1Gb link speed (Half-duplex) */
28269 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
28271 /* 1Gb link speed (Full-duplex) */
28272 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
28274 /* 2Gb link speed */
28275 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
28277 /* 25Gb link speed */
28278 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
28280 /* 10Gb link speed */
28281 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
28283 /* 20Gb link speed */
28284 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
28286 /* 25Gb link speed */
28287 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
28289 /* 40Gb link speed */
28290 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
28292 /* 50Gb link speed */
28293 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
28295 /* 100Gb link speed */
28296 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
28298 /* 10Mb link speed (Half-duplex) */
28299 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
28301 /* 10Mb link speed (Full-duplex) */
28302 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
28305 * This is a bit mask to indicate what speeds are supported
28306 * for EEE on this link.
28307 * For each speed that can be autonegotiated when EEE is enabled
28308 * on this link, the corresponding mask bit shall be set to '1'.
28309 * This field is only valid when the eee_supported is set to '1'.
28311 uint16_t supported_speeds_eee_mode;
28313 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
28315 /* 100Mb link speed (Full-duplex) */
28316 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
28319 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
28321 /* 1Gb link speed (Full-duplex) */
28322 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
28325 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
28328 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
28330 /* 10Gb link speed */
28331 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
28333 uint32_t tx_lpi_timer_low;
28335 * The lowest value of TX LPI timer that can be set on this link
28336 * when EEE is enabled. This value is in microseconds.
28337 * This field is valid only when_eee_supported is set to '1'.
28339 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
28341 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
28343 * Reserved field. The HWRM shall set this field to 0.
28344 * An HWRM client shall ignore this field.
28346 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
28347 UINT32_C(0xff000000)
28348 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
28349 uint32_t valid_tx_lpi_timer_high;
28351 * The highest value of TX LPI timer that can be set on this link
28352 * when EEE is enabled. This value is in microseconds.
28353 * This field is valid only when_eee_supported is set to '1'.
28355 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
28357 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
28359 * Reserved field. The HWRM shall set this field to 0.
28360 * An HWRM client shall ignore this field.
28362 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
28363 UINT32_C(0xff000000)
28364 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
28366 * This field is used to advertise which PAM4 speeds are supported
28369 uint16_t supported_pam4_speeds_auto_mode;
28370 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
28372 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
28374 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
28377 * This field is used to advertise which PAM4 speeds are supported
28380 uint16_t supported_pam4_speeds_force_mode;
28381 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
28383 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
28385 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
28387 /* More PHY capability flags */
28390 * If set to 1, then this field indicates that
28391 * 802.3x flow control is not supported.
28393 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \
28396 * If set to 1, then this field indicates that
28397 * priority-based flow control is not supported.
28399 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \
28402 * Number of internal ports for this device. This field allows the FW
28403 * to advertise how many internal ports are present. Manufacturing
28404 * tools uses this to determine how many internal ports should have
28405 * the PRBS test run on them. This field always return 0 unless NVM
28406 * option "HPTN_MODE" is set to 1.
28408 uint8_t internal_port_cnt;
28410 * This field is used in Output records to indicate that the output
28411 * is completely written to RAM. This field should be read as '1'
28412 * to indicate that the output has been completely written.
28413 * When writing a command completion or response to an internal processor,
28414 * the order of writes has to be such that this field is written last.
28419 /****************************
28420 * hwrm_port_phy_mdio_write *
28421 ****************************/
28424 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
28425 struct hwrm_port_phy_mdio_write_input {
28426 /* The HWRM command request type. */
28429 * The completion ring to send the completion event on. This should
28430 * be the NQ ID returned from the `nq_alloc` HWRM command.
28432 uint16_t cmpl_ring;
28434 * The sequence ID is used by the driver for tracking multiple
28435 * commands. This ID is treated as opaque data by the firmware and
28436 * the value is returned in the `hwrm_resp_hdr` upon completion.
28440 * The target ID of the command:
28441 * * 0x0-0xFFF8 - The function ID
28442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28443 * * 0xFFFD - Reserved for user-space HWRM interface
28446 uint16_t target_id;
28448 * A physical address pointer pointing to a host buffer that the
28449 * command's response data will be written. This can be either a host
28450 * physical address (HPA) or a guest physical address (GPA) and must
28451 * point to a physically contiguous block of memory.
28453 uint64_t resp_addr;
28454 /* Reserved for future use. */
28455 uint32_t unused_0[2];
28456 /* Port ID of port. */
28458 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
28460 /* 8-bit device address. */
28462 /* 16-bit register address. */
28464 /* 16-bit register data. */
28467 * When this bit is set to 1 a Clause 45 mdio access is done.
28468 * when this bit is set to 0 a Clause 22 mdio access is done.
28472 uint8_t unused_1[7];
28475 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
28476 struct hwrm_port_phy_mdio_write_output {
28477 /* The specific error status for the command. */
28478 uint16_t error_code;
28479 /* The HWRM command request type. */
28481 /* The sequence ID from the original command. */
28483 /* The length of the response data in number of bytes. */
28485 uint8_t unused_0[7];
28487 * This field is used in Output records to indicate that the output
28488 * is completely written to RAM. This field should be read as '1'
28489 * to indicate that the output has been completely written.
28490 * When writing a command completion or response to an internal processor,
28491 * the order of writes has to be such that this field is written last.
28496 /***************************
28497 * hwrm_port_phy_mdio_read *
28498 ***************************/
28501 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
28502 struct hwrm_port_phy_mdio_read_input {
28503 /* The HWRM command request type. */
28506 * The completion ring to send the completion event on. This should
28507 * be the NQ ID returned from the `nq_alloc` HWRM command.
28509 uint16_t cmpl_ring;
28511 * The sequence ID is used by the driver for tracking multiple
28512 * commands. This ID is treated as opaque data by the firmware and
28513 * the value is returned in the `hwrm_resp_hdr` upon completion.
28517 * The target ID of the command:
28518 * * 0x0-0xFFF8 - The function ID
28519 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28520 * * 0xFFFD - Reserved for user-space HWRM interface
28523 uint16_t target_id;
28525 * A physical address pointer pointing to a host buffer that the
28526 * command's response data will be written. This can be either a host
28527 * physical address (HPA) or a guest physical address (GPA) and must
28528 * point to a physically contiguous block of memory.
28530 uint64_t resp_addr;
28531 /* Reserved for future use. */
28532 uint32_t unused_0[2];
28533 /* Port ID of port. */
28535 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
28537 /* 8-bit device address. */
28539 /* 16-bit register address. */
28542 * When this bit is set to 1 a Clause 45 mdio access is done.
28543 * when this bit is set to 0 a Clause 22 mdio access is done.
28550 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
28551 struct hwrm_port_phy_mdio_read_output {
28552 /* The specific error status for the command. */
28553 uint16_t error_code;
28554 /* The HWRM command request type. */
28556 /* The sequence ID from the original command. */
28558 /* The length of the response data in number of bytes. */
28560 /* 16-bit register data. */
28562 uint8_t unused_0[5];
28564 * This field is used in Output records to indicate that the output
28565 * is completely written to RAM. This field should be read as '1'
28566 * to indicate that the output has been completely written.
28567 * When writing a command completion or response to an internal processor,
28568 * the order of writes has to be such that this field is written last.
28573 /*********************
28574 * hwrm_port_led_cfg *
28575 *********************/
28578 /* hwrm_port_led_cfg_input (size:512b/64B) */
28579 struct hwrm_port_led_cfg_input {
28580 /* The HWRM command request type. */
28583 * The completion ring to send the completion event on. This should
28584 * be the NQ ID returned from the `nq_alloc` HWRM command.
28586 uint16_t cmpl_ring;
28588 * The sequence ID is used by the driver for tracking multiple
28589 * commands. This ID is treated as opaque data by the firmware and
28590 * the value is returned in the `hwrm_resp_hdr` upon completion.
28594 * The target ID of the command:
28595 * * 0x0-0xFFF8 - The function ID
28596 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28597 * * 0xFFFD - Reserved for user-space HWRM interface
28600 uint16_t target_id;
28602 * A physical address pointer pointing to a host buffer that the
28603 * command's response data will be written. This can be either a host
28604 * physical address (HPA) or a guest physical address (GPA) and must
28605 * point to a physically contiguous block of memory.
28607 uint64_t resp_addr;
28610 * This bit must be '1' for the led0_id field to be
28613 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
28616 * This bit must be '1' for the led0_state field to be
28619 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
28622 * This bit must be '1' for the led0_color field to be
28625 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
28628 * This bit must be '1' for the led0_blink_on field to be
28631 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
28634 * This bit must be '1' for the led0_blink_off field to be
28637 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
28640 * This bit must be '1' for the led0_group_id field to be
28643 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
28646 * This bit must be '1' for the led1_id field to be
28649 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
28652 * This bit must be '1' for the led1_state field to be
28655 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
28658 * This bit must be '1' for the led1_color field to be
28661 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
28664 * This bit must be '1' for the led1_blink_on field to be
28667 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
28670 * This bit must be '1' for the led1_blink_off field to be
28673 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
28676 * This bit must be '1' for the led1_group_id field to be
28679 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
28682 * This bit must be '1' for the led2_id field to be
28685 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
28688 * This bit must be '1' for the led2_state field to be
28691 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
28694 * This bit must be '1' for the led2_color field to be
28697 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
28700 * This bit must be '1' for the led2_blink_on field to be
28703 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
28706 * This bit must be '1' for the led2_blink_off field to be
28709 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
28712 * This bit must be '1' for the led2_group_id field to be
28715 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
28718 * This bit must be '1' for the led3_id field to be
28721 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
28724 * This bit must be '1' for the led3_state field to be
28727 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
28730 * This bit must be '1' for the led3_color field to be
28733 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
28736 * This bit must be '1' for the led3_blink_on field to be
28739 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
28742 * This bit must be '1' for the led3_blink_off field to be
28745 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
28748 * This bit must be '1' for the led3_group_id field to be
28751 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
28753 /* Port ID of port whose LEDs are configured. */
28756 * The number of LEDs that are being configured.
28757 * Up to 4 LEDs can be configured with this command.
28760 /* Reserved field. */
28762 /* An identifier for the LED #0. */
28764 /* The requested state of the LED #0. */
28765 uint8_t led0_state;
28766 /* Default state of the LED */
28767 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
28769 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
28771 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
28773 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
28774 /* Blink Alternately */
28775 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
28776 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
28777 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
28778 /* The requested color of LED #0. */
28779 uint8_t led0_color;
28781 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
28783 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
28785 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
28786 /* Green or Amber */
28787 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
28788 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
28789 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
28792 * If the LED #0 state is "blink" or "blinkalt", then
28793 * this field represents the requested time in milliseconds
28794 * to keep LED on between cycles.
28796 uint16_t led0_blink_on;
28798 * If the LED #0 state is "blink" or "blinkalt", then
28799 * this field represents the requested time in milliseconds
28800 * to keep LED off between cycles.
28802 uint16_t led0_blink_off;
28804 * An identifier for the group of LEDs that LED #0 belongs
28806 * If set to 0, then the LED #0 shall not be grouped and
28807 * shall be treated as an individual resource.
28808 * For all other non-zero values of this field, LED #0 shall
28809 * be grouped together with the LEDs with the same group ID
28812 uint8_t led0_group_id;
28813 /* Reserved field. */
28815 /* An identifier for the LED #1. */
28817 /* The requested state of the LED #1. */
28818 uint8_t led1_state;
28819 /* Default state of the LED */
28820 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
28822 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
28824 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
28826 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
28827 /* Blink Alternately */
28828 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
28829 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
28830 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
28831 /* The requested color of LED #1. */
28832 uint8_t led1_color;
28834 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
28836 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
28838 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
28839 /* Green or Amber */
28840 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
28841 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
28842 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
28845 * If the LED #1 state is "blink" or "blinkalt", then
28846 * this field represents the requested time in milliseconds
28847 * to keep LED on between cycles.
28849 uint16_t led1_blink_on;
28851 * If the LED #1 state is "blink" or "blinkalt", then
28852 * this field represents the requested time in milliseconds
28853 * to keep LED off between cycles.
28855 uint16_t led1_blink_off;
28857 * An identifier for the group of LEDs that LED #1 belongs
28859 * If set to 0, then the LED #1 shall not be grouped and
28860 * shall be treated as an individual resource.
28861 * For all other non-zero values of this field, LED #1 shall
28862 * be grouped together with the LEDs with the same group ID
28865 uint8_t led1_group_id;
28866 /* Reserved field. */
28868 /* An identifier for the LED #2. */
28870 /* The requested state of the LED #2. */
28871 uint8_t led2_state;
28872 /* Default state of the LED */
28873 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
28875 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
28877 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
28879 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
28880 /* Blink Alternately */
28881 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
28882 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
28883 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
28884 /* The requested color of LED #2. */
28885 uint8_t led2_color;
28887 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
28889 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
28891 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
28892 /* Green or Amber */
28893 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
28894 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
28895 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
28898 * If the LED #2 state is "blink" or "blinkalt", then
28899 * this field represents the requested time in milliseconds
28900 * to keep LED on between cycles.
28902 uint16_t led2_blink_on;
28904 * If the LED #2 state is "blink" or "blinkalt", then
28905 * this field represents the requested time in milliseconds
28906 * to keep LED off between cycles.
28908 uint16_t led2_blink_off;
28910 * An identifier for the group of LEDs that LED #2 belongs
28912 * If set to 0, then the LED #2 shall not be grouped and
28913 * shall be treated as an individual resource.
28914 * For all other non-zero values of this field, LED #2 shall
28915 * be grouped together with the LEDs with the same group ID
28918 uint8_t led2_group_id;
28919 /* Reserved field. */
28921 /* An identifier for the LED #3. */
28923 /* The requested state of the LED #3. */
28924 uint8_t led3_state;
28925 /* Default state of the LED */
28926 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
28928 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
28930 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
28932 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
28933 /* Blink Alternately */
28934 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
28935 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
28936 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
28937 /* The requested color of LED #3. */
28938 uint8_t led3_color;
28940 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
28942 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
28944 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
28945 /* Green or Amber */
28946 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
28947 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
28948 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
28951 * If the LED #3 state is "blink" or "blinkalt", then
28952 * this field represents the requested time in milliseconds
28953 * to keep LED on between cycles.
28955 uint16_t led3_blink_on;
28957 * If the LED #3 state is "blink" or "blinkalt", then
28958 * this field represents the requested time in milliseconds
28959 * to keep LED off between cycles.
28961 uint16_t led3_blink_off;
28963 * An identifier for the group of LEDs that LED #3 belongs
28965 * If set to 0, then the LED #3 shall not be grouped and
28966 * shall be treated as an individual resource.
28967 * For all other non-zero values of this field, LED #3 shall
28968 * be grouped together with the LEDs with the same group ID
28971 uint8_t led3_group_id;
28972 /* Reserved field. */
28976 /* hwrm_port_led_cfg_output (size:128b/16B) */
28977 struct hwrm_port_led_cfg_output {
28978 /* The specific error status for the command. */
28979 uint16_t error_code;
28980 /* The HWRM command request type. */
28982 /* The sequence ID from the original command. */
28984 /* The length of the response data in number of bytes. */
28986 uint8_t unused_0[7];
28988 * This field is used in Output records to indicate that the output
28989 * is completely written to RAM. This field should be read as '1'
28990 * to indicate that the output has been completely written.
28991 * When writing a command completion or response to an internal processor,
28992 * the order of writes has to be such that this field is written last.
28997 /**********************
28998 * hwrm_port_led_qcfg *
28999 **********************/
29002 /* hwrm_port_led_qcfg_input (size:192b/24B) */
29003 struct hwrm_port_led_qcfg_input {
29004 /* The HWRM command request type. */
29007 * The completion ring to send the completion event on. This should
29008 * be the NQ ID returned from the `nq_alloc` HWRM command.
29010 uint16_t cmpl_ring;
29012 * The sequence ID is used by the driver for tracking multiple
29013 * commands. This ID is treated as opaque data by the firmware and
29014 * the value is returned in the `hwrm_resp_hdr` upon completion.
29018 * The target ID of the command:
29019 * * 0x0-0xFFF8 - The function ID
29020 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29021 * * 0xFFFD - Reserved for user-space HWRM interface
29024 uint16_t target_id;
29026 * A physical address pointer pointing to a host buffer that the
29027 * command's response data will be written. This can be either a host
29028 * physical address (HPA) or a guest physical address (GPA) and must
29029 * point to a physically contiguous block of memory.
29031 uint64_t resp_addr;
29032 /* Port ID of port whose LED configuration is being queried. */
29034 uint8_t unused_0[6];
29037 /* hwrm_port_led_qcfg_output (size:448b/56B) */
29038 struct hwrm_port_led_qcfg_output {
29039 /* The specific error status for the command. */
29040 uint16_t error_code;
29041 /* The HWRM command request type. */
29043 /* The sequence ID from the original command. */
29045 /* The length of the response data in number of bytes. */
29048 * The number of LEDs that are configured on this port.
29049 * Up to 4 LEDs can be returned in the response.
29052 /* An identifier for the LED #0. */
29054 /* The type of LED #0. */
29057 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
29059 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
29061 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
29062 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
29063 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
29064 /* The current state of the LED #0. */
29065 uint8_t led0_state;
29066 /* Default state of the LED */
29067 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
29069 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
29071 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
29073 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
29074 /* Blink Alternately */
29075 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
29076 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
29077 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
29078 /* The color of LED #0. */
29079 uint8_t led0_color;
29081 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
29083 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
29085 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
29086 /* Green or Amber */
29087 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
29088 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
29089 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
29092 * If the LED #0 state is "blink" or "blinkalt", then
29093 * this field represents the requested time in milliseconds
29094 * to keep LED on between cycles.
29096 uint16_t led0_blink_on;
29098 * If the LED #0 state is "blink" or "blinkalt", then
29099 * this field represents the requested time in milliseconds
29100 * to keep LED off between cycles.
29102 uint16_t led0_blink_off;
29104 * An identifier for the group of LEDs that LED #0 belongs
29106 * If set to 0, then the LED #0 is not grouped.
29107 * For all other non-zero values of this field, LED #0 is
29108 * grouped together with the LEDs with the same group ID
29111 uint8_t led0_group_id;
29112 /* An identifier for the LED #1. */
29114 /* The type of LED #1. */
29117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
29119 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
29121 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
29122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
29123 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
29124 /* The current state of the LED #1. */
29125 uint8_t led1_state;
29126 /* Default state of the LED */
29127 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
29129 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
29131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
29133 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
29134 /* Blink Alternately */
29135 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
29136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
29137 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
29138 /* The color of LED #1. */
29139 uint8_t led1_color;
29141 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
29143 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
29145 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
29146 /* Green or Amber */
29147 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
29148 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
29149 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
29152 * If the LED #1 state is "blink" or "blinkalt", then
29153 * this field represents the requested time in milliseconds
29154 * to keep LED on between cycles.
29156 uint16_t led1_blink_on;
29158 * If the LED #1 state is "blink" or "blinkalt", then
29159 * this field represents the requested time in milliseconds
29160 * to keep LED off between cycles.
29162 uint16_t led1_blink_off;
29164 * An identifier for the group of LEDs that LED #1 belongs
29166 * If set to 0, then the LED #1 is not grouped.
29167 * For all other non-zero values of this field, LED #1 is
29168 * grouped together with the LEDs with the same group ID
29171 uint8_t led1_group_id;
29172 /* An identifier for the LED #2. */
29174 /* The type of LED #2. */
29177 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
29179 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
29181 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
29182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
29183 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
29184 /* The current state of the LED #2. */
29185 uint8_t led2_state;
29186 /* Default state of the LED */
29187 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
29189 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
29191 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
29193 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
29194 /* Blink Alternately */
29195 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
29196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
29197 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
29198 /* The color of LED #2. */
29199 uint8_t led2_color;
29201 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
29203 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
29205 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
29206 /* Green or Amber */
29207 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
29208 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
29209 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
29212 * If the LED #2 state is "blink" or "blinkalt", then
29213 * this field represents the requested time in milliseconds
29214 * to keep LED on between cycles.
29216 uint16_t led2_blink_on;
29218 * If the LED #2 state is "blink" or "blinkalt", then
29219 * this field represents the requested time in milliseconds
29220 * to keep LED off between cycles.
29222 uint16_t led2_blink_off;
29224 * An identifier for the group of LEDs that LED #2 belongs
29226 * If set to 0, then the LED #2 is not grouped.
29227 * For all other non-zero values of this field, LED #2 is
29228 * grouped together with the LEDs with the same group ID
29231 uint8_t led2_group_id;
29232 /* An identifier for the LED #3. */
29234 /* The type of LED #3. */
29237 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
29239 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
29241 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
29242 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
29243 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
29244 /* The current state of the LED #3. */
29245 uint8_t led3_state;
29246 /* Default state of the LED */
29247 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
29249 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
29251 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
29253 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
29254 /* Blink Alternately */
29255 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
29256 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
29257 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
29258 /* The color of LED #3. */
29259 uint8_t led3_color;
29261 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
29263 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
29265 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
29266 /* Green or Amber */
29267 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
29268 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
29269 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
29272 * If the LED #3 state is "blink" or "blinkalt", then
29273 * this field represents the requested time in milliseconds
29274 * to keep LED on between cycles.
29276 uint16_t led3_blink_on;
29278 * If the LED #3 state is "blink" or "blinkalt", then
29279 * this field represents the requested time in milliseconds
29280 * to keep LED off between cycles.
29282 uint16_t led3_blink_off;
29284 * An identifier for the group of LEDs that LED #3 belongs
29286 * If set to 0, then the LED #3 is not grouped.
29287 * For all other non-zero values of this field, LED #3 is
29288 * grouped together with the LEDs with the same group ID
29291 uint8_t led3_group_id;
29292 uint8_t unused_4[6];
29294 * This field is used in Output records to indicate that the output
29295 * is completely written to RAM. This field should be read as '1'
29296 * to indicate that the output has been completely written.
29297 * When writing a command completion or response to an internal processor,
29298 * the order of writes has to be such that this field is written last.
29303 /***********************
29304 * hwrm_port_led_qcaps *
29305 ***********************/
29308 /* hwrm_port_led_qcaps_input (size:192b/24B) */
29309 struct hwrm_port_led_qcaps_input {
29310 /* The HWRM command request type. */
29313 * The completion ring to send the completion event on. This should
29314 * be the NQ ID returned from the `nq_alloc` HWRM command.
29316 uint16_t cmpl_ring;
29318 * The sequence ID is used by the driver for tracking multiple
29319 * commands. This ID is treated as opaque data by the firmware and
29320 * the value is returned in the `hwrm_resp_hdr` upon completion.
29324 * The target ID of the command:
29325 * * 0x0-0xFFF8 - The function ID
29326 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29327 * * 0xFFFD - Reserved for user-space HWRM interface
29330 uint16_t target_id;
29332 * A physical address pointer pointing to a host buffer that the
29333 * command's response data will be written. This can be either a host
29334 * physical address (HPA) or a guest physical address (GPA) and must
29335 * point to a physically contiguous block of memory.
29337 uint64_t resp_addr;
29338 /* Port ID of port whose LED configuration is being queried. */
29340 uint8_t unused_0[6];
29343 /* hwrm_port_led_qcaps_output (size:384b/48B) */
29344 struct hwrm_port_led_qcaps_output {
29345 /* The specific error status for the command. */
29346 uint16_t error_code;
29347 /* The HWRM command request type. */
29349 /* The sequence ID from the original command. */
29351 /* The length of the response data in number of bytes. */
29354 * The number of LEDs that are configured on this port.
29355 * Up to 4 LEDs can be returned in the response.
29358 /* Reserved for future use. */
29360 /* An identifier for the LED #0. */
29362 /* The type of LED #0. */
29365 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
29367 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
29369 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
29370 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
29371 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
29373 * An identifier for the group of LEDs that LED #0 belongs
29375 * If set to 0, then the LED #0 cannot be grouped.
29376 * For all other non-zero values of this field, LED #0 is
29377 * grouped together with the LEDs with the same group ID
29380 uint8_t led0_group_id;
29382 /* The states supported by LED #0. */
29383 uint16_t led0_state_caps;
29385 * If set to 1, this LED is enabled.
29386 * If set to 0, this LED is disabled.
29388 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
29391 * If set to 1, off state is supported on this LED.
29392 * If set to 0, off state is not supported on this LED.
29394 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
29397 * If set to 1, on state is supported on this LED.
29398 * If set to 0, on state is not supported on this LED.
29400 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
29403 * If set to 1, blink state is supported on this LED.
29404 * If set to 0, blink state is not supported on this LED.
29406 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
29409 * If set to 1, blink_alt state is supported on this LED.
29410 * If set to 0, blink_alt state is not supported on this LED.
29412 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
29414 /* The colors supported by LED #0. */
29415 uint16_t led0_color_caps;
29417 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
29420 * If set to 1, Amber color is supported on this LED.
29421 * If set to 0, Amber color is not supported on this LED.
29423 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
29426 * If set to 1, Green color is supported on this LED.
29427 * If set to 0, Green color is not supported on this LED.
29429 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
29431 /* An identifier for the LED #1. */
29433 /* The type of LED #1. */
29436 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
29438 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
29440 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
29441 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
29442 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
29444 * An identifier for the group of LEDs that LED #1 belongs
29446 * If set to 0, then the LED #0 cannot be grouped.
29447 * For all other non-zero values of this field, LED #0 is
29448 * grouped together with the LEDs with the same group ID
29451 uint8_t led1_group_id;
29453 /* The states supported by LED #1. */
29454 uint16_t led1_state_caps;
29456 * If set to 1, this LED is enabled.
29457 * If set to 0, this LED is disabled.
29459 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
29462 * If set to 1, off state is supported on this LED.
29463 * If set to 0, off state is not supported on this LED.
29465 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
29468 * If set to 1, on state is supported on this LED.
29469 * If set to 0, on state is not supported on this LED.
29471 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
29474 * If set to 1, blink state is supported on this LED.
29475 * If set to 0, blink state is not supported on this LED.
29477 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
29480 * If set to 1, blink_alt state is supported on this LED.
29481 * If set to 0, blink_alt state is not supported on this LED.
29483 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
29485 /* The colors supported by LED #1. */
29486 uint16_t led1_color_caps;
29488 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
29491 * If set to 1, Amber color is supported on this LED.
29492 * If set to 0, Amber color is not supported on this LED.
29494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
29497 * If set to 1, Green color is supported on this LED.
29498 * If set to 0, Green color is not supported on this LED.
29500 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
29502 /* An identifier for the LED #2. */
29504 /* The type of LED #2. */
29507 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
29509 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
29511 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
29512 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
29513 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
29515 * An identifier for the group of LEDs that LED #0 belongs
29517 * If set to 0, then the LED #0 cannot be grouped.
29518 * For all other non-zero values of this field, LED #0 is
29519 * grouped together with the LEDs with the same group ID
29522 uint8_t led2_group_id;
29524 /* The states supported by LED #2. */
29525 uint16_t led2_state_caps;
29527 * If set to 1, this LED is enabled.
29528 * If set to 0, this LED is disabled.
29530 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
29533 * If set to 1, off state is supported on this LED.
29534 * If set to 0, off state is not supported on this LED.
29536 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
29539 * If set to 1, on state is supported on this LED.
29540 * If set to 0, on state is not supported on this LED.
29542 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
29545 * If set to 1, blink state is supported on this LED.
29546 * If set to 0, blink state is not supported on this LED.
29548 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
29551 * If set to 1, blink_alt state is supported on this LED.
29552 * If set to 0, blink_alt state is not supported on this LED.
29554 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
29556 /* The colors supported by LED #2. */
29557 uint16_t led2_color_caps;
29559 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
29562 * If set to 1, Amber color is supported on this LED.
29563 * If set to 0, Amber color is not supported on this LED.
29565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
29568 * If set to 1, Green color is supported on this LED.
29569 * If set to 0, Green color is not supported on this LED.
29571 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
29573 /* An identifier for the LED #3. */
29575 /* The type of LED #3. */
29578 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
29580 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
29582 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
29583 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
29584 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
29586 * An identifier for the group of LEDs that LED #3 belongs
29588 * If set to 0, then the LED #0 cannot be grouped.
29589 * For all other non-zero values of this field, LED #0 is
29590 * grouped together with the LEDs with the same group ID
29593 uint8_t led3_group_id;
29595 /* The states supported by LED #3. */
29596 uint16_t led3_state_caps;
29598 * If set to 1, this LED is enabled.
29599 * If set to 0, this LED is disabled.
29601 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
29604 * If set to 1, off state is supported on this LED.
29605 * If set to 0, off state is not supported on this LED.
29607 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
29610 * If set to 1, on state is supported on this LED.
29611 * If set to 0, on state is not supported on this LED.
29613 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
29616 * If set to 1, blink state is supported on this LED.
29617 * If set to 0, blink state is not supported on this LED.
29619 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
29622 * If set to 1, blink_alt state is supported on this LED.
29623 * If set to 0, blink_alt state is not supported on this LED.
29625 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
29627 /* The colors supported by LED #3. */
29628 uint16_t led3_color_caps;
29630 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
29633 * If set to 1, Amber color is supported on this LED.
29634 * If set to 0, Amber color is not supported on this LED.
29636 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
29639 * If set to 1, Green color is supported on this LED.
29640 * If set to 0, Green color is not supported on this LED.
29642 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
29644 uint8_t unused_4[3];
29646 * This field is used in Output records to indicate that the output
29647 * is completely written to RAM. This field should be read as '1'
29648 * to indicate that the output has been completely written.
29649 * When writing a command completion or response to an internal processor,
29650 * the order of writes has to be such that this field is written last.
29655 /***********************
29656 * hwrm_port_prbs_test *
29657 ***********************/
29660 /* hwrm_port_prbs_test_input (size:384b/48B) */
29661 struct hwrm_port_prbs_test_input {
29662 /* The HWRM command request type. */
29665 * The completion ring to send the completion event on. This should
29666 * be the NQ ID returned from the `nq_alloc` HWRM command.
29668 uint16_t cmpl_ring;
29670 * The sequence ID is used by the driver for tracking multiple
29671 * commands. This ID is treated as opaque data by the firmware and
29672 * the value is returned in the `hwrm_resp_hdr` upon completion.
29676 * The target ID of the command:
29677 * * 0x0-0xFFF8 - The function ID
29678 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29679 * * 0xFFFD - Reserved for user-space HWRM interface
29682 uint16_t target_id;
29684 * A physical address pointer pointing to a host buffer that the
29685 * command's response data will be written. This can be either a host
29686 * physical address (HPA) or a guest physical address (GPA) and must
29687 * point to a physically contiguous block of memory.
29689 uint64_t resp_addr;
29690 /* Host address data is to DMA'd to. */
29691 uint64_t resp_data_addr;
29693 * Size of the buffer pointed to by resp_data_addr. The firmware may
29694 * use this entire buffer or less than the entire buffer, but never more.
29699 * If set, the port_id field should be interpreted as an internal
29700 * port. The internal port id range is returned in port_phy_qcaps
29701 * response internal_port_cnt field.
29703 #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1)
29705 /* Port ID of port where PRBS test to be run. */
29707 /* Polynomial selection for PRBS test. */
29710 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
29712 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
29714 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
29716 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
29718 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
29720 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
29722 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
29724 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
29725 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
29726 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
29728 * Configuration bits for PRBS test.
29729 * Use enable bit to start/stop test.
29730 * Use tx/rx lane map bits to run test on specific lanes,
29731 * if set to 0 test will be run on all lanes.
29733 uint16_t prbs_config;
29735 * Set 0 to stop test currently in progress
29736 * Set 1 to start test with configuration provided.
29738 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
29741 * If set to 1, tx_lane_map bitmap should have lane bits set.
29742 * If set to 0, test will be run on all lanes for this port.
29744 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
29747 * If set to 1, rx_lane_map bitmap should have lane bits set.
29748 * If set to 0, test will be run on all lanes for this port.
29750 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
29752 /* Duration in seconds to run the PRBS test. */
29755 * If tx_lane_map_valid is set to 1, this field is a bitmap
29756 * of tx lanes to run PRBS test. bit0 = lane0,
29757 * bit1 = lane1 ..bit31 = lane31
29759 uint32_t tx_lane_map;
29761 * If rx_lane_map_valid is set to 1, this field is a bitmap
29762 * of rx lanes to run PRBS test. bit0 = lane0,
29763 * bit1 = lane1 ..bit31 = lane31
29765 uint32_t rx_lane_map;
29768 /* hwrm_port_prbs_test_output (size:128b/16B) */
29769 struct hwrm_port_prbs_test_output {
29770 /* The specific error status for the command. */
29771 uint16_t error_code;
29772 /* The HWRM command request type. */
29774 /* The sequence ID from the original command. */
29776 /* The length of the response data in number of bytes. */
29778 /* Total length of stored data. */
29779 uint16_t total_data_len;
29781 uint8_t unused_1[3];
29783 * This field is used in Output records to indicate that the output
29784 * is completely written to RAM. This field should be read as '1'
29785 * to indicate that the output has been completely written.
29786 * When writing a command completion or response to an internal processor,
29787 * the order of writes has to be such that this field is written last.
29792 /**********************
29793 * hwrm_port_dsc_dump *
29794 **********************/
29797 /* hwrm_port_dsc_dump_input (size:320b/40B) */
29798 struct hwrm_port_dsc_dump_input {
29799 /* The HWRM command request type. */
29802 * The completion ring to send the completion event on. This should
29803 * be the NQ ID returned from the `nq_alloc` HWRM command.
29805 uint16_t cmpl_ring;
29807 * The sequence ID is used by the driver for tracking multiple
29808 * commands. This ID is treated as opaque data by the firmware and
29809 * the value is returned in the `hwrm_resp_hdr` upon completion.
29813 * The target ID of the command:
29814 * * 0x0-0xFFF8 - The function ID
29815 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29816 * * 0xFFFD - Reserved for user-space HWRM interface
29819 uint16_t target_id;
29821 * A physical address pointer pointing to a host buffer that the
29822 * command's response data will be written. This can be either a host
29823 * physical address (HPA) or a guest physical address (GPA) and must
29824 * point to a physically contiguous block of memory.
29826 uint64_t resp_addr;
29827 /* Host address where response diagnostic data is returned. */
29828 uint64_t resp_data_addr;
29830 * Size of the buffer pointed to by resp_data_addr. The firmware
29831 * may use this entire buffer or less than the entire buffer, but
29837 /* Port ID of port where dsc dump to be collected. */
29839 /* Diag level specified by the user */
29840 uint16_t diag_level;
29841 /* SRDS_DIAG_LANE */
29842 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
29844 /* SRDS_DIAG_CORE */
29845 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
29847 /* SRDS_DIAG_EVENT */
29848 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
29850 /* SRDS_DIAG_EYE */
29851 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
29853 /* SRDS_DIAG_REG_CORE */
29854 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
29856 /* SRDS_DIAG_REG_LANE */
29857 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
29859 /* SRDS_DIAG_UC_CORE */
29860 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
29862 /* SRDS_DIAG_UC_LANE */
29863 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
29865 /* SRDS_DIAG_LANE_DEBUG */
29866 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
29868 /* SRDS_DIAG_BER_VERT */
29869 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
29871 /* SRDS_DIAG_BER_HORZ */
29872 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
29874 /* SRDS_DIAG_EVENT_SAFE */
29875 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
29877 /* SRDS_DIAG_TIMESTAMP */
29878 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
29880 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
29881 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
29883 * This field is a lane number
29884 * on which to collect the dsc dump
29886 uint16_t lane_number;
29888 * Configuration bits.
29889 * Use enable bit to start dsc dump or retrieve dump
29891 uint16_t dsc_dump_config;
29893 * Set 0 to retrieve the dsc dump
29894 * Set 1 to start the dsc dump
29896 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
29900 /* hwrm_port_dsc_dump_output (size:128b/16B) */
29901 struct hwrm_port_dsc_dump_output {
29902 /* The specific error status for the command. */
29903 uint16_t error_code;
29904 /* The HWRM command request type. */
29906 /* The sequence ID from the original command. */
29908 /* The length of the response data in number of bytes. */
29910 /* Total length of stored data. */
29911 uint16_t total_data_len;
29913 uint8_t unused_1[3];
29915 * This field is used in Output records to indicate that the output
29916 * is completely written to RAM. This field should be read as '1'
29917 * to indicate that the output has been completely written.
29918 * When writing a command completion or response to an internal processor,
29919 * the order of writes has to be such that this field is written last.
29924 /******************************
29925 * hwrm_port_sfp_sideband_cfg *
29926 ******************************/
29929 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
29930 struct hwrm_port_sfp_sideband_cfg_input {
29931 /* The HWRM command request type. */
29934 * The completion ring to send the completion event on. This should
29935 * be the NQ ID returned from the `nq_alloc` HWRM command.
29937 uint16_t cmpl_ring;
29939 * The sequence ID is used by the driver for tracking multiple
29940 * commands. This ID is treated as opaque data by the firmware and
29941 * the value is returned in the `hwrm_resp_hdr` upon completion.
29945 * The target ID of the command:
29946 * * 0x0-0xFFF8 - The function ID
29947 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29948 * * 0xFFFD - Reserved for user-space HWRM interface
29951 uint16_t target_id;
29953 * A physical address pointer pointing to a host buffer that the
29954 * command's response data will be written. This can be either a host
29955 * physical address (HPA) or a guest physical address (GPA) and must
29956 * point to a physically contiguous block of memory.
29958 uint64_t resp_addr;
29959 /* Port ID of port that is to be queried. */
29961 uint8_t unused_0[6];
29963 * This bitfield is used to specify which bits from the 'flags'
29964 * fields are being configured by the caller.
29967 /* This bit must be '1' for rs0 to be configured. */
29968 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
29970 /* This bit must be '1' for rs1 to be configured. */
29971 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
29973 /* This bit must be '1' for tx_disable to be configured. */
29974 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
29977 * This bit must be '1' for mod_sel to be configured.
29978 * Valid only on QSFP modules
29980 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
29982 /* This bit must be '1' for reset_l to be configured. */
29983 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
29985 /* This bit must be '1' for lp_mode to be configured. */
29986 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
29988 /* This bit must be '1' for pwr_disable to be configured. */
29989 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
29992 * Only bits that have corresponding bits in the 'enables'
29993 * bitfield are processed by the firmware, all other bits
29994 * of 'flags' are ignored.
29998 * This bit along with rs1 configures the current speed of the dual
29999 * rate module. If these pins are GNDed then the speed can be changed
30000 * by directly writing to EEPROM.
30002 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
30005 * This bit along with rs0 configures the current speed of the dual
30006 * rate module. If these pins are GNDed then the speed can be changed
30007 * by directly writing to EEPROM.
30009 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
30012 * When this bit is set to '1', tx_disable is set.
30013 * On a 1G BASE-T module, if this bit is set,
30014 * module PHY registers will not be accessible.
30016 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
30019 * When this bit is set to '1', this module is selected.
30020 * Valid only on QSFP modules
30022 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
30025 * If reset_l is set to 0, Module will be taken out of reset
30026 * and other signals will be set to their requested state once
30027 * the module is out of reset.
30028 * Valid only on QSFP modules
30030 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
30033 * When this bit is set to '1', the module will be configured
30034 * in low power mode.
30035 * Valid only on QSFP modules
30037 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
30039 /* When this bit is set to '1', the module will be powered down. */
30040 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
30044 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
30045 struct hwrm_port_sfp_sideband_cfg_output {
30046 /* The specific error status for the command. */
30047 uint16_t error_code;
30048 /* The HWRM command request type. */
30050 /* The sequence ID from the original command. */
30052 /* The length of the response data in number of bytes. */
30056 * This field is used in Output records to indicate that the output
30057 * is completely written to RAM. This field should be read as '1'
30058 * to indicate that the output has been completely written. When
30059 * writing a command completion or response to an internal processor,
30060 * the order of writes has to be such that this field is written last.
30065 /*******************************
30066 * hwrm_port_sfp_sideband_qcfg *
30067 *******************************/
30070 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
30071 struct hwrm_port_sfp_sideband_qcfg_input {
30072 /* The HWRM command request type. */
30075 * The completion ring to send the completion event on. This should
30076 * be the NQ ID returned from the `nq_alloc` HWRM command.
30078 uint16_t cmpl_ring;
30080 * The sequence ID is used by the driver for tracking multiple
30081 * commands. This ID is treated as opaque data by the firmware and
30082 * the value is returned in the `hwrm_resp_hdr` upon completion.
30086 * The target ID of the command:
30087 * * 0x0-0xFFF8 - The function ID
30088 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30089 * * 0xFFFD - Reserved for user-space HWRM interface
30092 uint16_t target_id;
30094 * A physical address pointer pointing to a host buffer that the
30095 * command's response data will be written. This can be either a host
30096 * physical address (HPA) or a guest physical address (GPA) and must
30097 * point to a physically contiguous block of memory.
30099 uint64_t resp_addr;
30100 /* Port ID of port that is to be queried. */
30102 uint8_t unused_0[6];
30105 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
30106 struct hwrm_port_sfp_sideband_qcfg_output {
30107 /* The specific error status for the command. */
30108 uint16_t error_code;
30109 /* The HWRM command request type. */
30111 /* The sequence ID from the original command. */
30113 /* The length of the response data in number of bytes. */
30116 * Bitmask indicating which sideband signals are valid.
30117 * This is based on the board and nvm cfg that is present on the board.
30119 uint32_t supported_mask;
30120 uint32_t sideband_signals;
30121 /* When this bit is set to '1', the Module is absent. */
30122 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
30125 * When this bit is set to '1', there is no valid signal on RX.
30126 * This signal is a filtered version of Signal Detect.
30128 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
30131 * This bit along with rs1 indicates the current speed of the dual
30132 * rate module.If these pins are grounded then the speed can be
30133 * changed by directly writing to EEPROM.
30135 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
30138 * This bit along with rs0 indicates the current speed of the dual
30139 * rate module.If these pins are grounded then the speed can be
30140 * changed by directly writing to EEPROM.
30142 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
30145 * When this bit is set to '1', tx_disable is set.
30146 * On a 1G BASE-T module, if this bit is set, module PHY
30147 * registers will not be accessible.
30149 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
30151 /* When this bit is set to '1', tx_fault is set. */
30152 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
30155 * When this bit is set to '1', module is selected.
30156 * Valid only on QSFP modules
30158 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
30161 * When this bit is set to '0', the module is held in reset.
30162 * if reset_l is set to 1,first module is taken out of reset
30163 * and other signals will be set to their requested state.
30164 * Valid only on QSFP modules.
30166 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
30169 * When this bit is set to '1', the module is in low power mode.
30170 * Valid only on QSFP modules
30172 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
30174 /* When this bit is set to '1', module is in power down state. */
30175 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
30179 * This field is used in Output records to indicate that the output
30180 * is completely written to RAM. This field should be read as '1'
30181 * to indicate that the output has been completely written. When
30182 * writing a command completion or response to an internal processor,
30183 * the order of writes has to be such that this field is written last.
30188 /**********************************
30189 * hwrm_port_phy_mdio_bus_acquire *
30190 **********************************/
30193 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
30194 struct hwrm_port_phy_mdio_bus_acquire_input {
30195 /* The HWRM command request type. */
30198 * The completion ring to send the completion event on. This should
30199 * be the NQ ID returned from the `nq_alloc` HWRM command.
30201 uint16_t cmpl_ring;
30203 * The sequence ID is used by the driver for tracking multiple
30204 * commands. This ID is treated as opaque data by the firmware and
30205 * the value is returned in the `hwrm_resp_hdr` upon completion.
30209 * The target ID of the command:
30210 * * 0x0-0xFFF8 - The function ID
30211 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30212 * * 0xFFFD - Reserved for user-space HWRM interface
30215 uint16_t target_id;
30217 * A physical address pointer pointing to a host buffer that the
30218 * command's response data will be written. This can be either a host
30219 * physical address (HPA) or a guest physical address (GPA) and must
30220 * point to a physically contiguous block of memory.
30222 uint64_t resp_addr;
30223 /* Port ID of the port. */
30226 * client_id of the client requesting BUS access.
30227 * Any value from 0x10 to 0xFFFF can be used.
30228 * Client should make sure that the returned client_id
30229 * in response matches the client_id in request.
30230 * 0-0xF are reserved for internal use.
30232 uint16_t client_id;
30234 * Timeout in milli seconds, MDIO BUS will be released automatically
30235 * after this time, if another mdio acquire command is not received
30236 * within the timeout window from the same client.
30237 * A 0xFFFF will hold the bus until this bus is released.
30239 uint16_t mdio_bus_timeout;
30240 uint8_t unused_0[2];
30243 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
30244 struct hwrm_port_phy_mdio_bus_acquire_output {
30245 /* The specific error status for the command. */
30246 uint16_t error_code;
30247 /* The HWRM command request type. */
30249 /* The sequence ID from the original command. */
30251 /* The length of the response data in number of bytes. */
30255 * client_id of the module holding the BUS.
30256 * 0-0xF are reserved for internal use.
30258 uint16_t client_id;
30259 uint8_t unused_1[3];
30261 * This field is used in Output records to indicate that the output
30262 * is completely written to RAM. This field should be read as '1'
30263 * to indicate that the output has been completely written.
30264 * When writing a command completion or response to an internal processor,
30265 * the order of writes has to be such that this field is written last.
30270 /**********************************
30271 * hwrm_port_phy_mdio_bus_release *
30272 **********************************/
30275 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
30276 struct hwrm_port_phy_mdio_bus_release_input {
30277 /* The HWRM command request type. */
30280 * The completion ring to send the completion event on. This should
30281 * be the NQ ID returned from the `nq_alloc` HWRM command.
30283 uint16_t cmpl_ring;
30285 * The sequence ID is used by the driver for tracking multiple
30286 * commands. This ID is treated as opaque data by the firmware and
30287 * the value is returned in the `hwrm_resp_hdr` upon completion.
30291 * The target ID of the command:
30292 * * 0x0-0xFFF8 - The function ID
30293 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30294 * * 0xFFFD - Reserved for user-space HWRM interface
30297 uint16_t target_id;
30299 * A physical address pointer pointing to a host buffer that the
30300 * command's response data will be written. This can be either a host
30301 * physical address (HPA) or a guest physical address (GPA) and must
30302 * point to a physically contiguous block of memory.
30304 uint64_t resp_addr;
30305 /* Port ID of the port. */
30308 * client_id of the client requesting BUS release.
30309 * A client should not release any other clients BUS.
30311 uint16_t client_id;
30312 uint8_t unused_0[4];
30315 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
30316 struct hwrm_port_phy_mdio_bus_release_output {
30317 /* The specific error status for the command. */
30318 uint16_t error_code;
30319 /* The HWRM command request type. */
30321 /* The sequence ID from the original command. */
30323 /* The length of the response data in number of bytes. */
30326 /* The BUS is released if client_id matches the client_id in request. */
30327 uint16_t clients_id;
30328 uint8_t unused_1[3];
30330 * This field is used in Output records to indicate that the output
30331 * is completely written to RAM. This field should be read as '1'
30332 * to indicate that the output has been completely written.
30333 * When writing a command completion or response to an internal processor,
30334 * the order of writes has to be such that this field is written last.
30339 /************************
30340 * hwrm_port_tx_fir_cfg *
30341 ************************/
30344 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
30345 struct hwrm_port_tx_fir_cfg_input {
30346 /* The HWRM command request type. */
30349 * The completion ring to send the completion event on. This should
30350 * be the NQ ID returned from the `nq_alloc` HWRM command.
30352 uint16_t cmpl_ring;
30354 * The sequence ID is used by the driver for tracking multiple
30355 * commands. This ID is treated as opaque data by the firmware and
30356 * the value is returned in the `hwrm_resp_hdr` upon completion.
30360 * The target ID of the command:
30361 * * 0x0-0xFFF8 - The function ID
30362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30363 * * 0xFFFD - Reserved for user-space HWRM interface
30366 uint16_t target_id;
30368 * A physical address pointer pointing to a host buffer that the
30369 * command's response data will be written. This can be either a host
30370 * physical address (HPA) or a guest physical address (GPA) and must
30371 * point to a physically contiguous block of memory.
30373 uint64_t resp_addr;
30374 /* Modulation types of TX FIR: NRZ, PAM4. */
30377 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
30379 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
30380 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
30381 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
30382 /* The lane mask of the lane TX FIR will be configured. */
30384 uint8_t unused_0[2];
30385 /* Value1 of TX FIR, required for NRZ or PAM4. */
30386 uint32_t txfir_val_1;
30387 /* Value2 of TX FIR, required for NRZ or PAM4. */
30388 uint32_t txfir_val_2;
30389 /* Value3 of TX FIR, required for PAM4. */
30390 uint32_t txfir_val_3;
30391 /* Value4 of TX FIR, required for PAM4. */
30392 uint32_t txfir_val_4;
30393 uint8_t unused_1[4];
30396 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
30397 struct hwrm_port_tx_fir_cfg_output {
30398 /* The specific error status for the command. */
30399 uint16_t error_code;
30400 /* The HWRM command request type. */
30402 /* The sequence ID from the original command. */
30404 /* The length of the response data in number of bytes. */
30408 * This field is used in Output records to indicate that the output
30409 * is completely written to RAM. This field should be read as '1'
30410 * to indicate that the output has been completely written.
30411 * When writing a command completion or response to an internal processor,
30412 * the order of writes has to be such that this field is written last.
30417 /*************************
30418 * hwrm_port_tx_fir_qcfg *
30419 *************************/
30422 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
30423 struct hwrm_port_tx_fir_qcfg_input {
30424 /* The HWRM command request type. */
30427 * The completion ring to send the completion event on. This should
30428 * be the NQ ID returned from the `nq_alloc` HWRM command.
30430 uint16_t cmpl_ring;
30432 * The sequence ID is used by the driver for tracking multiple
30433 * commands. This ID is treated as opaque data by the firmware and
30434 * the value is returned in the `hwrm_resp_hdr` upon completion.
30438 * The target ID of the command:
30439 * * 0x0-0xFFF8 - The function ID
30440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30441 * * 0xFFFD - Reserved for user-space HWRM interface
30444 uint16_t target_id;
30446 * A physical address pointer pointing to a host buffer that the
30447 * command's response data will be written. This can be either a host
30448 * physical address (HPA) or a guest physical address (GPA) and must
30449 * point to a physically contiguous block of memory.
30451 uint64_t resp_addr;
30452 /* Modulation types of TX FIR: NRZ, PAM4. */
30455 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
30457 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
30458 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
30459 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
30460 /* The ID of the lane TX FIR will be queried. */
30465 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
30466 struct hwrm_port_tx_fir_qcfg_output {
30467 /* The specific error status for the command. */
30468 uint16_t error_code;
30469 /* The HWRM command request type. */
30471 /* The sequence ID from the original command. */
30473 /* The length of the response data in number of bytes. */
30475 /* Value1 of TX FIR, required for NRZ or PAM4. */
30476 uint32_t txfir_val_1;
30477 /* Value2 of TX FIR, required for NRZ or PAM4. */
30478 uint32_t txfir_val_2;
30479 /* Value3 of TX FIR, required for PAM4. */
30480 uint32_t txfir_val_3;
30481 /* Value4 of TX FIR, required for PAM4. */
30482 uint32_t txfir_val_4;
30485 * This field is used in Output records to indicate that the output
30486 * is completely written to RAM. This field should be read as '1'
30487 * to indicate that the output has been completely written.
30488 * When writing a command completion or response to an internal processor,
30489 * the order of writes has to be such that this field is written last.
30494 /***********************
30495 * hwrm_port_ep_tx_cfg *
30496 ***********************/
30499 /* hwrm_port_ep_tx_cfg_input (size:256b/32B) */
30500 struct hwrm_port_ep_tx_cfg_input {
30501 /* The HWRM command request type. */
30504 * The completion ring to send the completion event on. This should
30505 * be the NQ ID returned from the `nq_alloc` HWRM command.
30507 uint16_t cmpl_ring;
30509 * The sequence ID is used by the driver for tracking multiple
30510 * commands. This ID is treated as opaque data by the firmware and
30511 * the value is returned in the `hwrm_resp_hdr` upon completion.
30515 * The target ID of the command:
30516 * * 0x0-0xFFF8 - The function ID
30517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30518 * * 0xFFFD - Reserved for user-space HWRM interface
30521 uint16_t target_id;
30523 * A physical address pointer pointing to a host buffer that the
30524 * command's response data will be written. This can be either a host
30525 * physical address (HPA) or a guest physical address (GPA) and must
30526 * point to a physically contiguous block of memory.
30528 uint64_t resp_addr;
30530 /* When this bit is '1', the value in the ep0_min_bw field is valid. */
30531 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
30532 /* When this bit is '1', the value in the ep0_max_bw field is valid. */
30533 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
30534 /* When this bit is '1', the value in the ep1_min_bw field is valid. */
30535 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
30536 /* When this bit is '1', the value in the ep1_max_bw field is valid. */
30537 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
30538 /* When this bit is '1', the value in the ep2_min_bw field is valid. */
30539 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
30540 /* When this bit is '1', the value in the ep2_max_bw field is valid. */
30541 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
30542 /* When this bit is '1', the value in the ep3_min_bw field is valid. */
30543 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
30544 /* When this bit is '1', the value in the ep3_max_bw field is valid. */
30545 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
30546 /* A port index, from 0 to the number of front panel ports, minus 1. */
30550 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30551 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
30552 * the specified port. The range is 0 to 100. A value of 0 indicates no
30553 * minimum rate. The endpoint's min_bw must be less than or equal to
30554 * max_bw. The sum of all configured minimum bandwidths for a port must
30555 * be less than or equal to 100.
30557 uint8_t ep0_min_bw;
30559 * Specifies the maximum portion of the port's bandwidth that the set
30560 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
30561 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30564 uint8_t ep0_max_bw;
30566 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30567 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
30568 * the specified port. The range is 0 to 100. A value of 0 indicates no
30569 * minimum rate. The endpoint's min_bw must be less than or equal to
30570 * max_bw. The sum of all configured minimum bandwidths for a port must
30571 * be less than or equal to 100.
30573 uint8_t ep1_min_bw;
30575 * Specifies the maximum portion of the port's bandwidth that the set
30576 * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
30577 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30580 uint8_t ep1_max_bw;
30582 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30583 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
30584 * the specified port. The range is 0 to 100. A value of 0 indicates no
30585 * minimum rate. The endpoint's min_bw must be less than or equal to
30586 * max_bw. The sum of all configured minimum bandwidths for a port must
30587 * be less than or equal to 100.
30589 uint8_t ep2_min_bw;
30591 * Specifies the maximum portion of the port's bandwidth that the set of
30592 * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of
30593 * the link bandwidth, from 0 to 100. A value of 0 indicates no
30596 uint8_t ep2_max_bw;
30598 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30599 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
30600 * the specified port. The range is 0 to 100. A value of 0 indicates no
30601 * minimum rate. The endpoint's min_bw must be less than or equal to
30602 * max_bw. The sum of all configured minimum bandwidths for a port must
30603 * be less than or equal to 100.
30605 uint8_t ep3_min_bw;
30607 * Specifies the maximum portion of the port's bandwidth that the set
30608 * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
30609 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30612 uint8_t ep3_max_bw;
30613 uint8_t unused_1[4];
30616 /* hwrm_port_ep_tx_cfg_output (size:128b/16B) */
30617 struct hwrm_port_ep_tx_cfg_output {
30618 /* The specific error status for the command. */
30619 uint16_t error_code;
30620 /* The HWRM command request type. */
30622 /* The sequence ID from the original command. */
30624 /* The length of the response data in number of bytes. */
30626 uint8_t unused_0[7];
30628 * This field is used in output records to indicate that the output
30629 * is completely written to RAM. This field should be read as '1'
30630 * to indicate that the output has been completely written.
30631 * When writing a command completion or response to an internal
30632 * processor, the order of writes has to be such that this field
30638 /* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */
30639 struct hwrm_port_ep_tx_cfg_cmd_err {
30641 * command specific error codes for the cmd_err field in
30645 /* Unknown error. */
30646 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \
30648 /* The port ID is invalid */
30649 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \
30651 /* One of the PCIe endpoints configured is not active. */
30652 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \
30654 /* A minimum bandwidth is out of range. */
30655 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \
30658 * One endpoint's minimum bandwidth is more than its maximum
30661 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \
30663 /* The sum of the minimum bandwidths on the port is more than 100%. */
30664 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \
30667 * The NIC does not support enforcement of a minimum guaranteed
30668 * bandwidth for an endpoint.
30670 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \
30672 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \
30673 HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED
30674 uint8_t unused_0[7];
30677 /************************
30678 * hwrm_port_ep_tx_qcfg *
30679 ************************/
30682 /* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */
30683 struct hwrm_port_ep_tx_qcfg_input {
30684 /* The HWRM command request type. */
30687 * The completion ring to send the completion event on. This should
30688 * be the NQ ID returned from the `nq_alloc` HWRM command.
30690 uint16_t cmpl_ring;
30692 * The sequence ID is used by the driver for tracking multiple
30693 * commands. This ID is treated as opaque data by the firmware and
30694 * the value is returned in the `hwrm_resp_hdr` upon completion.
30698 * The target ID of the command:
30699 * * 0x0-0xFFF8 - The function ID
30700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30701 * * 0xFFFD - Reserved for user-space HWRM interface
30704 uint16_t target_id;
30706 * A physical address pointer pointing to a host buffer that the
30707 * command's response data will be written. This can be either a host
30708 * physical address (HPA) or a guest physical address (GPA) and must
30709 * point to a physically contiguous block of memory.
30711 uint64_t resp_addr;
30712 /* The port whose endpoint rate limits are queried. */
30717 /* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */
30718 struct hwrm_port_ep_tx_qcfg_output {
30719 /* The specific error status for the command. */
30720 uint16_t error_code;
30721 /* The HWRM command request type. */
30723 /* The sequence ID from the original command. */
30725 /* The length of the response data in number of bytes. */
30728 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30729 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
30730 * the specified port. The range is 0 to 100. A value of 0 indicates no
30731 * minimum rate. The endpoint's min_bw must be less than or equal to
30732 * max_bw. The sum of all configured minimum bandwidths for a port must
30733 * be less than or equal to 100.
30735 uint8_t ep0_min_bw;
30737 * Specifies the maximum portion of the port's bandwidth that the set
30738 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
30739 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30742 uint8_t ep0_max_bw;
30744 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30745 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
30746 * the specified port. The range is 0 to 100. A value of 0 indicates no
30747 * minimum rate. The endpoint's min_bw must be less than or equal to
30748 * max_bw. The sum of all configured minimum bandwidths for a port must
30749 * be less than or equal to 100.
30751 uint8_t ep1_min_bw;
30753 * Specifies the maximum portion of the port's bandwidth that the set
30754 * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
30755 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30758 uint8_t ep1_max_bw;
30760 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30761 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
30762 * the specified port. The range is 0 to 100. A value of 0 indicates no
30763 * minimum rate. The endpoint's min_bw must be less than or equal to
30764 * max_bw. The sum of all configured minimum bandwidths for a port must
30765 * be less than or equal to 100.
30767 uint8_t ep2_min_bw;
30769 * Specifies the maximum portion of the port's bandwidth that the set
30770 * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage
30771 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30774 uint8_t ep2_max_bw;
30776 * Specifies a minimum guaranteed bandwidth, as a percentage of the
30777 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
30778 * the specified port. The range is 0 to 100. A value of 0 indicates no
30779 * minimum rate. The endpoint's min_bw must be less than or equal to
30780 * max_bw. The sum of all configured minimum bandwidths for a port must
30781 * be less than or equal to 100.
30783 uint8_t ep3_min_bw;
30785 * Specifies the maximum portion of the port's bandwidth that the set
30786 * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
30787 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
30790 uint8_t ep3_max_bw;
30791 uint8_t unused_0[7];
30793 * This field is used in output records to indicate that the output
30794 * is completely written to RAM. This field should be read as '1'
30795 * to indicate that the output has been completely written.
30796 * When writing a command completion or response to an internal
30797 * processor, the order of writes has to be such that this field is
30803 /***********************
30804 * hwrm_queue_qportcfg *
30805 ***********************/
30808 /* hwrm_queue_qportcfg_input (size:192b/24B) */
30809 struct hwrm_queue_qportcfg_input {
30810 /* The HWRM command request type. */
30813 * The completion ring to send the completion event on. This should
30814 * be the NQ ID returned from the `nq_alloc` HWRM command.
30816 uint16_t cmpl_ring;
30818 * The sequence ID is used by the driver for tracking multiple
30819 * commands. This ID is treated as opaque data by the firmware and
30820 * the value is returned in the `hwrm_resp_hdr` upon completion.
30824 * The target ID of the command:
30825 * * 0x0-0xFFF8 - The function ID
30826 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30827 * * 0xFFFD - Reserved for user-space HWRM interface
30830 uint16_t target_id;
30832 * A physical address pointer pointing to a host buffer that the
30833 * command's response data will be written. This can be either a host
30834 * physical address (HPA) or a guest physical address (GPA) and must
30835 * point to a physically contiguous block of memory.
30837 uint64_t resp_addr;
30840 * Enumeration denoting the RX, TX type of the resource.
30841 * This enumeration is used for resources that are similar for both
30842 * TX and RX paths of the chip.
30844 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
30846 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30848 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30849 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
30850 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
30852 * Port ID of port for which the queue configuration is being
30853 * queried. This field is only required when sent by IPC.
30857 * Drivers will set this capability when it can use
30858 * queue_idx_service_profile to map the queues to application.
30860 uint8_t drv_qmap_cap;
30862 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
30864 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
30865 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
30866 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
30870 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
30871 struct hwrm_queue_qportcfg_output {
30872 /* The specific error status for the command. */
30873 uint16_t error_code;
30874 /* The HWRM command request type. */
30876 /* The sequence ID from the original command. */
30878 /* The length of the response data in number of bytes. */
30881 * The maximum number of queues that can be configured on this
30883 * Valid values range from 1 through 8.
30885 uint8_t max_configurable_queues;
30887 * The maximum number of lossless queues that can be configured
30889 * Valid values range from 0 through 8.
30891 uint8_t max_configurable_lossless_queues;
30893 * Bitmask indicating which queues can be configured by the
30894 * hwrm_queue_cfg command.
30896 * Each bit represents a specific queue where bit 0 represents
30897 * queue 0 and bit 7 represents queue 7.
30898 * # A value of 0 indicates that the queue is not configurable
30899 * by the hwrm_queue_cfg command.
30900 * # A value of 1 indicates that the queue is configurable.
30901 * # A hwrm_queue_cfg command shall return error when trying to
30902 * configure a queue not configurable.
30904 uint8_t queue_cfg_allowed;
30905 /* Information about queue configuration. */
30906 uint8_t queue_cfg_info;
30908 * If this flag is set to '1', then the queues are
30909 * configured asymmetrically on TX and RX sides.
30910 * If this flag is set to '0', then the queues are
30911 * configured symmetrically on TX and RX sides. For
30912 * symmetric configuration, the queue configuration
30913 * including queue ids and service profiles on the
30914 * TX side is the same as the corresponding queue
30915 * configuration on the RX side.
30917 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
30920 * If this flag is set to '1', then service_profile will carry
30921 * either lossy/lossless type and the new service_profile_type
30922 * field will be used to determine if the queue is for L2/ROCE/CNP.
30924 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \
30927 * Bitmask indicating which queues can be configured by the
30928 * hwrm_queue_pfcenable_cfg command.
30930 * Each bit represents a specific priority where bit 0 represents
30931 * priority 0 and bit 7 represents priority 7.
30932 * # A value of 0 indicates that the priority is not configurable by
30933 * the hwrm_queue_pfcenable_cfg command.
30934 * # A value of 1 indicates that the priority is configurable.
30935 * # A hwrm_queue_pfcenable_cfg command shall return error when
30936 * trying to configure a priority that is not configurable.
30938 uint8_t queue_pfcenable_cfg_allowed;
30940 * Bitmask indicating which queues can be configured by the
30941 * hwrm_queue_pri2cos_cfg command.
30943 * Each bit represents a specific queue where bit 0 represents
30944 * queue 0 and bit 7 represents queue 7.
30945 * # A value of 0 indicates that the queue is not configurable
30946 * by the hwrm_queue_pri2cos_cfg command.
30947 * # A value of 1 indicates that the queue is configurable.
30948 * # A hwrm_queue_pri2cos_cfg command shall return error when
30949 * trying to configure a queue that is not configurable.
30951 uint8_t queue_pri2cos_cfg_allowed;
30953 * Bitmask indicating which queues can be configured by the
30954 * hwrm_queue_pri2cos_cfg command.
30956 * Each bit represents a specific queue where bit 0 represents
30957 * queue 0 and bit 7 represents queue 7.
30958 * # A value of 0 indicates that the queue is not configurable
30959 * by the hwrm_queue_pri2cos_cfg command.
30960 * # A value of 1 indicates that the queue is configurable.
30961 * # A hwrm_queue_pri2cos_cfg command shall return error when
30962 * trying to configure a queue not configurable.
30964 uint8_t queue_cos2bw_cfg_allowed;
30966 * ID of CoS Queue 0.
30969 * # This ID can be used on any subsequent call to an hwrm command
30970 * that takes a queue id.
30971 * # IDs must always be queried by this command before any use
30972 * by the driver or software.
30973 * # The CoS queue index is obtained by applying modulo 10 to the
30974 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
30975 * The CoS queue index is used to reference port statistics for the
30977 * # A value of 0xff indicates that the queue is not available.
30978 * # Available queues may not be in sequential order.
30981 /* This value specifies service profile kind for CoS queue */
30982 uint8_t queue_id0_service_profile;
30983 /* Lossy (best-effort) */
30984 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
30987 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
30989 /* Lossless RoCE (deprecated) */
30990 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
30992 /* Lossy RoCE CNP (deprecated) */
30993 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
30995 /* Lossless NIC (deprecated) */
30996 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
30998 /* Set to 0xFF... (All Fs) if there is no service profile specified */
30999 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
31001 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
31002 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
31004 * ID of CoS Queue 1.
31007 * # This ID can be used on any subsequent call to an hwrm command
31008 * that takes a queue id.
31009 * # IDs must always be queried by this command before any use
31010 * by the driver or software.
31011 * # The CoS queue index is obtained by applying modulo 10 to the
31012 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31013 * The CoS queue index is used to reference port statistics for the
31015 * # A value of 0xff indicates that the queue is not available.
31016 * # Available queues may not be in sequential order.
31019 /* This value specifies service profile kind for CoS queue */
31020 uint8_t queue_id1_service_profile;
31021 /* Lossy (best-effort) */
31022 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
31025 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
31027 /* Lossless RoCE (deprecated) */
31028 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
31030 /* Lossy RoCE CNP (deprecated) */
31031 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31033 /* Lossless NIC (deprecated) */
31034 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
31036 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31037 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
31039 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
31040 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
31042 * ID of CoS Queue 2.
31045 * # This ID can be used on any subsequent call to an hwrm command
31046 * that takes a queue id.
31047 * # IDs must always be queried by this command before any use
31048 * by the driver or software.
31049 * # The CoS queue index is obtained by applying modulo 10 to the
31050 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31051 * The CoS queue index is used to reference port statistics for the
31053 * # A value of 0xff indicates that the queue is not available.
31054 * # Available queues may not be in sequential order.
31057 /* This value specifies service profile kind for CoS queue */
31058 uint8_t queue_id2_service_profile;
31059 /* Lossy (best-effort) */
31060 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
31063 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
31065 /* Lossless RoCE (deprecated) */
31066 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
31068 /* Lossy RoCE CNP (deprecated) */
31069 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31071 /* Lossless NIC (deprecated) */
31072 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
31074 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31075 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
31077 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
31078 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
31080 * ID of CoS Queue 3.
31083 * # This ID can be used on any subsequent call to an hwrm command
31084 * that takes a queue id.
31085 * # IDs must always be queried by this command before any use
31086 * by the driver or software.
31087 * # The CoS queue index is obtained by applying modulo 10 to the
31088 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31089 * The CoS queue index is used to reference port statistics for the
31091 * # A value of 0xff indicates that the queue is not available.
31092 * # Available queues may not be in sequential order.
31095 /* This value specifies service profile kind for CoS queue */
31096 uint8_t queue_id3_service_profile;
31097 /* Lossy (best-effort) */
31098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
31101 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
31103 /* Lossless RoCE (deprecated) */
31104 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
31106 /* Lossy RoCE CNP (deprecated) */
31107 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31109 /* Lossless NIC (deprecated) */
31110 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
31112 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31113 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
31115 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
31116 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
31118 * ID of CoS Queue 4.
31121 * # This ID can be used on any subsequent call to an hwrm command
31122 * that takes a queue id.
31123 * # IDs must always be queried by this command before any use
31124 * by the driver or software.
31125 * # The CoS queue index is obtained by applying modulo 10 to the
31126 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31127 * The CoS queue index is used to reference port statistics for the
31129 * # A value of 0xff indicates that the queue is not available.
31130 * # Available queues may not be in sequential order.
31133 /* This value specifies service profile kind for CoS queue */
31134 uint8_t queue_id4_service_profile;
31135 /* Lossy (best-effort) */
31136 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
31139 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
31141 /* Lossless RoCE (deprecated) */
31142 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
31144 /* Lossy RoCE CNP (deprecated) */
31145 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31147 /* Lossless NIC (deprecated) */
31148 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
31150 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31151 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
31153 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
31154 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
31156 * ID of CoS Queue 5.
31159 * # This ID can be used on any subsequent call to an hwrm command
31160 * that takes a queue id.
31161 * # IDs must always be queried by this command before any use
31162 * by the driver or software.
31163 * # The CoS queue index is obtained by applying modulo 10 to the
31164 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31165 * The CoS queue index is used to reference port statistics for the
31167 * # A value of 0xff indicates that the queue is not available.
31168 * # Available queues may not be in sequential order.
31171 /* This value specifies service profile kind for CoS queue */
31172 uint8_t queue_id5_service_profile;
31173 /* Lossy (best-effort) */
31174 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
31177 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
31179 /* Lossless RoCE (deprecated) */
31180 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
31182 /* Lossy RoCE CNP (deprecated) */
31183 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31185 /* Lossless NIC (deprecated) */
31186 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
31188 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31189 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
31191 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
31192 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
31194 * ID of CoS Queue 6.
31197 * # This ID can be used on any subsequent call to an hwrm command
31198 * that takes a queue id.
31199 * # IDs must always be queried by this command before any use
31200 * by the driver or software.
31201 * # The CoS queue index is obtained by applying modulo 10 to the
31202 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31203 * The CoS queue index is used to reference port statistics for the
31205 * # A value of 0xff indicates that the queue is not available.
31206 * # Available queues may not be in sequential order.
31209 /* This value specifies service profile kind for CoS queue */
31210 uint8_t queue_id6_service_profile;
31211 /* Lossy (best-effort) */
31212 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
31215 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
31217 /* Lossless RoCE (deprecated) */
31218 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
31220 /* Lossy RoCE CNP (deprecated) */
31221 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31223 /* Lossless NIC (deprecated) */
31224 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
31226 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31227 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
31229 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
31230 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
31232 * ID of CoS Queue 7.
31235 * # This ID can be used on any subsequent call to an hwrm command
31236 * that takes a queue id.
31237 * # IDs must always be queried by this command before any use
31238 * by the driver or software.
31239 * # The CoS queue index is obtained by applying modulo 10 to the
31240 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
31241 * The CoS queue index is used to reference port statistics for the
31243 * # A value of 0xff indicates that the queue is not available.
31244 * # Available queues may not be in sequential order.
31247 /* This value specifies service profile kind for CoS queue */
31248 uint8_t queue_id7_service_profile;
31249 /* Lossy (best-effort) */
31250 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
31253 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
31255 /* Lossless RoCE (deprecated) */
31256 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
31258 /* Lossy RoCE CNP (deprecated) */
31259 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
31261 /* Lossless NIC (deprecated) */
31262 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
31264 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31265 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
31267 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
31268 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
31270 * This value specifies traffic type for the service profile. We can
31271 * have a TC mapped to multiple traffic types. For example shared
31272 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31273 * A value of zero is considered as invalid.
31275 uint8_t queue_id0_service_profile_type;
31276 /* Recommended to be used for RoCE traffic only. */
31277 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
31279 /* Recommended to be used for NIC/L2 traffic only. */
31280 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
31282 /* Recommended to be used for CNP traffic only. */
31283 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
31286 * Up to 16 bytes of null padded ASCII string describing this queue.
31287 * The queue name includes a CoS queue index and, in some cases, text
31288 * that distinguishes the queue from other queues in the group.
31290 char qid0_name[16];
31291 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31292 char qid1_name[16];
31293 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31294 char qid2_name[16];
31295 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31296 char qid3_name[16];
31297 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31298 char qid4_name[16];
31299 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31300 char qid5_name[16];
31301 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31302 char qid6_name[16];
31303 /* Up to 16 bytes of null padded ASCII string describing this queue. */
31304 char qid7_name[16];
31306 * This value specifies traffic type for the service profile. We can
31307 * have a TC mapped to multiple traffic types. For example shared
31308 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31309 * A value of zero is considered as invalid.
31311 uint8_t queue_id1_service_profile_type;
31312 /* Recommended to be used for RoCE traffic only. */
31313 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
31315 /* Recommended to be used for NIC/L2 traffic only. */
31316 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
31318 /* Recommended to be used for CNP traffic only. */
31319 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
31322 * This value specifies traffic type for the service profile. We can
31323 * have a TC mapped to multiple traffic types. For example shared
31324 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31325 * A value of zero is considered as invalid.
31327 uint8_t queue_id2_service_profile_type;
31328 /* Recommended to be used for RoCE traffic only. */
31329 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
31331 /* Recommended to be used for NIC/L2 traffic only. */
31332 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
31334 /* Recommended to be used for CNP traffic only. */
31335 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
31338 * This value specifies traffic type for the service profile. We can
31339 * have a TC mapped to multiple traffic types. For example shared
31340 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31341 * A value of zero is considered as invalid.
31343 uint8_t queue_id3_service_profile_type;
31344 /* Recommended to be used for RoCE traffic only. */
31345 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
31347 /* Recommended to be used for NIC/L2 traffic only. */
31348 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
31350 /* Recommended to be used for CNP traffic only. */
31351 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
31354 * This value specifies traffic type for the service profile. We can
31355 * have a TC mapped to multiple traffic types. For example shared
31356 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31357 * A value of zero is considered as invalid.
31359 uint8_t queue_id4_service_profile_type;
31360 /* Recommended to be used for RoCE traffic only. */
31361 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
31363 /* Recommended to be used for NIC/L2 traffic only. */
31364 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
31366 /* Recommended to be used for CNP traffic only. */
31367 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
31370 * This value specifies traffic type for the service profile. We can
31371 * have a TC mapped to multiple traffic types. For example shared
31372 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31373 * A value of zero is considered as invalid.
31375 uint8_t queue_id5_service_profile_type;
31376 /* Recommended to be used for RoCE traffic only. */
31377 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
31379 /* Recommended to be used for NIC/L2 traffic only. */
31380 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
31382 /* Recommended to be used for CNP traffic only. */
31383 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
31386 * This value specifies traffic type for the service profile. We can
31387 * have a TC mapped to multiple traffic types. For example shared
31388 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31389 * A value of zero is considered as invalid.
31391 uint8_t queue_id6_service_profile_type;
31392 /* Recommended to be used for RoCE traffic only. */
31393 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
31395 /* Recommended to be used for NIC/L2 traffic only. */
31396 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
31398 /* Recommended to be used for CNP traffic only. */
31399 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
31402 * This value specifies traffic type for the service profile. We can
31403 * have a TC mapped to multiple traffic types. For example shared
31404 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
31405 * A value of zero is considered as invalid.
31407 uint8_t queue_id7_service_profile_type;
31408 /* Recommended to be used for RoCE traffic only. */
31409 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
31411 /* Recommended to be used for NIC/L2 traffic only. */
31412 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
31414 /* Recommended to be used for CNP traffic only. */
31415 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
31418 * This field is used in Output records to indicate that the output
31419 * is completely written to RAM. This field should be read as '1'
31420 * to indicate that the output has been completely written.
31421 * When writing a command completion or response to an internal processor,
31422 * the order of writes has to be such that this field is written last.
31427 /*******************
31428 * hwrm_queue_qcfg *
31429 *******************/
31432 /* hwrm_queue_qcfg_input (size:192b/24B) */
31433 struct hwrm_queue_qcfg_input {
31434 /* The HWRM command request type. */
31437 * The completion ring to send the completion event on. This should
31438 * be the NQ ID returned from the `nq_alloc` HWRM command.
31440 uint16_t cmpl_ring;
31442 * The sequence ID is used by the driver for tracking multiple
31443 * commands. This ID is treated as opaque data by the firmware and
31444 * the value is returned in the `hwrm_resp_hdr` upon completion.
31448 * The target ID of the command:
31449 * * 0x0-0xFFF8 - The function ID
31450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31451 * * 0xFFFD - Reserved for user-space HWRM interface
31454 uint16_t target_id;
31456 * A physical address pointer pointing to a host buffer that the
31457 * command's response data will be written. This can be either a host
31458 * physical address (HPA) or a guest physical address (GPA) and must
31459 * point to a physically contiguous block of memory.
31461 uint64_t resp_addr;
31464 * Enumeration denoting the RX, TX type of the resource.
31465 * This enumeration is used for resources that are similar for both
31466 * TX and RX paths of the chip.
31468 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31470 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31472 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31473 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
31474 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
31475 /* Queue ID of the queue. */
31479 /* hwrm_queue_qcfg_output (size:128b/16B) */
31480 struct hwrm_queue_qcfg_output {
31481 /* The specific error status for the command. */
31482 uint16_t error_code;
31483 /* The HWRM command request type. */
31485 /* The sequence ID from the original command. */
31487 /* The length of the response data in number of bytes. */
31490 * This value is the estimate packet length used in the
31493 uint32_t queue_len;
31494 /* This value is applicable to CoS queues only. */
31495 uint8_t service_profile;
31496 /* Lossy (best-effort) */
31497 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
31499 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
31500 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31501 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
31502 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
31503 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
31504 /* Information about queue configuration. */
31505 uint8_t queue_cfg_info;
31507 * If this flag is set to '1', then the queue is
31508 * configured asymmetrically on TX and RX sides.
31509 * If this flag is set to '0', then this queue is
31510 * configured symmetrically on TX and RX sides.
31512 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
31516 * This field is used in Output records to indicate that the output
31517 * is completely written to RAM. This field should be read as '1'
31518 * to indicate that the output has been completely written.
31519 * When writing a command completion or response to an internal processor,
31520 * the order of writes has to be such that this field is written last.
31525 /******************
31527 ******************/
31530 /* hwrm_queue_cfg_input (size:320b/40B) */
31531 struct hwrm_queue_cfg_input {
31532 /* The HWRM command request type. */
31535 * The completion ring to send the completion event on. This should
31536 * be the NQ ID returned from the `nq_alloc` HWRM command.
31538 uint16_t cmpl_ring;
31540 * The sequence ID is used by the driver for tracking multiple
31541 * commands. This ID is treated as opaque data by the firmware and
31542 * the value is returned in the `hwrm_resp_hdr` upon completion.
31546 * The target ID of the command:
31547 * * 0x0-0xFFF8 - The function ID
31548 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31549 * * 0xFFFD - Reserved for user-space HWRM interface
31552 uint16_t target_id;
31554 * A physical address pointer pointing to a host buffer that the
31555 * command's response data will be written. This can be either a host
31556 * physical address (HPA) or a guest physical address (GPA) and must
31557 * point to a physically contiguous block of memory.
31559 uint64_t resp_addr;
31562 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
31563 * This enumeration is used for resources that are similar for both
31564 * TX and RX paths of the chip.
31566 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
31567 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
31569 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31571 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31572 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
31573 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
31574 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
31575 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
31578 * This bit must be '1' for the dflt_len field to be
31581 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
31583 * This bit must be '1' for the service_profile field to be
31586 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
31587 /* Queue ID of queue that is to be configured by this function. */
31590 * This value is a the estimate packet length used in the
31592 * Set to 0xFF... (All Fs) to not adjust this value.
31595 /* This value is applicable to CoS queues only. */
31596 uint8_t service_profile;
31597 /* Lossy (best-effort) */
31598 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
31600 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
31601 /* Set to 0xFF... (All Fs) if there is no service profile specified */
31602 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
31603 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
31604 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
31605 uint8_t unused_0[7];
31608 /* hwrm_queue_cfg_output (size:128b/16B) */
31609 struct hwrm_queue_cfg_output {
31610 /* The specific error status for the command. */
31611 uint16_t error_code;
31612 /* The HWRM command request type. */
31614 /* The sequence ID from the original command. */
31616 /* The length of the response data in number of bytes. */
31618 uint8_t unused_0[7];
31620 * This field is used in Output records to indicate that the output
31621 * is completely written to RAM. This field should be read as '1'
31622 * to indicate that the output has been completely written.
31623 * When writing a command completion or response to an internal processor,
31624 * the order of writes has to be such that this field is written last.
31629 /*****************************
31630 * hwrm_queue_pfcenable_qcfg *
31631 *****************************/
31634 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
31635 struct hwrm_queue_pfcenable_qcfg_input {
31636 /* The HWRM command request type. */
31639 * The completion ring to send the completion event on. This should
31640 * be the NQ ID returned from the `nq_alloc` HWRM command.
31642 uint16_t cmpl_ring;
31644 * The sequence ID is used by the driver for tracking multiple
31645 * commands. This ID is treated as opaque data by the firmware and
31646 * the value is returned in the `hwrm_resp_hdr` upon completion.
31650 * The target ID of the command:
31651 * * 0x0-0xFFF8 - The function ID
31652 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31653 * * 0xFFFD - Reserved for user-space HWRM interface
31656 uint16_t target_id;
31658 * A physical address pointer pointing to a host buffer that the
31659 * command's response data will be written. This can be either a host
31660 * physical address (HPA) or a guest physical address (GPA) and must
31661 * point to a physically contiguous block of memory.
31663 uint64_t resp_addr;
31665 * Port ID of port for which the table is being configured.
31666 * The HWRM needs to check whether this function is allowed
31667 * to configure pri2cos mapping on this port.
31670 uint8_t unused_0[6];
31673 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
31674 struct hwrm_queue_pfcenable_qcfg_output {
31675 /* The specific error status for the command. */
31676 uint16_t error_code;
31677 /* The HWRM command request type. */
31679 /* The sequence ID from the original command. */
31681 /* The length of the response data in number of bytes. */
31684 /* If set to 1, then PFC is enabled on PRI 0. */
31685 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
31687 /* If set to 1, then PFC is enabled on PRI 1. */
31688 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
31690 /* If set to 1, then PFC is enabled on PRI 2. */
31691 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
31693 /* If set to 1, then PFC is enabled on PRI 3. */
31694 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
31696 /* If set to 1, then PFC is enabled on PRI 4. */
31697 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
31699 /* If set to 1, then PFC is enabled on PRI 5. */
31700 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
31702 /* If set to 1, then PFC is enabled on PRI 6. */
31703 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
31705 /* If set to 1, then PFC is enabled on PRI 7. */
31706 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
31708 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
31709 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
31711 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
31712 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
31714 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
31715 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
31717 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
31718 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
31720 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
31721 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
31723 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
31724 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
31726 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
31727 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
31729 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
31730 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
31732 uint8_t unused_0[3];
31734 * This field is used in Output records to indicate that the output
31735 * is completely written to RAM. This field should be read as '1'
31736 * to indicate that the output has been completely written.
31737 * When writing a command completion or response to an internal processor,
31738 * the order of writes has to be such that this field is written last.
31743 /****************************
31744 * hwrm_queue_pfcenable_cfg *
31745 ****************************/
31748 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
31749 struct hwrm_queue_pfcenable_cfg_input {
31750 /* The HWRM command request type. */
31753 * The completion ring to send the completion event on. This should
31754 * be the NQ ID returned from the `nq_alloc` HWRM command.
31756 uint16_t cmpl_ring;
31758 * The sequence ID is used by the driver for tracking multiple
31759 * commands. This ID is treated as opaque data by the firmware and
31760 * the value is returned in the `hwrm_resp_hdr` upon completion.
31764 * The target ID of the command:
31765 * * 0x0-0xFFF8 - The function ID
31766 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31767 * * 0xFFFD - Reserved for user-space HWRM interface
31770 uint16_t target_id;
31772 * A physical address pointer pointing to a host buffer that the
31773 * command's response data will be written. This can be either a host
31774 * physical address (HPA) or a guest physical address (GPA) and must
31775 * point to a physically contiguous block of memory.
31777 uint64_t resp_addr;
31779 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
31780 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
31782 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
31783 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
31785 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
31786 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
31788 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
31789 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
31791 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
31792 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
31794 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
31795 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
31797 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
31798 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
31800 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
31801 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
31803 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
31804 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
31806 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
31807 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
31809 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
31810 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
31812 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
31813 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
31815 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
31816 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
31818 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
31819 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
31821 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
31822 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
31824 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
31825 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
31828 * Port ID of port for which the table is being configured.
31829 * The HWRM needs to check whether this function is allowed
31830 * to configure pri2cos mapping on this port.
31833 uint8_t unused_0[2];
31836 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
31837 struct hwrm_queue_pfcenable_cfg_output {
31838 /* The specific error status for the command. */
31839 uint16_t error_code;
31840 /* The HWRM command request type. */
31842 /* The sequence ID from the original command. */
31844 /* The length of the response data in number of bytes. */
31846 uint8_t unused_0[7];
31848 * This field is used in Output records to indicate that the output
31849 * is completely written to RAM. This field should be read as '1'
31850 * to indicate that the output has been completely written.
31851 * When writing a command completion or response to an internal processor,
31852 * the order of writes has to be such that this field is written last.
31857 /***************************
31858 * hwrm_queue_pri2cos_qcfg *
31859 ***************************/
31862 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
31863 struct hwrm_queue_pri2cos_qcfg_input {
31864 /* The HWRM command request type. */
31867 * The completion ring to send the completion event on. This should
31868 * be the NQ ID returned from the `nq_alloc` HWRM command.
31870 uint16_t cmpl_ring;
31872 * The sequence ID is used by the driver for tracking multiple
31873 * commands. This ID is treated as opaque data by the firmware and
31874 * the value is returned in the `hwrm_resp_hdr` upon completion.
31878 * The target ID of the command:
31879 * * 0x0-0xFFF8 - The function ID
31880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31881 * * 0xFFFD - Reserved for user-space HWRM interface
31884 uint16_t target_id;
31886 * A physical address pointer pointing to a host buffer that the
31887 * command's response data will be written. This can be either a host
31888 * physical address (HPA) or a guest physical address (GPA) and must
31889 * point to a physically contiguous block of memory.
31891 uint64_t resp_addr;
31894 * Enumeration denoting the RX, TX type of the resource.
31895 * This enumeration is used for resources that are similar for both
31896 * TX and RX paths of the chip.
31898 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31900 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31902 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31903 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
31904 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
31906 * When this bit is set to '0', the query is
31907 * for PRI from tunnel headers.
31908 * When this bit is set to '1', the query is
31909 * for PRI from inner packet headers.
31911 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
31913 * Port ID of port for which the table is being configured.
31914 * The HWRM needs to check whether this function is allowed
31915 * to configure pri2cos mapping on this port.
31918 uint8_t unused_0[3];
31921 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
31922 struct hwrm_queue_pri2cos_qcfg_output {
31923 /* The specific error status for the command. */
31924 uint16_t error_code;
31925 /* The HWRM command request type. */
31927 /* The sequence ID from the original command. */
31929 /* The length of the response data in number of bytes. */
31932 * CoS Queue assigned to priority 0. This value can only
31933 * be changed before traffic has started.
31934 * A value of 0xff indicates that no CoS queue is assigned to the
31935 * specified priority.
31937 uint8_t pri0_cos_queue_id;
31939 * CoS Queue assigned to priority 1. This value can only
31940 * be changed before traffic has started.
31941 * A value of 0xff indicates that no CoS queue is assigned to the
31942 * specified priority.
31944 uint8_t pri1_cos_queue_id;
31946 * CoS Queue assigned to priority 2. This value can only
31947 * be changed before traffic has started.
31948 * A value of 0xff indicates that no CoS queue is assigned to the
31949 * specified priority.
31951 uint8_t pri2_cos_queue_id;
31953 * CoS Queue assigned to priority 3. This value can only
31954 * be changed before traffic has started.
31955 * A value of 0xff indicates that no CoS queue is assigned to the
31956 * specified priority.
31958 uint8_t pri3_cos_queue_id;
31960 * CoS Queue assigned to priority 4. This value can only
31961 * be changed before traffic has started.
31962 * A value of 0xff indicates that no CoS queue is assigned to the
31963 * specified priority.
31965 uint8_t pri4_cos_queue_id;
31967 * CoS Queue assigned to priority 5. This value can only
31968 * be changed before traffic has started.
31969 * A value of 0xff indicates that no CoS queue is assigned to the
31970 * specified priority.
31972 uint8_t pri5_cos_queue_id;
31974 * CoS Queue assigned to priority 6. This value can only
31975 * be changed before traffic has started.
31976 * A value of 0xff indicates that no CoS queue is assigned to the
31977 * specified priority.
31979 uint8_t pri6_cos_queue_id;
31981 * CoS Queue assigned to priority 7. This value can only
31982 * be changed before traffic has started.
31983 * A value of 0xff indicates that no CoS queue is assigned to the
31984 * specified priority.
31986 uint8_t pri7_cos_queue_id;
31987 /* Information about queue configuration. */
31988 uint8_t queue_cfg_info;
31990 * If this flag is set to '1', then the PRI to CoS
31991 * configuration is asymmetric on TX and RX sides.
31992 * If this flag is set to '0', then PRI to CoS configuration
31993 * is symmetric on TX and RX sides.
31995 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
31997 uint8_t unused_0[6];
31999 * This field is used in Output records to indicate that the output
32000 * is completely written to RAM. This field should be read as '1'
32001 * to indicate that the output has been completely written.
32002 * When writing a command completion or response to an internal processor,
32003 * the order of writes has to be such that this field is written last.
32008 /**************************
32009 * hwrm_queue_pri2cos_cfg *
32010 **************************/
32013 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
32014 struct hwrm_queue_pri2cos_cfg_input {
32015 /* The HWRM command request type. */
32018 * The completion ring to send the completion event on. This should
32019 * be the NQ ID returned from the `nq_alloc` HWRM command.
32021 uint16_t cmpl_ring;
32023 * The sequence ID is used by the driver for tracking multiple
32024 * commands. This ID is treated as opaque data by the firmware and
32025 * the value is returned in the `hwrm_resp_hdr` upon completion.
32029 * The target ID of the command:
32030 * * 0x0-0xFFF8 - The function ID
32031 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32032 * * 0xFFFD - Reserved for user-space HWRM interface
32035 uint16_t target_id;
32037 * A physical address pointer pointing to a host buffer that the
32038 * command's response data will be written. This can be either a host
32039 * physical address (HPA) or a guest physical address (GPA) and must
32040 * point to a physically contiguous block of memory.
32042 uint64_t resp_addr;
32045 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
32046 * This enumeration is used for resources that are similar for both
32047 * TX and RX paths of the chip.
32049 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
32050 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
32052 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
32054 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
32055 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
32056 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
32057 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
32058 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
32060 * When this bit is set to '0', the mapping is requested
32061 * for PRI from tunnel headers.
32062 * When this bit is set to '1', the mapping is requested
32063 * for PRI from inner packet headers.
32065 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
32068 * This bit must be '1' for the pri0_cos_queue_id field to be
32071 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
32074 * This bit must be '1' for the pri1_cos_queue_id field to be
32077 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
32080 * This bit must be '1' for the pri2_cos_queue_id field to be
32083 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
32086 * This bit must be '1' for the pri3_cos_queue_id field to be
32089 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
32092 * This bit must be '1' for the pri4_cos_queue_id field to be
32095 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
32098 * This bit must be '1' for the pri5_cos_queue_id field to be
32101 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
32104 * This bit must be '1' for the pri6_cos_queue_id field to be
32107 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
32110 * This bit must be '1' for the pri7_cos_queue_id field to be
32113 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
32116 * Port ID of port for which the table is being configured.
32117 * The HWRM needs to check whether this function is allowed
32118 * to configure pri2cos mapping on this port.
32122 * CoS Queue assigned to priority 0. This value can only
32123 * be changed before traffic has started.
32125 uint8_t pri0_cos_queue_id;
32127 * CoS Queue assigned to priority 1. This value can only
32128 * be changed before traffic has started.
32130 uint8_t pri1_cos_queue_id;
32132 * CoS Queue assigned to priority 2 This value can only
32133 * be changed before traffic has started.
32135 uint8_t pri2_cos_queue_id;
32137 * CoS Queue assigned to priority 3. This value can only
32138 * be changed before traffic has started.
32140 uint8_t pri3_cos_queue_id;
32142 * CoS Queue assigned to priority 4. This value can only
32143 * be changed before traffic has started.
32145 uint8_t pri4_cos_queue_id;
32147 * CoS Queue assigned to priority 5. This value can only
32148 * be changed before traffic has started.
32150 uint8_t pri5_cos_queue_id;
32152 * CoS Queue assigned to priority 6. This value can only
32153 * be changed before traffic has started.
32155 uint8_t pri6_cos_queue_id;
32157 * CoS Queue assigned to priority 7. This value can only
32158 * be changed before traffic has started.
32160 uint8_t pri7_cos_queue_id;
32161 uint8_t unused_0[7];
32164 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
32165 struct hwrm_queue_pri2cos_cfg_output {
32166 /* The specific error status for the command. */
32167 uint16_t error_code;
32168 /* The HWRM command request type. */
32170 /* The sequence ID from the original command. */
32172 /* The length of the response data in number of bytes. */
32174 uint8_t unused_0[7];
32176 * This field is used in Output records to indicate that the output
32177 * is completely written to RAM. This field should be read as '1'
32178 * to indicate that the output has been completely written.
32179 * When writing a command completion or response to an internal processor,
32180 * the order of writes has to be such that this field is written last.
32185 /**************************
32186 * hwrm_queue_cos2bw_qcfg *
32187 **************************/
32190 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
32191 struct hwrm_queue_cos2bw_qcfg_input {
32192 /* The HWRM command request type. */
32195 * The completion ring to send the completion event on. This should
32196 * be the NQ ID returned from the `nq_alloc` HWRM command.
32198 uint16_t cmpl_ring;
32200 * The sequence ID is used by the driver for tracking multiple
32201 * commands. This ID is treated as opaque data by the firmware and
32202 * the value is returned in the `hwrm_resp_hdr` upon completion.
32206 * The target ID of the command:
32207 * * 0x0-0xFFF8 - The function ID
32208 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32209 * * 0xFFFD - Reserved for user-space HWRM interface
32212 uint16_t target_id;
32214 * A physical address pointer pointing to a host buffer that the
32215 * command's response data will be written. This can be either a host
32216 * physical address (HPA) or a guest physical address (GPA) and must
32217 * point to a physically contiguous block of memory.
32219 uint64_t resp_addr;
32221 * Port ID of port for which the table is being configured.
32222 * The HWRM needs to check whether this function is allowed
32223 * to configure TC BW assignment on this port.
32226 uint8_t unused_0[6];
32229 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
32230 struct hwrm_queue_cos2bw_qcfg_output {
32231 /* The specific error status for the command. */
32232 uint16_t error_code;
32233 /* The HWRM command request type. */
32235 /* The sequence ID from the original command. */
32237 /* The length of the response data in number of bytes. */
32239 /* ID of CoS Queue 0. */
32244 * Minimum BW allocated to CoS Queue.
32245 * The HWRM will translate this value into byte counter and
32246 * time interval used for this COS inside the device.
32248 uint32_t queue_id0_min_bw;
32249 /* The bandwidth value. */
32250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
32251 UINT32_C(0xfffffff)
32252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
32254 /* The granularity of the value (bits or bytes). */
32255 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
32256 UINT32_C(0x10000000)
32257 /* Value is in bits. */
32258 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
32259 (UINT32_C(0x0) << 28)
32260 /* Value is in bytes. */
32261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
32262 (UINT32_C(0x1) << 28)
32263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
32264 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
32265 /* bw_value_unit is 3 b */
32266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
32267 UINT32_C(0xe0000000)
32268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
32270 /* Value is in Mb or MB (base 10). */
32271 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
32272 (UINT32_C(0x0) << 29)
32273 /* Value is in Kb or KB (base 10). */
32274 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
32275 (UINT32_C(0x2) << 29)
32276 /* Value is in bits or bytes. */
32277 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
32278 (UINT32_C(0x4) << 29)
32279 /* Value is in Gb or GB (base 10). */
32280 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
32281 (UINT32_C(0x6) << 29)
32282 /* Value is in 1/100th of a percentage of total bandwidth. */
32283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32284 (UINT32_C(0x1) << 29)
32286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
32287 (UINT32_C(0x7) << 29)
32288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
32289 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
32291 * Maximum BW allocated to CoS Queue.
32292 * The HWRM will translate this value into byte counter and
32293 * time interval used for this COS inside the device.
32295 uint32_t queue_id0_max_bw;
32296 /* The bandwidth value. */
32297 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
32298 UINT32_C(0xfffffff)
32299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
32301 /* The granularity of the value (bits or bytes). */
32302 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
32303 UINT32_C(0x10000000)
32304 /* Value is in bits. */
32305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
32306 (UINT32_C(0x0) << 28)
32307 /* Value is in bytes. */
32308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
32309 (UINT32_C(0x1) << 28)
32310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
32311 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
32312 /* bw_value_unit is 3 b */
32313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
32314 UINT32_C(0xe0000000)
32315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
32317 /* Value is in Mb or MB (base 10). */
32318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
32319 (UINT32_C(0x0) << 29)
32320 /* Value is in Kb or KB (base 10). */
32321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
32322 (UINT32_C(0x2) << 29)
32323 /* Value is in bits or bytes. */
32324 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
32325 (UINT32_C(0x4) << 29)
32326 /* Value is in Gb or GB (base 10). */
32327 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
32328 (UINT32_C(0x6) << 29)
32329 /* Value is in 1/100th of a percentage of total bandwidth. */
32330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32331 (UINT32_C(0x1) << 29)
32333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
32334 (UINT32_C(0x7) << 29)
32335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
32336 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
32337 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32338 uint8_t queue_id0_tsa_assign;
32339 /* Strict Priority */
32340 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
32342 /* Enhanced Transmission Selection */
32343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
32346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
32349 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
32352 * Priority level for strict priority. Valid only when the
32353 * tsa_assign is 0 - Strict Priority (SP)
32354 * 0..7 - Valid values.
32355 * 8..255 - Reserved.
32357 uint8_t queue_id0_pri_lvl;
32359 * Weight used to allocate remaining BW for this COS after
32360 * servicing guaranteed bandwidths for all COS.
32362 uint8_t queue_id0_bw_weight;
32363 /* ID of CoS Queue 1. */
32366 * Minimum BW allocated to CoS Queue.
32367 * The HWRM will translate this value into byte counter and
32368 * time interval used for this COS inside the device.
32370 uint32_t queue_id1_min_bw;
32371 /* The bandwidth value. */
32372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
32373 UINT32_C(0xfffffff)
32374 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
32376 /* The granularity of the value (bits or bytes). */
32377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
32378 UINT32_C(0x10000000)
32379 /* Value is in bits. */
32380 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
32381 (UINT32_C(0x0) << 28)
32382 /* Value is in bytes. */
32383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
32384 (UINT32_C(0x1) << 28)
32385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
32386 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
32387 /* bw_value_unit is 3 b */
32388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
32389 UINT32_C(0xe0000000)
32390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
32392 /* Value is in Mb or MB (base 10). */
32393 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
32394 (UINT32_C(0x0) << 29)
32395 /* Value is in Kb or KB (base 10). */
32396 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
32397 (UINT32_C(0x2) << 29)
32398 /* Value is in bits or bytes. */
32399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
32400 (UINT32_C(0x4) << 29)
32401 /* Value is in Gb or GB (base 10). */
32402 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
32403 (UINT32_C(0x6) << 29)
32404 /* Value is in 1/100th of a percentage of total bandwidth. */
32405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32406 (UINT32_C(0x1) << 29)
32408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
32409 (UINT32_C(0x7) << 29)
32410 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
32411 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
32413 * Maximum BW allocated to CoS queue.
32414 * The HWRM will translate this value into byte counter and
32415 * time interval used for this COS inside the device.
32417 uint32_t queue_id1_max_bw;
32418 /* The bandwidth value. */
32419 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
32420 UINT32_C(0xfffffff)
32421 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
32423 /* The granularity of the value (bits or bytes). */
32424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
32425 UINT32_C(0x10000000)
32426 /* Value is in bits. */
32427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
32428 (UINT32_C(0x0) << 28)
32429 /* Value is in bytes. */
32430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
32431 (UINT32_C(0x1) << 28)
32432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
32433 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
32434 /* bw_value_unit is 3 b */
32435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
32436 UINT32_C(0xe0000000)
32437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
32439 /* Value is in Mb or MB (base 10). */
32440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
32441 (UINT32_C(0x0) << 29)
32442 /* Value is in Kb or KB (base 10). */
32443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
32444 (UINT32_C(0x2) << 29)
32445 /* Value is in bits or bytes. */
32446 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
32447 (UINT32_C(0x4) << 29)
32448 /* Value is in Gb or GB (base 10). */
32449 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
32450 (UINT32_C(0x6) << 29)
32451 /* Value is in 1/100th of a percentage of total bandwidth. */
32452 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32453 (UINT32_C(0x1) << 29)
32455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
32456 (UINT32_C(0x7) << 29)
32457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
32458 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
32459 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32460 uint8_t queue_id1_tsa_assign;
32461 /* Strict Priority */
32462 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
32464 /* Enhanced Transmission Selection */
32465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
32468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
32471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
32474 * Priority level for strict priority. Valid only when the
32475 * tsa_assign is 0 - Strict Priority (SP)
32476 * 0..7 - Valid values.
32477 * 8..255 - Reserved.
32479 uint8_t queue_id1_pri_lvl;
32481 * Weight used to allocate remaining BW for this COS after
32482 * servicing guaranteed bandwidths for all COS.
32484 uint8_t queue_id1_bw_weight;
32485 /* ID of CoS Queue 2. */
32488 * Minimum BW allocated to CoS Queue.
32489 * The HWRM will translate this value into byte counter and
32490 * time interval used for this COS inside the device.
32492 uint32_t queue_id2_min_bw;
32493 /* The bandwidth value. */
32494 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
32495 UINT32_C(0xfffffff)
32496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
32498 /* The granularity of the value (bits or bytes). */
32499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
32500 UINT32_C(0x10000000)
32501 /* Value is in bits. */
32502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
32503 (UINT32_C(0x0) << 28)
32504 /* Value is in bytes. */
32505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
32506 (UINT32_C(0x1) << 28)
32507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
32508 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
32509 /* bw_value_unit is 3 b */
32510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
32511 UINT32_C(0xe0000000)
32512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
32514 /* Value is in Mb or MB (base 10). */
32515 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
32516 (UINT32_C(0x0) << 29)
32517 /* Value is in Kb or KB (base 10). */
32518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
32519 (UINT32_C(0x2) << 29)
32520 /* Value is in bits or bytes. */
32521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
32522 (UINT32_C(0x4) << 29)
32523 /* Value is in Gb or GB (base 10). */
32524 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
32525 (UINT32_C(0x6) << 29)
32526 /* Value is in 1/100th of a percentage of total bandwidth. */
32527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32528 (UINT32_C(0x1) << 29)
32530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
32531 (UINT32_C(0x7) << 29)
32532 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
32533 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
32535 * Maximum BW allocated to CoS queue.
32536 * The HWRM will translate this value into byte counter and
32537 * time interval used for this COS inside the device.
32539 uint32_t queue_id2_max_bw;
32540 /* The bandwidth value. */
32541 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
32542 UINT32_C(0xfffffff)
32543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
32545 /* The granularity of the value (bits or bytes). */
32546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
32547 UINT32_C(0x10000000)
32548 /* Value is in bits. */
32549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
32550 (UINT32_C(0x0) << 28)
32551 /* Value is in bytes. */
32552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
32553 (UINT32_C(0x1) << 28)
32554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
32555 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
32556 /* bw_value_unit is 3 b */
32557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
32558 UINT32_C(0xe0000000)
32559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
32561 /* Value is in Mb or MB (base 10). */
32562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
32563 (UINT32_C(0x0) << 29)
32564 /* Value is in Kb or KB (base 10). */
32565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
32566 (UINT32_C(0x2) << 29)
32567 /* Value is in bits or bytes. */
32568 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
32569 (UINT32_C(0x4) << 29)
32570 /* Value is in Gb or GB (base 10). */
32571 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
32572 (UINT32_C(0x6) << 29)
32573 /* Value is in 1/100th of a percentage of total bandwidth. */
32574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32575 (UINT32_C(0x1) << 29)
32577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
32578 (UINT32_C(0x7) << 29)
32579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
32580 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
32581 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32582 uint8_t queue_id2_tsa_assign;
32583 /* Strict Priority */
32584 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
32586 /* Enhanced Transmission Selection */
32587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
32590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
32593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
32596 * Priority level for strict priority. Valid only when the
32597 * tsa_assign is 0 - Strict Priority (SP)
32598 * 0..7 - Valid values.
32599 * 8..255 - Reserved.
32601 uint8_t queue_id2_pri_lvl;
32603 * Weight used to allocate remaining BW for this COS after
32604 * servicing guaranteed bandwidths for all COS.
32606 uint8_t queue_id2_bw_weight;
32607 /* ID of CoS Queue 3. */
32610 * Minimum BW allocated to CoS Queue.
32611 * The HWRM will translate this value into byte counter and
32612 * time interval used for this COS inside the device.
32614 uint32_t queue_id3_min_bw;
32615 /* The bandwidth value. */
32616 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
32617 UINT32_C(0xfffffff)
32618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
32620 /* The granularity of the value (bits or bytes). */
32621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
32622 UINT32_C(0x10000000)
32623 /* Value is in bits. */
32624 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
32625 (UINT32_C(0x0) << 28)
32626 /* Value is in bytes. */
32627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
32628 (UINT32_C(0x1) << 28)
32629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
32630 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
32631 /* bw_value_unit is 3 b */
32632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
32633 UINT32_C(0xe0000000)
32634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
32636 /* Value is in Mb or MB (base 10). */
32637 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
32638 (UINT32_C(0x0) << 29)
32639 /* Value is in Kb or KB (base 10). */
32640 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
32641 (UINT32_C(0x2) << 29)
32642 /* Value is in bits or bytes. */
32643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
32644 (UINT32_C(0x4) << 29)
32645 /* Value is in Gb or GB (base 10). */
32646 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
32647 (UINT32_C(0x6) << 29)
32648 /* Value is in 1/100th of a percentage of total bandwidth. */
32649 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32650 (UINT32_C(0x1) << 29)
32652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
32653 (UINT32_C(0x7) << 29)
32654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
32655 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
32657 * Maximum BW allocated to CoS queue.
32658 * The HWRM will translate this value into byte counter and
32659 * time interval used for this COS inside the device.
32661 uint32_t queue_id3_max_bw;
32662 /* The bandwidth value. */
32663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
32664 UINT32_C(0xfffffff)
32665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
32667 /* The granularity of the value (bits or bytes). */
32668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
32669 UINT32_C(0x10000000)
32670 /* Value is in bits. */
32671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
32672 (UINT32_C(0x0) << 28)
32673 /* Value is in bytes. */
32674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
32675 (UINT32_C(0x1) << 28)
32676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
32677 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
32678 /* bw_value_unit is 3 b */
32679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
32680 UINT32_C(0xe0000000)
32681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
32683 /* Value is in Mb or MB (base 10). */
32684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
32685 (UINT32_C(0x0) << 29)
32686 /* Value is in Kb or KB (base 10). */
32687 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
32688 (UINT32_C(0x2) << 29)
32689 /* Value is in bits or bytes. */
32690 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
32691 (UINT32_C(0x4) << 29)
32692 /* Value is in Gb or GB (base 10). */
32693 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
32694 (UINT32_C(0x6) << 29)
32695 /* Value is in 1/100th of a percentage of total bandwidth. */
32696 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32697 (UINT32_C(0x1) << 29)
32699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
32700 (UINT32_C(0x7) << 29)
32701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
32702 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
32703 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32704 uint8_t queue_id3_tsa_assign;
32705 /* Strict Priority */
32706 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
32708 /* Enhanced Transmission Selection */
32709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
32712 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
32715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
32718 * Priority level for strict priority. Valid only when the
32719 * tsa_assign is 0 - Strict Priority (SP)
32720 * 0..7 - Valid values.
32721 * 8..255 - Reserved.
32723 uint8_t queue_id3_pri_lvl;
32725 * Weight used to allocate remaining BW for this COS after
32726 * servicing guaranteed bandwidths for all COS.
32728 uint8_t queue_id3_bw_weight;
32729 /* ID of CoS Queue 4. */
32732 * Minimum BW allocated to CoS Queue.
32733 * The HWRM will translate this value into byte counter and
32734 * time interval used for this COS inside the device.
32736 uint32_t queue_id4_min_bw;
32737 /* The bandwidth value. */
32738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
32739 UINT32_C(0xfffffff)
32740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
32742 /* The granularity of the value (bits or bytes). */
32743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
32744 UINT32_C(0x10000000)
32745 /* Value is in bits. */
32746 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
32747 (UINT32_C(0x0) << 28)
32748 /* Value is in bytes. */
32749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
32750 (UINT32_C(0x1) << 28)
32751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
32752 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
32753 /* bw_value_unit is 3 b */
32754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
32755 UINT32_C(0xe0000000)
32756 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
32758 /* Value is in Mb or MB (base 10). */
32759 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
32760 (UINT32_C(0x0) << 29)
32761 /* Value is in Kb or KB (base 10). */
32762 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
32763 (UINT32_C(0x2) << 29)
32764 /* Value is in bits or bytes. */
32765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
32766 (UINT32_C(0x4) << 29)
32767 /* Value is in Gb or GB (base 10). */
32768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
32769 (UINT32_C(0x6) << 29)
32770 /* Value is in 1/100th of a percentage of total bandwidth. */
32771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32772 (UINT32_C(0x1) << 29)
32774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
32775 (UINT32_C(0x7) << 29)
32776 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
32777 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
32779 * Maximum BW allocated to CoS queue.
32780 * The HWRM will translate this value into byte counter and
32781 * time interval used for this COS inside the device.
32783 uint32_t queue_id4_max_bw;
32784 /* The bandwidth value. */
32785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
32786 UINT32_C(0xfffffff)
32787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
32789 /* The granularity of the value (bits or bytes). */
32790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
32791 UINT32_C(0x10000000)
32792 /* Value is in bits. */
32793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
32794 (UINT32_C(0x0) << 28)
32795 /* Value is in bytes. */
32796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
32797 (UINT32_C(0x1) << 28)
32798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
32799 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
32800 /* bw_value_unit is 3 b */
32801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
32802 UINT32_C(0xe0000000)
32803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
32805 /* Value is in Mb or MB (base 10). */
32806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
32807 (UINT32_C(0x0) << 29)
32808 /* Value is in Kb or KB (base 10). */
32809 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
32810 (UINT32_C(0x2) << 29)
32811 /* Value is in bits or bytes. */
32812 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
32813 (UINT32_C(0x4) << 29)
32814 /* Value is in Gb or GB (base 10). */
32815 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
32816 (UINT32_C(0x6) << 29)
32817 /* Value is in 1/100th of a percentage of total bandwidth. */
32818 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32819 (UINT32_C(0x1) << 29)
32821 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
32822 (UINT32_C(0x7) << 29)
32823 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
32824 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
32825 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32826 uint8_t queue_id4_tsa_assign;
32827 /* Strict Priority */
32828 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
32830 /* Enhanced Transmission Selection */
32831 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
32834 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
32837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
32840 * Priority level for strict priority. Valid only when the
32841 * tsa_assign is 0 - Strict Priority (SP)
32842 * 0..7 - Valid values.
32843 * 8..255 - Reserved.
32845 uint8_t queue_id4_pri_lvl;
32847 * Weight used to allocate remaining BW for this COS after
32848 * servicing guaranteed bandwidths for all COS.
32850 uint8_t queue_id4_bw_weight;
32851 /* ID of CoS Queue 5. */
32854 * Minimum BW allocated to CoS Queue.
32855 * The HWRM will translate this value into byte counter and
32856 * time interval used for this COS inside the device.
32858 uint32_t queue_id5_min_bw;
32859 /* The bandwidth value. */
32860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
32861 UINT32_C(0xfffffff)
32862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
32864 /* The granularity of the value (bits or bytes). */
32865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
32866 UINT32_C(0x10000000)
32867 /* Value is in bits. */
32868 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
32869 (UINT32_C(0x0) << 28)
32870 /* Value is in bytes. */
32871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
32872 (UINT32_C(0x1) << 28)
32873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
32874 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
32875 /* bw_value_unit is 3 b */
32876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
32877 UINT32_C(0xe0000000)
32878 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
32880 /* Value is in Mb or MB (base 10). */
32881 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
32882 (UINT32_C(0x0) << 29)
32883 /* Value is in Kb or KB (base 10). */
32884 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
32885 (UINT32_C(0x2) << 29)
32886 /* Value is in bits or bytes. */
32887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
32888 (UINT32_C(0x4) << 29)
32889 /* Value is in Gb or GB (base 10). */
32890 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
32891 (UINT32_C(0x6) << 29)
32892 /* Value is in 1/100th of a percentage of total bandwidth. */
32893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
32894 (UINT32_C(0x1) << 29)
32896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
32897 (UINT32_C(0x7) << 29)
32898 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
32899 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
32901 * Maximum BW allocated to CoS queue.
32902 * The HWRM will translate this value into byte counter and
32903 * time interval used for this COS inside the device.
32905 uint32_t queue_id5_max_bw;
32906 /* The bandwidth value. */
32907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
32908 UINT32_C(0xfffffff)
32909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
32911 /* The granularity of the value (bits or bytes). */
32912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
32913 UINT32_C(0x10000000)
32914 /* Value is in bits. */
32915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
32916 (UINT32_C(0x0) << 28)
32917 /* Value is in bytes. */
32918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
32919 (UINT32_C(0x1) << 28)
32920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
32921 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
32922 /* bw_value_unit is 3 b */
32923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
32924 UINT32_C(0xe0000000)
32925 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
32927 /* Value is in Mb or MB (base 10). */
32928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
32929 (UINT32_C(0x0) << 29)
32930 /* Value is in Kb or KB (base 10). */
32931 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
32932 (UINT32_C(0x2) << 29)
32933 /* Value is in bits or bytes. */
32934 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
32935 (UINT32_C(0x4) << 29)
32936 /* Value is in Gb or GB (base 10). */
32937 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
32938 (UINT32_C(0x6) << 29)
32939 /* Value is in 1/100th of a percentage of total bandwidth. */
32940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32941 (UINT32_C(0x1) << 29)
32943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
32944 (UINT32_C(0x7) << 29)
32945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
32946 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
32947 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
32948 uint8_t queue_id5_tsa_assign;
32949 /* Strict Priority */
32950 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
32952 /* Enhanced Transmission Selection */
32953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
32956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
32959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
32962 * Priority level for strict priority. Valid only when the
32963 * tsa_assign is 0 - Strict Priority (SP)
32964 * 0..7 - Valid values.
32965 * 8..255 - Reserved.
32967 uint8_t queue_id5_pri_lvl;
32969 * Weight used to allocate remaining BW for this COS after
32970 * servicing guaranteed bandwidths for all COS.
32972 uint8_t queue_id5_bw_weight;
32973 /* ID of CoS Queue 6. */
32976 * Minimum BW allocated to CoS Queue.
32977 * The HWRM will translate this value into byte counter and
32978 * time interval used for this COS inside the device.
32980 uint32_t queue_id6_min_bw;
32981 /* The bandwidth value. */
32982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
32983 UINT32_C(0xfffffff)
32984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
32986 /* The granularity of the value (bits or bytes). */
32987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
32988 UINT32_C(0x10000000)
32989 /* Value is in bits. */
32990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
32991 (UINT32_C(0x0) << 28)
32992 /* Value is in bytes. */
32993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
32994 (UINT32_C(0x1) << 28)
32995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
32996 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
32997 /* bw_value_unit is 3 b */
32998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
32999 UINT32_C(0xe0000000)
33000 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
33002 /* Value is in Mb or MB (base 10). */
33003 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
33004 (UINT32_C(0x0) << 29)
33005 /* Value is in Kb or KB (base 10). */
33006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
33007 (UINT32_C(0x2) << 29)
33008 /* Value is in bits or bytes. */
33009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
33010 (UINT32_C(0x4) << 29)
33011 /* Value is in Gb or GB (base 10). */
33012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
33013 (UINT32_C(0x6) << 29)
33014 /* Value is in 1/100th of a percentage of total bandwidth. */
33015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33016 (UINT32_C(0x1) << 29)
33018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
33019 (UINT32_C(0x7) << 29)
33020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
33021 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
33023 * Maximum BW allocated to CoS queue.
33024 * The HWRM will translate this value into byte counter and
33025 * time interval used for this COS inside the device.
33027 uint32_t queue_id6_max_bw;
33028 /* The bandwidth value. */
33029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
33030 UINT32_C(0xfffffff)
33031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
33033 /* The granularity of the value (bits or bytes). */
33034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
33035 UINT32_C(0x10000000)
33036 /* Value is in bits. */
33037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
33038 (UINT32_C(0x0) << 28)
33039 /* Value is in bytes. */
33040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
33041 (UINT32_C(0x1) << 28)
33042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
33043 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
33044 /* bw_value_unit is 3 b */
33045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
33046 UINT32_C(0xe0000000)
33047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
33049 /* Value is in Mb or MB (base 10). */
33050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
33051 (UINT32_C(0x0) << 29)
33052 /* Value is in Kb or KB (base 10). */
33053 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
33054 (UINT32_C(0x2) << 29)
33055 /* Value is in bits or bytes. */
33056 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
33057 (UINT32_C(0x4) << 29)
33058 /* Value is in Gb or GB (base 10). */
33059 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
33060 (UINT32_C(0x6) << 29)
33061 /* Value is in 1/100th of a percentage of total bandwidth. */
33062 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33063 (UINT32_C(0x1) << 29)
33065 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
33066 (UINT32_C(0x7) << 29)
33067 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
33068 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
33069 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33070 uint8_t queue_id6_tsa_assign;
33071 /* Strict Priority */
33072 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
33074 /* Enhanced Transmission Selection */
33075 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
33078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
33081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
33084 * Priority level for strict priority. Valid only when the
33085 * tsa_assign is 0 - Strict Priority (SP)
33086 * 0..7 - Valid values.
33087 * 8..255 - Reserved.
33089 uint8_t queue_id6_pri_lvl;
33091 * Weight used to allocate remaining BW for this COS after
33092 * servicing guaranteed bandwidths for all COS.
33094 uint8_t queue_id6_bw_weight;
33095 /* ID of CoS Queue 7. */
33098 * Minimum BW allocated to CoS Queue.
33099 * The HWRM will translate this value into byte counter and
33100 * time interval used for this COS inside the device.
33102 uint32_t queue_id7_min_bw;
33103 /* The bandwidth value. */
33104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
33105 UINT32_C(0xfffffff)
33106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
33108 /* The granularity of the value (bits or bytes). */
33109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
33110 UINT32_C(0x10000000)
33111 /* Value is in bits. */
33112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
33113 (UINT32_C(0x0) << 28)
33114 /* Value is in bytes. */
33115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
33116 (UINT32_C(0x1) << 28)
33117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
33118 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
33119 /* bw_value_unit is 3 b */
33120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
33121 UINT32_C(0xe0000000)
33122 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
33124 /* Value is in Mb or MB (base 10). */
33125 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
33126 (UINT32_C(0x0) << 29)
33127 /* Value is in Kb or KB (base 10). */
33128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
33129 (UINT32_C(0x2) << 29)
33130 /* Value is in bits or bytes. */
33131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
33132 (UINT32_C(0x4) << 29)
33133 /* Value is in Gb or GB (base 10). */
33134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
33135 (UINT32_C(0x6) << 29)
33136 /* Value is in 1/100th of a percentage of total bandwidth. */
33137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33138 (UINT32_C(0x1) << 29)
33140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
33141 (UINT32_C(0x7) << 29)
33142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
33143 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
33145 * Maximum BW allocated to CoS queue.
33146 * The HWRM will translate this value into byte counter and
33147 * time interval used for this COS inside the device.
33149 uint32_t queue_id7_max_bw;
33150 /* The bandwidth value. */
33151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
33152 UINT32_C(0xfffffff)
33153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
33155 /* The granularity of the value (bits or bytes). */
33156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
33157 UINT32_C(0x10000000)
33158 /* Value is in bits. */
33159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
33160 (UINT32_C(0x0) << 28)
33161 /* Value is in bytes. */
33162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
33163 (UINT32_C(0x1) << 28)
33164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
33165 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
33166 /* bw_value_unit is 3 b */
33167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
33168 UINT32_C(0xe0000000)
33169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
33171 /* Value is in Mb or MB (base 10). */
33172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
33173 (UINT32_C(0x0) << 29)
33174 /* Value is in Kb or KB (base 10). */
33175 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
33176 (UINT32_C(0x2) << 29)
33177 /* Value is in bits or bytes. */
33178 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
33179 (UINT32_C(0x4) << 29)
33180 /* Value is in Gb or GB (base 10). */
33181 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
33182 (UINT32_C(0x6) << 29)
33183 /* Value is in 1/100th of a percentage of total bandwidth. */
33184 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33185 (UINT32_C(0x1) << 29)
33187 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
33188 (UINT32_C(0x7) << 29)
33189 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
33190 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
33191 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33192 uint8_t queue_id7_tsa_assign;
33193 /* Strict Priority */
33194 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
33196 /* Enhanced Transmission Selection */
33197 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
33200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
33203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
33206 * Priority level for strict priority. Valid only when the
33207 * tsa_assign is 0 - Strict Priority (SP)
33208 * 0..7 - Valid values.
33209 * 8..255 - Reserved.
33211 uint8_t queue_id7_pri_lvl;
33213 * Weight used to allocate remaining BW for this COS after
33214 * servicing guaranteed bandwidths for all COS.
33216 uint8_t queue_id7_bw_weight;
33217 uint8_t unused_2[4];
33219 * This field is used in Output records to indicate that the output
33220 * is completely written to RAM. This field should be read as '1'
33221 * to indicate that the output has been completely written.
33222 * When writing a command completion or response to an internal processor,
33223 * the order of writes has to be such that this field is written last.
33228 /*************************
33229 * hwrm_queue_cos2bw_cfg *
33230 *************************/
33233 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
33234 struct hwrm_queue_cos2bw_cfg_input {
33235 /* The HWRM command request type. */
33238 * The completion ring to send the completion event on. This should
33239 * be the NQ ID returned from the `nq_alloc` HWRM command.
33241 uint16_t cmpl_ring;
33243 * The sequence ID is used by the driver for tracking multiple
33244 * commands. This ID is treated as opaque data by the firmware and
33245 * the value is returned in the `hwrm_resp_hdr` upon completion.
33249 * The target ID of the command:
33250 * * 0x0-0xFFF8 - The function ID
33251 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33252 * * 0xFFFD - Reserved for user-space HWRM interface
33255 uint16_t target_id;
33257 * A physical address pointer pointing to a host buffer that the
33258 * command's response data will be written. This can be either a host
33259 * physical address (HPA) or a guest physical address (GPA) and must
33260 * point to a physically contiguous block of memory.
33262 uint64_t resp_addr;
33266 * If this bit is set to 1, then all queue_id0 related
33267 * parameters in this command are valid.
33269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
33272 * If this bit is set to 1, then all queue_id1 related
33273 * parameters in this command are valid.
33275 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
33278 * If this bit is set to 1, then all queue_id2 related
33279 * parameters in this command are valid.
33281 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
33284 * If this bit is set to 1, then all queue_id3 related
33285 * parameters in this command are valid.
33287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
33290 * If this bit is set to 1, then all queue_id4 related
33291 * parameters in this command are valid.
33293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
33296 * If this bit is set to 1, then all queue_id5 related
33297 * parameters in this command are valid.
33299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
33302 * If this bit is set to 1, then all queue_id6 related
33303 * parameters in this command are valid.
33305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
33308 * If this bit is set to 1, then all queue_id7 related
33309 * parameters in this command are valid.
33311 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
33314 * Port ID of port for which the table is being configured.
33315 * The HWRM needs to check whether this function is allowed
33316 * to configure TC BW assignment on this port.
33319 /* ID of CoS Queue 0. */
33323 * Minimum BW allocated to CoS Queue.
33324 * The HWRM will translate this value into byte counter and
33325 * time interval used for this COS inside the device.
33327 uint32_t queue_id0_min_bw;
33328 /* The bandwidth value. */
33329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
33330 UINT32_C(0xfffffff)
33331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
33333 /* The granularity of the value (bits or bytes). */
33334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
33335 UINT32_C(0x10000000)
33336 /* Value is in bits. */
33337 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
33338 (UINT32_C(0x0) << 28)
33339 /* Value is in bytes. */
33340 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
33341 (UINT32_C(0x1) << 28)
33342 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
33343 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
33344 /* bw_value_unit is 3 b */
33345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
33346 UINT32_C(0xe0000000)
33347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
33349 /* Value is in Mb or MB (base 10). */
33350 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
33351 (UINT32_C(0x0) << 29)
33352 /* Value is in Kb or KB (base 10). */
33353 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
33354 (UINT32_C(0x2) << 29)
33355 /* Value is in bits or bytes. */
33356 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
33357 (UINT32_C(0x4) << 29)
33358 /* Value is in Gb or GB (base 10). */
33359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
33360 (UINT32_C(0x6) << 29)
33361 /* Value is in 1/100th of a percentage of total bandwidth. */
33362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33363 (UINT32_C(0x1) << 29)
33365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
33366 (UINT32_C(0x7) << 29)
33367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
33368 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
33370 * Maximum BW allocated to CoS Queue.
33371 * The HWRM will translate this value into byte counter and
33372 * time interval used for this COS inside the device.
33374 uint32_t queue_id0_max_bw;
33375 /* The bandwidth value. */
33376 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
33377 UINT32_C(0xfffffff)
33378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
33380 /* The granularity of the value (bits or bytes). */
33381 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
33382 UINT32_C(0x10000000)
33383 /* Value is in bits. */
33384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
33385 (UINT32_C(0x0) << 28)
33386 /* Value is in bytes. */
33387 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
33388 (UINT32_C(0x1) << 28)
33389 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
33390 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
33391 /* bw_value_unit is 3 b */
33392 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
33393 UINT32_C(0xe0000000)
33394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
33396 /* Value is in Mb or MB (base 10). */
33397 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
33398 (UINT32_C(0x0) << 29)
33399 /* Value is in Kb or KB (base 10). */
33400 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
33401 (UINT32_C(0x2) << 29)
33402 /* Value is in bits or bytes. */
33403 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
33404 (UINT32_C(0x4) << 29)
33405 /* Value is in Gb or GB (base 10). */
33406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
33407 (UINT32_C(0x6) << 29)
33408 /* Value is in 1/100th of a percentage of total bandwidth. */
33409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33410 (UINT32_C(0x1) << 29)
33412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
33413 (UINT32_C(0x7) << 29)
33414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
33415 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
33416 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33417 uint8_t queue_id0_tsa_assign;
33418 /* Strict Priority */
33419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
33421 /* Enhanced Transmission Selection */
33422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
33425 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
33428 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
33431 * Priority level for strict priority. Valid only when the
33432 * tsa_assign is 0 - Strict Priority (SP)
33433 * 0..7 - Valid values.
33434 * 8..255 - Reserved.
33436 uint8_t queue_id0_pri_lvl;
33438 * Weight used to allocate remaining BW for this COS after
33439 * servicing guaranteed bandwidths for all COS.
33441 uint8_t queue_id0_bw_weight;
33442 /* ID of CoS Queue 1. */
33445 * Minimum BW allocated to CoS Queue.
33446 * The HWRM will translate this value into byte counter and
33447 * time interval used for this COS inside the device.
33449 uint32_t queue_id1_min_bw;
33450 /* The bandwidth value. */
33451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
33452 UINT32_C(0xfffffff)
33453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
33455 /* The granularity of the value (bits or bytes). */
33456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
33457 UINT32_C(0x10000000)
33458 /* Value is in bits. */
33459 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
33460 (UINT32_C(0x0) << 28)
33461 /* Value is in bytes. */
33462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
33463 (UINT32_C(0x1) << 28)
33464 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
33465 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
33466 /* bw_value_unit is 3 b */
33467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
33468 UINT32_C(0xe0000000)
33469 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
33471 /* Value is in Mb or MB (base 10). */
33472 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
33473 (UINT32_C(0x0) << 29)
33474 /* Value is in Kb or KB (base 10). */
33475 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
33476 (UINT32_C(0x2) << 29)
33477 /* Value is in bits or bytes. */
33478 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
33479 (UINT32_C(0x4) << 29)
33480 /* Value is in Gb or GB (base 10). */
33481 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
33482 (UINT32_C(0x6) << 29)
33483 /* Value is in 1/100th of a percentage of total bandwidth. */
33484 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33485 (UINT32_C(0x1) << 29)
33487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
33488 (UINT32_C(0x7) << 29)
33489 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
33490 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
33492 * Maximum BW allocated to CoS queue.
33493 * The HWRM will translate this value into byte counter and
33494 * time interval used for this COS inside the device.
33496 uint32_t queue_id1_max_bw;
33497 /* The bandwidth value. */
33498 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
33499 UINT32_C(0xfffffff)
33500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
33502 /* The granularity of the value (bits or bytes). */
33503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
33504 UINT32_C(0x10000000)
33505 /* Value is in bits. */
33506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
33507 (UINT32_C(0x0) << 28)
33508 /* Value is in bytes. */
33509 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
33510 (UINT32_C(0x1) << 28)
33511 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
33512 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
33513 /* bw_value_unit is 3 b */
33514 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
33515 UINT32_C(0xe0000000)
33516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
33518 /* Value is in Mb or MB (base 10). */
33519 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
33520 (UINT32_C(0x0) << 29)
33521 /* Value is in Kb or KB (base 10). */
33522 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
33523 (UINT32_C(0x2) << 29)
33524 /* Value is in bits or bytes. */
33525 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
33526 (UINT32_C(0x4) << 29)
33527 /* Value is in Gb or GB (base 10). */
33528 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
33529 (UINT32_C(0x6) << 29)
33530 /* Value is in 1/100th of a percentage of total bandwidth. */
33531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33532 (UINT32_C(0x1) << 29)
33534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
33535 (UINT32_C(0x7) << 29)
33536 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
33537 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
33538 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33539 uint8_t queue_id1_tsa_assign;
33540 /* Strict Priority */
33541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
33543 /* Enhanced Transmission Selection */
33544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
33547 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
33550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
33553 * Priority level for strict priority. Valid only when the
33554 * tsa_assign is 0 - Strict Priority (SP)
33555 * 0..7 - Valid values.
33556 * 8..255 - Reserved.
33558 uint8_t queue_id1_pri_lvl;
33560 * Weight used to allocate remaining BW for this COS after
33561 * servicing guaranteed bandwidths for all COS.
33563 uint8_t queue_id1_bw_weight;
33564 /* ID of CoS Queue 2. */
33567 * Minimum BW allocated to CoS Queue.
33568 * The HWRM will translate this value into byte counter and
33569 * time interval used for this COS inside the device.
33571 uint32_t queue_id2_min_bw;
33572 /* The bandwidth value. */
33573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
33574 UINT32_C(0xfffffff)
33575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
33577 /* The granularity of the value (bits or bytes). */
33578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
33579 UINT32_C(0x10000000)
33580 /* Value is in bits. */
33581 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
33582 (UINT32_C(0x0) << 28)
33583 /* Value is in bytes. */
33584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
33585 (UINT32_C(0x1) << 28)
33586 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
33587 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
33588 /* bw_value_unit is 3 b */
33589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
33590 UINT32_C(0xe0000000)
33591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
33593 /* Value is in Mb or MB (base 10). */
33594 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
33595 (UINT32_C(0x0) << 29)
33596 /* Value is in Kb or KB (base 10). */
33597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
33598 (UINT32_C(0x2) << 29)
33599 /* Value is in bits or bytes. */
33600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
33601 (UINT32_C(0x4) << 29)
33602 /* Value is in Gb or GB (base 10). */
33603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
33604 (UINT32_C(0x6) << 29)
33605 /* Value is in 1/100th of a percentage of total bandwidth. */
33606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33607 (UINT32_C(0x1) << 29)
33609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
33610 (UINT32_C(0x7) << 29)
33611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
33612 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
33614 * Maximum BW allocated to CoS queue.
33615 * The HWRM will translate this value into byte counter and
33616 * time interval used for this COS inside the device.
33618 uint32_t queue_id2_max_bw;
33619 /* The bandwidth value. */
33620 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
33621 UINT32_C(0xfffffff)
33622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
33624 /* The granularity of the value (bits or bytes). */
33625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
33626 UINT32_C(0x10000000)
33627 /* Value is in bits. */
33628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
33629 (UINT32_C(0x0) << 28)
33630 /* Value is in bytes. */
33631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
33632 (UINT32_C(0x1) << 28)
33633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
33634 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
33635 /* bw_value_unit is 3 b */
33636 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
33637 UINT32_C(0xe0000000)
33638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
33640 /* Value is in Mb or MB (base 10). */
33641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
33642 (UINT32_C(0x0) << 29)
33643 /* Value is in Kb or KB (base 10). */
33644 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
33645 (UINT32_C(0x2) << 29)
33646 /* Value is in bits or bytes. */
33647 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
33648 (UINT32_C(0x4) << 29)
33649 /* Value is in Gb or GB (base 10). */
33650 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
33651 (UINT32_C(0x6) << 29)
33652 /* Value is in 1/100th of a percentage of total bandwidth. */
33653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33654 (UINT32_C(0x1) << 29)
33656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
33657 (UINT32_C(0x7) << 29)
33658 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
33659 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
33660 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33661 uint8_t queue_id2_tsa_assign;
33662 /* Strict Priority */
33663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
33665 /* Enhanced Transmission Selection */
33666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
33669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
33672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
33675 * Priority level for strict priority. Valid only when the
33676 * tsa_assign is 0 - Strict Priority (SP)
33677 * 0..7 - Valid values.
33678 * 8..255 - Reserved.
33680 uint8_t queue_id2_pri_lvl;
33682 * Weight used to allocate remaining BW for this COS after
33683 * servicing guaranteed bandwidths for all COS.
33685 uint8_t queue_id2_bw_weight;
33686 /* ID of CoS Queue 3. */
33689 * Minimum BW allocated to CoS Queue.
33690 * The HWRM will translate this value into byte counter and
33691 * time interval used for this COS inside the device.
33693 uint32_t queue_id3_min_bw;
33694 /* The bandwidth value. */
33695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
33696 UINT32_C(0xfffffff)
33697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
33699 /* The granularity of the value (bits or bytes). */
33700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
33701 UINT32_C(0x10000000)
33702 /* Value is in bits. */
33703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
33704 (UINT32_C(0x0) << 28)
33705 /* Value is in bytes. */
33706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
33707 (UINT32_C(0x1) << 28)
33708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
33709 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
33710 /* bw_value_unit is 3 b */
33711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
33712 UINT32_C(0xe0000000)
33713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
33715 /* Value is in Mb or MB (base 10). */
33716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
33717 (UINT32_C(0x0) << 29)
33718 /* Value is in Kb or KB (base 10). */
33719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
33720 (UINT32_C(0x2) << 29)
33721 /* Value is in bits or bytes. */
33722 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
33723 (UINT32_C(0x4) << 29)
33724 /* Value is in Gb or GB (base 10). */
33725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
33726 (UINT32_C(0x6) << 29)
33727 /* Value is in 1/100th of a percentage of total bandwidth. */
33728 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33729 (UINT32_C(0x1) << 29)
33731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
33732 (UINT32_C(0x7) << 29)
33733 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
33734 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
33736 * Maximum BW allocated to CoS queue.
33737 * The HWRM will translate this value into byte counter and
33738 * time interval used for this COS inside the device.
33740 uint32_t queue_id3_max_bw;
33741 /* The bandwidth value. */
33742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
33743 UINT32_C(0xfffffff)
33744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
33746 /* The granularity of the value (bits or bytes). */
33747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
33748 UINT32_C(0x10000000)
33749 /* Value is in bits. */
33750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
33751 (UINT32_C(0x0) << 28)
33752 /* Value is in bytes. */
33753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
33754 (UINT32_C(0x1) << 28)
33755 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
33756 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
33757 /* bw_value_unit is 3 b */
33758 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
33759 UINT32_C(0xe0000000)
33760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
33762 /* Value is in Mb or MB (base 10). */
33763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
33764 (UINT32_C(0x0) << 29)
33765 /* Value is in Kb or KB (base 10). */
33766 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
33767 (UINT32_C(0x2) << 29)
33768 /* Value is in bits or bytes. */
33769 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
33770 (UINT32_C(0x4) << 29)
33771 /* Value is in Gb or GB (base 10). */
33772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
33773 (UINT32_C(0x6) << 29)
33774 /* Value is in 1/100th of a percentage of total bandwidth. */
33775 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33776 (UINT32_C(0x1) << 29)
33778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
33779 (UINT32_C(0x7) << 29)
33780 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
33781 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
33782 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33783 uint8_t queue_id3_tsa_assign;
33784 /* Strict Priority */
33785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
33787 /* Enhanced Transmission Selection */
33788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
33791 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
33794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
33797 * Priority level for strict priority. Valid only when the
33798 * tsa_assign is 0 - Strict Priority (SP)
33799 * 0..7 - Valid values.
33800 * 8..255 - Reserved.
33802 uint8_t queue_id3_pri_lvl;
33804 * Weight used to allocate remaining BW for this COS after
33805 * servicing guaranteed bandwidths for all COS.
33807 uint8_t queue_id3_bw_weight;
33808 /* ID of CoS Queue 4. */
33811 * Minimum BW allocated to CoS Queue.
33812 * The HWRM will translate this value into byte counter and
33813 * time interval used for this COS inside the device.
33815 uint32_t queue_id4_min_bw;
33816 /* The bandwidth value. */
33817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
33818 UINT32_C(0xfffffff)
33819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
33821 /* The granularity of the value (bits or bytes). */
33822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
33823 UINT32_C(0x10000000)
33824 /* Value is in bits. */
33825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
33826 (UINT32_C(0x0) << 28)
33827 /* Value is in bytes. */
33828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
33829 (UINT32_C(0x1) << 28)
33830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
33831 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
33832 /* bw_value_unit is 3 b */
33833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
33834 UINT32_C(0xe0000000)
33835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
33837 /* Value is in Mb or MB (base 10). */
33838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
33839 (UINT32_C(0x0) << 29)
33840 /* Value is in Kb or KB (base 10). */
33841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
33842 (UINT32_C(0x2) << 29)
33843 /* Value is in bits or bytes. */
33844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
33845 (UINT32_C(0x4) << 29)
33846 /* Value is in Gb or GB (base 10). */
33847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
33848 (UINT32_C(0x6) << 29)
33849 /* Value is in 1/100th of a percentage of total bandwidth. */
33850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33851 (UINT32_C(0x1) << 29)
33853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
33854 (UINT32_C(0x7) << 29)
33855 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
33856 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
33858 * Maximum BW allocated to CoS queue.
33859 * The HWRM will translate this value into byte counter and
33860 * time interval used for this COS inside the device.
33862 uint32_t queue_id4_max_bw;
33863 /* The bandwidth value. */
33864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
33865 UINT32_C(0xfffffff)
33866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
33868 /* The granularity of the value (bits or bytes). */
33869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
33870 UINT32_C(0x10000000)
33871 /* Value is in bits. */
33872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
33873 (UINT32_C(0x0) << 28)
33874 /* Value is in bytes. */
33875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
33876 (UINT32_C(0x1) << 28)
33877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
33878 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
33879 /* bw_value_unit is 3 b */
33880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
33881 UINT32_C(0xe0000000)
33882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
33884 /* Value is in Mb or MB (base 10). */
33885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
33886 (UINT32_C(0x0) << 29)
33887 /* Value is in Kb or KB (base 10). */
33888 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
33889 (UINT32_C(0x2) << 29)
33890 /* Value is in bits or bytes. */
33891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
33892 (UINT32_C(0x4) << 29)
33893 /* Value is in Gb or GB (base 10). */
33894 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
33895 (UINT32_C(0x6) << 29)
33896 /* Value is in 1/100th of a percentage of total bandwidth. */
33897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
33898 (UINT32_C(0x1) << 29)
33900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
33901 (UINT32_C(0x7) << 29)
33902 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
33903 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
33904 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
33905 uint8_t queue_id4_tsa_assign;
33906 /* Strict Priority */
33907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
33909 /* Enhanced Transmission Selection */
33910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
33913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
33916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
33919 * Priority level for strict priority. Valid only when the
33920 * tsa_assign is 0 - Strict Priority (SP)
33921 * 0..7 - Valid values.
33922 * 8..255 - Reserved.
33924 uint8_t queue_id4_pri_lvl;
33926 * Weight used to allocate remaining BW for this COS after
33927 * servicing guaranteed bandwidths for all COS.
33929 uint8_t queue_id4_bw_weight;
33930 /* ID of CoS Queue 5. */
33933 * Minimum BW allocated to CoS Queue.
33934 * The HWRM will translate this value into byte counter and
33935 * time interval used for this COS inside the device.
33937 uint32_t queue_id5_min_bw;
33938 /* The bandwidth value. */
33939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
33940 UINT32_C(0xfffffff)
33941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
33943 /* The granularity of the value (bits or bytes). */
33944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
33945 UINT32_C(0x10000000)
33946 /* Value is in bits. */
33947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
33948 (UINT32_C(0x0) << 28)
33949 /* Value is in bytes. */
33950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
33951 (UINT32_C(0x1) << 28)
33952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
33953 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
33954 /* bw_value_unit is 3 b */
33955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
33956 UINT32_C(0xe0000000)
33957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
33959 /* Value is in Mb or MB (base 10). */
33960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
33961 (UINT32_C(0x0) << 29)
33962 /* Value is in Kb or KB (base 10). */
33963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
33964 (UINT32_C(0x2) << 29)
33965 /* Value is in bits or bytes. */
33966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
33967 (UINT32_C(0x4) << 29)
33968 /* Value is in Gb or GB (base 10). */
33969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
33970 (UINT32_C(0x6) << 29)
33971 /* Value is in 1/100th of a percentage of total bandwidth. */
33972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
33973 (UINT32_C(0x1) << 29)
33975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
33976 (UINT32_C(0x7) << 29)
33977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
33978 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
33980 * Maximum BW allocated to CoS queue.
33981 * The HWRM will translate this value into byte counter and
33982 * time interval used for this COS inside the device.
33984 uint32_t queue_id5_max_bw;
33985 /* The bandwidth value. */
33986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
33987 UINT32_C(0xfffffff)
33988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
33990 /* The granularity of the value (bits or bytes). */
33991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
33992 UINT32_C(0x10000000)
33993 /* Value is in bits. */
33994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
33995 (UINT32_C(0x0) << 28)
33996 /* Value is in bytes. */
33997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
33998 (UINT32_C(0x1) << 28)
33999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
34000 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
34001 /* bw_value_unit is 3 b */
34002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
34003 UINT32_C(0xe0000000)
34004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
34006 /* Value is in Mb or MB (base 10). */
34007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
34008 (UINT32_C(0x0) << 29)
34009 /* Value is in Kb or KB (base 10). */
34010 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
34011 (UINT32_C(0x2) << 29)
34012 /* Value is in bits or bytes. */
34013 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
34014 (UINT32_C(0x4) << 29)
34015 /* Value is in Gb or GB (base 10). */
34016 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
34017 (UINT32_C(0x6) << 29)
34018 /* Value is in 1/100th of a percentage of total bandwidth. */
34019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
34020 (UINT32_C(0x1) << 29)
34022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
34023 (UINT32_C(0x7) << 29)
34024 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
34025 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
34026 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
34027 uint8_t queue_id5_tsa_assign;
34028 /* Strict Priority */
34029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
34031 /* Enhanced Transmission Selection */
34032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
34035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
34038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
34041 * Priority level for strict priority. Valid only when the
34042 * tsa_assign is 0 - Strict Priority (SP)
34043 * 0..7 - Valid values.
34044 * 8..255 - Reserved.
34046 uint8_t queue_id5_pri_lvl;
34048 * Weight used to allocate remaining BW for this COS after
34049 * servicing guaranteed bandwidths for all COS.
34051 uint8_t queue_id5_bw_weight;
34052 /* ID of CoS Queue 6. */
34055 * Minimum BW allocated to CoS Queue.
34056 * The HWRM will translate this value into byte counter and
34057 * time interval used for this COS inside the device.
34059 uint32_t queue_id6_min_bw;
34060 /* The bandwidth value. */
34061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
34062 UINT32_C(0xfffffff)
34063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
34065 /* The granularity of the value (bits or bytes). */
34066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
34067 UINT32_C(0x10000000)
34068 /* Value is in bits. */
34069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
34070 (UINT32_C(0x0) << 28)
34071 /* Value is in bytes. */
34072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
34073 (UINT32_C(0x1) << 28)
34074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
34075 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
34076 /* bw_value_unit is 3 b */
34077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
34078 UINT32_C(0xe0000000)
34079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
34081 /* Value is in Mb or MB (base 10). */
34082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
34083 (UINT32_C(0x0) << 29)
34084 /* Value is in Kb or KB (base 10). */
34085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
34086 (UINT32_C(0x2) << 29)
34087 /* Value is in bits or bytes. */
34088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
34089 (UINT32_C(0x4) << 29)
34090 /* Value is in Gb or GB (base 10). */
34091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
34092 (UINT32_C(0x6) << 29)
34093 /* Value is in 1/100th of a percentage of total bandwidth. */
34094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
34095 (UINT32_C(0x1) << 29)
34097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
34098 (UINT32_C(0x7) << 29)
34099 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
34100 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
34102 * Maximum BW allocated to CoS queue.
34103 * The HWRM will translate this value into byte counter and
34104 * time interval used for this COS inside the device.
34106 uint32_t queue_id6_max_bw;
34107 /* The bandwidth value. */
34108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
34109 UINT32_C(0xfffffff)
34110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
34112 /* The granularity of the value (bits or bytes). */
34113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
34114 UINT32_C(0x10000000)
34115 /* Value is in bits. */
34116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
34117 (UINT32_C(0x0) << 28)
34118 /* Value is in bytes. */
34119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
34120 (UINT32_C(0x1) << 28)
34121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
34122 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
34123 /* bw_value_unit is 3 b */
34124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
34125 UINT32_C(0xe0000000)
34126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
34128 /* Value is in Mb or MB (base 10). */
34129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
34130 (UINT32_C(0x0) << 29)
34131 /* Value is in Kb or KB (base 10). */
34132 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
34133 (UINT32_C(0x2) << 29)
34134 /* Value is in bits or bytes. */
34135 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
34136 (UINT32_C(0x4) << 29)
34137 /* Value is in Gb or GB (base 10). */
34138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
34139 (UINT32_C(0x6) << 29)
34140 /* Value is in 1/100th of a percentage of total bandwidth. */
34141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
34142 (UINT32_C(0x1) << 29)
34144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
34145 (UINT32_C(0x7) << 29)
34146 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
34147 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
34148 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
34149 uint8_t queue_id6_tsa_assign;
34150 /* Strict Priority */
34151 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
34153 /* Enhanced Transmission Selection */
34154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
34157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
34160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
34163 * Priority level for strict priority. Valid only when the
34164 * tsa_assign is 0 - Strict Priority (SP)
34165 * 0..7 - Valid values.
34166 * 8..255 - Reserved.
34168 uint8_t queue_id6_pri_lvl;
34170 * Weight used to allocate remaining BW for this COS after
34171 * servicing guaranteed bandwidths for all COS.
34173 uint8_t queue_id6_bw_weight;
34174 /* ID of CoS Queue 7. */
34177 * Minimum BW allocated to CoS Queue.
34178 * The HWRM will translate this value into byte counter and
34179 * time interval used for this COS inside the device.
34181 uint32_t queue_id7_min_bw;
34182 /* The bandwidth value. */
34183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
34184 UINT32_C(0xfffffff)
34185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
34187 /* The granularity of the value (bits or bytes). */
34188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
34189 UINT32_C(0x10000000)
34190 /* Value is in bits. */
34191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
34192 (UINT32_C(0x0) << 28)
34193 /* Value is in bytes. */
34194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
34195 (UINT32_C(0x1) << 28)
34196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
34197 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
34198 /* bw_value_unit is 3 b */
34199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
34200 UINT32_C(0xe0000000)
34201 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
34203 /* Value is in Mb or MB (base 10). */
34204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
34205 (UINT32_C(0x0) << 29)
34206 /* Value is in Kb or KB (base 10). */
34207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
34208 (UINT32_C(0x2) << 29)
34209 /* Value is in bits or bytes. */
34210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
34211 (UINT32_C(0x4) << 29)
34212 /* Value is in Gb or GB (base 10). */
34213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
34214 (UINT32_C(0x6) << 29)
34215 /* Value is in 1/100th of a percentage of total bandwidth. */
34216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
34217 (UINT32_C(0x1) << 29)
34219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
34220 (UINT32_C(0x7) << 29)
34221 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
34222 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
34224 * Maximum BW allocated to CoS queue.
34225 * The HWRM will translate this value into byte counter and
34226 * time interval used for this COS inside the device.
34228 uint32_t queue_id7_max_bw;
34229 /* The bandwidth value. */
34230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
34231 UINT32_C(0xfffffff)
34232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
34234 /* The granularity of the value (bits or bytes). */
34235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
34236 UINT32_C(0x10000000)
34237 /* Value is in bits. */
34238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
34239 (UINT32_C(0x0) << 28)
34240 /* Value is in bytes. */
34241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
34242 (UINT32_C(0x1) << 28)
34243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
34244 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
34245 /* bw_value_unit is 3 b */
34246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
34247 UINT32_C(0xe0000000)
34248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
34250 /* Value is in Mb or MB (base 10). */
34251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
34252 (UINT32_C(0x0) << 29)
34253 /* Value is in Kb or KB (base 10). */
34254 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
34255 (UINT32_C(0x2) << 29)
34256 /* Value is in bits or bytes. */
34257 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
34258 (UINT32_C(0x4) << 29)
34259 /* Value is in Gb or GB (base 10). */
34260 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
34261 (UINT32_C(0x6) << 29)
34262 /* Value is in 1/100th of a percentage of total bandwidth. */
34263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
34264 (UINT32_C(0x1) << 29)
34266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
34267 (UINT32_C(0x7) << 29)
34268 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
34269 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
34270 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
34271 uint8_t queue_id7_tsa_assign;
34272 /* Strict Priority */
34273 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
34275 /* Enhanced Transmission Selection */
34276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
34279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
34282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
34285 * Priority level for strict priority. Valid only when the
34286 * tsa_assign is 0 - Strict Priority (SP)
34287 * 0..7 - Valid values.
34288 * 8..255 - Reserved.
34290 uint8_t queue_id7_pri_lvl;
34292 * Weight used to allocate remaining BW for this COS after
34293 * servicing guaranteed bandwidths for all COS.
34295 uint8_t queue_id7_bw_weight;
34296 uint8_t unused_1[5];
34299 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
34300 struct hwrm_queue_cos2bw_cfg_output {
34301 /* The specific error status for the command. */
34302 uint16_t error_code;
34303 /* The HWRM command request type. */
34305 /* The sequence ID from the original command. */
34307 /* The length of the response data in number of bytes. */
34309 uint8_t unused_0[7];
34311 * This field is used in Output records to indicate that the output
34312 * is completely written to RAM. This field should be read as '1'
34313 * to indicate that the output has been completely written.
34314 * When writing a command completion or response to an internal processor,
34315 * the order of writes has to be such that this field is written last.
34320 /*************************
34321 * hwrm_queue_dscp_qcaps *
34322 *************************/
34325 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
34326 struct hwrm_queue_dscp_qcaps_input {
34327 /* The HWRM command request type. */
34330 * The completion ring to send the completion event on. This should
34331 * be the NQ ID returned from the `nq_alloc` HWRM command.
34333 uint16_t cmpl_ring;
34335 * The sequence ID is used by the driver for tracking multiple
34336 * commands. This ID is treated as opaque data by the firmware and
34337 * the value is returned in the `hwrm_resp_hdr` upon completion.
34341 * The target ID of the command:
34342 * * 0x0-0xFFF8 - The function ID
34343 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34344 * * 0xFFFD - Reserved for user-space HWRM interface
34347 uint16_t target_id;
34349 * A physical address pointer pointing to a host buffer that the
34350 * command's response data will be written. This can be either a host
34351 * physical address (HPA) or a guest physical address (GPA) and must
34352 * point to a physically contiguous block of memory.
34354 uint64_t resp_addr;
34356 * Port ID of port for which the table is being configured.
34357 * The HWRM needs to check whether this function is allowed
34358 * to configure pri2cos mapping on this port.
34361 uint8_t unused_0[7];
34364 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
34365 struct hwrm_queue_dscp_qcaps_output {
34366 /* The specific error status for the command. */
34367 uint16_t error_code;
34368 /* The HWRM command request type. */
34370 /* The sequence ID from the original command. */
34372 /* The length of the response data in number of bytes. */
34374 /* The number of bits provided by the hardware for the DSCP value. */
34375 uint8_t num_dscp_bits;
34377 /* Max number of DSCP-MASK-PRI entries supported. */
34378 uint16_t max_entries;
34379 uint8_t unused_1[3];
34381 * This field is used in Output records to indicate that the output
34382 * is completely written to RAM. This field should be read as '1'
34383 * to indicate that the output has been completely written.
34384 * When writing a command completion or response to an internal processor,
34385 * the order of writes has to be such that this field is written last.
34390 /****************************
34391 * hwrm_queue_dscp2pri_qcfg *
34392 ****************************/
34395 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
34396 struct hwrm_queue_dscp2pri_qcfg_input {
34397 /* The HWRM command request type. */
34400 * The completion ring to send the completion event on. This should
34401 * be the NQ ID returned from the `nq_alloc` HWRM command.
34403 uint16_t cmpl_ring;
34405 * The sequence ID is used by the driver for tracking multiple
34406 * commands. This ID is treated as opaque data by the firmware and
34407 * the value is returned in the `hwrm_resp_hdr` upon completion.
34411 * The target ID of the command:
34412 * * 0x0-0xFFF8 - The function ID
34413 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34414 * * 0xFFFD - Reserved for user-space HWRM interface
34417 uint16_t target_id;
34419 * A physical address pointer pointing to a host buffer that the
34420 * command's response data will be written. This can be either a host
34421 * physical address (HPA) or a guest physical address (GPA) and must
34422 * point to a physically contiguous block of memory.
34424 uint64_t resp_addr;
34426 * This is the host address where the 24-bits DSCP-MASK-PRI
34427 * tuple(s) will be copied to.
34429 uint64_t dest_data_addr;
34431 * Port ID of port for which the table is being configured.
34432 * The HWRM needs to check whether this function is allowed
34433 * to configure pri2cos mapping on this port.
34437 /* Size of the buffer pointed to by dest_data_addr. */
34438 uint16_t dest_data_buffer_size;
34439 uint8_t unused_1[4];
34442 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
34443 struct hwrm_queue_dscp2pri_qcfg_output {
34444 /* The specific error status for the command. */
34445 uint16_t error_code;
34446 /* The HWRM command request type. */
34448 /* The sequence ID from the original command. */
34450 /* The length of the response data in number of bytes. */
34453 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
34454 * by the dest_data_addr.
34456 uint16_t entry_cnt;
34458 * This is the default PRI which un-initialized DSCP values are
34461 uint8_t default_pri;
34462 uint8_t unused_0[4];
34464 * This field is used in Output records to indicate that the output
34465 * is completely written to RAM. This field should be read as '1'
34466 * to indicate that the output has been completely written.
34467 * When writing a command completion or response to an internal processor,
34468 * the order of writes has to be such that this field is written last.
34473 /***************************
34474 * hwrm_queue_dscp2pri_cfg *
34475 ***************************/
34478 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
34479 struct hwrm_queue_dscp2pri_cfg_input {
34480 /* The HWRM command request type. */
34483 * The completion ring to send the completion event on. This should
34484 * be the NQ ID returned from the `nq_alloc` HWRM command.
34486 uint16_t cmpl_ring;
34488 * The sequence ID is used by the driver for tracking multiple
34489 * commands. This ID is treated as opaque data by the firmware and
34490 * the value is returned in the `hwrm_resp_hdr` upon completion.
34494 * The target ID of the command:
34495 * * 0x0-0xFFF8 - The function ID
34496 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34497 * * 0xFFFD - Reserved for user-space HWRM interface
34500 uint16_t target_id;
34502 * A physical address pointer pointing to a host buffer that the
34503 * command's response data will be written. This can be either a host
34504 * physical address (HPA) or a guest physical address (GPA) and must
34505 * point to a physically contiguous block of memory.
34507 uint64_t resp_addr;
34509 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
34510 * will be copied from. A non-zero mask "adds" a tuple, while
34511 * a mask equal to 0 triggers the firmware to remove a tuple.
34512 * Only tuples with unique DSCP values are stored. On chips
34513 * prior to Thor a mask can be 0 - 0x3f, while on Thor it can
34516 uint64_t src_data_addr;
34518 /* use_hw_default_pri is 1 b */
34519 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
34523 * This bit must be '1' for the default_pri field to be
34526 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
34529 * Port ID of port for which the table is being configured.
34530 * The HWRM needs to check whether this function is allowed
34531 * to configure pri2cos mapping on this port.
34535 * This is the default PRI which un-initialized DSCP values will be
34538 uint8_t default_pri;
34540 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
34541 * to by src_data_addr.
34543 uint16_t entry_cnt;
34544 uint8_t unused_0[4];
34547 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
34548 struct hwrm_queue_dscp2pri_cfg_output {
34549 /* The specific error status for the command. */
34550 uint16_t error_code;
34551 /* The HWRM command request type. */
34553 /* The sequence ID from the original command. */
34555 /* The length of the response data in number of bytes. */
34557 uint8_t unused_0[7];
34559 * This field is used in Output records to indicate that the output
34560 * is completely written to RAM. This field should be read as '1'
34561 * to indicate that the output has been completely written.
34562 * When writing a command completion or response to an internal processor,
34563 * the order of writes has to be such that this field is written last.
34568 /*************************
34569 * hwrm_queue_mpls_qcaps *
34570 *************************/
34573 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
34574 struct hwrm_queue_mpls_qcaps_input {
34575 /* The HWRM command request type. */
34578 * The completion ring to send the completion event on. This should
34579 * be the NQ ID returned from the `nq_alloc` HWRM command.
34581 uint16_t cmpl_ring;
34583 * The sequence ID is used by the driver for tracking multiple
34584 * commands. This ID is treated as opaque data by the firmware and
34585 * the value is returned in the `hwrm_resp_hdr` upon completion.
34589 * The target ID of the command:
34590 * * 0x0-0xFFF8 - The function ID
34591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34592 * * 0xFFFD - Reserved for user-space HWRM interface
34595 uint16_t target_id;
34597 * A physical address pointer pointing to a host buffer that the
34598 * command's response data will be written. This can be either a host
34599 * physical address (HPA) or a guest physical address (GPA) and must
34600 * point to a physically contiguous block of memory.
34602 uint64_t resp_addr;
34604 * Port ID of port for which the table is being configured.
34605 * The HWRM needs to check whether this function is allowed
34606 * to configure MPLS TC(EXP) to pri mapping on this port.
34609 uint8_t unused_0[7];
34612 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
34613 struct hwrm_queue_mpls_qcaps_output {
34614 /* The specific error status for the command. */
34615 uint16_t error_code;
34616 /* The HWRM command request type. */
34618 /* The sequence ID from the original command. */
34620 /* The length of the response data in number of bytes. */
34623 * Bitmask indicating which queues can be configured by the
34624 * hwrm_queue_mplstc2pri_cfg command.
34626 * Each bit represents a specific pri where bit 0 represents
34627 * pri 0 and bit 7 represents pri 7.
34628 * # A value of 0 indicates that the pri is not configurable
34629 * by the hwrm_queue_mplstc2pri_cfg command.
34630 * # A value of 1 indicates that the pri is configurable.
34631 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
34632 * trying to configure a pri that is not configurable.
34634 uint8_t queue_mplstc2pri_cfg_allowed;
34636 * This is the default PRI which un-initialized MPLS values will be
34639 uint8_t hw_default_pri;
34640 uint8_t unused_0[5];
34642 * This field is used in Output records to indicate that the output
34643 * is completely written to RAM. This field should be read as '1'
34644 * to indicate that the output has been completely written.
34645 * When writing a command completion or response to an internal processor,
34646 * the order of writes has to be such that this field is written last.
34651 /******************************
34652 * hwrm_queue_mplstc2pri_qcfg *
34653 ******************************/
34656 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
34657 struct hwrm_queue_mplstc2pri_qcfg_input {
34658 /* The HWRM command request type. */
34661 * The completion ring to send the completion event on. This should
34662 * be the NQ ID returned from the `nq_alloc` HWRM command.
34664 uint16_t cmpl_ring;
34666 * The sequence ID is used by the driver for tracking multiple
34667 * commands. This ID is treated as opaque data by the firmware and
34668 * the value is returned in the `hwrm_resp_hdr` upon completion.
34672 * The target ID of the command:
34673 * * 0x0-0xFFF8 - The function ID
34674 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34675 * * 0xFFFD - Reserved for user-space HWRM interface
34678 uint16_t target_id;
34680 * A physical address pointer pointing to a host buffer that the
34681 * command's response data will be written. This can be either a host
34682 * physical address (HPA) or a guest physical address (GPA) and must
34683 * point to a physically contiguous block of memory.
34685 uint64_t resp_addr;
34687 * Port ID of port for which the table is being configured.
34688 * The HWRM needs to check whether this function is allowed
34689 * to configure MPLS TC(EXP) to pri mapping on this port.
34692 uint8_t unused_0[7];
34695 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
34696 struct hwrm_queue_mplstc2pri_qcfg_output {
34697 /* The specific error status for the command. */
34698 uint16_t error_code;
34699 /* The HWRM command request type. */
34701 /* The sequence ID from the original command. */
34703 /* The length of the response data in number of bytes. */
34706 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
34707 * before traffic has started.
34708 * A value of 0xff indicates that no pri is assigned to the
34711 uint8_t tc0_pri_queue_id;
34713 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
34714 * before traffic has started.
34715 * A value of 0xff indicates that no pri is assigned to the
34718 uint8_t tc1_pri_queue_id;
34720 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
34721 * before traffic has started.
34722 * A value of 0xff indicates that no pri is assigned to the
34725 uint8_t tc2_pri_queue_id;
34727 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
34728 * before traffic has started.
34729 * A value of 0xff indicates that no pri is assigned to the
34732 uint8_t tc3_pri_queue_id;
34734 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
34735 * before traffic has started.
34736 * A value of 0xff indicates that no pri is assigned to the
34739 uint8_t tc4_pri_queue_id;
34741 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
34742 * before traffic has started.
34743 * A value of 0xff indicates that no pri is assigned to the
34746 uint8_t tc5_pri_queue_id;
34748 * pri assigned to MPLS TC(EXP) 6. This value can only
34749 * be changed before traffic has started.
34750 * A value of 0xff indicates that no pri is assigned to the
34753 uint8_t tc6_pri_queue_id;
34755 * pri assigned to MPLS TC(EXP) 7. This value can only
34756 * be changed before traffic has started.
34757 * A value of 0xff indicates that no pri is assigned to the
34760 uint8_t tc7_pri_queue_id;
34761 uint8_t unused_0[7];
34763 * This field is used in Output records to indicate that the output
34764 * is completely written to RAM. This field should be read as '1'
34765 * to indicate that the output has been completely written.
34766 * When writing a command completion or response to an internal processor,
34767 * the order of writes has to be such that this field is written last.
34772 /*****************************
34773 * hwrm_queue_mplstc2pri_cfg *
34774 *****************************/
34777 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
34778 struct hwrm_queue_mplstc2pri_cfg_input {
34779 /* The HWRM command request type. */
34782 * The completion ring to send the completion event on. This should
34783 * be the NQ ID returned from the `nq_alloc` HWRM command.
34785 uint16_t cmpl_ring;
34787 * The sequence ID is used by the driver for tracking multiple
34788 * commands. This ID is treated as opaque data by the firmware and
34789 * the value is returned in the `hwrm_resp_hdr` upon completion.
34793 * The target ID of the command:
34794 * * 0x0-0xFFF8 - The function ID
34795 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34796 * * 0xFFFD - Reserved for user-space HWRM interface
34799 uint16_t target_id;
34801 * A physical address pointer pointing to a host buffer that the
34802 * command's response data will be written. This can be either a host
34803 * physical address (HPA) or a guest physical address (GPA) and must
34804 * point to a physically contiguous block of memory.
34806 uint64_t resp_addr;
34809 * This bit must be '1' for the mplstc0_pri_queue_id field to be
34812 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
34815 * This bit must be '1' for the mplstc1_pri_queue_id field to be
34818 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
34821 * This bit must be '1' for the mplstc2_pri_queue_id field to be
34824 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
34827 * This bit must be '1' for the mplstc3_pri_queue_id field to be
34830 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
34833 * This bit must be '1' for the mplstc4_pri_queue_id field to be
34836 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
34839 * This bit must be '1' for the mplstc5_pri_queue_id field to be
34842 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
34845 * This bit must be '1' for the mplstc6_pri_queue_id field to be
34848 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
34851 * This bit must be '1' for the mplstc7_pri_queue_id field to be
34854 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
34857 * Port ID of port for which the table is being configured.
34858 * The HWRM needs to check whether this function is allowed
34859 * to configure MPLS TC(EXP)to pri mapping on this port.
34862 uint8_t unused_0[3];
34864 * pri assigned to MPLS TC(EXP) 0. This value can only
34865 * be changed before traffic has started.
34867 uint8_t tc0_pri_queue_id;
34869 * pri assigned to MPLS TC(EXP) 1. This value can only
34870 * be changed before traffic has started.
34872 uint8_t tc1_pri_queue_id;
34874 * pri assigned to MPLS TC(EXP) 2 This value can only
34875 * be changed before traffic has started.
34877 uint8_t tc2_pri_queue_id;
34879 * pri assigned to MPLS TC(EXP) 3. This value can only
34880 * be changed before traffic has started.
34882 uint8_t tc3_pri_queue_id;
34884 * pri assigned to MPLS TC(EXP) 4. This value can only
34885 * be changed before traffic has started.
34887 uint8_t tc4_pri_queue_id;
34889 * pri assigned to MPLS TC(EXP) 5. This value can only
34890 * be changed before traffic has started.
34892 uint8_t tc5_pri_queue_id;
34894 * pri assigned to MPLS TC(EXP) 6. This value can only
34895 * be changed before traffic has started.
34897 uint8_t tc6_pri_queue_id;
34899 * pri assigned to MPLS TC(EXP) 7. This value can only
34900 * be changed before traffic has started.
34902 uint8_t tc7_pri_queue_id;
34905 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
34906 struct hwrm_queue_mplstc2pri_cfg_output {
34907 /* The specific error status for the command. */
34908 uint16_t error_code;
34909 /* The HWRM command request type. */
34911 /* The sequence ID from the original command. */
34913 /* The length of the response data in number of bytes. */
34915 uint8_t unused_0[7];
34917 * This field is used in Output records to indicate that the output
34918 * is completely written to RAM. This field should be read as '1'
34919 * to indicate that the output has been completely written.
34920 * When writing a command completion or response to an internal processor,
34921 * the order of writes has to be such that this field is written last.
34926 /****************************
34927 * hwrm_queue_vlanpri_qcaps *
34928 ****************************/
34931 /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
34932 struct hwrm_queue_vlanpri_qcaps_input {
34933 /* The HWRM command request type. */
34936 * The completion ring to send the completion event on. This should
34937 * be the NQ ID returned from the `nq_alloc` HWRM command.
34939 uint16_t cmpl_ring;
34941 * The sequence ID is used by the driver for tracking multiple
34942 * commands. This ID is treated as opaque data by the firmware and
34943 * the value is returned in the `hwrm_resp_hdr` upon completion.
34947 * The target ID of the command:
34948 * * 0x0-0xFFF8 - The function ID
34949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34950 * * 0xFFFD - Reserved for user-space HWRM interface
34953 uint16_t target_id;
34955 * A physical address pointer pointing to a host buffer that the
34956 * command's response data will be written. This can be either a host
34957 * physical address (HPA) or a guest physical address (GPA) and must
34958 * point to a physically contiguous block of memory.
34960 uint64_t resp_addr;
34962 * Port ID of port for which the table is being configured.
34963 * The HWRM needs to check whether this function is allowed
34964 * to configure VLAN priority to user priority mapping on this port.
34967 uint8_t unused_0[7];
34970 /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
34971 struct hwrm_queue_vlanpri_qcaps_output {
34972 /* The specific error status for the command. */
34973 uint16_t error_code;
34974 /* The HWRM command request type. */
34976 /* The sequence ID from the original command. */
34978 /* The length of the response data in number of bytes. */
34981 * This is the default user priority which all VLAN priority values
34982 * are mapped to if there is no VLAN priority to user priority mapping.
34984 uint8_t hw_default_pri;
34985 uint8_t unused_0[6];
34987 * This field is used in Output records to indicate that the output
34988 * is completely written to RAM. This field should be read as '1'
34989 * to indicate that the output has been completely written.
34990 * When writing a command completion or response to an internal processor,
34991 * the order of writes has to be such that this field is written last.
34996 /*******************************
34997 * hwrm_queue_vlanpri2pri_qcfg *
34998 *******************************/
35001 /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
35002 struct hwrm_queue_vlanpri2pri_qcfg_input {
35003 /* The HWRM command request type. */
35006 * The completion ring to send the completion event on. This should
35007 * be the NQ ID returned from the `nq_alloc` HWRM command.
35009 uint16_t cmpl_ring;
35011 * The sequence ID is used by the driver for tracking multiple
35012 * commands. This ID is treated as opaque data by the firmware and
35013 * the value is returned in the `hwrm_resp_hdr` upon completion.
35017 * The target ID of the command:
35018 * * 0x0-0xFFF8 - The function ID
35019 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35020 * * 0xFFFD - Reserved for user-space HWRM interface
35023 uint16_t target_id;
35025 * A physical address pointer pointing to a host buffer that the
35026 * command's response data will be written. This can be either a host
35027 * physical address (HPA) or a guest physical address (GPA) and must
35028 * point to a physically contiguous block of memory.
35030 uint64_t resp_addr;
35032 * Port ID of port for which the table is being configured.
35033 * The HWRM needs to check whether this function is allowed
35034 * to configure VLAN priority to user priority mapping on this port.
35037 uint8_t unused_0[7];
35040 /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
35041 struct hwrm_queue_vlanpri2pri_qcfg_output {
35042 /* The specific error status for the command. */
35043 uint16_t error_code;
35044 /* The HWRM command request type. */
35046 /* The sequence ID from the original command. */
35048 /* The length of the response data in number of bytes. */
35051 * User priority assigned to VLAN priority 0. A value of 0xff
35052 * indicates that no user priority is assigned. The default user
35053 * priority will be used.
35055 uint8_t vlanpri0_user_pri_id;
35057 * User priority assigned to VLAN priority 1. A value of 0xff
35058 * indicates that no user priority is assigned. The default user
35059 * priority will be used.
35061 uint8_t vlanpri1_user_pri_id;
35063 * User priority assigned to VLAN priority 2. A value of 0xff
35064 * indicates that no user priority is assigned. The default user
35065 * priority will be used.
35067 uint8_t vlanpri2_user_pri_id;
35069 * User priority assigned to VLAN priority 3. A value of 0xff
35070 * indicates that no user priority is assigned. The default user
35071 * priority will be used.
35073 uint8_t vlanpri3_user_pri_id;
35075 * User priority assigned to VLAN priority 4. A value of 0xff
35076 * indicates that no user priority is assigned. The default user
35077 * priority will be used.
35079 uint8_t vlanpri4_user_pri_id;
35081 * User priority assigned to VLAN priority 5. A value of 0xff
35082 * indicates that no user priority is assigned. The default user
35083 * priority will be used.
35085 uint8_t vlanpri5_user_pri_id;
35087 * User priority assigned to VLAN priority 6. A value of 0xff
35088 * indicates that no user priority is assigned. The default user
35089 * priority will be used.
35091 uint8_t vlanpri6_user_pri_id;
35093 * User priority assigned to VLAN priority 7. A value of 0xff
35094 * indicates that no user priority is assigned. The default user
35095 * priority will be used.
35097 uint8_t vlanpri7_user_pri_id;
35098 uint8_t unused_0[7];
35100 * This field is used in Output records to indicate that the output
35101 * is completely written to RAM. This field should be read as '1'
35102 * to indicate that the output has been completely written.
35103 * When writing a command completion or response to an internal processor,
35104 * the order of writes has to be such that this field is written last.
35109 /******************************
35110 * hwrm_queue_vlanpri2pri_cfg *
35111 ******************************/
35114 /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
35115 struct hwrm_queue_vlanpri2pri_cfg_input {
35116 /* The HWRM command request type. */
35119 * The completion ring to send the completion event on. This should
35120 * be the NQ ID returned from the `nq_alloc` HWRM command.
35122 uint16_t cmpl_ring;
35124 * The sequence ID is used by the driver for tracking multiple
35125 * commands. This ID is treated as opaque data by the firmware and
35126 * the value is returned in the `hwrm_resp_hdr` upon completion.
35130 * The target ID of the command:
35131 * * 0x0-0xFFF8 - The function ID
35132 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35133 * * 0xFFFD - Reserved for user-space HWRM interface
35136 uint16_t target_id;
35138 * A physical address pointer pointing to a host buffer that the
35139 * command's response data will be written. This can be either a host
35140 * physical address (HPA) or a guest physical address (GPA) and must
35141 * point to a physically contiguous block of memory.
35143 uint64_t resp_addr;
35146 * This bit must be '1' for the vlanpri0_user_pri_id field to be
35149 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
35152 * This bit must be '1' for the vlanpri1_user_pri_id field to be
35155 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
35158 * This bit must be '1' for the vlanpri2_user_pri_id field to be
35161 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
35164 * This bit must be '1' for the vlanpri3_user_pri_id field to be
35167 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
35170 * This bit must be '1' for the vlanpri4_user_pri_id field to be
35173 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
35176 * This bit must be '1' for the vlanpri5_user_pri_id field to be
35179 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
35182 * This bit must be '1' for the vlanpri6_user_pri_id field to be
35185 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
35188 * This bit must be '1' for the vlanpri7_user_pri_id field to be
35191 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
35194 * Port ID of port for which the table is being configured.
35195 * The HWRM needs to check whether this function is allowed
35196 * to configure VLAN priority to user priority mapping on this port.
35199 uint8_t unused_0[3];
35201 * User priority assigned to VLAN priority 0. This value can only
35202 * be changed before traffic has started.
35204 uint8_t vlanpri0_user_pri_id;
35206 * User priority assigned to VLAN priority 1. This value can only
35207 * be changed before traffic has started.
35209 uint8_t vlanpri1_user_pri_id;
35211 * User priority assigned to VLAN priority 2. This value can only
35212 * be changed before traffic has started.
35214 uint8_t vlanpri2_user_pri_id;
35216 * User priority assigned to VLAN priority 3. This value can only
35217 * be changed before traffic has started.
35219 uint8_t vlanpri3_user_pri_id;
35221 * User priority assigned to VLAN priority 4. This value can only
35222 * be changed before traffic has started.
35224 uint8_t vlanpri4_user_pri_id;
35226 * User priority assigned to VLAN priority 5. This value can only
35227 * be changed before traffic has started.
35229 uint8_t vlanpri5_user_pri_id;
35231 * User priority assigned to VLAN priority 6. This value can only
35232 * be changed before traffic has started.
35234 uint8_t vlanpri6_user_pri_id;
35236 * User priority assigned to VLAN priority 7. This value can only
35237 * be changed before traffic has started.
35239 uint8_t vlanpri7_user_pri_id;
35242 /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
35243 struct hwrm_queue_vlanpri2pri_cfg_output {
35244 /* The specific error status for the command. */
35245 uint16_t error_code;
35246 /* The HWRM command request type. */
35248 /* The sequence ID from the original command. */
35250 /* The length of the response data in number of bytes. */
35252 uint8_t unused_0[7];
35254 * This field is used in Output records to indicate that the output
35255 * is completely written to RAM. This field should be read as '1'
35256 * to indicate that the output has been completely written.
35257 * When writing a command completion or response to an internal processor,
35258 * the order of writes has to be such that this field is written last.
35263 /*************************
35264 * hwrm_queue_global_cfg *
35265 *************************/
35268 /* hwrm_queue_global_cfg_input (size:192b/24B) */
35269 struct hwrm_queue_global_cfg_input {
35270 /* The HWRM command request type. */
35273 * The completion ring to send the completion event on. This should
35274 * be the NQ ID returned from the `nq_alloc` HWRM command.
35276 uint16_t cmpl_ring;
35278 * The sequence ID is used by the driver for tracking multiple
35279 * commands. This ID is treated as opaque data by the firmware and
35280 * the value is returned in the `hwrm_resp_hdr` upon completion.
35284 * The target ID of the command:
35285 * * 0x0-0xFFF8 - The function ID
35286 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35287 * * 0xFFFD - Reserved for user-space HWRM interface
35290 uint16_t target_id;
35292 * A physical address pointer pointing to a host buffer that the
35293 * command's response data will be written. This can be either a host
35294 * physical address (HPA) or a guest physical address (GPA) and must
35295 * point to a physically contiguous block of memory.
35297 uint64_t resp_addr;
35299 * Configuration mode for rx cos queues, configuring whether they
35300 * use one shared buffer pool (across ports or PCIe endpoints) or
35301 * independent per port or per endpoint buffer pools.
35304 /* One shared buffer pool to be used by all RX CoS queues */
35305 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
35307 * Each port or PCIe endpoint to use an independent buffer pool
35308 * for its RX CoS queues
35310 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
35311 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \
35312 HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT
35315 /* This bit must be '1' when the mode field is configured. */
35316 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
35318 * This bit must be '1' when the maximum bandwidth for queue group 0
35319 * (g0_max_bw) is configured.
35321 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
35323 * This bit must be '1' when the maximum bandwidth for queue group 1
35324 * (g1_max_bw) is configured.
35326 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
35328 * This bit must be '1' when the maximum bandwidth for queue group 2
35329 * (g2_max_bw) is configured.
35331 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
35333 * This bit must be '1' when the maximum bandwidth for queue group 3
35334 * (g3_max_bw) is configured.
35336 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \
35339 * Specifies the maximum receive rate, as a percentage of total link
35340 * bandwidth, of the receive traffic through queue group 0. A value
35341 * of 0 indicates no rate limit.
35343 * A queue group is a set of queues, one per traffic class. In
35344 * single-host mode, each panel port has its own queue group, and thus,
35345 * this rate limit shapes the traffic received on a port, in this case,
35346 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
35347 * on the NIC has its own queue group. In these cases, the rate limit
35348 * shapes the traffic sent to the host through one of the PCIe
35349 * endpoints, in this case endpoint 0.
35353 * Specifies the maximum rate of the traffic through receive CoS queue
35354 * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of
35355 * total link bandwidth (the sum of the bandwidths of all links). A
35356 * value of 0 indicates no rate limit.
35360 * Specifies the maximum rate of the traffic through receive CoS queue
35361 * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of
35362 * total link bandwidth (the sum of the bandwidths of all links). A
35363 * value of 0 indicates no rate limit.
35367 * Specifies the maximum receive rate, in Mbps, of the receive traffic
35368 * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
35369 * indicates no rate limit.
35374 /* hwrm_queue_global_cfg_output (size:128b/16B) */
35375 struct hwrm_queue_global_cfg_output {
35376 /* The specific error status for the command. */
35377 uint16_t error_code;
35378 /* The HWRM command request type. */
35380 /* The sequence ID from the original command. */
35382 /* The length of the response data in number of bytes. */
35384 uint8_t unused_0[7];
35386 * This field is used in Output records to indicate that the output
35387 * is completely written to RAM. This field should be read as '1'
35388 * to indicate that the output has been completely written.
35389 * When writing a command completion or response to an internal processor,
35390 * the order of writes has to be such that this field is written last.
35395 /**************************
35396 * hwrm_queue_global_qcfg *
35397 **************************/
35400 /* hwrm_queue_global_qcfg_input (size:128b/16B) */
35401 struct hwrm_queue_global_qcfg_input {
35402 /* The HWRM command request type. */
35405 * The completion ring to send the completion event on. This should
35406 * be the NQ ID returned from the `nq_alloc` HWRM command.
35408 uint16_t cmpl_ring;
35410 * The sequence ID is used by the driver for tracking multiple
35411 * commands. This ID is treated as opaque data by the firmware and
35412 * the value is returned in the `hwrm_resp_hdr` upon completion.
35416 * The target ID of the command:
35417 * * 0x0-0xFFF8 - The function ID
35418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35419 * * 0xFFFD - Reserved for user-space HWRM interface
35422 uint16_t target_id;
35424 * A physical address pointer pointing to a host buffer that the
35425 * command's response data will be written. This can be either a host
35426 * physical address (HPA) or a guest physical address (GPA) and must
35427 * point to a physically contiguous block of memory.
35429 uint64_t resp_addr;
35432 /* hwrm_queue_global_qcfg_output (size:320b/40B) */
35433 struct hwrm_queue_global_qcfg_output {
35434 /* The specific error status for the command. */
35435 uint16_t error_code;
35436 /* The HWRM command request type. */
35438 /* The sequence ID from the original command. */
35440 /* The length of the response data in number of bytes. */
35442 /* Port or PCIe endpoint id to be mapped for buffer pool 0. */
35443 uint8_t buffer_pool_id0_map;
35444 /* Port or PCIe endpoint id to be mapped for buffer pool 1. */
35445 uint8_t buffer_pool_id1_map;
35446 /* Port or PCIe endpoint id to be mapped for buffer pool 2. */
35447 uint8_t buffer_pool_id2_map;
35448 /* Port or PCIe endpoint id to be mapped for buffer pool 3. */
35449 uint8_t buffer_pool_id3_map;
35450 /* Size of buffer pool 0 (KBytes). */
35451 uint32_t buffer_pool_id0_size;
35452 /* Size of buffer pool 1 (KBytes). */
35453 uint32_t buffer_pool_id1_size;
35454 /* Size of buffer pool 2 (KBytes). */
35455 uint32_t buffer_pool_id2_size;
35456 /* Size of buffer pool 3 (KBytes). */
35457 uint32_t buffer_pool_id3_size;
35460 * Enumeration denoting whether the rx buffer pool mapping is
35461 * per port or per PCIe endpoint
35463 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \
35466 * The buffer_pool_id[0-3]_map field represents mapping of rx
35467 * buffer pools to a port.
35469 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \
35472 * The buffer_pool_id[0-3]_map field represents mapping of rx
35473 * buffer pools to a PCIe endpoint.
35475 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \
35477 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \
35478 HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT
35480 * Configuration mode for rx cos queues, configuring whether they
35481 * use one shared buffer pool (across ports or PCIe endpoints) or
35482 * independent per port or per endpoint buffer pools.
35485 /* One shared buffer pool to be used by all RX CoS queues */
35486 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
35488 * Each port or PCIe endpoint to use an independent buffer pool
35489 * for its RX CoS queues
35491 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
35492 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \
35493 HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT
35496 * Reports the rate limit applied to traffic through receive CoS queue
35497 * group 0. The rate limit is a percentage of total link bandwidth. A
35498 * value of 0 indicates no rate limit.
35500 * A queue group is a set of queues, one per traffic class. In
35501 * single-host mode, each panel port has its own queue group, and thus,
35502 * this rate limit shapes the traffic received on a port, in this case,
35503 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
35504 * on the NIC has its own queue group. In these cases, the rate limit
35505 * shapes the traffic sent to the host through one of the PCIe
35506 * endpoints, in this case endpoint 0.
35510 * Reports the rate limit applied to traffic through receive CoS queue
35511 * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a
35512 * percentage of total link bandwidth. A value of 0 indicates no rate
35517 * Reports the rate limit applied to traffic through receive CoS queue
35518 * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a
35519 * percentage of total link bandwidth. A value of 0 indicates no rate
35524 * Reports the rate limit applied to traffic through receive CoS queue
35525 * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a
35526 * percentage of total link bandwidth. A value of 0 indicates no rate
35530 uint8_t unused_1[3];
35532 * This field is used in Output records to indicate that the output
35533 * is completely written to RAM. This field should be read as '1'
35534 * to indicate that the output has been completely written.
35535 * When writing a command completion or response to an internal processor,
35536 * the order of writes has to be such that this field is written last.
35541 /*******************
35542 * hwrm_vnic_alloc *
35543 *******************/
35546 /* hwrm_vnic_alloc_input (size:192b/24B) */
35547 struct hwrm_vnic_alloc_input {
35548 /* The HWRM command request type. */
35551 * The completion ring to send the completion event on. This should
35552 * be the NQ ID returned from the `nq_alloc` HWRM command.
35554 uint16_t cmpl_ring;
35556 * The sequence ID is used by the driver for tracking multiple
35557 * commands. This ID is treated as opaque data by the firmware and
35558 * the value is returned in the `hwrm_resp_hdr` upon completion.
35562 * The target ID of the command:
35563 * * 0x0-0xFFF8 - The function ID
35564 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35565 * * 0xFFFD - Reserved for user-space HWRM interface
35568 uint16_t target_id;
35570 * A physical address pointer pointing to a host buffer that the
35571 * command's response data will be written. This can be either a host
35572 * physical address (HPA) or a guest physical address (GPA) and must
35573 * point to a physically contiguous block of memory.
35575 uint64_t resp_addr;
35578 * When this bit is '1', this VNIC is requested to
35579 * be the default VNIC for this function.
35581 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
35584 * When this bit is '1', proxy VEE PF is requesting
35585 * allocation of a default VNIC on behalf of virtio-net
35586 * function given in virtio_net_fid field.
35588 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
35591 * Virtio-net function's FID.
35592 * This virtio-net function is requesting allocation of default
35593 * VNIC through proxy VEE PF.
35595 uint16_t virtio_net_fid;
35596 uint8_t unused_0[2];
35599 /* hwrm_vnic_alloc_output (size:128b/16B) */
35600 struct hwrm_vnic_alloc_output {
35601 /* The specific error status for the command. */
35602 uint16_t error_code;
35603 /* The HWRM command request type. */
35605 /* The sequence ID from the original command. */
35607 /* The length of the response data in number of bytes. */
35609 /* Logical vnic ID */
35611 uint8_t unused_0[3];
35613 * This field is used in Output records to indicate that the output
35614 * is completely written to RAM. This field should be read as '1'
35615 * to indicate that the output has been completely written.
35616 * When writing a command completion or response to an internal processor,
35617 * the order of writes has to be such that this field is written last.
35622 /********************
35623 * hwrm_vnic_update *
35624 ********************/
35627 /* hwrm_vnic_update_input (size:256b/32B) */
35628 struct hwrm_vnic_update_input {
35629 /* The HWRM command request type. */
35632 * The completion ring to send the completion event on. This should
35633 * be the NQ ID returned from the `nq_alloc` HWRM command.
35635 uint16_t cmpl_ring;
35637 * The sequence ID is used by the driver for tracking multiple
35638 * commands. This ID is treated as opaque data by the firmware and
35639 * the value is returned in the `hwrm_resp_hdr` upon completion.
35643 * The target ID of the command:
35644 * * 0x0-0xFFF8 - The function ID
35645 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35646 * * 0xFFFD - Reserved for user-space HWRM interface
35649 uint16_t target_id;
35651 * A physical address pointer pointing to a host buffer that the
35652 * command's response data will be written. This can be either a host
35653 * physical address (HPA) or a guest physical address (GPA) and must
35654 * point to a physically contiguous block of memory.
35656 uint64_t resp_addr;
35657 /* Logical vnic ID */
35661 * This bit must be '1' for the vnic_state field to be
35664 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
35667 * This bit must be '1' for the mru field to be
35670 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
35673 * This bit must be '1' for the metadata_format_type field to be
35676 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
35679 * This will update the context variable with the same name if
35680 * the corresponding enable is set.
35682 uint8_t vnic_state;
35683 /* Normal operation state for the VNIC. */
35684 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
35685 /* All packets are dropped in this state. */
35686 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
35687 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
35688 HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
35690 * The metadata format type used in all the RX packet completions
35691 * going through this VNIC.
35693 uint8_t metadata_format_type;
35694 /* No metadata information. */
35695 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
35698 * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
35701 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
35703 /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
35704 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
35706 /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
35707 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
35709 /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
35710 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
35712 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
35713 HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
35715 * The maximum receive unit of the vnic.
35716 * Each vnic is associated with a function.
35717 * The vnic mru value overwrites the mru setting of the
35718 * associated function.
35719 * The HWRM shall make sure that vnic mru does not exceed
35720 * the mru of the port the function is associated with.
35723 uint8_t unused_1[4];
35726 /* hwrm_vnic_update_output (size:128b/16B) */
35727 struct hwrm_vnic_update_output {
35728 /* The specific error status for the command. */
35729 uint16_t error_code;
35730 /* The HWRM command request type. */
35732 /* The sequence ID from the original command. */
35734 /* The length of the response data in number of bytes. */
35736 uint8_t unused_0[7];
35738 * This field is used in Output records to indicate that the output
35739 * is completely written to RAM. This field should be read as '1'
35740 * to indicate that the output has been completely written.
35741 * When writing a command completion or response to an internal
35742 * processor, the order of writes has to be such that this field is
35748 /******************
35750 ******************/
35753 /* hwrm_vnic_free_input (size:192b/24B) */
35754 struct hwrm_vnic_free_input {
35755 /* The HWRM command request type. */
35758 * The completion ring to send the completion event on. This should
35759 * be the NQ ID returned from the `nq_alloc` HWRM command.
35761 uint16_t cmpl_ring;
35763 * The sequence ID is used by the driver for tracking multiple
35764 * commands. This ID is treated as opaque data by the firmware and
35765 * the value is returned in the `hwrm_resp_hdr` upon completion.
35769 * The target ID of the command:
35770 * * 0x0-0xFFF8 - The function ID
35771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35772 * * 0xFFFD - Reserved for user-space HWRM interface
35775 uint16_t target_id;
35777 * A physical address pointer pointing to a host buffer that the
35778 * command's response data will be written. This can be either a host
35779 * physical address (HPA) or a guest physical address (GPA) and must
35780 * point to a physically contiguous block of memory.
35782 uint64_t resp_addr;
35783 /* Logical vnic ID */
35785 uint8_t unused_0[4];
35788 /* hwrm_vnic_free_output (size:128b/16B) */
35789 struct hwrm_vnic_free_output {
35790 /* The specific error status for the command. */
35791 uint16_t error_code;
35792 /* The HWRM command request type. */
35794 /* The sequence ID from the original command. */
35796 /* The length of the response data in number of bytes. */
35798 uint8_t unused_0[7];
35800 * This field is used in Output records to indicate that the output
35801 * is completely written to RAM. This field should be read as '1'
35802 * to indicate that the output has been completely written.
35803 * When writing a command completion or response to an internal processor,
35804 * the order of writes has to be such that this field is written last.
35814 /* hwrm_vnic_cfg_input (size:384b/48B) */
35815 struct hwrm_vnic_cfg_input {
35816 /* The HWRM command request type. */
35819 * The completion ring to send the completion event on. This should
35820 * be the NQ ID returned from the `nq_alloc` HWRM command.
35822 uint16_t cmpl_ring;
35824 * The sequence ID is used by the driver for tracking multiple
35825 * commands. This ID is treated as opaque data by the firmware and
35826 * the value is returned in the `hwrm_resp_hdr` upon completion.
35830 * The target ID of the command:
35831 * * 0x0-0xFFF8 - The function ID
35832 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35833 * * 0xFFFD - Reserved for user-space HWRM interface
35836 uint16_t target_id;
35838 * A physical address pointer pointing to a host buffer that the
35839 * command's response data will be written. This can be either a host
35840 * physical address (HPA) or a guest physical address (GPA) and must
35841 * point to a physically contiguous block of memory.
35843 uint64_t resp_addr;
35846 * When this bit is '1', the VNIC is requested to
35847 * be the default VNIC for the function.
35849 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
35852 * When this bit is '1', the VNIC is being configured to
35853 * strip VLAN in the RX path.
35854 * If set to '0', then VLAN stripping is disabled on
35857 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
35860 * When this bit is '1', the VNIC is being configured to
35861 * buffer receive packets in the hardware until the host
35862 * posts new receive buffers.
35863 * If set to '0', then bd_stall is being configured to be
35864 * disabled on this VNIC.
35866 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
35869 * When this bit is '1', the VNIC is being configured to
35870 * receive both RoCE and non-RoCE traffic.
35871 * If set to '0', then this VNIC is not configured to be
35872 * operating in dual VNIC mode.
35874 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
35877 * When this flag is set to '1', the VNIC is requested to
35878 * be configured to receive only RoCE traffic.
35879 * If this flag is set to '0', then this flag shall be
35880 * ignored by the HWRM.
35881 * If roce_dual_vnic_mode flag is set to '1'
35882 * or roce_mirroring_capable_vnic_mode flag to 1,
35883 * then the HWRM client shall not set this flag to '1'.
35885 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
35888 * When a VNIC uses one destination ring group for certain
35889 * application (e.g. Receive Flow Steering) where
35890 * exact match is used to direct packets to a VNIC with one
35891 * destination ring group only, there is no need to configure
35892 * RSS indirection table for that VNIC as only one destination
35893 * ring group is used.
35895 * This flag is used to enable a mode where
35896 * RSS is enabled in the VNIC using a RSS context
35897 * for computing RSS hash but the RSS indirection table is
35898 * not configured using hwrm_vnic_rss_cfg.
35900 * If this mode is enabled, then the driver should not program
35901 * RSS indirection table for the RSS context that is used for
35902 * computing RSS hash only.
35904 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
35907 * When this bit is '1', the VNIC is being configured to
35908 * receive both RoCE and non-RoCE traffic, but forward only the
35909 * RoCE traffic further. Also, RoCE traffic can be mirrored to
35912 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
35916 * This bit must be '1' for the dflt_ring_grp field to be
35919 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
35922 * This bit must be '1' for the rss_rule field to be
35925 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
35928 * This bit must be '1' for the cos_rule field to be
35931 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
35934 * This bit must be '1' for the lb_rule field to be
35937 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
35940 * This bit must be '1' for the mru field to be
35943 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
35946 * This bit must be '1' for the default_rx_ring_id field to be
35949 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
35952 * This bit must be '1' for the default_cmpl_ring_id field to be
35955 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
35957 /* This bit must be '1' for the queue_id field to be configured. */
35958 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
35960 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
35961 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
35963 /* This bit must be '1' for the l2_cqe_mode field to be configured. */
35964 #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE \
35966 /* Logical vnic ID */
35969 * Default Completion ring for the VNIC. This ring will
35970 * be chosen if packet does not match any RSS rules and if
35971 * there is no COS rule.
35973 uint16_t dflt_ring_grp;
35975 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
35976 * there is no RSS rule.
35980 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
35981 * there is no COS rule.
35985 * RSS ID for load balancing rule/table structure.
35986 * 0xFF... (All Fs) if there is no LB rule.
35990 * The maximum receive unit of the vnic.
35991 * Each vnic is associated with a function.
35992 * The vnic mru value overwrites the mru setting of the
35993 * associated function.
35994 * The HWRM shall make sure that vnic mru does not exceed
35995 * the mru of the port the function is associated with.
35999 * Default Rx ring for the VNIC. This ring will
36000 * be chosen if packet does not match any RSS rules.
36001 * The aggregation ring associated with the Rx ring is
36002 * implied based on the Rx ring specified when the
36003 * aggregation ring was allocated.
36005 uint16_t default_rx_ring_id;
36007 * Default completion ring for the VNIC. This ring will
36008 * be chosen if packet does not match any RSS rules.
36010 uint16_t default_cmpl_ring_id;
36012 * When specified, only incoming packets classified to the specified CoS
36013 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
36014 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
36015 * ntuple filters with VNIC destination specified are invalid since they
36016 * conflict with the CoS to VNIC steering rules in this mode.
36018 * If this field is not specified, packet to VNIC steering will be
36019 * subject to the standard L2 filter rules and any additional ntuple
36020 * filter rules with destination VNIC specified.
36024 * If the device supports the RX V2 and RX TPA start V2 completion
36025 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
36026 * used to specify the two RX checksum modes supported by these
36027 * completion records.
36029 uint8_t rx_csum_v2_mode;
36031 * When configured with this checksum mode, the number of header
36032 * groups in the delivered packet with a valid IP checksum and
36033 * the number of header groups in the delivered packet with a valid
36034 * L4 checksum are reported. Valid checksums are counted from the
36035 * outermost header group to the innermost header group, stopping at
36036 * the first error. This is the default checksum mode supported if
36037 * the driver doesn't explicitly configure the RX checksum mode.
36039 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
36041 * When configured with this checksum mode, the checksum status is
36042 * reported using 'all ok' mode. In the RX completion record, one
36043 * bit indicates if the IP checksum is valid for all the parsed
36044 * header groups with an IP checksum. Another bit indicates if the
36045 * L4 checksum is valid for all the parsed header groups with an L4
36046 * checksum. The number of header groups that were parsed by the
36047 * chip and passed in the delivered packet is also reported.
36049 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
36051 * Any rx_csum_v2_mode value larger than or equal to this is not
36054 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
36055 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
36056 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
36058 * If the device supports different L2 RX CQE modes, as indicated by
36059 * the HWRM_VNIC_QCAPS command, this field is used to configure the
36062 uint8_t l2_cqe_mode;
36064 * When configured with this cqe mode, A normal (32B) CQE
36065 * will be generated. This is the default mode.
36067 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
36069 * When configured with this cqe mode, A compressed (16B) CQE
36070 * will be generated. In this mode TPA and HDS are not supported.
36071 * Host drivers should not configure the TPA and HDS along with
36072 * compressed mode, per VNIC. FW returns error, if host drivers
36073 * try to configure the VNIC with compressed mode and (TPA or HDS).
36074 * The compressed completion does not include PTP data. Host
36075 * drivers should not use this mode to receive the PTP data.
36077 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
36079 * When configured with this cqe mode, HW generates either a 32B
36080 * completion or a 16B completion depending on use case within a
36081 * VNIC. For ex. a simple L2 packet could use the compressed form
36082 * while a PTP packet on the same VNIC would use the 32B form.
36084 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
36085 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST \
36086 HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED
36087 uint8_t unused0[4];
36090 /* hwrm_vnic_cfg_output (size:128b/16B) */
36091 struct hwrm_vnic_cfg_output {
36092 /* The specific error status for the command. */
36093 uint16_t error_code;
36094 /* The HWRM command request type. */
36096 /* The sequence ID from the original command. */
36098 /* The length of the response data in number of bytes. */
36100 uint8_t unused_0[7];
36102 * This field is used in Output records to indicate that the output
36103 * is completely written to RAM. This field should be read as '1'
36104 * to indicate that the output has been completely written.
36105 * When writing a command completion or response to an internal processor,
36106 * the order of writes has to be such that this field is written last.
36111 /******************
36113 ******************/
36116 /* hwrm_vnic_qcfg_input (size:256b/32B) */
36117 struct hwrm_vnic_qcfg_input {
36118 /* The HWRM command request type. */
36121 * The completion ring to send the completion event on. This should
36122 * be the NQ ID returned from the `nq_alloc` HWRM command.
36124 uint16_t cmpl_ring;
36126 * The sequence ID is used by the driver for tracking multiple
36127 * commands. This ID is treated as opaque data by the firmware and
36128 * the value is returned in the `hwrm_resp_hdr` upon completion.
36132 * The target ID of the command:
36133 * * 0x0-0xFFF8 - The function ID
36134 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36135 * * 0xFFFD - Reserved for user-space HWRM interface
36138 uint16_t target_id;
36140 * A physical address pointer pointing to a host buffer that the
36141 * command's response data will be written. This can be either a host
36142 * physical address (HPA) or a guest physical address (GPA) and must
36143 * point to a physically contiguous block of memory.
36145 uint64_t resp_addr;
36148 * This bit must be '1' for the vf_id_valid field to be
36151 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
36152 /* Logical vnic ID */
36154 /* ID of Virtual Function whose VNIC resource is being queried. */
36156 uint8_t unused_0[6];
36159 /* hwrm_vnic_qcfg_output (size:256b/32B) */
36160 struct hwrm_vnic_qcfg_output {
36161 /* The specific error status for the command. */
36162 uint16_t error_code;
36163 /* The HWRM command request type. */
36165 /* The sequence ID from the original command. */
36167 /* The length of the response data in number of bytes. */
36169 /* Default Completion ring for the VNIC. */
36170 uint16_t dflt_ring_grp;
36172 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
36173 * there is no RSS rule.
36177 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
36178 * there is no COS rule.
36182 * RSS ID for load balancing rule/table structure.
36183 * 0xFF... (All Fs) if there is no LB rule.
36186 /* The maximum receive unit of the vnic. */
36188 uint8_t unused_0[2];
36191 * When this bit is '1', the VNIC is the default VNIC for
36194 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
36197 * When this bit is '1', the VNIC is configured to
36198 * strip VLAN in the RX path.
36199 * If set to '0', then VLAN stripping is disabled on
36202 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
36205 * When this bit is '1', the VNIC is configured to
36206 * buffer receive packets in the hardware until the host
36207 * posts new receive buffers.
36208 * If set to '0', then bd_stall is disabled on
36211 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
36214 * When this bit is '1', the VNIC is configured to
36215 * receive both RoCE and non-RoCE traffic.
36216 * If set to '0', then this VNIC is not configured to
36217 * operate in dual VNIC mode.
36219 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
36222 * When this flag is set to '1', the VNIC is configured to
36223 * receive only RoCE traffic.
36224 * When this flag is set to '0', the VNIC is not configured
36225 * to receive only RoCE traffic.
36226 * If roce_dual_vnic_mode flag and this flag both are set
36227 * to '1', then it is an invalid configuration of the
36228 * VNIC. The HWRM should not allow that type of
36229 * mis-configuration by HWRM clients.
36231 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
36234 * When a VNIC uses one destination ring group for certain
36235 * application (e.g. Receive Flow Steering) where
36236 * exact match is used to direct packets to a VNIC with one
36237 * destination ring group only, there is no need to configure
36238 * RSS indirection table for that VNIC as only one destination
36239 * ring group is used.
36241 * When this bit is set to '1', then the VNIC is enabled in a
36242 * mode where RSS is enabled in the VNIC using a RSS context
36243 * for computing RSS hash but the RSS indirection table is
36246 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
36249 * When this bit is '1', the VNIC is configured to
36250 * receive both RoCE and non-RoCE traffic, but forward only
36251 * RoCE traffic further. Also RoCE traffic can be mirrored to
36254 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
36257 * When this bit is '0', VNIC is in normal operation state.
36258 * When this bit is '1', VNIC drops all the received packets.
36260 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
36263 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
36264 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
36265 * queue association.
36269 * If the device supports the RX V2 and RX TPA start V2 completion
36270 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
36271 * used to specify the current RX checksum mode configured for all the
36272 * RX rings of a VNIC.
36274 uint8_t rx_csum_v2_mode;
36276 * This value indicates that the VNIC is configured to use the
36277 * default RX checksum mode for all the rings associated with this
36280 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
36282 * This value indicates that the VNIC is configured to use the RX
36283 * checksum ‘all_ok’ mode for all the rings associated with this
36286 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
36288 * Any rx_csum_v2_mode value larger than or equal to this is not
36291 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
36292 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
36293 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
36295 * If the device supports different L2 RX CQE modes, as indicated by
36296 * the HWRM_VNIC_QCAPS command, this field is used to convey the
36297 * configured CQE mode.
36299 uint8_t l2_cqe_mode;
36301 * This value indicates that the VNIC is configured with normal
36304 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
36306 * This value indicates that the VNIC is configured with compressed
36309 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
36311 * This value indicates that the VNIC is configured with mixed
36312 * CQE mode. HW generates either a 32B completion or a 16B
36313 * completion depending on use case within a VNIC.
36315 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
36316 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \
36317 HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED
36318 uint8_t unused_1[3];
36320 * This field is used in Output records to indicate that the output
36321 * is completely written to RAM. This field should be read as '1'
36322 * to indicate that the output has been completely written.
36323 * When writing a command completion or response to an internal processor,
36324 * the order of writes has to be such that this field is written last.
36329 /*******************
36330 * hwrm_vnic_qcaps *
36331 *******************/
36334 /* hwrm_vnic_qcaps_input (size:192b/24B) */
36335 struct hwrm_vnic_qcaps_input {
36336 /* The HWRM command request type. */
36339 * The completion ring to send the completion event on. This should
36340 * be the NQ ID returned from the `nq_alloc` HWRM command.
36342 uint16_t cmpl_ring;
36344 * The sequence ID is used by the driver for tracking multiple
36345 * commands. This ID is treated as opaque data by the firmware and
36346 * the value is returned in the `hwrm_resp_hdr` upon completion.
36350 * The target ID of the command:
36351 * * 0x0-0xFFF8 - The function ID
36352 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36353 * * 0xFFFD - Reserved for user-space HWRM interface
36356 uint16_t target_id;
36358 * A physical address pointer pointing to a host buffer that the
36359 * command's response data will be written. This can be either a host
36360 * physical address (HPA) or a guest physical address (GPA) and must
36361 * point to a physically contiguous block of memory.
36363 uint64_t resp_addr;
36365 uint8_t unused_0[4];
36368 /* hwrm_vnic_qcaps_output (size:192b/24B) */
36369 struct hwrm_vnic_qcaps_output {
36370 /* The specific error status for the command. */
36371 uint16_t error_code;
36372 /* The HWRM command request type. */
36374 /* The sequence ID from the original command. */
36376 /* The length of the response data in number of bytes. */
36378 /* The maximum receive unit that is settable on a vnic. */
36380 uint8_t unused_0[2];
36383 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
36386 * When this bit is '1', the capability of stripping VLAN in
36387 * the RX path is supported on VNIC(s).
36388 * If set to '0', then VLAN stripping capability is
36389 * not supported on VNIC(s).
36391 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
36394 * When this bit is '1', the capability to buffer receive
36395 * packets in the hardware until the host posts new receive buffers
36396 * is supported on VNIC(s).
36397 * If set to '0', then bd_stall capability is not supported
36400 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
36403 * When this bit is '1', the capability to
36404 * receive both RoCE and non-RoCE traffic on VNIC(s) is
36406 * If set to '0', then the capability to receive
36407 * both RoCE and non-RoCE traffic on VNIC(s) is
36410 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
36413 * When this bit is set to '1', the capability to configure
36414 * a VNIC to receive only RoCE traffic is supported.
36415 * When this flag is set to '0', the VNIC capability to
36416 * configure to receive only RoCE traffic is not supported.
36418 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
36421 * When this bit is set to '1', then the capability to enable
36422 * a VNIC in a mode where RSS context without configuring
36423 * RSS indirection table is supported (for RSS hash computation).
36424 * When this bit is set to '0', then a VNIC can not be configured
36425 * with a mode to enable RSS context without configuring RSS
36426 * indirection table.
36428 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
36431 * When this bit is '1', the capability to
36432 * mirror the RoCE traffic is supported.
36433 * If set to '0', then the capability to mirror the
36434 * RoCE traffic is not supported.
36436 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
36439 * When this bit is '1', the outermost RSS hashing capability
36440 * is supported. If set to '0', then the outermost RSS hashing
36441 * capability is not supported.
36443 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
36446 * When this bit is '1', it indicates that firmware supports the
36447 * ability to steer incoming packets from one CoS queue to one
36448 * VNIC. This optional feature can then be enabled
36449 * using HWRM_VNIC_CFG on any VNIC. This feature is only
36450 * available when NVM option “enable_cos_classification” is set
36451 * to 1. If set to '0', firmware does not support this feature.
36453 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
36456 * When this bit is '1', it indicates that HW and firmware supports
36457 * the use of RX V2 and RX TPA start V2 completion records for all
36458 * the RX rings of a VNIC. Once set, this feature is mandatory to
36459 * be used for the RX rings of the VNIC. Additionally, two new RX
36460 * checksum features supported by these completion records can be
36461 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
36462 * HW and the firmware does not support this feature.
36464 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
36467 * When this bit is '1', it indicates that HW and firmware support
36468 * vnic state change. Host drivers can change the vnic state using
36469 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
36470 * support this feature.
36472 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
36475 * When this bit is '1', it indicates that firmware supports
36476 * virtio-net functions default VNIC allocation using
36478 * This capability is available only on Proxy VEE PF. If set to '0',
36479 * firmware does not support this feature.
36481 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
36484 * When this bit is set '1', then the capability to configure the
36485 * metadata format in the RX completion is supported for the VNIC.
36486 * When this bit is set to '0', then the capability to configure
36487 * the metadata format in the RX completion is not supported for
36490 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
36493 * When this bit is set '1', it indicates that firmware returns
36494 * INVALID_PARAM error, if host drivers choose invalid hash type
36495 * bit combinations in vnic_rss_cfg.
36497 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \
36500 * When this bit is set '1', it indicates that firmware supports
36501 * the hash_type include and exclude flags in hwrm_vnic_rss_cfg.
36503 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \
36506 * When this bit is '1', it indicates that HW is capable of using
36507 * Toeplitz algorithm. This mode uses Toeplitz algorithm and
36508 * provided Toeplitz hash key to hash the packets according to the
36509 * configured hash type and hash mode. The Toeplitz hash results and
36510 * the provided Toeplitz RSS indirection table are used to determine
36513 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP \
36516 * When this bit is '1', it indicates that HW is capable of using
36517 * XOR algorithm. This mode uses XOR algorithm to hash the packets
36518 * according to the configured hash type and hash mode. The XOR
36519 * hash results and the provided XOR RSS indirection table are
36520 * used to determine the RSS rings. Host drivers provided hash key
36521 * is not honored in this mode.
36523 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP \
36526 * When this bit is '1', it indicates that HW is capable of using
36527 * checksum algorithm. In this mode, HW uses inner packets checksum
36528 * algorithm to distribute the packets across the rings and Toeplitz
36529 * algorithm to calculate the hash to convey it in the RX
36530 * completions. Host drivers should provide Toeplitz hash key.
36531 * As HW uses innermost packets checksum to distribute the packets
36532 * across the rings, host drivers can't convey hash mode to choose
36533 * outer headers to calculate Toeplitz hash. FW will fail such
36536 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP \
36539 * When this bit is '1' HW supports hash calculation
36540 * based on IPV6 flow labels.
36542 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \
36545 * When this bit is '1', it indicates that HW and firmware supports
36546 * the use of RX V3 and RX TPA start V3 completion records for all
36547 * the RX rings of a VNIC. Once set, this feature is mandatory to
36548 * be used for the RX rings of the VNIC. If set to '0', the
36549 * HW and the firmware does not support this feature.
36551 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP \
36554 * When this bit is '1' HW supports different RX CQE record types.
36555 * Host drivers can choose the mode based on their application
36556 * requirements like performance, TPA, HDS and PTP.
36558 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \
36561 * This field advertises the maximum concurrent TPA aggregations
36562 * supported by the VNIC on new devices that support TPA v2 or v3.
36563 * '0' means that both the TPA v2 and v3 are not supported.
36565 uint16_t max_aggs_supported;
36566 uint8_t unused_1[5];
36568 * This field is used in Output records to indicate that the output
36569 * is completely written to RAM. This field should be read as '1'
36570 * to indicate that the output has been completely written.
36571 * When writing a command completion or response to an internal processor,
36572 * the order of writes has to be such that this field is written last.
36577 /*********************
36578 * hwrm_vnic_tpa_cfg *
36579 *********************/
36582 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
36583 struct hwrm_vnic_tpa_cfg_input {
36584 /* The HWRM command request type. */
36587 * The completion ring to send the completion event on. This should
36588 * be the NQ ID returned from the `nq_alloc` HWRM command.
36590 uint16_t cmpl_ring;
36592 * The sequence ID is used by the driver for tracking multiple
36593 * commands. This ID is treated as opaque data by the firmware and
36594 * the value is returned in the `hwrm_resp_hdr` upon completion.
36598 * The target ID of the command:
36599 * * 0x0-0xFFF8 - The function ID
36600 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36601 * * 0xFFFD - Reserved for user-space HWRM interface
36604 uint16_t target_id;
36606 * A physical address pointer pointing to a host buffer that the
36607 * command's response data will be written. This can be either a host
36608 * physical address (HPA) or a guest physical address (GPA) and must
36609 * point to a physically contiguous block of memory.
36611 uint64_t resp_addr;
36614 * When this bit is '1', the VNIC shall be configured to
36615 * perform transparent packet aggregation (TPA) of
36616 * non-tunneled TCP packets.
36618 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
36621 * When this bit is '1', the VNIC shall be configured to
36622 * perform transparent packet aggregation (TPA) of
36623 * tunneled TCP packets.
36625 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
36628 * When this bit is '1', the VNIC shall be configured to
36629 * perform transparent packet aggregation (TPA) according
36630 * to Windows Receive Segment Coalescing (RSC) rules.
36632 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
36635 * When this bit is '1', the VNIC shall be configured to
36636 * perform transparent packet aggregation (TPA) according
36637 * to Linux Generic Receive Offload (GRO) rules.
36639 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
36642 * When this bit is '1', the VNIC shall be configured to
36643 * perform transparent packet aggregation (TPA) for TCP
36644 * packets with IP ECN set to non-zero.
36646 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
36649 * When this bit is '1', the VNIC shall be configured to
36650 * perform transparent packet aggregation (TPA) for
36651 * GRE tunneled TCP packets only if all packets have the
36652 * same GRE sequence.
36654 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
36657 * When this bit is '1' and the GRO mode is enabled,
36658 * the VNIC shall be configured to
36659 * perform transparent packet aggregation (TPA) for
36660 * TCP/IPv4 packets with consecutively increasing IPIDs.
36661 * In other words, the last packet that is being
36662 * aggregated to an already existing aggregation context
36663 * shall have IPID 1 more than the IPID of the last packet
36664 * that was aggregated in that aggregation context.
36666 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
36669 * When this bit is '1' and the GRO mode is enabled,
36670 * the VNIC shall be configured to
36671 * perform transparent packet aggregation (TPA) for
36672 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
36675 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
36678 * When this bit is '1' and the GRO mode is enabled,
36679 * the VNIC shall DMA payload data using GRO rules.
36680 * When this bit is '0', the VNIC shall DMA payload data
36681 * using the more efficient LRO rules of filling all
36682 * aggregation buffers.
36684 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
36688 * This bit must be '1' for the max_agg_segs field to be
36691 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
36693 * This bit must be '1' for the max_aggs field to be
36696 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
36698 * This bit must be '1' for the max_agg_timer field to be
36701 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
36702 /* deprecated bit. Do not use!!! */
36703 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
36704 /* Logical vnic ID */
36707 * This is the maximum number of TCP segments that can
36708 * be aggregated (unit is Log2). Max value is 31. On new
36709 * devices supporting TPA v2, the unit is multiples of 4 and
36710 * valid values are > 0 and <= 63.
36712 uint16_t max_agg_segs;
36714 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
36716 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
36718 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
36720 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
36721 /* Any segment size larger than this is not valid */
36722 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
36723 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
36724 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
36726 * This is the maximum number of aggregations this VNIC is
36727 * allowed (unit is Log2). Max value is 7. On new devices
36728 * supporting TPA v2, this is in unit of 1 and must be > 0
36729 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
36730 * to enable TPA v2.
36733 /* 1 aggregation */
36734 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
36735 /* 2 aggregations */
36736 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
36737 /* 4 aggregations */
36738 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
36739 /* 8 aggregations */
36740 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
36741 /* 16 aggregations */
36742 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
36743 /* Any aggregation size larger than this is not valid */
36744 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
36745 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
36746 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
36747 uint8_t unused_0[2];
36749 * This is the maximum amount of time allowed for
36750 * an aggregation context to complete after it was initiated.
36752 uint32_t max_agg_timer;
36754 * This is the minimum amount of payload length required to
36755 * start an aggregation context. This field is deprecated and
36756 * should be set to 0. The minimum length is set by firmware
36757 * and can be queried using hwrm_vnic_tpa_qcfg.
36759 uint32_t min_agg_len;
36762 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
36763 struct hwrm_vnic_tpa_cfg_output {
36764 /* The specific error status for the command. */
36765 uint16_t error_code;
36766 /* The HWRM command request type. */
36768 /* The sequence ID from the original command. */
36770 /* The length of the response data in number of bytes. */
36772 uint8_t unused_0[7];
36774 * This field is used in Output records to indicate that the output
36775 * is completely written to RAM. This field should be read as '1'
36776 * to indicate that the output has been completely written.
36777 * When writing a command completion or response to an internal processor,
36778 * the order of writes has to be such that this field is written last.
36783 /*********************
36784 * hwrm_vnic_rss_cfg *
36785 *********************/
36788 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
36789 struct hwrm_vnic_rss_cfg_input {
36790 /* The HWRM command request type. */
36793 * The completion ring to send the completion event on. This should
36794 * be the NQ ID returned from the `nq_alloc` HWRM command.
36796 uint16_t cmpl_ring;
36798 * The sequence ID is used by the driver for tracking multiple
36799 * commands. This ID is treated as opaque data by the firmware and
36800 * the value is returned in the `hwrm_resp_hdr` upon completion.
36804 * The target ID of the command:
36805 * * 0x0-0xFFF8 - The function ID
36806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36807 * * 0xFFFD - Reserved for user-space HWRM interface
36810 uint16_t target_id;
36812 * A physical address pointer pointing to a host buffer that the
36813 * command's response data will be written. This can be either a host
36814 * physical address (HPA) or a guest physical address (GPA) and must
36815 * point to a physically contiguous block of memory.
36817 uint64_t resp_addr;
36818 uint32_t hash_type;
36820 * When this bit is '1', the RSS hash shall be computed
36821 * over source and destination IPv4 addresses of IPv4
36824 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 \
36827 * When this bit is '1', the RSS hash shall be computed
36828 * over source/destination IPv4 addresses and
36829 * source/destination ports of TCP/IPv4 packets.
36831 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 \
36834 * When this bit is '1', the RSS hash shall be computed
36835 * over source/destination IPv4 addresses and
36836 * source/destination ports of UDP/IPv4 packets.
36838 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 \
36841 * When this bit is '1', the RSS hash shall be computed
36842 * over source and destination IPv6 addresses of IPv6
36845 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 \
36848 * When this bit is '1', the RSS hash shall be computed
36849 * over source/destination IPv6 addresses and
36850 * source/destination ports of TCP/IPv6 packets.
36852 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 \
36855 * When this bit is '1', the RSS hash shall be computed
36856 * over source/destination IPv6 addresses and
36857 * source/destination ports of UDP/IPv6 packets.
36859 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 \
36862 * When this bit is '1', the RSS hash shall be computed
36863 * over source, destination IPv6 addresses and flow label of IPv6
36864 * packets. Hash type ipv6 and ipv6_flow_label are mutually
36865 * exclusive. HW does not include the flow_label in hash
36866 * calculation for the packets that are matching tcp_ipv6 and
36867 * udp_ipv6 hash types. Host drivers should set this bit based on
36868 * rss_ipv6_flow_label_cap.
36870 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \
36872 /* VNIC ID of VNIC associated with RSS table being configured. */
36875 * Specifies which VNIC ring table pair to configure.
36876 * Valid values range from 0 to 7.
36878 uint8_t ring_table_pair_index;
36879 /* Flags to specify different RSS hash modes. */
36880 uint8_t hash_mode_flags;
36882 * When this bit is '1', it indicates using current RSS
36883 * hash mode setting configured in the device.
36885 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
36888 * When this bit is '1', it indicates requesting support of
36889 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
36890 * l4.src, l4.dest} for tunnel packets. For none-tunnel
36891 * packets, the RSS hash is computed over the normal
36892 * src/dest l3 and src/dest l4 headers.
36894 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
36897 * When this bit is '1', it indicates requesting support of
36898 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
36899 * tunnel packets. For none-tunnel packets, the RSS hash is
36900 * computed over the normal src/dest l3 headers.
36902 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
36905 * When this bit is '1', it indicates requesting support of
36906 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
36907 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
36908 * packets, the RSS hash is computed over the normal
36909 * src/dest l3 and src/dest l4 headers.
36911 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
36914 * When this bit is '1', it indicates requesting support of
36915 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
36916 * tunnel packets. For none-tunnel packets, the RSS hash is
36917 * computed over the normal src/dest l3 headers.
36919 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
36921 /* This is the address for rss ring group table */
36922 uint64_t ring_grp_tbl_addr;
36923 /* This is the address for rss hash key table */
36924 uint64_t hash_key_tbl_addr;
36925 /* Index to the rss indirection table. */
36926 uint16_t rss_ctx_idx;
36929 * When this bit is '1', it indicates that the hash_type field is
36930 * interpreted as a change relative the current configuration. Each
36931 * '1' bit in hash_type represents a header to add to the current
36932 * hash. Zeroes designate the hash_type state bits that should remain
36933 * unchanged, if possible. If this constraint on the existing state
36934 * cannot be satisfied, then the implementation should preference
36935 * adding other headers so as to honor the request to add the
36936 * specified headers. It is an error to set this flag concurrently
36937 * with hash_type_exclude.
36939 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \
36942 * When this bit is '1', it indicates that the hash_type field is
36943 * interpreted as a change relative the current configuration. Each
36944 * '1' bit in hash_type represents a header to remove from the
36945 * current hash. Zeroes designate the hash_type state bits that
36946 * should remain unchanged, if possible. If this constraint on the
36947 * existing state cannot be satisfied, then the implementation should
36948 * preference removing other headers so as to honor the request to
36949 * remove the specified headers. It is an error to set this flag
36950 * concurrently with hash_type_include.
36952 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \
36954 uint8_t ring_select_mode;
36956 * In this mode, HW uses Toeplitz algorithm and provided Toeplitz
36957 * hash key to hash the packets according to the configured hash
36958 * type and hash mode. The Toeplitz hash results and the provided
36959 * Toeplitz RSS indirection table are used to determine the RSS
36962 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ \
36965 * In this mode, HW uses XOR algorithm to hash the packets according
36966 * to the configured hash type and hash mode. The XOR hash results
36967 * and the provided XOR RSS indirection table are used to determine
36968 * the RSS rings. Host drivers provided hash key is not honored in
36971 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR \
36974 * In this mode, HW uses inner packets checksum algorithm to
36975 * distribute the packets across the rings and Toeplitz algorithm
36976 * to calculate the hash to convey it in the RX completions. Host
36977 * drivers should provide Toeplitz hash key. As HW uses innermost
36978 * packets checksum to distribute the packets across the rings,
36979 * host drivers can't convey hash mode to choose outer headers to
36980 * calculate Toeplitz hash. FW will fail such configuration.
36982 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \
36984 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST \
36985 HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
36986 uint8_t unused_1[4];
36989 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
36990 struct hwrm_vnic_rss_cfg_output {
36991 /* The specific error status for the command. */
36992 uint16_t error_code;
36993 /* The HWRM command request type. */
36995 /* The sequence ID from the original command. */
36997 /* The length of the response data in number of bytes. */
36999 uint8_t unused_0[7];
37001 * This field is used in Output records to indicate that the output
37002 * is completely written to RAM. This field should be read as '1'
37003 * to indicate that the output has been completely written.
37004 * When writing a command completion or response to an internal processor,
37005 * the order of writes has to be such that this field is written last.
37010 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
37011 struct hwrm_vnic_rss_cfg_cmd_err {
37013 * command specific error codes that goes to
37014 * the cmd_err field in Common HWRM Error Response.
37017 /* Unknown error */
37018 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
37021 * Unable to change global RSS mode to outer due to all active
37022 * interfaces are not ready to support outer RSS hashing.
37024 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
37026 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
37027 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
37028 uint8_t unused_0[7];
37031 /**********************
37032 * hwrm_vnic_rss_qcfg *
37033 **********************/
37036 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
37037 struct hwrm_vnic_rss_qcfg_input {
37038 /* The HWRM command request type. */
37041 * The completion ring to send the completion event on. This should
37042 * be the NQ ID returned from the `nq_alloc` HWRM command.
37044 uint16_t cmpl_ring;
37046 * The sequence ID is used by the driver for tracking multiple
37047 * commands. This ID is treated as opaque data by the firmware and
37048 * the value is returned in the `hwrm_resp_hdr` upon completion.
37052 * The target ID of the command:
37053 * * 0x0-0xFFF8 - The function ID
37054 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37055 * * 0xFFFD - Reserved for user-space HWRM interface
37058 uint16_t target_id;
37060 * A physical address pointer pointing to a host buffer that the
37061 * command's response data will be written. This can be either a host
37062 * physical address (HPA) or a guest physical address (GPA) and must
37063 * point to a physically contiguous block of memory.
37065 uint64_t resp_addr;
37066 /* Index to the rss indirection table. */
37067 uint16_t rss_ctx_idx;
37068 uint8_t unused_0[6];
37071 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
37072 struct hwrm_vnic_rss_qcfg_output {
37073 /* The specific error status for the command. */
37074 uint16_t error_code;
37075 /* The HWRM command request type. */
37077 /* The sequence ID from the original command. */
37079 /* The length of the response data in number of bytes. */
37081 uint32_t hash_type;
37083 * When this bit is '1', the RSS hash shall be computed
37084 * over source and destination IPv4 addresses of IPv4
37087 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
37089 * When this bit is '1', the RSS hash shall be computed
37090 * over source/destination IPv4 addresses and
37091 * source/destination ports of TCP/IPv4 packets.
37093 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
37095 * When this bit is '1', the RSS hash shall be computed
37096 * over source/destination IPv4 addresses and
37097 * source/destination ports of UDP/IPv4 packets.
37099 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
37101 * When this bit is '1', the RSS hash shall be computed
37102 * over source and destination IPv6 addresses of IPv6
37105 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
37107 * When this bit is '1', the RSS hash shall be computed
37108 * over source/destination IPv6 addresses and
37109 * source/destination ports of TCP/IPv6 packets.
37111 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
37113 * When this bit is '1', the RSS hash shall be computed
37114 * over source/destination IPv6 addresses and
37115 * source/destination ports of UDP/IPv6 packets.
37117 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
37118 uint8_t unused_0[4];
37119 /* This is the value of rss hash key */
37120 uint32_t hash_key[10];
37121 /* Flags to specify different RSS hash modes. */
37122 uint8_t hash_mode_flags;
37124 * When this bit is '1', it indicates using current RSS
37125 * hash mode setting configured in the device.
37127 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
37130 * When this bit is '1', it indicates requesting support of
37131 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
37132 * l4.src, l4.dest} for tunnel packets. For none-tunnel
37133 * packets, the RSS hash is computed over the normal
37134 * src/dest l3 and src/dest l4 headers.
37136 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
37139 * When this bit is '1', it indicates requesting support of
37140 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
37141 * tunnel packets. For none-tunnel packets, the RSS hash is
37142 * computed over the normal src/dest l3 headers.
37144 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
37147 * When this bit is '1', it indicates requesting support of
37148 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
37149 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
37150 * packets, the RSS hash is computed over the normal
37151 * src/dest l3 and src/dest l4 headers.
37153 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
37156 * When this bit is '1', it indicates requesting support of
37157 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
37158 * tunnel packets. For none-tunnel packets, the RSS hash is
37159 * computed over the normal src/dest l3 headers.
37161 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
37163 uint8_t ring_select_mode;
37165 * In this mode, HW uses Toeplitz algorithm and provided Toeplitz
37166 * hash key to hash the packets according to the configured hash
37167 * type and hash mode. The Toeplitz hash results and the provided
37168 * Toeplitz RSS indirection table are used to determine the RSS
37171 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ \
37174 * In this mode, HW uses XOR algorithm to hash the packets according
37175 * to the configured hash type and hash mode. The XOR hash results
37176 * and the provided XOR RSS indirection table are used to determine
37177 * the RSS rings. Host drivers provided hash key is not honored in
37180 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR \
37183 * In this mode, HW uses inner packets checksum algorithm to
37184 * distribute the packets across the rings and Toeplitz algorithm
37185 * to calculate the hash to convey it in the RX completions. Host
37186 * drivers should provide Toeplitz hash key. As HW uses innermost
37187 * packets checksum to distribute the packets across the rings,
37188 * host drivers can't convey hash mode to choose outer headers to
37189 * calculate Toeplitz hash. FW will fail such configuration.
37191 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \
37193 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_LAST \
37194 HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
37195 uint8_t unused_1[5];
37197 * This field is used in Output records to indicate that the output
37198 * is completely written to RAM. This field should be read as '1'
37199 * to indicate that the output has been completely written.
37200 * When writing a command completion or response to an internal processor,
37201 * the order of writes has to be such that this field is written last.
37206 /**************************
37207 * hwrm_vnic_plcmodes_cfg *
37208 **************************/
37211 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
37212 struct hwrm_vnic_plcmodes_cfg_input {
37213 /* The HWRM command request type. */
37216 * The completion ring to send the completion event on. This should
37217 * be the NQ ID returned from the `nq_alloc` HWRM command.
37219 uint16_t cmpl_ring;
37221 * The sequence ID is used by the driver for tracking multiple
37222 * commands. This ID is treated as opaque data by the firmware and
37223 * the value is returned in the `hwrm_resp_hdr` upon completion.
37227 * The target ID of the command:
37228 * * 0x0-0xFFF8 - The function ID
37229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37230 * * 0xFFFD - Reserved for user-space HWRM interface
37233 uint16_t target_id;
37235 * A physical address pointer pointing to a host buffer that the
37236 * command's response data will be written. This can be either a host
37237 * physical address (HPA) or a guest physical address (GPA) and must
37238 * point to a physically contiguous block of memory.
37240 uint64_t resp_addr;
37243 * When this bit is '1', the VNIC shall be configured to
37244 * use regular placement algorithm.
37245 * By default, the regular placement algorithm shall be
37246 * enabled on the VNIC.
37248 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
37251 * When this bit is '1', the VNIC shall be configured
37252 * use the jumbo placement algorithm.
37254 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
37257 * When this bit is '1', the VNIC shall be configured
37258 * to enable Header-Data split for IPv4 packets according
37259 * to the following rules:
37260 * # If the packet is identified as TCP/IPv4, then the
37261 * packet is split at the beginning of the TCP payload.
37262 * # If the packet is identified as UDP/IPv4, then the
37263 * packet is split at the beginning of UDP payload.
37264 * # If the packet is identified as non-TCP and non-UDP
37265 * IPv4 packet, then the packet is split at the beginning
37266 * of the upper layer protocol header carried in the IPv4
37269 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
37272 * When this bit is '1', the VNIC shall be configured
37273 * to enable Header-Data split for IPv6 packets according
37274 * to the following rules:
37275 * # If the packet is identified as TCP/IPv6, then the
37276 * packet is split at the beginning of the TCP payload.
37277 * # If the packet is identified as UDP/IPv6, then the
37278 * packet is split at the beginning of UDP payload.
37279 * # If the packet is identified as non-TCP and non-UDP
37280 * IPv6 packet, then the packet is split at the beginning
37281 * of the upper layer protocol header carried in the IPv6
37284 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
37287 * When this bit is '1', the VNIC shall be configured
37288 * to enable Header-Data split for FCoE packets at the
37289 * beginning of FC payload.
37291 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
37294 * When this bit is '1', the VNIC shall be configured
37295 * to enable Header-Data split for RoCE packets at the
37296 * beginning of RoCE payload (after BTH/GRH headers).
37298 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
37301 * When this bit is '1', the VNIC shall be configured use the virtio
37302 * placement algorithm. This feature can only be configured when
37303 * proxy mode is supported on the function.
37305 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
37309 * This bit must be '1' for the jumbo_thresh_valid field to be
37312 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
37315 * This bit must be '1' for the hds_offset_valid field to be
37318 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
37321 * This bit must be '1' for the hds_threshold_valid field to be
37324 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
37327 * This bit must be '1' for the max_bds_valid field to be
37330 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
37332 /* Logical vnic ID */
37335 * When jumbo placement algorithm is enabled, this value
37336 * is used to determine the threshold for jumbo placement.
37337 * Packets with length larger than this value will be
37338 * placed according to the jumbo placement algorithm.
37340 uint16_t jumbo_thresh;
37342 * This value is used to determine the offset into
37343 * packet buffer where the split data (payload) will be
37344 * placed according to one of HDS placement algorithm.
37346 * The lengths of packet buffers provided for split data
37347 * shall be larger than this value.
37349 uint16_t hds_offset;
37351 * When one of the HDS placement algorithm is enabled, this
37352 * value is used to determine the threshold for HDS
37354 * Packets with length larger than this value will be
37355 * placed according to the HDS placement algorithm.
37356 * This value shall be in multiple of 4 bytes.
37358 uint16_t hds_threshold;
37360 * When virtio placement algorithm is enabled, this
37361 * value is used to determine the maximum number of BDs
37362 * that can be used to place an Rx Packet.
37363 * If an incoming packet does not fit in the buffers described
37364 * by the max BDs, the packet will be dropped and an error
37365 * will be reported in the completion. Valid values for this
37366 * field are between 1 and 8. If the VNIC uses header-data-
37367 * separation and/or TPA with buffer spanning enabled, valid
37368 * values for this field are between 2 and 8.
37369 * This feature can only be configured when proxy mode is
37370 * supported on the function.
37373 uint8_t unused_0[4];
37376 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
37377 struct hwrm_vnic_plcmodes_cfg_output {
37378 /* The specific error status for the command. */
37379 uint16_t error_code;
37380 /* The HWRM command request type. */
37382 /* The sequence ID from the original command. */
37384 /* The length of the response data in number of bytes. */
37386 uint8_t unused_0[7];
37388 * This field is used in Output records to indicate that the output
37389 * is completely written to RAM. This field should be read as '1'
37390 * to indicate that the output has been completely written.
37391 * When writing a command completion or response to an internal
37392 * processor, the order of writes has to be such that this field is
37398 /***************************
37399 * hwrm_vnic_plcmodes_qcfg *
37400 ***************************/
37403 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
37404 struct hwrm_vnic_plcmodes_qcfg_input {
37405 /* The HWRM command request type. */
37408 * The completion ring to send the completion event on. This should
37409 * be the NQ ID returned from the `nq_alloc` HWRM command.
37411 uint16_t cmpl_ring;
37413 * The sequence ID is used by the driver for tracking multiple
37414 * commands. This ID is treated as opaque data by the firmware and
37415 * the value is returned in the `hwrm_resp_hdr` upon completion.
37419 * The target ID of the command:
37420 * * 0x0-0xFFF8 - The function ID
37421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37422 * * 0xFFFD - Reserved for user-space HWRM interface
37425 uint16_t target_id;
37427 * A physical address pointer pointing to a host buffer that the
37428 * command's response data will be written. This can be either a host
37429 * physical address (HPA) or a guest physical address (GPA) and must
37430 * point to a physically contiguous block of memory.
37432 uint64_t resp_addr;
37433 /* Logical vnic ID */
37435 uint8_t unused_0[4];
37438 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
37439 struct hwrm_vnic_plcmodes_qcfg_output {
37440 /* The specific error status for the command. */
37441 uint16_t error_code;
37442 /* The HWRM command request type. */
37444 /* The sequence ID from the original command. */
37446 /* The length of the response data in number of bytes. */
37450 * When this bit is '1', the VNIC is configured to
37451 * use regular placement algorithm.
37453 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
37456 * When this bit is '1', the VNIC is configured to
37457 * use the jumbo placement algorithm.
37459 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
37462 * When this bit is '1', the VNIC is configured
37463 * to enable Header-Data split for IPv4 packets.
37465 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
37468 * When this bit is '1', the VNIC is configured
37469 * to enable Header-Data split for IPv6 packets.
37471 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
37474 * When this bit is '1', the VNIC is configured
37475 * to enable Header-Data split for FCoE packets.
37477 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
37480 * When this bit is '1', the VNIC is configured
37481 * to enable Header-Data split for RoCE packets.
37483 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
37486 * When this bit is '1', the VNIC is configured
37487 * to be the default VNIC of the requesting function.
37489 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
37492 * When this bit is '1', the VNIC is configured to use the virtio
37493 * placement algorithm. This feature can only be configured when
37494 * proxy mode is supported on the function.
37496 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
37499 * When jumbo placement algorithm is enabled, this value
37500 * is used to determine the threshold for jumbo placement.
37501 * Packets with length larger than this value will be
37502 * placed according to the jumbo placement algorithm.
37504 uint16_t jumbo_thresh;
37506 * This value is used to determine the offset into
37507 * packet buffer where the split data (payload) will be
37508 * placed according to one of HDS placement algorithm.
37510 * The lengths of packet buffers provided for split data
37511 * shall be larger than this value.
37513 uint16_t hds_offset;
37515 * When one of the HDS placement algorithm is enabled, this
37516 * value is used to determine the threshold for HDS
37518 * Packets with length larger than this value will be
37519 * placed according to the HDS placement algorithm.
37520 * This value shall be in multiple of 4 bytes.
37522 uint16_t hds_threshold;
37524 * When virtio placement algorithm is enabled, this
37525 * value is used to determine the maximum number of BDs
37526 * that can be used to place an Rx Packet.
37527 * If an incoming packet does not fit in the buffers described
37528 * by the max BDs, the packet will be dropped and an error
37529 * will be reported in the completion. Valid values for this
37530 * field are between 1 and 8. If the VNIC uses header-data-
37531 * separation and/or TPA with buffer spanning enabled, valid
37532 * values for this field are between 2 and 8.
37533 * This feature can only be configured when proxy mode is supported
37537 uint8_t unused_0[3];
37539 * This field is used in Output records to indicate that the output
37540 * is completely written to RAM. This field should be read as '1'
37541 * to indicate that the output has been completely written.
37542 * When writing a command completion or response to an internal
37543 * processor, the order of writes has to be such that this field is
37549 /**********************************
37550 * hwrm_vnic_rss_cos_lb_ctx_alloc *
37551 **********************************/
37554 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
37555 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
37556 /* The HWRM command request type. */
37559 * The completion ring to send the completion event on. This should
37560 * be the NQ ID returned from the `nq_alloc` HWRM command.
37562 uint16_t cmpl_ring;
37564 * The sequence ID is used by the driver for tracking multiple
37565 * commands. This ID is treated as opaque data by the firmware and
37566 * the value is returned in the `hwrm_resp_hdr` upon completion.
37570 * The target ID of the command:
37571 * * 0x0-0xFFF8 - The function ID
37572 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37573 * * 0xFFFD - Reserved for user-space HWRM interface
37576 uint16_t target_id;
37578 * A physical address pointer pointing to a host buffer that the
37579 * command's response data will be written. This can be either a host
37580 * physical address (HPA) or a guest physical address (GPA) and must
37581 * point to a physically contiguous block of memory.
37583 uint64_t resp_addr;
37586 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
37587 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
37588 /* The specific error status for the command. */
37589 uint16_t error_code;
37590 /* The HWRM command request type. */
37592 /* The sequence ID from the original command. */
37594 /* The length of the response data in number of bytes. */
37596 /* rss_cos_lb_ctx_id is 16 b */
37597 uint16_t rss_cos_lb_ctx_id;
37598 uint8_t unused_0[5];
37600 * This field is used in Output records to indicate that the output
37601 * is completely written to RAM. This field should be read as '1'
37602 * to indicate that the output has been completely written.
37603 * When writing a command completion or response to an internal processor,
37604 * the order of writes has to be such that this field is written last.
37609 /*********************************
37610 * hwrm_vnic_rss_cos_lb_ctx_free *
37611 *********************************/
37614 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
37615 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
37616 /* The HWRM command request type. */
37619 * The completion ring to send the completion event on. This should
37620 * be the NQ ID returned from the `nq_alloc` HWRM command.
37622 uint16_t cmpl_ring;
37624 * The sequence ID is used by the driver for tracking multiple
37625 * commands. This ID is treated as opaque data by the firmware and
37626 * the value is returned in the `hwrm_resp_hdr` upon completion.
37630 * The target ID of the command:
37631 * * 0x0-0xFFF8 - The function ID
37632 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37633 * * 0xFFFD - Reserved for user-space HWRM interface
37636 uint16_t target_id;
37638 * A physical address pointer pointing to a host buffer that the
37639 * command's response data will be written. This can be either a host
37640 * physical address (HPA) or a guest physical address (GPA) and must
37641 * point to a physically contiguous block of memory.
37643 uint64_t resp_addr;
37644 /* rss_cos_lb_ctx_id is 16 b */
37645 uint16_t rss_cos_lb_ctx_id;
37646 uint8_t unused_0[6];
37649 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
37650 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
37651 /* The specific error status for the command. */
37652 uint16_t error_code;
37653 /* The HWRM command request type. */
37655 /* The sequence ID from the original command. */
37657 /* The length of the response data in number of bytes. */
37659 uint8_t unused_0[7];
37661 * This field is used in Output records to indicate that the output
37662 * is completely written to RAM. This field should be read as '1'
37663 * to indicate that the output has been completely written.
37664 * When writing a command completion or response to an internal processor,
37665 * the order of writes has to be such that this field is written last.
37670 /*******************
37671 * hwrm_ring_alloc *
37672 *******************/
37675 /* hwrm_ring_alloc_input (size:704b/88B) */
37676 struct hwrm_ring_alloc_input {
37677 /* The HWRM command request type. */
37680 * The completion ring to send the completion event on. This should
37681 * be the NQ ID returned from the `nq_alloc` HWRM command.
37683 uint16_t cmpl_ring;
37685 * The sequence ID is used by the driver for tracking multiple
37686 * commands. This ID is treated as opaque data by the firmware and
37687 * the value is returned in the `hwrm_resp_hdr` upon completion.
37691 * The target ID of the command:
37692 * * 0x0-0xFFF8 - The function ID
37693 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37694 * * 0xFFFD - Reserved for user-space HWRM interface
37697 uint16_t target_id;
37699 * A physical address pointer pointing to a host buffer that the
37700 * command's response data will be written. This can be either a host
37701 * physical address (HPA) or a guest physical address (GPA) and must
37702 * point to a physically contiguous block of memory.
37704 uint64_t resp_addr;
37707 * This bit must be '1' for the ring_arb_cfg field to be
37710 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
37713 * This bit must be '1' for the stat_ctx_id_valid field to be
37716 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
37719 * This bit must be '1' for the max_bw_valid field to be
37722 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
37725 * This bit must be '1' for the rx_ring_id field to be
37728 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
37731 * This bit must be '1' for the nq_ring_id field to be
37734 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
37737 * This bit must be '1' for the rx_buf_size field to be
37740 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
37743 * This bit must be '1' for the schq_id field to be
37746 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
37749 * This bit must be '1' for the mpc_chnls_type field to be
37752 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
37756 /* L2 Completion Ring (CR) */
37757 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
37759 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
37761 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
37762 /* RoCE Notification Completion Ring (ROCE_CR) */
37763 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
37764 /* RX Aggregation Ring */
37765 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
37766 /* Notification Queue */
37767 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
37768 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
37769 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
37771 * This field controls the number of packets transmitted before a TX
37772 * completion is generated. Non-zero values for the field are only
37773 * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion
37774 * records capability is supported.
37776 uint8_t cmpl_coal_cnt;
37777 /* Generates a legacy TX completion on every packet. */
37778 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
37779 /* Generates a TX coalesced completion for up to 4 TX packets. */
37780 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1)
37781 /* Generates a TX coalesced completion for up to 8 TX packets. */
37782 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2)
37783 /* Generates a TX coalesced completion for up to 12 TX packets. */
37784 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3)
37785 /* Generates a TX coalesced completion for up to 16 TX packets. */
37786 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4)
37787 /* Generates a TX coalesced completion for up to 24 TX packets. */
37788 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5)
37789 /* Generates a TX coalesced completion for up to 32 TX packets. */
37790 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6)
37791 /* Generates a TX coalesced completion for up to 48 TX packets. */
37792 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7)
37793 /* Generates a TX coalesced completion for up to 64 TX packets. */
37794 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8)
37795 /* Generates a TX coalesced completion for up to 96 TX packets. */
37796 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9)
37797 /* Generates a TX coalesced completion for up to 128 TX packets. */
37798 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
37799 /* Generates a TX coalesced completion for up to 192 TX packets. */
37800 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
37801 /* Generates a TX coalesced completion for up to 256 TX packets. */
37802 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
37803 /* Generates a TX coalesced completion for up to 320 TX packets. */
37804 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
37805 /* Generates a TX coalesced completion for up to 384 TX packets. */
37806 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
37807 /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */
37808 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
37809 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \
37810 HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX
37811 /* Ring allocation flags. */
37814 * For Rx rings, the incoming packet data can be placed at either
37815 * a 0B or 2B offset from the start of the Rx packet buffer. When
37816 * '1', the received packet will be padded with 2B of zeros at the
37817 * front of the packet. Note that this flag is only used for
37818 * Rx rings and is ignored for all other rings included Rx
37819 * Aggregation rings.
37821 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD \
37824 * When the HW Doorbell Drop Recovery feature is enabled,
37825 * HW can flag false CQ overflow when CQ consumer index
37826 * doorbells are dropped when there really wasn't any overflow.
37827 * The CQE values could have already been processed by the driver,
37828 * but HW doesn't know about this because of the doorbell drop.
37829 * To avoid false detection of CQ overflow events,
37830 * it is recommended that CQ overflow detection is disabled
37831 * by the driver when HW based doorbell recovery is enabled.
37833 #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \
37836 * This value is a pointer to the page table for the
37839 uint64_t page_tbl_addr;
37840 /* First Byte Offset of the first entry in the first page. */
37843 * Actual page size in 2^page_size. The supported range is increments
37844 * in powers of 2 from 16 bytes to 1GB.
37846 * Page size is 16 B.
37848 * Page size is 4 KB.
37850 * Page size is 8 KB.
37852 * Page size is 64 KB.
37854 * Page size is 2 MB.
37856 * Page size is 4 MB.
37858 * Page size is 1 GB.
37862 * This value indicates the depth of page table.
37863 * For this version of the specification, value other than 0 or
37864 * 1 shall be considered as an invalid value.
37865 * When the page_tbl_depth = 0, then it is treated as a
37866 * special case with the following.
37867 * 1. FBO and page size fields are not valid.
37868 * 2. page_tbl_addr is the physical address of the first
37869 * element of the ring.
37871 uint8_t page_tbl_depth;
37872 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
37875 * Number of 16B units in the ring. Minimum size for
37876 * a ring is 16 16B entries.
37880 * Logical ring number for the ring to be allocated.
37881 * This value determines the position in the doorbell
37882 * area where the update to the ring will be made.
37884 * For completion rings, this value is also the MSI-X
37885 * vector number for the function the completion ring is
37888 uint16_t logical_id;
37890 * This field is used only when ring_type is a TX ring.
37891 * This value indicates what completion ring the TX ring
37892 * is associated with.
37894 uint16_t cmpl_ring_id;
37896 * This field is used only when ring_type is a TX ring.
37897 * This value indicates what CoS queue the TX ring
37898 * is associated with.
37902 * When allocating a Rx ring or Rx aggregation ring, this field
37903 * specifies the size of the buffer descriptors posted to the ring.
37905 uint16_t rx_buf_size;
37907 * When allocating an Rx aggregation ring, this field
37908 * specifies the associated Rx ring ID.
37910 uint16_t rx_ring_id;
37912 * When allocating a completion ring, this field
37913 * specifies the associated NQ ring ID.
37915 uint16_t nq_ring_id;
37917 * This field is used only when ring_type is a TX ring.
37918 * This field is used to configure arbitration related
37919 * parameters for a TX ring.
37921 uint16_t ring_arb_cfg;
37922 /* Arbitration policy used for the ring. */
37923 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
37925 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
37927 * Use strict priority for the TX ring.
37928 * Priority value is specified in arb_policy_param
37930 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
37933 * Use weighted fair queue arbitration for the TX ring.
37934 * Weight is specified in arb_policy_param
37936 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
37938 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
37939 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
37940 /* Reserved field. */
37941 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
37943 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
37945 * Arbitration policy specific parameter.
37946 * # For strict priority arbitration policy, this field
37947 * represents a priority value. If set to 0, then the priority
37948 * is not specified and the HWRM is allowed to select
37949 * any priority for this TX ring.
37950 * # For weighted fair queue arbitration policy, this field
37951 * represents a weight value. If set to 0, then the weight
37952 * is not specified and the HWRM is allowed to select
37953 * any weight for this TX ring.
37955 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
37957 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
37960 * This field is reserved for the future use.
37961 * It shall be set to 0.
37963 uint32_t reserved3;
37965 * This field is used only when ring_type is a TX ring.
37966 * This input indicates what statistics context this ring
37967 * should be associated with.
37969 uint32_t stat_ctx_id;
37971 * This field is reserved for the future use.
37972 * It shall be set to 0.
37974 uint32_t reserved4;
37976 * This field is used only when ring_type is a TX ring
37977 * to specify maximum BW allocated to the TX ring.
37978 * The HWRM will translate this value into byte counter and
37979 * time interval used for this ring inside the device.
37982 /* The bandwidth value. */
37983 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
37984 UINT32_C(0xfffffff)
37985 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
37986 /* The granularity of the value (bits or bytes). */
37987 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
37988 UINT32_C(0x10000000)
37989 /* Value is in bits. */
37990 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
37991 (UINT32_C(0x0) << 28)
37992 /* Value is in bytes. */
37993 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
37994 (UINT32_C(0x1) << 28)
37995 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
37996 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
37997 /* bw_value_unit is 3 b */
37998 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
37999 UINT32_C(0xe0000000)
38000 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
38001 /* Value is in Mb or MB (base 10). */
38002 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
38003 (UINT32_C(0x0) << 29)
38004 /* Value is in Kb or KB (base 10). */
38005 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
38006 (UINT32_C(0x2) << 29)
38007 /* Value is in bits or bytes. */
38008 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
38009 (UINT32_C(0x4) << 29)
38010 /* Value is in Gb or GB (base 10). */
38011 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
38012 (UINT32_C(0x6) << 29)
38013 /* Value is in 1/100th of a percentage of total bandwidth. */
38014 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
38015 (UINT32_C(0x1) << 29)
38017 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
38018 (UINT32_C(0x7) << 29)
38019 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
38020 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
38022 * This field is used only when ring_type is a Completion ring.
38023 * This value indicates what interrupt mode should be used
38024 * on this completion ring.
38025 * Note: In the legacy interrupt mode, no more than 16
38026 * completion rings are allowed.
38030 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
38032 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
38034 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
38035 /* No Interrupt - Polled mode */
38036 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
38037 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
38038 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
38039 /* Midpath channel type */
38040 uint8_t mpc_chnls_type;
38042 * Indicate the TX ring alloc MPC channel type is a MPC channel
38043 * with destination to the TX crypto engine block.
38045 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
38047 * Indicate the RX ring alloc MPC channel type is a MPC channel
38048 * with destination to the RX crypto engine block.
38050 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
38052 * Indicate the RX ring alloc MPC channel type is a MPC channel
38053 * with destination to the TX configurable flow processing block.
38055 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
38057 * Indicate the RX ring alloc MPC channel type is a MPC channel
38058 * with destination to the RX configurable flow processing block.
38060 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
38062 * Indicate the RX ring alloc MPC channel type is a MPC channel
38063 * with destination to the primate processor block.
38065 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
38066 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
38067 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
38068 uint8_t unused_4[2];
38070 * The cq_handle is specified when allocating a completion ring. For
38071 * devices that support NQs, this cq_handle will be included in the
38072 * NQE to specify which CQ should be read to retrieve the completion
38075 uint64_t cq_handle;
38078 /* hwrm_ring_alloc_output (size:128b/16B) */
38079 struct hwrm_ring_alloc_output {
38080 /* The specific error status for the command. */
38081 uint16_t error_code;
38082 /* The HWRM command request type. */
38084 /* The sequence ID from the original command. */
38086 /* The length of the response data in number of bytes. */
38089 * Physical number of ring allocated.
38090 * This value shall be unique for a ring type.
38093 /* Logical number of ring allocated. */
38094 uint16_t logical_ring_id;
38096 * This field will tell whether to use ping or pong buffer
38097 * for first push operation.
38099 uint8_t push_buffer_index;
38100 /* Start push from ping buffer index */
38101 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
38103 /* Start push from pong buffer index */
38104 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
38106 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
38107 HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
38108 uint8_t unused_0[2];
38110 * This field is used in Output records to indicate that the output
38111 * is completely written to RAM. This field should be read as '1'
38112 * to indicate that the output has been completely written.
38113 * When writing a command completion or response to an internal processor,
38114 * the order of writes has to be such that this field is written last.
38119 /******************
38121 ******************/
38124 /* hwrm_ring_free_input (size:256b/32B) */
38125 struct hwrm_ring_free_input {
38126 /* The HWRM command request type. */
38129 * The completion ring to send the completion event on. This should
38130 * be the NQ ID returned from the `nq_alloc` HWRM command.
38132 uint16_t cmpl_ring;
38134 * The sequence ID is used by the driver for tracking multiple
38135 * commands. This ID is treated as opaque data by the firmware and
38136 * the value is returned in the `hwrm_resp_hdr` upon completion.
38140 * The target ID of the command:
38141 * * 0x0-0xFFF8 - The function ID
38142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38143 * * 0xFFFD - Reserved for user-space HWRM interface
38146 uint16_t target_id;
38148 * A physical address pointer pointing to a host buffer that the
38149 * command's response data will be written. This can be either a host
38150 * physical address (HPA) or a guest physical address (GPA) and must
38151 * point to a physically contiguous block of memory.
38153 uint64_t resp_addr;
38156 /* L2 Completion Ring (CR) */
38157 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
38159 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
38161 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
38162 /* RoCE Notification Completion Ring (ROCE_CR) */
38163 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
38164 /* RX Aggregation Ring */
38165 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
38166 /* Notification Queue */
38167 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
38168 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
38169 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
38172 * If this bit is set to '1', ring_id in this command belongs to
38173 * virtio function. prod_idx in this command corresponds to doorbell
38174 * producer index. opaque field in this command needs to be inserted
38175 * by firmware in VEE_FLUSH completion record.
38176 * Firmware will poll the corresponding ring context to reach the
38177 * given producer index before sending successful response. It will
38178 * finish the completion using VEE_FLUSH completion record.
38180 * If this bit is '0', firmware will not treat ring_id as virtio
38181 * ring and ignore prod_idx, opaque fields.
38183 * This feature is not applicable for L2 or RoCE.
38185 #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
38186 #define HWRM_RING_FREE_INPUT_FLAGS_LAST \
38187 HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID
38188 /* Physical number of ring allocated. */
38191 * Ring BD producer index posted by the virtio block.
38192 * This field is valid if virtio_ring_valid flag is set.
38196 * User defined opaque field to be inserted into VEE_FLUSH completion
38197 * record. This field is valid if virtio_ring_valid flag is set.
38203 /* hwrm_ring_free_output (size:128b/16B) */
38204 struct hwrm_ring_free_output {
38205 /* The specific error status for the command. */
38206 uint16_t error_code;
38207 /* The HWRM command request type. */
38209 /* The sequence ID from the original command. */
38211 /* The length of the response data in number of bytes. */
38213 uint8_t unused_0[7];
38215 * This field is used in Output records to indicate that the output
38216 * is completely written to RAM. This field should be read as '1'
38217 * to indicate that the output has been completely written.
38218 * When writing a command completion or response to an internal processor,
38219 * the order of writes has to be such that this field is written last.
38224 /*******************
38225 * hwrm_ring_reset *
38226 *******************/
38229 /* hwrm_ring_reset_input (size:192b/24B) */
38230 struct hwrm_ring_reset_input {
38231 /* The HWRM command request type. */
38234 * The completion ring to send the completion event on. This should
38235 * be the NQ ID returned from the `nq_alloc` HWRM command.
38237 uint16_t cmpl_ring;
38239 * The sequence ID is used by the driver for tracking multiple
38240 * commands. This ID is treated as opaque data by the firmware and
38241 * the value is returned in the `hwrm_resp_hdr` upon completion.
38245 * The target ID of the command:
38246 * * 0x0-0xFFF8 - The function ID
38247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38248 * * 0xFFFD - Reserved for user-space HWRM interface
38251 uint16_t target_id;
38253 * A physical address pointer pointing to a host buffer that the
38254 * command's response data will be written. This can be either a host
38255 * physical address (HPA) or a guest physical address (GPA) and must
38256 * point to a physically contiguous block of memory.
38258 uint64_t resp_addr;
38261 /* L2 Completion Ring (CR) */
38262 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
38264 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
38266 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
38267 /* RoCE Notification Completion Ring (ROCE_CR) */
38268 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
38270 * Rx Ring Group. This is to reset rx and aggregation in an atomic
38271 * operation. Completion ring associated with this ring group is
38274 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
38275 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
38276 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
38279 * Physical number of the ring. When ring type is rx_ring_grp, ring id
38280 * actually refers to ring group id.
38283 uint8_t unused_1[4];
38286 /* hwrm_ring_reset_output (size:128b/16B) */
38287 struct hwrm_ring_reset_output {
38288 /* The specific error status for the command. */
38289 uint16_t error_code;
38290 /* The HWRM command request type. */
38292 /* The sequence ID from the original command. */
38294 /* The length of the response data in number of bytes. */
38297 * This field will tell whether to use ping or pong buffer
38298 * for first push operation.
38300 uint8_t push_buffer_index;
38301 /* Start push from ping buffer index */
38302 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
38304 /* Start push from pong buffer index */
38305 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
38307 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
38308 HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
38309 uint8_t unused_0[3];
38310 /* Position of consumer index after ring reset completes. */
38311 uint8_t consumer_idx[3];
38313 * This field is used in Output records to indicate that the output
38314 * is completely written to RAM. This field should be read as '1'
38315 * to indicate that the output has been completely written.
38316 * When writing a command completion or response to an internal processor,
38317 * the order of writes has to be such that this field is written last.
38327 /* hwrm_ring_cfg_input (size:320b/40B) */
38328 struct hwrm_ring_cfg_input {
38329 /* The HWRM command request type. */
38332 * The completion ring to send the completion event on. This should
38333 * be the NQ ID returned from the `nq_alloc` HWRM command.
38335 uint16_t cmpl_ring;
38337 * The sequence ID is used by the driver for tracking multiple
38338 * commands. This ID is treated as opaque data by the firmware and
38339 * the value is returned in the `hwrm_resp_hdr` upon completion.
38343 * The target ID of the command:
38344 * * 0x0-0xFFF8 - The function ID
38345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38346 * * 0xFFFD - Reserved for user-space HWRM interface
38349 uint16_t target_id;
38351 * A physical address pointer pointing to a host buffer that the
38352 * command's response data will be written. This can be either a host
38353 * physical address (HPA) or a guest physical address (GPA) and must
38354 * point to a physically contiguous block of memory.
38356 uint64_t resp_addr;
38360 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
38362 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
38363 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
38364 HWRM_RING_CFG_INPUT_RING_TYPE_RX
38366 /* Physical number of the ring. */
38368 /* Ring config enable bits. */
38371 * For Rx rings, the incoming packet data can be placed at either
38372 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
38374 * When '1', the received packet will be padded with 2B, 10B or 12B
38375 * of zeros at the front of the packet. The exact offset is specified
38376 * by rx_sop_pad_bytes parameter.
38377 * When '0', the received packet will not be padded.
38378 * Note that this flag is only used for Rx rings and is ignored
38379 * for all other rings included Rx Aggregation rings.
38381 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
38384 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
38385 * When rings are allocated, the PCI function on which driver issues
38386 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
38387 * the buffer descriptors (BDs) from those rings is assumed to issue
38388 * packet payload DMA using same PCI function. When proxy mode is
38389 * enabled, hardware can perform payload DMA using another PCI
38390 * function on same or different host.
38391 * When set to '0', the PCI function on which driver issues
38392 * HWRM_RING_CFG command is used for host payload DMA operation.
38393 * When set to '1', the host PCI function specified by proxy_fid is
38394 * used for host payload DMA operation.
38396 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
38399 * Tx ring packet source interface override, for Tx rings only.
38400 * When TX rings are allocated, the PCI function on which driver
38401 * issues HWRM_RING_CFG is assumed to be source interface of
38402 * packets sent from TX ring.
38403 * When set to '1', the host PCI function specified by proxy_fid
38404 * is used as source interface of the transmitted packets.
38406 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
38408 /* The schq_id field is valid */
38409 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
38411 /* Update completion ring ID associated with Tx or Rx ring. */
38412 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
38415 * When set to '1', metadata value provided by tx_metadata
38416 * field in this command is inserted in the lb_header_metadata
38417 * QP context field. When set to '0', no change done to metadata.
38418 * Firmware rejects the tx ring metadata programming with
38419 * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
38420 * metadata feature is not disabled.
38422 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
38425 * Proxy function FID value.
38426 * This value is only used when either proxy_mode_enable flag or
38427 * tx_proxy_svif_override is set to '1'.
38428 * When proxy_mode_enable is set to '1', it identifies a host PCI
38429 * function used for host payload DMA operations.
38430 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
38431 * function as source interface for all transmitted packets from
38434 uint16_t proxy_fid;
38436 * Identifies the new scheduler queue (SCHQ) to associate with the
38437 * ring. Only valid for Tx rings.
38438 * A value of zero indicates that the Tx ring should be associated
38439 * with the default scheduler queue (SCHQ).
38443 * This field is valid for TX or Rx rings. This value identifies the
38444 * new completion ring ID to associate with the TX or Rx ring.
38446 uint16_t cmpl_ring_id;
38448 * Rx SOP padding amount in bytes.
38449 * This value is only used when rx_sop_pad_enable flag is set to '1'.
38451 uint8_t rx_sop_pad_bytes;
38452 uint8_t unused_1[3];
38454 * When tx_metadata enable bit is set, value specified in this field
38455 * is copied to lb_header_metadata in the QP context.
38457 uint32_t tx_metadata;
38458 uint8_t unused_2[4];
38461 /* hwrm_ring_cfg_output (size:128b/16B) */
38462 struct hwrm_ring_cfg_output {
38463 /* The specific error status for the command. */
38464 uint16_t error_code;
38465 /* The HWRM command request type. */
38467 /* The sequence ID from the original command. */
38469 /* The length of the response data in number of bytes. */
38471 uint8_t unused_0[7];
38473 * This field is used in Output records to indicate that the output
38474 * is completely written to RAM. This field should be read as '1'
38475 * to indicate that the output has been completely written.
38476 * When writing a command completion or response to an internal
38477 * processor, the order of writes has to be such that this field is
38483 /******************
38485 ******************/
38488 /* hwrm_ring_qcfg_input (size:192b/24B) */
38489 struct hwrm_ring_qcfg_input {
38490 /* The HWRM command request type. */
38493 * The completion ring to send the completion event on. This should
38494 * be the NQ ID returned from the `nq_alloc` HWRM command.
38496 uint16_t cmpl_ring;
38498 * The sequence ID is used by the driver for tracking multiple
38499 * commands. This ID is treated as opaque data by the firmware and
38500 * the value is returned in the `hwrm_resp_hdr` upon completion.
38504 * The target ID of the command:
38505 * * 0x0-0xFFF8 - The function ID
38506 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38507 * * 0xFFFD - Reserved for user-space HWRM interface
38510 uint16_t target_id;
38512 * A physical address pointer pointing to a host buffer that the
38513 * command's response data will be written. This can be either a host
38514 * physical address (HPA) or a guest physical address (GPA) and must
38515 * point to a physically contiguous block of memory.
38517 uint64_t resp_addr;
38521 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
38523 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
38524 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
38525 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
38526 uint8_t unused_0[5];
38527 /* Physical number of the ring. */
38531 /* hwrm_ring_qcfg_output (size:256b/32B) */
38532 struct hwrm_ring_qcfg_output {
38533 /* The specific error status for the command. */
38534 uint16_t error_code;
38535 /* The HWRM command request type. */
38537 /* The sequence ID from the original command. */
38539 /* The length of the response data in number of bytes. */
38541 /* Ring config enable bits. */
38544 * For Rx rings, the incoming packet data can be placed at either
38545 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
38547 * When '1', the received packet will be padded with 2B, 10B or 12B
38548 * of zeros at the front of the packet. The exact offset is specified
38549 * by rx_sop_pad_bytes parameter.
38550 * When '0', the received packet will not be padded.
38551 * Note that this flag is only used for Rx rings and is ignored
38552 * for all other rings included Rx Aggregation rings.
38554 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
38557 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
38558 * When rings are allocated, the PCI function on which driver issues
38559 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
38560 * the buffer descriptors (BDs) from those rings is assumed to issue
38561 * packet payload DMA using same PCI function. When proxy mode is
38562 * enabled, hardware can perform payload DMA using another PCI
38563 * function on same or different host.
38564 * When set to '0', the PCI function on which driver issues
38565 * HWRM_RING_CFG command is used for host payload DMA operation.
38566 * When set to '1', the host PCI function specified by proxy_fid is
38567 * used for host payload DMA operation.
38569 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
38572 * Tx ring packet source interface override, for Tx rings only.
38573 * When TX rings are allocated, the PCI function on which driver
38574 * issues HWRM_RING_CFG is assumed to be source interface of
38575 * packets sent from TX ring.
38576 * When set to '1', the host PCI function specified by proxy_fid is
38577 * used as source interface of the transmitted packets.
38579 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
38582 * Proxy function FID value.
38583 * This value is only used when either proxy_mode_enable flag or
38584 * tx_proxy_svif_override is set to '1'.
38585 * When proxy_mode_enable is set to '1', it identifies a host PCI
38586 * function used for host payload DMA operations.
38587 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
38588 * function as source interface for all transmitted packets from the TX
38591 uint16_t proxy_fid;
38593 * Identifies the new scheduler queue (SCHQ) to associate with the
38594 * ring. Only valid for Tx rings.
38595 * A value of zero indicates that the Tx ring should be associated with
38596 * the default scheduler queue (SCHQ).
38600 * This field is used when ring_type is a TX or Rx ring.
38601 * This value indicates what completion ring the TX or Rx ring
38602 * is associated with.
38604 uint16_t cmpl_ring_id;
38606 * Rx SOP padding amount in bytes.
38607 * This value is only used when rx_sop_pad_enable flag is set to '1'.
38609 uint8_t rx_sop_pad_bytes;
38610 uint8_t unused_0[3];
38611 /* lb_header_metadata in the QP context is copied to this field. */
38612 uint32_t tx_metadata;
38613 uint8_t unused_1[7];
38615 * This field is used in Output records to indicate that the output
38616 * is completely written to RAM. This field should be read as '1'
38617 * to indicate that the output has been completely written.
38618 * When writing a command completion or response to an internal
38619 * processor, the order of writes has to be such that this field is
38625 /**************************
38626 * hwrm_ring_aggint_qcaps *
38627 **************************/
38630 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
38631 struct hwrm_ring_aggint_qcaps_input {
38632 /* The HWRM command request type. */
38635 * The completion ring to send the completion event on. This should
38636 * be the NQ ID returned from the `nq_alloc` HWRM command.
38638 uint16_t cmpl_ring;
38640 * The sequence ID is used by the driver for tracking multiple
38641 * commands. This ID is treated as opaque data by the firmware and
38642 * the value is returned in the `hwrm_resp_hdr` upon completion.
38646 * The target ID of the command:
38647 * * 0x0-0xFFF8 - The function ID
38648 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38649 * * 0xFFFD - Reserved for user-space HWRM interface
38652 uint16_t target_id;
38654 * A physical address pointer pointing to a host buffer that the
38655 * command's response data will be written. This can be either a host
38656 * physical address (HPA) or a guest physical address (GPA) and must
38657 * point to a physically contiguous block of memory.
38659 uint64_t resp_addr;
38662 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
38663 struct hwrm_ring_aggint_qcaps_output {
38664 /* The specific error status for the command. */
38665 uint16_t error_code;
38666 /* The HWRM command request type. */
38668 /* The sequence ID from the original command. */
38670 /* The length of the response data in number of bytes. */
38672 uint32_t cmpl_params;
38674 * When this bit is set to '1', int_lat_tmr_min can be configured
38675 * on completion rings.
38677 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
38680 * When this bit is set to '1', int_lat_tmr_max can be configured
38681 * on completion rings.
38683 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
38686 * When this bit is set to '1', timer_reset can be enabled
38687 * on completion rings.
38689 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
38692 * When this bit is set to '1', ring_idle can be enabled
38693 * on completion rings.
38695 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
38698 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
38699 * on completion rings.
38701 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
38704 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
38705 * on completion rings.
38707 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
38710 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
38711 * on completion rings.
38713 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
38716 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
38717 * on completion rings.
38719 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
38722 * When this bit is set to '1', num_cmpl_aggr_int can be configured
38723 * on completion rings.
38725 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
38727 uint32_t nq_params;
38729 * When this bit is set to '1', int_lat_tmr_min can be configured
38730 * on notification queues.
38732 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
38734 /* Minimum value for num_cmpl_dma_aggr */
38735 uint16_t num_cmpl_dma_aggr_min;
38736 /* Maximum value for num_cmpl_dma_aggr */
38737 uint16_t num_cmpl_dma_aggr_max;
38738 /* Minimum value for num_cmpl_dma_aggr_during_int */
38739 uint16_t num_cmpl_dma_aggr_during_int_min;
38740 /* Maximum value for num_cmpl_dma_aggr_during_int */
38741 uint16_t num_cmpl_dma_aggr_during_int_max;
38742 /* Minimum value for cmpl_aggr_dma_tmr */
38743 uint16_t cmpl_aggr_dma_tmr_min;
38744 /* Maximum value for cmpl_aggr_dma_tmr */
38745 uint16_t cmpl_aggr_dma_tmr_max;
38746 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
38747 uint16_t cmpl_aggr_dma_tmr_during_int_min;
38748 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
38749 uint16_t cmpl_aggr_dma_tmr_during_int_max;
38750 /* Minimum value for int_lat_tmr_min */
38751 uint16_t int_lat_tmr_min_min;
38752 /* Maximum value for int_lat_tmr_min */
38753 uint16_t int_lat_tmr_min_max;
38754 /* Minimum value for int_lat_tmr_max */
38755 uint16_t int_lat_tmr_max_min;
38756 /* Maximum value for int_lat_tmr_max */
38757 uint16_t int_lat_tmr_max_max;
38758 /* Minimum value for num_cmpl_aggr_int */
38759 uint16_t num_cmpl_aggr_int_min;
38760 /* Maximum value for num_cmpl_aggr_int */
38761 uint16_t num_cmpl_aggr_int_max;
38762 /* The units for timer parameters, in nanoseconds. */
38763 uint16_t timer_units;
38764 uint8_t unused_0[1];
38766 * This field is used in Output records to indicate that the output
38767 * is completely written to RAM. This field should be read as '1'
38768 * to indicate that the output has been completely written.
38769 * When writing a command completion or response to an internal processor,
38770 * the order of writes has to be such that this field is written last.
38775 /**************************************
38776 * hwrm_ring_cmpl_ring_qaggint_params *
38777 **************************************/
38780 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
38781 struct hwrm_ring_cmpl_ring_qaggint_params_input {
38782 /* The HWRM command request type. */
38785 * The completion ring to send the completion event on. This should
38786 * be the NQ ID returned from the `nq_alloc` HWRM command.
38788 uint16_t cmpl_ring;
38790 * The sequence ID is used by the driver for tracking multiple
38791 * commands. This ID is treated as opaque data by the firmware and
38792 * the value is returned in the `hwrm_resp_hdr` upon completion.
38796 * The target ID of the command:
38797 * * 0x0-0xFFF8 - The function ID
38798 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38799 * * 0xFFFD - Reserved for user-space HWRM interface
38802 uint16_t target_id;
38804 * A physical address pointer pointing to a host buffer that the
38805 * command's response data will be written. This can be either a host
38806 * physical address (HPA) or a guest physical address (GPA) and must
38807 * point to a physically contiguous block of memory.
38809 uint64_t resp_addr;
38810 /* Physical number of completion ring. */
38813 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
38815 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
38817 * Set this flag to 1 when querying parameters on a notification
38818 * queue. Set this flag to 0 when querying parameters on a
38819 * completion queue or completion ring.
38821 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
38823 uint8_t unused_0[4];
38826 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
38827 struct hwrm_ring_cmpl_ring_qaggint_params_output {
38828 /* The specific error status for the command. */
38829 uint16_t error_code;
38830 /* The HWRM command request type. */
38832 /* The sequence ID from the original command. */
38834 /* The length of the response data in number of bytes. */
38838 * When this bit is set to '1', interrupt max
38839 * timer is reset whenever a completion is received.
38841 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
38844 * When this bit is set to '1', ring idle mode
38845 * aggregation will be enabled.
38847 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
38850 * Number of completions to aggregate before DMA
38851 * during the normal mode.
38853 uint16_t num_cmpl_dma_aggr;
38855 * Number of completions to aggregate before DMA
38856 * during the interrupt mode.
38858 uint16_t num_cmpl_dma_aggr_during_int;
38860 * Timer used to aggregate completions before
38861 * DMA during the normal mode (not in interrupt mode).
38863 uint16_t cmpl_aggr_dma_tmr;
38865 * Timer used to aggregate completions before
38866 * DMA when in interrupt mode.
38868 uint16_t cmpl_aggr_dma_tmr_during_int;
38869 /* Minimum time between two interrupts. */
38870 uint16_t int_lat_tmr_min;
38872 * Maximum wait time spent aggregating
38873 * completions before signaling the interrupt after the
38874 * interrupt is enabled.
38876 uint16_t int_lat_tmr_max;
38878 * Minimum number of completions aggregated before signaling
38881 uint16_t num_cmpl_aggr_int;
38882 uint8_t unused_0[7];
38884 * This field is used in Output records to indicate that the output
38885 * is completely written to RAM. This field should be read as '1'
38886 * to indicate that the output has been completely written.
38887 * When writing a command completion or response to an internal processor,
38888 * the order of writes has to be such that this field is written last.
38893 /*****************************************
38894 * hwrm_ring_cmpl_ring_cfg_aggint_params *
38895 *****************************************/
38898 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
38899 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
38900 /* The HWRM command request type. */
38903 * The completion ring to send the completion event on. This should
38904 * be the NQ ID returned from the `nq_alloc` HWRM command.
38906 uint16_t cmpl_ring;
38908 * The sequence ID is used by the driver for tracking multiple
38909 * commands. This ID is treated as opaque data by the firmware and
38910 * the value is returned in the `hwrm_resp_hdr` upon completion.
38914 * The target ID of the command:
38915 * * 0x0-0xFFF8 - The function ID
38916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38917 * * 0xFFFD - Reserved for user-space HWRM interface
38920 uint16_t target_id;
38922 * A physical address pointer pointing to a host buffer that the
38923 * command's response data will be written. This can be either a host
38924 * physical address (HPA) or a guest physical address (GPA) and must
38925 * point to a physically contiguous block of memory.
38927 uint64_t resp_addr;
38928 /* Physical number of completion ring. */
38932 * When this bit is set to '1', interrupt latency max
38933 * timer is reset whenever a completion is received.
38935 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
38938 * When this bit is set to '1', ring idle mode
38939 * aggregation will be enabled.
38941 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
38944 * Set this flag to 1 when configuring parameters on a
38945 * notification queue. Set this flag to 0 when configuring
38946 * parameters on a completion queue or completion ring.
38948 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
38951 * Number of completions to aggregate before DMA
38952 * during the normal mode.
38954 uint16_t num_cmpl_dma_aggr;
38956 * Number of completions to aggregate before DMA
38957 * during the interrupt mode.
38959 uint16_t num_cmpl_dma_aggr_during_int;
38961 * Timer used to aggregate completions before
38962 * DMA during the normal mode (not in interrupt mode).
38964 uint16_t cmpl_aggr_dma_tmr;
38966 * Timer used to aggregate completions before
38967 * DMA while in interrupt mode.
38969 uint16_t cmpl_aggr_dma_tmr_during_int;
38970 /* Minimum time between two interrupts. */
38971 uint16_t int_lat_tmr_min;
38973 * Maximum wait time spent aggregating
38974 * completions before signaling the interrupt after the
38975 * interrupt is enabled.
38977 uint16_t int_lat_tmr_max;
38979 * Minimum number of completions aggregated before signaling
38982 uint16_t num_cmpl_aggr_int;
38984 * Bitfield that indicates which parameters are to be applied. Only
38985 * required when configuring devices with notification queues, and
38986 * used in that case to set certain parameters on completion queues
38987 * and others on notification queues.
38991 * This bit must be '1' for the num_cmpl_dma_aggr field to be
38994 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
38997 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
39000 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
39003 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
39006 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
39009 * This bit must be '1' for the int_lat_tmr_min field to be
39012 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
39015 * This bit must be '1' for the int_lat_tmr_max field to be
39018 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
39021 * This bit must be '1' for the num_cmpl_aggr_int field to be
39024 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
39026 uint8_t unused_0[4];
39029 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
39030 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
39031 /* The specific error status for the command. */
39032 uint16_t error_code;
39033 /* The HWRM command request type. */
39035 /* The sequence ID from the original command. */
39037 /* The length of the response data in number of bytes. */
39039 uint8_t unused_0[7];
39041 * This field is used in Output records to indicate that the output
39042 * is completely written to RAM. This field should be read as '1'
39043 * to indicate that the output has been completely written.
39044 * When writing a command completion or response to an internal processor,
39045 * the order of writes has to be such that this field is written last.
39050 /***********************
39051 * hwrm_ring_grp_alloc *
39052 ***********************/
39055 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
39056 struct hwrm_ring_grp_alloc_input {
39057 /* The HWRM command request type. */
39060 * The completion ring to send the completion event on. This should
39061 * be the NQ ID returned from the `nq_alloc` HWRM command.
39063 uint16_t cmpl_ring;
39065 * The sequence ID is used by the driver for tracking multiple
39066 * commands. This ID is treated as opaque data by the firmware and
39067 * the value is returned in the `hwrm_resp_hdr` upon completion.
39071 * The target ID of the command:
39072 * * 0x0-0xFFF8 - The function ID
39073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39074 * * 0xFFFD - Reserved for user-space HWRM interface
39077 uint16_t target_id;
39079 * A physical address pointer pointing to a host buffer that the
39080 * command's response data will be written. This can be either a host
39081 * physical address (HPA) or a guest physical address (GPA) and must
39082 * point to a physically contiguous block of memory.
39084 uint64_t resp_addr;
39086 * This value identifies the CR associated with the ring
39091 * This value identifies the main RR associated with the ring
39096 * This value identifies the aggregation RR associated with
39097 * the ring group. If this value is 0xFF... (All Fs), then no
39098 * Aggregation ring will be set.
39102 * This value identifies the statistics context associated
39103 * with the ring group.
39108 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
39109 struct hwrm_ring_grp_alloc_output {
39110 /* The specific error status for the command. */
39111 uint16_t error_code;
39112 /* The HWRM command request type. */
39114 /* The sequence ID from the original command. */
39116 /* The length of the response data in number of bytes. */
39119 * This is the ring group ID value. Use this value to program
39120 * the default ring group for the VNIC or as table entries
39121 * in an RSS/COS context.
39123 uint32_t ring_group_id;
39124 uint8_t unused_0[3];
39126 * This field is used in Output records to indicate that the output
39127 * is completely written to RAM. This field should be read as '1'
39128 * to indicate that the output has been completely written.
39129 * When writing a command completion or response to an internal processor,
39130 * the order of writes has to be such that this field is written last.
39135 /**********************
39136 * hwrm_ring_grp_free *
39137 **********************/
39140 /* hwrm_ring_grp_free_input (size:192b/24B) */
39141 struct hwrm_ring_grp_free_input {
39142 /* The HWRM command request type. */
39145 * The completion ring to send the completion event on. This should
39146 * be the NQ ID returned from the `nq_alloc` HWRM command.
39148 uint16_t cmpl_ring;
39150 * The sequence ID is used by the driver for tracking multiple
39151 * commands. This ID is treated as opaque data by the firmware and
39152 * the value is returned in the `hwrm_resp_hdr` upon completion.
39156 * The target ID of the command:
39157 * * 0x0-0xFFF8 - The function ID
39158 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39159 * * 0xFFFD - Reserved for user-space HWRM interface
39162 uint16_t target_id;
39164 * A physical address pointer pointing to a host buffer that the
39165 * command's response data will be written. This can be either a host
39166 * physical address (HPA) or a guest physical address (GPA) and must
39167 * point to a physically contiguous block of memory.
39169 uint64_t resp_addr;
39170 /* This is the ring group ID value. */
39171 uint32_t ring_group_id;
39172 uint8_t unused_0[4];
39175 /* hwrm_ring_grp_free_output (size:128b/16B) */
39176 struct hwrm_ring_grp_free_output {
39177 /* The specific error status for the command. */
39178 uint16_t error_code;
39179 /* The HWRM command request type. */
39181 /* The sequence ID from the original command. */
39183 /* The length of the response data in number of bytes. */
39185 uint8_t unused_0[7];
39187 * This field is used in Output records to indicate that the output
39188 * is completely written to RAM. This field should be read as '1'
39189 * to indicate that the output has been completely written.
39190 * When writing a command completion or response to an internal processor,
39191 * the order of writes has to be such that this field is written last.
39196 /************************
39197 * hwrm_ring_schq_alloc *
39198 ************************/
39201 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
39202 struct hwrm_ring_schq_alloc_input {
39203 /* The HWRM command request type. */
39206 * The completion ring to send the completion event on. This should
39207 * be the NQ ID returned from the `nq_alloc` HWRM command.
39209 uint16_t cmpl_ring;
39211 * The sequence ID is used by the driver for tracking multiple
39212 * commands. This ID is treated as opaque data by the firmware and
39213 * the value is returned in the `hwrm_resp_hdr` upon completion.
39217 * The target ID of the command:
39218 * * 0x0-0xFFF8 - The function ID
39219 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39220 * * 0xFFFD - Reserved for user-space HWRM interface
39223 uint16_t target_id;
39225 * A physical address pointer pointing to a host buffer that the
39226 * command's response data will be written. This can be either a host
39227 * physical address (HPA) or a guest physical address (GPA) and must
39228 * point to a physically contiguous block of memory.
39230 uint64_t resp_addr;
39233 * This bit must be '1' for the tqm_ring0 fields to be
39236 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
39238 * This bit must be '1' for the tqm_ring1 fields to be
39241 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
39243 * This bit must be '1' for the tqm_ring2 fields to be
39246 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
39248 * This bit must be '1' for the tqm_ring3 fields to be
39251 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
39253 * This bit must be '1' for the tqm_ring4 fields to be
39256 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
39258 * This bit must be '1' for the tqm_ring5 fields to be
39261 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
39263 * This bit must be '1' for the tqm_ring6 fields to be
39266 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
39268 * This bit must be '1' for the tqm_ring7 fields to be
39271 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
39272 /* Reserved for future use. */
39274 /* TQM ring 0 page size and level. */
39275 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
39276 /* TQM ring 0 PBL indirect levels. */
39277 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
39279 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
39280 /* PBL pointer is physical start address. */
39281 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
39283 /* PBL pointer points to PTE table. */
39284 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
39287 * PBL pointer points to PDE table with each entry pointing to PTE
39290 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
39292 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
39293 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
39294 /* TQM ring 0 page size. */
39295 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
39297 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
39299 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
39300 (UINT32_C(0x0) << 4)
39302 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
39303 (UINT32_C(0x1) << 4)
39305 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
39306 (UINT32_C(0x2) << 4)
39308 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
39309 (UINT32_C(0x3) << 4)
39311 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
39312 (UINT32_C(0x4) << 4)
39314 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
39315 (UINT32_C(0x5) << 4)
39316 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
39317 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
39318 /* TQM ring 1 page size and level. */
39319 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
39320 /* TQM ring 1 PBL indirect levels. */
39321 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
39323 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
39324 /* PBL pointer is physical start address. */
39325 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
39327 /* PBL pointer points to PTE table. */
39328 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
39331 * PBL pointer points to PDE table with each entry pointing to PTE
39334 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
39336 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
39337 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
39338 /* TQM ring 1 page size. */
39339 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
39341 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
39343 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
39344 (UINT32_C(0x0) << 4)
39346 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
39347 (UINT32_C(0x1) << 4)
39349 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
39350 (UINT32_C(0x2) << 4)
39352 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
39353 (UINT32_C(0x3) << 4)
39355 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
39356 (UINT32_C(0x4) << 4)
39358 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
39359 (UINT32_C(0x5) << 4)
39360 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
39361 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
39362 /* TQM ring 2 page size and level. */
39363 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
39364 /* TQM ring 2 PBL indirect levels. */
39365 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
39367 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
39368 /* PBL pointer is physical start address. */
39369 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
39371 /* PBL pointer points to PTE table. */
39372 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
39375 * PBL pointer points to PDE table with each entry pointing to PTE
39378 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
39380 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
39381 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
39382 /* TQM ring 2 page size. */
39383 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
39385 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
39387 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
39388 (UINT32_C(0x0) << 4)
39390 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
39391 (UINT32_C(0x1) << 4)
39393 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
39394 (UINT32_C(0x2) << 4)
39396 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
39397 (UINT32_C(0x3) << 4)
39399 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
39400 (UINT32_C(0x4) << 4)
39402 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
39403 (UINT32_C(0x5) << 4)
39404 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
39405 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
39406 /* TQM ring 3 page size and level. */
39407 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
39408 /* TQM ring 3 PBL indirect levels. */
39409 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
39411 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
39412 /* PBL pointer is physical start address. */
39413 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
39415 /* PBL pointer points to PTE table. */
39416 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
39419 * PBL pointer points to PDE table with each entry pointing to PTE
39422 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
39424 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
39425 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
39426 /* TQM ring 3 page size. */
39427 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
39429 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
39431 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
39432 (UINT32_C(0x0) << 4)
39434 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
39435 (UINT32_C(0x1) << 4)
39437 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
39438 (UINT32_C(0x2) << 4)
39440 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
39441 (UINT32_C(0x3) << 4)
39443 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
39444 (UINT32_C(0x4) << 4)
39446 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
39447 (UINT32_C(0x5) << 4)
39448 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
39449 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
39450 /* TQM ring 4 page size and level. */
39451 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
39452 /* TQM ring 4 PBL indirect levels. */
39453 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
39455 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
39456 /* PBL pointer is physical start address. */
39457 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
39459 /* PBL pointer points to PTE table. */
39460 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
39463 * PBL pointer points to PDE table with each entry pointing to PTE
39466 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
39468 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
39469 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
39470 /* TQM ring 4 page size. */
39471 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
39473 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
39475 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
39476 (UINT32_C(0x0) << 4)
39478 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
39479 (UINT32_C(0x1) << 4)
39481 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
39482 (UINT32_C(0x2) << 4)
39484 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
39485 (UINT32_C(0x3) << 4)
39487 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
39488 (UINT32_C(0x4) << 4)
39490 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
39491 (UINT32_C(0x5) << 4)
39492 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
39493 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
39494 /* TQM ring 5 page size and level. */
39495 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
39496 /* TQM ring 5 PBL indirect levels. */
39497 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
39499 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
39500 /* PBL pointer is physical start address. */
39501 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
39503 /* PBL pointer points to PTE table. */
39504 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
39507 * PBL pointer points to PDE table with each entry pointing to PTE
39510 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
39512 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
39513 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
39514 /* TQM ring 5 page size. */
39515 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
39517 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
39519 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
39520 (UINT32_C(0x0) << 4)
39522 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
39523 (UINT32_C(0x1) << 4)
39525 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
39526 (UINT32_C(0x2) << 4)
39528 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
39529 (UINT32_C(0x3) << 4)
39531 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
39532 (UINT32_C(0x4) << 4)
39534 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
39535 (UINT32_C(0x5) << 4)
39536 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
39537 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
39538 /* TQM ring 6 page size and level. */
39539 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
39540 /* TQM ring 6 PBL indirect levels. */
39541 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
39543 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
39544 /* PBL pointer is physical start address. */
39545 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
39547 /* PBL pointer points to PTE table. */
39548 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
39551 * PBL pointer points to PDE table with each entry pointing to PTE
39554 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
39556 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
39557 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
39558 /* TQM ring 6 page size. */
39559 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
39561 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
39563 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
39564 (UINT32_C(0x0) << 4)
39566 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
39567 (UINT32_C(0x1) << 4)
39569 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
39570 (UINT32_C(0x2) << 4)
39572 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
39573 (UINT32_C(0x3) << 4)
39575 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
39576 (UINT32_C(0x4) << 4)
39578 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
39579 (UINT32_C(0x5) << 4)
39580 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
39581 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
39582 /* TQM ring 7 page size and level. */
39583 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
39584 /* TQM ring 7 PBL indirect levels. */
39585 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
39587 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
39588 /* PBL pointer is physical start address. */
39589 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
39591 /* PBL pointer points to PTE table. */
39592 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
39595 * PBL pointer points to PDE table with each entry pointing to PTE
39598 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
39600 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
39601 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
39602 /* TQM ring 7 page size. */
39603 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
39605 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
39607 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
39608 (UINT32_C(0x0) << 4)
39610 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
39611 (UINT32_C(0x1) << 4)
39613 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
39614 (UINT32_C(0x2) << 4)
39616 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
39617 (UINT32_C(0x3) << 4)
39619 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
39620 (UINT32_C(0x4) << 4)
39622 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
39623 (UINT32_C(0x5) << 4)
39624 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
39625 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
39626 /* TQM ring 0 page directory. */
39627 uint64_t tqm_ring0_page_dir;
39628 /* TQM ring 1 page directory. */
39629 uint64_t tqm_ring1_page_dir;
39630 /* TQM ring 2 page directory. */
39631 uint64_t tqm_ring2_page_dir;
39632 /* TQM ring 3 page directory. */
39633 uint64_t tqm_ring3_page_dir;
39634 /* TQM ring 4 page directory. */
39635 uint64_t tqm_ring4_page_dir;
39636 /* TQM ring 5 page directory. */
39637 uint64_t tqm_ring5_page_dir;
39638 /* TQM ring 6 page directory. */
39639 uint64_t tqm_ring6_page_dir;
39640 /* TQM ring 7 page directory. */
39641 uint64_t tqm_ring7_page_dir;
39643 * Number of TQM ring 0 entries.
39645 * TQM fastpath rings should be sized large enough to accommodate the
39646 * maximum number of QPs (either L2 or RoCE, or both if shared)
39647 * that can be enqueued to the TQM ring.
39649 * Note that TQM ring sizes cannot be extended while the system is
39650 * operational. If a PF driver needs to extend a TQM ring, it needs
39651 * to delete the SCHQ and then reallocate it.
39653 uint32_t tqm_ring0_num_entries;
39655 * Number of TQM ring 1 entries.
39657 * TQM fastpath rings should be sized large enough to accommodate the
39658 * maximum number of QPs (either L2 or RoCE, or both if shared)
39659 * that can be enqueued to the TQM ring.
39661 * Note that TQM ring sizes cannot be extended while the system is
39662 * operational. If a PF driver needs to extend a TQM ring, it needs
39663 * to delete the SCHQ and then reallocate it.
39665 uint32_t tqm_ring1_num_entries;
39667 * Number of TQM ring 2 entries.
39669 * TQM fastpath rings should be sized large enough to accommodate the
39670 * maximum number of QPs (either L2 or RoCE, or both if shared)
39671 * that can be enqueued to the TQM ring.
39673 * Note that TQM ring sizes cannot be extended while the system is
39674 * operational. If a PF driver needs to extend a TQM ring, it needs
39675 * to delete the SCHQ and then reallocate it.
39677 uint32_t tqm_ring2_num_entries;
39679 * Number of TQM ring 3 entries.
39681 * TQM fastpath rings should be sized large enough to accommodate the
39682 * maximum number of QPs (either L2 or RoCE, or both if shared)
39683 * that can be enqueued to the TQM ring.
39685 * Note that TQM ring sizes cannot be extended while the system is
39686 * operational. If a PF driver needs to extend a TQM ring, it needs
39687 * to delete the SCHQ and then reallocate it.
39689 uint32_t tqm_ring3_num_entries;
39691 * Number of TQM ring 4 entries.
39693 * TQM fastpath rings should be sized large enough to accommodate the
39694 * maximum number of QPs (either L2 or RoCE, or both if shared)
39695 * that can be enqueued to the TQM ring.
39697 * Note that TQM ring sizes cannot be extended while the system is
39698 * operational. If a PF driver needs to extend a TQM ring, it needs
39699 * to delete the SCHQ and then reallocate it.
39701 uint32_t tqm_ring4_num_entries;
39703 * Number of TQM ring 5 entries.
39705 * TQM fastpath rings should be sized large enough to accommodate the
39706 * maximum number of QPs (either L2 or RoCE, or both if shared)
39707 * that can be enqueued to the TQM ring.
39709 * Note that TQM ring sizes cannot be extended while the system is
39710 * operational. If a PF driver needs to extend a TQM ring, it needs
39711 * to delete the SCHQ and then reallocate it.
39713 uint32_t tqm_ring5_num_entries;
39715 * Number of TQM ring 6 entries.
39717 * TQM fastpath rings should be sized large enough to accommodate the
39718 * maximum number of QPs (either L2 or RoCE, or both if shared)
39719 * that can be enqueued to the TQM ring.
39721 * Note that TQM ring sizes cannot be extended while the system is
39722 * operational. If a PF driver needs to extend a TQM ring, it needs
39723 * to delete the SCHQ and then reallocate it.
39725 uint32_t tqm_ring6_num_entries;
39727 * Number of TQM ring 7 entries.
39729 * TQM fastpath rings should be sized large enough to accommodate the
39730 * maximum number of QPs (either L2 or RoCE, or both if shared)
39731 * that can be enqueued to the TQM ring.
39733 * Note that TQM ring sizes cannot be extended while the system is
39734 * operational. If a PF driver needs to extend a TQM ring, it needs
39735 * to delete the SCHQ and then reallocate it.
39737 uint32_t tqm_ring7_num_entries;
39738 /* Number of bytes that have been allocated for each context entry. */
39739 uint16_t tqm_entry_size;
39740 uint8_t unused_0[6];
39743 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
39744 struct hwrm_ring_schq_alloc_output {
39745 /* The specific error status for the command. */
39746 uint16_t error_code;
39747 /* The HWRM command request type. */
39749 /* The sequence ID from the original command. */
39751 /* The length of the response data in number of bytes. */
39754 * This is an identifier for the SCHQ to be used in other HWRM commands
39755 * that need to reference this SCHQ. This value is greater than zero
39756 * (i.e. a schq_id of zero references the default SCHQ).
39759 uint8_t unused_0[5];
39761 * This field is used in Output records to indicate that the output
39762 * is completely written to RAM. This field should be read as '1'
39763 * to indicate that the output has been completely written.
39764 * When writing a command completion or response to an internal processor,
39765 * the order of writes has to be such that this field is written last.
39770 /**********************
39771 * hwrm_ring_schq_cfg *
39772 **********************/
39775 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
39776 struct hwrm_ring_schq_cfg_input {
39777 /* The HWRM command request type. */
39780 * The completion ring to send the completion event on. This should
39781 * be the NQ ID returned from the `nq_alloc` HWRM command.
39783 uint16_t cmpl_ring;
39785 * The sequence ID is used by the driver for tracking multiple
39786 * commands. This ID is treated as opaque data by the firmware and
39787 * the value is returned in the `hwrm_resp_hdr` upon completion.
39791 * The target ID of the command:
39792 * * 0x0-0xFFF8 - The function ID
39793 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39794 * * 0xFFFD - Reserved for user-space HWRM interface
39797 uint16_t target_id;
39799 * A physical address pointer pointing to a host buffer that the
39800 * command's response data will be written. This can be either a host
39801 * physical address (HPA) or a guest physical address (GPA) and must
39802 * point to a physically contiguous block of memory.
39804 uint64_t resp_addr;
39806 * Identifies the SCHQ being configured. A schq_id of zero refers to
39807 * the default SCHQ.
39811 * This field is an 8 bit bitmap that indicates which TCs are enabled
39812 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
39815 uint8_t tc_enabled;
39818 /* The tc_max_bw array and the max_bw parameters are valid */
39819 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
39821 /* The tc_min_bw array is valid */
39822 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
39824 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39825 uint32_t max_bw_tc0;
39826 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39827 uint32_t max_bw_tc1;
39828 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39829 uint32_t max_bw_tc2;
39830 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39831 uint32_t max_bw_tc3;
39832 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39833 uint32_t max_bw_tc4;
39834 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39835 uint32_t max_bw_tc5;
39836 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39837 uint32_t max_bw_tc6;
39838 /* Maximum bandwidth of the traffic class, specified in Mbps. */
39839 uint32_t max_bw_tc7;
39841 * Bandwidth reservation for the traffic class, specified in Mbps.
39842 * A value of zero signifies that traffic belonging to this class
39843 * shares the bandwidth reservation for the same traffic class of
39844 * the default SCHQ.
39846 uint32_t min_bw_tc0;
39848 * Bandwidth reservation for the traffic class, specified in Mbps.
39849 * A value of zero signifies that traffic belonging to this class
39850 * shares the bandwidth reservation for the same traffic class of
39851 * the default SCHQ.
39853 uint32_t min_bw_tc1;
39855 * Bandwidth reservation for the traffic class, specified in Mbps.
39856 * A value of zero signifies that traffic belonging to this class
39857 * shares the bandwidth reservation for the same traffic class of
39858 * the default SCHQ.
39860 uint32_t min_bw_tc2;
39862 * Bandwidth reservation for the traffic class, specified in Mbps.
39863 * A value of zero signifies that traffic belonging to this class
39864 * shares the bandwidth reservation for the same traffic class of
39865 * the default SCHQ.
39867 uint32_t min_bw_tc3;
39869 * Bandwidth reservation for the traffic class, specified in Mbps.
39870 * A value of zero signifies that traffic belonging to this class
39871 * shares the bandwidth reservation for the same traffic class of
39872 * the default SCHQ.
39874 uint32_t min_bw_tc4;
39876 * Bandwidth reservation for the traffic class, specified in Mbps.
39877 * A value of zero signifies that traffic belonging to this class
39878 * shares the bandwidth reservation for the same traffic class of
39879 * the default SCHQ.
39881 uint32_t min_bw_tc5;
39883 * Bandwidth reservation for the traffic class, specified in Mbps.
39884 * A value of zero signifies that traffic belonging to this class
39885 * shares the bandwidth reservation for the same traffic class of
39886 * the default SCHQ.
39888 uint32_t min_bw_tc6;
39890 * Bandwidth reservation for the traffic class, specified in Mbps.
39891 * A value of zero signifies that traffic belonging to this class
39892 * shares the bandwidth reservation for the same traffic class of
39893 * the default SCHQ.
39895 uint32_t min_bw_tc7;
39897 * Indicates the max bandwidth for all enabled traffic classes in
39898 * this SCHQ, specified in Mbps.
39901 uint8_t unused_1[4];
39904 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
39905 struct hwrm_ring_schq_cfg_output {
39906 /* The specific error status for the command. */
39907 uint16_t error_code;
39908 /* The HWRM command request type. */
39910 /* The sequence ID from the original command. */
39912 /* The length of the response data in number of bytes. */
39914 uint8_t unused_0[7];
39916 * This field is used in Output records to indicate that the output
39917 * is completely written to RAM. This field should be read as '1'
39918 * to indicate that the output has been completely written.
39919 * When writing a command completion or response to an internal processor,
39920 * the order of writes has to be such that this field is written last.
39925 /***********************
39926 * hwrm_ring_schq_free *
39927 ***********************/
39930 /* hwrm_ring_schq_free_input (size:192b/24B) */
39931 struct hwrm_ring_schq_free_input {
39932 /* The HWRM command request type. */
39935 * The completion ring to send the completion event on. This should
39936 * be the NQ ID returned from the `nq_alloc` HWRM command.
39938 uint16_t cmpl_ring;
39940 * The sequence ID is used by the driver for tracking multiple
39941 * commands. This ID is treated as opaque data by the firmware and
39942 * the value is returned in the `hwrm_resp_hdr` upon completion.
39946 * The target ID of the command:
39947 * * 0x0-0xFFF8 - The function ID
39948 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39949 * * 0xFFFD - Reserved for user-space HWRM interface
39952 uint16_t target_id;
39954 * A physical address pointer pointing to a host buffer that the
39955 * command's response data will be written. This can be either a host
39956 * physical address (HPA) or a guest physical address (GPA) and must
39957 * point to a physically contiguous block of memory.
39959 uint64_t resp_addr;
39960 /* Identifies the SCHQ being freed. */
39962 uint8_t unused_0[6];
39965 /* hwrm_ring_schq_free_output (size:128b/16B) */
39966 struct hwrm_ring_schq_free_output {
39967 /* The specific error status for the command. */
39968 uint16_t error_code;
39969 /* The HWRM command request type. */
39971 /* The sequence ID from the original command. */
39973 /* The length of the response data in number of bytes. */
39975 uint8_t unused_0[7];
39977 * This field is used in Output records to indicate that the output
39978 * is completely written to RAM. This field should be read as '1'
39979 * to indicate that the output has been completely written.
39980 * When writing a command completion or response to an internal processor,
39981 * the order of writes has to be such that this field is written last.
39986 * special reserved flow ID to identify per function default
39987 * flows for vSwitch offload
39989 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
39991 * special reserved flow ID to identify per function RoCEv1
39994 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
39996 * special reserved flow ID to identify per function RoCEv2
39999 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
40001 * special reserved flow ID to identify per function RoCEv2
40004 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
40006 /****************************
40007 * hwrm_cfa_l2_filter_alloc *
40008 ****************************/
40011 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
40012 struct hwrm_cfa_l2_filter_alloc_input {
40013 /* The HWRM command request type. */
40016 * The completion ring to send the completion event on. This should
40017 * be the NQ ID returned from the `nq_alloc` HWRM command.
40019 uint16_t cmpl_ring;
40021 * The sequence ID is used by the driver for tracking multiple
40022 * commands. This ID is treated as opaque data by the firmware and
40023 * the value is returned in the `hwrm_resp_hdr` upon completion.
40027 * The target ID of the command:
40028 * * 0x0-0xFFF8 - The function ID
40029 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40030 * * 0xFFFD - Reserved for user-space HWRM interface
40033 uint16_t target_id;
40035 * A physical address pointer pointing to a host buffer that the
40036 * command's response data will be written. This can be either a host
40037 * physical address (HPA) or a guest physical address (GPA) and must
40038 * point to a physically contiguous block of memory.
40040 uint64_t resp_addr;
40043 * Enumeration denoting the RX, TX type of the resource.
40044 * This enumeration is used for resources that are similar for both
40045 * TX and RX paths of the chip.
40047 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
40050 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
40053 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
40055 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
40056 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
40058 * Setting of this flag indicates the applicability to the loopback
40061 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
40064 * Setting of this flag indicates drop action. If this flag is not
40065 * set, then it should be considered accept action.
40067 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
40070 * If this flag is set, all t_l2_* fields are invalid
40071 * and they should not be specified.
40072 * If this flag is set, then l2_* fields refer to
40073 * fields of outermost L2 header.
40075 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
40078 * Enumeration denoting NO_ROCE_L2 to support old drivers.
40079 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
40081 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
40083 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
40084 /* To support old drivers */
40085 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
40086 (UINT32_C(0x0) << 4)
40087 /* Only L2 traffic */
40088 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
40089 (UINT32_C(0x1) << 4)
40090 /* Roce & L2 traffic */
40091 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
40092 (UINT32_C(0x2) << 4)
40093 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
40094 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
40096 * Setting of this flag indicates that no XDP filter is created with
40098 * 0 - legacy behavior, XDP filter is created with L2 filter
40099 * 1 - XDP filter won't be created with L2 filter
40101 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
40104 * Setting this flag to 1 indicate the L2 fields in this command
40105 * pertain to source fields. Setting this flag to 0 indicate the
40106 * L2 fields in this command pertain to the destination fields
40107 * and this is the default/legacy behavior.
40109 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
40113 * This bit must be '1' for the l2_addr field to be
40116 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
40119 * This bit must be '1' for the l2_addr_mask field to be
40122 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
40125 * This bit must be '1' for the l2_ovlan field to be
40128 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
40131 * This bit must be '1' for the l2_ovlan_mask field to be
40134 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
40137 * This bit must be '1' for the l2_ivlan field to be
40140 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
40143 * This bit must be '1' for the l2_ivlan_mask field to be
40146 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
40149 * This bit must be '1' for the t_l2_addr field to be
40152 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
40155 * This bit must be '1' for the t_l2_addr_mask field to be
40158 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
40161 * This bit must be '1' for the t_l2_ovlan field to be
40164 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
40167 * This bit must be '1' for the t_l2_ovlan_mask field to be
40170 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
40173 * This bit must be '1' for the t_l2_ivlan field to be
40176 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
40179 * This bit must be '1' for the t_l2_ivlan_mask field to be
40182 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
40185 * This bit must be '1' for the src_type field to be
40188 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
40191 * This bit must be '1' for the src_id field to be
40194 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
40197 * This bit must be '1' for the tunnel_type field to be
40200 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
40203 * This bit must be '1' for the dst_id field to be
40206 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
40209 * This bit must be '1' for the mirror_vnic_id field to be
40212 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
40215 * This bit must be '1' for the num_vlans field to be
40218 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
40221 * This bit must be '1' for the t_num_vlans field to be
40224 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
40227 * This value sets the match value for the L2 MAC address.
40228 * Destination MAC address for RX path.
40229 * Source MAC address for TX path.
40231 uint8_t l2_addr[6];
40232 /* This value sets the match value for the number of VLANs. */
40235 * This value sets the match value for the number of VLANs
40236 * in the tunnel headers.
40238 uint8_t t_num_vlans;
40240 * This value sets the mask value for the L2 address.
40241 * A value of 0 will mask the corresponding bit from
40244 uint8_t l2_addr_mask[6];
40245 /* This value sets VLAN ID value for outer VLAN. */
40248 * This value sets the mask value for the ovlan id.
40249 * A value of 0 will mask the corresponding bit from
40252 uint16_t l2_ovlan_mask;
40253 /* This value sets VLAN ID value for inner VLAN. */
40256 * This value sets the mask value for the ivlan id.
40257 * A value of 0 will mask the corresponding bit from
40260 uint16_t l2_ivlan_mask;
40261 uint8_t unused_1[2];
40263 * This value sets the match value for the tunnel
40265 * Destination MAC address for RX path.
40266 * Source MAC address for TX path.
40268 uint8_t t_l2_addr[6];
40269 uint8_t unused_2[2];
40271 * This value sets the mask value for the tunnel L2
40273 * A value of 0 will mask the corresponding bit from
40276 uint8_t t_l2_addr_mask[6];
40277 /* This value sets VLAN ID value for tunnel outer VLAN. */
40278 uint16_t t_l2_ovlan;
40280 * This value sets the mask value for the tunnel ovlan id.
40281 * A value of 0 will mask the corresponding bit from
40284 uint16_t t_l2_ovlan_mask;
40285 /* This value sets VLAN ID value for tunnel inner VLAN. */
40286 uint16_t t_l2_ivlan;
40288 * This value sets the mask value for the tunnel ivlan id.
40289 * A value of 0 will mask the corresponding bit from
40292 uint16_t t_l2_ivlan_mask;
40293 /* This value identifies the type of source of the packet. */
40296 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
40297 /* Physical function */
40298 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
40299 /* Virtual function */
40300 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
40301 /* Virtual NIC of a function */
40302 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
40303 /* Embedded processor for CFA management */
40304 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
40305 /* Embedded processor for OOB management */
40306 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
40307 /* Embedded processor for RoCE */
40308 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
40309 /* Embedded processor for network proxy functions */
40310 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
40311 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
40312 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
40315 * This value is the id of the source.
40316 * For a network port, it represents port_id.
40317 * For a physical function, it represents fid.
40318 * For a virtual function, it represents vf_id.
40319 * For a vnic, it represents vnic_id.
40320 * For embedded processors, this id is not valid.
40323 * 1. The function ID is implied if it src_id is
40324 * not provided for a src_type that is either
40328 uint8_t tunnel_type;
40330 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
40332 /* Virtual eXtensible Local Area Network (VXLAN) */
40333 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
40335 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
40336 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
40338 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
40339 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
40342 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
40344 /* Generic Network Virtualization Encapsulation (Geneve) */
40345 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
40347 /* Multi-Protocol Label Switching (MPLS) */
40348 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
40350 /* Stateless Transport Tunnel (STT) */
40351 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
40353 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
40354 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
40356 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
40357 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
40360 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
40363 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
40365 /* Use fixed layer 2 ether type of 0xFFFF */
40366 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
40369 * IPV6 over virtual eXtensible Local Area Network with GPE header
40372 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
40374 /* Any tunneled traffic */
40375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
40377 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
40378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
40381 * If set, this value shall represent the
40382 * Logical VNIC ID of the destination VNIC for the RX
40383 * path and network port id of the destination port for
40388 * Logical VNIC ID of the VNIC where traffic is
40391 uint16_t mirror_vnic_id;
40393 * This hint is provided to help in placing
40394 * the filter in the filter table.
40397 /* No preference */
40398 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
40400 /* Above the given filter */
40401 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
40403 /* Below the given filter */
40404 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
40406 /* As high as possible */
40407 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
40409 /* As low as possible */
40410 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
40412 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
40413 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
40417 * This is the ID of the filter that goes along with
40420 * This field is valid only for the following values.
40421 * 1 - Above the given filter
40422 * 2 - Below the given filter
40424 uint64_t l2_filter_id_hint;
40427 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
40428 struct hwrm_cfa_l2_filter_alloc_output {
40429 /* The specific error status for the command. */
40430 uint16_t error_code;
40431 /* The HWRM command request type. */
40433 /* The sequence ID from the original command. */
40435 /* The length of the response data in number of bytes. */
40438 * This value identifies a set of CFA data structures used for an L2
40441 uint64_t l2_filter_id;
40443 * The flow id value in bit 0-29 is the actual ID of the flow
40444 * associated with this filter and it shall be used to match
40445 * and associate the flow identifier returned in completion
40446 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
40447 * shall indicate no valid flow id.
40450 /* Indicate the flow id value. */
40451 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
40452 UINT32_C(0x3fffffff)
40453 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
40454 /* Indicate type of the flow. */
40455 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
40456 UINT32_C(0x40000000)
40458 * If this bit set to 0, then it indicates that the flow is
40461 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
40462 (UINT32_C(0x0) << 30)
40464 * If this bit is set to 1, then it indicates that the flow is
40467 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
40468 (UINT32_C(0x1) << 30)
40469 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
40470 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
40471 /* Indicate the flow direction. */
40472 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
40473 UINT32_C(0x80000000)
40474 /* If this bit set to 0, then it indicates rx flow. */
40475 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
40476 (UINT32_C(0x0) << 31)
40477 /* If this bit is set to 1, then it indicates that tx flow. */
40478 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
40479 (UINT32_C(0x1) << 31)
40480 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
40481 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
40482 uint8_t unused_0[3];
40484 * This field is used in Output records to indicate that the output
40485 * is completely written to RAM. This field should be read as '1'
40486 * to indicate that the output has been completely written.
40487 * When writing a command completion or response to an internal
40488 * processor, the order of writes has to be such that this field is
40494 /***************************
40495 * hwrm_cfa_l2_filter_free *
40496 ***************************/
40499 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
40500 struct hwrm_cfa_l2_filter_free_input {
40501 /* The HWRM command request type. */
40504 * The completion ring to send the completion event on. This should
40505 * be the NQ ID returned from the `nq_alloc` HWRM command.
40507 uint16_t cmpl_ring;
40509 * The sequence ID is used by the driver for tracking multiple
40510 * commands. This ID is treated as opaque data by the firmware and
40511 * the value is returned in the `hwrm_resp_hdr` upon completion.
40515 * The target ID of the command:
40516 * * 0x0-0xFFF8 - The function ID
40517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40518 * * 0xFFFD - Reserved for user-space HWRM interface
40521 uint16_t target_id;
40523 * A physical address pointer pointing to a host buffer that the
40524 * command's response data will be written. This can be either a host
40525 * physical address (HPA) or a guest physical address (GPA) and must
40526 * point to a physically contiguous block of memory.
40528 uint64_t resp_addr;
40530 * This value identifies a set of CFA data structures used for an L2
40533 uint64_t l2_filter_id;
40536 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
40537 struct hwrm_cfa_l2_filter_free_output {
40538 /* The specific error status for the command. */
40539 uint16_t error_code;
40540 /* The HWRM command request type. */
40542 /* The sequence ID from the original command. */
40544 /* The length of the response data in number of bytes. */
40546 uint8_t unused_0[7];
40548 * This field is used in Output records to indicate that the output
40549 * is completely written to RAM. This field should be read as '1'
40550 * to indicate that the output has been completely written.
40551 * When writing a command completion or response to an internal
40552 * processor, the order of writes has to be such that this field is
40558 /**************************
40559 * hwrm_cfa_l2_filter_cfg *
40560 **************************/
40563 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
40564 struct hwrm_cfa_l2_filter_cfg_input {
40565 /* The HWRM command request type. */
40568 * The completion ring to send the completion event on. This should
40569 * be the NQ ID returned from the `nq_alloc` HWRM command.
40571 uint16_t cmpl_ring;
40573 * The sequence ID is used by the driver for tracking multiple
40574 * commands. This ID is treated as opaque data by the firmware and
40575 * the value is returned in the `hwrm_resp_hdr` upon completion.
40579 * The target ID of the command:
40580 * * 0x0-0xFFF8 - The function ID
40581 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40582 * * 0xFFFD - Reserved for user-space HWRM interface
40585 uint16_t target_id;
40587 * A physical address pointer pointing to a host buffer that the
40588 * command's response data will be written. This can be either a host
40589 * physical address (HPA) or a guest physical address (GPA) and must
40590 * point to a physically contiguous block of memory.
40592 uint64_t resp_addr;
40595 * Enumeration denoting the RX, TX type of the resource.
40596 * This enumeration is used for resources that are similar for both
40597 * TX and RX paths of the chip.
40599 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
40602 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
40605 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
40607 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
40608 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
40610 * Setting of this flag indicates drop action. If this flag is not
40611 * set, then it should be considered accept action.
40613 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
40616 * Enumeration denoting NO_ROCE_L2 to support old drivers.
40617 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
40619 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
40621 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
40622 /* To support old drivers */
40623 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
40624 (UINT32_C(0x0) << 2)
40625 /* Only L2 traffic */
40626 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
40627 (UINT32_C(0x1) << 2)
40628 /* Roce & L2 traffic */
40629 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
40630 (UINT32_C(0x2) << 2)
40631 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
40632 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
40635 * This bit must be '1' for the dst_id field to be
40638 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
40641 * This bit must be '1' for the new_mirror_vnic_id field to be
40644 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
40647 * This value identifies a set of CFA data structures used for an L2
40650 uint64_t l2_filter_id;
40652 * If set, this value shall represent the
40653 * Logical VNIC ID of the destination VNIC for the RX
40654 * path and network port id of the destination port for
40659 * New Logical VNIC ID of the VNIC where traffic is
40662 uint32_t new_mirror_vnic_id;
40665 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
40666 struct hwrm_cfa_l2_filter_cfg_output {
40667 /* The specific error status for the command. */
40668 uint16_t error_code;
40669 /* The HWRM command request type. */
40671 /* The sequence ID from the original command. */
40673 /* The length of the response data in number of bytes. */
40675 uint8_t unused_0[7];
40677 * This field is used in Output records to indicate that the output
40678 * is completely written to RAM. This field should be read as '1'
40679 * to indicate that the output has been completely written.
40680 * When writing a command completion or response to an internal
40681 * processor, the order of writes has to be such that this field is
40687 /***************************
40688 * hwrm_cfa_l2_set_rx_mask *
40689 ***************************/
40692 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
40693 struct hwrm_cfa_l2_set_rx_mask_input {
40694 /* The HWRM command request type. */
40697 * The completion ring to send the completion event on. This should
40698 * be the NQ ID returned from the `nq_alloc` HWRM command.
40700 uint16_t cmpl_ring;
40702 * The sequence ID is used by the driver for tracking multiple
40703 * commands. This ID is treated as opaque data by the firmware and
40704 * the value is returned in the `hwrm_resp_hdr` upon completion.
40708 * The target ID of the command:
40709 * * 0x0-0xFFF8 - The function ID
40710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40711 * * 0xFFFD - Reserved for user-space HWRM interface
40714 uint16_t target_id;
40716 * A physical address pointer pointing to a host buffer that the
40717 * command's response data will be written. This can be either a host
40718 * physical address (HPA) or a guest physical address (GPA) and must
40719 * point to a physically contiguous block of memory.
40721 uint64_t resp_addr;
40726 * When this bit is '1', the function is requested to accept
40727 * multi-cast packets specified by the multicast addr table.
40729 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
40732 * When this bit is '1', the function is requested to accept
40733 * all multi-cast packets.
40735 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
40738 * When this bit is '1', the function is requested to accept
40739 * broadcast packets.
40741 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
40744 * When this bit is '1', the function is requested to be
40745 * put in the promiscuous mode.
40747 * The HWRM should accept any function to set up
40748 * promiscuous mode.
40750 * The HWRM shall follow the semantics below for the
40751 * promiscuous mode support.
40752 * # When partitioning is not enabled on a port
40753 * (i.e. single PF on the port), then the PF shall
40754 * be allowed to be in the promiscuous mode. When the
40755 * PF is in the promiscuous mode, then it shall
40756 * receive all host bound traffic on that port.
40757 * # When partitioning is enabled on a port
40758 * (i.e. multiple PFs per port) and a PF on that
40759 * port is in the promiscuous mode, then the PF
40760 * receives all traffic within that partition as
40761 * identified by a unique identifier for the
40762 * PF (e.g. S-Tag). If a unique outer VLAN
40763 * for the PF is specified, then the setting of
40764 * promiscuous mode on that PF shall result in the
40765 * PF receiving all host bound traffic with matching
40767 * # A VF shall can be set in the promiscuous mode.
40768 * In the promiscuous mode, the VF does not receive any
40769 * traffic unless a unique outer VLAN for the
40770 * VF is specified. If a unique outer VLAN
40771 * for the VF is specified, then the setting of
40772 * promiscuous mode on that VF shall result in the
40773 * VF receiving all host bound traffic with the
40774 * matching outer VLAN.
40775 * # The HWRM shall allow the setting of promiscuous
40776 * mode on a function independently from the
40777 * promiscuous mode settings on other functions.
40779 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
40782 * If this flag is set, the corresponding RX
40783 * filters shall be set up to cover multicast/broadcast
40784 * filters for the outermost Layer 2 destination MAC
40787 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
40790 * If this flag is set, the corresponding RX
40791 * filters shall be set up to cover multicast/broadcast
40792 * filters for the VLAN-tagged packets that match the
40793 * TPID and VID fields of VLAN tags in the VLAN tag
40794 * table specified in this command.
40796 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
40799 * If this flag is set, the corresponding RX
40800 * filters shall be set up to cover multicast/broadcast
40801 * filters for non-VLAN tagged packets and VLAN-tagged
40802 * packets that match the TPID and VID fields of VLAN
40803 * tags in the VLAN tag table specified in this command.
40805 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
40808 * If this flag is set, the corresponding RX
40809 * filters shall be set up to cover multicast/broadcast
40810 * filters for non-VLAN tagged packets and VLAN-tagged
40811 * packets matching any VLAN tag.
40813 * If this flag is set, then the HWRM shall ignore
40814 * VLAN tags specified in vlan_tag_tbl.
40816 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
40817 * flags is set, then the HWRM shall ignore
40818 * VLAN tags specified in vlan_tag_tbl.
40820 * The HWRM client shall set at most one flag out of
40821 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
40823 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
40825 /* This is the address for mcast address tbl. */
40826 uint64_t mc_tbl_addr;
40828 * This value indicates how many entries in mc_tbl are valid.
40829 * Each entry is 6 bytes.
40831 uint32_t num_mc_entries;
40832 uint8_t unused_0[4];
40834 * This is the address for VLAN tag table.
40835 * Each VLAN entry in the table is 4 bytes of a VLAN tag
40836 * including TPID, PCP, DEI, and VID fields in network byte
40839 uint64_t vlan_tag_tbl_addr;
40841 * This value indicates how many entries in vlan_tag_tbl are
40842 * valid. Each entry is 4 bytes.
40844 uint32_t num_vlan_tags;
40845 uint8_t unused_1[4];
40848 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
40849 struct hwrm_cfa_l2_set_rx_mask_output {
40850 /* The specific error status for the command. */
40851 uint16_t error_code;
40852 /* The HWRM command request type. */
40854 /* The sequence ID from the original command. */
40856 /* The length of the response data in number of bytes. */
40858 uint8_t unused_0[7];
40860 * This field is used in Output records to indicate that the output
40861 * is completely written to RAM. This field should be read as '1'
40862 * to indicate that the output has been completely written.
40863 * When writing a command completion or response to an internal
40864 * processor, the order of writes has to be such that this field is
40870 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
40871 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
40873 * command specific error codes that goes to
40874 * the cmd_err field in Common HWRM Error Response.
40877 /* Unknown error */
40878 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
40880 /* Unable to complete operation due to conflict with Ntuple Filter */
40881 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
40883 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
40884 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
40885 uint8_t unused_0[7];
40888 /*******************************
40889 * hwrm_cfa_vlan_antispoof_cfg *
40890 *******************************/
40893 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
40894 struct hwrm_cfa_vlan_antispoof_cfg_input {
40895 /* The HWRM command request type. */
40898 * The completion ring to send the completion event on. This should
40899 * be the NQ ID returned from the `nq_alloc` HWRM command.
40901 uint16_t cmpl_ring;
40903 * The sequence ID is used by the driver for tracking multiple
40904 * commands. This ID is treated as opaque data by the firmware and
40905 * the value is returned in the `hwrm_resp_hdr` upon completion.
40909 * The target ID of the command:
40910 * * 0x0-0xFFF8 - The function ID
40911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40912 * * 0xFFFD - Reserved for user-space HWRM interface
40915 uint16_t target_id;
40917 * A physical address pointer pointing to a host buffer that the
40918 * command's response data will be written. This can be either a host
40919 * physical address (HPA) or a guest physical address (GPA) and must
40920 * point to a physically contiguous block of memory.
40922 uint64_t resp_addr;
40924 * Function ID of the function that is being configured.
40925 * Only valid for a VF FID configured by the PF.
40928 uint8_t unused_0[2];
40929 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
40930 uint32_t num_vlan_entries;
40932 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
40933 * antispoof table. Each table entry contains the 16-bit TPID
40934 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
40935 * all in network order to match hwrm_cfa_l2_set_rx_mask.
40936 * For an individual VLAN entry, the mask value should be 0xfff
40937 * for the 12-bit VLAN ID.
40939 uint64_t vlan_tag_mask_tbl_addr;
40942 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
40943 struct hwrm_cfa_vlan_antispoof_cfg_output {
40944 /* The specific error status for the command. */
40945 uint16_t error_code;
40946 /* The HWRM command request type. */
40948 /* The sequence ID from the original command. */
40950 /* The length of the response data in number of bytes. */
40952 uint8_t unused_0[7];
40954 * This field is used in Output records to indicate that the output
40955 * is completely written to RAM. This field should be read as '1'
40956 * to indicate that the output has been completely written.
40957 * When writing a command completion or response to an internal
40958 * processor, the order of writes has to be such that this field is
40964 /********************************
40965 * hwrm_cfa_vlan_antispoof_qcfg *
40966 ********************************/
40969 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
40970 struct hwrm_cfa_vlan_antispoof_qcfg_input {
40971 /* The HWRM command request type. */
40974 * The completion ring to send the completion event on. This should
40975 * be the NQ ID returned from the `nq_alloc` HWRM command.
40977 uint16_t cmpl_ring;
40979 * The sequence ID is used by the driver for tracking multiple
40980 * commands. This ID is treated as opaque data by the firmware and
40981 * the value is returned in the `hwrm_resp_hdr` upon completion.
40985 * The target ID of the command:
40986 * * 0x0-0xFFF8 - The function ID
40987 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40988 * * 0xFFFD - Reserved for user-space HWRM interface
40991 uint16_t target_id;
40993 * A physical address pointer pointing to a host buffer that the
40994 * command's response data will be written. This can be either a host
40995 * physical address (HPA) or a guest physical address (GPA) and must
40996 * point to a physically contiguous block of memory.
40998 uint64_t resp_addr;
41000 * Function ID of the function that is being queried.
41001 * Only valid for a VF FID queried by the PF.
41004 uint8_t unused_0[2];
41006 * Maximum number of VLAN entries the firmware is allowed to DMA
41007 * to vlan_tag_mask_tbl.
41009 uint32_t max_vlan_entries;
41011 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
41012 * antispoof table to which firmware will DMA to. Each table
41013 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
41014 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
41015 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
41016 * the mask value should be 0xfff for the 12-bit VLAN ID.
41018 uint64_t vlan_tag_mask_tbl_addr;
41021 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
41022 struct hwrm_cfa_vlan_antispoof_qcfg_output {
41023 /* The specific error status for the command. */
41024 uint16_t error_code;
41025 /* The HWRM command request type. */
41027 /* The sequence ID from the original command. */
41029 /* The length of the response data in number of bytes. */
41031 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
41032 uint32_t num_vlan_entries;
41033 uint8_t unused_0[3];
41035 * This field is used in Output records to indicate that the output
41036 * is completely written to RAM. This field should be read as '1'
41037 * to indicate that the output has been completely written.
41038 * When writing a command completion or response to an internal
41039 * processor, the order of writes has to be such that this field is
41045 /********************************
41046 * hwrm_cfa_tunnel_filter_alloc *
41047 ********************************/
41050 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
41051 struct hwrm_cfa_tunnel_filter_alloc_input {
41052 /* The HWRM command request type. */
41055 * The completion ring to send the completion event on. This should
41056 * be the NQ ID returned from the `nq_alloc` HWRM command.
41058 uint16_t cmpl_ring;
41060 * The sequence ID is used by the driver for tracking multiple
41061 * commands. This ID is treated as opaque data by the firmware and
41062 * the value is returned in the `hwrm_resp_hdr` upon completion.
41066 * The target ID of the command:
41067 * * 0x0-0xFFF8 - The function ID
41068 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41069 * * 0xFFFD - Reserved for user-space HWRM interface
41072 uint16_t target_id;
41074 * A physical address pointer pointing to a host buffer that the
41075 * command's response data will be written. This can be either a host
41076 * physical address (HPA) or a guest physical address (GPA) and must
41077 * point to a physically contiguous block of memory.
41079 uint64_t resp_addr;
41082 * Setting of this flag indicates the applicability to the loopback
41085 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
41089 * This bit must be '1' for the l2_filter_id field to be
41092 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
41095 * This bit must be '1' for the l2_addr field to be
41098 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
41101 * This bit must be '1' for the l2_ivlan field to be
41104 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
41107 * This bit must be '1' for the l3_addr field to be
41110 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
41113 * This bit must be '1' for the l3_addr_type field to be
41116 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
41119 * This bit must be '1' for the t_l3_addr_type field to be
41122 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
41125 * This bit must be '1' for the t_l3_addr field to be
41128 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
41131 * This bit must be '1' for the tunnel_type field to be
41134 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
41137 * This bit must be '1' for the vni field to be
41140 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
41143 * This bit must be '1' for the dst_vnic_id field to be
41146 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
41149 * This bit must be '1' for the mirror_vnic_id field to be
41152 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
41155 * This value identifies a set of CFA data structures used for an L2
41158 uint64_t l2_filter_id;
41160 * This value sets the match value for the inner L2
41162 * Destination MAC address for RX path.
41163 * Source MAC address for TX path.
41165 uint8_t l2_addr[6];
41167 * This value sets VLAN ID value for inner VLAN.
41168 * Only 12-bits of VLAN ID are used in setting the filter.
41172 * The value of inner destination IP address to be used in filtering.
41173 * For IPv4, first four bytes represent the IP address.
41175 uint32_t l3_addr[4];
41177 * The value of tunnel destination IP address to be used in filtering.
41178 * For IPv4, first four bytes represent the IP address.
41180 uint32_t t_l3_addr[4];
41182 * This value indicates the type of inner IP address.
41185 * All others are invalid.
41187 uint8_t l3_addr_type;
41189 * This value indicates the type of tunnel IP address.
41192 * All others are invalid.
41194 uint8_t t_l3_addr_type;
41196 uint8_t tunnel_type;
41198 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
41200 /* Virtual eXtensible Local Area Network (VXLAN) */
41201 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
41203 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41204 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
41206 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41207 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
41210 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
41212 /* Generic Network Virtualization Encapsulation (Geneve) */
41213 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
41215 /* Multi-Protocol Label Switching (MPLS) */
41216 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
41218 /* Stateless Transport Tunnel (STT) */
41219 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
41221 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41222 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
41224 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41225 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
41228 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41231 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
41233 /* Use fixed layer 2 ether type of 0xFFFF */
41234 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
41237 * IPV6 over virtual eXtensible Local Area Network with GPE header
41240 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
41242 /* Any tunneled traffic */
41243 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
41245 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
41246 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
41248 * tunnel_flags allows the user to indicate the tunnel tag detection
41249 * for the tunnel type specified in tunnel_type.
41251 uint8_t tunnel_flags;
41253 * If the tunnel_type is geneve, then this bit indicates if we
41254 * need to match the geneve OAM packet.
41255 * If the tunnel_type is nvgre or gre, then this bit indicates if
41256 * we need to detect checksum present bit in geneve header.
41257 * If the tunnel_type is mpls, then this bit indicates if we need
41258 * to match mpls packet with explicit IPV4/IPV6 null header.
41260 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
41263 * If the tunnel_type is geneve, then this bit indicates if we
41264 * need to detect the critical option bit set in the oam packet.
41265 * If the tunnel_type is nvgre or gre, then this bit indicates
41266 * if we need to match nvgre packets with key present bit set in
41268 * If the tunnel_type is mpls, then this bit indicates if we
41269 * need to match mpls packet with S bit from inner/second label.
41271 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
41274 * If the tunnel_type is geneve, then this bit indicates if we
41275 * need to match geneve packet with extended header bit set in
41277 * If the tunnel_type is nvgre or gre, then this bit indicates
41278 * if we need to match nvgre packets with sequence number
41279 * present bit set in gre header.
41280 * If the tunnel_type is mpls, then this bit indicates if we
41281 * need to match mpls packet with S bit from out/first label.
41283 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
41286 * Virtual Network Identifier (VNI). Only valid with
41287 * tunnel_types VXLAN, NVGRE, and Geneve.
41288 * Only lower 24-bits of VNI field are used
41289 * in setting up the filter.
41292 /* Logical VNIC ID of the destination VNIC. */
41293 uint32_t dst_vnic_id;
41295 * Logical VNIC ID of the VNIC where traffic is
41298 uint32_t mirror_vnic_id;
41301 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
41302 struct hwrm_cfa_tunnel_filter_alloc_output {
41303 /* The specific error status for the command. */
41304 uint16_t error_code;
41305 /* The HWRM command request type. */
41307 /* The sequence ID from the original command. */
41309 /* The length of the response data in number of bytes. */
41311 /* This value is an opaque id into CFA data structures. */
41312 uint64_t tunnel_filter_id;
41314 * The flow id value in bit 0-29 is the actual ID of the flow
41315 * associated with this filter and it shall be used to match
41316 * and associate the flow identifier returned in completion
41317 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
41318 * shall indicate no valid flow id.
41321 /* Indicate the flow id value. */
41322 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
41323 UINT32_C(0x3fffffff)
41324 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
41325 /* Indicate type of the flow. */
41326 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
41327 UINT32_C(0x40000000)
41329 * If this bit set to 0, then it indicates that the flow is
41332 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
41333 (UINT32_C(0x0) << 30)
41335 * If this bit is set to 1, then it indicates that the flow is
41338 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
41339 (UINT32_C(0x1) << 30)
41340 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
41341 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
41342 /* Indicate the flow direction. */
41343 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
41344 UINT32_C(0x80000000)
41345 /* If this bit set to 0, then it indicates rx flow. */
41346 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
41347 (UINT32_C(0x0) << 31)
41348 /* If this bit is set to 1, then it indicates that tx flow. */
41349 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
41350 (UINT32_C(0x1) << 31)
41351 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
41352 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
41353 uint8_t unused_0[3];
41355 * This field is used in Output records to indicate that the output
41356 * is completely written to RAM. This field should be read as '1'
41357 * to indicate that the output has been completely written.
41358 * When writing a command completion or response to an internal
41359 * processor, the order of writes has to be such that this field is
41365 /*******************************
41366 * hwrm_cfa_tunnel_filter_free *
41367 *******************************/
41370 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
41371 struct hwrm_cfa_tunnel_filter_free_input {
41372 /* The HWRM command request type. */
41375 * The completion ring to send the completion event on. This should
41376 * be the NQ ID returned from the `nq_alloc` HWRM command.
41378 uint16_t cmpl_ring;
41380 * The sequence ID is used by the driver for tracking multiple
41381 * commands. This ID is treated as opaque data by the firmware and
41382 * the value is returned in the `hwrm_resp_hdr` upon completion.
41386 * The target ID of the command:
41387 * * 0x0-0xFFF8 - The function ID
41388 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41389 * * 0xFFFD - Reserved for user-space HWRM interface
41392 uint16_t target_id;
41394 * A physical address pointer pointing to a host buffer that the
41395 * command's response data will be written. This can be either a host
41396 * physical address (HPA) or a guest physical address (GPA) and must
41397 * point to a physically contiguous block of memory.
41399 uint64_t resp_addr;
41400 /* This value is an opaque id into CFA data structures. */
41401 uint64_t tunnel_filter_id;
41404 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
41405 struct hwrm_cfa_tunnel_filter_free_output {
41406 /* The specific error status for the command. */
41407 uint16_t error_code;
41408 /* The HWRM command request type. */
41410 /* The sequence ID from the original command. */
41412 /* The length of the response data in number of bytes. */
41414 uint8_t unused_0[7];
41416 * This field is used in Output records to indicate that the output
41417 * is completely written to RAM. This field should be read as '1'
41418 * to indicate that the output has been completely written.
41419 * When writing a command completion or response to an internal
41420 * processor, the order of writes has to be such that this field is
41426 /***************************************
41427 * hwrm_cfa_redirect_tunnel_type_alloc *
41428 ***************************************/
41431 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
41432 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
41433 /* The HWRM command request type. */
41436 * The completion ring to send the completion event on. This should
41437 * be the NQ ID returned from the `nq_alloc` HWRM command.
41439 uint16_t cmpl_ring;
41441 * The sequence ID is used by the driver for tracking multiple
41442 * commands. This ID is treated as opaque data by the firmware and
41443 * the value is returned in the `hwrm_resp_hdr` upon completion.
41447 * The target ID of the command:
41448 * * 0x0-0xFFF8 - The function ID
41449 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41450 * * 0xFFFD - Reserved for user-space HWRM interface
41453 uint16_t target_id;
41455 * A physical address pointer pointing to a host buffer that the
41456 * command's response data will be written. This can be either a host
41457 * physical address (HPA) or a guest physical address (GPA) and must
41458 * point to a physically contiguous block of memory.
41460 uint64_t resp_addr;
41461 /* The destination function id, to whom the traffic is redirected. */
41464 uint8_t tunnel_type;
41466 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
41468 /* Virtual eXtensible Local Area Network (VXLAN) */
41469 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
41471 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41472 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
41474 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
41478 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
41480 /* Generic Network Virtualization Encapsulation (Geneve) */
41481 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
41483 /* Multi-Protocol Label Switching (MPLS) */
41484 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
41486 /* Stateless Transport Tunnel (STT) */
41487 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
41489 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41490 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
41492 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41493 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
41496 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41499 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
41501 /* Use fixed layer 2 ether type of 0xFFFF */
41502 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
41505 * IPV6 over virtual eXtensible Local Area Network with GPE header
41508 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
41510 /* Any tunneled traffic */
41511 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
41513 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
41514 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
41515 /* Tunnel alloc flags. */
41518 * Setting of this flag indicates modify existing redirect tunnel
41519 * to new destination function ID.
41521 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
41523 uint8_t unused_0[4];
41526 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
41527 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
41528 /* The specific error status for the command. */
41529 uint16_t error_code;
41530 /* The HWRM command request type. */
41532 /* The sequence ID from the original command. */
41534 /* The length of the response data in number of bytes. */
41536 uint8_t unused_0[7];
41538 * This field is used in Output records to indicate that the output
41539 * is completely written to RAM. This field should be read as '1'
41540 * to indicate that the output has been completely written.
41541 * When writing a command completion or response to an internal
41542 * processor, the order of writes has to be such that this field is
41548 /**************************************
41549 * hwrm_cfa_redirect_tunnel_type_free *
41550 **************************************/
41553 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
41554 struct hwrm_cfa_redirect_tunnel_type_free_input {
41555 /* The HWRM command request type. */
41558 * The completion ring to send the completion event on. This should
41559 * be the NQ ID returned from the `nq_alloc` HWRM command.
41561 uint16_t cmpl_ring;
41563 * The sequence ID is used by the driver for tracking multiple
41564 * commands. This ID is treated as opaque data by the firmware and
41565 * the value is returned in the `hwrm_resp_hdr` upon completion.
41569 * The target ID of the command:
41570 * * 0x0-0xFFF8 - The function ID
41571 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41572 * * 0xFFFD - Reserved for user-space HWRM interface
41575 uint16_t target_id;
41577 * A physical address pointer pointing to a host buffer that the
41578 * command's response data will be written. This can be either a host
41579 * physical address (HPA) or a guest physical address (GPA) and must
41580 * point to a physically contiguous block of memory.
41582 uint64_t resp_addr;
41583 /* The destination function id, to whom the traffic is redirected. */
41586 uint8_t tunnel_type;
41588 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
41590 /* Virtual eXtensible Local Area Network (VXLAN) */
41591 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
41593 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41594 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
41596 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41597 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
41600 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
41602 /* Generic Network Virtualization Encapsulation (Geneve) */
41603 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
41605 /* Multi-Protocol Label Switching (MPLS) */
41606 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
41608 /* Stateless Transport Tunnel (STT) */
41609 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
41611 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41612 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
41614 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41615 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
41618 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41621 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
41623 /* Use fixed layer 2 ether type of 0xFFFF */
41624 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
41627 * IPV6 over virtual eXtensible Local Area Network with GPE header
41630 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
41632 /* Any tunneled traffic */
41633 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
41635 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
41636 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
41637 uint8_t unused_0[5];
41640 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
41641 struct hwrm_cfa_redirect_tunnel_type_free_output {
41642 /* The specific error status for the command. */
41643 uint16_t error_code;
41644 /* The HWRM command request type. */
41646 /* The sequence ID from the original command. */
41648 /* The length of the response data in number of bytes. */
41650 uint8_t unused_0[7];
41652 * This field is used in Output records to indicate that the output
41653 * is completely written to RAM. This field should be read as '1'
41654 * to indicate that the output has been completely written.
41655 * When writing a command completion or response to an internal
41656 * processor, the order of writes has to be such that this field is
41662 /**************************************
41663 * hwrm_cfa_redirect_tunnel_type_info *
41664 **************************************/
41667 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
41668 struct hwrm_cfa_redirect_tunnel_type_info_input {
41669 /* The HWRM command request type. */
41672 * The completion ring to send the completion event on. This should
41673 * be the NQ ID returned from the `nq_alloc` HWRM command.
41675 uint16_t cmpl_ring;
41677 * The sequence ID is used by the driver for tracking multiple
41678 * commands. This ID is treated as opaque data by the firmware and
41679 * the value is returned in the `hwrm_resp_hdr` upon completion.
41683 * The target ID of the command:
41684 * * 0x0-0xFFF8 - The function ID
41685 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41686 * * 0xFFFD - Reserved for user-space HWRM interface
41689 uint16_t target_id;
41691 * A physical address pointer pointing to a host buffer that the
41692 * command's response data will be written. This can be either a host
41693 * physical address (HPA) or a guest physical address (GPA) and must
41694 * point to a physically contiguous block of memory.
41696 uint64_t resp_addr;
41697 /* The source function id. */
41700 uint8_t tunnel_type;
41702 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
41704 /* Virtual eXtensible Local Area Network (VXLAN) */
41705 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
41707 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41708 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
41710 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41711 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
41714 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
41716 /* Generic Network Virtualization Encapsulation (Geneve) */
41717 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
41719 /* Multi-Protocol Label Switching (MPLS) */
41720 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
41722 /* Stateless Transport Tunnel (STT) */
41723 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
41725 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41726 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
41728 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41729 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
41732 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41735 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
41737 /* Use fixed layer 2 ether type of 0xFFFF */
41738 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
41741 * IPV6 over virtual eXtensible Local Area Network with GPE header
41744 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
41746 /* Any tunneled traffic */
41747 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
41749 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
41750 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
41751 uint8_t unused_0[5];
41754 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
41755 struct hwrm_cfa_redirect_tunnel_type_info_output {
41756 /* The specific error status for the command. */
41757 uint16_t error_code;
41758 /* The HWRM command request type. */
41760 /* The sequence ID from the original command. */
41762 /* The length of the response data in number of bytes. */
41764 /* The destination function id, to whom the traffic is redirected. */
41766 uint8_t unused_0[5];
41768 * This field is used in Output records to indicate that the output
41769 * is completely written to RAM. This field should be read as '1'
41770 * to indicate that the output has been completely written.
41771 * When writing a command completion or response to an internal
41772 * processor, the order of writes has to be such that this field is
41778 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
41779 struct hwrm_vxlan_ipv4_hdr {
41780 /* IPv4 version and header length. */
41782 /* IPv4 header length */
41783 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
41784 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
41786 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
41787 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
41788 /* IPv4 type of service. */
41790 /* IPv4 identification. */
41792 /* IPv4 flags and offset. */
41793 uint16_t flags_frag_offset;
41796 /* IPv4 protocol. */
41798 /* IPv4 source address. */
41799 uint32_t src_ip_addr;
41800 /* IPv4 destination address. */
41801 uint32_t dest_ip_addr;
41804 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
41805 struct hwrm_vxlan_ipv6_hdr {
41806 /* IPv6 version, traffic class and flow label. */
41807 uint32_t ver_tc_flow_label;
41808 /* IPv6 version shift */
41809 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
41811 /* IPv6 version mask */
41812 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
41813 UINT32_C(0xf0000000)
41814 /* IPv6 TC shift */
41815 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
41818 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
41819 UINT32_C(0xff00000)
41820 /* IPv6 flow label shift */
41821 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
41823 /* IPv6 flow label mask */
41824 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
41826 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
41827 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
41828 /* IPv6 payload length. */
41829 uint16_t payload_len;
41830 /* IPv6 next header. */
41834 /* IPv6 source address. */
41835 uint32_t src_ip_addr[4];
41836 /* IPv6 destination address. */
41837 uint32_t dest_ip_addr[4];
41840 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
41841 struct hwrm_cfa_encap_data_vxlan {
41842 /* Source MAC address. */
41843 uint8_t src_mac_addr[6];
41846 /* Destination MAC address. */
41847 uint8_t dst_mac_addr[6];
41848 /* Number of VLAN tags. */
41849 uint8_t num_vlan_tags;
41852 /* Outer VLAN TPID. */
41853 uint16_t ovlan_tpid;
41854 /* Outer VLAN TCI. */
41855 uint16_t ovlan_tci;
41856 /* Inner VLAN TPID. */
41857 uint16_t ivlan_tpid;
41858 /* Inner VLAN TCI. */
41859 uint16_t ivlan_tci;
41860 /* L3 header fields. */
41862 /* IP version mask. */
41863 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
41864 /* IP version 4. */
41865 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
41866 /* IP version 6. */
41867 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
41868 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
41869 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
41870 /* UDP source port. */
41872 /* UDP destination port. */
41874 /* VXLAN Network Identifier. */
41877 * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
41880 uint8_t hdr_rsvd0[3];
41881 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
41883 /* VXLAN header flags field. */
41888 /*******************************
41889 * hwrm_cfa_encap_record_alloc *
41890 *******************************/
41893 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
41894 struct hwrm_cfa_encap_record_alloc_input {
41895 /* The HWRM command request type. */
41898 * The completion ring to send the completion event on. This should
41899 * be the NQ ID returned from the `nq_alloc` HWRM command.
41901 uint16_t cmpl_ring;
41903 * The sequence ID is used by the driver for tracking multiple
41904 * commands. This ID is treated as opaque data by the firmware and
41905 * the value is returned in the `hwrm_resp_hdr` upon completion.
41909 * The target ID of the command:
41910 * * 0x0-0xFFF8 - The function ID
41911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41912 * * 0xFFFD - Reserved for user-space HWRM interface
41915 uint16_t target_id;
41917 * A physical address pointer pointing to a host buffer that the
41918 * command's response data will be written. This can be either a host
41919 * physical address (HPA) or a guest physical address (GPA) and must
41920 * point to a physically contiguous block of memory.
41922 uint64_t resp_addr;
41925 * Setting of this flag indicates the applicability to the loopback
41928 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
41931 * Setting of this flag indicates this encap record is external
41932 * encap record. Resetting of this flag indicates this flag is
41933 * internal encap record and this is the default setting.
41935 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
41937 /* Encapsulation Type. */
41938 uint8_t encap_type;
41939 /* Virtual eXtensible Local Area Network (VXLAN) */
41940 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
41942 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41943 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
41945 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
41946 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
41949 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
41951 /* Generic Network Virtualization Encapsulation (Geneve) */
41952 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
41954 /* Multi-Protocol Label Switching (MPLS) */
41955 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
41958 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
41960 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41961 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
41963 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41964 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
41967 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41970 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
41972 /* Use fixed layer 2 ether type of 0xFFFF */
41973 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
41976 * IPV6 over virtual eXtensible Local Area Network with GPE header
41979 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
41981 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
41982 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
41983 uint8_t unused_0[3];
41984 /* This value is encap data used for the given encap type. */
41985 uint32_t encap_data[20];
41988 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
41989 struct hwrm_cfa_encap_record_alloc_output {
41990 /* The specific error status for the command. */
41991 uint16_t error_code;
41992 /* The HWRM command request type. */
41994 /* The sequence ID from the original command. */
41996 /* The length of the response data in number of bytes. */
41998 /* This value is an opaque id into CFA data structures. */
41999 uint32_t encap_record_id;
42000 uint8_t unused_0[3];
42002 * This field is used in Output records to indicate that the output
42003 * is completely written to RAM. This field should be read as '1'
42004 * to indicate that the output has been completely written.
42005 * When writing a command completion or response to an internal
42006 * processor, the order of writes has to be such that this field is
42012 /******************************
42013 * hwrm_cfa_encap_record_free *
42014 ******************************/
42017 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
42018 struct hwrm_cfa_encap_record_free_input {
42019 /* The HWRM command request type. */
42022 * The completion ring to send the completion event on. This should
42023 * be the NQ ID returned from the `nq_alloc` HWRM command.
42025 uint16_t cmpl_ring;
42027 * The sequence ID is used by the driver for tracking multiple
42028 * commands. This ID is treated as opaque data by the firmware and
42029 * the value is returned in the `hwrm_resp_hdr` upon completion.
42033 * The target ID of the command:
42034 * * 0x0-0xFFF8 - The function ID
42035 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42036 * * 0xFFFD - Reserved for user-space HWRM interface
42039 uint16_t target_id;
42041 * A physical address pointer pointing to a host buffer that the
42042 * command's response data will be written. This can be either a host
42043 * physical address (HPA) or a guest physical address (GPA) and must
42044 * point to a physically contiguous block of memory.
42046 uint64_t resp_addr;
42047 /* This value is an opaque id into CFA data structures. */
42048 uint32_t encap_record_id;
42049 uint8_t unused_0[4];
42052 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
42053 struct hwrm_cfa_encap_record_free_output {
42054 /* The specific error status for the command. */
42055 uint16_t error_code;
42056 /* The HWRM command request type. */
42058 /* The sequence ID from the original command. */
42060 /* The length of the response data in number of bytes. */
42062 uint8_t unused_0[7];
42064 * This field is used in Output records to indicate that the output
42065 * is completely written to RAM. This field should be read as '1'
42066 * to indicate that the output has been completely written.
42067 * When writing a command completion or response to an internal
42068 * processor, the order of writes has to be such that this field is
42074 /********************************
42075 * hwrm_cfa_ntuple_filter_alloc *
42076 ********************************/
42079 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
42080 struct hwrm_cfa_ntuple_filter_alloc_input {
42081 /* The HWRM command request type. */
42084 * The completion ring to send the completion event on. This should
42085 * be the NQ ID returned from the `nq_alloc` HWRM command.
42087 uint16_t cmpl_ring;
42089 * The sequence ID is used by the driver for tracking multiple
42090 * commands. This ID is treated as opaque data by the firmware and
42091 * the value is returned in the `hwrm_resp_hdr` upon completion.
42095 * The target ID of the command:
42096 * * 0x0-0xFFF8 - The function ID
42097 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42098 * * 0xFFFD - Reserved for user-space HWRM interface
42101 uint16_t target_id;
42103 * A physical address pointer pointing to a host buffer that the
42104 * command's response data will be written. This can be either a host
42105 * physical address (HPA) or a guest physical address (GPA) and must
42106 * point to a physically contiguous block of memory.
42108 uint64_t resp_addr;
42111 * Setting of this flag indicates the applicability to the loopback
42114 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
42117 * Setting of this flag indicates drop action. If this flag is not
42118 * set, then it should be considered accept action.
42120 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
42123 * Setting of this flag indicates that a meter is expected to be
42124 * attached to this flow. This hint can be used when choosing the
42125 * action record format required for the flow.
42127 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
42130 * Setting of this flag indicates that the dst_id field contains
42131 * function ID. If this is not set it indicates dest_id is VNIC
42134 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
42137 * Setting of this flag indicates match on arp reply when ethertype
42138 * is 0x0806. If this is not set it indicates no specific arp opcode
42141 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
42144 * Setting of this flag indicates that the dst_id field contains RFS
42145 * ring table index. If this is not set it indicates dst_id is VNIC
42146 * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
42147 * can’t be set at the same time.
42149 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
42152 * Setting of this flag indicates that when the ntuple filter is
42153 * created, the L2 context should not be used in the filter. This
42154 * allows packet from different L2 contexts to match and be directed
42155 * to the same destination.
42157 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \
42161 * This bit must be '1' for the l2_filter_id field to be
42164 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
42167 * This bit must be '1' for the ethertype field to be
42170 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
42173 * This bit must be '1' for the tunnel_type field to be
42176 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
42179 * This bit must be '1' for the src_macaddr field to be
42182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
42185 * This bit must be '1' for the ipaddr_type field to be
42188 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
42191 * This bit must be '1' for the src_ipaddr field to be
42194 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
42197 * This bit must be '1' for the src_ipaddr_mask field to be
42200 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
42203 * This bit must be '1' for the dst_ipaddr field to be
42206 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
42209 * This bit must be '1' for the dst_ipaddr_mask field to be
42212 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
42215 * This bit must be '1' for the ip_protocol field to be
42218 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
42221 * This bit must be '1' for the src_port field to be
42224 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
42227 * This bit must be '1' for the src_port_mask field to be
42230 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
42233 * This bit must be '1' for the dst_port field to be
42236 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
42239 * This bit must be '1' for the dst_port_mask field to be
42242 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
42245 * This bit must be '1' for the pri_hint field to be
42248 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
42251 * This bit must be '1' for the ntuple_filter_id field to be
42254 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
42257 * This bit must be '1' for the dst_id field to be
42260 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
42263 * This bit must be '1' for the mirror_vnic_id field to be
42266 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
42269 * This bit must be '1' for the dst_macaddr field to be
42272 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
42274 /* This flag is deprecated. */
42275 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
42278 * This value identifies a set of CFA data structures used for an L2
42281 uint64_t l2_filter_id;
42283 * This value indicates the source MAC address in
42284 * the Ethernet header.
42286 uint8_t src_macaddr[6];
42287 /* This value indicates the ethertype in the Ethernet header. */
42288 uint16_t ethertype;
42290 * This value indicates the type of IP address.
42293 * All others are invalid.
42295 uint8_t ip_addr_type;
42297 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
42300 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
42303 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
42305 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
42306 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
42308 * The value of protocol filed in IP header.
42309 * Applies to UDP and TCP traffic.
42313 uint8_t ip_protocol;
42315 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
42318 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
42321 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
42323 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
42324 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
42326 * If set, this value shall represent the
42327 * Logical VNIC ID of the destination VNIC for the RX
42328 * path and network port id of the destination port for
42333 * Logical VNIC ID of the VNIC where traffic is
42336 uint16_t mirror_vnic_id;
42338 * This value indicates the tunnel type for this filter.
42339 * If this field is not specified, then the filter shall
42340 * apply to both non-tunneled and tunneled packets.
42341 * If this field conflicts with the tunnel_type specified
42342 * in the l2_filter_id, then the HWRM shall return an
42343 * error for this command.
42345 uint8_t tunnel_type;
42347 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
42349 /* Virtual eXtensible Local Area Network (VXLAN) */
42350 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
42352 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
42353 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
42355 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
42356 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
42359 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
42361 /* Generic Network Virtualization Encapsulation (Geneve) */
42362 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
42364 /* Multi-Protocol Label Switching (MPLS) */
42365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
42367 /* Stateless Transport Tunnel (STT) */
42368 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
42370 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
42371 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
42373 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
42374 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
42377 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
42380 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
42382 /* Use fixed layer 2 ether type of 0xFFFF */
42383 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
42386 * IPV6 over virtual eXtensible Local Area Network with GPE header
42389 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
42391 /* Any tunneled traffic */
42392 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
42394 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
42395 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
42397 * This hint is provided to help in placing
42398 * the filter in the filter table.
42401 /* No preference */
42402 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
42404 /* Above the given filter */
42405 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
42407 /* Below the given filter */
42408 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
42410 /* As high as possible */
42411 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
42413 /* As low as possible */
42414 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
42416 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
42417 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
42419 * The value of source IP address to be used in filtering.
42420 * For IPv4, first four bytes represent the IP address.
42422 uint32_t src_ipaddr[4];
42424 * The value of source IP address mask to be used in
42426 * For IPv4, first four bytes represent the IP address mask.
42428 uint32_t src_ipaddr_mask[4];
42430 * The value of destination IP address to be used in filtering.
42431 * For IPv4, first four bytes represent the IP address.
42433 uint32_t dst_ipaddr[4];
42435 * The value of destination IP address mask to be used in
42437 * For IPv4, first four bytes represent the IP address mask.
42439 uint32_t dst_ipaddr_mask[4];
42441 * The value of source port to be used in filtering.
42442 * Applies to UDP and TCP traffic.
42446 * The value of source port mask to be used in filtering.
42447 * Applies to UDP and TCP traffic.
42449 uint16_t src_port_mask;
42451 * The value of destination port to be used in filtering.
42452 * Applies to UDP and TCP traffic.
42456 * The value of destination port mask to be used in
42458 * Applies to UDP and TCP traffic.
42460 uint16_t dst_port_mask;
42462 * This is the ID of the filter that goes along with
42465 uint64_t ntuple_filter_id_hint;
42468 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
42469 struct hwrm_cfa_ntuple_filter_alloc_output {
42470 /* The specific error status for the command. */
42471 uint16_t error_code;
42472 /* The HWRM command request type. */
42474 /* The sequence ID from the original command. */
42476 /* The length of the response data in number of bytes. */
42478 /* This value is an opaque id into CFA data structures. */
42479 uint64_t ntuple_filter_id;
42481 * The flow id value in bit 0-29 is the actual ID of the flow
42482 * associated with this filter and it shall be used to match
42483 * and associate the flow identifier returned in completion
42484 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
42485 * shall indicate no valid flow id.
42488 /* Indicate the flow id value. */
42489 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
42490 UINT32_C(0x3fffffff)
42491 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
42492 /* Indicate type of the flow. */
42493 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
42494 UINT32_C(0x40000000)
42496 * If this bit set to 0, then it indicates that the flow is
42499 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
42500 (UINT32_C(0x0) << 30)
42502 * If this bit is set to 1, then it indicates that the flow is
42505 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
42506 (UINT32_C(0x1) << 30)
42507 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
42508 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
42509 /* Indicate the flow direction. */
42510 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
42511 UINT32_C(0x80000000)
42512 /* If this bit set to 0, then it indicates rx flow. */
42513 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
42514 (UINT32_C(0x0) << 31)
42515 /* If this bit is set to 1, then it indicates that tx flow. */
42516 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
42517 (UINT32_C(0x1) << 31)
42518 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
42519 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
42520 uint8_t unused_0[3];
42522 * This field is used in Output records to indicate that the output
42523 * is completely written to RAM. This field should be read as '1'
42524 * to indicate that the output has been completely written.
42525 * When writing a command completion or response to an internal
42526 * processor, the order of writes has to be such that this field is
42532 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
42533 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
42535 * command specific error codes that goes to
42536 * the cmd_err field in Common HWRM Error Response.
42539 /* Unknown error */
42540 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
42542 /* Unable to complete operation due to conflict with Rx Mask VLAN */
42543 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
42545 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
42546 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
42547 uint8_t unused_0[7];
42550 /*******************************
42551 * hwrm_cfa_ntuple_filter_free *
42552 *******************************/
42555 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
42556 struct hwrm_cfa_ntuple_filter_free_input {
42557 /* The HWRM command request type. */
42560 * The completion ring to send the completion event on. This should
42561 * be the NQ ID returned from the `nq_alloc` HWRM command.
42563 uint16_t cmpl_ring;
42565 * The sequence ID is used by the driver for tracking multiple
42566 * commands. This ID is treated as opaque data by the firmware and
42567 * the value is returned in the `hwrm_resp_hdr` upon completion.
42571 * The target ID of the command:
42572 * * 0x0-0xFFF8 - The function ID
42573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42574 * * 0xFFFD - Reserved for user-space HWRM interface
42577 uint16_t target_id;
42579 * A physical address pointer pointing to a host buffer that the
42580 * command's response data will be written. This can be either a host
42581 * physical address (HPA) or a guest physical address (GPA) and must
42582 * point to a physically contiguous block of memory.
42584 uint64_t resp_addr;
42585 /* This value is an opaque id into CFA data structures. */
42586 uint64_t ntuple_filter_id;
42589 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
42590 struct hwrm_cfa_ntuple_filter_free_output {
42591 /* The specific error status for the command. */
42592 uint16_t error_code;
42593 /* The HWRM command request type. */
42595 /* The sequence ID from the original command. */
42597 /* The length of the response data in number of bytes. */
42599 uint8_t unused_0[7];
42601 * This field is used in Output records to indicate that the output
42602 * is completely written to RAM. This field should be read as '1'
42603 * to indicate that the output has been completely written.
42604 * When writing a command completion or response to an internal
42605 * processor, the order of writes has to be such that this field is
42611 /******************************
42612 * hwrm_cfa_ntuple_filter_cfg *
42613 ******************************/
42616 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
42617 struct hwrm_cfa_ntuple_filter_cfg_input {
42618 /* The HWRM command request type. */
42621 * The completion ring to send the completion event on. This should
42622 * be the NQ ID returned from the `nq_alloc` HWRM command.
42624 uint16_t cmpl_ring;
42626 * The sequence ID is used by the driver for tracking multiple
42627 * commands. This ID is treated as opaque data by the firmware and
42628 * the value is returned in the `hwrm_resp_hdr` upon completion.
42632 * The target ID of the command:
42633 * * 0x0-0xFFF8 - The function ID
42634 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42635 * * 0xFFFD - Reserved for user-space HWRM interface
42638 uint16_t target_id;
42640 * A physical address pointer pointing to a host buffer that the
42641 * command's response data will be written. This can be either a host
42642 * physical address (HPA) or a guest physical address (GPA) and must
42643 * point to a physically contiguous block of memory.
42645 uint64_t resp_addr;
42648 * This bit must be '1' for the new_dst_id field to be
42651 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
42654 * This bit must be '1' for the new_mirror_vnic_id field to be
42657 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
42660 * This bit must be '1' for the new_meter_instance_id field to be
42663 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
42667 * Setting this bit to 1 indicates that dest_id field contains FID.
42668 * Setting this to 0 indicates that dest_id field contains VNIC or
42671 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
42674 * Setting of this flag indicates that the new_dst_id field contains
42675 * RFS ring table index. If this is not set it indicates new_dst_id
42676 * is VNIC or VPORT or function ID. Note dest_fid and
42677 * dest_rfs_ring_idx can’t be set at the same time.
42679 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
42682 * Setting of this flag indicates that when the ntuple filter is
42683 * created, the L2 context should not be used in the filter. This
42684 * allows packet from different L2 contexts to match and be directed
42685 * to the same destination.
42687 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \
42689 /* This value is an opaque id into CFA data structures. */
42690 uint64_t ntuple_filter_id;
42692 * If set, this value shall represent the new
42693 * Logical VNIC ID of the destination VNIC for the RX
42694 * path and new network port id of the destination port for
42697 uint32_t new_dst_id;
42699 * New Logical VNIC ID of the VNIC where traffic is
42702 uint32_t new_mirror_vnic_id;
42704 * New meter to attach to the flow. Specifying the
42705 * invalid instance ID is used to remove any existing
42706 * meter from the flow.
42708 uint16_t new_meter_instance_id;
42710 * A value of 0xfff is considered invalid and implies the
42711 * instance is not configured.
42713 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
42715 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
42716 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
42717 uint8_t unused_1[6];
42720 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
42721 struct hwrm_cfa_ntuple_filter_cfg_output {
42722 /* The specific error status for the command. */
42723 uint16_t error_code;
42724 /* The HWRM command request type. */
42726 /* The sequence ID from the original command. */
42728 /* The length of the response data in number of bytes. */
42730 uint8_t unused_0[7];
42732 * This field is used in Output records to indicate that the output
42733 * is completely written to RAM. This field should be read as '1'
42734 * to indicate that the output has been completely written.
42735 * When writing a command completion or response to an internal
42736 * processor, the order of writes has to be such that this field is
42742 /**************************
42743 * hwrm_cfa_em_flow_alloc *
42744 **************************/
42747 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
42748 struct hwrm_cfa_em_flow_alloc_input {
42749 /* The HWRM command request type. */
42752 * The completion ring to send the completion event on. This should
42753 * be the NQ ID returned from the `nq_alloc` HWRM command.
42755 uint16_t cmpl_ring;
42757 * The sequence ID is used by the driver for tracking multiple
42758 * commands. This ID is treated as opaque data by the firmware and
42759 * the value is returned in the `hwrm_resp_hdr` upon completion.
42763 * The target ID of the command:
42764 * * 0x0-0xFFF8 - The function ID
42765 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42766 * * 0xFFFD - Reserved for user-space HWRM interface
42769 uint16_t target_id;
42771 * A physical address pointer pointing to a host buffer that the
42772 * command's response data will be written. This can be either a host
42773 * physical address (HPA) or a guest physical address (GPA) and must
42774 * point to a physically contiguous block of memory.
42776 uint64_t resp_addr;
42779 * Enumeration denoting the RX, TX type of the resource.
42780 * This enumeration is used for resources that are similar for both
42781 * TX and RX paths of the chip.
42783 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
42785 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
42787 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
42788 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
42789 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
42791 * Setting of this flag indicates enabling of a byte counter for a
42794 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
42796 * Setting of this flag indicates enabling of a packet counter for a
42799 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
42801 * Setting of this flag indicates de-capsulation action for the
42804 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
42806 * Setting of this flag indicates encapsulation action for the
42809 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
42811 * Setting of this flag indicates drop action. If this flag is not
42812 * set, then it should be considered accept action.
42814 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
42816 * Setting of this flag indicates that a meter is expected to be
42817 * attached to this flow. This hint can be used when choosing the
42818 * action record format required for the flow.
42820 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
42823 * This bit must be '1' for the l2_filter_id field to be
42826 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
42829 * This bit must be '1' for the tunnel_type field to be
42832 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
42835 * This bit must be '1' for the tunnel_id field to be
42838 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
42841 * This bit must be '1' for the src_macaddr field to be
42844 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
42847 * This bit must be '1' for the dst_macaddr field to be
42850 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
42853 * This bit must be '1' for the ovlan_vid field to be
42856 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
42859 * This bit must be '1' for the ivlan_vid field to be
42862 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
42865 * This bit must be '1' for the ethertype field to be
42868 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
42871 * This bit must be '1' for the src_ipaddr field to be
42874 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
42877 * This bit must be '1' for the dst_ipaddr field to be
42880 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
42883 * This bit must be '1' for the ipaddr_type field to be
42886 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
42889 * This bit must be '1' for the ip_protocol field to be
42892 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
42895 * This bit must be '1' for the src_port field to be
42898 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
42901 * This bit must be '1' for the dst_port field to be
42904 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
42907 * This bit must be '1' for the dst_id field to be
42910 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
42913 * This bit must be '1' for the mirror_vnic_id field to be
42916 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
42919 * This bit must be '1' for the encap_record_id field to be
42922 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
42925 * This bit must be '1' for the meter_instance_id field to be
42928 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
42931 * This value identifies a set of CFA data structures used for an L2
42934 uint64_t l2_filter_id;
42936 uint8_t tunnel_type;
42938 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
42940 /* Virtual eXtensible Local Area Network (VXLAN) */
42941 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
42943 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
42944 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
42946 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
42947 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
42950 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
42952 /* Generic Network Virtualization Encapsulation (Geneve) */
42953 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
42955 /* Multi-Protocol Label Switching (MPLS) */
42956 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
42958 /* Stateless Transport Tunnel (STT) */
42959 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
42961 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
42962 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
42964 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
42965 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
42968 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
42971 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
42973 /* Use fixed layer 2 ether type of 0xFFFF */
42974 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
42977 * IPV6 over virtual eXtensible Local Area Network with GPE header
42980 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
42982 /* Any tunneled traffic */
42983 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
42985 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
42986 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
42987 uint8_t unused_0[3];
42989 * Tunnel identifier.
42990 * Virtual Network Identifier (VNI). Only valid with
42991 * tunnel_types VXLAN, NVGRE, and Geneve.
42992 * Only lower 24-bits of VNI field are used
42993 * in setting up the filter.
42995 uint32_t tunnel_id;
42997 * This value indicates the source MAC address in
42998 * the Ethernet header.
43000 uint8_t src_macaddr[6];
43001 /* The meter instance to attach to the flow. */
43002 uint16_t meter_instance_id;
43004 * A value of 0xfff is considered invalid and implies the
43005 * instance is not configured.
43007 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
43009 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
43010 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
43012 * This value indicates the destination MAC address in
43013 * the Ethernet header.
43015 uint8_t dst_macaddr[6];
43017 * This value indicates the VLAN ID of the outer VLAN tag
43018 * in the Ethernet header.
43020 uint16_t ovlan_vid;
43022 * This value indicates the VLAN ID of the inner VLAN tag
43023 * in the Ethernet header.
43025 uint16_t ivlan_vid;
43026 /* This value indicates the ethertype in the Ethernet header. */
43027 uint16_t ethertype;
43029 * This value indicates the type of IP address.
43032 * All others are invalid.
43034 uint8_t ip_addr_type;
43036 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
43038 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
43040 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
43041 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
43042 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
43044 * The value of protocol filed in IP header.
43045 * Applies to UDP and TCP traffic.
43049 uint8_t ip_protocol;
43051 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
43053 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
43055 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
43056 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
43057 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
43058 uint8_t unused_1[2];
43060 * The value of source IP address to be used in filtering.
43061 * For IPv4, first four bytes represent the IP address.
43063 uint32_t src_ipaddr[4];
43065 * big_endian = True
43066 * The value of destination IP address to be used in filtering.
43067 * For IPv4, first four bytes represent the IP address.
43069 uint32_t dst_ipaddr[4];
43071 * The value of source port to be used in filtering.
43072 * Applies to UDP and TCP traffic.
43076 * The value of destination port to be used in filtering.
43077 * Applies to UDP and TCP traffic.
43081 * If set, this value shall represent the
43082 * Logical VNIC ID of the destination VNIC for the RX
43083 * path and network port id of the destination port for
43088 * Logical VNIC ID of the VNIC where traffic is
43091 uint16_t mirror_vnic_id;
43092 /* Logical ID of the encapsulation record. */
43093 uint32_t encap_record_id;
43094 uint8_t unused_2[4];
43097 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
43098 struct hwrm_cfa_em_flow_alloc_output {
43099 /* The specific error status for the command. */
43100 uint16_t error_code;
43101 /* The HWRM command request type. */
43103 /* The sequence ID from the original command. */
43105 /* The length of the response data in number of bytes. */
43107 /* This value is an opaque id into CFA data structures. */
43108 uint64_t em_filter_id;
43110 * The flow id value in bit 0-29 is the actual ID of the flow
43111 * associated with this filter and it shall be used to match
43112 * and associate the flow identifier returned in completion
43113 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
43114 * shall indicate no valid flow id.
43117 /* Indicate the flow id value. */
43118 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
43119 UINT32_C(0x3fffffff)
43120 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
43121 /* Indicate type of the flow. */
43122 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
43123 UINT32_C(0x40000000)
43125 * If this bit set to 0, then it indicates that the flow is
43128 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
43129 (UINT32_C(0x0) << 30)
43131 * If this bit is set to 1, then it indicates that the flow is
43134 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
43135 (UINT32_C(0x1) << 30)
43136 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
43137 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
43138 /* Indicate the flow direction. */
43139 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
43140 UINT32_C(0x80000000)
43141 /* If this bit set to 0, then it indicates rx flow. */
43142 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
43143 (UINT32_C(0x0) << 31)
43144 /* If this bit is set to 1, then it indicates that tx flow. */
43145 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
43146 (UINT32_C(0x1) << 31)
43147 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
43148 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
43149 uint8_t unused_0[3];
43151 * This field is used in Output records to indicate that the output
43152 * is completely written to RAM. This field should be read as '1'
43153 * to indicate that the output has been completely written.
43154 * When writing a command completion or response to an internal
43155 * processor, the order of writes has to be such that this field is
43161 /*************************
43162 * hwrm_cfa_em_flow_free *
43163 *************************/
43166 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
43167 struct hwrm_cfa_em_flow_free_input {
43168 /* The HWRM command request type. */
43171 * The completion ring to send the completion event on. This should
43172 * be the NQ ID returned from the `nq_alloc` HWRM command.
43174 uint16_t cmpl_ring;
43176 * The sequence ID is used by the driver for tracking multiple
43177 * commands. This ID is treated as opaque data by the firmware and
43178 * the value is returned in the `hwrm_resp_hdr` upon completion.
43182 * The target ID of the command:
43183 * * 0x0-0xFFF8 - The function ID
43184 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43185 * * 0xFFFD - Reserved for user-space HWRM interface
43188 uint16_t target_id;
43190 * A physical address pointer pointing to a host buffer that the
43191 * command's response data will be written. This can be either a host
43192 * physical address (HPA) or a guest physical address (GPA) and must
43193 * point to a physically contiguous block of memory.
43195 uint64_t resp_addr;
43196 /* This value is an opaque id into CFA data structures. */
43197 uint64_t em_filter_id;
43200 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
43201 struct hwrm_cfa_em_flow_free_output {
43202 /* The specific error status for the command. */
43203 uint16_t error_code;
43204 /* The HWRM command request type. */
43206 /* The sequence ID from the original command. */
43208 /* The length of the response data in number of bytes. */
43210 uint8_t unused_0[7];
43212 * This field is used in Output records to indicate that the output
43213 * is completely written to RAM. This field should be read as '1'
43214 * to indicate that the output has been completely written.
43215 * When writing a command completion or response to an internal
43216 * processor, the order of writes has to be such that this field is
43222 /************************
43223 * hwrm_cfa_meter_qcaps *
43224 ************************/
43227 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
43228 struct hwrm_cfa_meter_qcaps_input {
43229 /* The HWRM command request type. */
43232 * The completion ring to send the completion event on. This should
43233 * be the NQ ID returned from the `nq_alloc` HWRM command.
43235 uint16_t cmpl_ring;
43237 * The sequence ID is used by the driver for tracking multiple
43238 * commands. This ID is treated as opaque data by the firmware and
43239 * the value is returned in the `hwrm_resp_hdr` upon completion.
43243 * The target ID of the command:
43244 * * 0x0-0xFFF8 - The function ID
43245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43246 * * 0xFFFD - Reserved for user-space HWRM interface
43249 uint16_t target_id;
43251 * A physical address pointer pointing to a host buffer that the
43252 * command's response data will be written. This can be either a host
43253 * physical address (HPA) or a guest physical address (GPA) and must
43254 * point to a physically contiguous block of memory.
43256 uint64_t resp_addr;
43259 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
43260 struct hwrm_cfa_meter_qcaps_output {
43261 /* The specific error status for the command. */
43262 uint16_t error_code;
43263 /* The HWRM command request type. */
43265 /* The sequence ID from the original command. */
43267 /* The length of the response data in number of bytes. */
43271 * Enumeration denoting the clock at which the Meter is running
43272 * with. This enumeration is used for resources that are similar
43273 * for both TX and RX paths of the chip.
43275 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
43276 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
43278 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
43280 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
43281 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
43282 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
43283 uint8_t unused_0[4];
43285 * The minimum guaranteed number of tx meter profiles supported
43286 * for this function.
43288 uint16_t min_tx_profile;
43290 * The maximum non-guaranteed number of tx meter profiles supported
43291 * for this function.
43293 uint16_t max_tx_profile;
43295 * The minimum guaranteed number of rx meter profiles supported
43296 * for this function.
43298 uint16_t min_rx_profile;
43300 * The maximum non-guaranteed number of rx meter profiles supported
43301 * for this function.
43303 uint16_t max_rx_profile;
43305 * The minimum guaranteed number of tx meter instances supported
43306 * for this function.
43308 uint16_t min_tx_instance;
43310 * The maximum non-guaranteed number of tx meter instances supported
43311 * for this function.
43313 uint16_t max_tx_instance;
43315 * The minimum guaranteed number of rx meter instances supported
43316 * for this function.
43318 uint16_t min_rx_instance;
43320 * The maximum non-guaranteed number of rx meter instances supported
43321 * for this function.
43323 uint16_t max_rx_instance;
43324 uint8_t unused_1[7];
43326 * This field is used in Output records to indicate that the output
43327 * is completely written to RAM. This field should be read as '1'
43328 * to indicate that the output has been completely written.
43329 * When writing a command completion or response to an internal
43330 * processor, the order of writes has to be such that this field is
43336 /********************************
43337 * hwrm_cfa_meter_profile_alloc *
43338 ********************************/
43341 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
43342 struct hwrm_cfa_meter_profile_alloc_input {
43343 /* The HWRM command request type. */
43346 * The completion ring to send the completion event on. This should
43347 * be the NQ ID returned from the `nq_alloc` HWRM command.
43349 uint16_t cmpl_ring;
43351 * The sequence ID is used by the driver for tracking multiple
43352 * commands. This ID is treated as opaque data by the firmware and
43353 * the value is returned in the `hwrm_resp_hdr` upon completion.
43357 * The target ID of the command:
43358 * * 0x0-0xFFF8 - The function ID
43359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43360 * * 0xFFFD - Reserved for user-space HWRM interface
43363 uint16_t target_id;
43365 * A physical address pointer pointing to a host buffer that the
43366 * command's response data will be written. This can be either a host
43367 * physical address (HPA) or a guest physical address (GPA) and must
43368 * point to a physically contiguous block of memory.
43370 uint64_t resp_addr;
43373 * Enumeration denoting the RX, TX type of the resource.
43374 * This enumeration is used for resources that are similar for both
43375 * TX and RX paths of the chip.
43377 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
43379 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
43382 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
43384 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
43385 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
43386 /* The meter algorithm type. */
43387 uint8_t meter_type;
43388 /* RFC 2697 (srTCM) */
43389 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
43391 /* RFC 2698 (trTCM) */
43392 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
43394 /* RFC 4115 (trTCM) */
43395 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
43397 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
43398 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
43400 * This field is reserved for the future use.
43401 * It shall be set to 0.
43403 uint16_t reserved1;
43405 * This field is reserved for the future use.
43406 * It shall be set to 0.
43408 uint32_t reserved2;
43409 /* A meter rate specified in bytes-per-second. */
43410 uint32_t commit_rate;
43411 /* The bandwidth value. */
43412 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
43413 UINT32_C(0xfffffff)
43414 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
43416 /* The granularity of the value (bits or bytes). */
43417 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
43418 UINT32_C(0x10000000)
43419 /* Value is in bits. */
43420 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
43421 (UINT32_C(0x0) << 28)
43422 /* Value is in bytes. */
43423 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
43424 (UINT32_C(0x1) << 28)
43425 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
43426 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
43427 /* bw_value_unit is 3 b */
43428 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
43429 UINT32_C(0xe0000000)
43430 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
43432 /* Value is in Mb or MB (base 10). */
43433 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
43434 (UINT32_C(0x0) << 29)
43435 /* Value is in Kb or KB (base 10). */
43436 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
43437 (UINT32_C(0x2) << 29)
43438 /* Value is in bits or bytes. */
43439 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
43440 (UINT32_C(0x4) << 29)
43441 /* Value is in Gb or GB (base 10). */
43442 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
43443 (UINT32_C(0x6) << 29)
43444 /* Value is in 1/100th of a percentage of total bandwidth. */
43445 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
43446 (UINT32_C(0x1) << 29)
43448 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
43449 (UINT32_C(0x7) << 29)
43450 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
43451 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
43452 /* A meter burst size specified in bytes. */
43453 uint32_t commit_burst;
43454 /* The bandwidth value. */
43455 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
43456 UINT32_C(0xfffffff)
43457 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
43459 /* The granularity of the value (bits or bytes). */
43460 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
43461 UINT32_C(0x10000000)
43462 /* Value is in bits. */
43463 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
43464 (UINT32_C(0x0) << 28)
43465 /* Value is in bytes. */
43466 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
43467 (UINT32_C(0x1) << 28)
43468 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
43469 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
43470 /* bw_value_unit is 3 b */
43471 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
43472 UINT32_C(0xe0000000)
43473 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
43475 /* Value is in Mb or MB (base 10). */
43476 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
43477 (UINT32_C(0x0) << 29)
43478 /* Value is in Kb or KB (base 10). */
43479 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
43480 (UINT32_C(0x2) << 29)
43481 /* Value is in bits or bytes. */
43482 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
43483 (UINT32_C(0x4) << 29)
43484 /* Value is in Gb or GB (base 10). */
43485 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
43486 (UINT32_C(0x6) << 29)
43487 /* Value is in 1/100th of a percentage of total bandwidth. */
43488 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
43489 (UINT32_C(0x1) << 29)
43490 /* Invalid value */
43491 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
43492 (UINT32_C(0x7) << 29)
43493 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
43494 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
43495 /* A meter rate specified in bytes-per-second. */
43496 uint32_t excess_peak_rate;
43497 /* The bandwidth value. */
43498 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
43499 UINT32_C(0xfffffff)
43500 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
43502 /* The granularity of the value (bits or bytes). */
43503 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
43504 UINT32_C(0x10000000)
43505 /* Value is in bits. */
43506 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
43507 (UINT32_C(0x0) << 28)
43508 /* Value is in bytes. */
43509 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
43510 (UINT32_C(0x1) << 28)
43511 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
43512 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
43513 /* bw_value_unit is 3 b */
43514 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
43515 UINT32_C(0xe0000000)
43516 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
43518 /* Value is in Mb or MB (base 10). */
43519 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
43520 (UINT32_C(0x0) << 29)
43521 /* Value is in Kb or KB (base 10). */
43522 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
43523 (UINT32_C(0x2) << 29)
43524 /* Value is in bits or bytes. */
43525 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
43526 (UINT32_C(0x4) << 29)
43527 /* Value is in Gb or GB (base 10). */
43528 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
43529 (UINT32_C(0x6) << 29)
43530 /* Value is in 1/100th of a percentage of total bandwidth. */
43531 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
43532 (UINT32_C(0x1) << 29)
43534 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
43535 (UINT32_C(0x7) << 29)
43536 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
43537 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
43538 /* A meter burst size specified in bytes. */
43539 uint32_t excess_peak_burst;
43540 /* The bandwidth value. */
43541 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
43542 UINT32_C(0xfffffff)
43543 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
43545 /* The granularity of the value (bits or bytes). */
43546 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
43547 UINT32_C(0x10000000)
43548 /* Value is in bits. */
43549 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
43550 (UINT32_C(0x0) << 28)
43551 /* Value is in bytes. */
43552 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
43553 (UINT32_C(0x1) << 28)
43554 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
43555 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
43556 /* bw_value_unit is 3 b */
43557 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
43558 UINT32_C(0xe0000000)
43559 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
43561 /* Value is in Mb or MB (base 10). */
43562 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
43563 (UINT32_C(0x0) << 29)
43564 /* Value is in Kb or KB (base 10). */
43565 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
43566 (UINT32_C(0x2) << 29)
43567 /* Value is in bits or bytes. */
43568 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
43569 (UINT32_C(0x4) << 29)
43570 /* Value is in Gb or GB (base 10). */
43571 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
43572 (UINT32_C(0x6) << 29)
43573 /* Value is in 1/100th of a percentage of total bandwidth. */
43574 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
43575 (UINT32_C(0x1) << 29)
43577 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
43578 (UINT32_C(0x7) << 29)
43579 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
43580 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
43583 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
43584 struct hwrm_cfa_meter_profile_alloc_output {
43585 /* The specific error status for the command. */
43586 uint16_t error_code;
43587 /* The HWRM command request type. */
43589 /* The sequence ID from the original command. */
43591 /* The length of the response data in number of bytes. */
43593 /* This value identifies a meter profile in CFA. */
43594 uint16_t meter_profile_id;
43596 * A value of 0xfff is considered invalid and implies the
43597 * profile is not configured.
43599 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
43601 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
43602 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
43603 uint8_t unused_0[5];
43605 * This field is used in Output records to indicate that the output
43606 * is completely written to RAM. This field should be read as '1'
43607 * to indicate that the output has been completely written.
43608 * When writing a command completion or response to an internal
43609 * processor, the order of writes has to be such that this field is
43615 /*******************************
43616 * hwrm_cfa_meter_profile_free *
43617 *******************************/
43620 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
43621 struct hwrm_cfa_meter_profile_free_input {
43622 /* The HWRM command request type. */
43625 * The completion ring to send the completion event on. This should
43626 * be the NQ ID returned from the `nq_alloc` HWRM command.
43628 uint16_t cmpl_ring;
43630 * The sequence ID is used by the driver for tracking multiple
43631 * commands. This ID is treated as opaque data by the firmware and
43632 * the value is returned in the `hwrm_resp_hdr` upon completion.
43636 * The target ID of the command:
43637 * * 0x0-0xFFF8 - The function ID
43638 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43639 * * 0xFFFD - Reserved for user-space HWRM interface
43642 uint16_t target_id;
43644 * A physical address pointer pointing to a host buffer that the
43645 * command's response data will be written. This can be either a host
43646 * physical address (HPA) or a guest physical address (GPA) and must
43647 * point to a physically contiguous block of memory.
43649 uint64_t resp_addr;
43652 * Enumeration denoting the RX, TX type of the resource.
43653 * This enumeration is used for resources that are similar for both
43654 * TX and RX paths of the chip.
43656 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
43658 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
43661 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
43663 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
43664 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
43666 /* This value identifies a meter profile in CFA. */
43667 uint16_t meter_profile_id;
43669 * A value of 0xfff is considered invalid and implies the
43670 * profile is not configured.
43672 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
43674 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
43675 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
43676 uint8_t unused_1[4];
43679 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
43680 struct hwrm_cfa_meter_profile_free_output {
43681 /* The specific error status for the command. */
43682 uint16_t error_code;
43683 /* The HWRM command request type. */
43685 /* The sequence ID from the original command. */
43687 /* The length of the response data in number of bytes. */
43689 uint8_t unused_0[7];
43691 * This field is used in Output records to indicate that the output
43692 * is completely written to RAM. This field should be read as '1'
43693 * to indicate that the output has been completely written.
43694 * When writing a command completion or response to an internal
43695 * processor, the order of writes has to be such that this field is
43701 /******************************
43702 * hwrm_cfa_meter_profile_cfg *
43703 ******************************/
43706 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
43707 struct hwrm_cfa_meter_profile_cfg_input {
43708 /* The HWRM command request type. */
43711 * The completion ring to send the completion event on. This should
43712 * be the NQ ID returned from the `nq_alloc` HWRM command.
43714 uint16_t cmpl_ring;
43716 * The sequence ID is used by the driver for tracking multiple
43717 * commands. This ID is treated as opaque data by the firmware and
43718 * the value is returned in the `hwrm_resp_hdr` upon completion.
43722 * The target ID of the command:
43723 * * 0x0-0xFFF8 - The function ID
43724 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43725 * * 0xFFFD - Reserved for user-space HWRM interface
43728 uint16_t target_id;
43730 * A physical address pointer pointing to a host buffer that the
43731 * command's response data will be written. This can be either a host
43732 * physical address (HPA) or a guest physical address (GPA) and must
43733 * point to a physically contiguous block of memory.
43735 uint64_t resp_addr;
43738 * Enumeration denoting the RX, TX type of the resource.
43739 * This enumeration is used for resources that are similar for both
43740 * TX and RX paths of the chip.
43742 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
43744 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
43746 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
43747 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
43748 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
43749 /* The meter algorithm type. */
43750 uint8_t meter_type;
43751 /* RFC 2697 (srTCM) */
43752 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
43754 /* RFC 2698 (trTCM) */
43755 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
43757 /* RFC 4115 (trTCM) */
43758 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
43760 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
43761 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
43762 /* This value identifies a meter profile in CFA. */
43763 uint16_t meter_profile_id;
43765 * A value of 0xfff is considered invalid and implies the
43766 * profile is not configured.
43768 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
43770 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
43771 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
43773 * This field is reserved for the future use.
43774 * It shall be set to 0.
43777 /* A meter rate specified in bytes-per-second. */
43778 uint32_t commit_rate;
43779 /* The bandwidth value. */
43780 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
43781 UINT32_C(0xfffffff)
43782 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
43784 /* The granularity of the value (bits or bytes). */
43785 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
43786 UINT32_C(0x10000000)
43787 /* Value is in bits. */
43788 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
43789 (UINT32_C(0x0) << 28)
43790 /* Value is in bytes. */
43791 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
43792 (UINT32_C(0x1) << 28)
43793 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
43794 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
43795 /* bw_value_unit is 3 b */
43796 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
43797 UINT32_C(0xe0000000)
43798 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
43800 /* Value is in Mb or MB (base 10). */
43801 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
43802 (UINT32_C(0x0) << 29)
43803 /* Value is in Kb or KB (base 10). */
43804 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
43805 (UINT32_C(0x2) << 29)
43806 /* Value is in bits or bytes. */
43807 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
43808 (UINT32_C(0x4) << 29)
43809 /* Value is in Gb or GB (base 10). */
43810 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
43811 (UINT32_C(0x6) << 29)
43812 /* Value is in 1/100th of a percentage of total bandwidth. */
43813 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
43814 (UINT32_C(0x1) << 29)
43816 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
43817 (UINT32_C(0x7) << 29)
43818 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
43819 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
43820 /* A meter burst size specified in bytes. */
43821 uint32_t commit_burst;
43822 /* The bandwidth value. */
43823 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
43824 UINT32_C(0xfffffff)
43825 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
43827 /* The granularity of the value (bits or bytes). */
43828 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
43829 UINT32_C(0x10000000)
43830 /* Value is in bits. */
43831 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
43832 (UINT32_C(0x0) << 28)
43833 /* Value is in bytes. */
43834 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
43835 (UINT32_C(0x1) << 28)
43836 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
43837 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
43838 /* bw_value_unit is 3 b */
43839 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
43840 UINT32_C(0xe0000000)
43841 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
43843 /* Value is in Mb or MB (base 10). */
43844 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
43845 (UINT32_C(0x0) << 29)
43846 /* Value is in Kb or KB (base 10). */
43847 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
43848 (UINT32_C(0x2) << 29)
43849 /* Value is in bits or bytes. */
43850 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
43851 (UINT32_C(0x4) << 29)
43852 /* Value is in Gb or GB (base 10). */
43853 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
43854 (UINT32_C(0x6) << 29)
43855 /* Value is in 1/100th of a percentage of total bandwidth. */
43856 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
43857 (UINT32_C(0x1) << 29)
43858 /* Invalid value */
43859 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
43860 (UINT32_C(0x7) << 29)
43861 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
43862 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
43863 /* A meter rate specified in bytes-per-second. */
43864 uint32_t excess_peak_rate;
43865 /* The bandwidth value. */
43866 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
43867 UINT32_C(0xfffffff)
43868 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
43870 /* The granularity of the value (bits or bytes). */
43871 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
43872 UINT32_C(0x10000000)
43873 /* Value is in bits. */
43874 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
43875 (UINT32_C(0x0) << 28)
43876 /* Value is in bytes. */
43877 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
43878 (UINT32_C(0x1) << 28)
43879 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
43880 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
43881 /* bw_value_unit is 3 b */
43882 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
43883 UINT32_C(0xe0000000)
43884 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
43886 /* Value is in Mb or MB (base 10). */
43887 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
43888 (UINT32_C(0x0) << 29)
43889 /* Value is in Kb or KB (base 10). */
43890 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
43891 (UINT32_C(0x2) << 29)
43892 /* Value is in bits or bytes. */
43893 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
43894 (UINT32_C(0x4) << 29)
43895 /* Value is in Gb or GB (base 10). */
43896 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
43897 (UINT32_C(0x6) << 29)
43898 /* Value is in 1/100th of a percentage of total bandwidth. */
43899 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
43900 (UINT32_C(0x1) << 29)
43902 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
43903 (UINT32_C(0x7) << 29)
43904 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
43905 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
43906 /* A meter burst size specified in bytes. */
43907 uint32_t excess_peak_burst;
43908 /* The bandwidth value. */
43909 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
43910 UINT32_C(0xfffffff)
43911 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
43913 /* The granularity of the value (bits or bytes). */
43914 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
43915 UINT32_C(0x10000000)
43916 /* Value is in bits. */
43917 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
43918 (UINT32_C(0x0) << 28)
43919 /* Value is in bytes. */
43920 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
43921 (UINT32_C(0x1) << 28)
43922 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
43923 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
43924 /* bw_value_unit is 3 b */
43925 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
43926 UINT32_C(0xe0000000)
43927 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
43929 /* Value is in Mb or MB (base 10). */
43930 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
43931 (UINT32_C(0x0) << 29)
43932 /* Value is in Kb or KB (base 10). */
43933 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
43934 (UINT32_C(0x2) << 29)
43935 /* Value is in bits or bytes. */
43936 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
43937 (UINT32_C(0x4) << 29)
43938 /* Value is in Gb or GB (base 10). */
43939 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
43940 (UINT32_C(0x6) << 29)
43941 /* Value is in 1/100th of a percentage of total bandwidth. */
43942 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
43943 (UINT32_C(0x1) << 29)
43945 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
43946 (UINT32_C(0x7) << 29)
43947 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
43948 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
43951 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
43952 struct hwrm_cfa_meter_profile_cfg_output {
43953 /* The specific error status for the command. */
43954 uint16_t error_code;
43955 /* The HWRM command request type. */
43957 /* The sequence ID from the original command. */
43959 /* The length of the response data in number of bytes. */
43961 uint8_t unused_0[7];
43963 * This field is used in Output records to indicate that the output
43964 * is completely written to RAM. This field should be read as '1'
43965 * to indicate that the output has been completely written.
43966 * When writing a command completion or response to an internal
43967 * processor, the order of writes has to be such that this field is
43973 /*********************************
43974 * hwrm_cfa_meter_instance_alloc *
43975 *********************************/
43978 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
43979 struct hwrm_cfa_meter_instance_alloc_input {
43980 /* The HWRM command request type. */
43983 * The completion ring to send the completion event on. This should
43984 * be the NQ ID returned from the `nq_alloc` HWRM command.
43986 uint16_t cmpl_ring;
43988 * The sequence ID is used by the driver for tracking multiple
43989 * commands. This ID is treated as opaque data by the firmware and
43990 * the value is returned in the `hwrm_resp_hdr` upon completion.
43994 * The target ID of the command:
43995 * * 0x0-0xFFF8 - The function ID
43996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43997 * * 0xFFFD - Reserved for user-space HWRM interface
44000 uint16_t target_id;
44002 * A physical address pointer pointing to a host buffer that the
44003 * command's response data will be written. This can be either a host
44004 * physical address (HPA) or a guest physical address (GPA) and must
44005 * point to a physically contiguous block of memory.
44007 uint64_t resp_addr;
44010 * Enumeration denoting the RX, TX type of the resource.
44011 * This enumeration is used for resources that are similar for both
44012 * TX and RX paths of the chip.
44014 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
44017 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
44020 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
44022 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
44023 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
44025 /* This value identifies a meter profile in CFA. */
44026 uint16_t meter_profile_id;
44028 * A value of 0xffff is considered invalid and implies the
44029 * profile is not configured.
44031 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
44033 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
44034 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
44035 uint8_t unused_1[4];
44038 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
44039 struct hwrm_cfa_meter_instance_alloc_output {
44040 /* The specific error status for the command. */
44041 uint16_t error_code;
44042 /* The HWRM command request type. */
44044 /* The sequence ID from the original command. */
44046 /* The length of the response data in number of bytes. */
44048 /* This value identifies a meter instance in CFA. */
44049 uint16_t meter_instance_id;
44051 * A value of 0xffff is considered invalid and implies the
44052 * instance is not configured.
44054 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
44056 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
44057 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
44058 uint8_t unused_0[5];
44060 * This field is used in Output records to indicate that the output
44061 * is completely written to RAM. This field should be read as '1'
44062 * to indicate that the output has been completely written.
44063 * When writing a command completion or response to an internal
44064 * processor, the order of writes has to be such that this field is
44070 /*******************************
44071 * hwrm_cfa_meter_instance_cfg *
44072 *******************************/
44075 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
44076 struct hwrm_cfa_meter_instance_cfg_input {
44077 /* The HWRM command request type. */
44080 * The completion ring to send the completion event on. This should
44081 * be the NQ ID returned from the `nq_alloc` HWRM command.
44083 uint16_t cmpl_ring;
44085 * The sequence ID is used by the driver for tracking multiple
44086 * commands. This ID is treated as opaque data by the firmware and
44087 * the value is returned in the `hwrm_resp_hdr` upon completion.
44091 * The target ID of the command:
44092 * * 0x0-0xFFF8 - The function ID
44093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44094 * * 0xFFFD - Reserved for user-space HWRM interface
44097 uint16_t target_id;
44099 * A physical address pointer pointing to a host buffer that the
44100 * command's response data will be written. This can be either a host
44101 * physical address (HPA) or a guest physical address (GPA) and must
44102 * point to a physically contiguous block of memory.
44104 uint64_t resp_addr;
44107 * Enumeration denoting the RX, TX type of the resource.
44108 * This enumeration is used for resources that are similar for both
44109 * TX and RX paths of the chip.
44111 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
44113 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
44116 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
44118 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
44119 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
44122 * This value identifies a new meter profile to be associated with
44123 * the meter instance specified in this command.
44125 uint16_t meter_profile_id;
44127 * A value of 0xffff is considered invalid and implies the
44128 * profile is not configured.
44130 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
44132 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
44133 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
44135 * This value identifies the ID of a meter instance that needs to be
44136 * updated with a new meter profile specified in this command.
44138 uint16_t meter_instance_id;
44139 uint8_t unused_1[2];
44142 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
44143 struct hwrm_cfa_meter_instance_cfg_output {
44144 /* The specific error status for the command. */
44145 uint16_t error_code;
44146 /* The HWRM command request type. */
44148 /* The sequence ID from the original command. */
44150 /* The length of the response data in number of bytes. */
44152 uint8_t unused_0[7];
44154 * This field is used in Output records to indicate that the output
44155 * is completely written to RAM. This field should be read as '1'
44156 * to indicate that the output has been completely written.
44157 * When writing a command completion or response to an internal
44158 * processor, the order of writes has to be such that this field is
44164 /********************************
44165 * hwrm_cfa_meter_instance_free *
44166 ********************************/
44169 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
44170 struct hwrm_cfa_meter_instance_free_input {
44171 /* The HWRM command request type. */
44174 * The completion ring to send the completion event on. This should
44175 * be the NQ ID returned from the `nq_alloc` HWRM command.
44177 uint16_t cmpl_ring;
44179 * The sequence ID is used by the driver for tracking multiple
44180 * commands. This ID is treated as opaque data by the firmware and
44181 * the value is returned in the `hwrm_resp_hdr` upon completion.
44185 * The target ID of the command:
44186 * * 0x0-0xFFF8 - The function ID
44187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44188 * * 0xFFFD - Reserved for user-space HWRM interface
44191 uint16_t target_id;
44193 * A physical address pointer pointing to a host buffer that the
44194 * command's response data will be written. This can be either a host
44195 * physical address (HPA) or a guest physical address (GPA) and must
44196 * point to a physically contiguous block of memory.
44198 uint64_t resp_addr;
44201 * Enumeration denoting the RX, TX type of the resource.
44202 * This enumeration is used for resources that are similar for both
44203 * TX and RX paths of the chip.
44205 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
44207 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
44210 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
44212 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
44213 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
44215 /* This value identifies a meter instance in CFA. */
44216 uint16_t meter_instance_id;
44218 * A value of 0xfff is considered invalid and implies the
44219 * instance is not configured.
44221 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
44223 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
44224 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
44225 uint8_t unused_1[4];
44228 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
44229 struct hwrm_cfa_meter_instance_free_output {
44230 /* The specific error status for the command. */
44231 uint16_t error_code;
44232 /* The HWRM command request type. */
44234 /* The sequence ID from the original command. */
44236 /* The length of the response data in number of bytes. */
44238 uint8_t unused_0[7];
44240 * This field is used in Output records to indicate that the output
44241 * is completely written to RAM. This field should be read as '1'
44242 * to indicate that the output has been completely written.
44243 * When writing a command completion or response to an internal
44244 * processor, the order of writes has to be such that this field is
44250 /*******************************
44251 * hwrm_cfa_decap_filter_alloc *
44252 *******************************/
44255 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
44256 struct hwrm_cfa_decap_filter_alloc_input {
44257 /* The HWRM command request type. */
44260 * The completion ring to send the completion event on. This should
44261 * be the NQ ID returned from the `nq_alloc` HWRM command.
44263 uint16_t cmpl_ring;
44265 * The sequence ID is used by the driver for tracking multiple
44266 * commands. This ID is treated as opaque data by the firmware and
44267 * the value is returned in the `hwrm_resp_hdr` upon completion.
44271 * The target ID of the command:
44272 * * 0x0-0xFFF8 - The function ID
44273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44274 * * 0xFFFD - Reserved for user-space HWRM interface
44277 uint16_t target_id;
44279 * A physical address pointer pointing to a host buffer that the
44280 * command's response data will be written. This can be either a host
44281 * physical address (HPA) or a guest physical address (GPA) and must
44282 * point to a physically contiguous block of memory.
44284 uint64_t resp_addr;
44286 /* ovs_tunnel is 1 b */
44287 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
44291 * This bit must be '1' for the tunnel_type field to be
44294 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
44297 * This bit must be '1' for the tunnel_id field to be
44300 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
44303 * This bit must be '1' for the src_macaddr field to be
44306 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
44309 * This bit must be '1' for the dst_macaddr field to be
44312 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
44315 * This bit must be '1' for the ovlan_vid field to be
44318 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
44321 * This bit must be '1' for the ivlan_vid field to be
44324 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
44327 * This bit must be '1' for the t_ovlan_vid field to be
44330 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
44333 * This bit must be '1' for the t_ivlan_vid field to be
44336 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
44339 * This bit must be '1' for the ethertype field to be
44342 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
44345 * This bit must be '1' for the src_ipaddr field to be
44348 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
44351 * This bit must be '1' for the dst_ipaddr field to be
44354 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
44357 * This bit must be '1' for the ipaddr_type field to be
44360 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
44363 * This bit must be '1' for the ip_protocol field to be
44366 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
44369 * This bit must be '1' for the src_port field to be
44372 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
44375 * This bit must be '1' for the dst_port field to be
44378 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
44381 * This bit must be '1' for the dst_id field to be
44384 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
44387 * This bit must be '1' for the mirror_vnic_id field to be
44390 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
44393 * Tunnel identifier.
44394 * Virtual Network Identifier (VNI). Only valid with
44395 * tunnel_types VXLAN, NVGRE, and Geneve.
44396 * Only lower 24-bits of VNI field are used
44397 * in setting up the filter.
44399 uint32_t tunnel_id;
44401 uint8_t tunnel_type;
44403 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
44405 /* Virtual eXtensible Local Area Network (VXLAN) */
44406 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
44408 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
44409 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
44411 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
44412 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
44415 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
44417 /* Generic Network Virtualization Encapsulation (Geneve) */
44418 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
44420 /* Multi-Protocol Label Switching (MPLS) */
44421 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
44423 /* Stateless Transport Tunnel (STT) */
44424 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
44426 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
44427 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
44429 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
44430 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
44433 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
44436 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
44438 /* Use fixed layer 2 ether type of 0xFFFF */
44439 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
44442 * IPV6 over virtual eXtensible Local Area Network with GPE header
44445 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
44447 /* Any tunneled traffic */
44448 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
44450 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
44451 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
44455 * This value indicates the source MAC address in
44456 * the Ethernet header.
44458 uint8_t src_macaddr[6];
44459 uint8_t unused_2[2];
44461 * This value indicates the destination MAC address in
44462 * the Ethernet header.
44464 uint8_t dst_macaddr[6];
44466 * This value indicates the VLAN ID of the outer VLAN tag
44467 * in the Ethernet header.
44469 uint16_t ovlan_vid;
44471 * This value indicates the VLAN ID of the inner VLAN tag
44472 * in the Ethernet header.
44474 uint16_t ivlan_vid;
44476 * This value indicates the VLAN ID of the outer VLAN tag
44477 * in the tunnel Ethernet header.
44479 uint16_t t_ovlan_vid;
44481 * This value indicates the VLAN ID of the inner VLAN tag
44482 * in the tunnel Ethernet header.
44484 uint16_t t_ivlan_vid;
44485 /* This value indicates the ethertype in the Ethernet header. */
44486 uint16_t ethertype;
44488 * This value indicates the type of IP address.
44491 * All others are invalid.
44493 uint8_t ip_addr_type;
44495 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
44498 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
44501 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
44503 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
44504 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
44506 * The value of protocol filed in IP header.
44507 * Applies to UDP and TCP traffic.
44511 uint8_t ip_protocol;
44513 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
44516 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
44519 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
44521 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
44522 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
44526 * The value of source IP address to be used in filtering.
44527 * For IPv4, first four bytes represent the IP address.
44529 uint32_t src_ipaddr[4];
44531 * The value of destination IP address to be used in filtering.
44532 * For IPv4, first four bytes represent the IP address.
44534 uint32_t dst_ipaddr[4];
44536 * The value of source port to be used in filtering.
44537 * Applies to UDP and TCP traffic.
44541 * The value of destination port to be used in filtering.
44542 * Applies to UDP and TCP traffic.
44546 * If set, this value shall represent the
44547 * Logical VNIC ID of the destination VNIC for the RX
44552 * If set, this value shall represent the L2 context that matches the
44553 * L2 information of the decap filter.
44555 uint16_t l2_ctxt_ref_id;
44558 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
44559 struct hwrm_cfa_decap_filter_alloc_output {
44560 /* The specific error status for the command. */
44561 uint16_t error_code;
44562 /* The HWRM command request type. */
44564 /* The sequence ID from the original command. */
44566 /* The length of the response data in number of bytes. */
44568 /* This value is an opaque id into CFA data structures. */
44569 uint32_t decap_filter_id;
44570 uint8_t unused_0[3];
44572 * This field is used in Output records to indicate that the output
44573 * is completely written to RAM. This field should be read as '1'
44574 * to indicate that the output has been completely written.
44575 * When writing a command completion or response to an internal
44576 * processor, the order of writes has to be such that this field is
44582 /******************************
44583 * hwrm_cfa_decap_filter_free *
44584 ******************************/
44587 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
44588 struct hwrm_cfa_decap_filter_free_input {
44589 /* The HWRM command request type. */
44592 * The completion ring to send the completion event on. This should
44593 * be the NQ ID returned from the `nq_alloc` HWRM command.
44595 uint16_t cmpl_ring;
44597 * The sequence ID is used by the driver for tracking multiple
44598 * commands. This ID is treated as opaque data by the firmware and
44599 * the value is returned in the `hwrm_resp_hdr` upon completion.
44603 * The target ID of the command:
44604 * * 0x0-0xFFF8 - The function ID
44605 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44606 * * 0xFFFD - Reserved for user-space HWRM interface
44609 uint16_t target_id;
44611 * A physical address pointer pointing to a host buffer that the
44612 * command's response data will be written. This can be either a host
44613 * physical address (HPA) or a guest physical address (GPA) and must
44614 * point to a physically contiguous block of memory.
44616 uint64_t resp_addr;
44617 /* This value is an opaque id into CFA data structures. */
44618 uint32_t decap_filter_id;
44619 uint8_t unused_0[4];
44622 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
44623 struct hwrm_cfa_decap_filter_free_output {
44624 /* The specific error status for the command. */
44625 uint16_t error_code;
44626 /* The HWRM command request type. */
44628 /* The sequence ID from the original command. */
44630 /* The length of the response data in number of bytes. */
44632 uint8_t unused_0[7];
44634 * This field is used in Output records to indicate that the output
44635 * is completely written to RAM. This field should be read as '1'
44636 * to indicate that the output has been completely written.
44637 * When writing a command completion or response to an internal
44638 * processor, the order of writes has to be such that this field is
44644 /***********************
44645 * hwrm_cfa_flow_alloc *
44646 ***********************/
44649 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
44650 struct hwrm_cfa_flow_alloc_input {
44651 /* The HWRM command request type. */
44654 * The completion ring to send the completion event on. This should
44655 * be the NQ ID returned from the `nq_alloc` HWRM command.
44657 uint16_t cmpl_ring;
44659 * The sequence ID is used by the driver for tracking multiple
44660 * commands. This ID is treated as opaque data by the firmware and
44661 * the value is returned in the `hwrm_resp_hdr` upon completion.
44665 * The target ID of the command:
44666 * * 0x0-0xFFF8 - The function ID
44667 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44668 * * 0xFFFD - Reserved for user-space HWRM interface
44671 uint16_t target_id;
44673 * A physical address pointer pointing to a host buffer that the
44674 * command's response data will be written. This can be either a host
44675 * physical address (HPA) or a guest physical address (GPA) and must
44676 * point to a physically contiguous block of memory.
44678 uint64_t resp_addr;
44680 /* tunnel is 1 b */
44681 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
44683 /* num_vlan is 2 b */
44684 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
44686 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
44688 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
44689 (UINT32_C(0x0) << 1)
44691 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
44692 (UINT32_C(0x1) << 1)
44694 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
44695 (UINT32_C(0x2) << 1)
44696 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
44697 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
44698 /* Enumeration denoting the Flow Type. */
44699 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
44701 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
44703 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
44704 (UINT32_C(0x0) << 3)
44706 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
44707 (UINT32_C(0x1) << 3)
44709 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
44710 (UINT32_C(0x2) << 3)
44711 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
44712 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
44714 * when set to 1, indicates TX flow offload for function specified
44715 * in src_fid and the dst_fid should be set to invalid value. To
44716 * indicate a VM to VM flow, both of the path_tx and path_rx flags
44717 * need to be set. For virtio vSwitch offload case, the src_fid and
44718 * dst_fid is set to the same fid value. For the SRIOV vSwitch
44719 * offload case, the src_fid and dst_fid must be set to the same VF
44720 * FID belong to the children VFs of the same PF to indicate VM to
44723 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
44726 * when set to 1, indicates RX flow offload for function specified
44727 * in dst_fid and the src_fid should be set to invalid value.
44729 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
44732 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
44733 * header is required and the VXLAN VNI value is stored in the first
44734 * 24 bits of the dmac field. This flag is only valid when the flow
44737 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
44740 * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
44743 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
44750 /* Tunnel handle valid when tunnel flag is set. */
44751 uint32_t tunnel_handle;
44752 uint16_t action_flags;
44754 * Setting of this flag indicates drop action. If this flag is not
44755 * set, then it should be considered accept action.
44757 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
44759 /* recycle is 1 b */
44760 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
44763 * Setting of this flag indicates drop action. If this flag is not
44764 * set, then it should be considered accept action.
44766 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
44769 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
44771 /* tunnel is 1 b */
44772 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
44774 /* nat_src is 1 b */
44775 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
44777 /* nat_dest is 1 b */
44778 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
44780 /* nat_ipv4_address is 1 b */
44781 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
44783 /* l2_header_rewrite is 1 b */
44784 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
44786 /* ttl_decrement is 1 b */
44787 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
44790 * If set to 1 and flow direction is TX, it indicates decap of L2
44791 * header and encap of tunnel header. If set to 1 and flow direction
44792 * is RX, it indicates decap of tunnel header and encap L2 header.
44793 * The type of tunnel is specified in the tunnel_type field.
44795 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
44797 /* If set to 1, flow aging is enabled for this flow. */
44798 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
44801 * If set to 1 an attempt will be made to try to offload this flow
44802 * to the most optimal flow table resource. If set to 0, the flow
44803 * will be placed to the default flow table resource.
44805 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
44808 * If set to 1 there will be no attempt to allocate an on-chip try
44809 * to offload this flow. If set to 0, which will keep compatibility
44810 * with the older drivers, will cause the FW to attempt to allocate
44811 * an on-chip flow counter for the newly created flow. This will
44812 * keep the existing behavior with EM flows which always had an
44813 * associated flow counter.
44815 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
44818 * Tx Flow: pf or vf fid.
44822 /* VLAN tpid, valid when push_vlan flag is set. */
44823 uint16_t l2_rewrite_vlan_tpid;
44824 /* VLAN tci, valid when push_vlan flag is set. */
44825 uint16_t l2_rewrite_vlan_tci;
44826 /* Meter id, valid when meter flag is set. */
44827 uint16_t act_meter_id;
44828 /* Flow with the same l2 context tcam key. */
44829 uint16_t ref_flow_handle;
44830 /* This value sets the match value for the ethertype. */
44831 uint16_t ethertype;
44832 /* valid when num tags is 1 or 2. */
44833 uint16_t outer_vlan_tci;
44834 /* This value sets the match value for the Destination MAC address. */
44836 /* valid when num tags is 2. */
44837 uint16_t inner_vlan_tci;
44838 /* This value sets the match value for the Source MAC address. */
44840 /* The bit length of destination IP address mask. */
44841 uint8_t ip_dst_mask_len;
44842 /* The bit length of source IP address mask. */
44843 uint8_t ip_src_mask_len;
44844 /* The value of destination IPv4/IPv6 address. */
44845 uint32_t ip_dst[4];
44846 /* The source IPv4/IPv6 address. */
44847 uint32_t ip_src[4];
44849 * The value of source port.
44850 * Applies to UDP and TCP traffic.
44852 uint16_t l4_src_port;
44854 * The value of source port mask.
44855 * Applies to UDP and TCP traffic.
44857 uint16_t l4_src_port_mask;
44859 * The value of destination port.
44860 * Applies to UDP and TCP traffic.
44862 uint16_t l4_dst_port;
44864 * The value of destination port mask.
44865 * Applies to UDP and TCP traffic.
44867 uint16_t l4_dst_port_mask;
44869 * NAT IPv4/6 address based on address type flag.
44870 * 0 values are ignored.
44872 uint32_t nat_ip_address[4];
44873 /* L2 header re-write Destination MAC address. */
44874 uint16_t l2_rewrite_dmac[3];
44876 * The NAT source/destination port based on direction flag.
44877 * Applies to UDP and TCP traffic.
44878 * 0 values are ignored.
44881 /* L2 header re-write Source MAC address. */
44882 uint16_t l2_rewrite_smac[3];
44883 /* The value of ip protocol. */
44886 uint8_t tunnel_type;
44888 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
44890 /* Virtual eXtensible Local Area Network (VXLAN) */
44891 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
44893 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
44894 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
44896 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
44897 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
44900 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
44902 /* Generic Network Virtualization Encapsulation (Geneve) */
44903 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
44905 /* Multi-Protocol Label Switching (MPLS) */
44906 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
44908 /* Stateless Transport Tunnel (STT) */
44909 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
44911 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
44912 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
44914 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
44915 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
44918 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
44921 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
44923 /* Use fixed layer 2 ether type of 0xFFFF */
44924 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
44927 * IPV6 over virtual eXtensible Local Area Network with GPE header
44930 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
44932 /* Any tunneled traffic */
44933 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
44935 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
44936 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
44939 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
44940 struct hwrm_cfa_flow_alloc_output {
44941 /* The specific error status for the command. */
44942 uint16_t error_code;
44943 /* The HWRM command request type. */
44945 /* The sequence ID from the original command. */
44947 /* The length of the response data in number of bytes. */
44949 /* Flow record index. */
44950 uint16_t flow_handle;
44951 uint8_t unused_0[2];
44953 * The flow id value in bit 0-29 is the actual ID of the flow
44954 * associated with this filter and it shall be used to match
44955 * and associate the flow identifier returned in completion
44956 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
44957 * shall indicate no valid flow id.
44960 /* Indicate the flow id value. */
44961 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
44962 UINT32_C(0x3fffffff)
44963 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
44964 /* Indicate type of the flow. */
44965 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
44966 UINT32_C(0x40000000)
44968 * If this bit set to 0, then it indicates that the flow is
44971 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
44972 (UINT32_C(0x0) << 30)
44974 * If this bit is set to 1, then it indicates that the flow is
44977 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
44978 (UINT32_C(0x1) << 30)
44979 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
44980 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
44981 /* Indicate the flow direction. */
44982 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
44983 UINT32_C(0x80000000)
44984 /* If this bit set to 0, then it indicates rx flow. */
44985 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
44986 (UINT32_C(0x0) << 31)
44987 /* If this bit is set to 1, then it indicates that tx flow. */
44988 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
44989 (UINT32_C(0x1) << 31)
44990 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
44991 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
44992 /* This value identifies a set of CFA data structures used for a flow. */
44993 uint64_t ext_flow_handle;
44994 uint32_t flow_counter_id;
44995 uint8_t unused_1[3];
44997 * This field is used in Output records to indicate that the output
44998 * is completely written to RAM. This field should be read as '1'
44999 * to indicate that the output has been completely written.
45000 * When writing a command completion or response to an internal
45001 * processor, the order of writes has to be such that this field is
45007 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
45008 struct hwrm_cfa_flow_alloc_cmd_err {
45010 * command specific error codes that goes to
45011 * the cmd_err field in Common HWRM Error Response.
45014 /* Unknown error */
45015 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
45016 /* No more L2 Context TCAM */
45017 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
45018 /* No more action records */
45019 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
45020 /* No more flow counters */
45021 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
45022 /* No more wild-card TCAM */
45023 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
45024 /* Hash collision in exact match tables */
45025 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
45026 /* Key is already installed */
45027 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
45028 /* Flow Context DB is out of resource */
45029 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
45030 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
45031 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
45032 uint8_t unused_0[7];
45035 /**********************
45036 * hwrm_cfa_flow_free *
45037 **********************/
45040 /* hwrm_cfa_flow_free_input (size:256b/32B) */
45041 struct hwrm_cfa_flow_free_input {
45042 /* The HWRM command request type. */
45045 * The completion ring to send the completion event on. This should
45046 * be the NQ ID returned from the `nq_alloc` HWRM command.
45048 uint16_t cmpl_ring;
45050 * The sequence ID is used by the driver for tracking multiple
45051 * commands. This ID is treated as opaque data by the firmware and
45052 * the value is returned in the `hwrm_resp_hdr` upon completion.
45056 * The target ID of the command:
45057 * * 0x0-0xFFF8 - The function ID
45058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45059 * * 0xFFFD - Reserved for user-space HWRM interface
45062 uint16_t target_id;
45064 * A physical address pointer pointing to a host buffer that the
45065 * command's response data will be written. This can be either a host
45066 * physical address (HPA) or a guest physical address (GPA) and must
45067 * point to a physically contiguous block of memory.
45069 uint64_t resp_addr;
45070 /* Flow record index. */
45071 uint16_t flow_handle;
45073 /* Flow counter id to be freed. */
45074 uint32_t flow_counter_id;
45075 /* This value identifies a set of CFA data structures used for a flow. */
45076 uint64_t ext_flow_handle;
45079 /* hwrm_cfa_flow_free_output (size:256b/32B) */
45080 struct hwrm_cfa_flow_free_output {
45081 /* The specific error status for the command. */
45082 uint16_t error_code;
45083 /* The HWRM command request type. */
45085 /* The sequence ID from the original command. */
45087 /* The length of the response data in number of bytes. */
45089 /* packet is 64 b */
45093 uint8_t unused_0[7];
45095 * This field is used in Output records to indicate that the output
45096 * is completely written to RAM. This field should be read as '1'
45097 * to indicate that the output has been completely written.
45098 * When writing a command completion or response to an internal
45099 * processor, the order of writes has to be such that this field is
45105 /* hwrm_cfa_flow_action_data (size:960b/120B) */
45106 struct hwrm_cfa_flow_action_data {
45107 uint16_t action_flags;
45108 /* Setting of this flag indicates accept action. */
45109 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
45111 /* Setting of this flag indicates recycle action. */
45112 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
45114 /* Setting of this flag indicates drop action. */
45115 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
45117 /* Setting of this flag indicates meter action. */
45118 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
45120 /* Setting of this flag indicates tunnel action. */
45121 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
45124 * If set to 1 and flow direction is TX, it indicates decap of L2
45125 * header and encap of tunnel header. If set to 1 and flow direction
45126 * is RX, it indicates decap of tunnel header and encap L2 header.
45128 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
45130 /* Setting of this flag indicates ttl decrement action. */
45131 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
45133 /* If set to 1, flow aging is enabled for this flow. */
45134 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
45136 /* Setting of this flag indicates encap action. */
45137 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
45139 /* Setting of this flag indicates decap action. */
45140 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
45143 uint16_t act_meter_id;
45146 /* vport number. */
45148 /* The NAT source/destination. */
45150 uint16_t unused_0[3];
45151 /* NAT IPv4/IPv6 address. */
45152 uint32_t nat_ip_address[4];
45153 /* Encapsulation Type. */
45154 uint8_t encap_type;
45155 /* Virtual eXtensible Local Area Network (VXLAN) */
45156 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
45157 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
45158 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
45159 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
45160 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
45162 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
45163 /* Generic Network Virtualization Encapsulation (Geneve) */
45164 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
45165 /* Multi-Protocol Label Switching (MPLS) */
45166 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
45168 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
45169 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
45170 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
45171 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45172 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
45174 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
45177 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
45178 /* Use fixed layer 2 ether type of 0xFFFF */
45179 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
45181 * IPV6 over virtual eXtensible Local Area Network with GPE header
45184 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45185 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
45186 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
45188 /* This value is encap data for the associated encap type. */
45189 uint32_t encap_data[20];
45192 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
45193 struct hwrm_cfa_flow_tunnel_hdr_data {
45195 uint8_t tunnel_type;
45197 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
45199 /* Virtual eXtensible Local Area Network (VXLAN) */
45200 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
45202 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
45203 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
45205 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
45206 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
45209 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
45211 /* Generic Network Virtualization Encapsulation (Geneve) */
45212 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
45214 /* Multi-Protocol Label Switching (MPLS) */
45215 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
45217 /* Stateless Transport Tunnel (STT) */
45218 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
45220 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
45221 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
45223 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45224 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
45227 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
45230 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
45232 /* Use fixed layer 2 ether type of 0xFFFF */
45233 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
45236 * IPV6 over virtual eXtensible Local Area Network with GPE header
45239 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
45241 /* Any tunneled traffic */
45242 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
45244 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
45245 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
45248 * Tunnel identifier.
45249 * Virtual Network Identifier (VNI).
45251 uint32_t tunnel_id;
45254 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
45255 struct hwrm_cfa_flow_l4_key_data {
45256 /* The value of source port. */
45257 uint16_t l4_src_port;
45258 /* The value of destination port. */
45259 uint16_t l4_dst_port;
45263 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
45264 struct hwrm_cfa_flow_l3_key_data {
45265 /* The value of ip protocol. */
45266 uint8_t ip_protocol;
45267 uint8_t unused_0[7];
45268 /* The value of destination IPv4/IPv6 address. */
45269 uint32_t ip_dst[4];
45270 /* The source IPv4/IPv6 address. */
45271 uint32_t ip_src[4];
45272 /* NAT IPv4/IPv6 address. */
45273 uint32_t nat_ip_address[4];
45274 uint32_t unused[2];
45277 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
45278 struct hwrm_cfa_flow_l2_key_data {
45279 /* Destination MAC address. */
45282 /* Source MAC address. */
45285 /* L2 header re-write Destination MAC address. */
45286 uint16_t l2_rewrite_dmac[3];
45288 /* L2 header re-write Source MAC address. */
45289 uint16_t l2_rewrite_smac[3];
45291 uint16_t ethertype;
45292 /* Number of VLAN tags. */
45293 uint16_t num_vlan_tags;
45295 uint16_t l2_rewrite_vlan_tpid;
45297 uint16_t l2_rewrite_vlan_tci;
45298 uint8_t unused_3[2];
45299 /* Outer VLAN TPID. */
45300 uint16_t ovlan_tpid;
45301 /* Outer VLAN TCI. */
45302 uint16_t ovlan_tci;
45303 /* Inner VLAN TPID. */
45304 uint16_t ivlan_tpid;
45305 /* Inner VLAN TCI. */
45306 uint16_t ivlan_tci;
45310 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
45311 struct hwrm_cfa_flow_key_data {
45312 /* Flow associated tunnel L2 header key info. */
45313 uint32_t t_l2_key_data[14];
45314 /* Flow associated tunnel L2 header mask info. */
45315 uint32_t t_l2_key_mask[14];
45316 /* Flow associated tunnel L3 header key info. */
45317 uint32_t t_l3_key_data[16];
45318 /* Flow associated tunnel L3 header mask info. */
45319 uint32_t t_l3_key_mask[16];
45320 /* Flow associated tunnel L4 header key info. */
45321 uint32_t t_l4_key_data[2];
45322 /* Flow associated tunnel L4 header mask info. */
45323 uint32_t t_l4_key_mask[2];
45324 /* Flow associated tunnel header info. */
45325 uint32_t tunnel_hdr[2];
45326 /* Flow associated L2 header key info. */
45327 uint32_t l2_key_data[14];
45328 /* Flow associated L2 header mask info. */
45329 uint32_t l2_key_mask[14];
45330 /* Flow associated L3 header key info. */
45331 uint32_t l3_key_data[16];
45332 /* Flow associated L3 header mask info. */
45333 uint32_t l3_key_mask[16];
45334 /* Flow associated L4 header key info. */
45335 uint32_t l4_key_data[2];
45336 /* Flow associated L4 header mask info. */
45337 uint32_t l4_key_mask[2];
45340 /**********************
45341 * hwrm_cfa_flow_info *
45342 **********************/
45345 /* hwrm_cfa_flow_info_input (size:256b/32B) */
45346 struct hwrm_cfa_flow_info_input {
45347 /* The HWRM command request type. */
45350 * The completion ring to send the completion event on. This should
45351 * be the NQ ID returned from the `nq_alloc` HWRM command.
45353 uint16_t cmpl_ring;
45355 * The sequence ID is used by the driver for tracking multiple
45356 * commands. This ID is treated as opaque data by the firmware and
45357 * the value is returned in the `hwrm_resp_hdr` upon completion.
45361 * The target ID of the command:
45362 * * 0x0-0xFFF8 - The function ID
45363 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45364 * * 0xFFFD - Reserved for user-space HWRM interface
45367 uint16_t target_id;
45369 * A physical address pointer pointing to a host buffer that the
45370 * command's response data will be written. This can be either a host
45371 * physical address (HPA) or a guest physical address (GPA) and must
45372 * point to a physically contiguous block of memory.
45374 uint64_t resp_addr;
45375 /* Flow record index. */
45376 uint16_t flow_handle;
45377 /* Max flow handle */
45378 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
45380 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
45381 /* CNP flow handle */
45382 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
45384 /* RoCEv1 flow handle */
45385 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
45387 /* RoCEv2 flow handle */
45388 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
45390 /* Direction rx = 1 */
45391 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
45393 uint8_t unused_0[6];
45394 /* This value identifies a set of CFA data structures used for a flow. */
45395 uint64_t ext_flow_handle;
45398 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
45399 struct hwrm_cfa_flow_info_output {
45400 /* The specific error status for the command. */
45401 uint16_t error_code;
45402 /* The HWRM command request type. */
45404 /* The sequence ID from the original command. */
45406 /* The length of the response data in number of bytes. */
45409 /* When set to 1, indicates the configuration is the TX flow. */
45410 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
45411 /* When set to 1, indicates the configuration is the RX flow. */
45412 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
45413 /* profile is 8 b */
45415 /* src_fid is 16 b */
45417 /* dst_fid is 16 b */
45419 /* l2_ctxt_id is 16 b */
45420 uint16_t l2_ctxt_id;
45421 /* em_info is 64 b */
45423 /* tcam_info is 64 b */
45424 uint64_t tcam_info;
45425 /* vfp_tcam_info is 64 b */
45426 uint64_t vfp_tcam_info;
45427 /* ar_id is 16 b */
45429 /* flow_handle is 16 b */
45430 uint16_t flow_handle;
45431 /* tunnel_handle is 32 b */
45432 uint32_t tunnel_handle;
45433 /* The flow aging timer for the flow, the unit is 100 milliseconds */
45434 uint16_t flow_timer;
45435 uint8_t unused_0[6];
45436 /* Flow associated L2, L3 and L4 headers info. */
45437 uint32_t flow_key_data[130];
45438 /* Flow associated action record info. */
45439 uint32_t flow_action_info[30];
45440 uint8_t unused_1[7];
45442 * This field is used in Output records to indicate that the output
45443 * is completely written to RAM. This field should be read as '1'
45444 * to indicate that the output has been completely written.
45445 * When writing a command completion or response to an internal
45446 * processor, the order of writes has to be such that this field is
45452 /***********************
45453 * hwrm_cfa_flow_flush *
45454 ***********************/
45457 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
45458 struct hwrm_cfa_flow_flush_input {
45459 /* The HWRM command request type. */
45462 * The completion ring to send the completion event on. This should
45463 * be the NQ ID returned from the `nq_alloc` HWRM command.
45465 uint16_t cmpl_ring;
45467 * The sequence ID is used by the driver for tracking multiple
45468 * commands. This ID is treated as opaque data by the firmware and
45469 * the value is returned in the `hwrm_resp_hdr` upon completion.
45473 * The target ID of the command:
45474 * * 0x0-0xFFF8 - The function ID
45475 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45476 * * 0xFFFD - Reserved for user-space HWRM interface
45479 uint16_t target_id;
45481 * A physical address pointer pointing to a host buffer that the
45482 * command's response data will be written. This can be either a host
45483 * physical address (HPA) or a guest physical address (GPA) and must
45484 * point to a physically contiguous block of memory.
45486 uint64_t resp_addr;
45487 /* flags is 32 b */
45490 * Set to 1 to indicate the page size, page layers, and
45491 * flow_handle_table_dma_addr fields are valid. The flow flush
45492 * operation should only flush the flows from the flow table
45493 * specified. This flag is set to 0 by older driver. For older
45494 * firmware, setting this flag has no effect.
45496 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
45499 * Set to 1 to indicate flow flush operation to cleanup all the
45500 * flows, meters, CFA context memory tables etc. This flag is set to
45501 * 0 by older driver. For older firmware, setting this flag has no
45504 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
45507 * Set to 1 to indicate flow flush operation to cleanup all the
45508 * flows by the caller. This flag is set to 0 by older driver. For
45509 * older firmware, setting this flag has no effect.
45511 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
45514 * Set to 1 to indicate the flow counter IDs are included in the
45517 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
45518 UINT32_C(0x8000000)
45520 * This specifies the size of flow handle entries provided by the
45521 * driver in the flow table specified below. Only two flow handle
45522 * size enums are defined.
45524 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
45525 UINT32_C(0xc0000000)
45526 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
45528 /* The flow handle is 16bit */
45529 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
45530 (UINT32_C(0x0) << 30)
45531 /* The flow handle is 64bit */
45532 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
45533 (UINT32_C(0x1) << 30)
45534 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
45535 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
45536 /* Specify page size of the flow table memory. */
45538 /* The page size is 4K */
45539 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
45540 /* The page size is 8K */
45541 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
45542 /* The page size is 64K */
45543 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
45544 /* The page size is 256K */
45545 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
45546 /* The page size is 1M */
45547 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
45548 /* The page size is 2M */
45549 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
45550 /* The page size is 4M */
45551 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
45552 /* The page size is 1G */
45553 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
45554 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
45555 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
45556 /* FLow table memory indirect levels. */
45557 uint8_t page_level;
45558 /* PBL pointer is physical start address. */
45559 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
45560 /* PBL pointer points to PTE table. */
45561 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
45563 * PBL pointer points to PDE table with each entry pointing to PTE
45566 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
45567 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
45568 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
45569 /* number of flows in the flow table */
45570 uint16_t num_flows;
45571 /* Pointer to the PBL, or PDL depending on number of levels */
45575 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
45576 struct hwrm_cfa_flow_flush_output {
45577 /* The specific error status for the command. */
45578 uint16_t error_code;
45579 /* The HWRM command request type. */
45581 /* The sequence ID from the original command. */
45583 /* The length of the response data in number of bytes. */
45585 uint8_t unused_0[7];
45587 * This field is used in Output records to indicate that the output
45588 * is completely written to RAM. This field should be read as '1'
45589 * to indicate that the output has been completely written.
45590 * When writing a command completion or response to an internal
45591 * processor, the order of writes has to be such that this field is
45597 /***********************
45598 * hwrm_cfa_flow_stats *
45599 ***********************/
45602 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
45603 struct hwrm_cfa_flow_stats_input {
45604 /* The HWRM command request type. */
45607 * The completion ring to send the completion event on. This should
45608 * be the NQ ID returned from the `nq_alloc` HWRM command.
45610 uint16_t cmpl_ring;
45612 * The sequence ID is used by the driver for tracking multiple
45613 * commands. This ID is treated as opaque data by the firmware and
45614 * the value is returned in the `hwrm_resp_hdr` upon completion.
45618 * The target ID of the command:
45619 * * 0x0-0xFFF8 - The function ID
45620 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45621 * * 0xFFFD - Reserved for user-space HWRM interface
45624 uint16_t target_id;
45626 * A physical address pointer pointing to a host buffer that the
45627 * command's response data will be written. This can be either a host
45628 * physical address (HPA) or a guest physical address (GPA) and must
45629 * point to a physically contiguous block of memory.
45631 uint64_t resp_addr;
45633 uint16_t num_flows;
45635 uint16_t flow_handle_0;
45637 uint16_t flow_handle_1;
45639 uint16_t flow_handle_2;
45641 uint16_t flow_handle_3;
45643 uint16_t flow_handle_4;
45645 uint16_t flow_handle_5;
45647 uint16_t flow_handle_6;
45649 uint16_t flow_handle_7;
45651 uint16_t flow_handle_8;
45653 uint16_t flow_handle_9;
45654 uint8_t unused_0[2];
45655 /* Flow ID of a flow. */
45656 uint32_t flow_id_0;
45657 /* Flow ID of a flow. */
45658 uint32_t flow_id_1;
45659 /* Flow ID of a flow. */
45660 uint32_t flow_id_2;
45661 /* Flow ID of a flow. */
45662 uint32_t flow_id_3;
45663 /* Flow ID of a flow. */
45664 uint32_t flow_id_4;
45665 /* Flow ID of a flow. */
45666 uint32_t flow_id_5;
45667 /* Flow ID of a flow. */
45668 uint32_t flow_id_6;
45669 /* Flow ID of a flow. */
45670 uint32_t flow_id_7;
45671 /* Flow ID of a flow. */
45672 uint32_t flow_id_8;
45673 /* Flow ID of a flow. */
45674 uint32_t flow_id_9;
45677 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
45678 struct hwrm_cfa_flow_stats_output {
45679 /* The specific error status for the command. */
45680 uint16_t error_code;
45681 /* The HWRM command request type. */
45683 /* The sequence ID from the original command. */
45685 /* The length of the response data in number of bytes. */
45687 /* packet_0 is 64 b */
45689 /* packet_1 is 64 b */
45691 /* packet_2 is 64 b */
45693 /* packet_3 is 64 b */
45695 /* packet_4 is 64 b */
45697 /* packet_5 is 64 b */
45699 /* packet_6 is 64 b */
45701 /* packet_7 is 64 b */
45703 /* packet_8 is 64 b */
45705 /* packet_9 is 64 b */
45707 /* byte_0 is 64 b */
45709 /* byte_1 is 64 b */
45711 /* byte_2 is 64 b */
45713 /* byte_3 is 64 b */
45715 /* byte_4 is 64 b */
45717 /* byte_5 is 64 b */
45719 /* byte_6 is 64 b */
45721 /* byte_7 is 64 b */
45723 /* byte_8 is 64 b */
45725 /* byte_9 is 64 b */
45727 uint8_t unused_0[7];
45729 * This field is used in Output records to indicate that the output
45730 * is completely written to RAM. This field should be read as '1'
45731 * to indicate that the output has been completely written.
45732 * When writing a command completion or response to an internal
45733 * processor, the order of writes has to be such that this field is
45739 /***********************************
45740 * hwrm_cfa_flow_aging_timer_reset *
45741 ***********************************/
45744 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
45745 struct hwrm_cfa_flow_aging_timer_reset_input {
45746 /* The HWRM command request type. */
45749 * The completion ring to send the completion event on. This should
45750 * be the NQ ID returned from the `nq_alloc` HWRM command.
45752 uint16_t cmpl_ring;
45754 * The sequence ID is used by the driver for tracking multiple
45755 * commands. This ID is treated as opaque data by the firmware and
45756 * the value is returned in the `hwrm_resp_hdr` upon completion.
45760 * The target ID of the command:
45761 * * 0x0-0xFFF8 - The function ID
45762 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45763 * * 0xFFFD - Reserved for user-space HWRM interface
45766 uint16_t target_id;
45768 * A physical address pointer pointing to a host buffer that the
45769 * command's response data will be written. This can be either a host
45770 * physical address (HPA) or a guest physical address (GPA) and must
45771 * point to a physically contiguous block of memory.
45773 uint64_t resp_addr;
45774 /* Flow record index. */
45775 uint16_t flow_handle;
45776 uint8_t unused_0[2];
45778 * New flow timer value for the flow specified in the ext_flow_handle.
45779 * The flow timer unit is 100ms.
45781 uint32_t flow_timer;
45782 /* This value identifies a set of CFA data structures used for a flow. */
45783 uint64_t ext_flow_handle;
45786 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
45787 struct hwrm_cfa_flow_aging_timer_reset_output {
45788 /* The specific error status for the command. */
45789 uint16_t error_code;
45790 /* The HWRM command request type. */
45792 /* The sequence ID from the original command. */
45794 /* The length of the response data in number of bytes. */
45796 uint8_t unused_0[7];
45798 * This field is used in Output records to indicate that the output
45799 * is completely written to RAM. This field should be read as '1'
45800 * to indicate that the output has been completely written.
45801 * When writing a command completion or response to an internal
45802 * processor, the order of writes has to be such that this field is
45808 /***************************
45809 * hwrm_cfa_flow_aging_cfg *
45810 ***************************/
45813 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
45814 struct hwrm_cfa_flow_aging_cfg_input {
45815 /* The HWRM command request type. */
45818 * The completion ring to send the completion event on. This should
45819 * be the NQ ID returned from the `nq_alloc` HWRM command.
45821 uint16_t cmpl_ring;
45823 * The sequence ID is used by the driver for tracking multiple
45824 * commands. This ID is treated as opaque data by the firmware and
45825 * the value is returned in the `hwrm_resp_hdr` upon completion.
45829 * The target ID of the command:
45830 * * 0x0-0xFFF8 - The function ID
45831 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45832 * * 0xFFFD - Reserved for user-space HWRM interface
45835 uint16_t target_id;
45837 * A physical address pointer pointing to a host buffer that the
45838 * command's response data will be written. This can be either a host
45839 * physical address (HPA) or a guest physical address (GPA) and must
45840 * point to a physically contiguous block of memory.
45842 uint64_t resp_addr;
45843 /* The bit field to enable per flow aging configuration. */
45846 * This bit must be '1' for the tcp flow timer field to be
45849 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
45852 * This bit must be '1' for the tcp finish timer field to be
45855 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
45858 * This bit must be '1' for the udp flow timer field to be
45861 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
45864 * This bit must be '1' for the eem dma interval field to be
45867 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
45870 * This bit must be '1' for the eem notice interval field to be
45873 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
45876 * This bit must be '1' for the eem context memory maximum entries
45877 * field to be configured
45879 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
45882 * This bit must be '1' for the eem context memory ID field to be
45885 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
45888 * This bit must be '1' for the eem context memory type field to be
45891 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
45894 /* Enumeration denoting the RX, TX type of the resource. */
45895 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
45897 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
45899 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
45900 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
45901 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
45903 * Enumeration denoting the enable, disable eem flow aging
45906 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
45908 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
45909 (UINT32_C(0x0) << 1)
45911 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
45912 (UINT32_C(0x1) << 1)
45913 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
45914 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
45917 * The flow aging timer for all TCP flows, the unit is 100
45920 uint32_t tcp_flow_timer;
45922 * The TCP finished timer for all TCP flows, the unit is 100
45925 uint32_t tcp_fin_timer;
45927 * The flow aging timer for all UDP flows, the unit is 100
45930 uint32_t udp_flow_timer;
45932 * The interval to dma eem ejection data to host memory, the unit is
45935 uint16_t eem_dma_interval;
45937 * The interval to notify driver to read the eem ejection data, the
45938 * unit is milliseconds.
45940 uint16_t eem_notice_interval;
45941 /* The maximum entries number in the eem context memory. */
45942 uint32_t eem_ctx_max_entries;
45943 /* The context memory ID for eem flow aging. */
45944 uint16_t eem_ctx_id;
45945 uint16_t eem_ctx_mem_type;
45947 * The content of context memory is eem ejection data, the size of
45948 * each entry is 4 bytes.
45950 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
45952 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
45953 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
45954 uint8_t unused_1[4];
45957 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
45958 struct hwrm_cfa_flow_aging_cfg_output {
45959 /* The specific error status for the command. */
45960 uint16_t error_code;
45961 /* The HWRM command request type. */
45963 /* The sequence ID from the original command. */
45965 /* The length of the response data in number of bytes. */
45967 uint8_t unused_0[7];
45969 * This field is used in Output records to indicate that the output
45970 * is completely written to RAM. This field should be read as '1'
45971 * to indicate that the output has been completely written.
45972 * When writing a command completion or response to an internal
45973 * processor, the order of writes has to be such that this field is
45979 /****************************
45980 * hwrm_cfa_flow_aging_qcfg *
45981 ****************************/
45984 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
45985 struct hwrm_cfa_flow_aging_qcfg_input {
45986 /* The HWRM command request type. */
45989 * The completion ring to send the completion event on. This should
45990 * be the NQ ID returned from the `nq_alloc` HWRM command.
45992 uint16_t cmpl_ring;
45994 * The sequence ID is used by the driver for tracking multiple
45995 * commands. This ID is treated as opaque data by the firmware and
45996 * the value is returned in the `hwrm_resp_hdr` upon completion.
46000 * The target ID of the command:
46001 * * 0x0-0xFFF8 - The function ID
46002 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46003 * * 0xFFFD - Reserved for user-space HWRM interface
46006 uint16_t target_id;
46008 * A physical address pointer pointing to a host buffer that the
46009 * command's response data will be written. This can be either a host
46010 * physical address (HPA) or a guest physical address (GPA) and must
46011 * point to a physically contiguous block of memory.
46013 uint64_t resp_addr;
46015 * The direction for the flow aging configuration, 1 is rx path, 2 is
46019 /* Enumeration denoting the RX, TX type of the resource. */
46020 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
46022 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
46024 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
46025 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
46026 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
46027 uint8_t unused_0[7];
46030 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
46031 struct hwrm_cfa_flow_aging_qcfg_output {
46032 /* The specific error status for the command. */
46033 uint16_t error_code;
46034 /* The HWRM command request type. */
46036 /* The sequence ID from the original command. */
46038 /* The length of the response data in number of bytes. */
46041 * The current flow aging timer for all TCP flows, the unit is 100
46044 uint32_t tcp_flow_timer;
46046 * The current TCP finished timer for all TCP flows, the unit is 100
46049 uint32_t tcp_fin_timer;
46051 * The current flow aging timer for all UDP flows, the unit is 100
46054 uint32_t udp_flow_timer;
46056 * The interval to dma eem ejection data to host memory, the unit is
46059 uint16_t eem_dma_interval;
46061 * The interval to notify driver to read the eem ejection data, the
46062 * unit is milliseconds.
46064 uint16_t eem_notice_interval;
46065 /* The maximum entries number in the eem context memory. */
46066 uint32_t eem_ctx_max_entries;
46067 /* The context memory ID for eem flow aging. */
46068 uint16_t eem_ctx_id;
46069 /* The context memory type for eem flow aging. */
46070 uint16_t eem_ctx_mem_type;
46071 uint8_t unused_0[7];
46073 * This field is used in Output records to indicate that the output
46074 * is completely written to RAM. This field should be read as '1'
46075 * to indicate that the output has been completely written.
46076 * When writing a command completion or response to an internal
46077 * processor, the order of writes has to be such that this field is
46083 /*****************************
46084 * hwrm_cfa_flow_aging_qcaps *
46085 *****************************/
46088 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
46089 struct hwrm_cfa_flow_aging_qcaps_input {
46090 /* The HWRM command request type. */
46093 * The completion ring to send the completion event on. This should
46094 * be the NQ ID returned from the `nq_alloc` HWRM command.
46096 uint16_t cmpl_ring;
46098 * The sequence ID is used by the driver for tracking multiple
46099 * commands. This ID is treated as opaque data by the firmware and
46100 * the value is returned in the `hwrm_resp_hdr` upon completion.
46104 * The target ID of the command:
46105 * * 0x0-0xFFF8 - The function ID
46106 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46107 * * 0xFFFD - Reserved for user-space HWRM interface
46110 uint16_t target_id;
46112 * A physical address pointer pointing to a host buffer that the
46113 * command's response data will be written. This can be either a host
46114 * physical address (HPA) or a guest physical address (GPA) and must
46115 * point to a physically contiguous block of memory.
46117 uint64_t resp_addr;
46119 * The direction for the flow aging configuration, 1 is rx path, 2 is
46123 /* Enumeration denoting the RX, TX type of the resource. */
46124 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
46126 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
46128 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
46129 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
46130 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
46131 uint8_t unused_0[7];
46134 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
46135 struct hwrm_cfa_flow_aging_qcaps_output {
46136 /* The specific error status for the command. */
46137 uint16_t error_code;
46138 /* The HWRM command request type. */
46140 /* The sequence ID from the original command. */
46142 /* The length of the response data in number of bytes. */
46145 * The maximum flow aging timer for all TCP flows, the unit is 100
46148 uint32_t max_tcp_flow_timer;
46150 * The maximum TCP finished timer for all TCP flows, the unit is 100
46153 uint32_t max_tcp_fin_timer;
46155 * The maximum flow aging timer for all UDP flows, the unit is 100
46158 uint32_t max_udp_flow_timer;
46159 /* The maximum aging flows that HW can support. */
46160 uint32_t max_aging_flows;
46161 uint8_t unused_0[7];
46163 * This field is used in Output records to indicate that the output
46164 * is completely written to RAM. This field should be read as '1'
46165 * to indicate that the output has been completely written.
46166 * When writing a command completion or response to an internal
46167 * processor, the order of writes has to be such that this field is
46173 /**********************************
46174 * hwrm_cfa_tcp_flag_process_qcfg *
46175 **********************************/
46178 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
46179 struct hwrm_cfa_tcp_flag_process_qcfg_input {
46180 /* The HWRM command request type. */
46183 * The completion ring to send the completion event on. This should
46184 * be the NQ ID returned from the `nq_alloc` HWRM command.
46186 uint16_t cmpl_ring;
46188 * The sequence ID is used by the driver for tracking multiple
46189 * commands. This ID is treated as opaque data by the firmware and
46190 * the value is returned in the `hwrm_resp_hdr` upon completion.
46194 * The target ID of the command:
46195 * * 0x0-0xFFF8 - The function ID
46196 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46197 * * 0xFFFD - Reserved for user-space HWRM interface
46200 uint16_t target_id;
46202 * A physical address pointer pointing to a host buffer that the
46203 * command's response data will be written. This can be either a host
46204 * physical address (HPA) or a guest physical address (GPA) and must
46205 * point to a physically contiguous block of memory.
46207 uint64_t resp_addr;
46210 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
46211 struct hwrm_cfa_tcp_flag_process_qcfg_output {
46212 /* The specific error status for the command. */
46213 uint16_t error_code;
46214 /* The HWRM command request type. */
46216 /* The sequence ID from the original command. */
46218 /* The length of the response data in number of bytes. */
46220 /* The port 0 RX mirror action record ID. */
46221 uint16_t rx_ar_id_port0;
46222 /* The port 1 RX mirror action record ID. */
46223 uint16_t rx_ar_id_port1;
46225 * The port 0 RX action record ID for TX TCP flag packets from
46228 uint16_t tx_ar_id_port0;
46230 * The port 1 RX action record ID for TX TCP flag packets from
46233 uint16_t tx_ar_id_port1;
46234 uint8_t unused_0[7];
46236 * This field is used in Output records to indicate that the output
46237 * is completely written to RAM. This field should be read as '1'
46238 * to indicate that the output has been completely written.
46239 * When writing a command completion or response to an internal
46240 * processor, the order of writes has to be such that this field is
46246 /**************************
46247 * hwrm_cfa_vf_pair_alloc *
46248 **************************/
46251 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
46252 struct hwrm_cfa_vf_pair_alloc_input {
46253 /* The HWRM command request type. */
46256 * The completion ring to send the completion event on. This should
46257 * be the NQ ID returned from the `nq_alloc` HWRM command.
46259 uint16_t cmpl_ring;
46261 * The sequence ID is used by the driver for tracking multiple
46262 * commands. This ID is treated as opaque data by the firmware and
46263 * the value is returned in the `hwrm_resp_hdr` upon completion.
46267 * The target ID of the command:
46268 * * 0x0-0xFFF8 - The function ID
46269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46270 * * 0xFFFD - Reserved for user-space HWRM interface
46273 uint16_t target_id;
46275 * A physical address pointer pointing to a host buffer that the
46276 * command's response data will be written. This can be either a host
46277 * physical address (HPA) or a guest physical address (GPA) and must
46278 * point to a physically contiguous block of memory.
46280 uint64_t resp_addr;
46281 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46283 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46285 uint8_t unused_0[4];
46286 /* VF Pair name (32 byte string). */
46287 char pair_name[32];
46290 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
46291 struct hwrm_cfa_vf_pair_alloc_output {
46292 /* The specific error status for the command. */
46293 uint16_t error_code;
46294 /* The HWRM command request type. */
46296 /* The sequence ID from the original command. */
46298 /* The length of the response data in number of bytes. */
46300 uint8_t unused_0[7];
46302 * This field is used in Output records to indicate that the output
46303 * is completely written to RAM. This field should be read as '1'
46304 * to indicate that the output has been completely written.
46305 * When writing a command completion or response to an internal
46306 * processor, the order of writes has to be such that this field is
46312 /*************************
46313 * hwrm_cfa_vf_pair_free *
46314 *************************/
46317 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
46318 struct hwrm_cfa_vf_pair_free_input {
46319 /* The HWRM command request type. */
46322 * The completion ring to send the completion event on. This should
46323 * be the NQ ID returned from the `nq_alloc` HWRM command.
46325 uint16_t cmpl_ring;
46327 * The sequence ID is used by the driver for tracking multiple
46328 * commands. This ID is treated as opaque data by the firmware and
46329 * the value is returned in the `hwrm_resp_hdr` upon completion.
46333 * The target ID of the command:
46334 * * 0x0-0xFFF8 - The function ID
46335 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46336 * * 0xFFFD - Reserved for user-space HWRM interface
46339 uint16_t target_id;
46341 * A physical address pointer pointing to a host buffer that the
46342 * command's response data will be written. This can be either a host
46343 * physical address (HPA) or a guest physical address (GPA) and must
46344 * point to a physically contiguous block of memory.
46346 uint64_t resp_addr;
46347 /* VF Pair name (32 byte string). */
46348 char pair_name[32];
46351 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
46352 struct hwrm_cfa_vf_pair_free_output {
46353 /* The specific error status for the command. */
46354 uint16_t error_code;
46355 /* The HWRM command request type. */
46357 /* The sequence ID from the original command. */
46359 /* The length of the response data in number of bytes. */
46361 uint8_t unused_0[7];
46363 * This field is used in Output records to indicate that the output
46364 * is completely written to RAM. This field should be read as '1'
46365 * to indicate that the output has been completely written.
46366 * When writing a command completion or response to an internal
46367 * processor, the order of writes has to be such that this field is
46373 /*************************
46374 * hwrm_cfa_vf_pair_info *
46375 *************************/
46378 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
46379 struct hwrm_cfa_vf_pair_info_input {
46380 /* The HWRM command request type. */
46383 * The completion ring to send the completion event on. This should
46384 * be the NQ ID returned from the `nq_alloc` HWRM command.
46386 uint16_t cmpl_ring;
46388 * The sequence ID is used by the driver for tracking multiple
46389 * commands. This ID is treated as opaque data by the firmware and
46390 * the value is returned in the `hwrm_resp_hdr` upon completion.
46394 * The target ID of the command:
46395 * * 0x0-0xFFF8 - The function ID
46396 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46397 * * 0xFFFD - Reserved for user-space HWRM interface
46400 uint16_t target_id;
46402 * A physical address pointer pointing to a host buffer that the
46403 * command's response data will be written. This can be either a host
46404 * physical address (HPA) or a guest physical address (GPA) and must
46405 * point to a physically contiguous block of memory.
46407 uint64_t resp_addr;
46409 /* If this flag is set, lookup by name else lookup by index. */
46410 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
46411 /* vf pair table index. */
46412 uint16_t vf_pair_index;
46413 uint8_t unused_0[2];
46414 /* VF Pair name (32 byte string). */
46415 char vf_pair_name[32];
46418 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
46419 struct hwrm_cfa_vf_pair_info_output {
46420 /* The specific error status for the command. */
46421 uint16_t error_code;
46422 /* The HWRM command request type. */
46424 /* The sequence ID from the original command. */
46426 /* The length of the response data in number of bytes. */
46428 /* vf pair table index. */
46429 uint16_t next_vf_pair_index;
46430 /* vf pair member a's vf_fid. */
46432 /* vf pair member a's Linux logical VF number. */
46433 uint16_t vf_a_index;
46434 /* vf pair member b's vf_fid. */
46436 /* vf pair member a's Linux logical VF number. */
46437 uint16_t vf_b_index;
46438 /* vf pair state. */
46439 uint8_t pair_state;
46440 /* Pair has been allocated */
46441 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
46442 /* Both pair members are active */
46443 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
46444 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
46445 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
46446 uint8_t unused_0[5];
46447 /* VF Pair name (32 byte string). */
46448 char pair_name[32];
46449 uint8_t unused_1[7];
46451 * This field is used in Output records to indicate that the output
46452 * is completely written to RAM. This field should be read as '1'
46453 * to indicate that the output has been completely written.
46454 * When writing a command completion or response to an internal
46455 * processor, the order of writes has to be such that this field is
46461 /***********************
46462 * hwrm_cfa_pair_alloc *
46463 ***********************/
46466 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
46467 struct hwrm_cfa_pair_alloc_input {
46468 /* The HWRM command request type. */
46471 * The completion ring to send the completion event on. This should
46472 * be the NQ ID returned from the `nq_alloc` HWRM command.
46474 uint16_t cmpl_ring;
46476 * The sequence ID is used by the driver for tracking multiple
46477 * commands. This ID is treated as opaque data by the firmware and
46478 * the value is returned in the `hwrm_resp_hdr` upon completion.
46482 * The target ID of the command:
46483 * * 0x0-0xFFF8 - The function ID
46484 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46485 * * 0xFFFD - Reserved for user-space HWRM interface
46488 uint16_t target_id;
46490 * A physical address pointer pointing to a host buffer that the
46491 * command's response data will be written. This can be either a host
46492 * physical address (HPA) or a guest physical address (GPA) and must
46493 * point to a physically contiguous block of memory.
46495 uint64_t resp_addr;
46497 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
46498 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
46500 uint16_t pair_mode;
46501 /* Pair between VF on local host with PF or VF on specified host. */
46502 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
46504 /* Pair between REP on local host with PF or VF on specified host. */
46505 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
46507 /* Pair between REP on local host with REP on specified host. */
46508 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
46510 /* Pair for the proxy interface. */
46511 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
46513 /* Pair for the PF interface. */
46514 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
46516 /* Modify existing rep2fn pair and move pair to new PF. */
46517 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
46520 * Modify existing rep2fn pairs paired with same PF and move pairs
46523 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
46526 * Truflow pair between REP on local host with PF or VF on specified
46529 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
46531 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
46532 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
46533 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46535 /* Logical Host (0xff-local host). */
46537 /* Logical PF (0xff-PF for command channel). */
46539 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46541 /* Loopback port (0xff-internal loopback), valid for mode-3. */
46543 /* Priority used for encap of loopback packets valid for mode-3. */
46545 /* New PF for rep2fn modify, valid for mode 5. */
46546 uint16_t new_pf_fid;
46549 * This bit must be '1' for the q_ab field to be
46552 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
46554 * This bit must be '1' for the q_ba field to be
46557 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
46559 * This bit must be '1' for the fc_ab field to be
46562 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
46564 * This bit must be '1' for the fc_ba field to be
46567 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
46568 /* VF Pair name (32 byte string). */
46569 char pair_name[32];
46571 * The q_ab value specifies the logical index of the TX/RX CoS
46572 * queue to be assigned for traffic in the A to B direction of
46573 * the interface pair. The default value is 0.
46577 * The q_ba value specifies the logical index of the TX/RX CoS
46578 * queue to be assigned for traffic in the B to A direction of
46579 * the interface pair. The default value is 1.
46583 * Specifies whether RX ring flow control is disabled (0) or enabled
46584 * (1) in the A to B direction. The default value is 0, meaning that
46585 * packets will be dropped when the B-side RX rings are full.
46589 * Specifies whether RX ring flow control is disabled (0) or enabled
46590 * (1) in the B to A direction. The default value is 1, meaning that
46591 * the RX CoS queue will be flow controlled when the A-side RX rings
46595 uint8_t unused_1[4];
46598 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
46599 struct hwrm_cfa_pair_alloc_output {
46600 /* The specific error status for the command. */
46601 uint16_t error_code;
46602 /* The HWRM command request type. */
46604 /* The sequence ID from the original command. */
46606 /* The length of the response data in number of bytes. */
46608 /* Only valid for modes 1 and 2. */
46609 uint16_t rx_cfa_code_a;
46610 /* Only valid for modes 1 and 2. */
46611 uint16_t tx_cfa_action_a;
46612 /* Only valid for mode 2. */
46613 uint16_t rx_cfa_code_b;
46614 /* Only valid for mode 2. */
46615 uint16_t tx_cfa_action_b;
46616 uint8_t unused_0[7];
46618 * This field is used in Output records to indicate that the output
46619 * is completely written to RAM. This field should be read as '1'
46620 * to indicate that the output has been completely written.
46621 * When writing a command completion or response to an internal
46622 * processor, the order of writes has to be such that this field is
46628 /**********************
46629 * hwrm_cfa_pair_free *
46630 **********************/
46633 /* hwrm_cfa_pair_free_input (size:448b/56B) */
46634 struct hwrm_cfa_pair_free_input {
46635 /* The HWRM command request type. */
46638 * The completion ring to send the completion event on. This should
46639 * be the NQ ID returned from the `nq_alloc` HWRM command.
46641 uint16_t cmpl_ring;
46643 * The sequence ID is used by the driver for tracking multiple
46644 * commands. This ID is treated as opaque data by the firmware and
46645 * the value is returned in the `hwrm_resp_hdr` upon completion.
46649 * The target ID of the command:
46650 * * 0x0-0xFFF8 - The function ID
46651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46652 * * 0xFFFD - Reserved for user-space HWRM interface
46655 uint16_t target_id;
46657 * A physical address pointer pointing to a host buffer that the
46658 * command's response data will be written. This can be either a host
46659 * physical address (HPA) or a guest physical address (GPA) and must
46660 * point to a physically contiguous block of memory.
46662 uint64_t resp_addr;
46663 /* VF Pair name (32 byte string). */
46664 char pair_name[32];
46665 /* Logical PF (0xff-PF for command channel). */
46667 uint8_t unused_0[3];
46668 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46671 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
46672 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
46674 uint16_t pair_mode;
46675 /* Pair between VF on local host with PF or VF on specified host. */
46676 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
46677 /* Pair between REP on local host with PF or VF on specified host. */
46678 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
46679 /* Pair between REP on local host with REP on specified host. */
46680 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
46681 /* Pair for the proxy interface. */
46682 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
46683 /* Pair for the PF interface. */
46684 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
46685 /* Modify existing rep2fn pair and move pair to new PF. */
46686 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
46688 * Modify existing rep2fn pairs paired with same PF and move pairs
46691 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
46693 * Truflow pair between REP on local host with PF or VF on
46696 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
46697 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
46698 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
46701 /* hwrm_cfa_pair_free_output (size:128b/16B) */
46702 struct hwrm_cfa_pair_free_output {
46703 /* The specific error status for the command. */
46704 uint16_t error_code;
46705 /* The HWRM command request type. */
46707 /* The sequence ID from the original command. */
46709 /* The length of the response data in number of bytes. */
46711 uint8_t unused_0[7];
46713 * This field is used in Output records to indicate that the output
46714 * is completely written to RAM. This field should be read as '1'
46715 * to indicate that the output has been completely written.
46716 * When writing a command completion or response to an internal
46717 * processor, the order of writes has to be such that this field is
46723 /**********************
46724 * hwrm_cfa_pair_info *
46725 **********************/
46728 /* hwrm_cfa_pair_info_input (size:448b/56B) */
46729 struct hwrm_cfa_pair_info_input {
46730 /* The HWRM command request type. */
46733 * The completion ring to send the completion event on. This should
46734 * be the NQ ID returned from the `nq_alloc` HWRM command.
46736 uint16_t cmpl_ring;
46738 * The sequence ID is used by the driver for tracking multiple
46739 * commands. This ID is treated as opaque data by the firmware and
46740 * the value is returned in the `hwrm_resp_hdr` upon completion.
46744 * The target ID of the command:
46745 * * 0x0-0xFFF8 - The function ID
46746 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46747 * * 0xFFFD - Reserved for user-space HWRM interface
46750 uint16_t target_id;
46752 * A physical address pointer pointing to a host buffer that the
46753 * command's response data will be written. This can be either a host
46754 * physical address (HPA) or a guest physical address (GPA) and must
46755 * point to a physically contiguous block of memory.
46757 uint64_t resp_addr;
46759 /* If this flag is set, lookup by name else lookup by index. */
46760 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
46761 /* If this flag is set, lookup by PF id and VF id. */
46762 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
46763 /* Pair table index. */
46764 uint16_t pair_index;
46765 /* Pair pf index. */
46767 /* Pair vf index. */
46769 /* Pair name (32 byte string). */
46770 char pair_name[32];
46773 /* hwrm_cfa_pair_info_output (size:576b/72B) */
46774 struct hwrm_cfa_pair_info_output {
46775 /* The specific error status for the command. */
46776 uint16_t error_code;
46777 /* The HWRM command request type. */
46779 /* The sequence ID from the original command. */
46781 /* The length of the response data in number of bytes. */
46783 /* Pair table index. */
46784 uint16_t next_pair_index;
46785 /* Pair member a's fid. */
46787 /* Logical host number. */
46788 uint8_t host_a_index;
46789 /* Logical PF number. */
46790 uint8_t pf_a_index;
46791 /* Pair member a's Linux logical VF number. */
46792 uint16_t vf_a_index;
46794 uint16_t rx_cfa_code_a;
46795 /* Tx CFA action. */
46796 uint16_t tx_cfa_action_a;
46797 /* Pair member b's fid. */
46799 /* Logical host number. */
46800 uint8_t host_b_index;
46801 /* Logical PF number. */
46802 uint8_t pf_b_index;
46803 /* Pair member a's Linux logical VF number. */
46804 uint16_t vf_b_index;
46806 uint16_t rx_cfa_code_b;
46807 /* Tx CFA action. */
46808 uint16_t tx_cfa_action_b;
46809 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
46811 /* Pair between VF on local host with PF or VF on specified host. */
46812 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
46813 /* Pair between REP on local host with PF or VF on specified host. */
46814 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
46815 /* Pair between REP on local host with REP on specified host. */
46816 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
46817 /* Pair for the proxy interface. */
46818 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
46819 /* Pair for the PF interface. */
46820 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
46821 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
46822 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
46824 uint8_t pair_state;
46825 /* Pair has been allocated */
46826 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
46827 /* Both pair members are active */
46828 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
46829 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
46830 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
46831 /* Pair name (32 byte string). */
46832 char pair_name[32];
46833 uint8_t unused_0[7];
46835 * This field is used in Output records to indicate that the output
46836 * is completely written to RAM. This field should be read as '1'
46837 * to indicate that the output has been completely written.
46838 * When writing a command completion or response to an internal
46839 * processor, the order of writes has to be such that this field is
46845 /**********************
46846 * hwrm_cfa_vfr_alloc *
46847 **********************/
46850 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
46851 struct hwrm_cfa_vfr_alloc_input {
46852 /* The HWRM command request type. */
46855 * The completion ring to send the completion event on. This should
46856 * be the NQ ID returned from the `nq_alloc` HWRM command.
46858 uint16_t cmpl_ring;
46860 * The sequence ID is used by the driver for tracking multiple
46861 * commands. This ID is treated as opaque data by the firmware and
46862 * the value is returned in the `hwrm_resp_hdr` upon completion.
46866 * The target ID of the command:
46867 * * 0x0-0xFFF8 - The function ID
46868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46869 * * 0xFFFD - Reserved for user-space HWRM interface
46872 uint16_t target_id;
46874 * A physical address pointer pointing to a host buffer that the
46875 * command's response data will be written. This can be either a host
46876 * physical address (HPA) or a guest physical address (GPA) and must
46877 * point to a physically contiguous block of memory.
46879 uint64_t resp_addr;
46880 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46883 * This field is reserved for the future use.
46884 * It shall be set to 0.
46887 uint8_t unused_0[4];
46888 /* VF Representor name (32 byte string). */
46892 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
46893 struct hwrm_cfa_vfr_alloc_output {
46894 /* The specific error status for the command. */
46895 uint16_t error_code;
46896 /* The HWRM command request type. */
46898 /* The sequence ID from the original command. */
46900 /* The length of the response data in number of bytes. */
46903 uint16_t rx_cfa_code;
46904 /* Tx CFA action. */
46905 uint16_t tx_cfa_action;
46906 uint8_t unused_0[3];
46908 * This field is used in Output records to indicate that the output
46909 * is completely written to RAM. This field should be read as '1'
46910 * to indicate that the output has been completely written.
46911 * When writing a command completion or response to an internal
46912 * processor, the order of writes has to be such that this field is
46918 /*********************
46919 * hwrm_cfa_vfr_free *
46920 *********************/
46923 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
46924 struct hwrm_cfa_vfr_free_input {
46925 /* The HWRM command request type. */
46928 * The completion ring to send the completion event on. This should
46929 * be the NQ ID returned from the `nq_alloc` HWRM command.
46931 uint16_t cmpl_ring;
46933 * The sequence ID is used by the driver for tracking multiple
46934 * commands. This ID is treated as opaque data by the firmware and
46935 * the value is returned in the `hwrm_resp_hdr` upon completion.
46939 * The target ID of the command:
46940 * * 0x0-0xFFF8 - The function ID
46941 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46942 * * 0xFFFD - Reserved for user-space HWRM interface
46945 uint16_t target_id;
46947 * A physical address pointer pointing to a host buffer that the
46948 * command's response data will be written. This can be either a host
46949 * physical address (HPA) or a guest physical address (GPA) and must
46950 * point to a physically contiguous block of memory.
46952 uint64_t resp_addr;
46953 /* VF Representor name (32 byte string). */
46955 /* Logical VF number (range: 0 -> MAX_VFS -1). */
46958 * This field is reserved for the future use.
46959 * It shall be set to 0.
46962 uint8_t unused_0[4];
46965 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
46966 struct hwrm_cfa_vfr_free_output {
46967 /* The specific error status for the command. */
46968 uint16_t error_code;
46969 /* The HWRM command request type. */
46971 /* The sequence ID from the original command. */
46973 /* The length of the response data in number of bytes. */
46975 uint8_t unused_0[7];
46977 * This field is used in Output records to indicate that the output
46978 * is completely written to RAM. This field should be read as '1'
46979 * to indicate that the output has been completely written.
46980 * When writing a command completion or response to an internal
46981 * processor, the order of writes has to be such that this field is
46987 /***************************************
46988 * hwrm_cfa_redirect_query_tunnel_type *
46989 ***************************************/
46992 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
46993 struct hwrm_cfa_redirect_query_tunnel_type_input {
46994 /* The HWRM command request type. */
46997 * The completion ring to send the completion event on. This should
46998 * be the NQ ID returned from the `nq_alloc` HWRM command.
47000 uint16_t cmpl_ring;
47002 * The sequence ID is used by the driver for tracking multiple
47003 * commands. This ID is treated as opaque data by the firmware and
47004 * the value is returned in the `hwrm_resp_hdr` upon completion.
47008 * The target ID of the command:
47009 * * 0x0-0xFFF8 - The function ID
47010 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47011 * * 0xFFFD - Reserved for user-space HWRM interface
47014 uint16_t target_id;
47016 * A physical address pointer pointing to a host buffer that the
47017 * command's response data will be written. This can be either a host
47018 * physical address (HPA) or a guest physical address (GPA) and must
47019 * point to a physically contiguous block of memory.
47021 uint64_t resp_addr;
47022 /* The source function id. */
47024 uint8_t unused_0[6];
47027 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
47028 struct hwrm_cfa_redirect_query_tunnel_type_output {
47029 /* The specific error status for the command. */
47030 uint16_t error_code;
47031 /* The HWRM command request type. */
47033 /* The sequence ID from the original command. */
47035 /* The length of the response data in number of bytes. */
47038 uint32_t tunnel_mask;
47040 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
47042 /* Virtual eXtensible Local Area Network (VXLAN) */
47043 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
47045 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
47046 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
47048 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
47049 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
47052 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
47054 /* Generic Network Virtualization Encapsulation (Geneve) */
47055 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
47057 /* Multi-Protocol Label Switching (MPLS) */
47058 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
47060 /* Stateless Transport Tunnel (STT) */
47061 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
47063 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
47064 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
47066 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
47067 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
47070 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
47073 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
47075 /* Any tunneled traffic */
47076 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
47078 /* Use fixed layer 2 ether type of 0xFFFF */
47079 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
47082 * IPV6 over virtual eXtensible Local Area Network with GPE header
47085 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
47087 uint8_t unused_0[3];
47089 * This field is used in Output records to indicate that the output
47090 * is completely written to RAM. This field should be read as '1'
47091 * to indicate that the output has been completely written.
47092 * When writing a command completion or response to an internal
47093 * processor, the order of writes has to be such that this field is
47099 /*************************
47100 * hwrm_cfa_ctx_mem_rgtr *
47101 *************************/
47104 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
47105 struct hwrm_cfa_ctx_mem_rgtr_input {
47106 /* The HWRM command request type. */
47109 * The completion ring to send the completion event on. This should
47110 * be the NQ ID returned from the `nq_alloc` HWRM command.
47112 uint16_t cmpl_ring;
47114 * The sequence ID is used by the driver for tracking multiple
47115 * commands. This ID is treated as opaque data by the firmware and
47116 * the value is returned in the `hwrm_resp_hdr` upon completion.
47120 * The target ID of the command:
47121 * * 0x0-0xFFF8 - The function ID
47122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47123 * * 0xFFFD - Reserved for user-space HWRM interface
47126 uint16_t target_id;
47128 * A physical address pointer pointing to a host buffer that the
47129 * command's response data will be written. This can be either a host
47130 * physical address (HPA) or a guest physical address (GPA) and must
47131 * point to a physically contiguous block of memory.
47133 uint64_t resp_addr;
47135 /* Counter PBL indirect levels. */
47136 uint8_t page_level;
47137 /* PBL pointer is physical start address. */
47138 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
47139 /* PBL pointer points to PTE table. */
47140 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
47142 * PBL pointer points to PDE table with each entry pointing to PTE
47145 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
47146 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
47147 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
47150 /* 4KB page size. */
47151 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
47152 /* 8KB page size. */
47153 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
47154 /* 64KB page size. */
47155 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
47156 /* 256KB page size. */
47157 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
47158 /* 1MB page size. */
47159 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
47160 /* 2MB page size. */
47161 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
47162 /* 4MB page size. */
47163 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
47164 /* 1GB page size. */
47165 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
47166 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
47167 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
47169 /* Pointer to the PBL, or PDL depending on number of levels */
47173 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
47174 struct hwrm_cfa_ctx_mem_rgtr_output {
47175 /* The specific error status for the command. */
47176 uint16_t error_code;
47177 /* The HWRM command request type. */
47179 /* The sequence ID from the original command. */
47181 /* The length of the response data in number of bytes. */
47184 * Id/Handle to the recently register context memory. This handle is
47185 * passed to the CFA feature.
47188 uint8_t unused_0[5];
47190 * This field is used in Output records to indicate that the output
47191 * is completely written to RAM. This field should be read as '1'
47192 * to indicate that the output has been completely written.
47193 * When writing a command completion or response to an internal
47194 * processor, the order of writes has to be such that this field is
47200 /***************************
47201 * hwrm_cfa_ctx_mem_unrgtr *
47202 ***************************/
47205 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
47206 struct hwrm_cfa_ctx_mem_unrgtr_input {
47207 /* The HWRM command request type. */
47210 * The completion ring to send the completion event on. This should
47211 * be the NQ ID returned from the `nq_alloc` HWRM command.
47213 uint16_t cmpl_ring;
47215 * The sequence ID is used by the driver for tracking multiple
47216 * commands. This ID is treated as opaque data by the firmware and
47217 * the value is returned in the `hwrm_resp_hdr` upon completion.
47221 * The target ID of the command:
47222 * * 0x0-0xFFF8 - The function ID
47223 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47224 * * 0xFFFD - Reserved for user-space HWRM interface
47227 uint16_t target_id;
47229 * A physical address pointer pointing to a host buffer that the
47230 * command's response data will be written. This can be either a host
47231 * physical address (HPA) or a guest physical address (GPA) and must
47232 * point to a physically contiguous block of memory.
47234 uint64_t resp_addr;
47236 * Id/Handle to the recently register context memory. This handle is
47237 * passed to the CFA feature.
47240 uint8_t unused_0[6];
47243 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
47244 struct hwrm_cfa_ctx_mem_unrgtr_output {
47245 /* The specific error status for the command. */
47246 uint16_t error_code;
47247 /* The HWRM command request type. */
47249 /* The sequence ID from the original command. */
47251 /* The length of the response data in number of bytes. */
47253 uint8_t unused_0[7];
47255 * This field is used in Output records to indicate that the output
47256 * is completely written to RAM. This field should be read as '1'
47257 * to indicate that the output has been completely written.
47258 * When writing a command completion or response to an internal
47259 * processor, the order of writes has to be such that this field is
47265 /*************************
47266 * hwrm_cfa_ctx_mem_qctx *
47267 *************************/
47270 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
47271 struct hwrm_cfa_ctx_mem_qctx_input {
47272 /* The HWRM command request type. */
47275 * The completion ring to send the completion event on. This should
47276 * be the NQ ID returned from the `nq_alloc` HWRM command.
47278 uint16_t cmpl_ring;
47280 * The sequence ID is used by the driver for tracking multiple
47281 * commands. This ID is treated as opaque data by the firmware and
47282 * the value is returned in the `hwrm_resp_hdr` upon completion.
47286 * The target ID of the command:
47287 * * 0x0-0xFFF8 - The function ID
47288 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47289 * * 0xFFFD - Reserved for user-space HWRM interface
47292 uint16_t target_id;
47294 * A physical address pointer pointing to a host buffer that the
47295 * command's response data will be written. This can be either a host
47296 * physical address (HPA) or a guest physical address (GPA) and must
47297 * point to a physically contiguous block of memory.
47299 uint64_t resp_addr;
47301 * Id/Handle to the recently register context memory. This handle is
47302 * passed to the CFA feature.
47305 uint8_t unused_0[6];
47308 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
47309 struct hwrm_cfa_ctx_mem_qctx_output {
47310 /* The specific error status for the command. */
47311 uint16_t error_code;
47312 /* The HWRM command request type. */
47314 /* The sequence ID from the original command. */
47316 /* The length of the response data in number of bytes. */
47319 /* Counter PBL indirect levels. */
47320 uint8_t page_level;
47321 /* PBL pointer is physical start address. */
47322 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
47323 /* PBL pointer points to PTE table. */
47324 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
47326 * PBL pointer points to PDE table with each entry pointing to PTE
47329 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
47330 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
47331 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
47334 /* 4KB page size. */
47335 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
47336 /* 8KB page size. */
47337 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
47338 /* 64KB page size. */
47339 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
47340 /* 256KB page size. */
47341 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
47342 /* 1MB page size. */
47343 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
47344 /* 2MB page size. */
47345 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
47346 /* 4MB page size. */
47347 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
47348 /* 1GB page size. */
47349 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
47350 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
47351 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
47352 uint8_t unused_0[4];
47353 /* Pointer to the PBL, or PDL depending on number of levels */
47355 uint8_t unused_1[7];
47357 * This field is used in Output records to indicate that the output
47358 * is completely written to RAM. This field should be read as '1'
47359 * to indicate that the output has been completely written.
47360 * When writing a command completion or response to an internal
47361 * processor, the order of writes has to be such that this field is
47367 /**************************
47368 * hwrm_cfa_ctx_mem_qcaps *
47369 **************************/
47372 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
47373 struct hwrm_cfa_ctx_mem_qcaps_input {
47374 /* The HWRM command request type. */
47377 * The completion ring to send the completion event on. This should
47378 * be the NQ ID returned from the `nq_alloc` HWRM command.
47380 uint16_t cmpl_ring;
47382 * The sequence ID is used by the driver for tracking multiple
47383 * commands. This ID is treated as opaque data by the firmware and
47384 * the value is returned in the `hwrm_resp_hdr` upon completion.
47388 * The target ID of the command:
47389 * * 0x0-0xFFF8 - The function ID
47390 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47391 * * 0xFFFD - Reserved for user-space HWRM interface
47394 uint16_t target_id;
47396 * A physical address pointer pointing to a host buffer that the
47397 * command's response data will be written. This can be either a host
47398 * physical address (HPA) or a guest physical address (GPA) and must
47399 * point to a physically contiguous block of memory.
47401 uint64_t resp_addr;
47404 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
47405 struct hwrm_cfa_ctx_mem_qcaps_output {
47406 /* The specific error status for the command. */
47407 uint16_t error_code;
47408 /* The HWRM command request type. */
47410 /* The sequence ID from the original command. */
47412 /* The length of the response data in number of bytes. */
47415 * Indicates the maximum number of context memory which can be
47418 uint16_t max_entries;
47419 uint8_t unused_0[5];
47421 * This field is used in Output records to indicate that the output
47422 * is completely written to RAM. This field should be read as '1'
47423 * to indicate that the output has been completely written.
47424 * When writing a command completion or response to an internal
47425 * processor, the order of writes has to be such that this field is
47431 /**************************
47432 * hwrm_cfa_counter_qcaps *
47433 **************************/
47436 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
47437 struct hwrm_cfa_counter_qcaps_input {
47438 /* The HWRM command request type. */
47441 * The completion ring to send the completion event on. This should
47442 * be the NQ ID returned from the `nq_alloc` HWRM command.
47444 uint16_t cmpl_ring;
47446 * The sequence ID is used by the driver for tracking multiple
47447 * commands. This ID is treated as opaque data by the firmware and
47448 * the value is returned in the `hwrm_resp_hdr` upon completion.
47452 * The target ID of the command:
47453 * * 0x0-0xFFF8 - The function ID
47454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47455 * * 0xFFFD - Reserved for user-space HWRM interface
47458 uint16_t target_id;
47460 * A physical address pointer pointing to a host buffer that the
47461 * command's response data will be written. This can be either a host
47462 * physical address (HPA) or a guest physical address (GPA) and must
47463 * point to a physically contiguous block of memory.
47465 uint64_t resp_addr;
47468 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
47469 struct hwrm_cfa_counter_qcaps_output {
47470 /* The specific error status for the command. */
47471 uint16_t error_code;
47472 /* The HWRM command request type. */
47474 /* The sequence ID from the original command. */
47476 /* The length of the response data in number of bytes. */
47479 /* Enumeration denoting the supported CFA counter format. */
47480 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
47482 /* CFA counter types are not supported. */
47483 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
47485 /* 64-bit packet counters followed by 64-bit byte counters format. */
47486 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
47488 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
47489 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
47492 * Minimum guaranteed number of flow counters supported for this
47493 * function, in RX direction.
47495 uint32_t min_rx_fc;
47497 * Maximum non-guaranteed number of flow counters supported for this
47498 * function, in RX direction.
47500 uint32_t max_rx_fc;
47502 * Minimum guaranteed number of flow counters supported for this
47503 * function, in TX direction.
47505 uint32_t min_tx_fc;
47507 * Maximum non-guaranteed number of flow counters supported for this
47508 * function, in TX direction.
47510 uint32_t max_tx_fc;
47512 * Minimum guaranteed number of extension flow counters supported for
47513 * this function, in RX direction.
47515 uint32_t min_rx_efc;
47517 * Maximum non-guaranteed number of extension flow counters supported
47518 * for this function, in RX direction.
47520 uint32_t max_rx_efc;
47522 * Minimum guaranteed number of extension flow counters supported for
47523 * this function, in TX direction.
47525 uint32_t min_tx_efc;
47527 * Maximum non-guaranteed number of extension flow counters supported
47528 * for this function, in TX direction.
47530 uint32_t max_tx_efc;
47532 * Minimum guaranteed number of meter drop counters supported for
47533 * this function, in RX direction.
47535 uint32_t min_rx_mdc;
47537 * Maximum non-guaranteed number of meter drop counters supported for
47538 * this function, in RX direction.
47540 uint32_t max_rx_mdc;
47542 * Minimum guaranteed number of meter drop counters supported for this
47543 * function, in TX direction.
47545 uint32_t min_tx_mdc;
47547 * Maximum non-guaranteed number of meter drop counters supported for
47548 * this function, in TX direction.
47550 uint32_t max_tx_mdc;
47552 * Maximum guaranteed number of flow counters which can be used during
47555 uint32_t max_flow_alloc_fc;
47556 uint8_t unused_1[3];
47558 * This field is used in Output records to indicate that the output
47559 * is completely written to RAM. This field should be read as '1'
47560 * to indicate that the output has been completely written.
47561 * When writing a command completion or response to an internal
47562 * processor, the order of writes has to be such that this field is
47568 /************************
47569 * hwrm_cfa_counter_cfg *
47570 ************************/
47573 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
47574 struct hwrm_cfa_counter_cfg_input {
47575 /* The HWRM command request type. */
47578 * The completion ring to send the completion event on. This should
47579 * be the NQ ID returned from the `nq_alloc` HWRM command.
47581 uint16_t cmpl_ring;
47583 * The sequence ID is used by the driver for tracking multiple
47584 * commands. This ID is treated as opaque data by the firmware and
47585 * the value is returned in the `hwrm_resp_hdr` upon completion.
47589 * The target ID of the command:
47590 * * 0x0-0xFFF8 - The function ID
47591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47592 * * 0xFFFD - Reserved for user-space HWRM interface
47595 uint16_t target_id;
47597 * A physical address pointer pointing to a host buffer that the
47598 * command's response data will be written. This can be either a host
47599 * physical address (HPA) or a guest physical address (GPA) and must
47600 * point to a physically contiguous block of memory.
47602 uint64_t resp_addr;
47604 /* Enumeration denoting the configuration mode. */
47605 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
47607 /* Disable the configuration mode. */
47608 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
47610 /* Enable the configuration mode. */
47611 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
47613 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
47614 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
47615 /* Enumeration denoting the RX, TX type of the resource. */
47616 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
47619 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
47620 (UINT32_C(0x0) << 1)
47622 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
47623 (UINT32_C(0x1) << 1)
47624 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
47625 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
47626 /* Enumeration denoting the data transfer mode. */
47627 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
47629 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
47631 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
47632 (UINT32_C(0x0) << 2)
47634 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
47635 (UINT32_C(0x1) << 2)
47636 /* Pull on async update. */
47637 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
47638 (UINT32_C(0x2) << 2)
47639 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
47640 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
47641 uint16_t counter_type;
47642 /* Flow counters. */
47643 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
47644 /* Extended flow counters. */
47645 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
47646 /* Meter drop counters. */
47647 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
47648 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
47649 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
47650 /* Ctx memory handle to be used for the counter. */
47652 /* Counter update cadence hint (only in Push mode). */
47653 uint16_t update_tmr_ms;
47654 /* Total number of entries. */
47655 uint32_t num_entries;
47659 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
47660 struct hwrm_cfa_counter_cfg_output {
47661 /* The specific error status for the command. */
47662 uint16_t error_code;
47663 /* The HWRM command request type. */
47665 /* The sequence ID from the original command. */
47667 /* The length of the response data in number of bytes. */
47669 uint8_t unused_0[7];
47671 * This field is used in Output records to indicate that the output
47672 * is completely written to RAM. This field should be read as '1'
47673 * to indicate that the output has been completely written.
47674 * When writing a command completion or response to an internal
47675 * processor, the order of writes has to be such that this field is
47681 /***************************
47682 * hwrm_cfa_counter_qstats *
47683 ***************************/
47686 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
47687 struct hwrm_cfa_counter_qstats_input {
47688 /* The HWRM command request type. */
47691 * The completion ring to send the completion event on. This should
47692 * be the NQ ID returned from the `nq_alloc` HWRM command.
47694 uint16_t cmpl_ring;
47696 * The sequence ID is used by the driver for tracking multiple
47697 * commands. This ID is treated as opaque data by the firmware and
47698 * the value is returned in the `hwrm_resp_hdr` upon completion.
47702 * The target ID of the command:
47703 * * 0x0-0xFFF8 - The function ID
47704 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47705 * * 0xFFFD - Reserved for user-space HWRM interface
47708 uint16_t target_id;
47710 * A physical address pointer pointing to a host buffer that the
47711 * command's response data will be written. This can be either a host
47712 * physical address (HPA) or a guest physical address (GPA) and must
47713 * point to a physically contiguous block of memory.
47715 uint64_t resp_addr;
47717 /* Enumeration denoting the RX, TX type of the resource. */
47718 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
47720 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47722 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47723 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
47724 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
47725 uint16_t counter_type;
47726 uint16_t input_flow_ctx_id;
47727 uint16_t num_entries;
47728 uint16_t delta_time_ms;
47729 uint16_t meter_instance_id;
47730 uint16_t mdc_ctx_id;
47731 uint8_t unused_0[2];
47732 uint64_t expected_count;
47735 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
47736 struct hwrm_cfa_counter_qstats_output {
47737 /* The specific error status for the command. */
47738 uint16_t error_code;
47739 /* The HWRM command request type. */
47741 /* The sequence ID from the original command. */
47743 /* The length of the response data in number of bytes. */
47745 uint8_t unused_0[7];
47747 * This field is used in Output records to indicate that the output
47748 * is completely written to RAM. This field should be read as '1'
47749 * to indicate that the output has been completely written.
47750 * When writing a command completion or response to an internal
47751 * processor, the order of writes has to be such that this field is
47757 /**********************
47758 * hwrm_cfa_eem_qcaps *
47759 **********************/
47762 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
47763 struct hwrm_cfa_eem_qcaps_input {
47764 /* The HWRM command request type. */
47767 * The completion ring to send the completion event on. This should
47768 * be the NQ ID returned from the `nq_alloc` HWRM command.
47770 uint16_t cmpl_ring;
47772 * The sequence ID is used by the driver for tracking multiple
47773 * commands. This ID is treated as opaque data by the firmware and
47774 * the value is returned in the `hwrm_resp_hdr` upon completion.
47778 * The target ID of the command:
47779 * * 0x0-0xFFF8 - The function ID
47780 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47781 * * 0xFFFD - Reserved for user-space HWRM interface
47784 uint16_t target_id;
47786 * A physical address pointer pointing to a host buffer that the
47787 * command's response data will be written. This can be either a host
47788 * physical address (HPA) or a guest physical address (GPA) and must
47789 * point to a physically contiguous block of memory.
47791 uint64_t resp_addr;
47794 * When set to 1, indicates the configuration will apply to TX flows
47795 * which are to be offloaded.
47796 * Note if this bit is set then the path_rx bit can't be set.
47798 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
47801 * When set to 1, indicates the configuration will apply to RX flows
47802 * which are to be offloaded.
47803 * Note if this bit is set then the path_tx bit can't be set.
47805 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
47807 /* When set to 1, all offloaded flows will be sent to EEM. */
47808 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
47813 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
47814 struct hwrm_cfa_eem_qcaps_output {
47815 /* The specific error status for the command. */
47816 uint16_t error_code;
47817 /* The HWRM command request type. */
47819 /* The sequence ID from the original command. */
47821 /* The length of the response data in number of bytes. */
47825 * When set to 1, indicates the configuration will apply to TX flows
47826 * which are to be offloaded.
47827 * Note if this bit is set then the path_rx bit can't be set.
47829 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
47832 * When set to 1, indicates the configuration will apply to RX flows
47833 * which are to be offloaded.
47834 * Note if this bit is set then the path_tx bit can't be set.
47836 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
47839 * When set to 1, indicates the FW supports the Centralized
47840 * Memory Model. The concept designates one entity for the
47841 * memory allocation while all others ‘subscribe’ to it.
47843 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
47846 * When set to 1, indicates the FW supports the Detached
47847 * Centralized Memory Model. The memory is allocated and managed
47848 * as a separate entity. All PFs and VFs will be granted direct
47849 * or semi-direct access to the allocated memory while none of
47850 * which can interfere with the management of the memory.
47852 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
47855 uint32_t supported;
47857 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
47858 * If set to 0, EEM KEY0 table is not supported.
47860 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
47863 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
47864 * If set to 0, EEM KEY1 table is not supported.
47866 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
47869 * If set to 1, then EEM External Record table is supported.
47870 * If set to 0, EEM External Record table is not supported.
47871 * (This table includes action record, EFC pointers, encap pointers)
47873 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
47876 * If set to 1, then EEM External Flow Counters table is supported.
47877 * If set to 0, EEM External Flow Counters table is not supported.
47879 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
47882 * If set to 1, then FID table used for implicit flow flush is
47884 * If set to 0, then FID table used for implicit flow flush is
47887 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
47890 * The maximum number of entries supported by EEM. When configuring
47891 * the host memory, the number of numbers of entries that can
47893 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
47895 * Any value that are not these values, the FW will round down to the
47896 * closest support number of entries.
47898 uint32_t max_entries_supported;
47899 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
47900 uint16_t key_entry_size;
47901 /* The entry size in bytes of each entry in the EEM RECORD tables. */
47902 uint16_t record_entry_size;
47903 /* The entry size in bytes of each entry in the EEM EFC tables. */
47904 uint16_t efc_entry_size;
47905 /* The FID size in bytes of each entry in the EEM FID tables. */
47906 uint16_t fid_entry_size;
47907 uint8_t unused_1[7];
47909 * This field is used in Output records to indicate that the output
47910 * is completely written to RAM. This field should be read as '1'
47911 * to indicate that the output has been completely written.
47912 * When writing a command completion or response to an internal
47913 * processor, the order of writes has to be such that this field is
47919 /********************
47920 * hwrm_cfa_eem_cfg *
47921 ********************/
47924 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
47925 struct hwrm_cfa_eem_cfg_input {
47926 /* The HWRM command request type. */
47929 * The completion ring to send the completion event on. This should
47930 * be the NQ ID returned from the `nq_alloc` HWRM command.
47932 uint16_t cmpl_ring;
47934 * The sequence ID is used by the driver for tracking multiple
47935 * commands. This ID is treated as opaque data by the firmware and
47936 * the value is returned in the `hwrm_resp_hdr` upon completion.
47940 * The target ID of the command:
47941 * * 0x0-0xFFF8 - The function ID
47942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47943 * * 0xFFFD - Reserved for user-space HWRM interface
47946 uint16_t target_id;
47948 * A physical address pointer pointing to a host buffer that the
47949 * command's response data will be written. This can be either a host
47950 * physical address (HPA) or a guest physical address (GPA) and must
47951 * point to a physically contiguous block of memory.
47953 uint64_t resp_addr;
47956 * When set to 1, indicates the configuration will apply to TX flows
47957 * which are to be offloaded.
47958 * Note if this bit is set then the path_rx bit can't be set.
47960 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
47963 * When set to 1, indicates the configuration will apply to RX flows
47964 * which are to be offloaded.
47965 * Note if this bit is set then the path_tx bit can't be set.
47967 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
47969 /* When set to 1, all offloaded flows will be sent to EEM. */
47970 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
47972 /* When set to 1, secondary, 0 means primary. */
47973 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
47976 * Group_id which used by Firmware to identify memory pools belonging
47977 * to certain group.
47982 * Configured EEM with the given number of entries. All the EEM tables
47983 * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
47984 * tables will be configured using this value. Current minimum value
47985 * is 32k. Current maximum value is 128M.
47987 uint32_t num_entries;
47989 /* Configured EEM with the given context if for KEY0 table. */
47990 uint16_t key0_ctx_id;
47991 /* Configured EEM with the given context if for KEY1 table. */
47992 uint16_t key1_ctx_id;
47993 /* Configured EEM with the given context if for RECORD table. */
47994 uint16_t record_ctx_id;
47995 /* Configured EEM with the given context if for EFC table. */
47996 uint16_t efc_ctx_id;
47997 /* Configured EEM with the given context if for EFC table. */
47998 uint16_t fid_ctx_id;
48003 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
48004 struct hwrm_cfa_eem_cfg_output {
48005 /* The specific error status for the command. */
48006 uint16_t error_code;
48007 /* The HWRM command request type. */
48009 /* The sequence ID from the original command. */
48011 /* The length of the response data in number of bytes. */
48013 uint8_t unused_0[7];
48015 * This field is used in Output records to indicate that the output
48016 * is completely written to RAM. This field should be read as '1'
48017 * to indicate that the output has been completely written.
48018 * When writing a command completion or response to an internal
48019 * processor, the order of writes has to be such that this field is
48025 /*********************
48026 * hwrm_cfa_eem_qcfg *
48027 *********************/
48030 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
48031 struct hwrm_cfa_eem_qcfg_input {
48032 /* The HWRM command request type. */
48035 * The completion ring to send the completion event on. This should
48036 * be the NQ ID returned from the `nq_alloc` HWRM command.
48038 uint16_t cmpl_ring;
48040 * The sequence ID is used by the driver for tracking multiple
48041 * commands. This ID is treated as opaque data by the firmware and
48042 * the value is returned in the `hwrm_resp_hdr` upon completion.
48046 * The target ID of the command:
48047 * * 0x0-0xFFF8 - The function ID
48048 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48049 * * 0xFFFD - Reserved for user-space HWRM interface
48052 uint16_t target_id;
48054 * A physical address pointer pointing to a host buffer that the
48055 * command's response data will be written. This can be either a host
48056 * physical address (HPA) or a guest physical address (GPA) and must
48057 * point to a physically contiguous block of memory.
48059 uint64_t resp_addr;
48061 /* When set to 1, indicates the configuration is the TX flow. */
48062 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
48063 /* When set to 1, indicates the configuration is the RX flow. */
48064 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
48068 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
48069 struct hwrm_cfa_eem_qcfg_output {
48070 /* The specific error status for the command. */
48071 uint16_t error_code;
48072 /* The HWRM command request type. */
48074 /* The sequence ID from the original command. */
48076 /* The length of the response data in number of bytes. */
48079 /* When set to 1, indicates the configuration is the TX flow. */
48080 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
48082 /* When set to 1, indicates the configuration is the RX flow. */
48083 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
48085 /* When set to 1, all offloaded flows will be sent to EEM. */
48086 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
48088 /* The number of entries the FW has configured for EEM. */
48089 uint32_t num_entries;
48090 /* Configured EEM with the given context if for KEY0 table. */
48091 uint16_t key0_ctx_id;
48092 /* Configured EEM with the given context if for KEY1 table. */
48093 uint16_t key1_ctx_id;
48094 /* Configured EEM with the given context if for RECORD table. */
48095 uint16_t record_ctx_id;
48096 /* Configured EEM with the given context if for EFC table. */
48097 uint16_t efc_ctx_id;
48098 /* Configured EEM with the given context if for EFC table. */
48099 uint16_t fid_ctx_id;
48100 uint8_t unused_2[5];
48102 * This field is used in Output records to indicate that the output
48103 * is completely written to RAM. This field should be read as '1'
48104 * to indicate that the output has been completely written.
48105 * When writing a command completion or response to an internal
48106 * processor, the order of writes has to be such that this field is
48112 /*******************
48113 * hwrm_cfa_eem_op *
48114 *******************/
48117 /* hwrm_cfa_eem_op_input (size:192b/24B) */
48118 struct hwrm_cfa_eem_op_input {
48119 /* The HWRM command request type. */
48122 * The completion ring to send the completion event on. This should
48123 * be the NQ ID returned from the `nq_alloc` HWRM command.
48125 uint16_t cmpl_ring;
48127 * The sequence ID is used by the driver for tracking multiple
48128 * commands. This ID is treated as opaque data by the firmware and
48129 * the value is returned in the `hwrm_resp_hdr` upon completion.
48133 * The target ID of the command:
48134 * * 0x0-0xFFF8 - The function ID
48135 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48136 * * 0xFFFD - Reserved for user-space HWRM interface
48139 uint16_t target_id;
48141 * A physical address pointer pointing to a host buffer that the
48142 * command's response data will be written. This can be either a host
48143 * physical address (HPA) or a guest physical address (GPA) and must
48144 * point to a physically contiguous block of memory.
48146 uint64_t resp_addr;
48149 * When set to 1, indicates the host memory which is passed will be
48150 * used for the TX flow offload function specified in fid.
48151 * Note if this bit is set then the path_rx bit can't be set.
48153 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
48155 * When set to 1, indicates the host memory which is passed will be
48156 * used for the RX flow offload function specified in fid.
48157 * Note if this bit is set then the path_tx bit can't be set.
48159 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
48161 /* The number of EEM key table entries to be configured. */
48163 /* This value is reserved and should not be used. */
48164 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
48166 * To properly stop EEM and ensure there are no DMA's, the caller
48167 * must disable EEM for the given PF, using this call. This will
48168 * safely disable EEM and ensure that all DMA'ed to the
48169 * keys/records/efc have been completed.
48171 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
48173 * Once the EEM host memory has been configured, EEM options have
48174 * been configured. Then the caller should enable EEM for the given
48175 * PF. Note once this call has been made, then the EEM mechanism
48176 * will be active and DMA's will occur as packets are processed.
48178 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
48180 * Clear EEM settings for the given PF so that the register values
48181 * are reset back to there initial state.
48183 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
48184 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
48185 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
48188 /* hwrm_cfa_eem_op_output (size:128b/16B) */
48189 struct hwrm_cfa_eem_op_output {
48190 /* The specific error status for the command. */
48191 uint16_t error_code;
48192 /* The HWRM command request type. */
48194 /* The sequence ID from the original command. */
48196 /* The length of the response data in number of bytes. */
48198 uint8_t unused_0[7];
48200 * This field is used in Output records to indicate that the output
48201 * is completely written to RAM. This field should be read as '1'
48202 * to indicate that the output has been completely written.
48203 * When writing a command completion or response to an internal
48204 * processor, the order of writes has to be such that this field is
48210 /********************************
48211 * hwrm_cfa_adv_flow_mgnt_qcaps *
48212 ********************************/
48215 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
48216 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
48217 /* The HWRM command request type. */
48220 * The completion ring to send the completion event on. This should
48221 * be the NQ ID returned from the `nq_alloc` HWRM command.
48223 uint16_t cmpl_ring;
48225 * The sequence ID is used by the driver for tracking multiple
48226 * commands. This ID is treated as opaque data by the firmware and
48227 * the value is returned in the `hwrm_resp_hdr` upon completion.
48231 * The target ID of the command:
48232 * * 0x0-0xFFF8 - The function ID
48233 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48234 * * 0xFFFD - Reserved for user-space HWRM interface
48237 uint16_t target_id;
48239 * A physical address pointer pointing to a host buffer that the
48240 * command's response data will be written. This can be either a host
48241 * physical address (HPA) or a guest physical address (GPA) and must
48242 * point to a physically contiguous block of memory.
48244 uint64_t resp_addr;
48245 uint32_t unused_0[4];
48248 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
48249 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
48250 /* The specific error status for the command. */
48251 uint16_t error_code;
48252 /* The HWRM command request type. */
48254 /* The sequence ID from the original command. */
48256 /* The length of the response data in number of bytes. */
48260 * Value of 1 to indicate firmware support 16-bit flow handle.
48261 * Value of 0 to indicate firmware not support 16-bit flow handle.
48263 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
48266 * Value of 1 to indicate firmware support 64-bit flow handle.
48267 * Value of 0 to indicate firmware not support 64-bit flow handle.
48269 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
48272 * Value of 1 to indicate firmware support flow batch delete
48273 * operation through HWRM_CFA_FLOW_FLUSH command.
48274 * Value of 0 to indicate that the firmware does not support flow
48275 * batch delete operation.
48277 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
48280 * Value of 1 to indicate that the firmware support flow reset all
48281 * operation through HWRM_CFA_FLOW_FLUSH command.
48282 * Value of 0 indicates firmware does not support flow reset all
48285 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
48288 * Value of 1 to indicate that firmware supports use of FID as
48289 * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
48290 * Value of 0 indicates firmware does not support use of FID as
48293 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
48296 * Value of 1 to indicate that firmware supports TX EEM flows.
48297 * Value of 0 indicates firmware does not support TX EEM flows.
48299 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
48302 * Value of 1 to indicate that firmware supports RX EEM flows.
48303 * Value of 0 indicates firmware does not support RX EEM flows.
48305 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
48308 * Value of 1 to indicate that firmware supports the dynamic
48309 * allocation of an on-chip flow counter which can be used for EEM
48310 * flows. Value of 0 indicates firmware does not support the dynamic
48311 * allocation of an on-chip flow counter.
48313 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
48316 * Value of 1 to indicate that firmware supports setting of
48317 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
48318 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
48320 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
48323 * Value of 1 to indicate that firmware supports untagged matching
48324 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
48325 * indicates firmware does not support untagged matching.
48327 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
48330 * Value of 1 to indicate that firmware supports XDP filter. Value
48331 * of 0 indicates firmware does not support XDP filter.
48333 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
48336 * Value of 1 to indicate that the firmware support L2 header source
48337 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
48338 * Value of 0 indicates firmware does not support L2 header source
48341 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
48344 * If set to 1, firmware is capable of supporting ARP ethertype as
48345 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
48346 * RX direction. By default, this flag should be 0 for older version
48349 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
48352 * Value of 1 to indicate that firmware supports setting of
48353 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
48354 * command. Value of 0 indicates firmware does not support
48355 * rfs_ring_tbl_idx in dst_id field.
48357 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
48360 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
48361 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
48362 * direction. By default, this flag should be 0 for older version
48365 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
48368 * When this bit is '1', it indicates that core firmware is
48369 * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
48370 * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
48372 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
48375 * If set to 1, firmware is capable of supporting L2/ROCE as
48376 * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
48377 * By default, this flag should be 0 for older version of firmware.
48379 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
48382 * If set to 1, firmware is capable of HW LAG. This bit is only
48383 * advertised if the calling function is a PAXC function.
48385 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \
48388 * If set to 1, firmware is capable installing ntuple rules without
48389 * additional classification on the L2 Context.
48391 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \
48393 uint8_t unused_0[3];
48395 * This field is used in Output records to indicate that the output
48396 * is completely written to RAM. This field should be read as '1'
48397 * to indicate that the output has been completely written.
48398 * When writing a command completion or response to an internal
48399 * processor, the order of writes has to be such that this field is
48405 /******************
48407 ******************/
48410 /* hwrm_cfa_tflib_input (size:1024b/128B) */
48411 struct hwrm_cfa_tflib_input {
48412 /* The HWRM command request type. */
48415 * The completion ring to send the completion event on. This should
48416 * be the NQ ID returned from the `nq_alloc` HWRM command.
48418 uint16_t cmpl_ring;
48420 * The sequence ID is used by the driver for tracking multiple
48421 * commands. This ID is treated as opaque data by the firmware and
48422 * the value is returned in the `hwrm_resp_hdr` upon completion.
48426 * The target ID of the command:
48427 * * 0x0-0xFFF8 - The function ID
48428 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48429 * * 0xFFFD - Reserved for user-space HWRM interface
48432 uint16_t target_id;
48434 * A physical address pointer pointing to a host buffer that the
48435 * command's response data will be written. This can be either a host
48436 * physical address (HPA) or a guest physical address (GPA) and must
48437 * point to a physically contiguous block of memory.
48439 uint64_t resp_addr;
48440 /* TFLIB message type. */
48442 /* TFLIB message subtype. */
48443 uint16_t tf_subtype;
48445 uint8_t unused0[4];
48446 /* TFLIB request data. */
48447 uint32_t tf_req[26];
48450 /* hwrm_cfa_tflib_output (size:5632b/704B) */
48451 struct hwrm_cfa_tflib_output {
48452 /* The specific error status for the command. */
48453 uint16_t error_code;
48454 /* The HWRM command request type. */
48456 /* The sequence ID from the original command. */
48458 /* The length of the response data in number of bytes. */
48460 /* TFLIB message type. */
48462 /* TFLIB message subtype. */
48463 uint16_t tf_subtype;
48464 /* TFLIB response code */
48465 uint32_t tf_resp_code;
48466 /* TFLIB response data. */
48467 uint32_t tf_resp[170];
48469 uint8_t unused1[7];
48471 * This field is used in Output records to indicate that the output
48472 * is completely written to RAM. This field should be read as '1'
48473 * to indicate that the output has been completely written.
48474 * When writing a command completion or response to an internal
48475 * processor, the order of writes has to be such that this field is
48481 /**********************************
48482 * hwrm_cfa_lag_group_member_rgtr *
48483 **********************************/
48486 /* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */
48487 struct hwrm_cfa_lag_group_member_rgtr_input {
48488 /* The HWRM command request type. */
48491 * The completion ring to send the completion event on. This should
48492 * be the NQ ID returned from the `nq_alloc` HWRM command.
48494 uint16_t cmpl_ring;
48496 * The sequence ID is used by the driver for tracking multiple
48497 * commands. This ID is treated as opaque data by the firmware and
48498 * the value is returned in the `hwrm_resp_hdr` upon completion.
48502 * The target ID of the command:
48503 * * 0x0-0xFFF8 - The function ID
48504 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48505 * * 0xFFFD - Reserved for user-space HWRM interface
48508 uint16_t target_id;
48510 * A physical address pointer pointing to a host buffer that the
48511 * command's response data will be written. This can be either a host
48512 * physical address (HPA) or a guest physical address (GPA) and must
48513 * point to a physically contiguous block of memory.
48515 uint64_t resp_addr;
48518 * Transmit only on the active port. Automatically failover
48521 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \
48524 * Transmit based on packet header ntuple hash. Packet with only
48525 * layer 2 headers will hash using the destination MAC, source MAC
48526 * and Ethertype fields. Packets with layer 3 (IP) headers will
48527 * hash using the destination MAC, source MAC, IP protocol/next
48528 * header, source IP address and destination IP address. Packets
48529 * with layer 4 (TCP/UDP) headers will hash using the destination
48530 * MAC, source MAC, IP protocol/next header, source IP address,
48531 * destination IP address, source port and destination port fields.
48533 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \
48535 /* Transmit packets on all specified ports. */
48536 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \
48538 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \
48539 HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST
48541 * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
48542 * bit2 = port 2, bit3 = port 4, bit4 = loopback port
48544 uint8_t port_bitmap;
48545 /* Specify the active port when active-backup mode is specified */
48546 uint8_t active_port;
48547 uint8_t unused_0[5];
48550 /* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */
48551 struct hwrm_cfa_lag_group_member_rgtr_output {
48552 /* The specific error status for the command. */
48553 uint16_t error_code;
48554 /* The HWRM command request type. */
48556 /* The sequence ID from the original command. */
48558 /* The length of the response data in number of bytes. */
48560 /* lag group ID configured for the function */
48562 uint8_t unused_0[5];
48564 * This field is used in Output records to indicate that the output
48565 * is completely written to RAM. This field should be read as '1'
48566 * to indicate that the output has been completely written.
48567 * When writing a command completion or response to an internal
48568 * processor, the order of writes has to be such that this field is
48574 /************************************
48575 * hwrm_cfa_lag_group_member_unrgtr *
48576 ************************************/
48579 /* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */
48580 struct hwrm_cfa_lag_group_member_unrgtr_input {
48581 /* The HWRM command request type. */
48584 * The completion ring to send the completion event on. This should
48585 * be the NQ ID returned from the `nq_alloc` HWRM command.
48587 uint16_t cmpl_ring;
48589 * The sequence ID is used by the driver for tracking multiple
48590 * commands. This ID is treated as opaque data by the firmware and
48591 * the value is returned in the `hwrm_resp_hdr` upon completion.
48595 * The target ID of the command:
48596 * * 0x0-0xFFF8 - The function ID
48597 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48598 * * 0xFFFD - Reserved for user-space HWRM interface
48601 uint16_t target_id;
48603 * A physical address pointer pointing to a host buffer that the
48604 * command's response data will be written. This can be either a host
48605 * physical address (HPA) or a guest physical address (GPA) and must
48606 * point to a physically contiguous block of memory.
48608 uint64_t resp_addr;
48609 /* lag group ID configured for the function */
48611 uint8_t unused_0[6];
48614 /* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */
48615 struct hwrm_cfa_lag_group_member_unrgtr_output {
48616 /* The specific error status for the command. */
48617 uint16_t error_code;
48618 /* The HWRM command request type. */
48620 /* The sequence ID from the original command. */
48622 /* The length of the response data in number of bytes. */
48624 uint8_t unused_0[7];
48626 * This field is used in Output records to indicate that the output
48627 * is completely written to RAM. This field should be read as '1'
48628 * to indicate that the output has been completely written.
48629 * When writing a command completion or response to an internal
48630 * processor, the order of writes has to be such that this field is
48636 /*****************************
48637 * hwrm_cfa_tls_filter_alloc *
48638 *****************************/
48641 /* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */
48642 struct hwrm_cfa_tls_filter_alloc_input {
48643 /* The HWRM command request type. */
48646 * The completion ring to send the completion event on. This should
48647 * be the NQ ID returned from the `nq_alloc` HWRM command.
48649 uint16_t cmpl_ring;
48651 * The sequence ID is used by the driver for tracking multiple
48652 * commands. This ID is treated as opaque data by the firmware and
48653 * the value is returned in the `hwrm_resp_hdr` upon completion.
48657 * The target ID of the command:
48658 * * 0x0-0xFFF8 - The function ID
48659 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48660 * * 0xFFFD - Reserved for user-space HWRM interface
48663 uint16_t target_id;
48665 * A physical address pointer pointing to a host buffer that the
48666 * command's response data will be written. This can be either a host
48667 * physical address (HPA) or a guest physical address (GPA) and must
48668 * point to a physically contiguous block of memory.
48670 uint64_t resp_addr;
48674 * This bit must be '1' for the l2_filter_id field to be
48677 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
48680 * This bit must be '1' for the ethertype field to be
48683 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
48686 * This bit must be '1' for the ipaddr_type field to be
48689 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
48692 * This bit must be '1' for the src_ipaddr field to be
48695 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
48698 * This bit must be '1' for the dst_ipaddr field to be
48701 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
48704 * This bit must be '1' for the ip_protocol field to be
48707 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
48710 * This bit must be '1' for the src_port field to be
48713 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
48716 * This bit must be '1' for the dst_port field to be
48719 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
48722 * This bit must be '1' for the kid field to be
48725 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID \
48728 * This bit must be '1' for the dst_id field to be
48731 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
48734 * This bit must be '1' for the mirror_vnic_id field to be
48737 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
48740 * This value identifies a set of CFA data structures used for an L2
48743 uint64_t l2_filter_id;
48744 uint8_t unused_1[6];
48745 /* This value indicates the ethertype in the Ethernet header. */
48746 uint16_t ethertype;
48748 * This value indicates the type of IP address.
48751 * All others are invalid.
48753 uint8_t ip_addr_type;
48755 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
48758 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
48761 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
48763 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
48764 HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
48766 * The value of protocol filed in IP header.
48767 * Applies to UDP and TCP traffic.
48771 uint8_t ip_protocol;
48773 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
48776 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
48779 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
48781 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
48782 HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
48784 * If set, this value shall represent the
48785 * Logical VNIC ID of the destination VNIC for the RX
48786 * path and network port id of the destination port for
48791 * Logical VNIC ID of the VNIC where traffic is
48794 uint16_t mirror_vnic_id;
48795 uint8_t unused_2[2];
48797 * The value of source IP address to be used in filtering.
48798 * For IPv4, first four bytes represent the IP address.
48800 uint32_t src_ipaddr[4];
48802 * The value of destination IP address to be used in filtering.
48803 * For IPv4, first four bytes represent the IP address.
48805 uint32_t dst_ipaddr[4];
48807 * The value of source port to be used in filtering.
48808 * Applies to UDP and TCP traffic.
48812 * The value of destination port to be used in filtering.
48813 * Applies to UDP and TCP traffic.
48817 * The Key Context Identifier (KID) for use with KTLS.
48818 * KID is limited to 20-bits.
48823 /* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */
48824 struct hwrm_cfa_tls_filter_alloc_output {
48825 /* The specific error status for the command. */
48826 uint16_t error_code;
48827 /* The HWRM command request type. */
48829 /* The sequence ID from the original command. */
48831 /* The length of the response data in number of bytes. */
48833 /* This value is an opaque id into CFA data structures. */
48834 uint64_t tls_filter_id;
48836 * The flow id value in bit 0-29 is the actual ID of the flow
48837 * associated with this filter and it shall be used to match
48838 * and associate the flow identifier returned in completion
48839 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
48840 * shall indicate no valid flow id.
48843 /* Indicate the flow id value. */
48844 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
48845 UINT32_C(0x3fffffff)
48846 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
48847 /* Indicate type of the flow. */
48848 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
48849 UINT32_C(0x40000000)
48851 * If this bit set to 0, then it indicates that the flow is
48854 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
48855 (UINT32_C(0x0) << 30)
48857 * If this bit is set to 1, then it indicates that the flow is
48860 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
48861 (UINT32_C(0x1) << 30)
48862 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
48863 HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
48864 /* Indicate the flow direction. */
48865 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
48866 UINT32_C(0x80000000)
48867 /* If this bit set to 0, then it indicates rx flow. */
48868 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
48869 (UINT32_C(0x0) << 31)
48870 /* If this bit is set to 1, then it indicates that tx flow. */
48871 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
48872 (UINT32_C(0x1) << 31)
48873 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
48874 HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
48875 uint8_t unused_0[3];
48877 * This field is used in Output records to indicate that the output
48878 * is completely written to RAM. This field should be read as '1'
48879 * to indicate that the output has been completely written.
48880 * When writing a command completion or response to an internal
48881 * processor, the order of writes has to be such that this field is
48887 /****************************
48888 * hwrm_cfa_tls_filter_free *
48889 ****************************/
48892 /* hwrm_cfa_tls_filter_free_input (size:192b/24B) */
48893 struct hwrm_cfa_tls_filter_free_input {
48894 /* The HWRM command request type. */
48897 * The completion ring to send the completion event on. This should
48898 * be the NQ ID returned from the `nq_alloc` HWRM command.
48900 uint16_t cmpl_ring;
48902 * The sequence ID is used by the driver for tracking multiple
48903 * commands. This ID is treated as opaque data by the firmware and
48904 * the value is returned in the `hwrm_resp_hdr` upon completion.
48908 * The target ID of the command:
48909 * * 0x0-0xFFF8 - The function ID
48910 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48911 * * 0xFFFD - Reserved for user-space HWRM interface
48914 uint16_t target_id;
48916 * A physical address pointer pointing to a host buffer that the
48917 * command's response data will be written. This can be either a host
48918 * physical address (HPA) or a guest physical address (GPA) and must
48919 * point to a physically contiguous block of memory.
48921 uint64_t resp_addr;
48922 /* This value is an opaque id into CFA data structures. */
48923 uint64_t tls_filter_id;
48926 /* hwrm_cfa_tls_filter_free_output (size:128b/16B) */
48927 struct hwrm_cfa_tls_filter_free_output {
48928 /* The specific error status for the command. */
48929 uint16_t error_code;
48930 /* The HWRM command request type. */
48932 /* The sequence ID from the original command. */
48934 /* The length of the response data in number of bytes. */
48936 uint8_t unused_0[7];
48938 * This field is used in Output records to indicate that the output
48939 * is completely written to RAM. This field should be read as '1'
48940 * to indicate that the output has been completely written.
48941 * When writing a command completion or response to an internal
48942 * processor, the order of writes has to be such that this field is
48953 /* hwrm_tf_input (size:1024b/128B) */
48954 struct hwrm_tf_input {
48955 /* The HWRM command request type. */
48958 * The completion ring to send the completion event on. This should
48959 * be the NQ ID returned from the `nq_alloc` HWRM command.
48961 uint16_t cmpl_ring;
48963 * The sequence ID is used by the driver for tracking multiple
48964 * commands. This ID is treated as opaque data by the firmware and
48965 * the value is returned in the `hwrm_resp_hdr` upon completion.
48969 * The target ID of the command:
48970 * * 0x0-0xFFF8 - The function ID
48971 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48972 * * 0xFFFD - Reserved for user-space HWRM interface
48975 uint16_t target_id;
48977 * A physical address pointer pointing to a host buffer that the
48978 * command's response data will be written. This can be either a host
48979 * physical address (HPA) or a guest physical address (GPA) and must
48980 * point to a physically contiguous block of memory.
48982 uint64_t resp_addr;
48983 /* TF message type. */
48985 /* TF message subtype. */
48988 uint8_t unused0[4];
48989 /* TF request data. */
48993 /* hwrm_tf_output (size:5632b/704B) */
48994 struct hwrm_tf_output {
48995 /* The specific error status for the command. */
48996 uint16_t error_code;
48997 /* The HWRM command request type. */
48999 /* The sequence ID from the original command. */
49001 /* The length of the response data in number of bytes. */
49003 /* TF message type. */
49005 /* TF message subtype. */
49007 /* TF response code */
49008 uint32_t resp_code;
49009 /* TF response data. */
49010 uint32_t resp[170];
49012 uint8_t unused1[7];
49014 * This field is used in Output records to indicate that the
49015 * output is completely written to RAM. This field should be
49016 * read as '1' to indicate that the output has been
49017 * completely written. When writing a command completion or
49018 * response to an internal processor, the order of writes has
49019 * to be such that this field is written last.
49024 /***********************
49025 * hwrm_tf_version_get *
49026 ***********************/
49029 /* hwrm_tf_version_get_input (size:128b/16B) */
49030 struct hwrm_tf_version_get_input {
49031 /* The HWRM command request type. */
49034 * The completion ring to send the completion event on. This should
49035 * be the NQ ID returned from the `nq_alloc` HWRM command.
49037 uint16_t cmpl_ring;
49039 * The sequence ID is used by the driver for tracking multiple
49040 * commands. This ID is treated as opaque data by the firmware and
49041 * the value is returned in the `hwrm_resp_hdr` upon completion.
49045 * The target ID of the command:
49046 * * 0x0-0xFFF8 - The function ID
49047 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49048 * * 0xFFFD - Reserved for user-space HWRM interface
49051 uint16_t target_id;
49053 * A physical address pointer pointing to a host buffer that the
49054 * command's response data will be written. This can be either a host
49055 * physical address (HPA) or a guest physical address (GPA) and must
49056 * point to a physically contiguous block of memory.
49058 uint64_t resp_addr;
49061 /* hwrm_tf_version_get_output (size:256b/32B) */
49062 struct hwrm_tf_version_get_output {
49063 /* The specific error status for the command. */
49064 uint16_t error_code;
49065 /* The HWRM command request type. */
49067 /* The sequence ID from the original command. */
49069 /* The length of the response data in number of bytes. */
49071 /* Version Major number. */
49073 /* Version Minor number. */
49075 /* Version Update number. */
49078 uint8_t unused0[5];
49080 * This field is used to indicate device's capabilities and
49083 uint64_t dev_caps_cfg;
49085 uint8_t unused1[7];
49087 * This field is used in Output records to indicate that the output
49088 * is completely written to RAM. This field should be read as '1'
49089 * to indicate that the output has been completely written.
49090 * When writing a command completion or response to an internal
49091 * processor, the order of writes has to be such that this field is
49097 /************************
49098 * hwrm_tf_session_open *
49099 ************************/
49102 /* hwrm_tf_session_open_input (size:640b/80B) */
49103 struct hwrm_tf_session_open_input {
49104 /* The HWRM command request type. */
49107 * The completion ring to send the completion event on. This should
49108 * be the NQ ID returned from the `nq_alloc` HWRM command.
49110 uint16_t cmpl_ring;
49112 * The sequence ID is used by the driver for tracking multiple
49113 * commands. This ID is treated as opaque data by the firmware and
49114 * the value is returned in the `hwrm_resp_hdr` upon completion.
49118 * The target ID of the command:
49119 * * 0x0-0xFFF8 - The function ID
49120 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49121 * * 0xFFFD - Reserved for user-space HWRM interface
49124 uint16_t target_id;
49126 * A physical address pointer pointing to a host buffer that the
49127 * command's response data will be written. This can be either a host
49128 * physical address (HPA) or a guest physical address (GPA) and must
49129 * point to a physically contiguous block of memory.
49131 uint64_t resp_addr;
49132 /* Name of the session. */
49133 uint8_t session_name[64];
49136 /* hwrm_tf_session_open_output (size:192b/24B) */
49137 struct hwrm_tf_session_open_output {
49138 /* The specific error status for the command. */
49139 uint16_t error_code;
49140 /* The HWRM command request type. */
49142 /* The sequence ID from the original command. */
49144 /* The length of the response data in number of bytes. */
49147 * Unique session identifier for the session created by the
49150 uint32_t fw_session_id;
49152 * Unique session client identifier for the first client on
49153 * the newly created session.
49155 uint32_t fw_session_client_id;
49156 /* This field is used to return the status of fw session to host. */
49159 * Indicates if the shared session has been created. Shared session
49160 * should be the first session created ever. Its fw_rm_client_id
49161 * should be 1. The AFM session's fw_rm_client_id is 0.
49163 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
49166 * If this bit set to 0, then it indicates the shared session
49167 * has been created by another session.
49169 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \
49172 * If this bit is set to 1, then it indicates the shared session
49173 * is created by this session.
49175 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \
49177 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \
49178 HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR
49180 uint8_t unused1[3];
49182 * This field is used in Output records to indicate that the output
49183 * is completely written to RAM. This field should be read as '1'
49184 * to indicate that the output has been completely written.
49185 * When writing a command completion or response to an internal
49186 * processor, the order of writes has to be such that this field is
49192 /**************************
49193 * hwrm_tf_session_attach *
49194 **************************/
49197 /* hwrm_tf_session_attach_input (size:704b/88B) */
49198 struct hwrm_tf_session_attach_input {
49199 /* The HWRM command request type. */
49202 * The completion ring to send the completion event on. This should
49203 * be the NQ ID returned from the `nq_alloc` HWRM command.
49205 uint16_t cmpl_ring;
49207 * The sequence ID is used by the driver for tracking multiple
49208 * commands. This ID is treated as opaque data by the firmware and
49209 * the value is returned in the `hwrm_resp_hdr` upon completion.
49213 * The target ID of the command:
49214 * * 0x0-0xFFF8 - The function ID
49215 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49216 * * 0xFFFD - Reserved for user-space HWRM interface
49219 uint16_t target_id;
49221 * A physical address pointer pointing to a host buffer that the
49222 * command's response data will be written. This can be either a host
49223 * physical address (HPA) or a guest physical address (GPA) and must
49224 * point to a physically contiguous block of memory.
49226 uint64_t resp_addr;
49228 * Unique session identifier for the session that the attach
49229 * request want to attach to. This value originates from the
49230 * shared session memory that the attach request opened by
49231 * way of the 'attach name' that was passed in to the core
49233 * The fw_session_id of the attach session includes PCIe bus
49234 * info to distinguish the PF and session info to identify
49235 * the associated TruFlow session.
49237 uint32_t attach_fw_session_id;
49240 /* Name of the session it self. */
49241 uint8_t session_name[64];
49244 /* hwrm_tf_session_attach_output (size:128b/16B) */
49245 struct hwrm_tf_session_attach_output {
49246 /* The specific error status for the command. */
49247 uint16_t error_code;
49248 /* The HWRM command request type. */
49250 /* The sequence ID from the original command. */
49252 /* The length of the response data in number of bytes. */
49255 * Unique session identifier for the session created by the
49256 * firmware. It includes PCIe bus info to distinguish the PF
49257 * and session info to identify the associated TruFlow
49258 * session. This fw_session_id is unique to the attach
49261 uint32_t fw_session_id;
49263 uint8_t unused0[3];
49265 * This field is used in Output records to indicate that the output
49266 * is completely written to RAM. This field should be read as '1'
49267 * to indicate that the output has been completely written.
49268 * When writing a command completion or response to an internal
49269 * processor, the order of writes has to be such that this field is
49275 /****************************
49276 * hwrm_tf_session_register *
49277 ****************************/
49280 /* hwrm_tf_session_register_input (size:704b/88B) */
49281 struct hwrm_tf_session_register_input {
49282 /* The HWRM command request type. */
49285 * The completion ring to send the completion event on. This should
49286 * be the NQ ID returned from the `nq_alloc` HWRM command.
49288 uint16_t cmpl_ring;
49290 * The sequence ID is used by the driver for tracking multiple
49291 * commands. This ID is treated as opaque data by the firmware and
49292 * the value is returned in the `hwrm_resp_hdr` upon completion.
49296 * The target ID of the command:
49297 * * 0x0-0xFFF8 - The function ID
49298 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49299 * * 0xFFFD - Reserved for user-space HWRM interface
49302 uint16_t target_id;
49304 * A physical address pointer pointing to a host buffer that the
49305 * command's response data will be written. This can be either a host
49306 * physical address (HPA) or a guest physical address (GPA) and must
49307 * point to a physically contiguous block of memory.
49309 uint64_t resp_addr;
49311 * Unique session identifier for the session that the
49312 * register request want to create a new client on. This
49313 * value originates from the first open request.
49314 * The fw_session_id of the attach session includes PCIe bus
49315 * info to distinguish the PF and session info to identify
49316 * the associated TruFlow session.
49318 uint32_t fw_session_id;
49321 /* Name of the session client. */
49322 uint8_t session_client_name[64];
49325 /* hwrm_tf_session_register_output (size:128b/16B) */
49326 struct hwrm_tf_session_register_output {
49327 /* The specific error status for the command. */
49328 uint16_t error_code;
49329 /* The HWRM command request type. */
49331 /* The sequence ID from the original command. */
49333 /* The length of the response data in number of bytes. */
49336 * Unique session client identifier for the session created
49337 * by the firmware. It includes the session the client it
49338 * attached to and session client info.
49340 uint32_t fw_session_client_id;
49342 uint8_t unused0[3];
49344 * This field is used in Output records to indicate that the output
49345 * is completely written to RAM. This field should be read as '1'
49346 * to indicate that the output has been completely written.
49347 * When writing a command completion or response to an internal
49348 * processor, the order of writes has to be such that this field is
49354 /******************************
49355 * hwrm_tf_session_unregister *
49356 ******************************/
49359 /* hwrm_tf_session_unregister_input (size:192b/24B) */
49360 struct hwrm_tf_session_unregister_input {
49361 /* The HWRM command request type. */
49364 * The completion ring to send the completion event on. This should
49365 * be the NQ ID returned from the `nq_alloc` HWRM command.
49367 uint16_t cmpl_ring;
49369 * The sequence ID is used by the driver for tracking multiple
49370 * commands. This ID is treated as opaque data by the firmware and
49371 * the value is returned in the `hwrm_resp_hdr` upon completion.
49375 * The target ID of the command:
49376 * * 0x0-0xFFF8 - The function ID
49377 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49378 * * 0xFFFD - Reserved for user-space HWRM interface
49381 uint16_t target_id;
49383 * A physical address pointer pointing to a host buffer that the
49384 * command's response data will be written. This can be either a host
49385 * physical address (HPA) or a guest physical address (GPA) and must
49386 * point to a physically contiguous block of memory.
49388 uint64_t resp_addr;
49390 * Unique session identifier for the session that the
49391 * unregister request want to close a session client on.
49393 uint32_t fw_session_id;
49395 * Unique session client identifier for the session that the
49396 * unregister request want to close.
49398 uint32_t fw_session_client_id;
49401 /* hwrm_tf_session_unregister_output (size:128b/16B) */
49402 struct hwrm_tf_session_unregister_output {
49403 /* The specific error status for the command. */
49404 uint16_t error_code;
49405 /* The HWRM command request type. */
49407 /* The sequence ID from the original command. */
49409 /* The length of the response data in number of bytes. */
49412 uint8_t unused0[7];
49414 * This field is used in Output records to indicate that the output
49415 * is completely written to RAM. This field should be read as '1'
49416 * to indicate that the output has been completely written.
49417 * When writing a command completion or response to an internal
49418 * processor, the order of writes has to be such that this field is
49424 /*************************
49425 * hwrm_tf_session_close *
49426 *************************/
49429 /* hwrm_tf_session_close_input (size:192b/24B) */
49430 struct hwrm_tf_session_close_input {
49431 /* The HWRM command request type. */
49434 * The completion ring to send the completion event on. This should
49435 * be the NQ ID returned from the `nq_alloc` HWRM command.
49437 uint16_t cmpl_ring;
49439 * The sequence ID is used by the driver for tracking multiple
49440 * commands. This ID is treated as opaque data by the firmware and
49441 * the value is returned in the `hwrm_resp_hdr` upon completion.
49445 * The target ID of the command:
49446 * * 0x0-0xFFF8 - The function ID
49447 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49448 * * 0xFFFD - Reserved for user-space HWRM interface
49451 uint16_t target_id;
49453 * A physical address pointer pointing to a host buffer that the
49454 * command's response data will be written. This can be either a host
49455 * physical address (HPA) or a guest physical address (GPA) and must
49456 * point to a physically contiguous block of memory.
49458 uint64_t resp_addr;
49459 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49460 uint32_t fw_session_id;
49462 uint8_t unused0[4];
49465 /* hwrm_tf_session_close_output (size:128b/16B) */
49466 struct hwrm_tf_session_close_output {
49467 /* The specific error status for the command. */
49468 uint16_t error_code;
49469 /* The HWRM command request type. */
49471 /* The sequence ID from the original command. */
49473 /* The length of the response data in number of bytes. */
49476 uint8_t unused0[7];
49478 * This field is used in Output records to indicate that the output
49479 * is completely written to RAM. This field should be read as '1'
49480 * to indicate that the output has been completely written.
49481 * When writing a command completion or response to an internal
49482 * processor, the order of writes has to be such that this field
49488 /************************
49489 * hwrm_tf_session_qcfg *
49490 ************************/
49493 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
49494 struct hwrm_tf_session_qcfg_input {
49495 /* The HWRM command request type. */
49498 * The completion ring to send the completion event on. This should
49499 * be the NQ ID returned from the `nq_alloc` HWRM command.
49501 uint16_t cmpl_ring;
49503 * The sequence ID is used by the driver for tracking multiple
49504 * commands. This ID is treated as opaque data by the firmware and
49505 * the value is returned in the `hwrm_resp_hdr` upon completion.
49509 * The target ID of the command:
49510 * * 0x0-0xFFF8 - The function ID
49511 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49512 * * 0xFFFD - Reserved for user-space HWRM interface
49515 uint16_t target_id;
49517 * A physical address pointer pointing to a host buffer that the
49518 * command's response data will be written. This can be either a host
49519 * physical address (HPA) or a guest physical address (GPA) and must
49520 * point to a physically contiguous block of memory.
49522 uint64_t resp_addr;
49523 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49524 uint32_t fw_session_id;
49526 uint8_t unused0[4];
49529 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
49530 struct hwrm_tf_session_qcfg_output {
49531 /* The specific error status for the command. */
49532 uint16_t error_code;
49533 /* The HWRM command request type. */
49535 /* The sequence ID from the original command. */
49537 /* The length of the response data in number of bytes. */
49539 /* RX action control settings flags. */
49540 uint8_t rx_act_flags;
49542 * A value of 1 in this field indicates that Global Flow ID
49543 * reporting into cfa_code and cfa_metadata is enabled.
49545 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
49548 * A value of 1 in this field indicates that both inner and outer
49549 * are stripped and inner tag is passed.
49552 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
49555 * A value of 1 in this field indicates that the re-use of
49556 * existing tunnel L2 header SMAC is enabled for
49557 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
49559 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
49561 /* TX Action control settings flags. */
49562 uint8_t tx_act_flags;
49564 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
49567 * When set to 1 any GRE tunnels will include the
49568 * optional Key field.
49570 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
49573 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
49574 * field of the outer header is inherited from the inner header
49575 * (if present) or the fixed value as taken from the encap
49578 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
49581 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
49582 * field of the outer header is inherited from the inner header
49583 * (if present) or the fixed value as taken from the encap record.
49585 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
49588 uint8_t unused0[5];
49590 * This field is used in Output records to indicate that the output
49591 * is completely written to RAM. This field should be read as '1'
49592 * to indicate that the output has been completely written.
49593 * When writing a command completion or response to an internal
49594 * processor, the order of writes has to be such that this field
49600 /******************************
49601 * hwrm_tf_session_resc_qcaps *
49602 ******************************/
49605 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
49606 struct hwrm_tf_session_resc_qcaps_input {
49607 /* The HWRM command request type. */
49610 * The completion ring to send the completion event on. This should
49611 * be the NQ ID returned from the `nq_alloc` HWRM command.
49613 uint16_t cmpl_ring;
49615 * The sequence ID is used by the driver for tracking multiple
49616 * commands. This ID is treated as opaque data by the firmware and
49617 * the value is returned in the `hwrm_resp_hdr` upon completion.
49621 * The target ID of the command:
49622 * * 0x0-0xFFF8 - The function ID
49623 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49624 * * 0xFFFD - Reserved for user-space HWRM interface
49627 uint16_t target_id;
49629 * A physical address pointer pointing to a host buffer that the
49630 * command's response data will be written. This can be either a host
49631 * physical address (HPA) or a guest physical address (GPA) and must
49632 * point to a physically contiguous block of memory.
49634 uint64_t resp_addr;
49635 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49636 uint32_t fw_session_id;
49637 /* Control flags. */
49639 /* Indicates the flow direction. */
49640 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
49641 /* If this bit set to 0, then it indicates rx flow. */
49642 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49643 /* If this bit is set to 1, then it indicates tx flow. */
49644 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49645 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
49646 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
49648 * Defines the size of the provided qcaps_addr array
49649 * buffer. The size should be set to the Resource Manager
49650 * provided max number of qcaps entries which is device
49651 * specific. Resource Manager gets the max size from HCAPI
49654 uint16_t qcaps_size;
49656 * This is the DMA address for the qcaps output data array
49657 * buffer. Array is of tf_rm_resc_req_entry type and is
49660 uint64_t qcaps_addr;
49663 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
49664 struct hwrm_tf_session_resc_qcaps_output {
49665 /* The specific error status for the command. */
49666 uint16_t error_code;
49667 /* The HWRM command request type. */
49669 /* The sequence ID from the original command. */
49671 /* The length of the response data in number of bytes. */
49673 /* Control flags. */
49675 /* Session reservation strategy. */
49676 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
49678 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
49680 /* Static partitioning. */
49681 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
49684 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
49687 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
49690 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
49692 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
49693 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
49695 * Size of the returned qcaps_addr data array buffer. The
49696 * value cannot exceed the size defined by the input msg,
49701 * SRAM profile number that sets the partition of SRAM memory
49702 * between TF and AFM within the 4 internal memory banks (Thor).
49704 uint8_t sram_profile;
49708 uint8_t unused1[7];
49710 * This field is used in Output records to indicate that the output
49711 * is completely written to RAM. This field should be read as '1'
49712 * to indicate that the output has been completely written.
49713 * When writing a command completion or response to an internal
49714 * processor, the order of writes has to be such that this field is
49720 /******************************
49721 * hwrm_tf_session_resc_alloc *
49722 ******************************/
49725 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
49726 struct hwrm_tf_session_resc_alloc_input {
49727 /* The HWRM command request type. */
49730 * The completion ring to send the completion event on. This should
49731 * be the NQ ID returned from the `nq_alloc` HWRM command.
49733 uint16_t cmpl_ring;
49735 * The sequence ID is used by the driver for tracking multiple
49736 * commands. This ID is treated as opaque data by the firmware and
49737 * the value is returned in the `hwrm_resp_hdr` upon completion.
49741 * The target ID of the command:
49742 * * 0x0-0xFFF8 - The function ID
49743 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49744 * * 0xFFFD - Reserved for user-space HWRM interface
49747 uint16_t target_id;
49749 * A physical address pointer pointing to a host buffer that the
49750 * command's response data will be written. This can be either a host
49751 * physical address (HPA) or a guest physical address (GPA) and must
49752 * point to a physically contiguous block of memory.
49754 uint64_t resp_addr;
49755 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49756 uint32_t fw_session_id;
49757 /* Control flags. */
49759 /* Indicates the flow direction. */
49760 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
49761 /* If this bit set to 0, then it indicates rx flow. */
49762 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49763 /* If this bit is set to 1, then it indicates tx flow. */
49764 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49765 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
49766 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
49768 * Defines the array size of the provided req_addr and
49769 * resv_addr array buffers. Should be set to the number of
49774 * This is the DMA address for the request input data array
49775 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
49776 * array buffer is provided by the 'req_size' field in this
49781 * This is the DMA address for the resc output data array
49782 * buffer. Array is of tf_rm_resc_entry type. Size of the array
49783 * buffer is provided by the 'req_size' field in this
49786 uint64_t resc_addr;
49789 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
49790 struct hwrm_tf_session_resc_alloc_output {
49791 /* The specific error status for the command. */
49792 uint16_t error_code;
49793 /* The HWRM command request type. */
49795 /* The sequence ID from the original command. */
49797 /* The length of the response data in number of bytes. */
49800 * Size of the returned tf_rm_resc_entry data array. The value
49801 * cannot exceed the req_size defined by the input msg. The data
49802 * array is returned using the resv_addr specified DMA
49803 * address also provided by the input msg.
49807 uint8_t unused0[5];
49809 * This field is used in Output records to indicate that the output
49810 * is completely written to RAM. This field should be read as '1'
49811 * to indicate that the output has been completely written.
49812 * When writing a command completion or response to an internal
49813 * processor, the order of writes has to be such that this field is
49819 /*****************************
49820 * hwrm_tf_session_resc_free *
49821 *****************************/
49824 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
49825 struct hwrm_tf_session_resc_free_input {
49826 /* The HWRM command request type. */
49829 * The completion ring to send the completion event on. This should
49830 * be the NQ ID returned from the `nq_alloc` HWRM command.
49832 uint16_t cmpl_ring;
49834 * The sequence ID is used by the driver for tracking multiple
49835 * commands. This ID is treated as opaque data by the firmware and
49836 * the value is returned in the `hwrm_resp_hdr` upon completion.
49840 * The target ID of the command:
49841 * * 0x0-0xFFF8 - The function ID
49842 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49843 * * 0xFFFD - Reserved for user-space HWRM interface
49846 uint16_t target_id;
49848 * A physical address pointer pointing to a host buffer that the
49849 * command's response data will be written. This can be either a host
49850 * physical address (HPA) or a guest physical address (GPA) and must
49851 * point to a physically contiguous block of memory.
49853 uint64_t resp_addr;
49854 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49855 uint32_t fw_session_id;
49856 /* Control flags. */
49858 /* Indicates the flow direction. */
49859 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
49860 /* If this bit set to 0, then it indicates rx flow. */
49861 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49862 /* If this bit is set to 1, then it indicates tx flow. */
49863 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49864 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
49865 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
49867 * Defines the size, in bytes, of the provided free_addr
49870 uint16_t free_size;
49872 * This is the DMA address for the free input data array
49873 * buffer. Array is of tf_rm_resc_entry type. Size of the
49874 * buffer is provided by the 'free_size' field of this
49877 uint64_t free_addr;
49880 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
49881 struct hwrm_tf_session_resc_free_output {
49882 /* The specific error status for the command. */
49883 uint16_t error_code;
49884 /* The HWRM command request type. */
49886 /* The sequence ID from the original command. */
49888 /* The length of the response data in number of bytes. */
49891 uint8_t unused0[7];
49893 * This field is used in Output records to indicate that the output
49894 * is completely written to RAM. This field should be read as '1'
49895 * to indicate that the output has been completely written.
49896 * When writing a command completion or response to an internal
49897 * processor, the order of writes has to be such that this field is
49903 /******************************
49904 * hwrm_tf_session_resc_flush *
49905 ******************************/
49908 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
49909 struct hwrm_tf_session_resc_flush_input {
49910 /* The HWRM command request type. */
49913 * The completion ring to send the completion event on. This should
49914 * be the NQ ID returned from the `nq_alloc` HWRM command.
49916 uint16_t cmpl_ring;
49918 * The sequence ID is used by the driver for tracking multiple
49919 * commands. This ID is treated as opaque data by the firmware and
49920 * the value is returned in the `hwrm_resp_hdr` upon completion.
49924 * The target ID of the command:
49925 * * 0x0-0xFFF8 - The function ID
49926 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49927 * * 0xFFFD - Reserved for user-space HWRM interface
49930 uint16_t target_id;
49932 * A physical address pointer pointing to a host buffer that the
49933 * command's response data will be written. This can be either a host
49934 * physical address (HPA) or a guest physical address (GPA) and must
49935 * point to a physically contiguous block of memory.
49937 uint64_t resp_addr;
49938 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
49939 uint32_t fw_session_id;
49940 /* Control flags. */
49942 /* Indicates the flow direction. */
49943 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
49944 /* If this bit set to 0, then it indicates rx flow. */
49945 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
49946 /* If this bit is set to 1, then it indicates tx flow. */
49947 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
49948 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
49949 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
49951 * Defines the size, in bytes, of the provided flush_addr
49954 uint16_t flush_size;
49956 * This is the DMA address for the flush input data array
49957 * buffer. Array of tf_rm_resc_entry type. Size of the
49958 * buffer is provided by the 'flush_size' field in this
49961 uint64_t flush_addr;
49964 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
49965 struct hwrm_tf_session_resc_flush_output {
49966 /* The specific error status for the command. */
49967 uint16_t error_code;
49968 /* The HWRM command request type. */
49970 /* The sequence ID from the original command. */
49972 /* The length of the response data in number of bytes. */
49975 uint8_t unused0[7];
49977 * This field is used in Output records to indicate that the output
49978 * is completely written to RAM. This field should be read as '1'
49979 * to indicate that the output has been completely written.
49980 * When writing a command completion or response to an internal
49981 * processor, the order of writes has to be such that this field is
49987 /*****************************
49988 * hwrm_tf_session_resc_info *
49989 *****************************/
49992 /* hwrm_tf_session_resc_info_input (size:320b/40B) */
49993 struct hwrm_tf_session_resc_info_input {
49994 /* The HWRM command request type. */
49997 * The completion ring to send the completion event on. This should
49998 * be the NQ ID returned from the `nq_alloc` HWRM command.
50000 uint16_t cmpl_ring;
50002 * The sequence ID is used by the driver for tracking multiple
50003 * commands. This ID is treated as opaque data by the firmware and
50004 * the value is returned in the `hwrm_resp_hdr` upon completion.
50008 * The target ID of the command:
50009 * * 0x0-0xFFF8 - The function ID
50010 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50011 * * 0xFFFD - Reserved for user-space HWRM interface
50014 uint16_t target_id;
50016 * A physical address pointer pointing to a host buffer that the
50017 * command's response data will be written. This can be either a host
50018 * physical address (HPA) or a guest physical address (GPA) and must
50019 * point to a physically contiguous block of memory.
50021 uint64_t resp_addr;
50022 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50023 uint32_t fw_session_id;
50024 /* Control flags. */
50026 /* Indicates the flow direction. */
50027 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
50028 /* If this bit set to 0, then it indicates rx flow. */
50029 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
50030 /* If this bit is set to 1, then it indicates tx flow. */
50031 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
50032 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \
50033 HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX
50035 * Defines the array size of the provided req_addr and
50036 * resv_addr array buffers. Should be set to the number of
50041 * This is the DMA address for the request input data array
50042 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
50043 * array buffer is provided by the 'req_size' field in this
50048 * This is the DMA address for the resc output data array
50049 * buffer. Array is of tf_rm_resc_entry type. Size of the array
50050 * buffer is provided by the 'req_size' field in this
50053 uint64_t resc_addr;
50056 /* hwrm_tf_session_resc_info_output (size:128b/16B) */
50057 struct hwrm_tf_session_resc_info_output {
50058 /* The specific error status for the command. */
50059 uint16_t error_code;
50060 /* The HWRM command request type. */
50062 /* The sequence ID from the original command. */
50064 /* The length of the response data in number of bytes. */
50067 * Size of the returned tf_rm_resc_entry data array. The value
50068 * cannot exceed the req_size defined by the input msg. The data
50069 * array is returned using the resv_addr specified DMA
50070 * address also provided by the input msg.
50074 uint8_t unused0[5];
50076 * This field is used in Output records to indicate that the output
50077 * is completely written to RAM. This field should be read as '1'
50078 * to indicate that the output has been completely written.
50079 * When writing a command completion or response to an internal
50080 * processor, the order of writes has to be such that this field is
50086 /* TruFlow RM capability of a resource. */
50087 /* tf_rm_resc_req_entry (size:64b/8B) */
50088 struct tf_rm_resc_req_entry {
50089 /* Type of the resource, defined globally in HCAPI RM. */
50091 /* Minimum value. */
50093 /* Maximum value. */
50097 /* TruFlow RM reservation information. */
50098 /* tf_rm_resc_entry (size:64b/8B) */
50099 struct tf_rm_resc_entry {
50100 /* Type of the resource, defined globally in HCAPI RM. */
50102 /* Start offset. */
50104 /* Number of resources. */
50108 /************************
50109 * hwrm_tf_tbl_type_get *
50110 ************************/
50113 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
50114 struct hwrm_tf_tbl_type_get_input {
50115 /* The HWRM command request type. */
50118 * The completion ring to send the completion event on. This should
50119 * be the NQ ID returned from the `nq_alloc` HWRM command.
50121 uint16_t cmpl_ring;
50123 * The sequence ID is used by the driver for tracking multiple
50124 * commands. This ID is treated as opaque data by the firmware and
50125 * the value is returned in the `hwrm_resp_hdr` upon completion.
50129 * The target ID of the command:
50130 * * 0x0-0xFFF8 - The function ID
50131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50132 * * 0xFFFD - Reserved for user-space HWRM interface
50135 uint16_t target_id;
50137 * A physical address pointer pointing to a host buffer that the
50138 * command's response data will be written. This can be either a host
50139 * physical address (HPA) or a guest physical address (GPA) and must
50140 * point to a physically contiguous block of memory.
50142 uint64_t resp_addr;
50143 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50144 uint32_t fw_session_id;
50145 /* Control flags. */
50147 /* Indicates the flow direction. */
50148 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \
50150 /* If this bit set to 0, then it indicates rx flow. */
50151 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \
50153 /* If this bit is set to 1, then it indicates tx flow. */
50154 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \
50156 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
50157 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
50159 * When set use the special access register access to clear
50160 * the table entry on read.
50162 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \
50165 uint8_t unused0[2];
50167 * Type of the resource, defined globally in the
50168 * hwrm_tf_resc_type enum.
50171 /* Index of the type to retrieve. */
50175 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
50176 struct hwrm_tf_tbl_type_get_output {
50177 /* The specific error status for the command. */
50178 uint16_t error_code;
50179 /* The HWRM command request type. */
50181 /* The sequence ID from the original command. */
50183 /* The length of the response data in number of bytes. */
50185 /* Response code. */
50186 uint32_t resp_code;
50187 /* Response size. */
50191 /* Response data. */
50194 uint8_t unused1[7];
50196 * This field is used in Output records to indicate that the output
50197 * is completely written to RAM. This field should be read as '1'
50198 * to indicate that the output has been completely written.
50199 * When writing a command completion or response to an internal
50200 * processor, the order of writes has to be such that this field
50206 /************************
50207 * hwrm_tf_tbl_type_set *
50208 ************************/
50211 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
50212 struct hwrm_tf_tbl_type_set_input {
50213 /* The HWRM command request type. */
50216 * The completion ring to send the completion event on. This should
50217 * be the NQ ID returned from the `nq_alloc` HWRM command.
50219 uint16_t cmpl_ring;
50221 * The sequence ID is used by the driver for tracking multiple
50222 * commands. This ID is treated as opaque data by the firmware and
50223 * the value is returned in the `hwrm_resp_hdr` upon completion.
50227 * The target ID of the command:
50228 * * 0x0-0xFFF8 - The function ID
50229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50230 * * 0xFFFD - Reserved for user-space HWRM interface
50233 uint16_t target_id;
50235 * A physical address pointer pointing to a host buffer that the
50236 * command's response data will be written. This can be either a host
50237 * physical address (HPA) or a guest physical address (GPA) and must
50238 * point to a physically contiguous block of memory.
50240 uint64_t resp_addr;
50241 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50242 uint32_t fw_session_id;
50243 /* Control flags. */
50245 /* Indicates the flow direction. */
50246 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
50247 /* If this bit set to 0, then it indicates rx flow. */
50248 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
50249 /* If this bit is set to 1, then it indicates tx flow. */
50250 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
50251 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
50252 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
50254 uint8_t unused0[2];
50256 * Type of the resource, defined globally in the
50257 * hwrm_tf_resc_type enum.
50260 /* Index of the type to retrieve. */
50262 /* Size of the data to set. */
50265 uint8_t unused1[6];
50266 /* Data to be set. */
50270 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
50271 struct hwrm_tf_tbl_type_set_output {
50272 /* The specific error status for the command. */
50273 uint16_t error_code;
50274 /* The HWRM command request type. */
50276 /* The sequence ID from the original command. */
50278 /* The length of the response data in number of bytes. */
50281 uint8_t unused0[7];
50283 * This field is used in Output records to indicate that the output
50284 * is completely written to RAM. This field should be read as '1'
50285 * to indicate that the output has been completely written.
50286 * When writing a command completion or response to an internal
50287 * processor, the order of writes has to be such that this field
50293 /**************************
50294 * hwrm_tf_ctxt_mem_alloc *
50295 **************************/
50298 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
50299 struct hwrm_tf_ctxt_mem_alloc_input {
50300 /* The HWRM command request type. */
50303 * The completion ring to send the completion event on. This should
50304 * be the NQ ID returned from the `nq_alloc` HWRM command.
50306 uint16_t cmpl_ring;
50308 * The sequence ID is used by the driver for tracking multiple
50309 * commands. This ID is treated as opaque data by the firmware and
50310 * the value is returned in the `hwrm_resp_hdr` upon completion.
50314 * The target ID of the command:
50315 * * 0x0-0xFFF8 - The function ID
50316 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50317 * * 0xFFFD - Reserved for user-space HWRM interface
50320 uint16_t target_id;
50322 * A physical address pointer pointing to a host buffer that the
50323 * command's response data will be written. This can be either a host
50324 * physical address (HPA) or a guest physical address (GPA) and must
50325 * point to a physically contiguous block of memory.
50327 uint64_t resp_addr;
50328 /* Size in KB of memory to be allocated. */
50330 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50331 uint32_t fw_session_id;
50334 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
50335 struct hwrm_tf_ctxt_mem_alloc_output {
50336 /* The specific error status for the command. */
50337 uint16_t error_code;
50338 /* The HWRM command request type. */
50340 /* The sequence ID from the original command. */
50342 /* The length of the response data in number of bytes. */
50344 /* Pointer to the PBL, or PDL depending on number of levels */
50346 /* Size of memory allocated. */
50348 /* Counter PBL indirect levels. */
50349 uint8_t page_level;
50350 /* PBL pointer is physical start address. */
50351 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
50352 /* PBL pointer points to PTE table. */
50353 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
50355 * PBL pointer points to PDE table with each entry pointing
50358 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
50359 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
50360 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
50363 /* 4KB page size. */
50364 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
50365 /* 8KB page size. */
50366 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
50367 /* 64KB page size. */
50368 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
50369 /* 128KB page size. */
50370 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
50371 /* 256KB page size. */
50372 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
50373 /* 512KB page size. */
50374 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
50375 /* 1MB page size. */
50376 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
50377 /* 2MB page size. */
50378 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
50379 /* 4MB page size. */
50380 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
50381 /* 8MB page size. */
50382 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
50383 /* 1GB page size. */
50384 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
50385 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
50386 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
50390 * This field is used in Output records to indicate that the
50391 * output is completely written to RAM. This field should be
50392 * read as '1' to indicate that the output has been
50393 * completely written. When writing a command completion or
50394 * response to an internal processor, the order of writes has
50395 * to be such that this field is written last.
50400 /*************************
50401 * hwrm_tf_ctxt_mem_free *
50402 *************************/
50405 /* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
50406 struct hwrm_tf_ctxt_mem_free_input {
50407 /* The HWRM command request type. */
50410 * The completion ring to send the completion event on. This should
50411 * be the NQ ID returned from the `nq_alloc` HWRM command.
50413 uint16_t cmpl_ring;
50415 * The sequence ID is used by the driver for tracking multiple
50416 * commands. This ID is treated as opaque data by the firmware and
50417 * the value is returned in the `hwrm_resp_hdr` upon completion.
50421 * The target ID of the command:
50422 * * 0x0-0xFFF8 - The function ID
50423 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50424 * * 0xFFFD - Reserved for user-space HWRM interface
50427 uint16_t target_id;
50429 * A physical address pointer pointing to a host buffer that the
50430 * command's response data will be written. This can be either a host
50431 * physical address (HPA) or a guest physical address (GPA) and must
50432 * point to a physically contiguous block of memory.
50434 uint64_t resp_addr;
50435 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50436 uint32_t fw_session_id;
50437 /* Counter PBL indirect levels. */
50438 uint8_t page_level;
50439 /* PBL pointer is physical start address. */
50440 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
50441 /* PBL pointer points to PTE table. */
50442 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
50444 * PBL pointer points to PDE table with each entry pointing
50447 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
50448 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
50449 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
50452 /* 4KB page size. */
50453 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
50454 /* 8KB page size. */
50455 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
50456 /* 64KB page size. */
50457 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
50458 /* 128KB page size. */
50459 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
50460 /* 256KB page size. */
50461 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
50462 /* 512KB page size. */
50463 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
50464 /* 1MB page size. */
50465 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
50466 /* 2MB page size. */
50467 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
50468 /* 4MB page size. */
50469 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
50470 /* 8MB page size. */
50471 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
50472 /* 1GB page size. */
50473 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
50474 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
50475 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
50477 uint8_t unused0[2];
50478 /* Pointer to the PBL, or PDL depending on number of levels */
50480 /* Size of memory allocated. */
50483 uint8_t unused1[4];
50486 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
50487 struct hwrm_tf_ctxt_mem_free_output {
50488 /* The specific error status for the command. */
50489 uint16_t error_code;
50490 /* The HWRM command request type. */
50492 /* The sequence ID from the original command. */
50494 /* The length of the response data in number of bytes. */
50497 uint8_t unused0[7];
50499 * This field is used in Output records to indicate that the
50500 * output is completely written to RAM. This field should be
50501 * read as '1' to indicate that the output has been
50502 * completely written. When writing a command completion or
50503 * response to an internal processor, the order of writes has
50504 * to be such that this field is written last.
50509 /*************************
50510 * hwrm_tf_ctxt_mem_rgtr *
50511 *************************/
50514 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
50515 struct hwrm_tf_ctxt_mem_rgtr_input {
50516 /* The HWRM command request type. */
50519 * The completion ring to send the completion event on. This should
50520 * be the NQ ID returned from the `nq_alloc` HWRM command.
50522 uint16_t cmpl_ring;
50524 * The sequence ID is used by the driver for tracking multiple
50525 * commands. This ID is treated as opaque data by the firmware and
50526 * the value is returned in the `hwrm_resp_hdr` upon completion.
50530 * The target ID of the command:
50531 * * 0x0-0xFFF8 - The function ID
50532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50533 * * 0xFFFD - Reserved for user-space HWRM interface
50536 uint16_t target_id;
50538 * A physical address pointer pointing to a host buffer that the
50539 * command's response data will be written. This can be either a host
50540 * physical address (HPA) or a guest physical address (GPA) and must
50541 * point to a physically contiguous block of memory.
50543 uint64_t resp_addr;
50544 /* Control flags. */
50546 /* Counter PBL indirect levels. */
50547 uint8_t page_level;
50548 /* PBL pointer is physical start address. */
50549 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
50550 /* PBL pointer points to PTE table. */
50551 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
50553 * PBL pointer points to PDE table with each entry pointing
50556 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
50557 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
50558 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
50561 /* 4KB page size. */
50562 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
50563 /* 8KB page size. */
50564 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
50565 /* 64KB page size. */
50566 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
50567 /* 128KB page size. */
50568 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
50569 /* 256KB page size. */
50570 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
50571 /* 512KB page size. */
50572 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
50573 /* 1MB page size. */
50574 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
50575 /* 2MB page size. */
50576 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
50577 /* 4MB page size. */
50578 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
50579 /* 8MB page size. */
50580 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
50581 /* 1GB page size. */
50582 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
50583 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
50584 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
50585 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50586 uint32_t fw_session_id;
50587 /* Pointer to the PBL, or PDL depending on number of levels */
50591 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
50592 struct hwrm_tf_ctxt_mem_rgtr_output {
50593 /* The specific error status for the command. */
50594 uint16_t error_code;
50595 /* The HWRM command request type. */
50597 /* The sequence ID from the original command. */
50599 /* The length of the response data in number of bytes. */
50602 * Id/Handle to the recently register context memory. This
50603 * handle is passed to the TF session.
50607 uint8_t unused0[5];
50609 * This field is used in Output records to indicate that the
50610 * output is completely written to RAM. This field should be
50611 * read as '1' to indicate that the output has been
50612 * completely written. When writing a command completion or
50613 * response to an internal processor, the order of writes has
50614 * to be such that this field is written last.
50619 /***************************
50620 * hwrm_tf_ctxt_mem_unrgtr *
50621 ***************************/
50624 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
50625 struct hwrm_tf_ctxt_mem_unrgtr_input {
50626 /* The HWRM command request type. */
50629 * The completion ring to send the completion event on. This should
50630 * be the NQ ID returned from the `nq_alloc` HWRM command.
50632 uint16_t cmpl_ring;
50634 * The sequence ID is used by the driver for tracking multiple
50635 * commands. This ID is treated as opaque data by the firmware and
50636 * the value is returned in the `hwrm_resp_hdr` upon completion.
50640 * The target ID of the command:
50641 * * 0x0-0xFFF8 - The function ID
50642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50643 * * 0xFFFD - Reserved for user-space HWRM interface
50646 uint16_t target_id;
50648 * A physical address pointer pointing to a host buffer that the
50649 * command's response data will be written. This can be either a host
50650 * physical address (HPA) or a guest physical address (GPA) and must
50651 * point to a physically contiguous block of memory.
50653 uint64_t resp_addr;
50655 * Id/Handle to the recently register context memory. This
50656 * handle is passed to the TF session.
50660 uint8_t unused0[2];
50661 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50662 uint32_t fw_session_id;
50665 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
50666 struct hwrm_tf_ctxt_mem_unrgtr_output {
50667 /* The specific error status for the command. */
50668 uint16_t error_code;
50669 /* The HWRM command request type. */
50671 /* The sequence ID from the original command. */
50673 /* The length of the response data in number of bytes. */
50676 uint8_t unused0[7];
50678 * This field is used in Output records to indicate that the
50679 * output is completely written to RAM. This field should be
50680 * read as '1' to indicate that the output has been
50681 * completely written. When writing a command completion or
50682 * response to an internal processor, the order of writes has
50683 * to be such that this field is written last.
50688 /************************
50689 * hwrm_tf_ext_em_qcaps *
50690 ************************/
50693 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
50694 struct hwrm_tf_ext_em_qcaps_input {
50695 /* The HWRM command request type. */
50698 * The completion ring to send the completion event on. This should
50699 * be the NQ ID returned from the `nq_alloc` HWRM command.
50701 uint16_t cmpl_ring;
50703 * The sequence ID is used by the driver for tracking multiple
50704 * commands. This ID is treated as opaque data by the firmware and
50705 * the value is returned in the `hwrm_resp_hdr` upon completion.
50709 * The target ID of the command:
50710 * * 0x0-0xFFF8 - The function ID
50711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50712 * * 0xFFFD - Reserved for user-space HWRM interface
50715 uint16_t target_id;
50717 * A physical address pointer pointing to a host buffer that the
50718 * command's response data will be written. This can be either a host
50719 * physical address (HPA) or a guest physical address (GPA) and must
50720 * point to a physically contiguous block of memory.
50722 uint64_t resp_addr;
50723 /* Control flags. */
50725 /* Indicates the flow direction. */
50726 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
50728 /* If this bit set to 0, then it indicates rx flow. */
50729 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
50731 /* If this bit is set to 1, then it indicates tx flow. */
50732 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
50734 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
50735 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
50736 /* When set to 1, all offloaded flows will be sent to EXT EM. */
50737 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
50739 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50740 uint32_t fw_session_id;
50743 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
50744 struct hwrm_tf_ext_em_qcaps_output {
50745 /* The specific error status for the command. */
50746 uint16_t error_code;
50747 /* The HWRM command request type. */
50749 /* The sequence ID from the original command. */
50751 /* The length of the response data in number of bytes. */
50755 * When set to 1, indicates the FW supports the Centralized
50756 * Memory Model. The concept designates one entity for the
50757 * memory allocation while all others ‘subscribe’ to it.
50759 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
50762 * When set to 1, indicates the FW supports the Detached
50763 * Centralized Memory Model. The memory is allocated and managed
50764 * as a separate entity. All PFs and VFs will be granted direct
50765 * or semi-direct access to the allocated memory while none of
50766 * which can interfere with the management of the memory.
50768 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
50770 /* When set to 1, indicates FW support for host based EEM memory. */
50771 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
50773 /* When set to 1, indicates FW support for on-chip based EEM memory. */
50774 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
50778 /* Support flags. */
50779 uint32_t supported;
50781 * If set to 1, then EXT EM KEY0 table is supported using
50783 * If set to 0, EXT EM KEY0 table is not supported.
50785 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
50788 * If set to 1, then EXT EM KEY1 table is supported using
50790 * If set to 0, EXT EM KEY1 table is not supported.
50792 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
50795 * If set to 1, then EXT EM External Record table is supported.
50796 * If set to 0, EXT EM External Record table is not
50797 * supported. (This table includes action record, EFC
50798 * pointers, encap pointers)
50800 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
50803 * If set to 1, then EXT EM External Flow Counters table is
50805 * If set to 0, EXT EM External Flow Counters table is not
50808 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
50811 * If set to 1, then FID table used for implicit flow flush
50813 * If set to 0, then FID table used for implicit flow flush
50814 * is not supported.
50816 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
50819 * If set to 1, then table scopes are supported.
50820 * If set to 0, then table scopes are not supported.
50822 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
50825 * The maximum number of entries supported by EXT EM. When
50826 * configuring the host memory the number of numbers of
50827 * entries that can supported are -
50828 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
50830 * Any value that are not these values, the FW will round
50831 * down to the closest support number of entries.
50833 uint32_t max_entries_supported;
50835 * The entry size in bytes of each entry in the EXT EM
50836 * KEY0/KEY1 tables.
50838 uint16_t key_entry_size;
50840 * The entry size in bytes of each entry in the EXT EM RECORD
50843 uint16_t record_entry_size;
50844 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
50845 uint16_t efc_entry_size;
50846 /* The FID size in bytes of each entry in the EXT EM FID tables. */
50847 uint16_t fid_entry_size;
50848 /* Maximum number of ctxt mem allocations allowed. */
50849 uint32_t max_ctxt_mem_allocs;
50851 * Maximum number of static buckets that can be assigned to lookup
50854 uint32_t max_static_buckets;
50856 uint8_t unused1[7];
50858 * This field is used in Output records to indicate that the
50859 * output is completely written to RAM. This field should be
50860 * read as '1' to indicate that the output has been
50861 * completely written. When writing a command completion or
50862 * response to an internal processor, the order of writes has
50863 * to be such that this field is written last.
50868 /*********************
50869 * hwrm_tf_ext_em_op *
50870 *********************/
50873 /* hwrm_tf_ext_em_op_input (size:256b/32B) */
50874 struct hwrm_tf_ext_em_op_input {
50875 /* The HWRM command request type. */
50878 * The completion ring to send the completion event on. This should
50879 * be the NQ ID returned from the `nq_alloc` HWRM command.
50881 uint16_t cmpl_ring;
50883 * The sequence ID is used by the driver for tracking multiple
50884 * commands. This ID is treated as opaque data by the firmware and
50885 * the value is returned in the `hwrm_resp_hdr` upon completion.
50889 * The target ID of the command:
50890 * * 0x0-0xFFF8 - The function ID
50891 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50892 * * 0xFFFD - Reserved for user-space HWRM interface
50895 uint16_t target_id;
50897 * A physical address pointer pointing to a host buffer that the
50898 * command's response data will be written. This can be either a host
50899 * physical address (HPA) or a guest physical address (GPA) and must
50900 * point to a physically contiguous block of memory.
50902 uint64_t resp_addr;
50903 /* Control flags. */
50905 /* Indicates the flow direction. */
50906 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
50907 /* If this bit set to 0, then it indicates rx flow. */
50908 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
50909 /* If this bit is set to 1, then it indicates tx flow. */
50910 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
50911 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
50912 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
50915 /* The number of EXT EM key table entries to be configured. */
50917 /* This value is reserved and should not be used. */
50918 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
50920 * To properly stop EXT EM and ensure there are no DMA's,
50921 * the caller must disable EXT EM for the given PF, using
50922 * this call. This will safely disable EXT EM and ensure
50923 * that all DMA'ed to the keys/records/efc have been
50926 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
50928 * Once the EXT EM host memory has been configured, EXT EM
50929 * options have been configured. Then the caller should
50930 * enable EXT EM for the given PF. Note once this call has
50931 * been made, then the EXT EM mechanism will be active and
50932 * DMA's will occur as packets are processed.
50934 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
50936 * Clear EXT EM settings for the given PF so that the
50937 * register values are reset back to their initial state.
50939 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
50940 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
50941 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
50944 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
50945 uint32_t fw_session_id;
50950 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
50951 struct hwrm_tf_ext_em_op_output {
50952 /* The specific error status for the command. */
50953 uint16_t error_code;
50954 /* The HWRM command request type. */
50956 /* The sequence ID from the original command. */
50958 /* The length of the response data in number of bytes. */
50961 uint8_t unused0[7];
50963 * This field is used in Output records to indicate that the
50964 * output is completely written to RAM. This field should be
50965 * read as '1' to indicate that the output has been
50966 * completely written. When writing a command completion or
50967 * response to an internal processor, the order of writes has
50968 * to be such that this field is written last.
50973 /**********************
50974 * hwrm_tf_ext_em_cfg *
50975 **********************/
50978 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
50979 struct hwrm_tf_ext_em_cfg_input {
50980 /* The HWRM command request type. */
50983 * The completion ring to send the completion event on. This should
50984 * be the NQ ID returned from the `nq_alloc` HWRM command.
50986 uint16_t cmpl_ring;
50988 * The sequence ID is used by the driver for tracking multiple
50989 * commands. This ID is treated as opaque data by the firmware and
50990 * the value is returned in the `hwrm_resp_hdr` upon completion.
50994 * The target ID of the command:
50995 * * 0x0-0xFFF8 - The function ID
50996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50997 * * 0xFFFD - Reserved for user-space HWRM interface
51000 uint16_t target_id;
51002 * A physical address pointer pointing to a host buffer that the
51003 * command's response data will be written. This can be either a host
51004 * physical address (HPA) or a guest physical address (GPA) and must
51005 * point to a physically contiguous block of memory.
51007 uint64_t resp_addr;
51008 /* Control flags. */
51010 /* Indicates the flow direction. */
51011 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
51013 /* If this bit set to 0, then it indicates rx flow. */
51014 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
51016 /* If this bit is set to 1, then it indicates tx flow. */
51017 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
51019 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
51020 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
51021 /* When set to 1, all offloaded flows will be sent to EXT EM. */
51022 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
51024 /* When set to 1, secondary, 0 means primary. */
51025 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
51028 * Group_id which used by Firmware to identify memory pools belonging
51029 * to certain group.
51033 * Dynamically reconfigure EEM pending cache every 1/10th of second.
51034 * If set to 0 it will disable the EEM HW flush of the pending cache.
51036 uint8_t flush_interval;
51040 * Configured EXT EM with the given number of entries. All
51041 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
51042 * same number of entries and all tables will be configured
51043 * using this value. Current minimum value is 32k. Current
51044 * maximum value is 128M.
51046 uint32_t num_entries;
51049 * This bit must be '1' for the group_id field to be
51052 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
51055 * This bit must be '1' for the flush_interval field to be
51058 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
51061 * This bit must be '1' for the num_entries field to be
51064 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
51067 * This bit must be '1' for the key0_ctx_id field to be
51070 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
51073 * This bit must be '1' for the key1_ctx_id field to be
51076 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
51079 * This bit must be '1' for the record_ctx_id field to be
51082 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
51085 * This bit must be '1' for the efc_ctx_id field to be
51088 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
51091 * This bit must be '1' for the fid_ctx_id field to be
51094 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
51097 * This bit must be '1' for the action_ctx_id field to be
51100 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
51103 * This bit must be '1' for the action_tbl_scope field to be
51106 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
51109 * This bit must be '1' for the lkup_ctx_id field to be
51112 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
51115 * This bit must be '1' for the lkup_tbl_scope field to be
51118 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
51121 * This bit must be '1' for the lkup_static_buckets field to be
51124 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
51126 /* Configured EXT EM with the given context if for KEY0 table. */
51127 uint16_t key0_ctx_id;
51128 /* Configured EXT EM with the given context if for KEY1 table. */
51129 uint16_t key1_ctx_id;
51130 /* Configured EXT EM with the given context if for RECORD table. */
51131 uint16_t record_ctx_id;
51132 /* Configured EXT EM with the given context if for EFC table. */
51133 uint16_t efc_ctx_id;
51134 /* Configured EXT EM with the given context if for EFC table. */
51135 uint16_t fid_ctx_id;
51136 /* Context id of action table scope. */
51137 uint16_t action_ctx_id;
51138 /* Table scope id used for action record entries. */
51139 uint16_t action_tbl_scope;
51140 /* Context id of lookup table scope. */
51141 uint16_t lkup_ctx_id;
51142 /* Table scope id used for EM lookup entries. */
51143 uint16_t lkup_tbl_scope;
51147 * Number of 32B static buckets to be allocated at the beginning
51150 uint32_t lkup_static_buckets;
51151 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51152 uint32_t fw_session_id;
51157 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
51158 struct hwrm_tf_ext_em_cfg_output {
51159 /* The specific error status for the command. */
51160 uint16_t error_code;
51161 /* The HWRM command request type. */
51163 /* The sequence ID from the original command. */
51165 /* The length of the response data in number of bytes. */
51168 uint8_t unused0[7];
51170 * This field is used in Output records to indicate that the
51171 * output is completely written to RAM. This field should be
51172 * read as '1' to indicate that the output has been
51173 * completely written. When writing a command completion or
51174 * response to an internal processor, the order of writes has
51175 * to be such that this field is written last.
51180 /***********************
51181 * hwrm_tf_ext_em_qcfg *
51182 ***********************/
51185 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
51186 struct hwrm_tf_ext_em_qcfg_input {
51187 /* The HWRM command request type. */
51190 * The completion ring to send the completion event on. This should
51191 * be the NQ ID returned from the `nq_alloc` HWRM command.
51193 uint16_t cmpl_ring;
51195 * The sequence ID is used by the driver for tracking multiple
51196 * commands. This ID is treated as opaque data by the firmware and
51197 * the value is returned in the `hwrm_resp_hdr` upon completion.
51201 * The target ID of the command:
51202 * * 0x0-0xFFF8 - The function ID
51203 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51204 * * 0xFFFD - Reserved for user-space HWRM interface
51207 uint16_t target_id;
51209 * A physical address pointer pointing to a host buffer that the
51210 * command's response data will be written. This can be either a host
51211 * physical address (HPA) or a guest physical address (GPA) and must
51212 * point to a physically contiguous block of memory.
51214 uint64_t resp_addr;
51215 /* Control flags. */
51217 /* Indicates the flow direction. */
51218 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
51219 /* If this bit set to 0, then it indicates rx flow. */
51220 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51221 /* If this bit is set to 1, then it indicates tx flow. */
51222 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51223 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
51224 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
51225 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51226 uint32_t fw_session_id;
51229 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
51230 struct hwrm_tf_ext_em_qcfg_output {
51231 /* The specific error status for the command. */
51232 uint16_t error_code;
51233 /* The HWRM command request type. */
51235 /* The sequence ID from the original command. */
51237 /* The length of the response data in number of bytes. */
51239 /* Control flags. */
51241 /* Indicates the flow direction. */
51242 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
51244 /* If this bit set to 0, then it indicates rx flow. */
51245 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
51247 /* If this bit is set to 1, then it indicates tx flow. */
51248 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
51250 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
51251 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
51252 /* When set to 1, all offloaded flows will be sent to EXT EM. */
51253 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
51255 /* The number of entries the FW has configured for EXT EM. */
51256 uint32_t num_entries;
51257 /* Configured EXT EM with the given context if for KEY0 table. */
51258 uint16_t key0_ctx_id;
51259 /* Configured EXT EM with the given context if for KEY1 table. */
51260 uint16_t key1_ctx_id;
51261 /* Configured EXT EM with the given context if for RECORD table. */
51262 uint16_t record_ctx_id;
51263 /* Configured EXT EM with the given context if for EFC table. */
51264 uint16_t efc_ctx_id;
51265 /* Configured EXT EM with the given context if for EFC table. */
51266 uint16_t fid_ctx_id;
51269 uint32_t supported;
51270 /* This bit must be '1' for the group_id field is set. */
51271 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
51273 /* This bit must be '1' for the flush_interval field is set. */
51274 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
51276 /* This bit must be '1' for the num_entries field is set. */
51277 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
51279 /* This bit must be '1' for the key0_ctx_id field is set. */
51280 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
51282 /* This bit must be '1' for the key1_ctx_id field is set. */
51283 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
51285 /* This bit must be '1' for the record_ctx_id field is set. */
51286 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
51288 /* This bit must be '1' for the efc_ctx_id field is set. */
51289 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
51291 /* This bit must be '1' for the fid_ctx_id field is set. */
51292 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
51294 /* This bit must be '1' for the action_ctx_id field is set. */
51295 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
51297 /* This bit must be '1' for the action_tbl_scope field is set. */
51298 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
51300 /* This bit must be '1' for the lkup_ctx_id field is set. */
51301 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
51303 /* This bit must be '1' for the lkup_tbl_scope field is set. */
51304 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
51306 /* This bit must be '1' for the lkup_static_buckets field is set. */
51307 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
51310 * Group id is used by firmware to identify memory pools belonging
51311 * to certain group.
51314 /* EEM pending cache flush interval in 1/10th of second. */
51315 uint8_t flush_interval;
51318 /* Context id of action table scope. */
51319 uint16_t action_ctx_id;
51320 /* Table scope id used for action record entries. */
51321 uint16_t action_tbl_scope;
51322 /* Context id of lookup table scope. */
51323 uint16_t lkup_ctx_id;
51324 /* Table scope id used for EM lookup entries. */
51325 uint16_t lkup_tbl_scope;
51327 * Number of 32B static buckets to be allocated at the beginning
51330 uint32_t lkup_static_buckets;
51332 uint8_t unused2[7];
51334 * This field is used in Output records to indicate that the
51335 * output is completely written to RAM. This field should be
51336 * read as '1' to indicate that the output has been
51337 * completely written. When writing a command completion or
51338 * response to an internal processor, the order of writes has
51339 * to be such that this field is written last.
51344 /*********************
51345 * hwrm_tf_em_insert *
51346 *********************/
51349 /* hwrm_tf_em_insert_input (size:832b/104B) */
51350 struct hwrm_tf_em_insert_input {
51351 /* The HWRM command request type. */
51354 * The completion ring to send the completion event on. This should
51355 * be the NQ ID returned from the `nq_alloc` HWRM command.
51357 uint16_t cmpl_ring;
51359 * The sequence ID is used by the driver for tracking multiple
51360 * commands. This ID is treated as opaque data by the firmware and
51361 * the value is returned in the `hwrm_resp_hdr` upon completion.
51365 * The target ID of the command:
51366 * * 0x0-0xFFF8 - The function ID
51367 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51368 * * 0xFFFD - Reserved for user-space HWRM interface
51371 uint16_t target_id;
51373 * A physical address pointer pointing to a host buffer that the
51374 * command's response data will be written. This can be either a host
51375 * physical address (HPA) or a guest physical address (GPA) and must
51376 * point to a physically contiguous block of memory.
51378 uint64_t resp_addr;
51379 /* Firmware Session Id. */
51380 uint32_t fw_session_id;
51381 /* Control Flags. */
51383 /* Indicates the flow direction. */
51384 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
51385 /* If this bit set to 0, then it indicates rx flow. */
51386 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51387 /* If this bit is set to 1, then it indicates tx flow. */
51388 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51389 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
51390 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
51391 /* Reported match strength. */
51393 /* Index to action. */
51394 uint32_t action_ptr;
51395 /* Index of EM record. */
51396 uint32_t em_record_idx;
51397 /* EM Key value. */
51398 uint64_t em_key[8];
51399 /* Number of bits in em_key. */
51400 uint16_t em_key_bitlen;
51402 uint16_t unused0[3];
51405 /* hwrm_tf_em_insert_output (size:128b/16B) */
51406 struct hwrm_tf_em_insert_output {
51407 /* The specific error status for the command. */
51408 uint16_t error_code;
51409 /* The HWRM command request type. */
51411 /* The sequence ID from the original command. */
51413 /* The length of the response data in number of bytes. */
51415 /* EM record pointer index. */
51416 uint16_t rptr_index;
51417 /* EM record offset 0~3. */
51418 uint8_t rptr_entry;
51419 /* Number of word entries consumed by the key. */
51420 uint8_t num_of_entries;
51425 /**************************
51426 * hwrm_tf_em_hash_insert *
51427 **************************/
51430 /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
51431 struct hwrm_tf_em_hash_insert_input {
51432 /* The HWRM command request type. */
51435 * The completion ring to send the completion event on. This should
51436 * be the NQ ID returned from the `nq_alloc` HWRM command.
51438 uint16_t cmpl_ring;
51440 * The sequence ID is used by the driver for tracking multiple
51441 * commands. This ID is treated as opaque data by the firmware and
51442 * the value is returned in the `hwrm_resp_hdr` upon completion.
51446 * The target ID of the command:
51447 * * 0x0-0xFFF8 - The function ID
51448 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51449 * * 0xFFFD - Reserved for user-space HWRM interface
51452 uint16_t target_id;
51454 * A physical address pointer pointing to a host buffer that the
51455 * command's response data will be written. This can be either a host
51456 * physical address (HPA) or a guest physical address (GPA) and must
51457 * point to a physically contiguous block of memory.
51459 uint64_t resp_addr;
51460 /* Firmware Session Id. */
51461 uint32_t fw_session_id;
51462 /* Control Flags. */
51464 /* Indicates the flow direction. */
51465 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
51466 /* If this bit set to 0, then it indicates rx flow. */
51467 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51468 /* If this bit is set to 1, then it indicates tx flow. */
51469 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51470 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
51471 HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
51472 /* Number of bits in the EM record. */
51473 uint16_t em_record_size_bits;
51474 /* CRC32 hash of key. */
51475 uint32_t key0_hash;
51476 /* Lookup3 hash of key. */
51477 uint32_t key1_hash;
51478 /* Index of EM record. */
51479 uint32_t em_record_idx;
51483 uint64_t em_record[11];
51486 /* hwrm_tf_em_hash_insert_output (size:128b/16B) */
51487 struct hwrm_tf_em_hash_insert_output {
51488 /* The specific error status for the command. */
51489 uint16_t error_code;
51490 /* The HWRM command request type. */
51492 /* The sequence ID from the original command. */
51494 /* The length of the response data in number of bytes. */
51496 /* EM record pointer index. */
51497 uint16_t rptr_index;
51498 /* EM record offset 0~3. */
51499 uint8_t rptr_entry;
51500 /* Number of word entries consumed by the key. */
51501 uint8_t num_of_entries;
51506 /*********************
51507 * hwrm_tf_em_delete *
51508 *********************/
51511 /* hwrm_tf_em_delete_input (size:832b/104B) */
51512 struct hwrm_tf_em_delete_input {
51513 /* The HWRM command request type. */
51516 * The completion ring to send the completion event on. This should
51517 * be the NQ ID returned from the `nq_alloc` HWRM command.
51519 uint16_t cmpl_ring;
51521 * The sequence ID is used by the driver for tracking multiple
51522 * commands. This ID is treated as opaque data by the firmware and
51523 * the value is returned in the `hwrm_resp_hdr` upon completion.
51527 * The target ID of the command:
51528 * * 0x0-0xFFF8 - The function ID
51529 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51530 * * 0xFFFD - Reserved for user-space HWRM interface
51533 uint16_t target_id;
51535 * A physical address pointer pointing to a host buffer that the
51536 * command's response data will be written. This can be either a host
51537 * physical address (HPA) or a guest physical address (GPA) and must
51538 * point to a physically contiguous block of memory.
51540 uint64_t resp_addr;
51542 uint32_t fw_session_id;
51543 /* Control flags. */
51545 /* Indicates the flow direction. */
51546 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
51547 /* If this bit set to 0, then it indicates rx flow. */
51548 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51549 /* If this bit is set to 1, then it indicates tx flow. */
51550 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51551 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
51552 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
51555 /* EM internal flow handle. */
51556 uint64_t flow_handle;
51558 uint64_t em_key[8];
51559 /* Number of bits in em_key. */
51560 uint16_t em_key_bitlen;
51562 uint16_t unused1[3];
51565 /* hwrm_tf_em_delete_output (size:128b/16B) */
51566 struct hwrm_tf_em_delete_output {
51567 /* The specific error status for the command. */
51568 uint16_t error_code;
51569 /* The HWRM command request type. */
51571 /* The sequence ID from the original command. */
51573 /* The length of the response data in number of bytes. */
51575 /* Original stack allocation index. */
51578 uint16_t unused0[3];
51581 /*******************
51582 * hwrm_tf_em_move *
51583 *******************/
51586 /* hwrm_tf_em_move_input (size:320b/40B) */
51587 struct hwrm_tf_em_move_input {
51588 /* The HWRM command request type. */
51591 * The completion ring to send the completion event on. This should
51592 * be the NQ ID returned from the `nq_alloc` HWRM command.
51594 uint16_t cmpl_ring;
51596 * The sequence ID is used by the driver for tracking multiple
51597 * commands. This ID is treated as opaque data by the firmware and
51598 * the value is returned in the `hwrm_resp_hdr` upon completion.
51602 * The target ID of the command:
51603 * * 0x0-0xFFF8 - The function ID
51604 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51605 * * 0xFFFD - Reserved for user-space HWRM interface
51608 uint16_t target_id;
51610 * A physical address pointer pointing to a host buffer that the
51611 * command's response data will be written. This can be either a host
51612 * physical address (HPA) or a guest physical address (GPA) and must
51613 * point to a physically contiguous block of memory.
51615 uint64_t resp_addr;
51617 uint32_t fw_session_id;
51618 /* Control flags. */
51620 /* Indicates the flow direction. */
51621 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
51622 /* If this bit set to 0, then it indicates rx flow. */
51623 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51624 /* If this bit is set to 1, then it indicates tx flow. */
51625 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51626 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \
51627 HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX
51628 /* Number of EM entry blocks */
51629 uint16_t num_blocks;
51630 /* New index for entry */
51631 uint32_t new_index;
51634 /* EM internal flow handle. */
51635 uint64_t flow_handle;
51638 /* hwrm_tf_em_move_output (size:128b/16B) */
51639 struct hwrm_tf_em_move_output {
51640 /* The specific error status for the command. */
51641 uint16_t error_code;
51642 /* The HWRM command request type. */
51644 /* The sequence ID from the original command. */
51646 /* The length of the response data in number of bytes. */
51648 /* Index of old entry. */
51651 uint16_t unused0[3];
51654 /********************
51655 * hwrm_tf_tcam_set *
51656 ********************/
51659 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
51660 struct hwrm_tf_tcam_set_input {
51661 /* The HWRM command request type. */
51664 * The completion ring to send the completion event on. This should
51665 * be the NQ ID returned from the `nq_alloc` HWRM command.
51667 uint16_t cmpl_ring;
51669 * The sequence ID is used by the driver for tracking multiple
51670 * commands. This ID is treated as opaque data by the firmware and
51671 * the value is returned in the `hwrm_resp_hdr` upon completion.
51675 * The target ID of the command:
51676 * * 0x0-0xFFF8 - The function ID
51677 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51678 * * 0xFFFD - Reserved for user-space HWRM interface
51681 uint16_t target_id;
51683 * A physical address pointer pointing to a host buffer that the
51684 * command's response data will be written. This can be either a host
51685 * physical address (HPA) or a guest physical address (GPA) and must
51686 * point to a physically contiguous block of memory.
51688 uint64_t resp_addr;
51689 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51690 uint32_t fw_session_id;
51691 /* Control flags. */
51693 /* Indicates the flow direction. */
51694 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
51695 /* If this bit set to 0, then it indicates rx flow. */
51696 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51697 /* If this bit is set to 1, then it indicates tx flow. */
51698 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51699 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
51700 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
51702 * Indicate device data is being sent via DMA, the device
51703 * data is packing does not change.
51705 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
51707 * TCAM type of the resource, defined globally in the
51708 * hwrm_tf_resc_type enum.
51711 /* Index of TCAM entry. */
51713 /* Number of bytes in the TCAM key. */
51715 /* Number of bytes in the TCAM result. */
51716 uint8_t result_size;
51718 * Offset from which the mask bytes start in the device data
51719 * array, key offset is always 0.
51721 uint8_t mask_offset;
51722 /* Offset from which the result bytes start in the device data array. */
51723 uint8_t result_offset;
51725 uint8_t unused0[6];
51727 * TCAM key located at offset 0, mask located at mask_offset
51728 * and result at result_offset for the device.
51730 uint8_t dev_data[88];
51733 /* hwrm_tf_tcam_set_output (size:128b/16B) */
51734 struct hwrm_tf_tcam_set_output {
51735 /* The specific error status for the command. */
51736 uint16_t error_code;
51737 /* The HWRM command request type. */
51739 /* The sequence ID from the original command. */
51741 /* The length of the response data in number of bytes. */
51744 uint8_t unused0[7];
51746 * This field is used in Output records to indicate that the
51747 * output is completely written to RAM. This field should be
51748 * read as '1' to indicate that the output has been
51749 * completely written. When writing a command completion or
51750 * response to an internal processor, the order of writes has
51751 * to be such that this field is written last.
51756 /********************
51757 * hwrm_tf_tcam_get *
51758 ********************/
51761 /* hwrm_tf_tcam_get_input (size:256b/32B) */
51762 struct hwrm_tf_tcam_get_input {
51763 /* The HWRM command request type. */
51766 * The completion ring to send the completion event on. This should
51767 * be the NQ ID returned from the `nq_alloc` HWRM command.
51769 uint16_t cmpl_ring;
51771 * The sequence ID is used by the driver for tracking multiple
51772 * commands. This ID is treated as opaque data by the firmware and
51773 * the value is returned in the `hwrm_resp_hdr` upon completion.
51777 * The target ID of the command:
51778 * * 0x0-0xFFF8 - The function ID
51779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51780 * * 0xFFFD - Reserved for user-space HWRM interface
51783 uint16_t target_id;
51785 * A physical address pointer pointing to a host buffer that the
51786 * command's response data will be written. This can be either a host
51787 * physical address (HPA) or a guest physical address (GPA) and must
51788 * point to a physically contiguous block of memory.
51790 uint64_t resp_addr;
51791 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51792 uint32_t fw_session_id;
51793 /* Control flags. */
51795 /* Indicates the flow direction. */
51796 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
51797 /* If this bit set to 0, then it indicates rx flow. */
51798 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51799 /* If this bit is set to 1, then it indicates tx flow. */
51800 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51801 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
51802 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
51804 * TCAM type of the resource, defined globally in the
51805 * hwrm_tf_resc_type enum.
51808 /* Index of a TCAM entry. */
51814 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
51815 struct hwrm_tf_tcam_get_output {
51816 /* The specific error status for the command. */
51817 uint16_t error_code;
51818 /* The HWRM command request type. */
51820 /* The sequence ID from the original command. */
51822 /* The length of the response data in number of bytes. */
51824 /* Number of bytes in the TCAM key. */
51826 /* Number of bytes in the TCAM entry. */
51827 uint8_t result_size;
51828 /* Offset from which the mask bytes start in the device data array. */
51829 uint8_t mask_offset;
51830 /* Offset from which the result bytes start in the device data array. */
51831 uint8_t result_offset;
51833 uint8_t unused0[4];
51835 * TCAM key located at offset 0, mask located at mask_offset
51836 * and result at result_offset for the device.
51838 uint8_t dev_data[272];
51840 uint8_t unused1[7];
51842 * This field is used in Output records to indicate that the
51843 * output is completely written to RAM. This field should be
51844 * read as '1' to indicate that the output has been
51845 * completely written. When writing a command completion or
51846 * response to an internal processor, the order of writes has
51847 * to be such that this field is written last.
51852 /*********************
51853 * hwrm_tf_tcam_move *
51854 *********************/
51857 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
51858 struct hwrm_tf_tcam_move_input {
51859 /* The HWRM command request type. */
51862 * The completion ring to send the completion event on. This should
51863 * be the NQ ID returned from the `nq_alloc` HWRM command.
51865 uint16_t cmpl_ring;
51867 * The sequence ID is used by the driver for tracking multiple
51868 * commands. This ID is treated as opaque data by the firmware and
51869 * the value is returned in the `hwrm_resp_hdr` upon completion.
51873 * The target ID of the command:
51874 * * 0x0-0xFFF8 - The function ID
51875 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51876 * * 0xFFFD - Reserved for user-space HWRM interface
51879 uint16_t target_id;
51881 * A physical address pointer pointing to a host buffer that the
51882 * command's response data will be written. This can be either a host
51883 * physical address (HPA) or a guest physical address (GPA) and must
51884 * point to a physically contiguous block of memory.
51886 uint64_t resp_addr;
51887 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51888 uint32_t fw_session_id;
51889 /* Control flags. */
51891 /* Indicates the flow direction. */
51892 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
51893 /* If this bit set to 0, then it indicates rx flow. */
51894 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51895 /* If this bit is set to 1, then it indicates tx flow. */
51896 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51897 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
51898 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
51900 * TCAM type of the resource, defined globally in the
51901 * hwrm_tf_resc_type enum.
51904 /* Number of TCAM index pairs to be swapped for the device. */
51908 /* TCAM index pairs to be swapped for the device. */
51909 uint16_t idx_pairs[48];
51912 /* hwrm_tf_tcam_move_output (size:128b/16B) */
51913 struct hwrm_tf_tcam_move_output {
51914 /* The specific error status for the command. */
51915 uint16_t error_code;
51916 /* The HWRM command request type. */
51918 /* The sequence ID from the original command. */
51920 /* The length of the response data in number of bytes. */
51923 uint8_t unused0[7];
51925 * This field is used in Output records to indicate that the
51926 * output is completely written to RAM. This field should be
51927 * read as '1' to indicate that the output has been
51928 * completely written. When writing a command completion or
51929 * response to an internal processor, the order of writes has
51930 * to be such that this field is written last.
51935 /*********************
51936 * hwrm_tf_tcam_free *
51937 *********************/
51940 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
51941 struct hwrm_tf_tcam_free_input {
51942 /* The HWRM command request type. */
51945 * The completion ring to send the completion event on. This should
51946 * be the NQ ID returned from the `nq_alloc` HWRM command.
51948 uint16_t cmpl_ring;
51950 * The sequence ID is used by the driver for tracking multiple
51951 * commands. This ID is treated as opaque data by the firmware and
51952 * the value is returned in the `hwrm_resp_hdr` upon completion.
51956 * The target ID of the command:
51957 * * 0x0-0xFFF8 - The function ID
51958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51959 * * 0xFFFD - Reserved for user-space HWRM interface
51962 uint16_t target_id;
51964 * A physical address pointer pointing to a host buffer that the
51965 * command's response data will be written. This can be either a host
51966 * physical address (HPA) or a guest physical address (GPA) and must
51967 * point to a physically contiguous block of memory.
51969 uint64_t resp_addr;
51970 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
51971 uint32_t fw_session_id;
51972 /* Control flags. */
51974 /* Indicates the flow direction. */
51975 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
51976 /* If this bit set to 0, then it indicates rx flow. */
51977 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
51978 /* If this bit is set to 1, then it indicates tx flow. */
51979 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
51980 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
51981 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
51983 * TCAM type of the resource, defined globally in the
51984 * hwrm_tf_resc_type enum.
51987 /* Number of TCAM index to be deleted for the device. */
51991 /* TCAM index list to be deleted for the device. */
51992 uint16_t idx_list[48];
51995 /* hwrm_tf_tcam_free_output (size:128b/16B) */
51996 struct hwrm_tf_tcam_free_output {
51997 /* The specific error status for the command. */
51998 uint16_t error_code;
51999 /* The HWRM command request type. */
52001 /* The sequence ID from the original command. */
52003 /* The length of the response data in number of bytes. */
52006 uint8_t unused0[7];
52008 * This field is used in Output records to indicate that the
52009 * output is completely written to RAM. This field should be
52010 * read as '1' to indicate that the output has been
52011 * completely written. When writing a command completion or
52012 * response to an internal processor, the order of writes has
52013 * to be such that this field is written last.
52018 /**************************
52019 * hwrm_tf_global_cfg_set *
52020 **************************/
52023 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
52024 struct hwrm_tf_global_cfg_set_input {
52025 /* The HWRM command request type. */
52028 * The completion ring to send the completion event on. This should
52029 * be the NQ ID returned from the `nq_alloc` HWRM command.
52031 uint16_t cmpl_ring;
52033 * The sequence ID is used by the driver for tracking multiple
52034 * commands. This ID is treated as opaque data by the firmware and
52035 * the value is returned in the `hwrm_resp_hdr` upon completion.
52039 * The target ID of the command:
52040 * * 0x0-0xFFF8 - The function ID
52041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52042 * * 0xFFFD - Reserved for user-space HWRM interface
52045 uint16_t target_id;
52047 * A physical address pointer pointing to a host buffer that the
52048 * command's response data will be written. This can be either a host
52049 * physical address (HPA) or a guest physical address (GPA) and must
52050 * point to a physically contiguous block of memory.
52052 uint64_t resp_addr;
52053 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
52054 uint32_t fw_session_id;
52055 /* Control flags. */
52057 /* Indicates the flow direction. */
52058 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
52059 /* If this bit set to 0, then it indicates rx flow. */
52060 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
52061 /* If this bit is set to 1, then it indicates tx flow. */
52062 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
52063 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
52064 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
52065 /* Global Cfg type */
52067 /* Offset of the type */
52069 /* Size of the data to set in bytes */
52072 uint8_t unused0[6];
52075 /* Mask of data to set, 0 indicates no mask */
52079 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
52080 struct hwrm_tf_global_cfg_set_output {
52081 /* The specific error status for the command. */
52082 uint16_t error_code;
52083 /* The HWRM command request type. */
52085 /* The sequence ID from the original command. */
52087 /* The length of the response data in number of bytes. */
52090 uint8_t unused0[7];
52092 * This field is used in Output records to indicate that the
52093 * output is completely written to RAM. This field should be
52094 * read as '1' to indicate that the output has been
52095 * completely written. When writing a command completion or
52096 * response to an internal processor, the order of writes has
52097 * to be such that this field is written last.
52102 /**************************
52103 * hwrm_tf_global_cfg_get *
52104 **************************/
52107 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
52108 struct hwrm_tf_global_cfg_get_input {
52109 /* The HWRM command request type. */
52112 * The completion ring to send the completion event on. This should
52113 * be the NQ ID returned from the `nq_alloc` HWRM command.
52115 uint16_t cmpl_ring;
52117 * The sequence ID is used by the driver for tracking multiple
52118 * commands. This ID is treated as opaque data by the firmware and
52119 * the value is returned in the `hwrm_resp_hdr` upon completion.
52123 * The target ID of the command:
52124 * * 0x0-0xFFF8 - The function ID
52125 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52126 * * 0xFFFD - Reserved for user-space HWRM interface
52129 uint16_t target_id;
52131 * A physical address pointer pointing to a host buffer that the
52132 * command's response data will be written. This can be either a host
52133 * physical address (HPA) or a guest physical address (GPA) and must
52134 * point to a physically contiguous block of memory.
52136 uint64_t resp_addr;
52137 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
52138 uint32_t fw_session_id;
52139 /* Control flags. */
52141 /* Indicates the flow direction. */
52142 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
52143 /* If this bit set to 0, then it indicates rx flow. */
52144 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
52145 /* If this bit is set to 1, then it indicates tx flow. */
52146 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
52147 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
52148 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
52149 /* Global Cfg type */
52151 /* Offset of the type */
52153 /* Size of the data to set in bytes */
52156 uint8_t unused0[6];
52159 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
52160 struct hwrm_tf_global_cfg_get_output {
52161 /* The specific error status for the command. */
52162 uint16_t error_code;
52163 /* The HWRM command request type. */
52165 /* The sequence ID from the original command. */
52167 /* The length of the response data in number of bytes. */
52169 /* Size of the data read in bytes */
52172 uint8_t unused0[6];
52177 /**********************
52178 * hwrm_tf_if_tbl_get *
52179 **********************/
52182 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
52183 struct hwrm_tf_if_tbl_get_input {
52184 /* The HWRM command request type. */
52187 * The completion ring to send the completion event on. This should
52188 * be the NQ ID returned from the `nq_alloc` HWRM command.
52190 uint16_t cmpl_ring;
52192 * The sequence ID is used by the driver for tracking multiple
52193 * commands. This ID is treated as opaque data by the firmware and
52194 * the value is returned in the `hwrm_resp_hdr` upon completion.
52198 * The target ID of the command:
52199 * * 0x0-0xFFF8 - The function ID
52200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52201 * * 0xFFFD - Reserved for user-space HWRM interface
52204 uint16_t target_id;
52206 * A physical address pointer pointing to a host buffer that the
52207 * command's response data will be written. This can be either a host
52208 * physical address (HPA) or a guest physical address (GPA) and must
52209 * point to a physically contiguous block of memory.
52211 uint64_t resp_addr;
52212 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
52213 uint32_t fw_session_id;
52214 /* Control flags. */
52216 /* Indicates the flow direction. */
52217 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
52218 /* If this bit set to 0, then it indicates rx flow. */
52219 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
52220 /* If this bit is set to 1, then it indicates tx flow. */
52221 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
52222 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
52223 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
52224 /* Size of the data to set. */
52227 * Type of the resource, defined globally in the
52228 * hwrm_tf_resc_type enum.
52231 /* Index of the type to retrieve. */
52235 /* hwrm_tf_if_tbl_get_output (size:1216b/152B) */
52236 struct hwrm_tf_if_tbl_get_output {
52237 /* The specific error status for the command. */
52238 uint16_t error_code;
52239 /* The HWRM command request type. */
52241 /* The sequence ID from the original command. */
52243 /* The length of the response data in number of bytes. */
52245 /* Response code. */
52246 uint32_t resp_code;
52247 /* Response size. */
52251 /* Response data. */
52254 uint8_t unused1[7];
52256 * This field is used in Output records to indicate that the output
52257 * is completely written to RAM. This field should be read as '1'
52258 * to indicate that the output has been completely written.
52259 * When writing a command completion or response to an internal
52260 * processor, the order of writes has to be such that this field
52266 /***************************
52267 * hwrm_tf_if_tbl_type_set *
52268 ***************************/
52271 /* hwrm_tf_if_tbl_set_input (size:1024b/128B) */
52272 struct hwrm_tf_if_tbl_set_input {
52273 /* The HWRM command request type. */
52276 * The completion ring to send the completion event on. This should
52277 * be the NQ ID returned from the `nq_alloc` HWRM command.
52279 uint16_t cmpl_ring;
52281 * The sequence ID is used by the driver for tracking multiple
52282 * commands. This ID is treated as opaque data by the firmware and
52283 * the value is returned in the `hwrm_resp_hdr` upon completion.
52287 * The target ID of the command:
52288 * * 0x0-0xFFF8 - The function ID
52289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52290 * * 0xFFFD - Reserved for user-space HWRM interface
52293 uint16_t target_id;
52295 * A physical address pointer pointing to a host buffer that the
52296 * command's response data will be written. This can be either a host
52297 * physical address (HPA) or a guest physical address (GPA) and must
52298 * point to a physically contiguous block of memory.
52300 uint64_t resp_addr;
52301 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
52302 uint32_t fw_session_id;
52303 /* Control flags. */
52305 /* Indicates the flow direction. */
52306 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
52307 /* If this bit set to 0, then it indicates rx flow. */
52308 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
52309 /* If this bit is set to 1, then it indicates tx flow. */
52310 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
52311 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
52312 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
52314 uint8_t unused0[2];
52316 * Type of the resource, defined globally in the
52317 * hwrm_tf_resc_type enum.
52320 /* Index of the type to set. */
52322 /* Size of the data to set. */
52325 uint8_t unused1[6];
52326 /* Data to be set. */
52330 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
52331 struct hwrm_tf_if_tbl_set_output {
52332 /* The specific error status for the command. */
52333 uint16_t error_code;
52334 /* The HWRM command request type. */
52336 /* The sequence ID from the original command. */
52338 /* The length of the response data in number of bytes. */
52341 uint8_t unused0[7];
52343 * This field is used in Output records to indicate that the output
52344 * is completely written to RAM. This field should be read as '1'
52345 * to indicate that the output has been completely written.
52346 * When writing a command completion or response to an internal
52347 * processor, the order of writes has to be such that this field
52353 /*****************************
52354 * hwrm_tf_tbl_type_bulk_get *
52355 *****************************/
52358 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
52359 struct hwrm_tf_tbl_type_bulk_get_input {
52360 /* The HWRM command request type. */
52363 * The completion ring to send the completion event on. This should
52364 * be the NQ ID returned from the `nq_alloc` HWRM command.
52366 uint16_t cmpl_ring;
52368 * The sequence ID is used by the driver for tracking multiple
52369 * commands. This ID is treated as opaque data by the firmware and
52370 * the value is returned in the `hwrm_resp_hdr` upon completion.
52374 * The target ID of the command:
52375 * * 0x0-0xFFF8 - The function ID
52376 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52377 * * 0xFFFD - Reserved for user-space HWRM interface
52380 uint16_t target_id;
52382 * A physical address pointer pointing to a host buffer that the
52383 * command's response data will be written. This can be either a host
52384 * physical address (HPA) or a guest physical address (GPA) and must
52385 * point to a physically contiguous block of memory.
52387 uint64_t resp_addr;
52388 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
52389 uint32_t fw_session_id;
52390 /* Control flags. */
52392 /* Indicates the flow direction. */
52393 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
52395 /* If this bit set to 0, then it indicates rx flow. */
52396 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
52398 /* If this bit is set to 1, then it indicates tx flow. */
52399 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
52401 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
52402 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
52404 * When set use the special access register access to clear
52405 * the table entries on read.
52407 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
52410 uint8_t unused0[2];
52412 * Type of the resource, defined globally in the
52413 * hwrm_tf_resc_type enum.
52416 /* Starting index of the type to retrieve. */
52417 uint32_t start_index;
52418 /* Number of entries to retrieve. */
52419 uint32_t num_entries;
52420 /* Number of entries to retrieve. */
52422 /* Host memory where data will be stored. */
52423 uint64_t host_addr;
52426 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
52427 struct hwrm_tf_tbl_type_bulk_get_output {
52428 /* The specific error status for the command. */
52429 uint16_t error_code;
52430 /* The HWRM command request type. */
52432 /* The sequence ID from the original command. */
52434 /* The length of the response data in number of bytes. */
52436 /* Response code. */
52437 uint32_t resp_code;
52438 /* Response size. */
52443 * This field is used in Output records to indicate that the output
52444 * is completely written to RAM. This field should be read as '1'
52445 * to indicate that the output has been completely written.
52446 * When writing a command completion or response to an internal
52447 * processor, the order of writes has to be such that this field
52453 /******************************
52454 * hwrm_tunnel_dst_port_query *
52455 ******************************/
52458 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
52459 struct hwrm_tunnel_dst_port_query_input {
52460 /* The HWRM command request type. */
52463 * The completion ring to send the completion event on. This should
52464 * be the NQ ID returned from the `nq_alloc` HWRM command.
52466 uint16_t cmpl_ring;
52468 * The sequence ID is used by the driver for tracking multiple
52469 * commands. This ID is treated as opaque data by the firmware and
52470 * the value is returned in the `hwrm_resp_hdr` upon completion.
52474 * The target ID of the command:
52475 * * 0x0-0xFFF8 - The function ID
52476 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52477 * * 0xFFFD - Reserved for user-space HWRM interface
52480 uint16_t target_id;
52482 * A physical address pointer pointing to a host buffer that the
52483 * command's response data will be written. This can be either a host
52484 * physical address (HPA) or a guest physical address (GPA) and must
52485 * point to a physically contiguous block of memory.
52487 uint64_t resp_addr;
52489 uint8_t tunnel_type;
52490 /* Virtual eXtensible Local Area Network (VXLAN) */
52491 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
52493 /* Generic Network Virtualization Encapsulation (Geneve) */
52494 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
52496 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
52497 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
52499 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
52500 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
52502 /* Use fixed layer 2 ether type of 0xFFFF */
52503 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
52505 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
52506 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
52508 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
52509 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
52510 uint8_t unused_0[7];
52513 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
52514 struct hwrm_tunnel_dst_port_query_output {
52515 /* The specific error status for the command. */
52516 uint16_t error_code;
52517 /* The HWRM command request type. */
52519 /* The sequence ID from the original command. */
52521 /* The length of the response data in number of bytes. */
52524 * This field represents the identifier of L4 destination port
52525 * used for the given tunnel type. This field is valid for
52526 * specific tunnel types that use layer 4 (e.g. UDP)
52527 * transports for tunneling.
52529 uint16_t tunnel_dst_port_id;
52531 * This field represents the value of L4 destination port
52532 * identified by tunnel_dst_port_id. This field is valid for
52533 * specific tunnel types that use layer 4 (e.g. UDP)
52534 * transports for tunneling.
52535 * This field is in network byte order.
52537 * A value of 0 means that the destination port is not
52540 uint16_t tunnel_dst_port_val;
52541 uint8_t unused_0[3];
52543 * This field is used in Output records to indicate that the output
52544 * is completely written to RAM. This field should be read as '1'
52545 * to indicate that the output has been completely written.
52546 * When writing a command completion or response to an internal processor,
52547 * the order of writes has to be such that this field is written last.
52552 /******************************
52553 * hwrm_tunnel_dst_port_alloc *
52554 ******************************/
52557 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
52558 struct hwrm_tunnel_dst_port_alloc_input {
52559 /* The HWRM command request type. */
52562 * The completion ring to send the completion event on. This should
52563 * be the NQ ID returned from the `nq_alloc` HWRM command.
52565 uint16_t cmpl_ring;
52567 * The sequence ID is used by the driver for tracking multiple
52568 * commands. This ID is treated as opaque data by the firmware and
52569 * the value is returned in the `hwrm_resp_hdr` upon completion.
52573 * The target ID of the command:
52574 * * 0x0-0xFFF8 - The function ID
52575 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52576 * * 0xFFFD - Reserved for user-space HWRM interface
52579 uint16_t target_id;
52581 * A physical address pointer pointing to a host buffer that the
52582 * command's response data will be written. This can be either a host
52583 * physical address (HPA) or a guest physical address (GPA) and must
52584 * point to a physically contiguous block of memory.
52586 uint64_t resp_addr;
52588 uint8_t tunnel_type;
52589 /* Virtual eXtensible Local Area Network (VXLAN) */
52590 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
52592 /* Generic Network Virtualization Encapsulation (Geneve) */
52593 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
52595 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
52596 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
52598 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
52599 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
52601 /* Use fixed layer 2 ether type of 0xFFFF */
52602 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
52604 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
52605 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
52607 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
52608 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
52611 * This field represents the value of L4 destination port used
52612 * for the given tunnel type. This field is valid for
52613 * specific tunnel types that use layer 4 (e.g. UDP)
52614 * transports for tunneling.
52616 * This field is in network byte order.
52618 * A value of 0 shall fail the command.
52620 uint16_t tunnel_dst_port_val;
52621 uint8_t unused_1[4];
52624 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
52625 struct hwrm_tunnel_dst_port_alloc_output {
52626 /* The specific error status for the command. */
52627 uint16_t error_code;
52628 /* The HWRM command request type. */
52630 /* The sequence ID from the original command. */
52632 /* The length of the response data in number of bytes. */
52635 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
52636 * types that has l4 destination port parameters.
52638 uint16_t tunnel_dst_port_id;
52639 uint8_t unused_0[5];
52641 * This field is used in Output records to indicate that the output
52642 * is completely written to RAM. This field should be read as '1'
52643 * to indicate that the output has been completely written.
52644 * When writing a command completion or response to an internal processor,
52645 * the order of writes has to be such that this field is written last.
52650 /*****************************
52651 * hwrm_tunnel_dst_port_free *
52652 *****************************/
52655 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
52656 struct hwrm_tunnel_dst_port_free_input {
52657 /* The HWRM command request type. */
52660 * The completion ring to send the completion event on. This should
52661 * be the NQ ID returned from the `nq_alloc` HWRM command.
52663 uint16_t cmpl_ring;
52665 * The sequence ID is used by the driver for tracking multiple
52666 * commands. This ID is treated as opaque data by the firmware and
52667 * the value is returned in the `hwrm_resp_hdr` upon completion.
52671 * The target ID of the command:
52672 * * 0x0-0xFFF8 - The function ID
52673 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52674 * * 0xFFFD - Reserved for user-space HWRM interface
52677 uint16_t target_id;
52679 * A physical address pointer pointing to a host buffer that the
52680 * command's response data will be written. This can be either a host
52681 * physical address (HPA) or a guest physical address (GPA) and must
52682 * point to a physically contiguous block of memory.
52684 uint64_t resp_addr;
52686 uint8_t tunnel_type;
52687 /* Virtual eXtensible Local Area Network (VXLAN) */
52688 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
52690 /* Generic Network Virtualization Encapsulation (Geneve) */
52691 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
52693 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
52694 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
52696 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
52697 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
52699 /* Use fixed layer 2 ether type of 0xFFFF */
52700 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
52702 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
52703 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
52705 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
52706 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
52709 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
52710 * types that has l4 destination port parameters.
52712 uint16_t tunnel_dst_port_id;
52713 uint8_t unused_1[4];
52716 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
52717 struct hwrm_tunnel_dst_port_free_output {
52718 /* The specific error status for the command. */
52719 uint16_t error_code;
52720 /* The HWRM command request type. */
52722 /* The sequence ID from the original command. */
52724 /* The length of the response data in number of bytes. */
52726 uint8_t unused_1[7];
52728 * This field is used in Output records to indicate that the output
52729 * is completely written to RAM. This field should be read as '1'
52730 * to indicate that the output has been completely written.
52731 * When writing a command completion or response to an internal processor,
52732 * the order of writes has to be such that this field is written last.
52737 /* Periodic statistics context DMA to host. */
52738 /* ctx_hw_stats (size:1280b/160B) */
52739 struct ctx_hw_stats {
52740 /* Number of received unicast packets */
52741 uint64_t rx_ucast_pkts;
52742 /* Number of received multicast packets */
52743 uint64_t rx_mcast_pkts;
52744 /* Number of received broadcast packets */
52745 uint64_t rx_bcast_pkts;
52746 /* Number of discarded packets on receive path */
52747 uint64_t rx_discard_pkts;
52748 /* Number of packets on receive path with error */
52749 uint64_t rx_error_pkts;
52750 /* Number of received bytes for unicast traffic */
52751 uint64_t rx_ucast_bytes;
52752 /* Number of received bytes for multicast traffic */
52753 uint64_t rx_mcast_bytes;
52754 /* Number of received bytes for broadcast traffic */
52755 uint64_t rx_bcast_bytes;
52756 /* Number of transmitted unicast packets */
52757 uint64_t tx_ucast_pkts;
52758 /* Number of transmitted multicast packets */
52759 uint64_t tx_mcast_pkts;
52760 /* Number of transmitted broadcast packets */
52761 uint64_t tx_bcast_pkts;
52762 /* Number of packets on transmit path with error */
52763 uint64_t tx_error_pkts;
52764 /* Number of discarded packets on transmit path */
52765 uint64_t tx_discard_pkts;
52766 /* Number of transmitted bytes for unicast traffic */
52767 uint64_t tx_ucast_bytes;
52768 /* Number of transmitted bytes for multicast traffic */
52769 uint64_t tx_mcast_bytes;
52770 /* Number of transmitted bytes for broadcast traffic */
52771 uint64_t tx_bcast_bytes;
52772 /* Number of TPA packets */
52774 /* Number of TPA bytes */
52775 uint64_t tpa_bytes;
52776 /* Number of TPA events */
52777 uint64_t tpa_events;
52778 /* Number of TPA aborts */
52779 uint64_t tpa_aborts;
52783 * Extended periodic statistics context DMA to host. On cards that
52784 * support TPA v2, additional TPA related stats exist and can be retrieved
52785 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
52787 /* ctx_hw_stats_ext (size:1408b/176B) */
52788 struct ctx_hw_stats_ext {
52789 /* Number of received unicast packets */
52790 uint64_t rx_ucast_pkts;
52791 /* Number of received multicast packets */
52792 uint64_t rx_mcast_pkts;
52793 /* Number of received broadcast packets */
52794 uint64_t rx_bcast_pkts;
52795 /* Number of discarded packets on receive path */
52796 uint64_t rx_discard_pkts;
52797 /* Number of packets on receive path with error */
52798 uint64_t rx_error_pkts;
52799 /* Number of received bytes for unicast traffic */
52800 uint64_t rx_ucast_bytes;
52801 /* Number of received bytes for multicast traffic */
52802 uint64_t rx_mcast_bytes;
52803 /* Number of received bytes for broadcast traffic */
52804 uint64_t rx_bcast_bytes;
52805 /* Number of transmitted unicast packets */
52806 uint64_t tx_ucast_pkts;
52807 /* Number of transmitted multicast packets */
52808 uint64_t tx_mcast_pkts;
52809 /* Number of transmitted broadcast packets */
52810 uint64_t tx_bcast_pkts;
52811 /* Number of packets on transmit path with error */
52812 uint64_t tx_error_pkts;
52813 /* Number of discarded packets on transmit path */
52814 uint64_t tx_discard_pkts;
52815 /* Number of transmitted bytes for unicast traffic */
52816 uint64_t tx_ucast_bytes;
52817 /* Number of transmitted bytes for multicast traffic */
52818 uint64_t tx_mcast_bytes;
52819 /* Number of transmitted bytes for broadcast traffic */
52820 uint64_t tx_bcast_bytes;
52821 /* Number of TPA eligible packets */
52822 uint64_t rx_tpa_eligible_pkt;
52823 /* Number of TPA eligible bytes */
52824 uint64_t rx_tpa_eligible_bytes;
52825 /* Number of TPA packets */
52826 uint64_t rx_tpa_pkt;
52827 /* Number of TPA bytes */
52828 uint64_t rx_tpa_bytes;
52829 /* Number of TPA errors */
52830 uint64_t rx_tpa_errors;
52831 /* Number of TPA events */
52832 uint64_t rx_tpa_events;
52835 /* Periodic Engine statistics context DMA to host. */
52836 /* ctx_eng_stats (size:512b/64B) */
52837 struct ctx_eng_stats {
52839 * Count of data bytes into the Engine.
52840 * This includes any user supplied prefix,
52841 * but does not include any predefined
52844 uint64_t eng_bytes_in;
52845 /* Count of data bytes out of the Engine. */
52846 uint64_t eng_bytes_out;
52848 * Count, in 4-byte (dword) units, of bytes
52849 * that are input as auxiliary data.
52850 * This includes the aux_cmd data.
52852 uint64_t aux_bytes_in;
52854 * Count, in 4-byte (dword) units, of bytes
52855 * that are output as auxiliary data.
52856 * This count is the buffer space for aux_data
52857 * output provided in the RQE, not the actual
52860 uint64_t aux_bytes_out;
52861 /* Count of number of commands executed. */
52864 * Count of number of error commands.
52865 * These are the commands with a
52866 * non-zero status value.
52868 uint64_t error_commands;
52870 * Compression/Encryption Engine usage,
52871 * the unit is count of clock cycles
52873 uint64_t cce_engine_usage;
52875 * De-Compression/De-cryption Engine usage,
52876 * the unit is count of clock cycles
52878 uint64_t cdd_engine_usage;
52881 /***********************
52882 * hwrm_stat_ctx_alloc *
52883 ***********************/
52886 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
52887 struct hwrm_stat_ctx_alloc_input {
52888 /* The HWRM command request type. */
52891 * The completion ring to send the completion event on. This should
52892 * be the NQ ID returned from the `nq_alloc` HWRM command.
52894 uint16_t cmpl_ring;
52896 * The sequence ID is used by the driver for tracking multiple
52897 * commands. This ID is treated as opaque data by the firmware and
52898 * the value is returned in the `hwrm_resp_hdr` upon completion.
52902 * The target ID of the command:
52903 * * 0x0-0xFFF8 - The function ID
52904 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52905 * * 0xFFFD - Reserved for user-space HWRM interface
52908 uint16_t target_id;
52910 * A physical address pointer pointing to a host buffer that the
52911 * command's response data will be written. This can be either a host
52912 * physical address (HPA) or a guest physical address (GPA) and must
52913 * point to a physically contiguous block of memory.
52915 uint64_t resp_addr;
52917 * This is the address for statistic block.
52918 * > For new versions of the chip, this address should be 128B
52921 uint64_t stats_dma_addr;
52923 * The statistic block update period in ms.
52924 * e.g. 250ms, 500ms, 750ms, 1000ms.
52925 * If update_period_ms is 0, then the stats update
52926 * shall be never done and the DMA address shall not be used.
52927 * In this case, the stat block can only be read by
52928 * hwrm_stat_ctx_query command.
52929 * On Ethernet/L2 based devices:
52930 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
52931 * ctx_hw_stats_ext is used for DMA,
52933 * ctx_hw_stats is used for DMA.
52935 uint32_t update_period_ms;
52937 * This field is used to specify statistics context specific
52938 * configuration flags.
52940 uint8_t stat_ctx_flags;
52942 * When this bit is set to '1', the statistics context shall be
52943 * allocated for RoCE traffic only. In this case, traffic other
52944 * than offloaded RoCE traffic shall not be included in this
52945 * statistic context.
52946 * When this bit is set to '0', the statistics context shall be
52947 * used for network traffic or engine traffic.
52949 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
52952 * This is the size of the structure (ctx_hw_stats or
52953 * ctx_hw_stats_ext) that the driver has allocated to be used
52954 * for the periodic DMA updates.
52956 uint16_t stats_dma_length;
52959 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
52960 struct hwrm_stat_ctx_alloc_output {
52961 /* The specific error status for the command. */
52962 uint16_t error_code;
52963 /* The HWRM command request type. */
52965 /* The sequence ID from the original command. */
52967 /* The length of the response data in number of bytes. */
52969 /* This is the statistics context ID value. */
52970 uint32_t stat_ctx_id;
52971 uint8_t unused_0[3];
52973 * This field is used in Output records to indicate that the output
52974 * is completely written to RAM. This field should be read as '1'
52975 * to indicate that the output has been completely written.
52976 * When writing a command completion or response to an internal processor,
52977 * the order of writes has to be such that this field is written last.
52982 /**********************
52983 * hwrm_stat_ctx_free *
52984 **********************/
52987 /* hwrm_stat_ctx_free_input (size:192b/24B) */
52988 struct hwrm_stat_ctx_free_input {
52989 /* The HWRM command request type. */
52992 * The completion ring to send the completion event on. This should
52993 * be the NQ ID returned from the `nq_alloc` HWRM command.
52995 uint16_t cmpl_ring;
52997 * The sequence ID is used by the driver for tracking multiple
52998 * commands. This ID is treated as opaque data by the firmware and
52999 * the value is returned in the `hwrm_resp_hdr` upon completion.
53003 * The target ID of the command:
53004 * * 0x0-0xFFF8 - The function ID
53005 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53006 * * 0xFFFD - Reserved for user-space HWRM interface
53009 uint16_t target_id;
53011 * A physical address pointer pointing to a host buffer that the
53012 * command's response data will be written. This can be either a host
53013 * physical address (HPA) or a guest physical address (GPA) and must
53014 * point to a physically contiguous block of memory.
53016 uint64_t resp_addr;
53017 /* ID of the statistics context that is being queried. */
53018 uint32_t stat_ctx_id;
53019 uint8_t unused_0[4];
53022 /* hwrm_stat_ctx_free_output (size:128b/16B) */
53023 struct hwrm_stat_ctx_free_output {
53024 /* The specific error status for the command. */
53025 uint16_t error_code;
53026 /* The HWRM command request type. */
53028 /* The sequence ID from the original command. */
53030 /* The length of the response data in number of bytes. */
53032 /* This is the statistics context ID value. */
53033 uint32_t stat_ctx_id;
53034 uint8_t unused_0[3];
53036 * This field is used in Output records to indicate that the output
53037 * is completely written to RAM. This field should be read as '1'
53038 * to indicate that the output has been completely written.
53039 * When writing a command completion or response to an internal processor,
53040 * the order of writes has to be such that this field is written last.
53045 /***********************
53046 * hwrm_stat_ctx_query *
53047 ***********************/
53050 /* hwrm_stat_ctx_query_input (size:192b/24B) */
53051 struct hwrm_stat_ctx_query_input {
53052 /* The HWRM command request type. */
53055 * The completion ring to send the completion event on. This should
53056 * be the NQ ID returned from the `nq_alloc` HWRM command.
53058 uint16_t cmpl_ring;
53060 * The sequence ID is used by the driver for tracking multiple
53061 * commands. This ID is treated as opaque data by the firmware and
53062 * the value is returned in the `hwrm_resp_hdr` upon completion.
53066 * The target ID of the command:
53067 * * 0x0-0xFFF8 - The function ID
53068 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53069 * * 0xFFFD - Reserved for user-space HWRM interface
53072 uint16_t target_id;
53074 * A physical address pointer pointing to a host buffer that the
53075 * command's response data will be written. This can be either a host
53076 * physical address (HPA) or a guest physical address (GPA) and must
53077 * point to a physically contiguous block of memory.
53079 uint64_t resp_addr;
53080 /* ID of the statistics context that is being queried. */
53081 uint32_t stat_ctx_id;
53084 * This bit is set to 1 when request is for a counter mask,
53085 * representing the width of each of the stats counters, rather
53086 * than counters themselves.
53088 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
53089 uint8_t unused_0[3];
53092 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
53093 struct hwrm_stat_ctx_query_output {
53094 /* The specific error status for the command. */
53095 uint16_t error_code;
53096 /* The HWRM command request type. */
53098 /* The sequence ID from the original command. */
53100 /* The length of the response data in number of bytes. */
53102 /* Number of transmitted unicast packets */
53103 uint64_t tx_ucast_pkts;
53104 /* Number of transmitted multicast packets */
53105 uint64_t tx_mcast_pkts;
53106 /* Number of transmitted broadcast packets */
53107 uint64_t tx_bcast_pkts;
53108 /* Number of packets discarded in transmit path */
53109 uint64_t tx_discard_pkts;
53110 /* Number of packets in transmit path with error */
53111 uint64_t tx_error_pkts;
53112 /* Number of transmitted bytes for unicast traffic */
53113 uint64_t tx_ucast_bytes;
53114 /* Number of transmitted bytes for multicast traffic */
53115 uint64_t tx_mcast_bytes;
53116 /* Number of transmitted bytes for broadcast traffic */
53117 uint64_t tx_bcast_bytes;
53118 /* Number of received unicast packets */
53119 uint64_t rx_ucast_pkts;
53120 /* Number of received multicast packets */
53121 uint64_t rx_mcast_pkts;
53122 /* Number of received broadcast packets */
53123 uint64_t rx_bcast_pkts;
53124 /* Number of packets discarded in receive path */
53125 uint64_t rx_discard_pkts;
53126 /* Number of packets in receive path with errors */
53127 uint64_t rx_error_pkts;
53128 /* Number of received bytes for unicast traffic */
53129 uint64_t rx_ucast_bytes;
53130 /* Number of received bytes for multicast traffic */
53131 uint64_t rx_mcast_bytes;
53132 /* Number of received bytes for broadcast traffic */
53133 uint64_t rx_bcast_bytes;
53134 /* Number of aggregated unicast packets */
53135 uint64_t rx_agg_pkts;
53136 /* Number of aggregated unicast bytes */
53137 uint64_t rx_agg_bytes;
53138 /* Number of aggregation events */
53139 uint64_t rx_agg_events;
53140 /* Number of aborted aggregations */
53141 uint64_t rx_agg_aborts;
53142 uint8_t unused_0[7];
53144 * This field is used in Output records to indicate that the output
53145 * is completely written to RAM. This field should be read as '1'
53146 * to indicate that the output has been completely written.
53147 * When writing a command completion or response to an internal processor,
53148 * the order of writes has to be such that this field is written last.
53153 /***************************
53154 * hwrm_stat_ext_ctx_query *
53155 ***************************/
53158 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
53159 struct hwrm_stat_ext_ctx_query_input {
53160 /* The HWRM command request type. */
53163 * The completion ring to send the completion event on. This should
53164 * be the NQ ID returned from the `nq_alloc` HWRM command.
53166 uint16_t cmpl_ring;
53168 * The sequence ID is used by the driver for tracking multiple
53169 * commands. This ID is treated as opaque data by the firmware and
53170 * the value is returned in the `hwrm_resp_hdr` upon completion.
53174 * The target ID of the command:
53175 * * 0x0-0xFFF8 - The function ID
53176 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53177 * * 0xFFFD - Reserved for user-space HWRM interface
53180 uint16_t target_id;
53182 * A physical address pointer pointing to a host buffer that the
53183 * command's response data will be written. This can be either a host
53184 * physical address (HPA) or a guest physical address (GPA) and must
53185 * point to a physically contiguous block of memory.
53187 uint64_t resp_addr;
53188 /* ID of the extended statistics context that is being queried. */
53189 uint32_t stat_ctx_id;
53192 * This bit is set to 1 when request is for a counter mask,
53193 * representing the width of each of the stats counters, rather
53194 * than counters themselves.
53196 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
53198 uint8_t unused_0[3];
53201 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
53202 struct hwrm_stat_ext_ctx_query_output {
53203 /* The specific error status for the command. */
53204 uint16_t error_code;
53205 /* The HWRM command request type. */
53207 /* The sequence ID from the original command. */
53209 /* The length of the response data in number of bytes. */
53211 /* Number of received unicast packets */
53212 uint64_t rx_ucast_pkts;
53213 /* Number of received multicast packets */
53214 uint64_t rx_mcast_pkts;
53215 /* Number of received broadcast packets */
53216 uint64_t rx_bcast_pkts;
53217 /* Number of discarded packets on receive path */
53218 uint64_t rx_discard_pkts;
53219 /* Number of packets on receive path with error */
53220 uint64_t rx_error_pkts;
53221 /* Number of received bytes for unicast traffic */
53222 uint64_t rx_ucast_bytes;
53223 /* Number of received bytes for multicast traffic */
53224 uint64_t rx_mcast_bytes;
53225 /* Number of received bytes for broadcast traffic */
53226 uint64_t rx_bcast_bytes;
53227 /* Number of transmitted unicast packets */
53228 uint64_t tx_ucast_pkts;
53229 /* Number of transmitted multicast packets */
53230 uint64_t tx_mcast_pkts;
53231 /* Number of transmitted broadcast packets */
53232 uint64_t tx_bcast_pkts;
53233 /* Number of packets on transmit path with error */
53234 uint64_t tx_error_pkts;
53235 /* Number of discarded packets on transmit path */
53236 uint64_t tx_discard_pkts;
53237 /* Number of transmitted bytes for unicast traffic */
53238 uint64_t tx_ucast_bytes;
53239 /* Number of transmitted bytes for multicast traffic */
53240 uint64_t tx_mcast_bytes;
53241 /* Number of transmitted bytes for broadcast traffic */
53242 uint64_t tx_bcast_bytes;
53243 /* Number of TPA eligible packets */
53244 uint64_t rx_tpa_eligible_pkt;
53245 /* Number of TPA eligible bytes */
53246 uint64_t rx_tpa_eligible_bytes;
53247 /* Number of TPA packets */
53248 uint64_t rx_tpa_pkt;
53249 /* Number of TPA bytes */
53250 uint64_t rx_tpa_bytes;
53251 /* Number of TPA errors */
53252 uint64_t rx_tpa_errors;
53253 /* Number of TPA events */
53254 uint64_t rx_tpa_events;
53255 uint8_t unused_0[7];
53257 * This field is used in Output records to indicate that the output
53258 * is completely written to RAM. This field should be read as '1'
53259 * to indicate that the output has been completely written.
53260 * When writing a command completion or response to an internal processor,
53261 * the order of writes has to be such that this field is written last.
53266 /***************************
53267 * hwrm_stat_ctx_eng_query *
53268 ***************************/
53271 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
53272 struct hwrm_stat_ctx_eng_query_input {
53273 /* The HWRM command request type. */
53276 * The completion ring to send the completion event on. This should
53277 * be the NQ ID returned from the `nq_alloc` HWRM command.
53279 uint16_t cmpl_ring;
53281 * The sequence ID is used by the driver for tracking multiple
53282 * commands. This ID is treated as opaque data by the firmware and
53283 * the value is returned in the `hwrm_resp_hdr` upon completion.
53287 * The target ID of the command:
53288 * * 0x0-0xFFF8 - The function ID
53289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53290 * * 0xFFFD - Reserved for user-space HWRM interface
53293 uint16_t target_id;
53295 * A physical address pointer pointing to a host buffer that the
53296 * command's response data will be written. This can be either a host
53297 * physical address (HPA) or a guest physical address (GPA) and must
53298 * point to a physically contiguous block of memory.
53300 uint64_t resp_addr;
53301 /* ID of the statistics context that is being queried. */
53302 uint32_t stat_ctx_id;
53303 uint8_t unused_0[4];
53306 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
53307 struct hwrm_stat_ctx_eng_query_output {
53308 /* The specific error status for the command. */
53309 uint16_t error_code;
53310 /* The HWRM command request type. */
53312 /* The sequence ID from the original command. */
53314 /* The length of the response data in number of bytes. */
53317 * Count of data bytes into the Engine.
53318 * This includes any user supplied prefix,
53319 * but does not include any predefined
53322 uint64_t eng_bytes_in;
53323 /* Count of data bytes out of the Engine. */
53324 uint64_t eng_bytes_out;
53326 * Count, in 4-byte (dword) units, of bytes
53327 * that are input as auxiliary data.
53328 * This includes the aux_cmd data.
53330 uint64_t aux_bytes_in;
53332 * Count, in 4-byte (dword) units, of bytes
53333 * that are output as auxiliary data.
53334 * This count is the buffer space for aux_data
53335 * output provided in the RQE, not the actual
53338 uint64_t aux_bytes_out;
53339 /* Count of number of commands executed. */
53342 * Count of number of error commands.
53343 * These are the commands with a
53344 * non-zero status value.
53346 uint64_t error_commands;
53348 * Compression/Encryption Engine usage,
53349 * the unit is count of clock cycles
53351 uint64_t cce_engine_usage;
53353 * De-Compression/De-cryption Engine usage,
53354 * the unit is count of clock cycles
53356 uint64_t cdd_engine_usage;
53357 uint8_t unused_0[7];
53359 * This field is used in Output records to indicate that the output
53360 * is completely written to RAM. This field should be read as '1'
53361 * to indicate that the output has been completely written.
53362 * When writing a command completion or response to an internal processor,
53363 * the order of writes has to be such that this field is written last.
53368 /***************************
53369 * hwrm_stat_ctx_clr_stats *
53370 ***************************/
53373 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
53374 struct hwrm_stat_ctx_clr_stats_input {
53375 /* The HWRM command request type. */
53378 * The completion ring to send the completion event on. This should
53379 * be the NQ ID returned from the `nq_alloc` HWRM command.
53381 uint16_t cmpl_ring;
53383 * The sequence ID is used by the driver for tracking multiple
53384 * commands. This ID is treated as opaque data by the firmware and
53385 * the value is returned in the `hwrm_resp_hdr` upon completion.
53389 * The target ID of the command:
53390 * * 0x0-0xFFF8 - The function ID
53391 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53392 * * 0xFFFD - Reserved for user-space HWRM interface
53395 uint16_t target_id;
53397 * A physical address pointer pointing to a host buffer that the
53398 * command's response data will be written. This can be either a host
53399 * physical address (HPA) or a guest physical address (GPA) and must
53400 * point to a physically contiguous block of memory.
53402 uint64_t resp_addr;
53403 /* ID of the statistics context that is being queried. */
53404 uint32_t stat_ctx_id;
53405 uint8_t unused_0[4];
53408 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
53409 struct hwrm_stat_ctx_clr_stats_output {
53410 /* The specific error status for the command. */
53411 uint16_t error_code;
53412 /* The HWRM command request type. */
53414 /* The sequence ID from the original command. */
53416 /* The length of the response data in number of bytes. */
53418 uint8_t unused_0[7];
53420 * This field is used in Output records to indicate that the output
53421 * is completely written to RAM. This field should be read as '1'
53422 * to indicate that the output has been completely written.
53423 * When writing a command completion or response to an internal processor,
53424 * the order of writes has to be such that this field is written last.
53429 /********************
53430 * hwrm_pcie_qstats *
53431 ********************/
53434 /* hwrm_pcie_qstats_input (size:256b/32B) */
53435 struct hwrm_pcie_qstats_input {
53436 /* The HWRM command request type. */
53439 * The completion ring to send the completion event on. This should
53440 * be the NQ ID returned from the `nq_alloc` HWRM command.
53442 uint16_t cmpl_ring;
53444 * The sequence ID is used by the driver for tracking multiple
53445 * commands. This ID is treated as opaque data by the firmware and
53446 * the value is returned in the `hwrm_resp_hdr` upon completion.
53450 * The target ID of the command:
53451 * * 0x0-0xFFF8 - The function ID
53452 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53453 * * 0xFFFD - Reserved for user-space HWRM interface
53456 uint16_t target_id;
53458 * A physical address pointer pointing to a host buffer that the
53459 * command's response data will be written. This can be either a host
53460 * physical address (HPA) or a guest physical address (GPA) and must
53461 * point to a physically contiguous block of memory.
53463 uint64_t resp_addr;
53465 * The size of PCIe statistics block in bytes.
53466 * Firmware will DMA the PCIe statistics to
53467 * the host with this field size in the response.
53469 uint16_t pcie_stat_size;
53470 uint8_t unused_0[6];
53472 * This is the host address where
53473 * PCIe statistics will be stored
53475 uint64_t pcie_stat_host_addr;
53478 /* hwrm_pcie_qstats_output (size:128b/16B) */
53479 struct hwrm_pcie_qstats_output {
53480 /* The specific error status for the command. */
53481 uint16_t error_code;
53482 /* The HWRM command request type. */
53484 /* The sequence ID from the original command. */
53486 /* The length of the response data in number of bytes. */
53488 /* The size of PCIe statistics block in bytes. */
53489 uint16_t pcie_stat_size;
53490 uint8_t unused_0[5];
53492 * This field is used in Output records to indicate that the output
53493 * is completely written to RAM. This field should be read as '1'
53494 * to indicate that the output has been completely written.
53495 * When writing a command completion or response to an internal processor,
53496 * the order of writes has to be such that this field is written last.
53501 /* PCIe Statistics Formats */
53502 /* pcie_ctx_hw_stats (size:768b/96B) */
53503 struct pcie_ctx_hw_stats {
53504 /* Number of physical layer receiver errors */
53505 uint64_t pcie_pl_signal_integrity;
53506 /* Number of DLLP CRC errors detected by Data Link Layer */
53507 uint64_t pcie_dl_signal_integrity;
53509 * Number of TLP LCRC and sequence number errors detected
53510 * by Data Link Layer
53512 uint64_t pcie_tl_signal_integrity;
53513 /* Number of times LTSSM entered Recovery state */
53514 uint64_t pcie_link_integrity;
53515 /* Report number of TLP bits that have been transmitted in Mbps */
53516 uint64_t pcie_tx_traffic_rate;
53517 /* Report number of TLP bits that have been received in Mbps */
53518 uint64_t pcie_rx_traffic_rate;
53519 /* Number of DLLP bytes that have been transmitted */
53520 uint64_t pcie_tx_dllp_statistics;
53521 /* Number of DLLP bytes that have been received */
53522 uint64_t pcie_rx_dllp_statistics;
53524 * Number of times spent in each phase of gen3
53527 uint64_t pcie_equalization_time;
53528 /* Records the last 16 transitions of the LTSSM */
53529 uint32_t pcie_ltssm_histogram[4];
53531 * Record the last 8 reasons on why LTSSM transitioned
53534 uint64_t pcie_recovery_histogram;
53537 /**********************
53538 * hwrm_exec_fwd_resp *
53539 **********************/
53542 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
53543 struct hwrm_exec_fwd_resp_input {
53544 /* The HWRM command request type. */
53547 * The completion ring to send the completion event on. This should
53548 * be the NQ ID returned from the `nq_alloc` HWRM command.
53550 uint16_t cmpl_ring;
53552 * The sequence ID is used by the driver for tracking multiple
53553 * commands. This ID is treated as opaque data by the firmware and
53554 * the value is returned in the `hwrm_resp_hdr` upon completion.
53558 * The target ID of the command:
53559 * * 0x0-0xFFF8 - The function ID
53560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53561 * * 0xFFFD - Reserved for user-space HWRM interface
53564 uint16_t target_id;
53566 * A physical address pointer pointing to a host buffer that the
53567 * command's response data will be written. This can be either a host
53568 * physical address (HPA) or a guest physical address (GPA) and must
53569 * point to a physically contiguous block of memory.
53571 uint64_t resp_addr;
53573 * This is an encapsulated request. This request should
53574 * be executed by the HWRM and the response should be
53575 * provided in the response buffer inside the encapsulated
53578 uint32_t encap_request[26];
53580 * This value indicates the target id of the response to
53581 * the encapsulated request.
53582 * 0x0 - 0xFFF8 - Used for function ids
53583 * 0xFFF8 - 0xFFFE - Reserved for internal processors
53586 uint16_t encap_resp_target_id;
53587 uint8_t unused_0[6];
53590 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
53591 struct hwrm_exec_fwd_resp_output {
53592 /* The specific error status for the command. */
53593 uint16_t error_code;
53594 /* The HWRM command request type. */
53596 /* The sequence ID from the original command. */
53598 /* The length of the response data in number of bytes. */
53600 uint8_t unused_0[7];
53602 * This field is used in Output records to indicate that the output
53603 * is completely written to RAM. This field should be read as '1'
53604 * to indicate that the output has been completely written.
53605 * When writing a command completion or response to an internal processor,
53606 * the order of writes has to be such that this field is written last.
53611 /************************
53612 * hwrm_reject_fwd_resp *
53613 ************************/
53616 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
53617 struct hwrm_reject_fwd_resp_input {
53618 /* The HWRM command request type. */
53621 * The completion ring to send the completion event on. This should
53622 * be the NQ ID returned from the `nq_alloc` HWRM command.
53624 uint16_t cmpl_ring;
53626 * The sequence ID is used by the driver for tracking multiple
53627 * commands. This ID is treated as opaque data by the firmware and
53628 * the value is returned in the `hwrm_resp_hdr` upon completion.
53632 * The target ID of the command:
53633 * * 0x0-0xFFF8 - The function ID
53634 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53635 * * 0xFFFD - Reserved for user-space HWRM interface
53638 uint16_t target_id;
53640 * A physical address pointer pointing to a host buffer that the
53641 * command's response data will be written. This can be either a host
53642 * physical address (HPA) or a guest physical address (GPA) and must
53643 * point to a physically contiguous block of memory.
53645 uint64_t resp_addr;
53647 * This is an encapsulated request. This request should
53648 * be rejected by the HWRM and the error response should be
53649 * provided in the response buffer inside the encapsulated
53652 uint32_t encap_request[26];
53654 * This value indicates the target id of the response to
53655 * the encapsulated request.
53656 * 0x0 - 0xFFF8 - Used for function ids
53657 * 0xFFF8 - 0xFFFE - Reserved for internal processors
53660 uint16_t encap_resp_target_id;
53661 uint8_t unused_0[6];
53664 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
53665 struct hwrm_reject_fwd_resp_output {
53666 /* The specific error status for the command. */
53667 uint16_t error_code;
53668 /* The HWRM command request type. */
53670 /* The sequence ID from the original command. */
53672 /* The length of the response data in number of bytes. */
53674 uint8_t unused_0[7];
53676 * This field is used in Output records to indicate that the output
53677 * is completely written to RAM. This field should be read as '1'
53678 * to indicate that the output has been completely written.
53679 * When writing a command completion or response to an internal processor,
53680 * the order of writes has to be such that this field is written last.
53690 /* hwrm_fwd_resp_input (size:1024b/128B) */
53691 struct hwrm_fwd_resp_input {
53692 /* The HWRM command request type. */
53695 * The completion ring to send the completion event on. This should
53696 * be the NQ ID returned from the `nq_alloc` HWRM command.
53698 uint16_t cmpl_ring;
53700 * The sequence ID is used by the driver for tracking multiple
53701 * commands. This ID is treated as opaque data by the firmware and
53702 * the value is returned in the `hwrm_resp_hdr` upon completion.
53706 * The target ID of the command:
53707 * * 0x0-0xFFF8 - The function ID
53708 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53709 * * 0xFFFD - Reserved for user-space HWRM interface
53712 uint16_t target_id;
53714 * A physical address pointer pointing to a host buffer that the
53715 * command's response data will be written. This can be either a host
53716 * physical address (HPA) or a guest physical address (GPA) and must
53717 * point to a physically contiguous block of memory.
53719 uint64_t resp_addr;
53721 * This value indicates the target id of the encapsulated
53723 * 0x0 - 0xFFF8 - Used for function ids
53724 * 0xFFF8 - 0xFFFE - Reserved for internal processors
53727 uint16_t encap_resp_target_id;
53729 * This value indicates the completion ring the encapsulated
53730 * response will be optionally completed on. If the value is
53731 * -1, then no CR completion shall be generated for the
53732 * encapsulated response. Any other value must be a
53733 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
53734 * is provided, then a CR completion shall be generated for
53735 * the encapsulated response.
53737 uint16_t encap_resp_cmpl_ring;
53738 /* This field indicates the length of encapsulated response. */
53739 uint16_t encap_resp_len;
53743 * This is the host address where the encapsulated response
53745 * This area must be 16B aligned and must be cleared to zero
53746 * before the original request is made.
53748 uint64_t encap_resp_addr;
53749 /* This is an encapsulated response. */
53750 uint32_t encap_resp[24];
53753 /* hwrm_fwd_resp_output (size:128b/16B) */
53754 struct hwrm_fwd_resp_output {
53755 /* The specific error status for the command. */
53756 uint16_t error_code;
53757 /* The HWRM command request type. */
53759 /* The sequence ID from the original command. */
53761 /* The length of the response data in number of bytes. */
53763 uint8_t unused_0[7];
53765 * This field is used in Output records to indicate that the output
53766 * is completely written to RAM. This field should be read as '1'
53767 * to indicate that the output has been completely written.
53768 * When writing a command completion or response to an internal processor,
53769 * the order of writes has to be such that this field is written last.
53774 /*****************************
53775 * hwrm_fwd_async_event_cmpl *
53776 *****************************/
53779 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
53780 struct hwrm_fwd_async_event_cmpl_input {
53781 /* The HWRM command request type. */
53784 * The completion ring to send the completion event on. This should
53785 * be the NQ ID returned from the `nq_alloc` HWRM command.
53787 uint16_t cmpl_ring;
53789 * The sequence ID is used by the driver for tracking multiple
53790 * commands. This ID is treated as opaque data by the firmware and
53791 * the value is returned in the `hwrm_resp_hdr` upon completion.
53795 * The target ID of the command:
53796 * * 0x0-0xFFF8 - The function ID
53797 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53798 * * 0xFFFD - Reserved for user-space HWRM interface
53801 uint16_t target_id;
53803 * A physical address pointer pointing to a host buffer that the
53804 * command's response data will be written. This can be either a host
53805 * physical address (HPA) or a guest physical address (GPA) and must
53806 * point to a physically contiguous block of memory.
53808 uint64_t resp_addr;
53810 * This value indicates the target id of the encapsulated
53811 * asynchronous event.
53812 * 0x0 - 0xFFF8 - Used for function ids
53813 * 0xFFF8 - 0xFFFE - Reserved for internal processors
53814 * 0xFFFF - Broadcast to all children VFs (only applicable when
53815 * a PF is the requester)
53817 uint16_t encap_async_event_target_id;
53818 uint8_t unused_0[6];
53819 /* This is an encapsulated asynchronous event completion. */
53820 uint32_t encap_async_event_cmpl[4];
53823 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
53824 struct hwrm_fwd_async_event_cmpl_output {
53825 /* The specific error status for the command. */
53826 uint16_t error_code;
53827 /* The HWRM command request type. */
53829 /* The sequence ID from the original command. */
53831 /* The length of the response data in number of bytes. */
53833 uint8_t unused_0[7];
53835 * This field is used in Output records to indicate that the output
53836 * is completely written to RAM. This field should be read as '1'
53837 * to indicate that the output has been completely written.
53838 * When writing a command completion or response to an internal processor,
53839 * the order of writes has to be such that this field is written last.
53844 /**************************
53845 * hwrm_nvm_raw_write_blk *
53846 **************************/
53849 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
53850 struct hwrm_nvm_raw_write_blk_input {
53851 /* The HWRM command request type. */
53854 * The completion ring to send the completion event on. This should
53855 * be the NQ ID returned from the `nq_alloc` HWRM command.
53857 uint16_t cmpl_ring;
53859 * The sequence ID is used by the driver for tracking multiple
53860 * commands. This ID is treated as opaque data by the firmware and
53861 * the value is returned in the `hwrm_resp_hdr` upon completion.
53865 * The target ID of the command:
53866 * * 0x0-0xFFF8 - The function ID
53867 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53868 * * 0xFFFD - Reserved for user-space HWRM interface
53871 uint16_t target_id;
53873 * A physical address pointer pointing to a host buffer that the
53874 * command's response data will be written. This can be either a host
53875 * physical address (HPA) or a guest physical address (GPA) and must
53876 * point to a physically contiguous block of memory.
53878 uint64_t resp_addr;
53880 * 64-bit Host Source Address.
53881 * This is the location of the source data to be written.
53883 uint64_t host_src_addr;
53885 * 32-bit Destination Address.
53886 * This is the NVRAM byte-offset where the source data will be written to.
53888 uint32_t dest_addr;
53889 /* Length of data to be written, in bytes. */
53893 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
53894 struct hwrm_nvm_raw_write_blk_output {
53895 /* The specific error status for the command. */
53896 uint16_t error_code;
53897 /* The HWRM command request type. */
53899 /* The sequence ID from the original command. */
53901 /* The length of the response data in number of bytes. */
53903 uint8_t unused_0[7];
53905 * This field is used in Output records to indicate that the output
53906 * is completely written to RAM. This field should be read as '1'
53907 * to indicate that the output has been completely written.
53908 * When writing a command completion or response to an internal processor,
53909 * the order of writes has to be such that this field is written last.
53919 /* hwrm_nvm_read_input (size:320b/40B) */
53920 struct hwrm_nvm_read_input {
53921 /* The HWRM command request type. */
53924 * The completion ring to send the completion event on. This should
53925 * be the NQ ID returned from the `nq_alloc` HWRM command.
53927 uint16_t cmpl_ring;
53929 * The sequence ID is used by the driver for tracking multiple
53930 * commands. This ID is treated as opaque data by the firmware and
53931 * the value is returned in the `hwrm_resp_hdr` upon completion.
53935 * The target ID of the command:
53936 * * 0x0-0xFFF8 - The function ID
53937 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53938 * * 0xFFFD - Reserved for user-space HWRM interface
53941 uint16_t target_id;
53943 * A physical address pointer pointing to a host buffer that the
53944 * command's response data will be written. This can be either a host
53945 * physical address (HPA) or a guest physical address (GPA) and must
53946 * point to a physically contiguous block of memory.
53948 uint64_t resp_addr;
53950 * 64-bit Host Destination Address.
53951 * This is the host address where the data will be written to.
53953 uint64_t host_dest_addr;
53954 /* The 0-based index of the directory entry. */
53956 uint8_t unused_0[2];
53957 /* The NVRAM byte-offset to read from. */
53959 /* The length of the data to be read, in bytes. */
53961 uint8_t unused_1[4];
53964 /* hwrm_nvm_read_output (size:128b/16B) */
53965 struct hwrm_nvm_read_output {
53966 /* The specific error status for the command. */
53967 uint16_t error_code;
53968 /* The HWRM command request type. */
53970 /* The sequence ID from the original command. */
53972 /* The length of the response data in number of bytes. */
53974 uint8_t unused_0[7];
53976 * This field is used in Output records to indicate that the output
53977 * is completely written to RAM. This field should be read as '1'
53978 * to indicate that the output has been completely written.
53979 * When writing a command completion or response to an internal processor,
53980 * the order of writes has to be such that this field is written last.
53985 /*********************
53986 * hwrm_nvm_raw_dump *
53987 *********************/
53990 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
53991 struct hwrm_nvm_raw_dump_input {
53992 /* The HWRM command request type. */
53995 * The completion ring to send the completion event on. This should
53996 * be the NQ ID returned from the `nq_alloc` HWRM command.
53998 uint16_t cmpl_ring;
54000 * The sequence ID is used by the driver for tracking multiple
54001 * commands. This ID is treated as opaque data by the firmware and
54002 * the value is returned in the `hwrm_resp_hdr` upon completion.
54006 * The target ID of the command:
54007 * * 0x0-0xFFF8 - The function ID
54008 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54009 * * 0xFFFD - Reserved for user-space HWRM interface
54012 uint16_t target_id;
54014 * A physical address pointer pointing to a host buffer that the
54015 * command's response data will be written. This can be either a host
54016 * physical address (HPA) or a guest physical address (GPA) and must
54017 * point to a physically contiguous block of memory.
54019 uint64_t resp_addr;
54021 * 64-bit Host Destination Address.
54022 * This is the host address where the data will be written to.
54024 uint64_t host_dest_addr;
54025 /* 32-bit NVRAM byte-offset to read from. */
54027 /* Total length of NVRAM contents to be read, in bytes. */
54031 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
54032 struct hwrm_nvm_raw_dump_output {
54033 /* The specific error status for the command. */
54034 uint16_t error_code;
54035 /* The HWRM command request type. */
54037 /* The sequence ID from the original command. */
54039 /* The length of the response data in number of bytes. */
54041 uint8_t unused_0[7];
54043 * This field is used in Output records to indicate that the output
54044 * is completely written to RAM. This field should be read as '1'
54045 * to indicate that the output has been completely written.
54046 * When writing a command completion or response to an internal processor,
54047 * the order of writes has to be such that this field is written last.
54052 /****************************
54053 * hwrm_nvm_get_dir_entries *
54054 ****************************/
54057 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
54058 struct hwrm_nvm_get_dir_entries_input {
54059 /* The HWRM command request type. */
54062 * The completion ring to send the completion event on. This should
54063 * be the NQ ID returned from the `nq_alloc` HWRM command.
54065 uint16_t cmpl_ring;
54067 * The sequence ID is used by the driver for tracking multiple
54068 * commands. This ID is treated as opaque data by the firmware and
54069 * the value is returned in the `hwrm_resp_hdr` upon completion.
54073 * The target ID of the command:
54074 * * 0x0-0xFFF8 - The function ID
54075 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54076 * * 0xFFFD - Reserved for user-space HWRM interface
54079 uint16_t target_id;
54081 * A physical address pointer pointing to a host buffer that the
54082 * command's response data will be written. This can be either a host
54083 * physical address (HPA) or a guest physical address (GPA) and must
54084 * point to a physically contiguous block of memory.
54086 uint64_t resp_addr;
54088 * 64-bit Host Destination Address.
54089 * This is the host address where the directory will be written.
54091 uint64_t host_dest_addr;
54094 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
54095 struct hwrm_nvm_get_dir_entries_output {
54096 /* The specific error status for the command. */
54097 uint16_t error_code;
54098 /* The HWRM command request type. */
54100 /* The sequence ID from the original command. */
54102 /* The length of the response data in number of bytes. */
54104 uint8_t unused_0[7];
54106 * This field is used in Output records to indicate that the output
54107 * is completely written to RAM. This field should be read as '1'
54108 * to indicate that the output has been completely written.
54109 * When writing a command completion or response to an internal processor,
54110 * the order of writes has to be such that this field is written last.
54115 /*************************
54116 * hwrm_nvm_get_dir_info *
54117 *************************/
54120 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
54121 struct hwrm_nvm_get_dir_info_input {
54122 /* The HWRM command request type. */
54125 * The completion ring to send the completion event on. This should
54126 * be the NQ ID returned from the `nq_alloc` HWRM command.
54128 uint16_t cmpl_ring;
54130 * The sequence ID is used by the driver for tracking multiple
54131 * commands. This ID is treated as opaque data by the firmware and
54132 * the value is returned in the `hwrm_resp_hdr` upon completion.
54136 * The target ID of the command:
54137 * * 0x0-0xFFF8 - The function ID
54138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54139 * * 0xFFFD - Reserved for user-space HWRM interface
54142 uint16_t target_id;
54144 * A physical address pointer pointing to a host buffer that the
54145 * command's response data will be written. This can be either a host
54146 * physical address (HPA) or a guest physical address (GPA) and must
54147 * point to a physically contiguous block of memory.
54149 uint64_t resp_addr;
54152 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
54153 struct hwrm_nvm_get_dir_info_output {
54154 /* The specific error status for the command. */
54155 uint16_t error_code;
54156 /* The HWRM command request type. */
54158 /* The sequence ID from the original command. */
54160 /* The length of the response data in number of bytes. */
54162 /* Number of directory entries in the directory. */
54164 /* Size of each directory entry, in bytes. */
54165 uint32_t entry_length;
54166 uint8_t unused_0[7];
54168 * This field is used in Output records to indicate that the output
54169 * is completely written to RAM. This field should be read as '1'
54170 * to indicate that the output has been completely written.
54171 * When writing a command completion or response to an internal processor,
54172 * the order of writes has to be such that this field is written last.
54177 /******************
54179 ******************/
54182 /* hwrm_nvm_write_input (size:448b/56B) */
54183 struct hwrm_nvm_write_input {
54184 /* The HWRM command request type. */
54187 * The completion ring to send the completion event on. This should
54188 * be the NQ ID returned from the `nq_alloc` HWRM command.
54190 uint16_t cmpl_ring;
54192 * The sequence ID is used by the driver for tracking multiple
54193 * commands. This ID is treated as opaque data by the firmware and
54194 * the value is returned in the `hwrm_resp_hdr` upon completion.
54198 * The target ID of the command:
54199 * * 0x0-0xFFF8 - The function ID
54200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54201 * * 0xFFFD - Reserved for user-space HWRM interface
54204 uint16_t target_id;
54206 * A physical address pointer pointing to a host buffer that the
54207 * command's response data will be written. This can be either a host
54208 * physical address (HPA) or a guest physical address (GPA) and must
54209 * point to a physically contiguous block of memory.
54211 uint64_t resp_addr;
54213 * 64-bit Host Source Address.
54214 * This is where the source data is.
54216 uint64_t host_src_addr;
54218 * The Directory Entry Type (valid values are defined in the
54219 * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
54223 * Directory ordinal.
54224 * The 0-based instance of the combined Directory Entry Type and Extension.
54226 uint16_t dir_ordinal;
54228 * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file
54233 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file
54238 * Length of data to write, in bytes. May be less than or equal to the
54239 * allocated size for the directory entry.
54240 * The data length stored in the directory entry will be updated to
54241 * reflect this value once the write is complete.
54243 uint32_t dir_data_length;
54248 * When this bit is '1', the original active image
54249 * will not be removed. TBD: what purpose is this?
54251 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
54254 * This flag indicates the sender wants to modify a continuous
54255 * NVRAM area using a batch of this HWRM requests. The
54256 * offset of a request must be continuous to the end of previous
54257 * request's. Firmware does not update the directory entry until
54258 * receiving the last request, which is indicated by the batch_last
54259 * flag. This flag is set usually when a sender does not have a
54260 * block of memory that is big enough to hold the entire NVRAM
54261 * data for send at one time.
54263 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \
54266 * This flag can be used only when the batch_mode flag is set. It
54267 * indicates this request is the last of batch requests.
54269 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \
54272 * The requested length of the allocated NVM for the item, in bytes.
54273 * This value may be greater than or equal to the specified data
54274 * length (dir_data_length).
54275 * If this value is less than the specified data length, it will be ignored.
54276 * The response will contain the actual allocated item length,
54277 * which may be greater than the requested item length.
54278 * The purpose for allocating more than the required number of bytes
54279 * for an item's data is to pre-allocate extra storage (padding) to
54280 * accommodate the potential future growth of an item (e.g. upgraded
54281 * firmware with a size increase, log growth, expanded configuration data).
54283 uint32_t dir_item_length;
54285 * 32-bit offset of data blob from where data is being written.
54286 * Only valid for batch mode. For non-batch writes 'dont care'.
54290 * Length of data to be written.Should be non-zero.
54291 * Only valid for batch mode. For non-batch writes 'dont care'.
54297 /* hwrm_nvm_write_output (size:128b/16B) */
54298 struct hwrm_nvm_write_output {
54299 /* The specific error status for the command. */
54300 uint16_t error_code;
54301 /* The HWRM command request type. */
54303 /* The sequence ID from the original command. */
54305 /* The length of the response data in number of bytes. */
54308 * Length of the allocated NVM for the item, in bytes. The value may be
54309 * greater than or equal to the specified data length or the requested
54311 * The actual item length used when creating a new directory entry will
54312 * be a multiple of an NVM block size.
54314 uint32_t dir_item_length;
54315 /* The directory index of the created or modified item. */
54319 * This field is used in Output records to indicate that the output
54320 * is completely written to RAM. This field should be read as '1'
54321 * to indicate that the output has been completely written.
54322 * When writing a command completion or response to an internal processor,
54323 * the order of writes has to be such that this field is written last.
54328 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
54329 struct hwrm_nvm_write_cmd_err {
54331 * command specific error codes that goes to
54332 * the cmd_err field in Common HWRM Error Response.
54335 /* Unknown error */
54336 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
54337 /* Unable to complete operation due to fragmentation */
54338 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
54339 /* nvm is completely full. */
54340 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
54341 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
54342 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
54343 uint8_t unused_0[7];
54346 /*******************
54347 * hwrm_nvm_modify *
54348 *******************/
54351 /* hwrm_nvm_modify_input (size:320b/40B) */
54352 struct hwrm_nvm_modify_input {
54353 /* The HWRM command request type. */
54356 * The completion ring to send the completion event on. This should
54357 * be the NQ ID returned from the `nq_alloc` HWRM command.
54359 uint16_t cmpl_ring;
54361 * The sequence ID is used by the driver for tracking multiple
54362 * commands. This ID is treated as opaque data by the firmware and
54363 * the value is returned in the `hwrm_resp_hdr` upon completion.
54367 * The target ID of the command:
54368 * * 0x0-0xFFF8 - The function ID
54369 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54370 * * 0xFFFD - Reserved for user-space HWRM interface
54373 uint16_t target_id;
54375 * A physical address pointer pointing to a host buffer that the
54376 * command's response data will be written. This can be either a host
54377 * physical address (HPA) or a guest physical address (GPA) and must
54378 * point to a physically contiguous block of memory.
54380 uint64_t resp_addr;
54382 * 64-bit Host Source Address.
54383 * This is where the modified data is.
54385 uint64_t host_src_addr;
54386 /* 16-bit directory entry index. */
54390 * This flag indicates the sender wants to modify a continuous NVRAM
54391 * area using a batch of this HWRM requests. The offset of a request
54392 * must be continuous to the end of previous request's. Firmware does
54393 * not update the directory entry until receiving the last request,
54394 * which is indicated by the batch_last flag.
54395 * This flag is set usually when a sender does not have a block of
54396 * memory that is big enough to hold the entire NVRAM data for send
54399 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
54401 * This flag can be used only when the batch_mode flag is set.
54402 * It indicates this request is the last of batch requests.
54404 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
54405 /* 32-bit NVRAM byte-offset to modify content from. */
54408 * Length of data to be modified, in bytes. The length shall
54412 uint8_t unused_1[4];
54415 /* hwrm_nvm_modify_output (size:128b/16B) */
54416 struct hwrm_nvm_modify_output {
54417 /* The specific error status for the command. */
54418 uint16_t error_code;
54419 /* The HWRM command request type. */
54421 /* The sequence ID from the original command. */
54423 /* The length of the response data in number of bytes. */
54425 uint8_t unused_0[7];
54427 * This field is used in Output records to indicate that the output
54428 * is completely written to RAM. This field should be read as '1'
54429 * to indicate that the output has been completely written.
54430 * When writing a command completion or response to an internal processor,
54431 * the order of writes has to be such that this field is written last.
54436 /***************************
54437 * hwrm_nvm_find_dir_entry *
54438 ***************************/
54441 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
54442 struct hwrm_nvm_find_dir_entry_input {
54443 /* The HWRM command request type. */
54446 * The completion ring to send the completion event on. This should
54447 * be the NQ ID returned from the `nq_alloc` HWRM command.
54449 uint16_t cmpl_ring;
54451 * The sequence ID is used by the driver for tracking multiple
54452 * commands. This ID is treated as opaque data by the firmware and
54453 * the value is returned in the `hwrm_resp_hdr` upon completion.
54457 * The target ID of the command:
54458 * * 0x0-0xFFF8 - The function ID
54459 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54460 * * 0xFFFD - Reserved for user-space HWRM interface
54463 uint16_t target_id;
54465 * A physical address pointer pointing to a host buffer that the
54466 * command's response data will be written. This can be either a host
54467 * physical address (HPA) or a guest physical address (GPA) and must
54468 * point to a physically contiguous block of memory.
54470 uint64_t resp_addr;
54473 * This bit must be '1' for the dir_idx_valid field to be
54476 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
54478 /* Directory Entry Index */
54480 /* Directory Entry (Image) Type */
54483 * Directory ordinal.
54484 * The instance of this Directory Type
54486 uint16_t dir_ordinal;
54487 /* The Directory Entry Extension flags. */
54489 /* This value indicates the search option using dir_ordinal. */
54490 uint8_t opt_ordinal;
54491 /* This value indicates the search option using dir_ordinal. */
54492 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
54493 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
54494 /* Equal to specified ordinal value. */
54495 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
54496 /* Greater than or equal to specified ordinal value */
54497 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
54498 /* Greater than specified ordinal value */
54499 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
54500 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
54501 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
54502 uint8_t unused_0[3];
54505 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
54506 struct hwrm_nvm_find_dir_entry_output {
54507 /* The specific error status for the command. */
54508 uint16_t error_code;
54509 /* The HWRM command request type. */
54511 /* The sequence ID from the original command. */
54513 /* The length of the response data in number of bytes. */
54515 /* Allocated NVRAM for this directory entry, in bytes. */
54516 uint32_t dir_item_length;
54517 /* Size of the stored data for this directory entry, in bytes. */
54518 uint32_t dir_data_length;
54520 * Firmware version.
54521 * Only valid if the directory entry is for embedded firmware stored
54522 * in APE_BIN Format.
54525 /* Directory ordinal. */
54526 uint16_t dir_ordinal;
54527 /* Directory Entry Index */
54529 uint8_t unused_0[7];
54531 * This field is used in Output records to indicate that the output
54532 * is completely written to RAM. This field should be read as '1'
54533 * to indicate that the output has been completely written.
54534 * When writing a command completion or response to an internal processor,
54535 * the order of writes has to be such that this field is written last.
54540 /****************************
54541 * hwrm_nvm_erase_dir_entry *
54542 ****************************/
54545 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
54546 struct hwrm_nvm_erase_dir_entry_input {
54547 /* The HWRM command request type. */
54550 * The completion ring to send the completion event on. This should
54551 * be the NQ ID returned from the `nq_alloc` HWRM command.
54553 uint16_t cmpl_ring;
54555 * The sequence ID is used by the driver for tracking multiple
54556 * commands. This ID is treated as opaque data by the firmware and
54557 * the value is returned in the `hwrm_resp_hdr` upon completion.
54561 * The target ID of the command:
54562 * * 0x0-0xFFF8 - The function ID
54563 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54564 * * 0xFFFD - Reserved for user-space HWRM interface
54567 uint16_t target_id;
54569 * A physical address pointer pointing to a host buffer that the
54570 * command's response data will be written. This can be either a host
54571 * physical address (HPA) or a guest physical address (GPA) and must
54572 * point to a physically contiguous block of memory.
54574 uint64_t resp_addr;
54575 /* Directory Entry Index */
54577 uint8_t unused_0[6];
54580 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
54581 struct hwrm_nvm_erase_dir_entry_output {
54582 /* The specific error status for the command. */
54583 uint16_t error_code;
54584 /* The HWRM command request type. */
54586 /* The sequence ID from the original command. */
54588 /* The length of the response data in number of bytes. */
54590 uint8_t unused_0[7];
54592 * This field is used in Output records to indicate that the output
54593 * is completely written to RAM. This field should be read as '1'
54594 * to indicate that the output has been completely written.
54595 * When writing a command completion or response to an internal processor,
54596 * the order of writes has to be such that this field is written last.
54601 /*************************
54602 * hwrm_nvm_get_dev_info *
54603 *************************/
54606 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
54607 struct hwrm_nvm_get_dev_info_input {
54608 /* The HWRM command request type. */
54611 * The completion ring to send the completion event on. This should
54612 * be the NQ ID returned from the `nq_alloc` HWRM command.
54614 uint16_t cmpl_ring;
54616 * The sequence ID is used by the driver for tracking multiple
54617 * commands. This ID is treated as opaque data by the firmware and
54618 * the value is returned in the `hwrm_resp_hdr` upon completion.
54622 * The target ID of the command:
54623 * * 0x0-0xFFF8 - The function ID
54624 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54625 * * 0xFFFD - Reserved for user-space HWRM interface
54628 uint16_t target_id;
54630 * A physical address pointer pointing to a host buffer that the
54631 * command's response data will be written. This can be either a host
54632 * physical address (HPA) or a guest physical address (GPA) and must
54633 * point to a physically contiguous block of memory.
54635 uint64_t resp_addr;
54638 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
54639 struct hwrm_nvm_get_dev_info_output {
54640 /* The specific error status for the command. */
54641 uint16_t error_code;
54642 /* The HWRM command request type. */
54644 /* The sequence ID from the original command. */
54646 /* The length of the response data in number of bytes. */
54648 /* Manufacturer ID. */
54649 uint16_t manufacturer_id;
54651 uint16_t device_id;
54652 /* Sector size of the NVRAM device. */
54653 uint32_t sector_size;
54654 /* Total size, in bytes of the NVRAM device. */
54655 uint32_t nvram_size;
54656 uint32_t reserved_size;
54658 * Available size that can be used, in bytes. Available size is the
54659 * NVRAM size take away the used size and reserved size.
54661 uint32_t available_size;
54662 /* This field represents the major version of NVM cfg */
54663 uint8_t nvm_cfg_ver_maj;
54664 /* This field represents the minor version of NVM cfg */
54665 uint8_t nvm_cfg_ver_min;
54666 /* This field represents the update version of NVM cfg */
54667 uint8_t nvm_cfg_ver_upd;
54670 * If set to 1, firmware will provide various firmware version
54671 * information stored in the flash.
54673 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
54676 * This field represents the board package name stored in the flash.
54677 * (ASCII chars with NULL at the end).
54681 * This field represents the major version of HWRM firmware, stored in
54684 uint16_t hwrm_fw_major;
54686 * This field represents the minor version of HWRM firmware, stored in
54689 uint16_t hwrm_fw_minor;
54691 * This field represents the build version of HWRM firmware, stored in
54694 uint16_t hwrm_fw_build;
54696 * This field can be used to represent firmware branches or customer
54697 * specific releases tied to a specific (major, minor, build) version
54698 * of the HWRM firmware.
54700 uint16_t hwrm_fw_patch;
54702 * This field represents the major version of mgmt firmware, stored in
54705 uint16_t mgmt_fw_major;
54707 * This field represents the minor version of mgmt firmware, stored in
54710 uint16_t mgmt_fw_minor;
54712 * This field represents the build version of mgmt firmware, stored in
54715 uint16_t mgmt_fw_build;
54717 * This field can be used to represent firmware branches or customer
54718 * specific releases tied to a specific (major, minor, build) version
54719 * of the mgmt firmware.
54721 uint16_t mgmt_fw_patch;
54723 * This field represents the major version of roce firmware, stored in
54726 uint16_t roce_fw_major;
54728 * This field represents the minor version of roce firmware, stored in
54731 uint16_t roce_fw_minor;
54733 * This field represents the build version of roce firmware, stored in
54736 uint16_t roce_fw_build;
54738 * This field can be used to represent firmware branches or customer
54739 * specific releases tied to a specific (major, minor, build) version
54740 * of the roce firmware.
54742 uint16_t roce_fw_patch;
54743 uint8_t unused_0[7];
54745 * This field is used in Output records to indicate that the output
54746 * is completely written to RAM. This field should be read as '1'
54747 * to indicate that the output has been completely written.
54748 * When writing a command completion or response to an internal processor,
54749 * the order of writes has to be such that this field is written last.
54754 /**************************
54755 * hwrm_nvm_mod_dir_entry *
54756 **************************/
54759 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
54760 struct hwrm_nvm_mod_dir_entry_input {
54761 /* The HWRM command request type. */
54764 * The completion ring to send the completion event on. This should
54765 * be the NQ ID returned from the `nq_alloc` HWRM command.
54767 uint16_t cmpl_ring;
54769 * The sequence ID is used by the driver for tracking multiple
54770 * commands. This ID is treated as opaque data by the firmware and
54771 * the value is returned in the `hwrm_resp_hdr` upon completion.
54775 * The target ID of the command:
54776 * * 0x0-0xFFF8 - The function ID
54777 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54778 * * 0xFFFD - Reserved for user-space HWRM interface
54781 uint16_t target_id;
54783 * A physical address pointer pointing to a host buffer that the
54784 * command's response data will be written. This can be either a host
54785 * physical address (HPA) or a guest physical address (GPA) and must
54786 * point to a physically contiguous block of memory.
54788 uint64_t resp_addr;
54791 * This bit must be '1' for the checksum field to be
54794 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
54795 /* Directory Entry Index */
54798 * Directory ordinal.
54799 * The (0-based) instance of this Directory Type.
54801 uint16_t dir_ordinal;
54803 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
54804 * extension flag definitions).
54808 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute
54809 * flag definitions).
54813 * If valid, then this field updates the checksum
54814 * value of the content in the directory entry.
54819 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
54820 struct hwrm_nvm_mod_dir_entry_output {
54821 /* The specific error status for the command. */
54822 uint16_t error_code;
54823 /* The HWRM command request type. */
54825 /* The sequence ID from the original command. */
54827 /* The length of the response data in number of bytes. */
54829 uint8_t unused_0[7];
54831 * This field is used in Output records to indicate that the output
54832 * is completely written to RAM. This field should be read as '1'
54833 * to indicate that the output has been completely written.
54834 * When writing a command completion or response to an internal processor,
54835 * the order of writes has to be such that this field is written last.
54840 /**************************
54841 * hwrm_nvm_verify_update *
54842 **************************/
54845 /* hwrm_nvm_verify_update_input (size:192b/24B) */
54846 struct hwrm_nvm_verify_update_input {
54847 /* The HWRM command request type. */
54850 * The completion ring to send the completion event on. This should
54851 * be the NQ ID returned from the `nq_alloc` HWRM command.
54853 uint16_t cmpl_ring;
54855 * The sequence ID is used by the driver for tracking multiple
54856 * commands. This ID is treated as opaque data by the firmware and
54857 * the value is returned in the `hwrm_resp_hdr` upon completion.
54861 * The target ID of the command:
54862 * * 0x0-0xFFF8 - The function ID
54863 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54864 * * 0xFFFD - Reserved for user-space HWRM interface
54867 uint16_t target_id;
54869 * A physical address pointer pointing to a host buffer that the
54870 * command's response data will be written. This can be either a host
54871 * physical address (HPA) or a guest physical address (GPA) and must
54872 * point to a physically contiguous block of memory.
54874 uint64_t resp_addr;
54875 /* Directory Entry Type, to be verified. */
54878 * Directory ordinal.
54879 * The instance of the Directory Type to be verified.
54881 uint16_t dir_ordinal;
54883 * The Directory Entry Extension flags.
54884 * The "UPDATE" extension flag must be set in this value.
54885 * A corresponding directory entry with the same type and ordinal
54886 * values but *without*
54887 * the "UPDATE" extension flag must also exist. The other flags of
54888 * the extension must
54889 * be identical between the active and update entries.
54892 uint8_t unused_0[2];
54895 /* hwrm_nvm_verify_update_output (size:128b/16B) */
54896 struct hwrm_nvm_verify_update_output {
54897 /* The specific error status for the command. */
54898 uint16_t error_code;
54899 /* The HWRM command request type. */
54901 /* The sequence ID from the original command. */
54903 /* The length of the response data in number of bytes. */
54905 uint8_t unused_0[7];
54907 * This field is used in Output records to indicate that the output
54908 * is completely written to RAM. This field should be read as '1'
54909 * to indicate that the output has been completely written.
54910 * When writing a command completion or response to an internal processor,
54911 * the order of writes has to be such that this field is written last.
54916 /***************************
54917 * hwrm_nvm_install_update *
54918 ***************************/
54921 /* hwrm_nvm_install_update_input (size:192b/24B) */
54922 struct hwrm_nvm_install_update_input {
54923 /* The HWRM command request type. */
54926 * The completion ring to send the completion event on. This should
54927 * be the NQ ID returned from the `nq_alloc` HWRM command.
54929 uint16_t cmpl_ring;
54931 * The sequence ID is used by the driver for tracking multiple
54932 * commands. This ID is treated as opaque data by the firmware and
54933 * the value is returned in the `hwrm_resp_hdr` upon completion.
54937 * The target ID of the command:
54938 * * 0x0-0xFFF8 - The function ID
54939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54940 * * 0xFFFD - Reserved for user-space HWRM interface
54943 uint16_t target_id;
54945 * A physical address pointer pointing to a host buffer that the
54946 * command's response data will be written. This can be either a host
54947 * physical address (HPA) or a guest physical address (GPA) and must
54948 * point to a physically contiguous block of memory.
54950 uint64_t resp_addr;
54952 * Installation type. If the value 3 through 0xffff is used,
54953 * only packaged items with that type value will be installed and
54954 * conditional installation directives for those packaged items
54955 * will be over-ridden (i.e. 'create' or 'replace' will be treated
54958 uint32_t install_type;
54960 * Perform a normal package installation. Conditional installation
54961 * directives (e.g. 'create' and 'replace') of packaged items
54962 * will be followed.
54964 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
54966 * Install all packaged items regardless of installation directive
54967 * (i.e. treat all packaged items as though they have an installation
54968 * directive of 'install').
54970 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
54971 UINT32_C(0xffffffff)
54972 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
54973 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
54976 * If set to 1, then securely erase all unused locations in
54977 * persistent storage.
54979 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
54982 * If set to 1, then unspecified images, images not in the package
54983 * file, will be safely deleted.
54984 * When combined with erase_unused_space then unspecified images will
54985 * be securely erased.
54987 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
54990 * If set to 1, FW will defragment the NVM if defragmentation is
54991 * required for the update.
54992 * Allow additional time for this command to complete if this bit is
54995 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
54998 * If set to 1, FW will verify the package in the "UPDATE" NVM item
54999 * without installing it. This flag is for FW internal use only.
55000 * Users should not set this flag. The request will otherwise fail.
55002 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
55004 uint8_t unused_0[2];
55007 /* hwrm_nvm_install_update_output (size:192b/24B) */
55008 struct hwrm_nvm_install_update_output {
55009 /* The specific error status for the command. */
55010 uint16_t error_code;
55011 /* The HWRM command request type. */
55013 /* The sequence ID from the original command. */
55015 /* The length of the response data in number of bytes. */
55018 * Bit-mask of successfully installed items.
55019 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
55020 * A value of 0 indicates that no items were successfully installed.
55022 uint64_t installed_items;
55023 /* result is 8 b corresponding to BCMRETVAL error codes */
55025 /* There was no problem with the package installation. */
55026 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \
55028 /* Generic failure */
55029 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \
55031 /* Allocation error malloc failure */
55032 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \
55034 /* NVM install error due to invalid index */
55035 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \
55037 /* NVM install error due to invalid type */
55038 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \
55040 /* Invalid package due to invalid prerequisite */
55041 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \
55043 /* Invalid package due to invalid file header */
55044 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \
55046 /* Invalid package due to invalid format */
55047 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \
55049 /* Invalid package due to invalid property stream */
55050 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \
55052 /* Invalid package due to invalid property length */
55053 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \
55055 /* Invalid package due to invalid manifest */
55056 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \
55058 /* Invalid package due to invalid trailer */
55059 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \
55061 /* Invalid package due to invalid checksum */
55062 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \
55064 /* Invalid package due to invalid item checksum */
55065 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \
55067 /* Invalid package due to invalid length */
55068 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \
55070 /* Invalid package due to invalid directive */
55071 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \
55073 /* Invalid device due to unsupported chip revision */
55074 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \
55076 /* Invalid device due to unsupported device ID */
55077 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \
55079 /* Invalid device due to unsupported subsystem vendor */
55080 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \
55082 /* Invalid device due to unsupported subsystem ID */
55083 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \
55085 /* Invalid device due to unsupported product ID or customer ID */
55086 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \
55088 /* Invalid package due to duplicate item */
55089 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \
55091 /* Invalid package due to zero length item */
55092 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \
55094 /* NVM integrity error checksum */
55095 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \
55097 /* NVM integrity error */
55098 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \
55100 /* Authentication error */
55101 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \
55103 /* NVM install error item not found */
55104 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \
55106 /* NVM install error item locked */
55107 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \
55109 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
55110 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED
55111 /* problem_item is 8 b */
55112 uint8_t problem_item;
55113 /* There was no problem with any packaged items. */
55114 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
55116 /* There was a problem with the NVM package itself. */
55117 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
55119 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
55120 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
55121 /* reset_required is 8 b */
55122 uint8_t reset_required;
55124 * No reset is required for installed/updated firmware or
55125 * microcode to take effect.
55127 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
55130 * A PCIe reset (e.g. system reboot) is
55131 * required for newly installed/updated firmware or
55132 * microcode to take effect.
55134 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
55137 * A controller power reset (e.g. system power-cycle) is
55138 * required for newly installed/updated firmware or
55139 * microcode to take effect. Some newly installed/updated
55140 * firmware or microcode may still take effect upon the
55143 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
55145 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
55146 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
55147 uint8_t unused_0[4];
55149 * This field is used in Output records to indicate that the output
55150 * is completely written to RAM. This field should be read as '1'
55151 * to indicate that the output has been completely written.
55152 * When writing a command completion or response to an internal processor,
55153 * the order of writes has to be such that this field is written last.
55158 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
55159 struct hwrm_nvm_install_update_cmd_err {
55161 * command specific error codes that goes to
55162 * the cmd_err field in Common HWRM Error Response.
55165 /* Unknown error */
55166 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \
55168 /* Unable to complete operation due to fragmentation */
55169 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \
55171 /* nvm is completely full. */
55172 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \
55174 /* Firmware update failed due to Anti-rollback. */
55175 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
55177 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
55178 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
55179 uint8_t unused_0[7];
55182 /******************
55184 ******************/
55187 /* hwrm_nvm_flush_input (size:128b/16B) */
55188 struct hwrm_nvm_flush_input {
55189 /* The HWRM command request type. */
55192 * The completion ring to send the completion event on. This should
55193 * be the NQ ID returned from the `nq_alloc` HWRM command.
55195 uint16_t cmpl_ring;
55197 * The sequence ID is used by the driver for tracking multiple
55198 * commands. This ID is treated as opaque data by the firmware and
55199 * the value is returned in the `hwrm_resp_hdr` upon completion.
55203 * The target ID of the command:
55204 * * 0x0-0xFFF8 - The function ID
55205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55206 * * 0xFFFD - Reserved for user-space HWRM interface
55209 uint16_t target_id;
55211 * A physical address pointer pointing to a host buffer that the
55212 * command's response data will be written. This can be either a host
55213 * physical address (HPA) or a guest physical address (GPA) and must
55214 * point to a physically contiguous block of memory.
55216 uint64_t resp_addr;
55219 /* hwrm_nvm_flush_output (size:128b/16B) */
55220 struct hwrm_nvm_flush_output {
55221 /* The specific error status for the command. */
55222 uint16_t error_code;
55223 /* The HWRM command request type. */
55225 /* The sequence ID from the original command. */
55227 /* The length of the response data in number of bytes. */
55229 uint8_t unused_0[7];
55231 * This field is used in Output records to indicate that the output
55232 * is completely written to RAM. This field should be read as '1'
55233 * to indicate that the output has been completely written.
55234 * When writing a command completion or response to an internal processor,
55235 * the order of writes has to be such that this field is written last.
55240 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
55241 struct hwrm_nvm_flush_cmd_err {
55243 * command specific error codes that goes to
55244 * the cmd_err field in Common HWRM Error Response.
55247 /* Unknown error */
55248 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
55249 /* flush could not be performed */
55250 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
55251 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
55252 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
55253 uint8_t unused_0[7];
55256 /*************************
55257 * hwrm_nvm_get_variable *
55258 *************************/
55261 /* hwrm_nvm_get_variable_input (size:320b/40B) */
55262 struct hwrm_nvm_get_variable_input {
55263 /* The HWRM command request type. */
55266 * The completion ring to send the completion event on. This should
55267 * be the NQ ID returned from the `nq_alloc` HWRM command.
55269 uint16_t cmpl_ring;
55271 * The sequence ID is used by the driver for tracking multiple
55272 * commands. This ID is treated as opaque data by the firmware and
55273 * the value is returned in the `hwrm_resp_hdr` upon completion.
55277 * The target ID of the command:
55278 * * 0x0-0xFFF8 - The function ID
55279 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55280 * * 0xFFFD - Reserved for user-space HWRM interface
55283 uint16_t target_id;
55285 * A physical address pointer pointing to a host buffer that the
55286 * command's response data will be written. This can be either a host
55287 * physical address (HPA) or a guest physical address (GPA) and must
55288 * point to a physically contiguous block of memory.
55290 uint64_t resp_addr;
55292 * This is the host address where
55293 * nvm variable will be stored
55295 uint64_t dest_data_addr;
55296 /* size of data in bits */
55298 /* nvm cfg option number */
55299 uint16_t option_num;
55301 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
55303 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
55305 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
55306 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
55308 * Number of dimensions for this nvm configuration variable.
55309 * This value indicates how many of the indexN values to use.
55310 * A value of 0 means that none of the indexN values are valid.
55311 * A value of 1 requires at index0 is valued, a value of 2
55312 * requires that index0 and index1 are valid, and so forth
55314 uint16_t dimensions;
55315 /* index for the 1st dimensions */
55317 /* index for the 2nd dimensions */
55319 /* index for the 3rd dimensions */
55321 /* index for the 4th dimensions */
55325 * When this bit is set to 1, the factory default value will be returned,
55326 * 0 returns the operational value.
55328 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
55333 /* hwrm_nvm_get_variable_output (size:128b/16B) */
55334 struct hwrm_nvm_get_variable_output {
55335 /* The specific error status for the command. */
55336 uint16_t error_code;
55337 /* The HWRM command request type. */
55339 /* The sequence ID from the original command. */
55341 /* The length of the response data in number of bytes. */
55343 /* size of data of the actual variable retrieved in bits */
55346 * option_num is the option number for the data retrieved. It is
55347 * possible in the future that the option number returned would be
55348 * different than requested. This condition could occur if an option is
55349 * deprecated and a new option id is defined with similar
55350 * characteristics, but has a slightly different definition. This
55351 * also makes it convenient for the caller to identify the variable
55352 * result with the option id from the response.
55354 uint16_t option_num;
55356 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
55358 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
55360 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
55361 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
55362 uint8_t unused_0[3];
55364 * This field is used in Output records to indicate that the output
55365 * is completely written to RAM. This field should be read as '1'
55366 * to indicate that the output has been completely written.
55367 * When writing a command completion or response to an internal processor,
55368 * the order of writes has to be such that this field is written last.
55373 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
55374 struct hwrm_nvm_get_variable_cmd_err {
55376 * command specific error codes that goes to
55377 * the cmd_err field in Common HWRM Error Response.
55380 /* Unknown error */
55381 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
55382 /* variable does not exist */
55383 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
55384 /* configuration is corrupted and the variable cannot be saved */
55385 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
55386 /* length specified is too small */
55387 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
55388 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
55389 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
55390 uint8_t unused_0[7];
55393 /*************************
55394 * hwrm_nvm_set_variable *
55395 *************************/
55398 /* hwrm_nvm_set_variable_input (size:320b/40B) */
55399 struct hwrm_nvm_set_variable_input {
55400 /* The HWRM command request type. */
55403 * The completion ring to send the completion event on. This should
55404 * be the NQ ID returned from the `nq_alloc` HWRM command.
55406 uint16_t cmpl_ring;
55408 * The sequence ID is used by the driver for tracking multiple
55409 * commands. This ID is treated as opaque data by the firmware and
55410 * the value is returned in the `hwrm_resp_hdr` upon completion.
55414 * The target ID of the command:
55415 * * 0x0-0xFFF8 - The function ID
55416 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55417 * * 0xFFFD - Reserved for user-space HWRM interface
55420 uint16_t target_id;
55422 * A physical address pointer pointing to a host buffer that the
55423 * command's response data will be written. This can be either a host
55424 * physical address (HPA) or a guest physical address (GPA) and must
55425 * point to a physically contiguous block of memory.
55427 uint64_t resp_addr;
55429 * This is the host address where
55430 * nvm variable will be copied from
55432 uint64_t src_data_addr;
55433 /* size of data in bits */
55435 /* nvm cfg option number */
55436 uint16_t option_num;
55438 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
55440 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
55442 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
55443 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
55445 * Number of dimensions for this nvm configuration variable.
55446 * This value indicates how many of the indexN values to use.
55447 * A value of 0 means that none of the indexN values are valid.
55448 * A value of 1 requires at index0 is valued, a value of 2
55449 * requires that index0 and index1 are valid, and so forth
55451 uint16_t dimensions;
55452 /* index for the 1st dimensions */
55454 /* index for the 2nd dimensions */
55456 /* index for the 3rd dimensions */
55458 /* index for the 4th dimensions */
55462 * When this bit is 1, flush internal cache after this write
55463 * operation (see hwrm_nvm_flush command.)
55465 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
55467 /* encryption method */
55468 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
55470 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
55471 /* No encryption. */
55472 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
55473 (UINT32_C(0x0) << 1)
55474 /* one-way encryption. */
55475 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
55476 (UINT32_C(0x1) << 1)
55477 /* symmetric AES256 encryption. */
55478 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
55479 (UINT32_C(0x2) << 1)
55480 /* SHA1 digest appended to plaintext contents, for authentication */
55481 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
55482 (UINT32_C(0x3) << 1)
55483 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
55484 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
55485 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
55487 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
55488 /* When this bit is 1, update the factory default region */
55489 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
55494 /* hwrm_nvm_set_variable_output (size:128b/16B) */
55495 struct hwrm_nvm_set_variable_output {
55496 /* The specific error status for the command. */
55497 uint16_t error_code;
55498 /* The HWRM command request type. */
55500 /* The sequence ID from the original command. */
55502 /* The length of the response data in number of bytes. */
55504 uint8_t unused_0[7];
55506 * This field is used in Output records to indicate that the output
55507 * is completely written to RAM. This field should be read as '1'
55508 * to indicate that the output has been completely written.
55509 * When writing a command completion or response to an internal processor,
55510 * the order of writes has to be such that this field is written last.
55515 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
55516 struct hwrm_nvm_set_variable_cmd_err {
55518 * command specific error codes that goes to
55519 * the cmd_err field in Common HWRM Error Response.
55522 /* Unknown error */
55523 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
55524 /* variable does not exist */
55525 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
55526 /* configuration is corrupted and the variable cannot be saved */
55527 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
55528 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
55529 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
55530 uint8_t unused_0[7];
55533 /****************************
55534 * hwrm_nvm_validate_option *
55535 ****************************/
55538 /* hwrm_nvm_validate_option_input (size:320b/40B) */
55539 struct hwrm_nvm_validate_option_input {
55540 /* The HWRM command request type. */
55543 * The completion ring to send the completion event on. This should
55544 * be the NQ ID returned from the `nq_alloc` HWRM command.
55546 uint16_t cmpl_ring;
55548 * The sequence ID is used by the driver for tracking multiple
55549 * commands. This ID is treated as opaque data by the firmware and
55550 * the value is returned in the `hwrm_resp_hdr` upon completion.
55554 * The target ID of the command:
55555 * * 0x0-0xFFF8 - The function ID
55556 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55557 * * 0xFFFD - Reserved for user-space HWRM interface
55560 uint16_t target_id;
55562 * A physical address pointer pointing to a host buffer that the
55563 * command's response data will be written. This can be either a host
55564 * physical address (HPA) or a guest physical address (GPA) and must
55565 * point to a physically contiguous block of memory.
55567 uint64_t resp_addr;
55569 * This is the host address where
55570 * nvm variable will be copied from
55572 uint64_t src_data_addr;
55573 /* size of data in bits */
55575 /* nvm cfg option number */
55576 uint16_t option_num;
55578 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
55581 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
55583 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
55584 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
55586 * Number of dimensions for this nvm configuration variable.
55587 * This value indicates how many of the indexN values to use.
55588 * A value of 0 means that none of the indexN values are valid.
55589 * A value of 1 requires at index0 is valued, a value of 2
55590 * requires that index0 and index1 are valid, and so forth
55592 uint16_t dimensions;
55593 /* index for the 1st dimensions */
55595 /* index for the 2nd dimensions */
55597 /* index for the 3rd dimensions */
55599 /* index for the 4th dimensions */
55601 uint8_t unused_0[2];
55604 /* hwrm_nvm_validate_option_output (size:128b/16B) */
55605 struct hwrm_nvm_validate_option_output {
55606 /* The specific error status for the command. */
55607 uint16_t error_code;
55608 /* The HWRM command request type. */
55610 /* The sequence ID from the original command. */
55612 /* The length of the response data in number of bytes. */
55616 * indicates that the value provided for the option is not matching
55617 * with the saved data.
55619 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
55621 * indicates that the value provided for the option is matching the
55624 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
55625 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
55626 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
55627 uint8_t unused_0[6];
55629 * This field is used in Output records to indicate that the output
55630 * is completely written to RAM. This field should be read as '1'
55631 * to indicate that the output has been completely written.
55632 * When writing a command completion or response to an internal processor,
55633 * the order of writes has to be such that this field is written last.
55638 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
55639 struct hwrm_nvm_validate_option_cmd_err {
55641 * command specific error codes that goes to
55642 * the cmd_err field in Common HWRM Error Response.
55645 /* Unknown error */
55646 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
55647 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
55648 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
55649 uint8_t unused_0[7];
55652 /*******************
55653 * hwrm_nvm_defrag *
55654 *******************/
55657 /* hwrm_nvm_defrag_input (size:192b/24B) */
55658 struct hwrm_nvm_defrag_input {
55659 /* The HWRM command request type. */
55662 * The completion ring to send the completion event on. This should
55663 * be the NQ ID returned from the `nq_alloc` HWRM command.
55665 uint16_t cmpl_ring;
55667 * The sequence ID is used by the driver for tracking multiple
55668 * commands. This ID is treated as opaque data by the firmware and
55669 * the value is returned in the `hwrm_resp_hdr` upon completion.
55673 * The target ID of the command:
55674 * * 0x0-0xFFF8 - The function ID
55675 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55676 * * 0xFFFD - Reserved for user-space HWRM interface
55679 uint16_t target_id;
55681 * A physical address pointer pointing to a host buffer that the
55682 * command's response data will be written. This can be either a host
55683 * physical address (HPA) or a guest physical address (GPA) and must
55684 * point to a physically contiguous block of memory.
55686 uint64_t resp_addr;
55688 /* This bit must be '1' to perform NVM defragmentation. */
55689 #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
55690 uint8_t unused_0[4];
55693 /* hwrm_nvm_defrag_output (size:128b/16B) */
55694 struct hwrm_nvm_defrag_output {
55695 /* The specific error status for the command. */
55696 uint16_t error_code;
55697 /* The HWRM command request type. */
55699 /* The sequence ID from the original command. */
55701 /* The length of the response data in number of bytes. */
55703 uint8_t unused_0[7];
55705 * This field is used in Output records to indicate that the output
55706 * is completely written to RAM. This field should be read as '1'
55707 * to indicate that the output has been completely written.
55708 * When writing a command completion or response to an internal processor,
55709 * the order of writes has to be such that this field is written last.
55714 /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */
55715 struct hwrm_nvm_defrag_cmd_err {
55717 * command specific error codes that goes to
55718 * the cmd_err field in Common HWRM Error Response.
55721 /* Unknown error */
55722 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
55723 /* NVM defragmentation could not be performed */
55724 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
55725 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \
55726 HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL
55727 uint8_t unused_0[7];
55735 /* hwrm_oem_cmd_input (size:1024b/128B) */
55736 struct hwrm_oem_cmd_input {
55737 /* The HWRM command request type. */
55740 * The completion ring to send the completion event on. This should
55741 * be the NQ ID returned from the `nq_alloc` HWRM command.
55743 uint16_t cmpl_ring;
55745 * The sequence ID is used by the driver for tracking multiple
55746 * commands. This ID is treated as opaque data by the firmware and
55747 * the value is returned in the `hwrm_resp_hdr` upon completion.
55751 * The target ID of the command:
55752 * * 0x0-0xFFF8 - The function ID
55753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55754 * * 0xFFFD - Reserved for user-space HWRM interface
55757 uint16_t target_id;
55759 * A physical address pointer pointing to a host buffer that the
55760 * command's response data will be written. This can be either a host
55761 * physical address (HPA) or a guest physical address (GPA) and must
55762 * point to a physically contiguous block of memory.
55764 uint64_t resp_addr;
55767 /* This field contains the vendor specific command data. */
55768 uint32_t oem_data[26];
55771 /* hwrm_oem_cmd_output (size:768b/96B) */
55772 struct hwrm_oem_cmd_output {
55773 /* The specific error status for the command. */
55774 uint16_t error_code;
55775 /* The HWRM command request type. */
55777 /* The sequence ID from the original command. */
55779 /* The length of the response data in number of bytes. */
55783 /* This field contains the vendor specific response data. */
55784 uint32_t oem_data[18];
55785 uint8_t unused_1[7];
55787 * This field is used in Output records to indicate that the output
55788 * is completely written to RAM. This field should be read as '1'
55789 * to indicate that the output has been completely written.
55790 * When writing a command completion or response to an internal processor,
55791 * the order of writes has to be such that this field is written last.
55798 ******************/
55801 /* hwrm_fw_reset_input (size:192b/24B) */
55802 struct hwrm_fw_reset_input {
55803 /* The HWRM command request type. */
55806 * The completion ring to send the completion event on. This should
55807 * be the NQ ID returned from the `nq_alloc` HWRM command.
55809 uint16_t cmpl_ring;
55811 * The sequence ID is used by the driver for tracking multiple
55812 * commands. This ID is treated as opaque data by the firmware and
55813 * the value is returned in the `hwrm_resp_hdr` upon completion.
55817 * The target ID of the command:
55818 * * 0x0-0xFFF8 - The function ID
55819 * * 0xFFF8-0xFFFE - Reserved for internal processors
55822 uint16_t target_id;
55824 * A physical address pointer pointing to a host buffer that the
55825 * command's response data will be written. This can be either a host
55826 * physical address (HPA) or a guest physical address (GPA) and must
55827 * point to a physically contiguous block of memory.
55829 uint64_t resp_addr;
55830 /* Type of embedded processor. */
55831 uint8_t embedded_proc_type;
55832 /* Boot Processor */
55833 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
55835 /* Management Processor */
55836 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
55838 /* Network control processor */
55839 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
55841 /* RoCE control processor */
55842 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
55845 * Host (in multi-host environment): This is only valid if requester is IPC.
55846 * Reinit host hardware resources and PCIe.
55848 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
55851 * AP processor complex (in multi-host environment).
55852 * Use host_idx to control which core is reset
55854 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
55856 /* Reset all blocks of the chip (including all processors) */
55857 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
55860 * Host (in multi-host environment): This is only valid if requester is IPC.
55861 * Reinit host hardware resources.
55863 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
55865 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
55866 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
55867 /* Type of self reset. */
55868 uint8_t selfrst_status;
55869 /* No Self Reset */
55870 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
55872 /* Self Reset as soon as possible to do so safely */
55873 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
55875 /* Self Reset on PCIe Reset */
55876 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
55878 /* Self Reset immediately after notification to all clients. */
55879 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
55881 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
55882 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
55884 * Indicate which host is being reset. 0 means first host.
55885 * Only valid when embedded_proc_type is host in multihost
55891 * When this bit is '1', then the core firmware initiates
55892 * the reset only after graceful shut down of all registered instances.
55893 * If not, the device will continue with the existing firmware.
55895 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
55896 uint8_t unused_0[4];
55899 /* hwrm_fw_reset_output (size:128b/16B) */
55900 struct hwrm_fw_reset_output {
55901 /* The specific error status for the command. */
55902 uint16_t error_code;
55903 /* The HWRM command request type. */
55905 /* The sequence ID from the original command. */
55907 /* The length of the response data in number of bytes. */
55909 /* Type of self reset. */
55910 uint8_t selfrst_status;
55911 /* No Self Reset */
55912 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
55914 /* Self Reset as soon as possible to do so safely */
55915 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
55917 /* Self Reset on PCIe Reset */
55918 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
55920 /* Self Reset immediately after notification to all clients. */
55921 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
55923 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
55924 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
55925 uint8_t unused_0[6];
55927 * This field is used in Output records to indicate that the output
55928 * is completely written to RAM. This field should be read as '1'
55929 * to indicate that the output has been completely written.
55930 * When writing a command completion or response to an internal processor,
55931 * the order of writes has to be such that this field is written last.
55936 /**********************
55937 * hwrm_port_ts_query *
55938 ***********************/
55941 /* hwrm_port_ts_query_input (size:192b/24B) */
55942 struct hwrm_port_ts_query_input {
55943 /* The HWRM command request type. */
55946 * The completion ring to send the completion event on. This should
55947 * be the NQ ID returned from the `nq_alloc` HWRM command.
55949 uint16_t cmpl_ring;
55951 * The sequence ID is used by the driver for tracking multiple
55952 * commands. This ID is treated as opaque data by the firmware and
55953 * the value is returned in the `hwrm_resp_hdr` upon completion.
55957 * The target ID of the command:
55958 * * 0x0-0xFFF8 - The function ID
55959 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55960 * * 0xFFFD - Reserved for user-space HWRM interface
55963 uint16_t target_id;
55965 * A physical address pointer pointing to a host buffer that the
55966 * command's response data will be written. This can be either a host
55967 * physical address (HPA) or a guest physical address (GPA) and must
55968 * point to a physically contiguous block of memory.
55970 uint64_t resp_addr;
55973 * Enumeration denoting the RX, TX type of the resource.
55974 * This enumeration is used for resources that are similar for both
55975 * TX and RX paths of the chip.
55977 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
55979 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
55981 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
55982 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
55983 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
55985 * If set, the response includes the current value of the free
55988 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
55989 /* Port ID of port that is being queried. */
55991 uint8_t unused_0[2];
55994 /* hwrm_port_ts_query_output (size:192b/24B) */
55995 struct hwrm_port_ts_query_output {
55996 /* The specific error status for the command. */
55997 uint16_t error_code;
55998 /* The HWRM command request type. */
56000 /* The sequence ID from the original command. */
56002 /* The length of the response data in number of bytes. */
56005 * Timestamp value of PTP message captured, or current value of
56006 * free running timer.
56008 uint32_t ptp_msg_ts[2];
56009 /* Sequence ID of the PTP message captured. */
56010 uint16_t ptp_msg_seqid;
56011 uint8_t unused_0[5];
56013 * This field is used in Output records to indicate that the output
56014 * is completely written to RAM. This field should be read as '1'
56015 * to indicate that the output has been completely written.
56016 * When writing a command completion or response to an internal processor,
56017 * the order of writes has to be such that this field is written last.
56023 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
56024 * offset: 0x31001F0). Host software is expected to read from this
56025 * location for a defined signature. If it exists, the software can
56026 * assume the presence of this structure and the validity of the
56027 * FW_STATUS location in the next field.
56029 /* hcomm_status (size:64b/8B) */
56030 struct hcomm_status {
56033 * This field defines the version of the structure. The latest
56034 * version value is 1.
56036 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
56037 #define HCOMM_STATUS_VER_SFT 0
56038 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
56039 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
56041 * This field is to store the signature value to indicate the
56042 * presence of the structure.
56044 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
56045 #define HCOMM_STATUS_SIGNATURE_SFT 8
56046 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
56047 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
56048 uint32_t fw_status_loc;
56049 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
56050 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
56051 /* PCIE configuration space */
56052 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
56054 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
56056 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
56058 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
56059 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
56060 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
56062 * This offset where the fw_status register is located. The value
56063 * is generally 4-byte aligned.
56065 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
56066 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
56068 /* This is the GRC offset where the hcomm_status struct resides. */
56069 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
56071 /**************************
56072 * hwrm_port_phy_i2c_read *
56073 **************************/
56076 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
56077 struct hwrm_port_phy_i2c_read_input {
56078 /* The HWRM command request type. */
56081 * The completion ring to send the completion event on. This should
56082 * be the NQ ID returned from the `nq_alloc` HWRM command.
56084 uint16_t cmpl_ring;
56086 * The sequence ID is used by the driver for tracking multiple
56087 * commands. This ID is treated as opaque data by the firmware and
56088 * the value is returned in the `hwrm_resp_hdr` upon completion.
56092 * The target ID of the command:
56093 * * 0x0-0xFFF8 - The function ID
56094 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56095 * * 0xFFFD - Reserved for user-space HWRM interface
56098 uint16_t target_id;
56100 * A physical address pointer pointing to a host buffer that the
56101 * command's response data will be written. This can be either a host
56102 * physical address (HPA) or a guest physical address (GPA) and must
56103 * point to a physically contiguous block of memory.
56105 uint64_t resp_addr;
56109 * This bit must be '1' for the page_offset field to be
56112 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL
56113 /* Port ID of port. */
56115 /* 8-bit I2C slave address. */
56116 uint8_t i2c_slave_addr;
56118 /* The page number that is being accessed over I2C. */
56119 uint16_t page_number;
56120 /* Offset within the page that is being accessed over I2C. */
56121 uint16_t page_offset;
56123 * Length of data to read, in bytes starting at the offset
56124 * specified above. If the offset is not specified, then
56125 * the data shall be read from the beginning of the page.
56127 uint8_t data_length;
56128 uint8_t unused_1[7];
56131 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
56132 struct hwrm_port_phy_i2c_read_output {
56133 /* The specific error status for the command. */
56134 uint16_t error_code;
56135 /* The HWRM command request type. */
56137 /* The sequence ID from the original command. */
56139 /* The length of the response data in number of bytes. */
56141 /* Up to 64B of data. */
56143 uint8_t unused_0[7];
56145 * This field is used in Output records to indicate that the output
56146 * is completely written to RAM. This field should be read as '1'
56147 * to indicate that the output has been completely written.
56148 * When writing a command completion or response to an internal processor,
56149 * the order of writes has to be such that this field is written last.
56153 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */