1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_RESET UINT32_C(0x5e)
345 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
346 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
347 /* Reserved for future use. */
348 #define HWRM_RESERVED5 UINT32_C(0x64)
349 /* Reserved for future use. */
350 #define HWRM_RESERVED6 UINT32_C(0x65)
351 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
353 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
354 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
355 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
356 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
357 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
358 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
359 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
360 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
361 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
362 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
364 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
366 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
368 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
369 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
371 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
373 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
375 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
376 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
377 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
378 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
379 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
380 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
381 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
382 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
383 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
384 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
385 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
386 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
387 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
388 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
389 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
390 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
391 #define HWRM_FW_RESET UINT32_C(0xc0)
392 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
393 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
394 #define HWRM_FW_SYNC UINT32_C(0xc3)
395 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
396 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
397 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
398 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
400 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
402 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
404 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
406 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
408 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
409 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
410 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
411 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
412 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
413 #define HWRM_FWD_RESP UINT32_C(0xd2)
414 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
415 #define HWRM_OEM_CMD UINT32_C(0xd4)
416 /* Tells the fw to run PRBS test on a given port and lane. */
417 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
418 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
419 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
420 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
421 /* Tells the fw to collect dsc dump on a given port and lane. */
422 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
423 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
424 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
425 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
426 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
427 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
428 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
429 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
430 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
432 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
434 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
436 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
438 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
440 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
442 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
444 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
446 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
448 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
450 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
452 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
454 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
456 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
458 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
460 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
462 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
464 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
466 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
468 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
469 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
470 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
471 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
473 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
475 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
477 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
479 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
480 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
481 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
483 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
485 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
487 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
489 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
491 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
493 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
495 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
497 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
499 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
501 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
503 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
505 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
507 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
509 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
511 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
513 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
515 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
517 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
518 /* Experimental - DEPRECATED */
519 #define HWRM_CFA_TFLIB UINT32_C(0x125)
520 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
521 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
522 /* Engine CKV - Add a new CKEK used to encrypt keys. */
523 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
524 /* Engine CKV - Delete a previously added CKEK. */
525 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
526 /* Engine CKV - Add a new key to the key vault. */
527 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
528 /* Engine CKV - Delete a key from the key vault. */
529 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
530 /* Engine CKV - Delete all keys from the key vault. */
531 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
532 /* Engine CKV - Get random data. */
533 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
534 /* Engine CKV - Generate and encrypt a new AES key. */
535 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
536 /* Engine CKV - Configure a label index with a label value. */
537 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
538 /* Engine CKV - Query a label */
539 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
540 /* Engine - Query the available queue groups configuration. */
541 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
542 /* Engine - Query the queue groups assigned to a function. */
543 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
544 /* Engine - Query the available queue group meter profile configuration. */
545 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
546 /* Engine - Query the configuration of a queue group meter profile. */
547 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
548 /* Engine - Allocate a queue group meter profile. */
549 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
550 /* Engine - Free a queue group meter profile. */
551 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
552 /* Engine - Query the meters assigned to a queue group. */
553 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
554 /* Engine - Bind a queue group meter profile to a queue group. */
555 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
556 /* Engine - Unbind a queue group meter profile from a queue group. */
557 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
558 /* Engine - Bind a queue group to a function. */
559 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
560 /* Engine - Query the scheduling group configuration. */
561 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
562 /* Engine - Query the queue groups assigned to a scheduling group. */
563 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
564 /* Engine - Query the configuration of a scheduling group's meter profiles. */
565 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
566 /* Engine - Configure a scheduling group's meter profiles. */
567 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
568 /* Engine - Bind a queue group to a scheduling group. */
569 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
570 /* Engine - Unbind a queue group from its scheduling group. */
571 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
572 /* Engine - Query the Engine configuration. */
573 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
574 /* Engine - Configure the statistics accumulator for an Engine. */
575 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
576 /* Engine - Clear the statistics accumulator for an Engine. */
577 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
578 /* Engine - Query the statistics accumulator for an Engine. */
579 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
580 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
581 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
582 /* Engine - Allocate an Engine RQ. */
583 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
584 /* Engine - Free an Engine RQ. */
585 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
586 /* Engine - Allocate an Engine CQ. */
587 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
588 /* Engine - Free an Engine CQ. */
589 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
590 /* Engine - Allocate an NQ. */
591 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
592 /* Engine - Free an NQ. */
593 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
594 /* Engine - Set the on-die RQE credit update location. */
595 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
596 /* Engine - Query the engine function configuration. */
597 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
599 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
601 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
603 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
605 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
607 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
608 /* Configures the BW of any VF */
609 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
610 /* Queries the BW of any VF */
611 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
612 /* Queries pf ids belong to specified host(s) */
613 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
614 /* Queries extended stats per function */
615 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
616 /* Queries extended statistics context */
617 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
619 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
621 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
623 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
625 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
627 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
629 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
630 /* Returns the current value of a free running counter from the device. */
631 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
633 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
635 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
637 * Tells the fw to run the DMA read from the host and DMA write
640 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
641 /* Tells the fw to program the fru memory */
642 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
643 /* Tells the fw to read the fru memory */
644 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
646 #define HWRM_TF UINT32_C(0x2bc)
648 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
650 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
652 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
654 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
656 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
658 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
660 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
662 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
664 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
666 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
668 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
670 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
672 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
674 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
676 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
678 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
680 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
682 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
684 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
686 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
688 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
690 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
692 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
694 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
696 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
698 #define HWRM_SV UINT32_C(0x400)
700 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
702 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
704 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
706 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
707 #define HWRM_DBG_DUMP UINT32_C(0xff14)
709 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
711 #define HWRM_DBG_CFG UINT32_C(0xff16)
713 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
715 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
717 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
719 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
721 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
723 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
725 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
727 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
728 /* Send driver debug information to firmware */
729 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
730 /* Query debug capabilities of firmware */
731 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
732 /* Retrieve debug settings of firmware */
733 #define HWRM_DBG_QCFG UINT32_C(0xff21)
734 /* Set destination parameters for crashdump medium */
735 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
736 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
738 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
739 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
740 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
741 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
742 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
743 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
744 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
745 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
746 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
747 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
748 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
749 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
750 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
751 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
752 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
753 #define HWRM_NVM_READ UINT32_C(0xfffd)
754 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
755 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
756 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
757 uint16_t unused_0[3];
761 /* ret_codes (size:64b/8B) */
764 /* Request was successfully executed by the HWRM. */
765 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
766 /* The HWRM failed to execute the request. */
767 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
769 * The request contains invalid argument(s) or input
772 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
774 * The requester is not allowed to access the requested
775 * resource. This error code shall be provided in a
776 * response to a request to query or modify an existing
777 * resource that is not accessible by the requester.
779 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
781 * The HWRM is unable to allocate the requested resource.
782 * This code only applies to requests for HWRM resource
785 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
787 * Invalid combination of flags is specified in the
790 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
792 * Invalid combination of enables fields is specified in
795 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
797 * Request contains a required TLV that is not supported by
798 * the installed version of firmware.
800 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
802 * No firmware buffer available to accept the request. Driver
803 * should retry the request.
805 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
807 * This error code is only reported by firmware when some
808 * sub-option of a supported HWRM command is unsupported.
810 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
812 * This error code is only reported by firmware when the specific
813 * request is not able to process when the HOT reset in progress.
815 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
817 * This error code is only reported by firmware when the registered
818 * driver instances are not capable of hot reset.
820 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
822 * This error code is only reported by the firmware when during
823 * flow allocation when a request for a flow counter fails because
824 * the number of flow counters are exhausted.
826 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
828 * This error code is only reported by firmware when the registered
829 * driver instances requested to offloaded a flow but was unable to because
830 * the requested key's hash collides with the installed keys.
832 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
834 * This error code is only reported by firmware when the registered
835 * driver instances requested to offloaded a flow but was unable to because
836 * the same key has already been installed.
838 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
840 * Generic HWRM execution error that represents an
843 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
845 * Firmware is unable to service the request at the present time. Caller
846 * may try again later.
848 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
850 * This value indicates that the HWRM response is in TLV format and
851 * should be interpreted as one or more TLVs starting with the
852 * hwrm_resp_hdr TLV. This value is not an indication of any error
853 * by itself, just an indication that the response should be parsed
854 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
856 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
858 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
859 /* Unsupported or invalid command */
860 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
861 #define HWRM_ERR_CODE_LAST \
862 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
863 uint16_t unused_0[3];
867 /* hwrm_err_output (size:128b/16B) */
868 struct hwrm_err_output {
870 * Pass/Fail or error type
872 * Note: receiver to verify the in parameters, and fail the call
873 * with an error when appropriate
876 /* This field returns the type of original request. */
878 /* This field provides original sequence number of the command. */
881 * This field is the length of the response in bytes. The
882 * last byte of the response is a valid flag that will read
883 * as '1' when the command has been completely written to
887 /* debug info for this error response. */
889 /* debug info for this error response. */
892 * In the case of an error response, command specific error
893 * code is returned in this field.
897 * This field is used in Output records to indicate that the output
898 * is completely written to RAM. This field should be read as '1'
899 * to indicate that the output has been completely written.
900 * When writing a command completion or response to an internal processor,
901 * the order of writes has to be such that this field is written last.
906 * Following is the signature for HWRM message field that indicates not
907 * applicable (All F's). Need to cast it the size of the field if needed.
909 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
910 /* hwrm_func_buf_rgtr */
911 #define HWRM_MAX_REQ_LEN 128
912 /* hwrm_cfa_flow_info */
913 #define HWRM_MAX_RESP_LEN 704
914 /* 7 bit indirection table index. */
915 #define HW_HASH_INDEX_SIZE 0x80
916 #define HW_HASH_KEY_SIZE 40
917 /* valid key for HWRM response */
918 #define HWRM_RESP_VALID_KEY 1
919 /* Reserved for BONO processor */
920 #define HWRM_TARGET_ID_BONO 0xFFF8
921 /* Reserved for KONG processor */
922 #define HWRM_TARGET_ID_KONG 0xFFF9
923 /* Reserved for APE processor */
924 #define HWRM_TARGET_ID_APE 0xFFFA
926 * This value will be used by tools for User-space HWRM Interface.
927 * When tool execute any HWRM command with this target_id, firmware
928 * will copy the response and/or data payload via register space instead
931 #define HWRM_TARGET_ID_TOOLS 0xFFFD
932 #define HWRM_VERSION_MAJOR 1
933 #define HWRM_VERSION_MINOR 10
934 #define HWRM_VERSION_UPDATE 1
935 /* non-zero means beta version */
936 #define HWRM_VERSION_RSVD 45
937 #define HWRM_VERSION_STR "1.10.1.45"
944 /* hwrm_ver_get_input (size:192b/24B) */
945 struct hwrm_ver_get_input {
946 /* The HWRM command request type. */
949 * The completion ring to send the completion event on. This should
950 * be the NQ ID returned from the `nq_alloc` HWRM command.
954 * The sequence ID is used by the driver for tracking multiple
955 * commands. This ID is treated as opaque data by the firmware and
956 * the value is returned in the `hwrm_resp_hdr` upon completion.
960 * The target ID of the command:
961 * * 0x0-0xFFF8 - The function ID
962 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
963 * * 0xFFFD - Reserved for user-space HWRM interface
968 * A physical address pointer pointing to a host buffer that the
969 * command's response data will be written. This can be either a host
970 * physical address (HPA) or a guest physical address (GPA) and must
971 * point to a physically contiguous block of memory.
975 * This field represents the major version of HWRM interface
976 * specification supported by the driver HWRM implementation.
977 * The interface major version is intended to change only when
978 * non backward compatible changes are made to the HWRM
979 * interface specification.
981 uint8_t hwrm_intf_maj;
983 * This field represents the minor version of HWRM interface
984 * specification supported by the driver HWRM implementation.
985 * A change in interface minor version is used to reflect
986 * significant backward compatible modification to HWRM
987 * interface specification.
988 * This can be due to addition or removal of functionality.
989 * HWRM interface specifications with the same major version
990 * but different minor versions are compatible.
992 uint8_t hwrm_intf_min;
994 * This field represents the update version of HWRM interface
995 * specification supported by the driver HWRM implementation.
996 * The interface update version is used to reflect minor
997 * changes or bug fixes to a released HWRM interface
1000 uint8_t hwrm_intf_upd;
1001 uint8_t unused_0[5];
1004 /* hwrm_ver_get_output (size:1408b/176B) */
1005 struct hwrm_ver_get_output {
1006 /* The specific error status for the command. */
1007 uint16_t error_code;
1008 /* The HWRM command request type. */
1010 /* The sequence ID from the original command. */
1012 /* The length of the response data in number of bytes. */
1015 * This field represents the major version of HWRM interface
1016 * specification supported by the HWRM implementation.
1017 * The interface major version is intended to change only when
1018 * non backward compatible changes are made to the HWRM
1019 * interface specification.
1020 * A HWRM implementation that is compliant with this
1021 * specification shall provide value of 1 in this field.
1023 uint8_t hwrm_intf_maj_8b;
1025 * This field represents the minor version of HWRM interface
1026 * specification supported by the HWRM implementation.
1027 * A change in interface minor version is used to reflect
1028 * significant backward compatible modification to HWRM
1029 * interface specification.
1030 * This can be due to addition or removal of functionality.
1031 * HWRM interface specifications with the same major version
1032 * but different minor versions are compatible.
1033 * A HWRM implementation that is compliant with this
1034 * specification shall provide value of 2 in this field.
1036 uint8_t hwrm_intf_min_8b;
1038 * This field represents the update version of HWRM interface
1039 * specification supported by the HWRM implementation.
1040 * The interface update version is used to reflect minor
1041 * changes or bug fixes to a released HWRM interface
1043 * A HWRM implementation that is compliant with this
1044 * specification shall provide value of 2 in this field.
1046 uint8_t hwrm_intf_upd_8b;
1047 uint8_t hwrm_intf_rsvd_8b;
1049 * This field represents the major version of HWRM firmware.
1050 * A change in firmware major version represents a major
1053 uint8_t hwrm_fw_maj_8b;
1055 * This field represents the minor version of HWRM firmware.
1056 * A change in firmware minor version represents significant
1057 * firmware functionality changes.
1059 uint8_t hwrm_fw_min_8b;
1061 * This field represents the build version of HWRM firmware.
1062 * A change in firmware build version represents bug fixes
1063 * to a released firmware.
1065 uint8_t hwrm_fw_bld_8b;
1067 * This field is a reserved field. This field can be used to
1068 * represent firmware branches or customer specific releases
1069 * tied to a specific (major,minor,update) version of the
1072 uint8_t hwrm_fw_rsvd_8b;
1074 * This field represents the major version of mgmt firmware.
1075 * A change in major version represents a major release.
1077 uint8_t mgmt_fw_maj_8b;
1079 * This field represents the minor version of mgmt firmware.
1080 * A change in minor version represents significant
1081 * functionality changes.
1083 uint8_t mgmt_fw_min_8b;
1085 * This field represents the build version of mgmt firmware.
1086 * A change in update version represents bug fixes.
1088 uint8_t mgmt_fw_bld_8b;
1090 * This field is a reserved field. This field can be used to
1091 * represent firmware branches or customer specific releases
1092 * tied to a specific (major,minor,update) version
1094 uint8_t mgmt_fw_rsvd_8b;
1096 * This field represents the major version of network
1098 * A change in major version represents a major release.
1100 uint8_t netctrl_fw_maj_8b;
1102 * This field represents the minor version of network
1104 * A change in minor version represents significant
1105 * functionality changes.
1107 uint8_t netctrl_fw_min_8b;
1109 * This field represents the build version of network
1111 * A change in update version represents bug fixes.
1113 uint8_t netctrl_fw_bld_8b;
1115 * This field is a reserved field. This field can be used to
1116 * represent firmware branches or customer specific releases
1117 * tied to a specific (major,minor,update) version
1119 uint8_t netctrl_fw_rsvd_8b;
1121 * This field is used to indicate device's capabilities and
1124 uint32_t dev_caps_cfg;
1126 * If set to 1, then secure firmware update behavior
1128 * If set to 0, then secure firmware update behavior is
1131 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1134 * If set to 1, then firmware based DCBX agent is supported.
1135 * If set to 0, then firmware based DCBX agent capability
1136 * is not supported on this device.
1138 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1141 * If set to 1, then HWRM short command format is supported.
1142 * If set to 0, then HWRM short command format is not supported.
1144 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1147 * If set to 1, then HWRM short command format is required.
1148 * If set to 0, then HWRM short command format is not required.
1150 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1153 * If set to 1, then the KONG host mailbox channel is supported.
1154 * If set to 0, then the KONG host mailbox channel is not supported.
1155 * By default, this flag should be 0 for older version of core firmware.
1157 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1160 * If set to 1, then the 64bit flow handle is supported in addition to the
1161 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1162 * supported. By default, this flag should be 0 for older version of core firmware.
1164 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1167 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1168 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1169 * If set to 0, then filter types not supported.
1170 * By default, this flag should be 0 for older version of core firmware.
1172 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1175 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1176 * If set to 0, firmware can't supported virtio vSwitch offload model.
1177 * By default, this flag should be 0 for older version of core firmware.
1179 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1182 * If set to 1, firmware is capable to support trusted VF.
1183 * If set to 0, firmware is not capable to support trusted VF.
1184 * By default, this flag should be 0 for older version of core firmware.
1186 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1189 * If set to 1, firmware is capable to support flow aging.
1190 * If set to 0, firmware is not capable to support flow aging.
1191 * By default, this flag should be 0 for older version of core firmware.
1193 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1196 * If set to 1, firmware is capable to support advanced flow counters like,
1197 * Meter drop counters and EEM counters.
1198 * If set to 0, firmware is not capable to support advanced flow counters.
1199 * By default, this flag should be 0 for older version of core firmware.
1201 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1204 * If set to 1, the firmware is able to support the use of the CFA
1205 * Extended Exact Match(EEM) feature.
1206 * If set to 0, firmware is not capable to support the use of the
1208 * By default, this flag should be 0 for older version of core firmware.
1210 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1213 * If set to 1, the firmware is able to support advance CFA flow management
1214 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1215 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1217 * By default, this flag should be 0 for older version of core firmware.
1219 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1222 * Deprecated and replaced with cfa_truflow_supported.
1223 * If set to 1, the firmware is able to support TFLIB features.
1224 * If set to 0, then the firmware doesn’t support TFLIB features.
1225 * By default, this flag should be 0 for older version of core firmware.
1227 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1230 * If set to 1, the firmware is able to support TruFlow features.
1231 * If set to 0, then the firmware doesn’t support TruFlow features.
1232 * By default, this flag should be 0 for older version of
1235 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1238 * This field represents the major version of RoCE firmware.
1239 * A change in major version represents a major release.
1241 uint8_t roce_fw_maj_8b;
1243 * This field represents the minor version of RoCE firmware.
1244 * A change in minor version represents significant
1245 * functionality changes.
1247 uint8_t roce_fw_min_8b;
1249 * This field represents the build version of RoCE firmware.
1250 * A change in update version represents bug fixes.
1252 uint8_t roce_fw_bld_8b;
1254 * This field is a reserved field. This field can be used to
1255 * represent firmware branches or customer specific releases
1256 * tied to a specific (major,minor,update) version
1258 uint8_t roce_fw_rsvd_8b;
1260 * This field represents the name of HWRM FW (ASCII chars
1261 * with NULL at the end).
1263 char hwrm_fw_name[16];
1265 * This field represents the name of mgmt FW (ASCII chars
1266 * with NULL at the end).
1268 char mgmt_fw_name[16];
1270 * This field represents the name of network control
1271 * firmware (ASCII chars with NULL at the end).
1273 char netctrl_fw_name[16];
1274 /* This field represents the active board package name. */
1275 char active_pkg_name[16];
1277 * This field represents the name of RoCE FW (ASCII chars
1278 * with NULL at the end).
1280 char roce_fw_name[16];
1281 /* This field returns the chip number. */
1283 /* This field returns the revision of chip. */
1285 /* This field returns the chip metal number. */
1287 /* This field returns the bond id of the chip. */
1288 uint8_t chip_bond_id;
1289 /* This value indicates the type of platform used for chip implementation. */
1290 uint8_t chip_platform_type;
1292 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1293 /* FPGA platform of the chip. */
1294 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1295 /* Palladium platform of the chip. */
1296 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1297 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1298 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1300 * This field returns the maximum value of request window that
1301 * is supported by the HWRM. The request window is mapped
1302 * into device address space using MMIO.
1304 uint16_t max_req_win_len;
1306 * This field returns the maximum value of response buffer in
1309 uint16_t max_resp_len;
1311 * This field returns the default request timeout value in
1314 uint16_t def_req_timeout;
1316 * This field will indicate if any subsystems is not fully
1321 * If set to 1, it will indicate to host drivers that firmware is
1322 * not ready to start full blown HWRM commands. Host drivers should
1323 * re-try HWRM_VER_GET with some timeout period. The timeout period
1324 * can be selected up to 5 seconds.
1325 * For Example, PCIe hot-plug:
1326 * Hot plug timing is system dependent. It generally takes up to
1327 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1328 * If set to 0, device is ready to accept all HWRM commands.
1330 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1332 * If set to 1, external version present.
1333 * If set to 0, external version not present.
1335 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1336 uint8_t unused_0[2];
1338 * For backward compatibility this field must be set to 1.
1339 * Older drivers might look for this field to be 1 before
1340 * processing the message.
1344 * This field represents the major version of HWRM interface
1345 * specification supported by the HWRM implementation.
1346 * The interface major version is intended to change only when
1347 * non backward compatible changes are made to the HWRM
1348 * interface specification. A HWRM implementation that is
1349 * compliant with this specification shall provide value of 1
1352 uint16_t hwrm_intf_major;
1354 * This field represents the minor version of HWRM interface
1355 * specification supported by the HWRM implementation.
1356 * A change in interface minor version is used to reflect
1357 * significant backward compatible modification to HWRM
1358 * interface specification. This can be due to addition or
1359 * removal of functionality. HWRM interface specifications
1360 * with the same major version but different minor versions are
1361 * compatible. A HWRM implementation that is compliant with
1362 * this specification shall provide value of 2 in this field.
1364 uint16_t hwrm_intf_minor;
1366 * This field represents the update version of HWRM interface
1367 * specification supported by the HWRM implementation. The
1368 * interface update version is used to reflect minor changes or
1369 * bug fixes to a released HWRM interface specification.
1370 * A HWRM implementation that is compliant with this
1371 * specification shall provide value of 2 in this field.
1373 uint16_t hwrm_intf_build;
1375 * This field represents the patch version of HWRM interface
1376 * specification supported by the HWRM implementation.
1378 uint16_t hwrm_intf_patch;
1380 * This field represents the major version of HWRM firmware.
1381 * A change in firmware major version represents a major
1384 uint16_t hwrm_fw_major;
1386 * This field represents the minor version of HWRM firmware.
1387 * A change in firmware minor version represents significant
1388 * firmware functionality changes.
1390 uint16_t hwrm_fw_minor;
1392 * This field represents the build version of HWRM firmware.
1393 * A change in firmware build version represents bug fixes to
1394 * a released firmware.
1396 uint16_t hwrm_fw_build;
1398 * This field is a reserved field.
1399 * This field can be used to represent firmware branches or customer
1400 * specific releases tied to a specific (major,minor,update) version
1401 * of the HWRM firmware.
1403 uint16_t hwrm_fw_patch;
1405 * This field represents the major version of mgmt firmware.
1406 * A change in major version represents a major release.
1408 uint16_t mgmt_fw_major;
1410 * This field represents the minor version of HWRM firmware.
1411 * A change in firmware minor version represents significant
1412 * firmware functionality changes.
1414 uint16_t mgmt_fw_minor;
1416 * This field represents the build version of mgmt firmware.
1417 * A change in update version represents bug fixes.
1419 uint16_t mgmt_fw_build;
1421 * This field is a reserved field. This field can be used to
1422 * represent firmware branches or customer specific releases
1423 * tied to a specific (major,minor,update) version.
1425 uint16_t mgmt_fw_patch;
1427 * This field represents the major version of network control
1428 * firmware. A change in major version represents
1431 uint16_t netctrl_fw_major;
1433 * This field represents the minor version of network control
1434 * firmware. A change in minor version represents significant
1435 * functionality changes.
1437 uint16_t netctrl_fw_minor;
1439 * This field represents the build version of network control
1440 * firmware. A change in update version represents bug fixes.
1442 uint16_t netctrl_fw_build;
1444 * This field is a reserved field. This field can be used to
1445 * represent firmware branches or customer specific releases
1446 * tied to a specific (major,minor,update) version
1448 uint16_t netctrl_fw_patch;
1450 * This field represents the major version of RoCE firmware.
1451 * A change in major version represents a major release.
1453 uint16_t roce_fw_major;
1455 * This field represents the minor version of RoCE firmware.
1456 * A change in minor version represents significant
1457 * functionality changes.
1459 uint16_t roce_fw_minor;
1461 * This field represents the build version of RoCE firmware.
1462 * A change in update version represents bug fixes.
1464 uint16_t roce_fw_build;
1466 * This field is a reserved field. This field can be used to
1467 * represent firmware branches or customer specific releases
1468 * tied to a specific (major,minor,update) version
1470 uint16_t roce_fw_patch;
1472 * This field returns the maximum extended request length acceptable
1473 * by the device which allows requests greater than mailbox size when
1474 * used with the short cmd request format.
1476 uint16_t max_ext_req_len;
1477 uint8_t unused_1[5];
1479 * This field is used in Output records to indicate that the output
1480 * is completely written to RAM. This field should be read as '1'
1481 * to indicate that the output has been completely written.
1482 * When writing a command completion or response to an internal processor,
1483 * the order of writes has to be such that this field is written last.
1488 /* bd_base (size:64b/8B) */
1491 /* This value identifies the type of buffer descriptor. */
1492 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1493 #define BD_BASE_TYPE_SFT 0
1495 * Indicates that this BD is 16B long and is used for
1496 * normal L2 packet transmission.
1498 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1500 * Indicates that this BD is 1BB long and is an empty
1501 * TX BD. Not valid for use by the driver.
1503 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1505 * Indicates that this BD is 16B long and is an RX Producer
1506 * (i.e. empty) buffer descriptor.
1508 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1510 * Indicates that this BD is 16B long and is an RX
1511 * Producer Buffer BD.
1513 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1515 * Indicates that this BD is 16B long and is an
1516 * RX Producer Assembly Buffer Descriptor.
1518 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1520 * Indicates that this BD is 32B long and is used for
1521 * normal L2 packet transmission.
1523 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1525 * Indicates that this BD is 32B long and is used for
1526 * L2 packet transmission for small packets that require
1529 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1530 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1531 uint8_t unused_1[7];
1534 /* tx_bd_short (size:128b/16B) */
1535 struct tx_bd_short {
1537 * All bits in this field must be valid on the first BD of a packet.
1538 * Only the packet_end bit must be valid for the remaining BDs
1541 uint16_t flags_type;
1542 /* This value identifies the type of buffer descriptor. */
1543 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1544 #define TX_BD_SHORT_TYPE_SFT 0
1546 * Indicates that this BD is 16B long and is used for
1547 * normal L2 packet transmission.
1549 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1550 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1552 * All bits in this field must be valid on the first BD of a packet.
1553 * Only the packet_end bit must be valid for the remaining BDs
1556 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1557 #define TX_BD_SHORT_FLAGS_SFT 6
1559 * If set to 1, the packet ends with the data in the buffer
1560 * pointed to by this descriptor. This flag must be
1561 * valid on every BD.
1563 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1565 * If set to 1, the device will not generate a completion for
1566 * this transmit packet unless there is an error in it's
1569 * is set to 0, then the packet will be completed normally.
1571 * This bit must be valid only on the first BD of a packet.
1573 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1575 * This value indicates how many 16B BD locations are consumed
1576 * in the ring by this packet.
1577 * A value of 1 indicates that this BD is the only BD (and that
1578 * it is a short BD). A value
1579 * of 3 indicates either 3 short BDs or 1 long BD and one short
1580 * BD in the packet. A value of 0 indicates
1581 * that there are 32 BD locations in the packet (the maximum).
1583 * This field is valid only on the first BD of a packet.
1585 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1586 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1588 * This value is a hint for the length of the entire packet.
1589 * It is used by the chip to optimize internal processing.
1591 * The packet will be dropped if the hint is too short.
1593 * This field is valid only on the first BD of a packet.
1595 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1596 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1597 /* indicates packet length < 512B */
1598 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1599 /* indicates 512 <= packet length < 1KB */
1600 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1601 /* indicates 1KB <= packet length < 2KB */
1602 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1603 /* indicates packet length >= 2KB */
1604 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1605 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1606 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1608 * If set to 1, the device immediately updates the Send Consumer
1609 * Index after the buffer associated with this descriptor has
1610 * been transferred via DMA to NIC memory from host memory. An
1611 * interrupt may or may not be generated according to the state
1612 * of the interrupt avoidance mechanisms. If this bit
1613 * is set to 0, then the Consumer Index is only updated as soon
1614 * as one of the host interrupt coalescing conditions has been met.
1616 * This bit must be valid on the first BD of a packet.
1618 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1620 * This is the length of the host physical buffer this BD describes
1623 * This field must be valid on all BDs of a packet.
1627 * The opaque data field is pass through to the completion and can be
1628 * used for any data that the driver wants to associate with the
1631 * This field must be valid on the first BD of a packet.
1635 * This is the host physical address for the portion of the packet
1636 * described by this TX BD.
1638 * This value must be valid on all BDs of a packet.
1643 /* tx_bd_long (size:128b/16B) */
1645 /* This value identifies the type of buffer descriptor. */
1646 uint16_t flags_type;
1648 * This value indicates the type of buffer descriptor.
1651 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1652 #define TX_BD_LONG_TYPE_SFT 0
1654 * Indicates that this BD is 32B long and is used for
1655 * normal L2 packet transmission.
1657 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1658 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1660 * All bits in this field must be valid on the first BD of a packet.
1661 * Only the packet_end bit must be valid for the remaining BDs
1664 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1665 #define TX_BD_LONG_FLAGS_SFT 6
1667 * If set to 1, the packet ends with the data in the buffer
1668 * pointed to by this descriptor. This flag must be
1669 * valid on every BD.
1671 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1673 * If set to 1, the device will not generate a completion for
1674 * this transmit packet unless there is an error in it's
1677 * is set to 0, then the packet will be completed normally.
1679 * This bit must be valid only on the first BD of a packet.
1681 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1683 * This value indicates how many 16B BD locations are consumed
1684 * in the ring by this packet.
1685 * A value of 1 indicates that this BD is the only BD (and that
1686 * it is a short BD). A value
1687 * of 3 indicates either 3 short BDs or 1 long BD and one short
1688 * BD in the packet. A value of 0 indicates
1689 * that there are 32 BD locations in the packet (the maximum).
1691 * This field is valid only on the first BD of a packet.
1693 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1694 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1696 * This value is a hint for the length of the entire packet.
1697 * It is used by the chip to optimize internal processing.
1699 * The packet will be dropped if the hint is too short.
1701 * This field is valid only on the first BD of a packet.
1703 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1704 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1705 /* indicates packet length < 512B */
1706 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1707 /* indicates 512 <= packet length < 1KB */
1708 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1709 /* indicates 1KB <= packet length < 2KB */
1710 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1711 /* indicates packet length >= 2KB */
1712 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1713 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1715 * If set to 1, the device immediately updates the Send Consumer
1716 * Index after the buffer associated with this descriptor has
1717 * been transferred via DMA to NIC memory from host memory. An
1718 * interrupt may or may not be generated according to the state
1719 * of the interrupt avoidance mechanisms. If this bit
1720 * is set to 0, then the Consumer Index is only updated as soon
1721 * as one of the host interrupt coalescing conditions has been met.
1723 * This bit must be valid on the first BD of a packet.
1725 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1727 * This is the length of the host physical buffer this BD describes
1730 * This field must be valid on all BDs of a packet.
1734 * The opaque data field is pass through to the completion and can be
1735 * used for any data that the driver wants to associate with the
1738 * This field must be valid on the first BD of a packet.
1742 * This is the host physical address for the portion of the packet
1743 * described by this TX BD.
1745 * This value must be valid on all BDs of a packet.
1750 /* Last 16 bytes of tx_bd_long. */
1751 /* tx_bd_long_hi (size:128b/16B) */
1752 struct tx_bd_long_hi {
1754 * All bits in this field must be valid on the first BD of a packet.
1755 * Their value on other BDs of the packet will be ignored.
1759 * If set to 1, the controller replaces the TCP/UPD checksum
1760 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1761 * checksum field of the encapsulated TCP/UDP packets with the
1762 * hardware calculated TCP/UDP checksum for the packet associated
1763 * with this descriptor. The flag is ignored if the LSO flag is set.
1765 * This bit must be valid on the first BD of a packet.
1767 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1769 * If set to 1, the controller replaces the IP checksum of the
1770 * normal packets, or the inner IP checksum of the encapsulated
1771 * packets with the hardware calculated IP checksum for the
1772 * packet associated with this descriptor.
1774 * This bit must be valid on the first BD of a packet.
1776 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1778 * If set to 1, the controller will not append an Ethernet CRC
1779 * to the end of the frame.
1781 * This bit must be valid on the first BD of a packet.
1783 * Packet must be 64B or longer when this flag is set. It is not
1784 * useful to use this bit with any form of TX offload such as
1785 * CSO or LSO. The intent is that the packet from the host already
1786 * has a valid Ethernet CRC on the packet.
1788 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1790 * If set to 1, the device will record the time at which the packet
1791 * was actually transmitted at the TX MAC.
1793 * This bit must be valid on the first BD of a packet.
1795 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1797 * If set to 1, The controller replaces the tunnel IP checksum
1798 * field with hardware calculated IP checksum for the IP header
1799 * of the packet associated with this descriptor.
1801 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1802 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1803 * bit is set, outer UDP checksum will be calculated for the following
1805 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1806 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1807 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1808 * checksum will not be calculated.
1809 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1810 * as part of LSO operation.
1812 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1814 * If set to 1, the device will treat this packet with LSO(Large
1815 * Send Offload) processing for both normal or encapsulated
1816 * packets, which is a form of TCP segmentation. When this bit
1817 * is 1, the hdr_size and mss fields must be valid. The driver
1818 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1819 * flags since the controller will replace the appropriate
1820 * checksum fields for segmented packets.
1822 * When this bit is 1, the hdr_size and mss fields must be valid.
1824 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1826 * If set to zero when LSO is '1', then the IPID will be treated
1827 * as a 16b number and will be wrapped if it exceeds a value of
1830 * If set to one when LSO is '1', then the IPID will be treated
1831 * as a 15b number and will be wrapped if it exceeds a value 0f
1834 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1836 * If set to zero when LSO is '1', then the IPID of the tunnel
1837 * IP header will not be modified during LSO operations.
1839 * If set to one when LSO is '1', then the IPID of the tunnel
1840 * IP header will be incremented for each subsequent segment of an
1843 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1846 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1848 * If set to '1', then the RoCE ICRC will be appended to the
1849 * packet. Packet must be a valid RoCE format packet.
1851 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1853 * If set to '1', then the FCoE CRC will be appended to the
1854 * packet. Packet must be a valid FCoE format packet.
1856 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1859 * When LSO is '1', this field must contain the offset of the
1860 * TCP payload from the beginning of the packet in as
1861 * 16b words. In case of encapsulated/tunneling packet, this field
1862 * contains the offset of the inner TCP payload from beginning of the
1863 * packet as 16-bit words.
1865 * This value must be valid on the first BD of a packet.
1867 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1868 #define TX_BD_LONG_HDR_SIZE_SFT 0
1871 * This is the MSS value that will be used to do the LSO processing.
1872 * The value is the length in bytes of the TCP payload for each
1873 * segment generated by the LSO operation.
1875 * This value must be valid on the first BD of a packet.
1877 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1878 #define TX_BD_LONG_MSS_SFT 0
1881 * This value selects a CFA action to perform on the packet.
1882 * Set this value to zero if no CFA action is desired.
1884 * This value must be valid on the first BD of a packet.
1886 uint16_t cfa_action;
1888 * This value is action meta-data that defines CFA edit operations
1889 * that are done in addition to any action editing.
1892 /* When key=1, This is the VLAN tag VID value. */
1893 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1894 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1895 /* When key=1, This is the VLAN tag DE value. */
1896 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1897 /* When key=1, This is the VLAN tag PRI value. */
1898 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1899 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1900 /* When key=1, This is the VLAN tag TPID select value. */
1901 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1902 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1904 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1906 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1908 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1910 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1912 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1913 /* Value programmed in CFA VLANTPID register. */
1914 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1915 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1916 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1917 /* When key=1, This is the VLAN tag TPID select value. */
1918 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1919 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1921 * This field identifies the type of edit to be performed
1924 * This value must be valid on the first BD of a packet.
1926 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1927 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1929 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1931 * - meta[17:16] - TPID select value (0 = 0x8100).
1932 * - meta[15:12] - PRI/DE value.
1933 * - meta[11:0] - VID value.
1935 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1936 #define TX_BD_LONG_CFA_META_KEY_LAST \
1937 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1941 * This structure is used to inform the NIC of packet data that needs to be
1942 * transmitted with additional processing that requires extra data such as
1943 * VLAN insertion plus attached inline data. This BD type may be used to
1944 * improve latency for small packets needing the additional extended features
1945 * supported by long BDs.
1947 /* tx_bd_long_inline (size:256b/32B) */
1948 struct tx_bd_long_inline {
1949 uint16_t flags_type;
1950 /* This value identifies the type of buffer descriptor. */
1951 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1952 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1954 * This type of BD is 32B long and is used for inline L2 packet
1957 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1958 #define TX_BD_LONG_INLINE_TYPE_LAST \
1959 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1961 * All bits in this field may be set on the first BD of a packet.
1962 * Only the packet_end bit may be set in non-first BDs.
1964 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1965 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1967 * If set to 1, the packet ends with the data in the buffer
1968 * pointed to by this descriptor. This flag must be
1969 * valid on every BD.
1971 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1973 * If set to 1, the device will not generate a completion for
1974 * this transmit packet unless there is an error in its processing.
1975 * If this bit is set to 0, then the packet will be completed
1978 * This bit may be set only on the first BD of a packet.
1980 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1982 * This value indicates how many 16B BD locations are consumed
1983 * in the ring by this packet, including the BD and inline
1986 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1987 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1988 /* This field is deprecated. */
1989 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1990 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1992 * If set to 1, the device immediately updates the Send Consumer
1993 * Index after the buffer associated with this descriptor has
1994 * been transferred via DMA to NIC memory from host memory. An
1995 * interrupt may or may not be generated according to the state
1996 * of the interrupt avoidance mechanisms. If this bit
1997 * is set to 0, then the Consumer Index is only updated as soon
1998 * as one of the host interrupt coalescing conditions has been met.
2000 * This bit must be valid on the first BD of a packet.
2002 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2004 * This is the length of the inline data, not including BD length, in
2006 * The maximum value is 480.
2008 * This field must be valid on all BDs of a packet.
2012 * The opaque data field is passed through to the completion and can be
2013 * used for any data that the driver wants to associate with the transmit
2016 * This field must be valid on the first BD of a packet.
2021 * All bits in this field must be valid on the first BD of a packet.
2022 * Their value on other BDs of the packet is ignored.
2026 * If set to 1, the controller replaces the TCP/UPD checksum
2027 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2028 * checksum field of the encapsulated TCP/UDP packets with the
2029 * hardware calculated TCP/UDP checksum for the packet associated
2030 * with this descriptor. The flag is ignored if the LSO flag is set.
2032 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2034 * If set to 1, the controller replaces the IP checksum of the
2035 * normal packets, or the inner IP checksum of the encapsulated
2036 * packets with the hardware calculated IP checksum for the
2037 * packet associated with this descriptor.
2039 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2041 * If set to 1, the controller will not append an Ethernet CRC
2042 * to the end of the frame.
2044 * Packet must be 64B or longer when this flag is set. It is not
2045 * useful to use this bit with any form of TX offload such as
2046 * CSO or LSO. The intent is that the packet from the host already
2047 * has a valid Ethernet CRC on the packet.
2049 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2051 * If set to 1, the device will record the time at which the packet
2052 * was actually transmitted at the TX MAC.
2054 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2056 * If set to 1, the controller replaces the tunnel IP checksum
2057 * field with hardware calculated IP checksum for the IP header
2058 * of the packet associated with this descriptor. The hardware
2059 * updates an outer UDP checksum if it is non-zero.
2061 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2063 * This bit must be 0 for BDs of this type. LSO is not supported with
2066 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2067 /* Since LSO is not supported with inline BDs, this bit is not used. */
2068 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2069 /* Since LSO is not supported with inline BDs, this bit is not used. */
2070 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2072 * If set to '1', then the RoCE ICRC will be appended to the
2073 * packet. Packet must be a valid RoCE format packet.
2075 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2077 * If set to '1', then the FCoE CRC will be appended to the
2078 * packet. Packet must be a valid FCoE format packet.
2080 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2085 * This value selects a CFA action to perform on the packet.
2086 * Set this value to zero if no CFA action is desired.
2088 * This value must be valid on the first BD of a packet.
2090 uint16_t cfa_action;
2092 * This value is action meta-data that defines CFA edit operations
2093 * that are done in addition to any action editing.
2096 /* When key = 1, this is the VLAN tag VID value. */
2097 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2098 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2099 /* When key = 1, this is the VLAN tag DE value. */
2100 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2101 /* When key = 1, this is the VLAN tag PRI value. */
2102 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2103 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2104 /* When key = 1, this is the VLAN tag TPID select value. */
2105 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2106 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2108 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2109 (UINT32_C(0x0) << 16)
2111 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2112 (UINT32_C(0x1) << 16)
2114 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2115 (UINT32_C(0x2) << 16)
2117 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2118 (UINT32_C(0x3) << 16)
2120 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2121 (UINT32_C(0x4) << 16)
2122 /* Value programmed in CFA VLANTPID register. */
2123 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2124 (UINT32_C(0x5) << 16)
2125 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2126 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2127 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2129 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2131 * This field identifies the type of edit to be performed
2134 * This value must be valid on the first BD of a packet.
2136 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2137 UINT32_C(0xf0000000)
2138 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2140 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2141 (UINT32_C(0x0) << 28)
2143 * - meta[17:16] - TPID select value (0 = 0x8100).
2144 * - meta[15:12] - PRI/DE value.
2145 * - meta[11:0] - VID value.
2147 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2148 (UINT32_C(0x1) << 28)
2149 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2150 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2153 /* tx_bd_empty (size:128b/16B) */
2154 struct tx_bd_empty {
2155 /* This value identifies the type of buffer descriptor. */
2157 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2158 #define TX_BD_EMPTY_TYPE_SFT 0
2160 * Indicates that this BD is 1BB long and is an empty
2161 * TX BD. Not valid for use by the driver.
2163 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2164 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2165 uint8_t unused_1[3];
2167 uint8_t unused_3[3];
2168 uint8_t unused_4[8];
2171 /* rx_prod_pkt_bd (size:128b/16B) */
2172 struct rx_prod_pkt_bd {
2173 /* This value identifies the type of buffer descriptor. */
2174 uint16_t flags_type;
2175 /* This value identifies the type of buffer descriptor. */
2176 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2177 #define RX_PROD_PKT_BD_TYPE_SFT 0
2179 * Indicates that this BD is 16B long and is an RX Producer
2180 * (i.e. empty) buffer descriptor.
2182 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2183 #define RX_PROD_PKT_BD_TYPE_LAST \
2184 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2185 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2186 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2188 * If set to 1, the packet will be placed at the address plus
2189 * 2B. The 2 Bytes of padding will be written as zero.
2191 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2193 * If set to 1, the packet write will be padded out to the
2194 * nearest cache-line with zero value padding.
2196 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2198 * This value is the number of additional buffers in the ring that
2199 * describe the buffer space to be consumed for this packet.
2200 * If the value is zero, then the packet must fit within the
2201 * space described by this BD. If this value is 1 or more, it
2202 * indicates how many additional "buffer" BDs are in the ring
2203 * immediately following this BD to be used for the same
2206 * Even if the packet to be placed does not need all the
2207 * additional buffers, they will be consumed anyway.
2209 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2210 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2212 * This is the length in Bytes of the host physical buffer where
2213 * data for the packet may be placed in host memory.
2217 * The opaque data field is pass through to the completion and can be
2218 * used for any data that the driver wants to associate with this
2219 * receive buffer set.
2223 * This is the host physical address where data for the packet may
2224 * be placed in host memory.
2229 /* rx_prod_bfr_bd (size:128b/16B) */
2230 struct rx_prod_bfr_bd {
2231 /* This value identifies the type of buffer descriptor. */
2232 uint16_t flags_type;
2233 /* This value identifies the type of buffer descriptor. */
2234 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2235 #define RX_PROD_BFR_BD_TYPE_SFT 0
2237 * Indicates that this BD is 16B long and is an RX
2238 * Producer Buffer BD.
2240 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2241 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2242 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2243 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2245 * This is the length in Bytes of the host physical buffer where
2246 * data for the packet may be placed in host memory.
2249 /* This field is not used. */
2252 * This is the host physical address where data for the packet may
2253 * be placed in host memory.
2258 /* rx_prod_agg_bd (size:128b/16B) */
2259 struct rx_prod_agg_bd {
2260 /* This value identifies the type of buffer descriptor. */
2261 uint16_t flags_type;
2262 /* This value identifies the type of buffer descriptor. */
2263 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2264 #define RX_PROD_AGG_BD_TYPE_SFT 0
2266 * Indicates that this BD is 16B long and is an
2267 * RX Producer Assembly Buffer Descriptor.
2269 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2270 #define RX_PROD_AGG_BD_TYPE_LAST \
2271 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2272 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2273 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2275 * If set to 1, the packet write will be padded out to the
2276 * nearest cache-line with zero value padding.
2278 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2280 * This is the length in Bytes of the host physical buffer where
2281 * data for the packet may be placed in host memory.
2285 * The opaque data field is pass through to the completion and can be
2286 * used for any data that the driver wants to associate with this
2287 * receive assembly buffer.
2291 * This is the host physical address where data for the packet may
2292 * be placed in host memory.
2297 /* cmpl_base (size:128b/16B) */
2301 * This field indicates the exact type of the completion.
2302 * By convention, the LSB identifies the length of the
2303 * record in 16B units. Even values indicate 16B
2304 * records. Odd values indicate 32B
2307 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2308 #define CMPL_BASE_TYPE_SFT 0
2311 * Completion of TX packet. Length = 16B
2313 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2316 * Completion of NO-OP. Length = 16B
2318 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
2320 * TX L2 coalesced completion:
2321 * Completion of coalesced TX packet. Length = 16B
2323 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
2325 * TX L2 PTP completion:
2326 * Completion of PTP TX packet. Length = 32B
2328 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
2330 * RX L2 TPA Start V2 Completion:
2331 * Completion of and L2 RX packet. Length = 32B
2332 * This is the new version of the RX_TPA_START completion used
2333 * in SR2 and later chips.
2335 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
2337 * RX L2 V2 completion:
2338 * Completion of and L2 RX packet. Length = 32B
2339 * This is the new version of the RX_L2 completion used in SR2
2342 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
2345 * Completion of and L2 RX packet. Length = 32B
2347 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2349 * RX Aggregation Buffer completion :
2350 * Completion of an L2 aggregation buffer in support of
2351 * TPA, HDS, or Jumbo packet completion. Length = 16B
2353 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2355 * RX L2 TPA Start Completion:
2356 * Completion at the beginning of a TPA operation.
2359 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2361 * RX L2 TPA End Completion:
2362 * Completion at the end of a TPA operation.
2365 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2367 * Statistics Ejection Completion:
2368 * Completion of statistics data ejection buffer.
2371 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2373 * VEE Flush Completion:
2374 * This completion is inserted manually by
2375 * the Primate and processed by the VEE hardware to ensure that
2376 * all completions on a VEE function have been processed by the
2377 * VEE hardware before FLR process is completed.
2379 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
2381 * Mid Path Short Completion :
2382 * Completion of a Mid Path Command. Length = 16B
2384 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
2386 * Mid Path Long Completion :
2387 * Completion of a Mid Path Command. Length = 32B
2389 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
2391 * HWRM Command Completion:
2392 * Completion of an HWRM command.
2394 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2395 /* Forwarded HWRM Request */
2396 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2397 /* Forwarded HWRM Response */
2398 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2399 /* HWRM Asynchronous Event Information */
2400 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2401 /* CQ Notification */
2402 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2403 /* SRQ Threshold Event */
2404 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2405 /* DBQ Threshold Event */
2406 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2407 /* QP Async Notification */
2408 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2409 /* Function Async Notification */
2410 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2411 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2417 * This value is written by the NIC such that it will be different
2418 * for each pass through the completion queue. The even passes
2419 * will write 1. The odd passes will write 0.
2422 #define CMPL_BASE_V UINT32_C(0x1)
2423 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2424 #define CMPL_BASE_INFO3_SFT 1
2429 /* tx_cmpl (size:128b/16B) */
2431 uint16_t flags_type;
2433 * This field indicates the exact type of the completion.
2434 * By convention, the LSB identifies the length of the
2435 * record in 16B units. Even values indicate 16B
2436 * records. Odd values indicate 32B
2439 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2440 #define TX_CMPL_TYPE_SFT 0
2443 * Completion of TX packet. Length = 16B
2445 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2446 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2447 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2448 #define TX_CMPL_FLAGS_SFT 6
2450 * When this bit is '1', it indicates a packet that has an
2451 * error of some type. Type of error is indicated in
2454 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2456 * When this bit is '1', it indicates that the packet completed
2457 * was transmitted using the push acceleration data provided
2458 * by the driver. When this bit is '0', it indicates that the
2459 * packet had not push acceleration data written or was executed
2460 * as a normal packet even though push data was provided.
2462 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2463 /* unused1 is 16 b */
2466 * This is a copy of the opaque field from the first TX BD of this
2467 * transmitted packet. Note that, if the packet was described by a short
2468 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2469 * short CSO BD will appear in the bottom 16 bits of this field.
2474 * This value is written by the NIC such that it will be different
2475 * for each pass through the completion queue. The even passes
2476 * will write 1. The odd passes will write 0.
2478 #define TX_CMPL_V UINT32_C(0x1)
2479 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2480 #define TX_CMPL_ERRORS_SFT 1
2482 * This error indicates that there was some sort of problem
2483 * with the BDs for the packet.
2485 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2486 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2488 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
2489 (UINT32_C(0x0) << 1)
2492 * BDs were not formatted correctly.
2494 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
2495 (UINT32_C(0x2) << 1)
2496 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2497 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2499 * When this bit is '1', it indicates that the length of
2500 * the packet was zero. No packet was transmitted.
2502 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2504 * When this bit is '1', it indicates that the packet
2505 * was longer than the programmed limit in TDI. No
2506 * packet was transmitted.
2508 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2510 * When this bit is '1', it indicates that one or more of the
2511 * BDs associated with this packet generated a PCI error.
2512 * This probably means the address was not valid.
2514 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2516 * When this bit is '1', it indicates that the packet was longer
2517 * than indicated by the hint. No packet was transmitted.
2519 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2521 * When this bit is '1', it indicates that the packet was
2522 * dropped due to Poison TLP error on one or more of the
2523 * TLPs in the PXP completion.
2525 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2527 * When this bit is '1', it indicates that the packet was dropped
2528 * due to a transient internal error in TDC. The packet or LSO can
2529 * be retried and may transmit successfully on a subsequent attempt.
2531 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2533 * When this bit is '1', it was not possible to collect a a timestamp
2534 * for a PTP completion, in which case the timestamp_hi and
2535 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2536 * completion, the timestamp_hi and timestamp_lo fields are valid.
2537 * RJRN will copy the value of this bit into the field of the same
2538 * name in all TX completions, regardless of whether such completions
2539 * are PTP completions or other TX completions.
2541 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2542 /* unused2 is 16 b */
2544 /* unused3 is 32 b */
2548 /* tx_cmpl_coal (size:128b/16B) */
2549 struct tx_cmpl_coal {
2550 uint16_t flags_type;
2552 * This field indicates the exact type of the completion.
2553 * By convention, the LSB identifies the length of the
2554 * record in 16B units. Even values indicate 16B
2555 * records. Odd values indicate 32B
2558 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
2559 #define TX_CMPL_COAL_TYPE_SFT 0
2561 * TX L2 coalesced completion:
2562 * Completion of TX packet. Length = 16B
2564 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
2565 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
2566 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
2567 #define TX_CMPL_COAL_FLAGS_SFT 6
2569 * When this bit is '1', it indicates a packet that has an
2570 * error of some type. Type of error is indicated in
2573 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
2575 * When this bit is '1', it indicates that the packet completed
2576 * was transmitted using the push acceleration data provided
2577 * by the driver. When this bit is '0', it indicates that the
2578 * packet had not push acceleration data written or was executed
2579 * as a normal packet even though push data was provided.
2581 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
2582 /* unused1 is 16 b */
2585 * This is a copy of the opaque field from the first TX BD of the packet
2586 * which corresponds with the reported sq_cons_idx. Note that, with
2587 * coalesced completions, completions are generated for only some of the
2588 * packets. The driver will see the opaque field for only those packets.
2589 * Note that, if the packet was described by a short CSO or short CSO
2590 * inline BD, then the 16-bit opaque field from the short CSO BD will
2591 * appear in the bottom 16 bits of this field. For TX rings with
2592 * completion coalescing enabled (which would use the coalesced
2593 * completion record), it is suggested that the driver populate the
2594 * opaque field to indicate the specific TX ring with which the
2595 * completion is associated, then utilize the opaque and sq_cons_idx
2596 * fields in the coalesced completion record to determine the specific
2597 * packets that are to be completed on that ring.
2602 * This value is written by the NIC such that it will be different
2603 * for each pass through the completion queue. The even passes
2604 * will write 1. The odd passes will write 0.
2606 #define TX_CMPL_COAL_V UINT32_C(0x1)
2607 #define TX_CMPL_COAL_ERRORS_MASK \
2609 #define TX_CMPL_COAL_ERRORS_SFT 1
2611 * This error indicates that there was some sort of problem
2612 * with the BDs for the packet.
2614 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2615 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
2617 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
2618 (UINT32_C(0x0) << 1)
2621 * BDs were not formatted correctly.
2623 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
2624 (UINT32_C(0x2) << 1)
2625 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
2626 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
2628 * When this bit is '1', it indicates that the length of
2629 * the packet was zero. No packet was transmitted.
2631 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2633 * When this bit is '1', it indicates that the packet
2634 * was longer than the programmed limit in TDI. No
2635 * packet was transmitted.
2637 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2639 * When this bit is '1', it indicates that one or more of the
2640 * BDs associated with this packet generated a PCI error.
2641 * This probably means the address was not valid.
2643 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
2645 * When this bit is '1', it indicates that the packet was longer
2646 * than indicated by the hint. No packet was transmitted.
2648 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2650 * When this bit is '1', it indicates that the packet was
2651 * dropped due to Poison TLP error on one or more of the
2652 * TLPs in the PXP completion.
2654 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
2657 * When this bit is '1', it indicates that the packet was dropped
2658 * due to a transient internal error in TDC. The packet or LSO can
2659 * be retried and may transmit successfully on a subsequent attempt.
2661 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
2664 * When this bit is '1', it was not possible to collect a a timestamp
2665 * for a PTP completion, in which case the timestamp_hi and
2666 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2667 * completion, the timestamp_hi and timestamp_lo fields are valid.
2668 * RJRN will copy the value of this bit into the field of the same
2669 * name in all TX completions, regardless of whether such
2670 * completions are PTP completions or other TX completions.
2672 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
2674 /* unused2 is 16 b */
2676 uint32_t sq_cons_idx;
2678 * This value is SQ index for the start of the packet following the
2679 * last completed packet.
2681 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
2682 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
2685 /* tx_cmpl_ptp (size:128b/16B) */
2686 struct tx_cmpl_ptp {
2687 uint16_t flags_type;
2689 * This field indicates the exact type of the completion.
2690 * By convention, the LSB identifies the length of the
2691 * record in 16B units. Even values indicate 16B
2692 * records. Odd values indicate 32B
2695 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
2696 #define TX_CMPL_PTP_TYPE_SFT 0
2698 * TX L2 PTP completion:
2699 * Completion of TX packet. Length = 32B
2701 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
2702 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
2703 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
2704 #define TX_CMPL_PTP_FLAGS_SFT 6
2706 * When this bit is '1', it indicates a packet that has an
2707 * error of some type. Type of error is indicated in
2710 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
2712 * When this bit is '1', it indicates that the packet completed
2713 * was transmitted using the push acceleration data provided
2714 * by the driver. When this bit is '0', it indicates that the
2715 * packet had not push acceleration data written or was executed
2716 * as a normal packet even though push data was provided.
2718 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
2719 /* unused1 is 16 b */
2722 * This is a copy of the opaque field from the first TX BD of this
2723 * transmitted packet. Note that, if the packet was described by a short
2724 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2725 * short CSO BD will appear in the bottom 16 bits of this field.
2730 * This value is written by the NIC such that it will be different
2731 * for each pass through the completion queue. The even passes
2732 * will write 1. The odd passes will write 0.
2734 #define TX_CMPL_PTP_V UINT32_C(0x1)
2735 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
2736 #define TX_CMPL_PTP_ERRORS_SFT 1
2738 * This error indicates that there was some sort of problem
2739 * with the BDs for the packet.
2741 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2742 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
2744 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
2745 (UINT32_C(0x0) << 1)
2748 * BDs were not formatted correctly.
2750 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
2751 (UINT32_C(0x2) << 1)
2752 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
2753 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
2755 * When this bit is '1', it indicates that the length of
2756 * the packet was zero. No packet was transmitted.
2758 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2760 * When this bit is '1', it indicates that the packet
2761 * was longer than the programmed limit in TDI. No
2762 * packet was transmitted.
2764 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2766 * When this bit is '1', it indicates that one or more of the
2767 * BDs associated with this packet generated a PCI error.
2768 * This probably means the address was not valid.
2770 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
2772 * When this bit is '1', it indicates that the packet was longer
2773 * than indicated by the hint. No packet was transmitted.
2775 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2777 * When this bit is '1', it indicates that the packet was
2778 * dropped due to Poison TLP error on one or more of the
2779 * TLPs in the PXP completion.
2781 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2783 * When this bit is '1', it indicates that the packet was dropped due
2784 * to a transient internal error in TDC. The packet or LSO can be
2785 * retried and may transmit successfully on a subsequent attempt.
2787 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2789 * When this bit is '1', it was not possible to collect a a timestamp
2790 * for a PTP completion, in which case the timestamp_hi and
2791 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2792 * completion, the timestamp_hi and timestamp_lo fields are valid.
2793 * RJRN will copy the value of this bit into the field of the same
2794 * name in all TX completions, regardless of whether such
2795 * completions are PTP completions or other TX completions.
2797 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2798 /* unused2 is 16 b */
2801 * This is timestamp value (lower 32bits) read from PM for the PTP
2802 * timestamp enabled packet.
2804 uint32_t timestamp_lo;
2807 /* tx_cmpl_ptp_hi (size:128b/16B) */
2808 struct tx_cmpl_ptp_hi {
2810 * This is timestamp value (lower 32bits) read from PM for the PTP
2811 * timestamp enabled packet.
2813 uint16_t timestamp_hi[3];
2814 uint16_t reserved16;
2817 * This value is written by the NIC such that it will be different for
2818 * each pass through the completion queue.The even passes will write 1.
2819 * The odd passes will write 0
2821 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
2824 /* rx_pkt_cmpl (size:128b/16B) */
2825 struct rx_pkt_cmpl {
2826 uint16_t flags_type;
2828 * This field indicates the exact type of the completion.
2829 * By convention, the LSB identifies the length of the
2830 * record in 16B units. Even values indicate 16B
2831 * records. Odd values indicate 32B
2834 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2835 #define RX_PKT_CMPL_TYPE_SFT 0
2838 * Completion of and L2 RX packet. Length = 32B
2840 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2841 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2842 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2843 #define RX_PKT_CMPL_FLAGS_SFT 6
2845 * When this bit is '1', it indicates a packet that has an
2846 * error of some type. Type of error is indicated in
2849 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2850 /* This field indicates how the packet was placed in the buffer. */
2851 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2852 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2855 * Packet was placed using normal algorithm.
2857 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2860 * Packet was placed using jumbo algorithm.
2862 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2864 * Header/Data Separation:
2865 * Packet was placed using Header/Data separation algorithm.
2866 * The separation location is indicated by the itype field.
2868 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2869 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2870 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2871 /* This bit is '1' if the RSS field in this completion is valid. */
2872 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2874 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2876 * This value indicates what the inner packet determined for the
2879 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2880 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2883 * Indicates that the packet type was not known.
2885 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2886 (UINT32_C(0x0) << 12)
2889 * Indicates that the packet was an IP packet, but further
2890 * classification was not possible.
2892 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2893 (UINT32_C(0x1) << 12)
2896 * Indicates that the packet was IP and TCP.
2897 * This indicates that the payload_offset field is valid.
2899 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2900 (UINT32_C(0x2) << 12)
2903 * Indicates that the packet was IP and UDP.
2904 * This indicates that the payload_offset field is valid.
2906 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2907 (UINT32_C(0x3) << 12)
2910 * Indicates that the packet was recognized as a FCoE.
2911 * This also indicates that the payload_offset field is valid.
2913 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2914 (UINT32_C(0x4) << 12)
2917 * Indicates that the packet was recognized as a RoCE.
2918 * This also indicates that the payload_offset field is valid.
2920 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2921 (UINT32_C(0x5) << 12)
2924 * Indicates that the packet was recognized as ICMP.
2925 * This indicates that the payload_offset field is valid.
2927 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2928 (UINT32_C(0x7) << 12)
2930 * PtP packet wo/timestamp:
2931 * Indicates that the packet was recognized as a PtP
2934 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2935 (UINT32_C(0x8) << 12)
2937 * PtP packet w/timestamp:
2938 * Indicates that the packet was recognized as a PtP
2939 * packet and that a timestamp was taken for the packet.
2941 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2942 (UINT32_C(0x9) << 12)
2943 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2944 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2946 * This is the length of the data for the packet stored in the
2947 * buffer(s) identified by the opaque value. This includes
2948 * the packet BD and any associated buffer BDs. This does not include
2949 * the length of any data places in aggregation BDs.
2953 * This is a copy of the opaque field from the RX BD this completion
2957 uint8_t agg_bufs_v1;
2959 * This value is written by the NIC such that it will be different
2960 * for each pass through the completion queue. The even passes
2961 * will write 1. The odd passes will write 0.
2963 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2965 * This value is the number of aggregation buffers that follow this
2966 * entry in the completion ring that are a part of this packet.
2967 * If the value is zero, then the packet is completely contained
2968 * in the buffer space provided for the packet in the RX ring.
2970 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2971 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2972 /* unused1 is 2 b */
2973 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2974 #define RX_PKT_CMPL_UNUSED1_SFT 6
2976 * This is the RSS hash type for the packet. The value is packed
2977 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2979 * The value of tuple_extrac_op provides the information about
2980 * what fields the hash was computed on.
2981 * * 0: The RSS hash was computed over source IP address,
2982 * destination IP address, source port, and destination port of inner
2983 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2984 * the packet headers are considered inner packet headers for the RSS
2985 * hash computation purpose.
2986 * * 1: The RSS hash was computed over source IP address and destination
2987 * IP address of inner IP header. Note: For non-tunneled packets,
2988 * the packet headers are considered inner packet headers for the RSS
2989 * hash computation purpose.
2990 * * 2: The RSS hash was computed over source IP address,
2991 * destination IP address, source port, and destination port of
2992 * IP and TCP or UDP headers of outer tunnel headers.
2993 * Note: For non-tunneled packets, this value is not applicable.
2994 * * 3: The RSS hash was computed over source IP address and
2995 * destination IP address of IP header of outer tunnel headers.
2996 * Note: For non-tunneled packets, this value is not applicable.
2998 * Note that 4-tuples values listed above are applicable
2999 * for layer 4 protocols supported and enabled for RSS in the hardware,
3000 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3001 * enabled for TCP traffic only, then the values of tuple_extract_op
3002 * corresponding to 4-tuples are only valid for TCP traffic.
3004 uint8_t rss_hash_type;
3006 * This value indicates the offset in bytes from the beginning of the packet
3007 * where the inner payload starts. This value is valid for TCP, UDP,
3008 * FCoE, and RoCE packets.
3010 * A value of zero indicates that header is 256B into the packet.
3012 uint8_t payload_offset;
3013 /* unused2 is 8 b */
3016 * This value is the RSS hash value calculated for the packet
3017 * based on the mode bits and key value in the VNIC.
3022 /* Last 16 bytes of rx_pkt_cmpl. */
3023 /* rx_pkt_cmpl_hi (size:128b/16B) */
3024 struct rx_pkt_cmpl_hi {
3027 * This indicates that the ip checksum was calculated for the
3028 * inner packet and that the ip_cs_error field indicates if there
3031 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3033 * This indicates that the TCP, UDP or ICMP checksum was
3034 * calculated for the inner packet and that the l4_cs_error field
3035 * indicates if there was an error.
3037 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3039 * This indicates that the ip checksum was calculated for the
3040 * tunnel header and that the t_ip_cs_error field indicates if there
3043 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3045 * This indicates that the UDP checksum was
3046 * calculated for the tunnel packet and that the t_l4_cs_error field
3047 * indicates if there was an error.
3049 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3050 /* This value indicates what format the metadata field is. */
3051 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3052 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
3053 /* No metadata information. Value is zero. */
3054 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
3055 (UINT32_C(0x0) << 4)
3057 * The metadata field contains the VLAN tag and TPID value.
3058 * - metadata[11:0] contains the vlan VID value.
3059 * - metadata[12] contains the vlan DE value.
3060 * - metadata[15:13] contains the vlan PRI value.
3061 * - metadata[31:16] contains the vlan TPID value.
3063 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
3064 (UINT32_C(0x1) << 4)
3066 * If ext_meta_format is equal to 1, the metadata field
3067 * contains the lower 16b of the tunnel ID value, justified
3069 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3070 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3071 * - NVGRE = TNI[23:0] -> Tenant Network ID
3072 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
3073 * - IPV4 = 0 (not populated)
3074 * - IPV6 = Flow Label[19:0]
3075 * - PPPoE = sessionID[15:0]
3076 * - MPLs = Outer label[19:0]
3077 * - UPAR = Selected[31:0] with bit mask
3079 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3080 (UINT32_C(0x2) << 4)
3082 * if ext_meta_format is equal to 1, metadata field contains
3083 * 16b metadata from the prepended header (chdr_data).
3085 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3086 (UINT32_C(0x3) << 4)
3088 * If ext_meta_format is equal to 1, the metadata field contains
3089 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3091 * - metadata[8:0] contains the outer_l3_offset.
3092 * - metadata[17:9] contains the inner_l2_offset.
3093 * - metadata[26:18] contains the inner_l3_offset.
3094 * - metadata[31:27] contains the inner_l4_size.
3096 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3097 (UINT32_C(0x4) << 4)
3098 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
3099 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3101 * This field indicates the IP type for the inner-most IP header.
3102 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3103 * This value is only valid if itype indicates a packet
3104 * with an IP header.
3106 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3108 * This indicates that the complete 1's complement checksum was
3109 * calculated for the packet.
3111 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
3113 * The combination of this value and meta_format indicated what
3114 * format the metadata field is.
3116 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
3117 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3119 * This value is the complete 1's complement checksum calculated from
3120 * the start of the outer L3 header to the end of the packet (not
3121 * including the ethernet crc). It is valid when the
3122 * 'complete_checksum_calc' flag is set.
3124 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3125 UINT32_C(0xffff0000)
3126 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3128 * This is data from the CFA block as indicated by the meta_format
3132 /* When meta_format=1, this value is the VLAN VID. */
3133 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3134 #define RX_PKT_CMPL_METADATA_VID_SFT 0
3135 /* When meta_format=1, this value is the VLAN DE. */
3136 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
3137 /* When meta_format=1, this value is the VLAN PRI. */
3138 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3139 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
3140 /* When meta_format=1, this value is the VLAN TPID. */
3141 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3142 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
3145 * This value is written by the NIC such that it will be different
3146 * for each pass through the completion queue. The even passes
3147 * will write 1. The odd passes will write 0.
3149 #define RX_PKT_CMPL_V2 \
3151 #define RX_PKT_CMPL_ERRORS_MASK \
3153 #define RX_PKT_CMPL_ERRORS_SFT 1
3155 * This error indicates that there was some sort of problem with
3156 * the BDs for the packet that was found after part of the
3157 * packet was already placed. The packet should be treated as
3160 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
3162 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3163 /* No buffer error */
3164 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3165 (UINT32_C(0x0) << 1)
3168 * Packet did not fit into packet buffer provided.
3169 * For regular placement, this means the packet did not fit
3170 * in the buffer provided. For HDS and jumbo placement, this
3171 * means that the packet could not be placed into 7 physical
3174 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3175 (UINT32_C(0x1) << 1)
3178 * All BDs needed for the packet were not on-chip when
3179 * the packet arrived.
3181 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3182 (UINT32_C(0x2) << 1)
3185 * BDs were not formatted correctly.
3187 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3188 (UINT32_C(0x3) << 1)
3191 * There was a bad_format error on the previous operation
3193 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3194 (UINT32_C(0x5) << 1)
3195 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3196 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3198 * This indicates that there was an error in the IP header
3201 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
3204 * This indicates that there was an error in the TCP, UDP
3207 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
3210 * This indicates that there was an error in the tunnel
3211 * IP header checksum.
3213 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
3216 * This indicates that there was an error in the tunnel
3219 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
3222 * This indicates that there was a CRC error on either an FCoE
3223 * or RoCE packet. The itype indicates the packet type.
3225 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
3228 * This indicates that there was an error in the tunnel
3229 * portion of the packet when this
3230 * field is non-zero.
3232 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
3234 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
3236 * No additional error occurred on the tunnel portion
3237 * or the packet of the packet does not have a tunnel.
3239 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
3240 (UINT32_C(0x0) << 9)
3242 * Indicates that IP header version does not match
3243 * expectation from L2 Ethertype for IPv4 and IPv6
3244 * in the tunnel header.
3246 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3247 (UINT32_C(0x1) << 9)
3249 * Indicates that header length is out of range in the
3250 * tunnel header. Valid for
3253 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3254 (UINT32_C(0x2) << 9)
3256 * Indicates that the physical packet is shorter than that
3257 * claimed by the PPPoE header length for a tunnel PPPoE
3260 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
3261 (UINT32_C(0x3) << 9)
3263 * Indicates that physical packet is shorter than that claimed
3264 * by the tunnel l3 header length. Valid for IPv4, or IPv6
3265 * tunnel packet packets.
3267 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3268 (UINT32_C(0x4) << 9)
3270 * Indicates that the physical packet is shorter than that
3271 * claimed by the tunnel UDP header length for a tunnel
3272 * UDP packet that is not fragmented.
3274 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3275 (UINT32_C(0x5) << 9)
3277 * indicates that the IPv4 TTL or IPv6 hop limit check
3278 * have failed (e.g. TTL = 0) in the tunnel header. Valid
3279 * for IPv4, and IPv6.
3281 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3282 (UINT32_C(0x6) << 9)
3283 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
3284 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
3286 * This indicates that there was an error in the inner
3287 * portion of the packet when this
3288 * field is non-zero.
3290 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
3292 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
3294 * No additional error occurred on the tunnel portion
3295 * or the packet of the packet does not have a tunnel.
3297 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
3298 (UINT32_C(0x0) << 12)
3300 * Indicates that IP header version does not match
3301 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3302 * option other than VFT was parsed on
3305 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3306 (UINT32_C(0x1) << 12)
3308 * indicates that header length is out of range. Valid for
3311 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3312 (UINT32_C(0x2) << 12)
3314 * indicates that the IPv4 TTL or IPv6 hop limit check
3315 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3317 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
3318 (UINT32_C(0x3) << 12)
3320 * Indicates that physical packet is shorter than that
3321 * claimed by the l3 header length. Valid for IPv4,
3322 * IPv6 packet or RoCE packets.
3324 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3325 (UINT32_C(0x4) << 12)
3327 * Indicates that the physical packet is shorter than that
3328 * claimed by the UDP header length for a UDP packet that is
3331 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3332 (UINT32_C(0x5) << 12)
3334 * Indicates that TCP header length > IP payload. Valid for
3337 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3338 (UINT32_C(0x6) << 12)
3339 /* Indicates that TCP header length < 5. Valid for TCP. */
3340 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3341 (UINT32_C(0x7) << 12)
3343 * Indicates that TCP option headers result in a TCP header
3344 * size that does not match data offset in TCP header. Valid
3347 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3348 (UINT32_C(0x8) << 12)
3349 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
3350 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
3352 * This field identifies the CFA action rule that was used for this
3358 * This value holds the reordering sequence number for the packet.
3359 * If the reordering sequence is not valid, then this value is zero.
3360 * The reordering domain for the packet is in the bottom 8 to 10b of
3361 * the rss_hash value. The bottom 20b of this value contain the
3362 * ordering domain value for the packet.
3364 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
3365 #define RX_PKT_CMPL_REORDER_SFT 0
3368 /* rx_pkt_v2_cmpl (size:128b/16B) */
3369 struct rx_pkt_v2_cmpl {
3370 uint16_t flags_type;
3372 * This field indicates the exact type of the completion.
3373 * By convention, the LSB identifies the length of the
3374 * record in 16B units. Even values indicate 16B
3375 * records. Odd values indicate 32B
3378 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
3379 #define RX_PKT_V2_CMPL_TYPE_SFT 0
3381 * RX L2 V2 completion:
3382 * Completion of and L2 RX packet. Length = 32B
3383 * This is the new version of the RX_L2 completion used in SR2
3386 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
3387 #define RX_PKT_V2_CMPL_TYPE_LAST \
3388 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
3389 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3390 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
3392 * When this bit is '1', it indicates a packet that has an
3393 * error of some type. Type of error is indicated in
3396 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
3397 /* This field indicates how the packet was placed in the buffer. */
3398 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3399 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
3402 * Packet was placed using normal algorithm.
3404 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
3405 (UINT32_C(0x0) << 7)
3408 * Packet was placed using jumbo algorithm.
3410 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
3411 (UINT32_C(0x1) << 7)
3413 * Header/Data Separation:
3414 * Packet was placed using Header/Data separation algorithm.
3415 * The separation location is indicated by the itype field.
3417 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
3418 (UINT32_C(0x2) << 7)
3421 * Packet was placed using truncation algorithm. The
3422 * placed (truncated) length is indicated in the payload_offset
3423 * field. The original length is indicated in the len field.
3425 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
3426 (UINT32_C(0x3) << 7)
3427 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
3428 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
3429 /* This bit is '1' if the RSS field in this completion is valid. */
3430 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3432 * This bit is '1' if metadata has been added to the end of the
3433 * packet in host memory. Metadata starts at the first 32B boundary
3434 * after the end of the packet for regular and jumbo placement.
3435 * It starts at the first 32B boundary after the end of the header
3436 * for HDS placement. The length of the metadata is indicated in the
3439 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
3441 * This value indicates what the inner packet determined for the
3444 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3445 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
3448 * Indicates that the packet type was not known.
3450 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
3451 (UINT32_C(0x0) << 12)
3454 * Indicates that the packet was an IP packet, but further
3455 * classification was not possible.
3457 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
3458 (UINT32_C(0x1) << 12)
3461 * Indicates that the packet was IP and TCP.
3462 * This indicates that the payload_offset field is valid.
3464 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
3465 (UINT32_C(0x2) << 12)
3468 * Indicates that the packet was IP and UDP.
3469 * This indicates that the payload_offset field is valid.
3471 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
3472 (UINT32_C(0x3) << 12)
3475 * Indicates that the packet was recognized as a FCoE.
3476 * This also indicates that the payload_offset field is valid.
3478 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
3479 (UINT32_C(0x4) << 12)
3482 * Indicates that the packet was recognized as a RoCE.
3483 * This also indicates that the payload_offset field is valid.
3485 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
3486 (UINT32_C(0x5) << 12)
3489 * Indicates that the packet was recognized as ICMP.
3490 * This indicates that the payload_offset field is valid.
3492 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
3493 (UINT32_C(0x7) << 12)
3495 * PtP packet wo/timestamp:
3496 * Indicates that the packet was recognized as a PtP
3499 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
3500 (UINT32_C(0x8) << 12)
3502 * PtP packet w/timestamp:
3503 * Indicates that the packet was recognized as a PtP
3504 * packet and that a timestamp was taken for the packet.
3506 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
3507 (UINT32_C(0x9) << 12)
3508 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
3509 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
3511 * This is the length of the data for the packet stored in the
3512 * buffer(s) identified by the opaque value. This includes
3513 * the packet BD and any associated buffer BDs. This does not include
3514 * the length of any data places in aggregation BDs.
3518 * This is a copy of the opaque field from the RX BD this completion
3522 uint8_t agg_bufs_v1;
3524 * This value is written by the NIC such that it will be different
3525 * for each pass through the completion queue. The even passes
3526 * will write 1. The odd passes will write 0.
3528 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
3530 * This value is the number of aggregation buffers that follow this
3531 * entry in the completion ring that are a part of this packet.
3532 * If the value is zero, then the packet is completely contained
3533 * in the buffer space provided for the packet in the RX ring.
3535 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
3536 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
3537 /* unused1 is 2 b */
3538 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
3539 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
3541 * This is the RSS hash type for the packet. The value is packed
3542 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3544 * The value of tuple_extrac_op provides the information about
3545 * what fields the hash was computed on.
3546 * * 0: The RSS hash was computed over source IP address,
3547 * destination IP address, source port, and destination port of inner
3548 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3549 * the packet headers are considered inner packet headers for the RSS
3550 * hash computation purpose.
3551 * * 1: The RSS hash was computed over source IP address and destination
3552 * IP address of inner IP header. Note: For non-tunneled packets,
3553 * the packet headers are considered inner packet headers for the RSS
3554 * hash computation purpose.
3555 * * 2: The RSS hash was computed over source IP address,
3556 * destination IP address, source port, and destination port of
3557 * IP and TCP or UDP headers of outer tunnel headers.
3558 * Note: For non-tunneled packets, this value is not applicable.
3559 * * 3: The RSS hash was computed over source IP address and
3560 * destination IP address of IP header of outer tunnel headers.
3561 * Note: For non-tunneled packets, this value is not applicable.
3563 * Note that 4-tuples values listed above are applicable
3564 * for layer 4 protocols supported and enabled for RSS in the hardware,
3565 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3566 * enabled for TCP traffic only, then the values of tuple_extract_op
3567 * corresponding to 4-tuples are only valid for TCP traffic.
3569 uint8_t rss_hash_type;
3570 uint16_t metadata1_payload_offset;
3572 * This is data from the CFA as indicated by the meta_format field.
3573 * If truncation placement is not used, this value indicates the offset
3574 * in bytes from the beginning of the packet where the inner payload
3575 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
3576 * truncation placement is used, this value represents the placed
3577 * (truncated) length of the packet.
3579 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
3580 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
3581 /* This is data from the CFA as indicated by the meta_format field. */
3582 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
3583 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
3584 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3585 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
3586 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
3587 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3588 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
3590 * This value is the RSS hash value calculated for the packet
3591 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
3592 * is set in VNIC context, this is the lower 32b of the host address
3593 * from the first BD used to place the packet.
3598 /* Last 16 bytes of RX Packet V2 Completion Record */
3599 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
3600 struct rx_pkt_v2_cmpl_hi {
3603 * When this bit is '0', the cs_ok field has the following definition:-
3604 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
3605 * in the delivered packet, counted from the outer-most header group to
3606 * the inner-most header group, stopping at the first error. -
3607 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
3608 * in the delivered packet, counted from the outer-most header group to
3609 * the inner-most header group, stopping at the first error. When this
3610 * bit is '1', the cs_ok field has the following definition: -
3611 * hdr_cnt[2:0] = The number of header groups that were parsed by the
3612 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
3613 * will be '1' if all the parsed header groups with an IP checksum are
3614 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
3615 * header groups with an L4 checksum are valid.
3617 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
3619 /* This value indicates what format the metadata field is. */
3620 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
3622 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
3623 /* There is no metadata information. Values are zero. */
3624 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
3625 (UINT32_C(0x0) << 4)
3627 * The {metadata1, metadata0} fields contain the vtag
3628 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
3629 * de, vid[11:0]} The metadata2 field contains the table scope
3630 * and action record pointer. - metadata2[25:0] contains the
3631 * action record pointer. - metadata2[31:26] contains the table
3634 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
3635 (UINT32_C(0x1) << 4)
3637 * The {metadata1, metadata0} fields contain the vtag
3639 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3640 * The metadata2 field contains the Tunnel ID
3641 * value, justified to LSB. i
3642 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3643 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
3644 * - NVGRE = TNI[23:0] -> Tenant Network ID
3645 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
3646 * - IPv4 = 0 (not populated)
3647 * - IPv6 = Flow Label[19:0]
3648 * - PPPoE = sessionID[15:0]
3649 * - MPLs = Outer label[19:0]
3650 * - UPAR = Selected[31:0] with bit mask
3652 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
3653 (UINT32_C(0x2) << 4)
3655 * The {metadata1, metadata0} fields contain the vtag
3657 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
3658 * The metadata2 field contains the 32b metadata from the prepended
3659 * header (chdr_data).
3661 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
3662 (UINT32_C(0x3) << 4)
3664 * The {metadata1, metadata0} fields contain the vtag
3666 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3667 * The metadata2 field contains the outer_l3_offset,
3668 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
3669 * - metadata2[8:0] contains the outer_l3_offset.
3670 * - metadata2[17:9] contains the inner_l2_offset.
3671 * - metadata2[26:18] contains the inner_l3_offset.
3672 * - metadata2[31:27] contains the inner_l4_size.
3674 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
3675 (UINT32_C(0x4) << 4)
3676 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
3677 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
3679 * This field indicates the IP type for the inner-most IP header.
3680 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3681 * This value is only valid if itype indicates a packet
3682 * with an IP header.
3684 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
3687 * This indicates that the complete 1's complement checksum was
3688 * calculated for the packet.
3690 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
3693 * This field indicates the status of IP and L4 CS calculations done
3694 * by the chip. The format of this field is indicated by the
3695 * cs_all_ok_mode bit.
3697 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
3699 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
3701 * This value is the complete 1's complement checksum calculated from
3702 * the start of the outer L3 header to the end of the packet (not
3703 * including the ethernet crc). It is valid when the
3704 * 'complete_checksum_calc' flag is set.
3706 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
3707 UINT32_C(0xffff0000)
3708 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3710 * This is data from the CFA block as indicated by the meta_format
3712 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
3713 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
3714 * act_rec_ptr[25:0]}
3715 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
3716 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
3717 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
3718 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
3719 * of the host address from the first BD used to place the packet.
3724 * This value is written by the NIC such that it will be different
3725 * for each pass through the completion queue. The even passes
3726 * will write 1. The odd passes will write 0.
3728 #define RX_PKT_V2_CMPL_HI_V2 \
3730 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
3732 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
3734 * This error indicates that there was some sort of problem with
3735 * the BDs for the packet that was found after part of the
3736 * packet was already placed. The packet should be treated as
3739 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
3741 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
3742 /* No buffer error */
3743 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
3744 (UINT32_C(0x0) << 1)
3746 * Did Not Fit: Packet did not fit into packet buffer provided.
3747 * For regular placement, this means the packet did not fit in
3748 * the buffer provided. For HDS and jumbo placement, this means
3749 * that the packet could not be placed into 8 physical buffers
3750 * (if fixed-size buffers are used), or that the packet could
3751 * not be placed in the number of physical buffers configured
3752 * for the VNIC (if variable-size buffers are used)
3754 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3755 (UINT32_C(0x1) << 1)
3757 * Not On Chip: All BDs needed for the packet were not on-chip
3758 * when the packet arrived. For regular placement, this error is
3759 * not valid. For HDS and jumbo placement, this means that not
3760 * enough agg BDs were posted to place the packet.
3762 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3763 (UINT32_C(0x2) << 1)
3766 * BDs were not formatted correctly.
3768 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3769 (UINT32_C(0x3) << 1)
3772 * There was a bad_format error on the previous operation
3774 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
3775 (UINT32_C(0x5) << 1)
3776 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
3777 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
3779 * This indicates that there was an error in the outer tunnel
3780 * portion of the packet when this field is non-zero.
3782 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
3784 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
3786 * No additional error occurred on the outer tunnel portion
3787 * of the packet or the packet does not have a outer tunnel.
3789 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
3790 (UINT32_C(0x0) << 4)
3792 * Indicates that IP header version does not match expectation
3793 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
3795 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
3796 (UINT32_C(0x1) << 4)
3798 * Indicates that header length is out of range in the outer
3799 * tunnel header. Valid for IPv4.
3801 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
3802 (UINT32_C(0x2) << 4)
3804 * Indicates that physical packet is shorter than that claimed
3805 * by the outer tunnel l3 header length. Valid for IPv4, or
3806 * IPv6 outer tunnel packets.
3808 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
3809 (UINT32_C(0x3) << 4)
3811 * Indicates that the physical packet is shorter than that
3812 * claimed by the outer tunnel UDP header length for a outer
3813 * tunnel UDP packet that is not fragmented.
3815 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
3816 (UINT32_C(0x4) << 4)
3818 * Indicates that the IPv4 TTL or IPv6 hop limit check have
3819 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
3822 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
3823 (UINT32_C(0x5) << 4)
3825 * Indicates that the IP checksum failed its check in the outer
3828 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
3829 (UINT32_C(0x6) << 4)
3831 * Indicates that the L4 checksum failed its check in the outer
3834 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
3835 (UINT32_C(0x7) << 4)
3836 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
3837 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
3839 * This indicates that there was a CRC error on either an FCoE
3840 * or RoCE packet. The itype indicates the packet type.
3842 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
3845 * This indicates that there was an error in the tunnel portion
3846 * of the packet when this field is non-zero.
3848 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
3850 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
3852 * No additional error occurred on the tunnel portion
3853 * of the packet or the packet does not have a tunnel.
3855 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
3856 (UINT32_C(0x0) << 9)
3858 * Indicates that IP header version does not match expectation
3859 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
3861 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3862 (UINT32_C(0x1) << 9)
3864 * Indicates that header length is out of range in the tunnel
3865 * header. Valid for IPv4.
3867 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3868 (UINT32_C(0x2) << 9)
3870 * Indicates that physical packet is shorter than that claimed
3871 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
3874 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3875 (UINT32_C(0x3) << 9)
3877 * Indicates that the physical packet is shorter than that claimed
3878 * by the tunnel UDP header length for a tunnel UDP packet that is
3881 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3882 (UINT32_C(0x4) << 9)
3884 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
3885 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
3887 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3888 (UINT32_C(0x5) << 9)
3890 * Indicates that the IP checksum failed its check in the tunnel
3893 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
3894 (UINT32_C(0x6) << 9)
3896 * Indicates that the L4 checksum failed its check in the tunnel
3899 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
3900 (UINT32_C(0x7) << 9)
3901 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
3902 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
3904 * This indicates that there was an error in the inner
3905 * portion of the packet when this
3906 * field is non-zero.
3908 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
3910 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
3912 * No additional error occurred on the tunnel portion
3913 * or the packet of the packet does not have a tunnel.
3915 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
3916 (UINT32_C(0x0) << 12)
3918 * Indicates that IP header version does not match
3919 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3920 * option other than VFT was parsed on
3923 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3924 (UINT32_C(0x1) << 12)
3926 * indicates that header length is out of range. Valid for
3929 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3930 (UINT32_C(0x2) << 12)
3932 * indicates that the IPv4 TTL or IPv6 hop limit check
3933 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3935 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
3936 (UINT32_C(0x3) << 12)
3938 * Indicates that physical packet is shorter than that
3939 * claimed by the l3 header length. Valid for IPv4,
3940 * IPv6 packet or RoCE packets.
3942 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3943 (UINT32_C(0x4) << 12)
3945 * Indicates that the physical packet is shorter than that
3946 * claimed by the UDP header length for a UDP packet that is
3949 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3950 (UINT32_C(0x5) << 12)
3952 * Indicates that TCP header length > IP payload. Valid for
3955 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3956 (UINT32_C(0x6) << 12)
3957 /* Indicates that TCP header length < 5. Valid for TCP. */
3958 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3959 (UINT32_C(0x7) << 12)
3961 * Indicates that TCP option headers result in a TCP header
3962 * size that does not match data offset in TCP header. Valid
3965 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3966 (UINT32_C(0x8) << 12)
3968 * Indicates that the IP checksum failed its check in the
3971 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
3972 (UINT32_C(0x9) << 12)
3974 * Indicates that the L4 checksum failed its check in the
3977 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
3978 (UINT32_C(0xa) << 12)
3979 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
3980 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
3982 * This is data from the CFA block as indicated by the meta_format
3986 /* When meta_format=1, this value is the VLAN VID. */
3987 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
3988 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
3989 /* When meta_format=1, this value is the VLAN DE. */
3990 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
3991 /* When meta_format=1, this value is the VLAN PRI. */
3992 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
3993 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
3995 * The timestamp field contains the 32b timestamp for the packet from
4002 * This TPA completion structure is used on devices where the
4003 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4005 /* rx_tpa_start_cmpl (size:128b/16B) */
4006 struct rx_tpa_start_cmpl {
4007 uint16_t flags_type;
4009 * This field indicates the exact type of the completion.
4010 * By convention, the LSB identifies the length of the
4011 * record in 16B units. Even values indicate 16B
4012 * records. Odd values indicate 32B
4015 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
4016 #define RX_TPA_START_CMPL_TYPE_SFT 0
4018 * RX L2 TPA Start Completion:
4019 * Completion at the beginning of a TPA operation.
4022 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
4023 #define RX_TPA_START_CMPL_TYPE_LAST \
4024 RX_TPA_START_CMPL_TYPE_RX_TPA_START
4025 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4026 #define RX_TPA_START_CMPL_FLAGS_SFT 6
4027 /* This bit will always be '0' for TPA start completions. */
4028 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
4029 /* This field indicates how the packet was placed in the buffer. */
4030 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4031 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
4034 * TPA Packet was placed using jumbo algorithm. This means
4035 * that the first buffer will be filled with data before
4036 * moving to aggregation buffers. Each aggregation buffer
4037 * will be filled before moving to the next aggregation
4040 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
4041 (UINT32_C(0x1) << 7)
4043 * Header/Data Separation:
4044 * Packet was placed using Header/Data separation algorithm.
4045 * The separation location is indicated by the itype field.
4047 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
4048 (UINT32_C(0x2) << 7)
4051 * Packet will be placed using GRO/Jumbo where the first
4052 * packet is filled with data. Subsequent packets will be
4053 * placed such that any one packet does not span two
4054 * aggregation buffers unless it starts at the beginning of
4055 * an aggregation buffer.
4057 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4058 (UINT32_C(0x5) << 7)
4060 * GRO/Header-Data Separation:
4061 * Packet will be placed using GRO/HDS where the header
4062 * is in the first packet.
4063 * Payload of each packet will be
4064 * placed such that any one packet does not span two
4065 * aggregation buffers unless it starts at the beginning of
4066 * an aggregation buffer.
4068 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4069 (UINT32_C(0x6) << 7)
4070 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
4071 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
4072 /* This bit is '1' if the RSS field in this completion is valid. */
4073 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4075 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4077 * This value indicates what the inner packet determined for the
4080 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4081 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
4084 * Indicates that the packet was IP and TCP.
4086 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
4087 (UINT32_C(0x2) << 12)
4088 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
4089 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
4091 * This value indicates the amount of packet data written to the
4092 * buffer the opaque field in this completion corresponds to.
4096 * This is a copy of the opaque field from the RX BD this completion
4101 * This value is written by the NIC such that it will be different
4102 * for each pass through the completion queue. The even passes
4103 * will write 1. The odd passes will write 0.
4107 * This value is written by the NIC such that it will be different
4108 * for each pass through the completion queue. The even passes
4109 * will write 1. The odd passes will write 0.
4111 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
4112 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
4114 * This is the RSS hash type for the packet. The value is packed
4115 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4117 * The value of tuple_extrac_op provides the information about
4118 * what fields the hash was computed on.
4119 * * 0: The RSS hash was computed over source IP address,
4120 * destination IP address, source port, and destination port of inner
4121 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4122 * the packet headers are considered inner packet headers for the RSS
4123 * hash computation purpose.
4124 * * 1: The RSS hash was computed over source IP address and destination
4125 * IP address of inner IP header. Note: For non-tunneled packets,
4126 * the packet headers are considered inner packet headers for the RSS
4127 * hash computation purpose.
4128 * * 2: The RSS hash was computed over source IP address,
4129 * destination IP address, source port, and destination port of
4130 * IP and TCP or UDP headers of outer tunnel headers.
4131 * Note: For non-tunneled packets, this value is not applicable.
4132 * * 3: The RSS hash was computed over source IP address and
4133 * destination IP address of IP header of outer tunnel headers.
4134 * Note: For non-tunneled packets, this value is not applicable.
4136 * Note that 4-tuples values listed above are applicable
4137 * for layer 4 protocols supported and enabled for RSS in the hardware,
4138 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4139 * enabled for TCP traffic only, then the values of tuple_extract_op
4140 * corresponding to 4-tuples are only valid for TCP traffic.
4142 uint8_t rss_hash_type;
4144 * This is the aggregation ID that the completion is associated
4145 * with. Use this number to correlate the TPA start completion
4146 * with the TPA end completion.
4149 /* unused2 is 9 b */
4150 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
4151 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
4153 * This is the aggregation ID that the completion is associated
4154 * with. Use this number to correlate the TPA start completion
4155 * with the TPA end completion.
4157 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
4158 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
4160 * This value is the RSS hash value calculated for the packet
4161 * based on the mode bits and key value in the VNIC.
4167 * Last 16 bytes of rx_tpa_start_cmpl.
4169 * This TPA completion structure is used on devices where the
4170 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4172 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
4173 struct rx_tpa_start_cmpl_hi {
4176 * This indicates that the ip checksum was calculated for the
4177 * inner packet and that the sum passed for all segments
4178 * included in the aggregation.
4180 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4182 * This indicates that the TCP, UDP or ICMP checksum was
4183 * calculated for the inner packet and that the sum passed
4184 * for all segments included in the aggregation.
4186 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4188 * This indicates that the ip checksum was calculated for the
4189 * tunnel header and that the sum passed for all segments
4190 * included in the aggregation.
4192 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4194 * This indicates that the UDP checksum was
4195 * calculated for the tunnel packet and that the sum passed for
4196 * all segments included in the aggregation.
4198 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4199 /* This value indicates what format the metadata field is. */
4200 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4201 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
4202 /* No metadata information. Value is zero. */
4203 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
4204 (UINT32_C(0x0) << 4)
4206 * The metadata field contains the VLAN tag and TPID value.
4207 * - metadata[11:0] contains the vlan VID value.
4208 * - metadata[12] contains the vlan DE value.
4209 * - metadata[15:13] contains the vlan PRI value.
4210 * - metadata[31:16] contains the vlan TPID value.
4212 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
4213 (UINT32_C(0x1) << 4)
4214 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
4215 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
4217 * This field indicates the IP type for the inner-most IP header.
4218 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4220 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4222 * This is data from the CFA block as indicated by the meta_format
4226 /* When meta_format=1, this value is the VLAN VID. */
4227 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4228 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
4229 /* When meta_format=1, this value is the VLAN DE. */
4230 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
4231 /* When meta_format=1, this value is the VLAN PRI. */
4232 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4233 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
4234 /* When meta_format=1, this value is the VLAN TPID. */
4235 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4236 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
4239 * This value is written by the NIC such that it will be different
4240 * for each pass through the completion queue. The even passes
4241 * will write 1. The odd passes will write 0.
4243 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
4245 * This field identifies the CFA action rule that was used for this
4250 * This is the size in bytes of the inner most L4 header.
4251 * This can be subtracted from the payload_offset to determine
4252 * the start of the inner most L4 header.
4254 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
4256 * This is the offset from the beginning of the packet in bytes for
4257 * the outer L3 header. If there is no outer L3 header, then this
4260 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
4261 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
4263 * This is the offset from the beginning of the packet in bytes for
4264 * the inner most L2 header.
4266 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
4267 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
4269 * This is the offset from the beginning of the packet in bytes for
4270 * the inner most L3 header.
4272 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
4273 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
4275 * This is the size in bytes of the inner most L4 header.
4276 * This can be subtracted from the payload_offset to determine
4277 * the start of the inner most L4 header.
4279 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
4280 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
4284 * This TPA completion structure is used on devices where the
4285 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4286 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
4289 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
4290 struct rx_tpa_start_v2_cmpl {
4291 uint16_t flags_type;
4293 * This field indicates the exact type of the completion.
4294 * By convention, the LSB identifies the length of the
4295 * record in 16B units. Even values indicate 16B
4296 * records. Odd values indicate 32B
4299 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
4301 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
4303 * RX L2 TPA Start V2 Completion:
4304 * Completion at the beginning of a TPA operation.
4306 * This is the new version of the RX_TPA_START completion used
4307 * in SR2 and later chips.
4309 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
4311 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
4312 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
4313 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
4315 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
4317 * When this bit is '1', it indicates a packet that has an error
4318 * of some type. Type of error is indicated in error_flags.
4320 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
4322 /* This field indicates how the packet was placed in the buffer. */
4323 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
4325 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4328 * TPA Packet was placed using jumbo algorithm. This means
4329 * that the first buffer will be filled with data before
4330 * moving to aggregation buffers. Each aggregation buffer
4331 * will be filled before moving to the next aggregation
4334 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4335 (UINT32_C(0x1) << 7)
4337 * Header/Data Separation:
4338 * Packet was placed using Header/Data separation algorithm.
4339 * The separation location is indicated by the itype field.
4341 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
4342 (UINT32_C(0x2) << 7)
4345 * Packet will be placed using In-Order Completion/Jumbo where
4346 * the first packet of the aggregation is placed using Jumbo
4347 * Placement. Subsequent packets will be placed such that each
4348 * packet starts at the beginning of an aggregation buffer.
4350 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4351 (UINT32_C(0x4) << 7)
4354 * Packet will be placed using GRO/Jumbo where the first
4355 * packet is filled with data. Subsequent packets will be
4356 * placed such that any one packet does not span two
4357 * aggregation buffers unless it starts at the beginning of
4358 * an aggregation buffer.
4360 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4361 (UINT32_C(0x5) << 7)
4363 * GRO/Header-Data Separation:
4364 * Packet will be placed using GRO/HDS where the header
4365 * is in the first packet.
4366 * Payload of each packet will be
4367 * placed such that any one packet does not span two
4368 * aggregation buffers unless it starts at the beginning of
4369 * an aggregation buffer.
4371 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4372 (UINT32_C(0x6) << 7)
4374 * IOC/Header-Data Separation:
4375 * Packet will be placed using In-Order Completion/HDS where
4376 * the header is in the first packet buffer. Payload of each
4377 * packet will be placed such that each packet starts at the
4378 * beginning of an aggregation buffer.
4380 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4381 (UINT32_C(0x7) << 7)
4382 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
4383 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
4384 /* This bit is '1' if the RSS field in this completion is valid. */
4385 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
4388 * This bit is '1' if metadata has been added to the end of the
4389 * packet in host memory. Metadata starts at the first 32B boundary
4390 * after the end of the packet for regular and jumbo placement. It
4391 * starts at the first 32B boundary after the end of the header for
4392 * HDS placement. The length of the metadata is indicated in the
4395 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
4398 * This value indicates what the inner packet determined for the
4401 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
4403 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
4406 * Indicates that the packet was IP and TCP.
4408 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
4409 (UINT32_C(0x2) << 12)
4410 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
4411 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
4413 * This value indicates the amount of packet data written to the
4414 * buffer the opaque field in this completion corresponds to.
4418 * This is a copy of the opaque field from the RX BD this completion
4419 * corresponds to. If the VNIC is configured to not use an Rx BD for
4420 * the TPA Start completion, then this is a copy of the opaque field
4421 * from the first BD used to place the TPA Start packet.
4425 * This value is written by the NIC such that it will be different
4426 * for each pass through the completion queue. The even passes
4427 * will write 1. The odd passes will write 0.
4431 * This value is written by the NIC such that it will be different
4432 * for each pass through the completion queue. The even passes
4433 * will write 1. The odd passes will write 0.
4435 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
4436 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
4438 * This is the RSS hash type for the packet. The value is packed
4439 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4441 * The value of tuple_extrac_op provides the information about
4442 * what fields the hash was computed on.
4443 * * 0: The RSS hash was computed over source IP address,
4444 * destination IP address, source port, and destination port of inner
4445 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4446 * the packet headers are considered inner packet headers for the RSS
4447 * hash computation purpose.
4448 * * 1: The RSS hash was computed over source IP address and destination
4449 * IP address of inner IP header. Note: For non-tunneled packets,
4450 * the packet headers are considered inner packet headers for the RSS
4451 * hash computation purpose.
4452 * * 2: The RSS hash was computed over source IP address,
4453 * destination IP address, source port, and destination port of
4454 * IP and TCP or UDP headers of outer tunnel headers.
4455 * Note: For non-tunneled packets, this value is not applicable.
4456 * * 3: The RSS hash was computed over source IP address and
4457 * destination IP address of IP header of outer tunnel headers.
4458 * Note: For non-tunneled packets, this value is not applicable.
4460 * Note that 4-tuples values listed above are applicable
4461 * for layer 4 protocols supported and enabled for RSS in the hardware,
4462 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4463 * enabled for TCP traffic only, then the values of tuple_extract_op
4464 * corresponding to 4-tuples are only valid for TCP traffic.
4466 uint8_t rss_hash_type;
4468 * This is the aggregation ID that the completion is associated
4469 * with. Use this number to correlate the TPA start completion
4470 * with the TPA end completion.
4474 * This is the aggregation ID that the completion is associated
4475 * with. Use this number to correlate the TPA start completion
4476 * with the TPA end completion.
4478 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
4479 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
4480 #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4481 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
4482 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4483 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4484 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4485 /* When meta_format != 0, this value is the VLAN valid. */
4486 #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4488 * This value is the RSS hash value calculated for the packet
4489 * based on the mode bits and key value in the VNIC.
4490 * When vee_cmpl_mode is set in VNIC context, this is the lower
4491 * 32b of the host address from the first BD used to place the packet.
4497 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
4499 * This TPA completion structure is used on devices where the
4500 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4502 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
4503 struct rx_tpa_start_v2_cmpl_hi {
4505 /* This indicates that the aggregation was done using GRO rules. */
4506 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
4509 * When this bit is '0', the cs_ok field has the following definition:-
4510 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4511 * in the delivered packet, counted from the outer-most header group to
4512 * the inner-most header group, stopping at the first error. -
4513 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4514 * in the delivered packet, counted from the outer-most header group to
4515 * the inner-most header group, stopping at the first error. When this
4516 * bit is '1', the cs_ok field has the following definition: -
4517 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4518 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4519 * will be '1' if all the parsed header groups with an IP checksum are
4520 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4521 * header groups with an L4 checksum are valid.
4523 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
4525 /* This value indicates what format the metadata field is. */
4526 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
4528 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
4529 /* There is no metadata information. Values are zero. */
4530 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
4531 (UINT32_C(0x0) << 4)
4533 * The {metadata1, metadata0} fields contain the vtag
4534 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4535 * de, vid[11:0]} The metadata2 field contains the table scope
4536 * and action record pointer. - metadata2[25:0] contains the
4537 * action record pointer. - metadata2[31:26] contains the table
4540 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
4541 (UINT32_C(0x1) << 4)
4543 * The {metadata1, metadata0} fields contain the vtag
4545 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4546 * The metadata2 field contains the Tunnel ID
4547 * value, justified to LSB. i
4548 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4549 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4550 * - NVGRE = TNI[23:0] -> Tenant Network ID
4551 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4552 * - IPv4 = 0 (not populated)
4553 * - IPv6 = Flow Label[19:0]
4554 * - PPPoE = sessionID[15:0]
4555 * - MPLs = Outer label[19:0]
4556 * - UPAR = Selected[31:0] with bit mask
4558 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4559 (UINT32_C(0x2) << 4)
4561 * The {metadata1, metadata0} fields contain the vtag
4563 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4564 * The metadata2 field contains the 32b metadata from the prepended
4565 * header (chdr_data).
4567 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4568 (UINT32_C(0x3) << 4)
4570 * The {metadata1, metadata0} fields contain the vtag
4572 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4573 * The metadata2 field contains the outer_l3_offset,
4574 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4575 * - metadata2[8:0] contains the outer_l3_offset.
4576 * - metadata2[17:9] contains the inner_l2_offset.
4577 * - metadata2[26:18] contains the inner_l3_offset.
4578 * - metadata2[31:27] contains the inner_l4_size.
4580 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4581 (UINT32_C(0x4) << 4)
4582 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
4583 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4585 * This field indicates the IP type for the inner-most IP header.
4586 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4587 * This value is only valid if itype indicates a packet
4588 * with an IP header.
4590 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
4593 * This indicates that the complete 1's complement checksum was
4594 * calculated for the packet in the affregation.
4596 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
4599 * This field indicates the status of IP and L4 CS calculations done
4600 * by the chip. The format of this field is indicated by the
4601 * cs_all_ok_mode bit.
4602 * CS status for TPA packets is always valid. This means that "all_ok"
4603 * status will always be set. The ok count status will be set
4604 * appropriately for the packet header, such that all existing CS
4607 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
4609 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
4611 * This value is the complete 1's complement checksum calculated from
4612 * the start of the outer L3 header to the end of the packet (not
4613 * including the ethernet crc). It is valid when the
4614 * 'complete_checksum_calc' flag is set. For TPA Start completions,
4615 * the complete checksum is calculated for the first packet in the
4618 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4619 UINT32_C(0xffff0000)
4620 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4622 * This is data from the CFA block as indicated by the meta_format
4624 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
4625 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
4626 * act_rec_ptr[25:0]}
4627 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
4628 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
4629 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
4630 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
4631 * of the host address from the first BD used to place the packet.
4636 * This value is written by the NIC such that it will be different
4637 * for each pass through the completion queue. The even passes
4638 * will write 1. The odd passes will write 0.
4640 #define RX_TPA_START_V2_CMPL_V2 \
4642 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
4644 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
4646 * This error indicates that there was some sort of problem with
4647 * the BDs for the packetThe packet should be treated as
4650 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
4652 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4653 /* No buffer error */
4654 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4655 (UINT32_C(0x0) << 1)
4658 * Packet did not fit into packet buffer provided. This means
4659 * that the TPA Start packet was too big to be placed into the
4660 * per-packet maximum number of physical buffers configured for
4661 * the VNIC, or that it was too big to be placed into the
4662 * per-aggregation maximum number of physical buffers configured
4663 * for the VNIC. This error only occurs when the VNIC is
4664 * configured for variable size receive buffers.
4666 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4667 (UINT32_C(0x1) << 1)
4670 * BDs were not formatted correctly.
4672 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4673 (UINT32_C(0x3) << 1)
4676 * There was a bad_format error on the previous operation
4678 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4679 (UINT32_C(0x5) << 1)
4680 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
4681 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4683 * This is data from the CFA block as indicated by the meta_format
4687 /* When meta_format != 0, this value is the VLAN VID. */
4688 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
4689 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
4690 /* When meta_format != 0, this value is the VLAN DE. */
4691 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
4692 /* When meta_format != 0, this value is the VLAN PRI. */
4693 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
4694 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
4696 * This field contains the outer_l3_offset, inner_l2_offset,
4697 * inner_l3_offset, and inner_l4_size.
4699 * hdr_offsets[8:0] contains the outer_l3_offset.
4700 * hdr_offsets[17:9] contains the inner_l2_offset.
4701 * hdr_offsets[26:18] contains the inner_l3_offset.
4702 * hdr_offsets[31:27] contains the inner_l4_size.
4704 uint32_t hdr_offsets;
4708 * This TPA completion structure is used on devices where the
4709 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4711 /* rx_tpa_end_cmpl (size:128b/16B) */
4712 struct rx_tpa_end_cmpl {
4713 uint16_t flags_type;
4715 * This field indicates the exact type of the completion.
4716 * By convention, the LSB identifies the length of the
4717 * record in 16B units. Even values indicate 16B
4718 * records. Odd values indicate 32B
4721 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
4722 #define RX_TPA_END_CMPL_TYPE_SFT 0
4724 * RX L2 TPA End Completion:
4725 * Completion at the end of a TPA operation.
4728 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
4729 #define RX_TPA_END_CMPL_TYPE_LAST \
4730 RX_TPA_END_CMPL_TYPE_RX_TPA_END
4731 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4732 #define RX_TPA_END_CMPL_FLAGS_SFT 6
4734 * When this bit is '1', it indicates a packet that has an
4735 * error of some type. Type of error is indicated in
4738 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
4739 /* This field indicates how the packet was placed in the buffer. */
4740 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4741 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
4744 * TPA Packet was placed using jumbo algorithm. This means
4745 * that the first buffer will be filled with data before
4746 * moving to aggregation buffers. Each aggregation buffer
4747 * will be filled before moving to the next aggregation
4750 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
4751 (UINT32_C(0x1) << 7)
4753 * Header/Data Separation:
4754 * Packet was placed using Header/Data separation algorithm.
4755 * The separation location is indicated by the itype field.
4757 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
4758 (UINT32_C(0x2) << 7)
4761 * Packet will be placed using In-Order Completion/Jumbo where
4762 * the first packet of the aggregation is placed using Jumbo
4763 * Placement. Subsequent packets will be placed such that each
4764 * packet starts at the beginning of an aggregation buffer.
4766 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4767 (UINT32_C(0x4) << 7)
4770 * Packet will be placed using GRO/Jumbo where the first
4771 * packet is filled with data. Subsequent packets will be
4772 * placed such that any one packet does not span two
4773 * aggregation buffers unless it starts at the beginning of
4774 * an aggregation buffer.
4776 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4777 (UINT32_C(0x5) << 7)
4779 * GRO/Header-Data Separation:
4780 * Packet will be placed using GRO/HDS where the header
4781 * is in the first packet.
4782 * Payload of each packet will be
4783 * placed such that any one packet does not span two
4784 * aggregation buffers unless it starts at the beginning of
4785 * an aggregation buffer.
4787 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4788 (UINT32_C(0x6) << 7)
4790 * IOC/Header-Data Separation:
4791 * Packet will be placed using In-Order Completion/HDS where
4792 * the header is in the first packet buffer. Payload of each
4793 * packet will be placed such that each packet starts at the
4794 * beginning of an aggregation buffer.
4796 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4797 (UINT32_C(0x7) << 7)
4798 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
4799 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
4801 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
4803 * This bit is '1' if metadata has been added to the end of the
4804 * packet in host memory. Metadata starts at the first 32B boundary
4805 * after the end of the packet for regular and jumbo placement.
4806 * It starts at the first 32B boundary after the end of the header
4807 * for HDS placement. The length of the metadata is indicated in the
4810 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4812 * This value indicates what the inner packet determined for the
4815 * Indicates that the packet was IP and TCP. This indicates
4816 * that the ip_cs field is valid and that the tcp_udp_cs
4817 * field is valid and contains the TCP checksum.
4818 * This also indicates that the payload_offset field is valid.
4820 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
4822 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
4824 * This value is zero for TPA End completions.
4825 * There is no data in the buffer that corresponds to the opaque
4826 * value in this completion.
4830 * This is a copy of the opaque field from the RX BD this completion
4835 * This value is written by the NIC such that it will be different
4836 * for each pass through the completion queue. The even passes
4837 * will write 1. The odd passes will write 0.
4839 uint8_t agg_bufs_v1;
4841 * This value is written by the NIC such that it will be different
4842 * for each pass through the completion queue. The even passes
4843 * will write 1. The odd passes will write 0.
4845 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
4847 * This value is the number of aggregation buffers that follow this
4848 * entry in the completion ring that are a part of this aggregation
4850 * If the value is zero, then the packet is completely contained
4851 * in the buffer space provided in the aggregation start completion.
4853 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
4854 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
4855 /* This value is the number of segments in the TPA operation. */
4858 * This value indicates the offset in bytes from the beginning of the packet
4859 * where the inner payload starts. This value is valid for TCP, UDP,
4860 * FCoE, and RoCE packets.
4862 * A value of zero indicates an offset of 256 bytes.
4864 uint8_t payload_offset;
4866 /* unused2 is 1 b */
4867 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
4869 * This is the aggregation ID that the completion is associated
4870 * with. Use this number to correlate the TPA start completion
4871 * with the TPA end completion.
4873 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
4874 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
4876 * For non-GRO packets, this value is the
4877 * timestamp delta between earliest and latest timestamp values for
4878 * TPA packet. If packets were not time stamped, then delta will be
4881 * For GRO packets, this field is zero except for the following
4884 * Timestamp present indication. When '0', no Timestamp
4885 * option is in the packet. When '1', then a Timestamp
4886 * option is present in the packet.
4892 * Last 16 bytes of rx_tpa_end_cmpl.
4894 * This TPA completion structure is used on devices where the
4895 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4897 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
4898 struct rx_tpa_end_cmpl_hi {
4899 uint32_t tpa_dup_acks;
4901 * This value is the number of duplicate ACKs that have been
4902 * received as part of the TPA operation.
4904 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
4905 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
4907 * This value is the valid when TPA completion is active. It
4908 * indicates the length of the longest segment of the TPA operation
4909 * for LRO mode and the length of the first segment in GRO mode.
4911 * This value may be used by GRO software to re-construct the original
4912 * packet stream from the TPA packet. This is the length of all
4913 * but the last segment for GRO. In LRO mode this value may be used
4914 * to indicate MSS size to the stack.
4916 uint16_t tpa_seg_len;
4917 /* unused4 is 16 b */
4921 * This value is written by the NIC such that it will be different
4922 * for each pass through the completion queue. The even passes
4923 * will write 1. The odd passes will write 0.
4925 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
4926 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4927 #define RX_TPA_END_CMPL_ERRORS_SFT 1
4929 * This error indicates that there was some sort of problem with
4930 * the BDs for the packet that was found after part of the
4931 * packet was already placed. The packet should be treated as
4934 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4935 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4937 * This error occurs when there is a fatal HW problem in
4938 * the chip only. It indicates that there were not
4939 * BDs on chip but that there was adequate reservation.
4940 * provided by the TPA block.
4942 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4943 (UINT32_C(0x2) << 1)
4945 * This error occurs when TPA block was not configured to
4946 * reserve adequate BDs for TPA operations on this RX
4947 * ring. All data for the TPA operation was not placed.
4949 * This error can also be generated when the number of
4950 * segments is not programmed correctly in TPA and the
4951 * 33 total aggregation buffers allowed for the TPA
4952 * operation has been exceeded.
4954 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4955 (UINT32_C(0x4) << 1)
4956 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4957 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
4958 /* unused5 is 16 b */
4961 * This is the opaque value that was completed for the TPA start
4962 * completion that corresponds to this TPA end completion.
4964 uint32_t start_opaque;
4968 * This TPA completion structure is used on devices where the
4969 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4971 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
4972 struct rx_tpa_v2_start_cmpl {
4973 uint16_t flags_type;
4975 * This field indicates the exact type of the completion.
4976 * By convention, the LSB identifies the length of the
4977 * record in 16B units. Even values indicate 16B
4978 * records. Odd values indicate 32B
4981 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
4983 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
4985 * RX L2 TPA Start Completion:
4986 * Completion at the beginning of a TPA operation.
4989 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
4991 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
4992 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
4993 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
4995 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
4996 /* This bit will always be '0' for TPA start completions. */
4997 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
4999 /* This field indicates how the packet was placed in the buffer. */
5000 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
5002 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
5005 * TPA Packet was placed using jumbo algorithm. This means
5006 * that the first buffer will be filled with data before
5007 * moving to aggregation buffers. Each aggregation buffer
5008 * will be filled before moving to the next aggregation
5011 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5012 (UINT32_C(0x1) << 7)
5014 * Header/Data Separation:
5015 * Packet was placed using Header/Data separation algorithm.
5016 * The separation location is indicated by the itype field.
5018 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
5019 (UINT32_C(0x2) << 7)
5022 * Packet will be placed using GRO/Jumbo where the first
5023 * packet is filled with data. Subsequent packets will be
5024 * placed such that any one packet does not span two
5025 * aggregation buffers unless it starts at the beginning of
5026 * an aggregation buffer.
5028 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5029 (UINT32_C(0x5) << 7)
5031 * GRO/Header-Data Separation:
5032 * Packet will be placed using GRO/HDS where the header
5033 * is in the first packet.
5034 * Payload of each packet will be
5035 * placed such that any one packet does not span two
5036 * aggregation buffers unless it starts at the beginning of
5037 * an aggregation buffer.
5039 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5040 (UINT32_C(0x6) << 7)
5041 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
5042 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5043 /* This bit is '1' if the RSS field in this completion is valid. */
5044 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
5047 * For devices that support timestamps, when this bit is cleared the
5048 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5049 * field contains the 32b timestamp for
5050 * the packet from the MAC. When this bit is set, the
5051 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5052 * field contains the outer_l3_offset, inner_l2_offset,
5053 * inner_l3_offset, and inner_l4_size.
5055 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
5058 * This value indicates what the inner packet determined for the
5061 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
5063 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
5066 * Indicates that the packet was IP and TCP.
5068 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
5069 (UINT32_C(0x2) << 12)
5070 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
5071 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
5073 * This value indicates the amount of packet data written to the
5074 * buffer the opaque field in this completion corresponds to.
5078 * This is a copy of the opaque field from the RX BD this completion
5083 * This value is written by the NIC such that it will be different
5084 * for each pass through the completion queue. The even passes
5085 * will write 1. The odd passes will write 0.
5089 * This value is written by the NIC such that it will be different
5090 * for each pass through the completion queue. The even passes
5091 * will write 1. The odd passes will write 0.
5093 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
5094 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
5096 * This is the RSS hash type for the packet. The value is packed
5097 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5099 * The value of tuple_extrac_op provides the information about
5100 * what fields the hash was computed on.
5101 * * 0: The RSS hash was computed over source IP address,
5102 * destination IP address, source port, and destination port of inner
5103 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5104 * the packet headers are considered inner packet headers for the RSS
5105 * hash computation purpose.
5106 * * 1: The RSS hash was computed over source IP address and destination
5107 * IP address of inner IP header. Note: For non-tunneled packets,
5108 * the packet headers are considered inner packet headers for the RSS
5109 * hash computation purpose.
5110 * * 2: The RSS hash was computed over source IP address,
5111 * destination IP address, source port, and destination port of
5112 * IP and TCP or UDP headers of outer tunnel headers.
5113 * Note: For non-tunneled packets, this value is not applicable.
5114 * * 3: The RSS hash was computed over source IP address and
5115 * destination IP address of IP header of outer tunnel headers.
5116 * Note: For non-tunneled packets, this value is not applicable.
5118 * Note that 4-tuples values listed above are applicable
5119 * for layer 4 protocols supported and enabled for RSS in the hardware,
5120 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5121 * enabled for TCP traffic only, then the values of tuple_extract_op
5122 * corresponding to 4-tuples are only valid for TCP traffic.
5124 uint8_t rss_hash_type;
5126 * This is the aggregation ID that the completion is associated
5127 * with. Use this number to correlate the TPA start completion
5128 * with the TPA end completion.
5132 * This value is the RSS hash value calculated for the packet
5133 * based on the mode bits and key value in the VNIC.
5139 * Last 16 bytes of rx_tpa_v2_start_cmpl.
5141 * This TPA completion structure is used on devices where the
5142 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5144 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
5145 struct rx_tpa_v2_start_cmpl_hi {
5148 * This indicates that the ip checksum was calculated for the
5149 * inner packet and that the sum passed for all segments
5150 * included in the aggregation.
5152 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
5155 * This indicates that the TCP, UDP or ICMP checksum was
5156 * calculated for the inner packet and that the sum passed
5157 * for all segments included in the aggregation.
5159 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
5162 * This indicates that the ip checksum was calculated for the
5163 * tunnel header and that the sum passed for all segments
5164 * included in the aggregation.
5166 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
5169 * This indicates that the UDP checksum was
5170 * calculated for the tunnel packet and that the sum passed for
5171 * all segments included in the aggregation.
5173 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
5175 /* This value indicates what format the metadata field is. */
5176 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
5178 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5179 /* No metadata informtaion. Value is zero. */
5180 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
5181 (UINT32_C(0x0) << 4)
5183 * The metadata field contains the VLAN tag and TPID value.
5184 * - metadata[11:0] contains the vlan VID value.
5185 * - metadata[12] contains the vlan DE value.
5186 * - metadata[15:13] contains the vlan PRI value.
5187 * - metadata[31:16] contains the vlan TPID value.
5189 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5190 (UINT32_C(0x1) << 4)
5192 * If ext_meta_format is equal to 1, the metadata field
5193 * contains the lower 16b of the tunnel ID value, justified
5195 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5196 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5197 * - NVGRE = TNI[23:0] -> Tenant Network ID
5198 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
5199 * - IPV4 = 0 (not populated)
5200 * - IPV6 = Flow Label[19:0]
5201 * - PPPoE = sessionID[15:0]
5202 * - MPLs = Outer label[19:0]
5203 * - UPAR = Selected[31:0] with bit mask
5205 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5206 (UINT32_C(0x2) << 4)
5208 * if ext_meta_format is equal to 1, metadata field contains
5209 * 16b metadata from the prepended header (chdr_data).
5211 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5212 (UINT32_C(0x3) << 4)
5214 * If ext_meta_format is equal to 1, the metadata field contains
5215 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
5217 * - metadata[8:0] contains the outer_l3_offset.
5218 * - metadata[17:9] contains the inner_l2_offset.
5219 * - metadata[26:18] contains the inner_l3_offset.
5220 * - metadata[31:27] contains the inner_l4_size.
5222 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5223 (UINT32_C(0x4) << 4)
5224 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
5225 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5227 * This field indicates the IP type for the inner-most IP header.
5228 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5230 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
5233 * This indicates that the complete 1's complement checksum was
5234 * calculated for the packet.
5236 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5239 * The combination of this value and meta_format indicated what
5240 * format the metadata field is.
5242 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
5244 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
5246 * This value is the complete 1's complement checksum calculated from
5247 * the start of the outer L3 header to the end of the packet (not
5248 * including the ethernet crc). It is valid when the
5249 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5250 * the complete checksum is calculated for the first packet in the
5253 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5254 UINT32_C(0xffff0000)
5255 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5257 * This is data from the CFA block as indicated by the meta_format
5261 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
5262 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5263 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
5264 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
5265 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
5266 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
5267 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5268 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
5269 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
5270 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5271 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
5274 * This value is written by the NIC such that it will be different
5275 * for each pass through the completion queue. The even passes
5276 * will write 1. The odd passes will write 0.
5278 #define RX_TPA_V2_START_CMPL_V2 \
5280 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
5282 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
5284 * This error indicates that there was some sort of problem with
5285 * the BDs for the packet that was found after part of the
5286 * packet was already placed. The packet should be treated as
5289 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
5291 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5292 /* No buffer error */
5293 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5294 (UINT32_C(0x0) << 1)
5297 * BDs were not formatted correctly.
5299 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5300 (UINT32_C(0x3) << 1)
5303 * There was a bad_format error on the previous operation
5305 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5306 (UINT32_C(0x5) << 1)
5307 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
5308 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5310 * This field identifies the CFA action rule that was used for this
5315 * For devices that support timestamps this field is overridden
5316 * with the timestamp value. When `flags.timestamp_fld_format` is
5317 * cleared, this field contains the 32b timestamp for the packet from the
5320 * When `flags.timestamp_fld_format` is set, this field contains the
5321 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
5324 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5326 * This is the offset from the beginning of the packet in bytes for
5327 * the outer L3 header. If there is no outer L3 header, then this
5330 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5331 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
5333 * This is the offset from the beginning of the packet in bytes for
5334 * the inner most L2 header.
5336 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5337 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
5339 * This is the offset from the beginning of the packet in bytes for
5340 * the inner most L3 header.
5342 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5343 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
5345 * This is the size in bytes of the inner most L4 header.
5346 * This can be subtracted from the payload_offset to determine
5347 * the start of the inner most L4 header.
5349 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5350 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
5354 * This TPA completion structure is used on devices where the
5355 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5357 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
5358 struct rx_tpa_v2_end_cmpl {
5359 uint16_t flags_type;
5361 * This field indicates the exact type of the completion.
5362 * By convention, the LSB identifies the length of the
5363 * record in 16B units. Even values indicate 16B
5364 * records. Odd values indicate 32B
5367 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
5368 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
5370 * RX L2 TPA End Completion:
5371 * Completion at the end of a TPA operation.
5374 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
5375 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
5376 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
5377 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5378 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
5380 * When this bit is '1', it indicates a packet that has an
5381 * error of some type. Type of error is indicated in
5384 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
5385 /* This field indicates how the packet was placed in the buffer. */
5386 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5387 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
5390 * TPA Packet was placed using jumbo algorithm. This means
5391 * that the first buffer will be filled with data before
5392 * moving to aggregation buffers. Each aggregation buffer
5393 * will be filled before moving to the next aggregation
5396 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
5397 (UINT32_C(0x1) << 7)
5399 * Header/Data Separation:
5400 * Packet was placed using Header/Data separation algorithm.
5401 * The separation location is indicated by the itype field.
5403 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
5404 (UINT32_C(0x2) << 7)
5407 * Packet will be placed using GRO/Jumbo where the first
5408 * packet is filled with data. Subsequent packets will be
5409 * placed such that any one packet does not span two
5410 * aggregation buffers unless it starts at the beginning of
5411 * an aggregation buffer.
5413 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5414 (UINT32_C(0x5) << 7)
5416 * GRO/Header-Data Separation:
5417 * Packet will be placed using GRO/HDS where the header
5418 * is in the first packet.
5419 * Payload of each packet will be
5420 * placed such that any one packet does not span two
5421 * aggregation buffers unless it starts at the beginning of
5422 * an aggregation buffer.
5424 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5425 (UINT32_C(0x6) << 7)
5426 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
5427 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
5429 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
5430 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
5432 * This value indicates what the inner packet determined for the
5435 * Indicates that the packet was IP and TCP. This indicates
5436 * that the ip_cs field is valid and that the tcp_udp_cs
5437 * field is valid and contains the TCP checksum.
5438 * This also indicates that the payload_offset field is valid.
5440 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5441 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
5443 * This value is zero for TPA End completions.
5444 * There is no data in the buffer that corresponds to the opaque
5445 * value in this completion.
5449 * This is a copy of the opaque field from the RX BD this completion
5455 * This value is written by the NIC such that it will be different
5456 * for each pass through the completion queue. The even passes
5457 * will write 1. The odd passes will write 0.
5459 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
5460 /* This value is the number of segments in the TPA operation. */
5463 * This is the aggregation ID that the completion is associated
5464 * with. Use this number to correlate the TPA start completion
5465 * with the TPA end completion.
5469 * For non-GRO packets, this value is the
5470 * timestamp delta between earliest and latest timestamp values for
5471 * TPA packet. If packets were not time stamped, then delta will be
5474 * For GRO packets, this field is zero except for the following
5477 * Timestamp present indication. When '0', no Timestamp
5478 * option is in the packet. When '1', then a Timestamp
5479 * option is present in the packet.
5485 * Last 16 bytes of rx_tpa_v2_end_cmpl.
5487 * This TPA completion structure is used on devices where the
5488 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5490 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
5491 struct rx_tpa_v2_end_cmpl_hi {
5493 * This value is the number of duplicate ACKs that have been
5494 * received as part of the TPA operation.
5496 uint16_t tpa_dup_acks;
5498 * This value is the number of duplicate ACKs that have been
5499 * received as part of the TPA operation.
5501 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
5502 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
5504 * This value indicated the offset in bytes from the beginning of
5505 * the packet where the inner payload starts. This value is valid
5506 * for TCP, UDP, FCoE and RoCE packets
5508 uint8_t payload_offset;
5510 * The value is the total number of aggregation buffers that were
5511 * used in the TPA operation. All TPA aggregation buffer completions
5512 * precede the TPA End completion. If the value is zero, then the
5513 * aggregation is completely contained in the buffer space provided
5514 * in the aggregation start completion.
5515 * Note that the field is simply provided as a cross check.
5517 uint8_t tpa_agg_bufs;
5519 * This value is the valid when TPA completion is active. It
5520 * indicates the length of the longest segment of the TPA operation
5521 * for LRO mode and the length of the first segment in GRO mode.
5523 * This value may be used by GRO software to re-construct the original
5524 * packet stream from the TPA packet. This is the length of all
5525 * but the last segment for GRO. In LRO mode this value may be used
5526 * to indicate MSS size to the stack.
5528 uint16_t tpa_seg_len;
5532 * This value is written by the NIC such that it will be different
5533 * for each pass through the completion queue. The even passes
5534 * will write 1. The odd passes will write 0.
5536 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
5537 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
5539 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
5541 * This error indicates that there was some sort of problem with
5542 * the BDs for the packet that was found after part of the
5543 * packet was already placed. The packet should be treated as
5546 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
5548 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5549 /* No buffer error */
5550 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5551 (UINT32_C(0x0) << 1)
5553 * This error occurs when there is a fatal HW problem in
5554 * the chip only. It indicates that there were not
5555 * BDs on chip but that there was adequate reservation.
5556 * provided by the TPA block.
5558 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5559 (UINT32_C(0x2) << 1)
5562 * BDs were not formatted correctly.
5564 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5565 (UINT32_C(0x3) << 1)
5567 * This error occurs when TPA block was not configured to
5568 * reserve adequate BDs for TPA operations on this RX
5569 * ring. All data for the TPA operation was not placed.
5571 * This error can also be generated when the number of
5572 * segments is not programmed correctly in TPA and the
5573 * 33 total aggregation buffers allowed for the TPA
5574 * operation has been exceeded.
5576 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5577 (UINT32_C(0x4) << 1)
5580 * There was a bad_format error on the previous operation
5582 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5583 (UINT32_C(0x5) << 1)
5584 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5585 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5588 * This is the opaque value that was completed for the TPA start
5589 * completion that corresponds to this TPA end completion.
5591 uint32_t start_opaque;
5595 * This TPA completion structure is used on devices where the
5596 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5598 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
5599 struct rx_tpa_v2_abuf_cmpl {
5602 * This field indicates the exact type of the completion.
5603 * By convention, the LSB identifies the length of the
5604 * record in 16B units. Even values indicate 16B
5605 * records. Odd values indicate 32B
5608 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5609 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
5611 * RX TPA Aggregation Buffer completion :
5612 * Completion of an L2 aggregation buffer in support of
5613 * TPA packet completion. Length = 16B
5615 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
5616 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
5617 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
5619 * This is the length of the data for the packet stored in this
5620 * aggregation buffer identified by the opaque value. This does not
5621 * include the length of any
5622 * data placed in other aggregation BDs or in the packet or buffer
5623 * BDs. This length does not include any space added due to
5624 * hdr_offset register during HDS placement mode.
5628 * This is a copy of the opaque field from the RX BD this aggregation
5629 * buffer corresponds to.
5634 * This value is written by the NIC such that it will be different
5635 * for each pass through the completion queue. The even passes
5636 * will write 1. The odd passes will write 0.
5638 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
5640 * This is the aggregation ID that the completion is associated with. Use
5641 * this number to correlate the TPA agg completion with the TPA start
5642 * completion and the TPA end completion.
5648 /* rx_abuf_cmpl (size:128b/16B) */
5649 struct rx_abuf_cmpl {
5652 * This field indicates the exact type of the completion.
5653 * By convention, the LSB identifies the length of the
5654 * record in 16B units. Even values indicate 16B
5655 * records. Odd values indicate 32B
5658 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5659 #define RX_ABUF_CMPL_TYPE_SFT 0
5661 * RX Aggregation Buffer completion :
5662 * Completion of an L2 aggregation buffer in support of
5663 * TPA, HDS, or Jumbo packet completion. Length = 16B
5665 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
5666 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
5668 * This is the length of the data for the packet stored in this
5669 * aggregation buffer identified by the opaque value. This does not
5670 * include the length of any
5671 * data placed in other aggregation BDs or in the packet or buffer
5672 * BDs. This length does not include any space added due to
5673 * hdr_offset register during HDS placement mode.
5677 * This is a copy of the opaque field from the RX BD this aggregation
5678 * buffer corresponds to.
5683 * This value is written by the NIC such that it will be different
5684 * for each pass through the completion queue. The even passes
5685 * will write 1. The odd passes will write 0.
5687 #define RX_ABUF_CMPL_V UINT32_C(0x1)
5688 /* unused3 is 32 b */
5692 /* VEE FLUSH Completion Record (16 bytes) */
5693 /* vee_flush (size:128b/16B) */
5695 uint32_t downstream_path_type;
5697 * This field indicates the exact type of the completion.
5698 * By convention, the LSB identifies the length of the
5699 * record in 16B units. Even values indicate 16B
5700 * records. Odd values indicate 32B
5703 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
5704 #define VEE_FLUSH_TYPE_SFT 0
5706 * VEE Flush Completion:
5707 * This completion is inserted manually by the Primate and processed
5708 * by the VEE hardware to ensure that all completions on a VEE
5709 * function have been processed by the VEE hardware before FLR
5710 * process is completed.
5712 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
5713 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
5714 /* downstream_path is 1 b */
5715 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
5716 /* This completion is associated with VEE Transmit */
5717 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
5718 /* This completion is associated with VEE Receive */
5719 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
5720 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
5722 * This is an opaque value that is passed through the completion
5723 * to the VEE handler SW and is used to indicate what VEE VQ or
5724 * function has completed FLR processing.
5729 * This value is written by the NIC such that it will be different
5730 * for each pass through the completion queue. The even passes will
5731 * write 1. The odd passes will write 0.
5733 #define VEE_FLUSH_V UINT32_C(0x1)
5734 /* unused3 is 32 b */
5738 /* eject_cmpl (size:128b/16B) */
5742 * This field indicates the exact type of the completion.
5743 * By convention, the LSB identifies the length of the
5744 * record in 16B units. Even values indicate 16B
5745 * records. Odd values indicate 32B
5748 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
5749 #define EJECT_CMPL_TYPE_SFT 0
5751 * Statistics Ejection Completion:
5752 * Completion of statistics data ejection buffer.
5755 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
5756 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
5757 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5758 #define EJECT_CMPL_FLAGS_SFT 6
5760 * When this bit is '1', it indicates a packet that has an
5761 * error of some type. Type of error is indicated in
5764 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
5766 * This is the length of the statistics data stored in this
5771 * This is a copy of the opaque field from the RX BD this ejection
5772 * buffer corresponds to.
5777 * This value is written by the NIC such that it will be different
5778 * for each pass through the completion queue. The even passes
5779 * will write 1. The odd passes will write 0.
5781 #define EJECT_CMPL_V UINT32_C(0x1)
5782 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
5783 #define EJECT_CMPL_ERRORS_SFT 1
5785 * This error indicates that there was some sort of problem with
5786 * the BDs for statistics ejection. The statistics ejection should
5787 * be treated as invalid
5789 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5790 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5791 /* No buffer error */
5792 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5793 (UINT32_C(0x0) << 1)
5796 * Statistics did not fit into aggregation buffer provided.
5798 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5799 (UINT32_C(0x1) << 1)
5802 * BDs were not formatted correctly.
5804 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5805 (UINT32_C(0x3) << 1)
5808 * There was a bad_format error on the previous operation
5810 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5811 (UINT32_C(0x5) << 1)
5812 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
5813 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5814 /* reserved16 is 16 b */
5815 uint16_t reserved16;
5816 /* unused3 is 32 b */
5820 /* hwrm_cmpl (size:128b/16B) */
5824 * This field indicates the exact type of the completion.
5825 * By convention, the LSB identifies the length of the
5826 * record in 16B units. Even values indicate 16B
5827 * records. Odd values indicate 32B
5830 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
5831 #define HWRM_CMPL_TYPE_SFT 0
5833 * HWRM Command Completion:
5834 * Completion of an HWRM command.
5836 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
5837 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
5838 /* This is the sequence_id of the HWRM command that has completed. */
5839 uint16_t sequence_id;
5840 /* unused2 is 32 b */
5844 * This value is written by the NIC such that it will be different
5845 * for each pass through the completion queue. The even passes
5846 * will write 1. The odd passes will write 0.
5848 #define HWRM_CMPL_V UINT32_C(0x1)
5849 /* unused4 is 32 b */
5853 /* hwrm_fwd_req_cmpl (size:128b/16B) */
5854 struct hwrm_fwd_req_cmpl {
5856 * This field indicates the exact type of the completion.
5857 * By convention, the LSB identifies the length of the
5858 * record in 16B units. Even values indicate 16B
5859 * records. Odd values indicate 32B
5862 uint16_t req_len_type;
5864 * This field indicates the exact type of the completion.
5865 * By convention, the LSB identifies the length of the
5866 * record in 16B units. Even values indicate 16B
5867 * records. Odd values indicate 32B
5870 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
5871 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
5872 /* Forwarded HWRM Request */
5873 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
5874 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
5875 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
5876 /* Length of forwarded request in bytes. */
5877 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
5878 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
5880 * Source ID of this request.
5881 * Typically used in forwarding requests and responses.
5882 * 0x0 - 0xFFF8 - Used for function ids
5883 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5887 /* unused1 is 32 b */
5889 /* Address of forwarded request. */
5890 uint32_t req_buf_addr_v[2];
5892 * This value is written by the NIC such that it will be different
5893 * for each pass through the completion queue. The even passes
5894 * will write 1. The odd passes will write 0.
5896 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
5897 /* Address of forwarded request. */
5898 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5899 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
5902 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
5903 struct hwrm_fwd_resp_cmpl {
5906 * This field indicates the exact type of the completion.
5907 * By convention, the LSB identifies the length of the
5908 * record in 16B units. Even values indicate 16B
5909 * records. Odd values indicate 32B
5912 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
5913 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
5914 /* Forwarded HWRM Response */
5915 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
5916 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
5917 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
5919 * Source ID of this response.
5920 * Typically used in forwarding requests and responses.
5921 * 0x0 - 0xFFF8 - Used for function ids
5922 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5926 /* Length of forwarded response in bytes. */
5928 /* unused2 is 16 b */
5930 /* Address of forwarded request. */
5931 uint32_t resp_buf_addr_v[2];
5933 * This value is written by the NIC such that it will be different
5934 * for each pass through the completion queue. The even passes
5935 * will write 1. The odd passes will write 0.
5937 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
5938 /* Address of forwarded request. */
5939 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5940 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
5943 /* hwrm_async_event_cmpl (size:128b/16B) */
5944 struct hwrm_async_event_cmpl {
5947 * This field indicates the exact type of the completion.
5948 * By convention, the LSB identifies the length of the
5949 * record in 16B units. Even values indicate 16B
5950 * records. Odd values indicate 32B
5953 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
5954 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
5955 /* HWRM Asynchronous Event Information */
5956 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
5957 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
5958 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
5959 /* Identifiers of events. */
5961 /* Link status changed */
5962 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
5964 /* Link MTU changed */
5965 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
5967 /* Link speed changed */
5968 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
5970 /* DCB Configuration changed */
5971 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
5973 /* Port connection not allowed */
5974 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
5976 /* Link speed configuration was not allowed */
5977 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
5979 /* Link speed configuration change */
5980 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
5982 /* Port PHY configuration change */
5983 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
5985 /* Reset notification to clients */
5986 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
5988 /* Master function selection event */
5989 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
5991 /* Function driver unloaded */
5992 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
5994 /* Function driver loaded */
5995 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
5997 /* Function FLR related processing has completed */
5998 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
6000 /* PF driver unloaded */
6001 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
6003 /* PF driver loaded */
6004 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
6006 /* VF Function Level Reset (FLR) */
6007 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
6009 /* VF MAC Address Change */
6010 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
6012 /* PF-VF communication channel status change. */
6013 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
6015 /* VF Configuration Change */
6016 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
6018 /* LLFC/PFC Configuration Change */
6019 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
6021 /* Default VNIC Configuration Change */
6022 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
6025 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
6028 * A debug notification being posted to the driver. These
6029 * notifications are purely for diagnostic purpose and should not be
6030 * used for functional purpose. The driver is not supposed to act
6031 * on these messages except to log/record it.
6033 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
6036 * An EEM flow cached memory flush for all flows request event being
6037 * posted to the PF driver.
6039 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6042 * An EEM flow cache memory flush completion event being posted to the
6043 * firmware by the PF driver. This is indication that host EEM flush
6044 * has completed by the PF.
6046 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6049 * A tcp flag action change event being posted to the PF or trusted VF
6050 * driver by the firmware. The PF or trusted VF driver should query
6051 * the firmware for the new TCP flag action update after receiving
6054 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6057 * An EEM flow active event being posted to the PF or trusted VF driver
6058 * by the firmware. The PF or trusted VF driver should update the
6059 * flow's aging timer after receiving this async event.
6061 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
6064 * A eem cfg change event being posted to the trusted VF driver by the
6065 * firmware if the parent PF EEM configuration changed.
6067 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
6071 * TFLIB unique default VNIC Configuration Change
6073 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
6077 * TFLIB unique link status changed
6079 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
6082 * An event signifying completion for HWRM_FW_STATE_QUIESCE
6083 * (completion, timeout, or error)
6085 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
6088 * An event signifying a HWRM command is in progress and its
6089 * response will be deferred. This event is used on crypto controllers
6092 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
6095 * An event signifying that a PFC WatchDog configuration
6096 * has changed on any port / cos.
6098 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
6101 * A trace log message. This contains firmware trace logs string
6102 * embedded in the asynchronous message. This is an experimental
6103 * event, not meant for production use at this time.
6105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
6108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
6110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
6111 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
6112 /* Event specific data */
6113 uint32_t event_data2;
6116 * This value is written by the NIC such that it will be different
6117 * for each pass through the completion queue. The even passes
6118 * will write 1. The odd passes will write 0.
6120 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
6122 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
6123 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
6124 /* 8-lsb timestamp from POR (100-msec resolution) */
6125 uint8_t timestamp_lo;
6126 /* 16-lsb timestamp from POR (100-msec resolution) */
6127 uint16_t timestamp_hi;
6128 /* Event specific data */
6129 uint32_t event_data1;
6132 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
6133 struct hwrm_async_event_cmpl_link_status_change {
6136 * This field indicates the exact type of the completion.
6137 * By convention, the LSB identifies the length of the
6138 * record in 16B units. Even values indicate 16B
6139 * records. Odd values indicate 32B
6142 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
6144 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
6145 /* HWRM Asynchronous Event Information */
6146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
6149 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
6150 /* Identifiers of events. */
6152 /* Link status changed */
6153 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
6155 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
6156 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
6157 /* Event specific data */
6158 uint32_t event_data2;
6161 * This value is written by the NIC such that it will be different
6162 * for each pass through the completion queue. The even passes
6163 * will write 1. The odd passes will write 0.
6165 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
6168 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
6170 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
6171 /* 8-lsb timestamp from POR (100-msec resolution) */
6172 uint8_t timestamp_lo;
6173 /* 16-lsb timestamp from POR (100-msec resolution) */
6174 uint16_t timestamp_hi;
6175 /* Event specific data */
6176 uint32_t event_data1;
6177 /* Indicates link status change */
6178 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
6181 * If this bit set to 0, then it indicates that the link
6182 * was up and it went down.
6184 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
6187 * If this bit is set to 1, then it indicates that the link
6188 * was down and it went up.
6190 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
6192 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
6193 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
6194 /* Indicates the physical port this link status change occur */
6195 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
6197 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
6200 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6202 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6204 /* Indicates the physical function this event occurred on. */
6205 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
6207 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
6211 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
6212 struct hwrm_async_event_cmpl_link_mtu_change {
6215 * This field indicates the exact type of the completion.
6216 * By convention, the LSB identifies the length of the
6217 * record in 16B units. Even values indicate 16B
6218 * records. Odd values indicate 32B
6221 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
6223 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
6224 /* HWRM Asynchronous Event Information */
6225 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6227 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
6228 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
6229 /* Identifiers of events. */
6231 /* Link MTU changed */
6232 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
6234 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
6235 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
6236 /* Event specific data */
6237 uint32_t event_data2;
6240 * This value is written by the NIC such that it will be different
6241 * for each pass through the completion queue. The even passes
6242 * will write 1. The odd passes will write 0.
6244 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
6246 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
6248 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
6249 /* 8-lsb timestamp from POR (100-msec resolution) */
6250 uint8_t timestamp_lo;
6251 /* 16-lsb timestamp from POR (100-msec resolution) */
6252 uint16_t timestamp_hi;
6253 /* Event specific data */
6254 uint32_t event_data1;
6255 /* The new MTU of the link in bytes. */
6256 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
6258 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
6261 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
6262 struct hwrm_async_event_cmpl_link_speed_change {
6265 * This field indicates the exact type of the completion.
6266 * By convention, the LSB identifies the length of the
6267 * record in 16B units. Even values indicate 16B
6268 * records. Odd values indicate 32B
6271 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
6273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
6274 /* HWRM Asynchronous Event Information */
6275 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6277 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
6278 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
6279 /* Identifiers of events. */
6281 /* Link speed changed */
6282 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
6284 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
6285 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
6286 /* Event specific data */
6287 uint32_t event_data2;
6290 * This value is written by the NIC such that it will be different
6291 * for each pass through the completion queue. The even passes
6292 * will write 1. The odd passes will write 0.
6294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
6297 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
6299 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
6300 /* 8-lsb timestamp from POR (100-msec resolution) */
6301 uint8_t timestamp_lo;
6302 /* 16-lsb timestamp from POR (100-msec resolution) */
6303 uint16_t timestamp_hi;
6304 /* Event specific data */
6305 uint32_t event_data1;
6307 * When this bit is '1', the link was forced to the
6308 * force_link_speed value.
6310 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
6312 /* The new link speed in 100 Mbps units. */
6313 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
6315 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
6317 /* 100Mb link speed */
6318 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
6319 (UINT32_C(0x1) << 1)
6320 /* 1Gb link speed */
6321 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
6322 (UINT32_C(0xa) << 1)
6323 /* 2Gb link speed */
6324 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
6325 (UINT32_C(0x14) << 1)
6326 /* 25Gb link speed */
6327 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
6328 (UINT32_C(0x19) << 1)
6329 /* 10Gb link speed */
6330 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
6331 (UINT32_C(0x64) << 1)
6332 /* 20Mb link speed */
6333 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
6334 (UINT32_C(0xc8) << 1)
6335 /* 25Gb link speed */
6336 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
6337 (UINT32_C(0xfa) << 1)
6338 /* 40Gb link speed */
6339 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
6340 (UINT32_C(0x190) << 1)
6341 /* 50Gb link speed */
6342 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
6343 (UINT32_C(0x1f4) << 1)
6344 /* 100Gb link speed */
6345 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
6346 (UINT32_C(0x3e8) << 1)
6347 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
6348 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
6350 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6351 UINT32_C(0xffff0000)
6352 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6356 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
6357 struct hwrm_async_event_cmpl_dcb_config_change {
6360 * This field indicates the exact type of the completion.
6361 * By convention, the LSB identifies the length of the
6362 * record in 16B units. Even values indicate 16B
6363 * records. Odd values indicate 32B
6366 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
6368 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
6369 /* HWRM Asynchronous Event Information */
6370 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6372 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
6373 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6374 /* Identifiers of events. */
6376 /* DCB Configuration changed */
6377 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
6379 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
6380 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
6381 /* Event specific data */
6382 uint32_t event_data2;
6383 /* ETS configuration change */
6384 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
6386 /* PFC configuration change */
6387 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
6389 /* APP configuration change */
6390 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
6394 * This value is written by the NIC such that it will be different
6395 * for each pass through the completion queue. The even passes
6396 * will write 1. The odd passes will write 0.
6398 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
6401 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
6403 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
6404 /* 8-lsb timestamp from POR (100-msec resolution) */
6405 uint8_t timestamp_lo;
6406 /* 16-lsb timestamp from POR (100-msec resolution) */
6407 uint16_t timestamp_hi;
6408 /* Event specific data */
6409 uint32_t event_data1;
6411 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6413 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6415 /* Priority recommended for RoCE traffic */
6416 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
6418 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
6421 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
6422 (UINT32_C(0xff) << 16)
6423 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
6424 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
6425 /* Priority recommended for L2 traffic */
6426 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
6427 UINT32_C(0xff000000)
6428 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
6431 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
6432 (UINT32_C(0xff) << 24)
6433 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
6434 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
6437 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
6438 struct hwrm_async_event_cmpl_port_conn_not_allowed {
6441 * This field indicates the exact type of the completion.
6442 * By convention, the LSB identifies the length of the
6443 * record in 16B units. Even values indicate 16B
6444 * records. Odd values indicate 32B
6447 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
6449 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
6451 /* HWRM Asynchronous Event Information */
6452 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6454 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
6455 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6456 /* Identifiers of events. */
6458 /* Port connection not allowed */
6459 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6461 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
6462 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
6463 /* Event specific data */
6464 uint32_t event_data2;
6467 * This value is written by the NIC such that it will be different
6468 * for each pass through the completion queue. The even passes
6469 * will write 1. The odd passes will write 0.
6471 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
6474 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
6476 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
6477 /* 8-lsb timestamp from POR (100-msec resolution) */
6478 uint8_t timestamp_lo;
6479 /* 16-lsb timestamp from POR (100-msec resolution) */
6480 uint16_t timestamp_hi;
6481 /* Event specific data */
6482 uint32_t event_data1;
6484 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6486 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6489 * This value indicates the current port level enforcement policy
6490 * for the optics module when there is an optical module mismatch
6491 * and port is not connected.
6493 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
6495 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
6497 /* No enforcement */
6498 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
6499 (UINT32_C(0x0) << 16)
6500 /* Disable Transmit side Laser. */
6501 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
6502 (UINT32_C(0x1) << 16)
6503 /* Raise a warning message. */
6504 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
6505 (UINT32_C(0x2) << 16)
6506 /* Power down the module. */
6507 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
6508 (UINT32_C(0x3) << 16)
6509 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
6510 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
6513 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
6514 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
6517 * This field indicates the exact type of the completion.
6518 * By convention, the LSB identifies the length of the
6519 * record in 16B units. Even values indicate 16B
6520 * records. Odd values indicate 32B
6523 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
6525 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
6527 /* HWRM Asynchronous Event Information */
6528 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6530 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
6531 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6532 /* Identifiers of events. */
6534 /* Link speed configuration was not allowed */
6535 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6537 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
6538 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
6539 /* Event specific data */
6540 uint32_t event_data2;
6543 * This value is written by the NIC such that it will be different
6544 * for each pass through the completion queue. The even passes
6545 * will write 1. The odd passes will write 0.
6547 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
6550 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
6552 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
6553 /* 8-lsb timestamp from POR (100-msec resolution) */
6554 uint8_t timestamp_lo;
6555 /* 16-lsb timestamp from POR (100-msec resolution) */
6556 uint16_t timestamp_hi;
6557 /* Event specific data */
6558 uint32_t event_data1;
6560 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6562 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6566 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
6567 struct hwrm_async_event_cmpl_link_speed_cfg_change {
6570 * This field indicates the exact type of the completion.
6571 * By convention, the LSB identifies the length of the
6572 * record in 16B units. Even values indicate 16B
6573 * records. Odd values indicate 32B
6576 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
6578 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
6580 /* HWRM Asynchronous Event Information */
6581 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6583 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
6584 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6585 /* Identifiers of events. */
6587 /* Link speed configuration change */
6588 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6590 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
6591 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
6592 /* Event specific data */
6593 uint32_t event_data2;
6596 * This value is written by the NIC such that it will be different
6597 * for each pass through the completion queue. The even passes
6598 * will write 1. The odd passes will write 0.
6600 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
6603 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
6605 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
6606 /* 8-lsb timestamp from POR (100-msec resolution) */
6607 uint8_t timestamp_lo;
6608 /* 16-lsb timestamp from POR (100-msec resolution) */
6609 uint16_t timestamp_hi;
6610 /* Event specific data */
6611 uint32_t event_data1;
6613 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6615 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6618 * If set to 1, it indicates that the supported link speeds
6619 * configuration on the port has changed.
6620 * If set to 0, then there is no change in supported link speeds
6623 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
6626 * If set to 1, it indicates that the link speed configuration
6627 * on the port has become illegal or invalid.
6628 * If set to 0, then the link speed configuration on the port is
6631 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
6635 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
6636 struct hwrm_async_event_cmpl_port_phy_cfg_change {
6639 * This field indicates the exact type of the completion.
6640 * By convention, the LSB identifies the length of the
6641 * record in 16B units. Even values indicate 16B
6642 * records. Odd values indicate 32B
6645 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
6647 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
6649 /* HWRM Asynchronous Event Information */
6650 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6652 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
6653 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6654 /* Identifiers of events. */
6656 /* Port PHY configuration change */
6657 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
6659 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
6660 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
6661 /* Event specific data */
6662 uint32_t event_data2;
6665 * This value is written by the NIC such that it will be different
6666 * for each pass through the completion queue. The even passes
6667 * will write 1. The odd passes will write 0.
6669 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
6672 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
6674 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
6675 /* 8-lsb timestamp from POR (100-msec resolution) */
6676 uint8_t timestamp_lo;
6677 /* 16-lsb timestamp from POR (100-msec resolution) */
6678 uint16_t timestamp_hi;
6679 /* Event specific data */
6680 uint32_t event_data1;
6682 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6684 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6687 * If set to 1, it indicates that the FEC
6688 * configuration on the port has changed.
6689 * If set to 0, then there is no change in FEC configuration.
6691 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
6694 * If set to 1, it indicates that the EEE configuration
6695 * on the port has changed.
6696 * If set to 0, then there is no change in EEE configuration
6699 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
6702 * If set to 1, it indicates that the pause configuration
6703 * on the PHY has changed.
6704 * If set to 0, then there is no change in the pause
6705 * configuration on the PHY.
6707 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
6711 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
6712 struct hwrm_async_event_cmpl_reset_notify {
6715 * This field indicates the exact type of the completion.
6716 * By convention, the LSB identifies the length of the
6717 * record in 16B units. Even values indicate 16B
6718 * records. Odd values indicate 32B
6721 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
6723 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
6724 /* HWRM Asynchronous Event Information */
6725 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
6727 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
6728 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
6729 /* Identifiers of events. */
6731 /* Notify clients of imminent reset. */
6732 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
6734 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
6735 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
6736 /* Event specific data */
6737 uint32_t event_data2;
6740 * This value is written by the NIC such that it will be different
6741 * for each pass through the completion queue. The even passes
6742 * will write 1. The odd passes will write 0.
6744 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
6746 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
6747 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
6749 * 8-lsb timestamp (100-msec resolution)
6750 * The Minimum time required for the Firmware readiness after sending this
6751 * notification to the driver instances.
6753 uint8_t timestamp_lo;
6755 * 16-lsb timestamp (100-msec resolution)
6756 * The Maximum Firmware Reset bail out value in the order of 100
6757 * milli seconds. The driver instances will use this value to re-initiate the
6758 * registration process again if the core firmware didn’t set the ready
6761 uint16_t timestamp_hi;
6762 /* Event specific data */
6763 uint32_t event_data1;
6764 /* Indicates driver action requested */
6765 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
6767 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
6770 * If set to 1, it indicates that the l2 client should
6771 * stop sending in band traffic to Nitro.
6772 * if set to 0, there is no change in L2 client behavior.
6774 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
6777 * If set to 1, it indicates that the L2 client should
6778 * bring down the interface.
6779 * If set to 0, then there is no change in L2 client behavior.
6781 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
6783 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
6784 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
6785 /* Indicates reason for reset. */
6786 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
6788 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
6790 /* A management client has requested reset. */
6791 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
6792 (UINT32_C(0x1) << 8)
6793 /* A fatal firmware exception has occurred. */
6794 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
6795 (UINT32_C(0x2) << 8)
6796 /* A non-fatal firmware exception has occurred. */
6797 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
6798 (UINT32_C(0x3) << 8)
6799 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
6800 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
6802 * Minimum time before driver should attempt access - units 100ms ticks.
6805 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
6806 UINT32_C(0xffff0000)
6807 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
6811 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
6812 struct hwrm_async_event_cmpl_error_recovery {
6815 * This field indicates the exact type of the completion.
6816 * By convention, the LSB identifies the length of the
6817 * record in 16B units. Even values indicate 16B
6818 * records. Odd values indicate 32B
6821 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
6823 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
6824 /* HWRM Asynchronous Event Information */
6825 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
6827 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
6828 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
6829 /* Identifiers of events. */
6832 * This async notification message can be used for selecting or
6833 * deselecting master function for error recovery,
6834 * and to communicate to all the functions whether error recovery
6835 * was enabled/disabled.
6837 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
6839 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
6840 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
6841 /* Event specific data */
6842 uint32_t event_data2;
6845 * This value is written by the NIC such that it will be different
6846 * for each pass through the completion queue. The even passes
6847 * will write 1. The odd passes will write 0.
6849 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
6851 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
6852 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
6853 /* 8-lsb timestamp (100-msec resolution) */
6854 uint8_t timestamp_lo;
6855 /* 16-lsb timestamp (100-msec resolution) */
6856 uint16_t timestamp_hi;
6857 /* Event specific data */
6858 uint32_t event_data1;
6859 /* Indicates driver action requested */
6860 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
6862 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
6865 * If set to 1, this function is selected as Master function.
6866 * This function has responsibility to do 'chip reset' when it
6867 * detects a fatal error. If set to 0, master function functionality
6868 * is disabled on this function.
6870 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
6873 * If set to 1, error recovery is enabled.
6874 * If set to 0, error recovery is disabled.
6876 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
6880 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
6881 struct hwrm_async_event_cmpl_func_drvr_unload {
6884 * This field indicates the exact type of the completion.
6885 * By convention, the LSB identifies the length of the
6886 * record in 16B units. Even values indicate 16B
6887 * records. Odd values indicate 32B
6890 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
6892 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
6893 /* HWRM Asynchronous Event Information */
6894 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
6896 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
6897 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
6898 /* Identifiers of events. */
6900 /* Function driver unloaded */
6901 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
6903 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
6904 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
6905 /* Event specific data */
6906 uint32_t event_data2;
6909 * This value is written by the NIC such that it will be different
6910 * for each pass through the completion queue. The even passes
6911 * will write 1. The odd passes will write 0.
6913 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
6915 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
6917 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
6918 /* 8-lsb timestamp from POR (100-msec resolution) */
6919 uint8_t timestamp_lo;
6920 /* 16-lsb timestamp from POR (100-msec resolution) */
6921 uint16_t timestamp_hi;
6922 /* Event specific data */
6923 uint32_t event_data1;
6925 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
6927 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
6931 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
6932 struct hwrm_async_event_cmpl_func_drvr_load {
6935 * This field indicates the exact type of the completion.
6936 * By convention, the LSB identifies the length of the
6937 * record in 16B units. Even values indicate 16B
6938 * records. Odd values indicate 32B
6941 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
6943 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
6944 /* HWRM Asynchronous Event Information */
6945 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
6947 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
6948 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
6949 /* Identifiers of events. */
6951 /* Function driver loaded */
6952 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
6954 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
6955 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
6956 /* Event specific data */
6957 uint32_t event_data2;
6960 * This value is written by the NIC such that it will be different
6961 * for each pass through the completion queue. The even passes
6962 * will write 1. The odd passes will write 0.
6964 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
6966 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
6967 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
6968 /* 8-lsb timestamp from POR (100-msec resolution) */
6969 uint8_t timestamp_lo;
6970 /* 16-lsb timestamp from POR (100-msec resolution) */
6971 uint16_t timestamp_hi;
6972 /* Event specific data */
6973 uint32_t event_data1;
6975 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
6977 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
6980 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
6981 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
6984 * This field indicates the exact type of the completion.
6985 * By convention, the LSB identifies the length of the
6986 * record in 16B units. Even values indicate 16B
6987 * records. Odd values indicate 32B
6990 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
6992 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
6994 /* HWRM Asynchronous Event Information */
6995 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
6997 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
6998 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
6999 /* Identifiers of events. */
7001 /* Function FLR related processing has completed */
7002 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7004 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
7005 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
7006 /* Event specific data */
7007 uint32_t event_data2;
7010 * This value is written by the NIC such that it will be different
7011 * for each pass through the completion queue. The even passes
7012 * will write 1. The odd passes will write 0.
7014 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
7017 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
7019 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
7020 /* 8-lsb timestamp from POR (100-msec resolution) */
7021 uint8_t timestamp_lo;
7022 /* 16-lsb timestamp from POR (100-msec resolution) */
7023 uint16_t timestamp_hi;
7024 /* Event specific data */
7025 uint32_t event_data1;
7027 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
7029 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
7033 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
7034 struct hwrm_async_event_cmpl_pf_drvr_unload {
7037 * This field indicates the exact type of the completion.
7038 * By convention, the LSB identifies the length of the
7039 * record in 16B units. Even values indicate 16B
7040 * records. Odd values indicate 32B
7043 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
7045 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
7046 /* HWRM Asynchronous Event Information */
7047 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
7049 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
7050 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
7051 /* Identifiers of events. */
7053 /* PF driver unloaded */
7054 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
7056 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
7057 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
7058 /* Event specific data */
7059 uint32_t event_data2;
7062 * This value is written by the NIC such that it will be different
7063 * for each pass through the completion queue. The even passes
7064 * will write 1. The odd passes will write 0.
7066 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
7068 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
7069 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
7070 /* 8-lsb timestamp from POR (100-msec resolution) */
7071 uint8_t timestamp_lo;
7072 /* 16-lsb timestamp from POR (100-msec resolution) */
7073 uint16_t timestamp_hi;
7074 /* Event specific data */
7075 uint32_t event_data1;
7077 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
7079 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
7080 /* Indicates the physical port this pf belongs to */
7081 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
7083 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
7086 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
7087 struct hwrm_async_event_cmpl_pf_drvr_load {
7090 * This field indicates the exact type of the completion.
7091 * By convention, the LSB identifies the length of the
7092 * record in 16B units. Even values indicate 16B
7093 * records. Odd values indicate 32B
7096 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
7098 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
7099 /* HWRM Asynchronous Event Information */
7100 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7102 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
7103 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7104 /* Identifiers of events. */
7106 /* PF driver loaded */
7107 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
7109 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
7110 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
7111 /* Event specific data */
7112 uint32_t event_data2;
7115 * This value is written by the NIC such that it will be different
7116 * for each pass through the completion queue. The even passes
7117 * will write 1. The odd passes will write 0.
7119 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
7121 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7122 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
7123 /* 8-lsb timestamp from POR (100-msec resolution) */
7124 uint8_t timestamp_lo;
7125 /* 16-lsb timestamp from POR (100-msec resolution) */
7126 uint16_t timestamp_hi;
7127 /* Event specific data */
7128 uint32_t event_data1;
7130 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7132 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7133 /* Indicates the physical port this pf belongs to */
7134 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
7136 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
7139 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
7140 struct hwrm_async_event_cmpl_vf_flr {
7143 * This field indicates the exact type of the completion.
7144 * By convention, the LSB identifies the length of the
7145 * record in 16B units. Even values indicate 16B
7146 * records. Odd values indicate 32B
7149 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
7151 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
7152 /* HWRM Asynchronous Event Information */
7153 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
7155 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
7156 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
7157 /* Identifiers of events. */
7159 /* VF Function Level Reset (FLR) */
7160 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
7161 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
7162 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
7163 /* Event specific data */
7164 uint32_t event_data2;
7167 * This value is written by the NIC such that it will be different
7168 * for each pass through the completion queue. The even passes
7169 * will write 1. The odd passes will write 0.
7171 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
7173 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
7174 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
7175 /* 8-lsb timestamp from POR (100-msec resolution) */
7176 uint8_t timestamp_lo;
7177 /* 16-lsb timestamp from POR (100-msec resolution) */
7178 uint16_t timestamp_hi;
7179 /* Event specific data */
7180 uint32_t event_data1;
7182 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
7184 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
7185 /* Indicates the physical function this event occurred on. */
7186 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
7188 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
7191 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
7192 struct hwrm_async_event_cmpl_vf_mac_addr_change {
7195 * This field indicates the exact type of the completion.
7196 * By convention, the LSB identifies the length of the
7197 * record in 16B units. Even values indicate 16B
7198 * records. Odd values indicate 32B
7201 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
7203 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
7204 /* HWRM Asynchronous Event Information */
7205 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7207 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
7208 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
7209 /* Identifiers of events. */
7211 /* VF MAC Address Change */
7212 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
7214 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
7215 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
7216 /* Event specific data */
7217 uint32_t event_data2;
7220 * This value is written by the NIC such that it will be different
7221 * for each pass through the completion queue. The even passes
7222 * will write 1. The odd passes will write 0.
7224 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
7227 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
7229 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
7230 /* 8-lsb timestamp from POR (100-msec resolution) */
7231 uint8_t timestamp_lo;
7232 /* 16-lsb timestamp from POR (100-msec resolution) */
7233 uint16_t timestamp_hi;
7234 /* Event specific data */
7235 uint32_t event_data1;
7237 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
7239 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
7243 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
7244 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
7247 * This field indicates the exact type of the completion.
7248 * By convention, the LSB identifies the length of the
7249 * record in 16B units. Even values indicate 16B
7250 * records. Odd values indicate 32B
7253 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
7255 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
7257 /* HWRM Asynchronous Event Information */
7258 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7260 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
7261 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7262 /* Identifiers of events. */
7264 /* PF-VF communication channel status change. */
7265 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7267 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
7268 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
7269 /* Event specific data */
7270 uint32_t event_data2;
7273 * This value is written by the NIC such that it will be different
7274 * for each pass through the completion queue. The even passes
7275 * will write 1. The odd passes will write 0.
7277 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
7280 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
7282 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
7283 /* 8-lsb timestamp from POR (100-msec resolution) */
7284 uint8_t timestamp_lo;
7285 /* 16-lsb timestamp from POR (100-msec resolution) */
7286 uint16_t timestamp_hi;
7287 /* Event specific data */
7288 uint32_t event_data1;
7290 * If this bit is set to 1, then it indicates that the PF-VF
7291 * communication was lost and it is established.
7292 * If this bit set to 0, then it indicates that the PF-VF
7293 * communication was established and it is lost.
7295 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
7299 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
7300 struct hwrm_async_event_cmpl_vf_cfg_change {
7303 * This field indicates the exact type of the completion.
7304 * By convention, the LSB identifies the length of the
7305 * record in 16B units. Even values indicate 16B
7306 * records. Odd values indicate 32B
7309 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
7311 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
7312 /* HWRM Asynchronous Event Information */
7313 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7315 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
7316 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7317 /* Identifiers of events. */
7319 /* VF Configuration Change */
7320 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
7322 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
7323 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
7324 /* Event specific data */
7325 uint32_t event_data2;
7328 * This value is written by the NIC such that it will be different
7329 * for each pass through the completion queue. The even passes
7330 * will write 1. The odd passes will write 0.
7332 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
7334 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7335 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
7336 /* 8-lsb timestamp from POR (100-msec resolution) */
7337 uint8_t timestamp_lo;
7338 /* 16-lsb timestamp from POR (100-msec resolution) */
7339 uint16_t timestamp_hi;
7341 * Each flag provided in this field indicates a specific VF
7342 * configuration change. At least one of these flags shall be set to 1
7343 * when an asynchronous event completion of this type is provided
7346 uint32_t event_data1;
7348 * If this bit is set to 1, then the value of MTU
7349 * was changed on this VF.
7350 * If set to 0, then this bit should be ignored.
7352 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
7355 * If this bit is set to 1, then the value of MRU
7356 * was changed on this VF.
7357 * If set to 0, then this bit should be ignored.
7359 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
7362 * If this bit is set to 1, then the value of default MAC
7363 * address was changed on this VF.
7364 * If set to 0, then this bit should be ignored.
7366 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
7369 * If this bit is set to 1, then the value of default VLAN
7370 * was changed on this VF.
7371 * If set to 0, then this bit should be ignored.
7373 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
7376 * If this bit is set to 1, then the value of trusted VF enable
7377 * was changed on this VF.
7378 * If set to 0, then this bit should be ignored.
7380 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
7384 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
7385 struct hwrm_async_event_cmpl_llfc_pfc_change {
7388 * This field indicates the exact type of the completion.
7389 * By convention, the LSB identifies the length of the
7390 * record in 16B units. Even values indicate 16B
7391 * records. Odd values indicate 32B
7394 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
7396 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
7397 /* HWRM Asynchronous Event Information */
7398 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7400 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
7401 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7402 /* unused1 is 10 b */
7403 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
7405 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
7406 /* Identifiers of events. */
7408 /* LLFC/PFC Configuration Change */
7409 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
7411 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
7412 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
7413 /* Event specific data */
7414 uint32_t event_data2;
7417 * This value is written by the NIC such that it will be different
7418 * for each pass through the completion queue. The even passes
7419 * will write 1. The odd passes will write 0.
7421 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
7423 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
7425 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
7426 /* 8-lsb timestamp from POR (100-msec resolution) */
7427 uint8_t timestamp_lo;
7428 /* 16-lsb timestamp from POR (100-msec resolution) */
7429 uint16_t timestamp_hi;
7430 /* Event specific data */
7431 uint32_t event_data1;
7432 /* Indicates llfc pfc status change */
7433 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
7435 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
7438 * If this field set to 1, then it indicates that llfc is
7441 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
7444 * If this field is set to 2, then it indicates that pfc
7447 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
7449 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
7450 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
7451 /* Indicates the physical port this llfc pfc change occur */
7452 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
7454 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
7457 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7459 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7463 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
7464 struct hwrm_async_event_cmpl_default_vnic_change {
7467 * This field indicates the exact type of the completion.
7468 * By convention, the LSB identifies the length of the
7469 * record in 16B units. Even values indicate 16B
7470 * records. Odd values indicate 32B
7473 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
7475 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
7477 /* HWRM Asynchronous Event Information */
7478 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7480 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
7481 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7482 /* unused1 is 10 b */
7483 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
7485 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
7487 /* Identifiers of events. */
7489 /* Notification of a default vnic allocation or free */
7490 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
7492 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
7493 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
7494 /* Event specific data */
7495 uint32_t event_data2;
7498 * This value is written by the NIC such that it will be different
7499 * for each pass through the completion queue. The even passes
7500 * will write 1. The odd passes will write 0.
7502 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
7505 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
7507 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
7508 /* 8-lsb timestamp from POR (100-msec resolution) */
7509 uint8_t timestamp_lo;
7510 /* 16-lsb timestamp from POR (100-msec resolution) */
7511 uint16_t timestamp_hi;
7512 /* Event specific data */
7513 uint32_t event_data1;
7514 /* Indicates default vnic configuration change */
7515 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
7517 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
7520 * If this field is set to 1, then it indicates that
7521 * a default VNIC has been allocate.
7523 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
7526 * If this field is set to 2, then it indicates that
7527 * a default VNIC has been freed.
7529 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
7531 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
7532 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
7533 /* Indicates the physical function this event occurred on. */
7534 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
7536 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
7538 /* Indicates the virtual function this event occurred on */
7539 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
7541 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
7545 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
7546 struct hwrm_async_event_cmpl_hw_flow_aged {
7549 * This field indicates the exact type of the completion.
7550 * By convention, the LSB identifies the length of the
7551 * record in 16B units. Even values indicate 16B
7552 * records. Odd values indicate 32B
7555 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
7557 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
7558 /* HWRM Asynchronous Event Information */
7559 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
7561 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
7562 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
7563 /* Identifiers of events. */
7565 /* Notification of a hw flow aged */
7566 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
7568 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
7569 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
7570 /* Event specific data */
7571 uint32_t event_data2;
7574 * This value is written by the NIC such that it will be different
7575 * for each pass through the completion queue. The even passes
7576 * will write 1. The odd passes will write 0.
7578 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
7580 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
7581 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
7582 /* 8-lsb timestamp from POR (100-msec resolution) */
7583 uint8_t timestamp_lo;
7584 /* 16-lsb timestamp from POR (100-msec resolution) */
7585 uint16_t timestamp_hi;
7586 /* Event specific data */
7587 uint32_t event_data1;
7588 /* Indicates flow ID this event occurred on. */
7589 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
7590 UINT32_C(0x7fffffff)
7591 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
7593 /* Indicates flow direction this event occurred on. */
7594 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
7595 UINT32_C(0x80000000)
7597 * If this bit set to 0, then it indicates that the aged
7598 * event was rx flow.
7600 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
7601 (UINT32_C(0x0) << 31)
7603 * If this bit is set to 1, then it indicates that the aged
7604 * event was tx flow.
7606 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
7607 (UINT32_C(0x1) << 31)
7608 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
7609 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
7612 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
7613 struct hwrm_async_event_cmpl_eem_cache_flush_req {
7616 * This field indicates the exact type of the completion.
7617 * By convention, the LSB identifies the length of the
7618 * record in 16B units. Even values indicate 16B
7619 * records. Odd values indicate 32B
7622 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
7624 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
7626 /* HWRM Asynchronous Event Information */
7627 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
7629 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
7630 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
7631 /* Identifiers of events. */
7633 /* Notification of a eem_cache_flush request */
7634 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7636 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
7637 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
7638 /* Event specific data */
7639 uint32_t event_data2;
7642 * This value is written by the NIC such that it will be different
7643 * for each pass through the completion queue. The even passes
7644 * will write 1. The odd passes will write 0.
7646 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
7649 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
7651 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
7652 /* 8-lsb timestamp from POR (100-msec resolution) */
7653 uint8_t timestamp_lo;
7654 /* 16-lsb timestamp from POR (100-msec resolution) */
7655 uint16_t timestamp_hi;
7656 /* Event specific data */
7657 uint32_t event_data1;
7660 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
7661 struct hwrm_async_event_cmpl_eem_cache_flush_done {
7664 * This field indicates the exact type of the completion.
7665 * By convention, the LSB identifies the length of the
7666 * record in 16B units. Even values indicate 16B
7667 * records. Odd values indicate 32B
7670 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
7672 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
7674 /* HWRM Asynchronous Event Information */
7675 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
7677 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
7678 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
7679 /* Identifiers of events. */
7682 * Notification of a host eem_cache_flush has completed. This event
7683 * is generated by the host driver.
7685 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7687 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
7688 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
7689 /* Event specific data */
7690 uint32_t event_data2;
7693 * This value is written by the NIC such that it will be different
7694 * for each pass through the completion queue. The even passes
7695 * will write 1. The odd passes will write 0.
7697 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
7700 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
7702 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
7703 /* 8-lsb timestamp from POR (100-msec resolution) */
7704 uint8_t timestamp_lo;
7705 /* 16-lsb timestamp from POR (100-msec resolution) */
7706 uint16_t timestamp_hi;
7707 /* Event specific data */
7708 uint32_t event_data1;
7709 /* Indicates function ID that this event occurred on. */
7710 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
7712 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
7716 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
7717 struct hwrm_async_event_cmpl_tcp_flag_action_change {
7720 * This field indicates the exact type of the completion.
7721 * By convention, the LSB identifies the length of the
7722 * record in 16B units. Even values indicate 16B
7723 * records. Odd values indicate 32B
7726 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
7728 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
7730 /* HWRM Asynchronous Event Information */
7731 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7733 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
7734 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
7735 /* Identifiers of events. */
7737 /* Notification of tcp flag action change */
7738 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7740 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
7741 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
7742 /* Event specific data */
7743 uint32_t event_data2;
7746 * This value is written by the NIC such that it will be different
7747 * for each pass through the completion queue. The even passes
7748 * will write 1. The odd passes will write 0.
7750 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
7753 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
7755 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
7756 /* 8-lsb timestamp from POR (100-msec resolution) */
7757 uint8_t timestamp_lo;
7758 /* 16-lsb timestamp from POR (100-msec resolution) */
7759 uint16_t timestamp_hi;
7760 /* Event specific data */
7761 uint32_t event_data1;
7764 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
7765 struct hwrm_async_event_cmpl_eem_flow_active {
7768 * This field indicates the exact type of the completion.
7769 * By convention, the LSB identifies the length of the
7770 * record in 16B units. Even values indicate 16B
7771 * records. Odd values indicate 32B
7774 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
7776 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
7777 /* HWRM Asynchronous Event Information */
7778 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
7780 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
7781 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
7782 /* Identifiers of events. */
7784 /* Notification of an active eem flow */
7785 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
7787 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
7788 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
7789 /* Event specific data */
7790 uint32_t event_data2;
7791 /* Indicates the 2nd global id this event occurred on. */
7792 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
7793 UINT32_C(0x3fffffff)
7794 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
7797 * Indicates flow direction of the flow identified by
7800 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
7801 UINT32_C(0x40000000)
7802 /* If this bit is set to 0, then it indicates that this rx flow. */
7803 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
7804 (UINT32_C(0x0) << 30)
7805 /* If this bit is set to 1, then it indicates that this tx flow. */
7806 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
7807 (UINT32_C(0x1) << 30)
7808 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
7809 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
7812 * This value is written by the NIC such that it will be different
7813 * for each pass through the completion queue. The even passes
7814 * will write 1. The odd passes will write 0.
7816 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
7818 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
7820 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
7821 /* 8-lsb timestamp from POR (100-msec resolution) */
7822 uint8_t timestamp_lo;
7823 /* 16-lsb timestamp from POR (100-msec resolution) */
7824 uint16_t timestamp_hi;
7825 /* Event specific data */
7826 uint32_t event_data1;
7827 /* Indicates the 1st global id this event occurred on. */
7828 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
7829 UINT32_C(0x3fffffff)
7830 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
7833 * Indicates flow direction of the flow identified by the
7836 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
7837 UINT32_C(0x40000000)
7838 /* If this bit is set to 0, then it indicates that this is rx flow. */
7839 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
7840 (UINT32_C(0x0) << 30)
7841 /* If this bit is set to 1, then it indicates that this is tx flow. */
7842 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
7843 (UINT32_C(0x1) << 30)
7844 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
7845 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
7847 * Indicates EEM flow aging mode this event occurred on. If
7848 * this bit is set to 0, the event_data1 is the EEM global
7849 * ID. If this bit is set to 1, the event_data1 is the number
7850 * of global ID in the context memory.
7852 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
7853 UINT32_C(0x80000000)
7854 /* EEM flow aging mode 0. */
7855 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
7856 (UINT32_C(0x0) << 31)
7857 /* EEM flow aging mode 1. */
7858 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
7859 (UINT32_C(0x1) << 31)
7860 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
7861 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
7864 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
7865 struct hwrm_async_event_cmpl_eem_cfg_change {
7868 * This field indicates the exact type of the completion.
7869 * By convention, the LSB identifies the length of the
7870 * record in 16B units. Even values indicate 16B
7871 * records. Odd values indicate 32B
7874 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
7876 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
7877 /* HWRM Asynchronous Event Information */
7878 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7880 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
7881 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7882 /* Identifiers of events. */
7884 /* Notification of EEM configuration change */
7885 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
7887 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
7888 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
7889 /* Event specific data */
7890 uint32_t event_data2;
7893 * This value is written by the NIC such that it will be different
7894 * for each pass through the completion queue. The even passes
7895 * will write 1. The odd passes will write 0.
7897 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
7899 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7900 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
7901 /* 8-lsb timestamp from POR (100-msec resolution) */
7902 uint8_t timestamp_lo;
7903 /* 16-lsb timestamp from POR (100-msec resolution) */
7904 uint16_t timestamp_hi;
7905 /* Event specific data */
7906 uint32_t event_data1;
7908 * Value of 1 to indicate EEM TX configuration is enabled. Value of
7909 * 0 to indicate the EEM TX configuration is disabled.
7911 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
7914 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
7915 * to indicate the EEM RX configuration is disabled.
7917 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
7921 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
7922 struct hwrm_async_event_cmpl_quiesce_done {
7925 * This field indicates the exact type of the completion.
7926 * By convention, the LSB identifies the length of the
7927 * record in 16B units. Even values indicate 16B
7928 * records. Odd values indicate 32B
7931 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
7933 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
7934 /* HWRM Asynchronous Event Information */
7935 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
7937 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
7938 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
7939 /* Identifiers of events. */
7941 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
7942 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
7944 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
7945 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
7946 /* Event specific data */
7947 uint32_t event_data2;
7948 /* Status of HWRM_FW_STATE_QUIESCE completion */
7949 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
7951 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
7954 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
7955 * completed successfully.
7957 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
7960 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
7963 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
7966 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
7967 * encountered an error.
7969 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
7971 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
7972 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
7974 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
7976 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
7979 * Additional information about internal hardware state related to
7980 * idle/quiesce state. QUIESCE may succeed per quiesce_status
7981 * regardless of idle_state_flags. If QUIESCE fails, the host may
7982 * inspect idle_state_flags to determine whether a retry is warranted.
7984 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
7986 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
7989 * Failure to quiesce is caused by host not updating the NQ consumer
7992 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
7994 /* Flag 1 indicating partial non-idle state. */
7995 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
7997 /* Flag 2 indicating partial non-idle state. */
7998 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
8000 /* Flag 3 indicating partial non-idle state. */
8001 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
8005 * This value is written by the NIC such that it will be different
8006 * for each pass through the completion queue. The even passes
8007 * will write 1. The odd passes will write 0.
8009 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
8011 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
8012 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
8013 /* 8-lsb timestamp from POR (100-msec resolution) */
8014 uint8_t timestamp_lo;
8015 /* 16-lsb timestamp from POR (100-msec resolution) */
8016 uint16_t timestamp_hi;
8017 /* Event specific data */
8018 uint32_t event_data1;
8019 /* Time stamp for error event */
8020 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
8024 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
8025 struct hwrm_async_event_cmpl_deferred_response {
8028 * This field indicates the exact type of the completion.
8029 * By convention, the LSB identifies the length of the
8030 * record in 16B units. Even values indicate 16B
8031 * records. Odd values indicate 32B
8034 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
8036 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
8037 /* HWRM Asynchronous Event Information */
8038 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
8040 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
8041 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
8042 /* Identifiers of events. */
8045 * An event signifying a HWRM command is in progress and its
8046 * response will be deferred
8048 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
8050 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
8051 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
8052 /* Event specific data */
8053 uint32_t event_data2;
8055 * The PF's mailbox is clear to issue another command.
8056 * A command with this seq_id is still in progress
8057 * and will return a regular HWRM completion when done.
8058 * 'event_data1' field, if non-zero, contains the estimated
8059 * execution time for the command.
8061 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
8063 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
8067 * This value is written by the NIC such that it will be different
8068 * for each pass through the completion queue. The even passes
8069 * will write 1. The odd passes will write 0.
8071 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
8074 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
8076 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
8077 /* 8-lsb timestamp from POR (100-msec resolution) */
8078 uint8_t timestamp_lo;
8079 /* 16-lsb timestamp from POR (100-msec resolution) */
8080 uint16_t timestamp_hi;
8081 /* Estimated remaining time of command execution in ms (if not zero) */
8082 uint32_t event_data1;
8085 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
8086 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
8089 * This field indicates the exact type of the completion.
8090 * By convention, the LSB identifies the length of the
8091 * record in 16B units. Even values indicate 16B
8092 * records. Odd values indicate 32B
8095 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
8097 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
8099 /* HWRM Asynchronous Event Information */
8100 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8102 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
8103 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8104 /* Identifiers of events. */
8106 /* PFC watchdog configuration change for given port/cos */
8107 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
8109 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
8110 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
8111 /* Event specific data */
8112 uint32_t event_data2;
8115 * This value is written by the NIC such that it will be different
8116 * for each pass through the completion queue. The even passes
8117 * will write 1. The odd passes will write 0.
8119 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
8122 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
8124 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
8125 /* 8-lsb timestamp from POR (100-msec resolution) */
8126 uint8_t timestamp_lo;
8127 /* 16-lsb timestamp from POR (100-msec resolution) */
8128 uint16_t timestamp_hi;
8129 /* Event specific data */
8130 uint32_t event_data1;
8132 * 1 in bit position X indicates PFC watchdog should
8135 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
8137 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
8139 /* 1 means PFC WD for COS0 is on, 0 - off. */
8140 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
8142 /* 1 means PFC WD for COS1 is on, 0 - off. */
8143 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
8145 /* 1 means PFC WD for COS2 is on, 0 - off. */
8146 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
8148 /* 1 means PFC WD for COS3 is on, 0 - off. */
8149 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
8151 /* 1 means PFC WD for COS4 is on, 0 - off. */
8152 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
8154 /* 1 means PFC WD for COS5 is on, 0 - off. */
8155 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
8157 /* 1 means PFC WD for COS6 is on, 0 - off. */
8158 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
8160 /* 1 means PFC WD for COS7 is on, 0 - off. */
8161 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
8164 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8166 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8170 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
8171 struct hwrm_async_event_cmpl_fw_trace_msg {
8174 * This field indicates the exact type of the completion.
8175 * By convention, the LSB identifies the length of the
8176 * record in 16B units. Even values indicate 16B
8177 * records. Odd values indicate 32B
8180 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
8182 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
8183 /* HWRM Asynchronous Event Information */
8184 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
8186 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
8187 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
8188 /* Identifiers of events. */
8190 /* Firmware trace log message */
8191 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
8193 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
8194 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
8195 /* Trace byte 0 to 3 */
8196 uint32_t event_data2;
8198 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
8200 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
8202 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
8204 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
8206 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
8208 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
8210 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
8211 UINT32_C(0xff000000)
8212 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
8215 * This value is written by the NIC such that it will be different
8216 * for each pass through the completion queue. The even passes
8217 * will write 1. The odd passes will write 0.
8219 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
8221 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
8222 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
8224 uint8_t timestamp_lo;
8225 /* Indicates if the string is partial or complete. */
8226 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
8228 /* Complete string */
8229 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
8231 /* Partial string */
8232 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
8234 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
8235 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
8236 /* Indicates the firmware that sent the trace message. */
8237 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
8239 /* Primary firmware */
8240 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
8241 (UINT32_C(0x0) << 1)
8242 /* Secondary firmware */
8243 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
8244 (UINT32_C(0x1) << 1)
8245 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
8246 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
8247 /* Trace byte 4 to 5 */
8248 uint16_t timestamp_hi;
8250 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
8252 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
8254 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
8256 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
8257 /* Trace byte 6 to 9 */
8258 uint32_t event_data1;
8260 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
8262 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
8264 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
8266 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
8268 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
8270 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
8272 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
8273 UINT32_C(0xff000000)
8274 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
8277 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
8278 struct hwrm_async_event_cmpl_hwrm_error {
8281 * This field indicates the exact type of the completion.
8282 * By convention, the LSB identifies the length of the
8283 * record in 16B units. Even values indicate 16B
8284 * records. Odd values indicate 32B
8287 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
8289 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
8290 /* HWRM Asynchronous Event Information */
8291 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
8293 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
8294 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
8295 /* Identifiers of events. */
8298 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
8300 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
8301 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
8302 /* Event specific data */
8303 uint32_t event_data2;
8304 /* Severity of HWRM Error */
8305 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
8307 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
8309 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
8311 /* Non-fatal Error */
8312 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
8315 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
8317 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
8318 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
8321 * This value is written by the NIC such that it will be different
8322 * for each pass through the completion queue. The even passes
8323 * will write 1. The odd passes will write 0.
8325 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
8327 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
8328 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
8329 /* 8-lsb timestamp from POR (100-msec resolution) */
8330 uint8_t timestamp_lo;
8331 /* 16-lsb timestamp from POR (100-msec resolution) */
8332 uint16_t timestamp_hi;
8333 /* Event specific data */
8334 uint32_t event_data1;
8335 /* Time stamp for error event */
8336 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
8340 /*******************
8342 *******************/
8345 /* hwrm_func_reset_input (size:192b/24B) */
8346 struct hwrm_func_reset_input {
8347 /* The HWRM command request type. */
8350 * The completion ring to send the completion event on. This should
8351 * be the NQ ID returned from the `nq_alloc` HWRM command.
8355 * The sequence ID is used by the driver for tracking multiple
8356 * commands. This ID is treated as opaque data by the firmware and
8357 * the value is returned in the `hwrm_resp_hdr` upon completion.
8361 * The target ID of the command:
8362 * * 0x0-0xFFF8 - The function ID
8363 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8364 * * 0xFFFD - Reserved for user-space HWRM interface
8369 * A physical address pointer pointing to a host buffer that the
8370 * command's response data will be written. This can be either a host
8371 * physical address (HPA) or a guest physical address (GPA) and must
8372 * point to a physically contiguous block of memory.
8377 * This bit must be '1' for the vf_id_valid field to be
8380 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
8382 * The ID of the VF that this PF is trying to reset.
8383 * Only the parent PF shall be allowed to reset a child VF.
8385 * A parent PF driver shall use this field only when a specific child VF
8386 * is requested to be reset.
8389 /* This value indicates the level of a function reset. */
8390 uint8_t func_reset_level;
8392 * Reset the caller function and its children VFs (if any). If no
8393 * children functions exist, then reset the caller function only.
8395 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
8397 /* Reset the caller function only */
8398 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
8401 * Reset all children VFs of the caller function driver if the
8402 * caller is a PF driver.
8403 * It is an error to specify this level by a VF driver.
8404 * It is an error to specify this level by a PF driver with
8407 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
8410 * Reset a specific VF of the caller function driver if the caller
8411 * is the parent PF driver.
8412 * It is an error to specify this level by a VF driver.
8413 * It is an error to specify this level by a PF driver that is not
8414 * the parent of the VF that is being requested to reset.
8416 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
8418 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
8419 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
8423 /* hwrm_func_reset_output (size:128b/16B) */
8424 struct hwrm_func_reset_output {
8425 /* The specific error status for the command. */
8426 uint16_t error_code;
8427 /* The HWRM command request type. */
8429 /* The sequence ID from the original command. */
8431 /* The length of the response data in number of bytes. */
8433 uint8_t unused_0[7];
8435 * This field is used in Output records to indicate that the output
8436 * is completely written to RAM. This field should be read as '1'
8437 * to indicate that the output has been completely written.
8438 * When writing a command completion or response to an internal processor,
8439 * the order of writes has to be such that this field is written last.
8444 /********************
8445 * hwrm_func_getfid *
8446 ********************/
8449 /* hwrm_func_getfid_input (size:192b/24B) */
8450 struct hwrm_func_getfid_input {
8451 /* The HWRM command request type. */
8454 * The completion ring to send the completion event on. This should
8455 * be the NQ ID returned from the `nq_alloc` HWRM command.
8459 * The sequence ID is used by the driver for tracking multiple
8460 * commands. This ID is treated as opaque data by the firmware and
8461 * the value is returned in the `hwrm_resp_hdr` upon completion.
8465 * The target ID of the command:
8466 * * 0x0-0xFFF8 - The function ID
8467 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8468 * * 0xFFFD - Reserved for user-space HWRM interface
8473 * A physical address pointer pointing to a host buffer that the
8474 * command's response data will be written. This can be either a host
8475 * physical address (HPA) or a guest physical address (GPA) and must
8476 * point to a physically contiguous block of memory.
8481 * This bit must be '1' for the pci_id field to be
8484 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
8486 * This value is the PCI ID of the queried function.
8487 * If ARI is enabled, then it is
8488 * Bus Number (8b):Function Number(8b). Otherwise, it is
8489 * Bus Number (8b):Device Number (5b):Function Number(3b).
8492 uint8_t unused_0[2];
8495 /* hwrm_func_getfid_output (size:128b/16B) */
8496 struct hwrm_func_getfid_output {
8497 /* The specific error status for the command. */
8498 uint16_t error_code;
8499 /* The HWRM command request type. */
8501 /* The sequence ID from the original command. */
8503 /* The length of the response data in number of bytes. */
8506 * FID value. This value is used to identify operations on the PCI
8507 * bus as belonging to a particular PCI function.
8510 uint8_t unused_0[5];
8512 * This field is used in Output records to indicate that the output
8513 * is completely written to RAM. This field should be read as '1'
8514 * to indicate that the output has been completely written.
8515 * When writing a command completion or response to an internal processor,
8516 * the order of writes has to be such that this field is written last.
8521 /**********************
8522 * hwrm_func_vf_alloc *
8523 **********************/
8526 /* hwrm_func_vf_alloc_input (size:192b/24B) */
8527 struct hwrm_func_vf_alloc_input {
8528 /* The HWRM command request type. */
8531 * The completion ring to send the completion event on. This should
8532 * be the NQ ID returned from the `nq_alloc` HWRM command.
8536 * The sequence ID is used by the driver for tracking multiple
8537 * commands. This ID is treated as opaque data by the firmware and
8538 * the value is returned in the `hwrm_resp_hdr` upon completion.
8542 * The target ID of the command:
8543 * * 0x0-0xFFF8 - The function ID
8544 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8545 * * 0xFFFD - Reserved for user-space HWRM interface
8550 * A physical address pointer pointing to a host buffer that the
8551 * command's response data will be written. This can be either a host
8552 * physical address (HPA) or a guest physical address (GPA) and must
8553 * point to a physically contiguous block of memory.
8558 * This bit must be '1' for the first_vf_id field to be
8561 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8563 * This value is used to identify a Virtual Function (VF).
8564 * The scope of VF ID is local within a PF.
8566 uint16_t first_vf_id;
8567 /* The number of virtual functions requested. */
8571 /* hwrm_func_vf_alloc_output (size:128b/16B) */
8572 struct hwrm_func_vf_alloc_output {
8573 /* The specific error status for the command. */
8574 uint16_t error_code;
8575 /* The HWRM command request type. */
8577 /* The sequence ID from the original command. */
8579 /* The length of the response data in number of bytes. */
8581 /* The ID of the first VF allocated. */
8582 uint16_t first_vf_id;
8583 uint8_t unused_0[5];
8585 * This field is used in Output records to indicate that the output
8586 * is completely written to RAM. This field should be read as '1'
8587 * to indicate that the output has been completely written.
8588 * When writing a command completion or response to an internal processor,
8589 * the order of writes has to be such that this field is written last.
8594 /*********************
8595 * hwrm_func_vf_free *
8596 *********************/
8599 /* hwrm_func_vf_free_input (size:192b/24B) */
8600 struct hwrm_func_vf_free_input {
8601 /* The HWRM command request type. */
8604 * The completion ring to send the completion event on. This should
8605 * be the NQ ID returned from the `nq_alloc` HWRM command.
8609 * The sequence ID is used by the driver for tracking multiple
8610 * commands. This ID is treated as opaque data by the firmware and
8611 * the value is returned in the `hwrm_resp_hdr` upon completion.
8615 * The target ID of the command:
8616 * * 0x0-0xFFF8 - The function ID
8617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8618 * * 0xFFFD - Reserved for user-space HWRM interface
8623 * A physical address pointer pointing to a host buffer that the
8624 * command's response data will be written. This can be either a host
8625 * physical address (HPA) or a guest physical address (GPA) and must
8626 * point to a physically contiguous block of memory.
8631 * This bit must be '1' for the first_vf_id field to be
8634 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8636 * This value is used to identify a Virtual Function (VF).
8637 * The scope of VF ID is local within a PF.
8639 uint16_t first_vf_id;
8641 * The number of virtual functions requested.
8642 * 0xFFFF - Cleanup all children of this PF.
8647 /* hwrm_func_vf_free_output (size:128b/16B) */
8648 struct hwrm_func_vf_free_output {
8649 /* The specific error status for the command. */
8650 uint16_t error_code;
8651 /* The HWRM command request type. */
8653 /* The sequence ID from the original command. */
8655 /* The length of the response data in number of bytes. */
8657 uint8_t unused_0[7];
8659 * This field is used in Output records to indicate that the output
8660 * is completely written to RAM. This field should be read as '1'
8661 * to indicate that the output has been completely written.
8662 * When writing a command completion or response to an internal processor,
8663 * the order of writes has to be such that this field is written last.
8668 /********************
8669 * hwrm_func_vf_cfg *
8670 ********************/
8673 /* hwrm_func_vf_cfg_input (size:448b/56B) */
8674 struct hwrm_func_vf_cfg_input {
8675 /* The HWRM command request type. */
8678 * The completion ring to send the completion event on. This should
8679 * be the NQ ID returned from the `nq_alloc` HWRM command.
8683 * The sequence ID is used by the driver for tracking multiple
8684 * commands. This ID is treated as opaque data by the firmware and
8685 * the value is returned in the `hwrm_resp_hdr` upon completion.
8689 * The target ID of the command:
8690 * * 0x0-0xFFF8 - The function ID
8691 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8692 * * 0xFFFD - Reserved for user-space HWRM interface
8697 * A physical address pointer pointing to a host buffer that the
8698 * command's response data will be written. This can be either a host
8699 * physical address (HPA) or a guest physical address (GPA) and must
8700 * point to a physically contiguous block of memory.
8705 * This bit must be '1' for the mtu field to be
8708 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
8711 * This bit must be '1' for the guest_vlan field to be
8714 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
8717 * This bit must be '1' for the async_event_cr field to be
8720 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8723 * This bit must be '1' for the dflt_mac_addr field to be
8726 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8729 * This bit must be '1' for the num_rsscos_ctxs field to be
8732 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8735 * This bit must be '1' for the num_cmpl_rings field to be
8738 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8741 * This bit must be '1' for the num_tx_rings field to be
8744 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8747 * This bit must be '1' for the num_rx_rings field to be
8750 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8753 * This bit must be '1' for the num_l2_ctxs field to be
8756 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8759 * This bit must be '1' for the num_vnics field to be
8762 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
8765 * This bit must be '1' for the num_stat_ctxs field to be
8768 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8771 * This bit must be '1' for the num_hw_ring_grps field to be
8774 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8777 * The maximum transmission unit requested on the function.
8778 * The HWRM should make sure that the mtu of
8779 * the function does not exceed the mtu of the physical
8780 * port that this function is associated with.
8782 * In addition to requesting mtu per function, it is
8783 * possible to configure mtu per transmit ring.
8784 * By default, the mtu of each transmit ring associated
8785 * with a function is equal to the mtu of the function.
8786 * The HWRM should make sure that the mtu of each transmit
8787 * ring that is assigned to a function has a valid mtu.
8791 * The guest VLAN for the function being configured.
8792 * This field's format is same as 802.1Q Tag's
8793 * Tag Control Information (TCI) format that includes both
8794 * Priority Code Point (PCP) and VLAN Identifier (VID).
8796 uint16_t guest_vlan;
8798 * ID of the target completion ring for receiving asynchronous
8799 * event completions. If this field is not valid, then the
8800 * HWRM shall use the default completion ring of the function
8801 * that is being configured as the target completion ring for
8802 * providing any asynchronous event completions for that
8804 * If this field is valid, then the HWRM shall use the
8805 * completion ring identified by this ID as the target
8806 * completion ring for providing any asynchronous event
8807 * completions for the function that is being configured.
8809 uint16_t async_event_cr;
8811 * This value is the current MAC address requested by the VF
8812 * driver to be configured on this VF. A value of
8813 * 00-00-00-00-00-00 indicates no MAC address configuration
8814 * is requested by the VF driver.
8815 * The parent PF driver may reject or overwrite this
8818 uint8_t dflt_mac_addr[6];
8821 * This bit requests that the firmware test to see if all the assets
8822 * requested in this command (i.e. number of TX rings) are available.
8823 * The firmware will return an error if the requested assets are
8824 * not available. The firwmare will NOT reserve the assets if they
8827 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8830 * This bit requests that the firmware test to see if all the assets
8831 * requested in this command (i.e. number of RX rings) are available.
8832 * The firmware will return an error if the requested assets are
8833 * not available. The firwmare will NOT reserve the assets if they
8836 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8839 * This bit requests that the firmware test to see if all the assets
8840 * requested in this command (i.e. number of CMPL rings) are available.
8841 * The firmware will return an error if the requested assets are
8842 * not available. The firwmare will NOT reserve the assets if they
8845 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8848 * This bit requests that the firmware test to see if all the assets
8849 * requested in this command (i.e. number of RSS ctx) are available.
8850 * The firmware will return an error if the requested assets are
8851 * not available. The firwmare will NOT reserve the assets if they
8854 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8857 * This bit requests that the firmware test to see if all the assets
8858 * requested in this command (i.e. number of ring groups) are available.
8859 * The firmware will return an error if the requested assets are
8860 * not available. The firwmare will NOT reserve the assets if they
8863 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8866 * This bit requests that the firmware test to see if all the assets
8867 * requested in this command (i.e. number of stat ctx) are available.
8868 * The firmware will return an error if the requested assets are
8869 * not available. The firwmare will NOT reserve the assets if they
8872 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8875 * This bit requests that the firmware test to see if all the assets
8876 * requested in this command (i.e. number of VNICs) are available.
8877 * The firmware will return an error if the requested assets are
8878 * not available. The firwmare will NOT reserve the assets if they
8881 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8884 * This bit requests that the firmware test to see if all the assets
8885 * requested in this command (i.e. number of L2 ctx) are available.
8886 * The firmware will return an error if the requested assets are
8887 * not available. The firwmare will NOT reserve the assets if they
8890 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8892 /* The number of RSS/COS contexts requested for the VF. */
8893 uint16_t num_rsscos_ctxs;
8894 /* The number of completion rings requested for the VF. */
8895 uint16_t num_cmpl_rings;
8896 /* The number of transmit rings requested for the VF. */
8897 uint16_t num_tx_rings;
8898 /* The number of receive rings requested for the VF. */
8899 uint16_t num_rx_rings;
8900 /* The number of L2 contexts requested for the VF. */
8901 uint16_t num_l2_ctxs;
8902 /* The number of vnics requested for the VF. */
8904 /* The number of statistic contexts requested for the VF. */
8905 uint16_t num_stat_ctxs;
8906 /* The number of HW ring groups requested for the VF. */
8907 uint16_t num_hw_ring_grps;
8908 uint8_t unused_0[4];
8911 /* hwrm_func_vf_cfg_output (size:128b/16B) */
8912 struct hwrm_func_vf_cfg_output {
8913 /* The specific error status for the command. */
8914 uint16_t error_code;
8915 /* The HWRM command request type. */
8917 /* The sequence ID from the original command. */
8919 /* The length of the response data in number of bytes. */
8921 uint8_t unused_0[7];
8923 * This field is used in Output records to indicate that the output
8924 * is completely written to RAM. This field should be read as '1'
8925 * to indicate that the output has been completely written.
8926 * When writing a command completion or response to an internal processor,
8927 * the order of writes has to be such that this field is written last.
8932 /*******************
8934 *******************/
8937 /* hwrm_func_qcaps_input (size:192b/24B) */
8938 struct hwrm_func_qcaps_input {
8939 /* The HWRM command request type. */
8942 * The completion ring to send the completion event on. This should
8943 * be the NQ ID returned from the `nq_alloc` HWRM command.
8947 * The sequence ID is used by the driver for tracking multiple
8948 * commands. This ID is treated as opaque data by the firmware and
8949 * the value is returned in the `hwrm_resp_hdr` upon completion.
8953 * The target ID of the command:
8954 * * 0x0-0xFFF8 - The function ID
8955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8956 * * 0xFFFD - Reserved for user-space HWRM interface
8961 * A physical address pointer pointing to a host buffer that the
8962 * command's response data will be written. This can be either a host
8963 * physical address (HPA) or a guest physical address (GPA) and must
8964 * point to a physically contiguous block of memory.
8968 * Function ID of the function that is being queried.
8969 * 0xFF... (All Fs) if the query is for the requesting
8971 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
8972 * to be used by a trusted VF to query its parent PF.
8975 uint8_t unused_0[6];
8978 /* hwrm_func_qcaps_output (size:704b/88B) */
8979 struct hwrm_func_qcaps_output {
8980 /* The specific error status for the command. */
8981 uint16_t error_code;
8982 /* The HWRM command request type. */
8984 /* The sequence ID from the original command. */
8986 /* The length of the response data in number of bytes. */
8989 * FID value. This value is used to identify operations on the PCI
8990 * bus as belonging to a particular PCI function.
8994 * Port ID of port that this function is associated with.
8995 * Valid only for the PF.
8996 * 0xFF... (All Fs) if this function is not associated with
8998 * 0xFF... (All Fs) if this function is called from a VF.
9002 /* If 1, then Push mode is supported on this function. */
9003 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
9006 * If 1, then the global MSI-X auto-masking is enabled for the
9009 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
9012 * If 1, then the Precision Time Protocol (PTP) processing
9013 * is supported on this function.
9014 * The HWRM should enable PTP on only a single Physical
9015 * Function (PF) per port.
9017 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
9020 * If 1, then RDMA over Converged Ethernet (RoCE) v1
9021 * is supported on this function.
9023 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
9026 * If 1, then RDMA over Converged Ethernet (RoCE) v2
9027 * is supported on this function.
9029 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
9032 * If 1, then control and configuration of WoL magic packet
9033 * are supported on this function.
9035 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
9038 * If 1, then control and configuration of bitmap pattern
9039 * packet are supported on this function.
9041 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
9044 * If set to 1, then the control and configuration of rate limit
9045 * of an allocated TX ring on the queried function is supported.
9047 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
9050 * If 1, then control and configuration of minimum and
9051 * maximum bandwidths are supported on the queried function.
9053 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
9056 * If the query is for a VF, then this flag shall be ignored.
9057 * If this query is for a PF and this flag is set to 1,
9058 * then the PF has the capability to set the rate limits
9059 * on the TX rings of its children VFs.
9060 * If this query is for a PF and this flag is set to 0, then
9061 * the PF does not have the capability to set the rate limits
9062 * on the TX rings of its children VFs.
9064 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
9067 * If the query is for a VF, then this flag shall be ignored.
9068 * If this query is for a PF and this flag is set to 1,
9069 * then the PF has the capability to set the minimum and/or
9070 * maximum bandwidths for its children VFs.
9071 * If this query is for a PF and this flag is set to 0, then
9072 * the PF does not have the capability to set the minimum or
9073 * maximum bandwidths for its children VFs.
9075 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
9078 * Standard TX Ring mode is used for the allocation of TX ring
9079 * and underlying scheduling resources that allow bandwidth
9080 * reservation and limit settings on the queried function.
9081 * If set to 1, then standard TX ring mode is supported
9082 * on the queried function.
9083 * If set to 0, then standard TX ring mode is not available
9084 * on the queried function.
9086 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
9089 * If the query is for a VF, then this flag shall be ignored,
9090 * If this query is for a PF and this flag is set to 1,
9091 * then the PF has the capability to detect GENEVE tunnel
9094 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
9097 * If the query is for a VF, then this flag shall be ignored,
9098 * If this query is for a PF and this flag is set to 1,
9099 * then the PF has the capability to detect NVGRE tunnel
9102 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
9105 * If the query is for a VF, then this flag shall be ignored,
9106 * If this query is for a PF and this flag is set to 1,
9107 * then the PF has the capability to detect GRE tunnel
9110 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
9113 * If the query is for a VF, then this flag shall be ignored,
9114 * If this query is for a PF and this flag is set to 1,
9115 * then the PF has the capability to detect MPLS tunnel
9118 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
9121 * If the query is for a VF, then this flag shall be ignored,
9122 * If this query is for a PF and this flag is set to 1,
9123 * then the PF has the capability to support pcie stats.
9125 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
9128 * If the query is for a VF, then this flag shall be ignored,
9129 * If this query is for a PF and this flag is set to 1,
9130 * then the PF has the capability to adopt the VF's belonging
9133 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
9136 * If the query is for a VF, then this flag shall be ignored,
9137 * If this query is for a PF and this flag is set to 1,
9138 * then the PF has the administrative privilege to configure another PF
9140 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
9143 * If the query is for a VF, then this flag shall be ignored.
9144 * If this query is for a PF and this flag is set to 1, then
9145 * the PF will know that the firmware has the capability to track
9146 * the virtual link status.
9148 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
9151 * If 1, then this function supports the push mode that uses
9152 * write combine buffers and the long inline tx buffer descriptor.
9154 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
9157 * If 1, then FW has capability to allocate TX rings dynamically
9158 * in ring alloc even if PF reserved pool is zero.
9159 * This bit will be used only for PFs.
9161 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
9164 * When this bit is '1', it indicates that core firmware is
9165 * capable of Hot Reset.
9167 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
9170 * This flag will be set to 1 by the FW if FW supports adapter error
9173 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
9176 * If the query is for a VF, then this flag shall be ignored.
9177 * If this query is for a PF and this flag is set to 1, then
9178 * the PF has the capability to support extended stats.
9180 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
9183 * If the query is for a VF, then this flag shall be ignored.
9184 * If this query is for a PF and this flag is set to 1, then host
9185 * must initiate reset or reload (or fastboot) the firmware image
9186 * upon detection of device shutdown state.
9188 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
9191 * If the query is for a VF, then this flag (always set to 0) shall
9192 * be ignored. If this query is for a PF and this flag is set to 1,
9193 * host, when registered for the default vnic change async event,
9194 * receives async notification whenever a default vnic state is
9195 * changed for any of child or adopted VFs.
9197 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
9199 /* If set to 1, then the vlan acceleration for TX is disabled. */
9200 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
9203 * When this bit is '1', it indicates that core firmware supports
9204 * DBG_COREDUMP_XXX commands.
9206 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
9207 UINT32_C(0x10000000)
9209 * When this bit is '1', it indicates that core firmware supports
9210 * DBG_CRASHDUMP_XXX commands.
9212 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
9213 UINT32_C(0x20000000)
9215 * If the query is for a VF, then this flag should be ignored.
9216 * If the query is for a PF and this flag is set to 1, then
9217 * the PF has the capability to support retrieval of
9218 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
9219 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
9220 * If this flag is set to 1, only that (supported) command should
9221 * be used for retrieval of PFC related statistics (rather than
9222 * hwrm_port_qstats_ext command, which could previously be used).
9224 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
9225 UINT32_C(0x40000000)
9227 * When this bit is '1', it indicates that core firmware supports
9230 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
9231 UINT32_C(0x80000000)
9233 * This value is current MAC address configured for this
9234 * function. A value of 00-00-00-00-00-00 indicates no
9235 * MAC address is currently configured.
9237 uint8_t mac_address[6];
9239 * The maximum number of RSS/COS contexts that can be
9240 * allocated to the function.
9242 uint16_t max_rsscos_ctx;
9244 * The maximum number of completion rings that can be
9245 * allocated to the function.
9247 uint16_t max_cmpl_rings;
9249 * The maximum number of transmit rings that can be
9250 * allocated to the function.
9252 uint16_t max_tx_rings;
9254 * The maximum number of receive rings that can be
9255 * allocated to the function.
9257 uint16_t max_rx_rings;
9259 * The maximum number of L2 contexts that can be
9260 * allocated to the function.
9262 uint16_t max_l2_ctxs;
9264 * The maximum number of VNICs that can be
9265 * allocated to the function.
9269 * The identifier for the first VF enabled on a PF. This
9270 * is valid only on the PF with SR-IOV enabled.
9271 * 0xFF... (All Fs) if this command is called on a PF with
9272 * SR-IOV disabled or on a VF.
9274 uint16_t first_vf_id;
9276 * The maximum number of VFs that can be
9277 * allocated to the function. This is valid only on the
9278 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
9279 * command is called on a PF with SR-IOV disabled or
9284 * The maximum number of statistic contexts that can be
9285 * allocated to the function.
9287 uint16_t max_stat_ctx;
9289 * The maximum number of Encapsulation records that can be
9290 * offloaded by this function.
9292 uint32_t max_encap_records;
9294 * The maximum number of decapsulation records that can
9295 * be offloaded by this function.
9297 uint32_t max_decap_records;
9299 * The maximum number of Exact Match (EM) flows that can be
9300 * offloaded by this function on the TX side.
9302 uint32_t max_tx_em_flows;
9304 * The maximum number of Wildcard Match (WM) flows that can
9305 * be offloaded by this function on the TX side.
9307 uint32_t max_tx_wm_flows;
9309 * The maximum number of Exact Match (EM) flows that can be
9310 * offloaded by this function on the RX side.
9312 uint32_t max_rx_em_flows;
9314 * The maximum number of Wildcard Match (WM) flows that can
9315 * be offloaded by this function on the RX side.
9317 uint32_t max_rx_wm_flows;
9319 * The maximum number of multicast filters that can
9320 * be supported by this function on the RX side.
9322 uint32_t max_mcast_filters;
9324 * The maximum value of flow_id that can be supported
9325 * in completion records.
9327 uint32_t max_flow_id;
9329 * The maximum number of HW ring groups that can be
9330 * supported on this function.
9332 uint32_t max_hw_ring_grps;
9334 * The maximum number of strict priority transmit rings
9335 * that can be allocated to the function.
9336 * This number indicates the maximum number of TX rings
9337 * that can be assigned strict priorities out of the
9338 * maximum number of TX rings that can be allocated
9339 * (max_tx_rings) to the function.
9341 uint16_t max_sp_tx_rings;
9342 uint8_t unused_0[2];
9345 * If 1, the device can be configured to set the ECN bits in the
9346 * IP header of received packets if the receive queue length
9347 * exceeds a given threshold.
9349 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
9352 * If 1, the device can report the number of received packets
9353 * that it marked as having experienced congestion.
9355 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
9358 * If 1, the device can report extended hw statistics (including
9359 * additional tpa statistics).
9361 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
9364 * If set to 1, then the core firmware has support to enable/
9365 * disable hot reset support for interface dynamically through
9368 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
9370 uint8_t unused_1[3];
9372 * This field is used in Output records to indicate that the output
9373 * is completely written to RAM. This field should be read as '1'
9374 * to indicate that the output has been completely written.
9375 * When writing a command completion or response to an internal processor,
9376 * the order of writes has to be such that this field is written last.
9386 /* hwrm_func_qcfg_input (size:192b/24B) */
9387 struct hwrm_func_qcfg_input {
9388 /* The HWRM command request type. */
9391 * The completion ring to send the completion event on. This should
9392 * be the NQ ID returned from the `nq_alloc` HWRM command.
9396 * The sequence ID is used by the driver for tracking multiple
9397 * commands. This ID is treated as opaque data by the firmware and
9398 * the value is returned in the `hwrm_resp_hdr` upon completion.
9402 * The target ID of the command:
9403 * * 0x0-0xFFF8 - The function ID
9404 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9405 * * 0xFFFD - Reserved for user-space HWRM interface
9410 * A physical address pointer pointing to a host buffer that the
9411 * command's response data will be written. This can be either a host
9412 * physical address (HPA) or a guest physical address (GPA) and must
9413 * point to a physically contiguous block of memory.
9417 * Function ID of the function that is being queried.
9418 * 0xFF... (All Fs) if the query is for the requesting
9420 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9421 * to be used by a trusted VF to query its parent PF.
9424 uint8_t unused_0[6];
9427 /* hwrm_func_qcfg_output (size:768b/96B) */
9428 struct hwrm_func_qcfg_output {
9429 /* The specific error status for the command. */
9430 uint16_t error_code;
9431 /* The HWRM command request type. */
9433 /* The sequence ID from the original command. */
9435 /* The length of the response data in number of bytes. */
9438 * FID value. This value is used to identify operations on the PCI
9439 * bus as belonging to a particular PCI function.
9443 * Port ID of port that this function is associated with.
9444 * 0xFF... (All Fs) if this function is not associated with
9449 * This value is the current VLAN setting for this
9450 * function. The value of 0 for this field indicates
9451 * no priority tagging or VLAN is used.
9452 * This field's format is same as 802.1Q Tag's
9453 * Tag Control Information (TCI) format that includes both
9454 * Priority Code Point (PCP) and VLAN Identifier (VID).
9459 * If 1, then magic packet based Out-Of-Box WoL is enabled on
9460 * the port associated with this function.
9462 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
9465 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
9466 * on the port associated with this function.
9468 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
9471 * If set to 1, then FW based DCBX agent is enabled and running on
9472 * the port associated with this function.
9473 * If set to 0, then DCBX agent is not running in the firmware.
9475 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
9478 * Standard TX Ring mode is used for the allocation of TX ring
9479 * and underlying scheduling resources that allow bandwidth
9480 * reservation and limit settings on the queried function.
9481 * If set to 1, then standard TX ring mode is enabled
9482 * on the queried function.
9483 * If set to 0, then the standard TX ring mode is disabled
9484 * on the queried function. In this extended TX ring resource
9485 * mode, the minimum and maximum bandwidth settings are not
9486 * supported to allow the allocation of TX rings to span multiple
9489 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
9492 * If set to 1 then FW based LLDP agent is enabled and running on
9493 * the port associated with this function.
9494 * If set to 0 then the LLDP agent is not running in the firmware.
9496 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
9499 * If set to 1, then multi-host mode is active for this function.
9500 * If set to 0, then multi-host mode is inactive for this function
9501 * or not applicable for this device.
9503 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
9506 * If the function that is being queried is a PF, then the HWRM shall
9507 * set this field to 0 and the HWRM client shall ignore this field.
9508 * If the function that is being queried is a VF, then the HWRM shall
9509 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
9510 * shall set this field to 0.
9512 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
9515 * If set to 1, then secure mode is enabled for this function or device.
9516 * If set to 0, then secure mode is disabled (or normal mode) for this
9517 * function or device.
9519 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
9522 * If set to 1, then this PF is enabled with a preboot driver that
9523 * requires access to the legacy L2 ring model and legacy 32b
9524 * doorbells. If set to 0, then this PF is not allowed to use
9525 * the legacy L2 rings. This feature is not allowed on VFs and
9526 * is only relevant for devices that require a context backing
9529 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
9532 * If set to 1, then the firmware and all currently registered driver
9533 * instances support hot reset. The hot reset support will be updated
9534 * dynamically based on the driver interface advertisement.
9535 * If set to 0, then the adapter is not currently able to initiate
9538 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
9541 * This value is current MAC address configured for this
9542 * function. A value of 00-00-00-00-00-00 indicates no
9543 * MAC address is currently configured.
9545 uint8_t mac_address[6];
9547 * This value is current PCI ID of this
9548 * function. If ARI is enabled, then it is
9549 * Bus Number (8b):Function Number(8b). Otherwise, it is
9550 * Bus Number (8b):Device Number (4b):Function Number(4b).
9551 * If multi-host mode is active, the 4 lsb will indicate
9552 * the PF index for this function.
9556 * The number of RSS/COS contexts currently
9557 * allocated to the function.
9559 uint16_t alloc_rsscos_ctx;
9561 * The number of completion rings currently allocated to
9562 * the function. This does not include the rings allocated
9563 * to any children functions if any.
9565 uint16_t alloc_cmpl_rings;
9567 * The number of transmit rings currently allocated to
9568 * the function. This does not include the rings allocated
9569 * to any children functions if any.
9571 uint16_t alloc_tx_rings;
9573 * The number of receive rings currently allocated to
9574 * the function. This does not include the rings allocated
9575 * to any children functions if any.
9577 uint16_t alloc_rx_rings;
9578 /* The allocated number of L2 contexts to the function. */
9579 uint16_t alloc_l2_ctx;
9580 /* The allocated number of vnics to the function. */
9581 uint16_t alloc_vnics;
9583 * The maximum transmission unit of the function.
9584 * If the reported mtu value is non-zero then it will used for the
9585 * rings allocated on this function. otherwise the default
9586 * value is used if ring MTU is not specified.
9590 * The maximum receive unit of the function.
9591 * For vnics allocated on this function, this default
9592 * value is used if vnic MRU is not specified.
9595 /* The statistics context assigned to a function. */
9596 uint16_t stat_ctx_id;
9598 * The HWRM shall return Unknown value for this field
9599 * when this command is used to query VF's configuration.
9601 uint8_t port_partition_type;
9602 /* Single physical function */
9603 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
9604 /* Multiple physical functions */
9605 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
9606 /* Network Partitioning 1.0 */
9607 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
9608 /* Network Partitioning 1.5 */
9609 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
9610 /* Network Partitioning 2.0 */
9611 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
9613 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
9615 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
9616 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
9618 * This field will indicate number of physical functions on this port_partition.
9619 * HWRM shall return unavail (i.e. value of 0) for this field
9620 * when this command is used to query VF's configuration or
9621 * from older firmware that doesn't support this field.
9623 uint8_t port_pf_cnt;
9624 /* number of PFs is not available */
9625 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
9626 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
9627 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
9629 * The default VNIC ID assigned to a function that is
9632 uint16_t dflt_vnic_id;
9633 uint16_t max_mtu_configured;
9635 * Minimum BW allocated for this function.
9636 * The HWRM will translate this value into byte counter and
9637 * time interval used for the scheduler inside the device.
9638 * A value of 0 indicates the minimum bandwidth is not
9642 /* The bandwidth value. */
9643 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
9645 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
9646 /* The granularity of the value (bits or bytes). */
9647 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
9648 UINT32_C(0x10000000)
9649 /* Value is in bits. */
9650 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
9651 (UINT32_C(0x0) << 28)
9652 /* Value is in bytes. */
9653 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
9654 (UINT32_C(0x1) << 28)
9655 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
9656 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
9657 /* bw_value_unit is 3 b */
9658 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
9659 UINT32_C(0xe0000000)
9660 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
9661 /* Value is in Mb or MB (base 10). */
9662 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
9663 (UINT32_C(0x0) << 29)
9664 /* Value is in Kb or KB (base 10). */
9665 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
9666 (UINT32_C(0x2) << 29)
9667 /* Value is in bits or bytes. */
9668 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
9669 (UINT32_C(0x4) << 29)
9670 /* Value is in Gb or GB (base 10). */
9671 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
9672 (UINT32_C(0x6) << 29)
9673 /* Value is in 1/100th of a percentage of total bandwidth. */
9674 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
9675 (UINT32_C(0x1) << 29)
9677 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
9678 (UINT32_C(0x7) << 29)
9679 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
9680 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
9682 * Maximum BW allocated for this function.
9683 * The HWRM will translate this value into byte counter and
9684 * time interval used for the scheduler inside the device.
9685 * A value of 0 indicates that the maximum bandwidth is not
9689 /* The bandwidth value. */
9690 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
9692 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
9693 /* The granularity of the value (bits or bytes). */
9694 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
9695 UINT32_C(0x10000000)
9696 /* Value is in bits. */
9697 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
9698 (UINT32_C(0x0) << 28)
9699 /* Value is in bytes. */
9700 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
9701 (UINT32_C(0x1) << 28)
9702 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
9703 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
9704 /* bw_value_unit is 3 b */
9705 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
9706 UINT32_C(0xe0000000)
9707 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
9708 /* Value is in Mb or MB (base 10). */
9709 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
9710 (UINT32_C(0x0) << 29)
9711 /* Value is in Kb or KB (base 10). */
9712 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
9713 (UINT32_C(0x2) << 29)
9714 /* Value is in bits or bytes. */
9715 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
9716 (UINT32_C(0x4) << 29)
9717 /* Value is in Gb or GB (base 10). */
9718 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
9719 (UINT32_C(0x6) << 29)
9720 /* Value is in 1/100th of a percentage of total bandwidth. */
9721 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
9722 (UINT32_C(0x1) << 29)
9724 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
9725 (UINT32_C(0x7) << 29)
9726 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
9727 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
9729 * This value indicates the Edge virtual bridge mode for the
9730 * domain that this function belongs to.
9733 /* No Edge Virtual Bridging (EVB) */
9734 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
9735 /* Virtual Ethernet Bridge (VEB) */
9736 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
9737 /* Virtual Ethernet Port Aggregator (VEPA) */
9738 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
9739 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
9740 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
9743 * This value indicates the PCIE device cache line size.
9744 * The cache line size allows the DMA writes to terminate and
9745 * start at the cache boundary.
9747 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
9749 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
9750 /* Cache Line Size 64 bytes */
9751 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
9753 /* Cache Line Size 128 bytes */
9754 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
9756 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
9757 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
9758 /* This value is the virtual link admin state setting. */
9759 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
9761 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
9762 /* Admin link state is in forced down mode. */
9763 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
9764 (UINT32_C(0x0) << 2)
9765 /* Admin link state is in forced up mode. */
9766 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
9767 (UINT32_C(0x1) << 2)
9768 /* Admin link state is in auto mode - follows the physical link state. */
9769 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
9770 (UINT32_C(0x2) << 2)
9771 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
9772 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
9773 /* Reserved for future. */
9774 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
9776 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
9778 * The number of VFs that are allocated to the function.
9779 * This is valid only on the PF with SR-IOV enabled.
9780 * 0xFF... (All Fs) if this command is called on a PF with
9781 * SR-IOV disabled or on a VF.
9785 * The number of allocated multicast filters for this
9786 * function on the RX side.
9788 uint32_t alloc_mcast_filters;
9790 * The number of allocated HW ring groups for this
9793 uint32_t alloc_hw_ring_grps;
9795 * The number of strict priority transmit rings out of
9796 * currently allocated TX rings to the function
9799 uint16_t alloc_sp_tx_rings;
9801 * The number of statistics contexts
9802 * currently reserved for the function.
9804 uint16_t alloc_stat_ctx;
9806 * This field specifies how many NQs are reserved for the PF.
9807 * Remaining NQs that belong to the PF are available for VFs.
9808 * Once a PF has created VFs, it cannot change how many NQs are
9809 * reserved for itself (since the NQs must be contiguous in HW).
9811 uint16_t alloc_msix;
9813 * The number of registered VF’s associated with the PF. This field
9814 * should be ignored when the request received on the VF interface.
9815 * This field will be updated on the PF interface to initiate
9816 * the unregister request on PF in the HOT Reset Process.
9818 uint16_t registered_vfs;
9820 * The size of the doorbell BAR in KBytes reserved for L2 including
9821 * any area that is shared between L2 and RoCE. The L2 driver
9822 * should only map the L2 portion of the doorbell BAR. Any rounding
9823 * of the BAR size to the native CPU page size should be performed
9824 * by the driver. If the value is zero, no special partitioning
9825 * of the doorbell BAR between L2 and RoCE is required.
9827 uint16_t l2_doorbell_bar_size_kb;
9830 * For backward compatibility this field must be set to 1.
9831 * Older drivers might look for this field to be 1 before
9832 * processing the message.
9836 * This GRC address location is used by the Host driver interfaces to poll
9837 * the adapter ready state to re-initiate the registration process again
9838 * after receiving the RESET Notify event.
9840 uint32_t reset_addr_poll;
9842 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
9843 * this value to find out the doorbell page offset from the BAR.
9845 uint16_t legacy_l2_db_size_kb;
9848 * This field specifies the source virtual interface of the function being
9849 * queried. Drivers can use this to program svif field in the L2 context
9852 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
9853 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
9854 /* This field specifies whether svif is valid or not */
9855 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
9856 uint8_t unused_2[7];
9858 * This field is used in Output records to indicate that the output
9859 * is completely written to RAM. This field should be read as '1'
9860 * to indicate that the output has been completely written.
9861 * When writing a command completion or response to an internal processor,
9862 * the order of writes has to be such that this field is written last.
9872 /* hwrm_func_cfg_input (size:704b/88B) */
9873 struct hwrm_func_cfg_input {
9874 /* The HWRM command request type. */
9877 * The completion ring to send the completion event on. This should
9878 * be the NQ ID returned from the `nq_alloc` HWRM command.
9882 * The sequence ID is used by the driver for tracking multiple
9883 * commands. This ID is treated as opaque data by the firmware and
9884 * the value is returned in the `hwrm_resp_hdr` upon completion.
9888 * The target ID of the command:
9889 * * 0x0-0xFFF8 - The function ID
9890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9891 * * 0xFFFD - Reserved for user-space HWRM interface
9896 * A physical address pointer pointing to a host buffer that the
9897 * command's response data will be written. This can be either a host
9898 * physical address (HPA) or a guest physical address (GPA) and must
9899 * point to a physically contiguous block of memory.
9903 * Function ID of the function that is being
9905 * If set to 0xFF... (All Fs), then the the configuration is
9906 * for the requesting function.
9910 * This field specifies how many NQs will be reserved for the PF.
9911 * Remaining NQs that belong to the PF become available for VFs.
9912 * Once a PF has created VFs, it cannot change how many NQs are
9913 * reserved for itself (since the NQs must be contiguous in HW).
9918 * When this bit is '1', the function is disabled with
9919 * source MAC address check.
9920 * This is an anti-spoofing check. If this flag is set,
9921 * then the function shall be configured to disallow
9922 * transmission of frames with the source MAC address that
9923 * is configured for this function.
9925 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
9928 * When this bit is '1', the function is enabled with
9929 * source MAC address check.
9930 * This is an anti-spoofing check. If this flag is set,
9931 * then the function shall be configured to allow
9932 * transmission of frames with the source MAC address that
9933 * is configured for this function.
9935 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
9938 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
9940 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
9942 * Standard TX Ring mode is used for the allocation of TX ring
9943 * and underlying scheduling resources that allow bandwidth
9944 * reservation and limit settings on the queried function.
9945 * If set to 1, then standard TX ring mode is requested to be
9946 * enabled on the function being configured.
9948 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
9951 * Standard TX Ring mode is used for the allocation of TX ring
9952 * and underlying scheduling resources that allow bandwidth
9953 * reservation and limit settings on the queried function.
9954 * If set to 1, then the standard TX ring mode is requested to
9955 * be disabled on the function being configured. In this extended
9956 * TX ring resource mode, the minimum and maximum bandwidth settings
9957 * are not supported to allow the allocation of TX rings to
9958 * span multiple scheduler nodes.
9960 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
9963 * If this bit is set, virtual mac address configured
9964 * in this command will be persistent over warm boot.
9966 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
9969 * This bit only applies to the VF. If this bit is set, the statistic
9970 * context counters will not be cleared when the statistic context is freed
9971 * or a function reset is called on VF. This bit will be cleared when the PF
9972 * is unloaded or a function reset is called on the PF.
9974 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
9977 * This bit requests that the firmware test to see if all the assets
9978 * requested in this command (i.e. number of TX rings) are available.
9979 * The firmware will return an error if the requested assets are
9980 * not available. The firwmare will NOT reserve the assets if they
9983 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
9986 * This bit requests that the firmware test to see if all the assets
9987 * requested in this command (i.e. number of RX rings) are available.
9988 * The firmware will return an error if the requested assets are
9989 * not available. The firwmare will NOT reserve the assets if they
9992 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
9995 * This bit requests that the firmware test to see if all the assets
9996 * requested in this command (i.e. number of CMPL rings) are available.
9997 * The firmware will return an error if the requested assets are
9998 * not available. The firwmare will NOT reserve the assets if they
10001 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10004 * This bit requests that the firmware test to see if all the assets
10005 * requested in this command (i.e. number of RSS ctx) are available.
10006 * The firmware will return an error if the requested assets are
10007 * not available. The firwmare will NOT reserve the assets if they
10010 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10013 * This bit requests that the firmware test to see if all the assets
10014 * requested in this command (i.e. number of ring groups) are available.
10015 * The firmware will return an error if the requested assets are
10016 * not available. The firwmare will NOT reserve the assets if they
10019 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10022 * This bit requests that the firmware test to see if all the assets
10023 * requested in this command (i.e. number of stat ctx) are available.
10024 * The firmware will return an error if the requested assets are
10025 * not available. The firwmare will NOT reserve the assets if they
10028 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10031 * This bit requests that the firmware test to see if all the assets
10032 * requested in this command (i.e. number of VNICs) are available.
10033 * The firmware will return an error if the requested assets are
10034 * not available. The firwmare will NOT reserve the assets if they
10037 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10040 * This bit requests that the firmware test to see if all the assets
10041 * requested in this command (i.e. number of L2 ctx) are available.
10042 * The firmware will return an error if the requested assets are
10043 * not available. The firwmare will NOT reserve the assets if they
10046 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10049 * This configuration change can be initiated by a PF driver. This
10050 * configuration request shall be targeted to a VF. From local host
10051 * resident HWRM clients, only the parent PF driver shall be allowed
10052 * to initiate this change on one of its children VFs. If this bit is
10053 * set to 1, then the VF that is being configured is requested to be
10056 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
10059 * When this bit it set, even if PF reserved pool size is zero,
10060 * FW will allow driver to create TX rings in ring alloc,
10061 * by reserving TX ring, S3 node dynamically.
10063 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
10066 * This bit requests that the firmware test to see if all the assets
10067 * requested in this command (i.e. number of NQ rings) are available.
10068 * The firmware will return an error if the requested assets are
10069 * not available. The firwmare will NOT reserve the assets if they
10072 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
10075 * This configuration change can be initiated by a PF driver. This
10076 * configuration request shall be targeted to a VF. From local host
10077 * resident HWRM clients, only the parent PF driver shall be allowed
10078 * to initiate this change on one of its children VFs. If this bit is
10079 * set to 1, then the VF that is being configured is requested to be
10082 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
10083 UINT32_C(0x1000000)
10085 * This bit is used by preboot drivers on a PF that require access
10086 * to the legacy L2 ring model and legacy 32b doorbells. This
10087 * feature is not allowed on VFs and is only relevant for devices
10088 * that require a context backing store.
10090 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
10091 UINT32_C(0x2000000)
10093 * If this bit is set to 0, then the interface does not support hot
10094 * reset capability which it advertised with the hot_reset_support
10095 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
10096 * flag to 0, adapter cannot do the hot reset. In this state, if the
10097 * firmware receives a hot reset request, firmware must fail the
10098 * request. If this bit is set to 1, then interface is renabling the
10099 * hot reset capability.
10101 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
10102 UINT32_C(0x4000000)
10105 * This bit must be '1' for the mtu field to be
10108 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
10111 * This bit must be '1' for the mru field to be
10114 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
10117 * This bit must be '1' for the num_rsscos_ctxs field to be
10120 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10123 * This bit must be '1' for the num_cmpl_rings field to be
10126 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10129 * This bit must be '1' for the num_tx_rings field to be
10132 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10135 * This bit must be '1' for the num_rx_rings field to be
10138 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10141 * This bit must be '1' for the num_l2_ctxs field to be
10144 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10147 * This bit must be '1' for the num_vnics field to be
10150 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
10153 * This bit must be '1' for the num_stat_ctxs field to be
10156 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10159 * This bit must be '1' for the dflt_mac_addr field to be
10162 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10165 * This bit must be '1' for the dflt_vlan field to be
10168 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
10171 * This bit must be '1' for the dflt_ip_addr field to be
10174 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
10177 * This bit must be '1' for the min_bw field to be
10180 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
10183 * This bit must be '1' for the max_bw field to be
10186 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
10189 * This bit must be '1' for the async_event_cr field to be
10192 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10195 * This bit must be '1' for the vlan_antispoof_mode field to be
10198 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
10201 * This bit must be '1' for the allowed_vlan_pris field to be
10204 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
10207 * This bit must be '1' for the evb_mode field to be
10210 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
10213 * This bit must be '1' for the num_mcast_filters field to be
10216 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
10219 * This bit must be '1' for the num_hw_ring_grps field to be
10222 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10225 * This bit must be '1' for the cache_linesize field to be
10228 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
10231 * This bit must be '1' for the num_msix field to be
10234 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
10237 * This bit must be '1' for the link admin state field to be
10240 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
10243 * This bit must be '1' for the hot_reset_if_en_dis field to be
10246 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
10249 * The maximum transmission unit of the function.
10250 * The HWRM should make sure that the mtu of
10251 * the function does not exceed the mtu of the physical
10252 * port that this function is associated with.
10254 * In addition to configuring mtu per function, it is
10255 * possible to configure mtu per transmit ring.
10256 * By default, the mtu of each transmit ring associated
10257 * with a function is equal to the mtu of the function.
10258 * The HWRM should make sure that the mtu of each transmit
10259 * ring that is assigned to a function has a valid mtu.
10263 * The maximum receive unit of the function.
10264 * The HWRM should make sure that the mru of
10265 * the function does not exceed the mru of the physical
10266 * port that this function is associated with.
10268 * In addition to configuring mru per function, it is
10269 * possible to configure mru per vnic.
10270 * By default, the mru of each vnic associated
10271 * with a function is equal to the mru of the function.
10272 * The HWRM should make sure that the mru of each vnic
10273 * that is assigned to a function has a valid mru.
10277 * The number of RSS/COS contexts requested for the
10280 uint16_t num_rsscos_ctxs;
10282 * The number of completion rings requested for the
10283 * function. This does not include the rings allocated
10284 * to any children functions if any.
10286 uint16_t num_cmpl_rings;
10288 * The number of transmit rings requested for the function.
10289 * This does not include the rings allocated to any
10290 * children functions if any.
10292 uint16_t num_tx_rings;
10294 * The number of receive rings requested for the function.
10295 * This does not include the rings allocated
10296 * to any children functions if any.
10298 uint16_t num_rx_rings;
10299 /* The requested number of L2 contexts for the function. */
10300 uint16_t num_l2_ctxs;
10301 /* The requested number of vnics for the function. */
10302 uint16_t num_vnics;
10303 /* The requested number of statistic contexts for the function. */
10304 uint16_t num_stat_ctxs;
10306 * The number of HW ring groups that should
10307 * be reserved for this function.
10309 uint16_t num_hw_ring_grps;
10310 /* The default MAC address for the function being configured. */
10311 uint8_t dflt_mac_addr[6];
10313 * The default VLAN for the function being configured.
10314 * This field's format is same as 802.1Q Tag's
10315 * Tag Control Information (TCI) format that includes both
10316 * Priority Code Point (PCP) and VLAN Identifier (VID).
10318 uint16_t dflt_vlan;
10320 * The default IP address for the function being configured.
10321 * This address is only used in enabling source property check.
10323 uint32_t dflt_ip_addr[4];
10325 * Minimum BW allocated for this function.
10326 * The HWRM will translate this value into byte counter and
10327 * time interval used for the scheduler inside the device.
10330 /* The bandwidth value. */
10331 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
10332 UINT32_C(0xfffffff)
10333 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
10334 /* The granularity of the value (bits or bytes). */
10335 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
10336 UINT32_C(0x10000000)
10337 /* Value is in bits. */
10338 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
10339 (UINT32_C(0x0) << 28)
10340 /* Value is in bytes. */
10341 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
10342 (UINT32_C(0x1) << 28)
10343 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
10344 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
10345 /* bw_value_unit is 3 b */
10346 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
10347 UINT32_C(0xe0000000)
10348 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
10349 /* Value is in Mb or MB (base 10). */
10350 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
10351 (UINT32_C(0x0) << 29)
10352 /* Value is in Kb or KB (base 10). */
10353 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
10354 (UINT32_C(0x2) << 29)
10355 /* Value is in bits or bytes. */
10356 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
10357 (UINT32_C(0x4) << 29)
10358 /* Value is in Gb or GB (base 10). */
10359 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
10360 (UINT32_C(0x6) << 29)
10361 /* Value is in 1/100th of a percentage of total bandwidth. */
10362 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
10363 (UINT32_C(0x1) << 29)
10365 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
10366 (UINT32_C(0x7) << 29)
10367 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
10368 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
10370 * Maximum BW allocated for this function.
10371 * The HWRM will translate this value into byte counter and
10372 * time interval used for the scheduler inside the device.
10375 /* The bandwidth value. */
10376 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
10377 UINT32_C(0xfffffff)
10378 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
10379 /* The granularity of the value (bits or bytes). */
10380 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
10381 UINT32_C(0x10000000)
10382 /* Value is in bits. */
10383 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
10384 (UINT32_C(0x0) << 28)
10385 /* Value is in bytes. */
10386 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
10387 (UINT32_C(0x1) << 28)
10388 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
10389 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
10390 /* bw_value_unit is 3 b */
10391 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
10392 UINT32_C(0xe0000000)
10393 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
10394 /* Value is in Mb or MB (base 10). */
10395 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
10396 (UINT32_C(0x0) << 29)
10397 /* Value is in Kb or KB (base 10). */
10398 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
10399 (UINT32_C(0x2) << 29)
10400 /* Value is in bits or bytes. */
10401 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
10402 (UINT32_C(0x4) << 29)
10403 /* Value is in Gb or GB (base 10). */
10404 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
10405 (UINT32_C(0x6) << 29)
10406 /* Value is in 1/100th of a percentage of total bandwidth. */
10407 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
10408 (UINT32_C(0x1) << 29)
10410 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
10411 (UINT32_C(0x7) << 29)
10412 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
10413 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
10415 * ID of the target completion ring for receiving asynchronous
10416 * event completions. If this field is not valid, then the
10417 * HWRM shall use the default completion ring of the function
10418 * that is being configured as the target completion ring for
10419 * providing any asynchronous event completions for that
10421 * If this field is valid, then the HWRM shall use the
10422 * completion ring identified by this ID as the target
10423 * completion ring for providing any asynchronous event
10424 * completions for the function that is being configured.
10426 uint16_t async_event_cr;
10427 /* VLAN Anti-spoofing mode. */
10428 uint8_t vlan_antispoof_mode;
10429 /* No VLAN anti-spoofing checks are enabled */
10430 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
10432 /* Validate VLAN against the configured VLAN(s) */
10433 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
10435 /* Insert VLAN if it does not exist, otherwise discard */
10436 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
10438 /* Insert VLAN if it does not exist, override VLAN if it exists */
10439 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
10441 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
10442 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
10444 * This bit field defines VLAN PRIs that are allowed on
10446 * If nth bit is set, then VLAN PRI n is allowed on this
10449 uint8_t allowed_vlan_pris;
10451 * The HWRM shall allow a PF driver to change EVB mode for the
10452 * partition it belongs to.
10453 * The HWRM shall not allow a VF driver to change the EVB mode.
10454 * The HWRM shall take into account the switching of EVB mode
10455 * from one to another and reconfigure hardware resources as
10457 * The switching from VEB to VEPA mode requires
10458 * the disabling of the loopback traffic. Additionally,
10459 * source knock outs are handled differently in VEB and VEPA
10463 /* No Edge Virtual Bridging (EVB) */
10464 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
10465 /* Virtual Ethernet Bridge (VEB) */
10466 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
10467 /* Virtual Ethernet Port Aggregator (VEPA) */
10468 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
10469 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
10470 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
10473 * This value indicates the PCIE device cache line size.
10474 * The cache line size allows the DMA writes to terminate and
10475 * start at the cache boundary.
10477 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
10479 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
10480 /* Cache Line Size 64 bytes */
10481 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
10483 /* Cache Line Size 128 bytes */
10484 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
10486 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
10487 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
10488 /* This value is the virtual link admin state setting. */
10489 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
10491 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
10492 /* Admin state is forced down. */
10493 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
10494 (UINT32_C(0x0) << 2)
10495 /* Admin state is forced up. */
10496 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
10497 (UINT32_C(0x1) << 2)
10498 /* Admin state is in auto mode - is to follow the physical link state. */
10499 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
10500 (UINT32_C(0x2) << 2)
10501 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
10502 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
10503 /* Reserved for future. */
10504 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
10506 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
10508 * The number of multicast filters that should
10509 * be reserved for this function on the RX side.
10511 uint16_t num_mcast_filters;
10514 /* hwrm_func_cfg_output (size:128b/16B) */
10515 struct hwrm_func_cfg_output {
10516 /* The specific error status for the command. */
10517 uint16_t error_code;
10518 /* The HWRM command request type. */
10520 /* The sequence ID from the original command. */
10522 /* The length of the response data in number of bytes. */
10524 uint8_t unused_0[7];
10526 * This field is used in Output records to indicate that the output
10527 * is completely written to RAM. This field should be read as '1'
10528 * to indicate that the output has been completely written.
10529 * When writing a command completion or response to an internal processor,
10530 * the order of writes has to be such that this field is written last.
10535 /********************
10536 * hwrm_func_qstats *
10537 ********************/
10540 /* hwrm_func_qstats_input (size:192b/24B) */
10541 struct hwrm_func_qstats_input {
10542 /* The HWRM command request type. */
10545 * The completion ring to send the completion event on. This should
10546 * be the NQ ID returned from the `nq_alloc` HWRM command.
10548 uint16_t cmpl_ring;
10550 * The sequence ID is used by the driver for tracking multiple
10551 * commands. This ID is treated as opaque data by the firmware and
10552 * the value is returned in the `hwrm_resp_hdr` upon completion.
10556 * The target ID of the command:
10557 * * 0x0-0xFFF8 - The function ID
10558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10559 * * 0xFFFD - Reserved for user-space HWRM interface
10562 uint16_t target_id;
10564 * A physical address pointer pointing to a host buffer that the
10565 * command's response data will be written. This can be either a host
10566 * physical address (HPA) or a guest physical address (GPA) and must
10567 * point to a physically contiguous block of memory.
10569 uint64_t resp_addr;
10571 * Function ID of the function that is being queried.
10572 * 0xFF... (All Fs) if the query is for the requesting
10574 * A privileged PF can query for other function's statistics.
10577 /* This flags indicates the type of statistics request. */
10579 /* This value is not used to avoid backward compatibility issues. */
10580 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10582 * flags should be set to 1 when request is for only RoCE statistics.
10583 * This will be honored only if the caller_fid is a privileged PF.
10584 * In all other cases FID and caller_fid should be the same.
10586 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10588 * flags should be set to 2 when request is for the counter mask,
10589 * representing the width of each of the stats counters, rather
10590 * than counters themselves.
10592 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10593 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
10594 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
10595 uint8_t unused_0[5];
10598 /* hwrm_func_qstats_output (size:1408b/176B) */
10599 struct hwrm_func_qstats_output {
10600 /* The specific error status for the command. */
10601 uint16_t error_code;
10602 /* The HWRM command request type. */
10604 /* The sequence ID from the original command. */
10606 /* The length of the response data in number of bytes. */
10608 /* Number of transmitted unicast packets on the function. */
10609 uint64_t tx_ucast_pkts;
10610 /* Number of transmitted multicast packets on the function. */
10611 uint64_t tx_mcast_pkts;
10612 /* Number of transmitted broadcast packets on the function. */
10613 uint64_t tx_bcast_pkts;
10615 * Number of transmitted packets that were discarded due to
10616 * internal NIC resource problems. For transmit, this
10617 * can only happen if TMP is configured to allow dropping
10618 * in HOL blocking conditions, which is not a normal
10621 uint64_t tx_discard_pkts;
10623 * Number of dropped packets on transmit path on the function.
10624 * These are packets that have been marked for drop by
10625 * the TE CFA block or are packets that exceeded the
10626 * transmit MTU limit for the function.
10628 uint64_t tx_drop_pkts;
10629 /* Number of transmitted bytes for unicast traffic on the function. */
10630 uint64_t tx_ucast_bytes;
10631 /* Number of transmitted bytes for multicast traffic on the function. */
10632 uint64_t tx_mcast_bytes;
10633 /* Number of transmitted bytes for broadcast traffic on the function. */
10634 uint64_t tx_bcast_bytes;
10635 /* Number of received unicast packets on the function. */
10636 uint64_t rx_ucast_pkts;
10637 /* Number of received multicast packets on the function. */
10638 uint64_t rx_mcast_pkts;
10639 /* Number of received broadcast packets on the function. */
10640 uint64_t rx_bcast_pkts;
10642 * Number of received packets that were discarded on the function
10643 * due to resource limitations. This can happen for 3 reasons.
10644 * # The BD used for the packet has a bad format.
10645 * # There were no BDs available in the ring for the packet.
10646 * # There were no BDs available on-chip for the packet.
10648 uint64_t rx_discard_pkts;
10650 * Number of dropped packets on received path on the function.
10651 * These are packets that have been marked for drop by the
10654 uint64_t rx_drop_pkts;
10655 /* Number of received bytes for unicast traffic on the function. */
10656 uint64_t rx_ucast_bytes;
10657 /* Number of received bytes for multicast traffic on the function. */
10658 uint64_t rx_mcast_bytes;
10659 /* Number of received bytes for broadcast traffic on the function. */
10660 uint64_t rx_bcast_bytes;
10661 /* Number of aggregated unicast packets on the function. */
10662 uint64_t rx_agg_pkts;
10663 /* Number of aggregated unicast bytes on the function. */
10664 uint64_t rx_agg_bytes;
10665 /* Number of aggregation events on the function. */
10666 uint64_t rx_agg_events;
10667 /* Number of aborted aggregations on the function. */
10668 uint64_t rx_agg_aborts;
10669 uint8_t unused_0[7];
10671 * This field is used in Output records to indicate that the output
10672 * is completely written to RAM. This field should be read as '1'
10673 * to indicate that the output has been completely written.
10674 * When writing a command completion or response to an internal processor,
10675 * the order of writes has to be such that this field is written last.
10680 /************************
10681 * hwrm_func_qstats_ext *
10682 ************************/
10685 /* hwrm_func_qstats_ext_input (size:192b/24B) */
10686 struct hwrm_func_qstats_ext_input {
10687 /* The HWRM command request type. */
10690 * The completion ring to send the completion event on. This should
10691 * be the NQ ID returned from the `nq_alloc` HWRM command.
10693 uint16_t cmpl_ring;
10695 * The sequence ID is used by the driver for tracking multiple
10696 * commands. This ID is treated as opaque data by the firmware and
10697 * the value is returned in the `hwrm_resp_hdr` upon completion.
10701 * The target ID of the command:
10702 * * 0x0-0xFFF8 - The function ID
10703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10704 * * 0xFFFD - Reserved for user-space HWRM interface
10707 uint16_t target_id;
10709 * A physical address pointer pointing to a host buffer that the
10710 * command's response data will be written. This can be either a host
10711 * physical address (HPA) or a guest physical address (GPA) and must
10712 * point to a physically contiguous block of memory.
10714 uint64_t resp_addr;
10716 * Function ID of the function that is being queried.
10717 * 0xFF... (All Fs) if the query is for the requesting
10719 * A privileged PF can query for other function's statistics.
10722 /* This flags indicates the type of statistics request. */
10724 /* This value is not used to avoid backward compatibility issues. */
10725 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10727 * flags should be set to 1 when request is for only RoCE statistics.
10728 * This will be honored only if the caller_fid is a privileged PF.
10729 * In all other cases FID and caller_fid should be the same.
10731 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10733 * flags should be set to 2 when request is for the counter mask
10734 * representing the width of each of the stats counters, rather
10735 * than counters themselves.
10737 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10738 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
10739 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
10740 uint8_t unused_0[5];
10743 /* hwrm_func_qstats_ext_output (size:1472b/184B) */
10744 struct hwrm_func_qstats_ext_output {
10745 /* The specific error status for the command. */
10746 uint16_t error_code;
10747 /* The HWRM command request type. */
10749 /* The sequence ID from the original command. */
10751 /* The length of the response data in number of bytes. */
10753 /* Number of received unicast packets */
10754 uint64_t rx_ucast_pkts;
10755 /* Number of received multicast packets */
10756 uint64_t rx_mcast_pkts;
10757 /* Number of received broadcast packets */
10758 uint64_t rx_bcast_pkts;
10759 /* Number of discarded packets on received path */
10760 uint64_t rx_discard_pkts;
10761 /* Number of packets on receive path with error */
10762 uint64_t rx_error_pkts;
10763 /* Number of received bytes for unicast traffic */
10764 uint64_t rx_ucast_bytes;
10765 /* Number of received bytes for multicast traffic */
10766 uint64_t rx_mcast_bytes;
10767 /* Number of received bytes for broadcast traffic */
10768 uint64_t rx_bcast_bytes;
10769 /* Number of transmitted unicast packets */
10770 uint64_t tx_ucast_pkts;
10771 /* Number of transmitted multicast packets */
10772 uint64_t tx_mcast_pkts;
10773 /* Number of transmitted broadcast packets */
10774 uint64_t tx_bcast_pkts;
10775 /* Number of packets on transmit path with error */
10776 uint64_t tx_error_pkts;
10777 /* Number of discarded packets on transmit path */
10778 uint64_t tx_discard_pkts;
10779 /* Number of transmitted bytes for unicast traffic */
10780 uint64_t tx_ucast_bytes;
10781 /* Number of transmitted bytes for multicast traffic */
10782 uint64_t tx_mcast_bytes;
10783 /* Number of transmitted bytes for broadcast traffic */
10784 uint64_t tx_bcast_bytes;
10785 /* Number of TPA eligible packets */
10786 uint64_t rx_tpa_eligible_pkt;
10787 /* Number of TPA eligible bytes */
10788 uint64_t rx_tpa_eligible_bytes;
10789 /* Number of TPA packets */
10790 uint64_t rx_tpa_pkt;
10791 /* Number of TPA bytes */
10792 uint64_t rx_tpa_bytes;
10793 /* Number of TPA errors */
10794 uint64_t rx_tpa_errors;
10795 uint8_t unused_0[7];
10797 * This field is used in Output records to indicate that the output
10798 * is completely written to RAM. This field should be read as '1'
10799 * to indicate that the output has been completely written.
10800 * When writing a command completion or response to an internal processor,
10801 * the order of writes has to be such that this field is written last.
10806 /***********************
10807 * hwrm_func_clr_stats *
10808 ***********************/
10811 /* hwrm_func_clr_stats_input (size:192b/24B) */
10812 struct hwrm_func_clr_stats_input {
10813 /* The HWRM command request type. */
10816 * The completion ring to send the completion event on. This should
10817 * be the NQ ID returned from the `nq_alloc` HWRM command.
10819 uint16_t cmpl_ring;
10821 * The sequence ID is used by the driver for tracking multiple
10822 * commands. This ID is treated as opaque data by the firmware and
10823 * the value is returned in the `hwrm_resp_hdr` upon completion.
10827 * The target ID of the command:
10828 * * 0x0-0xFFF8 - The function ID
10829 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10830 * * 0xFFFD - Reserved for user-space HWRM interface
10833 uint16_t target_id;
10835 * A physical address pointer pointing to a host buffer that the
10836 * command's response data will be written. This can be either a host
10837 * physical address (HPA) or a guest physical address (GPA) and must
10838 * point to a physically contiguous block of memory.
10840 uint64_t resp_addr;
10842 * Function ID of the function.
10843 * 0xFF... (All Fs) if the query is for the requesting
10847 uint8_t unused_0[6];
10850 /* hwrm_func_clr_stats_output (size:128b/16B) */
10851 struct hwrm_func_clr_stats_output {
10852 /* The specific error status for the command. */
10853 uint16_t error_code;
10854 /* The HWRM command request type. */
10856 /* The sequence ID from the original command. */
10858 /* The length of the response data in number of bytes. */
10860 uint8_t unused_0[7];
10862 * This field is used in Output records to indicate that the output
10863 * is completely written to RAM. This field should be read as '1'
10864 * to indicate that the output has been completely written.
10865 * When writing a command completion or response to an internal processor,
10866 * the order of writes has to be such that this field is written last.
10871 /**************************
10872 * hwrm_func_vf_resc_free *
10873 **************************/
10876 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
10877 struct hwrm_func_vf_resc_free_input {
10878 /* The HWRM command request type. */
10881 * The completion ring to send the completion event on. This should
10882 * be the NQ ID returned from the `nq_alloc` HWRM command.
10884 uint16_t cmpl_ring;
10886 * The sequence ID is used by the driver for tracking multiple
10887 * commands. This ID is treated as opaque data by the firmware and
10888 * the value is returned in the `hwrm_resp_hdr` upon completion.
10892 * The target ID of the command:
10893 * * 0x0-0xFFF8 - The function ID
10894 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10895 * * 0xFFFD - Reserved for user-space HWRM interface
10898 uint16_t target_id;
10900 * A physical address pointer pointing to a host buffer that the
10901 * command's response data will be written. This can be either a host
10902 * physical address (HPA) or a guest physical address (GPA) and must
10903 * point to a physically contiguous block of memory.
10905 uint64_t resp_addr;
10907 * This value is used to identify a Virtual Function (VF).
10908 * The scope of VF ID is local within a PF.
10911 uint8_t unused_0[6];
10914 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
10915 struct hwrm_func_vf_resc_free_output {
10916 /* The specific error status for the command. */
10917 uint16_t error_code;
10918 /* The HWRM command request type. */
10920 /* The sequence ID from the original command. */
10922 /* The length of the response data in number of bytes. */
10924 uint8_t unused_0[7];
10926 * This field is used in Output records to indicate that the output
10927 * is completely written to RAM. This field should be read as '1'
10928 * to indicate that the output has been completely written.
10929 * When writing a command completion or response to an internal processor,
10930 * the order of writes has to be such that this field is written last.
10935 /**********************
10936 * hwrm_func_drv_rgtr *
10937 **********************/
10940 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
10941 struct hwrm_func_drv_rgtr_input {
10942 /* The HWRM command request type. */
10945 * The completion ring to send the completion event on. This should
10946 * be the NQ ID returned from the `nq_alloc` HWRM command.
10948 uint16_t cmpl_ring;
10950 * The sequence ID is used by the driver for tracking multiple
10951 * commands. This ID is treated as opaque data by the firmware and
10952 * the value is returned in the `hwrm_resp_hdr` upon completion.
10956 * The target ID of the command:
10957 * * 0x0-0xFFF8 - The function ID
10958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10959 * * 0xFFFD - Reserved for user-space HWRM interface
10962 uint16_t target_id;
10964 * A physical address pointer pointing to a host buffer that the
10965 * command's response data will be written. This can be either a host
10966 * physical address (HPA) or a guest physical address (GPA) and must
10967 * point to a physically contiguous block of memory.
10969 uint64_t resp_addr;
10972 * When this bit is '1', the function driver is requesting
10973 * all requests from its children VF drivers to be
10974 * forwarded to itself.
10975 * This flag can only be set by the PF driver.
10976 * If a VF driver sets this flag, it should be ignored
10979 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
10982 * When this bit is '1', the function is requesting none of
10983 * the requests from its children VF drivers to be
10984 * forwarded to itself.
10985 * This flag can only be set by the PF driver.
10986 * If a VF driver sets this flag, it should be ignored
10989 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
10992 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
10993 * fields shall be ignored and ver_maj, ver_min, ver_upd
10994 * and ver_patch shall be used for the driver version information.
10995 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
10996 * fields shall be used for the driver version information and
10997 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
10999 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
11002 * When this bit is '1', the function is indicating support of
11003 * 64bit flow handle. The firmware that only supports 64bit flow
11004 * handle should check this bit before allowing processing of
11005 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
11006 * with 64bit flow handle support can only be compatible with drivers
11007 * that support 64bit flow handle. The legacy drivers that don't support
11008 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
11009 * running with new firmware that only supports 64bit flow handle. The new
11010 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
11011 * status to the legacy driver when encounters these commands.
11013 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
11016 * When this bit is '1', the function is indicating support of
11017 * Hot Reset. The driver interface will destroy the resources,
11018 * unregister the function and register again up on receiving
11019 * the RESET_NOTIFY Async notification from the core firmware.
11020 * The core firmware will this use flag and trigger the Hot Reset
11021 * process only if all the registered driver instances are capable
11024 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
11027 * When this bit is 1, the function is indicating the support of the
11028 * error recovery capability. Error recovery support will be used by
11029 * firmware only if all the driver instances support error recovery
11030 * process. By setting this bit, driver is indicating support for
11031 * corresponding async event completion message. These will be
11032 * delivered to the driver even if they did not register for it.
11033 * If supported, after receiving reset notify async event with fatal
11034 * flag set in event data1, then all the drivers have to tear down
11035 * their resources without sending any HWRM commands to FW.
11037 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
11040 * When this bit is 1, the function is indicating the support of the
11041 * Master capability. The Firmware will use this capability to select the
11042 * Master function. The master function will be used to initiate
11043 * designated functionality like error recovery etc… If none of the
11044 * registered PF’s or trusted VF’s indicate this support, then
11045 * firmware will select the 1st registered PF as Master capable instance.
11047 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
11051 * This bit must be '1' for the os_type field to be
11054 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
11057 * This bit must be '1' for the ver field to be
11060 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
11063 * This bit must be '1' for the timestamp field to be
11066 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
11069 * This bit must be '1' for the vf_req_fwd field to be
11072 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
11075 * This bit must be '1' for the async_event_fwd field to be
11078 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
11080 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11083 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11084 /* Other OS not listed below. */
11085 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
11087 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11089 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11091 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11093 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
11095 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11096 /* VMware ESXi OS. */
11097 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
11098 /* Microsoft Windows 8 64-bit OS. */
11099 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11100 /* Microsoft Windows Server 2012 R2 OS. */
11101 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11103 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11104 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
11105 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
11106 /* This is the 8bit major version of the driver. */
11107 uint8_t ver_maj_8b;
11108 /* This is the 8bit minor version of the driver. */
11109 uint8_t ver_min_8b;
11110 /* This is the 8bit update version of the driver. */
11111 uint8_t ver_upd_8b;
11112 uint8_t unused_0[3];
11114 * This is a 32-bit timestamp provided by the driver for
11116 * The timestamp is in multiples of 1ms.
11118 uint32_t timestamp;
11119 uint8_t unused_1[4];
11121 * This is a 256-bit bit mask provided by the PF driver for
11122 * letting the HWRM know what commands issued by the VF driver
11123 * to the HWRM should be forwarded to the PF driver.
11124 * Nth bit refers to the Nth req_type.
11126 * Setting Nth bit to 1 indicates that requests from the
11127 * VF driver with req_type equal to N shall be forwarded to
11128 * the parent PF driver.
11130 * This field is not valid for the VF driver.
11132 uint32_t vf_req_fwd[8];
11134 * This is a 256-bit bit mask provided by the function driver
11135 * (PF or VF driver) to indicate the list of asynchronous event
11136 * completions to be forwarded.
11138 * Nth bit refers to the Nth event_id.
11140 * Setting Nth bit to 1 by the function driver shall result in
11141 * the HWRM forwarding asynchronous event completion with
11142 * event_id equal to N.
11144 * If all bits are set to 0 (value of 0), then the HWRM shall
11145 * not forward any asynchronous event completion to this
11148 uint32_t async_event_fwd[8];
11149 /* This is the 16bit major version of the driver. */
11151 /* This is the 16bit minor version of the driver. */
11153 /* This is the 16bit update version of the driver. */
11155 /* This is the 16bit patch version of the driver. */
11156 uint16_t ver_patch;
11159 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
11160 struct hwrm_func_drv_rgtr_output {
11161 /* The specific error status for the command. */
11162 uint16_t error_code;
11163 /* The HWRM command request type. */
11165 /* The sequence ID from the original command. */
11167 /* The length of the response data in number of bytes. */
11171 * When this bit is '1', it indicates that the
11172 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
11174 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
11176 uint8_t unused_0[3];
11178 * This field is used in Output records to indicate that the output
11179 * is completely written to RAM. This field should be read as '1'
11180 * to indicate that the output has been completely written.
11181 * When writing a command completion or response to an internal processor,
11182 * the order of writes has to be such that this field is written last.
11187 /************************
11188 * hwrm_func_drv_unrgtr *
11189 ************************/
11192 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
11193 struct hwrm_func_drv_unrgtr_input {
11194 /* The HWRM command request type. */
11197 * The completion ring to send the completion event on. This should
11198 * be the NQ ID returned from the `nq_alloc` HWRM command.
11200 uint16_t cmpl_ring;
11202 * The sequence ID is used by the driver for tracking multiple
11203 * commands. This ID is treated as opaque data by the firmware and
11204 * the value is returned in the `hwrm_resp_hdr` upon completion.
11208 * The target ID of the command:
11209 * * 0x0-0xFFF8 - The function ID
11210 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11211 * * 0xFFFD - Reserved for user-space HWRM interface
11214 uint16_t target_id;
11216 * A physical address pointer pointing to a host buffer that the
11217 * command's response data will be written. This can be either a host
11218 * physical address (HPA) or a guest physical address (GPA) and must
11219 * point to a physically contiguous block of memory.
11221 uint64_t resp_addr;
11224 * When this bit is '1', the function driver is notifying
11225 * the HWRM to prepare for the shutdown.
11227 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
11229 uint8_t unused_0[4];
11232 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
11233 struct hwrm_func_drv_unrgtr_output {
11234 /* The specific error status for the command. */
11235 uint16_t error_code;
11236 /* The HWRM command request type. */
11238 /* The sequence ID from the original command. */
11240 /* The length of the response data in number of bytes. */
11242 uint8_t unused_0[7];
11244 * This field is used in Output records to indicate that the output
11245 * is completely written to RAM. This field should be read as '1'
11246 * to indicate that the output has been completely written.
11247 * When writing a command completion or response to an internal processor,
11248 * the order of writes has to be such that this field is written last.
11253 /**********************
11254 * hwrm_func_buf_rgtr *
11255 **********************/
11258 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
11259 struct hwrm_func_buf_rgtr_input {
11260 /* The HWRM command request type. */
11263 * The completion ring to send the completion event on. This should
11264 * be the NQ ID returned from the `nq_alloc` HWRM command.
11266 uint16_t cmpl_ring;
11268 * The sequence ID is used by the driver for tracking multiple
11269 * commands. This ID is treated as opaque data by the firmware and
11270 * the value is returned in the `hwrm_resp_hdr` upon completion.
11274 * The target ID of the command:
11275 * * 0x0-0xFFF8 - The function ID
11276 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11277 * * 0xFFFD - Reserved for user-space HWRM interface
11280 uint16_t target_id;
11282 * A physical address pointer pointing to a host buffer that the
11283 * command's response data will be written. This can be either a host
11284 * physical address (HPA) or a guest physical address (GPA) and must
11285 * point to a physically contiguous block of memory.
11287 uint64_t resp_addr;
11290 * This bit must be '1' for the vf_id field to be
11293 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11295 * This bit must be '1' for the err_buf_addr field to be
11298 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
11300 * This value is used to identify a Virtual Function (VF).
11301 * The scope of VF ID is local within a PF.
11305 * This field represents the number of pages used for request
11308 uint16_t req_buf_num_pages;
11310 * This field represents the page size used for request
11313 uint16_t req_buf_page_size;
11315 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
11317 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
11319 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
11321 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
11323 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
11325 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
11327 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
11328 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
11329 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
11330 /* The length of the request buffer per VF in bytes. */
11331 uint16_t req_buf_len;
11332 /* The length of the response buffer in bytes. */
11333 uint16_t resp_buf_len;
11334 uint8_t unused_0[2];
11335 /* This field represents the page address of page #0. */
11336 uint64_t req_buf_page_addr0;
11337 /* This field represents the page address of page #1. */
11338 uint64_t req_buf_page_addr1;
11339 /* This field represents the page address of page #2. */
11340 uint64_t req_buf_page_addr2;
11341 /* This field represents the page address of page #3. */
11342 uint64_t req_buf_page_addr3;
11343 /* This field represents the page address of page #4. */
11344 uint64_t req_buf_page_addr4;
11345 /* This field represents the page address of page #5. */
11346 uint64_t req_buf_page_addr5;
11347 /* This field represents the page address of page #6. */
11348 uint64_t req_buf_page_addr6;
11349 /* This field represents the page address of page #7. */
11350 uint64_t req_buf_page_addr7;
11351 /* This field represents the page address of page #8. */
11352 uint64_t req_buf_page_addr8;
11353 /* This field represents the page address of page #9. */
11354 uint64_t req_buf_page_addr9;
11356 * This field is used to receive the error reporting from
11357 * the chipset. Only applicable for PFs.
11359 uint64_t error_buf_addr;
11361 * This field is used to receive the response forwarded by the
11364 uint64_t resp_buf_addr;
11367 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
11368 struct hwrm_func_buf_rgtr_output {
11369 /* The specific error status for the command. */
11370 uint16_t error_code;
11371 /* The HWRM command request type. */
11373 /* The sequence ID from the original command. */
11375 /* The length of the response data in number of bytes. */
11377 uint8_t unused_0[7];
11379 * This field is used in Output records to indicate that the output
11380 * is completely written to RAM. This field should be read as '1'
11381 * to indicate that the output has been completely written.
11382 * When writing a command completion or response to an internal processor,
11383 * the order of writes has to be such that this field is written last.
11388 /************************
11389 * hwrm_func_buf_unrgtr *
11390 ************************/
11393 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
11394 struct hwrm_func_buf_unrgtr_input {
11395 /* The HWRM command request type. */
11398 * The completion ring to send the completion event on. This should
11399 * be the NQ ID returned from the `nq_alloc` HWRM command.
11401 uint16_t cmpl_ring;
11403 * The sequence ID is used by the driver for tracking multiple
11404 * commands. This ID is treated as opaque data by the firmware and
11405 * the value is returned in the `hwrm_resp_hdr` upon completion.
11409 * The target ID of the command:
11410 * * 0x0-0xFFF8 - The function ID
11411 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11412 * * 0xFFFD - Reserved for user-space HWRM interface
11415 uint16_t target_id;
11417 * A physical address pointer pointing to a host buffer that the
11418 * command's response data will be written. This can be either a host
11419 * physical address (HPA) or a guest physical address (GPA) and must
11420 * point to a physically contiguous block of memory.
11422 uint64_t resp_addr;
11425 * This bit must be '1' for the vf_id field to be
11428 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11430 * This value is used to identify a Virtual Function (VF).
11431 * The scope of VF ID is local within a PF.
11434 uint8_t unused_0[2];
11437 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
11438 struct hwrm_func_buf_unrgtr_output {
11439 /* The specific error status for the command. */
11440 uint16_t error_code;
11441 /* The HWRM command request type. */
11443 /* The sequence ID from the original command. */
11445 /* The length of the response data in number of bytes. */
11447 uint8_t unused_0[7];
11449 * This field is used in Output records to indicate that the output
11450 * is completely written to RAM. This field should be read as '1'
11451 * to indicate that the output has been completely written.
11452 * When writing a command completion or response to an internal processor,
11453 * the order of writes has to be such that this field is written last.
11458 /**********************
11459 * hwrm_func_drv_qver *
11460 **********************/
11463 /* hwrm_func_drv_qver_input (size:192b/24B) */
11464 struct hwrm_func_drv_qver_input {
11465 /* The HWRM command request type. */
11468 * The completion ring to send the completion event on. This should
11469 * be the NQ ID returned from the `nq_alloc` HWRM command.
11471 uint16_t cmpl_ring;
11473 * The sequence ID is used by the driver for tracking multiple
11474 * commands. This ID is treated as opaque data by the firmware and
11475 * the value is returned in the `hwrm_resp_hdr` upon completion.
11479 * The target ID of the command:
11480 * * 0x0-0xFFF8 - The function ID
11481 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11482 * * 0xFFFD - Reserved for user-space HWRM interface
11485 uint16_t target_id;
11487 * A physical address pointer pointing to a host buffer that the
11488 * command's response data will be written. This can be either a host
11489 * physical address (HPA) or a guest physical address (GPA) and must
11490 * point to a physically contiguous block of memory.
11492 uint64_t resp_addr;
11493 /* Reserved for future use. */
11496 * Function ID of the function that is being queried.
11497 * 0xFF... (All Fs) if the query is for the requesting
11501 uint8_t unused_0[2];
11504 /* hwrm_func_drv_qver_output (size:256b/32B) */
11505 struct hwrm_func_drv_qver_output {
11506 /* The specific error status for the command. */
11507 uint16_t error_code;
11508 /* The HWRM command request type. */
11510 /* The sequence ID from the original command. */
11512 /* The length of the response data in number of bytes. */
11514 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11517 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11518 /* Other OS not listed below. */
11519 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
11521 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11523 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11525 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11527 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
11529 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11530 /* VMware ESXi OS. */
11531 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
11532 /* Microsoft Windows 8 64-bit OS. */
11533 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11534 /* Microsoft Windows Server 2012 R2 OS. */
11535 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11537 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11538 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
11539 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
11540 /* This is the 8bit major version of the driver. */
11541 uint8_t ver_maj_8b;
11542 /* This is the 8bit minor version of the driver. */
11543 uint8_t ver_min_8b;
11544 /* This is the 8bit update version of the driver. */
11545 uint8_t ver_upd_8b;
11546 uint8_t unused_0[3];
11547 /* This is the 16bit major version of the driver. */
11549 /* This is the 16bit minor version of the driver. */
11551 /* This is the 16bit update version of the driver. */
11553 /* This is the 16bit patch version of the driver. */
11554 uint16_t ver_patch;
11555 uint8_t unused_1[7];
11557 * This field is used in Output records to indicate that the output
11558 * is completely written to RAM. This field should be read as '1'
11559 * to indicate that the output has been completely written.
11560 * When writing a command completion or response to an internal processor,
11561 * the order of writes has to be such that this field is written last.
11566 /****************************
11567 * hwrm_func_resource_qcaps *
11568 ****************************/
11571 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
11572 struct hwrm_func_resource_qcaps_input {
11573 /* The HWRM command request type. */
11576 * The completion ring to send the completion event on. This should
11577 * be the NQ ID returned from the `nq_alloc` HWRM command.
11579 uint16_t cmpl_ring;
11581 * The sequence ID is used by the driver for tracking multiple
11582 * commands. This ID is treated as opaque data by the firmware and
11583 * the value is returned in the `hwrm_resp_hdr` upon completion.
11587 * The target ID of the command:
11588 * * 0x0-0xFFF8 - The function ID
11589 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11590 * * 0xFFFD - Reserved for user-space HWRM interface
11593 uint16_t target_id;
11595 * A physical address pointer pointing to a host buffer that the
11596 * command's response data will be written. This can be either a host
11597 * physical address (HPA) or a guest physical address (GPA) and must
11598 * point to a physically contiguous block of memory.
11600 uint64_t resp_addr;
11602 * Function ID of the function that is being queried.
11603 * 0xFF... (All Fs) if the query is for the requesting
11607 uint8_t unused_0[6];
11610 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
11611 struct hwrm_func_resource_qcaps_output {
11612 /* The specific error status for the command. */
11613 uint16_t error_code;
11614 /* The HWRM command request type. */
11616 /* The sequence ID from the original command. */
11618 /* The length of the response data in number of bytes. */
11620 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
11622 /* Maximum guaranteed number of MSI-X vectors supported by function */
11624 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
11625 uint16_t vf_reservation_strategy;
11626 /* The PF driver should evenly divide its remaining resources among all VFs. */
11627 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
11629 /* The PF driver should only reserve minimal resources for each VF. */
11630 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
11633 * The PF driver should not reserve any resources for each VF until the
11634 * the VF interface is brought up.
11636 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
11638 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
11639 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
11640 /* Minimum guaranteed number of RSS/COS contexts */
11641 uint16_t min_rsscos_ctx;
11642 /* Maximum non-guaranteed number of RSS/COS contexts */
11643 uint16_t max_rsscos_ctx;
11644 /* Minimum guaranteed number of completion rings */
11645 uint16_t min_cmpl_rings;
11646 /* Maximum non-guaranteed number of completion rings */
11647 uint16_t max_cmpl_rings;
11648 /* Minimum guaranteed number of transmit rings */
11649 uint16_t min_tx_rings;
11650 /* Maximum non-guaranteed number of transmit rings */
11651 uint16_t max_tx_rings;
11652 /* Minimum guaranteed number of receive rings */
11653 uint16_t min_rx_rings;
11654 /* Maximum non-guaranteed number of receive rings */
11655 uint16_t max_rx_rings;
11656 /* Minimum guaranteed number of L2 contexts */
11657 uint16_t min_l2_ctxs;
11658 /* Maximum non-guaranteed number of L2 contexts */
11659 uint16_t max_l2_ctxs;
11660 /* Minimum guaranteed number of VNICs */
11661 uint16_t min_vnics;
11662 /* Maximum non-guaranteed number of VNICs */
11663 uint16_t max_vnics;
11664 /* Minimum guaranteed number of statistic contexts */
11665 uint16_t min_stat_ctx;
11666 /* Maximum non-guaranteed number of statistic contexts */
11667 uint16_t max_stat_ctx;
11668 /* Minimum guaranteed number of ring groups */
11669 uint16_t min_hw_ring_grps;
11670 /* Maximum non-guaranteed number of ring groups */
11671 uint16_t max_hw_ring_grps;
11673 * Maximum number of inputs into the transmit scheduler for this function.
11674 * The number of TX rings assigned to the function cannot exceed this value.
11676 uint16_t max_tx_scheduler_inputs;
11679 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
11680 * feature to reserve all minimum resources when minimum >= 1, otherwise
11681 * returns an error.
11683 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
11685 uint8_t unused_0[5];
11687 * This field is used in Output records to indicate that the output
11688 * is completely written to RAM. This field should be read as '1'
11689 * to indicate that the output has been completely written.
11690 * When writing a command completion or response to an internal processor,
11691 * the order of writes has to be such that this field is written last.
11696 /*********************************
11697 * hwrm_func_backing_store_qcaps *
11698 *********************************/
11701 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
11702 struct hwrm_func_backing_store_qcaps_input {
11703 /* The HWRM command request type. */
11706 * The completion ring to send the completion event on. This should
11707 * be the NQ ID returned from the `nq_alloc` HWRM command.
11709 uint16_t cmpl_ring;
11711 * The sequence ID is used by the driver for tracking multiple
11712 * commands. This ID is treated as opaque data by the firmware and
11713 * the value is returned in the `hwrm_resp_hdr` upon completion.
11717 * The target ID of the command:
11718 * * 0x0-0xFFF8 - The function ID
11719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11720 * * 0xFFFD - Reserved for user-space HWRM interface
11723 uint16_t target_id;
11725 * A physical address pointer pointing to a host buffer that the
11726 * command's response data will be written. This can be either a host
11727 * physical address (HPA) or a guest physical address (GPA) and must
11728 * point to a physically contiguous block of memory.
11730 uint64_t resp_addr;
11733 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
11734 struct hwrm_func_backing_store_qcaps_output {
11735 /* The specific error status for the command. */
11736 uint16_t error_code;
11737 /* The HWRM command request type. */
11739 /* The sequence ID from the original command. */
11741 /* The length of the response data in number of bytes. */
11743 /* Maximum number of QP context entries supported for this function. */
11744 uint32_t qp_max_entries;
11746 * Minimum number of QP context entries that are needed to be reserved
11747 * for QP1 for the PF and its VFs. PF drivers must allocate at least
11748 * this many QP context entries, even if RoCE will not be used.
11750 uint16_t qp_min_qp1_entries;
11751 /* Maximum number of QP context entries that can be used for L2. */
11752 uint16_t qp_max_l2_entries;
11753 /* Number of bytes that must be allocated for each context entry. */
11754 uint16_t qp_entry_size;
11755 /* Maximum number of SRQ context entries that can be used for L2. */
11756 uint16_t srq_max_l2_entries;
11757 /* Maximum number of SRQ context entries supported for this function. */
11758 uint32_t srq_max_entries;
11759 /* Number of bytes that must be allocated for each context entry. */
11760 uint16_t srq_entry_size;
11761 /* Maximum number of CQ context entries that can be used for L2. */
11762 uint16_t cq_max_l2_entries;
11763 /* Maximum number of CQ context entries supported for this function. */
11764 uint32_t cq_max_entries;
11765 /* Number of bytes that must be allocated for each context entry. */
11766 uint16_t cq_entry_size;
11767 /* Maximum number of VNIC context entries supported for this function. */
11768 uint16_t vnic_max_vnic_entries;
11769 /* Maximum number of Ring table context entries supported for this function. */
11770 uint16_t vnic_max_ring_table_entries;
11771 /* Number of bytes that must be allocated for each context entry. */
11772 uint16_t vnic_entry_size;
11773 /* Maximum number of statistic context entries supported for this function. */
11774 uint32_t stat_max_entries;
11775 /* Number of bytes that must be allocated for each context entry. */
11776 uint16_t stat_entry_size;
11777 /* Number of bytes that must be allocated for each context entry. */
11778 uint16_t tqm_entry_size;
11779 /* Minimum number of TQM context entries required per ring. */
11780 uint32_t tqm_min_entries_per_ring;
11782 * Maximum number of TQM context entries supported per ring. This is
11783 * actually a recommended TQM queue size based on worst case usage of
11786 * TQM fastpath rings should be sized large enough to accommodate the
11787 * maximum number of QPs (either L2 or RoCE, or both if shared)
11788 * that can be enqueued to the TQM ring.
11790 * TQM slowpath rings should be sized as follows:
11792 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
11795 * num_vnics is the number of VNICs allocated in the VNIC backing store
11796 * num_l2_tx_rings is the number of L2 rings in the QP backing store
11797 * num_roce_qps is the number of RoCE QPs in the QP backing store
11798 * tqm_min_size is tqm_min_entries_per_ring reported by
11799 * HWRM_FUNC_BACKING_STORE_QCAPS
11801 * Note that TQM ring sizes cannot be extended while the system is
11802 * operational. If a PF driver needs to extend a TQM ring, it needs
11803 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11804 * the backing store.
11806 uint32_t tqm_max_entries_per_ring;
11808 * Maximum number of MR plus AV context entries supported for this
11811 uint32_t mrav_max_entries;
11812 /* Number of bytes that must be allocated for each context entry. */
11813 uint16_t mrav_entry_size;
11814 /* Number of bytes that must be allocated for each context entry. */
11815 uint16_t tim_entry_size;
11816 /* Maximum number of Timer context entries supported for this function. */
11817 uint32_t tim_max_entries;
11819 * When this field is zero, the 32b `mrav_num_entries` field in the
11820 * `backing_store_cfg` and `backing_store_qcfg` commands represents
11821 * the total number of MR plus AV entries allowed in the MR/AV backing
11824 * When this field is non-zero, the 32b `mrav_num_entries` field in
11825 * the `backing_store_cfg` and `backing_store_qcfg` commands is
11826 * logically divided into two 16b fields. Bits `[31:16]` represents
11827 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
11828 * Both of these values are represented in a unit granularity
11829 * specified by this field. For example, if this field is 16 and
11830 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
11831 * is 8192 and the number of AV entries is 4096.
11833 uint16_t mrav_num_entries_units;
11835 * The number of entries specified for any TQM ring must be a
11836 * multiple of this value to prevent any resource allocation
11839 uint8_t tqm_entries_multiple;
11841 * Initializer to be used by drivers
11842 * to initialize context memory to ensure
11843 * context subsystem flags an error for an attack
11844 * before the first time context load.
11846 uint8_t ctx_kind_initializer;
11847 /* Reserved for future. */
11849 /* Reserved for future. */
11852 * Count of TQM fastpath rings to be used for allocating backing store.
11853 * Backing store configuration must be specified for each TQM ring from
11854 * this count in `backing_store_cfg`.
11856 uint8_t tqm_fp_rings_count;
11858 * This field is used in Output records to indicate that the output
11859 * is completely written to RAM. This field should be read as '1'
11860 * to indicate that the output has been completely written.
11861 * When writing a command completion or response to an internal processor,
11862 * the order of writes has to be such that this field is written last.
11867 /*******************************
11868 * hwrm_func_backing_store_cfg *
11869 *******************************/
11872 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
11873 struct hwrm_func_backing_store_cfg_input {
11874 /* The HWRM command request type. */
11877 * The completion ring to send the completion event on. This should
11878 * be the NQ ID returned from the `nq_alloc` HWRM command.
11880 uint16_t cmpl_ring;
11882 * The sequence ID is used by the driver for tracking multiple
11883 * commands. This ID is treated as opaque data by the firmware and
11884 * the value is returned in the `hwrm_resp_hdr` upon completion.
11888 * The target ID of the command:
11889 * * 0x0-0xFFF8 - The function ID
11890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11891 * * 0xFFFD - Reserved for user-space HWRM interface
11894 uint16_t target_id;
11896 * A physical address pointer pointing to a host buffer that the
11897 * command's response data will be written. This can be either a host
11898 * physical address (HPA) or a guest physical address (GPA) and must
11899 * point to a physically contiguous block of memory.
11901 uint64_t resp_addr;
11904 * When set, the firmware only uses on-chip resources and does not
11905 * expect any backing store to be provided by the host driver. This
11906 * mode provides minimal L2 functionality (e.g. limited L2 resources,
11909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
11912 * When set, the 32b `mrav_num_entries` field is logically divided
11913 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
11915 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
11919 * This bit must be '1' for the qp fields to be
11922 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
11925 * This bit must be '1' for the srq fields to be
11928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
11931 * This bit must be '1' for the cq fields to be
11934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
11937 * This bit must be '1' for the vnic fields to be
11940 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
11943 * This bit must be '1' for the stat fields to be
11946 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
11949 * This bit must be '1' for the tqm_sp fields to be
11952 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
11955 * This bit must be '1' for the tqm_ring0 fields to be
11958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
11961 * This bit must be '1' for the tqm_ring1 fields to be
11964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
11967 * This bit must be '1' for the tqm_ring2 fields to be
11970 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
11973 * This bit must be '1' for the tqm_ring3 fields to be
11976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
11979 * This bit must be '1' for the tqm_ring4 fields to be
11982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
11985 * This bit must be '1' for the tqm_ring5 fields to be
11988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
11991 * This bit must be '1' for the tqm_ring6 fields to be
11994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
11997 * This bit must be '1' for the tqm_ring7 fields to be
12000 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
12003 * This bit must be '1' for the mrav fields to be
12006 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
12009 * This bit must be '1' for the tim fields to be
12012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
12014 /* QPC page size and level. */
12015 uint8_t qpc_pg_size_qpc_lvl;
12016 /* QPC PBL indirect levels. */
12017 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
12019 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
12020 /* PBL pointer is physical start address. */
12021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
12023 /* PBL pointer points to PTE table. */
12024 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
12026 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
12029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
12030 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
12031 /* QPC page size. */
12032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
12034 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
12036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
12037 (UINT32_C(0x0) << 4)
12039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
12040 (UINT32_C(0x1) << 4)
12042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
12043 (UINT32_C(0x2) << 4)
12045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
12046 (UINT32_C(0x3) << 4)
12048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
12049 (UINT32_C(0x4) << 4)
12051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
12052 (UINT32_C(0x5) << 4)
12053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
12054 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
12055 /* SRQ page size and level. */
12056 uint8_t srq_pg_size_srq_lvl;
12057 /* SRQ PBL indirect levels. */
12058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
12060 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
12061 /* PBL pointer is physical start address. */
12062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
12064 /* PBL pointer points to PTE table. */
12065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
12067 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
12070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
12071 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
12072 /* SRQ page size. */
12073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
12075 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
12077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
12078 (UINT32_C(0x0) << 4)
12080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
12081 (UINT32_C(0x1) << 4)
12083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
12084 (UINT32_C(0x2) << 4)
12086 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
12087 (UINT32_C(0x3) << 4)
12089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
12090 (UINT32_C(0x4) << 4)
12092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
12093 (UINT32_C(0x5) << 4)
12094 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
12095 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
12096 /* CQ page size and level. */
12097 uint8_t cq_pg_size_cq_lvl;
12098 /* CQ PBL indirect levels. */
12099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
12101 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
12102 /* PBL pointer is physical start address. */
12103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
12105 /* PBL pointer points to PTE table. */
12106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
12108 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
12111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
12112 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
12113 /* CQ page size. */
12114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
12116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
12118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
12119 (UINT32_C(0x0) << 4)
12121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
12122 (UINT32_C(0x1) << 4)
12124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
12125 (UINT32_C(0x2) << 4)
12127 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
12128 (UINT32_C(0x3) << 4)
12130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
12131 (UINT32_C(0x4) << 4)
12133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
12134 (UINT32_C(0x5) << 4)
12135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
12136 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
12137 /* VNIC page size and level. */
12138 uint8_t vnic_pg_size_vnic_lvl;
12139 /* VNIC PBL indirect levels. */
12140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
12142 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
12143 /* PBL pointer is physical start address. */
12144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
12146 /* PBL pointer points to PTE table. */
12147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
12149 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
12152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
12153 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
12154 /* VNIC page size. */
12155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
12157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
12159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
12160 (UINT32_C(0x0) << 4)
12162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
12163 (UINT32_C(0x1) << 4)
12165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
12166 (UINT32_C(0x2) << 4)
12168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
12169 (UINT32_C(0x3) << 4)
12171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
12172 (UINT32_C(0x4) << 4)
12174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
12175 (UINT32_C(0x5) << 4)
12176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
12177 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
12178 /* Stat page size and level. */
12179 uint8_t stat_pg_size_stat_lvl;
12180 /* Stat PBL indirect levels. */
12181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
12183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
12184 /* PBL pointer is physical start address. */
12185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
12187 /* PBL pointer points to PTE table. */
12188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
12190 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
12193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
12194 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
12195 /* Stat page size. */
12196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
12198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
12200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
12201 (UINT32_C(0x0) << 4)
12203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
12204 (UINT32_C(0x1) << 4)
12206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
12207 (UINT32_C(0x2) << 4)
12209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
12210 (UINT32_C(0x3) << 4)
12212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
12213 (UINT32_C(0x4) << 4)
12215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
12216 (UINT32_C(0x5) << 4)
12217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
12218 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
12219 /* TQM slow path page size and level. */
12220 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
12221 /* TQM slow path PBL indirect levels. */
12222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
12224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
12225 /* PBL pointer is physical start address. */
12226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
12228 /* PBL pointer points to PTE table. */
12229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
12231 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
12234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
12235 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
12236 /* TQM slow path page size. */
12237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
12239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
12241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
12242 (UINT32_C(0x0) << 4)
12244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
12245 (UINT32_C(0x1) << 4)
12247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
12248 (UINT32_C(0x2) << 4)
12250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
12251 (UINT32_C(0x3) << 4)
12253 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
12254 (UINT32_C(0x4) << 4)
12256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
12257 (UINT32_C(0x5) << 4)
12258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
12259 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
12260 /* TQM ring 0 page size and level. */
12261 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
12262 /* TQM ring 0 PBL indirect levels. */
12263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
12265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
12266 /* PBL pointer is physical start address. */
12267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
12269 /* PBL pointer points to PTE table. */
12270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
12272 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
12275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
12276 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
12277 /* TQM ring 0 page size. */
12278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
12280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
12282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
12283 (UINT32_C(0x0) << 4)
12285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
12286 (UINT32_C(0x1) << 4)
12288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
12289 (UINT32_C(0x2) << 4)
12291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
12292 (UINT32_C(0x3) << 4)
12294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
12295 (UINT32_C(0x4) << 4)
12297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
12298 (UINT32_C(0x5) << 4)
12299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
12300 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
12301 /* TQM ring 1 page size and level. */
12302 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
12303 /* TQM ring 1 PBL indirect levels. */
12304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
12306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
12307 /* PBL pointer is physical start address. */
12308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
12310 /* PBL pointer points to PTE table. */
12311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
12313 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
12316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
12317 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
12318 /* TQM ring 1 page size. */
12319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
12321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
12323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
12324 (UINT32_C(0x0) << 4)
12326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
12327 (UINT32_C(0x1) << 4)
12329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
12330 (UINT32_C(0x2) << 4)
12332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
12333 (UINT32_C(0x3) << 4)
12335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
12336 (UINT32_C(0x4) << 4)
12338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
12339 (UINT32_C(0x5) << 4)
12340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
12341 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
12342 /* TQM ring 2 page size and level. */
12343 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
12344 /* TQM ring 2 PBL indirect levels. */
12345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
12347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
12348 /* PBL pointer is physical start address. */
12349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
12351 /* PBL pointer points to PTE table. */
12352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
12354 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
12357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
12358 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
12359 /* TQM ring 2 page size. */
12360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
12362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
12364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
12365 (UINT32_C(0x0) << 4)
12367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
12368 (UINT32_C(0x1) << 4)
12370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
12371 (UINT32_C(0x2) << 4)
12373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
12374 (UINT32_C(0x3) << 4)
12376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
12377 (UINT32_C(0x4) << 4)
12379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
12380 (UINT32_C(0x5) << 4)
12381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
12382 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
12383 /* TQM ring 3 page size and level. */
12384 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
12385 /* TQM ring 3 PBL indirect levels. */
12386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
12388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
12389 /* PBL pointer is physical start address. */
12390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
12392 /* PBL pointer points to PTE table. */
12393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
12395 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
12398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
12399 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
12400 /* TQM ring 3 page size. */
12401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
12403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
12405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
12406 (UINT32_C(0x0) << 4)
12408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
12409 (UINT32_C(0x1) << 4)
12411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
12412 (UINT32_C(0x2) << 4)
12414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
12415 (UINT32_C(0x3) << 4)
12417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
12418 (UINT32_C(0x4) << 4)
12420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
12421 (UINT32_C(0x5) << 4)
12422 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
12423 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
12424 /* TQM ring 4 page size and level. */
12425 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
12426 /* TQM ring 4 PBL indirect levels. */
12427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
12429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
12430 /* PBL pointer is physical start address. */
12431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
12433 /* PBL pointer points to PTE table. */
12434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
12436 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
12439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
12440 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
12441 /* TQM ring 4 page size. */
12442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
12444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
12446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
12447 (UINT32_C(0x0) << 4)
12449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
12450 (UINT32_C(0x1) << 4)
12452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
12453 (UINT32_C(0x2) << 4)
12455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
12456 (UINT32_C(0x3) << 4)
12458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
12459 (UINT32_C(0x4) << 4)
12461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
12462 (UINT32_C(0x5) << 4)
12463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
12464 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
12465 /* TQM ring 5 page size and level. */
12466 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
12467 /* TQM ring 5 PBL indirect levels. */
12468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
12470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
12471 /* PBL pointer is physical start address. */
12472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
12474 /* PBL pointer points to PTE table. */
12475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
12477 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
12480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
12481 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
12482 /* TQM ring 5 page size. */
12483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
12485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
12487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
12488 (UINT32_C(0x0) << 4)
12490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
12491 (UINT32_C(0x1) << 4)
12493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
12494 (UINT32_C(0x2) << 4)
12496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
12497 (UINT32_C(0x3) << 4)
12499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
12500 (UINT32_C(0x4) << 4)
12502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
12503 (UINT32_C(0x5) << 4)
12504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
12505 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
12506 /* TQM ring 6 page size and level. */
12507 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
12508 /* TQM ring 6 PBL indirect levels. */
12509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
12511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
12512 /* PBL pointer is physical start address. */
12513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
12515 /* PBL pointer points to PTE table. */
12516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
12518 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
12521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
12522 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
12523 /* TQM ring 6 page size. */
12524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
12526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
12528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
12529 (UINT32_C(0x0) << 4)
12531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
12532 (UINT32_C(0x1) << 4)
12534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
12535 (UINT32_C(0x2) << 4)
12537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
12538 (UINT32_C(0x3) << 4)
12540 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
12541 (UINT32_C(0x4) << 4)
12543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
12544 (UINT32_C(0x5) << 4)
12545 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
12546 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
12547 /* TQM ring 7 page size and level. */
12548 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
12549 /* TQM ring 7 PBL indirect levels. */
12550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
12552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
12553 /* PBL pointer is physical start address. */
12554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
12556 /* PBL pointer points to PTE table. */
12557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
12559 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
12562 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
12563 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
12564 /* TQM ring 7 page size. */
12565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
12567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
12569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
12570 (UINT32_C(0x0) << 4)
12572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
12573 (UINT32_C(0x1) << 4)
12575 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
12576 (UINT32_C(0x2) << 4)
12578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
12579 (UINT32_C(0x3) << 4)
12581 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
12582 (UINT32_C(0x4) << 4)
12584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
12585 (UINT32_C(0x5) << 4)
12586 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
12587 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
12588 /* MR/AV page size and level. */
12589 uint8_t mrav_pg_size_mrav_lvl;
12590 /* MR/AV PBL indirect levels. */
12591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
12593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
12594 /* PBL pointer is physical start address. */
12595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
12597 /* PBL pointer points to PTE table. */
12598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
12600 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
12603 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
12604 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
12605 /* MR/AV page size. */
12606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
12608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
12610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
12611 (UINT32_C(0x0) << 4)
12613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
12614 (UINT32_C(0x1) << 4)
12616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
12617 (UINT32_C(0x2) << 4)
12619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
12620 (UINT32_C(0x3) << 4)
12622 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
12623 (UINT32_C(0x4) << 4)
12625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
12626 (UINT32_C(0x5) << 4)
12627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
12628 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
12629 /* Timer page size and level. */
12630 uint8_t tim_pg_size_tim_lvl;
12631 /* Timer PBL indirect levels. */
12632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
12634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
12635 /* PBL pointer is physical start address. */
12636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
12638 /* PBL pointer points to PTE table. */
12639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
12641 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
12644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
12645 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
12646 /* Timer page size. */
12647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
12649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
12651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
12652 (UINT32_C(0x0) << 4)
12654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
12655 (UINT32_C(0x1) << 4)
12657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
12658 (UINT32_C(0x2) << 4)
12660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
12661 (UINT32_C(0x3) << 4)
12663 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
12664 (UINT32_C(0x4) << 4)
12666 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
12667 (UINT32_C(0x5) << 4)
12668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
12669 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
12670 /* QP page directory. */
12671 uint64_t qpc_page_dir;
12672 /* SRQ page directory. */
12673 uint64_t srq_page_dir;
12674 /* CQ page directory. */
12675 uint64_t cq_page_dir;
12676 /* VNIC page directory. */
12677 uint64_t vnic_page_dir;
12678 /* Stat page directory. */
12679 uint64_t stat_page_dir;
12680 /* TQM slowpath page directory. */
12681 uint64_t tqm_sp_page_dir;
12682 /* TQM ring 0 page directory. */
12683 uint64_t tqm_ring0_page_dir;
12684 /* TQM ring 1 page directory. */
12685 uint64_t tqm_ring1_page_dir;
12686 /* TQM ring 2 page directory. */
12687 uint64_t tqm_ring2_page_dir;
12688 /* TQM ring 3 page directory. */
12689 uint64_t tqm_ring3_page_dir;
12690 /* TQM ring 4 page directory. */
12691 uint64_t tqm_ring4_page_dir;
12692 /* TQM ring 5 page directory. */
12693 uint64_t tqm_ring5_page_dir;
12694 /* TQM ring 6 page directory. */
12695 uint64_t tqm_ring6_page_dir;
12696 /* TQM ring 7 page directory. */
12697 uint64_t tqm_ring7_page_dir;
12698 /* MR/AV page directory. */
12699 uint64_t mrav_page_dir;
12700 /* Timer page directory. */
12701 uint64_t tim_page_dir;
12702 /* Number of QPs. */
12703 uint32_t qp_num_entries;
12704 /* Number of SRQs. */
12705 uint32_t srq_num_entries;
12706 /* Number of CQs. */
12707 uint32_t cq_num_entries;
12708 /* Number of Stats. */
12709 uint32_t stat_num_entries;
12711 * Number of TQM slowpath entries.
12713 * TQM slowpath rings should be sized as follows:
12715 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
12718 * num_vnics is the number of VNICs allocated in the VNIC backing store
12719 * num_l2_tx_rings is the number of L2 rings in the QP backing store
12720 * num_roce_qps is the number of RoCE QPs in the QP backing store
12721 * tqm_min_size is tqm_min_entries_per_ring reported by
12722 * HWRM_FUNC_BACKING_STORE_QCAPS
12724 * Note that TQM ring sizes cannot be extended while the system is
12725 * operational. If a PF driver needs to extend a TQM ring, it needs
12726 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12727 * the backing store.
12729 uint32_t tqm_sp_num_entries;
12731 * Number of TQM ring 0 entries.
12733 * TQM fastpath rings should be sized large enough to accommodate the
12734 * maximum number of QPs (either L2 or RoCE, or both if shared)
12735 * that can be enqueued to the TQM ring.
12737 * Note that TQM ring sizes cannot be extended while the system is
12738 * operational. If a PF driver needs to extend a TQM ring, it needs
12739 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12740 * the backing store.
12742 uint32_t tqm_ring0_num_entries;
12744 * Number of TQM ring 1 entries.
12746 * TQM fastpath rings should be sized large enough to accommodate the
12747 * maximum number of QPs (either L2 or RoCE, or both if shared)
12748 * that can be enqueued to the TQM ring.
12750 * Note that TQM ring sizes cannot be extended while the system is
12751 * operational. If a PF driver needs to extend a TQM ring, it needs
12752 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12753 * the backing store.
12755 uint32_t tqm_ring1_num_entries;
12757 * Number of TQM ring 2 entries.
12759 * TQM fastpath rings should be sized large enough to accommodate the
12760 * maximum number of QPs (either L2 or RoCE, or both if shared)
12761 * that can be enqueued to the TQM ring.
12763 * Note that TQM ring sizes cannot be extended while the system is
12764 * operational. If a PF driver needs to extend a TQM ring, it needs
12765 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12766 * the backing store.
12768 uint32_t tqm_ring2_num_entries;
12770 * Number of TQM ring 3 entries.
12772 * TQM fastpath rings should be sized large enough to accommodate the
12773 * maximum number of QPs (either L2 or RoCE, or both if shared)
12774 * that can be enqueued to the TQM ring.
12776 * Note that TQM ring sizes cannot be extended while the system is
12777 * operational. If a PF driver needs to extend a TQM ring, it needs
12778 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12779 * the backing store.
12781 uint32_t tqm_ring3_num_entries;
12783 * Number of TQM ring 4 entries.
12785 * TQM fastpath rings should be sized large enough to accommodate the
12786 * maximum number of QPs (either L2 or RoCE, or both if shared)
12787 * that can be enqueued to the TQM ring.
12789 * Note that TQM ring sizes cannot be extended while the system is
12790 * operational. If a PF driver needs to extend a TQM ring, it needs
12791 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12792 * the backing store.
12794 uint32_t tqm_ring4_num_entries;
12796 * Number of TQM ring 5 entries.
12798 * TQM fastpath rings should be sized large enough to accommodate the
12799 * maximum number of QPs (either L2 or RoCE, or both if shared)
12800 * that can be enqueued to the TQM ring.
12802 * Note that TQM ring sizes cannot be extended while the system is
12803 * operational. If a PF driver needs to extend a TQM ring, it needs
12804 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12805 * the backing store.
12807 uint32_t tqm_ring5_num_entries;
12809 * Number of TQM ring 6 entries.
12811 * TQM fastpath rings should be sized large enough to accommodate the
12812 * maximum number of QPs (either L2 or RoCE, or both if shared)
12813 * that can be enqueued to the TQM ring.
12815 * Note that TQM ring sizes cannot be extended while the system is
12816 * operational. If a PF driver needs to extend a TQM ring, it needs
12817 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12818 * the backing store.
12820 uint32_t tqm_ring6_num_entries;
12822 * Number of TQM ring 7 entries.
12824 * TQM fastpath rings should be sized large enough to accommodate the
12825 * maximum number of QPs (either L2 or RoCE, or both if shared)
12826 * that can be enqueued to the TQM ring.
12828 * Note that TQM ring sizes cannot be extended while the system is
12829 * operational. If a PF driver needs to extend a TQM ring, it needs
12830 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12831 * the backing store.
12833 uint32_t tqm_ring7_num_entries;
12835 * If the MR/AV split reservation flag is not set, then this field
12836 * represents the total number of MR plus AV entries. For versions
12837 * of firmware that support the split reservation, when it is not
12838 * specified half of the entries will be reserved for MRs and the
12839 * other half for AVs.
12841 * If the MR/AV split reservation flag is set, then this
12842 * field is logically divided into two 16b fields. Bits `[31:16]`
12843 * represents the `mr_num_entries` and bits `[15:0]` represents
12844 * `av_num_entries`. The granularity of these values is defined by
12845 * the `mrav_num_entries_unit` field returned by the
12846 * `backing_store_qcaps` command.
12848 uint32_t mrav_num_entries;
12849 /* Number of Timer entries. */
12850 uint32_t tim_num_entries;
12851 /* Number of entries to reserve for QP1 */
12852 uint16_t qp_num_qp1_entries;
12853 /* Number of entries to reserve for L2 */
12854 uint16_t qp_num_l2_entries;
12855 /* Number of bytes that have been allocated for each context entry. */
12856 uint16_t qp_entry_size;
12857 /* Number of entries to reserve for L2 */
12858 uint16_t srq_num_l2_entries;
12859 /* Number of bytes that have been allocated for each context entry. */
12860 uint16_t srq_entry_size;
12861 /* Number of entries to reserve for L2 */
12862 uint16_t cq_num_l2_entries;
12863 /* Number of bytes that have been allocated for each context entry. */
12864 uint16_t cq_entry_size;
12865 /* Number of entries to reserve for VNIC entries */
12866 uint16_t vnic_num_vnic_entries;
12867 /* Number of entries to reserve for Ring table entries */
12868 uint16_t vnic_num_ring_table_entries;
12869 /* Number of bytes that have been allocated for each context entry. */
12870 uint16_t vnic_entry_size;
12871 /* Number of bytes that have been allocated for each context entry. */
12872 uint16_t stat_entry_size;
12873 /* Number of bytes that have been allocated for each context entry. */
12874 uint16_t tqm_entry_size;
12875 /* Number of bytes that have been allocated for each context entry. */
12876 uint16_t mrav_entry_size;
12877 /* Number of bytes that have been allocated for each context entry. */
12878 uint16_t tim_entry_size;
12881 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
12882 struct hwrm_func_backing_store_cfg_output {
12883 /* The specific error status for the command. */
12884 uint16_t error_code;
12885 /* The HWRM command request type. */
12887 /* The sequence ID from the original command. */
12889 /* The length of the response data in number of bytes. */
12891 uint8_t unused_0[7];
12893 * This field is used in Output records to indicate that the output
12894 * is completely written to RAM. This field should be read as '1'
12895 * to indicate that the output has been completely written.
12896 * When writing a command completion or response to an internal processor,
12897 * the order of writes has to be such that this field is written last.
12902 /********************************
12903 * hwrm_func_backing_store_qcfg *
12904 ********************************/
12907 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
12908 struct hwrm_func_backing_store_qcfg_input {
12909 /* The HWRM command request type. */
12912 * The completion ring to send the completion event on. This should
12913 * be the NQ ID returned from the `nq_alloc` HWRM command.
12915 uint16_t cmpl_ring;
12917 * The sequence ID is used by the driver for tracking multiple
12918 * commands. This ID is treated as opaque data by the firmware and
12919 * the value is returned in the `hwrm_resp_hdr` upon completion.
12923 * The target ID of the command:
12924 * * 0x0-0xFFF8 - The function ID
12925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12926 * * 0xFFFD - Reserved for user-space HWRM interface
12929 uint16_t target_id;
12931 * A physical address pointer pointing to a host buffer that the
12932 * command's response data will be written. This can be either a host
12933 * physical address (HPA) or a guest physical address (GPA) and must
12934 * point to a physically contiguous block of memory.
12936 uint64_t resp_addr;
12939 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
12940 struct hwrm_func_backing_store_qcfg_output {
12941 /* The specific error status for the command. */
12942 uint16_t error_code;
12943 /* The HWRM command request type. */
12945 /* The sequence ID from the original command. */
12947 /* The length of the response data in number of bytes. */
12951 * When set, the firmware only uses on-chip resources and does not
12952 * expect any backing store to be provided by the host driver. This
12953 * mode provides minimal L2 functionality (e.g. limited L2 resources,
12956 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
12959 * When set, the 32b `mrav_num_entries` field is logically divided
12960 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
12962 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
12964 uint8_t unused_0[4];
12966 * This bit must be '1' for the qp fields to be
12969 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
12972 * This bit must be '1' for the srq fields to be
12975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
12978 * This bit must be '1' for the cq fields to be
12981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
12984 * This bit must be '1' for the vnic fields to be
12987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
12990 * This bit must be '1' for the stat fields to be
12993 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
12996 * This bit must be '1' for the tqm_sp fields to be
12999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
13002 * This bit must be '1' for the tqm_ring0 fields to be
13005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
13008 * This bit must be '1' for the tqm_ring1 fields to be
13011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
13014 * This bit must be '1' for the tqm_ring2 fields to be
13017 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
13020 * This bit must be '1' for the tqm_ring3 fields to be
13023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
13026 * This bit must be '1' for the tqm_ring4 fields to be
13029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
13032 * This bit must be '1' for the tqm_ring5 fields to be
13035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
13038 * This bit must be '1' for the tqm_ring6 fields to be
13041 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
13044 * This bit must be '1' for the tqm_ring7 fields to be
13047 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
13050 * This bit must be '1' for the mrav fields to be
13053 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
13056 * This bit must be '1' for the tim fields to be
13059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
13061 /* QPC page size and level. */
13062 uint8_t qpc_pg_size_qpc_lvl;
13063 /* QPC PBL indirect levels. */
13064 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
13066 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
13067 /* PBL pointer is physical start address. */
13068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
13070 /* PBL pointer points to PTE table. */
13071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
13073 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
13076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
13077 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
13078 /* QPC page size. */
13079 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
13081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
13083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
13084 (UINT32_C(0x0) << 4)
13086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
13087 (UINT32_C(0x1) << 4)
13089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
13090 (UINT32_C(0x2) << 4)
13092 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
13093 (UINT32_C(0x3) << 4)
13095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
13096 (UINT32_C(0x4) << 4)
13098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
13099 (UINT32_C(0x5) << 4)
13100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
13101 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
13102 /* SRQ page size and level. */
13103 uint8_t srq_pg_size_srq_lvl;
13104 /* SRQ PBL indirect levels. */
13105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
13107 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
13108 /* PBL pointer is physical start address. */
13109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
13111 /* PBL pointer points to PTE table. */
13112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
13114 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
13117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
13118 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
13119 /* SRQ page size. */
13120 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
13122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
13124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
13125 (UINT32_C(0x0) << 4)
13127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
13128 (UINT32_C(0x1) << 4)
13130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
13131 (UINT32_C(0x2) << 4)
13133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
13134 (UINT32_C(0x3) << 4)
13136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
13137 (UINT32_C(0x4) << 4)
13139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
13140 (UINT32_C(0x5) << 4)
13141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
13142 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
13143 /* CQ page size and level. */
13144 uint8_t cq_pg_size_cq_lvl;
13145 /* CQ PBL indirect levels. */
13146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
13148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
13149 /* PBL pointer is physical start address. */
13150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
13152 /* PBL pointer points to PTE table. */
13153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
13155 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
13158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
13159 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
13160 /* CQ page size. */
13161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
13163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
13165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
13166 (UINT32_C(0x0) << 4)
13168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
13169 (UINT32_C(0x1) << 4)
13171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
13172 (UINT32_C(0x2) << 4)
13174 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
13175 (UINT32_C(0x3) << 4)
13177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
13178 (UINT32_C(0x4) << 4)
13180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
13181 (UINT32_C(0x5) << 4)
13182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
13183 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
13184 /* VNIC page size and level. */
13185 uint8_t vnic_pg_size_vnic_lvl;
13186 /* VNIC PBL indirect levels. */
13187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
13189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
13190 /* PBL pointer is physical start address. */
13191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
13193 /* PBL pointer points to PTE table. */
13194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
13196 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
13199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
13200 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
13201 /* VNIC page size. */
13202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
13204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
13206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
13207 (UINT32_C(0x0) << 4)
13209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
13210 (UINT32_C(0x1) << 4)
13212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
13213 (UINT32_C(0x2) << 4)
13215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
13216 (UINT32_C(0x3) << 4)
13218 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
13219 (UINT32_C(0x4) << 4)
13221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
13222 (UINT32_C(0x5) << 4)
13223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
13224 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
13225 /* Stat page size and level. */
13226 uint8_t stat_pg_size_stat_lvl;
13227 /* Stat PBL indirect levels. */
13228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
13230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
13231 /* PBL pointer is physical start address. */
13232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
13234 /* PBL pointer points to PTE table. */
13235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
13237 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
13240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
13241 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
13242 /* Stat page size. */
13243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
13245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
13247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
13248 (UINT32_C(0x0) << 4)
13250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
13251 (UINT32_C(0x1) << 4)
13253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
13254 (UINT32_C(0x2) << 4)
13256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
13257 (UINT32_C(0x3) << 4)
13259 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
13260 (UINT32_C(0x4) << 4)
13262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
13263 (UINT32_C(0x5) << 4)
13264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
13265 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
13266 /* TQM slow path page size and level. */
13267 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
13268 /* TQM slow path PBL indirect levels. */
13269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
13271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
13272 /* PBL pointer is physical start address. */
13273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
13275 /* PBL pointer points to PTE table. */
13276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
13278 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
13281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
13282 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
13283 /* TQM slow path page size. */
13284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
13286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
13288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
13289 (UINT32_C(0x0) << 4)
13291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
13292 (UINT32_C(0x1) << 4)
13294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
13295 (UINT32_C(0x2) << 4)
13297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
13298 (UINT32_C(0x3) << 4)
13300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
13301 (UINT32_C(0x4) << 4)
13303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
13304 (UINT32_C(0x5) << 4)
13305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
13306 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
13307 /* TQM ring 0 page size and level. */
13308 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
13309 /* TQM ring 0 PBL indirect levels. */
13310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
13312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
13313 /* PBL pointer is physical start address. */
13314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
13316 /* PBL pointer points to PTE table. */
13317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
13319 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
13322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
13323 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
13324 /* TQM ring 0 page size. */
13325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
13327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
13329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
13330 (UINT32_C(0x0) << 4)
13332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
13333 (UINT32_C(0x1) << 4)
13335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
13336 (UINT32_C(0x2) << 4)
13338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
13339 (UINT32_C(0x3) << 4)
13341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
13342 (UINT32_C(0x4) << 4)
13344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
13345 (UINT32_C(0x5) << 4)
13346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
13347 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
13348 /* TQM ring 1 page size and level. */
13349 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
13350 /* TQM ring 1 PBL indirect levels. */
13351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
13353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
13354 /* PBL pointer is physical start address. */
13355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
13357 /* PBL pointer points to PTE table. */
13358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
13360 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
13363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
13364 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
13365 /* TQM ring 1 page size. */
13366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
13368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
13370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
13371 (UINT32_C(0x0) << 4)
13373 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
13374 (UINT32_C(0x1) << 4)
13376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
13377 (UINT32_C(0x2) << 4)
13379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
13380 (UINT32_C(0x3) << 4)
13382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
13383 (UINT32_C(0x4) << 4)
13385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
13386 (UINT32_C(0x5) << 4)
13387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
13388 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
13389 /* TQM ring 2 page size and level. */
13390 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
13391 /* TQM ring 2 PBL indirect levels. */
13392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
13394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
13395 /* PBL pointer is physical start address. */
13396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
13398 /* PBL pointer points to PTE table. */
13399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
13401 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
13404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
13405 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
13406 /* TQM ring 2 page size. */
13407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
13409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
13411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
13412 (UINT32_C(0x0) << 4)
13414 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
13415 (UINT32_C(0x1) << 4)
13417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
13418 (UINT32_C(0x2) << 4)
13420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
13421 (UINT32_C(0x3) << 4)
13423 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
13424 (UINT32_C(0x4) << 4)
13426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
13427 (UINT32_C(0x5) << 4)
13428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
13429 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
13430 /* TQM ring 3 page size and level. */
13431 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
13432 /* TQM ring 3 PBL indirect levels. */
13433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
13435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
13436 /* PBL pointer is physical start address. */
13437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
13439 /* PBL pointer points to PTE table. */
13440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
13442 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
13445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
13446 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
13447 /* TQM ring 3 page size. */
13448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
13450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
13452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
13453 (UINT32_C(0x0) << 4)
13455 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
13456 (UINT32_C(0x1) << 4)
13458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
13459 (UINT32_C(0x2) << 4)
13461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
13462 (UINT32_C(0x3) << 4)
13464 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
13465 (UINT32_C(0x4) << 4)
13467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
13468 (UINT32_C(0x5) << 4)
13469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
13470 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
13471 /* TQM ring 4 page size and level. */
13472 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
13473 /* TQM ring 4 PBL indirect levels. */
13474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
13476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
13477 /* PBL pointer is physical start address. */
13478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
13480 /* PBL pointer points to PTE table. */
13481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
13483 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
13486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
13487 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
13488 /* TQM ring 4 page size. */
13489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
13491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
13493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
13494 (UINT32_C(0x0) << 4)
13496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
13497 (UINT32_C(0x1) << 4)
13499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
13500 (UINT32_C(0x2) << 4)
13502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
13503 (UINT32_C(0x3) << 4)
13505 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
13506 (UINT32_C(0x4) << 4)
13508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
13509 (UINT32_C(0x5) << 4)
13510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
13511 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
13512 /* TQM ring 5 page size and level. */
13513 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
13514 /* TQM ring 5 PBL indirect levels. */
13515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
13517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
13518 /* PBL pointer is physical start address. */
13519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
13521 /* PBL pointer points to PTE table. */
13522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
13524 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
13527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
13528 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
13529 /* TQM ring 5 page size. */
13530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
13532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
13534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
13535 (UINT32_C(0x0) << 4)
13537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
13538 (UINT32_C(0x1) << 4)
13540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
13541 (UINT32_C(0x2) << 4)
13543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
13544 (UINT32_C(0x3) << 4)
13546 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
13547 (UINT32_C(0x4) << 4)
13549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
13550 (UINT32_C(0x5) << 4)
13551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
13552 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
13553 /* TQM ring 6 page size and level. */
13554 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
13555 /* TQM ring 6 PBL indirect levels. */
13556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
13558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
13559 /* PBL pointer is physical start address. */
13560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
13562 /* PBL pointer points to PTE table. */
13563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
13565 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
13568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
13569 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
13570 /* TQM ring 6 page size. */
13571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
13573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
13575 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
13576 (UINT32_C(0x0) << 4)
13578 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
13579 (UINT32_C(0x1) << 4)
13581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
13582 (UINT32_C(0x2) << 4)
13584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
13585 (UINT32_C(0x3) << 4)
13587 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
13588 (UINT32_C(0x4) << 4)
13590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
13591 (UINT32_C(0x5) << 4)
13592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
13593 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
13594 /* TQM ring 7 page size and level. */
13595 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
13596 /* TQM ring 7 PBL indirect levels. */
13597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
13599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
13600 /* PBL pointer is physical start address. */
13601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
13603 /* PBL pointer points to PTE table. */
13604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
13606 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
13609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
13610 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
13611 /* TQM ring 7 page size. */
13612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
13614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
13616 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
13617 (UINT32_C(0x0) << 4)
13619 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
13620 (UINT32_C(0x1) << 4)
13622 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
13623 (UINT32_C(0x2) << 4)
13625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
13626 (UINT32_C(0x3) << 4)
13628 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
13629 (UINT32_C(0x4) << 4)
13631 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
13632 (UINT32_C(0x5) << 4)
13633 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
13634 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
13635 /* MR/AV page size and level. */
13636 uint8_t mrav_pg_size_mrav_lvl;
13637 /* MR/AV PBL indirect levels. */
13638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
13640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
13641 /* PBL pointer is physical start address. */
13642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
13644 /* PBL pointer points to PTE table. */
13645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
13647 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
13650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
13651 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
13652 /* MR/AV page size. */
13653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
13655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
13657 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
13658 (UINT32_C(0x0) << 4)
13660 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
13661 (UINT32_C(0x1) << 4)
13663 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
13664 (UINT32_C(0x2) << 4)
13666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
13667 (UINT32_C(0x3) << 4)
13669 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
13670 (UINT32_C(0x4) << 4)
13672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
13673 (UINT32_C(0x5) << 4)
13674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
13675 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
13676 /* Timer page size and level. */
13677 uint8_t tim_pg_size_tim_lvl;
13678 /* Timer PBL indirect levels. */
13679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
13681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
13682 /* PBL pointer is physical start address. */
13683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
13685 /* PBL pointer points to PTE table. */
13686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
13688 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
13691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
13692 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
13693 /* Timer page size. */
13694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
13696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
13698 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
13699 (UINT32_C(0x0) << 4)
13701 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
13702 (UINT32_C(0x1) << 4)
13704 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
13705 (UINT32_C(0x2) << 4)
13707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
13708 (UINT32_C(0x3) << 4)
13710 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
13711 (UINT32_C(0x4) << 4)
13713 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
13714 (UINT32_C(0x5) << 4)
13715 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
13716 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
13717 /* QP page directory. */
13718 uint64_t qpc_page_dir;
13719 /* SRQ page directory. */
13720 uint64_t srq_page_dir;
13721 /* CQ page directory. */
13722 uint64_t cq_page_dir;
13723 /* VNIC page directory. */
13724 uint64_t vnic_page_dir;
13725 /* Stat page directory. */
13726 uint64_t stat_page_dir;
13727 /* TQM slowpath page directory. */
13728 uint64_t tqm_sp_page_dir;
13729 /* TQM ring 0 page directory. */
13730 uint64_t tqm_ring0_page_dir;
13731 /* TQM ring 1 page directory. */
13732 uint64_t tqm_ring1_page_dir;
13733 /* TQM ring 2 page directory. */
13734 uint64_t tqm_ring2_page_dir;
13735 /* TQM ring 3 page directory. */
13736 uint64_t tqm_ring3_page_dir;
13737 /* TQM ring 4 page directory. */
13738 uint64_t tqm_ring4_page_dir;
13739 /* TQM ring 5 page directory. */
13740 uint64_t tqm_ring5_page_dir;
13741 /* TQM ring 6 page directory. */
13742 uint64_t tqm_ring6_page_dir;
13743 /* TQM ring 7 page directory. */
13744 uint64_t tqm_ring7_page_dir;
13745 /* MR/AV page directory. */
13746 uint64_t mrav_page_dir;
13747 /* Timer page directory. */
13748 uint64_t tim_page_dir;
13749 /* Number of entries to reserve for QP1 */
13750 uint16_t qp_num_qp1_entries;
13751 /* Number of entries to reserve for L2 */
13752 uint16_t qp_num_l2_entries;
13753 /* Number of QPs. */
13754 uint32_t qp_num_entries;
13755 /* Number of SRQs. */
13756 uint32_t srq_num_entries;
13757 /* Number of entries to reserve for L2 */
13758 uint16_t srq_num_l2_entries;
13759 /* Number of entries to reserve for L2 */
13760 uint16_t cq_num_l2_entries;
13761 /* Number of CQs. */
13762 uint32_t cq_num_entries;
13763 /* Number of entries to reserve for VNIC entries */
13764 uint16_t vnic_num_vnic_entries;
13765 /* Number of entries to reserve for Ring table entries */
13766 uint16_t vnic_num_ring_table_entries;
13767 /* Number of Stats. */
13768 uint32_t stat_num_entries;
13769 /* Number of TQM slowpath entries. */
13770 uint32_t tqm_sp_num_entries;
13771 /* Number of TQM ring 0 entries. */
13772 uint32_t tqm_ring0_num_entries;
13773 /* Number of TQM ring 1 entries. */
13774 uint32_t tqm_ring1_num_entries;
13775 /* Number of TQM ring 2 entries. */
13776 uint32_t tqm_ring2_num_entries;
13777 /* Number of TQM ring 3 entries. */
13778 uint32_t tqm_ring3_num_entries;
13779 /* Number of TQM ring 4 entries. */
13780 uint32_t tqm_ring4_num_entries;
13781 /* Number of TQM ring 5 entries. */
13782 uint32_t tqm_ring5_num_entries;
13783 /* Number of TQM ring 6 entries. */
13784 uint32_t tqm_ring6_num_entries;
13785 /* Number of TQM ring 7 entries. */
13786 uint32_t tqm_ring7_num_entries;
13788 * If the MR/AV split reservation flag is not set, then this field
13789 * represents the total number of MR plus AV entries. For versions
13790 * of firmware that support the split reservation, when it is not
13791 * specified half of the entries will be reserved for MRs and the
13792 * other half for AVs.
13794 * If the MR/AV split reservation flag is set, then this
13795 * field is logically divided into two 16b fields. Bits `[31:16]`
13796 * represents the `mr_num_entries` and bits `[15:0]` represents
13797 * `av_num_entries`. The granularity of these values is defined by
13798 * the `mrav_num_entries_unit` field returned by the
13799 * `backing_store_qcaps` command.
13801 uint32_t mrav_num_entries;
13802 /* Number of Timer entries. */
13803 uint32_t tim_num_entries;
13804 uint8_t unused_1[7];
13806 * This field is used in Output records to indicate that the output
13807 * is completely written to RAM. This field should be read as 1
13808 * to indicate that the output has been completely written.
13809 * When writing a command completion or response to an internal
13810 * processor, the order of writes has to be such that this field
13816 /****************************
13817 * hwrm_error_recovery_qcfg *
13818 ****************************/
13821 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
13822 struct hwrm_error_recovery_qcfg_input {
13823 /* The HWRM command request type. */
13826 * The completion ring to send the completion event on. This should
13827 * be the NQ ID returned from the `nq_alloc` HWRM command.
13829 uint16_t cmpl_ring;
13831 * The sequence ID is used by the driver for tracking multiple
13832 * commands. This ID is treated as opaque data by the firmware and
13833 * the value is returned in the `hwrm_resp_hdr` upon completion.
13837 * The target ID of the command:
13838 * * 0x0-0xFFF8 - The function ID
13839 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13840 * * 0xFFFD - Reserved for user-space HWRM interface
13843 uint16_t target_id;
13845 * A physical address pointer pointing to a host buffer that the
13846 * command's response data will be written. This can be either a host
13847 * physical address (HPA) or a guest physical address (GPA) and must
13848 * point to a physically contiguous block of memory.
13850 uint64_t resp_addr;
13851 uint8_t unused_0[8];
13854 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
13855 struct hwrm_error_recovery_qcfg_output {
13856 /* The specific error status for the command. */
13857 uint16_t error_code;
13858 /* The HWRM command request type. */
13860 /* The sequence ID from the original command. */
13862 /* The length of the response data in number of bytes. */
13866 * When this flag is set to 1, error recovery will be initiated
13867 * through master function driver.
13869 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
13871 * When this flag is set to 1, error recovery will be performed
13872 * through Co processor.
13874 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
13876 * Driver Polling frequency. This value is in units of 100msec.
13877 * Typical value would be 10 to indicate 1sec.
13878 * Drivers can poll FW health status, Heartbeat, reset_counter with
13881 uint32_t driver_polling_freq;
13883 * This value is in units of 100msec.
13884 * Typical value would be 30 to indicate 3sec.
13885 * Master function wait period from detecting a fatal error to
13886 * initiating reset. In this time period Master PF expects every
13887 * active driver will detect fatal error.
13889 uint32_t master_func_wait_period;
13891 * This value is in units of 100msec.
13892 * Typical value would be 50 to indicate 5sec.
13893 * Normal function wait period from fatal error detection to
13894 * polling FW health status. In this time period, drivers should not
13895 * do any PCIe MMIO transaction and should not send any HWRM commands.
13897 uint32_t normal_func_wait_period;
13899 * This value is in units of 100msec.
13900 * Typical value would be 20 to indicate 2sec.
13901 * This field indicates that, master function wait period after chip
13902 * reset. After this time, master function should reinitialize with
13905 uint32_t master_func_wait_period_after_reset;
13907 * This value is in units of 100msec.
13908 * Typical value would be 60 to indicate 6sec.
13909 * This field is applicable to both master and normal functions.
13910 * Even after chip reset, if FW status not changed to ready,
13911 * then all the functions can poll for this much time and bailout.
13913 uint32_t max_bailout_time_after_reset;
13915 * FW health status register.
13916 * Lower 2 bits indicates address space location and upper 30 bits
13917 * indicates upper 30bits of the register address.
13918 * A value of 0xFFFF-FFFF indicates this register does not exist.
13920 uint32_t fw_health_status_reg;
13921 /* Lower 2 bits indicates address space location. */
13922 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
13924 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
13927 * If value is 0, this register is located in PCIe config space.
13928 * Drivers have to map appropriate window to access this
13931 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
13934 * If value is 1, this register is located in GRC address space.
13935 * Drivers have to map appropriate window to access this
13938 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
13941 * If value is 2, this register is located in first BAR address
13942 * space. Drivers have to map appropriate window to access this
13945 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
13948 * If value is 3, this register is located in second BAR address
13949 * space. Drivers have to map appropriate window to access this
13950 * Drivers have to map appropriate window to access this
13953 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
13955 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
13956 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
13957 /* Upper 30bits of the register address. */
13958 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
13959 UINT32_C(0xfffffffc)
13960 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
13963 * FW HeartBeat register.
13964 * Lower 2 bits indicates address space location and upper 30 bits
13965 * indicates actual address.
13966 * A value of 0xFFFF-FFFF indicates this register does not exist.
13968 uint32_t fw_heartbeat_reg;
13969 /* Lower 2 bits indicates address space location. */
13970 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
13972 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
13975 * If value is 0, this register is located in PCIe config space.
13976 * Drivers have to map appropriate window to access this
13979 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
13982 * If value is 1, this register is located in GRC address space.
13983 * Drivers have to map appropriate window to access this
13986 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
13989 * If value is 2, this register is located in first BAR address
13990 * space. Drivers have to map appropriate window to access this
13993 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
13996 * If value is 3, this register is located in second BAR address
13997 * space. Drivers have to map appropriate window to access this
14000 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
14002 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
14003 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
14004 /* Upper 30bits of the register address. */
14005 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
14006 UINT32_C(0xfffffffc)
14007 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
14010 * FW reset counter.
14011 * Lower 2 bits indicates address space location and upper 30 bits
14012 * indicates actual address.
14013 * A value of 0xFFFF-FFFF indicates this register does not exist.
14015 uint32_t fw_reset_cnt_reg;
14016 /* Lower 2 bits indicates address space location. */
14017 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
14019 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
14022 * If value is 0, this register is located in PCIe config space.
14023 * Drivers have to map appropriate window to access this
14026 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
14029 * If value is 1, this register is located in GRC address space.
14030 * Drivers have to map appropriate window to access this
14033 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
14036 * If value is 2, this register is located in first BAR address
14037 * space. Drivers have to map appropriate window to access this
14040 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
14043 * If value is 3, this register is located in second BAR address
14044 * space. Drivers have to map appropriate window to access this
14047 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
14049 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
14050 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
14051 /* Upper 30bits of the register address. */
14052 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
14053 UINT32_C(0xfffffffc)
14054 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
14057 * Reset Inprogress Register address for PFs.
14058 * Lower 2 bits indicates address space location and upper 30 bits
14059 * indicates actual address.
14060 * A value of 0xFFFF-FFFF indicates this register does not exist.
14062 uint32_t reset_inprogress_reg;
14063 /* Lower 2 bits indicates address space location. */
14064 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
14066 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
14069 * If value is 0, this register is located in PCIe config space.
14070 * Drivers have to map appropriate window to access this
14073 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
14076 * If value is 1, this register is located in GRC address space.
14077 * Drivers have to map appropriate window to access this
14080 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
14083 * If value is 2, this register is located in first BAR address
14084 * space. Drivers have to map appropriate window to access this
14087 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
14090 * If value is 3, this register is located in second BAR address
14091 * space. Drivers have to map appropriate window to access this
14094 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
14096 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
14097 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
14098 /* Upper 30bits of the register address. */
14099 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
14100 UINT32_C(0xfffffffc)
14101 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
14103 /* This field indicates the mask value for reset_inprogress_reg. */
14104 uint32_t reset_inprogress_reg_mask;
14105 uint8_t unused_0[3];
14107 * Array of registers and value count to reset the Chip
14108 * Each array count has reset_reg, reset_reg_val, delay_after_reset
14109 * in TLV format. Depending upon Chip type, number of reset registers
14110 * will vary. Drivers have to write reset_reg_val in the reset_reg
14111 * location in the same sequence in order to recover from a fatal
14114 uint8_t reg_array_cnt;
14117 * Lower 2 bits indicates address space location and upper 30 bits
14118 * indicates actual address.
14119 * A value of 0xFFFF-FFFF indicates this register does not exist.
14121 uint32_t reset_reg[16];
14122 /* Lower 2 bits indicates address space location. */
14123 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
14125 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
14127 * If value is 0, this register is located in PCIe config space.
14128 * Drivers have to map appropriate window to access this
14131 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
14134 * If value is 1, this register is located in GRC address space.
14135 * Drivers have to map appropriate window to access this
14138 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
14141 * If value is 2, this register is located in first BAR address
14142 * space. Drivers have to map appropriate window to access this
14145 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
14148 * If value is 3, this register is located in second BAR address
14149 * space. Drivers have to map appropriate window to access this
14152 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
14154 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
14155 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
14156 /* Upper 30bits of the register address. */
14157 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
14158 UINT32_C(0xfffffffc)
14159 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
14160 /* Value to be written in reset_reg to reset the controller. */
14161 uint32_t reset_reg_val[16];
14163 * This value is in units of 1msec.
14164 * Typical value would be 10 to indicate 10msec.
14165 * Some of the operations like Core reset require delay before
14166 * accessing PCIE MMIO register space.
14167 * If this value is non-zero, drivers have to wait for
14168 * this much time after writing reset_reg_val in reset_reg.
14170 uint8_t delay_after_reset[16];
14172 * Error recovery counter.
14173 * Lower 2 bits indicates address space location and upper 30 bits
14174 * indicates actual address.
14175 * A value of 0xFFFF-FFFF indicates this register does not exist.
14177 uint32_t err_recovery_cnt_reg;
14178 /* Lower 2 bits indicates address space location. */
14179 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
14181 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
14184 * If value is 0, this register is located in PCIe config space.
14185 * Drivers have to map appropriate window to access this
14188 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
14191 * If value is 1, this register is located in GRC address space.
14192 * Drivers have to map appropriate window to access this
14195 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
14198 * If value is 2, this register is located in first BAR address
14199 * space. Drivers have to map appropriate window to access this
14202 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
14205 * If value is 3, this register is located in second BAR address
14206 * space. Drivers have to map appropriate window to access this
14209 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
14211 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
14212 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
14213 /* Upper 30bits of the register address. */
14214 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
14215 UINT32_C(0xfffffffc)
14216 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
14218 uint8_t unused_1[3];
14220 * This field is used in Output records to indicate that the output
14221 * is completely written to RAM. This field should be read as '1'
14222 * to indicate that the output has been completely written.
14223 * When writing a command completion or response to an internal
14224 * processor, the order of writes has to be such that this field
14230 /***********************
14231 * hwrm_func_vlan_qcfg *
14232 ***********************/
14235 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
14236 struct hwrm_func_vlan_qcfg_input {
14237 /* The HWRM command request type. */
14240 * The completion ring to send the completion event on. This should
14241 * be the NQ ID returned from the `nq_alloc` HWRM command.
14243 uint16_t cmpl_ring;
14245 * The sequence ID is used by the driver for tracking multiple
14246 * commands. This ID is treated as opaque data by the firmware and
14247 * the value is returned in the `hwrm_resp_hdr` upon completion.
14251 * The target ID of the command:
14252 * * 0x0-0xFFF8 - The function ID
14253 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14254 * * 0xFFFD - Reserved for user-space HWRM interface
14257 uint16_t target_id;
14259 * A physical address pointer pointing to a host buffer that the
14260 * command's response data will be written. This can be either a host
14261 * physical address (HPA) or a guest physical address (GPA) and must
14262 * point to a physically contiguous block of memory.
14264 uint64_t resp_addr;
14266 * Function ID of the function that is being
14268 * If set to 0xFF... (All Fs), then the configuration is
14269 * for the requesting function.
14272 uint8_t unused_0[6];
14275 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
14276 struct hwrm_func_vlan_qcfg_output {
14277 /* The specific error status for the command. */
14278 uint16_t error_code;
14279 /* The HWRM command request type. */
14281 /* The sequence ID from the original command. */
14283 /* The length of the response data in number of bytes. */
14286 /* S-TAG VLAN identifier configured for the function. */
14288 /* S-TAG PCP value configured for the function. */
14292 * S-TAG TPID value configured for the function. This field is specified in
14293 * network byte order.
14295 uint16_t stag_tpid;
14296 /* C-TAG VLAN identifier configured for the function. */
14298 /* C-TAG PCP value configured for the function. */
14302 * C-TAG TPID value configured for the function. This field is specified in
14303 * network byte order.
14305 uint16_t ctag_tpid;
14310 uint8_t unused_3[3];
14312 * This field is used in Output records to indicate that the output
14313 * is completely written to RAM. This field should be read as '1'
14314 * to indicate that the output has been completely written.
14315 * When writing a command completion or response to an internal processor,
14316 * the order of writes has to be such that this field is written last.
14321 /**********************
14322 * hwrm_func_vlan_cfg *
14323 **********************/
14326 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
14327 struct hwrm_func_vlan_cfg_input {
14328 /* The HWRM command request type. */
14331 * The completion ring to send the completion event on. This should
14332 * be the NQ ID returned from the `nq_alloc` HWRM command.
14334 uint16_t cmpl_ring;
14336 * The sequence ID is used by the driver for tracking multiple
14337 * commands. This ID is treated as opaque data by the firmware and
14338 * the value is returned in the `hwrm_resp_hdr` upon completion.
14342 * The target ID of the command:
14343 * * 0x0-0xFFF8 - The function ID
14344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14345 * * 0xFFFD - Reserved for user-space HWRM interface
14348 uint16_t target_id;
14350 * A physical address pointer pointing to a host buffer that the
14351 * command's response data will be written. This can be either a host
14352 * physical address (HPA) or a guest physical address (GPA) and must
14353 * point to a physically contiguous block of memory.
14355 uint64_t resp_addr;
14357 * Function ID of the function that is being
14359 * If set to 0xFF... (All Fs), then the configuration is
14360 * for the requesting function.
14363 uint8_t unused_0[2];
14366 * This bit must be '1' for the stag_vid field to be
14369 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
14371 * This bit must be '1' for the ctag_vid field to be
14374 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
14376 * This bit must be '1' for the stag_pcp field to be
14379 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
14381 * This bit must be '1' for the ctag_pcp field to be
14384 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
14386 * This bit must be '1' for the stag_tpid field to be
14389 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
14391 * This bit must be '1' for the ctag_tpid field to be
14394 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
14395 /* S-TAG VLAN identifier configured for the function. */
14397 /* S-TAG PCP value configured for the function. */
14401 * S-TAG TPID value configured for the function. This field is specified in
14402 * network byte order.
14404 uint16_t stag_tpid;
14405 /* C-TAG VLAN identifier configured for the function. */
14407 /* C-TAG PCP value configured for the function. */
14411 * C-TAG TPID value configured for the function. This field is specified in
14412 * network byte order.
14414 uint16_t ctag_tpid;
14419 uint8_t unused_3[4];
14422 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
14423 struct hwrm_func_vlan_cfg_output {
14424 /* The specific error status for the command. */
14425 uint16_t error_code;
14426 /* The HWRM command request type. */
14428 /* The sequence ID from the original command. */
14430 /* The length of the response data in number of bytes. */
14432 uint8_t unused_0[7];
14434 * This field is used in Output records to indicate that the output
14435 * is completely written to RAM. This field should be read as '1'
14436 * to indicate that the output has been completely written.
14437 * When writing a command completion or response to an internal processor,
14438 * the order of writes has to be such that this field is written last.
14443 /*******************************
14444 * hwrm_func_vf_vnic_ids_query *
14445 *******************************/
14448 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
14449 struct hwrm_func_vf_vnic_ids_query_input {
14450 /* The HWRM command request type. */
14453 * The completion ring to send the completion event on. This should
14454 * be the NQ ID returned from the `nq_alloc` HWRM command.
14456 uint16_t cmpl_ring;
14458 * The sequence ID is used by the driver for tracking multiple
14459 * commands. This ID is treated as opaque data by the firmware and
14460 * the value is returned in the `hwrm_resp_hdr` upon completion.
14464 * The target ID of the command:
14465 * * 0x0-0xFFF8 - The function ID
14466 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14467 * * 0xFFFD - Reserved for user-space HWRM interface
14470 uint16_t target_id;
14472 * A physical address pointer pointing to a host buffer that the
14473 * command's response data will be written. This can be either a host
14474 * physical address (HPA) or a guest physical address (GPA) and must
14475 * point to a physically contiguous block of memory.
14477 uint64_t resp_addr;
14479 * This value is used to identify a Virtual Function (VF).
14480 * The scope of VF ID is local within a PF.
14483 uint8_t unused_0[2];
14484 /* Max number of vnic ids in vnic id table */
14485 uint32_t max_vnic_id_cnt;
14486 /* This is the address for VF VNIC ID table */
14487 uint64_t vnic_id_tbl_addr;
14490 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
14491 struct hwrm_func_vf_vnic_ids_query_output {
14492 /* The specific error status for the command. */
14493 uint16_t error_code;
14494 /* The HWRM command request type. */
14496 /* The sequence ID from the original command. */
14498 /* The length of the response data in number of bytes. */
14501 * Actual number of vnic ids
14503 * Each VNIC ID is written as a 32-bit number.
14505 uint32_t vnic_id_cnt;
14506 uint8_t unused_0[3];
14508 * This field is used in Output records to indicate that the output
14509 * is completely written to RAM. This field should be read as '1'
14510 * to indicate that the output has been completely written.
14511 * When writing a command completion or response to an internal processor,
14512 * the order of writes has to be such that this field is written last.
14517 /***********************
14518 * hwrm_func_vf_bw_cfg *
14519 ***********************/
14522 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
14523 struct hwrm_func_vf_bw_cfg_input {
14524 /* The HWRM command request type. */
14527 * The completion ring to send the completion event on. This should
14528 * be the NQ ID returned from the `nq_alloc` HWRM command.
14530 uint16_t cmpl_ring;
14532 * The sequence ID is used by the driver for tracking multiple
14533 * commands. This ID is treated as opaque data by the firmware and
14534 * the value is returned in the `hwrm_resp_hdr` upon completion.
14538 * The target ID of the command:
14539 * * 0x0-0xFFF8 - The function ID
14540 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14541 * * 0xFFFD - Reserved for user-space HWRM interface
14544 uint16_t target_id;
14546 * A physical address pointer pointing to a host buffer that the
14547 * command's response data will be written. This can be either a host
14548 * physical address (HPA) or a guest physical address (GPA) and must
14549 * point to a physically contiguous block of memory.
14551 uint64_t resp_addr;
14553 * The number of VF functions that are being configured.
14554 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
14557 uint16_t unused[3];
14558 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14560 /* The physical VF id the adjustment will be made to. */
14561 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14562 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
14564 * This field configures the rate scale percentage of the VF as specified
14565 * by the physical VF id.
14567 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
14568 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
14569 /* 0% of the max tx rate */
14570 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
14571 (UINT32_C(0x0) << 12)
14572 /* 6.66% of the max tx rate */
14573 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
14574 (UINT32_C(0x1) << 12)
14575 /* 13.33% of the max tx rate */
14576 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
14577 (UINT32_C(0x2) << 12)
14578 /* 20% of the max tx rate */
14579 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
14580 (UINT32_C(0x3) << 12)
14581 /* 26.66% of the max tx rate */
14582 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
14583 (UINT32_C(0x4) << 12)
14584 /* 33% of the max tx rate */
14585 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
14586 (UINT32_C(0x5) << 12)
14587 /* 40% of the max tx rate */
14588 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
14589 (UINT32_C(0x6) << 12)
14590 /* 46.66% of the max tx rate */
14591 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
14592 (UINT32_C(0x7) << 12)
14593 /* 53.33% of the max tx rate */
14594 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
14595 (UINT32_C(0x8) << 12)
14596 /* 60% of the max tx rate */
14597 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
14598 (UINT32_C(0x9) << 12)
14599 /* 66.66% of the max tx rate */
14600 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
14601 (UINT32_C(0xa) << 12)
14602 /* 53.33% of the max tx rate */
14603 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
14604 (UINT32_C(0xb) << 12)
14605 /* 80% of the max tx rate */
14606 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
14607 (UINT32_C(0xc) << 12)
14608 /* 86.66% of the max tx rate */
14609 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
14610 (UINT32_C(0xd) << 12)
14611 /* 93.33% of the max tx rate */
14612 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
14613 (UINT32_C(0xe) << 12)
14614 /* 100% of the max tx rate */
14615 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
14616 (UINT32_C(0xf) << 12)
14617 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
14618 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
14621 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
14622 struct hwrm_func_vf_bw_cfg_output {
14623 /* The specific error status for the command. */
14624 uint16_t error_code;
14625 /* The HWRM command request type. */
14627 /* The sequence ID from the original command. */
14629 /* The length of the response data in number of bytes. */
14631 uint8_t unused_0[7];
14633 * This field is used in Output records to indicate that the output
14634 * is completely written to RAM. This field should be read as '1'
14635 * to indicate that the output has been completely written.
14636 * When writing a command completion or response to an internal processor,
14637 * the order of writes has to be such that this field is written last.
14642 /************************
14643 * hwrm_func_vf_bw_qcfg *
14644 ************************/
14647 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
14648 struct hwrm_func_vf_bw_qcfg_input {
14649 /* The HWRM command request type. */
14652 * The completion ring to send the completion event on. This should
14653 * be the NQ ID returned from the `nq_alloc` HWRM command.
14655 uint16_t cmpl_ring;
14657 * The sequence ID is used by the driver for tracking multiple
14658 * commands. This ID is treated as opaque data by the firmware and
14659 * the value is returned in the `hwrm_resp_hdr` upon completion.
14663 * The target ID of the command:
14664 * * 0x0-0xFFF8 - The function ID
14665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14666 * * 0xFFFD - Reserved for user-space HWRM interface
14669 uint16_t target_id;
14671 * A physical address pointer pointing to a host buffer that the
14672 * command's response data will be written. This can be either a host
14673 * physical address (HPA) or a guest physical address (GPA) and must
14674 * point to a physically contiguous block of memory.
14676 uint64_t resp_addr;
14678 * The number of VF functions that are being queried.
14679 * The inline response space allows the host to query up to 50 VFs'
14680 * rate scale percentage
14683 uint16_t unused[3];
14684 /* These 16-bit fields contain the VF fid */
14686 /* The physical VF id of interest */
14687 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14688 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
14691 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
14692 struct hwrm_func_vf_bw_qcfg_output {
14693 /* The specific error status for the command. */
14694 uint16_t error_code;
14695 /* The HWRM command request type. */
14697 /* The sequence ID from the original command. */
14699 /* The length of the response data in number of bytes. */
14702 * The number of VF functions that are being queried.
14703 * The inline response space allows the host to query up to 50 VFs' rate
14707 uint16_t unused[3];
14708 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14710 /* The physical VF id the adjustment will be made to. */
14711 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
14712 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
14714 * This field configures the rate scale percentage of the VF as specified
14715 * by the physical VF id.
14717 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
14718 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
14719 /* 0% of the max tx rate */
14720 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
14721 (UINT32_C(0x0) << 12)
14722 /* 6.66% of the max tx rate */
14723 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
14724 (UINT32_C(0x1) << 12)
14725 /* 13.33% of the max tx rate */
14726 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
14727 (UINT32_C(0x2) << 12)
14728 /* 20% of the max tx rate */
14729 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
14730 (UINT32_C(0x3) << 12)
14731 /* 26.66% of the max tx rate */
14732 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
14733 (UINT32_C(0x4) << 12)
14734 /* 33% of the max tx rate */
14735 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
14736 (UINT32_C(0x5) << 12)
14737 /* 40% of the max tx rate */
14738 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
14739 (UINT32_C(0x6) << 12)
14740 /* 46.66% of the max tx rate */
14741 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
14742 (UINT32_C(0x7) << 12)
14743 /* 53.33% of the max tx rate */
14744 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
14745 (UINT32_C(0x8) << 12)
14746 /* 60% of the max tx rate */
14747 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
14748 (UINT32_C(0x9) << 12)
14749 /* 66.66% of the max tx rate */
14750 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
14751 (UINT32_C(0xa) << 12)
14752 /* 53.33% of the max tx rate */
14753 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
14754 (UINT32_C(0xb) << 12)
14755 /* 80% of the max tx rate */
14756 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
14757 (UINT32_C(0xc) << 12)
14758 /* 86.66% of the max tx rate */
14759 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
14760 (UINT32_C(0xd) << 12)
14761 /* 93.33% of the max tx rate */
14762 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
14763 (UINT32_C(0xe) << 12)
14764 /* 100% of the max tx rate */
14765 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
14766 (UINT32_C(0xf) << 12)
14767 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
14768 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
14769 uint8_t unused_0[7];
14771 * This field is used in Output records to indicate that the output
14772 * is completely written to RAM. This field should be read as '1'
14773 * to indicate that the output has been completely written.
14774 * When writing a command completion or response to an internal processor,
14775 * the order of writes has to be such that this field is written last.
14780 /***************************
14781 * hwrm_func_drv_if_change *
14782 ***************************/
14785 /* hwrm_func_drv_if_change_input (size:192b/24B) */
14786 struct hwrm_func_drv_if_change_input {
14787 /* The HWRM command request type. */
14790 * The completion ring to send the completion event on. This should
14791 * be the NQ ID returned from the `nq_alloc` HWRM command.
14793 uint16_t cmpl_ring;
14795 * The sequence ID is used by the driver for tracking multiple
14796 * commands. This ID is treated as opaque data by the firmware and
14797 * the value is returned in the `hwrm_resp_hdr` upon completion.
14801 * The target ID of the command:
14802 * * 0x0-0xFFF8 - The function ID
14803 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14804 * * 0xFFFD - Reserved for user-space HWRM interface
14807 uint16_t target_id;
14809 * A physical address pointer pointing to a host buffer that the
14810 * command's response data will be written. This can be either a host
14811 * physical address (HPA) or a guest physical address (GPA) and must
14812 * point to a physically contiguous block of memory.
14814 uint64_t resp_addr;
14817 * When this bit is '1', the function driver is indicating
14818 * that the IF state is changing to UP state. The call should
14819 * be made at the beginning of the driver's open call before
14820 * resources are allocated. After making the call, the driver
14821 * should check the response to see if any resources may have
14822 * changed (see the response below). If the driver fails
14823 * the open call, the driver should make this call again with
14824 * this bit cleared to indicate that the IF state is not UP.
14825 * During the driver's close call when the IF state is changing
14826 * to DOWN, the driver should make this call with the bit cleared
14827 * after all resources have been freed.
14829 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
14833 /* hwrm_func_drv_if_change_output (size:128b/16B) */
14834 struct hwrm_func_drv_if_change_output {
14835 /* The specific error status for the command. */
14836 uint16_t error_code;
14837 /* The HWRM command request type. */
14839 /* The sequence ID from the original command. */
14841 /* The length of the response data in number of bytes. */
14845 * When this bit is '1', it indicates that the resources reserved
14846 * for this function may have changed. The driver should check
14847 * resource capabilities and reserve resources again before
14848 * allocating resources.
14850 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
14853 * When this bit is '1', it indicates that the firmware got changed / reset.
14854 * The driver should do complete re-initialization when that bit is set.
14856 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
14858 uint8_t unused_0[3];
14860 * This field is used in Output records to indicate that the output
14861 * is completely written to RAM. This field should be read as '1'
14862 * to indicate that the output has been completely written.
14863 * When writing a command completion or response to an internal processor,
14864 * the order of writes has to be such that this field is written last.
14869 /*******************************
14870 * hwrm_func_host_pf_ids_query *
14871 *******************************/
14874 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
14875 struct hwrm_func_host_pf_ids_query_input {
14876 /* The HWRM command request type. */
14879 * The completion ring to send the completion event on. This should
14880 * be the NQ ID returned from the `nq_alloc` HWRM command.
14882 uint16_t cmpl_ring;
14884 * The sequence ID is used by the driver for tracking multiple
14885 * commands. This ID is treated as opaque data by the firmware and
14886 * the value is returned in the `hwrm_resp_hdr` upon completion.
14890 * The target ID of the command:
14891 * * 0x0-0xFFF8 - The function ID
14892 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14893 * * 0xFFFD - Reserved for user-space HWRM interface
14896 uint16_t target_id;
14898 * A physical address pointer pointing to a host buffer that the
14899 * command's response data will be written. This can be either a host
14900 * physical address (HPA) or a guest physical address (GPA) and must
14901 * point to a physically contiguous block of memory.
14903 uint64_t resp_addr;
14906 * # If this bit is set to '1', the query will contain PF(s)
14907 * belongs to SOC host.
14909 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
14911 * # If this bit is set to '1', the query will contain PF(s)
14912 * belongs to EP0 host.
14914 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
14916 * # If this bit is set to '1', the query will contain PF(s)
14917 * belongs to EP1 host.
14919 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
14921 * # If this bit is set to '1', the query will contain PF(s)
14922 * belongs to EP2 host.
14924 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
14926 * # If this bit is set to '1', the query will contain PF(s)
14927 * belongs to EP3 host.
14929 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
14931 * This provides a filter of what PF(s) will be returned in the
14936 * all available PF(s) belong to the host(s) (defined in the
14937 * host field). This includes the hidden PFs.
14939 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
14941 * all available PF(s) belong to the host(s) (defined in the
14942 * host field) that is available for L2 traffic.
14944 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
14946 * all available PF(s) belong to the host(s) (defined in the
14947 * host field) that is available for ROCE traffic.
14949 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
14950 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
14951 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
14952 uint8_t unused_1[6];
14955 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
14956 struct hwrm_func_host_pf_ids_query_output {
14957 /* The specific error status for the command. */
14958 uint16_t error_code;
14959 /* The HWRM command request type. */
14961 /* The sequence ID from the original command. */
14963 /* The length of the response data in number of bytes. */
14965 /* This provides the first PF ID of the device. */
14966 uint16_t first_pf_id;
14967 uint16_t pf_ordinal_mask;
14969 * When this bit is '1', it indicates first PF belongs to one of
14970 * the hosts defined in the input request.
14972 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
14975 * When this bit is '1', it indicates 2nd PF belongs to one of the
14976 * hosts defined in the input request.
14978 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
14981 * When this bit is '1', it indicates 3rd PF belongs to one of the
14982 * hosts defined in the input request.
14984 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
14987 * When this bit is '1', it indicates 4th PF belongs to one of the
14988 * hosts defined in the input request.
14990 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
14993 * When this bit is '1', it indicates 5th PF belongs to one of the
14994 * hosts defined in the input request.
14996 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
14999 * When this bit is '1', it indicates 6th PF belongs to one of the
15000 * hosts defined in the input request.
15002 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
15005 * When this bit is '1', it indicates 7th PF belongs to one of the
15006 * hosts defined in the input request.
15008 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
15011 * When this bit is '1', it indicates 8th PF belongs to one of the
15012 * hosts defined in the input request.
15014 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
15017 * When this bit is '1', it indicates 9th PF belongs to one of the
15018 * hosts defined in the input request.
15020 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
15023 * When this bit is '1', it indicates 10th PF belongs to one of the
15024 * hosts defined in the input request.
15026 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
15029 * When this bit is '1', it indicates 11th PF belongs to one of the
15030 * hosts defined in the input request.
15032 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
15035 * When this bit is '1', it indicates 12th PF belongs to one of the
15036 * hosts defined in the input request.
15038 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
15041 * When this bit is '1', it indicates 13th PF belongs to one of the
15042 * hosts defined in the input request.
15044 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
15047 * When this bit is '1', it indicates 14th PF belongs to one of the
15048 * hosts defined in the input request.
15050 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
15053 * When this bit is '1', it indicates 15th PF belongs to one of the
15054 * hosts defined in the input request.
15056 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
15059 * When this bit is '1', it indicates 16th PF belongs to one of the
15060 * hosts defined in the input request.
15062 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
15064 uint8_t unused_1[3];
15066 * This field is used in Output records to indicate that the output
15067 * is completely written to RAM. This field should be read as '1'
15068 * to indicate that the output has been completely written.
15069 * When writing a command completion or response to an internal processor,
15070 * the order of writes has to be such that this field is written last.
15075 /*********************
15076 * hwrm_port_phy_cfg *
15077 *********************/
15080 /* hwrm_port_phy_cfg_input (size:448b/56B) */
15081 struct hwrm_port_phy_cfg_input {
15082 /* The HWRM command request type. */
15085 * The completion ring to send the completion event on. This should
15086 * be the NQ ID returned from the `nq_alloc` HWRM command.
15088 uint16_t cmpl_ring;
15090 * The sequence ID is used by the driver for tracking multiple
15091 * commands. This ID is treated as opaque data by the firmware and
15092 * the value is returned in the `hwrm_resp_hdr` upon completion.
15096 * The target ID of the command:
15097 * * 0x0-0xFFF8 - The function ID
15098 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15099 * * 0xFFFD - Reserved for user-space HWRM interface
15102 uint16_t target_id;
15104 * A physical address pointer pointing to a host buffer that the
15105 * command's response data will be written. This can be either a host
15106 * physical address (HPA) or a guest physical address (GPA) and must
15107 * point to a physically contiguous block of memory.
15109 uint64_t resp_addr;
15112 * When this bit is set to '1', the PHY for the port shall
15115 * # If this bit is set to 1, then the HWRM shall reset the
15116 * PHY after applying PHY configuration changes specified
15118 * # In order to guarantee that PHY configuration changes
15119 * specified in this command take effect, the HWRM
15120 * client should set this flag to 1.
15121 * # If this bit is not set to 1, then the HWRM may reset
15122 * the PHY depending on the current PHY configuration and
15123 * settings specified in this command.
15125 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
15127 /* deprecated bit. Do not use!!! */
15128 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
15131 * When this bit is set to '1', the link shall be forced to
15132 * the force_link_speed value.
15134 * When this bit is set to '1', the HWRM client should
15135 * not enable any of the auto negotiation related
15136 * fields represented by auto_XXX fields in this command.
15137 * When this bit is set to '1' and the HWRM client has
15138 * enabled a auto_XXX field in this command, then the
15139 * HWRM shall ignore the enabled auto_XXX field.
15141 * When this bit is set to zero, the link
15142 * shall be allowed to autoneg.
15144 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
15147 * When this bit is set to '1', the auto-negotiation process
15148 * shall be restarted on the link.
15150 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
15153 * When this bit is set to '1', Energy Efficient Ethernet
15154 * (EEE) is requested to be enabled on this link.
15155 * If EEE is not supported on this port, then this flag
15156 * shall be ignored by the HWRM.
15158 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
15161 * When this bit is set to '1', Energy Efficient Ethernet
15162 * (EEE) is requested to be disabled on this link.
15163 * If EEE is not supported on this port, then this flag
15164 * shall be ignored by the HWRM.
15166 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
15169 * When this bit is set to '1' and EEE is enabled on this
15170 * link, then TX LPI is requested to be enabled on the link.
15171 * If EEE is not supported on this port, then this flag
15172 * shall be ignored by the HWRM.
15173 * If EEE is disabled on this port, then this flag shall be
15174 * ignored by the HWRM.
15176 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
15179 * When this bit is set to '1' and EEE is enabled on this
15180 * link, then TX LPI is requested to be disabled on the link.
15181 * If EEE is not supported on this port, then this flag
15182 * shall be ignored by the HWRM.
15183 * If EEE is disabled on this port, then this flag shall be
15184 * ignored by the HWRM.
15186 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
15189 * When set to 1, then the HWRM shall enable FEC autonegotitation
15190 * on this port if supported.
15191 * When set to 0, then this flag shall be ignored.
15192 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15195 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
15198 * When set to 1, then the HWRM shall disable FEC autonegotiation
15199 * on this port if supported.
15200 * When set to 0, then this flag shall be ignored.
15201 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15204 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
15207 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
15208 * on this port if supported.
15209 * When set to 0, then this flag shall be ignored.
15210 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15213 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
15216 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
15217 * on this port if supported.
15218 * When set to 0, then this flag shall be ignored.
15219 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15222 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
15225 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
15226 * on this port if supported.
15227 * When set to 0, then this flag shall be ignored.
15228 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15231 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
15234 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
15235 * on this port if supported.
15236 * When set to 0, then this flag shall be ignored.
15237 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15240 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
15243 * When this bit is set to '1', the link shall be forced to
15246 * # When this bit is set to '1", all other
15247 * command input settings related to the link speed shall
15249 * Once the link state is forced down, it can be
15250 * explicitly cleared from that state by setting this flag
15252 * # If this flag is set to '0', then the link shall be
15253 * cleared from forced down state if the link is in forced
15255 * There may be conditions (e.g. out-of-band or sideband
15256 * configuration changes for the link) outside the scope
15257 * of the HWRM implementation that may clear forced down
15260 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
15264 * This bit must be '1' for the auto_mode field to be
15267 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
15270 * This bit must be '1' for the auto_duplex field to be
15273 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
15276 * This bit must be '1' for the auto_pause field to be
15279 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
15282 * This bit must be '1' for the auto_link_speed field to be
15285 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
15288 * This bit must be '1' for the auto_link_speed_mask field to be
15291 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
15294 * This bit must be '1' for the wirespeed field to be
15297 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
15300 * This bit must be '1' for the lpbk field to be
15303 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
15306 * This bit must be '1' for the preemphasis field to be
15309 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
15312 * This bit must be '1' for the force_pause field to be
15315 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
15318 * This bit must be '1' for the eee_link_speed_mask field to be
15321 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
15324 * This bit must be '1' for the tx_lpi_timer field to be
15327 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
15329 /* Port ID of port that is to be configured. */
15332 * This is the speed that will be used if the force
15333 * bit is '1'. If unsupported speed is selected, an error
15334 * will be generated.
15336 uint16_t force_link_speed;
15337 /* 100Mb link speed */
15338 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15339 /* 1Gb link speed */
15340 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15341 /* 2Gb link speed */
15342 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15343 /* 25Gb link speed */
15344 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15345 /* 10Gb link speed */
15346 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15347 /* 20Mb link speed */
15348 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15349 /* 25Gb link speed */
15350 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15351 /* 40Gb link speed */
15352 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
15353 /* 50Gb link speed */
15354 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
15355 /* 100Gb link speed */
15356 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
15357 /* 200Gb link speed */
15358 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
15359 /* 10Mb link speed */
15360 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
15361 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
15362 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
15364 * This value is used to identify what autoneg mode is
15365 * used when the link speed is not being forced.
15368 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15369 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
15370 /* Select all possible speeds for autoneg mode. */
15371 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15373 * Select only the auto_link_speed speed for autoneg mode. This mode has
15374 * been DEPRECATED. An HWRM client should not use this mode.
15376 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15378 * Select the auto_link_speed or any speed below that speed for autoneg.
15379 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15381 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15383 * Select the speeds based on the corresponding link speed mask value
15384 * that is provided.
15386 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15387 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
15388 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
15390 * This is the duplex setting that will be used if the autoneg_mode
15391 * is "one_speed" or "one_or_below".
15393 uint8_t auto_duplex;
15394 /* Half Duplex will be requested. */
15395 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
15396 /* Full duplex will be requested. */
15397 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
15398 /* Both Half and Full dupex will be requested. */
15399 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
15400 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
15401 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
15403 * This value is used to configure the pause that will be
15404 * used for autonegotiation.
15405 * Add text on the usage of auto_pause and force_pause.
15407 uint8_t auto_pause;
15409 * When this bit is '1', Generation of tx pause messages
15410 * has been requested. Disabled otherwise.
15412 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
15415 * When this bit is '1', Reception of rx pause messages
15416 * has been requested. Disabled otherwise.
15418 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
15421 * When set to 1, the advertisement of pause is enabled.
15423 * # When the auto_mode is not set to none and this flag is
15424 * set to 1, then the auto_pause bits on this port are being
15425 * advertised and autoneg pause results are being interpreted.
15426 * # When the auto_mode is not set to none and this
15427 * flag is set to 0, the pause is forced as indicated in
15428 * force_pause, and also advertised as auto_pause bits, but
15429 * the autoneg results are not interpreted since the pause
15430 * configuration is being forced.
15431 * # When the auto_mode is set to none and this flag is set to
15432 * 1, auto_pause bits should be ignored and should be set to 0.
15434 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
15438 * This is the speed that will be used if the autoneg_mode
15439 * is "one_speed" or "one_or_below". If an unsupported speed
15440 * is selected, an error will be generated.
15442 uint16_t auto_link_speed;
15443 /* 100Mb link speed */
15444 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
15445 /* 1Gb link speed */
15446 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
15447 /* 2Gb link speed */
15448 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
15449 /* 25Gb link speed */
15450 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
15451 /* 10Gb link speed */
15452 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
15453 /* 20Mb link speed */
15454 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
15455 /* 25Gb link speed */
15456 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
15457 /* 40Gb link speed */
15458 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
15459 /* 50Gb link speed */
15460 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
15461 /* 100Gb link speed */
15462 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
15463 /* 200Gb link speed */
15464 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
15465 /* 10Mb link speed */
15466 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
15467 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
15468 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
15470 * This is a mask of link speeds that will be used if
15471 * autoneg_mode is "mask". If unsupported speed is enabled
15472 * an error will be generated.
15474 uint16_t auto_link_speed_mask;
15475 /* 100Mb link speed (Half-duplex) */
15476 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
15478 /* 100Mb link speed (Full-duplex) */
15479 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
15481 /* 1Gb link speed (Half-duplex) */
15482 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
15484 /* 1Gb link speed (Full-duplex) */
15485 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
15487 /* 2Gb link speed */
15488 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
15490 /* 25Gb link speed */
15491 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
15493 /* 10Gb link speed */
15494 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
15496 /* 20Gb link speed */
15497 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
15499 /* 25Gb link speed */
15500 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
15502 /* 40Gb link speed */
15503 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
15505 /* 50Gb link speed */
15506 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
15508 /* 100Gb link speed */
15509 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
15511 /* 10Mb link speed (Half-duplex) */
15512 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
15514 /* 10Mb link speed (Full-duplex) */
15515 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
15517 /* 200Gb link speed */
15518 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
15520 /* This value controls the wirespeed feature. */
15522 /* Wirespeed feature is disabled. */
15523 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
15524 /* Wirespeed feature is enabled. */
15525 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
15526 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
15527 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
15528 /* This value controls the loopback setting for the PHY. */
15530 /* No loopback is selected. Normal operation. */
15531 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
15533 * The HW will be configured with local loopback such that
15534 * host data is sent back to the host without modification.
15536 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
15538 * The HW will be configured with remote loopback such that
15539 * port logic will send packets back out the transmitter that
15542 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
15544 * The HW will be configured with external loopback such that
15545 * host data is sent on the transmitter and based on the external
15546 * loopback connection the data will be received without modification.
15548 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
15549 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
15550 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
15552 * This value is used to configure the pause that will be
15553 * used for force mode.
15555 uint8_t force_pause;
15557 * When this bit is '1', Generation of tx pause messages
15558 * is supported. Disabled otherwise.
15560 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
15562 * When this bit is '1', Reception of rx pause messages
15563 * is supported. Disabled otherwise.
15565 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
15568 * This value controls the pre-emphasis to be used for the
15569 * link. Driver should not set this value (use
15570 * enable.preemphasis = 0) unless driver is sure of setting.
15571 * Normally HWRM FW will determine proper pre-emphasis.
15573 uint32_t preemphasis;
15575 * Setting for link speed mask that is used to
15576 * advertise speeds during autonegotiation when EEE is enabled.
15577 * This field is valid only when EEE is enabled.
15578 * The speeds specified in this field shall be a subset of
15579 * speeds specified in auto_link_speed_mask.
15580 * If EEE is enabled,then at least one speed shall be provided
15583 uint16_t eee_link_speed_mask;
15585 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
15587 /* 100Mb link speed (Full-duplex) */
15588 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
15591 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
15593 /* 1Gb link speed (Full-duplex) */
15594 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
15597 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
15600 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
15602 /* 10Gb link speed */
15603 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
15605 uint8_t unused_2[2];
15607 * Requested setting of TX LPI timer in microseconds.
15608 * This field is valid only when EEE is enabled and TX LPI is
15611 uint32_t tx_lpi_timer;
15612 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
15613 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
15617 /* hwrm_port_phy_cfg_output (size:128b/16B) */
15618 struct hwrm_port_phy_cfg_output {
15619 /* The specific error status for the command. */
15620 uint16_t error_code;
15621 /* The HWRM command request type. */
15623 /* The sequence ID from the original command. */
15625 /* The length of the response data in number of bytes. */
15627 uint8_t unused_0[7];
15629 * This field is used in Output records to indicate that the output
15630 * is completely written to RAM. This field should be read as '1'
15631 * to indicate that the output has been completely written.
15632 * When writing a command completion or response to an internal processor,
15633 * the order of writes has to be such that this field is written last.
15638 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
15639 struct hwrm_port_phy_cfg_cmd_err {
15641 * command specific error codes that goes to
15642 * the cmd_err field in Common HWRM Error Response.
15645 /* Unknown error */
15646 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
15647 /* Unable to complete operation due to invalid speed */
15648 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
15650 * retry the command since the phy is not ready.
15651 * retry count is returned in opaque_0.
15652 * This is only valid for the first command and
15653 * this value will not change for successive calls.
15654 * but if a 0 is returned at any time then this should
15655 * be treated as an un recoverable failure,
15657 * retry interval in milli seconds is returned in opaque_1.
15658 * This specifies the time that user should wait before
15659 * issuing the next port_phy_cfg command.
15661 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
15662 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
15663 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
15664 uint8_t unused_0[7];
15667 /**********************
15668 * hwrm_port_phy_qcfg *
15669 **********************/
15672 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
15673 struct hwrm_port_phy_qcfg_input {
15674 /* The HWRM command request type. */
15677 * The completion ring to send the completion event on. This should
15678 * be the NQ ID returned from the `nq_alloc` HWRM command.
15680 uint16_t cmpl_ring;
15682 * The sequence ID is used by the driver for tracking multiple
15683 * commands. This ID is treated as opaque data by the firmware and
15684 * the value is returned in the `hwrm_resp_hdr` upon completion.
15688 * The target ID of the command:
15689 * * 0x0-0xFFF8 - The function ID
15690 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15691 * * 0xFFFD - Reserved for user-space HWRM interface
15694 uint16_t target_id;
15696 * A physical address pointer pointing to a host buffer that the
15697 * command's response data will be written. This can be either a host
15698 * physical address (HPA) or a guest physical address (GPA) and must
15699 * point to a physically contiguous block of memory.
15701 uint64_t resp_addr;
15702 /* Port ID of port that is to be queried. */
15704 uint8_t unused_0[6];
15707 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
15708 struct hwrm_port_phy_qcfg_output {
15709 /* The specific error status for the command. */
15710 uint16_t error_code;
15711 /* The HWRM command request type. */
15713 /* The sequence ID from the original command. */
15715 /* The length of the response data in number of bytes. */
15717 /* This value indicates the current link status. */
15719 /* There is no link or cable detected. */
15720 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
15721 /* There is no link, but a cable has been detected. */
15722 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
15723 /* There is a link. */
15724 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
15725 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
15726 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
15728 /* This value indicates the current link speed of the connection. */
15729 uint16_t link_speed;
15730 /* 100Mb link speed */
15731 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
15732 /* 1Gb link speed */
15733 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
15734 /* 2Gb link speed */
15735 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
15736 /* 25Gb link speed */
15737 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
15738 /* 10Gb link speed */
15739 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
15740 /* 20Mb link speed */
15741 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
15742 /* 25Gb link speed */
15743 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
15744 /* 40Gb link speed */
15745 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
15746 /* 50Gb link speed */
15747 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
15748 /* 100Gb link speed */
15749 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
15750 /* 200Gb link speed */
15751 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
15752 /* 10Mb link speed */
15753 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
15754 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
15755 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
15757 * This value is indicates the duplex of the current
15760 uint8_t duplex_cfg;
15761 /* Half Duplex connection. */
15762 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
15763 /* Full duplex connection. */
15764 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
15765 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
15766 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
15768 * This value is used to indicate the current
15769 * pause configuration. When autoneg is enabled, this value
15770 * represents the autoneg results of pause configuration.
15774 * When this bit is '1', Generation of tx pause messages
15775 * is supported. Disabled otherwise.
15777 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
15779 * When this bit is '1', Reception of rx pause messages
15780 * is supported. Disabled otherwise.
15782 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
15784 * The supported speeds for the port. This is a bit mask.
15785 * For each speed that is supported, the corrresponding
15786 * bit will be set to '1'.
15788 uint16_t support_speeds;
15789 /* 100Mb link speed (Half-duplex) */
15790 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
15792 /* 100Mb link speed (Full-duplex) */
15793 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
15795 /* 1Gb link speed (Half-duplex) */
15796 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
15798 /* 1Gb link speed (Full-duplex) */
15799 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
15801 /* 2Gb link speed */
15802 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
15804 /* 25Gb link speed */
15805 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
15807 /* 10Gb link speed */
15808 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
15810 /* 20Gb link speed */
15811 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
15813 /* 25Gb link speed */
15814 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
15816 /* 40Gb link speed */
15817 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
15819 /* 50Gb link speed */
15820 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
15822 /* 100Gb link speed */
15823 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
15825 /* 10Mb link speed (Half-duplex) */
15826 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
15828 /* 10Mb link speed (Full-duplex) */
15829 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
15831 /* 200Gb link speed */
15832 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
15835 * Current setting of forced link speed.
15836 * When the link speed is not being forced, this
15837 * value shall be set to 0.
15839 uint16_t force_link_speed;
15840 /* 100Mb link speed */
15841 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15842 /* 1Gb link speed */
15843 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15844 /* 2Gb link speed */
15845 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15846 /* 25Gb link speed */
15847 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15848 /* 10Gb link speed */
15849 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15850 /* 20Mb link speed */
15851 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15852 /* 25Gb link speed */
15853 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15854 /* 40Gb link speed */
15855 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
15857 /* 50Gb link speed */
15858 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
15860 /* 100Gb link speed */
15861 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
15863 /* 200Gb link speed */
15864 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
15866 /* 10Mb link speed */
15867 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
15869 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
15870 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
15871 /* Current setting of auto negotiation mode. */
15873 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15874 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
15875 /* Select all possible speeds for autoneg mode. */
15876 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15878 * Select only the auto_link_speed speed for autoneg mode. This mode has
15879 * been DEPRECATED. An HWRM client should not use this mode.
15881 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15883 * Select the auto_link_speed or any speed below that speed for autoneg.
15884 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15886 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15888 * Select the speeds based on the corresponding link speed mask value
15889 * that is provided.
15891 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15892 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
15893 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
15895 * Current setting of pause autonegotiation.
15896 * Move autoneg_pause flag here.
15898 uint8_t auto_pause;
15900 * When this bit is '1', Generation of tx pause messages
15901 * has been requested. Disabled otherwise.
15903 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
15906 * When this bit is '1', Reception of rx pause messages
15907 * has been requested. Disabled otherwise.
15909 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
15912 * When set to 1, the advertisement of pause is enabled.
15914 * # When the auto_mode is not set to none and this flag is
15915 * set to 1, then the auto_pause bits on this port are being
15916 * advertised and autoneg pause results are being interpreted.
15917 * # When the auto_mode is not set to none and this
15918 * flag is set to 0, the pause is forced as indicated in
15919 * force_pause, and also advertised as auto_pause bits, but
15920 * the autoneg results are not interpreted since the pause
15921 * configuration is being forced.
15922 * # When the auto_mode is set to none and this flag is set to
15923 * 1, auto_pause bits should be ignored and should be set to 0.
15925 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
15928 * Current setting for auto_link_speed. This field is only
15929 * valid when auto_mode is set to "one_speed" or "one_or_below".
15931 uint16_t auto_link_speed;
15932 /* 100Mb link speed */
15933 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
15934 /* 1Gb link speed */
15935 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
15936 /* 2Gb link speed */
15937 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
15938 /* 25Gb link speed */
15939 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
15940 /* 10Gb link speed */
15941 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
15942 /* 20Mb link speed */
15943 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
15944 /* 25Gb link speed */
15945 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
15946 /* 40Gb link speed */
15947 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
15948 /* 50Gb link speed */
15949 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
15950 /* 100Gb link speed */
15951 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
15952 /* 200Gb link speed */
15953 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
15954 /* 10Mb link speed */
15955 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
15957 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
15958 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
15960 * Current setting for auto_link_speed_mask that is used to
15961 * advertise speeds during autonegotiation.
15962 * This field is only valid when auto_mode is set to "mask".
15963 * The speeds specified in this field shall be a subset of
15964 * supported speeds on this port.
15966 uint16_t auto_link_speed_mask;
15967 /* 100Mb link speed (Half-duplex) */
15968 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
15970 /* 100Mb link speed (Full-duplex) */
15971 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
15973 /* 1Gb link speed (Half-duplex) */
15974 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
15976 /* 1Gb link speed (Full-duplex) */
15977 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
15979 /* 2Gb link speed */
15980 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
15982 /* 25Gb link speed */
15983 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
15985 /* 10Gb link speed */
15986 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
15988 /* 20Gb link speed */
15989 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
15991 /* 25Gb link speed */
15992 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
15994 /* 40Gb link speed */
15995 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
15997 /* 50Gb link speed */
15998 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
16000 /* 100Gb link speed */
16001 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
16003 /* 10Mb link speed (Half-duplex) */
16004 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
16006 /* 10Mb link speed (Full-duplex) */
16007 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
16009 /* 200Gb link speed */
16010 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
16012 /* Current setting for wirespeed. */
16014 /* Wirespeed feature is disabled. */
16015 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
16016 /* Wirespeed feature is enabled. */
16017 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
16018 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
16019 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
16020 /* Current setting for loopback. */
16022 /* No loopback is selected. Normal operation. */
16023 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
16025 * The HW will be configured with local loopback such that
16026 * host data is sent back to the host without modification.
16028 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
16030 * The HW will be configured with remote loopback such that
16031 * port logic will send packets back out the transmitter that
16034 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
16036 * The HW will be configured with external loopback such that
16037 * host data is sent on the transmitter and based on the external
16038 * loopback connection the data will be received without modification.
16040 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
16041 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
16042 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
16044 * Current setting of forced pause.
16045 * When the pause configuration is not being forced, then
16046 * this value shall be set to 0.
16048 uint8_t force_pause;
16050 * When this bit is '1', Generation of tx pause messages
16051 * is supported. Disabled otherwise.
16053 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
16055 * When this bit is '1', Reception of rx pause messages
16056 * is supported. Disabled otherwise.
16058 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
16060 * This value indicates the current status of the optics module on
16063 uint8_t module_status;
16064 /* Module is inserted and accepted */
16065 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
16067 /* Module is rejected and transmit side Laser is disabled. */
16068 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
16070 /* Module mismatch warning. */
16071 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
16073 /* Module is rejected and powered down. */
16074 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
16076 /* Module is not inserted. */
16077 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
16079 /* Module is powered down because of over current fault. */
16080 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
16082 /* Module status is not applicable. */
16083 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
16085 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
16086 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
16087 /* Current setting for preemphasis. */
16088 uint32_t preemphasis;
16089 /* This field represents the major version of the PHY. */
16091 /* This field represents the minor version of the PHY. */
16093 /* This field represents the build version of the PHY. */
16095 /* This value represents a PHY type. */
16098 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
16101 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
16103 /* BASE-KR4 (Deprecated) */
16104 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
16107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
16110 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
16112 /* BASE-KR2 (Deprecated) */
16113 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
16116 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
16119 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
16122 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
16124 /* EEE capable BASE-T */
16125 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
16127 /* SGMII connected external PHY */
16128 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
16130 /* 25G_BASECR_CA_L */
16131 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
16133 /* 25G_BASECR_CA_S */
16134 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
16136 /* 25G_BASECR_CA_N */
16137 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
16140 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
16143 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
16146 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
16149 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
16152 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
16154 /* 100G_BASESR10 */
16155 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
16158 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
16161 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
16164 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
16167 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
16169 /* 40G_ACTIVE_CABLE */
16170 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
16173 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
16176 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
16179 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
16182 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
16185 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
16188 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
16191 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
16193 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
16194 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
16195 /* This value represents a media type. */
16196 uint8_t media_type;
16198 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
16200 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
16201 /* Direct Attached Copper */
16202 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
16204 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
16205 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
16206 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
16207 /* This value represents a transceiver type. */
16208 uint8_t xcvr_pkg_type;
16209 /* PHY and MAC are in the same package */
16210 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
16212 /* PHY and MAC are in different packages */
16213 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
16215 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
16216 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
16217 uint8_t eee_config_phy_addr;
16218 /* This field represents PHY address. */
16219 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
16221 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
16223 * This field represents flags related to EEE configuration.
16224 * These EEE configuration flags are valid only when the
16225 * auto_mode is not set to none (in other words autonegotiation
16228 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
16230 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
16232 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
16233 * Speeds for autoneg with EEE mode enabled
16234 * are based on eee_link_speed_mask.
16236 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
16239 * This flag is valid only when eee_enabled is set to 1.
16241 * # If eee_enabled is set to 0, then EEE mode is disabled
16242 * and this flag shall be ignored.
16243 * # If eee_enabled is set to 1 and this flag is set to 1,
16244 * then Energy Efficient Ethernet (EEE) mode is enabled
16246 * # If eee_enabled is set to 1 and this flag is set to 0,
16247 * then Energy Efficient Ethernet (EEE) mode is enabled
16248 * but is currently not in use.
16250 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
16253 * This flag is valid only when eee_enabled is set to 1.
16255 * # If eee_enabled is set to 0, then EEE mode is disabled
16256 * and this flag shall be ignored.
16257 * # If eee_enabled is set to 1 and this flag is set to 1,
16258 * then Energy Efficient Ethernet (EEE) mode is enabled
16259 * and TX LPI is enabled.
16260 * # If eee_enabled is set to 1 and this flag is set to 0,
16261 * then Energy Efficient Ethernet (EEE) mode is enabled
16262 * but TX LPI is disabled.
16264 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
16267 * When set to 1, the parallel detection is used to determine
16268 * the speed of the link partner.
16270 * Parallel detection is used when a autonegotiation capable
16271 * device is connected to a link parter that is not capable
16272 * of autonegotiation.
16274 uint8_t parallel_detect;
16276 * When set to 1, the parallel detection is used to determine
16277 * the speed of the link partner.
16279 * Parallel detection is used when a autonegotiation capable
16280 * device is connected to a link parter that is not capable
16281 * of autonegotiation.
16283 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
16285 * The advertised speeds for the port by the link partner.
16286 * Each advertised speed will be set to '1'.
16288 uint16_t link_partner_adv_speeds;
16289 /* 100Mb link speed (Half-duplex) */
16290 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
16292 /* 100Mb link speed (Full-duplex) */
16293 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
16295 /* 1Gb link speed (Half-duplex) */
16296 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
16298 /* 1Gb link speed (Full-duplex) */
16299 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
16301 /* 2Gb link speed */
16302 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
16304 /* 25Gb link speed */
16305 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
16307 /* 10Gb link speed */
16308 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
16310 /* 20Gb link speed */
16311 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
16313 /* 25Gb link speed */
16314 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
16316 /* 40Gb link speed */
16317 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
16319 /* 50Gb link speed */
16320 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
16322 /* 100Gb link speed */
16323 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
16325 /* 10Mb link speed (Half-duplex) */
16326 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
16328 /* 10Mb link speed (Full-duplex) */
16329 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
16332 * The advertised autoneg for the port by the link partner.
16333 * This field is deprecated and should be set to 0.
16335 uint8_t link_partner_adv_auto_mode;
16336 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16337 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
16339 /* Select all possible speeds for autoneg mode. */
16340 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
16343 * Select only the auto_link_speed speed for autoneg mode. This mode has
16344 * been DEPRECATED. An HWRM client should not use this mode.
16346 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
16349 * Select the auto_link_speed or any speed below that speed for autoneg.
16350 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16352 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
16355 * Select the speeds based on the corresponding link speed mask value
16356 * that is provided.
16358 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
16360 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
16361 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
16362 /* The advertised pause settings on the port by the link partner. */
16363 uint8_t link_partner_adv_pause;
16365 * When this bit is '1', Generation of tx pause messages
16366 * is supported. Disabled otherwise.
16368 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
16371 * When this bit is '1', Reception of rx pause messages
16372 * is supported. Disabled otherwise.
16374 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
16377 * Current setting for link speed mask that is used to
16378 * advertise speeds during autonegotiation when EEE is enabled.
16379 * This field is valid only when eee_enabled flags is set to 1.
16380 * The speeds specified in this field shall be a subset of
16381 * speeds specified in auto_link_speed_mask.
16383 uint16_t adv_eee_link_speed_mask;
16385 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16387 /* 100Mb link speed (Full-duplex) */
16388 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
16391 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16393 /* 1Gb link speed (Full-duplex) */
16394 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
16397 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16400 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16402 /* 10Gb link speed */
16403 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
16406 * Current setting for link speed mask that is advertised by
16407 * the link partner when EEE is enabled.
16408 * This field is valid only when eee_enabled flags is set to 1.
16410 uint16_t link_partner_adv_eee_link_speed_mask;
16412 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16414 /* 100Mb link speed (Full-duplex) */
16415 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
16418 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16420 /* 1Gb link speed (Full-duplex) */
16421 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
16424 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16427 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16429 /* 10Gb link speed */
16430 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
16432 uint32_t xcvr_identifier_type_tx_lpi_timer;
16434 * Current setting of TX LPI timer in microseconds.
16435 * This field is valid only when_eee_enabled flag is set to 1
16436 * and tx_lpi_enabled is set to 1.
16438 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
16440 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
16441 /* This value represents transceiver identifier type. */
16442 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
16443 UINT32_C(0xff000000)
16444 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
16446 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
16447 (UINT32_C(0x0) << 24)
16448 /* SFP/SFP+/SFP28 */
16449 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
16450 (UINT32_C(0x3) << 24)
16452 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
16453 (UINT32_C(0xc) << 24)
16455 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
16456 (UINT32_C(0xd) << 24)
16458 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
16459 (UINT32_C(0x11) << 24)
16460 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
16461 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
16463 * This value represents the current configuration of
16464 * Forward Error Correction (FEC) on the port.
16468 * When set to 1, then FEC is not supported on this port. If this flag
16469 * is set to 1, then all other FEC configuration flags shall be ignored.
16470 * When set to 0, then FEC is supported as indicated by other
16471 * configuration flags.
16472 * If no cable is attached and the HWRM does not yet know the FEC
16473 * capability, then the HWRM shall set this flag to 1 when reporting
16476 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
16479 * When set to 1, then FEC autonegotiation is supported on this port.
16480 * When set to 0, then FEC autonegotiation is not supported on this port.
16482 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
16485 * When set to 1, then FEC autonegotiation is enabled on this port.
16486 * When set to 0, then FEC autonegotiation is disabled if supported.
16487 * This flag should be ignored if FEC autonegotiation is not supported on this port.
16489 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
16492 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
16493 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
16495 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
16498 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
16499 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
16500 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
16502 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
16505 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
16506 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
16508 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
16511 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
16512 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
16513 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
16515 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
16518 * This value is indicates the duplex of the current
16519 * connection state.
16521 uint8_t duplex_state;
16522 /* Half Duplex connection. */
16523 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
16524 /* Full duplex connection. */
16525 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
16526 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
16527 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
16528 /* Option flags fields. */
16529 uint8_t option_flags;
16530 /* When this bit is '1', Media auto detect is enabled. */
16531 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
16534 * Up to 16 bytes of null padded ASCII string representing
16536 * If the string is set to null, then the vendor name is not
16539 char phy_vendor_name[16];
16541 * Up to 16 bytes of null padded ASCII string that
16542 * identifies vendor specific part number of the PHY.
16543 * If the string is set to null, then the vendor specific
16544 * part number is not available.
16546 char phy_vendor_partnumber[16];
16547 uint8_t unused_2[7];
16549 * This field is used in Output records to indicate that the output
16550 * is completely written to RAM. This field should be read as '1'
16551 * to indicate that the output has been completely written.
16552 * When writing a command completion or response to an internal processor,
16553 * the order of writes has to be such that this field is written last.
16558 /*********************
16559 * hwrm_port_mac_cfg *
16560 *********************/
16563 /* hwrm_port_mac_cfg_input (size:384b/48B) */
16564 struct hwrm_port_mac_cfg_input {
16565 /* The HWRM command request type. */
16568 * The completion ring to send the completion event on. This should
16569 * be the NQ ID returned from the `nq_alloc` HWRM command.
16571 uint16_t cmpl_ring;
16573 * The sequence ID is used by the driver for tracking multiple
16574 * commands. This ID is treated as opaque data by the firmware and
16575 * the value is returned in the `hwrm_resp_hdr` upon completion.
16579 * The target ID of the command:
16580 * * 0x0-0xFFF8 - The function ID
16581 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16582 * * 0xFFFD - Reserved for user-space HWRM interface
16585 uint16_t target_id;
16587 * A physical address pointer pointing to a host buffer that the
16588 * command's response data will be written. This can be either a host
16589 * physical address (HPA) or a guest physical address (GPA) and must
16590 * point to a physically contiguous block of memory.
16592 uint64_t resp_addr;
16594 * In this field, there are a number of CoS mappings related flags
16595 * that are used to configure CoS mappings and their corresponding
16596 * priorities in the hardware.
16597 * For the priorities of CoS mappings, the HWRM uses the following
16598 * priority order (high to low) by default:
16601 * # tunnel_vlan_pri
16604 * A subset of CoS mappings can be enabled.
16605 * If a priority is not specified for an enabled CoS mapping, the
16606 * priority will be assigned in the above order for the enabled CoS
16607 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
16608 * enabled and their priorities are not specified, the following
16609 * priority order (high to low) will be used by the HWRM:
16614 * vlan_pri CoS mapping together with default CoS with lower priority
16615 * are enabled by default by the HWRM.
16619 * When this bit is '1', this command will configure
16620 * the MAC to match the current link state of the PHY.
16621 * If the link is not established on the PHY, then this
16622 * bit has no effect.
16624 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
16627 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16628 * is requested to be enabled.
16630 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
16633 * When this bit is set to '1', tunnel VLAN PRI field to
16634 * CoS mapping is requested to be enabled.
16636 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
16639 * When this bit is set to '1', the IP DSCP to CoS mapping is
16640 * requested to be enabled.
16642 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
16645 * When this bit is '1', the HWRM is requested to
16646 * enable timestamp capture capability on the receive side
16649 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
16652 * When this bit is '1', the HWRM is requested to
16653 * disable timestamp capture capability on the receive side
16656 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
16659 * When this bit is '1', the HWRM is requested to
16660 * enable timestamp capture capability on the transmit side
16663 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
16666 * When this bit is '1', the HWRM is requested to
16667 * disable timestamp capture capability on the transmit side
16670 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
16673 * When this bit is '1', the Out-Of-Box WoL is requested to
16674 * be enabled on this port.
16676 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
16679 * When this bit is '1', the Out-Of-Box WoL is requested to
16680 * be disabled on this port.
16682 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
16685 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16686 * is requested to be disabled.
16688 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
16691 * When this bit is set to '1', tunnel VLAN PRI field to
16692 * CoS mapping is requested to be disabled.
16694 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
16697 * When this bit is set to '1', the IP DSCP to CoS mapping is
16698 * requested to be disabled.
16700 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
16703 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
16704 * bit is set, then the device uses one step Tx timestamping.
16705 * This bit is temporary and used for experimental purposes.
16707 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
16711 * This bit must be '1' for the ipg field to be
16714 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
16717 * This bit must be '1' for the lpbk field to be
16720 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
16723 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
16726 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
16729 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
16732 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
16735 * This bit must be '1' for the dscp2cos_map_pri field to be
16738 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
16741 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
16744 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
16747 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
16750 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
16753 * This bit must be '1' for the cos_field_cfg field to be
16756 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
16759 * This bit must be '1' for the ptp_freq_adj_ppb field to be
16762 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
16764 /* Port ID of port that is to be configured. */
16767 * This value is used to configure the minimum IPG that will
16768 * be sent between packets by this port.
16771 /* This value controls the loopback setting for the MAC. */
16773 /* No loopback is selected. Normal operation. */
16774 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
16776 * The HW will be configured with local loopback such that
16777 * host data is sent back to the host without modification.
16779 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
16781 * The HW will be configured with remote loopback such that
16782 * port logic will send packets back out the transmitter that
16785 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
16786 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
16787 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
16789 * This value controls the priority setting of VLAN PRI to CoS
16790 * mapping based on VLAN Tags of inner packet headers of
16791 * tunneled packets or packet headers of non-tunneled packets.
16793 * # Each XXX_pri variable shall have a unique priority value
16794 * when it is being specified.
16795 * # When comparing priorities of mappings, higher value
16796 * indicates higher priority.
16797 * For example, a value of 0-3 is returned where 0 is being
16798 * the lowest priority and 3 is being the highest priority.
16800 uint8_t vlan_pri2cos_map_pri;
16801 /* Reserved field. */
16804 * This value controls the priority setting of VLAN PRI to CoS
16805 * mapping based on VLAN Tags of tunneled header.
16806 * This mapping only applies when tunneled headers
16809 * # Each XXX_pri variable shall have a unique priority value
16810 * when it is being specified.
16811 * # When comparing priorities of mappings, higher value
16812 * indicates higher priority.
16813 * For example, a value of 0-3 is returned where 0 is being
16814 * the lowest priority and 3 is being the highest priority.
16816 uint8_t tunnel_pri2cos_map_pri;
16818 * This value controls the priority setting of IP DSCP to CoS
16819 * mapping based on inner IP header of tunneled packets or
16820 * IP header of non-tunneled packets.
16822 * # Each XXX_pri variable shall have a unique priority value
16823 * when it is being specified.
16824 * # When comparing priorities of mappings, higher value
16825 * indicates higher priority.
16826 * For example, a value of 0-3 is returned where 0 is being
16827 * the lowest priority and 3 is being the highest priority.
16829 uint8_t dscp2pri_map_pri;
16831 * This is a 16-bit bit mask that is used to request a
16832 * specific configuration of time stamp capture of PTP messages
16833 * on the receive side of this port.
16834 * This field shall be ignored if the ptp_rx_ts_capture_enable
16835 * flag is not set in this command.
16836 * Otherwise, if bit 'i' is set, then the HWRM is being
16837 * requested to configure the receive side of the port to
16838 * capture the time stamp of every received PTP message
16839 * with messageType field value set to i.
16841 uint16_t rx_ts_capture_ptp_msg_type;
16843 * This is a 16-bit bit mask that is used to request a
16844 * specific configuration of time stamp capture of PTP messages
16845 * on the transmit side of this port.
16846 * This field shall be ignored if the ptp_tx_ts_capture_enable
16847 * flag is not set in this command.
16848 * Otherwise, if bit 'i' is set, then the HWRM is being
16849 * requested to configure the transmit side of the port to
16850 * capture the time stamp of every transmitted PTP message
16851 * with messageType field value set to i.
16853 uint16_t tx_ts_capture_ptp_msg_type;
16854 /* Configuration of CoS fields. */
16855 uint8_t cos_field_cfg;
16857 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
16860 * This field is used to specify selection of VLAN PRI value
16861 * based on whether one or two VLAN Tags are present in
16862 * the inner packet headers of tunneled packets or
16863 * non-tunneled packets.
16864 * This field is valid only if inner VLAN PRI to CoS mapping
16866 * If VLAN PRI to CoS mapping is not enabled, then this
16867 * field shall be ignored.
16869 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
16871 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
16874 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
16875 * present in the inner packet headers
16877 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
16878 (UINT32_C(0x0) << 1)
16880 * Select outer VLAN Tag PRI when 2 VLAN Tags are
16881 * present in the inner packet headers.
16882 * No VLAN PRI shall be selected for this configuration
16883 * if only one VLAN Tag is present in the inner
16886 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
16887 (UINT32_C(0x1) << 1)
16889 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
16890 * are present in the inner packet headers
16892 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
16893 (UINT32_C(0x2) << 1)
16895 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
16896 (UINT32_C(0x3) << 1)
16897 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
16898 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
16900 * This field is used to specify selection of tunnel VLAN
16901 * PRI value based on whether one or two VLAN Tags are
16902 * present in tunnel headers.
16903 * This field is valid only if tunnel VLAN PRI to CoS mapping
16905 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
16906 * field shall be ignored.
16908 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
16910 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
16913 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
16914 * present in the tunnel packet headers
16916 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
16917 (UINT32_C(0x0) << 3)
16919 * Select outer VLAN Tag PRI when 2 VLAN Tags are
16920 * present in the tunnel packet headers.
16921 * No tunnel VLAN PRI shall be selected for this
16922 * configuration if only one VLAN Tag is present in
16923 * the tunnel packet headers.
16925 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
16926 (UINT32_C(0x1) << 3)
16928 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
16929 * are present in the tunnel packet headers
16931 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
16932 (UINT32_C(0x2) << 3)
16934 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
16935 (UINT32_C(0x3) << 3)
16936 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
16937 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
16939 * This field shall be used to provide default CoS value
16940 * that has been configured on this port.
16941 * This field is valid only if default CoS mapping
16943 * If default CoS mapping is not enabled, then this
16944 * field shall be ignored.
16946 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
16948 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
16950 uint8_t unused_0[3];
16952 * This signed field specifies by how much to adjust the frequency
16953 * of sync timer updates (measured in parts per billion).
16955 int32_t ptp_freq_adj_ppb;
16956 uint8_t unused_1[4];
16959 /* hwrm_port_mac_cfg_output (size:128b/16B) */
16960 struct hwrm_port_mac_cfg_output {
16961 /* The specific error status for the command. */
16962 uint16_t error_code;
16963 /* The HWRM command request type. */
16965 /* The sequence ID from the original command. */
16967 /* The length of the response data in number of bytes. */
16970 * This is the configured maximum length of Ethernet packet
16971 * payload that is allowed to be received on the port.
16972 * This value does not include the number of bytes used by
16973 * Ethernet header and trailer (CRC).
16977 * This is the configured maximum length of Ethernet packet
16978 * payload that is allowed to be transmitted on the port.
16979 * This value does not include the number of bytes used by
16980 * Ethernet header and trailer (CRC).
16983 /* Current configuration of the IPG value. */
16985 /* Current value of the loopback value. */
16987 /* No loopback is selected. Normal operation. */
16988 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
16990 * The HW will be configured with local loopback such that
16991 * host data is sent back to the host without modification.
16993 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
16995 * The HW will be configured with remote loopback such that
16996 * port logic will send packets back out the transmitter that
16999 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17000 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
17001 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
17004 * This field is used in Output records to indicate that the output
17005 * is completely written to RAM. This field should be read as '1'
17006 * to indicate that the output has been completely written.
17007 * When writing a command completion or response to an internal processor,
17008 * the order of writes has to be such that this field is written last.
17013 /**********************
17014 * hwrm_port_mac_qcfg *
17015 **********************/
17018 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
17019 struct hwrm_port_mac_qcfg_input {
17020 /* The HWRM command request type. */
17023 * The completion ring to send the completion event on. This should
17024 * be the NQ ID returned from the `nq_alloc` HWRM command.
17026 uint16_t cmpl_ring;
17028 * The sequence ID is used by the driver for tracking multiple
17029 * commands. This ID is treated as opaque data by the firmware and
17030 * the value is returned in the `hwrm_resp_hdr` upon completion.
17034 * The target ID of the command:
17035 * * 0x0-0xFFF8 - The function ID
17036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17037 * * 0xFFFD - Reserved for user-space HWRM interface
17040 uint16_t target_id;
17042 * A physical address pointer pointing to a host buffer that the
17043 * command's response data will be written. This can be either a host
17044 * physical address (HPA) or a guest physical address (GPA) and must
17045 * point to a physically contiguous block of memory.
17047 uint64_t resp_addr;
17048 /* Port ID of port that is to be configured. */
17050 uint8_t unused_0[6];
17053 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
17054 struct hwrm_port_mac_qcfg_output {
17055 /* The specific error status for the command. */
17056 uint16_t error_code;
17057 /* The HWRM command request type. */
17059 /* The sequence ID from the original command. */
17061 /* The length of the response data in number of bytes. */
17064 * This is the configured maximum length of Ethernet packet
17065 * payload that is allowed to be received on the port.
17066 * This value does not include the number of bytes used by the
17067 * Ethernet header and trailer (CRC).
17071 * This is the configured maximum length of Ethernet packet
17072 * payload that is allowed to be transmitted on the port.
17073 * This value does not include the number of bytes used by the
17074 * Ethernet header and trailer (CRC).
17078 * The minimum IPG that will
17079 * be sent between packets by this port.
17082 /* The loopback setting for the MAC. */
17084 /* No loopback is selected. Normal operation. */
17085 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17087 * The HW will be configured with local loopback such that
17088 * host data is sent back to the host without modification.
17090 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17092 * The HW will be configured with remote loopback such that
17093 * port logic will send packets back out the transmitter that
17096 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17097 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
17098 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
17100 * Priority setting for VLAN PRI to CoS mapping.
17101 * # Each XXX_pri variable shall have a unique priority value
17102 * when it is being used.
17103 * # When comparing priorities of mappings, higher value
17104 * indicates higher priority.
17105 * For example, a value of 0-3 is returned where 0 is being
17106 * the lowest priority and 3 is being the highest priority.
17107 * # If the correspoding CoS mapping is not enabled, then this
17108 * field should be ignored.
17109 * # This value indicates the normalized priority value retained
17112 uint8_t vlan_pri2cos_map_pri;
17114 * In this field, a number of CoS mappings related flags
17115 * are used to indicate configured CoS mappings.
17119 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
17122 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
17125 * When this bit is set to '1', tunnel VLAN PRI field to
17126 * CoS mapping is enabled.
17128 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
17131 * When this bit is set to '1', the IP DSCP to CoS mapping is
17134 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
17137 * When this bit is '1', the Out-Of-Box WoL is enabled on this
17140 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
17142 /* When this bit is '1', PTP is enabled for RX on this port. */
17143 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
17145 /* When this bit is '1', PTP is enabled for TX on this port. */
17146 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
17149 * Priority setting for tunnel VLAN PRI to CoS mapping.
17150 * # Each XXX_pri variable shall have a unique priority value
17151 * when it is being used.
17152 * # When comparing priorities of mappings, higher value
17153 * indicates higher priority.
17154 * For example, a value of 0-3 is returned where 0 is being
17155 * the lowest priority and 3 is being the highest priority.
17156 * # If the correspoding CoS mapping is not enabled, then this
17157 * field should be ignored.
17158 * # This value indicates the normalized priority value retained
17161 uint8_t tunnel_pri2cos_map_pri;
17163 * Priority setting for DSCP to PRI mapping.
17164 * # Each XXX_pri variable shall have a unique priority value
17165 * when it is being used.
17166 * # When comparing priorities of mappings, higher value
17167 * indicates higher priority.
17168 * For example, a value of 0-3 is returned where 0 is being
17169 * the lowest priority and 3 is being the highest priority.
17170 * # If the correspoding CoS mapping is not enabled, then this
17171 * field should be ignored.
17172 * # This value indicates the normalized priority value retained
17175 uint8_t dscp2pri_map_pri;
17177 * This is a 16-bit bit mask that represents the
17178 * current configuration of time stamp capture of PTP messages
17179 * on the receive side of this port.
17180 * If bit 'i' is set, then the receive side of the port
17181 * is configured to capture the time stamp of every
17182 * received PTP message with messageType field value set
17184 * If all bits are set to 0 (i.e. field value set 0),
17185 * then the receive side of the port is not configured
17186 * to capture timestamp for PTP messages.
17187 * If all bits are set to 1, then the receive side of the
17188 * port is configured to capture timestamp for all PTP
17191 uint16_t rx_ts_capture_ptp_msg_type;
17193 * This is a 16-bit bit mask that represents the
17194 * current configuration of time stamp capture of PTP messages
17195 * on the transmit side of this port.
17196 * If bit 'i' is set, then the transmit side of the port
17197 * is configured to capture the time stamp of every
17198 * received PTP message with messageType field value set
17200 * If all bits are set to 0 (i.e. field value set 0),
17201 * then the transmit side of the port is not configured
17202 * to capture timestamp for PTP messages.
17203 * If all bits are set to 1, then the transmit side of the
17204 * port is configured to capture timestamp for all PTP
17207 uint16_t tx_ts_capture_ptp_msg_type;
17208 /* Configuration of CoS fields. */
17209 uint8_t cos_field_cfg;
17211 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
17214 * This field is used for selecting VLAN PRI value
17215 * based on whether one or two VLAN Tags are present in
17216 * the inner packet headers of tunneled packets or
17217 * non-tunneled packets.
17219 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17221 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17224 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17225 * present in the inner packet headers
17227 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17228 (UINT32_C(0x0) << 1)
17230 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17231 * present in the inner packet headers.
17232 * No VLAN PRI is selected for this configuration
17233 * if only one VLAN Tag is present in the inner
17236 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17237 (UINT32_C(0x1) << 1)
17239 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17240 * are present in the inner packet headers
17242 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17243 (UINT32_C(0x2) << 1)
17245 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17246 (UINT32_C(0x3) << 1)
17247 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17248 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17250 * This field is used for selecting tunnel VLAN PRI value
17251 * based on whether one or two VLAN Tags are present in
17252 * the tunnel headers of tunneled packets. This selection
17253 * does not apply to non-tunneled packets.
17255 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17257 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17260 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17261 * present in the tunnel packet headers
17263 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17264 (UINT32_C(0x0) << 3)
17266 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17267 * present in the tunnel packet headers.
17268 * No VLAN PRI is selected for this configuration
17269 * if only one VLAN Tag is present in the tunnel
17272 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17273 (UINT32_C(0x1) << 3)
17275 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17276 * are present in the tunnel packet headers
17278 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17279 (UINT32_C(0x2) << 3)
17281 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17282 (UINT32_C(0x3) << 3)
17283 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17284 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17286 * This field is used to provide default CoS value that
17287 * has been configured on this port.
17289 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17291 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17294 uint16_t port_svif_info;
17296 * This field specifies the source virtual interface of the port being
17297 * queried. Drivers can use this to program port svif field in the
17300 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
17302 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
17303 /* This field specifies whether port_svif is valid or not */
17304 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
17306 uint8_t unused_2[5];
17308 * This field is used in Output records to indicate that the output
17309 * is completely written to RAM. This field should be read as '1'
17310 * to indicate that the output has been completely written.
17311 * When writing a command completion or response to an internal processor,
17312 * the order of writes has to be such that this field is written last.
17317 /**************************
17318 * hwrm_port_mac_ptp_qcfg *
17319 **************************/
17322 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
17323 struct hwrm_port_mac_ptp_qcfg_input {
17324 /* The HWRM command request type. */
17327 * The completion ring to send the completion event on. This should
17328 * be the NQ ID returned from the `nq_alloc` HWRM command.
17330 uint16_t cmpl_ring;
17332 * The sequence ID is used by the driver for tracking multiple
17333 * commands. This ID is treated as opaque data by the firmware and
17334 * the value is returned in the `hwrm_resp_hdr` upon completion.
17338 * The target ID of the command:
17339 * * 0x0-0xFFF8 - The function ID
17340 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17341 * * 0xFFFD - Reserved for user-space HWRM interface
17344 uint16_t target_id;
17346 * A physical address pointer pointing to a host buffer that the
17347 * command's response data will be written. This can be either a host
17348 * physical address (HPA) or a guest physical address (GPA) and must
17349 * point to a physically contiguous block of memory.
17351 uint64_t resp_addr;
17352 /* Port ID of port that is being queried. */
17354 uint8_t unused_0[6];
17357 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
17358 struct hwrm_port_mac_ptp_qcfg_output {
17359 /* The specific error status for the command. */
17360 uint16_t error_code;
17361 /* The HWRM command request type. */
17363 /* The sequence ID from the original command. */
17365 /* The length of the response data in number of bytes. */
17368 * In this field, a number of PTP related flags
17369 * are used to indicate configured PTP capabilities.
17373 * When this bit is set to '1', the PTP related registers are
17374 * directly accessible by the host.
17376 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
17379 * When this bit is set to '1', the device supports one-step
17382 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
17385 * When this bit is set to '1', the PTP information is accessible
17386 * via HWRM commands.
17388 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
17390 uint8_t unused_0[3];
17391 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
17392 uint32_t rx_ts_reg_off_lower;
17393 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
17394 uint32_t rx_ts_reg_off_upper;
17395 /* Offset of the PTP register for the sequence ID for RX. */
17396 uint32_t rx_ts_reg_off_seq_id;
17397 /* Offset of the first PTP source ID for RX. */
17398 uint32_t rx_ts_reg_off_src_id_0;
17399 /* Offset of the second PTP source ID for RX. */
17400 uint32_t rx_ts_reg_off_src_id_1;
17401 /* Offset of the third PTP source ID for RX. */
17402 uint32_t rx_ts_reg_off_src_id_2;
17403 /* Offset of the domain ID for RX. */
17404 uint32_t rx_ts_reg_off_domain_id;
17405 /* Offset of the PTP FIFO register for RX. */
17406 uint32_t rx_ts_reg_off_fifo;
17407 /* Offset of the PTP advance FIFO register for RX. */
17408 uint32_t rx_ts_reg_off_fifo_adv;
17409 /* PTP timestamp granularity for RX. */
17410 uint32_t rx_ts_reg_off_granularity;
17411 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
17412 uint32_t tx_ts_reg_off_lower;
17413 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
17414 uint32_t tx_ts_reg_off_upper;
17415 /* Offset of the PTP register for the sequence ID for TX. */
17416 uint32_t tx_ts_reg_off_seq_id;
17417 /* Offset of the PTP FIFO register for TX. */
17418 uint32_t tx_ts_reg_off_fifo;
17419 /* PTP timestamp granularity for TX. */
17420 uint32_t tx_ts_reg_off_granularity;
17421 uint8_t unused_1[7];
17423 * This field is used in Output records to indicate that the output
17424 * is completely written to RAM. This field should be read as '1'
17425 * to indicate that the output has been completely written.
17426 * When writing a command completion or response to an internal processor,
17427 * the order of writes has to be such that this field is written last.
17432 /* Port Tx Statistics Format */
17433 /* tx_port_stats (size:3264b/408B) */
17434 struct tx_port_stats {
17435 /* Total Number of 64 Bytes frames transmitted */
17436 uint64_t tx_64b_frames;
17437 /* Total Number of 65-127 Bytes frames transmitted */
17438 uint64_t tx_65b_127b_frames;
17439 /* Total Number of 128-255 Bytes frames transmitted */
17440 uint64_t tx_128b_255b_frames;
17441 /* Total Number of 256-511 Bytes frames transmitted */
17442 uint64_t tx_256b_511b_frames;
17443 /* Total Number of 512-1023 Bytes frames transmitted */
17444 uint64_t tx_512b_1023b_frames;
17445 /* Total Number of 1024-1518 Bytes frames transmitted */
17446 uint64_t tx_1024b_1518b_frames;
17448 * Total Number of each good VLAN (exludes FCS errors)
17449 * frame transmitted which is 1519 to 1522 bytes in length
17450 * inclusive (excluding framing bits but including FCS bytes).
17452 uint64_t tx_good_vlan_frames;
17453 /* Total Number of 1519-2047 Bytes frames transmitted */
17454 uint64_t tx_1519b_2047b_frames;
17455 /* Total Number of 2048-4095 Bytes frames transmitted */
17456 uint64_t tx_2048b_4095b_frames;
17457 /* Total Number of 4096-9216 Bytes frames transmitted */
17458 uint64_t tx_4096b_9216b_frames;
17459 /* Total Number of 9217-16383 Bytes frames transmitted */
17460 uint64_t tx_9217b_16383b_frames;
17461 /* Total Number of good frames transmitted */
17462 uint64_t tx_good_frames;
17463 /* Total Number of frames transmitted */
17464 uint64_t tx_total_frames;
17465 /* Total number of unicast frames transmitted */
17466 uint64_t tx_ucast_frames;
17467 /* Total number of multicast frames transmitted */
17468 uint64_t tx_mcast_frames;
17469 /* Total number of broadcast frames transmitted */
17470 uint64_t tx_bcast_frames;
17471 /* Total number of PAUSE control frames transmitted */
17472 uint64_t tx_pause_frames;
17474 * Total number of PFC/per-priority PAUSE
17475 * control frames transmitted
17477 uint64_t tx_pfc_frames;
17478 /* Total number of jabber frames transmitted */
17479 uint64_t tx_jabber_frames;
17480 /* Total number of frames transmitted with FCS error */
17481 uint64_t tx_fcs_err_frames;
17482 /* Total number of control frames transmitted */
17483 uint64_t tx_control_frames;
17484 /* Total number of over-sized frames transmitted */
17485 uint64_t tx_oversz_frames;
17486 /* Total number of frames with single deferral */
17487 uint64_t tx_single_dfrl_frames;
17488 /* Total number of frames with multiple deferrals */
17489 uint64_t tx_multi_dfrl_frames;
17490 /* Total number of frames with single collision */
17491 uint64_t tx_single_coll_frames;
17492 /* Total number of frames with multiple collisions */
17493 uint64_t tx_multi_coll_frames;
17494 /* Total number of frames with late collisions */
17495 uint64_t tx_late_coll_frames;
17496 /* Total number of frames with excessive collisions */
17497 uint64_t tx_excessive_coll_frames;
17498 /* Total number of fragmented frames transmitted */
17499 uint64_t tx_frag_frames;
17500 /* Total number of transmit errors */
17502 /* Total number of single VLAN tagged frames transmitted */
17503 uint64_t tx_tagged_frames;
17504 /* Total number of double VLAN tagged frames transmitted */
17505 uint64_t tx_dbl_tagged_frames;
17506 /* Total number of runt frames transmitted */
17507 uint64_t tx_runt_frames;
17508 /* Total number of TX FIFO under runs */
17509 uint64_t tx_fifo_underruns;
17511 * Total number of PFC frames with PFC enabled bit for
17512 * Pri 0 transmitted
17514 uint64_t tx_pfc_ena_frames_pri0;
17516 * Total number of PFC frames with PFC enabled bit for
17517 * Pri 1 transmitted
17519 uint64_t tx_pfc_ena_frames_pri1;
17521 * Total number of PFC frames with PFC enabled bit for
17522 * Pri 2 transmitted
17524 uint64_t tx_pfc_ena_frames_pri2;
17526 * Total number of PFC frames with PFC enabled bit for
17527 * Pri 3 transmitted
17529 uint64_t tx_pfc_ena_frames_pri3;
17531 * Total number of PFC frames with PFC enabled bit for
17532 * Pri 4 transmitted
17534 uint64_t tx_pfc_ena_frames_pri4;
17536 * Total number of PFC frames with PFC enabled bit for
17537 * Pri 5 transmitted
17539 uint64_t tx_pfc_ena_frames_pri5;
17541 * Total number of PFC frames with PFC enabled bit for
17542 * Pri 6 transmitted
17544 uint64_t tx_pfc_ena_frames_pri6;
17546 * Total number of PFC frames with PFC enabled bit for
17547 * Pri 7 transmitted
17549 uint64_t tx_pfc_ena_frames_pri7;
17550 /* Total number of EEE LPI Events on TX */
17551 uint64_t tx_eee_lpi_events;
17552 /* EEE LPI Duration Counter on TX */
17553 uint64_t tx_eee_lpi_duration;
17555 * Total number of Link Level Flow Control (LLFC) messages
17558 uint64_t tx_llfc_logical_msgs;
17559 /* Total number of HCFC messages transmitted */
17560 uint64_t tx_hcfc_msgs;
17561 /* Total number of TX collisions */
17562 uint64_t tx_total_collisions;
17563 /* Total number of transmitted bytes */
17565 /* Total number of end-to-end HOL frames */
17566 uint64_t tx_xthol_frames;
17567 /* Total Tx Drops per Port reported by STATS block */
17568 uint64_t tx_stat_discard;
17569 /* Total Tx Error Drops per Port reported by STATS block */
17570 uint64_t tx_stat_error;
17573 /* Port Rx Statistics Format */
17574 /* rx_port_stats (size:4224b/528B) */
17575 struct rx_port_stats {
17576 /* Total Number of 64 Bytes frames received */
17577 uint64_t rx_64b_frames;
17578 /* Total Number of 65-127 Bytes frames received */
17579 uint64_t rx_65b_127b_frames;
17580 /* Total Number of 128-255 Bytes frames received */
17581 uint64_t rx_128b_255b_frames;
17582 /* Total Number of 256-511 Bytes frames received */
17583 uint64_t rx_256b_511b_frames;
17584 /* Total Number of 512-1023 Bytes frames received */
17585 uint64_t rx_512b_1023b_frames;
17586 /* Total Number of 1024-1518 Bytes frames received */
17587 uint64_t rx_1024b_1518b_frames;
17589 * Total Number of each good VLAN (exludes FCS errors)
17590 * frame received which is 1519 to 1522 bytes in length
17591 * inclusive (excluding framing bits but including FCS bytes).
17593 uint64_t rx_good_vlan_frames;
17594 /* Total Number of 1519-2047 Bytes frames received */
17595 uint64_t rx_1519b_2047b_frames;
17596 /* Total Number of 2048-4095 Bytes frames received */
17597 uint64_t rx_2048b_4095b_frames;
17598 /* Total Number of 4096-9216 Bytes frames received */
17599 uint64_t rx_4096b_9216b_frames;
17600 /* Total Number of 9217-16383 Bytes frames received */
17601 uint64_t rx_9217b_16383b_frames;
17602 /* Total number of frames received */
17603 uint64_t rx_total_frames;
17604 /* Total number of unicast frames received */
17605 uint64_t rx_ucast_frames;
17606 /* Total number of multicast frames received */
17607 uint64_t rx_mcast_frames;
17608 /* Total number of broadcast frames received */
17609 uint64_t rx_bcast_frames;
17610 /* Total number of received frames with FCS error */
17611 uint64_t rx_fcs_err_frames;
17612 /* Total number of control frames received */
17613 uint64_t rx_ctrl_frames;
17614 /* Total number of PAUSE frames received */
17615 uint64_t rx_pause_frames;
17616 /* Total number of PFC frames received */
17617 uint64_t rx_pfc_frames;
17619 * Total number of frames received with an unsupported
17622 uint64_t rx_unsupported_opcode_frames;
17624 * Total number of frames received with an unsupported
17625 * DA for pause and PFC
17627 uint64_t rx_unsupported_da_pausepfc_frames;
17628 /* Total number of frames received with an unsupported SA */
17629 uint64_t rx_wrong_sa_frames;
17630 /* Total number of received packets with alignment error */
17631 uint64_t rx_align_err_frames;
17632 /* Total number of received frames with out-of-range length */
17633 uint64_t rx_oor_len_frames;
17634 /* Total number of received frames with error termination */
17635 uint64_t rx_code_err_frames;
17637 * Total number of received frames with a false carrier is
17638 * detected during idle, as defined by RX_ER samples active
17639 * and RXD is 0xE. The event is reported along with the
17640 * statistics generated on the next received frame. Only
17641 * one false carrier condition can be detected and logged
17644 * Carrier event, valid for 10M/100M speed modes only.
17646 uint64_t rx_false_carrier_frames;
17647 /* Total number of over-sized frames received */
17648 uint64_t rx_ovrsz_frames;
17649 /* Total number of jabber packets received */
17650 uint64_t rx_jbr_frames;
17651 /* Total number of received frames with MTU error */
17652 uint64_t rx_mtu_err_frames;
17653 /* Total number of received frames with CRC match */
17654 uint64_t rx_match_crc_frames;
17655 /* Total number of frames received promiscuously */
17656 uint64_t rx_promiscuous_frames;
17658 * Total number of received frames with one or two VLAN
17661 uint64_t rx_tagged_frames;
17662 /* Total number of received frames with two VLAN tags */
17663 uint64_t rx_double_tagged_frames;
17664 /* Total number of truncated frames received */
17665 uint64_t rx_trunc_frames;
17666 /* Total number of good frames (without errors) received */
17667 uint64_t rx_good_frames;
17669 * Total number of received PFC frames with transition from
17670 * XON to XOFF on Pri 0
17672 uint64_t rx_pfc_xon2xoff_frames_pri0;
17674 * Total number of received PFC frames with transition from
17675 * XON to XOFF on Pri 1
17677 uint64_t rx_pfc_xon2xoff_frames_pri1;
17679 * Total number of received PFC frames with transition from
17680 * XON to XOFF on Pri 2
17682 uint64_t rx_pfc_xon2xoff_frames_pri2;
17684 * Total number of received PFC frames with transition from
17685 * XON to XOFF on Pri 3
17687 uint64_t rx_pfc_xon2xoff_frames_pri3;
17689 * Total number of received PFC frames with transition from
17690 * XON to XOFF on Pri 4
17692 uint64_t rx_pfc_xon2xoff_frames_pri4;
17694 * Total number of received PFC frames with transition from
17695 * XON to XOFF on Pri 5
17697 uint64_t rx_pfc_xon2xoff_frames_pri5;
17699 * Total number of received PFC frames with transition from
17700 * XON to XOFF on Pri 6
17702 uint64_t rx_pfc_xon2xoff_frames_pri6;
17704 * Total number of received PFC frames with transition from
17705 * XON to XOFF on Pri 7
17707 uint64_t rx_pfc_xon2xoff_frames_pri7;
17709 * Total number of received PFC frames with PFC enabled
17712 uint64_t rx_pfc_ena_frames_pri0;
17714 * Total number of received PFC frames with PFC enabled
17717 uint64_t rx_pfc_ena_frames_pri1;
17719 * Total number of received PFC frames with PFC enabled
17722 uint64_t rx_pfc_ena_frames_pri2;
17724 * Total number of received PFC frames with PFC enabled
17727 uint64_t rx_pfc_ena_frames_pri3;
17729 * Total number of received PFC frames with PFC enabled
17732 uint64_t rx_pfc_ena_frames_pri4;
17734 * Total number of received PFC frames with PFC enabled
17737 uint64_t rx_pfc_ena_frames_pri5;
17739 * Total number of received PFC frames with PFC enabled
17742 uint64_t rx_pfc_ena_frames_pri6;
17744 * Total number of received PFC frames with PFC enabled
17747 uint64_t rx_pfc_ena_frames_pri7;
17748 /* Total Number of frames received with SCH CRC error */
17749 uint64_t rx_sch_crc_err_frames;
17750 /* Total Number of under-sized frames received */
17751 uint64_t rx_undrsz_frames;
17752 /* Total Number of fragmented frames received */
17753 uint64_t rx_frag_frames;
17754 /* Total number of RX EEE LPI Events */
17755 uint64_t rx_eee_lpi_events;
17756 /* EEE LPI Duration Counter on RX */
17757 uint64_t rx_eee_lpi_duration;
17759 * Total number of physical type Link Level Flow Control
17760 * (LLFC) messages received
17762 uint64_t rx_llfc_physical_msgs;
17764 * Total number of logical type Link Level Flow Control
17765 * (LLFC) messages received
17767 uint64_t rx_llfc_logical_msgs;
17769 * Total number of logical type Link Level Flow Control
17770 * (LLFC) messages received with CRC error
17772 uint64_t rx_llfc_msgs_with_crc_err;
17773 /* Total number of HCFC messages received */
17774 uint64_t rx_hcfc_msgs;
17775 /* Total number of HCFC messages received with CRC error */
17776 uint64_t rx_hcfc_msgs_with_crc_err;
17777 /* Total number of received bytes */
17779 /* Total number of bytes received in runt frames */
17780 uint64_t rx_runt_bytes;
17781 /* Total number of runt frames received */
17782 uint64_t rx_runt_frames;
17783 /* Total Rx Discards per Port reported by STATS block */
17784 uint64_t rx_stat_discard;
17785 uint64_t rx_stat_err;
17788 /********************
17789 * hwrm_port_qstats *
17790 ********************/
17793 /* hwrm_port_qstats_input (size:320b/40B) */
17794 struct hwrm_port_qstats_input {
17795 /* The HWRM command request type. */
17798 * The completion ring to send the completion event on. This should
17799 * be the NQ ID returned from the `nq_alloc` HWRM command.
17801 uint16_t cmpl_ring;
17803 * The sequence ID is used by the driver for tracking multiple
17804 * commands. This ID is treated as opaque data by the firmware and
17805 * the value is returned in the `hwrm_resp_hdr` upon completion.
17809 * The target ID of the command:
17810 * * 0x0-0xFFF8 - The function ID
17811 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17812 * * 0xFFFD - Reserved for user-space HWRM interface
17815 uint16_t target_id;
17817 * A physical address pointer pointing to a host buffer that the
17818 * command's response data will be written. This can be either a host
17819 * physical address (HPA) or a guest physical address (GPA) and must
17820 * point to a physically contiguous block of memory.
17822 uint64_t resp_addr;
17823 /* Port ID of port that is being queried. */
17826 /* This value is not used to avoid backward compatibility issues. */
17827 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
17829 * This bit is set to 1 when request is for a counter mask,
17830 * representing the width of each of the stats counters, rather
17831 * than counters themselves.
17833 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
17834 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
17835 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
17836 uint8_t unused_0[5];
17838 * This is the host address where
17839 * Tx port statistics will be stored
17841 uint64_t tx_stat_host_addr;
17843 * This is the host address where
17844 * Rx port statistics will be stored
17846 uint64_t rx_stat_host_addr;
17849 /* hwrm_port_qstats_output (size:128b/16B) */
17850 struct hwrm_port_qstats_output {
17851 /* The specific error status for the command. */
17852 uint16_t error_code;
17853 /* The HWRM command request type. */
17855 /* The sequence ID from the original command. */
17857 /* The length of the response data in number of bytes. */
17859 /* The size of TX port statistics block in bytes. */
17860 uint16_t tx_stat_size;
17861 /* The size of RX port statistics block in bytes. */
17862 uint16_t rx_stat_size;
17863 uint8_t unused_0[3];
17865 * This field is used in Output records to indicate that the output
17866 * is completely written to RAM. This field should be read as '1'
17867 * to indicate that the output has been completely written.
17868 * When writing a command completion or response to an internal processor,
17869 * the order of writes has to be such that this field is written last.
17874 /* Port Tx Statistics extended Format */
17875 /* tx_port_stats_ext (size:2048b/256B) */
17876 struct tx_port_stats_ext {
17877 /* Total number of tx bytes count on cos queue 0 */
17878 uint64_t tx_bytes_cos0;
17879 /* Total number of tx bytes count on cos queue 1 */
17880 uint64_t tx_bytes_cos1;
17881 /* Total number of tx bytes count on cos queue 2 */
17882 uint64_t tx_bytes_cos2;
17883 /* Total number of tx bytes count on cos queue 3 */
17884 uint64_t tx_bytes_cos3;
17885 /* Total number of tx bytes count on cos queue 4 */
17886 uint64_t tx_bytes_cos4;
17887 /* Total number of tx bytes count on cos queue 5 */
17888 uint64_t tx_bytes_cos5;
17889 /* Total number of tx bytes count on cos queue 6 */
17890 uint64_t tx_bytes_cos6;
17891 /* Total number of tx bytes count on cos queue 7 */
17892 uint64_t tx_bytes_cos7;
17893 /* Total number of tx packets count on cos queue 0 */
17894 uint64_t tx_packets_cos0;
17895 /* Total number of tx packets count on cos queue 1 */
17896 uint64_t tx_packets_cos1;
17897 /* Total number of tx packets count on cos queue 2 */
17898 uint64_t tx_packets_cos2;
17899 /* Total number of tx packets count on cos queue 3 */
17900 uint64_t tx_packets_cos3;
17901 /* Total number of tx packets count on cos queue 4 */
17902 uint64_t tx_packets_cos4;
17903 /* Total number of tx packets count on cos queue 5 */
17904 uint64_t tx_packets_cos5;
17905 /* Total number of tx packets count on cos queue 6 */
17906 uint64_t tx_packets_cos6;
17907 /* Total number of tx packets count on cos queue 7 */
17908 uint64_t tx_packets_cos7;
17909 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
17910 uint64_t pfc_pri0_tx_duration_us;
17911 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
17912 uint64_t pfc_pri0_tx_transitions;
17913 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
17914 uint64_t pfc_pri1_tx_duration_us;
17915 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
17916 uint64_t pfc_pri1_tx_transitions;
17917 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
17918 uint64_t pfc_pri2_tx_duration_us;
17919 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
17920 uint64_t pfc_pri2_tx_transitions;
17921 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
17922 uint64_t pfc_pri3_tx_duration_us;
17923 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
17924 uint64_t pfc_pri3_tx_transitions;
17925 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
17926 uint64_t pfc_pri4_tx_duration_us;
17927 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
17928 uint64_t pfc_pri4_tx_transitions;
17929 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
17930 uint64_t pfc_pri5_tx_duration_us;
17931 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
17932 uint64_t pfc_pri5_tx_transitions;
17933 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
17934 uint64_t pfc_pri6_tx_duration_us;
17935 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
17936 uint64_t pfc_pri6_tx_transitions;
17937 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
17938 uint64_t pfc_pri7_tx_duration_us;
17939 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
17940 uint64_t pfc_pri7_tx_transitions;
17943 /* Port Rx Statistics extended Format */
17944 /* rx_port_stats_ext (size:3648b/456B) */
17945 struct rx_port_stats_ext {
17946 /* Number of times link state changed to down */
17947 uint64_t link_down_events;
17948 /* Number of times the idle rings with pause bit are found */
17949 uint64_t continuous_pause_events;
17950 /* Number of times the active rings pause bit resumed back */
17951 uint64_t resume_pause_events;
17952 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
17953 uint64_t continuous_roce_pause_events;
17954 /* Number of times, the ROCE cos queue PFC is enabled back */
17955 uint64_t resume_roce_pause_events;
17956 /* Total number of rx bytes count on cos queue 0 */
17957 uint64_t rx_bytes_cos0;
17958 /* Total number of rx bytes count on cos queue 1 */
17959 uint64_t rx_bytes_cos1;
17960 /* Total number of rx bytes count on cos queue 2 */
17961 uint64_t rx_bytes_cos2;
17962 /* Total number of rx bytes count on cos queue 3 */
17963 uint64_t rx_bytes_cos3;
17964 /* Total number of rx bytes count on cos queue 4 */
17965 uint64_t rx_bytes_cos4;
17966 /* Total number of rx bytes count on cos queue 5 */
17967 uint64_t rx_bytes_cos5;
17968 /* Total number of rx bytes count on cos queue 6 */
17969 uint64_t rx_bytes_cos6;
17970 /* Total number of rx bytes count on cos queue 7 */
17971 uint64_t rx_bytes_cos7;
17972 /* Total number of rx packets count on cos queue 0 */
17973 uint64_t rx_packets_cos0;
17974 /* Total number of rx packets count on cos queue 1 */
17975 uint64_t rx_packets_cos1;
17976 /* Total number of rx packets count on cos queue 2 */
17977 uint64_t rx_packets_cos2;
17978 /* Total number of rx packets count on cos queue 3 */
17979 uint64_t rx_packets_cos3;
17980 /* Total number of rx packets count on cos queue 4 */
17981 uint64_t rx_packets_cos4;
17982 /* Total number of rx packets count on cos queue 5 */
17983 uint64_t rx_packets_cos5;
17984 /* Total number of rx packets count on cos queue 6 */
17985 uint64_t rx_packets_cos6;
17986 /* Total number of rx packets count on cos queue 7 */
17987 uint64_t rx_packets_cos7;
17988 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
17989 uint64_t pfc_pri0_rx_duration_us;
17990 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
17991 uint64_t pfc_pri0_rx_transitions;
17992 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
17993 uint64_t pfc_pri1_rx_duration_us;
17994 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
17995 uint64_t pfc_pri1_rx_transitions;
17996 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
17997 uint64_t pfc_pri2_rx_duration_us;
17998 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
17999 uint64_t pfc_pri2_rx_transitions;
18000 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18001 uint64_t pfc_pri3_rx_duration_us;
18002 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18003 uint64_t pfc_pri3_rx_transitions;
18004 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18005 uint64_t pfc_pri4_rx_duration_us;
18006 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18007 uint64_t pfc_pri4_rx_transitions;
18008 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18009 uint64_t pfc_pri5_rx_duration_us;
18010 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18011 uint64_t pfc_pri5_rx_transitions;
18012 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18013 uint64_t pfc_pri6_rx_duration_us;
18014 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18015 uint64_t pfc_pri6_rx_transitions;
18016 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18017 uint64_t pfc_pri7_rx_duration_us;
18018 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18019 uint64_t pfc_pri7_rx_transitions;
18020 /* Total number of received bits */
18022 /* The number of events where the port receive buffer was over 85% full */
18023 uint64_t rx_buffer_passed_threshold;
18025 * The number of symbol errors that wasn't corrected by FEC correction
18028 uint64_t rx_pcs_symbol_err;
18029 /* The number of corrected bits on the port according to active FEC */
18030 uint64_t rx_corrected_bits;
18031 /* Total number of rx discard bytes count on cos queue 0 */
18032 uint64_t rx_discard_bytes_cos0;
18033 /* Total number of rx discard bytes count on cos queue 1 */
18034 uint64_t rx_discard_bytes_cos1;
18035 /* Total number of rx discard bytes count on cos queue 2 */
18036 uint64_t rx_discard_bytes_cos2;
18037 /* Total number of rx discard bytes count on cos queue 3 */
18038 uint64_t rx_discard_bytes_cos3;
18039 /* Total number of rx discard bytes count on cos queue 4 */
18040 uint64_t rx_discard_bytes_cos4;
18041 /* Total number of rx discard bytes count on cos queue 5 */
18042 uint64_t rx_discard_bytes_cos5;
18043 /* Total number of rx discard bytes count on cos queue 6 */
18044 uint64_t rx_discard_bytes_cos6;
18045 /* Total number of rx discard bytes count on cos queue 7 */
18046 uint64_t rx_discard_bytes_cos7;
18047 /* Total number of rx discard packets count on cos queue 0 */
18048 uint64_t rx_discard_packets_cos0;
18049 /* Total number of rx discard packets count on cos queue 1 */
18050 uint64_t rx_discard_packets_cos1;
18051 /* Total number of rx discard packets count on cos queue 2 */
18052 uint64_t rx_discard_packets_cos2;
18053 /* Total number of rx discard packets count on cos queue 3 */
18054 uint64_t rx_discard_packets_cos3;
18055 /* Total number of rx discard packets count on cos queue 4 */
18056 uint64_t rx_discard_packets_cos4;
18057 /* Total number of rx discard packets count on cos queue 5 */
18058 uint64_t rx_discard_packets_cos5;
18059 /* Total number of rx discard packets count on cos queue 6 */
18060 uint64_t rx_discard_packets_cos6;
18061 /* Total number of rx discard packets count on cos queue 7 */
18062 uint64_t rx_discard_packets_cos7;
18066 * Port Rx Statistics extended PFC WatchDog Format.
18067 * StormDetect and StormRevert event determination is based
18068 * on an integration period and a percentage threshold.
18069 * StormDetect event - when percentage of XOFF frames received
18070 * within an integration period exceeds the configured threshold.
18071 * StormRevert event - when percentage of XON frames received
18072 * within an integration period exceeds the configured threshold.
18073 * Actual number of XOFF/XON frames for the events to be triggered
18074 * depends on both configured integration period and sampling rate.
18075 * The statistics in this structure represent counts of specified
18076 * events from the moment the feature (PFC WatchDog) is enabled via
18077 * hwrm_queue_pfc_enable_cfg call.
18079 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
18080 struct rx_port_stats_ext_pfc_wd {
18082 * Total number of PFC WatchDog StormDetect events detected
18085 uint64_t rx_pfc_watchdog_storms_detected_pri0;
18087 * Total number of PFC WatchDog StormDetect events detected
18090 uint64_t rx_pfc_watchdog_storms_detected_pri1;
18092 * Total number of PFC WatchDog StormDetect events detected
18095 uint64_t rx_pfc_watchdog_storms_detected_pri2;
18097 * Total number of PFC WatchDog StormDetect events detected
18100 uint64_t rx_pfc_watchdog_storms_detected_pri3;
18102 * Total number of PFC WatchDog StormDetect events detected
18105 uint64_t rx_pfc_watchdog_storms_detected_pri4;
18107 * Total number of PFC WatchDog StormDetect events detected
18110 uint64_t rx_pfc_watchdog_storms_detected_pri5;
18112 * Total number of PFC WatchDog StormDetect events detected
18115 uint64_t rx_pfc_watchdog_storms_detected_pri6;
18117 * Total number of PFC WatchDog StormDetect events detected
18120 uint64_t rx_pfc_watchdog_storms_detected_pri7;
18122 * Total number of PFC WatchDog StormRevert events detected
18125 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
18127 * Total number of PFC WatchDog StormRevert events detected
18130 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
18132 * Total number of PFC WatchDog StormRevert events detected
18135 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
18137 * Total number of PFC WatchDog StormRevert events detected
18140 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
18142 * Total number of PFC WatchDog StormRevert events detected
18145 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
18147 * Total number of PFC WatchDog StormRevert events detected
18150 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
18152 * Total number of PFC WatchDog StormRevert events detected
18155 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
18157 * Total number of PFC WatchDog StormRevert events detected
18160 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
18162 * Total number of packets received during PFC watchdog storm
18165 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
18167 * Total number of packets received during PFC watchdog storm
18170 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
18172 * Total number of packets received during PFC watchdog storm
18175 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
18177 * Total number of packets received during PFC watchdog storm
18180 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
18182 * Total number of packets received during PFC watchdog storm
18185 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
18187 * Total number of packets received during PFC watchdog storm
18190 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
18192 * Total number of packets received during PFC watchdog storm
18195 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
18197 * Total number of packets received during PFC watchdog storm
18200 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
18202 * Total number of bytes received during PFC watchdog storm
18205 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
18207 * Total number of bytes received during PFC watchdog storm
18210 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
18212 * Total number of bytes received during PFC watchdog storm
18215 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
18217 * Total number of bytes received during PFC watchdog storm
18220 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
18222 * Total number of bytes received during PFC watchdog storm
18225 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
18227 * Total number of bytes received during PFC watchdog storm
18230 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
18232 * Total number of bytes received during PFC watchdog storm
18235 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
18237 * Total number of bytes received during PFC watchdog storm
18240 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
18242 * Total number of packets dropped on rx during PFC watchdog storm
18245 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
18247 * Total number of packets dropped on rx during PFC watchdog storm
18250 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
18252 * Total number of packets dropped on rx during PFC watchdog storm
18255 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
18257 * Total number of packets dropped on rx during PFC watchdog storm
18260 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
18262 * Total number of packets dropped on rx during PFC watchdog storm
18265 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
18267 * Total number of packets dropped on rx during PFC watchdog storm
18270 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
18272 * Total number of packets dropped on rx during PFC watchdog storm
18275 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
18277 * Total number of packets dropped on rx during PFC watchdog storm
18280 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
18282 * Total number of bytes dropped on rx during PFC watchdog storm
18285 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
18287 * Total number of bytes dropped on rx during PFC watchdog storm
18290 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
18292 * Total number of bytes dropped on rx during PFC watchdog storm
18295 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
18297 * Total number of bytes dropped on rx during PFC watchdog storm
18300 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
18302 * Total number of bytes dropped on rx during PFC watchdog storm
18305 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
18307 * Total number of bytes dropped on rx during PFC watchdog storm
18310 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
18312 * Total number of bytes dropped on rx during PFC watchdog storm
18315 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
18317 * Total number of bytes dropped on rx during PFC watchdog storm
18320 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
18322 * Number of packets received during last PFC watchdog storm
18325 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
18327 * Number of packets received during last PFC watchdog storm
18330 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
18332 * Number of packets received during last PFC watchdog storm
18335 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
18337 * Number of packets received during last PFC watchdog storm
18340 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
18342 * Number of packets received during last PFC watchdog storm
18345 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
18347 * Number of packets received during last PFC watchdog storm
18350 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
18352 * Number of packets received during last PFC watchdog storm
18355 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
18357 * Number of packets received during last PFC watchdog storm
18360 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
18362 * Number of bytes received during last PFC watchdog storm
18365 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
18367 * Number of bytes received during last PFC watchdog storm
18370 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
18372 * Number of bytes received during last PFC watchdog storm
18375 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
18377 * Number of bytes received during last PFC watchdog storm
18380 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
18382 * Number of bytes received during last PFC watchdog storm
18385 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
18387 * Number of bytes received during last PFC watchdog storm
18390 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
18392 * Number of bytes received during last PFC watchdog storm
18395 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
18397 * Number of bytes received during last PFC watchdog storm
18400 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
18402 * Number of packets dropped on rx during last PFC watchdog storm
18405 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
18407 * Number of packets dropped on rx during last PFC watchdog storm
18410 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
18412 * Number of packets dropped on rx during last PFC watchdog storm
18415 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
18417 * Number of packets dropped on rx during last PFC watchdog storm
18420 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
18422 * Number of packets dropped on rx during last PFC watchdog storm
18425 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
18427 * Number of packets dropped on rx during last PFC watchdog storm
18430 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
18432 * Number of packets dropped on rx during last PFC watchdog storm
18435 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
18437 * Number of packets dropped on rx during last PFC watchdog storm
18440 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
18442 * Total number of bytes dropped on rx during PFC watchdog storm
18445 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
18447 * Number of bytes dropped on rx during last PFC watchdog storm
18450 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
18452 * Number of bytes dropped on rx during last PFC watchdog storm
18455 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
18457 * Number of bytes dropped on rx during last PFC watchdog storm
18460 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
18462 * Number of bytes dropped on rx during last PFC watchdog storm
18465 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
18467 * Number of bytes dropped on rx during last PFC watchdog storm
18470 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
18472 * Number of bytes dropped on rx during last PFC watchdog storm
18475 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
18477 * Number of bytes dropped on rx during last PFC watchdog storm
18480 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
18483 /************************
18484 * hwrm_port_qstats_ext *
18485 ************************/
18488 /* hwrm_port_qstats_ext_input (size:320b/40B) */
18489 struct hwrm_port_qstats_ext_input {
18490 /* The HWRM command request type. */
18493 * The completion ring to send the completion event on. This should
18494 * be the NQ ID returned from the `nq_alloc` HWRM command.
18496 uint16_t cmpl_ring;
18498 * The sequence ID is used by the driver for tracking multiple
18499 * commands. This ID is treated as opaque data by the firmware and
18500 * the value is returned in the `hwrm_resp_hdr` upon completion.
18504 * The target ID of the command:
18505 * * 0x0-0xFFF8 - The function ID
18506 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18507 * * 0xFFFD - Reserved for user-space HWRM interface
18510 uint16_t target_id;
18512 * A physical address pointer pointing to a host buffer that the
18513 * command's response data will be written. This can be either a host
18514 * physical address (HPA) or a guest physical address (GPA) and must
18515 * point to a physically contiguous block of memory.
18517 uint64_t resp_addr;
18518 /* Port ID of port that is being queried. */
18521 * The size of TX port extended
18522 * statistics block in bytes.
18524 uint16_t tx_stat_size;
18526 * The size of RX port extended
18527 * statistics block in bytes
18529 uint16_t rx_stat_size;
18531 /* This value is not used to avoid backward compatibility issues. */
18532 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18534 * This bit is set to 1 when request is for the counter mask,
18535 * representing width of each of the stats counters, rather than
18536 * counters themselves.
18538 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18539 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
18540 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
18543 * This is the host address where
18544 * Tx port statistics will be stored
18546 uint64_t tx_stat_host_addr;
18548 * This is the host address where
18549 * Rx port statistics will be stored
18551 uint64_t rx_stat_host_addr;
18554 /* hwrm_port_qstats_ext_output (size:128b/16B) */
18555 struct hwrm_port_qstats_ext_output {
18556 /* The specific error status for the command. */
18557 uint16_t error_code;
18558 /* The HWRM command request type. */
18560 /* The sequence ID from the original command. */
18562 /* The length of the response data in number of bytes. */
18564 /* The size of TX port statistics block in bytes. */
18565 uint16_t tx_stat_size;
18566 /* The size of RX port statistics block in bytes. */
18567 uint16_t rx_stat_size;
18568 /* Total number of active cos queues available. */
18569 uint16_t total_active_cos_queues;
18572 * If set to 1, then this field indicates that clear
18573 * roce specific counters is supported.
18575 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
18578 * This field is used in Output records to indicate that the output
18579 * is completely written to RAM. This field should be read as '1'
18580 * to indicate that the output has been completely written.
18581 * When writing a command completion or response to an internal processor,
18582 * the order of writes has to be such that this field is written last.
18587 /*******************************
18588 * hwrm_port_qstats_ext_pfc_wd *
18589 *******************************/
18592 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
18593 struct hwrm_port_qstats_ext_pfc_wd_input {
18594 /* The HWRM command request type. */
18597 * The completion ring to send the completion event on. This should
18598 * be the NQ ID returned from the `nq_alloc` HWRM command.
18600 uint16_t cmpl_ring;
18602 * The sequence ID is used by the driver for tracking multiple
18603 * commands. This ID is treated as opaque data by the firmware and
18604 * the value is returned in the `hwrm_resp_hdr` upon completion.
18608 * The target ID of the command:
18609 * * 0x0-0xFFF8 - The function ID
18610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18611 * * 0xFFFD - Reserved for user-space HWRM interface
18614 uint16_t target_id;
18616 * A physical address pointer pointing to a host buffer that the
18617 * command's response data will be written. This can be either a host
18618 * physical address (HPA) or a guest physical address (GPA) and must
18619 * point to a physically contiguous block of memory.
18621 uint64_t resp_addr;
18622 /* Port ID of port that is being queried. */
18625 * The size of rx_port_stats_ext_pfc_wd
18628 uint16_t pfc_wd_stat_size;
18629 uint8_t unused_0[4];
18631 * This is the host address where
18632 * rx_port_stats_ext_pfc_wd will be stored
18634 uint64_t pfc_wd_stat_host_addr;
18637 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
18638 struct hwrm_port_qstats_ext_pfc_wd_output {
18639 /* The specific error status for the command. */
18640 uint16_t error_code;
18641 /* The HWRM command request type. */
18643 /* The sequence ID from the original command. */
18645 /* The length of the response data in number of bytes. */
18648 * The size of rx_port_stats_ext_pfc_wd
18649 * statistics block in bytes.
18651 uint16_t pfc_wd_stat_size;
18654 * This field is used in Output records to indicate that the output
18655 * is completely written to RAM. This field should be read as '1'
18656 * to indicate that the output has been completely written.
18657 * When writing a command completion or response to an internal processor,
18658 * the order of writes has to be such that this field is written last.
18661 uint8_t unused_0[4];
18664 /*************************
18665 * hwrm_port_lpbk_qstats *
18666 *************************/
18669 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
18670 struct hwrm_port_lpbk_qstats_input {
18671 /* The HWRM command request type. */
18674 * The completion ring to send the completion event on. This should
18675 * be the NQ ID returned from the `nq_alloc` HWRM command.
18677 uint16_t cmpl_ring;
18679 * The sequence ID is used by the driver for tracking multiple
18680 * commands. This ID is treated as opaque data by the firmware and
18681 * the value is returned in the `hwrm_resp_hdr` upon completion.
18685 * The target ID of the command:
18686 * * 0x0-0xFFF8 - The function ID
18687 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18688 * * 0xFFFD - Reserved for user-space HWRM interface
18691 uint16_t target_id;
18693 * A physical address pointer pointing to a host buffer that the
18694 * command's response data will be written. This can be either a host
18695 * physical address (HPA) or a guest physical address (GPA) and must
18696 * point to a physically contiguous block of memory.
18698 uint64_t resp_addr;
18701 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
18702 struct hwrm_port_lpbk_qstats_output {
18703 /* The specific error status for the command. */
18704 uint16_t error_code;
18705 /* The HWRM command request type. */
18707 /* The sequence ID from the original command. */
18709 /* The length of the response data in number of bytes. */
18711 /* Number of transmitted unicast frames */
18712 uint64_t lpbk_ucast_frames;
18713 /* Number of transmitted multicast frames */
18714 uint64_t lpbk_mcast_frames;
18715 /* Number of transmitted broadcast frames */
18716 uint64_t lpbk_bcast_frames;
18717 /* Number of transmitted bytes for unicast traffic */
18718 uint64_t lpbk_ucast_bytes;
18719 /* Number of transmitted bytes for multicast traffic */
18720 uint64_t lpbk_mcast_bytes;
18721 /* Number of transmitted bytes for broadcast traffic */
18722 uint64_t lpbk_bcast_bytes;
18723 /* Total Tx Drops for loopback traffic reported by STATS block */
18724 uint64_t tx_stat_discard;
18725 /* Total Tx Error Drops for loopback traffic reported by STATS block */
18726 uint64_t tx_stat_error;
18727 /* Total Rx Drops for loopback traffic reported by STATS block */
18728 uint64_t rx_stat_discard;
18729 /* Total Rx Error Drops for loopback traffic reported by STATS block */
18730 uint64_t rx_stat_error;
18731 uint8_t unused_0[7];
18733 * This field is used in Output records to indicate that the output
18734 * is completely written to RAM. This field should be read as '1'
18735 * to indicate that the output has been completely written.
18736 * When writing a command completion or response to an internal processor,
18737 * the order of writes has to be such that this field is written last.
18742 /************************
18743 * hwrm_port_ecn_qstats *
18744 ************************/
18747 /* hwrm_port_ecn_qstats_input (size:192b/24B) */
18748 struct hwrm_port_ecn_qstats_input {
18749 /* The HWRM command request type. */
18752 * The completion ring to send the completion event on. This should
18753 * be the NQ ID returned from the `nq_alloc` HWRM command.
18755 uint16_t cmpl_ring;
18757 * The sequence ID is used by the driver for tracking multiple
18758 * commands. This ID is treated as opaque data by the firmware and
18759 * the value is returned in the `hwrm_resp_hdr` upon completion.
18763 * The target ID of the command:
18764 * * 0x0-0xFFF8 - The function ID
18765 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18766 * * 0xFFFD - Reserved for user-space HWRM interface
18769 uint16_t target_id;
18771 * A physical address pointer pointing to a host buffer that the
18772 * command's response data will be written. This can be either a host
18773 * physical address (HPA) or a guest physical address (GPA) and must
18774 * point to a physically contiguous block of memory.
18776 uint64_t resp_addr;
18778 * Port ID of port that is being queried. Unused if NIC is in
18782 uint8_t unused_0[6];
18785 /* hwrm_port_ecn_qstats_output (size:384b/48B) */
18786 struct hwrm_port_ecn_qstats_output {
18787 /* The specific error status for the command. */
18788 uint16_t error_code;
18789 /* The HWRM command request type. */
18791 /* The sequence ID from the original command. */
18793 /* The length of the response data in number of bytes. */
18795 /* Number of packets marked in CoS queue 0. */
18796 uint32_t mark_cnt_cos0;
18797 /* Number of packets marked in CoS queue 1. */
18798 uint32_t mark_cnt_cos1;
18799 /* Number of packets marked in CoS queue 2. */
18800 uint32_t mark_cnt_cos2;
18801 /* Number of packets marked in CoS queue 3. */
18802 uint32_t mark_cnt_cos3;
18803 /* Number of packets marked in CoS queue 4. */
18804 uint32_t mark_cnt_cos4;
18805 /* Number of packets marked in CoS queue 5. */
18806 uint32_t mark_cnt_cos5;
18807 /* Number of packets marked in CoS queue 6. */
18808 uint32_t mark_cnt_cos6;
18809 /* Number of packets marked in CoS queue 7. */
18810 uint32_t mark_cnt_cos7;
18812 * Bitmask that indicates which CoS queues have ECN marking enabled.
18813 * Bit i corresponds to CoS queue i.
18816 uint8_t unused_0[6];
18818 * This field is used in Output records to indicate that the output
18819 * is completely written to RAM. This field should be read as '1'
18820 * to indicate that the output has been completely written.
18821 * When writing a command completion or response to an internal processor,
18822 * the order of writes has to be such that this field is written last.
18827 /***********************
18828 * hwrm_port_clr_stats *
18829 ***********************/
18832 /* hwrm_port_clr_stats_input (size:192b/24B) */
18833 struct hwrm_port_clr_stats_input {
18834 /* The HWRM command request type. */
18837 * The completion ring to send the completion event on. This should
18838 * be the NQ ID returned from the `nq_alloc` HWRM command.
18840 uint16_t cmpl_ring;
18842 * The sequence ID is used by the driver for tracking multiple
18843 * commands. This ID is treated as opaque data by the firmware and
18844 * the value is returned in the `hwrm_resp_hdr` upon completion.
18848 * The target ID of the command:
18849 * * 0x0-0xFFF8 - The function ID
18850 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18851 * * 0xFFFD - Reserved for user-space HWRM interface
18854 uint16_t target_id;
18856 * A physical address pointer pointing to a host buffer that the
18857 * command's response data will be written. This can be either a host
18858 * physical address (HPA) or a guest physical address (GPA) and must
18859 * point to a physically contiguous block of memory.
18861 uint64_t resp_addr;
18862 /* Port ID of port that is being queried. */
18866 * If set to 1, then this field indicates clear the following RoCE
18867 * specific counters.
18868 * RoCE associated TX/RX cos counters
18869 * CNP associated TX/RX cos counters
18870 * RoCE/CNP specific TX/RX flow counters
18871 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
18872 * This flag is honored only when RoCE is enabled on that port.
18874 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
18875 uint8_t unused_0[5];
18878 /* hwrm_port_clr_stats_output (size:128b/16B) */
18879 struct hwrm_port_clr_stats_output {
18880 /* The specific error status for the command. */
18881 uint16_t error_code;
18882 /* The HWRM command request type. */
18884 /* The sequence ID from the original command. */
18886 /* The length of the response data in number of bytes. */
18888 uint8_t unused_0[7];
18890 * This field is used in Output records to indicate that the output
18891 * is completely written to RAM. This field should be read as '1'
18892 * to indicate that the output has been completely written.
18893 * When writing a command completion or response to an internal processor,
18894 * the order of writes has to be such that this field is written last.
18899 /***********************
18900 * hwrm_port_phy_qcaps *
18901 ***********************/
18904 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
18905 struct hwrm_port_phy_qcaps_input {
18906 /* The HWRM command request type. */
18909 * The completion ring to send the completion event on. This should
18910 * be the NQ ID returned from the `nq_alloc` HWRM command.
18912 uint16_t cmpl_ring;
18914 * The sequence ID is used by the driver for tracking multiple
18915 * commands. This ID is treated as opaque data by the firmware and
18916 * the value is returned in the `hwrm_resp_hdr` upon completion.
18920 * The target ID of the command:
18921 * * 0x0-0xFFF8 - The function ID
18922 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18923 * * 0xFFFD - Reserved for user-space HWRM interface
18926 uint16_t target_id;
18928 * A physical address pointer pointing to a host buffer that the
18929 * command's response data will be written. This can be either a host
18930 * physical address (HPA) or a guest physical address (GPA) and must
18931 * point to a physically contiguous block of memory.
18933 uint64_t resp_addr;
18934 /* Port ID of port that is being queried. */
18936 uint8_t unused_0[6];
18939 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
18940 struct hwrm_port_phy_qcaps_output {
18941 /* The specific error status for the command. */
18942 uint16_t error_code;
18943 /* The HWRM command request type. */
18945 /* The sequence ID from the original command. */
18947 /* The length of the response data in number of bytes. */
18949 /* PHY capability flags */
18952 * If set to 1, then this field indicates that the
18953 * link is capable of supporting EEE.
18955 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
18958 * If set to 1, then this field indicates that the
18959 * PHY is capable of supporting external loopback.
18961 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
18964 * If set to 1, then this field indicates that the
18965 * PHY is capable of supporting loopback in autoneg mode.
18967 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
18970 * Indicates if the configuration of shared PHY settings is supported.
18971 * In cases where a physical port is shared by multiple functions
18972 * (e.g. NPAR, multihost, etc), the configuration of PHY
18973 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
18974 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
18976 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
18979 * Reserved field. The HWRM shall set this field to 0.
18980 * An HWRM client shall ignore this field.
18982 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
18984 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
18985 /* Number of front panel ports for this device. */
18987 /* Not supported or unknown */
18988 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
18989 /* single port device */
18990 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
18991 /* 2-port device */
18992 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
18993 /* 3-port device */
18994 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
18995 /* 4-port device */
18996 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
18997 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
18998 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
19000 * This is a bit mask to indicate what speeds are supported
19001 * as forced speeds on this link.
19002 * For each speed that can be forced on this link, the
19003 * corresponding mask bit shall be set to '1'.
19005 uint16_t supported_speeds_force_mode;
19006 /* 100Mb link speed (Half-duplex) */
19007 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
19009 /* 100Mb link speed (Full-duplex) */
19010 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
19012 /* 1Gb link speed (Half-duplex) */
19013 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
19015 /* 1Gb link speed (Full-duplex) */
19016 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
19018 /* 2Gb link speed */
19019 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
19021 /* 25Gb link speed */
19022 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
19024 /* 10Gb link speed */
19025 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
19027 /* 20Gb link speed */
19028 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
19030 /* 25Gb link speed */
19031 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
19033 /* 40Gb link speed */
19034 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
19036 /* 50Gb link speed */
19037 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
19039 /* 100Gb link speed */
19040 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
19042 /* 10Mb link speed (Half-duplex) */
19043 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
19045 /* 10Mb link speed (Full-duplex) */
19046 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
19048 /* 200Gb link speed */
19049 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
19052 * This is a bit mask to indicate what speeds are supported
19053 * for autonegotiation on this link.
19054 * For each speed that can be autonegotiated on this link, the
19055 * corresponding mask bit shall be set to '1'.
19057 uint16_t supported_speeds_auto_mode;
19058 /* 100Mb link speed (Half-duplex) */
19059 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
19061 /* 100Mb link speed (Full-duplex) */
19062 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
19064 /* 1Gb link speed (Half-duplex) */
19065 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
19067 /* 1Gb link speed (Full-duplex) */
19068 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
19070 /* 2Gb link speed */
19071 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
19073 /* 25Gb link speed */
19074 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
19076 /* 10Gb link speed */
19077 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
19079 /* 20Gb link speed */
19080 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
19082 /* 25Gb link speed */
19083 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
19085 /* 40Gb link speed */
19086 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
19088 /* 50Gb link speed */
19089 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
19091 /* 100Gb link speed */
19092 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
19094 /* 10Mb link speed (Half-duplex) */
19095 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
19097 /* 10Mb link speed (Full-duplex) */
19098 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
19100 /* 200Gb link speed */
19101 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
19104 * This is a bit mask to indicate what speeds are supported
19105 * for EEE on this link.
19106 * For each speed that can be autonegotiated when EEE is enabled
19107 * on this link, the corresponding mask bit shall be set to '1'.
19108 * This field is only valid when the eee_suppotred is set to '1'.
19110 uint16_t supported_speeds_eee_mode;
19112 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
19114 /* 100Mb link speed (Full-duplex) */
19115 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
19118 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
19120 /* 1Gb link speed (Full-duplex) */
19121 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
19124 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
19127 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
19129 /* 10Gb link speed */
19130 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
19132 uint32_t tx_lpi_timer_low;
19134 * The lowest value of TX LPI timer that can be set on this link
19135 * when EEE is enabled. This value is in microseconds.
19136 * This field is valid only when_eee_supported is set to '1'.
19138 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
19140 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
19142 * Reserved field. The HWRM shall set this field to 0.
19143 * An HWRM client shall ignore this field.
19145 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
19146 UINT32_C(0xff000000)
19147 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
19148 uint32_t valid_tx_lpi_timer_high;
19150 * The highest value of TX LPI timer that can be set on this link
19151 * when EEE is enabled. This value is in microseconds.
19152 * This field is valid only when_eee_supported is set to '1'.
19154 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
19156 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
19158 * This field is used in Output records to indicate that the output
19159 * is completely written to RAM. This field should be read as '1'
19160 * to indicate that the output has been completely written.
19161 * When writing a command completion or response to an internal processor,
19162 * the order of writes has to be such that this field is written last.
19164 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
19165 UINT32_C(0xff000000)
19166 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
19169 /****************************
19170 * hwrm_port_phy_mdio_write *
19171 ****************************/
19174 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
19175 struct hwrm_port_phy_mdio_write_input {
19176 /* The HWRM command request type. */
19179 * The completion ring to send the completion event on. This should
19180 * be the NQ ID returned from the `nq_alloc` HWRM command.
19182 uint16_t cmpl_ring;
19184 * The sequence ID is used by the driver for tracking multiple
19185 * commands. This ID is treated as opaque data by the firmware and
19186 * the value is returned in the `hwrm_resp_hdr` upon completion.
19190 * The target ID of the command:
19191 * * 0x0-0xFFF8 - The function ID
19192 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19193 * * 0xFFFD - Reserved for user-space HWRM interface
19196 uint16_t target_id;
19198 * A physical address pointer pointing to a host buffer that the
19199 * command's response data will be written. This can be either a host
19200 * physical address (HPA) or a guest physical address (GPA) and must
19201 * point to a physically contiguous block of memory.
19203 uint64_t resp_addr;
19204 /* Reserved for future use. */
19205 uint32_t unused_0[2];
19206 /* Port ID of port. */
19208 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19210 /* 8-bit device address. */
19212 /* 16-bit register address. */
19214 /* 16-bit register data. */
19217 * When this bit is set to 1 a Clause 45 mdio access is done.
19218 * when this bit is set to 0 a Clause 22 mdio access is done.
19222 uint8_t unused_1[7];
19225 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
19226 struct hwrm_port_phy_mdio_write_output {
19227 /* The specific error status for the command. */
19228 uint16_t error_code;
19229 /* The HWRM command request type. */
19231 /* The sequence ID from the original command. */
19233 /* The length of the response data in number of bytes. */
19235 uint8_t unused_0[7];
19237 * This field is used in Output records to indicate that the output
19238 * is completely written to RAM. This field should be read as '1'
19239 * to indicate that the output has been completely written.
19240 * When writing a command completion or response to an internal processor,
19241 * the order of writes has to be such that this field is written last.
19246 /***************************
19247 * hwrm_port_phy_mdio_read *
19248 ***************************/
19251 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
19252 struct hwrm_port_phy_mdio_read_input {
19253 /* The HWRM command request type. */
19256 * The completion ring to send the completion event on. This should
19257 * be the NQ ID returned from the `nq_alloc` HWRM command.
19259 uint16_t cmpl_ring;
19261 * The sequence ID is used by the driver for tracking multiple
19262 * commands. This ID is treated as opaque data by the firmware and
19263 * the value is returned in the `hwrm_resp_hdr` upon completion.
19267 * The target ID of the command:
19268 * * 0x0-0xFFF8 - The function ID
19269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19270 * * 0xFFFD - Reserved for user-space HWRM interface
19273 uint16_t target_id;
19275 * A physical address pointer pointing to a host buffer that the
19276 * command's response data will be written. This can be either a host
19277 * physical address (HPA) or a guest physical address (GPA) and must
19278 * point to a physically contiguous block of memory.
19280 uint64_t resp_addr;
19281 /* Reserved for future use. */
19282 uint32_t unused_0[2];
19283 /* Port ID of port. */
19285 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19287 /* 8-bit device address. */
19289 /* 16-bit register address. */
19292 * When this bit is set to 1 a Clause 45 mdio access is done.
19293 * when this bit is set to 0 a Clause 22 mdio access is done.
19300 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
19301 struct hwrm_port_phy_mdio_read_output {
19302 /* The specific error status for the command. */
19303 uint16_t error_code;
19304 /* The HWRM command request type. */
19306 /* The sequence ID from the original command. */
19308 /* The length of the response data in number of bytes. */
19310 /* 16-bit register data. */
19312 uint8_t unused_0[5];
19314 * This field is used in Output records to indicate that the output
19315 * is completely written to RAM. This field should be read as '1'
19316 * to indicate that the output has been completely written.
19317 * When writing a command completion or response to an internal processor,
19318 * the order of writes has to be such that this field is written last.
19323 /*********************
19324 * hwrm_port_led_cfg *
19325 *********************/
19328 /* hwrm_port_led_cfg_input (size:512b/64B) */
19329 struct hwrm_port_led_cfg_input {
19330 /* The HWRM command request type. */
19333 * The completion ring to send the completion event on. This should
19334 * be the NQ ID returned from the `nq_alloc` HWRM command.
19336 uint16_t cmpl_ring;
19338 * The sequence ID is used by the driver for tracking multiple
19339 * commands. This ID is treated as opaque data by the firmware and
19340 * the value is returned in the `hwrm_resp_hdr` upon completion.
19344 * The target ID of the command:
19345 * * 0x0-0xFFF8 - The function ID
19346 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19347 * * 0xFFFD - Reserved for user-space HWRM interface
19350 uint16_t target_id;
19352 * A physical address pointer pointing to a host buffer that the
19353 * command's response data will be written. This can be either a host
19354 * physical address (HPA) or a guest physical address (GPA) and must
19355 * point to a physically contiguous block of memory.
19357 uint64_t resp_addr;
19360 * This bit must be '1' for the led0_id field to be
19363 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
19366 * This bit must be '1' for the led0_state field to be
19369 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
19372 * This bit must be '1' for the led0_color field to be
19375 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
19378 * This bit must be '1' for the led0_blink_on field to be
19381 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
19384 * This bit must be '1' for the led0_blink_off field to be
19387 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
19390 * This bit must be '1' for the led0_group_id field to be
19393 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
19396 * This bit must be '1' for the led1_id field to be
19399 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
19402 * This bit must be '1' for the led1_state field to be
19405 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
19408 * This bit must be '1' for the led1_color field to be
19411 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
19414 * This bit must be '1' for the led1_blink_on field to be
19417 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
19420 * This bit must be '1' for the led1_blink_off field to be
19423 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
19426 * This bit must be '1' for the led1_group_id field to be
19429 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
19432 * This bit must be '1' for the led2_id field to be
19435 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
19438 * This bit must be '1' for the led2_state field to be
19441 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
19444 * This bit must be '1' for the led2_color field to be
19447 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
19450 * This bit must be '1' for the led2_blink_on field to be
19453 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
19456 * This bit must be '1' for the led2_blink_off field to be
19459 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
19462 * This bit must be '1' for the led2_group_id field to be
19465 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
19468 * This bit must be '1' for the led3_id field to be
19471 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
19474 * This bit must be '1' for the led3_state field to be
19477 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
19480 * This bit must be '1' for the led3_color field to be
19483 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
19486 * This bit must be '1' for the led3_blink_on field to be
19489 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
19492 * This bit must be '1' for the led3_blink_off field to be
19495 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
19498 * This bit must be '1' for the led3_group_id field to be
19501 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
19503 /* Port ID of port whose LEDs are configured. */
19506 * The number of LEDs that are being configured.
19507 * Up to 4 LEDs can be configured with this command.
19510 /* Reserved field. */
19512 /* An identifier for the LED #0. */
19514 /* The requested state of the LED #0. */
19515 uint8_t led0_state;
19516 /* Default state of the LED */
19517 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19519 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
19521 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
19523 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
19524 /* Blink Alternately */
19525 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19526 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
19527 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
19528 /* The requested color of LED #0. */
19529 uint8_t led0_color;
19531 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19533 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19535 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19536 /* Green or Amber */
19537 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19538 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
19539 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
19542 * If the LED #0 state is "blink" or "blinkalt", then
19543 * this field represents the requested time in milliseconds
19544 * to keep LED on between cycles.
19546 uint16_t led0_blink_on;
19548 * If the LED #0 state is "blink" or "blinkalt", then
19549 * this field represents the requested time in milliseconds
19550 * to keep LED off between cycles.
19552 uint16_t led0_blink_off;
19554 * An identifier for the group of LEDs that LED #0 belongs
19556 * If set to 0, then the LED #0 shall not be grouped and
19557 * shall be treated as an individual resource.
19558 * For all other non-zero values of this field, LED #0 shall
19559 * be grouped together with the LEDs with the same group ID
19562 uint8_t led0_group_id;
19563 /* Reserved field. */
19565 /* An identifier for the LED #1. */
19567 /* The requested state of the LED #1. */
19568 uint8_t led1_state;
19569 /* Default state of the LED */
19570 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19572 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
19574 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
19576 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
19577 /* Blink Alternately */
19578 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19579 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
19580 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
19581 /* The requested color of LED #1. */
19582 uint8_t led1_color;
19584 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19586 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19588 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
19589 /* Green or Amber */
19590 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
19591 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
19592 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
19595 * If the LED #1 state is "blink" or "blinkalt", then
19596 * this field represents the requested time in milliseconds
19597 * to keep LED on between cycles.
19599 uint16_t led1_blink_on;
19601 * If the LED #1 state is "blink" or "blinkalt", then
19602 * this field represents the requested time in milliseconds
19603 * to keep LED off between cycles.
19605 uint16_t led1_blink_off;
19607 * An identifier for the group of LEDs that LED #1 belongs
19609 * If set to 0, then the LED #1 shall not be grouped and
19610 * shall be treated as an individual resource.
19611 * For all other non-zero values of this field, LED #1 shall
19612 * be grouped together with the LEDs with the same group ID
19615 uint8_t led1_group_id;
19616 /* Reserved field. */
19618 /* An identifier for the LED #2. */
19620 /* The requested state of the LED #2. */
19621 uint8_t led2_state;
19622 /* Default state of the LED */
19623 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
19625 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
19627 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
19629 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
19630 /* Blink Alternately */
19631 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
19632 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
19633 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
19634 /* The requested color of LED #2. */
19635 uint8_t led2_color;
19637 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
19639 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
19641 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
19642 /* Green or Amber */
19643 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
19644 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
19645 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
19648 * If the LED #2 state is "blink" or "blinkalt", then
19649 * this field represents the requested time in milliseconds
19650 * to keep LED on between cycles.
19652 uint16_t led2_blink_on;
19654 * If the LED #2 state is "blink" or "blinkalt", then
19655 * this field represents the requested time in milliseconds
19656 * to keep LED off between cycles.
19658 uint16_t led2_blink_off;
19660 * An identifier for the group of LEDs that LED #2 belongs
19662 * If set to 0, then the LED #2 shall not be grouped and
19663 * shall be treated as an individual resource.
19664 * For all other non-zero values of this field, LED #2 shall
19665 * be grouped together with the LEDs with the same group ID
19668 uint8_t led2_group_id;
19669 /* Reserved field. */
19671 /* An identifier for the LED #3. */
19673 /* The requested state of the LED #3. */
19674 uint8_t led3_state;
19675 /* Default state of the LED */
19676 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
19678 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
19680 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
19682 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
19683 /* Blink Alternately */
19684 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
19685 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
19686 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
19687 /* The requested color of LED #3. */
19688 uint8_t led3_color;
19690 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
19692 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
19694 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
19695 /* Green or Amber */
19696 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
19697 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
19698 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
19701 * If the LED #3 state is "blink" or "blinkalt", then
19702 * this field represents the requested time in milliseconds
19703 * to keep LED on between cycles.
19705 uint16_t led3_blink_on;
19707 * If the LED #3 state is "blink" or "blinkalt", then
19708 * this field represents the requested time in milliseconds
19709 * to keep LED off between cycles.
19711 uint16_t led3_blink_off;
19713 * An identifier for the group of LEDs that LED #3 belongs
19715 * If set to 0, then the LED #3 shall not be grouped and
19716 * shall be treated as an individual resource.
19717 * For all other non-zero values of this field, LED #3 shall
19718 * be grouped together with the LEDs with the same group ID
19721 uint8_t led3_group_id;
19722 /* Reserved field. */
19726 /* hwrm_port_led_cfg_output (size:128b/16B) */
19727 struct hwrm_port_led_cfg_output {
19728 /* The specific error status for the command. */
19729 uint16_t error_code;
19730 /* The HWRM command request type. */
19732 /* The sequence ID from the original command. */
19734 /* The length of the response data in number of bytes. */
19736 uint8_t unused_0[7];
19738 * This field is used in Output records to indicate that the output
19739 * is completely written to RAM. This field should be read as '1'
19740 * to indicate that the output has been completely written.
19741 * When writing a command completion or response to an internal processor,
19742 * the order of writes has to be such that this field is written last.
19747 /**********************
19748 * hwrm_port_led_qcfg *
19749 **********************/
19752 /* hwrm_port_led_qcfg_input (size:192b/24B) */
19753 struct hwrm_port_led_qcfg_input {
19754 /* The HWRM command request type. */
19757 * The completion ring to send the completion event on. This should
19758 * be the NQ ID returned from the `nq_alloc` HWRM command.
19760 uint16_t cmpl_ring;
19762 * The sequence ID is used by the driver for tracking multiple
19763 * commands. This ID is treated as opaque data by the firmware and
19764 * the value is returned in the `hwrm_resp_hdr` upon completion.
19768 * The target ID of the command:
19769 * * 0x0-0xFFF8 - The function ID
19770 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19771 * * 0xFFFD - Reserved for user-space HWRM interface
19774 uint16_t target_id;
19776 * A physical address pointer pointing to a host buffer that the
19777 * command's response data will be written. This can be either a host
19778 * physical address (HPA) or a guest physical address (GPA) and must
19779 * point to a physically contiguous block of memory.
19781 uint64_t resp_addr;
19782 /* Port ID of port whose LED configuration is being queried. */
19784 uint8_t unused_0[6];
19787 /* hwrm_port_led_qcfg_output (size:448b/56B) */
19788 struct hwrm_port_led_qcfg_output {
19789 /* The specific error status for the command. */
19790 uint16_t error_code;
19791 /* The HWRM command request type. */
19793 /* The sequence ID from the original command. */
19795 /* The length of the response data in number of bytes. */
19798 * The number of LEDs that are configured on this port.
19799 * Up to 4 LEDs can be returned in the response.
19802 /* An identifier for the LED #0. */
19804 /* The type of LED #0. */
19807 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
19809 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
19811 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
19812 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
19813 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
19814 /* The current state of the LED #0. */
19815 uint8_t led0_state;
19816 /* Default state of the LED */
19817 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19819 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
19821 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
19823 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
19824 /* Blink Alternately */
19825 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19826 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
19827 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
19828 /* The color of LED #0. */
19829 uint8_t led0_color;
19831 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19833 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19835 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19836 /* Green or Amber */
19837 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19838 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
19839 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
19842 * If the LED #0 state is "blink" or "blinkalt", then
19843 * this field represents the requested time in milliseconds
19844 * to keep LED on between cycles.
19846 uint16_t led0_blink_on;
19848 * If the LED #0 state is "blink" or "blinkalt", then
19849 * this field represents the requested time in milliseconds
19850 * to keep LED off between cycles.
19852 uint16_t led0_blink_off;
19854 * An identifier for the group of LEDs that LED #0 belongs
19856 * If set to 0, then the LED #0 is not grouped.
19857 * For all other non-zero values of this field, LED #0 is
19858 * grouped together with the LEDs with the same group ID
19861 uint8_t led0_group_id;
19862 /* An identifier for the LED #1. */
19864 /* The type of LED #1. */
19867 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
19869 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
19871 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
19872 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
19873 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
19874 /* The current state of the LED #1. */
19875 uint8_t led1_state;
19876 /* Default state of the LED */
19877 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19879 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
19881 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
19883 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
19884 /* Blink Alternately */
19885 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19886 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
19887 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
19888 /* The color of LED #1. */
19889 uint8_t led1_color;
19891 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19893 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19895 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
19896 /* Green or Amber */
19897 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
19898 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
19899 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
19902 * If the LED #1 state is "blink" or "blinkalt", then
19903 * this field represents the requested time in milliseconds
19904 * to keep LED on between cycles.
19906 uint16_t led1_blink_on;
19908 * If the LED #1 state is "blink" or "blinkalt", then
19909 * this field represents the requested time in milliseconds
19910 * to keep LED off between cycles.
19912 uint16_t led1_blink_off;
19914 * An identifier for the group of LEDs that LED #1 belongs
19916 * If set to 0, then the LED #1 is not grouped.
19917 * For all other non-zero values of this field, LED #1 is
19918 * grouped together with the LEDs with the same group ID
19921 uint8_t led1_group_id;
19922 /* An identifier for the LED #2. */
19924 /* The type of LED #2. */
19927 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
19929 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
19931 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
19932 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
19933 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
19934 /* The current state of the LED #2. */
19935 uint8_t led2_state;
19936 /* Default state of the LED */
19937 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
19939 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
19941 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
19943 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
19944 /* Blink Alternately */
19945 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
19946 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
19947 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
19948 /* The color of LED #2. */
19949 uint8_t led2_color;
19951 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
19953 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
19955 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
19956 /* Green or Amber */
19957 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
19958 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
19959 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
19962 * If the LED #2 state is "blink" or "blinkalt", then
19963 * this field represents the requested time in milliseconds
19964 * to keep LED on between cycles.
19966 uint16_t led2_blink_on;
19968 * If the LED #2 state is "blink" or "blinkalt", then
19969 * this field represents the requested time in milliseconds
19970 * to keep LED off between cycles.
19972 uint16_t led2_blink_off;
19974 * An identifier for the group of LEDs that LED #2 belongs
19976 * If set to 0, then the LED #2 is not grouped.
19977 * For all other non-zero values of this field, LED #2 is
19978 * grouped together with the LEDs with the same group ID
19981 uint8_t led2_group_id;
19982 /* An identifier for the LED #3. */
19984 /* The type of LED #3. */
19987 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
19989 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
19991 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
19992 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
19993 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
19994 /* The current state of the LED #3. */
19995 uint8_t led3_state;
19996 /* Default state of the LED */
19997 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
19999 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
20001 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
20003 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
20004 /* Blink Alternately */
20005 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
20006 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
20007 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
20008 /* The color of LED #3. */
20009 uint8_t led3_color;
20011 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
20013 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
20015 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
20016 /* Green or Amber */
20017 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20018 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
20019 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
20022 * If the LED #3 state is "blink" or "blinkalt", then
20023 * this field represents the requested time in milliseconds
20024 * to keep LED on between cycles.
20026 uint16_t led3_blink_on;
20028 * If the LED #3 state is "blink" or "blinkalt", then
20029 * this field represents the requested time in milliseconds
20030 * to keep LED off between cycles.
20032 uint16_t led3_blink_off;
20034 * An identifier for the group of LEDs that LED #3 belongs
20036 * If set to 0, then the LED #3 is not grouped.
20037 * For all other non-zero values of this field, LED #3 is
20038 * grouped together with the LEDs with the same group ID
20041 uint8_t led3_group_id;
20042 uint8_t unused_4[6];
20044 * This field is used in Output records to indicate that the output
20045 * is completely written to RAM. This field should be read as '1'
20046 * to indicate that the output has been completely written.
20047 * When writing a command completion or response to an internal processor,
20048 * the order of writes has to be such that this field is written last.
20053 /***********************
20054 * hwrm_port_led_qcaps *
20055 ***********************/
20058 /* hwrm_port_led_qcaps_input (size:192b/24B) */
20059 struct hwrm_port_led_qcaps_input {
20060 /* The HWRM command request type. */
20063 * The completion ring to send the completion event on. This should
20064 * be the NQ ID returned from the `nq_alloc` HWRM command.
20066 uint16_t cmpl_ring;
20068 * The sequence ID is used by the driver for tracking multiple
20069 * commands. This ID is treated as opaque data by the firmware and
20070 * the value is returned in the `hwrm_resp_hdr` upon completion.
20074 * The target ID of the command:
20075 * * 0x0-0xFFF8 - The function ID
20076 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20077 * * 0xFFFD - Reserved for user-space HWRM interface
20080 uint16_t target_id;
20082 * A physical address pointer pointing to a host buffer that the
20083 * command's response data will be written. This can be either a host
20084 * physical address (HPA) or a guest physical address (GPA) and must
20085 * point to a physically contiguous block of memory.
20087 uint64_t resp_addr;
20088 /* Port ID of port whose LED configuration is being queried. */
20090 uint8_t unused_0[6];
20093 /* hwrm_port_led_qcaps_output (size:384b/48B) */
20094 struct hwrm_port_led_qcaps_output {
20095 /* The specific error status for the command. */
20096 uint16_t error_code;
20097 /* The HWRM command request type. */
20099 /* The sequence ID from the original command. */
20101 /* The length of the response data in number of bytes. */
20104 * The number of LEDs that are configured on this port.
20105 * Up to 4 LEDs can be returned in the response.
20108 /* Reserved for future use. */
20110 /* An identifier for the LED #0. */
20112 /* The type of LED #0. */
20115 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20117 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20119 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20120 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
20121 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
20123 * An identifier for the group of LEDs that LED #0 belongs
20125 * If set to 0, then the LED #0 cannot be grouped.
20126 * For all other non-zero values of this field, LED #0 is
20127 * grouped together with the LEDs with the same group ID
20130 uint8_t led0_group_id;
20132 /* The states supported by LED #0. */
20133 uint16_t led0_state_caps;
20135 * If set to 1, this LED is enabled.
20136 * If set to 0, this LED is disabled.
20138 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
20141 * If set to 1, off state is supported on this LED.
20142 * If set to 0, off state is not supported on this LED.
20144 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
20147 * If set to 1, on state is supported on this LED.
20148 * If set to 0, on state is not supported on this LED.
20150 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
20153 * If set to 1, blink state is supported on this LED.
20154 * If set to 0, blink state is not supported on this LED.
20156 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
20159 * If set to 1, blink_alt state is supported on this LED.
20160 * If set to 0, blink_alt state is not supported on this LED.
20162 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
20164 /* The colors supported by LED #0. */
20165 uint16_t led0_color_caps;
20167 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
20170 * If set to 1, Amber color is supported on this LED.
20171 * If set to 0, Amber color is not supported on this LED.
20173 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
20176 * If set to 1, Green color is supported on this LED.
20177 * If set to 0, Green color is not supported on this LED.
20179 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
20181 /* An identifier for the LED #1. */
20183 /* The type of LED #1. */
20186 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20188 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20190 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20191 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
20192 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
20194 * An identifier for the group of LEDs that LED #1 belongs
20196 * If set to 0, then the LED #0 cannot be grouped.
20197 * For all other non-zero values of this field, LED #0 is
20198 * grouped together with the LEDs with the same group ID
20201 uint8_t led1_group_id;
20203 /* The states supported by LED #1. */
20204 uint16_t led1_state_caps;
20206 * If set to 1, this LED is enabled.
20207 * If set to 0, this LED is disabled.
20209 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
20212 * If set to 1, off state is supported on this LED.
20213 * If set to 0, off state is not supported on this LED.
20215 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
20218 * If set to 1, on state is supported on this LED.
20219 * If set to 0, on state is not supported on this LED.
20221 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
20224 * If set to 1, blink state is supported on this LED.
20225 * If set to 0, blink state is not supported on this LED.
20227 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
20230 * If set to 1, blink_alt state is supported on this LED.
20231 * If set to 0, blink_alt state is not supported on this LED.
20233 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
20235 /* The colors supported by LED #1. */
20236 uint16_t led1_color_caps;
20238 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
20241 * If set to 1, Amber color is supported on this LED.
20242 * If set to 0, Amber color is not supported on this LED.
20244 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
20247 * If set to 1, Green color is supported on this LED.
20248 * If set to 0, Green color is not supported on this LED.
20250 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
20252 /* An identifier for the LED #2. */
20254 /* The type of LED #2. */
20257 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20259 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20261 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20262 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
20263 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
20265 * An identifier for the group of LEDs that LED #0 belongs
20267 * If set to 0, then the LED #0 cannot be grouped.
20268 * For all other non-zero values of this field, LED #0 is
20269 * grouped together with the LEDs with the same group ID
20272 uint8_t led2_group_id;
20274 /* The states supported by LED #2. */
20275 uint16_t led2_state_caps;
20277 * If set to 1, this LED is enabled.
20278 * If set to 0, this LED is disabled.
20280 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
20283 * If set to 1, off state is supported on this LED.
20284 * If set to 0, off state is not supported on this LED.
20286 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
20289 * If set to 1, on state is supported on this LED.
20290 * If set to 0, on state is not supported on this LED.
20292 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
20295 * If set to 1, blink state is supported on this LED.
20296 * If set to 0, blink state is not supported on this LED.
20298 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
20301 * If set to 1, blink_alt state is supported on this LED.
20302 * If set to 0, blink_alt state is not supported on this LED.
20304 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
20306 /* The colors supported by LED #2. */
20307 uint16_t led2_color_caps;
20309 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
20312 * If set to 1, Amber color is supported on this LED.
20313 * If set to 0, Amber color is not supported on this LED.
20315 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
20318 * If set to 1, Green color is supported on this LED.
20319 * If set to 0, Green color is not supported on this LED.
20321 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
20323 /* An identifier for the LED #3. */
20325 /* The type of LED #3. */
20328 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20330 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20332 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20333 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
20334 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
20336 * An identifier for the group of LEDs that LED #3 belongs
20338 * If set to 0, then the LED #0 cannot be grouped.
20339 * For all other non-zero values of this field, LED #0 is
20340 * grouped together with the LEDs with the same group ID
20343 uint8_t led3_group_id;
20345 /* The states supported by LED #3. */
20346 uint16_t led3_state_caps;
20348 * If set to 1, this LED is enabled.
20349 * If set to 0, this LED is disabled.
20351 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
20354 * If set to 1, off state is supported on this LED.
20355 * If set to 0, off state is not supported on this LED.
20357 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
20360 * If set to 1, on state is supported on this LED.
20361 * If set to 0, on state is not supported on this LED.
20363 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
20366 * If set to 1, blink state is supported on this LED.
20367 * If set to 0, blink state is not supported on this LED.
20369 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
20372 * If set to 1, blink_alt state is supported on this LED.
20373 * If set to 0, blink_alt state is not supported on this LED.
20375 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
20377 /* The colors supported by LED #3. */
20378 uint16_t led3_color_caps;
20380 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
20383 * If set to 1, Amber color is supported on this LED.
20384 * If set to 0, Amber color is not supported on this LED.
20386 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
20389 * If set to 1, Green color is supported on this LED.
20390 * If set to 0, Green color is not supported on this LED.
20392 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
20394 uint8_t unused_4[3];
20396 * This field is used in Output records to indicate that the output
20397 * is completely written to RAM. This field should be read as '1'
20398 * to indicate that the output has been completely written.
20399 * When writing a command completion or response to an internal processor,
20400 * the order of writes has to be such that this field is written last.
20405 /***********************
20406 * hwrm_port_prbs_test *
20407 ***********************/
20410 /* hwrm_port_prbs_test_input (size:384b/48B) */
20411 struct hwrm_port_prbs_test_input {
20412 /* The HWRM command request type. */
20415 * The completion ring to send the completion event on. This should
20416 * be the NQ ID returned from the `nq_alloc` HWRM command.
20418 uint16_t cmpl_ring;
20420 * The sequence ID is used by the driver for tracking multiple
20421 * commands. This ID is treated as opaque data by the firmware and
20422 * the value is returned in the `hwrm_resp_hdr` upon completion.
20426 * The target ID of the command:
20427 * * 0x0-0xFFF8 - The function ID
20428 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20429 * * 0xFFFD - Reserved for user-space HWRM interface
20432 uint16_t target_id;
20434 * A physical address pointer pointing to a host buffer that the
20435 * command's response data will be written. This can be either a host
20436 * physical address (HPA) or a guest physical address (GPA) and must
20437 * point to a physically contiguous block of memory.
20439 uint64_t resp_addr;
20440 /* Host address data is to DMA'd to. */
20441 uint64_t resp_data_addr;
20443 * Size of the buffer pointed to by resp_data_addr. The firmware may
20444 * use this entire buffer or less than the entire buffer, but never more.
20449 /* Port ID of port where PRBS test to be run. */
20451 /* Polynomial selection for PRBS test. */
20454 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
20456 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
20458 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
20460 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
20462 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
20464 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
20466 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
20468 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
20469 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
20470 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
20472 * Configuration bits for PRBS test.
20473 * Use enable bit to start/stop test.
20474 * Use tx/rx lane map bits to run test on specific lanes,
20475 * if set to 0 test will be run on all lanes.
20477 uint16_t prbs_config;
20479 * Set 0 to stop test currently in progress
20480 * Set 1 to start test with configuration provided.
20482 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
20485 * If set to 1, tx_lane_map bitmap should have lane bits set.
20486 * If set to 0, test will be run on all lanes for this port.
20488 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
20491 * If set to 1, rx_lane_map bitmap should have lane bits set.
20492 * If set to 0, test will be run on all lanes for this port.
20494 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
20496 /* Duration in seconds to run the PRBS test. */
20499 * If tx_lane_map_valid is set to 1, this field is a bitmap
20500 * of tx lanes to run PRBS test. bit0 = lane0,
20501 * bit1 = lane1 ..bit31 = lane31
20503 uint32_t tx_lane_map;
20505 * If rx_lane_map_valid is set to 1, this field is a bitmap
20506 * of rx lanes to run PRBS test. bit0 = lane0,
20507 * bit1 = lane1 ..bit31 = lane31
20509 uint32_t rx_lane_map;
20512 /* hwrm_port_prbs_test_output (size:128b/16B) */
20513 struct hwrm_port_prbs_test_output {
20514 /* The specific error status for the command. */
20515 uint16_t error_code;
20516 /* The HWRM command request type. */
20518 /* The sequence ID from the original command. */
20520 /* The length of the response data in number of bytes. */
20522 /* Total length of stored data. */
20523 uint16_t total_data_len;
20525 uint8_t unused_1[3];
20527 * This field is used in Output records to indicate that the output
20528 * is completely written to RAM. This field should be read as '1'
20529 * to indicate that the output has been completely written.
20530 * When writing a command completion or response to an internal processor,
20531 * the order of writes has to be such that this field is written last.
20536 /**********************
20537 * hwrm_port_dsc_dump *
20538 **********************/
20541 /* hwrm_port_dsc_dump_input (size:320b/40B) */
20542 struct hwrm_port_dsc_dump_input {
20543 /* The HWRM command request type. */
20546 * The completion ring to send the completion event on. This should
20547 * be the NQ ID returned from the `nq_alloc` HWRM command.
20549 uint16_t cmpl_ring;
20551 * The sequence ID is used by the driver for tracking multiple
20552 * commands. This ID is treated as opaque data by the firmware and
20553 * the value is returned in the `hwrm_resp_hdr` upon completion.
20557 * The target ID of the command:
20558 * * 0x0-0xFFF8 - The function ID
20559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20560 * * 0xFFFD - Reserved for user-space HWRM interface
20563 uint16_t target_id;
20565 * A physical address pointer pointing to a host buffer that the
20566 * command's response data will be written. This can be either a host
20567 * physical address (HPA) or a guest physical address (GPA) and must
20568 * point to a physically contiguous block of memory.
20570 uint64_t resp_addr;
20571 /* Host address where response diagnostic data is returned. */
20572 uint64_t resp_data_addr;
20574 * Size of the buffer pointed to by resp_data_addr. The firmware
20575 * may use this entire buffer or less than the entire buffer, but
20581 /* Port ID of port where dsc dump to be collected. */
20583 /* Diag level specified by the user */
20584 uint16_t diag_level;
20585 /* SRDS_DIAG_LANE */
20586 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
20588 /* SRDS_DIAG_CORE */
20589 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
20591 /* SRDS_DIAG_EVENT */
20592 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
20594 /* SRDS_DIAG_EYE */
20595 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
20597 /* SRDS_DIAG_REG_CORE */
20598 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
20600 /* SRDS_DIAG_REG_LANE */
20601 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
20603 /* SRDS_DIAG_UC_CORE */
20604 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
20606 /* SRDS_DIAG_UC_LANE */
20607 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
20609 /* SRDS_DIAG_LANE_DEBUG */
20610 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
20612 /* SRDS_DIAG_BER_VERT */
20613 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
20615 /* SRDS_DIAG_BER_HORZ */
20616 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
20618 /* SRDS_DIAG_EVENT_SAFE */
20619 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
20621 /* SRDS_DIAG_TIMESTAMP */
20622 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
20624 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
20625 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
20627 * This field is a lane number
20628 * on which to collect the dsc dump
20630 uint16_t lane_number;
20632 * Configuration bits.
20633 * Use enable bit to start dsc dump or retrieve dump
20635 uint16_t dsc_dump_config;
20637 * Set 0 to retrieve the dsc dump
20638 * Set 1 to start the dsc dump
20640 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
20644 /* hwrm_port_dsc_dump_output (size:128b/16B) */
20645 struct hwrm_port_dsc_dump_output {
20646 /* The specific error status for the command. */
20647 uint16_t error_code;
20648 /* The HWRM command request type. */
20650 /* The sequence ID from the original command. */
20652 /* The length of the response data in number of bytes. */
20654 /* Total length of stored data. */
20655 uint16_t total_data_len;
20657 uint8_t unused_1[3];
20659 * This field is used in Output records to indicate that the output
20660 * is completely written to RAM. This field should be read as '1'
20661 * to indicate that the output has been completely written.
20662 * When writing a command completion or response to an internal processor,
20663 * the order of writes has to be such that this field is written last.
20668 /******************************
20669 * hwrm_port_sfp_sideband_cfg *
20670 ******************************/
20673 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
20674 struct hwrm_port_sfp_sideband_cfg_input {
20675 /* The HWRM command request type. */
20678 * The completion ring to send the completion event on. This should
20679 * be the NQ ID returned from the `nq_alloc` HWRM command.
20681 uint16_t cmpl_ring;
20683 * The sequence ID is used by the driver for tracking multiple
20684 * commands. This ID is treated as opaque data by the firmware and
20685 * the value is returned in the `hwrm_resp_hdr` upon completion.
20689 * The target ID of the command:
20690 * * 0x0-0xFFF8 - The function ID
20691 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20692 * * 0xFFFD - Reserved for user-space HWRM interface
20695 uint16_t target_id;
20697 * A physical address pointer pointing to a host buffer that the
20698 * command's response data will be written. This can be either a host
20699 * physical address (HPA) or a guest physical address (GPA) and must
20700 * point to a physically contiguous block of memory.
20702 uint64_t resp_addr;
20703 /* Port ID of port that is to be queried. */
20705 uint8_t unused_0[6];
20707 * This bitfield is used to specify which bits from the 'flags'
20708 * fields are being configured by the caller.
20711 /* This bit must be '1' for rs0 to be configured. */
20712 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
20714 /* This bit must be '1' for rs1 to be configured. */
20715 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
20717 /* This bit must be '1' for tx_disable to be configured. */
20718 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
20721 * This bit must be '1' for mod_sel to be configured.
20722 * Valid only on QSFP modules
20724 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
20726 /* This bit must be '1' for reset_l to be configured. */
20727 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
20729 /* This bit must be '1' for lp_mode to be configured. */
20730 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
20732 /* This bit must be '1' for pwr_disable to be configured. */
20733 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
20736 * Only bits that have corresponding bits in the 'enables'
20737 * bitfield are processed by the firmware, all other bits
20738 * of 'flags' are ignored.
20742 * This bit along with rs1 configures the current speed of the dual
20743 * rate module. If these pins are GNDed then the speed can be changed
20744 * by driectly writing to EEPROM.
20746 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
20749 * This bit along with rs0 configures the current speed of the dual
20750 * rate module. If these pins are GNDed then the speed can be changed
20751 * by driectly writing to EEPROM.
20753 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
20756 * When this bit is set to '1', tx_disable is set.
20757 * On a 1G BASE-T module, if this bit is set,
20758 * module PHY registers will not be accessible.
20760 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
20763 * When this bit is set to '1', this module is selected.
20764 * Valid only on QSFP modules
20766 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
20769 * If reset_l is set to 0, Module will be taken out of reset
20770 * and other signals will be set to their requested state once
20771 * the module is out of reset.
20772 * Valid only on QSFP modules
20774 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
20777 * When this bit is set to '1', the module will be configured
20778 * in low power mode.
20779 * Valid only on QSFP modules
20781 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
20783 /* When this bit is set to '1', the module will be powered down. */
20784 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
20788 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
20789 struct hwrm_port_sfp_sideband_cfg_output {
20790 /* The specific error status for the command. */
20791 uint16_t error_code;
20792 /* The HWRM command request type. */
20794 /* The sequence ID from the original command. */
20796 /* The length of the response data in number of bytes. */
20800 * This field is used in Output records to indicate that the output
20801 * is completely written to RAM. This field should be read as '1'
20802 * to indicate that the output has been completely written. When
20803 * writing a command completion or response to an internal processor,
20804 * the order of writes has to be such that this field is written last.
20809 /*******************************
20810 * hwrm_port_sfp_sideband_qcfg *
20811 *******************************/
20814 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
20815 struct hwrm_port_sfp_sideband_qcfg_input {
20816 /* The HWRM command request type. */
20819 * The completion ring to send the completion event on. This should
20820 * be the NQ ID returned from the `nq_alloc` HWRM command.
20822 uint16_t cmpl_ring;
20824 * The sequence ID is used by the driver for tracking multiple
20825 * commands. This ID is treated as opaque data by the firmware and
20826 * the value is returned in the `hwrm_resp_hdr` upon completion.
20830 * The target ID of the command:
20831 * * 0x0-0xFFF8 - The function ID
20832 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20833 * * 0xFFFD - Reserved for user-space HWRM interface
20836 uint16_t target_id;
20838 * A physical address pointer pointing to a host buffer that the
20839 * command's response data will be written. This can be either a host
20840 * physical address (HPA) or a guest physical address (GPA) and must
20841 * point to a physically contiguous block of memory.
20843 uint64_t resp_addr;
20844 /* Port ID of port that is to be queried. */
20846 uint8_t unused_0[6];
20849 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
20850 struct hwrm_port_sfp_sideband_qcfg_output {
20851 /* The specific error status for the command. */
20852 uint16_t error_code;
20853 /* The HWRM command request type. */
20855 /* The sequence ID from the original command. */
20857 /* The length of the response data in number of bytes. */
20860 * Bitmask indicating which sideband signals are valid.
20861 * This is based on the board and nvm cfg that is present on the board.
20863 uint32_t supported_mask;
20864 uint32_t sideband_signals;
20865 /* When this bit is set to '1', the Module is absent. */
20866 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
20869 * When this bit is set to '1', there is no valid signal on RX.
20870 * This signal is a filtered version of Signal Detect.
20872 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
20875 * This bit along with rs1 indiactes the current speed of the dual
20876 * rate module.If these pins are grounded then the speed can be
20877 * changed by driectky writing to EEPROM.
20879 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
20882 * This bit along with rs0 indiactes the current speed of the dual
20883 * rate module.If these pins are grounded then the speed can be
20884 * changed by driectky writing to EEPROM.
20886 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
20889 * When this bit is set to '1', tx_disable is set.
20890 * On a 1G BASE-T module, if this bit is set, module PHY
20891 * registers will not be accessible.
20893 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
20895 /* When this bit is set to '1', tx_fault is set. */
20896 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
20899 * When this bit is set to '1', module is selected.
20900 * Valid only on QSFP modules
20902 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
20905 * When this bit is set to '0', the module is held in reset.
20906 * if reset_l is set to 1,first module is taken out of reset
20907 * and other signals will be set to their requested state.
20908 * Valid only on QSFP modules.
20910 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
20913 * When this bit is set to '1', the module is in low power mode.
20914 * Valid only on QSFP modules
20916 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
20918 /* When this bit is set to '1', module is in power down state. */
20919 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
20923 * This field is used in Output records to indicate that the output
20924 * is completely written to RAM. This field should be read as '1'
20925 * to indicate that the output has been completely written. When
20926 * writing a command completion or response to an internal processor,
20927 * the order of writes has to be such that this field is written last.
20932 /**********************************
20933 * hwrm_port_phy_mdio_bus_acquire *
20934 **********************************/
20937 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
20938 struct hwrm_port_phy_mdio_bus_acquire_input {
20939 /* The HWRM command request type. */
20942 * The completion ring to send the completion event on. This should
20943 * be the NQ ID returned from the `nq_alloc` HWRM command.
20945 uint16_t cmpl_ring;
20947 * The sequence ID is used by the driver for tracking multiple
20948 * commands. This ID is treated as opaque data by the firmware and
20949 * the value is returned in the `hwrm_resp_hdr` upon completion.
20953 * The target ID of the command:
20954 * * 0x0-0xFFF8 - The function ID
20955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20956 * * 0xFFFD - Reserved for user-space HWRM interface
20959 uint16_t target_id;
20961 * A physical address pointer pointing to a host buffer that the
20962 * command's response data will be written. This can be either a host
20963 * physical address (HPA) or a guest physical address (GPA) and must
20964 * point to a physically contiguous block of memory.
20966 uint64_t resp_addr;
20967 /* Port ID of the port. */
20970 * client_id of the client requesting BUS access.
20971 * Any value from 0x10 to 0xFFFF can be used.
20972 * Client should make sure that the returned client_id
20973 * in response matches the client_id in request.
20974 * 0-0xF are reserved for internal use.
20976 uint16_t client_id;
20978 * Timeout in milli seconds, MDIO BUS will be released automatically
20979 * after this time, if another mdio acquire command is not received
20980 * within the timeout window from the same client.
20981 * A 0xFFFF will hold the bus until this bus is released.
20983 uint16_t mdio_bus_timeout;
20984 uint8_t unused_0[2];
20987 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
20988 struct hwrm_port_phy_mdio_bus_acquire_output {
20989 /* The specific error status for the command. */
20990 uint16_t error_code;
20991 /* The HWRM command request type. */
20993 /* The sequence ID from the original command. */
20995 /* The length of the response data in number of bytes. */
20999 * client_id of the module holding the BUS.
21000 * 0-0xF are reserved for internal use.
21002 uint16_t client_id;
21003 uint8_t unused_1[3];
21005 * This field is used in Output records to indicate that the output
21006 * is completely written to RAM. This field should be read as '1'
21007 * to indicate that the output has been completely written.
21008 * When writing a command completion or response to an internal processor,
21009 * the order of writes has to be such that this field is written last.
21014 /**********************************
21015 * hwrm_port_phy_mdio_bus_release *
21016 **********************************/
21019 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
21020 struct hwrm_port_phy_mdio_bus_release_input {
21021 /* The HWRM command request type. */
21024 * The completion ring to send the completion event on. This should
21025 * be the NQ ID returned from the `nq_alloc` HWRM command.
21027 uint16_t cmpl_ring;
21029 * The sequence ID is used by the driver for tracking multiple
21030 * commands. This ID is treated as opaque data by the firmware and
21031 * the value is returned in the `hwrm_resp_hdr` upon completion.
21035 * The target ID of the command:
21036 * * 0x0-0xFFF8 - The function ID
21037 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21038 * * 0xFFFD - Reserved for user-space HWRM interface
21041 uint16_t target_id;
21043 * A physical address pointer pointing to a host buffer that the
21044 * command's response data will be written. This can be either a host
21045 * physical address (HPA) or a guest physical address (GPA) and must
21046 * point to a physically contiguous block of memory.
21048 uint64_t resp_addr;
21049 /* Port ID of the port. */
21052 * client_id of the client requesting BUS release.
21053 * A client should not release any other clients BUS.
21055 uint16_t client_id;
21056 uint8_t unused_0[4];
21059 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
21060 struct hwrm_port_phy_mdio_bus_release_output {
21061 /* The specific error status for the command. */
21062 uint16_t error_code;
21063 /* The HWRM command request type. */
21065 /* The sequence ID from the original command. */
21067 /* The length of the response data in number of bytes. */
21070 /* The BUS is released if client_id matches the client_id in request. */
21071 uint16_t clients_id;
21072 uint8_t unused_1[3];
21074 * This field is used in Output records to indicate that the output
21075 * is completely written to RAM. This field should be read as '1'
21076 * to indicate that the output has been completely written.
21077 * When writing a command completion or response to an internal processor,
21078 * the order of writes has to be such that this field is written last.
21083 /***********************
21084 * hwrm_queue_qportcfg *
21085 ***********************/
21088 /* hwrm_queue_qportcfg_input (size:192b/24B) */
21089 struct hwrm_queue_qportcfg_input {
21090 /* The HWRM command request type. */
21093 * The completion ring to send the completion event on. This should
21094 * be the NQ ID returned from the `nq_alloc` HWRM command.
21096 uint16_t cmpl_ring;
21098 * The sequence ID is used by the driver for tracking multiple
21099 * commands. This ID is treated as opaque data by the firmware and
21100 * the value is returned in the `hwrm_resp_hdr` upon completion.
21104 * The target ID of the command:
21105 * * 0x0-0xFFF8 - The function ID
21106 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21107 * * 0xFFFD - Reserved for user-space HWRM interface
21110 uint16_t target_id;
21112 * A physical address pointer pointing to a host buffer that the
21113 * command's response data will be written. This can be either a host
21114 * physical address (HPA) or a guest physical address (GPA) and must
21115 * point to a physically contiguous block of memory.
21117 uint64_t resp_addr;
21120 * Enumeration denoting the RX, TX type of the resource.
21121 * This enumeration is used for resources that are similar for both
21122 * TX and RX paths of the chip.
21124 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21126 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21128 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21129 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
21130 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
21132 * Port ID of port for which the queue configuration is being
21133 * queried. This field is only required when sent by IPC.
21137 * Drivers will set this capability when it can use
21138 * queue_idx_service_profile to map the queues to application.
21140 uint8_t drv_qmap_cap;
21142 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
21144 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
21145 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
21146 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
21150 /* hwrm_queue_qportcfg_output (size:256b/32B) */
21151 struct hwrm_queue_qportcfg_output {
21152 /* The specific error status for the command. */
21153 uint16_t error_code;
21154 /* The HWRM command request type. */
21156 /* The sequence ID from the original command. */
21158 /* The length of the response data in number of bytes. */
21161 * The maximum number of queues that can be configured on this
21163 * Valid values range from 1 through 8.
21165 uint8_t max_configurable_queues;
21167 * The maximum number of lossless queues that can be configured
21169 * Valid values range from 0 through 8.
21171 uint8_t max_configurable_lossless_queues;
21173 * Bitmask indicating which queues can be configured by the
21174 * hwrm_queue_cfg command.
21176 * Each bit represents a specific queue where bit 0 represents
21177 * queue 0 and bit 7 represents queue 7.
21178 * # A value of 0 indicates that the queue is not configurable
21179 * by the hwrm_queue_cfg command.
21180 * # A value of 1 indicates that the queue is configurable.
21181 * # A hwrm_queue_cfg command shall return error when trying to
21182 * configure a queue not configurable.
21184 uint8_t queue_cfg_allowed;
21185 /* Information about queue configuration. */
21186 uint8_t queue_cfg_info;
21188 * If this flag is set to '1', then the queues are
21189 * configured asymmetrically on TX and RX sides.
21190 * If this flag is set to '0', then the queues are
21191 * configured symmetrically on TX and RX sides. For
21192 * symmetric configuration, the queue configuration
21193 * including queue ids and service profiles on the
21194 * TX side is the same as the corresponding queue
21195 * configuration on the RX side.
21197 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21200 * Bitmask indicating which queues can be configured by the
21201 * hwrm_queue_pfcenable_cfg command.
21203 * Each bit represents a specific priority where bit 0 represents
21204 * priority 0 and bit 7 represents priority 7.
21205 * # A value of 0 indicates that the priority is not configurable by
21206 * the hwrm_queue_pfcenable_cfg command.
21207 * # A value of 1 indicates that the priority is configurable.
21208 * # A hwrm_queue_pfcenable_cfg command shall return error when
21209 * trying to configure a priority that is not configurable.
21211 uint8_t queue_pfcenable_cfg_allowed;
21213 * Bitmask indicating which queues can be configured by the
21214 * hwrm_queue_pri2cos_cfg command.
21216 * Each bit represents a specific queue where bit 0 represents
21217 * queue 0 and bit 7 represents queue 7.
21218 * # A value of 0 indicates that the queue is not configurable
21219 * by the hwrm_queue_pri2cos_cfg command.
21220 * # A value of 1 indicates that the queue is configurable.
21221 * # A hwrm_queue_pri2cos_cfg command shall return error when
21222 * trying to configure a queue that is not configurable.
21224 uint8_t queue_pri2cos_cfg_allowed;
21226 * Bitmask indicating which queues can be configured by the
21227 * hwrm_queue_pri2cos_cfg command.
21229 * Each bit represents a specific queue where bit 0 represents
21230 * queue 0 and bit 7 represents queue 7.
21231 * # A value of 0 indicates that the queue is not configurable
21232 * by the hwrm_queue_pri2cos_cfg command.
21233 * # A value of 1 indicates that the queue is configurable.
21234 * # A hwrm_queue_pri2cos_cfg command shall return error when
21235 * trying to configure a queue not configurable.
21237 uint8_t queue_cos2bw_cfg_allowed;
21239 * ID of CoS Queue 0.
21242 * # This ID can be used on any subsequent call to an hwrm command
21243 * that takes a queue id.
21244 * # IDs must always be queried by this command before any use
21245 * by the driver or software.
21246 * # Any driver or software should not make any assumptions about
21248 * # A value of 0xff indicates that the queue is not available.
21249 * # Available queues may not be in sequential order.
21252 /* This value is applicable to CoS queues only. */
21253 uint8_t queue_id0_service_profile;
21254 /* Lossy (best-effort) */
21255 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
21257 /* Lossless (legacy) */
21258 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
21260 /* Lossless RoCE */
21261 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
21263 /* Lossy RoCE CNP */
21264 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21267 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
21269 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21270 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
21272 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
21273 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
21275 * ID of CoS Queue 1.
21278 * # This ID can be used on any subsequent call to an hwrm command
21279 * that takes a queue id.
21280 * # IDs must always be queried by this command before any use
21281 * by the driver or software.
21282 * # Any driver or software should not make any assumptions about
21284 * # A value of 0xff indicates that the queue is not available.
21285 * # Available queues may not be in sequential order.
21288 /* This value is applicable to CoS queues only. */
21289 uint8_t queue_id1_service_profile;
21290 /* Lossy (best-effort) */
21291 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
21293 /* Lossless (legacy) */
21294 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
21296 /* Lossless RoCE */
21297 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
21299 /* Lossy RoCE CNP */
21300 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21303 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
21305 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21306 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
21308 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
21309 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
21311 * ID of CoS Queue 2.
21314 * # This ID can be used on any subsequent call to an hwrm command
21315 * that takes a queue id.
21316 * # IDs must always be queried by this command before any use
21317 * by the driver or software.
21318 * # Any driver or software should not make any assumptions about
21320 * # A value of 0xff indicates that the queue is not available.
21321 * # Available queues may not be in sequential order.
21324 /* This value is applicable to CoS queues only. */
21325 uint8_t queue_id2_service_profile;
21326 /* Lossy (best-effort) */
21327 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
21329 /* Lossless (legacy) */
21330 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
21332 /* Lossless RoCE */
21333 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
21335 /* Lossy RoCE CNP */
21336 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21339 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
21341 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21342 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
21344 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
21345 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
21347 * ID of CoS Queue 3.
21350 * # This ID can be used on any subsequent call to an hwrm command
21351 * that takes a queue id.
21352 * # IDs must always be queried by this command before any use
21353 * by the driver or software.
21354 * # Any driver or software should not make any assumptions about
21356 * # A value of 0xff indicates that the queue is not available.
21357 * # Available queues may not be in sequential order.
21360 /* This value is applicable to CoS queues only. */
21361 uint8_t queue_id3_service_profile;
21362 /* Lossy (best-effort) */
21363 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
21365 /* Lossless (legacy) */
21366 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
21368 /* Lossless RoCE */
21369 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
21371 /* Lossy RoCE CNP */
21372 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21375 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
21377 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21378 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
21380 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
21381 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
21383 * ID of CoS Queue 4.
21386 * # This ID can be used on any subsequent call to an hwrm command
21387 * that takes a queue id.
21388 * # IDs must always be queried by this command before any use
21389 * by the driver or software.
21390 * # Any driver or software should not make any assumptions about
21392 * # A value of 0xff indicates that the queue is not available.
21393 * # Available queues may not be in sequential order.
21396 /* This value is applicable to CoS queues only. */
21397 uint8_t queue_id4_service_profile;
21398 /* Lossy (best-effort) */
21399 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
21401 /* Lossless (legacy) */
21402 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
21404 /* Lossless RoCE */
21405 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
21407 /* Lossy RoCE CNP */
21408 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21411 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
21413 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21414 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
21416 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
21417 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
21419 * ID of CoS Queue 5.
21422 * # This ID can be used on any subsequent call to an hwrm command
21423 * that takes a queue id.
21424 * # IDs must always be queried by this command before any use
21425 * by the driver or software.
21426 * # Any driver or software should not make any assumptions about
21428 * # A value of 0xff indicates that the queue is not available.
21429 * # Available queues may not be in sequential order.
21432 /* This value is applicable to CoS queues only. */
21433 uint8_t queue_id5_service_profile;
21434 /* Lossy (best-effort) */
21435 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
21437 /* Lossless (legacy) */
21438 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
21440 /* Lossless RoCE */
21441 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
21443 /* Lossy RoCE CNP */
21444 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21447 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
21449 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21450 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
21452 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
21453 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
21455 * ID of CoS Queue 6.
21458 * # This ID can be used on any subsequent call to an hwrm command
21459 * that takes a queue id.
21460 * # IDs must always be queried by this command before any use
21461 * by the driver or software.
21462 * # Any driver or software should not make any assumptions about
21464 * # A value of 0xff indicates that the queue is not available.
21465 * # Available queues may not be in sequential order.
21468 /* This value is applicable to CoS queues only. */
21469 uint8_t queue_id6_service_profile;
21470 /* Lossy (best-effort) */
21471 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
21473 /* Lossless (legacy) */
21474 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
21476 /* Lossless RoCE */
21477 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
21479 /* Lossy RoCE CNP */
21480 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21483 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
21485 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21486 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
21488 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
21489 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
21491 * ID of CoS Queue 7.
21494 * # This ID can be used on any subsequent call to an hwrm command
21495 * that takes a queue id.
21496 * # IDs must always be queried by this command before any use
21497 * by the driver or software.
21498 * # Any driver or software should not make any assumptions about
21500 * # A value of 0xff indicates that the queue is not available.
21501 * # Available queues may not be in sequential order.
21504 /* This value is applicable to CoS queues only. */
21505 uint8_t queue_id7_service_profile;
21506 /* Lossy (best-effort) */
21507 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
21509 /* Lossless (legacy) */
21510 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
21512 /* Lossless RoCE */
21513 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
21515 /* Lossy RoCE CNP */
21516 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21519 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
21521 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21522 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
21524 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
21525 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
21527 * This field is used in Output records to indicate that the output
21528 * is completely written to RAM. This field should be read as '1'
21529 * to indicate that the output has been completely written.
21530 * When writing a command completion or response to an internal processor,
21531 * the order of writes has to be such that this field is written last.
21536 /*******************
21537 * hwrm_queue_qcfg *
21538 *******************/
21541 /* hwrm_queue_qcfg_input (size:192b/24B) */
21542 struct hwrm_queue_qcfg_input {
21543 /* The HWRM command request type. */
21546 * The completion ring to send the completion event on. This should
21547 * be the NQ ID returned from the `nq_alloc` HWRM command.
21549 uint16_t cmpl_ring;
21551 * The sequence ID is used by the driver for tracking multiple
21552 * commands. This ID is treated as opaque data by the firmware and
21553 * the value is returned in the `hwrm_resp_hdr` upon completion.
21557 * The target ID of the command:
21558 * * 0x0-0xFFF8 - The function ID
21559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21560 * * 0xFFFD - Reserved for user-space HWRM interface
21563 uint16_t target_id;
21565 * A physical address pointer pointing to a host buffer that the
21566 * command's response data will be written. This can be either a host
21567 * physical address (HPA) or a guest physical address (GPA) and must
21568 * point to a physically contiguous block of memory.
21570 uint64_t resp_addr;
21573 * Enumeration denoting the RX, TX type of the resource.
21574 * This enumeration is used for resources that are similar for both
21575 * TX and RX paths of the chip.
21577 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21579 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21581 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21582 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
21583 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
21584 /* Queue ID of the queue. */
21588 /* hwrm_queue_qcfg_output (size:128b/16B) */
21589 struct hwrm_queue_qcfg_output {
21590 /* The specific error status for the command. */
21591 uint16_t error_code;
21592 /* The HWRM command request type. */
21594 /* The sequence ID from the original command. */
21596 /* The length of the response data in number of bytes. */
21599 * This value is the estimate packet length used in the
21602 uint32_t queue_len;
21603 /* This value is applicable to CoS queues only. */
21604 uint8_t service_profile;
21605 /* Lossy (best-effort) */
21606 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
21608 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
21609 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21610 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
21611 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
21612 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
21613 /* Information about queue configuration. */
21614 uint8_t queue_cfg_info;
21616 * If this flag is set to '1', then the queue is
21617 * configured asymmetrically on TX and RX sides.
21618 * If this flag is set to '0', then this queue is
21619 * configured symmetrically on TX and RX sides.
21621 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21625 * This field is used in Output records to indicate that the output
21626 * is completely written to RAM. This field should be read as '1'
21627 * to indicate that the output has been completely written.
21628 * When writing a command completion or response to an internal processor,
21629 * the order of writes has to be such that this field is written last.
21634 /******************
21636 ******************/
21639 /* hwrm_queue_cfg_input (size:320b/40B) */
21640 struct hwrm_queue_cfg_input {
21641 /* The HWRM command request type. */
21644 * The completion ring to send the completion event on. This should
21645 * be the NQ ID returned from the `nq_alloc` HWRM command.
21647 uint16_t cmpl_ring;
21649 * The sequence ID is used by the driver for tracking multiple
21650 * commands. This ID is treated as opaque data by the firmware and
21651 * the value is returned in the `hwrm_resp_hdr` upon completion.
21655 * The target ID of the command:
21656 * * 0x0-0xFFF8 - The function ID
21657 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21658 * * 0xFFFD - Reserved for user-space HWRM interface
21661 uint16_t target_id;
21663 * A physical address pointer pointing to a host buffer that the
21664 * command's response data will be written. This can be either a host
21665 * physical address (HPA) or a guest physical address (GPA) and must
21666 * point to a physically contiguous block of memory.
21668 uint64_t resp_addr;
21671 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
21672 * This enumeration is used for resources that are similar for both
21673 * TX and RX paths of the chip.
21675 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
21676 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
21678 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21680 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21681 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
21682 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
21683 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
21684 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
21687 * This bit must be '1' for the dflt_len field to be
21690 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
21692 * This bit must be '1' for the service_profile field to be
21695 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
21696 /* Queue ID of queue that is to be configured by this function. */
21699 * This value is a the estimate packet length used in the
21701 * Set to 0xFF... (All Fs) to not adjust this value.
21704 /* This value is applicable to CoS queues only. */
21705 uint8_t service_profile;
21706 /* Lossy (best-effort) */
21707 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
21709 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
21710 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21711 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
21712 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
21713 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
21714 uint8_t unused_0[7];
21717 /* hwrm_queue_cfg_output (size:128b/16B) */
21718 struct hwrm_queue_cfg_output {
21719 /* The specific error status for the command. */
21720 uint16_t error_code;
21721 /* The HWRM command request type. */
21723 /* The sequence ID from the original command. */
21725 /* The length of the response data in number of bytes. */
21727 uint8_t unused_0[7];
21729 * This field is used in Output records to indicate that the output
21730 * is completely written to RAM. This field should be read as '1'
21731 * to indicate that the output has been completely written.
21732 * When writing a command completion or response to an internal processor,
21733 * the order of writes has to be such that this field is written last.
21738 /*****************************
21739 * hwrm_queue_pfcenable_qcfg *
21740 *****************************/
21743 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
21744 struct hwrm_queue_pfcenable_qcfg_input {
21745 /* The HWRM command request type. */
21748 * The completion ring to send the completion event on. This should
21749 * be the NQ ID returned from the `nq_alloc` HWRM command.
21751 uint16_t cmpl_ring;
21753 * The sequence ID is used by the driver for tracking multiple
21754 * commands. This ID is treated as opaque data by the firmware and
21755 * the value is returned in the `hwrm_resp_hdr` upon completion.
21759 * The target ID of the command:
21760 * * 0x0-0xFFF8 - The function ID
21761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21762 * * 0xFFFD - Reserved for user-space HWRM interface
21765 uint16_t target_id;
21767 * A physical address pointer pointing to a host buffer that the
21768 * command's response data will be written. This can be either a host
21769 * physical address (HPA) or a guest physical address (GPA) and must
21770 * point to a physically contiguous block of memory.
21772 uint64_t resp_addr;
21774 * Port ID of port for which the table is being configured.
21775 * The HWRM needs to check whether this function is allowed
21776 * to configure pri2cos mapping on this port.
21779 uint8_t unused_0[6];
21782 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
21783 struct hwrm_queue_pfcenable_qcfg_output {
21784 /* The specific error status for the command. */
21785 uint16_t error_code;
21786 /* The HWRM command request type. */
21788 /* The sequence ID from the original command. */
21790 /* The length of the response data in number of bytes. */
21793 /* If set to 1, then PFC is enabled on PRI 0. */
21794 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
21796 /* If set to 1, then PFC is enabled on PRI 1. */
21797 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
21799 /* If set to 1, then PFC is enabled on PRI 2. */
21800 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
21802 /* If set to 1, then PFC is enabled on PRI 3. */
21803 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
21805 /* If set to 1, then PFC is enabled on PRI 4. */
21806 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
21808 /* If set to 1, then PFC is enabled on PRI 5. */
21809 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
21811 /* If set to 1, then PFC is enabled on PRI 6. */
21812 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
21814 /* If set to 1, then PFC is enabled on PRI 7. */
21815 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
21817 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
21818 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
21820 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
21821 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
21823 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
21824 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
21826 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
21827 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
21829 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
21830 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
21832 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
21833 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
21835 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
21836 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
21838 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
21839 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
21841 uint8_t unused_0[3];
21843 * This field is used in Output records to indicate that the output
21844 * is completely written to RAM. This field should be read as '1'
21845 * to indicate that the output has been completely written.
21846 * When writing a command completion or response to an internal processor,
21847 * the order of writes has to be such that this field is written last.
21852 /****************************
21853 * hwrm_queue_pfcenable_cfg *
21854 ****************************/
21857 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
21858 struct hwrm_queue_pfcenable_cfg_input {
21859 /* The HWRM command request type. */
21862 * The completion ring to send the completion event on. This should
21863 * be the NQ ID returned from the `nq_alloc` HWRM command.
21865 uint16_t cmpl_ring;
21867 * The sequence ID is used by the driver for tracking multiple
21868 * commands. This ID is treated as opaque data by the firmware and
21869 * the value is returned in the `hwrm_resp_hdr` upon completion.
21873 * The target ID of the command:
21874 * * 0x0-0xFFF8 - The function ID
21875 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21876 * * 0xFFFD - Reserved for user-space HWRM interface
21879 uint16_t target_id;
21881 * A physical address pointer pointing to a host buffer that the
21882 * command's response data will be written. This can be either a host
21883 * physical address (HPA) or a guest physical address (GPA) and must
21884 * point to a physically contiguous block of memory.
21886 uint64_t resp_addr;
21888 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
21889 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
21891 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
21892 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
21894 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
21895 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
21897 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
21898 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
21900 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
21901 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
21903 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
21904 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
21906 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
21907 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
21909 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
21910 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
21912 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
21913 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
21915 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
21916 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
21918 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
21919 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
21921 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
21922 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
21924 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
21925 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
21927 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
21928 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
21930 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
21931 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
21933 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
21934 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
21937 * Port ID of port for which the table is being configured.
21938 * The HWRM needs to check whether this function is allowed
21939 * to configure pri2cos mapping on this port.
21942 uint8_t unused_0[2];
21945 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
21946 struct hwrm_queue_pfcenable_cfg_output {
21947 /* The specific error status for the command. */
21948 uint16_t error_code;
21949 /* The HWRM command request type. */
21951 /* The sequence ID from the original command. */
21953 /* The length of the response data in number of bytes. */
21955 uint8_t unused_0[7];
21957 * This field is used in Output records to indicate that the output
21958 * is completely written to RAM. This field should be read as '1'
21959 * to indicate that the output has been completely written.
21960 * When writing a command completion or response to an internal processor,
21961 * the order of writes has to be such that this field is written last.
21966 /***************************
21967 * hwrm_queue_pri2cos_qcfg *
21968 ***************************/
21971 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
21972 struct hwrm_queue_pri2cos_qcfg_input {
21973 /* The HWRM command request type. */
21976 * The completion ring to send the completion event on. This should
21977 * be the NQ ID returned from the `nq_alloc` HWRM command.
21979 uint16_t cmpl_ring;
21981 * The sequence ID is used by the driver for tracking multiple
21982 * commands. This ID is treated as opaque data by the firmware and
21983 * the value is returned in the `hwrm_resp_hdr` upon completion.
21987 * The target ID of the command:
21988 * * 0x0-0xFFF8 - The function ID
21989 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21990 * * 0xFFFD - Reserved for user-space HWRM interface
21993 uint16_t target_id;
21995 * A physical address pointer pointing to a host buffer that the
21996 * command's response data will be written. This can be either a host
21997 * physical address (HPA) or a guest physical address (GPA) and must
21998 * point to a physically contiguous block of memory.
22000 uint64_t resp_addr;
22003 * Enumeration denoting the RX, TX type of the resource.
22004 * This enumeration is used for resources that are similar for both
22005 * TX and RX paths of the chip.
22007 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
22009 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22011 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22012 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
22013 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
22015 * When this bit is set to '0', the query is
22016 * for PRI from tunnel headers.
22017 * When this bit is set to '1', the query is
22018 * for PRI from inner packet headers.
22020 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
22022 * Port ID of port for which the table is being configured.
22023 * The HWRM needs to check whether this function is allowed
22024 * to configure pri2cos mapping on this port.
22027 uint8_t unused_0[3];
22030 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
22031 struct hwrm_queue_pri2cos_qcfg_output {
22032 /* The specific error status for the command. */
22033 uint16_t error_code;
22034 /* The HWRM command request type. */
22036 /* The sequence ID from the original command. */
22038 /* The length of the response data in number of bytes. */
22041 * CoS Queue assigned to priority 0. This value can only
22042 * be changed before traffic has started.
22043 * A value of 0xff indicates that no CoS queue is assigned to the
22044 * specified priority.
22046 uint8_t pri0_cos_queue_id;
22048 * CoS Queue assigned to priority 1. This value can only
22049 * be changed before traffic has started.
22050 * A value of 0xff indicates that no CoS queue is assigned to the
22051 * specified priority.
22053 uint8_t pri1_cos_queue_id;
22055 * CoS Queue assigned to priority 2. This value can only
22056 * be changed before traffic has started.
22057 * A value of 0xff indicates that no CoS queue is assigned to the
22058 * specified priority.
22060 uint8_t pri2_cos_queue_id;
22062 * CoS Queue assigned to priority 3. This value can only
22063 * be changed before traffic has started.
22064 * A value of 0xff indicates that no CoS queue is assigned to the
22065 * specified priority.
22067 uint8_t pri3_cos_queue_id;
22069 * CoS Queue assigned to priority 4. This value can only
22070 * be changed before traffic has started.
22071 * A value of 0xff indicates that no CoS queue is assigned to the
22072 * specified priority.
22074 uint8_t pri4_cos_queue_id;
22076 * CoS Queue assigned to priority 5. This value can only
22077 * be changed before traffic has started.
22078 * A value of 0xff indicates that no CoS queue is assigned to the
22079 * specified priority.
22081 uint8_t pri5_cos_queue_id;
22083 * CoS Queue assigned to priority 6. This value can only
22084 * be changed before traffic has started.
22085 * A value of 0xff indicates that no CoS queue is assigned to the
22086 * specified priority.
22088 uint8_t pri6_cos_queue_id;
22090 * CoS Queue assigned to priority 7. This value can only
22091 * be changed before traffic has started.
22092 * A value of 0xff indicates that no CoS queue is assigned to the
22093 * specified priority.
22095 uint8_t pri7_cos_queue_id;
22096 /* Information about queue configuration. */
22097 uint8_t queue_cfg_info;
22099 * If this flag is set to '1', then the PRI to CoS
22100 * configuration is asymmetric on TX and RX sides.
22101 * If this flag is set to '0', then PRI to CoS configuration
22102 * is symmetric on TX and RX sides.
22104 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
22106 uint8_t unused_0[6];
22108 * This field is used in Output records to indicate that the output
22109 * is completely written to RAM. This field should be read as '1'
22110 * to indicate that the output has been completely written.
22111 * When writing a command completion or response to an internal processor,
22112 * the order of writes has to be such that this field is written last.
22117 /**************************
22118 * hwrm_queue_pri2cos_cfg *
22119 **************************/
22122 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
22123 struct hwrm_queue_pri2cos_cfg_input {
22124 /* The HWRM command request type. */
22127 * The completion ring to send the completion event on. This should
22128 * be the NQ ID returned from the `nq_alloc` HWRM command.
22130 uint16_t cmpl_ring;
22132 * The sequence ID is used by the driver for tracking multiple
22133 * commands. This ID is treated as opaque data by the firmware and
22134 * the value is returned in the `hwrm_resp_hdr` upon completion.
22138 * The target ID of the command:
22139 * * 0x0-0xFFF8 - The function ID
22140 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22141 * * 0xFFFD - Reserved for user-space HWRM interface
22144 uint16_t target_id;
22146 * A physical address pointer pointing to a host buffer that the
22147 * command's response data will be written. This can be either a host
22148 * physical address (HPA) or a guest physical address (GPA) and must
22149 * point to a physically contiguous block of memory.
22151 uint64_t resp_addr;
22154 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
22155 * This enumeration is used for resources that are similar for both
22156 * TX and RX paths of the chip.
22158 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22159 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
22161 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22163 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22164 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22165 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22166 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
22167 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
22169 * When this bit is set to '0', the mapping is requested
22170 * for PRI from tunnel headers.
22171 * When this bit is set to '1', the mapping is requested
22172 * for PRI from inner packet headers.
22174 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
22177 * This bit must be '1' for the pri0_cos_queue_id field to be
22180 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
22183 * This bit must be '1' for the pri1_cos_queue_id field to be
22186 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
22189 * This bit must be '1' for the pri2_cos_queue_id field to be
22192 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
22195 * This bit must be '1' for the pri3_cos_queue_id field to be
22198 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
22201 * This bit must be '1' for the pri4_cos_queue_id field to be
22204 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
22207 * This bit must be '1' for the pri5_cos_queue_id field to be
22210 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
22213 * This bit must be '1' for the pri6_cos_queue_id field to be
22216 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
22219 * This bit must be '1' for the pri7_cos_queue_id field to be
22222 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
22225 * Port ID of port for which the table is being configured.
22226 * The HWRM needs to check whether this function is allowed
22227 * to configure pri2cos mapping on this port.
22231 * CoS Queue assigned to priority 0. This value can only
22232 * be changed before traffic has started.
22234 uint8_t pri0_cos_queue_id;
22236 * CoS Queue assigned to priority 1. This value can only
22237 * be changed before traffic has started.
22239 uint8_t pri1_cos_queue_id;
22241 * CoS Queue assigned to priority 2 This value can only
22242 * be changed before traffic has started.
22244 uint8_t pri2_cos_queue_id;
22246 * CoS Queue assigned to priority 3. This value can only
22247 * be changed before traffic has started.
22249 uint8_t pri3_cos_queue_id;
22251 * CoS Queue assigned to priority 4. This value can only
22252 * be changed before traffic has started.
22254 uint8_t pri4_cos_queue_id;
22256 * CoS Queue assigned to priority 5. This value can only
22257 * be changed before traffic has started.
22259 uint8_t pri5_cos_queue_id;
22261 * CoS Queue assigned to priority 6. This value can only
22262 * be changed before traffic has started.
22264 uint8_t pri6_cos_queue_id;
22266 * CoS Queue assigned to priority 7. This value can only
22267 * be changed before traffic has started.
22269 uint8_t pri7_cos_queue_id;
22270 uint8_t unused_0[7];
22273 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
22274 struct hwrm_queue_pri2cos_cfg_output {
22275 /* The specific error status for the command. */
22276 uint16_t error_code;
22277 /* The HWRM command request type. */
22279 /* The sequence ID from the original command. */
22281 /* The length of the response data in number of bytes. */
22283 uint8_t unused_0[7];
22285 * This field is used in Output records to indicate that the output
22286 * is completely written to RAM. This field should be read as '1'
22287 * to indicate that the output has been completely written.
22288 * When writing a command completion or response to an internal processor,
22289 * the order of writes has to be such that this field is written last.
22294 /**************************
22295 * hwrm_queue_cos2bw_qcfg *
22296 **************************/
22299 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
22300 struct hwrm_queue_cos2bw_qcfg_input {
22301 /* The HWRM command request type. */
22304 * The completion ring to send the completion event on. This should
22305 * be the NQ ID returned from the `nq_alloc` HWRM command.
22307 uint16_t cmpl_ring;
22309 * The sequence ID is used by the driver for tracking multiple
22310 * commands. This ID is treated as opaque data by the firmware and
22311 * the value is returned in the `hwrm_resp_hdr` upon completion.
22315 * The target ID of the command:
22316 * * 0x0-0xFFF8 - The function ID
22317 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22318 * * 0xFFFD - Reserved for user-space HWRM interface
22321 uint16_t target_id;
22323 * A physical address pointer pointing to a host buffer that the
22324 * command's response data will be written. This can be either a host
22325 * physical address (HPA) or a guest physical address (GPA) and must
22326 * point to a physically contiguous block of memory.
22328 uint64_t resp_addr;
22330 * Port ID of port for which the table is being configured.
22331 * The HWRM needs to check whether this function is allowed
22332 * to configure TC BW assignment on this port.
22335 uint8_t unused_0[6];
22338 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
22339 struct hwrm_queue_cos2bw_qcfg_output {
22340 /* The specific error status for the command. */
22341 uint16_t error_code;
22342 /* The HWRM command request type. */
22344 /* The sequence ID from the original command. */
22346 /* The length of the response data in number of bytes. */
22348 /* ID of CoS Queue 0. */
22353 * Minimum BW allocated to CoS Queue.
22354 * The HWRM will translate this value into byte counter and
22355 * time interval used for this COS inside the device.
22357 uint32_t queue_id0_min_bw;
22358 /* The bandwidth value. */
22359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
22360 UINT32_C(0xfffffff)
22361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
22363 /* The granularity of the value (bits or bytes). */
22364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
22365 UINT32_C(0x10000000)
22366 /* Value is in bits. */
22367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
22368 (UINT32_C(0x0) << 28)
22369 /* Value is in bytes. */
22370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
22371 (UINT32_C(0x1) << 28)
22372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
22373 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
22374 /* bw_value_unit is 3 b */
22375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
22376 UINT32_C(0xe0000000)
22377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
22379 /* Value is in Mb or MB (base 10). */
22380 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
22381 (UINT32_C(0x0) << 29)
22382 /* Value is in Kb or KB (base 10). */
22383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
22384 (UINT32_C(0x2) << 29)
22385 /* Value is in bits or bytes. */
22386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
22387 (UINT32_C(0x4) << 29)
22388 /* Value is in Gb or GB (base 10). */
22389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
22390 (UINT32_C(0x6) << 29)
22391 /* Value is in 1/100th of a percentage of total bandwidth. */
22392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22393 (UINT32_C(0x1) << 29)
22395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
22396 (UINT32_C(0x7) << 29)
22397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
22398 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
22400 * Maximum BW allocated to CoS Queue.
22401 * The HWRM will translate this value into byte counter and
22402 * time interval used for this COS inside the device.
22404 uint32_t queue_id0_max_bw;
22405 /* The bandwidth value. */
22406 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
22407 UINT32_C(0xfffffff)
22408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
22410 /* The granularity of the value (bits or bytes). */
22411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
22412 UINT32_C(0x10000000)
22413 /* Value is in bits. */
22414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
22415 (UINT32_C(0x0) << 28)
22416 /* Value is in bytes. */
22417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
22418 (UINT32_C(0x1) << 28)
22419 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
22420 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
22421 /* bw_value_unit is 3 b */
22422 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
22423 UINT32_C(0xe0000000)
22424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
22426 /* Value is in Mb or MB (base 10). */
22427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
22428 (UINT32_C(0x0) << 29)
22429 /* Value is in Kb or KB (base 10). */
22430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
22431 (UINT32_C(0x2) << 29)
22432 /* Value is in bits or bytes. */
22433 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
22434 (UINT32_C(0x4) << 29)
22435 /* Value is in Gb or GB (base 10). */
22436 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
22437 (UINT32_C(0x6) << 29)
22438 /* Value is in 1/100th of a percentage of total bandwidth. */
22439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22440 (UINT32_C(0x1) << 29)
22442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
22443 (UINT32_C(0x7) << 29)
22444 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
22445 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
22446 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22447 uint8_t queue_id0_tsa_assign;
22448 /* Strict Priority */
22449 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
22451 /* Enhanced Transmission Selection */
22452 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
22455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
22458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
22461 * Priority level for strict priority. Valid only when the
22462 * tsa_assign is 0 - Strict Priority (SP)
22463 * 0..7 - Valid values.
22464 * 8..255 - Reserved.
22466 uint8_t queue_id0_pri_lvl;
22468 * Weight used to allocate remaining BW for this COS after
22469 * servicing guaranteed bandwidths for all COS.
22471 uint8_t queue_id0_bw_weight;
22472 /* ID of CoS Queue 1. */
22475 * Minimum BW allocated to CoS Queue.
22476 * The HWRM will translate this value into byte counter and
22477 * time interval used for this COS inside the device.
22479 uint32_t queue_id1_min_bw;
22480 /* The bandwidth value. */
22481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
22482 UINT32_C(0xfffffff)
22483 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
22485 /* The granularity of the value (bits or bytes). */
22486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
22487 UINT32_C(0x10000000)
22488 /* Value is in bits. */
22489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
22490 (UINT32_C(0x0) << 28)
22491 /* Value is in bytes. */
22492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
22493 (UINT32_C(0x1) << 28)
22494 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
22495 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
22496 /* bw_value_unit is 3 b */
22497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
22498 UINT32_C(0xe0000000)
22499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
22501 /* Value is in Mb or MB (base 10). */
22502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
22503 (UINT32_C(0x0) << 29)
22504 /* Value is in Kb or KB (base 10). */
22505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
22506 (UINT32_C(0x2) << 29)
22507 /* Value is in bits or bytes. */
22508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
22509 (UINT32_C(0x4) << 29)
22510 /* Value is in Gb or GB (base 10). */
22511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
22512 (UINT32_C(0x6) << 29)
22513 /* Value is in 1/100th of a percentage of total bandwidth. */
22514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22515 (UINT32_C(0x1) << 29)
22517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
22518 (UINT32_C(0x7) << 29)
22519 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
22520 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
22522 * Maximum BW allocated to CoS queue.
22523 * The HWRM will translate this value into byte counter and
22524 * time interval used for this COS inside the device.
22526 uint32_t queue_id1_max_bw;
22527 /* The bandwidth value. */
22528 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
22529 UINT32_C(0xfffffff)
22530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
22532 /* The granularity of the value (bits or bytes). */
22533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
22534 UINT32_C(0x10000000)
22535 /* Value is in bits. */
22536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
22537 (UINT32_C(0x0) << 28)
22538 /* Value is in bytes. */
22539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
22540 (UINT32_C(0x1) << 28)
22541 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
22542 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
22543 /* bw_value_unit is 3 b */
22544 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
22545 UINT32_C(0xe0000000)
22546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
22548 /* Value is in Mb or MB (base 10). */
22549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
22550 (UINT32_C(0x0) << 29)
22551 /* Value is in Kb or KB (base 10). */
22552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
22553 (UINT32_C(0x2) << 29)
22554 /* Value is in bits or bytes. */
22555 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
22556 (UINT32_C(0x4) << 29)
22557 /* Value is in Gb or GB (base 10). */
22558 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
22559 (UINT32_C(0x6) << 29)
22560 /* Value is in 1/100th of a percentage of total bandwidth. */
22561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22562 (UINT32_C(0x1) << 29)
22564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
22565 (UINT32_C(0x7) << 29)
22566 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
22567 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
22568 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22569 uint8_t queue_id1_tsa_assign;
22570 /* Strict Priority */
22571 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
22573 /* Enhanced Transmission Selection */
22574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
22577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
22580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
22583 * Priority level for strict priority. Valid only when the
22584 * tsa_assign is 0 - Strict Priority (SP)
22585 * 0..7 - Valid values.
22586 * 8..255 - Reserved.
22588 uint8_t queue_id1_pri_lvl;
22590 * Weight used to allocate remaining BW for this COS after
22591 * servicing guaranteed bandwidths for all COS.
22593 uint8_t queue_id1_bw_weight;
22594 /* ID of CoS Queue 2. */
22597 * Minimum BW allocated to CoS Queue.
22598 * The HWRM will translate this value into byte counter and
22599 * time interval used for this COS inside the device.
22601 uint32_t queue_id2_min_bw;
22602 /* The bandwidth value. */
22603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
22604 UINT32_C(0xfffffff)
22605 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
22607 /* The granularity of the value (bits or bytes). */
22608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
22609 UINT32_C(0x10000000)
22610 /* Value is in bits. */
22611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
22612 (UINT32_C(0x0) << 28)
22613 /* Value is in bytes. */
22614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
22615 (UINT32_C(0x1) << 28)
22616 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
22617 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
22618 /* bw_value_unit is 3 b */
22619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
22620 UINT32_C(0xe0000000)
22621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
22623 /* Value is in Mb or MB (base 10). */
22624 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
22625 (UINT32_C(0x0) << 29)
22626 /* Value is in Kb or KB (base 10). */
22627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
22628 (UINT32_C(0x2) << 29)
22629 /* Value is in bits or bytes. */
22630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
22631 (UINT32_C(0x4) << 29)
22632 /* Value is in Gb or GB (base 10). */
22633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
22634 (UINT32_C(0x6) << 29)
22635 /* Value is in 1/100th of a percentage of total bandwidth. */
22636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22637 (UINT32_C(0x1) << 29)
22639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
22640 (UINT32_C(0x7) << 29)
22641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
22642 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
22644 * Maximum BW allocated to CoS queue.
22645 * The HWRM will translate this value into byte counter and
22646 * time interval used for this COS inside the device.
22648 uint32_t queue_id2_max_bw;
22649 /* The bandwidth value. */
22650 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
22651 UINT32_C(0xfffffff)
22652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
22654 /* The granularity of the value (bits or bytes). */
22655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
22656 UINT32_C(0x10000000)
22657 /* Value is in bits. */
22658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
22659 (UINT32_C(0x0) << 28)
22660 /* Value is in bytes. */
22661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
22662 (UINT32_C(0x1) << 28)
22663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
22664 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
22665 /* bw_value_unit is 3 b */
22666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
22667 UINT32_C(0xe0000000)
22668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
22670 /* Value is in Mb or MB (base 10). */
22671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
22672 (UINT32_C(0x0) << 29)
22673 /* Value is in Kb or KB (base 10). */
22674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
22675 (UINT32_C(0x2) << 29)
22676 /* Value is in bits or bytes. */
22677 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
22678 (UINT32_C(0x4) << 29)
22679 /* Value is in Gb or GB (base 10). */
22680 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
22681 (UINT32_C(0x6) << 29)
22682 /* Value is in 1/100th of a percentage of total bandwidth. */
22683 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22684 (UINT32_C(0x1) << 29)
22686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
22687 (UINT32_C(0x7) << 29)
22688 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
22689 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
22690 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22691 uint8_t queue_id2_tsa_assign;
22692 /* Strict Priority */
22693 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
22695 /* Enhanced Transmission Selection */
22696 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
22699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
22702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
22705 * Priority level for strict priority. Valid only when the
22706 * tsa_assign is 0 - Strict Priority (SP)
22707 * 0..7 - Valid values.
22708 * 8..255 - Reserved.
22710 uint8_t queue_id2_pri_lvl;
22712 * Weight used to allocate remaining BW for this COS after
22713 * servicing guaranteed bandwidths for all COS.
22715 uint8_t queue_id2_bw_weight;
22716 /* ID of CoS Queue 3. */
22719 * Minimum BW allocated to CoS Queue.
22720 * The HWRM will translate this value into byte counter and
22721 * time interval used for this COS inside the device.
22723 uint32_t queue_id3_min_bw;
22724 /* The bandwidth value. */
22725 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
22726 UINT32_C(0xfffffff)
22727 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
22729 /* The granularity of the value (bits or bytes). */
22730 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
22731 UINT32_C(0x10000000)
22732 /* Value is in bits. */
22733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
22734 (UINT32_C(0x0) << 28)
22735 /* Value is in bytes. */
22736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
22737 (UINT32_C(0x1) << 28)
22738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
22739 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
22740 /* bw_value_unit is 3 b */
22741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
22742 UINT32_C(0xe0000000)
22743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
22745 /* Value is in Mb or MB (base 10). */
22746 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
22747 (UINT32_C(0x0) << 29)
22748 /* Value is in Kb or KB (base 10). */
22749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
22750 (UINT32_C(0x2) << 29)
22751 /* Value is in bits or bytes. */
22752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
22753 (UINT32_C(0x4) << 29)
22754 /* Value is in Gb or GB (base 10). */
22755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
22756 (UINT32_C(0x6) << 29)
22757 /* Value is in 1/100th of a percentage of total bandwidth. */
22758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22759 (UINT32_C(0x1) << 29)
22761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
22762 (UINT32_C(0x7) << 29)
22763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
22764 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
22766 * Maximum BW allocated to CoS queue.
22767 * The HWRM will translate this value into byte counter and
22768 * time interval used for this COS inside the device.
22770 uint32_t queue_id3_max_bw;
22771 /* The bandwidth value. */
22772 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
22773 UINT32_C(0xfffffff)
22774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
22776 /* The granularity of the value (bits or bytes). */
22777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
22778 UINT32_C(0x10000000)
22779 /* Value is in bits. */
22780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
22781 (UINT32_C(0x0) << 28)
22782 /* Value is in bytes. */
22783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
22784 (UINT32_C(0x1) << 28)
22785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
22786 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
22787 /* bw_value_unit is 3 b */
22788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
22789 UINT32_C(0xe0000000)
22790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
22792 /* Value is in Mb or MB (base 10). */
22793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
22794 (UINT32_C(0x0) << 29)
22795 /* Value is in Kb or KB (base 10). */
22796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
22797 (UINT32_C(0x2) << 29)
22798 /* Value is in bits or bytes. */
22799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
22800 (UINT32_C(0x4) << 29)
22801 /* Value is in Gb or GB (base 10). */
22802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
22803 (UINT32_C(0x6) << 29)
22804 /* Value is in 1/100th of a percentage of total bandwidth. */
22805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22806 (UINT32_C(0x1) << 29)
22808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
22809 (UINT32_C(0x7) << 29)
22810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
22811 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
22812 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22813 uint8_t queue_id3_tsa_assign;
22814 /* Strict Priority */
22815 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
22817 /* Enhanced Transmission Selection */
22818 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
22821 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
22824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
22827 * Priority level for strict priority. Valid only when the
22828 * tsa_assign is 0 - Strict Priority (SP)
22829 * 0..7 - Valid values.
22830 * 8..255 - Reserved.
22832 uint8_t queue_id3_pri_lvl;
22834 * Weight used to allocate remaining BW for this COS after
22835 * servicing guaranteed bandwidths for all COS.
22837 uint8_t queue_id3_bw_weight;
22838 /* ID of CoS Queue 4. */
22841 * Minimum BW allocated to CoS Queue.
22842 * The HWRM will translate this value into byte counter and
22843 * time interval used for this COS inside the device.
22845 uint32_t queue_id4_min_bw;
22846 /* The bandwidth value. */
22847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
22848 UINT32_C(0xfffffff)
22849 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
22851 /* The granularity of the value (bits or bytes). */
22852 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
22853 UINT32_C(0x10000000)
22854 /* Value is in bits. */
22855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
22856 (UINT32_C(0x0) << 28)
22857 /* Value is in bytes. */
22858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
22859 (UINT32_C(0x1) << 28)
22860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
22861 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
22862 /* bw_value_unit is 3 b */
22863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
22864 UINT32_C(0xe0000000)
22865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
22867 /* Value is in Mb or MB (base 10). */
22868 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
22869 (UINT32_C(0x0) << 29)
22870 /* Value is in Kb or KB (base 10). */
22871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
22872 (UINT32_C(0x2) << 29)
22873 /* Value is in bits or bytes. */
22874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
22875 (UINT32_C(0x4) << 29)
22876 /* Value is in Gb or GB (base 10). */
22877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
22878 (UINT32_C(0x6) << 29)
22879 /* Value is in 1/100th of a percentage of total bandwidth. */
22880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22881 (UINT32_C(0x1) << 29)
22883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
22884 (UINT32_C(0x7) << 29)
22885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
22886 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
22888 * Maximum BW allocated to CoS queue.
22889 * The HWRM will translate this value into byte counter and
22890 * time interval used for this COS inside the device.
22892 uint32_t queue_id4_max_bw;
22893 /* The bandwidth value. */
22894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
22895 UINT32_C(0xfffffff)
22896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
22898 /* The granularity of the value (bits or bytes). */
22899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
22900 UINT32_C(0x10000000)
22901 /* Value is in bits. */
22902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
22903 (UINT32_C(0x0) << 28)
22904 /* Value is in bytes. */
22905 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
22906 (UINT32_C(0x1) << 28)
22907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
22908 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
22909 /* bw_value_unit is 3 b */
22910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
22911 UINT32_C(0xe0000000)
22912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
22914 /* Value is in Mb or MB (base 10). */
22915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
22916 (UINT32_C(0x0) << 29)
22917 /* Value is in Kb or KB (base 10). */
22918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
22919 (UINT32_C(0x2) << 29)
22920 /* Value is in bits or bytes. */
22921 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
22922 (UINT32_C(0x4) << 29)
22923 /* Value is in Gb or GB (base 10). */
22924 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
22925 (UINT32_C(0x6) << 29)
22926 /* Value is in 1/100th of a percentage of total bandwidth. */
22927 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22928 (UINT32_C(0x1) << 29)
22930 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
22931 (UINT32_C(0x7) << 29)
22932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
22933 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
22934 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22935 uint8_t queue_id4_tsa_assign;
22936 /* Strict Priority */
22937 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
22939 /* Enhanced Transmission Selection */
22940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
22943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
22946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
22949 * Priority level for strict priority. Valid only when the
22950 * tsa_assign is 0 - Strict Priority (SP)
22951 * 0..7 - Valid values.
22952 * 8..255 - Reserved.
22954 uint8_t queue_id4_pri_lvl;
22956 * Weight used to allocate remaining BW for this COS after
22957 * servicing guaranteed bandwidths for all COS.
22959 uint8_t queue_id4_bw_weight;
22960 /* ID of CoS Queue 5. */
22963 * Minimum BW allocated to CoS Queue.
22964 * The HWRM will translate this value into byte counter and
22965 * time interval used for this COS inside the device.
22967 uint32_t queue_id5_min_bw;
22968 /* The bandwidth value. */
22969 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
22970 UINT32_C(0xfffffff)
22971 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
22973 /* The granularity of the value (bits or bytes). */
22974 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
22975 UINT32_C(0x10000000)
22976 /* Value is in bits. */
22977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
22978 (UINT32_C(0x0) << 28)
22979 /* Value is in bytes. */
22980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
22981 (UINT32_C(0x1) << 28)
22982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
22983 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
22984 /* bw_value_unit is 3 b */
22985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
22986 UINT32_C(0xe0000000)
22987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
22989 /* Value is in Mb or MB (base 10). */
22990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
22991 (UINT32_C(0x0) << 29)
22992 /* Value is in Kb or KB (base 10). */
22993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
22994 (UINT32_C(0x2) << 29)
22995 /* Value is in bits or bytes. */
22996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
22997 (UINT32_C(0x4) << 29)
22998 /* Value is in Gb or GB (base 10). */
22999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
23000 (UINT32_C(0x6) << 29)
23001 /* Value is in 1/100th of a percentage of total bandwidth. */
23002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23003 (UINT32_C(0x1) << 29)
23005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
23006 (UINT32_C(0x7) << 29)
23007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
23008 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
23010 * Maximum BW allocated to CoS queue.
23011 * The HWRM will translate this value into byte counter and
23012 * time interval used for this COS inside the device.
23014 uint32_t queue_id5_max_bw;
23015 /* The bandwidth value. */
23016 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
23017 UINT32_C(0xfffffff)
23018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
23020 /* The granularity of the value (bits or bytes). */
23021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
23022 UINT32_C(0x10000000)
23023 /* Value is in bits. */
23024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
23025 (UINT32_C(0x0) << 28)
23026 /* Value is in bytes. */
23027 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
23028 (UINT32_C(0x1) << 28)
23029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
23030 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
23031 /* bw_value_unit is 3 b */
23032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
23033 UINT32_C(0xe0000000)
23034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
23036 /* Value is in Mb or MB (base 10). */
23037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
23038 (UINT32_C(0x0) << 29)
23039 /* Value is in Kb or KB (base 10). */
23040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
23041 (UINT32_C(0x2) << 29)
23042 /* Value is in bits or bytes. */
23043 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
23044 (UINT32_C(0x4) << 29)
23045 /* Value is in Gb or GB (base 10). */
23046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
23047 (UINT32_C(0x6) << 29)
23048 /* Value is in 1/100th of a percentage of total bandwidth. */
23049 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23050 (UINT32_C(0x1) << 29)
23052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
23053 (UINT32_C(0x7) << 29)
23054 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
23055 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
23056 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23057 uint8_t queue_id5_tsa_assign;
23058 /* Strict Priority */
23059 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
23061 /* Enhanced Transmission Selection */
23062 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
23065 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
23068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
23071 * Priority level for strict priority. Valid only when the
23072 * tsa_assign is 0 - Strict Priority (SP)
23073 * 0..7 - Valid values.
23074 * 8..255 - Reserved.
23076 uint8_t queue_id5_pri_lvl;
23078 * Weight used to allocate remaining BW for this COS after
23079 * servicing guaranteed bandwidths for all COS.
23081 uint8_t queue_id5_bw_weight;
23082 /* ID of CoS Queue 6. */
23085 * Minimum BW allocated to CoS Queue.
23086 * The HWRM will translate this value into byte counter and
23087 * time interval used for this COS inside the device.
23089 uint32_t queue_id6_min_bw;
23090 /* The bandwidth value. */
23091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
23092 UINT32_C(0xfffffff)
23093 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
23095 /* The granularity of the value (bits or bytes). */
23096 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
23097 UINT32_C(0x10000000)
23098 /* Value is in bits. */
23099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
23100 (UINT32_C(0x0) << 28)
23101 /* Value is in bytes. */
23102 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
23103 (UINT32_C(0x1) << 28)
23104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
23105 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
23106 /* bw_value_unit is 3 b */
23107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
23108 UINT32_C(0xe0000000)
23109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
23111 /* Value is in Mb or MB (base 10). */
23112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
23113 (UINT32_C(0x0) << 29)
23114 /* Value is in Kb or KB (base 10). */
23115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
23116 (UINT32_C(0x2) << 29)
23117 /* Value is in bits or bytes. */
23118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
23119 (UINT32_C(0x4) << 29)
23120 /* Value is in Gb or GB (base 10). */
23121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
23122 (UINT32_C(0x6) << 29)
23123 /* Value is in 1/100th of a percentage of total bandwidth. */
23124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23125 (UINT32_C(0x1) << 29)
23127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
23128 (UINT32_C(0x7) << 29)
23129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
23130 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
23132 * Maximum BW allocated to CoS queue.
23133 * The HWRM will translate this value into byte counter and
23134 * time interval used for this COS inside the device.
23136 uint32_t queue_id6_max_bw;
23137 /* The bandwidth value. */
23138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
23139 UINT32_C(0xfffffff)
23140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
23142 /* The granularity of the value (bits or bytes). */
23143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
23144 UINT32_C(0x10000000)
23145 /* Value is in bits. */
23146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
23147 (UINT32_C(0x0) << 28)
23148 /* Value is in bytes. */
23149 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
23150 (UINT32_C(0x1) << 28)
23151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
23152 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
23153 /* bw_value_unit is 3 b */
23154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
23155 UINT32_C(0xe0000000)
23156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
23158 /* Value is in Mb or MB (base 10). */
23159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
23160 (UINT32_C(0x0) << 29)
23161 /* Value is in Kb or KB (base 10). */
23162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
23163 (UINT32_C(0x2) << 29)
23164 /* Value is in bits or bytes. */
23165 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
23166 (UINT32_C(0x4) << 29)
23167 /* Value is in Gb or GB (base 10). */
23168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
23169 (UINT32_C(0x6) << 29)
23170 /* Value is in 1/100th of a percentage of total bandwidth. */
23171 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23172 (UINT32_C(0x1) << 29)
23174 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
23175 (UINT32_C(0x7) << 29)
23176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
23177 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
23178 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23179 uint8_t queue_id6_tsa_assign;
23180 /* Strict Priority */
23181 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
23183 /* Enhanced Transmission Selection */
23184 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
23187 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
23190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
23193 * Priority level for strict priority. Valid only when the
23194 * tsa_assign is 0 - Strict Priority (SP)
23195 * 0..7 - Valid values.
23196 * 8..255 - Reserved.
23198 uint8_t queue_id6_pri_lvl;
23200 * Weight used to allocate remaining BW for this COS after
23201 * servicing guaranteed bandwidths for all COS.
23203 uint8_t queue_id6_bw_weight;
23204 /* ID of CoS Queue 7. */
23207 * Minimum BW allocated to CoS Queue.
23208 * The HWRM will translate this value into byte counter and
23209 * time interval used for this COS inside the device.
23211 uint32_t queue_id7_min_bw;
23212 /* The bandwidth value. */
23213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
23214 UINT32_C(0xfffffff)
23215 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
23217 /* The granularity of the value (bits or bytes). */
23218 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
23219 UINT32_C(0x10000000)
23220 /* Value is in bits. */
23221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
23222 (UINT32_C(0x0) << 28)
23223 /* Value is in bytes. */
23224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
23225 (UINT32_C(0x1) << 28)
23226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
23227 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
23228 /* bw_value_unit is 3 b */
23229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
23230 UINT32_C(0xe0000000)
23231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
23233 /* Value is in Mb or MB (base 10). */
23234 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
23235 (UINT32_C(0x0) << 29)
23236 /* Value is in Kb or KB (base 10). */
23237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
23238 (UINT32_C(0x2) << 29)
23239 /* Value is in bits or bytes. */
23240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
23241 (UINT32_C(0x4) << 29)
23242 /* Value is in Gb or GB (base 10). */
23243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
23244 (UINT32_C(0x6) << 29)
23245 /* Value is in 1/100th of a percentage of total bandwidth. */
23246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23247 (UINT32_C(0x1) << 29)
23249 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
23250 (UINT32_C(0x7) << 29)
23251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
23252 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
23254 * Maximum BW allocated to CoS queue.
23255 * The HWRM will translate this value into byte counter and
23256 * time interval used for this COS inside the device.
23258 uint32_t queue_id7_max_bw;
23259 /* The bandwidth value. */
23260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
23261 UINT32_C(0xfffffff)
23262 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
23264 /* The granularity of the value (bits or bytes). */
23265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
23266 UINT32_C(0x10000000)
23267 /* Value is in bits. */
23268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
23269 (UINT32_C(0x0) << 28)
23270 /* Value is in bytes. */
23271 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
23272 (UINT32_C(0x1) << 28)
23273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
23274 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
23275 /* bw_value_unit is 3 b */
23276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
23277 UINT32_C(0xe0000000)
23278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
23280 /* Value is in Mb or MB (base 10). */
23281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
23282 (UINT32_C(0x0) << 29)
23283 /* Value is in Kb or KB (base 10). */
23284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
23285 (UINT32_C(0x2) << 29)
23286 /* Value is in bits or bytes. */
23287 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
23288 (UINT32_C(0x4) << 29)
23289 /* Value is in Gb or GB (base 10). */
23290 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
23291 (UINT32_C(0x6) << 29)
23292 /* Value is in 1/100th of a percentage of total bandwidth. */
23293 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23294 (UINT32_C(0x1) << 29)
23296 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
23297 (UINT32_C(0x7) << 29)
23298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
23299 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
23300 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23301 uint8_t queue_id7_tsa_assign;
23302 /* Strict Priority */
23303 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
23305 /* Enhanced Transmission Selection */
23306 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
23309 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
23312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
23315 * Priority level for strict priority. Valid only when the
23316 * tsa_assign is 0 - Strict Priority (SP)
23317 * 0..7 - Valid values.
23318 * 8..255 - Reserved.
23320 uint8_t queue_id7_pri_lvl;
23322 * Weight used to allocate remaining BW for this COS after
23323 * servicing guaranteed bandwidths for all COS.
23325 uint8_t queue_id7_bw_weight;
23326 uint8_t unused_2[4];
23328 * This field is used in Output records to indicate that the output
23329 * is completely written to RAM. This field should be read as '1'
23330 * to indicate that the output has been completely written.
23331 * When writing a command completion or response to an internal processor,
23332 * the order of writes has to be such that this field is written last.
23337 /*************************
23338 * hwrm_queue_cos2bw_cfg *
23339 *************************/
23342 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
23343 struct hwrm_queue_cos2bw_cfg_input {
23344 /* The HWRM command request type. */
23347 * The completion ring to send the completion event on. This should
23348 * be the NQ ID returned from the `nq_alloc` HWRM command.
23350 uint16_t cmpl_ring;
23352 * The sequence ID is used by the driver for tracking multiple
23353 * commands. This ID is treated as opaque data by the firmware and
23354 * the value is returned in the `hwrm_resp_hdr` upon completion.
23358 * The target ID of the command:
23359 * * 0x0-0xFFF8 - The function ID
23360 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23361 * * 0xFFFD - Reserved for user-space HWRM interface
23364 uint16_t target_id;
23366 * A physical address pointer pointing to a host buffer that the
23367 * command's response data will be written. This can be either a host
23368 * physical address (HPA) or a guest physical address (GPA) and must
23369 * point to a physically contiguous block of memory.
23371 uint64_t resp_addr;
23375 * If this bit is set to 1, then all queue_id0 related
23376 * parameters in this command are valid.
23378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
23381 * If this bit is set to 1, then all queue_id1 related
23382 * parameters in this command are valid.
23384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
23387 * If this bit is set to 1, then all queue_id2 related
23388 * parameters in this command are valid.
23390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
23393 * If this bit is set to 1, then all queue_id3 related
23394 * parameters in this command are valid.
23396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
23399 * If this bit is set to 1, then all queue_id4 related
23400 * parameters in this command are valid.
23402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
23405 * If this bit is set to 1, then all queue_id5 related
23406 * parameters in this command are valid.
23408 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
23411 * If this bit is set to 1, then all queue_id6 related
23412 * parameters in this command are valid.
23414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
23417 * If this bit is set to 1, then all queue_id7 related
23418 * parameters in this command are valid.
23420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
23423 * Port ID of port for which the table is being configured.
23424 * The HWRM needs to check whether this function is allowed
23425 * to configure TC BW assignment on this port.
23428 /* ID of CoS Queue 0. */
23432 * Minimum BW allocated to CoS Queue.
23433 * The HWRM will translate this value into byte counter and
23434 * time interval used for this COS inside the device.
23436 uint32_t queue_id0_min_bw;
23437 /* The bandwidth value. */
23438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
23439 UINT32_C(0xfffffff)
23440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
23442 /* The granularity of the value (bits or bytes). */
23443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
23444 UINT32_C(0x10000000)
23445 /* Value is in bits. */
23446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
23447 (UINT32_C(0x0) << 28)
23448 /* Value is in bytes. */
23449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
23450 (UINT32_C(0x1) << 28)
23451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
23452 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
23453 /* bw_value_unit is 3 b */
23454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
23455 UINT32_C(0xe0000000)
23456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
23458 /* Value is in Mb or MB (base 10). */
23459 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
23460 (UINT32_C(0x0) << 29)
23461 /* Value is in Kb or KB (base 10). */
23462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
23463 (UINT32_C(0x2) << 29)
23464 /* Value is in bits or bytes. */
23465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
23466 (UINT32_C(0x4) << 29)
23467 /* Value is in Gb or GB (base 10). */
23468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
23469 (UINT32_C(0x6) << 29)
23470 /* Value is in 1/100th of a percentage of total bandwidth. */
23471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23472 (UINT32_C(0x1) << 29)
23474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
23475 (UINT32_C(0x7) << 29)
23476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
23477 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
23479 * Maximum BW allocated to CoS Queue.
23480 * The HWRM will translate this value into byte counter and
23481 * time interval used for this COS inside the device.
23483 uint32_t queue_id0_max_bw;
23484 /* The bandwidth value. */
23485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
23486 UINT32_C(0xfffffff)
23487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
23489 /* The granularity of the value (bits or bytes). */
23490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
23491 UINT32_C(0x10000000)
23492 /* Value is in bits. */
23493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
23494 (UINT32_C(0x0) << 28)
23495 /* Value is in bytes. */
23496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
23497 (UINT32_C(0x1) << 28)
23498 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
23499 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
23500 /* bw_value_unit is 3 b */
23501 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
23502 UINT32_C(0xe0000000)
23503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
23505 /* Value is in Mb or MB (base 10). */
23506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
23507 (UINT32_C(0x0) << 29)
23508 /* Value is in Kb or KB (base 10). */
23509 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
23510 (UINT32_C(0x2) << 29)
23511 /* Value is in bits or bytes. */
23512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
23513 (UINT32_C(0x4) << 29)
23514 /* Value is in Gb or GB (base 10). */
23515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
23516 (UINT32_C(0x6) << 29)
23517 /* Value is in 1/100th of a percentage of total bandwidth. */
23518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23519 (UINT32_C(0x1) << 29)
23521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
23522 (UINT32_C(0x7) << 29)
23523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
23524 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
23525 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23526 uint8_t queue_id0_tsa_assign;
23527 /* Strict Priority */
23528 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
23530 /* Enhanced Transmission Selection */
23531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
23534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
23537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
23540 * Priority level for strict priority. Valid only when the
23541 * tsa_assign is 0 - Strict Priority (SP)
23542 * 0..7 - Valid values.
23543 * 8..255 - Reserved.
23545 uint8_t queue_id0_pri_lvl;
23547 * Weight used to allocate remaining BW for this COS after
23548 * servicing guaranteed bandwidths for all COS.
23550 uint8_t queue_id0_bw_weight;
23551 /* ID of CoS Queue 1. */
23554 * Minimum BW allocated to CoS Queue.
23555 * The HWRM will translate this value into byte counter and
23556 * time interval used for this COS inside the device.
23558 uint32_t queue_id1_min_bw;
23559 /* The bandwidth value. */
23560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
23561 UINT32_C(0xfffffff)
23562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
23564 /* The granularity of the value (bits or bytes). */
23565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
23566 UINT32_C(0x10000000)
23567 /* Value is in bits. */
23568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
23569 (UINT32_C(0x0) << 28)
23570 /* Value is in bytes. */
23571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
23572 (UINT32_C(0x1) << 28)
23573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
23574 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
23575 /* bw_value_unit is 3 b */
23576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
23577 UINT32_C(0xe0000000)
23578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
23580 /* Value is in Mb or MB (base 10). */
23581 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
23582 (UINT32_C(0x0) << 29)
23583 /* Value is in Kb or KB (base 10). */
23584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
23585 (UINT32_C(0x2) << 29)
23586 /* Value is in bits or bytes. */
23587 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
23588 (UINT32_C(0x4) << 29)
23589 /* Value is in Gb or GB (base 10). */
23590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
23591 (UINT32_C(0x6) << 29)
23592 /* Value is in 1/100th of a percentage of total bandwidth. */
23593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23594 (UINT32_C(0x1) << 29)
23596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
23597 (UINT32_C(0x7) << 29)
23598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
23599 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
23601 * Maximum BW allocated to CoS queue.
23602 * The HWRM will translate this value into byte counter and
23603 * time interval used for this COS inside the device.
23605 uint32_t queue_id1_max_bw;
23606 /* The bandwidth value. */
23607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
23608 UINT32_C(0xfffffff)
23609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
23611 /* The granularity of the value (bits or bytes). */
23612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
23613 UINT32_C(0x10000000)
23614 /* Value is in bits. */
23615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
23616 (UINT32_C(0x0) << 28)
23617 /* Value is in bytes. */
23618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
23619 (UINT32_C(0x1) << 28)
23620 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
23621 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
23622 /* bw_value_unit is 3 b */
23623 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
23624 UINT32_C(0xe0000000)
23625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
23627 /* Value is in Mb or MB (base 10). */
23628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
23629 (UINT32_C(0x0) << 29)
23630 /* Value is in Kb or KB (base 10). */
23631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
23632 (UINT32_C(0x2) << 29)
23633 /* Value is in bits or bytes. */
23634 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
23635 (UINT32_C(0x4) << 29)
23636 /* Value is in Gb or GB (base 10). */
23637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
23638 (UINT32_C(0x6) << 29)
23639 /* Value is in 1/100th of a percentage of total bandwidth. */
23640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23641 (UINT32_C(0x1) << 29)
23643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
23644 (UINT32_C(0x7) << 29)
23645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
23646 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
23647 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23648 uint8_t queue_id1_tsa_assign;
23649 /* Strict Priority */
23650 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
23652 /* Enhanced Transmission Selection */
23653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
23656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
23659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
23662 * Priority level for strict priority. Valid only when the
23663 * tsa_assign is 0 - Strict Priority (SP)
23664 * 0..7 - Valid values.
23665 * 8..255 - Reserved.
23667 uint8_t queue_id1_pri_lvl;
23669 * Weight used to allocate remaining BW for this COS after
23670 * servicing guaranteed bandwidths for all COS.
23672 uint8_t queue_id1_bw_weight;
23673 /* ID of CoS Queue 2. */
23676 * Minimum BW allocated to CoS Queue.
23677 * The HWRM will translate this value into byte counter and
23678 * time interval used for this COS inside the device.
23680 uint32_t queue_id2_min_bw;
23681 /* The bandwidth value. */
23682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
23683 UINT32_C(0xfffffff)
23684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
23686 /* The granularity of the value (bits or bytes). */
23687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
23688 UINT32_C(0x10000000)
23689 /* Value is in bits. */
23690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
23691 (UINT32_C(0x0) << 28)
23692 /* Value is in bytes. */
23693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
23694 (UINT32_C(0x1) << 28)
23695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
23696 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
23697 /* bw_value_unit is 3 b */
23698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
23699 UINT32_C(0xe0000000)
23700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
23702 /* Value is in Mb or MB (base 10). */
23703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
23704 (UINT32_C(0x0) << 29)
23705 /* Value is in Kb or KB (base 10). */
23706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
23707 (UINT32_C(0x2) << 29)
23708 /* Value is in bits or bytes. */
23709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
23710 (UINT32_C(0x4) << 29)
23711 /* Value is in Gb or GB (base 10). */
23712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
23713 (UINT32_C(0x6) << 29)
23714 /* Value is in 1/100th of a percentage of total bandwidth. */
23715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23716 (UINT32_C(0x1) << 29)
23718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
23719 (UINT32_C(0x7) << 29)
23720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
23721 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
23723 * Maximum BW allocated to CoS queue.
23724 * The HWRM will translate this value into byte counter and
23725 * time interval used for this COS inside the device.
23727 uint32_t queue_id2_max_bw;
23728 /* The bandwidth value. */
23729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
23730 UINT32_C(0xfffffff)
23731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
23733 /* The granularity of the value (bits or bytes). */
23734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
23735 UINT32_C(0x10000000)
23736 /* Value is in bits. */
23737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
23738 (UINT32_C(0x0) << 28)
23739 /* Value is in bytes. */
23740 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
23741 (UINT32_C(0x1) << 28)
23742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
23743 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
23744 /* bw_value_unit is 3 b */
23745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
23746 UINT32_C(0xe0000000)
23747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
23749 /* Value is in Mb or MB (base 10). */
23750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
23751 (UINT32_C(0x0) << 29)
23752 /* Value is in Kb or KB (base 10). */
23753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
23754 (UINT32_C(0x2) << 29)
23755 /* Value is in bits or bytes. */
23756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
23757 (UINT32_C(0x4) << 29)
23758 /* Value is in Gb or GB (base 10). */
23759 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
23760 (UINT32_C(0x6) << 29)
23761 /* Value is in 1/100th of a percentage of total bandwidth. */
23762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23763 (UINT32_C(0x1) << 29)
23765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
23766 (UINT32_C(0x7) << 29)
23767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
23768 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
23769 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23770 uint8_t queue_id2_tsa_assign;
23771 /* Strict Priority */
23772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
23774 /* Enhanced Transmission Selection */
23775 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
23778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
23781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
23784 * Priority level for strict priority. Valid only when the
23785 * tsa_assign is 0 - Strict Priority (SP)
23786 * 0..7 - Valid values.
23787 * 8..255 - Reserved.
23789 uint8_t queue_id2_pri_lvl;
23791 * Weight used to allocate remaining BW for this COS after
23792 * servicing guaranteed bandwidths for all COS.
23794 uint8_t queue_id2_bw_weight;
23795 /* ID of CoS Queue 3. */
23798 * Minimum BW allocated to CoS Queue.
23799 * The HWRM will translate this value into byte counter and
23800 * time interval used for this COS inside the device.
23802 uint32_t queue_id3_min_bw;
23803 /* The bandwidth value. */
23804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
23805 UINT32_C(0xfffffff)
23806 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
23808 /* The granularity of the value (bits or bytes). */
23809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
23810 UINT32_C(0x10000000)
23811 /* Value is in bits. */
23812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
23813 (UINT32_C(0x0) << 28)
23814 /* Value is in bytes. */
23815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
23816 (UINT32_C(0x1) << 28)
23817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
23818 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
23819 /* bw_value_unit is 3 b */
23820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
23821 UINT32_C(0xe0000000)
23822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
23824 /* Value is in Mb or MB (base 10). */
23825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
23826 (UINT32_C(0x0) << 29)
23827 /* Value is in Kb or KB (base 10). */
23828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
23829 (UINT32_C(0x2) << 29)
23830 /* Value is in bits or bytes. */
23831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
23832 (UINT32_C(0x4) << 29)
23833 /* Value is in Gb or GB (base 10). */
23834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
23835 (UINT32_C(0x6) << 29)
23836 /* Value is in 1/100th of a percentage of total bandwidth. */
23837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23838 (UINT32_C(0x1) << 29)
23840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
23841 (UINT32_C(0x7) << 29)
23842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
23843 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
23845 * Maximum BW allocated to CoS queue.
23846 * The HWRM will translate this value into byte counter and
23847 * time interval used for this COS inside the device.
23849 uint32_t queue_id3_max_bw;
23850 /* The bandwidth value. */
23851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
23852 UINT32_C(0xfffffff)
23853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
23855 /* The granularity of the value (bits or bytes). */
23856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
23857 UINT32_C(0x10000000)
23858 /* Value is in bits. */
23859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
23860 (UINT32_C(0x0) << 28)
23861 /* Value is in bytes. */
23862 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
23863 (UINT32_C(0x1) << 28)
23864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
23865 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
23866 /* bw_value_unit is 3 b */
23867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
23868 UINT32_C(0xe0000000)
23869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
23871 /* Value is in Mb or MB (base 10). */
23872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
23873 (UINT32_C(0x0) << 29)
23874 /* Value is in Kb or KB (base 10). */
23875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
23876 (UINT32_C(0x2) << 29)
23877 /* Value is in bits or bytes. */
23878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
23879 (UINT32_C(0x4) << 29)
23880 /* Value is in Gb or GB (base 10). */
23881 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
23882 (UINT32_C(0x6) << 29)
23883 /* Value is in 1/100th of a percentage of total bandwidth. */
23884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23885 (UINT32_C(0x1) << 29)
23887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
23888 (UINT32_C(0x7) << 29)
23889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
23890 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
23891 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23892 uint8_t queue_id3_tsa_assign;
23893 /* Strict Priority */
23894 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
23896 /* Enhanced Transmission Selection */
23897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
23900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
23903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
23906 * Priority level for strict priority. Valid only when the
23907 * tsa_assign is 0 - Strict Priority (SP)
23908 * 0..7 - Valid values.
23909 * 8..255 - Reserved.
23911 uint8_t queue_id3_pri_lvl;
23913 * Weight used to allocate remaining BW for this COS after
23914 * servicing guaranteed bandwidths for all COS.
23916 uint8_t queue_id3_bw_weight;
23917 /* ID of CoS Queue 4. */
23920 * Minimum BW allocated to CoS Queue.
23921 * The HWRM will translate this value into byte counter and
23922 * time interval used for this COS inside the device.
23924 uint32_t queue_id4_min_bw;
23925 /* The bandwidth value. */
23926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
23927 UINT32_C(0xfffffff)
23928 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
23930 /* The granularity of the value (bits or bytes). */
23931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
23932 UINT32_C(0x10000000)
23933 /* Value is in bits. */
23934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
23935 (UINT32_C(0x0) << 28)
23936 /* Value is in bytes. */
23937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
23938 (UINT32_C(0x1) << 28)
23939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
23940 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
23941 /* bw_value_unit is 3 b */
23942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
23943 UINT32_C(0xe0000000)
23944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
23946 /* Value is in Mb or MB (base 10). */
23947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
23948 (UINT32_C(0x0) << 29)
23949 /* Value is in Kb or KB (base 10). */
23950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
23951 (UINT32_C(0x2) << 29)
23952 /* Value is in bits or bytes. */
23953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
23954 (UINT32_C(0x4) << 29)
23955 /* Value is in Gb or GB (base 10). */
23956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
23957 (UINT32_C(0x6) << 29)
23958 /* Value is in 1/100th of a percentage of total bandwidth. */
23959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23960 (UINT32_C(0x1) << 29)
23962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
23963 (UINT32_C(0x7) << 29)
23964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
23965 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
23967 * Maximum BW allocated to CoS queue.
23968 * The HWRM will translate this value into byte counter and
23969 * time interval used for this COS inside the device.
23971 uint32_t queue_id4_max_bw;
23972 /* The bandwidth value. */
23973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
23974 UINT32_C(0xfffffff)
23975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
23977 /* The granularity of the value (bits or bytes). */
23978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
23979 UINT32_C(0x10000000)
23980 /* Value is in bits. */
23981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
23982 (UINT32_C(0x0) << 28)
23983 /* Value is in bytes. */
23984 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
23985 (UINT32_C(0x1) << 28)
23986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
23987 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
23988 /* bw_value_unit is 3 b */
23989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
23990 UINT32_C(0xe0000000)
23991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
23993 /* Value is in Mb or MB (base 10). */
23994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
23995 (UINT32_C(0x0) << 29)
23996 /* Value is in Kb or KB (base 10). */
23997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
23998 (UINT32_C(0x2) << 29)
23999 /* Value is in bits or bytes. */
24000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
24001 (UINT32_C(0x4) << 29)
24002 /* Value is in Gb or GB (base 10). */
24003 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
24004 (UINT32_C(0x6) << 29)
24005 /* Value is in 1/100th of a percentage of total bandwidth. */
24006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24007 (UINT32_C(0x1) << 29)
24009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
24010 (UINT32_C(0x7) << 29)
24011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
24012 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
24013 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24014 uint8_t queue_id4_tsa_assign;
24015 /* Strict Priority */
24016 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
24018 /* Enhanced Transmission Selection */
24019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
24022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
24025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
24028 * Priority level for strict priority. Valid only when the
24029 * tsa_assign is 0 - Strict Priority (SP)
24030 * 0..7 - Valid values.
24031 * 8..255 - Reserved.
24033 uint8_t queue_id4_pri_lvl;
24035 * Weight used to allocate remaining BW for this COS after
24036 * servicing guaranteed bandwidths for all COS.
24038 uint8_t queue_id4_bw_weight;
24039 /* ID of CoS Queue 5. */
24042 * Minimum BW allocated to CoS Queue.
24043 * The HWRM will translate this value into byte counter and
24044 * time interval used for this COS inside the device.
24046 uint32_t queue_id5_min_bw;
24047 /* The bandwidth value. */
24048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
24049 UINT32_C(0xfffffff)
24050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
24052 /* The granularity of the value (bits or bytes). */
24053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
24054 UINT32_C(0x10000000)
24055 /* Value is in bits. */
24056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
24057 (UINT32_C(0x0) << 28)
24058 /* Value is in bytes. */
24059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
24060 (UINT32_C(0x1) << 28)
24061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
24062 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
24063 /* bw_value_unit is 3 b */
24064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
24065 UINT32_C(0xe0000000)
24066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
24068 /* Value is in Mb or MB (base 10). */
24069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
24070 (UINT32_C(0x0) << 29)
24071 /* Value is in Kb or KB (base 10). */
24072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
24073 (UINT32_C(0x2) << 29)
24074 /* Value is in bits or bytes. */
24075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
24076 (UINT32_C(0x4) << 29)
24077 /* Value is in Gb or GB (base 10). */
24078 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
24079 (UINT32_C(0x6) << 29)
24080 /* Value is in 1/100th of a percentage of total bandwidth. */
24081 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24082 (UINT32_C(0x1) << 29)
24084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
24085 (UINT32_C(0x7) << 29)
24086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
24087 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
24089 * Maximum BW allocated to CoS queue.
24090 * The HWRM will translate this value into byte counter and
24091 * time interval used for this COS inside the device.
24093 uint32_t queue_id5_max_bw;
24094 /* The bandwidth value. */
24095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
24096 UINT32_C(0xfffffff)
24097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
24099 /* The granularity of the value (bits or bytes). */
24100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
24101 UINT32_C(0x10000000)
24102 /* Value is in bits. */
24103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
24104 (UINT32_C(0x0) << 28)
24105 /* Value is in bytes. */
24106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
24107 (UINT32_C(0x1) << 28)
24108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
24109 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
24110 /* bw_value_unit is 3 b */
24111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
24112 UINT32_C(0xe0000000)
24113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
24115 /* Value is in Mb or MB (base 10). */
24116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
24117 (UINT32_C(0x0) << 29)
24118 /* Value is in Kb or KB (base 10). */
24119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
24120 (UINT32_C(0x2) << 29)
24121 /* Value is in bits or bytes. */
24122 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
24123 (UINT32_C(0x4) << 29)
24124 /* Value is in Gb or GB (base 10). */
24125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
24126 (UINT32_C(0x6) << 29)
24127 /* Value is in 1/100th of a percentage of total bandwidth. */
24128 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24129 (UINT32_C(0x1) << 29)
24131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
24132 (UINT32_C(0x7) << 29)
24133 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
24134 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
24135 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24136 uint8_t queue_id5_tsa_assign;
24137 /* Strict Priority */
24138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
24140 /* Enhanced Transmission Selection */
24141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
24144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
24147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
24150 * Priority level for strict priority. Valid only when the
24151 * tsa_assign is 0 - Strict Priority (SP)
24152 * 0..7 - Valid values.
24153 * 8..255 - Reserved.
24155 uint8_t queue_id5_pri_lvl;
24157 * Weight used to allocate remaining BW for this COS after
24158 * servicing guaranteed bandwidths for all COS.
24160 uint8_t queue_id5_bw_weight;
24161 /* ID of CoS Queue 6. */
24164 * Minimum BW allocated to CoS Queue.
24165 * The HWRM will translate this value into byte counter and
24166 * time interval used for this COS inside the device.
24168 uint32_t queue_id6_min_bw;
24169 /* The bandwidth value. */
24170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
24171 UINT32_C(0xfffffff)
24172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
24174 /* The granularity of the value (bits or bytes). */
24175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
24176 UINT32_C(0x10000000)
24177 /* Value is in bits. */
24178 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
24179 (UINT32_C(0x0) << 28)
24180 /* Value is in bytes. */
24181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
24182 (UINT32_C(0x1) << 28)
24183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
24184 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
24185 /* bw_value_unit is 3 b */
24186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
24187 UINT32_C(0xe0000000)
24188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
24190 /* Value is in Mb or MB (base 10). */
24191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
24192 (UINT32_C(0x0) << 29)
24193 /* Value is in Kb or KB (base 10). */
24194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
24195 (UINT32_C(0x2) << 29)
24196 /* Value is in bits or bytes. */
24197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
24198 (UINT32_C(0x4) << 29)
24199 /* Value is in Gb or GB (base 10). */
24200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
24201 (UINT32_C(0x6) << 29)
24202 /* Value is in 1/100th of a percentage of total bandwidth. */
24203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24204 (UINT32_C(0x1) << 29)
24206 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
24207 (UINT32_C(0x7) << 29)
24208 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
24209 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
24211 * Maximum BW allocated to CoS queue.
24212 * The HWRM will translate this value into byte counter and
24213 * time interval used for this COS inside the device.
24215 uint32_t queue_id6_max_bw;
24216 /* The bandwidth value. */
24217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
24218 UINT32_C(0xfffffff)
24219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
24221 /* The granularity of the value (bits or bytes). */
24222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
24223 UINT32_C(0x10000000)
24224 /* Value is in bits. */
24225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
24226 (UINT32_C(0x0) << 28)
24227 /* Value is in bytes. */
24228 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
24229 (UINT32_C(0x1) << 28)
24230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
24231 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
24232 /* bw_value_unit is 3 b */
24233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
24234 UINT32_C(0xe0000000)
24235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
24237 /* Value is in Mb or MB (base 10). */
24238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
24239 (UINT32_C(0x0) << 29)
24240 /* Value is in Kb or KB (base 10). */
24241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
24242 (UINT32_C(0x2) << 29)
24243 /* Value is in bits or bytes. */
24244 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
24245 (UINT32_C(0x4) << 29)
24246 /* Value is in Gb or GB (base 10). */
24247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
24248 (UINT32_C(0x6) << 29)
24249 /* Value is in 1/100th of a percentage of total bandwidth. */
24250 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24251 (UINT32_C(0x1) << 29)
24253 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
24254 (UINT32_C(0x7) << 29)
24255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
24256 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
24257 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24258 uint8_t queue_id6_tsa_assign;
24259 /* Strict Priority */
24260 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
24262 /* Enhanced Transmission Selection */
24263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
24266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
24269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
24272 * Priority level for strict priority. Valid only when the
24273 * tsa_assign is 0 - Strict Priority (SP)
24274 * 0..7 - Valid values.
24275 * 8..255 - Reserved.
24277 uint8_t queue_id6_pri_lvl;
24279 * Weight used to allocate remaining BW for this COS after
24280 * servicing guaranteed bandwidths for all COS.
24282 uint8_t queue_id6_bw_weight;
24283 /* ID of CoS Queue 7. */
24286 * Minimum BW allocated to CoS Queue.
24287 * The HWRM will translate this value into byte counter and
24288 * time interval used for this COS inside the device.
24290 uint32_t queue_id7_min_bw;
24291 /* The bandwidth value. */
24292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
24293 UINT32_C(0xfffffff)
24294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
24296 /* The granularity of the value (bits or bytes). */
24297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
24298 UINT32_C(0x10000000)
24299 /* Value is in bits. */
24300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
24301 (UINT32_C(0x0) << 28)
24302 /* Value is in bytes. */
24303 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
24304 (UINT32_C(0x1) << 28)
24305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
24306 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
24307 /* bw_value_unit is 3 b */
24308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
24309 UINT32_C(0xe0000000)
24310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
24312 /* Value is in Mb or MB (base 10). */
24313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
24314 (UINT32_C(0x0) << 29)
24315 /* Value is in Kb or KB (base 10). */
24316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
24317 (UINT32_C(0x2) << 29)
24318 /* Value is in bits or bytes. */
24319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
24320 (UINT32_C(0x4) << 29)
24321 /* Value is in Gb or GB (base 10). */
24322 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
24323 (UINT32_C(0x6) << 29)
24324 /* Value is in 1/100th of a percentage of total bandwidth. */
24325 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24326 (UINT32_C(0x1) << 29)
24328 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
24329 (UINT32_C(0x7) << 29)
24330 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
24331 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
24333 * Maximum BW allocated to CoS queue.
24334 * The HWRM will translate this value into byte counter and
24335 * time interval used for this COS inside the device.
24337 uint32_t queue_id7_max_bw;
24338 /* The bandwidth value. */
24339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
24340 UINT32_C(0xfffffff)
24341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
24343 /* The granularity of the value (bits or bytes). */
24344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
24345 UINT32_C(0x10000000)
24346 /* Value is in bits. */
24347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
24348 (UINT32_C(0x0) << 28)
24349 /* Value is in bytes. */
24350 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
24351 (UINT32_C(0x1) << 28)
24352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
24353 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
24354 /* bw_value_unit is 3 b */
24355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
24356 UINT32_C(0xe0000000)
24357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
24359 /* Value is in Mb or MB (base 10). */
24360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
24361 (UINT32_C(0x0) << 29)
24362 /* Value is in Kb or KB (base 10). */
24363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
24364 (UINT32_C(0x2) << 29)
24365 /* Value is in bits or bytes. */
24366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
24367 (UINT32_C(0x4) << 29)
24368 /* Value is in Gb or GB (base 10). */
24369 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
24370 (UINT32_C(0x6) << 29)
24371 /* Value is in 1/100th of a percentage of total bandwidth. */
24372 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24373 (UINT32_C(0x1) << 29)
24375 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
24376 (UINT32_C(0x7) << 29)
24377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
24378 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
24379 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24380 uint8_t queue_id7_tsa_assign;
24381 /* Strict Priority */
24382 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
24384 /* Enhanced Transmission Selection */
24385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
24388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
24391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
24394 * Priority level for strict priority. Valid only when the
24395 * tsa_assign is 0 - Strict Priority (SP)
24396 * 0..7 - Valid values.
24397 * 8..255 - Reserved.
24399 uint8_t queue_id7_pri_lvl;
24401 * Weight used to allocate remaining BW for this COS after
24402 * servicing guaranteed bandwidths for all COS.
24404 uint8_t queue_id7_bw_weight;
24405 uint8_t unused_1[5];
24408 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
24409 struct hwrm_queue_cos2bw_cfg_output {
24410 /* The specific error status for the command. */
24411 uint16_t error_code;
24412 /* The HWRM command request type. */
24414 /* The sequence ID from the original command. */
24416 /* The length of the response data in number of bytes. */
24418 uint8_t unused_0[7];
24420 * This field is used in Output records to indicate that the output
24421 * is completely written to RAM. This field should be read as '1'
24422 * to indicate that the output has been completely written.
24423 * When writing a command completion or response to an internal processor,
24424 * the order of writes has to be such that this field is written last.
24429 /*************************
24430 * hwrm_queue_dscp_qcaps *
24431 *************************/
24434 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
24435 struct hwrm_queue_dscp_qcaps_input {
24436 /* The HWRM command request type. */
24439 * The completion ring to send the completion event on. This should
24440 * be the NQ ID returned from the `nq_alloc` HWRM command.
24442 uint16_t cmpl_ring;
24444 * The sequence ID is used by the driver for tracking multiple
24445 * commands. This ID is treated as opaque data by the firmware and
24446 * the value is returned in the `hwrm_resp_hdr` upon completion.
24450 * The target ID of the command:
24451 * * 0x0-0xFFF8 - The function ID
24452 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24453 * * 0xFFFD - Reserved for user-space HWRM interface
24456 uint16_t target_id;
24458 * A physical address pointer pointing to a host buffer that the
24459 * command's response data will be written. This can be either a host
24460 * physical address (HPA) or a guest physical address (GPA) and must
24461 * point to a physically contiguous block of memory.
24463 uint64_t resp_addr;
24465 * Port ID of port for which the table is being configured.
24466 * The HWRM needs to check whether this function is allowed
24467 * to configure pri2cos mapping on this port.
24470 uint8_t unused_0[7];
24473 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
24474 struct hwrm_queue_dscp_qcaps_output {
24475 /* The specific error status for the command. */
24476 uint16_t error_code;
24477 /* The HWRM command request type. */
24479 /* The sequence ID from the original command. */
24481 /* The length of the response data in number of bytes. */
24483 /* The number of bits provided by the hardware for the DSCP value. */
24484 uint8_t num_dscp_bits;
24486 /* Max number of DSCP-MASK-PRI entries supported. */
24487 uint16_t max_entries;
24488 uint8_t unused_1[3];
24490 * This field is used in Output records to indicate that the output
24491 * is completely written to RAM. This field should be read as '1'
24492 * to indicate that the output has been completely written.
24493 * When writing a command completion or response to an internal processor,
24494 * the order of writes has to be such that this field is written last.
24499 /****************************
24500 * hwrm_queue_dscp2pri_qcfg *
24501 ****************************/
24504 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
24505 struct hwrm_queue_dscp2pri_qcfg_input {
24506 /* The HWRM command request type. */
24509 * The completion ring to send the completion event on. This should
24510 * be the NQ ID returned from the `nq_alloc` HWRM command.
24512 uint16_t cmpl_ring;
24514 * The sequence ID is used by the driver for tracking multiple
24515 * commands. This ID is treated as opaque data by the firmware and
24516 * the value is returned in the `hwrm_resp_hdr` upon completion.
24520 * The target ID of the command:
24521 * * 0x0-0xFFF8 - The function ID
24522 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24523 * * 0xFFFD - Reserved for user-space HWRM interface
24526 uint16_t target_id;
24528 * A physical address pointer pointing to a host buffer that the
24529 * command's response data will be written. This can be either a host
24530 * physical address (HPA) or a guest physical address (GPA) and must
24531 * point to a physically contiguous block of memory.
24533 uint64_t resp_addr;
24535 * This is the host address where the 24-bits DSCP-MASK-PRI
24536 * tuple(s) will be copied to.
24538 uint64_t dest_data_addr;
24540 * Port ID of port for which the table is being configured.
24541 * The HWRM needs to check whether this function is allowed
24542 * to configure pri2cos mapping on this port.
24546 /* Size of the buffer pointed to by dest_data_addr. */
24547 uint16_t dest_data_buffer_size;
24548 uint8_t unused_1[4];
24551 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
24552 struct hwrm_queue_dscp2pri_qcfg_output {
24553 /* The specific error status for the command. */
24554 uint16_t error_code;
24555 /* The HWRM command request type. */
24557 /* The sequence ID from the original command. */
24559 /* The length of the response data in number of bytes. */
24562 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
24563 * by the dest_data_addr.
24565 uint16_t entry_cnt;
24567 * This is the default PRI which un-initialized DSCP values are
24570 uint8_t default_pri;
24571 uint8_t unused_0[4];
24573 * This field is used in Output records to indicate that the output
24574 * is completely written to RAM. This field should be read as '1'
24575 * to indicate that the output has been completely written.
24576 * When writing a command completion or response to an internal processor,
24577 * the order of writes has to be such that this field is written last.
24582 /***************************
24583 * hwrm_queue_dscp2pri_cfg *
24584 ***************************/
24587 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
24588 struct hwrm_queue_dscp2pri_cfg_input {
24589 /* The HWRM command request type. */
24592 * The completion ring to send the completion event on. This should
24593 * be the NQ ID returned from the `nq_alloc` HWRM command.
24595 uint16_t cmpl_ring;
24597 * The sequence ID is used by the driver for tracking multiple
24598 * commands. This ID is treated as opaque data by the firmware and
24599 * the value is returned in the `hwrm_resp_hdr` upon completion.
24603 * The target ID of the command:
24604 * * 0x0-0xFFF8 - The function ID
24605 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24606 * * 0xFFFD - Reserved for user-space HWRM interface
24609 uint16_t target_id;
24611 * A physical address pointer pointing to a host buffer that the
24612 * command's response data will be written. This can be either a host
24613 * physical address (HPA) or a guest physical address (GPA) and must
24614 * point to a physically contiguous block of memory.
24616 uint64_t resp_addr;
24618 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
24619 * will be copied from.
24621 uint64_t src_data_addr;
24623 /* use_hw_default_pri is 1 b */
24624 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
24628 * This bit must be '1' for the default_pri field to be
24631 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
24634 * Port ID of port for which the table is being configured.
24635 * The HWRM needs to check whether this function is allowed
24636 * to configure pri2cos mapping on this port.
24640 * This is the default PRI which un-initialized DSCP values will be
24643 uint8_t default_pri;
24645 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
24646 * to by src_data_addr.
24648 uint16_t entry_cnt;
24649 uint8_t unused_0[4];
24652 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
24653 struct hwrm_queue_dscp2pri_cfg_output {
24654 /* The specific error status for the command. */
24655 uint16_t error_code;
24656 /* The HWRM command request type. */
24658 /* The sequence ID from the original command. */
24660 /* The length of the response data in number of bytes. */
24662 uint8_t unused_0[7];
24664 * This field is used in Output records to indicate that the output
24665 * is completely written to RAM. This field should be read as '1'
24666 * to indicate that the output has been completely written.
24667 * When writing a command completion or response to an internal processor,
24668 * the order of writes has to be such that this field is written last.
24673 /*************************
24674 * hwrm_queue_mpls_qcaps *
24675 *************************/
24678 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
24679 struct hwrm_queue_mpls_qcaps_input {
24680 /* The HWRM command request type. */
24683 * The completion ring to send the completion event on. This should
24684 * be the NQ ID returned from the `nq_alloc` HWRM command.
24686 uint16_t cmpl_ring;
24688 * The sequence ID is used by the driver for tracking multiple
24689 * commands. This ID is treated as opaque data by the firmware and
24690 * the value is returned in the `hwrm_resp_hdr` upon completion.
24694 * The target ID of the command:
24695 * * 0x0-0xFFF8 - The function ID
24696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24697 * * 0xFFFD - Reserved for user-space HWRM interface
24700 uint16_t target_id;
24702 * A physical address pointer pointing to a host buffer that the
24703 * command's response data will be written. This can be either a host
24704 * physical address (HPA) or a guest physical address (GPA) and must
24705 * point to a physically contiguous block of memory.
24707 uint64_t resp_addr;
24709 * Port ID of port for which the table is being configured.
24710 * The HWRM needs to check whether this function is allowed
24711 * to configure MPLS TC(EXP) to pri mapping on this port.
24714 uint8_t unused_0[7];
24717 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
24718 struct hwrm_queue_mpls_qcaps_output {
24719 /* The specific error status for the command. */
24720 uint16_t error_code;
24721 /* The HWRM command request type. */
24723 /* The sequence ID from the original command. */
24725 /* The length of the response data in number of bytes. */
24728 * Bitmask indicating which queues can be configured by the
24729 * hwrm_queue_mplstc2pri_cfg command.
24731 * Each bit represents a specific pri where bit 0 represents
24732 * pri 0 and bit 7 represents pri 7.
24733 * # A value of 0 indicates that the pri is not configurable
24734 * by the hwrm_queue_mplstc2pri_cfg command.
24735 * # A value of 1 indicates that the pri is configurable.
24736 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
24737 * trying to configure a pri that is not configurable.
24739 uint8_t queue_mplstc2pri_cfg_allowed;
24741 * This is the default PRI which un-initialized MPLS values will be
24744 uint8_t hw_default_pri;
24745 uint8_t unused_0[5];
24747 * This field is used in Output records to indicate that the output
24748 * is completely written to RAM. This field should be read as '1'
24749 * to indicate that the output has been completely written.
24750 * When writing a command completion or response to an internal processor,
24751 * the order of writes has to be such that this field is written last.
24756 /******************************
24757 * hwrm_queue_mplstc2pri_qcfg *
24758 ******************************/
24761 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
24762 struct hwrm_queue_mplstc2pri_qcfg_input {
24763 /* The HWRM command request type. */
24766 * The completion ring to send the completion event on. This should
24767 * be the NQ ID returned from the `nq_alloc` HWRM command.
24769 uint16_t cmpl_ring;
24771 * The sequence ID is used by the driver for tracking multiple
24772 * commands. This ID is treated as opaque data by the firmware and
24773 * the value is returned in the `hwrm_resp_hdr` upon completion.
24777 * The target ID of the command:
24778 * * 0x0-0xFFF8 - The function ID
24779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24780 * * 0xFFFD - Reserved for user-space HWRM interface
24783 uint16_t target_id;
24785 * A physical address pointer pointing to a host buffer that the
24786 * command's response data will be written. This can be either a host
24787 * physical address (HPA) or a guest physical address (GPA) and must
24788 * point to a physically contiguous block of memory.
24790 uint64_t resp_addr;
24792 * Port ID of port for which the table is being configured.
24793 * The HWRM needs to check whether this function is allowed
24794 * to configure MPLS TC(EXP) to pri mapping on this port.
24797 uint8_t unused_0[7];
24800 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
24801 struct hwrm_queue_mplstc2pri_qcfg_output {
24802 /* The specific error status for the command. */
24803 uint16_t error_code;
24804 /* The HWRM command request type. */
24806 /* The sequence ID from the original command. */
24808 /* The length of the response data in number of bytes. */
24811 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
24812 * before traffic has started.
24813 * A value of 0xff indicates that no pri is assigned to the
24816 uint8_t tc0_pri_queue_id;
24818 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
24819 * before traffic has started.
24820 * A value of 0xff indicates that no pri is assigned to the
24823 uint8_t tc1_pri_queue_id;
24825 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
24826 * before traffic has started.
24827 * A value of 0xff indicates that no pri is assigned to the
24830 uint8_t tc2_pri_queue_id;
24832 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
24833 * before traffic has started.
24834 * A value of 0xff indicates that no pri is assigned to the
24837 uint8_t tc3_pri_queue_id;
24839 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
24840 * before traffic has started.
24841 * A value of 0xff indicates that no pri is assigned to the
24844 uint8_t tc4_pri_queue_id;
24846 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
24847 * before traffic has started.
24848 * A value of 0xff indicates that no pri is assigned to the
24851 uint8_t tc5_pri_queue_id;
24853 * pri assigned to MPLS TC(EXP) 6. This value can only
24854 * be changed before traffic has started.
24855 * A value of 0xff indicates that no pri is assigned to the
24858 uint8_t tc6_pri_queue_id;
24860 * pri assigned to MPLS TC(EXP) 7. This value can only
24861 * be changed before traffic has started.
24862 * A value of 0xff indicates that no pri is assigned to the
24865 uint8_t tc7_pri_queue_id;
24866 uint8_t unused_0[7];
24868 * This field is used in Output records to indicate that the output
24869 * is completely written to RAM. This field should be read as '1'
24870 * to indicate that the output has been completely written.
24871 * When writing a command completion or response to an internal processor,
24872 * the order of writes has to be such that this field is written last.
24877 /*****************************
24878 * hwrm_queue_mplstc2pri_cfg *
24879 *****************************/
24882 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
24883 struct hwrm_queue_mplstc2pri_cfg_input {
24884 /* The HWRM command request type. */
24887 * The completion ring to send the completion event on. This should
24888 * be the NQ ID returned from the `nq_alloc` HWRM command.
24890 uint16_t cmpl_ring;
24892 * The sequence ID is used by the driver for tracking multiple
24893 * commands. This ID is treated as opaque data by the firmware and
24894 * the value is returned in the `hwrm_resp_hdr` upon completion.
24898 * The target ID of the command:
24899 * * 0x0-0xFFF8 - The function ID
24900 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24901 * * 0xFFFD - Reserved for user-space HWRM interface
24904 uint16_t target_id;
24906 * A physical address pointer pointing to a host buffer that the
24907 * command's response data will be written. This can be either a host
24908 * physical address (HPA) or a guest physical address (GPA) and must
24909 * point to a physically contiguous block of memory.
24911 uint64_t resp_addr;
24914 * This bit must be '1' for the mplstc0_pri_queue_id field to be
24917 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
24920 * This bit must be '1' for the mplstc1_pri_queue_id field to be
24923 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
24926 * This bit must be '1' for the mplstc2_pri_queue_id field to be
24929 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
24932 * This bit must be '1' for the mplstc3_pri_queue_id field to be
24935 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
24938 * This bit must be '1' for the mplstc4_pri_queue_id field to be
24941 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
24944 * This bit must be '1' for the mplstc5_pri_queue_id field to be
24947 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
24950 * This bit must be '1' for the mplstc6_pri_queue_id field to be
24953 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
24956 * This bit must be '1' for the mplstc7_pri_queue_id field to be
24959 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
24962 * Port ID of port for which the table is being configured.
24963 * The HWRM needs to check whether this function is allowed
24964 * to configure MPLS TC(EXP)to pri mapping on this port.
24967 uint8_t unused_0[3];
24969 * pri assigned to MPLS TC(EXP) 0. This value can only
24970 * be changed before traffic has started.
24972 uint8_t tc0_pri_queue_id;
24974 * pri assigned to MPLS TC(EXP) 1. This value can only
24975 * be changed before traffic has started.
24977 uint8_t tc1_pri_queue_id;
24979 * pri assigned to MPLS TC(EXP) 2 This value can only
24980 * be changed before traffic has started.
24982 uint8_t tc2_pri_queue_id;
24984 * pri assigned to MPLS TC(EXP) 3. This value can only
24985 * be changed before traffic has started.
24987 uint8_t tc3_pri_queue_id;
24989 * pri assigned to MPLS TC(EXP) 4. This value can only
24990 * be changed before traffic has started.
24992 uint8_t tc4_pri_queue_id;
24994 * pri assigned to MPLS TC(EXP) 5. This value can only
24995 * be changed before traffic has started.
24997 uint8_t tc5_pri_queue_id;
24999 * pri assigned to MPLS TC(EXP) 6. This value can only
25000 * be changed before traffic has started.
25002 uint8_t tc6_pri_queue_id;
25004 * pri assigned to MPLS TC(EXP) 7. This value can only
25005 * be changed before traffic has started.
25007 uint8_t tc7_pri_queue_id;
25010 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
25011 struct hwrm_queue_mplstc2pri_cfg_output {
25012 /* The specific error status for the command. */
25013 uint16_t error_code;
25014 /* The HWRM command request type. */
25016 /* The sequence ID from the original command. */
25018 /* The length of the response data in number of bytes. */
25020 uint8_t unused_0[7];
25022 * This field is used in Output records to indicate that the output
25023 * is completely written to RAM. This field should be read as '1'
25024 * to indicate that the output has been completely written.
25025 * When writing a command completion or response to an internal processor,
25026 * the order of writes has to be such that this field is written last.
25031 /*******************
25032 * hwrm_vnic_alloc *
25033 *******************/
25036 /* hwrm_vnic_alloc_input (size:192b/24B) */
25037 struct hwrm_vnic_alloc_input {
25038 /* The HWRM command request type. */
25041 * The completion ring to send the completion event on. This should
25042 * be the NQ ID returned from the `nq_alloc` HWRM command.
25044 uint16_t cmpl_ring;
25046 * The sequence ID is used by the driver for tracking multiple
25047 * commands. This ID is treated as opaque data by the firmware and
25048 * the value is returned in the `hwrm_resp_hdr` upon completion.
25052 * The target ID of the command:
25053 * * 0x0-0xFFF8 - The function ID
25054 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25055 * * 0xFFFD - Reserved for user-space HWRM interface
25058 uint16_t target_id;
25060 * A physical address pointer pointing to a host buffer that the
25061 * command's response data will be written. This can be either a host
25062 * physical address (HPA) or a guest physical address (GPA) and must
25063 * point to a physically contiguous block of memory.
25065 uint64_t resp_addr;
25068 * When this bit is '1', this VNIC is requested to
25069 * be the default VNIC for this function.
25071 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
25072 uint8_t unused_0[4];
25075 /* hwrm_vnic_alloc_output (size:128b/16B) */
25076 struct hwrm_vnic_alloc_output {
25077 /* The specific error status for the command. */
25078 uint16_t error_code;
25079 /* The HWRM command request type. */
25081 /* The sequence ID from the original command. */
25083 /* The length of the response data in number of bytes. */
25085 /* Logical vnic ID */
25087 uint8_t unused_0[3];
25089 * This field is used in Output records to indicate that the output
25090 * is completely written to RAM. This field should be read as '1'
25091 * to indicate that the output has been completely written.
25092 * When writing a command completion or response to an internal processor,
25093 * the order of writes has to be such that this field is written last.
25098 /******************
25100 ******************/
25103 /* hwrm_vnic_free_input (size:192b/24B) */
25104 struct hwrm_vnic_free_input {
25105 /* The HWRM command request type. */
25108 * The completion ring to send the completion event on. This should
25109 * be the NQ ID returned from the `nq_alloc` HWRM command.
25111 uint16_t cmpl_ring;
25113 * The sequence ID is used by the driver for tracking multiple
25114 * commands. This ID is treated as opaque data by the firmware and
25115 * the value is returned in the `hwrm_resp_hdr` upon completion.
25119 * The target ID of the command:
25120 * * 0x0-0xFFF8 - The function ID
25121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25122 * * 0xFFFD - Reserved for user-space HWRM interface
25125 uint16_t target_id;
25127 * A physical address pointer pointing to a host buffer that the
25128 * command's response data will be written. This can be either a host
25129 * physical address (HPA) or a guest physical address (GPA) and must
25130 * point to a physically contiguous block of memory.
25132 uint64_t resp_addr;
25133 /* Logical vnic ID */
25135 uint8_t unused_0[4];
25138 /* hwrm_vnic_free_output (size:128b/16B) */
25139 struct hwrm_vnic_free_output {
25140 /* The specific error status for the command. */
25141 uint16_t error_code;
25142 /* The HWRM command request type. */
25144 /* The sequence ID from the original command. */
25146 /* The length of the response data in number of bytes. */
25148 uint8_t unused_0[7];
25150 * This field is used in Output records to indicate that the output
25151 * is completely written to RAM. This field should be read as '1'
25152 * to indicate that the output has been completely written.
25153 * When writing a command completion or response to an internal processor,
25154 * the order of writes has to be such that this field is written last.
25164 /* hwrm_vnic_cfg_input (size:384b/48B) */
25165 struct hwrm_vnic_cfg_input {
25166 /* The HWRM command request type. */
25169 * The completion ring to send the completion event on. This should
25170 * be the NQ ID returned from the `nq_alloc` HWRM command.
25172 uint16_t cmpl_ring;
25174 * The sequence ID is used by the driver for tracking multiple
25175 * commands. This ID is treated as opaque data by the firmware and
25176 * the value is returned in the `hwrm_resp_hdr` upon completion.
25180 * The target ID of the command:
25181 * * 0x0-0xFFF8 - The function ID
25182 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25183 * * 0xFFFD - Reserved for user-space HWRM interface
25186 uint16_t target_id;
25188 * A physical address pointer pointing to a host buffer that the
25189 * command's response data will be written. This can be either a host
25190 * physical address (HPA) or a guest physical address (GPA) and must
25191 * point to a physically contiguous block of memory.
25193 uint64_t resp_addr;
25196 * When this bit is '1', the VNIC is requested to
25197 * be the default VNIC for the function.
25199 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
25202 * When this bit is '1', the VNIC is being configured to
25203 * strip VLAN in the RX path.
25204 * If set to '0', then VLAN stripping is disabled on
25207 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
25210 * When this bit is '1', the VNIC is being configured to
25211 * buffer receive packets in the hardware until the host
25212 * posts new receive buffers.
25213 * If set to '0', then bd_stall is being configured to be
25214 * disabled on this VNIC.
25216 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
25219 * When this bit is '1', the VNIC is being configured to
25220 * receive both RoCE and non-RoCE traffic.
25221 * If set to '0', then this VNIC is not configured to be
25222 * operating in dual VNIC mode.
25224 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25227 * When this flag is set to '1', the VNIC is requested to
25228 * be configured to receive only RoCE traffic.
25229 * If this flag is set to '0', then this flag shall be
25230 * ignored by the HWRM.
25231 * If roce_dual_vnic_mode flag is set to '1'
25232 * or roce_mirroring_capable_vnic_mode flag to 1,
25233 * then the HWRM client shall not set this flag to '1'.
25235 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25238 * When a VNIC uses one destination ring group for certain
25239 * application (e.g. Receive Flow Steering) where
25240 * exact match is used to direct packets to a VNIC with one
25241 * destination ring group only, there is no need to configure
25242 * RSS indirection table for that VNIC as only one destination
25243 * ring group is used.
25245 * This flag is used to enable a mode where
25246 * RSS is enabled in the VNIC using a RSS context
25247 * for computing RSS hash but the RSS indirection table is
25248 * not configured using hwrm_vnic_rss_cfg.
25250 * If this mode is enabled, then the driver should not program
25251 * RSS indirection table for the RSS context that is used for
25252 * computing RSS hash only.
25254 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
25257 * When this bit is '1', the VNIC is being configured to
25258 * receive both RoCE and non-RoCE traffic, but forward only the
25259 * RoCE traffic further. Also, RoCE traffic can be mirrored to
25262 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25266 * This bit must be '1' for the dflt_ring_grp field to be
25269 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
25272 * This bit must be '1' for the rss_rule field to be
25275 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
25278 * This bit must be '1' for the cos_rule field to be
25281 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
25284 * This bit must be '1' for the lb_rule field to be
25287 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
25290 * This bit must be '1' for the mru field to be
25293 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
25296 * This bit must be '1' for the default_rx_ring_id field to be
25299 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
25302 * This bit must be '1' for the default_cmpl_ring_id field to be
25305 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
25307 /* This bit must be '1' for the queue_id field to be configured. */
25308 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
25310 /* Logical vnic ID */
25313 * Default Completion ring for the VNIC. This ring will
25314 * be chosen if packet does not match any RSS rules and if
25315 * there is no COS rule.
25317 uint16_t dflt_ring_grp;
25319 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25320 * there is no RSS rule.
25324 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25325 * there is no COS rule.
25329 * RSS ID for load balancing rule/table structure.
25330 * 0xFF... (All Fs) if there is no LB rule.
25334 * The maximum receive unit of the vnic.
25335 * Each vnic is associated with a function.
25336 * The vnic mru value overwrites the mru setting of the
25337 * associated function.
25338 * The HWRM shall make sure that vnic mru does not exceed
25339 * the mru of the port the function is associated with.
25343 * Default Rx ring for the VNIC. This ring will
25344 * be chosen if packet does not match any RSS rules.
25345 * The aggregation ring associated with the Rx ring is
25346 * implied based on the Rx ring specified when the
25347 * aggregation ring was allocated.
25349 uint16_t default_rx_ring_id;
25351 * Default completion ring for the VNIC. This ring will
25352 * be chosen if packet does not match any RSS rules.
25354 uint16_t default_cmpl_ring_id;
25356 * When specified, only incoming packets classified to the specified CoS
25357 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
25358 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
25359 * ntuple filters with VNIC destination specified are invalid since they
25360 * conflict with the the CoS to VNIC steering rules in this mode.
25362 * If this field is not specified, packet to VNIC steering will be
25363 * subject to the standard L2 filter rules and any additional ntuple
25364 * filter rules with destination VNIC specified.
25367 uint8_t unused0[6];
25370 /* hwrm_vnic_cfg_output (size:128b/16B) */
25371 struct hwrm_vnic_cfg_output {
25372 /* The specific error status for the command. */
25373 uint16_t error_code;
25374 /* The HWRM command request type. */
25376 /* The sequence ID from the original command. */
25378 /* The length of the response data in number of bytes. */
25380 uint8_t unused_0[7];
25382 * This field is used in Output records to indicate that the output
25383 * is completely written to RAM. This field should be read as '1'
25384 * to indicate that the output has been completely written.
25385 * When writing a command completion or response to an internal processor,
25386 * the order of writes has to be such that this field is written last.
25391 /******************
25393 ******************/
25396 /* hwrm_vnic_qcfg_input (size:256b/32B) */
25397 struct hwrm_vnic_qcfg_input {
25398 /* The HWRM command request type. */
25401 * The completion ring to send the completion event on. This should
25402 * be the NQ ID returned from the `nq_alloc` HWRM command.
25404 uint16_t cmpl_ring;
25406 * The sequence ID is used by the driver for tracking multiple
25407 * commands. This ID is treated as opaque data by the firmware and
25408 * the value is returned in the `hwrm_resp_hdr` upon completion.
25412 * The target ID of the command:
25413 * * 0x0-0xFFF8 - The function ID
25414 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25415 * * 0xFFFD - Reserved for user-space HWRM interface
25418 uint16_t target_id;
25420 * A physical address pointer pointing to a host buffer that the
25421 * command's response data will be written. This can be either a host
25422 * physical address (HPA) or a guest physical address (GPA) and must
25423 * point to a physically contiguous block of memory.
25425 uint64_t resp_addr;
25428 * This bit must be '1' for the vf_id_valid field to be
25431 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
25432 /* Logical vnic ID */
25434 /* ID of Virtual Function whose VNIC resource is being queried. */
25436 uint8_t unused_0[6];
25439 /* hwrm_vnic_qcfg_output (size:256b/32B) */
25440 struct hwrm_vnic_qcfg_output {
25441 /* The specific error status for the command. */
25442 uint16_t error_code;
25443 /* The HWRM command request type. */
25445 /* The sequence ID from the original command. */
25447 /* The length of the response data in number of bytes. */
25449 /* Default Completion ring for the VNIC. */
25450 uint16_t dflt_ring_grp;
25452 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25453 * there is no RSS rule.
25457 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25458 * there is no COS rule.
25462 * RSS ID for load balancing rule/table structure.
25463 * 0xFF... (All Fs) if there is no LB rule.
25466 /* The maximum receive unit of the vnic. */
25468 uint8_t unused_0[2];
25471 * When this bit is '1', the VNIC is the default VNIC for
25474 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
25477 * When this bit is '1', the VNIC is configured to
25478 * strip VLAN in the RX path.
25479 * If set to '0', then VLAN stripping is disabled on
25482 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
25485 * When this bit is '1', the VNIC is configured to
25486 * buffer receive packets in the hardware until the host
25487 * posts new receive buffers.
25488 * If set to '0', then bd_stall is disabled on
25491 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
25494 * When this bit is '1', the VNIC is configured to
25495 * receive both RoCE and non-RoCE traffic.
25496 * If set to '0', then this VNIC is not configured to
25497 * operate in dual VNIC mode.
25499 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25502 * When this flag is set to '1', the VNIC is configured to
25503 * receive only RoCE traffic.
25504 * When this flag is set to '0', the VNIC is not configured
25505 * to receive only RoCE traffic.
25506 * If roce_dual_vnic_mode flag and this flag both are set
25507 * to '1', then it is an invalid configuration of the
25508 * VNIC. The HWRM should not allow that type of
25509 * mis-configuration by HWRM clients.
25511 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25514 * When a VNIC uses one destination ring group for certain
25515 * application (e.g. Receive Flow Steering) where
25516 * exact match is used to direct packets to a VNIC with one
25517 * destination ring group only, there is no need to configure
25518 * RSS indirection table for that VNIC as only one destination
25519 * ring group is used.
25521 * When this bit is set to '1', then the VNIC is enabled in a
25522 * mode where RSS is enabled in the VNIC using a RSS context
25523 * for computing RSS hash but the RSS indirection table is
25526 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
25529 * When this bit is '1', the VNIC is configured to
25530 * receive both RoCE and non-RoCE traffic, but forward only
25531 * RoCE traffic further. Also RoCE traffic can be mirrored to
25534 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25537 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
25538 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
25539 * queue association.
25542 uint8_t unused_1[5];
25544 * This field is used in Output records to indicate that the output
25545 * is completely written to RAM. This field should be read as '1'
25546 * to indicate that the output has been completely written.
25547 * When writing a command completion or response to an internal processor,
25548 * the order of writes has to be such that this field is written last.
25553 /*******************
25554 * hwrm_vnic_qcaps *
25555 *******************/
25558 /* hwrm_vnic_qcaps_input (size:192b/24B) */
25559 struct hwrm_vnic_qcaps_input {
25560 /* The HWRM command request type. */
25563 * The completion ring to send the completion event on. This should
25564 * be the NQ ID returned from the `nq_alloc` HWRM command.
25566 uint16_t cmpl_ring;
25568 * The sequence ID is used by the driver for tracking multiple
25569 * commands. This ID is treated as opaque data by the firmware and
25570 * the value is returned in the `hwrm_resp_hdr` upon completion.
25574 * The target ID of the command:
25575 * * 0x0-0xFFF8 - The function ID
25576 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25577 * * 0xFFFD - Reserved for user-space HWRM interface
25580 uint16_t target_id;
25582 * A physical address pointer pointing to a host buffer that the
25583 * command's response data will be written. This can be either a host
25584 * physical address (HPA) or a guest physical address (GPA) and must
25585 * point to a physically contiguous block of memory.
25587 uint64_t resp_addr;
25589 uint8_t unused_0[4];
25592 /* hwrm_vnic_qcaps_output (size:192b/24B) */
25593 struct hwrm_vnic_qcaps_output {
25594 /* The specific error status for the command. */
25595 uint16_t error_code;
25596 /* The HWRM command request type. */
25598 /* The sequence ID from the original command. */
25600 /* The length of the response data in number of bytes. */
25602 /* The maximum receive unit that is settable on a vnic. */
25604 uint8_t unused_0[2];
25607 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
25610 * When this bit is '1', the capability of stripping VLAN in
25611 * the RX path is supported on VNIC(s).
25612 * If set to '0', then VLAN stripping capability is
25613 * not supported on VNIC(s).
25615 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
25618 * When this bit is '1', the capability to buffer receive
25619 * packets in the hardware until the host posts new receive buffers
25620 * is supported on VNIC(s).
25621 * If set to '0', then bd_stall capability is not supported
25624 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
25627 * When this bit is '1', the capability to
25628 * receive both RoCE and non-RoCE traffic on VNIC(s) is
25630 * If set to '0', then the capability to receive
25631 * both RoCE and non-RoCE traffic on VNIC(s) is
25634 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
25637 * When this bit is set to '1', the capability to configure
25638 * a VNIC to receive only RoCE traffic is supported.
25639 * When this flag is set to '0', the VNIC capability to
25640 * configure to receive only RoCE traffic is not supported.
25642 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
25645 * When this bit is set to '1', then the capability to enable
25646 * a VNIC in a mode where RSS context without configuring
25647 * RSS indirection table is supported (for RSS hash computation).
25648 * When this bit is set to '0', then a VNIC can not be configured
25649 * with a mode to enable RSS context without configuring RSS
25650 * indirection table.
25652 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
25655 * When this bit is '1', the capability to
25656 * mirror the the RoCE traffic is supported.
25657 * If set to '0', then the capability to mirror the
25658 * RoCE traffic is not supported.
25660 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
25663 * When this bit is '1', the outermost RSS hashing capability
25664 * is supported. If set to '0', then the outermost RSS hashing
25665 * capability is not supported.
25667 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
25670 * When this bit is '1', it indicates that firmware supports the
25671 * ability to steer incoming packets from one CoS queue to one
25672 * VNIC. This optional feature can then be enabled
25673 * using HWRM_VNIC_CFG on any VNIC. This feature is only
25674 * available when NVM option “enable_cos_classfication” is set
25675 * to 1. If set to '0', firmware does not support this feature.
25677 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
25680 * This field advertises the maximum concurrent TPA aggregations
25681 * supported by the VNIC on new devices that support TPA v2.
25682 * '0' means that TPA v2 is not supported.
25684 uint16_t max_aggs_supported;
25685 uint8_t unused_1[5];
25687 * This field is used in Output records to indicate that the output
25688 * is completely written to RAM. This field should be read as '1'
25689 * to indicate that the output has been completely written.
25690 * When writing a command completion or response to an internal processor,
25691 * the order of writes has to be such that this field is written last.
25696 /*********************
25697 * hwrm_vnic_tpa_cfg *
25698 *********************/
25701 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
25702 struct hwrm_vnic_tpa_cfg_input {
25703 /* The HWRM command request type. */
25706 * The completion ring to send the completion event on. This should
25707 * be the NQ ID returned from the `nq_alloc` HWRM command.
25709 uint16_t cmpl_ring;
25711 * The sequence ID is used by the driver for tracking multiple
25712 * commands. This ID is treated as opaque data by the firmware and
25713 * the value is returned in the `hwrm_resp_hdr` upon completion.
25717 * The target ID of the command:
25718 * * 0x0-0xFFF8 - The function ID
25719 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25720 * * 0xFFFD - Reserved for user-space HWRM interface
25723 uint16_t target_id;
25725 * A physical address pointer pointing to a host buffer that the
25726 * command's response data will be written. This can be either a host
25727 * physical address (HPA) or a guest physical address (GPA) and must
25728 * point to a physically contiguous block of memory.
25730 uint64_t resp_addr;
25733 * When this bit is '1', the VNIC shall be configured to
25734 * perform transparent packet aggregation (TPA) of
25735 * non-tunneled TCP packets.
25737 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
25740 * When this bit is '1', the VNIC shall be configured to
25741 * perform transparent packet aggregation (TPA) of
25742 * tunneled TCP packets.
25744 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
25747 * When this bit is '1', the VNIC shall be configured to
25748 * perform transparent packet aggregation (TPA) according
25749 * to Windows Receive Segment Coalescing (RSC) rules.
25751 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
25754 * When this bit is '1', the VNIC shall be configured to
25755 * perform transparent packet aggregation (TPA) according
25756 * to Linux Generic Receive Offload (GRO) rules.
25758 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
25761 * When this bit is '1', the VNIC shall be configured to
25762 * perform transparent packet aggregation (TPA) for TCP
25763 * packets with IP ECN set to non-zero.
25765 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
25768 * When this bit is '1', the VNIC shall be configured to
25769 * perform transparent packet aggregation (TPA) for
25770 * GRE tunneled TCP packets only if all packets have the
25771 * same GRE sequence.
25773 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
25776 * When this bit is '1' and the GRO mode is enabled,
25777 * the VNIC shall be configured to
25778 * perform transparent packet aggregation (TPA) for
25779 * TCP/IPv4 packets with consecutively increasing IPIDs.
25780 * In other words, the last packet that is being
25781 * aggregated to an already existing aggregation context
25782 * shall have IPID 1 more than the IPID of the last packet
25783 * that was aggregated in that aggregation context.
25785 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
25788 * When this bit is '1' and the GRO mode is enabled,
25789 * the VNIC shall be configured to
25790 * perform transparent packet aggregation (TPA) for
25791 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
25794 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
25797 * When this bit is '1' and the GRO mode is enabled,
25798 * the VNIC shall DMA payload data using GRO rules.
25799 * When this bit is '0', the VNIC shall DMA payload data
25800 * using the more efficient LRO rules of filling all
25801 * aggregation buffers.
25803 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
25807 * This bit must be '1' for the max_agg_segs field to be
25810 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
25812 * This bit must be '1' for the max_aggs field to be
25815 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
25817 * This bit must be '1' for the max_agg_timer field to be
25820 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
25821 /* deprecated bit. Do not use!!! */
25822 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
25823 /* Logical vnic ID */
25826 * This is the maximum number of TCP segments that can
25827 * be aggregated (unit is Log2). Max value is 31. On new
25828 * devices supporting TPA v2, the unit is multiples of 4 and
25829 * valid values are > 0 and <= 63.
25831 uint16_t max_agg_segs;
25833 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
25835 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
25837 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
25839 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
25840 /* Any segment size larger than this is not valid */
25841 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
25842 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
25843 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
25845 * This is the maximum number of aggregations this VNIC is
25846 * allowed (unit is Log2). Max value is 7. On new devices
25847 * supporting TPA v2, this is in unit of 1 and must be > 0
25848 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
25849 * to enable TPA v2.
25852 /* 1 aggregation */
25853 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
25854 /* 2 aggregations */
25855 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
25856 /* 4 aggregations */
25857 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
25858 /* 8 aggregations */
25859 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
25860 /* 16 aggregations */
25861 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
25862 /* Any aggregation size larger than this is not valid */
25863 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
25864 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
25865 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
25866 uint8_t unused_0[2];
25868 * This is the maximum amount of time allowed for
25869 * an aggregation context to complete after it was initiated.
25871 uint32_t max_agg_timer;
25873 * This is the minimum amount of payload length required to
25874 * start an aggregation context. This field is deprecated and
25875 * should be set to 0. The minimum length is set by firmware
25876 * and can be queried using hwrm_vnic_tpa_qcfg.
25878 uint32_t min_agg_len;
25881 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
25882 struct hwrm_vnic_tpa_cfg_output {
25883 /* The specific error status for the command. */
25884 uint16_t error_code;
25885 /* The HWRM command request type. */
25887 /* The sequence ID from the original command. */
25889 /* The length of the response data in number of bytes. */
25891 uint8_t unused_0[7];
25893 * This field is used in Output records to indicate that the output
25894 * is completely written to RAM. This field should be read as '1'
25895 * to indicate that the output has been completely written.
25896 * When writing a command completion or response to an internal processor,
25897 * the order of writes has to be such that this field is written last.
25902 /*********************
25903 * hwrm_vnic_rss_cfg *
25904 *********************/
25907 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
25908 struct hwrm_vnic_rss_cfg_input {
25909 /* The HWRM command request type. */
25912 * The completion ring to send the completion event on. This should
25913 * be the NQ ID returned from the `nq_alloc` HWRM command.
25915 uint16_t cmpl_ring;
25917 * The sequence ID is used by the driver for tracking multiple
25918 * commands. This ID is treated as opaque data by the firmware and
25919 * the value is returned in the `hwrm_resp_hdr` upon completion.
25923 * The target ID of the command:
25924 * * 0x0-0xFFF8 - The function ID
25925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25926 * * 0xFFFD - Reserved for user-space HWRM interface
25929 uint16_t target_id;
25931 * A physical address pointer pointing to a host buffer that the
25932 * command's response data will be written. This can be either a host
25933 * physical address (HPA) or a guest physical address (GPA) and must
25934 * point to a physically contiguous block of memory.
25936 uint64_t resp_addr;
25937 uint32_t hash_type;
25939 * When this bit is '1', the RSS hash shall be computed
25940 * over source and destination IPv4 addresses of IPv4
25943 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
25945 * When this bit is '1', the RSS hash shall be computed
25946 * over source/destination IPv4 addresses and
25947 * source/destination ports of TCP/IPv4 packets.
25949 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
25951 * When this bit is '1', the RSS hash shall be computed
25952 * over source/destination IPv4 addresses and
25953 * source/destination ports of UDP/IPv4 packets.
25955 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
25957 * When this bit is '1', the RSS hash shall be computed
25958 * over source and destination IPv4 addresses of IPv6
25961 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
25963 * When this bit is '1', the RSS hash shall be computed
25964 * over source/destination IPv6 addresses and
25965 * source/destination ports of TCP/IPv6 packets.
25967 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
25969 * When this bit is '1', the RSS hash shall be computed
25970 * over source/destination IPv6 addresses and
25971 * source/destination ports of UDP/IPv6 packets.
25973 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
25974 /* VNIC ID of VNIC associated with RSS table being configured. */
25977 * Specifies which VNIC ring table pair to configure.
25978 * Valid values range from 0 to 7.
25980 uint8_t ring_table_pair_index;
25981 /* Flags to specify different RSS hash modes. */
25982 uint8_t hash_mode_flags;
25984 * When this bit is '1', it indicates using current RSS
25985 * hash mode setting configured in the device.
25987 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
25990 * When this bit is '1', it indicates requesting support of
25991 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
25992 * l4.src, l4.dest} for tunnel packets. For none-tunnel
25993 * packets, the RSS hash is computed over the normal
25994 * src/dest l3 and src/dest l4 headers.
25996 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
25999 * When this bit is '1', it indicates requesting support of
26000 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26001 * tunnel packets. For none-tunnel packets, the RSS hash is
26002 * computed over the normal src/dest l3 headers.
26004 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26007 * When this bit is '1', it indicates requesting support of
26008 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26009 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26010 * packets, the RSS hash is computed over the normal
26011 * src/dest l3 and src/dest l4 headers.
26013 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26016 * When this bit is '1', it indicates requesting support of
26017 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26018 * tunnel packets. For none-tunnel packets, the RSS hash is
26019 * computed over the normal src/dest l3 headers.
26021 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26023 /* This is the address for rss ring group table */
26024 uint64_t ring_grp_tbl_addr;
26025 /* This is the address for rss hash key table */
26026 uint64_t hash_key_tbl_addr;
26027 /* Index to the rss indirection table. */
26028 uint16_t rss_ctx_idx;
26029 uint8_t unused_1[6];
26032 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
26033 struct hwrm_vnic_rss_cfg_output {
26034 /* The specific error status for the command. */
26035 uint16_t error_code;
26036 /* The HWRM command request type. */
26038 /* The sequence ID from the original command. */
26040 /* The length of the response data in number of bytes. */
26042 uint8_t unused_0[7];
26044 * This field is used in Output records to indicate that the output
26045 * is completely written to RAM. This field should be read as '1'
26046 * to indicate that the output has been completely written.
26047 * When writing a command completion or response to an internal processor,
26048 * the order of writes has to be such that this field is written last.
26053 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
26054 struct hwrm_vnic_rss_cfg_cmd_err {
26056 * command specific error codes that goes to
26057 * the cmd_err field in Common HWRM Error Response.
26060 /* Unknown error */
26061 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
26064 * Unable to change global RSS mode to outer due to all active
26065 * interfaces are not ready to support outer RSS hashing.
26067 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
26069 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
26070 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
26071 uint8_t unused_0[7];
26074 /**********************
26075 * hwrm_vnic_rss_qcfg *
26076 **********************/
26079 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
26080 struct hwrm_vnic_rss_qcfg_input {
26081 /* The HWRM command request type. */
26084 * The completion ring to send the completion event on. This should
26085 * be the NQ ID returned from the `nq_alloc` HWRM command.
26087 uint16_t cmpl_ring;
26089 * The sequence ID is used by the driver for tracking multiple
26090 * commands. This ID is treated as opaque data by the firmware and
26091 * the value is returned in the `hwrm_resp_hdr` upon completion.
26095 * The target ID of the command:
26096 * * 0x0-0xFFF8 - The function ID
26097 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26098 * * 0xFFFD - Reserved for user-space HWRM interface
26101 uint16_t target_id;
26103 * A physical address pointer pointing to a host buffer that the
26104 * command's response data will be written. This can be either a host
26105 * physical address (HPA) or a guest physical address (GPA) and must
26106 * point to a physically contiguous block of memory.
26108 uint64_t resp_addr;
26109 /* Index to the rss indirection table. */
26110 uint16_t rss_ctx_idx;
26111 uint8_t unused_0[6];
26114 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
26115 struct hwrm_vnic_rss_qcfg_output {
26116 /* The specific error status for the command. */
26117 uint16_t error_code;
26118 /* The HWRM command request type. */
26120 /* The sequence ID from the original command. */
26122 /* The length of the response data in number of bytes. */
26124 uint32_t hash_type;
26126 * When this bit is '1', the RSS hash shall be computed
26127 * over source and destination IPv4 addresses of IPv4
26130 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26132 * When this bit is '1', the RSS hash shall be computed
26133 * over source/destination IPv4 addresses and
26134 * source/destination ports of TCP/IPv4 packets.
26136 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26138 * When this bit is '1', the RSS hash shall be computed
26139 * over source/destination IPv4 addresses and
26140 * source/destination ports of UDP/IPv4 packets.
26142 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26144 * When this bit is '1', the RSS hash shall be computed
26145 * over source and destination IPv4 addresses of IPv6
26148 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26150 * When this bit is '1', the RSS hash shall be computed
26151 * over source/destination IPv6 addresses and
26152 * source/destination ports of TCP/IPv6 packets.
26154 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26156 * When this bit is '1', the RSS hash shall be computed
26157 * over source/destination IPv6 addresses and
26158 * source/destination ports of UDP/IPv6 packets.
26160 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26161 uint8_t unused_0[4];
26162 /* This is the value of rss hash key */
26163 uint32_t hash_key[10];
26164 /* Flags to specify different RSS hash modes. */
26165 uint8_t hash_mode_flags;
26167 * When this bit is '1', it indicates using current RSS
26168 * hash mode setting configured in the device.
26170 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
26173 * When this bit is '1', it indicates requesting support of
26174 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26175 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26176 * packets, the RSS hash is computed over the normal
26177 * src/dest l3 and src/dest l4 headers.
26179 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26182 * When this bit is '1', it indicates requesting support of
26183 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26184 * tunnel packets. For none-tunnel packets, the RSS hash is
26185 * computed over the normal src/dest l3 headers.
26187 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26190 * When this bit is '1', it indicates requesting support of
26191 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26192 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26193 * packets, the RSS hash is computed over the normal
26194 * src/dest l3 and src/dest l4 headers.
26196 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26199 * When this bit is '1', it indicates requesting support of
26200 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26201 * tunnel packets. For none-tunnel packets, the RSS hash is
26202 * computed over the normal src/dest l3 headers.
26204 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26206 uint8_t unused_1[6];
26208 * This field is used in Output records to indicate that the output
26209 * is completely written to RAM. This field should be read as '1'
26210 * to indicate that the output has been completely written.
26211 * When writing a command completion or response to an internal processor,
26212 * the order of writes has to be such that this field is written last.
26217 /**************************
26218 * hwrm_vnic_plcmodes_cfg *
26219 **************************/
26222 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
26223 struct hwrm_vnic_plcmodes_cfg_input {
26224 /* The HWRM command request type. */
26227 * The completion ring to send the completion event on. This should
26228 * be the NQ ID returned from the `nq_alloc` HWRM command.
26230 uint16_t cmpl_ring;
26232 * The sequence ID is used by the driver for tracking multiple
26233 * commands. This ID is treated as opaque data by the firmware and
26234 * the value is returned in the `hwrm_resp_hdr` upon completion.
26238 * The target ID of the command:
26239 * * 0x0-0xFFF8 - The function ID
26240 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26241 * * 0xFFFD - Reserved for user-space HWRM interface
26244 uint16_t target_id;
26246 * A physical address pointer pointing to a host buffer that the
26247 * command's response data will be written. This can be either a host
26248 * physical address (HPA) or a guest physical address (GPA) and must
26249 * point to a physically contiguous block of memory.
26251 uint64_t resp_addr;
26254 * When this bit is '1', the VNIC shall be configured to
26255 * use regular placement algorithm.
26256 * By default, the regular placement algorithm shall be
26257 * enabled on the VNIC.
26259 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
26262 * When this bit is '1', the VNIC shall be configured
26263 * use the jumbo placement algorithm.
26265 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
26268 * When this bit is '1', the VNIC shall be configured
26269 * to enable Header-Data split for IPv4 packets according
26270 * to the following rules:
26271 * # If the packet is identified as TCP/IPv4, then the
26272 * packet is split at the beginning of the TCP payload.
26273 * # If the packet is identified as UDP/IPv4, then the
26274 * packet is split at the beginning of UDP payload.
26275 * # If the packet is identified as non-TCP and non-UDP
26276 * IPv4 packet, then the packet is split at the beginning
26277 * of the upper layer protocol header carried in the IPv4
26280 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
26283 * When this bit is '1', the VNIC shall be configured
26284 * to enable Header-Data split for IPv6 packets according
26285 * to the following rules:
26286 * # If the packet is identified as TCP/IPv6, then the
26287 * packet is split at the beginning of the TCP payload.
26288 * # If the packet is identified as UDP/IPv6, then the
26289 * packet is split at the beginning of UDP payload.
26290 * # If the packet is identified as non-TCP and non-UDP
26291 * IPv6 packet, then the packet is split at the beginning
26292 * of the upper layer protocol header carried in the IPv6
26295 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
26298 * When this bit is '1', the VNIC shall be configured
26299 * to enable Header-Data split for FCoE packets at the
26300 * beginning of FC payload.
26302 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
26305 * When this bit is '1', the VNIC shall be configured
26306 * to enable Header-Data split for RoCE packets at the
26307 * beginning of RoCE payload (after BTH/GRH headers).
26309 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
26313 * This bit must be '1' for the jumbo_thresh_valid field to be
26316 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
26319 * This bit must be '1' for the hds_offset_valid field to be
26322 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
26325 * This bit must be '1' for the hds_threshold_valid field to be
26328 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
26330 /* Logical vnic ID */
26333 * When jumbo placement algorithm is enabled, this value
26334 * is used to determine the threshold for jumbo placement.
26335 * Packets with length larger than this value will be
26336 * placed according to the jumbo placement algorithm.
26338 uint16_t jumbo_thresh;
26340 * This value is used to determine the offset into
26341 * packet buffer where the split data (payload) will be
26342 * placed according to one of HDS placement algorithm.
26344 * The lengths of packet buffers provided for split data
26345 * shall be larger than this value.
26347 uint16_t hds_offset;
26349 * When one of the HDS placement algorithm is enabled, this
26350 * value is used to determine the threshold for HDS
26352 * Packets with length larger than this value will be
26353 * placed according to the HDS placement algorithm.
26354 * This value shall be in multiple of 4 bytes.
26356 uint16_t hds_threshold;
26357 uint8_t unused_0[6];
26360 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
26361 struct hwrm_vnic_plcmodes_cfg_output {
26362 /* The specific error status for the command. */
26363 uint16_t error_code;
26364 /* The HWRM command request type. */
26366 /* The sequence ID from the original command. */
26368 /* The length of the response data in number of bytes. */
26370 uint8_t unused_0[7];
26372 * This field is used in Output records to indicate that the output
26373 * is completely written to RAM. This field should be read as '1'
26374 * to indicate that the output has been completely written.
26375 * When writing a command completion or response to an internal processor,
26376 * the order of writes has to be such that this field is written last.
26381 /***************************
26382 * hwrm_vnic_plcmodes_qcfg *
26383 ***************************/
26386 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
26387 struct hwrm_vnic_plcmodes_qcfg_input {
26388 /* The HWRM command request type. */
26391 * The completion ring to send the completion event on. This should
26392 * be the NQ ID returned from the `nq_alloc` HWRM command.
26394 uint16_t cmpl_ring;
26396 * The sequence ID is used by the driver for tracking multiple
26397 * commands. This ID is treated as opaque data by the firmware and
26398 * the value is returned in the `hwrm_resp_hdr` upon completion.
26402 * The target ID of the command:
26403 * * 0x0-0xFFF8 - The function ID
26404 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26405 * * 0xFFFD - Reserved for user-space HWRM interface
26408 uint16_t target_id;
26410 * A physical address pointer pointing to a host buffer that the
26411 * command's response data will be written. This can be either a host
26412 * physical address (HPA) or a guest physical address (GPA) and must
26413 * point to a physically contiguous block of memory.
26415 uint64_t resp_addr;
26416 /* Logical vnic ID */
26418 uint8_t unused_0[4];
26421 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
26422 struct hwrm_vnic_plcmodes_qcfg_output {
26423 /* The specific error status for the command. */
26424 uint16_t error_code;
26425 /* The HWRM command request type. */
26427 /* The sequence ID from the original command. */
26429 /* The length of the response data in number of bytes. */
26433 * When this bit is '1', the VNIC is configured to
26434 * use regular placement algorithm.
26436 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
26439 * When this bit is '1', the VNIC is configured to
26440 * use the jumbo placement algorithm.
26442 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
26445 * When this bit is '1', the VNIC is configured
26446 * to enable Header-Data split for IPv4 packets.
26448 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
26451 * When this bit is '1', the VNIC is configured
26452 * to enable Header-Data split for IPv6 packets.
26454 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
26457 * When this bit is '1', the VNIC is configured
26458 * to enable Header-Data split for FCoE packets.
26460 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
26463 * When this bit is '1', the VNIC is configured
26464 * to enable Header-Data split for RoCE packets.
26466 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
26469 * When this bit is '1', the VNIC is configured
26470 * to be the default VNIC of the requesting function.
26472 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
26475 * When jumbo placement algorithm is enabled, this value
26476 * is used to determine the threshold for jumbo placement.
26477 * Packets with length larger than this value will be
26478 * placed according to the jumbo placement algorithm.
26480 uint16_t jumbo_thresh;
26482 * This value is used to determine the offset into
26483 * packet buffer where the split data (payload) will be
26484 * placed according to one of HDS placement algorithm.
26486 * The lengths of packet buffers provided for split data
26487 * shall be larger than this value.
26489 uint16_t hds_offset;
26491 * When one of the HDS placement algorithm is enabled, this
26492 * value is used to determine the threshold for HDS
26494 * Packets with length larger than this value will be
26495 * placed according to the HDS placement algorithm.
26496 * This value shall be in multiple of 4 bytes.
26498 uint16_t hds_threshold;
26499 uint8_t unused_0[5];
26501 * This field is used in Output records to indicate that the output
26502 * is completely written to RAM. This field should be read as '1'
26503 * to indicate that the output has been completely written.
26504 * When writing a command completion or response to an internal processor,
26505 * the order of writes has to be such that this field is written last.
26510 /**********************************
26511 * hwrm_vnic_rss_cos_lb_ctx_alloc *
26512 **********************************/
26515 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
26516 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
26517 /* The HWRM command request type. */
26520 * The completion ring to send the completion event on. This should
26521 * be the NQ ID returned from the `nq_alloc` HWRM command.
26523 uint16_t cmpl_ring;
26525 * The sequence ID is used by the driver for tracking multiple
26526 * commands. This ID is treated as opaque data by the firmware and
26527 * the value is returned in the `hwrm_resp_hdr` upon completion.
26531 * The target ID of the command:
26532 * * 0x0-0xFFF8 - The function ID
26533 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26534 * * 0xFFFD - Reserved for user-space HWRM interface
26537 uint16_t target_id;
26539 * A physical address pointer pointing to a host buffer that the
26540 * command's response data will be written. This can be either a host
26541 * physical address (HPA) or a guest physical address (GPA) and must
26542 * point to a physically contiguous block of memory.
26544 uint64_t resp_addr;
26547 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
26548 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
26549 /* The specific error status for the command. */
26550 uint16_t error_code;
26551 /* The HWRM command request type. */
26553 /* The sequence ID from the original command. */
26555 /* The length of the response data in number of bytes. */
26557 /* rss_cos_lb_ctx_id is 16 b */
26558 uint16_t rss_cos_lb_ctx_id;
26559 uint8_t unused_0[5];
26561 * This field is used in Output records to indicate that the output
26562 * is completely written to RAM. This field should be read as '1'
26563 * to indicate that the output has been completely written.
26564 * When writing a command completion or response to an internal processor,
26565 * the order of writes has to be such that this field is written last.
26570 /*********************************
26571 * hwrm_vnic_rss_cos_lb_ctx_free *
26572 *********************************/
26575 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
26576 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
26577 /* The HWRM command request type. */
26580 * The completion ring to send the completion event on. This should
26581 * be the NQ ID returned from the `nq_alloc` HWRM command.
26583 uint16_t cmpl_ring;
26585 * The sequence ID is used by the driver for tracking multiple
26586 * commands. This ID is treated as opaque data by the firmware and
26587 * the value is returned in the `hwrm_resp_hdr` upon completion.
26591 * The target ID of the command:
26592 * * 0x0-0xFFF8 - The function ID
26593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26594 * * 0xFFFD - Reserved for user-space HWRM interface
26597 uint16_t target_id;
26599 * A physical address pointer pointing to a host buffer that the
26600 * command's response data will be written. This can be either a host
26601 * physical address (HPA) or a guest physical address (GPA) and must
26602 * point to a physically contiguous block of memory.
26604 uint64_t resp_addr;
26605 /* rss_cos_lb_ctx_id is 16 b */
26606 uint16_t rss_cos_lb_ctx_id;
26607 uint8_t unused_0[6];
26610 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
26611 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
26612 /* The specific error status for the command. */
26613 uint16_t error_code;
26614 /* The HWRM command request type. */
26616 /* The sequence ID from the original command. */
26618 /* The length of the response data in number of bytes. */
26620 uint8_t unused_0[7];
26622 * This field is used in Output records to indicate that the output
26623 * is completely written to RAM. This field should be read as '1'
26624 * to indicate that the output has been completely written.
26625 * When writing a command completion or response to an internal processor,
26626 * the order of writes has to be such that this field is written last.
26631 /*******************
26632 * hwrm_ring_alloc *
26633 *******************/
26636 /* hwrm_ring_alloc_input (size:704b/88B) */
26637 struct hwrm_ring_alloc_input {
26638 /* The HWRM command request type. */
26641 * The completion ring to send the completion event on. This should
26642 * be the NQ ID returned from the `nq_alloc` HWRM command.
26644 uint16_t cmpl_ring;
26646 * The sequence ID is used by the driver for tracking multiple
26647 * commands. This ID is treated as opaque data by the firmware and
26648 * the value is returned in the `hwrm_resp_hdr` upon completion.
26652 * The target ID of the command:
26653 * * 0x0-0xFFF8 - The function ID
26654 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26655 * * 0xFFFD - Reserved for user-space HWRM interface
26658 uint16_t target_id;
26660 * A physical address pointer pointing to a host buffer that the
26661 * command's response data will be written. This can be either a host
26662 * physical address (HPA) or a guest physical address (GPA) and must
26663 * point to a physically contiguous block of memory.
26665 uint64_t resp_addr;
26668 * This bit must be '1' for the ring_arb_cfg field to be
26671 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
26674 * This bit must be '1' for the stat_ctx_id_valid field to be
26677 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
26680 * This bit must be '1' for the max_bw_valid field to be
26683 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
26686 * This bit must be '1' for the rx_ring_id field to be
26689 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
26692 * This bit must be '1' for the nq_ring_id field to be
26695 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
26698 * This bit must be '1' for the rx_buf_size field to be
26701 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
26705 /* L2 Completion Ring (CR) */
26706 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
26708 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
26710 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
26711 /* RoCE Notification Completion Ring (ROCE_CR) */
26712 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
26713 /* RX Aggregation Ring */
26714 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
26715 /* Notification Queue */
26716 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
26717 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
26718 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
26720 /* Ring allocation flags. */
26723 * For Rx rings, the incoming packet data can be placed at either
26724 * a 0B or 2B offset from the start of the Rx packet buffer. When
26725 * '1', the received packet will be padded with 2B of zeros at the
26726 * front of the packet. Note that this flag is only used for
26727 * Rx rings and is ignored for all other rings included Rx
26728 * Aggregation rings.
26730 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
26732 * This value is a pointer to the page table for the
26735 uint64_t page_tbl_addr;
26736 /* First Byte Offset of the first entry in the first page. */
26739 * Actual page size in 2^page_size. The supported range is increments
26740 * in powers of 2 from 16 bytes to 1GB.
26742 * Page size is 16 B.
26744 * Page size is 4 KB.
26746 * Page size is 8 KB.
26748 * Page size is 64 KB.
26750 * Page size is 2 MB.
26752 * Page size is 4 MB.
26754 * Page size is 1 GB.
26758 * This value indicates the depth of page table.
26759 * For this version of the specification, value other than 0 or
26760 * 1 shall be considered as an invalid value.
26761 * When the page_tbl_depth = 0, then it is treated as a
26762 * special case with the following.
26763 * 1. FBO and page size fields are not valid.
26764 * 2. page_tbl_addr is the physical address of the first
26765 * element of the ring.
26767 uint8_t page_tbl_depth;
26768 uint8_t unused_1[2];
26770 * Number of 16B units in the ring. Minimum size for
26771 * a ring is 16 16B entries.
26775 * Logical ring number for the ring to be allocated.
26776 * This value determines the position in the doorbell
26777 * area where the update to the ring will be made.
26779 * For completion rings, this value is also the MSI-X
26780 * vector number for the function the completion ring is
26783 uint16_t logical_id;
26785 * This field is used only when ring_type is a TX ring.
26786 * This value indicates what completion ring the TX ring
26787 * is associated with.
26789 uint16_t cmpl_ring_id;
26791 * This field is used only when ring_type is a TX ring.
26792 * This value indicates what CoS queue the TX ring
26793 * is associated with.
26797 * When allocating a Rx ring or Rx aggregation ring, this field
26798 * specifies the size of the buffer descriptors posted to the ring.
26800 uint16_t rx_buf_size;
26802 * When allocating an Rx aggregation ring, this field
26803 * specifies the associated Rx ring ID.
26805 uint16_t rx_ring_id;
26807 * When allocating a completion ring, this field
26808 * specifies the associated NQ ring ID.
26810 uint16_t nq_ring_id;
26812 * This field is used only when ring_type is a TX ring.
26813 * This field is used to configure arbitration related
26814 * parameters for a TX ring.
26816 uint16_t ring_arb_cfg;
26817 /* Arbitration policy used for the ring. */
26818 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
26820 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
26822 * Use strict priority for the TX ring.
26823 * Priority value is specified in arb_policy_param
26825 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
26828 * Use weighted fair queue arbitration for the TX ring.
26829 * Weight is specified in arb_policy_param
26831 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
26833 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
26834 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
26835 /* Reserved field. */
26836 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
26838 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
26840 * Arbitration policy specific parameter.
26841 * # For strict priority arbitration policy, this field
26842 * represents a priority value. If set to 0, then the priority
26843 * is not specified and the HWRM is allowed to select
26844 * any priority for this TX ring.
26845 * # For weighted fair queue arbitration policy, this field
26846 * represents a weight value. If set to 0, then the weight
26847 * is not specified and the HWRM is allowed to select
26848 * any weight for this TX ring.
26850 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
26852 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
26855 * This field is reserved for the future use.
26856 * It shall be set to 0.
26858 uint32_t reserved3;
26860 * This field is used only when ring_type is a TX ring.
26861 * This input indicates what statistics context this ring
26862 * should be associated with.
26864 uint32_t stat_ctx_id;
26866 * This field is reserved for the future use.
26867 * It shall be set to 0.
26869 uint32_t reserved4;
26871 * This field is used only when ring_type is a TX ring
26872 * to specify maximum BW allocated to the TX ring.
26873 * The HWRM will translate this value into byte counter and
26874 * time interval used for this ring inside the device.
26877 /* The bandwidth value. */
26878 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
26879 UINT32_C(0xfffffff)
26880 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
26881 /* The granularity of the value (bits or bytes). */
26882 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
26883 UINT32_C(0x10000000)
26884 /* Value is in bits. */
26885 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
26886 (UINT32_C(0x0) << 28)
26887 /* Value is in bytes. */
26888 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
26889 (UINT32_C(0x1) << 28)
26890 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
26891 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
26892 /* bw_value_unit is 3 b */
26893 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
26894 UINT32_C(0xe0000000)
26895 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
26896 /* Value is in Mb or MB (base 10). */
26897 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
26898 (UINT32_C(0x0) << 29)
26899 /* Value is in Kb or KB (base 10). */
26900 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
26901 (UINT32_C(0x2) << 29)
26902 /* Value is in bits or bytes. */
26903 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
26904 (UINT32_C(0x4) << 29)
26905 /* Value is in Gb or GB (base 10). */
26906 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
26907 (UINT32_C(0x6) << 29)
26908 /* Value is in 1/100th of a percentage of total bandwidth. */
26909 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26910 (UINT32_C(0x1) << 29)
26912 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
26913 (UINT32_C(0x7) << 29)
26914 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
26915 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
26917 * This field is used only when ring_type is a Completion ring.
26918 * This value indicates what interrupt mode should be used
26919 * on this completion ring.
26920 * Note: In the legacy interrupt mode, no more than 16
26921 * completion rings are allowed.
26925 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
26927 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
26929 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
26930 /* No Interrupt - Polled mode */
26931 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
26932 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
26933 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
26934 uint8_t unused_4[3];
26936 * The cq_handle is specified when allocating a completion ring. For
26937 * devices that support NQs, this cq_handle will be included in the
26938 * NQE to specify which CQ should be read to retrieve the completion
26941 uint64_t cq_handle;
26944 /* hwrm_ring_alloc_output (size:128b/16B) */
26945 struct hwrm_ring_alloc_output {
26946 /* The specific error status for the command. */
26947 uint16_t error_code;
26948 /* The HWRM command request type. */
26950 /* The sequence ID from the original command. */
26952 /* The length of the response data in number of bytes. */
26955 * Physical number of ring allocated.
26956 * This value shall be unique for a ring type.
26959 /* Logical number of ring allocated. */
26960 uint16_t logical_ring_id;
26961 uint8_t unused_0[3];
26963 * This field is used in Output records to indicate that the output
26964 * is completely written to RAM. This field should be read as '1'
26965 * to indicate that the output has been completely written.
26966 * When writing a command completion or response to an internal processor,
26967 * the order of writes has to be such that this field is written last.
26972 /******************
26974 ******************/
26977 /* hwrm_ring_free_input (size:192b/24B) */
26978 struct hwrm_ring_free_input {
26979 /* The HWRM command request type. */
26982 * The completion ring to send the completion event on. This should
26983 * be the NQ ID returned from the `nq_alloc` HWRM command.
26985 uint16_t cmpl_ring;
26987 * The sequence ID is used by the driver for tracking multiple
26988 * commands. This ID is treated as opaque data by the firmware and
26989 * the value is returned in the `hwrm_resp_hdr` upon completion.
26993 * The target ID of the command:
26994 * * 0x0-0xFFF8 - The function ID
26995 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26996 * * 0xFFFD - Reserved for user-space HWRM interface
26999 uint16_t target_id;
27001 * A physical address pointer pointing to a host buffer that the
27002 * command's response data will be written. This can be either a host
27003 * physical address (HPA) or a guest physical address (GPA) and must
27004 * point to a physically contiguous block of memory.
27006 uint64_t resp_addr;
27009 /* L2 Completion Ring (CR) */
27010 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27012 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
27014 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
27015 /* RoCE Notification Completion Ring (ROCE_CR) */
27016 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27017 /* RX Aggregation Ring */
27018 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27019 /* Notification Queue */
27020 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27021 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
27022 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
27024 /* Physical number of ring allocated. */
27026 uint8_t unused_1[4];
27029 /* hwrm_ring_free_output (size:128b/16B) */
27030 struct hwrm_ring_free_output {
27031 /* The specific error status for the command. */
27032 uint16_t error_code;
27033 /* The HWRM command request type. */
27035 /* The sequence ID from the original command. */
27037 /* The length of the response data in number of bytes. */
27039 uint8_t unused_0[7];
27041 * This field is used in Output records to indicate that the output
27042 * is completely written to RAM. This field should be read as '1'
27043 * to indicate that the output has been completely written.
27044 * When writing a command completion or response to an internal processor,
27045 * the order of writes has to be such that this field is written last.
27050 /*******************
27051 * hwrm_ring_reset *
27052 *******************/
27055 /* hwrm_ring_reset_input (size:192b/24B) */
27056 struct hwrm_ring_reset_input {
27057 /* The HWRM command request type. */
27060 * The completion ring to send the completion event on. This should
27061 * be the NQ ID returned from the `nq_alloc` HWRM command.
27063 uint16_t cmpl_ring;
27065 * The sequence ID is used by the driver for tracking multiple
27066 * commands. This ID is treated as opaque data by the firmware and
27067 * the value is returned in the `hwrm_resp_hdr` upon completion.
27071 * The target ID of the command:
27072 * * 0x0-0xFFF8 - The function ID
27073 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27074 * * 0xFFFD - Reserved for user-space HWRM interface
27077 uint16_t target_id;
27079 * A physical address pointer pointing to a host buffer that the
27080 * command's response data will be written. This can be either a host
27081 * physical address (HPA) or a guest physical address (GPA) and must
27082 * point to a physically contiguous block of memory.
27084 uint64_t resp_addr;
27087 /* L2 Completion Ring (CR) */
27088 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27090 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
27092 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
27093 /* RoCE Notification Completion Ring (ROCE_CR) */
27094 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27096 * Rx Ring Group. This is to reset rx and aggregation in an atomic
27097 * operation. Completion ring associated with this ring group is
27100 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
27101 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
27102 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
27105 * Physical number of the ring. When ring type is rx_ring_grp, ring id
27106 * actually refers to ring group id.
27109 uint8_t unused_1[4];
27112 /* hwrm_ring_reset_output (size:128b/16B) */
27113 struct hwrm_ring_reset_output {
27114 /* The specific error status for the command. */
27115 uint16_t error_code;
27116 /* The HWRM command request type. */
27118 /* The sequence ID from the original command. */
27120 /* The length of the response data in number of bytes. */
27122 uint8_t unused_0[4];
27123 /* Position of consumer index after ring reset completes. */
27124 uint8_t consumer_idx[3];
27126 * This field is used in Output records to indicate that the output
27127 * is completely written to RAM. This field should be read as '1'
27128 * to indicate that the output has been completely written.
27129 * When writing a command completion or response to an internal processor,
27130 * the order of writes has to be such that this field is written last.
27135 /**************************
27136 * hwrm_ring_aggint_qcaps *
27137 **************************/
27140 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
27141 struct hwrm_ring_aggint_qcaps_input {
27142 /* The HWRM command request type. */
27145 * The completion ring to send the completion event on. This should
27146 * be the NQ ID returned from the `nq_alloc` HWRM command.
27148 uint16_t cmpl_ring;
27150 * The sequence ID is used by the driver for tracking multiple
27151 * commands. This ID is treated as opaque data by the firmware and
27152 * the value is returned in the `hwrm_resp_hdr` upon completion.
27156 * The target ID of the command:
27157 * * 0x0-0xFFF8 - The function ID
27158 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27159 * * 0xFFFD - Reserved for user-space HWRM interface
27162 uint16_t target_id;
27164 * A physical address pointer pointing to a host buffer that the
27165 * command's response data will be written. This can be either a host
27166 * physical address (HPA) or a guest physical address (GPA) and must
27167 * point to a physically contiguous block of memory.
27169 uint64_t resp_addr;
27172 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
27173 struct hwrm_ring_aggint_qcaps_output {
27174 /* The specific error status for the command. */
27175 uint16_t error_code;
27176 /* The HWRM command request type. */
27178 /* The sequence ID from the original command. */
27180 /* The length of the response data in number of bytes. */
27182 uint32_t cmpl_params;
27184 * When this bit is set to '1', int_lat_tmr_min can be configured
27185 * on completion rings.
27187 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
27190 * When this bit is set to '1', int_lat_tmr_max can be configured
27191 * on completion rings.
27193 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
27196 * When this bit is set to '1', timer_reset can be enabled
27197 * on completion rings.
27199 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
27202 * When this bit is set to '1', ring_idle can be enabled
27203 * on completion rings.
27205 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
27208 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
27209 * on completion rings.
27211 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
27214 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
27215 * on completion rings.
27217 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
27220 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
27221 * on completion rings.
27223 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
27226 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
27227 * on completion rings.
27229 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
27232 * When this bit is set to '1', num_cmpl_aggr_int can be configured
27233 * on completion rings.
27235 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
27237 uint32_t nq_params;
27239 * When this bit is set to '1', int_lat_tmr_min can be configured
27240 * on notification queues.
27242 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
27244 /* Minimum value for num_cmpl_dma_aggr */
27245 uint16_t num_cmpl_dma_aggr_min;
27246 /* Maximum value for num_cmpl_dma_aggr */
27247 uint16_t num_cmpl_dma_aggr_max;
27248 /* Minimum value for num_cmpl_dma_aggr_during_int */
27249 uint16_t num_cmpl_dma_aggr_during_int_min;
27250 /* Maximum value for num_cmpl_dma_aggr_during_int */
27251 uint16_t num_cmpl_dma_aggr_during_int_max;
27252 /* Minimum value for cmpl_aggr_dma_tmr */
27253 uint16_t cmpl_aggr_dma_tmr_min;
27254 /* Maximum value for cmpl_aggr_dma_tmr */
27255 uint16_t cmpl_aggr_dma_tmr_max;
27256 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
27257 uint16_t cmpl_aggr_dma_tmr_during_int_min;
27258 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
27259 uint16_t cmpl_aggr_dma_tmr_during_int_max;
27260 /* Minimum value for int_lat_tmr_min */
27261 uint16_t int_lat_tmr_min_min;
27262 /* Maximum value for int_lat_tmr_min */
27263 uint16_t int_lat_tmr_min_max;
27264 /* Minimum value for int_lat_tmr_max */
27265 uint16_t int_lat_tmr_max_min;
27266 /* Maximum value for int_lat_tmr_max */
27267 uint16_t int_lat_tmr_max_max;
27268 /* Minimum value for num_cmpl_aggr_int */
27269 uint16_t num_cmpl_aggr_int_min;
27270 /* Maximum value for num_cmpl_aggr_int */
27271 uint16_t num_cmpl_aggr_int_max;
27272 /* The units for timer parameters, in nanoseconds. */
27273 uint16_t timer_units;
27274 uint8_t unused_0[1];
27276 * This field is used in Output records to indicate that the output
27277 * is completely written to RAM. This field should be read as '1'
27278 * to indicate that the output has been completely written.
27279 * When writing a command completion or response to an internal processor,
27280 * the order of writes has to be such that this field is written last.
27285 /**************************************
27286 * hwrm_ring_cmpl_ring_qaggint_params *
27287 **************************************/
27290 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
27291 struct hwrm_ring_cmpl_ring_qaggint_params_input {
27292 /* The HWRM command request type. */
27295 * The completion ring to send the completion event on. This should
27296 * be the NQ ID returned from the `nq_alloc` HWRM command.
27298 uint16_t cmpl_ring;
27300 * The sequence ID is used by the driver for tracking multiple
27301 * commands. This ID is treated as opaque data by the firmware and
27302 * the value is returned in the `hwrm_resp_hdr` upon completion.
27306 * The target ID of the command:
27307 * * 0x0-0xFFF8 - The function ID
27308 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27309 * * 0xFFFD - Reserved for user-space HWRM interface
27312 uint16_t target_id;
27314 * A physical address pointer pointing to a host buffer that the
27315 * command's response data will be written. This can be either a host
27316 * physical address (HPA) or a guest physical address (GPA) and must
27317 * point to a physically contiguous block of memory.
27319 uint64_t resp_addr;
27320 /* Physical number of completion ring. */
27323 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
27325 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
27327 * Set this flag to 1 when querying parameters on a notification
27328 * queue. Set this flag to 0 when querying parameters on a
27329 * completion queue or completion ring.
27331 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
27333 uint8_t unused_0[4];
27336 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
27337 struct hwrm_ring_cmpl_ring_qaggint_params_output {
27338 /* The specific error status for the command. */
27339 uint16_t error_code;
27340 /* The HWRM command request type. */
27342 /* The sequence ID from the original command. */
27344 /* The length of the response data in number of bytes. */
27348 * When this bit is set to '1', interrupt max
27349 * timer is reset whenever a completion is received.
27351 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
27354 * When this bit is set to '1', ring idle mode
27355 * aggregation will be enabled.
27357 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
27360 * Number of completions to aggregate before DMA
27361 * during the normal mode.
27363 uint16_t num_cmpl_dma_aggr;
27365 * Number of completions to aggregate before DMA
27366 * during the interrupt mode.
27368 uint16_t num_cmpl_dma_aggr_during_int;
27370 * Timer used to aggregate completions before
27371 * DMA during the normal mode (not in interrupt mode).
27373 uint16_t cmpl_aggr_dma_tmr;
27375 * Timer used to aggregate completions before
27376 * DMA when in interrupt mode.
27378 uint16_t cmpl_aggr_dma_tmr_during_int;
27379 /* Minimum time between two interrupts. */
27380 uint16_t int_lat_tmr_min;
27382 * Maximum wait time spent aggregating
27383 * completions before signaling the interrupt after the
27384 * interrupt is enabled.
27386 uint16_t int_lat_tmr_max;
27388 * Minimum number of completions aggregated before signaling
27391 uint16_t num_cmpl_aggr_int;
27392 uint8_t unused_0[7];
27394 * This field is used in Output records to indicate that the output
27395 * is completely written to RAM. This field should be read as '1'
27396 * to indicate that the output has been completely written.
27397 * When writing a command completion or response to an internal processor,
27398 * the order of writes has to be such that this field is written last.
27403 /*****************************************
27404 * hwrm_ring_cmpl_ring_cfg_aggint_params *
27405 *****************************************/
27408 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
27409 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
27410 /* The HWRM command request type. */
27413 * The completion ring to send the completion event on. This should
27414 * be the NQ ID returned from the `nq_alloc` HWRM command.
27416 uint16_t cmpl_ring;
27418 * The sequence ID is used by the driver for tracking multiple
27419 * commands. This ID is treated as opaque data by the firmware and
27420 * the value is returned in the `hwrm_resp_hdr` upon completion.
27424 * The target ID of the command:
27425 * * 0x0-0xFFF8 - The function ID
27426 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27427 * * 0xFFFD - Reserved for user-space HWRM interface
27430 uint16_t target_id;
27432 * A physical address pointer pointing to a host buffer that the
27433 * command's response data will be written. This can be either a host
27434 * physical address (HPA) or a guest physical address (GPA) and must
27435 * point to a physically contiguous block of memory.
27437 uint64_t resp_addr;
27438 /* Physical number of completion ring. */
27442 * When this bit is set to '1', interrupt latency max
27443 * timer is reset whenever a completion is received.
27445 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
27448 * When this bit is set to '1', ring idle mode
27449 * aggregation will be enabled.
27451 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
27454 * Set this flag to 1 when configuring parameters on a
27455 * notification queue. Set this flag to 0 when configuring
27456 * parameters on a completion queue or completion ring.
27458 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
27461 * Number of completions to aggregate before DMA
27462 * during the normal mode.
27464 uint16_t num_cmpl_dma_aggr;
27466 * Number of completions to aggregate before DMA
27467 * during the interrupt mode.
27469 uint16_t num_cmpl_dma_aggr_during_int;
27471 * Timer used to aggregate completions before
27472 * DMA during the normal mode (not in interrupt mode).
27474 uint16_t cmpl_aggr_dma_tmr;
27476 * Timer used to aggregate completions before
27477 * DMA while in interrupt mode.
27479 uint16_t cmpl_aggr_dma_tmr_during_int;
27480 /* Minimum time between two interrupts. */
27481 uint16_t int_lat_tmr_min;
27483 * Maximum wait time spent aggregating
27484 * completions before signaling the interrupt after the
27485 * interrupt is enabled.
27487 uint16_t int_lat_tmr_max;
27489 * Minimum number of completions aggregated before signaling
27492 uint16_t num_cmpl_aggr_int;
27494 * Bitfield that indicates which parameters are to be applied. Only
27495 * required when configuring devices with notification queues, and
27496 * used in that case to set certain parameters on completion queues
27497 * and others on notification queues.
27501 * This bit must be '1' for the num_cmpl_dma_aggr field to be
27504 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
27507 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
27510 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
27513 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
27516 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
27519 * This bit must be '1' for the int_lat_tmr_min field to be
27522 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
27525 * This bit must be '1' for the int_lat_tmr_max field to be
27528 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
27531 * This bit must be '1' for the num_cmpl_aggr_int field to be
27534 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
27536 uint8_t unused_0[4];
27539 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
27540 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
27541 /* The specific error status for the command. */
27542 uint16_t error_code;
27543 /* The HWRM command request type. */
27545 /* The sequence ID from the original command. */
27547 /* The length of the response data in number of bytes. */
27549 uint8_t unused_0[7];
27551 * This field is used in Output records to indicate that the output
27552 * is completely written to RAM. This field should be read as '1'
27553 * to indicate that the output has been completely written.
27554 * When writing a command completion or response to an internal processor,
27555 * the order of writes has to be such that this field is written last.
27560 /***********************
27561 * hwrm_ring_grp_alloc *
27562 ***********************/
27565 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
27566 struct hwrm_ring_grp_alloc_input {
27567 /* The HWRM command request type. */
27570 * The completion ring to send the completion event on. This should
27571 * be the NQ ID returned from the `nq_alloc` HWRM command.
27573 uint16_t cmpl_ring;
27575 * The sequence ID is used by the driver for tracking multiple
27576 * commands. This ID is treated as opaque data by the firmware and
27577 * the value is returned in the `hwrm_resp_hdr` upon completion.
27581 * The target ID of the command:
27582 * * 0x0-0xFFF8 - The function ID
27583 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27584 * * 0xFFFD - Reserved for user-space HWRM interface
27587 uint16_t target_id;
27589 * A physical address pointer pointing to a host buffer that the
27590 * command's response data will be written. This can be either a host
27591 * physical address (HPA) or a guest physical address (GPA) and must
27592 * point to a physically contiguous block of memory.
27594 uint64_t resp_addr;
27596 * This value identifies the CR associated with the ring
27601 * This value identifies the main RR associated with the ring
27606 * This value identifies the aggregation RR associated with
27607 * the ring group. If this value is 0xFF... (All Fs), then no
27608 * Aggregation ring will be set.
27612 * This value identifies the statistics context associated
27613 * with the ring group.
27618 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
27619 struct hwrm_ring_grp_alloc_output {
27620 /* The specific error status for the command. */
27621 uint16_t error_code;
27622 /* The HWRM command request type. */
27624 /* The sequence ID from the original command. */
27626 /* The length of the response data in number of bytes. */
27629 * This is the ring group ID value. Use this value to program
27630 * the default ring group for the VNIC or as table entries
27631 * in an RSS/COS context.
27633 uint32_t ring_group_id;
27634 uint8_t unused_0[3];
27636 * This field is used in Output records to indicate that the output
27637 * is completely written to RAM. This field should be read as '1'
27638 * to indicate that the output has been completely written.
27639 * When writing a command completion or response to an internal processor,
27640 * the order of writes has to be such that this field is written last.
27645 /**********************
27646 * hwrm_ring_grp_free *
27647 **********************/
27650 /* hwrm_ring_grp_free_input (size:192b/24B) */
27651 struct hwrm_ring_grp_free_input {
27652 /* The HWRM command request type. */
27655 * The completion ring to send the completion event on. This should
27656 * be the NQ ID returned from the `nq_alloc` HWRM command.
27658 uint16_t cmpl_ring;
27660 * The sequence ID is used by the driver for tracking multiple
27661 * commands. This ID is treated as opaque data by the firmware and
27662 * the value is returned in the `hwrm_resp_hdr` upon completion.
27666 * The target ID of the command:
27667 * * 0x0-0xFFF8 - The function ID
27668 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27669 * * 0xFFFD - Reserved for user-space HWRM interface
27672 uint16_t target_id;
27674 * A physical address pointer pointing to a host buffer that the
27675 * command's response data will be written. This can be either a host
27676 * physical address (HPA) or a guest physical address (GPA) and must
27677 * point to a physically contiguous block of memory.
27679 uint64_t resp_addr;
27680 /* This is the ring group ID value. */
27681 uint32_t ring_group_id;
27682 uint8_t unused_0[4];
27685 /* hwrm_ring_grp_free_output (size:128b/16B) */
27686 struct hwrm_ring_grp_free_output {
27687 /* The specific error status for the command. */
27688 uint16_t error_code;
27689 /* The HWRM command request type. */
27691 /* The sequence ID from the original command. */
27693 /* The length of the response data in number of bytes. */
27695 uint8_t unused_0[7];
27697 * This field is used in Output records to indicate that the output
27698 * is completely written to RAM. This field should be read as '1'
27699 * to indicate that the output has been completely written.
27700 * When writing a command completion or response to an internal processor,
27701 * the order of writes has to be such that this field is written last.
27706 * special reserved flow ID to identify per function default
27707 * flows for vSwitch offload
27709 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
27711 * special reserved flow ID to identify per function RoCEv1
27714 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
27716 * special reserved flow ID to identify per function RoCEv2
27719 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
27721 * special reserved flow ID to identify per function RoCEv2
27724 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
27726 /****************************
27727 * hwrm_cfa_l2_filter_alloc *
27728 ****************************/
27731 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
27732 struct hwrm_cfa_l2_filter_alloc_input {
27733 /* The HWRM command request type. */
27736 * The completion ring to send the completion event on. This should
27737 * be the NQ ID returned from the `nq_alloc` HWRM command.
27739 uint16_t cmpl_ring;
27741 * The sequence ID is used by the driver for tracking multiple
27742 * commands. This ID is treated as opaque data by the firmware and
27743 * the value is returned in the `hwrm_resp_hdr` upon completion.
27747 * The target ID of the command:
27748 * * 0x0-0xFFF8 - The function ID
27749 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27750 * * 0xFFFD - Reserved for user-space HWRM interface
27753 uint16_t target_id;
27755 * A physical address pointer pointing to a host buffer that the
27756 * command's response data will be written. This can be either a host
27757 * physical address (HPA) or a guest physical address (GPA) and must
27758 * point to a physically contiguous block of memory.
27760 uint64_t resp_addr;
27763 * Enumeration denoting the RX, TX type of the resource.
27764 * This enumeration is used for resources that are similar for both
27765 * TX and RX paths of the chip.
27767 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
27770 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
27773 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
27775 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
27776 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
27777 /* Setting of this flag indicates the applicability to the loopback path. */
27778 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
27781 * Setting of this flag indicates drop action. If this flag is not set,
27782 * then it should be considered accept action.
27784 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
27787 * If this flag is set, all t_l2_* fields are invalid
27788 * and they should not be specified.
27789 * If this flag is set, then l2_* fields refer to
27790 * fields of outermost L2 header.
27792 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
27795 * Enumeration denoting NO_ROCE_L2 to support old drivers.
27796 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
27798 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
27800 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
27801 /* To support old drivers */
27802 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
27803 (UINT32_C(0x0) << 4)
27804 /* Only L2 traffic */
27805 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
27806 (UINT32_C(0x1) << 4)
27807 /* Roce & L2 traffic */
27808 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
27809 (UINT32_C(0x2) << 4)
27810 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
27811 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
27813 * Setting of this flag indicates that no XDP filter is created with
27815 * 0 - legacy behavior, XDP filter is created with L2 filter
27816 * 1 - XDP filter won't be created with L2 filter
27818 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
27821 * Setting this flag to 1 indicate the L2 fields in this command
27822 * pertain to source fields. Setting this flag to 0 indicate the
27823 * L2 fields in this command pertain to the destination fields
27824 * and this is the default/legacy behavior.
27826 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
27830 * This bit must be '1' for the l2_addr field to be
27833 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
27836 * This bit must be '1' for the l2_addr_mask field to be
27839 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
27842 * This bit must be '1' for the l2_ovlan field to be
27845 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
27848 * This bit must be '1' for the l2_ovlan_mask field to be
27851 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
27854 * This bit must be '1' for the l2_ivlan field to be
27857 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
27860 * This bit must be '1' for the l2_ivlan_mask field to be
27863 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
27866 * This bit must be '1' for the t_l2_addr field to be
27869 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
27872 * This bit must be '1' for the t_l2_addr_mask field to be
27875 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
27878 * This bit must be '1' for the t_l2_ovlan field to be
27881 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
27884 * This bit must be '1' for the t_l2_ovlan_mask field to be
27887 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
27890 * This bit must be '1' for the t_l2_ivlan field to be
27893 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
27896 * This bit must be '1' for the t_l2_ivlan_mask field to be
27899 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
27902 * This bit must be '1' for the src_type field to be
27905 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
27908 * This bit must be '1' for the src_id field to be
27911 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
27914 * This bit must be '1' for the tunnel_type field to be
27917 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27920 * This bit must be '1' for the dst_id field to be
27923 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27926 * This bit must be '1' for the mirror_vnic_id field to be
27929 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27932 * This bit must be '1' for the num_vlans field to be
27935 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
27938 * This bit must be '1' for the t_num_vlans field to be
27941 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
27944 * This value sets the match value for the L2 MAC address.
27945 * Destination MAC address for RX path.
27946 * Source MAC address for TX path.
27948 uint8_t l2_addr[6];
27949 /* This value sets the match value for the number of VLANs. */
27952 * This value sets the match value for the number of VLANs
27953 * in the tunnel headers.
27955 uint8_t t_num_vlans;
27957 * This value sets the mask value for the L2 address.
27958 * A value of 0 will mask the corresponding bit from
27961 uint8_t l2_addr_mask[6];
27962 /* This value sets VLAN ID value for outer VLAN. */
27965 * This value sets the mask value for the ovlan id.
27966 * A value of 0 will mask the corresponding bit from
27969 uint16_t l2_ovlan_mask;
27970 /* This value sets VLAN ID value for inner VLAN. */
27973 * This value sets the mask value for the ivlan id.
27974 * A value of 0 will mask the corresponding bit from
27977 uint16_t l2_ivlan_mask;
27978 uint8_t unused_1[2];
27980 * This value sets the match value for the tunnel
27982 * Destination MAC address for RX path.
27983 * Source MAC address for TX path.
27985 uint8_t t_l2_addr[6];
27986 uint8_t unused_2[2];
27988 * This value sets the mask value for the tunnel L2
27990 * A value of 0 will mask the corresponding bit from
27993 uint8_t t_l2_addr_mask[6];
27994 /* This value sets VLAN ID value for tunnel outer VLAN. */
27995 uint16_t t_l2_ovlan;
27997 * This value sets the mask value for the tunnel ovlan id.
27998 * A value of 0 will mask the corresponding bit from
28001 uint16_t t_l2_ovlan_mask;
28002 /* This value sets VLAN ID value for tunnel inner VLAN. */
28003 uint16_t t_l2_ivlan;
28005 * This value sets the mask value for the tunnel ivlan id.
28006 * A value of 0 will mask the corresponding bit from
28009 uint16_t t_l2_ivlan_mask;
28010 /* This value identifies the type of source of the packet. */
28013 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
28014 /* Physical function */
28015 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
28016 /* Virtual function */
28017 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
28018 /* Virtual NIC of a function */
28019 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
28020 /* Embedded processor for CFA management */
28021 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
28022 /* Embedded processor for OOB management */
28023 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
28024 /* Embedded processor for RoCE */
28025 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
28026 /* Embedded processor for network proxy functions */
28027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
28028 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
28029 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
28032 * This value is the id of the source.
28033 * For a network port, it represents port_id.
28034 * For a physical function, it represents fid.
28035 * For a virtual function, it represents vf_id.
28036 * For a vnic, it represents vnic_id.
28037 * For embedded processors, this id is not valid.
28040 * 1. The function ID is implied if it src_id is
28041 * not provided for a src_type that is either
28045 uint8_t tunnel_type;
28047 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28049 /* Virtual eXtensible Local Area Network (VXLAN) */
28050 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28052 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28053 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28055 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28056 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28059 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28061 /* Generic Network Virtualization Encapsulation (Geneve) */
28062 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28064 /* Multi-Protocol Label Switching (MPLS) */
28065 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28067 /* Stateless Transport Tunnel (STT) */
28068 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
28070 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28071 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28073 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28074 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28076 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28077 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28079 /* Use fixed layer 2 ether type of 0xFFFF */
28080 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28082 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28083 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28085 /* Any tunneled traffic */
28086 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28088 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28089 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28092 * If set, this value shall represent the
28093 * Logical VNIC ID of the destination VNIC for the RX
28094 * path and network port id of the destination port for
28099 * Logical VNIC ID of the VNIC where traffic is
28102 uint16_t mirror_vnic_id;
28104 * This hint is provided to help in placing
28105 * the filter in the filter table.
28108 /* No preference */
28109 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
28111 /* Above the given filter */
28112 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
28114 /* Below the given filter */
28115 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
28117 /* As high as possible */
28118 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
28120 /* As low as possible */
28121 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
28123 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
28124 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
28128 * This is the ID of the filter that goes along with
28131 * This field is valid only for the following values.
28132 * 1 - Above the given filter
28133 * 2 - Below the given filter
28135 uint64_t l2_filter_id_hint;
28138 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
28139 struct hwrm_cfa_l2_filter_alloc_output {
28140 /* The specific error status for the command. */
28141 uint16_t error_code;
28142 /* The HWRM command request type. */
28144 /* The sequence ID from the original command. */
28146 /* The length of the response data in number of bytes. */
28149 * This value identifies a set of CFA data structures used for an L2
28152 uint64_t l2_filter_id;
28154 * The flow id value in bit 0-29 is the actual ID of the flow
28155 * associated with this filter and it shall be used to match
28156 * and associate the flow identifier returned in completion
28157 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28158 * shall indicate no valid flow id.
28161 /* Indicate the flow id value. */
28162 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28163 UINT32_C(0x3fffffff)
28164 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28165 /* Indicate type of the flow. */
28166 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
28167 UINT32_C(0x40000000)
28169 * If this bit set to 0, then it indicates that the flow is
28172 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28173 (UINT32_C(0x0) << 30)
28175 * If this bit is set to 1, then it indicates that the flow is
28178 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28179 (UINT32_C(0x1) << 30)
28180 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28181 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28182 /* Indicate the flow direction. */
28183 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
28184 UINT32_C(0x80000000)
28185 /* If this bit set to 0, then it indicates rx flow. */
28186 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28187 (UINT32_C(0x0) << 31)
28188 /* If this bit is set to 1, then it indicates that tx flow. */
28189 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28190 (UINT32_C(0x1) << 31)
28191 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28192 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28193 uint8_t unused_0[3];
28195 * This field is used in Output records to indicate that the output
28196 * is completely written to RAM. This field should be read as '1'
28197 * to indicate that the output has been completely written.
28198 * When writing a command completion or response to an internal processor,
28199 * the order of writes has to be such that this field is written last.
28204 /***************************
28205 * hwrm_cfa_l2_filter_free *
28206 ***************************/
28209 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
28210 struct hwrm_cfa_l2_filter_free_input {
28211 /* The HWRM command request type. */
28214 * The completion ring to send the completion event on. This should
28215 * be the NQ ID returned from the `nq_alloc` HWRM command.
28217 uint16_t cmpl_ring;
28219 * The sequence ID is used by the driver for tracking multiple
28220 * commands. This ID is treated as opaque data by the firmware and
28221 * the value is returned in the `hwrm_resp_hdr` upon completion.
28225 * The target ID of the command:
28226 * * 0x0-0xFFF8 - The function ID
28227 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28228 * * 0xFFFD - Reserved for user-space HWRM interface
28231 uint16_t target_id;
28233 * A physical address pointer pointing to a host buffer that the
28234 * command's response data will be written. This can be either a host
28235 * physical address (HPA) or a guest physical address (GPA) and must
28236 * point to a physically contiguous block of memory.
28238 uint64_t resp_addr;
28240 * This value identifies a set of CFA data structures used for an L2
28243 uint64_t l2_filter_id;
28246 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
28247 struct hwrm_cfa_l2_filter_free_output {
28248 /* The specific error status for the command. */
28249 uint16_t error_code;
28250 /* The HWRM command request type. */
28252 /* The sequence ID from the original command. */
28254 /* The length of the response data in number of bytes. */
28256 uint8_t unused_0[7];
28258 * This field is used in Output records to indicate that the output
28259 * is completely written to RAM. This field should be read as '1'
28260 * to indicate that the output has been completely written.
28261 * When writing a command completion or response to an internal processor,
28262 * the order of writes has to be such that this field is written last.
28267 /**************************
28268 * hwrm_cfa_l2_filter_cfg *
28269 **************************/
28272 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
28273 struct hwrm_cfa_l2_filter_cfg_input {
28274 /* The HWRM command request type. */
28277 * The completion ring to send the completion event on. This should
28278 * be the NQ ID returned from the `nq_alloc` HWRM command.
28280 uint16_t cmpl_ring;
28282 * The sequence ID is used by the driver for tracking multiple
28283 * commands. This ID is treated as opaque data by the firmware and
28284 * the value is returned in the `hwrm_resp_hdr` upon completion.
28288 * The target ID of the command:
28289 * * 0x0-0xFFF8 - The function ID
28290 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28291 * * 0xFFFD - Reserved for user-space HWRM interface
28294 uint16_t target_id;
28296 * A physical address pointer pointing to a host buffer that the
28297 * command's response data will be written. This can be either a host
28298 * physical address (HPA) or a guest physical address (GPA) and must
28299 * point to a physically contiguous block of memory.
28301 uint64_t resp_addr;
28304 * Enumeration denoting the RX, TX type of the resource.
28305 * This enumeration is used for resources that are similar for both
28306 * TX and RX paths of the chip.
28308 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
28311 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
28314 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
28316 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
28317 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
28319 * Setting of this flag indicates drop action. If this flag is not set,
28320 * then it should be considered accept action.
28322 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
28325 * Enumeration denoting NO_ROCE_L2 to support old drivers.
28326 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
28328 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
28330 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
28331 /* To support old drivers */
28332 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
28333 (UINT32_C(0x0) << 2)
28334 /* Only L2 traffic */
28335 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
28336 (UINT32_C(0x1) << 2)
28337 /* Roce & L2 traffic */
28338 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
28339 (UINT32_C(0x2) << 2)
28340 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
28341 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
28344 * This bit must be '1' for the dst_id field to be
28347 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
28350 * This bit must be '1' for the new_mirror_vnic_id field to be
28353 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
28356 * This value identifies a set of CFA data structures used for an L2
28359 uint64_t l2_filter_id;
28361 * If set, this value shall represent the
28362 * Logical VNIC ID of the destination VNIC for the RX
28363 * path and network port id of the destination port for
28368 * New Logical VNIC ID of the VNIC where traffic is
28371 uint32_t new_mirror_vnic_id;
28374 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
28375 struct hwrm_cfa_l2_filter_cfg_output {
28376 /* The specific error status for the command. */
28377 uint16_t error_code;
28378 /* The HWRM command request type. */
28380 /* The sequence ID from the original command. */
28382 /* The length of the response data in number of bytes. */
28384 uint8_t unused_0[7];
28386 * This field is used in Output records to indicate that the output
28387 * is completely written to RAM. This field should be read as '1'
28388 * to indicate that the output has been completely written.
28389 * When writing a command completion or response to an internal processor,
28390 * the order of writes has to be such that this field is written last.
28395 /***************************
28396 * hwrm_cfa_l2_set_rx_mask *
28397 ***************************/
28400 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
28401 struct hwrm_cfa_l2_set_rx_mask_input {
28402 /* The HWRM command request type. */
28405 * The completion ring to send the completion event on. This should
28406 * be the NQ ID returned from the `nq_alloc` HWRM command.
28408 uint16_t cmpl_ring;
28410 * The sequence ID is used by the driver for tracking multiple
28411 * commands. This ID is treated as opaque data by the firmware and
28412 * the value is returned in the `hwrm_resp_hdr` upon completion.
28416 * The target ID of the command:
28417 * * 0x0-0xFFF8 - The function ID
28418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28419 * * 0xFFFD - Reserved for user-space HWRM interface
28422 uint16_t target_id;
28424 * A physical address pointer pointing to a host buffer that the
28425 * command's response data will be written. This can be either a host
28426 * physical address (HPA) or a guest physical address (GPA) and must
28427 * point to a physically contiguous block of memory.
28429 uint64_t resp_addr;
28434 * When this bit is '1', the function is requested to accept
28435 * multi-cast packets specified by the multicast addr table.
28437 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
28440 * When this bit is '1', the function is requested to accept
28441 * all multi-cast packets.
28443 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
28446 * When this bit is '1', the function is requested to accept
28447 * broadcast packets.
28449 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
28452 * When this bit is '1', the function is requested to be
28453 * put in the promiscuous mode.
28455 * The HWRM should accept any function to set up
28456 * promiscuous mode.
28458 * The HWRM shall follow the semantics below for the
28459 * promiscuous mode support.
28460 * # When partitioning is not enabled on a port
28461 * (i.e. single PF on the port), then the PF shall
28462 * be allowed to be in the promiscuous mode. When the
28463 * PF is in the promiscuous mode, then it shall
28464 * receive all host bound traffic on that port.
28465 * # When partitioning is enabled on a port
28466 * (i.e. multiple PFs per port) and a PF on that
28467 * port is in the promiscuous mode, then the PF
28468 * receives all traffic within that partition as
28469 * identified by a unique identifier for the
28470 * PF (e.g. S-Tag). If a unique outer VLAN
28471 * for the PF is specified, then the setting of
28472 * promiscuous mode on that PF shall result in the
28473 * PF receiving all host bound traffic with matching
28475 * # A VF shall can be set in the promiscuous mode.
28476 * In the promiscuous mode, the VF does not receive any
28477 * traffic unless a unique outer VLAN for the
28478 * VF is specified. If a unique outer VLAN
28479 * for the VF is specified, then the setting of
28480 * promiscuous mode on that VF shall result in the
28481 * VF receiving all host bound traffic with the
28482 * matching outer VLAN.
28483 * # The HWRM shall allow the setting of promiscuous
28484 * mode on a function independently from the
28485 * promiscuous mode settings on other functions.
28487 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
28490 * If this flag is set, the corresponding RX
28491 * filters shall be set up to cover multicast/broadcast
28492 * filters for the outermost Layer 2 destination MAC
28495 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
28498 * If this flag is set, the corresponding RX
28499 * filters shall be set up to cover multicast/broadcast
28500 * filters for the VLAN-tagged packets that match the
28501 * TPID and VID fields of VLAN tags in the VLAN tag
28502 * table specified in this command.
28504 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
28507 * If this flag is set, the corresponding RX
28508 * filters shall be set up to cover multicast/broadcast
28509 * filters for non-VLAN tagged packets and VLAN-tagged
28510 * packets that match the TPID and VID fields of VLAN
28511 * tags in the VLAN tag table specified in this command.
28513 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
28516 * If this flag is set, the corresponding RX
28517 * filters shall be set up to cover multicast/broadcast
28518 * filters for non-VLAN tagged packets and VLAN-tagged
28519 * packets matching any VLAN tag.
28521 * If this flag is set, then the HWRM shall ignore
28522 * VLAN tags specified in vlan_tag_tbl.
28524 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
28525 * flags is set, then the HWRM shall ignore
28526 * VLAN tags specified in vlan_tag_tbl.
28528 * The HWRM client shall set at most one flag out of
28529 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
28531 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
28533 /* This is the address for mcast address tbl. */
28534 uint64_t mc_tbl_addr;
28536 * This value indicates how many entries in mc_tbl are valid.
28537 * Each entry is 6 bytes.
28539 uint32_t num_mc_entries;
28540 uint8_t unused_0[4];
28542 * This is the address for VLAN tag table.
28543 * Each VLAN entry in the table is 4 bytes of a VLAN tag
28544 * including TPID, PCP, DEI, and VID fields in network byte
28547 uint64_t vlan_tag_tbl_addr;
28549 * This value indicates how many entries in vlan_tag_tbl are
28550 * valid. Each entry is 4 bytes.
28552 uint32_t num_vlan_tags;
28553 uint8_t unused_1[4];
28556 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
28557 struct hwrm_cfa_l2_set_rx_mask_output {
28558 /* The specific error status for the command. */
28559 uint16_t error_code;
28560 /* The HWRM command request type. */
28562 /* The sequence ID from the original command. */
28564 /* The length of the response data in number of bytes. */
28566 uint8_t unused_0[7];
28568 * This field is used in Output records to indicate that the output
28569 * is completely written to RAM. This field should be read as '1'
28570 * to indicate that the output has been completely written.
28571 * When writing a command completion or response to an internal processor,
28572 * the order of writes has to be such that this field is written last.
28577 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
28578 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
28580 * command specific error codes that goes to
28581 * the cmd_err field in Common HWRM Error Response.
28584 /* Unknown error */
28585 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
28587 /* Unable to complete operation due to conflict with Ntuple Filter */
28588 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
28590 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
28591 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
28592 uint8_t unused_0[7];
28595 /*******************************
28596 * hwrm_cfa_vlan_antispoof_cfg *
28597 *******************************/
28600 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
28601 struct hwrm_cfa_vlan_antispoof_cfg_input {
28602 /* The HWRM command request type. */
28605 * The completion ring to send the completion event on. This should
28606 * be the NQ ID returned from the `nq_alloc` HWRM command.
28608 uint16_t cmpl_ring;
28610 * The sequence ID is used by the driver for tracking multiple
28611 * commands. This ID is treated as opaque data by the firmware and
28612 * the value is returned in the `hwrm_resp_hdr` upon completion.
28616 * The target ID of the command:
28617 * * 0x0-0xFFF8 - The function ID
28618 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28619 * * 0xFFFD - Reserved for user-space HWRM interface
28622 uint16_t target_id;
28624 * A physical address pointer pointing to a host buffer that the
28625 * command's response data will be written. This can be either a host
28626 * physical address (HPA) or a guest physical address (GPA) and must
28627 * point to a physically contiguous block of memory.
28629 uint64_t resp_addr;
28631 * Function ID of the function that is being configured.
28632 * Only valid for a VF FID configured by the PF.
28635 uint8_t unused_0[2];
28636 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
28637 uint32_t num_vlan_entries;
28639 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
28640 * antispoof table. Each table entry contains the 16-bit TPID
28641 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
28642 * all in network order to match hwrm_cfa_l2_set_rx_mask.
28643 * For an individual VLAN entry, the mask value should be 0xfff
28644 * for the 12-bit VLAN ID.
28646 uint64_t vlan_tag_mask_tbl_addr;
28649 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
28650 struct hwrm_cfa_vlan_antispoof_cfg_output {
28651 /* The specific error status for the command. */
28652 uint16_t error_code;
28653 /* The HWRM command request type. */
28655 /* The sequence ID from the original command. */
28657 /* The length of the response data in number of bytes. */
28659 uint8_t unused_0[7];
28661 * This field is used in Output records to indicate that the output
28662 * is completely written to RAM. This field should be read as '1'
28663 * to indicate that the output has been completely written.
28664 * When writing a command completion or response to an internal processor,
28665 * the order of writes has to be such that this field is written last.
28670 /********************************
28671 * hwrm_cfa_vlan_antispoof_qcfg *
28672 ********************************/
28675 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
28676 struct hwrm_cfa_vlan_antispoof_qcfg_input {
28677 /* The HWRM command request type. */
28680 * The completion ring to send the completion event on. This should
28681 * be the NQ ID returned from the `nq_alloc` HWRM command.
28683 uint16_t cmpl_ring;
28685 * The sequence ID is used by the driver for tracking multiple
28686 * commands. This ID is treated as opaque data by the firmware and
28687 * the value is returned in the `hwrm_resp_hdr` upon completion.
28691 * The target ID of the command:
28692 * * 0x0-0xFFF8 - The function ID
28693 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28694 * * 0xFFFD - Reserved for user-space HWRM interface
28697 uint16_t target_id;
28699 * A physical address pointer pointing to a host buffer that the
28700 * command's response data will be written. This can be either a host
28701 * physical address (HPA) or a guest physical address (GPA) and must
28702 * point to a physically contiguous block of memory.
28704 uint64_t resp_addr;
28706 * Function ID of the function that is being queried.
28707 * Only valid for a VF FID queried by the PF.
28710 uint8_t unused_0[2];
28712 * Maximum number of VLAN entries the firmware is allowed to DMA
28713 * to vlan_tag_mask_tbl.
28715 uint32_t max_vlan_entries;
28717 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
28718 * antispoof table to which firmware will DMA to. Each table
28719 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
28720 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
28721 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
28722 * the mask value should be 0xfff for the 12-bit VLAN ID.
28724 uint64_t vlan_tag_mask_tbl_addr;
28727 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
28728 struct hwrm_cfa_vlan_antispoof_qcfg_output {
28729 /* The specific error status for the command. */
28730 uint16_t error_code;
28731 /* The HWRM command request type. */
28733 /* The sequence ID from the original command. */
28735 /* The length of the response data in number of bytes. */
28737 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
28738 uint32_t num_vlan_entries;
28739 uint8_t unused_0[3];
28741 * This field is used in Output records to indicate that the output
28742 * is completely written to RAM. This field should be read as '1'
28743 * to indicate that the output has been completely written.
28744 * When writing a command completion or response to an internal processor,
28745 * the order of writes has to be such that this field is written last.
28750 /********************************
28751 * hwrm_cfa_tunnel_filter_alloc *
28752 ********************************/
28755 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
28756 struct hwrm_cfa_tunnel_filter_alloc_input {
28757 /* The HWRM command request type. */
28760 * The completion ring to send the completion event on. This should
28761 * be the NQ ID returned from the `nq_alloc` HWRM command.
28763 uint16_t cmpl_ring;
28765 * The sequence ID is used by the driver for tracking multiple
28766 * commands. This ID is treated as opaque data by the firmware and
28767 * the value is returned in the `hwrm_resp_hdr` upon completion.
28771 * The target ID of the command:
28772 * * 0x0-0xFFF8 - The function ID
28773 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28774 * * 0xFFFD - Reserved for user-space HWRM interface
28777 uint16_t target_id;
28779 * A physical address pointer pointing to a host buffer that the
28780 * command's response data will be written. This can be either a host
28781 * physical address (HPA) or a guest physical address (GPA) and must
28782 * point to a physically contiguous block of memory.
28784 uint64_t resp_addr;
28786 /* Setting of this flag indicates the applicability to the loopback path. */
28787 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
28791 * This bit must be '1' for the l2_filter_id field to be
28794 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
28797 * This bit must be '1' for the l2_addr field to be
28800 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
28803 * This bit must be '1' for the l2_ivlan field to be
28806 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
28809 * This bit must be '1' for the l3_addr field to be
28812 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
28815 * This bit must be '1' for the l3_addr_type field to be
28818 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
28821 * This bit must be '1' for the t_l3_addr_type field to be
28824 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
28827 * This bit must be '1' for the t_l3_addr field to be
28830 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
28833 * This bit must be '1' for the tunnel_type field to be
28836 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
28839 * This bit must be '1' for the vni field to be
28842 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
28845 * This bit must be '1' for the dst_vnic_id field to be
28848 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
28851 * This bit must be '1' for the mirror_vnic_id field to be
28854 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
28857 * This value identifies a set of CFA data structures used for an L2
28860 uint64_t l2_filter_id;
28862 * This value sets the match value for the inner L2
28864 * Destination MAC address for RX path.
28865 * Source MAC address for TX path.
28867 uint8_t l2_addr[6];
28869 * This value sets VLAN ID value for inner VLAN.
28870 * Only 12-bits of VLAN ID are used in setting the filter.
28874 * The value of inner destination IP address to be used in filtering.
28875 * For IPv4, first four bytes represent the IP address.
28877 uint32_t l3_addr[4];
28879 * The value of tunnel destination IP address to be used in filtering.
28880 * For IPv4, first four bytes represent the IP address.
28882 uint32_t t_l3_addr[4];
28884 * This value indicates the type of inner IP address.
28887 * All others are invalid.
28889 uint8_t l3_addr_type;
28891 * This value indicates the type of tunnel IP address.
28894 * All others are invalid.
28896 uint8_t t_l3_addr_type;
28898 uint8_t tunnel_type;
28900 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28902 /* Virtual eXtensible Local Area Network (VXLAN) */
28903 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28905 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28906 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28908 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28909 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28912 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28914 /* Generic Network Virtualization Encapsulation (Geneve) */
28915 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28917 /* Multi-Protocol Label Switching (MPLS) */
28918 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28920 /* Stateless Transport Tunnel (STT) */
28921 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
28923 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28924 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28926 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28927 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28929 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28930 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28932 /* Use fixed layer 2 ether type of 0xFFFF */
28933 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28935 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28936 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28938 /* Any tunneled traffic */
28939 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28941 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28942 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28944 * tunnel_flags allows the user to indicate the tunnel tag detection
28945 * for the tunnel type specified in tunnel_type.
28947 uint8_t tunnel_flags;
28949 * If the tunnel_type is geneve, then this bit indicates if we
28950 * need to match the geneve OAM packet.
28951 * If the tunnel_type is nvgre or gre, then this bit indicates if
28952 * we need to detect checksum present bit in geneve header.
28953 * If the tunnel_type is mpls, then this bit indicates if we need
28954 * to match mpls packet with explicit IPV4/IPV6 null header.
28956 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
28959 * If the tunnel_type is geneve, then this bit indicates if we
28960 * need to detect the critical option bit set in the oam packet.
28961 * If the tunnel_type is nvgre or gre, then this bit indicates
28962 * if we need to match nvgre packets with key present bit set in
28964 * If the tunnel_type is mpls, then this bit indicates if we
28965 * need to match mpls packet with S bit from inner/second label.
28967 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
28970 * If the tunnel_type is geneve, then this bit indicates if we
28971 * need to match geneve packet with extended header bit set in
28973 * If the tunnel_type is nvgre or gre, then this bit indicates
28974 * if we need to match nvgre packets with sequence number
28975 * present bit set in gre header.
28976 * If the tunnel_type is mpls, then this bit indicates if we
28977 * need to match mpls packet with S bit from out/first label.
28979 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
28982 * Virtual Network Identifier (VNI). Only valid with
28983 * tunnel_types VXLAN, NVGRE, and Geneve.
28984 * Only lower 24-bits of VNI field are used
28985 * in setting up the filter.
28988 /* Logical VNIC ID of the destination VNIC. */
28989 uint32_t dst_vnic_id;
28991 * Logical VNIC ID of the VNIC where traffic is
28994 uint32_t mirror_vnic_id;
28997 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
28998 struct hwrm_cfa_tunnel_filter_alloc_output {
28999 /* The specific error status for the command. */
29000 uint16_t error_code;
29001 /* The HWRM command request type. */
29003 /* The sequence ID from the original command. */
29005 /* The length of the response data in number of bytes. */
29007 /* This value is an opaque id into CFA data structures. */
29008 uint64_t tunnel_filter_id;
29010 * The flow id value in bit 0-29 is the actual ID of the flow
29011 * associated with this filter and it shall be used to match
29012 * and associate the flow identifier returned in completion
29013 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29014 * shall indicate no valid flow id.
29017 /* Indicate the flow id value. */
29018 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29019 UINT32_C(0x3fffffff)
29020 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29021 /* Indicate type of the flow. */
29022 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
29023 UINT32_C(0x40000000)
29025 * If this bit set to 0, then it indicates that the flow is
29028 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29029 (UINT32_C(0x0) << 30)
29031 * If this bit is set to 1, then it indicates that the flow is
29034 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29035 (UINT32_C(0x1) << 30)
29036 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29037 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29038 /* Indicate the flow direction. */
29039 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
29040 UINT32_C(0x80000000)
29041 /* If this bit set to 0, then it indicates rx flow. */
29042 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29043 (UINT32_C(0x0) << 31)
29044 /* If this bit is set to 1, then it indicates that tx flow. */
29045 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29046 (UINT32_C(0x1) << 31)
29047 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29048 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29049 uint8_t unused_0[3];
29051 * This field is used in Output records to indicate that the output
29052 * is completely written to RAM. This field should be read as '1'
29053 * to indicate that the output has been completely written.
29054 * When writing a command completion or response to an internal processor,
29055 * the order of writes has to be such that this field is written last.
29060 /*******************************
29061 * hwrm_cfa_tunnel_filter_free *
29062 *******************************/
29065 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
29066 struct hwrm_cfa_tunnel_filter_free_input {
29067 /* The HWRM command request type. */
29070 * The completion ring to send the completion event on. This should
29071 * be the NQ ID returned from the `nq_alloc` HWRM command.
29073 uint16_t cmpl_ring;
29075 * The sequence ID is used by the driver for tracking multiple
29076 * commands. This ID is treated as opaque data by the firmware and
29077 * the value is returned in the `hwrm_resp_hdr` upon completion.
29081 * The target ID of the command:
29082 * * 0x0-0xFFF8 - The function ID
29083 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29084 * * 0xFFFD - Reserved for user-space HWRM interface
29087 uint16_t target_id;
29089 * A physical address pointer pointing to a host buffer that the
29090 * command's response data will be written. This can be either a host
29091 * physical address (HPA) or a guest physical address (GPA) and must
29092 * point to a physically contiguous block of memory.
29094 uint64_t resp_addr;
29095 /* This value is an opaque id into CFA data structures. */
29096 uint64_t tunnel_filter_id;
29099 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
29100 struct hwrm_cfa_tunnel_filter_free_output {
29101 /* The specific error status for the command. */
29102 uint16_t error_code;
29103 /* The HWRM command request type. */
29105 /* The sequence ID from the original command. */
29107 /* The length of the response data in number of bytes. */
29109 uint8_t unused_0[7];
29111 * This field is used in Output records to indicate that the output
29112 * is completely written to RAM. This field should be read as '1'
29113 * to indicate that the output has been completely written.
29114 * When writing a command completion or response to an internal processor,
29115 * the order of writes has to be such that this field is written last.
29120 /***************************************
29121 * hwrm_cfa_redirect_tunnel_type_alloc *
29122 ***************************************/
29125 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
29126 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
29127 /* The HWRM command request type. */
29130 * The completion ring to send the completion event on. This should
29131 * be the NQ ID returned from the `nq_alloc` HWRM command.
29133 uint16_t cmpl_ring;
29135 * The sequence ID is used by the driver for tracking multiple
29136 * commands. This ID is treated as opaque data by the firmware and
29137 * the value is returned in the `hwrm_resp_hdr` upon completion.
29141 * The target ID of the command:
29142 * * 0x0-0xFFF8 - The function ID
29143 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29144 * * 0xFFFD - Reserved for user-space HWRM interface
29147 uint16_t target_id;
29149 * A physical address pointer pointing to a host buffer that the
29150 * command's response data will be written. This can be either a host
29151 * physical address (HPA) or a guest physical address (GPA) and must
29152 * point to a physically contiguous block of memory.
29154 uint64_t resp_addr;
29155 /* The destination function id, to whom the traffic is redirected. */
29158 uint8_t tunnel_type;
29160 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29162 /* Virtual eXtensible Local Area Network (VXLAN) */
29163 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29165 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29166 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29168 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29169 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29172 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29174 /* Generic Network Virtualization Encapsulation (Geneve) */
29175 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29177 /* Multi-Protocol Label Switching (MPLS) */
29178 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29180 /* Stateless Transport Tunnel (STT) */
29181 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
29183 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29184 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29186 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29187 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29189 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29190 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29192 /* Use fixed layer 2 ether type of 0xFFFF */
29193 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29195 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29196 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29198 /* Any tunneled traffic */
29199 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29201 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29202 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29203 /* Tunnel alloc flags. */
29205 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
29206 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
29208 uint8_t unused_0[4];
29211 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
29212 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
29213 /* The specific error status for the command. */
29214 uint16_t error_code;
29215 /* The HWRM command request type. */
29217 /* The sequence ID from the original command. */
29219 /* The length of the response data in number of bytes. */
29221 uint8_t unused_0[7];
29223 * This field is used in Output records to indicate that the output
29224 * is completely written to RAM. This field should be read as '1'
29225 * to indicate that the output has been completely written.
29226 * When writing a command completion or response to an internal processor,
29227 * the order of writes has to be such that this field is written last.
29232 /**************************************
29233 * hwrm_cfa_redirect_tunnel_type_free *
29234 **************************************/
29237 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
29238 struct hwrm_cfa_redirect_tunnel_type_free_input {
29239 /* The HWRM command request type. */
29242 * The completion ring to send the completion event on. This should
29243 * be the NQ ID returned from the `nq_alloc` HWRM command.
29245 uint16_t cmpl_ring;
29247 * The sequence ID is used by the driver for tracking multiple
29248 * commands. This ID is treated as opaque data by the firmware and
29249 * the value is returned in the `hwrm_resp_hdr` upon completion.
29253 * The target ID of the command:
29254 * * 0x0-0xFFF8 - The function ID
29255 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29256 * * 0xFFFD - Reserved for user-space HWRM interface
29259 uint16_t target_id;
29261 * A physical address pointer pointing to a host buffer that the
29262 * command's response data will be written. This can be either a host
29263 * physical address (HPA) or a guest physical address (GPA) and must
29264 * point to a physically contiguous block of memory.
29266 uint64_t resp_addr;
29267 /* The destination function id, to whom the traffic is redirected. */
29270 uint8_t tunnel_type;
29272 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
29274 /* Virtual eXtensible Local Area Network (VXLAN) */
29275 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
29277 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29278 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
29280 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29281 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
29284 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
29286 /* Generic Network Virtualization Encapsulation (Geneve) */
29287 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
29289 /* Multi-Protocol Label Switching (MPLS) */
29290 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
29292 /* Stateless Transport Tunnel (STT) */
29293 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
29295 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29296 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
29298 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29299 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29301 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29302 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29304 /* Use fixed layer 2 ether type of 0xFFFF */
29305 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
29307 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29308 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29310 /* Any tunneled traffic */
29311 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
29314 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
29315 uint8_t unused_0[5];
29318 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
29319 struct hwrm_cfa_redirect_tunnel_type_free_output {
29320 /* The specific error status for the command. */
29321 uint16_t error_code;
29322 /* The HWRM command request type. */
29324 /* The sequence ID from the original command. */
29326 /* The length of the response data in number of bytes. */
29328 uint8_t unused_0[7];
29330 * This field is used in Output records to indicate that the output
29331 * is completely written to RAM. This field should be read as '1'
29332 * to indicate that the output has been completely written.
29333 * When writing a command completion or response to an internal processor,
29334 * the order of writes has to be such that this field is written last.
29339 /**************************************
29340 * hwrm_cfa_redirect_tunnel_type_info *
29341 **************************************/
29344 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
29345 struct hwrm_cfa_redirect_tunnel_type_info_input {
29346 /* The HWRM command request type. */
29349 * The completion ring to send the completion event on. This should
29350 * be the NQ ID returned from the `nq_alloc` HWRM command.
29352 uint16_t cmpl_ring;
29354 * The sequence ID is used by the driver for tracking multiple
29355 * commands. This ID is treated as opaque data by the firmware and
29356 * the value is returned in the `hwrm_resp_hdr` upon completion.
29360 * The target ID of the command:
29361 * * 0x0-0xFFF8 - The function ID
29362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29363 * * 0xFFFD - Reserved for user-space HWRM interface
29366 uint16_t target_id;
29368 * A physical address pointer pointing to a host buffer that the
29369 * command's response data will be written. This can be either a host
29370 * physical address (HPA) or a guest physical address (GPA) and must
29371 * point to a physically contiguous block of memory.
29373 uint64_t resp_addr;
29374 /* The source function id. */
29377 uint8_t tunnel_type;
29379 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
29381 /* Virtual eXtensible Local Area Network (VXLAN) */
29382 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
29384 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29385 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
29387 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29388 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
29391 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
29393 /* Generic Network Virtualization Encapsulation (Geneve) */
29394 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
29396 /* Multi-Protocol Label Switching (MPLS) */
29397 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
29399 /* Stateless Transport Tunnel (STT) */
29400 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
29402 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29403 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
29405 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29406 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29408 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29409 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29411 /* Use fixed layer 2 ether type of 0xFFFF */
29412 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
29414 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29415 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29417 /* Any tunneled traffic */
29418 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29420 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
29421 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
29422 uint8_t unused_0[5];
29425 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
29426 struct hwrm_cfa_redirect_tunnel_type_info_output {
29427 /* The specific error status for the command. */
29428 uint16_t error_code;
29429 /* The HWRM command request type. */
29431 /* The sequence ID from the original command. */
29433 /* The length of the response data in number of bytes. */
29435 /* The destination function id, to whom the traffic is redirected. */
29437 uint8_t unused_0[5];
29439 * This field is used in Output records to indicate that the output
29440 * is completely written to RAM. This field should be read as '1'
29441 * to indicate that the output has been completely written.
29442 * When writing a command completion or response to an internal processor,
29443 * the order of writes has to be such that this field is written last.
29448 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
29449 struct hwrm_vxlan_ipv4_hdr {
29450 /* IPv4 version and header length. */
29452 /* IPv4 header length */
29453 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
29454 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
29456 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
29457 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
29458 /* IPv4 type of service. */
29460 /* IPv4 identification. */
29462 /* IPv4 flags and offset. */
29463 uint16_t flags_frag_offset;
29466 /* IPv4 protocol. */
29468 /* IPv4 source address. */
29469 uint32_t src_ip_addr;
29470 /* IPv4 destination address. */
29471 uint32_t dest_ip_addr;
29474 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
29475 struct hwrm_vxlan_ipv6_hdr {
29476 /* IPv6 version, traffic class and flow label. */
29477 uint32_t ver_tc_flow_label;
29478 /* IPv6 version shift */
29479 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
29481 /* IPv6 version mask */
29482 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
29483 UINT32_C(0xf0000000)
29484 /* IPv6 TC shift */
29485 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
29488 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
29489 UINT32_C(0xff00000)
29490 /* IPv6 flow label shift */
29491 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
29493 /* IPv6 flow label mask */
29494 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
29496 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
29497 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
29498 /* IPv6 payload length. */
29499 uint16_t payload_len;
29500 /* IPv6 next header. */
29504 /* IPv6 source address. */
29505 uint32_t src_ip_addr[4];
29506 /* IPv6 destination address. */
29507 uint32_t dest_ip_addr[4];
29510 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
29511 struct hwrm_cfa_encap_data_vxlan {
29512 /* Source MAC address. */
29513 uint8_t src_mac_addr[6];
29516 /* Destination MAC address. */
29517 uint8_t dst_mac_addr[6];
29518 /* Number of VLAN tags. */
29519 uint8_t num_vlan_tags;
29522 /* Outer VLAN TPID. */
29523 uint16_t ovlan_tpid;
29524 /* Outer VLAN TCI. */
29525 uint16_t ovlan_tci;
29526 /* Inner VLAN TPID. */
29527 uint16_t ivlan_tpid;
29528 /* Inner VLAN TCI. */
29529 uint16_t ivlan_tci;
29530 /* L3 header fields. */
29532 /* IP version mask. */
29533 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
29534 /* IP version 4. */
29535 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
29536 /* IP version 6. */
29537 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
29538 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
29539 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
29540 /* UDP source port. */
29542 /* UDP destination port. */
29544 /* VXLAN Network Identifier. */
29546 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
29547 uint8_t hdr_rsvd0[3];
29548 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
29550 /* VXLAN header flags field. */
29555 /*******************************
29556 * hwrm_cfa_encap_record_alloc *
29557 *******************************/
29560 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
29561 struct hwrm_cfa_encap_record_alloc_input {
29562 /* The HWRM command request type. */
29565 * The completion ring to send the completion event on. This should
29566 * be the NQ ID returned from the `nq_alloc` HWRM command.
29568 uint16_t cmpl_ring;
29570 * The sequence ID is used by the driver for tracking multiple
29571 * commands. This ID is treated as opaque data by the firmware and
29572 * the value is returned in the `hwrm_resp_hdr` upon completion.
29576 * The target ID of the command:
29577 * * 0x0-0xFFF8 - The function ID
29578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29579 * * 0xFFFD - Reserved for user-space HWRM interface
29582 uint16_t target_id;
29584 * A physical address pointer pointing to a host buffer that the
29585 * command's response data will be written. This can be either a host
29586 * physical address (HPA) or a guest physical address (GPA) and must
29587 * point to a physically contiguous block of memory.
29589 uint64_t resp_addr;
29591 /* Setting of this flag indicates the applicability to the loopback path. */
29592 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
29595 * Setting of this flag indicates this encap record is external encap record.
29596 * Resetting of this flag indicates this flag is internal encap record and
29597 * this is the default setting.
29599 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
29601 /* Encapsulation Type. */
29602 uint8_t encap_type;
29603 /* Virtual eXtensible Local Area Network (VXLAN) */
29604 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
29606 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29607 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
29609 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
29610 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
29613 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
29615 /* Generic Network Virtualization Encapsulation (Geneve) */
29616 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
29618 /* Multi-Protocol Label Switching (MPLS) */
29619 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
29622 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
29624 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29625 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
29627 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29628 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
29630 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29631 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
29633 /* Use fixed layer 2 ether type of 0xFFFF */
29634 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
29636 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29637 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
29639 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
29640 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
29641 uint8_t unused_0[3];
29642 /* This value is encap data used for the given encap type. */
29643 uint32_t encap_data[20];
29646 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
29647 struct hwrm_cfa_encap_record_alloc_output {
29648 /* The specific error status for the command. */
29649 uint16_t error_code;
29650 /* The HWRM command request type. */
29652 /* The sequence ID from the original command. */
29654 /* The length of the response data in number of bytes. */
29656 /* This value is an opaque id into CFA data structures. */
29657 uint32_t encap_record_id;
29658 uint8_t unused_0[3];
29660 * This field is used in Output records to indicate that the output
29661 * is completely written to RAM. This field should be read as '1'
29662 * to indicate that the output has been completely written.
29663 * When writing a command completion or response to an internal processor,
29664 * the order of writes has to be such that this field is written last.
29669 /******************************
29670 * hwrm_cfa_encap_record_free *
29671 ******************************/
29674 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
29675 struct hwrm_cfa_encap_record_free_input {
29676 /* The HWRM command request type. */
29679 * The completion ring to send the completion event on. This should
29680 * be the NQ ID returned from the `nq_alloc` HWRM command.
29682 uint16_t cmpl_ring;
29684 * The sequence ID is used by the driver for tracking multiple
29685 * commands. This ID is treated as opaque data by the firmware and
29686 * the value is returned in the `hwrm_resp_hdr` upon completion.
29690 * The target ID of the command:
29691 * * 0x0-0xFFF8 - The function ID
29692 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29693 * * 0xFFFD - Reserved for user-space HWRM interface
29696 uint16_t target_id;
29698 * A physical address pointer pointing to a host buffer that the
29699 * command's response data will be written. This can be either a host
29700 * physical address (HPA) or a guest physical address (GPA) and must
29701 * point to a physically contiguous block of memory.
29703 uint64_t resp_addr;
29704 /* This value is an opaque id into CFA data structures. */
29705 uint32_t encap_record_id;
29706 uint8_t unused_0[4];
29709 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
29710 struct hwrm_cfa_encap_record_free_output {
29711 /* The specific error status for the command. */
29712 uint16_t error_code;
29713 /* The HWRM command request type. */
29715 /* The sequence ID from the original command. */
29717 /* The length of the response data in number of bytes. */
29719 uint8_t unused_0[7];
29721 * This field is used in Output records to indicate that the output
29722 * is completely written to RAM. This field should be read as '1'
29723 * to indicate that the output has been completely written.
29724 * When writing a command completion or response to an internal processor,
29725 * the order of writes has to be such that this field is written last.
29730 /********************************
29731 * hwrm_cfa_ntuple_filter_alloc *
29732 ********************************/
29735 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
29736 struct hwrm_cfa_ntuple_filter_alloc_input {
29737 /* The HWRM command request type. */
29740 * The completion ring to send the completion event on. This should
29741 * be the NQ ID returned from the `nq_alloc` HWRM command.
29743 uint16_t cmpl_ring;
29745 * The sequence ID is used by the driver for tracking multiple
29746 * commands. This ID is treated as opaque data by the firmware and
29747 * the value is returned in the `hwrm_resp_hdr` upon completion.
29751 * The target ID of the command:
29752 * * 0x0-0xFFF8 - The function ID
29753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29754 * * 0xFFFD - Reserved for user-space HWRM interface
29757 uint16_t target_id;
29759 * A physical address pointer pointing to a host buffer that the
29760 * command's response data will be written. This can be either a host
29761 * physical address (HPA) or a guest physical address (GPA) and must
29762 * point to a physically contiguous block of memory.
29764 uint64_t resp_addr;
29766 /* Setting of this flag indicates the applicability to the loopback path. */
29767 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
29770 * Setting of this flag indicates drop action. If this flag is not set,
29771 * then it should be considered accept action.
29773 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
29776 * Setting of this flag indicates that a meter is expected to be attached
29777 * to this flow. This hint can be used when choosing the action record
29778 * format required for the flow.
29780 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
29783 * Setting of this flag indicates that the dst_id field contains function ID.
29784 * If this is not set it indicates dest_id is VNIC or VPORT.
29786 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
29789 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
29790 * If this is not set it indicates no specific arp opcode matching.
29792 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
29795 * Setting of this flag indicates that the dst_id field contains RFS ring
29796 * table index. If this is not set it indicates dst_id is VNIC or VPORT
29797 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
29800 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
29804 * This bit must be '1' for the l2_filter_id field to be
29807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
29810 * This bit must be '1' for the ethertype field to be
29813 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
29816 * This bit must be '1' for the tunnel_type field to be
29819 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
29822 * This bit must be '1' for the src_macaddr field to be
29825 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
29828 * This bit must be '1' for the ipaddr_type field to be
29831 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
29834 * This bit must be '1' for the src_ipaddr field to be
29837 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
29840 * This bit must be '1' for the src_ipaddr_mask field to be
29843 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
29846 * This bit must be '1' for the dst_ipaddr field to be
29849 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
29852 * This bit must be '1' for the dst_ipaddr_mask field to be
29855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
29858 * This bit must be '1' for the ip_protocol field to be
29861 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
29864 * This bit must be '1' for the src_port field to be
29867 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
29870 * This bit must be '1' for the src_port_mask field to be
29873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
29876 * This bit must be '1' for the dst_port field to be
29879 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
29882 * This bit must be '1' for the dst_port_mask field to be
29885 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
29888 * This bit must be '1' for the pri_hint field to be
29891 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
29894 * This bit must be '1' for the ntuple_filter_id field to be
29897 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
29900 * This bit must be '1' for the dst_id field to be
29903 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
29906 * This bit must be '1' for the mirror_vnic_id field to be
29909 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
29912 * This bit must be '1' for the dst_macaddr field to be
29915 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
29917 /* This flag is deprecated. */
29918 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
29921 * This value identifies a set of CFA data structures used for an L2
29924 uint64_t l2_filter_id;
29926 * This value indicates the source MAC address in
29927 * the Ethernet header.
29929 uint8_t src_macaddr[6];
29930 /* This value indicates the ethertype in the Ethernet header. */
29931 uint16_t ethertype;
29933 * This value indicates the type of IP address.
29936 * All others are invalid.
29938 uint8_t ip_addr_type;
29940 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
29943 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
29946 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
29948 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
29949 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
29951 * The value of protocol filed in IP header.
29952 * Applies to UDP and TCP traffic.
29956 uint8_t ip_protocol;
29958 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
29961 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
29964 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
29966 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
29967 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
29969 * If set, this value shall represent the
29970 * Logical VNIC ID of the destination VNIC for the RX
29971 * path and network port id of the destination port for
29976 * Logical VNIC ID of the VNIC where traffic is
29979 uint16_t mirror_vnic_id;
29981 * This value indicates the tunnel type for this filter.
29982 * If this field is not specified, then the filter shall
29983 * apply to both non-tunneled and tunneled packets.
29984 * If this field conflicts with the tunnel_type specified
29985 * in the l2_filter_id, then the HWRM shall return an
29986 * error for this command.
29988 uint8_t tunnel_type;
29990 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29992 /* Virtual eXtensible Local Area Network (VXLAN) */
29993 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29995 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29996 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29998 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29999 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30002 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30004 /* Generic Network Virtualization Encapsulation (Geneve) */
30005 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30007 /* Multi-Protocol Label Switching (MPLS) */
30008 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30010 /* Stateless Transport Tunnel (STT) */
30011 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
30013 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30014 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30016 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30017 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30019 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30020 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30022 /* Use fixed layer 2 ether type of 0xFFFF */
30023 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30025 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30026 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30028 /* Any tunneled traffic */
30029 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30031 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30032 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30034 * This hint is provided to help in placing
30035 * the filter in the filter table.
30038 /* No preference */
30039 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
30041 /* Above the given filter */
30042 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
30044 /* Below the given filter */
30045 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
30047 /* As high as possible */
30048 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
30050 /* As low as possible */
30051 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
30053 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
30054 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
30056 * The value of source IP address to be used in filtering.
30057 * For IPv4, first four bytes represent the IP address.
30059 uint32_t src_ipaddr[4];
30061 * The value of source IP address mask to be used in
30063 * For IPv4, first four bytes represent the IP address mask.
30065 uint32_t src_ipaddr_mask[4];
30067 * The value of destination IP address to be used in filtering.
30068 * For IPv4, first four bytes represent the IP address.
30070 uint32_t dst_ipaddr[4];
30072 * The value of destination IP address mask to be used in
30074 * For IPv4, first four bytes represent the IP address mask.
30076 uint32_t dst_ipaddr_mask[4];
30078 * The value of source port to be used in filtering.
30079 * Applies to UDP and TCP traffic.
30083 * The value of source port mask to be used in filtering.
30084 * Applies to UDP and TCP traffic.
30086 uint16_t src_port_mask;
30088 * The value of destination port to be used in filtering.
30089 * Applies to UDP and TCP traffic.
30093 * The value of destination port mask to be used in
30095 * Applies to UDP and TCP traffic.
30097 uint16_t dst_port_mask;
30099 * This is the ID of the filter that goes along with
30102 uint64_t ntuple_filter_id_hint;
30105 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
30106 struct hwrm_cfa_ntuple_filter_alloc_output {
30107 /* The specific error status for the command. */
30108 uint16_t error_code;
30109 /* The HWRM command request type. */
30111 /* The sequence ID from the original command. */
30113 /* The length of the response data in number of bytes. */
30115 /* This value is an opaque id into CFA data structures. */
30116 uint64_t ntuple_filter_id;
30118 * The flow id value in bit 0-29 is the actual ID of the flow
30119 * associated with this filter and it shall be used to match
30120 * and associate the flow identifier returned in completion
30121 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30122 * shall indicate no valid flow id.
30125 /* Indicate the flow id value. */
30126 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30127 UINT32_C(0x3fffffff)
30128 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30129 /* Indicate type of the flow. */
30130 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
30131 UINT32_C(0x40000000)
30133 * If this bit set to 0, then it indicates that the flow is
30136 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30137 (UINT32_C(0x0) << 30)
30139 * If this bit is set to 1, then it indicates that the flow is
30142 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30143 (UINT32_C(0x1) << 30)
30144 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30145 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30146 /* Indicate the flow direction. */
30147 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
30148 UINT32_C(0x80000000)
30149 /* If this bit set to 0, then it indicates rx flow. */
30150 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30151 (UINT32_C(0x0) << 31)
30152 /* If this bit is set to 1, then it indicates that tx flow. */
30153 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30154 (UINT32_C(0x1) << 31)
30155 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30156 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30157 uint8_t unused_0[3];
30159 * This field is used in Output records to indicate that the output
30160 * is completely written to RAM. This field should be read as '1'
30161 * to indicate that the output has been completely written.
30162 * When writing a command completion or response to an internal processor,
30163 * the order of writes has to be such that this field is written last.
30168 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
30169 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
30171 * command specific error codes that goes to
30172 * the cmd_err field in Common HWRM Error Response.
30175 /* Unknown error */
30176 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
30178 /* Unable to complete operation due to conflict with Rx Mask VLAN */
30179 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
30181 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
30182 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
30183 uint8_t unused_0[7];
30186 /*******************************
30187 * hwrm_cfa_ntuple_filter_free *
30188 *******************************/
30191 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
30192 struct hwrm_cfa_ntuple_filter_free_input {
30193 /* The HWRM command request type. */
30196 * The completion ring to send the completion event on. This should
30197 * be the NQ ID returned from the `nq_alloc` HWRM command.
30199 uint16_t cmpl_ring;
30201 * The sequence ID is used by the driver for tracking multiple
30202 * commands. This ID is treated as opaque data by the firmware and
30203 * the value is returned in the `hwrm_resp_hdr` upon completion.
30207 * The target ID of the command:
30208 * * 0x0-0xFFF8 - The function ID
30209 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30210 * * 0xFFFD - Reserved for user-space HWRM interface
30213 uint16_t target_id;
30215 * A physical address pointer pointing to a host buffer that the
30216 * command's response data will be written. This can be either a host
30217 * physical address (HPA) or a guest physical address (GPA) and must
30218 * point to a physically contiguous block of memory.
30220 uint64_t resp_addr;
30221 /* This value is an opaque id into CFA data structures. */
30222 uint64_t ntuple_filter_id;
30225 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
30226 struct hwrm_cfa_ntuple_filter_free_output {
30227 /* The specific error status for the command. */
30228 uint16_t error_code;
30229 /* The HWRM command request type. */
30231 /* The sequence ID from the original command. */
30233 /* The length of the response data in number of bytes. */
30235 uint8_t unused_0[7];
30237 * This field is used in Output records to indicate that the output
30238 * is completely written to RAM. This field should be read as '1'
30239 * to indicate that the output has been completely written.
30240 * When writing a command completion or response to an internal processor,
30241 * the order of writes has to be such that this field is written last.
30246 /******************************
30247 * hwrm_cfa_ntuple_filter_cfg *
30248 ******************************/
30251 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
30252 struct hwrm_cfa_ntuple_filter_cfg_input {
30253 /* The HWRM command request type. */
30256 * The completion ring to send the completion event on. This should
30257 * be the NQ ID returned from the `nq_alloc` HWRM command.
30259 uint16_t cmpl_ring;
30261 * The sequence ID is used by the driver for tracking multiple
30262 * commands. This ID is treated as opaque data by the firmware and
30263 * the value is returned in the `hwrm_resp_hdr` upon completion.
30267 * The target ID of the command:
30268 * * 0x0-0xFFF8 - The function ID
30269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30270 * * 0xFFFD - Reserved for user-space HWRM interface
30273 uint16_t target_id;
30275 * A physical address pointer pointing to a host buffer that the
30276 * command's response data will be written. This can be either a host
30277 * physical address (HPA) or a guest physical address (GPA) and must
30278 * point to a physically contiguous block of memory.
30280 uint64_t resp_addr;
30283 * This bit must be '1' for the new_dst_id field to be
30286 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
30289 * This bit must be '1' for the new_mirror_vnic_id field to be
30292 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
30295 * This bit must be '1' for the new_meter_instance_id field to be
30298 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
30302 * Setting this bit to 1 indicates that dest_id field contains FID.
30303 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
30305 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
30308 * Setting of this flag indicates that the new_dst_id field contains
30309 * RFS ring table index. If this is not set it indicates new_dst_id is
30310 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
30311 * can’t be set at the same time.
30313 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
30315 /* This value is an opaque id into CFA data structures. */
30316 uint64_t ntuple_filter_id;
30318 * If set, this value shall represent the new
30319 * Logical VNIC ID of the destination VNIC for the RX
30320 * path and new network port id of the destination port for
30323 uint32_t new_dst_id;
30325 * New Logical VNIC ID of the VNIC where traffic is
30328 uint32_t new_mirror_vnic_id;
30330 * New meter to attach to the flow. Specifying the
30331 * invalid instance ID is used to remove any existing
30332 * meter from the flow.
30334 uint16_t new_meter_instance_id;
30336 * A value of 0xfff is considered invalid and implies the
30337 * instance is not configured.
30339 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
30341 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
30342 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
30343 uint8_t unused_1[6];
30346 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
30347 struct hwrm_cfa_ntuple_filter_cfg_output {
30348 /* The specific error status for the command. */
30349 uint16_t error_code;
30350 /* The HWRM command request type. */
30352 /* The sequence ID from the original command. */
30354 /* The length of the response data in number of bytes. */
30356 uint8_t unused_0[7];
30358 * This field is used in Output records to indicate that the output
30359 * is completely written to RAM. This field should be read as '1'
30360 * to indicate that the output has been completely written.
30361 * When writing a command completion or response to an internal processor,
30362 * the order of writes has to be such that this field is written last.
30367 /**************************
30368 * hwrm_cfa_em_flow_alloc *
30369 **************************/
30372 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
30373 struct hwrm_cfa_em_flow_alloc_input {
30374 /* The HWRM command request type. */
30377 * The completion ring to send the completion event on. This should
30378 * be the NQ ID returned from the `nq_alloc` HWRM command.
30380 uint16_t cmpl_ring;
30382 * The sequence ID is used by the driver for tracking multiple
30383 * commands. This ID is treated as opaque data by the firmware and
30384 * the value is returned in the `hwrm_resp_hdr` upon completion.
30388 * The target ID of the command:
30389 * * 0x0-0xFFF8 - The function ID
30390 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30391 * * 0xFFFD - Reserved for user-space HWRM interface
30394 uint16_t target_id;
30396 * A physical address pointer pointing to a host buffer that the
30397 * command's response data will be written. This can be either a host
30398 * physical address (HPA) or a guest physical address (GPA) and must
30399 * point to a physically contiguous block of memory.
30401 uint64_t resp_addr;
30404 * Enumeration denoting the RX, TX type of the resource.
30405 * This enumeration is used for resources that are similar for both
30406 * TX and RX paths of the chip.
30408 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
30410 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30412 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30413 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
30414 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
30416 * Setting of this flag indicates enabling of a byte counter for a given
30419 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
30421 * Setting of this flag indicates enabling of a packet counter for a given
30424 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
30425 /* Setting of this flag indicates de-capsulation action for the given flow. */
30426 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
30427 /* Setting of this flag indicates encapsulation action for the given flow. */
30428 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
30430 * Setting of this flag indicates drop action. If this flag is not set,
30431 * then it should be considered accept action.
30433 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
30435 * Setting of this flag indicates that a meter is expected to be attached
30436 * to this flow. This hint can be used when choosing the action record
30437 * format required for the flow.
30439 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
30442 * This bit must be '1' for the l2_filter_id field to be
30445 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
30448 * This bit must be '1' for the tunnel_type field to be
30451 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
30454 * This bit must be '1' for the tunnel_id field to be
30457 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
30460 * This bit must be '1' for the src_macaddr field to be
30463 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
30466 * This bit must be '1' for the dst_macaddr field to be
30469 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
30472 * This bit must be '1' for the ovlan_vid field to be
30475 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
30478 * This bit must be '1' for the ivlan_vid field to be
30481 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
30484 * This bit must be '1' for the ethertype field to be
30487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
30490 * This bit must be '1' for the src_ipaddr field to be
30493 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
30496 * This bit must be '1' for the dst_ipaddr field to be
30499 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
30502 * This bit must be '1' for the ipaddr_type field to be
30505 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
30508 * This bit must be '1' for the ip_protocol field to be
30511 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
30514 * This bit must be '1' for the src_port field to be
30517 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
30520 * This bit must be '1' for the dst_port field to be
30523 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
30526 * This bit must be '1' for the dst_id field to be
30529 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
30532 * This bit must be '1' for the mirror_vnic_id field to be
30535 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
30538 * This bit must be '1' for the encap_record_id field to be
30541 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
30544 * This bit must be '1' for the meter_instance_id field to be
30547 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
30550 * This value identifies a set of CFA data structures used for an L2
30553 uint64_t l2_filter_id;
30555 uint8_t tunnel_type;
30557 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30559 /* Virtual eXtensible Local Area Network (VXLAN) */
30560 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30562 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30563 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30565 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30566 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30569 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30571 /* Generic Network Virtualization Encapsulation (Geneve) */
30572 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30574 /* Multi-Protocol Label Switching (MPLS) */
30575 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30577 /* Stateless Transport Tunnel (STT) */
30578 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
30580 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30581 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30583 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30584 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30586 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30587 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30589 /* Use fixed layer 2 ether type of 0xFFFF */
30590 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30592 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30593 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30595 /* Any tunneled traffic */
30596 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30598 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30599 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30600 uint8_t unused_0[3];
30602 * Tunnel identifier.
30603 * Virtual Network Identifier (VNI). Only valid with
30604 * tunnel_types VXLAN, NVGRE, and Geneve.
30605 * Only lower 24-bits of VNI field are used
30606 * in setting up the filter.
30608 uint32_t tunnel_id;
30610 * This value indicates the source MAC address in
30611 * the Ethernet header.
30613 uint8_t src_macaddr[6];
30614 /* The meter instance to attach to the flow. */
30615 uint16_t meter_instance_id;
30617 * A value of 0xfff is considered invalid and implies the
30618 * instance is not configured.
30620 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
30622 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
30623 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
30625 * This value indicates the destination MAC address in
30626 * the Ethernet header.
30628 uint8_t dst_macaddr[6];
30630 * This value indicates the VLAN ID of the outer VLAN tag
30631 * in the Ethernet header.
30633 uint16_t ovlan_vid;
30635 * This value indicates the VLAN ID of the inner VLAN tag
30636 * in the Ethernet header.
30638 uint16_t ivlan_vid;
30639 /* This value indicates the ethertype in the Ethernet header. */
30640 uint16_t ethertype;
30642 * This value indicates the type of IP address.
30645 * All others are invalid.
30647 uint8_t ip_addr_type;
30649 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
30651 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
30653 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
30654 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
30655 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
30657 * The value of protocol filed in IP header.
30658 * Applies to UDP and TCP traffic.
30662 uint8_t ip_protocol;
30664 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
30666 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
30668 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
30669 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
30670 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
30671 uint8_t unused_1[2];
30673 * The value of source IP address to be used in filtering.
30674 * For IPv4, first four bytes represent the IP address.
30676 uint32_t src_ipaddr[4];
30678 * big_endian = True
30679 * The value of destination IP address to be used in filtering.
30680 * For IPv4, first four bytes represent the IP address.
30682 uint32_t dst_ipaddr[4];
30684 * The value of source port to be used in filtering.
30685 * Applies to UDP and TCP traffic.
30689 * The value of destination port to be used in filtering.
30690 * Applies to UDP and TCP traffic.
30694 * If set, this value shall represent the
30695 * Logical VNIC ID of the destination VNIC for the RX
30696 * path and network port id of the destination port for
30701 * Logical VNIC ID of the VNIC where traffic is
30704 uint16_t mirror_vnic_id;
30705 /* Logical ID of the encapsulation record. */
30706 uint32_t encap_record_id;
30707 uint8_t unused_2[4];
30710 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
30711 struct hwrm_cfa_em_flow_alloc_output {
30712 /* The specific error status for the command. */
30713 uint16_t error_code;
30714 /* The HWRM command request type. */
30716 /* The sequence ID from the original command. */
30718 /* The length of the response data in number of bytes. */
30720 /* This value is an opaque id into CFA data structures. */
30721 uint64_t em_filter_id;
30723 * The flow id value in bit 0-29 is the actual ID of the flow
30724 * associated with this filter and it shall be used to match
30725 * and associate the flow identifier returned in completion
30726 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30727 * shall indicate no valid flow id.
30730 /* Indicate the flow id value. */
30731 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30732 UINT32_C(0x3fffffff)
30733 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30734 /* Indicate type of the flow. */
30735 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
30736 UINT32_C(0x40000000)
30738 * If this bit set to 0, then it indicates that the flow is
30741 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30742 (UINT32_C(0x0) << 30)
30744 * If this bit is set to 1, then it indicates that the flow is
30747 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30748 (UINT32_C(0x1) << 30)
30749 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30750 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30751 /* Indicate the flow direction. */
30752 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
30753 UINT32_C(0x80000000)
30754 /* If this bit set to 0, then it indicates rx flow. */
30755 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30756 (UINT32_C(0x0) << 31)
30757 /* If this bit is set to 1, then it indicates that tx flow. */
30758 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30759 (UINT32_C(0x1) << 31)
30760 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30761 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30762 uint8_t unused_0[3];
30764 * This field is used in Output records to indicate that the output
30765 * is completely written to RAM. This field should be read as '1'
30766 * to indicate that the output has been completely written.
30767 * When writing a command completion or response to an internal processor,
30768 * the order of writes has to be such that this field is written last.
30773 /*************************
30774 * hwrm_cfa_em_flow_free *
30775 *************************/
30778 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
30779 struct hwrm_cfa_em_flow_free_input {
30780 /* The HWRM command request type. */
30783 * The completion ring to send the completion event on. This should
30784 * be the NQ ID returned from the `nq_alloc` HWRM command.
30786 uint16_t cmpl_ring;
30788 * The sequence ID is used by the driver for tracking multiple
30789 * commands. This ID is treated as opaque data by the firmware and
30790 * the value is returned in the `hwrm_resp_hdr` upon completion.
30794 * The target ID of the command:
30795 * * 0x0-0xFFF8 - The function ID
30796 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30797 * * 0xFFFD - Reserved for user-space HWRM interface
30800 uint16_t target_id;
30802 * A physical address pointer pointing to a host buffer that the
30803 * command's response data will be written. This can be either a host
30804 * physical address (HPA) or a guest physical address (GPA) and must
30805 * point to a physically contiguous block of memory.
30807 uint64_t resp_addr;
30808 /* This value is an opaque id into CFA data structures. */
30809 uint64_t em_filter_id;
30812 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
30813 struct hwrm_cfa_em_flow_free_output {
30814 /* The specific error status for the command. */
30815 uint16_t error_code;
30816 /* The HWRM command request type. */
30818 /* The sequence ID from the original command. */
30820 /* The length of the response data in number of bytes. */
30822 uint8_t unused_0[7];
30824 * This field is used in Output records to indicate that the output
30825 * is completely written to RAM. This field should be read as '1'
30826 * to indicate that the output has been completely written.
30827 * When writing a command completion or response to an internal processor,
30828 * the order of writes has to be such that this field is written last.
30833 /************************
30834 * hwrm_cfa_meter_qcaps *
30835 ************************/
30838 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
30839 struct hwrm_cfa_meter_qcaps_input {
30840 /* The HWRM command request type. */
30843 * The completion ring to send the completion event on. This should
30844 * be the NQ ID returned from the `nq_alloc` HWRM command.
30846 uint16_t cmpl_ring;
30848 * The sequence ID is used by the driver for tracking multiple
30849 * commands. This ID is treated as opaque data by the firmware and
30850 * the value is returned in the `hwrm_resp_hdr` upon completion.
30854 * The target ID of the command:
30855 * * 0x0-0xFFF8 - The function ID
30856 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30857 * * 0xFFFD - Reserved for user-space HWRM interface
30860 uint16_t target_id;
30862 * A physical address pointer pointing to a host buffer that the
30863 * command's response data will be written. This can be either a host
30864 * physical address (HPA) or a guest physical address (GPA) and must
30865 * point to a physically contiguous block of memory.
30867 uint64_t resp_addr;
30870 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
30871 struct hwrm_cfa_meter_qcaps_output {
30872 /* The specific error status for the command. */
30873 uint16_t error_code;
30874 /* The HWRM command request type. */
30876 /* The sequence ID from the original command. */
30878 /* The length of the response data in number of bytes. */
30882 * Enumeration denoting the clock at which the Meter is running with.
30883 * This enumeration is used for resources that are similar for both
30884 * TX and RX paths of the chip.
30886 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
30887 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
30889 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
30891 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
30892 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
30893 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
30894 uint8_t unused_0[4];
30896 * The minimum guaranteed number of tx meter profiles supported
30897 * for this function.
30899 uint16_t min_tx_profile;
30901 * The maximum non-guaranteed number of tx meter profiles supported
30902 * for this function.
30904 uint16_t max_tx_profile;
30906 * The minimum guaranteed number of rx meter profiles supported
30907 * for this function.
30909 uint16_t min_rx_profile;
30911 * The maximum non-guaranteed number of rx meter profiles supported
30912 * for this function.
30914 uint16_t max_rx_profile;
30916 * The minimum guaranteed number of tx meter instances supported
30917 * for this function.
30919 uint16_t min_tx_instance;
30921 * The maximum non-guaranteed number of tx meter instances supported
30922 * for this function.
30924 uint16_t max_tx_instance;
30926 * The minimum guaranteed number of rx meter instances supported
30927 * for this function.
30929 uint16_t min_rx_instance;
30931 * The maximum non-guaranteed number of rx meter instances supported
30932 * for this function.
30934 uint16_t max_rx_instance;
30935 uint8_t unused_1[7];
30937 * This field is used in Output records to indicate that the output
30938 * is completely written to RAM. This field should be read as '1'
30939 * to indicate that the output has been completely written.
30940 * When writing a command completion or response to an internal processor,
30941 * the order of writes has to be such that this field is written last.
30946 /********************************
30947 * hwrm_cfa_meter_profile_alloc *
30948 ********************************/
30951 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
30952 struct hwrm_cfa_meter_profile_alloc_input {
30953 /* The HWRM command request type. */
30956 * The completion ring to send the completion event on. This should
30957 * be the NQ ID returned from the `nq_alloc` HWRM command.
30959 uint16_t cmpl_ring;
30961 * The sequence ID is used by the driver for tracking multiple
30962 * commands. This ID is treated as opaque data by the firmware and
30963 * the value is returned in the `hwrm_resp_hdr` upon completion.
30967 * The target ID of the command:
30968 * * 0x0-0xFFF8 - The function ID
30969 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30970 * * 0xFFFD - Reserved for user-space HWRM interface
30973 uint16_t target_id;
30975 * A physical address pointer pointing to a host buffer that the
30976 * command's response data will be written. This can be either a host
30977 * physical address (HPA) or a guest physical address (GPA) and must
30978 * point to a physically contiguous block of memory.
30980 uint64_t resp_addr;
30983 * Enumeration denoting the RX, TX type of the resource.
30984 * This enumeration is used for resources that are similar for both
30985 * TX and RX paths of the chip.
30987 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
30989 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
30992 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
30994 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
30995 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
30996 /* The meter algorithm type. */
30997 uint8_t meter_type;
30998 /* RFC 2697 (srTCM) */
30999 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
31001 /* RFC 2698 (trTCM) */
31002 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
31004 /* RFC 4115 (trTCM) */
31005 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
31007 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
31008 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
31010 * This field is reserved for the future use.
31011 * It shall be set to 0.
31013 uint16_t reserved1;
31015 * This field is reserved for the future use.
31016 * It shall be set to 0.
31018 uint32_t reserved2;
31019 /* A meter rate specified in bytes-per-second. */
31020 uint32_t commit_rate;
31021 /* The bandwidth value. */
31022 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
31023 UINT32_C(0xfffffff)
31024 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
31026 /* The granularity of the value (bits or bytes). */
31027 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
31028 UINT32_C(0x10000000)
31029 /* Value is in bits. */
31030 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
31031 (UINT32_C(0x0) << 28)
31032 /* Value is in bytes. */
31033 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
31034 (UINT32_C(0x1) << 28)
31035 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
31036 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
31037 /* bw_value_unit is 3 b */
31038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
31039 UINT32_C(0xe0000000)
31040 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
31042 /* Value is in Mb or MB (base 10). */
31043 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
31044 (UINT32_C(0x0) << 29)
31045 /* Value is in Kb or KB (base 10). */
31046 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
31047 (UINT32_C(0x2) << 29)
31048 /* Value is in bits or bytes. */
31049 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
31050 (UINT32_C(0x4) << 29)
31051 /* Value is in Gb or GB (base 10). */
31052 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
31053 (UINT32_C(0x6) << 29)
31054 /* Value is in 1/100th of a percentage of total bandwidth. */
31055 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
31056 (UINT32_C(0x1) << 29)
31058 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
31059 (UINT32_C(0x7) << 29)
31060 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
31061 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
31062 /* A meter burst size specified in bytes. */
31063 uint32_t commit_burst;
31064 /* The bandwidth value. */
31065 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
31066 UINT32_C(0xfffffff)
31067 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
31069 /* The granularity of the value (bits or bytes). */
31070 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
31071 UINT32_C(0x10000000)
31072 /* Value is in bits. */
31073 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
31074 (UINT32_C(0x0) << 28)
31075 /* Value is in bytes. */
31076 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
31077 (UINT32_C(0x1) << 28)
31078 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
31079 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
31080 /* bw_value_unit is 3 b */
31081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
31082 UINT32_C(0xe0000000)
31083 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
31085 /* Value is in Mb or MB (base 10). */
31086 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
31087 (UINT32_C(0x0) << 29)
31088 /* Value is in Kb or KB (base 10). */
31089 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
31090 (UINT32_C(0x2) << 29)
31091 /* Value is in bits or bytes. */
31092 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
31093 (UINT32_C(0x4) << 29)
31094 /* Value is in Gb or GB (base 10). */
31095 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
31096 (UINT32_C(0x6) << 29)
31097 /* Value is in 1/100th of a percentage of total bandwidth. */
31098 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
31099 (UINT32_C(0x1) << 29)
31100 /* Invalid value */
31101 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
31102 (UINT32_C(0x7) << 29)
31103 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
31104 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
31105 /* A meter rate specified in bytes-per-second. */
31106 uint32_t excess_peak_rate;
31107 /* The bandwidth value. */
31108 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
31109 UINT32_C(0xfffffff)
31110 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
31112 /* The granularity of the value (bits or bytes). */
31113 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
31114 UINT32_C(0x10000000)
31115 /* Value is in bits. */
31116 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
31117 (UINT32_C(0x0) << 28)
31118 /* Value is in bytes. */
31119 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
31120 (UINT32_C(0x1) << 28)
31121 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
31122 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
31123 /* bw_value_unit is 3 b */
31124 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
31125 UINT32_C(0xe0000000)
31126 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
31128 /* Value is in Mb or MB (base 10). */
31129 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
31130 (UINT32_C(0x0) << 29)
31131 /* Value is in Kb or KB (base 10). */
31132 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
31133 (UINT32_C(0x2) << 29)
31134 /* Value is in bits or bytes. */
31135 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
31136 (UINT32_C(0x4) << 29)
31137 /* Value is in Gb or GB (base 10). */
31138 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
31139 (UINT32_C(0x6) << 29)
31140 /* Value is in 1/100th of a percentage of total bandwidth. */
31141 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
31142 (UINT32_C(0x1) << 29)
31144 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
31145 (UINT32_C(0x7) << 29)
31146 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
31147 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
31148 /* A meter burst size specified in bytes. */
31149 uint32_t excess_peak_burst;
31150 /* The bandwidth value. */
31151 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
31152 UINT32_C(0xfffffff)
31153 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
31155 /* The granularity of the value (bits or bytes). */
31156 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
31157 UINT32_C(0x10000000)
31158 /* Value is in bits. */
31159 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
31160 (UINT32_C(0x0) << 28)
31161 /* Value is in bytes. */
31162 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
31163 (UINT32_C(0x1) << 28)
31164 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
31165 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
31166 /* bw_value_unit is 3 b */
31167 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
31168 UINT32_C(0xe0000000)
31169 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
31171 /* Value is in Mb or MB (base 10). */
31172 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
31173 (UINT32_C(0x0) << 29)
31174 /* Value is in Kb or KB (base 10). */
31175 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
31176 (UINT32_C(0x2) << 29)
31177 /* Value is in bits or bytes. */
31178 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
31179 (UINT32_C(0x4) << 29)
31180 /* Value is in Gb or GB (base 10). */
31181 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
31182 (UINT32_C(0x6) << 29)
31183 /* Value is in 1/100th of a percentage of total bandwidth. */
31184 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
31185 (UINT32_C(0x1) << 29)
31187 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
31188 (UINT32_C(0x7) << 29)
31189 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
31190 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
31193 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
31194 struct hwrm_cfa_meter_profile_alloc_output {
31195 /* The specific error status for the command. */
31196 uint16_t error_code;
31197 /* The HWRM command request type. */
31199 /* The sequence ID from the original command. */
31201 /* The length of the response data in number of bytes. */
31203 /* This value identifies a meter profile in CFA. */
31204 uint16_t meter_profile_id;
31206 * A value of 0xfff is considered invalid and implies the
31207 * profile is not configured.
31209 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
31211 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
31212 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
31213 uint8_t unused_0[5];
31215 * This field is used in Output records to indicate that the output
31216 * is completely written to RAM. This field should be read as '1'
31217 * to indicate that the output has been completely written.
31218 * When writing a command completion or response to an internal processor,
31219 * the order of writes has to be such that this field is written last.
31224 /*******************************
31225 * hwrm_cfa_meter_profile_free *
31226 *******************************/
31229 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
31230 struct hwrm_cfa_meter_profile_free_input {
31231 /* The HWRM command request type. */
31234 * The completion ring to send the completion event on. This should
31235 * be the NQ ID returned from the `nq_alloc` HWRM command.
31237 uint16_t cmpl_ring;
31239 * The sequence ID is used by the driver for tracking multiple
31240 * commands. This ID is treated as opaque data by the firmware and
31241 * the value is returned in the `hwrm_resp_hdr` upon completion.
31245 * The target ID of the command:
31246 * * 0x0-0xFFF8 - The function ID
31247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31248 * * 0xFFFD - Reserved for user-space HWRM interface
31251 uint16_t target_id;
31253 * A physical address pointer pointing to a host buffer that the
31254 * command's response data will be written. This can be either a host
31255 * physical address (HPA) or a guest physical address (GPA) and must
31256 * point to a physically contiguous block of memory.
31258 uint64_t resp_addr;
31261 * Enumeration denoting the RX, TX type of the resource.
31262 * This enumeration is used for resources that are similar for both
31263 * TX and RX paths of the chip.
31265 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
31267 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
31270 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
31272 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
31273 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
31275 /* This value identifies a meter profile in CFA. */
31276 uint16_t meter_profile_id;
31278 * A value of 0xfff is considered invalid and implies the
31279 * profile is not configured.
31281 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
31283 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
31284 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
31285 uint8_t unused_1[4];
31288 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
31289 struct hwrm_cfa_meter_profile_free_output {
31290 /* The specific error status for the command. */
31291 uint16_t error_code;
31292 /* The HWRM command request type. */
31294 /* The sequence ID from the original command. */
31296 /* The length of the response data in number of bytes. */
31298 uint8_t unused_0[7];
31300 * This field is used in Output records to indicate that the output
31301 * is completely written to RAM. This field should be read as '1'
31302 * to indicate that the output has been completely written.
31303 * When writing a command completion or response to an internal processor,
31304 * the order of writes has to be such that this field is written last.
31309 /******************************
31310 * hwrm_cfa_meter_profile_cfg *
31311 ******************************/
31314 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
31315 struct hwrm_cfa_meter_profile_cfg_input {
31316 /* The HWRM command request type. */
31319 * The completion ring to send the completion event on. This should
31320 * be the NQ ID returned from the `nq_alloc` HWRM command.
31322 uint16_t cmpl_ring;
31324 * The sequence ID is used by the driver for tracking multiple
31325 * commands. This ID is treated as opaque data by the firmware and
31326 * the value is returned in the `hwrm_resp_hdr` upon completion.
31330 * The target ID of the command:
31331 * * 0x0-0xFFF8 - The function ID
31332 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31333 * * 0xFFFD - Reserved for user-space HWRM interface
31336 uint16_t target_id;
31338 * A physical address pointer pointing to a host buffer that the
31339 * command's response data will be written. This can be either a host
31340 * physical address (HPA) or a guest physical address (GPA) and must
31341 * point to a physically contiguous block of memory.
31343 uint64_t resp_addr;
31346 * Enumeration denoting the RX, TX type of the resource.
31347 * This enumeration is used for resources that are similar for both
31348 * TX and RX paths of the chip.
31350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31352 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31354 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31355 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
31356 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
31357 /* The meter algorithm type. */
31358 uint8_t meter_type;
31359 /* RFC 2697 (srTCM) */
31360 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
31362 /* RFC 2698 (trTCM) */
31363 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
31365 /* RFC 4115 (trTCM) */
31366 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
31368 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
31369 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
31370 /* This value identifies a meter profile in CFA. */
31371 uint16_t meter_profile_id;
31373 * A value of 0xfff is considered invalid and implies the
31374 * profile is not configured.
31376 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
31378 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
31379 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
31381 * This field is reserved for the future use.
31382 * It shall be set to 0.
31385 /* A meter rate specified in bytes-per-second. */
31386 uint32_t commit_rate;
31387 /* The bandwidth value. */
31388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
31389 UINT32_C(0xfffffff)
31390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
31392 /* The granularity of the value (bits or bytes). */
31393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
31394 UINT32_C(0x10000000)
31395 /* Value is in bits. */
31396 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
31397 (UINT32_C(0x0) << 28)
31398 /* Value is in bytes. */
31399 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
31400 (UINT32_C(0x1) << 28)
31401 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
31402 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
31403 /* bw_value_unit is 3 b */
31404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
31405 UINT32_C(0xe0000000)
31406 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
31408 /* Value is in Mb or MB (base 10). */
31409 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
31410 (UINT32_C(0x0) << 29)
31411 /* Value is in Kb or KB (base 10). */
31412 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
31413 (UINT32_C(0x2) << 29)
31414 /* Value is in bits or bytes. */
31415 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
31416 (UINT32_C(0x4) << 29)
31417 /* Value is in Gb or GB (base 10). */
31418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
31419 (UINT32_C(0x6) << 29)
31420 /* Value is in 1/100th of a percentage of total bandwidth. */
31421 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
31422 (UINT32_C(0x1) << 29)
31424 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
31425 (UINT32_C(0x7) << 29)
31426 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
31427 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
31428 /* A meter burst size specified in bytes. */
31429 uint32_t commit_burst;
31430 /* The bandwidth value. */
31431 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
31432 UINT32_C(0xfffffff)
31433 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
31435 /* The granularity of the value (bits or bytes). */
31436 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
31437 UINT32_C(0x10000000)
31438 /* Value is in bits. */
31439 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
31440 (UINT32_C(0x0) << 28)
31441 /* Value is in bytes. */
31442 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
31443 (UINT32_C(0x1) << 28)
31444 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
31445 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
31446 /* bw_value_unit is 3 b */
31447 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
31448 UINT32_C(0xe0000000)
31449 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
31451 /* Value is in Mb or MB (base 10). */
31452 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
31453 (UINT32_C(0x0) << 29)
31454 /* Value is in Kb or KB (base 10). */
31455 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
31456 (UINT32_C(0x2) << 29)
31457 /* Value is in bits or bytes. */
31458 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
31459 (UINT32_C(0x4) << 29)
31460 /* Value is in Gb or GB (base 10). */
31461 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
31462 (UINT32_C(0x6) << 29)
31463 /* Value is in 1/100th of a percentage of total bandwidth. */
31464 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
31465 (UINT32_C(0x1) << 29)
31466 /* Invalid value */
31467 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
31468 (UINT32_C(0x7) << 29)
31469 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
31470 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
31471 /* A meter rate specified in bytes-per-second. */
31472 uint32_t excess_peak_rate;
31473 /* The bandwidth value. */
31474 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
31475 UINT32_C(0xfffffff)
31476 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
31478 /* The granularity of the value (bits or bytes). */
31479 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
31480 UINT32_C(0x10000000)
31481 /* Value is in bits. */
31482 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
31483 (UINT32_C(0x0) << 28)
31484 /* Value is in bytes. */
31485 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
31486 (UINT32_C(0x1) << 28)
31487 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
31488 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
31489 /* bw_value_unit is 3 b */
31490 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
31491 UINT32_C(0xe0000000)
31492 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
31494 /* Value is in Mb or MB (base 10). */
31495 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
31496 (UINT32_C(0x0) << 29)
31497 /* Value is in Kb or KB (base 10). */
31498 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
31499 (UINT32_C(0x2) << 29)
31500 /* Value is in bits or bytes. */
31501 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
31502 (UINT32_C(0x4) << 29)
31503 /* Value is in Gb or GB (base 10). */
31504 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
31505 (UINT32_C(0x6) << 29)
31506 /* Value is in 1/100th of a percentage of total bandwidth. */
31507 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
31508 (UINT32_C(0x1) << 29)
31510 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
31511 (UINT32_C(0x7) << 29)
31512 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
31513 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
31514 /* A meter burst size specified in bytes. */
31515 uint32_t excess_peak_burst;
31516 /* The bandwidth value. */
31517 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
31518 UINT32_C(0xfffffff)
31519 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
31521 /* The granularity of the value (bits or bytes). */
31522 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
31523 UINT32_C(0x10000000)
31524 /* Value is in bits. */
31525 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
31526 (UINT32_C(0x0) << 28)
31527 /* Value is in bytes. */
31528 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
31529 (UINT32_C(0x1) << 28)
31530 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
31531 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
31532 /* bw_value_unit is 3 b */
31533 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
31534 UINT32_C(0xe0000000)
31535 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
31537 /* Value is in Mb or MB (base 10). */
31538 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
31539 (UINT32_C(0x0) << 29)
31540 /* Value is in Kb or KB (base 10). */
31541 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
31542 (UINT32_C(0x2) << 29)
31543 /* Value is in bits or bytes. */
31544 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
31545 (UINT32_C(0x4) << 29)
31546 /* Value is in Gb or GB (base 10). */
31547 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
31548 (UINT32_C(0x6) << 29)
31549 /* Value is in 1/100th of a percentage of total bandwidth. */
31550 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
31551 (UINT32_C(0x1) << 29)
31553 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
31554 (UINT32_C(0x7) << 29)
31555 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
31556 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
31559 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
31560 struct hwrm_cfa_meter_profile_cfg_output {
31561 /* The specific error status for the command. */
31562 uint16_t error_code;
31563 /* The HWRM command request type. */
31565 /* The sequence ID from the original command. */
31567 /* The length of the response data in number of bytes. */
31569 uint8_t unused_0[7];
31571 * This field is used in Output records to indicate that the output
31572 * is completely written to RAM. This field should be read as '1'
31573 * to indicate that the output has been completely written.
31574 * When writing a command completion or response to an internal processor,
31575 * the order of writes has to be such that this field is written last.
31580 /*********************************
31581 * hwrm_cfa_meter_instance_alloc *
31582 *********************************/
31585 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
31586 struct hwrm_cfa_meter_instance_alloc_input {
31587 /* The HWRM command request type. */
31590 * The completion ring to send the completion event on. This should
31591 * be the NQ ID returned from the `nq_alloc` HWRM command.
31593 uint16_t cmpl_ring;
31595 * The sequence ID is used by the driver for tracking multiple
31596 * commands. This ID is treated as opaque data by the firmware and
31597 * the value is returned in the `hwrm_resp_hdr` upon completion.
31601 * The target ID of the command:
31602 * * 0x0-0xFFF8 - The function ID
31603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31604 * * 0xFFFD - Reserved for user-space HWRM interface
31607 uint16_t target_id;
31609 * A physical address pointer pointing to a host buffer that the
31610 * command's response data will be written. This can be either a host
31611 * physical address (HPA) or a guest physical address (GPA) and must
31612 * point to a physically contiguous block of memory.
31614 uint64_t resp_addr;
31617 * Enumeration denoting the RX, TX type of the resource.
31618 * This enumeration is used for resources that are similar for both
31619 * TX and RX paths of the chip.
31621 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
31624 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
31627 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
31629 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
31630 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
31632 /* This value identifies a meter profile in CFA. */
31633 uint16_t meter_profile_id;
31635 * A value of 0xffff is considered invalid and implies the
31636 * profile is not configured.
31638 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
31640 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
31641 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
31642 uint8_t unused_1[4];
31645 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
31646 struct hwrm_cfa_meter_instance_alloc_output {
31647 /* The specific error status for the command. */
31648 uint16_t error_code;
31649 /* The HWRM command request type. */
31651 /* The sequence ID from the original command. */
31653 /* The length of the response data in number of bytes. */
31655 /* This value identifies a meter instance in CFA. */
31656 uint16_t meter_instance_id;
31658 * A value of 0xffff is considered invalid and implies the
31659 * instance is not configured.
31661 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
31663 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
31664 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
31665 uint8_t unused_0[5];
31667 * This field is used in Output records to indicate that the output
31668 * is completely written to RAM. This field should be read as '1'
31669 * to indicate that the output has been completely written.
31670 * When writing a command completion or response to an internal processor,
31671 * the order of writes has to be such that this field is written last.
31676 /*******************************
31677 * hwrm_cfa_meter_instance_cfg *
31678 *******************************/
31681 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
31682 struct hwrm_cfa_meter_instance_cfg_input {
31683 /* The HWRM command request type. */
31686 * The completion ring to send the completion event on. This should
31687 * be the NQ ID returned from the `nq_alloc` HWRM command.
31689 uint16_t cmpl_ring;
31691 * The sequence ID is used by the driver for tracking multiple
31692 * commands. This ID is treated as opaque data by the firmware and
31693 * the value is returned in the `hwrm_resp_hdr` upon completion.
31697 * The target ID of the command:
31698 * * 0x0-0xFFF8 - The function ID
31699 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31700 * * 0xFFFD - Reserved for user-space HWRM interface
31703 uint16_t target_id;
31705 * A physical address pointer pointing to a host buffer that the
31706 * command's response data will be written. This can be either a host
31707 * physical address (HPA) or a guest physical address (GPA) and must
31708 * point to a physically contiguous block of memory.
31710 uint64_t resp_addr;
31713 * Enumeration denoting the RX, TX type of the resource.
31714 * This enumeration is used for resources that are similar for both
31715 * TX and RX paths of the chip.
31717 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
31719 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
31722 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
31724 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
31725 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
31728 * This value identifies a new meter profile to be associated with
31729 * the meter instance specified in this command.
31731 uint16_t meter_profile_id;
31733 * A value of 0xffff is considered invalid and implies the
31734 * profile is not configured.
31736 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
31738 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
31739 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
31741 * This value identifies the ID of a meter instance that needs to be updated with
31742 * a new meter profile specified in this command.
31744 uint16_t meter_instance_id;
31745 uint8_t unused_1[2];
31748 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
31749 struct hwrm_cfa_meter_instance_cfg_output {
31750 /* The specific error status for the command. */
31751 uint16_t error_code;
31752 /* The HWRM command request type. */
31754 /* The sequence ID from the original command. */
31756 /* The length of the response data in number of bytes. */
31758 uint8_t unused_0[7];
31760 * This field is used in Output records to indicate that the output
31761 * is completely written to RAM. This field should be read as '1'
31762 * to indicate that the output has been completely written.
31763 * When writing a command completion or response to an internal processor,
31764 * the order of writes has to be such that this field is written last.
31769 /********************************
31770 * hwrm_cfa_meter_instance_free *
31771 ********************************/
31774 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
31775 struct hwrm_cfa_meter_instance_free_input {
31776 /* The HWRM command request type. */
31779 * The completion ring to send the completion event on. This should
31780 * be the NQ ID returned from the `nq_alloc` HWRM command.
31782 uint16_t cmpl_ring;
31784 * The sequence ID is used by the driver for tracking multiple
31785 * commands. This ID is treated as opaque data by the firmware and
31786 * the value is returned in the `hwrm_resp_hdr` upon completion.
31790 * The target ID of the command:
31791 * * 0x0-0xFFF8 - The function ID
31792 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31793 * * 0xFFFD - Reserved for user-space HWRM interface
31796 uint16_t target_id;
31798 * A physical address pointer pointing to a host buffer that the
31799 * command's response data will be written. This can be either a host
31800 * physical address (HPA) or a guest physical address (GPA) and must
31801 * point to a physically contiguous block of memory.
31803 uint64_t resp_addr;
31806 * Enumeration denoting the RX, TX type of the resource.
31807 * This enumeration is used for resources that are similar for both
31808 * TX and RX paths of the chip.
31810 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
31812 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
31815 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
31817 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
31818 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
31820 /* This value identifies a meter instance in CFA. */
31821 uint16_t meter_instance_id;
31823 * A value of 0xfff is considered invalid and implies the
31824 * instance is not configured.
31826 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
31828 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
31829 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
31830 uint8_t unused_1[4];
31833 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
31834 struct hwrm_cfa_meter_instance_free_output {
31835 /* The specific error status for the command. */
31836 uint16_t error_code;
31837 /* The HWRM command request type. */
31839 /* The sequence ID from the original command. */
31841 /* The length of the response data in number of bytes. */
31843 uint8_t unused_0[7];
31845 * This field is used in Output records to indicate that the output
31846 * is completely written to RAM. This field should be read as '1'
31847 * to indicate that the output has been completely written.
31848 * When writing a command completion or response to an internal processor,
31849 * the order of writes has to be such that this field is written last.
31854 /*******************************
31855 * hwrm_cfa_decap_filter_alloc *
31856 *******************************/
31859 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
31860 struct hwrm_cfa_decap_filter_alloc_input {
31861 /* The HWRM command request type. */
31864 * The completion ring to send the completion event on. This should
31865 * be the NQ ID returned from the `nq_alloc` HWRM command.
31867 uint16_t cmpl_ring;
31869 * The sequence ID is used by the driver for tracking multiple
31870 * commands. This ID is treated as opaque data by the firmware and
31871 * the value is returned in the `hwrm_resp_hdr` upon completion.
31875 * The target ID of the command:
31876 * * 0x0-0xFFF8 - The function ID
31877 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31878 * * 0xFFFD - Reserved for user-space HWRM interface
31881 uint16_t target_id;
31883 * A physical address pointer pointing to a host buffer that the
31884 * command's response data will be written. This can be either a host
31885 * physical address (HPA) or a guest physical address (GPA) and must
31886 * point to a physically contiguous block of memory.
31888 uint64_t resp_addr;
31890 /* ovs_tunnel is 1 b */
31891 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
31895 * This bit must be '1' for the tunnel_type field to be
31898 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31901 * This bit must be '1' for the tunnel_id field to be
31904 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
31907 * This bit must be '1' for the src_macaddr field to be
31910 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31913 * This bit must be '1' for the dst_macaddr field to be
31916 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
31919 * This bit must be '1' for the ovlan_vid field to be
31922 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
31925 * This bit must be '1' for the ivlan_vid field to be
31928 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
31931 * This bit must be '1' for the t_ovlan_vid field to be
31934 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
31937 * This bit must be '1' for the t_ivlan_vid field to be
31940 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
31943 * This bit must be '1' for the ethertype field to be
31946 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
31949 * This bit must be '1' for the src_ipaddr field to be
31952 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
31955 * This bit must be '1' for the dst_ipaddr field to be
31958 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
31961 * This bit must be '1' for the ipaddr_type field to be
31964 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
31967 * This bit must be '1' for the ip_protocol field to be
31970 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
31973 * This bit must be '1' for the src_port field to be
31976 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
31979 * This bit must be '1' for the dst_port field to be
31982 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
31985 * This bit must be '1' for the dst_id field to be
31988 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
31991 * This bit must be '1' for the mirror_vnic_id field to be
31994 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31997 * Tunnel identifier.
31998 * Virtual Network Identifier (VNI). Only valid with
31999 * tunnel_types VXLAN, NVGRE, and Geneve.
32000 * Only lower 24-bits of VNI field are used
32001 * in setting up the filter.
32003 uint32_t tunnel_id;
32005 uint8_t tunnel_type;
32007 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
32009 /* Virtual eXtensible Local Area Network (VXLAN) */
32010 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32012 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32013 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
32015 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32016 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
32019 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
32021 /* Generic Network Virtualization Encapsulation (Geneve) */
32022 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32024 /* Multi-Protocol Label Switching (MPLS) */
32025 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
32027 /* Stateless Transport Tunnel (STT) */
32028 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
32030 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32031 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
32033 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32034 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32036 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32037 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32039 /* Use fixed layer 2 ether type of 0xFFFF */
32040 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32042 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32043 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32045 /* Any tunneled traffic */
32046 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32048 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32049 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32053 * This value indicates the source MAC address in
32054 * the Ethernet header.
32056 uint8_t src_macaddr[6];
32057 uint8_t unused_2[2];
32059 * This value indicates the destination MAC address in
32060 * the Ethernet header.
32062 uint8_t dst_macaddr[6];
32064 * This value indicates the VLAN ID of the outer VLAN tag
32065 * in the Ethernet header.
32067 uint16_t ovlan_vid;
32069 * This value indicates the VLAN ID of the inner VLAN tag
32070 * in the Ethernet header.
32072 uint16_t ivlan_vid;
32074 * This value indicates the VLAN ID of the outer VLAN tag
32075 * in the tunnel Ethernet header.
32077 uint16_t t_ovlan_vid;
32079 * This value indicates the VLAN ID of the inner VLAN tag
32080 * in the tunnel Ethernet header.
32082 uint16_t t_ivlan_vid;
32083 /* This value indicates the ethertype in the Ethernet header. */
32084 uint16_t ethertype;
32086 * This value indicates the type of IP address.
32089 * All others are invalid.
32091 uint8_t ip_addr_type;
32093 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
32096 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
32099 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
32101 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
32102 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
32104 * The value of protocol filed in IP header.
32105 * Applies to UDP and TCP traffic.
32109 uint8_t ip_protocol;
32111 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
32114 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
32117 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
32119 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
32120 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
32124 * The value of source IP address to be used in filtering.
32125 * For IPv4, first four bytes represent the IP address.
32127 uint32_t src_ipaddr[4];
32129 * The value of destination IP address to be used in filtering.
32130 * For IPv4, first four bytes represent the IP address.
32132 uint32_t dst_ipaddr[4];
32134 * The value of source port to be used in filtering.
32135 * Applies to UDP and TCP traffic.
32139 * The value of destination port to be used in filtering.
32140 * Applies to UDP and TCP traffic.
32144 * If set, this value shall represent the
32145 * Logical VNIC ID of the destination VNIC for the RX
32150 * If set, this value shall represent the L2 context that matches the L2
32151 * information of the decap filter.
32153 uint16_t l2_ctxt_ref_id;
32156 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
32157 struct hwrm_cfa_decap_filter_alloc_output {
32158 /* The specific error status for the command. */
32159 uint16_t error_code;
32160 /* The HWRM command request type. */
32162 /* The sequence ID from the original command. */
32164 /* The length of the response data in number of bytes. */
32166 /* This value is an opaque id into CFA data structures. */
32167 uint32_t decap_filter_id;
32168 uint8_t unused_0[3];
32170 * This field is used in Output records to indicate that the output
32171 * is completely written to RAM. This field should be read as '1'
32172 * to indicate that the output has been completely written.
32173 * When writing a command completion or response to an internal processor,
32174 * the order of writes has to be such that this field is written last.
32179 /******************************
32180 * hwrm_cfa_decap_filter_free *
32181 ******************************/
32184 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
32185 struct hwrm_cfa_decap_filter_free_input {
32186 /* The HWRM command request type. */
32189 * The completion ring to send the completion event on. This should
32190 * be the NQ ID returned from the `nq_alloc` HWRM command.
32192 uint16_t cmpl_ring;
32194 * The sequence ID is used by the driver for tracking multiple
32195 * commands. This ID is treated as opaque data by the firmware and
32196 * the value is returned in the `hwrm_resp_hdr` upon completion.
32200 * The target ID of the command:
32201 * * 0x0-0xFFF8 - The function ID
32202 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32203 * * 0xFFFD - Reserved for user-space HWRM interface
32206 uint16_t target_id;
32208 * A physical address pointer pointing to a host buffer that the
32209 * command's response data will be written. This can be either a host
32210 * physical address (HPA) or a guest physical address (GPA) and must
32211 * point to a physically contiguous block of memory.
32213 uint64_t resp_addr;
32214 /* This value is an opaque id into CFA data structures. */
32215 uint32_t decap_filter_id;
32216 uint8_t unused_0[4];
32219 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
32220 struct hwrm_cfa_decap_filter_free_output {
32221 /* The specific error status for the command. */
32222 uint16_t error_code;
32223 /* The HWRM command request type. */
32225 /* The sequence ID from the original command. */
32227 /* The length of the response data in number of bytes. */
32229 uint8_t unused_0[7];
32231 * This field is used in Output records to indicate that the output
32232 * is completely written to RAM. This field should be read as '1'
32233 * to indicate that the output has been completely written.
32234 * When writing a command completion or response to an internal processor,
32235 * the order of writes has to be such that this field is written last.
32240 /***********************
32241 * hwrm_cfa_flow_alloc *
32242 ***********************/
32245 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
32246 struct hwrm_cfa_flow_alloc_input {
32247 /* The HWRM command request type. */
32250 * The completion ring to send the completion event on. This should
32251 * be the NQ ID returned from the `nq_alloc` HWRM command.
32253 uint16_t cmpl_ring;
32255 * The sequence ID is used by the driver for tracking multiple
32256 * commands. This ID is treated as opaque data by the firmware and
32257 * the value is returned in the `hwrm_resp_hdr` upon completion.
32261 * The target ID of the command:
32262 * * 0x0-0xFFF8 - The function ID
32263 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32264 * * 0xFFFD - Reserved for user-space HWRM interface
32267 uint16_t target_id;
32269 * A physical address pointer pointing to a host buffer that the
32270 * command's response data will be written. This can be either a host
32271 * physical address (HPA) or a guest physical address (GPA) and must
32272 * point to a physically contiguous block of memory.
32274 uint64_t resp_addr;
32276 /* tunnel is 1 b */
32277 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
32279 /* num_vlan is 2 b */
32280 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
32282 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
32284 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
32285 (UINT32_C(0x0) << 1)
32287 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
32288 (UINT32_C(0x1) << 1)
32290 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
32291 (UINT32_C(0x2) << 1)
32292 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
32293 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
32294 /* Enumeration denoting the Flow Type. */
32295 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
32297 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
32299 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
32300 (UINT32_C(0x0) << 3)
32302 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
32303 (UINT32_C(0x1) << 3)
32305 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
32306 (UINT32_C(0x2) << 3)
32307 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
32308 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
32310 * when set to 1, indicates TX flow offload for function specified in src_fid and
32311 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
32312 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
32313 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
32314 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
32315 * belong to the children VFs of the same PF to indicate VM to VM flow.
32317 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
32320 * when set to 1, indicates RX flow offload for function specified in dst_fid and
32321 * the src_fid should be set to invalid value.
32323 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
32326 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
32327 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
32328 * This flag is only valid when the flow direction is RX.
32330 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
32332 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
32333 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
32340 /* Tunnel handle valid when tunnel flag is set. */
32341 uint32_t tunnel_handle;
32342 uint16_t action_flags;
32344 * Setting of this flag indicates drop action. If this flag is not set,
32345 * then it should be considered accept action.
32347 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
32349 /* recycle is 1 b */
32350 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
32353 * Setting of this flag indicates drop action. If this flag is not set,
32354 * then it should be considered accept action.
32356 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
32359 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
32361 /* tunnel is 1 b */
32362 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
32364 /* nat_src is 1 b */
32365 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
32367 /* nat_dest is 1 b */
32368 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
32370 /* nat_ipv4_address is 1 b */
32371 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
32373 /* l2_header_rewrite is 1 b */
32374 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
32376 /* ttl_decrement is 1 b */
32377 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
32380 * If set to 1 and flow direction is TX, it indicates decap of L2 header
32381 * and encap of tunnel header. If set to 1 and flow direction is RX, it
32382 * indicates decap of tunnel header and encap L2 header. The type of tunnel
32383 * is specified in the tunnel_type field.
32385 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
32387 /* If set to 1, flow aging is enabled for this flow. */
32388 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
32391 * If set to 1 an attempt will be made to try to offload this flow to the
32392 * most optimal flow table resource. If set to 0, the flow will be
32393 * placed to the default flow table resource.
32395 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
32398 * If set to 1 there will be no attempt to allocate an on-chip try to
32399 * offload this flow. If set to 0, which will keep compatibility with the
32400 * older drivers, will cause the FW to attempt to allocate an on-chip flow
32401 * counter for the newly created flow. This will keep the existing behavior
32402 * with EM flows which always had an associated flow counter.
32404 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
32407 * Tx Flow: pf or vf fid.
32411 /* VLAN tpid, valid when push_vlan flag is set. */
32412 uint16_t l2_rewrite_vlan_tpid;
32413 /* VLAN tci, valid when push_vlan flag is set. */
32414 uint16_t l2_rewrite_vlan_tci;
32415 /* Meter id, valid when meter flag is set. */
32416 uint16_t act_meter_id;
32417 /* Flow with the same l2 context tcam key. */
32418 uint16_t ref_flow_handle;
32419 /* This value sets the match value for the ethertype. */
32420 uint16_t ethertype;
32421 /* valid when num tags is 1 or 2. */
32422 uint16_t outer_vlan_tci;
32423 /* This value sets the match value for the Destination MAC address. */
32425 /* valid when num tags is 2. */
32426 uint16_t inner_vlan_tci;
32427 /* This value sets the match value for the Source MAC address. */
32429 /* The bit length of destination IP address mask. */
32430 uint8_t ip_dst_mask_len;
32431 /* The bit length of source IP address mask. */
32432 uint8_t ip_src_mask_len;
32433 /* The value of destination IPv4/IPv6 address. */
32434 uint32_t ip_dst[4];
32435 /* The source IPv4/IPv6 address. */
32436 uint32_t ip_src[4];
32438 * The value of source port.
32439 * Applies to UDP and TCP traffic.
32441 uint16_t l4_src_port;
32443 * The value of source port mask.
32444 * Applies to UDP and TCP traffic.
32446 uint16_t l4_src_port_mask;
32448 * The value of destination port.
32449 * Applies to UDP and TCP traffic.
32451 uint16_t l4_dst_port;
32453 * The value of destination port mask.
32454 * Applies to UDP and TCP traffic.
32456 uint16_t l4_dst_port_mask;
32458 * NAT IPv4/6 address based on address type flag.
32459 * 0 values are ignored.
32461 uint32_t nat_ip_address[4];
32462 /* L2 header re-write Destination MAC address. */
32463 uint16_t l2_rewrite_dmac[3];
32465 * The NAT source/destination port based on direction flag.
32466 * Applies to UDP and TCP traffic.
32467 * 0 values are ignored.
32470 /* L2 header re-write Source MAC address. */
32471 uint16_t l2_rewrite_smac[3];
32472 /* The value of ip protocol. */
32475 uint8_t tunnel_type;
32477 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
32479 /* Virtual eXtensible Local Area Network (VXLAN) */
32480 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32482 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32483 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
32485 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32486 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
32489 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
32491 /* Generic Network Virtualization Encapsulation (Geneve) */
32492 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32494 /* Multi-Protocol Label Switching (MPLS) */
32495 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
32497 /* Stateless Transport Tunnel (STT) */
32498 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
32500 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32501 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
32503 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32504 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32506 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32507 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32509 /* Use fixed layer 2 ether type of 0xFFFF */
32510 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32512 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32513 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32515 /* Any tunneled traffic */
32516 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32518 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32519 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32522 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
32523 struct hwrm_cfa_flow_alloc_output {
32524 /* The specific error status for the command. */
32525 uint16_t error_code;
32526 /* The HWRM command request type. */
32528 /* The sequence ID from the original command. */
32530 /* The length of the response data in number of bytes. */
32532 /* Flow record index. */
32533 uint16_t flow_handle;
32534 uint8_t unused_0[2];
32536 * The flow id value in bit 0-29 is the actual ID of the flow
32537 * associated with this filter and it shall be used to match
32538 * and associate the flow identifier returned in completion
32539 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32540 * shall indicate no valid flow id.
32543 /* Indicate the flow id value. */
32544 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32545 UINT32_C(0x3fffffff)
32546 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32547 /* Indicate type of the flow. */
32548 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
32549 UINT32_C(0x40000000)
32551 * If this bit set to 0, then it indicates that the flow is
32554 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32555 (UINT32_C(0x0) << 30)
32557 * If this bit is set to 1, then it indicates that the flow is
32560 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32561 (UINT32_C(0x1) << 30)
32562 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32563 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32564 /* Indicate the flow direction. */
32565 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
32566 UINT32_C(0x80000000)
32567 /* If this bit set to 0, then it indicates rx flow. */
32568 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32569 (UINT32_C(0x0) << 31)
32570 /* If this bit is set to 1, then it indicates that tx flow. */
32571 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32572 (UINT32_C(0x1) << 31)
32573 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32574 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32575 /* This value identifies a set of CFA data structures used for a flow. */
32576 uint64_t ext_flow_handle;
32577 uint32_t flow_counter_id;
32578 uint8_t unused_1[3];
32580 * This field is used in Output records to indicate that the output
32581 * is completely written to RAM. This field should be read as '1'
32582 * to indicate that the output has been completely written.
32583 * When writing a command completion or response to an internal processor,
32584 * the order of writes has to be such that this field is written last.
32589 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
32590 struct hwrm_cfa_flow_alloc_cmd_err {
32592 * command specific error codes that goes to
32593 * the cmd_err field in Common HWRM Error Response.
32596 /* Unknown error */
32597 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32598 /* No more L2 Context TCAM */
32599 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
32600 /* No more action records */
32601 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
32602 /* No more flow counters */
32603 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
32604 /* No more wild-card TCAM */
32605 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
32606 /* Hash collsion in exact match tables */
32607 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
32608 /* Key is already installed */
32609 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
32610 /* Flow Context DB is out of resource */
32611 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
32612 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
32613 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
32614 uint8_t unused_0[7];
32617 /**********************
32618 * hwrm_cfa_flow_free *
32619 **********************/
32622 /* hwrm_cfa_flow_free_input (size:256b/32B) */
32623 struct hwrm_cfa_flow_free_input {
32624 /* The HWRM command request type. */
32627 * The completion ring to send the completion event on. This should
32628 * be the NQ ID returned from the `nq_alloc` HWRM command.
32630 uint16_t cmpl_ring;
32632 * The sequence ID is used by the driver for tracking multiple
32633 * commands. This ID is treated as opaque data by the firmware and
32634 * the value is returned in the `hwrm_resp_hdr` upon completion.
32638 * The target ID of the command:
32639 * * 0x0-0xFFF8 - The function ID
32640 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32641 * * 0xFFFD - Reserved for user-space HWRM interface
32644 uint16_t target_id;
32646 * A physical address pointer pointing to a host buffer that the
32647 * command's response data will be written. This can be either a host
32648 * physical address (HPA) or a guest physical address (GPA) and must
32649 * point to a physically contiguous block of memory.
32651 uint64_t resp_addr;
32652 /* Flow record index. */
32653 uint16_t flow_handle;
32655 /* Flow counter id to be freed. */
32656 uint32_t flow_counter_id;
32657 /* This value identifies a set of CFA data structures used for a flow. */
32658 uint64_t ext_flow_handle;
32661 /* hwrm_cfa_flow_free_output (size:256b/32B) */
32662 struct hwrm_cfa_flow_free_output {
32663 /* The specific error status for the command. */
32664 uint16_t error_code;
32665 /* The HWRM command request type. */
32667 /* The sequence ID from the original command. */
32669 /* The length of the response data in number of bytes. */
32671 /* packet is 64 b */
32675 uint8_t unused_0[7];
32677 * This field is used in Output records to indicate that the output
32678 * is completely written to RAM. This field should be read as '1'
32679 * to indicate that the output has been completely written.
32680 * When writing a command completion or response to an internal processor,
32681 * the order of writes has to be such that this field is written last.
32686 /* hwrm_cfa_flow_action_data (size:960b/120B) */
32687 struct hwrm_cfa_flow_action_data {
32688 uint16_t action_flags;
32689 /* Setting of this flag indicates accept action. */
32690 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
32692 /* Setting of this flag indicates recycle action. */
32693 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
32695 /* Setting of this flag indicates drop action. */
32696 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
32698 /* Setting of this flag indicates meter action. */
32699 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
32701 /* Setting of this flag indicates tunnel action. */
32702 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
32705 * If set to 1 and flow direction is TX, it indicates decap of L2 header
32706 * and encap of tunnel header. If set to 1 and flow direction is RX, it
32707 * indicates decap of tunnel header and encap L2 header.
32709 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
32711 /* Setting of this flag indicates ttl decrement action. */
32712 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
32714 /* If set to 1, flow aging is enabled for this flow. */
32715 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
32717 /* Setting of this flag indicates encap action. */
32718 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
32720 /* Setting of this flag indicates decap action. */
32721 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
32724 uint16_t act_meter_id;
32727 /* vport number. */
32729 /* The NAT source/destination. */
32731 uint16_t unused_0[3];
32732 /* NAT IPv4/IPv6 address. */
32733 uint32_t nat_ip_address[4];
32734 /* Encapsulation Type. */
32735 uint8_t encap_type;
32736 /* Virtual eXtensible Local Area Network (VXLAN) */
32737 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
32738 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32739 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
32740 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
32741 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
32743 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
32744 /* Generic Network Virtualization Encapsulation (Geneve) */
32745 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
32746 /* Multi-Protocol Label Switching (MPLS) */
32747 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
32749 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
32750 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32751 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
32752 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32753 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
32754 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32755 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
32756 /* Use fixed layer 2 ether type of 0xFFFF */
32757 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
32758 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32759 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
32760 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
32761 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
32763 /* This value is encap data for the associated encap type. */
32764 uint32_t encap_data[20];
32767 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
32768 struct hwrm_cfa_flow_tunnel_hdr_data {
32770 uint8_t tunnel_type;
32772 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
32774 /* Virtual eXtensible Local Area Network (VXLAN) */
32775 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
32777 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32778 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
32780 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32781 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
32784 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
32786 /* Generic Network Virtualization Encapsulation (Geneve) */
32787 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
32789 /* Multi-Protocol Label Switching (MPLS) */
32790 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
32792 /* Stateless Transport Tunnel (STT) */
32793 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
32795 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32796 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
32798 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32799 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
32801 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32802 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
32804 /* Use fixed layer 2 ether type of 0xFFFF */
32805 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
32807 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32808 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
32810 /* Any tunneled traffic */
32811 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
32813 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
32814 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
32817 * Tunnel identifier.
32818 * Virtual Network Identifier (VNI).
32820 uint32_t tunnel_id;
32823 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
32824 struct hwrm_cfa_flow_l4_key_data {
32825 /* The value of source port. */
32826 uint16_t l4_src_port;
32827 /* The value of destination port. */
32828 uint16_t l4_dst_port;
32832 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
32833 struct hwrm_cfa_flow_l3_key_data {
32834 /* The value of ip protocol. */
32835 uint8_t ip_protocol;
32836 uint8_t unused_0[7];
32837 /* The value of destination IPv4/IPv6 address. */
32838 uint32_t ip_dst[4];
32839 /* The source IPv4/IPv6 address. */
32840 uint32_t ip_src[4];
32841 /* NAT IPv4/IPv6 address. */
32842 uint32_t nat_ip_address[4];
32843 uint32_t unused[2];
32846 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
32847 struct hwrm_cfa_flow_l2_key_data {
32848 /* Destination MAC address. */
32851 /* Source MAC address. */
32854 /* L2 header re-write Destination MAC address. */
32855 uint16_t l2_rewrite_dmac[3];
32857 /* L2 header re-write Source MAC address. */
32858 uint16_t l2_rewrite_smac[3];
32860 uint16_t ethertype;
32861 /* Number of VLAN tags. */
32862 uint16_t num_vlan_tags;
32864 uint16_t l2_rewrite_vlan_tpid;
32866 uint16_t l2_rewrite_vlan_tci;
32867 uint8_t unused_3[2];
32868 /* Outer VLAN TPID. */
32869 uint16_t ovlan_tpid;
32870 /* Outer VLAN TCI. */
32871 uint16_t ovlan_tci;
32872 /* Inner VLAN TPID. */
32873 uint16_t ivlan_tpid;
32874 /* Inner VLAN TCI. */
32875 uint16_t ivlan_tci;
32879 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
32880 struct hwrm_cfa_flow_key_data {
32881 /* Flow associated tunnel L2 header key info. */
32882 uint32_t t_l2_key_data[14];
32883 /* Flow associated tunnel L2 header mask info. */
32884 uint32_t t_l2_key_mask[14];
32885 /* Flow associated tunnel L3 header key info. */
32886 uint32_t t_l3_key_data[16];
32887 /* Flow associated tunnel L3 header mask info. */
32888 uint32_t t_l3_key_mask[16];
32889 /* Flow associated tunnel L4 header key info. */
32890 uint32_t t_l4_key_data[2];
32891 /* Flow associated tunnel L4 header mask info. */
32892 uint32_t t_l4_key_mask[2];
32893 /* Flow associated tunnel header info. */
32894 uint32_t tunnel_hdr[2];
32895 /* Flow associated L2 header key info. */
32896 uint32_t l2_key_data[14];
32897 /* Flow associated L2 header mask info. */
32898 uint32_t l2_key_mask[14];
32899 /* Flow associated L3 header key info. */
32900 uint32_t l3_key_data[16];
32901 /* Flow associated L3 header mask info. */
32902 uint32_t l3_key_mask[16];
32903 /* Flow associated L4 header key info. */
32904 uint32_t l4_key_data[2];
32905 /* Flow associated L4 header mask info. */
32906 uint32_t l4_key_mask[2];
32909 /**********************
32910 * hwrm_cfa_flow_info *
32911 **********************/
32914 /* hwrm_cfa_flow_info_input (size:256b/32B) */
32915 struct hwrm_cfa_flow_info_input {
32916 /* The HWRM command request type. */
32919 * The completion ring to send the completion event on. This should
32920 * be the NQ ID returned from the `nq_alloc` HWRM command.
32922 uint16_t cmpl_ring;
32924 * The sequence ID is used by the driver for tracking multiple
32925 * commands. This ID is treated as opaque data by the firmware and
32926 * the value is returned in the `hwrm_resp_hdr` upon completion.
32930 * The target ID of the command:
32931 * * 0x0-0xFFF8 - The function ID
32932 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32933 * * 0xFFFD - Reserved for user-space HWRM interface
32936 uint16_t target_id;
32938 * A physical address pointer pointing to a host buffer that the
32939 * command's response data will be written. This can be either a host
32940 * physical address (HPA) or a guest physical address (GPA) and must
32941 * point to a physically contiguous block of memory.
32943 uint64_t resp_addr;
32944 /* Flow record index. */
32945 uint16_t flow_handle;
32946 /* Max flow handle */
32947 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
32949 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
32950 /* CNP flow handle */
32951 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
32953 /* RoCEv1 flow handle */
32954 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
32956 /* RoCEv2 flow handle */
32957 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
32959 /* Direction rx = 1 */
32960 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
32962 uint8_t unused_0[6];
32963 /* This value identifies a set of CFA data structures used for a flow. */
32964 uint64_t ext_flow_handle;
32967 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
32968 struct hwrm_cfa_flow_info_output {
32969 /* The specific error status for the command. */
32970 uint16_t error_code;
32971 /* The HWRM command request type. */
32973 /* The sequence ID from the original command. */
32975 /* The length of the response data in number of bytes. */
32978 /* When set to 1, indicates the configuration is the TX flow. */
32979 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
32980 /* When set to 1, indicates the configuration is the RX flow. */
32981 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
32982 /* profile is 8 b */
32984 /* src_fid is 16 b */
32986 /* dst_fid is 16 b */
32988 /* l2_ctxt_id is 16 b */
32989 uint16_t l2_ctxt_id;
32990 /* em_info is 64 b */
32992 /* tcam_info is 64 b */
32993 uint64_t tcam_info;
32994 /* vfp_tcam_info is 64 b */
32995 uint64_t vfp_tcam_info;
32996 /* ar_id is 16 b */
32998 /* flow_handle is 16 b */
32999 uint16_t flow_handle;
33000 /* tunnel_handle is 32 b */
33001 uint32_t tunnel_handle;
33002 /* The flow aging timer for the flow, the unit is 100 milliseconds */
33003 uint16_t flow_timer;
33004 uint8_t unused_0[6];
33005 /* Flow associated L2, L3 and L4 headers info. */
33006 uint32_t flow_key_data[130];
33007 /* Flow associated action record info. */
33008 uint32_t flow_action_info[30];
33009 uint8_t unused_1[7];
33011 * This field is used in Output records to indicate that the output
33012 * is completely written to RAM. This field should be read as '1'
33013 * to indicate that the output has been completely written.
33014 * When writing a command completion or response to an internal processor,
33015 * the order of writes has to be such that this field is written last.
33020 /***********************
33021 * hwrm_cfa_flow_flush *
33022 ***********************/
33025 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
33026 struct hwrm_cfa_flow_flush_input {
33027 /* The HWRM command request type. */
33030 * The completion ring to send the completion event on. This should
33031 * be the NQ ID returned from the `nq_alloc` HWRM command.
33033 uint16_t cmpl_ring;
33035 * The sequence ID is used by the driver for tracking multiple
33036 * commands. This ID is treated as opaque data by the firmware and
33037 * the value is returned in the `hwrm_resp_hdr` upon completion.
33041 * The target ID of the command:
33042 * * 0x0-0xFFF8 - The function ID
33043 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33044 * * 0xFFFD - Reserved for user-space HWRM interface
33047 uint16_t target_id;
33049 * A physical address pointer pointing to a host buffer that the
33050 * command's response data will be written. This can be either a host
33051 * physical address (HPA) or a guest physical address (GPA) and must
33052 * point to a physically contiguous block of memory.
33054 uint64_t resp_addr;
33055 /* flags is 32 b */
33058 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
33059 * fields are valid. The flow flush operation should only flush the flows from the
33060 * flow table specified. This flag is set to 0 by older driver. For older firmware,
33061 * setting this flag has no effect.
33063 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
33066 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
33067 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
33068 * setting this flag has no effect.
33070 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
33073 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
33074 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
33076 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
33078 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
33079 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
33080 UINT32_C(0x8000000)
33082 * This specifies the size of flow handle entries provided by the driver
33083 * in the flow table specified below. Only two flow handle size enums are defined.
33085 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
33086 UINT32_C(0xc0000000)
33087 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
33089 /* The flow handle is 16bit */
33090 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
33091 (UINT32_C(0x0) << 30)
33092 /* The flow handle is 64bit */
33093 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
33094 (UINT32_C(0x1) << 30)
33095 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
33096 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
33097 /* Specify page size of the flow table memory. */
33099 /* The page size is 4K */
33100 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
33101 /* The page size is 8K */
33102 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
33103 /* The page size is 64K */
33104 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
33105 /* The page size is 256K */
33106 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
33107 /* The page size is 1M */
33108 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
33109 /* The page size is 2M */
33110 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
33111 /* The page size is 4M */
33112 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
33113 /* The page size is 1G */
33114 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
33115 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
33116 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
33117 /* FLow table memory indirect levels. */
33118 uint8_t page_level;
33119 /* PBL pointer is physical start address. */
33120 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
33121 /* PBL pointer points to PTE table. */
33122 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
33123 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
33124 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
33125 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
33126 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
33127 /* number of flows in the flow table */
33128 uint16_t num_flows;
33129 /* Pointer to the PBL, or PDL depending on number of levels */
33133 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
33134 struct hwrm_cfa_flow_flush_output {
33135 /* The specific error status for the command. */
33136 uint16_t error_code;
33137 /* The HWRM command request type. */
33139 /* The sequence ID from the original command. */
33141 /* The length of the response data in number of bytes. */
33143 uint8_t unused_0[7];
33145 * This field is used in Output records to indicate that the output
33146 * is completely written to RAM. This field should be read as '1'
33147 * to indicate that the output has been completely written.
33148 * When writing a command completion or response to an internal processor,
33149 * the order of writes has to be such that this field is written last.
33154 /***********************
33155 * hwrm_cfa_flow_stats *
33156 ***********************/
33159 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
33160 struct hwrm_cfa_flow_stats_input {
33161 /* The HWRM command request type. */
33164 * The completion ring to send the completion event on. This should
33165 * be the NQ ID returned from the `nq_alloc` HWRM command.
33167 uint16_t cmpl_ring;
33169 * The sequence ID is used by the driver for tracking multiple
33170 * commands. This ID is treated as opaque data by the firmware and
33171 * the value is returned in the `hwrm_resp_hdr` upon completion.
33175 * The target ID of the command:
33176 * * 0x0-0xFFF8 - The function ID
33177 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33178 * * 0xFFFD - Reserved for user-space HWRM interface
33181 uint16_t target_id;
33183 * A physical address pointer pointing to a host buffer that the
33184 * command's response data will be written. This can be either a host
33185 * physical address (HPA) or a guest physical address (GPA) and must
33186 * point to a physically contiguous block of memory.
33188 uint64_t resp_addr;
33190 uint16_t num_flows;
33192 uint16_t flow_handle_0;
33194 uint16_t flow_handle_1;
33196 uint16_t flow_handle_2;
33198 uint16_t flow_handle_3;
33200 uint16_t flow_handle_4;
33202 uint16_t flow_handle_5;
33204 uint16_t flow_handle_6;
33206 uint16_t flow_handle_7;
33208 uint16_t flow_handle_8;
33210 uint16_t flow_handle_9;
33211 uint8_t unused_0[2];
33212 /* Flow ID of a flow. */
33213 uint32_t flow_id_0;
33214 /* Flow ID of a flow. */
33215 uint32_t flow_id_1;
33216 /* Flow ID of a flow. */
33217 uint32_t flow_id_2;
33218 /* Flow ID of a flow. */
33219 uint32_t flow_id_3;
33220 /* Flow ID of a flow. */
33221 uint32_t flow_id_4;
33222 /* Flow ID of a flow. */
33223 uint32_t flow_id_5;
33224 /* Flow ID of a flow. */
33225 uint32_t flow_id_6;
33226 /* Flow ID of a flow. */
33227 uint32_t flow_id_7;
33228 /* Flow ID of a flow. */
33229 uint32_t flow_id_8;
33230 /* Flow ID of a flow. */
33231 uint32_t flow_id_9;
33234 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
33235 struct hwrm_cfa_flow_stats_output {
33236 /* The specific error status for the command. */
33237 uint16_t error_code;
33238 /* The HWRM command request type. */
33240 /* The sequence ID from the original command. */
33242 /* The length of the response data in number of bytes. */
33244 /* packet_0 is 64 b */
33246 /* packet_1 is 64 b */
33248 /* packet_2 is 64 b */
33250 /* packet_3 is 64 b */
33252 /* packet_4 is 64 b */
33254 /* packet_5 is 64 b */
33256 /* packet_6 is 64 b */
33258 /* packet_7 is 64 b */
33260 /* packet_8 is 64 b */
33262 /* packet_9 is 64 b */
33264 /* byte_0 is 64 b */
33266 /* byte_1 is 64 b */
33268 /* byte_2 is 64 b */
33270 /* byte_3 is 64 b */
33272 /* byte_4 is 64 b */
33274 /* byte_5 is 64 b */
33276 /* byte_6 is 64 b */
33278 /* byte_7 is 64 b */
33280 /* byte_8 is 64 b */
33282 /* byte_9 is 64 b */
33284 uint8_t unused_0[7];
33286 * This field is used in Output records to indicate that the output
33287 * is completely written to RAM. This field should be read as '1'
33288 * to indicate that the output has been completely written.
33289 * When writing a command completion or response to an internal processor,
33290 * the order of writes has to be such that this field is written last.
33295 /***********************************
33296 * hwrm_cfa_flow_aging_timer_reset *
33297 ***********************************/
33300 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
33301 struct hwrm_cfa_flow_aging_timer_reset_input {
33302 /* The HWRM command request type. */
33305 * The completion ring to send the completion event on. This should
33306 * be the NQ ID returned from the `nq_alloc` HWRM command.
33308 uint16_t cmpl_ring;
33310 * The sequence ID is used by the driver for tracking multiple
33311 * commands. This ID is treated as opaque data by the firmware and
33312 * the value is returned in the `hwrm_resp_hdr` upon completion.
33316 * The target ID of the command:
33317 * * 0x0-0xFFF8 - The function ID
33318 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33319 * * 0xFFFD - Reserved for user-space HWRM interface
33322 uint16_t target_id;
33324 * A physical address pointer pointing to a host buffer that the
33325 * command's response data will be written. This can be either a host
33326 * physical address (HPA) or a guest physical address (GPA) and must
33327 * point to a physically contiguous block of memory.
33329 uint64_t resp_addr;
33330 /* Flow record index. */
33331 uint16_t flow_handle;
33332 uint8_t unused_0[2];
33334 * New flow timer value for the flow specified in the ext_flow_handle.
33335 * The flow timer unit is 100ms.
33337 uint32_t flow_timer;
33338 /* This value identifies a set of CFA data structures used for a flow. */
33339 uint64_t ext_flow_handle;
33342 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
33343 struct hwrm_cfa_flow_aging_timer_reset_output {
33344 /* The specific error status for the command. */
33345 uint16_t error_code;
33346 /* The HWRM command request type. */
33348 /* The sequence ID from the original command. */
33350 /* The length of the response data in number of bytes. */
33352 uint8_t unused_0[7];
33354 * This field is used in Output records to indicate that the output
33355 * is completely written to RAM. This field should be read as '1'
33356 * to indicate that the output has been completely written.
33357 * When writing a command completion or response to an internal processor,
33358 * the order of writes has to be such that this field is written last.
33363 /***************************
33364 * hwrm_cfa_flow_aging_cfg *
33365 ***************************/
33368 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
33369 struct hwrm_cfa_flow_aging_cfg_input {
33370 /* The HWRM command request type. */
33373 * The completion ring to send the completion event on. This should
33374 * be the NQ ID returned from the `nq_alloc` HWRM command.
33376 uint16_t cmpl_ring;
33378 * The sequence ID is used by the driver for tracking multiple
33379 * commands. This ID is treated as opaque data by the firmware and
33380 * the value is returned in the `hwrm_resp_hdr` upon completion.
33384 * The target ID of the command:
33385 * * 0x0-0xFFF8 - The function ID
33386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33387 * * 0xFFFD - Reserved for user-space HWRM interface
33390 uint16_t target_id;
33392 * A physical address pointer pointing to a host buffer that the
33393 * command's response data will be written. This can be either a host
33394 * physical address (HPA) or a guest physical address (GPA) and must
33395 * point to a physically contiguous block of memory.
33397 uint64_t resp_addr;
33398 /* The bit field to enable per flow aging configuration. */
33400 /* This bit must be '1' for the tcp flow timer field to be configured */
33401 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
33403 /* This bit must be '1' for the tcp finish timer field to be configured */
33404 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
33406 /* This bit must be '1' for the udp flow timer field to be configured */
33407 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
33409 /* This bit must be '1' for the eem dma interval field to be configured */
33410 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
33412 /* This bit must be '1' for the eem notice interval field to be configured */
33413 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
33415 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
33416 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
33418 /* This bit must be '1' for the eem context memory ID field to be configured */
33419 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
33421 /* This bit must be '1' for the eem context memory type field to be configured */
33422 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
33425 /* Enumeration denoting the RX, TX type of the resource. */
33426 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33428 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
33430 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
33431 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
33432 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
33433 /* Enumeration denoting the enable, disable eem flow aging configuration. */
33434 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
33436 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
33437 (UINT32_C(0x0) << 1)
33439 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
33440 (UINT32_C(0x1) << 1)
33441 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
33442 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
33444 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
33445 uint32_t tcp_flow_timer;
33446 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
33447 uint32_t tcp_fin_timer;
33448 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
33449 uint32_t udp_flow_timer;
33450 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
33451 uint16_t eem_dma_interval;
33452 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
33453 uint16_t eem_notice_interval;
33454 /* The maximum entries number in the eem context memory. */
33455 uint32_t eem_ctx_max_entries;
33456 /* The context memory ID for eem flow aging. */
33457 uint16_t eem_ctx_id;
33458 uint16_t eem_ctx_mem_type;
33459 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
33460 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
33462 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
33463 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
33464 uint8_t unused_1[4];
33467 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
33468 struct hwrm_cfa_flow_aging_cfg_output {
33469 /* The specific error status for the command. */
33470 uint16_t error_code;
33471 /* The HWRM command request type. */
33473 /* The sequence ID from the original command. */
33475 /* The length of the response data in number of bytes. */
33477 uint8_t unused_0[7];
33479 * This field is used in Output records to indicate that the output
33480 * is completely written to RAM. This field should be read as '1'
33481 * to indicate that the output has been completely written.
33482 * When writing a command completion or response to an internal processor,
33483 * the order of writes has to be such that this field is written last.
33488 /****************************
33489 * hwrm_cfa_flow_aging_qcfg *
33490 ****************************/
33493 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
33494 struct hwrm_cfa_flow_aging_qcfg_input {
33495 /* The HWRM command request type. */
33498 * The completion ring to send the completion event on. This should
33499 * be the NQ ID returned from the `nq_alloc` HWRM command.
33501 uint16_t cmpl_ring;
33503 * The sequence ID is used by the driver for tracking multiple
33504 * commands. This ID is treated as opaque data by the firmware and
33505 * the value is returned in the `hwrm_resp_hdr` upon completion.
33509 * The target ID of the command:
33510 * * 0x0-0xFFF8 - The function ID
33511 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33512 * * 0xFFFD - Reserved for user-space HWRM interface
33515 uint16_t target_id;
33517 * A physical address pointer pointing to a host buffer that the
33518 * command's response data will be written. This can be either a host
33519 * physical address (HPA) or a guest physical address (GPA) and must
33520 * point to a physically contiguous block of memory.
33522 uint64_t resp_addr;
33523 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
33525 /* Enumeration denoting the RX, TX type of the resource. */
33526 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33528 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
33530 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
33531 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
33532 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
33533 uint8_t unused_0[7];
33536 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
33537 struct hwrm_cfa_flow_aging_qcfg_output {
33538 /* The specific error status for the command. */
33539 uint16_t error_code;
33540 /* The HWRM command request type. */
33542 /* The sequence ID from the original command. */
33544 /* The length of the response data in number of bytes. */
33546 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
33547 uint32_t tcp_flow_timer;
33548 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
33549 uint32_t tcp_fin_timer;
33550 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
33551 uint32_t udp_flow_timer;
33552 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
33553 uint16_t eem_dma_interval;
33554 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
33555 uint16_t eem_notice_interval;
33556 /* The maximum entries number in the eem context memory. */
33557 uint32_t eem_ctx_max_entries;
33558 /* The context memory ID for eem flow aging. */
33559 uint16_t eem_ctx_id;
33560 /* The context memory type for eem flow aging. */
33561 uint16_t eem_ctx_mem_type;
33562 uint8_t unused_0[7];
33564 * This field is used in Output records to indicate that the output
33565 * is completely written to RAM. This field should be read as '1'
33566 * to indicate that the output has been completely written.
33567 * When writing a command completion or response to an internal processor,
33568 * the order of writes has to be such that this field is written last.
33573 /*****************************
33574 * hwrm_cfa_flow_aging_qcaps *
33575 *****************************/
33578 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
33579 struct hwrm_cfa_flow_aging_qcaps_input {
33580 /* The HWRM command request type. */
33583 * The completion ring to send the completion event on. This should
33584 * be the NQ ID returned from the `nq_alloc` HWRM command.
33586 uint16_t cmpl_ring;
33588 * The sequence ID is used by the driver for tracking multiple
33589 * commands. This ID is treated as opaque data by the firmware and
33590 * the value is returned in the `hwrm_resp_hdr` upon completion.
33594 * The target ID of the command:
33595 * * 0x0-0xFFF8 - The function ID
33596 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33597 * * 0xFFFD - Reserved for user-space HWRM interface
33600 uint16_t target_id;
33602 * A physical address pointer pointing to a host buffer that the
33603 * command's response data will be written. This can be either a host
33604 * physical address (HPA) or a guest physical address (GPA) and must
33605 * point to a physically contiguous block of memory.
33607 uint64_t resp_addr;
33608 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
33610 /* Enumeration denoting the RX, TX type of the resource. */
33611 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
33613 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
33615 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
33616 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
33617 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
33618 uint8_t unused_0[7];
33621 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
33622 struct hwrm_cfa_flow_aging_qcaps_output {
33623 /* The specific error status for the command. */
33624 uint16_t error_code;
33625 /* The HWRM command request type. */
33627 /* The sequence ID from the original command. */
33629 /* The length of the response data in number of bytes. */
33631 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
33632 uint32_t max_tcp_flow_timer;
33633 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
33634 uint32_t max_tcp_fin_timer;
33635 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
33636 uint32_t max_udp_flow_timer;
33637 /* The maximum aging flows that HW can support. */
33638 uint32_t max_aging_flows;
33639 uint8_t unused_0[7];
33641 * This field is used in Output records to indicate that the output
33642 * is completely written to RAM. This field should be read as '1'
33643 * to indicate that the output has been completely written.
33644 * When writing a command completion or response to an internal processor,
33645 * the order of writes has to be such that this field is written last.
33650 /**********************************
33651 * hwrm_cfa_tcp_flag_process_qcfg *
33652 **********************************/
33655 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
33656 struct hwrm_cfa_tcp_flag_process_qcfg_input {
33657 /* The HWRM command request type. */
33660 * The completion ring to send the completion event on. This should
33661 * be the NQ ID returned from the `nq_alloc` HWRM command.
33663 uint16_t cmpl_ring;
33665 * The sequence ID is used by the driver for tracking multiple
33666 * commands. This ID is treated as opaque data by the firmware and
33667 * the value is returned in the `hwrm_resp_hdr` upon completion.
33671 * The target ID of the command:
33672 * * 0x0-0xFFF8 - The function ID
33673 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33674 * * 0xFFFD - Reserved for user-space HWRM interface
33677 uint16_t target_id;
33679 * A physical address pointer pointing to a host buffer that the
33680 * command's response data will be written. This can be either a host
33681 * physical address (HPA) or a guest physical address (GPA) and must
33682 * point to a physically contiguous block of memory.
33684 uint64_t resp_addr;
33687 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
33688 struct hwrm_cfa_tcp_flag_process_qcfg_output {
33689 /* The specific error status for the command. */
33690 uint16_t error_code;
33691 /* The HWRM command request type. */
33693 /* The sequence ID from the original command. */
33695 /* The length of the response data in number of bytes. */
33697 /* The port 0 RX mirror action record ID. */
33698 uint16_t rx_ar_id_port0;
33699 /* The port 1 RX mirror action record ID. */
33700 uint16_t rx_ar_id_port1;
33701 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
33702 uint16_t tx_ar_id_port0;
33703 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
33704 uint16_t tx_ar_id_port1;
33705 uint8_t unused_0[7];
33707 * This field is used in Output records to indicate that the output
33708 * is completely written to RAM. This field should be read as '1'
33709 * to indicate that the output has been completely written.
33710 * When writing a command completion or response to an internal processor,
33711 * the order of writes has to be such that this field is written last.
33716 /**********************
33717 * hwrm_cfa_pair_info *
33718 **********************/
33721 /* hwrm_cfa_pair_info_input (size:448b/56B) */
33722 struct hwrm_cfa_pair_info_input {
33723 /* The HWRM command request type. */
33726 * The completion ring to send the completion event on. This should
33727 * be the NQ ID returned from the `nq_alloc` HWRM command.
33729 uint16_t cmpl_ring;
33731 * The sequence ID is used by the driver for tracking multiple
33732 * commands. This ID is treated as opaque data by the firmware and
33733 * the value is returned in the `hwrm_resp_hdr` upon completion.
33737 * The target ID of the command:
33738 * * 0x0-0xFFF8 - The function ID
33739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33740 * * 0xFFFD - Reserved for user-space HWRM interface
33743 uint16_t target_id;
33745 * A physical address pointer pointing to a host buffer that the
33746 * command's response data will be written. This can be either a host
33747 * physical address (HPA) or a guest physical address (GPA) and must
33748 * point to a physically contiguous block of memory.
33750 uint64_t resp_addr;
33752 /* If this flag is set, lookup by name else lookup by index. */
33753 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
33754 /* If this flag is set, lookup by PF id and VF id. */
33755 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
33756 /* Pair table index. */
33757 uint16_t pair_index;
33758 /* Pair pf index. */
33760 /* Pair vf index. */
33762 /* Pair name (32 byte string). */
33763 char pair_name[32];
33766 /* hwrm_cfa_pair_info_output (size:576b/72B) */
33767 struct hwrm_cfa_pair_info_output {
33768 /* The specific error status for the command. */
33769 uint16_t error_code;
33770 /* The HWRM command request type. */
33772 /* The sequence ID from the original command. */
33774 /* The length of the response data in number of bytes. */
33776 /* Pair table index. */
33777 uint16_t next_pair_index;
33778 /* Pair member a's fid. */
33780 /* Logical host number. */
33781 uint8_t host_a_index;
33782 /* Logical PF number. */
33783 uint8_t pf_a_index;
33784 /* Pair member a's Linux logical VF number. */
33785 uint16_t vf_a_index;
33787 uint16_t rx_cfa_code_a;
33788 /* Tx CFA action. */
33789 uint16_t tx_cfa_action_a;
33790 /* Pair member b's fid. */
33792 /* Logical host number. */
33793 uint8_t host_b_index;
33794 /* Logical PF number. */
33795 uint8_t pf_b_index;
33796 /* Pair member a's Linux logical VF number. */
33797 uint16_t vf_b_index;
33799 uint16_t rx_cfa_code_b;
33800 /* Tx CFA action. */
33801 uint16_t tx_cfa_action_b;
33802 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
33804 /* Pair between VF on local host with PF or VF on specified host. */
33805 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
33806 /* Pair between REP on local host with PF or VF on specified host. */
33807 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
33808 /* Pair between REP on local host with REP on specified host. */
33809 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
33810 /* Pair for the proxy interface. */
33811 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
33812 /* Pair for the PF interface. */
33813 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
33814 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
33815 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
33817 uint8_t pair_state;
33818 /* Pair has been allocated */
33819 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
33820 /* Both pair members are active */
33821 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
33822 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
33823 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
33824 /* Pair name (32 byte string). */
33825 char pair_name[32];
33826 uint8_t unused_0[7];
33828 * This field is used in Output records to indicate that the output
33829 * is completely written to RAM. This field should be read as '1'
33830 * to indicate that the output has been completely written.
33831 * When writing a command completion or response to an internal processor,
33832 * the order of writes has to be such that this field is written last.
33837 /***************************************
33838 * hwrm_cfa_redirect_query_tunnel_type *
33839 ***************************************/
33842 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
33843 struct hwrm_cfa_redirect_query_tunnel_type_input {
33844 /* The HWRM command request type. */
33847 * The completion ring to send the completion event on. This should
33848 * be the NQ ID returned from the `nq_alloc` HWRM command.
33850 uint16_t cmpl_ring;
33852 * The sequence ID is used by the driver for tracking multiple
33853 * commands. This ID is treated as opaque data by the firmware and
33854 * the value is returned in the `hwrm_resp_hdr` upon completion.
33858 * The target ID of the command:
33859 * * 0x0-0xFFF8 - The function ID
33860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33861 * * 0xFFFD - Reserved for user-space HWRM interface
33864 uint16_t target_id;
33866 * A physical address pointer pointing to a host buffer that the
33867 * command's response data will be written. This can be either a host
33868 * physical address (HPA) or a guest physical address (GPA) and must
33869 * point to a physically contiguous block of memory.
33871 uint64_t resp_addr;
33872 /* The source function id. */
33874 uint8_t unused_0[6];
33877 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
33878 struct hwrm_cfa_redirect_query_tunnel_type_output {
33879 /* The specific error status for the command. */
33880 uint16_t error_code;
33881 /* The HWRM command request type. */
33883 /* The sequence ID from the original command. */
33885 /* The length of the response data in number of bytes. */
33888 uint32_t tunnel_mask;
33890 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
33892 /* Virtual eXtensible Local Area Network (VXLAN) */
33893 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
33895 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33896 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
33898 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33899 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
33902 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
33904 /* Generic Network Virtualization Encapsulation (Geneve) */
33905 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
33907 /* Multi-Protocol Label Switching (MPLS) */
33908 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
33910 /* Stateless Transport Tunnel (STT) */
33911 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
33913 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33914 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
33916 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33917 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
33919 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33920 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
33922 /* Any tunneled traffic */
33923 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
33925 /* Use fixed layer 2 ether type of 0xFFFF */
33926 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
33928 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33929 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
33931 uint8_t unused_0[3];
33933 * This field is used in Output records to indicate that the output
33934 * is completely written to RAM. This field should be read as '1'
33935 * to indicate that the output has been completely written.
33936 * When writing a command completion or response to an internal processor,
33937 * the order of writes has to be such that this field is written last.
33942 /*************************
33943 * hwrm_cfa_ctx_mem_rgtr *
33944 *************************/
33947 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
33948 struct hwrm_cfa_ctx_mem_rgtr_input {
33949 /* The HWRM command request type. */
33952 * The completion ring to send the completion event on. This should
33953 * be the NQ ID returned from the `nq_alloc` HWRM command.
33955 uint16_t cmpl_ring;
33957 * The sequence ID is used by the driver for tracking multiple
33958 * commands. This ID is treated as opaque data by the firmware and
33959 * the value is returned in the `hwrm_resp_hdr` upon completion.
33963 * The target ID of the command:
33964 * * 0x0-0xFFF8 - The function ID
33965 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33966 * * 0xFFFD - Reserved for user-space HWRM interface
33969 uint16_t target_id;
33971 * A physical address pointer pointing to a host buffer that the
33972 * command's response data will be written. This can be either a host
33973 * physical address (HPA) or a guest physical address (GPA) and must
33974 * point to a physically contiguous block of memory.
33976 uint64_t resp_addr;
33978 /* Counter PBL indirect levels. */
33979 uint8_t page_level;
33980 /* PBL pointer is physical start address. */
33981 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
33982 /* PBL pointer points to PTE table. */
33983 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
33984 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
33985 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
33986 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
33987 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
33990 /* 4KB page size. */
33991 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
33992 /* 8KB page size. */
33993 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
33994 /* 64KB page size. */
33995 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
33996 /* 256KB page size. */
33997 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
33998 /* 1MB page size. */
33999 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
34000 /* 2MB page size. */
34001 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
34002 /* 4MB page size. */
34003 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
34004 /* 1GB page size. */
34005 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
34006 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
34007 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
34009 /* Pointer to the PBL, or PDL depending on number of levels */
34013 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
34014 struct hwrm_cfa_ctx_mem_rgtr_output {
34015 /* The specific error status for the command. */
34016 uint16_t error_code;
34017 /* The HWRM command request type. */
34019 /* The sequence ID from the original command. */
34021 /* The length of the response data in number of bytes. */
34024 * Id/Handle to the recently register context memory. This handle is passed
34025 * to the CFA feature.
34028 uint8_t unused_0[5];
34030 * This field is used in Output records to indicate that the output
34031 * is completely written to RAM. This field should be read as '1'
34032 * to indicate that the output has been completely written.
34033 * When writing a command completion or response to an internal processor,
34034 * the order of writes has to be such that this field is written last.
34039 /***************************
34040 * hwrm_cfa_ctx_mem_unrgtr *
34041 ***************************/
34044 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
34045 struct hwrm_cfa_ctx_mem_unrgtr_input {
34046 /* The HWRM command request type. */
34049 * The completion ring to send the completion event on. This should
34050 * be the NQ ID returned from the `nq_alloc` HWRM command.
34052 uint16_t cmpl_ring;
34054 * The sequence ID is used by the driver for tracking multiple
34055 * commands. This ID is treated as opaque data by the firmware and
34056 * the value is returned in the `hwrm_resp_hdr` upon completion.
34060 * The target ID of the command:
34061 * * 0x0-0xFFF8 - The function ID
34062 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34063 * * 0xFFFD - Reserved for user-space HWRM interface
34066 uint16_t target_id;
34068 * A physical address pointer pointing to a host buffer that the
34069 * command's response data will be written. This can be either a host
34070 * physical address (HPA) or a guest physical address (GPA) and must
34071 * point to a physically contiguous block of memory.
34073 uint64_t resp_addr;
34075 * Id/Handle to the recently register context memory. This handle is passed
34076 * to the CFA feature.
34079 uint8_t unused_0[6];
34082 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
34083 struct hwrm_cfa_ctx_mem_unrgtr_output {
34084 /* The specific error status for the command. */
34085 uint16_t error_code;
34086 /* The HWRM command request type. */
34088 /* The sequence ID from the original command. */
34090 /* The length of the response data in number of bytes. */
34092 uint8_t unused_0[7];
34094 * This field is used in Output records to indicate that the output
34095 * is completely written to RAM. This field should be read as '1'
34096 * to indicate that the output has been completely written.
34097 * When writing a command completion or response to an internal processor,
34098 * the order of writes has to be such that this field is written last.
34103 /*************************
34104 * hwrm_cfa_ctx_mem_qctx *
34105 *************************/
34108 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
34109 struct hwrm_cfa_ctx_mem_qctx_input {
34110 /* The HWRM command request type. */
34113 * The completion ring to send the completion event on. This should
34114 * be the NQ ID returned from the `nq_alloc` HWRM command.
34116 uint16_t cmpl_ring;
34118 * The sequence ID is used by the driver for tracking multiple
34119 * commands. This ID is treated as opaque data by the firmware and
34120 * the value is returned in the `hwrm_resp_hdr` upon completion.
34124 * The target ID of the command:
34125 * * 0x0-0xFFF8 - The function ID
34126 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34127 * * 0xFFFD - Reserved for user-space HWRM interface
34130 uint16_t target_id;
34132 * A physical address pointer pointing to a host buffer that the
34133 * command's response data will be written. This can be either a host
34134 * physical address (HPA) or a guest physical address (GPA) and must
34135 * point to a physically contiguous block of memory.
34137 uint64_t resp_addr;
34139 * Id/Handle to the recently register context memory. This handle is passed
34140 * to the CFA feature.
34143 uint8_t unused_0[6];
34146 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
34147 struct hwrm_cfa_ctx_mem_qctx_output {
34148 /* The specific error status for the command. */
34149 uint16_t error_code;
34150 /* The HWRM command request type. */
34152 /* The sequence ID from the original command. */
34154 /* The length of the response data in number of bytes. */
34157 /* Counter PBL indirect levels. */
34158 uint8_t page_level;
34159 /* PBL pointer is physical start address. */
34160 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
34161 /* PBL pointer points to PTE table. */
34162 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
34163 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
34164 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
34165 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
34166 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
34169 /* 4KB page size. */
34170 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
34171 /* 8KB page size. */
34172 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
34173 /* 64KB page size. */
34174 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
34175 /* 256KB page size. */
34176 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
34177 /* 1MB page size. */
34178 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
34179 /* 2MB page size. */
34180 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
34181 /* 4MB page size. */
34182 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
34183 /* 1GB page size. */
34184 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
34185 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
34186 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
34187 uint8_t unused_0[4];
34188 /* Pointer to the PBL, or PDL depending on number of levels */
34190 uint8_t unused_1[7];
34192 * This field is used in Output records to indicate that the output
34193 * is completely written to RAM. This field should be read as '1'
34194 * to indicate that the output has been completely written.
34195 * When writing a command completion or response to an internal processor,
34196 * the order of writes has to be such that this field is written last.
34201 /**************************
34202 * hwrm_cfa_ctx_mem_qcaps *
34203 **************************/
34206 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
34207 struct hwrm_cfa_ctx_mem_qcaps_input {
34208 /* The HWRM command request type. */
34211 * The completion ring to send the completion event on. This should
34212 * be the NQ ID returned from the `nq_alloc` HWRM command.
34214 uint16_t cmpl_ring;
34216 * The sequence ID is used by the driver for tracking multiple
34217 * commands. This ID is treated as opaque data by the firmware and
34218 * the value is returned in the `hwrm_resp_hdr` upon completion.
34222 * The target ID of the command:
34223 * * 0x0-0xFFF8 - The function ID
34224 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34225 * * 0xFFFD - Reserved for user-space HWRM interface
34228 uint16_t target_id;
34230 * A physical address pointer pointing to a host buffer that the
34231 * command's response data will be written. This can be either a host
34232 * physical address (HPA) or a guest physical address (GPA) and must
34233 * point to a physically contiguous block of memory.
34235 uint64_t resp_addr;
34238 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
34239 struct hwrm_cfa_ctx_mem_qcaps_output {
34240 /* The specific error status for the command. */
34241 uint16_t error_code;
34242 /* The HWRM command request type. */
34244 /* The sequence ID from the original command. */
34246 /* The length of the response data in number of bytes. */
34248 /* Indicates the maximum number of context memory which can be registered. */
34249 uint16_t max_entries;
34250 uint8_t unused_0[5];
34252 * This field is used in Output records to indicate that the output
34253 * is completely written to RAM. This field should be read as '1'
34254 * to indicate that the output has been completely written.
34255 * When writing a command completion or response to an internal processor,
34256 * the order of writes has to be such that this field is written last.
34261 /**********************
34262 * hwrm_cfa_eem_qcaps *
34263 **********************/
34266 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
34267 struct hwrm_cfa_eem_qcaps_input {
34268 /* The HWRM command request type. */
34271 * The completion ring to send the completion event on. This should
34272 * be the NQ ID returned from the `nq_alloc` HWRM command.
34274 uint16_t cmpl_ring;
34276 * The sequence ID is used by the driver for tracking multiple
34277 * commands. This ID is treated as opaque data by the firmware and
34278 * the value is returned in the `hwrm_resp_hdr` upon completion.
34282 * The target ID of the command:
34283 * * 0x0-0xFFF8 - The function ID
34284 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34285 * * 0xFFFD - Reserved for user-space HWRM interface
34288 uint16_t target_id;
34290 * A physical address pointer pointing to a host buffer that the
34291 * command's response data will be written. This can be either a host
34292 * physical address (HPA) or a guest physical address (GPA) and must
34293 * point to a physically contiguous block of memory.
34295 uint64_t resp_addr;
34298 * When set to 1, indicates the configuration will apply to TX flows
34299 * which are to be offloaded.
34300 * Note if this bit is set then the path_rx bit can't be set.
34302 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
34305 * When set to 1, indicates the configuration will apply to RX flows
34306 * which are to be offloaded.
34307 * Note if this bit is set then the path_tx bit can't be set.
34309 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
34311 /* When set to 1, all offloaded flows will be sent to EEM. */
34312 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
34317 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
34318 struct hwrm_cfa_eem_qcaps_output {
34319 /* The specific error status for the command. */
34320 uint16_t error_code;
34321 /* The HWRM command request type. */
34323 /* The sequence ID from the original command. */
34325 /* The length of the response data in number of bytes. */
34329 * When set to 1, indicates the configuration will apply to TX flows
34330 * which are to be offloaded.
34331 * Note if this bit is set then the path_rx bit can't be set.
34333 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
34336 * When set to 1, indicates the configuration will apply to RX flows
34337 * which are to be offloaded.
34338 * Note if this bit is set then the path_tx bit can't be set.
34340 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
34343 * When set to 1, indicates the the FW supports the Centralized
34344 * Memory Model. The concept designates one entity for the
34345 * memory allocation while all others ‘subscribe’ to it.
34347 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
34350 * When set to 1, indicates the the FW supports the Detached
34351 * Centralized Memory Model. The memory is allocated and managed
34352 * as a separate entity. All PFs and VFs will be granted direct
34353 * or semi-direct access to the allocated memory while none of
34354 * which can interfere with the management of the memory.
34356 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
34359 uint32_t supported;
34361 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
34362 * If set to 0, EEM KEY0 table is not supported.
34364 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
34367 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
34368 * If set to 0, EEM KEY1 table is not supported.
34370 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
34373 * If set to 1, then EEM External Record table is supported.
34374 * If set to 0, EEM External Record table is not supported.
34375 * (This table includes action record, EFC pointers, encap pointers)
34377 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
34380 * If set to 1, then EEM External Flow Counters table is supported.
34381 * If set to 0, EEM External Flow Counters table is not supported.
34383 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
34386 * If set to 1, then FID table used for implicit flow flush is supported.
34387 * If set to 0, then FID table used for implicit flow flush is not supported.
34389 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
34392 * The maximum number of entries supported by EEM. When configuring the host memory
34393 * the number of numbers of entries that can supported are -
34394 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
34395 * Any value that are not these values, the FW will round down to the closest support
34396 * number of entries.
34398 uint32_t max_entries_supported;
34399 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
34400 uint16_t key_entry_size;
34401 /* The entry size in bytes of each entry in the EEM RECORD tables. */
34402 uint16_t record_entry_size;
34403 /* The entry size in bytes of each entry in the EEM EFC tables. */
34404 uint16_t efc_entry_size;
34405 /* The FID size in bytes of each entry in the EEM FID tables. */
34406 uint16_t fid_entry_size;
34407 uint8_t unused_1[7];
34409 * This field is used in Output records to indicate that the output
34410 * is completely written to RAM. This field should be read as '1'
34411 * to indicate that the output has been completely written.
34412 * When writing a command completion or response to an internal processor,
34413 * the order of writes has to be such that this field is written last.
34418 /********************
34419 * hwrm_cfa_eem_cfg *
34420 ********************/
34423 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
34424 struct hwrm_cfa_eem_cfg_input {
34425 /* The HWRM command request type. */
34428 * The completion ring to send the completion event on. This should
34429 * be the NQ ID returned from the `nq_alloc` HWRM command.
34431 uint16_t cmpl_ring;
34433 * The sequence ID is used by the driver for tracking multiple
34434 * commands. This ID is treated as opaque data by the firmware and
34435 * the value is returned in the `hwrm_resp_hdr` upon completion.
34439 * The target ID of the command:
34440 * * 0x0-0xFFF8 - The function ID
34441 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34442 * * 0xFFFD - Reserved for user-space HWRM interface
34445 uint16_t target_id;
34447 * A physical address pointer pointing to a host buffer that the
34448 * command's response data will be written. This can be either a host
34449 * physical address (HPA) or a guest physical address (GPA) and must
34450 * point to a physically contiguous block of memory.
34452 uint64_t resp_addr;
34455 * When set to 1, indicates the configuration will apply to TX flows
34456 * which are to be offloaded.
34457 * Note if this bit is set then the path_rx bit can't be set.
34459 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
34462 * When set to 1, indicates the configuration will apply to RX flows
34463 * which are to be offloaded.
34464 * Note if this bit is set then the path_tx bit can't be set.
34466 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
34468 /* When set to 1, all offloaded flows will be sent to EEM. */
34469 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
34471 /* When set to 1, secondary, 0 means primary. */
34472 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
34475 * Group_id which used by Firmware to identify memory pools belonging
34476 * to certain group.
34481 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
34482 * RECORD, EFC all have the same number of entries and all tables will be configured
34483 * using this value. Current minimum value is 32k. Current maximum value is 128M.
34485 uint32_t num_entries;
34487 /* Configured EEM with the given context if for KEY0 table. */
34488 uint16_t key0_ctx_id;
34489 /* Configured EEM with the given context if for KEY1 table. */
34490 uint16_t key1_ctx_id;
34491 /* Configured EEM with the given context if for RECORD table. */
34492 uint16_t record_ctx_id;
34493 /* Configured EEM with the given context if for EFC table. */
34494 uint16_t efc_ctx_id;
34495 /* Configured EEM with the given context if for EFC table. */
34496 uint16_t fid_ctx_id;
34501 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
34502 struct hwrm_cfa_eem_cfg_output {
34503 /* The specific error status for the command. */
34504 uint16_t error_code;
34505 /* The HWRM command request type. */
34507 /* The sequence ID from the original command. */
34509 /* The length of the response data in number of bytes. */
34511 uint8_t unused_0[7];
34513 * This field is used in Output records to indicate that the output
34514 * is completely written to RAM. This field should be read as '1'
34515 * to indicate that the output has been completely written.
34516 * When writing a command completion or response to an internal processor,
34517 * the order of writes has to be such that this field is written last.
34522 /*********************
34523 * hwrm_cfa_eem_qcfg *
34524 *********************/
34527 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
34528 struct hwrm_cfa_eem_qcfg_input {
34529 /* The HWRM command request type. */
34532 * The completion ring to send the completion event on. This should
34533 * be the NQ ID returned from the `nq_alloc` HWRM command.
34535 uint16_t cmpl_ring;
34537 * The sequence ID is used by the driver for tracking multiple
34538 * commands. This ID is treated as opaque data by the firmware and
34539 * the value is returned in the `hwrm_resp_hdr` upon completion.
34543 * The target ID of the command:
34544 * * 0x0-0xFFF8 - The function ID
34545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34546 * * 0xFFFD - Reserved for user-space HWRM interface
34549 uint16_t target_id;
34551 * A physical address pointer pointing to a host buffer that the
34552 * command's response data will be written. This can be either a host
34553 * physical address (HPA) or a guest physical address (GPA) and must
34554 * point to a physically contiguous block of memory.
34556 uint64_t resp_addr;
34558 /* When set to 1, indicates the configuration is the TX flow. */
34559 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
34560 /* When set to 1, indicates the configuration is the RX flow. */
34561 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
34565 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
34566 struct hwrm_cfa_eem_qcfg_output {
34567 /* The specific error status for the command. */
34568 uint16_t error_code;
34569 /* The HWRM command request type. */
34571 /* The sequence ID from the original command. */
34573 /* The length of the response data in number of bytes. */
34576 /* When set to 1, indicates the configuration is the TX flow. */
34577 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
34579 /* When set to 1, indicates the configuration is the RX flow. */
34580 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
34582 /* When set to 1, all offloaded flows will be sent to EEM. */
34583 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
34585 /* The number of entries the FW has configured for EEM. */
34586 uint32_t num_entries;
34587 /* Configured EEM with the given context if for KEY0 table. */
34588 uint16_t key0_ctx_id;
34589 /* Configured EEM with the given context if for KEY1 table. */
34590 uint16_t key1_ctx_id;
34591 /* Configured EEM with the given context if for RECORD table. */
34592 uint16_t record_ctx_id;
34593 /* Configured EEM with the given context if for EFC table. */
34594 uint16_t efc_ctx_id;
34595 /* Configured EEM with the given context if for EFC table. */
34596 uint16_t fid_ctx_id;
34597 uint8_t unused_2[5];
34599 * This field is used in Output records to indicate that the output
34600 * is completely written to RAM. This field should be read as '1'
34601 * to indicate that the output has been completely written.
34602 * When writing a command completion or response to an internal processor,
34603 * the order of writes has to be such that this field is written last.
34608 /*******************
34609 * hwrm_cfa_eem_op *
34610 *******************/
34613 /* hwrm_cfa_eem_op_input (size:192b/24B) */
34614 struct hwrm_cfa_eem_op_input {
34615 /* The HWRM command request type. */
34618 * The completion ring to send the completion event on. This should
34619 * be the NQ ID returned from the `nq_alloc` HWRM command.
34621 uint16_t cmpl_ring;
34623 * The sequence ID is used by the driver for tracking multiple
34624 * commands. This ID is treated as opaque data by the firmware and
34625 * the value is returned in the `hwrm_resp_hdr` upon completion.
34629 * The target ID of the command:
34630 * * 0x0-0xFFF8 - The function ID
34631 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34632 * * 0xFFFD - Reserved for user-space HWRM interface
34635 uint16_t target_id;
34637 * A physical address pointer pointing to a host buffer that the
34638 * command's response data will be written. This can be either a host
34639 * physical address (HPA) or a guest physical address (GPA) and must
34640 * point to a physically contiguous block of memory.
34642 uint64_t resp_addr;
34645 * When set to 1, indicates the host memory which is passed will be
34646 * used for the TX flow offload function specified in fid.
34647 * Note if this bit is set then the path_rx bit can't be set.
34649 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
34651 * When set to 1, indicates the host memory which is passed will be
34652 * used for the RX flow offload function specified in fid.
34653 * Note if this bit is set then the path_tx bit can't be set.
34655 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
34657 /* The number of EEM key table entries to be configured. */
34659 /* This value is reserved and should not be used. */
34660 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
34662 * To properly stop EEM and ensure there are no DMA's, the caller
34663 * must disable EEM for the given PF, using this call. This will
34664 * safely disable EEM and ensure that all DMA'ed to the
34665 * keys/records/efc have been completed.
34667 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
34669 * Once the EEM host memory has been configured, EEM options have
34670 * been configured. Then the caller should enable EEM for the given
34671 * PF. Note once this call has been made, then the EEM mechanism
34672 * will be active and DMA's will occur as packets are processed.
34674 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
34676 * Clear EEM settings for the given PF so that the register values
34677 * are reset back to there initial state.
34679 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
34680 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
34681 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
34684 /* hwrm_cfa_eem_op_output (size:128b/16B) */
34685 struct hwrm_cfa_eem_op_output {
34686 /* The specific error status for the command. */
34687 uint16_t error_code;
34688 /* The HWRM command request type. */
34690 /* The sequence ID from the original command. */
34692 /* The length of the response data in number of bytes. */
34694 uint8_t unused_0[7];
34696 * This field is used in Output records to indicate that the output
34697 * is completely written to RAM. This field should be read as '1'
34698 * to indicate that the output has been completely written.
34699 * When writing a command completion or response to an internal processor,
34700 * the order of writes has to be such that this field is written last.
34705 /********************************
34706 * hwrm_cfa_adv_flow_mgnt_qcaps *
34707 ********************************/
34710 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
34711 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
34712 /* The HWRM command request type. */
34715 * The completion ring to send the completion event on. This should
34716 * be the NQ ID returned from the `nq_alloc` HWRM command.
34718 uint16_t cmpl_ring;
34720 * The sequence ID is used by the driver for tracking multiple
34721 * commands. This ID is treated as opaque data by the firmware and
34722 * the value is returned in the `hwrm_resp_hdr` upon completion.
34726 * The target ID of the command:
34727 * * 0x0-0xFFF8 - The function ID
34728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34729 * * 0xFFFD - Reserved for user-space HWRM interface
34732 uint16_t target_id;
34734 * A physical address pointer pointing to a host buffer that the
34735 * command's response data will be written. This can be either a host
34736 * physical address (HPA) or a guest physical address (GPA) and must
34737 * point to a physically contiguous block of memory.
34739 uint64_t resp_addr;
34740 uint32_t unused_0[4];
34743 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
34744 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
34745 /* The specific error status for the command. */
34746 uint16_t error_code;
34747 /* The HWRM command request type. */
34749 /* The sequence ID from the original command. */
34751 /* The length of the response data in number of bytes. */
34755 * Value of 1 to indicate firmware support 16-bit flow handle.
34756 * Value of 0 to indicate firmware not support 16-bit flow handle.
34758 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
34761 * Value of 1 to indicate firmware support 64-bit flow handle.
34762 * Value of 0 to indicate firmware not support 64-bit flow handle.
34764 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
34767 * Value of 1 to indicate firmware support flow batch delete operation through
34768 * HWRM_CFA_FLOW_FLUSH command.
34769 * Value of 0 to indicate that the firmware does not support flow batch delete
34772 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
34775 * Value of 1 to indicate that the firmware support flow reset all operation through
34776 * HWRM_CFA_FLOW_FLUSH command.
34777 * Value of 0 indicates firmware does not support flow reset all operation.
34779 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
34782 * Value of 1 to indicate that firmware supports use of FID as dest_id in
34783 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
34784 * Value of 0 indicates firmware does not support use of FID as dest_id.
34786 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
34789 * Value of 1 to indicate that firmware supports TX EEM flows.
34790 * Value of 0 indicates firmware does not support TX EEM flows.
34792 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
34795 * Value of 1 to indicate that firmware supports RX EEM flows.
34796 * Value of 0 indicates firmware does not support RX EEM flows.
34798 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
34801 * Value of 1 to indicate that firmware supports the dynamic allocation of an
34802 * on-chip flow counter which can be used for EEM flows.
34803 * Value of 0 indicates firmware does not support the dynamic allocation of an
34804 * on-chip flow counter.
34806 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
34809 * Value of 1 to indicate that firmware supports setting of
34810 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
34811 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
34813 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
34816 * Value of 1 to indicate that firmware supports untagged matching
34817 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
34818 * indicates firmware does not support untagged matching.
34820 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
34823 * Value of 1 to indicate that firmware supports XDP filter. Value
34824 * of 0 indicates firmware does not support XDP filter.
34826 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
34829 * Value of 1 to indicate that the firmware support L2 header source
34830 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
34831 * Value of 0 indicates firmware does not support L2 header source
34834 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
34837 * If set to 1, firmware is capable of supporting ARP ethertype as
34838 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
34839 * RX direction. By default, this flag should be 0 for older version
34842 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
34845 * Value of 1 to indicate that firmware supports setting of
34846 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
34847 * command. Value of 0 indicates firmware does not support
34848 * rfs_ring_tbl_idx in dst_id field.
34850 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
34853 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
34854 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
34855 * direction. By default, this flag should be 0 for older version
34858 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
34860 uint8_t unused_0[3];
34862 * This field is used in Output records to indicate that the output
34863 * is completely written to RAM. This field should be read as '1'
34864 * to indicate that the output has been completely written.
34865 * When writing a command completion or response to an internal processor,
34866 * the order of writes has to be such that this field is written last.
34871 /******************
34873 ******************/
34876 /* hwrm_cfa_tflib_input (size:1024b/128B) */
34877 struct hwrm_cfa_tflib_input {
34878 /* The HWRM command request type. */
34881 * The completion ring to send the completion event on. This should
34882 * be the NQ ID returned from the `nq_alloc` HWRM command.
34884 uint16_t cmpl_ring;
34886 * The sequence ID is used by the driver for tracking multiple
34887 * commands. This ID is treated as opaque data by the firmware and
34888 * the value is returned in the `hwrm_resp_hdr` upon completion.
34892 * The target ID of the command:
34893 * * 0x0-0xFFF8 - The function ID
34894 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34895 * * 0xFFFD - Reserved for user-space HWRM interface
34898 uint16_t target_id;
34900 * A physical address pointer pointing to a host buffer that the
34901 * command's response data will be written. This can be either a host
34902 * physical address (HPA) or a guest physical address (GPA) and must
34903 * point to a physically contiguous block of memory.
34905 uint64_t resp_addr;
34906 /* TFLIB message type. */
34908 /* TFLIB message subtype. */
34909 uint16_t tf_subtype;
34911 uint8_t unused0[4];
34912 /* TFLIB request data. */
34913 uint32_t tf_req[26];
34916 /* hwrm_cfa_tflib_output (size:5632b/704B) */
34917 struct hwrm_cfa_tflib_output {
34918 /* The specific error status for the command. */
34919 uint16_t error_code;
34920 /* The HWRM command request type. */
34922 /* The sequence ID from the original command. */
34924 /* The length of the response data in number of bytes. */
34926 /* TFLIB message type. */
34928 /* TFLIB message subtype. */
34929 uint16_t tf_subtype;
34930 /* TFLIB response code */
34931 uint32_t tf_resp_code;
34932 /* TFLIB response data. */
34933 uint32_t tf_resp[170];
34935 uint8_t unused1[7];
34937 * This field is used in Output records to indicate that the output
34938 * is completely written to RAM. This field should be read as '1'
34939 * to indicate that the output has been completely written.
34940 * When writing a command completion or response to an internal processor,
34941 * the order of writes has to be such that this field is written last.
34951 /* hwrm_tf_input (size:1024b/128B) */
34952 struct hwrm_tf_input {
34953 /* The HWRM command request type. */
34956 * The completion ring to send the completion event on. This should
34957 * be the NQ ID returned from the `nq_alloc` HWRM command.
34959 uint16_t cmpl_ring;
34961 * The sequence ID is used by the driver for tracking multiple
34962 * commands. This ID is treated as opaque data by the firmware and
34963 * the value is returned in the `hwrm_resp_hdr` upon completion.
34967 * The target ID of the command:
34968 * * 0x0-0xFFF8 - The function ID
34969 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34970 * * 0xFFFD - Reserved for user-space HWRM interface
34973 uint16_t target_id;
34975 * A physical address pointer pointing to a host buffer that the
34976 * command's response data will be written. This can be either a host
34977 * physical address (HPA) or a guest physical address (GPA) and must
34978 * point to a physically contiguous block of memory.
34980 uint64_t resp_addr;
34981 /* TF message type. */
34983 /* TF message subtype. */
34986 uint8_t unused0[4];
34987 /* TF request data. */
34991 /* hwrm_tf_output (size:5632b/704B) */
34992 struct hwrm_tf_output {
34993 /* The specific error status for the command. */
34994 uint16_t error_code;
34995 /* The HWRM command request type. */
34997 /* The sequence ID from the original command. */
34999 /* The length of the response data in number of bytes. */
35001 /* TF message type. */
35003 /* TF message subtype. */
35005 /* TF response code */
35006 uint32_t resp_code;
35007 /* TF response data. */
35008 uint32_t resp[170];
35010 uint8_t unused1[7];
35012 * This field is used in Output records to indicate that the
35013 * output is completely written to RAM. This field should be
35014 * read as '1' to indicate that the output has been
35015 * completely written. When writing a command completion or
35016 * response to an internal processor, the order of writes has
35017 * to be such that this field is written last.
35022 /***********************
35023 * hwrm_tf_version_get *
35024 ***********************/
35027 /* hwrm_tf_version_get_input (size:128b/16B) */
35028 struct hwrm_tf_version_get_input {
35029 /* The HWRM command request type. */
35032 * The completion ring to send the completion event on. This should
35033 * be the NQ ID returned from the `nq_alloc` HWRM command.
35035 uint16_t cmpl_ring;
35037 * The sequence ID is used by the driver for tracking multiple
35038 * commands. This ID is treated as opaque data by the firmware and
35039 * the value is returned in the `hwrm_resp_hdr` upon completion.
35043 * The target ID of the command:
35044 * * 0x0-0xFFF8 - The function ID
35045 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35046 * * 0xFFFD - Reserved for user-space HWRM interface
35049 uint16_t target_id;
35051 * A physical address pointer pointing to a host buffer that the
35052 * command's response data will be written. This can be either a host
35053 * physical address (HPA) or a guest physical address (GPA) and must
35054 * point to a physically contiguous block of memory.
35056 uint64_t resp_addr;
35059 /* hwrm_tf_version_get_output (size:128b/16B) */
35060 struct hwrm_tf_version_get_output {
35061 /* The specific error status for the command. */
35062 uint16_t error_code;
35063 /* The HWRM command request type. */
35065 /* The sequence ID from the original command. */
35067 /* The length of the response data in number of bytes. */
35069 /* Version Major number. */
35071 /* Version Minor number. */
35073 /* Version Update number. */
35076 uint8_t unused0[4];
35078 * This field is used in Output records to indicate that the output
35079 * is completely written to RAM. This field should be read as '1'
35080 * to indicate that the output has been completely written.
35081 * When writing a command completion or response to an internal
35082 * processor, the order of writes has to be such that this field is
35088 /************************
35089 * hwrm_tf_session_open *
35090 ************************/
35093 /* hwrm_tf_session_open_input (size:640b/80B) */
35094 struct hwrm_tf_session_open_input {
35095 /* The HWRM command request type. */
35098 * The completion ring to send the completion event on. This should
35099 * be the NQ ID returned from the `nq_alloc` HWRM command.
35101 uint16_t cmpl_ring;
35103 * The sequence ID is used by the driver for tracking multiple
35104 * commands. This ID is treated as opaque data by the firmware and
35105 * the value is returned in the `hwrm_resp_hdr` upon completion.
35109 * The target ID of the command:
35110 * * 0x0-0xFFF8 - The function ID
35111 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35112 * * 0xFFFD - Reserved for user-space HWRM interface
35115 uint16_t target_id;
35117 * A physical address pointer pointing to a host buffer that the
35118 * command's response data will be written. This can be either a host
35119 * physical address (HPA) or a guest physical address (GPA) and must
35120 * point to a physically contiguous block of memory.
35122 uint64_t resp_addr;
35123 /* Name of the session. */
35124 uint8_t session_name[64];
35127 /* hwrm_tf_session_open_output (size:192b/24B) */
35128 struct hwrm_tf_session_open_output {
35129 /* The specific error status for the command. */
35130 uint16_t error_code;
35131 /* The HWRM command request type. */
35133 /* The sequence ID from the original command. */
35135 /* The length of the response data in number of bytes. */
35138 * Unique session identifier for the session created by the
35141 uint32_t fw_session_id;
35143 * Unique session client identifier for the first client on
35144 * the newly created session.
35146 uint32_t fw_session_client_id;
35150 uint8_t unused1[3];
35152 * This field is used in Output records to indicate that the output
35153 * is completely written to RAM. This field should be read as '1'
35154 * to indicate that the output has been completely written.
35155 * When writing a command completion or response to an internal
35156 * processor, the order of writes has to be such that this field is
35162 /**************************
35163 * hwrm_tf_session_attach *
35164 **************************/
35167 /* hwrm_tf_session_attach_input (size:704b/88B) */
35168 struct hwrm_tf_session_attach_input {
35169 /* The HWRM command request type. */
35172 * The completion ring to send the completion event on. This should
35173 * be the NQ ID returned from the `nq_alloc` HWRM command.
35175 uint16_t cmpl_ring;
35177 * The sequence ID is used by the driver for tracking multiple
35178 * commands. This ID is treated as opaque data by the firmware and
35179 * the value is returned in the `hwrm_resp_hdr` upon completion.
35183 * The target ID of the command:
35184 * * 0x0-0xFFF8 - The function ID
35185 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35186 * * 0xFFFD - Reserved for user-space HWRM interface
35189 uint16_t target_id;
35191 * A physical address pointer pointing to a host buffer that the
35192 * command's response data will be written. This can be either a host
35193 * physical address (HPA) or a guest physical address (GPA) and must
35194 * point to a physically contiguous block of memory.
35196 uint64_t resp_addr;
35198 * Unique session identifier for the session that the attach
35199 * request want to attach to. This value originates from the
35200 * shared session memory that the attach request opened by
35201 * way of the 'attach name' that was passed in to the core
35203 * The fw_session_id of the attach session includes PCIe bus
35204 * info to distinguish the PF and session info to identify
35205 * the associated TruFlow session.
35207 uint32_t attach_fw_session_id;
35210 /* Name of the session it self. */
35211 uint8_t session_name[64];
35214 /* hwrm_tf_session_attach_output (size:128b/16B) */
35215 struct hwrm_tf_session_attach_output {
35216 /* The specific error status for the command. */
35217 uint16_t error_code;
35218 /* The HWRM command request type. */
35220 /* The sequence ID from the original command. */
35222 /* The length of the response data in number of bytes. */
35225 * Unique session identifier for the session created by the
35226 * firmware. It includes PCIe bus info to distinguish the PF
35227 * and session info to identify the associated TruFlow
35228 * session. This fw_session_id is unique to the attach
35231 uint32_t fw_session_id;
35233 uint8_t unused0[3];
35235 * This field is used in Output records to indicate that the output
35236 * is completely written to RAM. This field should be read as '1'
35237 * to indicate that the output has been completely written.
35238 * When writing a command completion or response to an internal
35239 * processor, the order of writes has to be such that this field is
35245 /****************************
35246 * hwrm_tf_session_register *
35247 ****************************/
35250 /* hwrm_tf_session_register_input (size:704b/88B) */
35251 struct hwrm_tf_session_register_input {
35252 /* The HWRM command request type. */
35255 * The completion ring to send the completion event on. This should
35256 * be the NQ ID returned from the `nq_alloc` HWRM command.
35258 uint16_t cmpl_ring;
35260 * The sequence ID is used by the driver for tracking multiple
35261 * commands. This ID is treated as opaque data by the firmware and
35262 * the value is returned in the `hwrm_resp_hdr` upon completion.
35266 * The target ID of the command:
35267 * * 0x0-0xFFF8 - The function ID
35268 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35269 * * 0xFFFD - Reserved for user-space HWRM interface
35272 uint16_t target_id;
35274 * A physical address pointer pointing to a host buffer that the
35275 * command's response data will be written. This can be either a host
35276 * physical address (HPA) or a guest physical address (GPA) and must
35277 * point to a physically contiguous block of memory.
35279 uint64_t resp_addr;
35281 * Unique session identifier for the session that the
35282 * register request want to create a new client on. This
35283 * value originates from the first open request.
35284 * The fw_session_id of the attach session includes PCIe bus
35285 * info to distinguish the PF and session info to identify
35286 * the associated TruFlow session.
35288 uint32_t fw_session_id;
35291 /* Name of the session client. */
35292 uint8_t session_client_name[64];
35295 /* hwrm_tf_session_register_output (size:128b/16B) */
35296 struct hwrm_tf_session_register_output {
35297 /* The specific error status for the command. */
35298 uint16_t error_code;
35299 /* The HWRM command request type. */
35301 /* The sequence ID from the original command. */
35303 /* The length of the response data in number of bytes. */
35306 * Unique session client identifier for the session created
35307 * by the firmware. It includes the session the client it
35308 * attached to and session client info.
35310 uint32_t fw_session_client_id;
35312 uint8_t unused0[3];
35314 * This field is used in Output records to indicate that the output
35315 * is completely written to RAM. This field should be read as '1'
35316 * to indicate that the output has been completely written.
35317 * When writing a command completion or response to an internal
35318 * processor, the order of writes has to be such that this field is
35324 /******************************
35325 * hwrm_tf_session_unregister *
35326 ******************************/
35329 /* hwrm_tf_session_unregister_input (size:192b/24B) */
35330 struct hwrm_tf_session_unregister_input {
35331 /* The HWRM command request type. */
35334 * The completion ring to send the completion event on. This should
35335 * be the NQ ID returned from the `nq_alloc` HWRM command.
35337 uint16_t cmpl_ring;
35339 * The sequence ID is used by the driver for tracking multiple
35340 * commands. This ID is treated as opaque data by the firmware and
35341 * the value is returned in the `hwrm_resp_hdr` upon completion.
35345 * The target ID of the command:
35346 * * 0x0-0xFFF8 - The function ID
35347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35348 * * 0xFFFD - Reserved for user-space HWRM interface
35351 uint16_t target_id;
35353 * A physical address pointer pointing to a host buffer that the
35354 * command's response data will be written. This can be either a host
35355 * physical address (HPA) or a guest physical address (GPA) and must
35356 * point to a physically contiguous block of memory.
35358 uint64_t resp_addr;
35360 * Unique session identifier for the session that the
35361 * unregister request want to close a session client on.
35363 uint32_t fw_session_id;
35365 * Unique session client identifier for the session that the
35366 * unregister request want to close.
35368 uint32_t fw_session_client_id;
35371 /* hwrm_tf_session_unregister_output (size:128b/16B) */
35372 struct hwrm_tf_session_unregister_output {
35373 /* The specific error status for the command. */
35374 uint16_t error_code;
35375 /* The HWRM command request type. */
35377 /* The sequence ID from the original command. */
35379 /* The length of the response data in number of bytes. */
35382 uint8_t unused0[7];
35384 * This field is used in Output records to indicate that the output
35385 * is completely written to RAM. This field should be read as '1'
35386 * to indicate that the output has been completely written.
35387 * When writing a command completion or response to an internal
35388 * processor, the order of writes has to be such that this field is
35394 /*************************
35395 * hwrm_tf_session_close *
35396 *************************/
35399 /* hwrm_tf_session_close_input (size:192b/24B) */
35400 struct hwrm_tf_session_close_input {
35401 /* The HWRM command request type. */
35404 * The completion ring to send the completion event on. This should
35405 * be the NQ ID returned from the `nq_alloc` HWRM command.
35407 uint16_t cmpl_ring;
35409 * The sequence ID is used by the driver for tracking multiple
35410 * commands. This ID is treated as opaque data by the firmware and
35411 * the value is returned in the `hwrm_resp_hdr` upon completion.
35415 * The target ID of the command:
35416 * * 0x0-0xFFF8 - The function ID
35417 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35418 * * 0xFFFD - Reserved for user-space HWRM interface
35421 uint16_t target_id;
35423 * A physical address pointer pointing to a host buffer that the
35424 * command's response data will be written. This can be either a host
35425 * physical address (HPA) or a guest physical address (GPA) and must
35426 * point to a physically contiguous block of memory.
35428 uint64_t resp_addr;
35429 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35430 uint32_t fw_session_id;
35432 uint8_t unused0[4];
35435 /* hwrm_tf_session_close_output (size:128b/16B) */
35436 struct hwrm_tf_session_close_output {
35437 /* The specific error status for the command. */
35438 uint16_t error_code;
35439 /* The HWRM command request type. */
35441 /* The sequence ID from the original command. */
35443 /* The length of the response data in number of bytes. */
35446 uint8_t unused0[7];
35448 * This field is used in Output records to indicate that the output
35449 * is completely written to RAM. This field should be read as '1'
35450 * to indicate that the output has been completely written.
35451 * When writing a command completion or response to an internal
35452 * processor, the order of writes has to be such that this field
35458 /************************
35459 * hwrm_tf_session_qcfg *
35460 ************************/
35463 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
35464 struct hwrm_tf_session_qcfg_input {
35465 /* The HWRM command request type. */
35468 * The completion ring to send the completion event on. This should
35469 * be the NQ ID returned from the `nq_alloc` HWRM command.
35471 uint16_t cmpl_ring;
35473 * The sequence ID is used by the driver for tracking multiple
35474 * commands. This ID is treated as opaque data by the firmware and
35475 * the value is returned in the `hwrm_resp_hdr` upon completion.
35479 * The target ID of the command:
35480 * * 0x0-0xFFF8 - The function ID
35481 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35482 * * 0xFFFD - Reserved for user-space HWRM interface
35485 uint16_t target_id;
35487 * A physical address pointer pointing to a host buffer that the
35488 * command's response data will be written. This can be either a host
35489 * physical address (HPA) or a guest physical address (GPA) and must
35490 * point to a physically contiguous block of memory.
35492 uint64_t resp_addr;
35493 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35494 uint32_t fw_session_id;
35496 uint8_t unused0[4];
35499 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
35500 struct hwrm_tf_session_qcfg_output {
35501 /* The specific error status for the command. */
35502 uint16_t error_code;
35503 /* The HWRM command request type. */
35505 /* The sequence ID from the original command. */
35507 /* The length of the response data in number of bytes. */
35509 /* RX action control settings flags. */
35510 uint8_t rx_act_flags;
35512 * A value of 1 in this field indicates that Global Flow ID
35513 * reporting into cfa_code and cfa_metadata is enabled.
35515 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
35518 * A value of 1 in this field indicates that both inner and outer
35519 * are stripped and inner tag is passed.
35522 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
35525 * A value of 1 in this field indicates that the re-use of
35526 * existing tunnel L2 header SMAC is enabled for
35527 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
35529 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
35531 /* TX Action control settings flags. */
35532 uint8_t tx_act_flags;
35534 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
35537 * When set to 1 any GRE tunnels will include the
35538 * optional Key field.
35540 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
35543 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
35544 * field of the outer header is inherited from the inner header
35545 * (if present) or the fixed value as taken from the encap
35548 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
35551 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
35552 * field of the outer header is inherited from the inner header
35553 * (if present) or the fixed value as taken from the encap record.
35555 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
35558 uint8_t unused0[5];
35560 * This field is used in Output records to indicate that the output
35561 * is completely written to RAM. This field should be read as '1'
35562 * to indicate that the output has been completely written.
35563 * When writing a command completion or response to an internal
35564 * processor, the order of writes has to be such that this field
35570 /******************************
35571 * hwrm_tf_session_resc_qcaps *
35572 ******************************/
35575 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
35576 struct hwrm_tf_session_resc_qcaps_input {
35577 /* The HWRM command request type. */
35580 * The completion ring to send the completion event on. This should
35581 * be the NQ ID returned from the `nq_alloc` HWRM command.
35583 uint16_t cmpl_ring;
35585 * The sequence ID is used by the driver for tracking multiple
35586 * commands. This ID is treated as opaque data by the firmware and
35587 * the value is returned in the `hwrm_resp_hdr` upon completion.
35591 * The target ID of the command:
35592 * * 0x0-0xFFF8 - The function ID
35593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35594 * * 0xFFFD - Reserved for user-space HWRM interface
35597 uint16_t target_id;
35599 * A physical address pointer pointing to a host buffer that the
35600 * command's response data will be written. This can be either a host
35601 * physical address (HPA) or a guest physical address (GPA) and must
35602 * point to a physically contiguous block of memory.
35604 uint64_t resp_addr;
35605 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35606 uint32_t fw_session_id;
35607 /* Control flags. */
35609 /* Indicates the flow direction. */
35610 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
35611 /* If this bit set to 0, then it indicates rx flow. */
35612 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35613 /* If this bit is set to 1, then it indicates that tx flow. */
35614 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35615 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
35616 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
35618 * Defines the size of the provided qcaps_addr array
35619 * buffer. The size should be set to the Resource Manager
35620 * provided max number of qcaps entries which is device
35621 * specific. Resource Manager gets the max size from HCAPI
35624 uint16_t qcaps_size;
35626 * This is the DMA address for the qcaps output data array
35627 * buffer. Array is of tf_rm_resc_req_entry type and is
35630 uint64_t qcaps_addr;
35633 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
35634 struct hwrm_tf_session_resc_qcaps_output {
35635 /* The specific error status for the command. */
35636 uint16_t error_code;
35637 /* The HWRM command request type. */
35639 /* The sequence ID from the original command. */
35641 /* The length of the response data in number of bytes. */
35643 /* Control flags. */
35645 /* Session reservation strategy. */
35646 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
35648 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
35650 /* Static partitioning. */
35651 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
35654 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
35657 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
35660 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
35662 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
35663 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
35665 * Size of the returned qcaps_addr data array buffer. The
35666 * value cannot exceed the size defined by the input msg,
35673 uint8_t unused1[7];
35675 * This field is used in Output records to indicate that the output
35676 * is completely written to RAM. This field should be read as '1'
35677 * to indicate that the output has been completely written.
35678 * When writing a command completion or response to an internal
35679 * processor, the order of writes has to be such that this field is
35685 /******************************
35686 * hwrm_tf_session_resc_alloc *
35687 ******************************/
35690 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
35691 struct hwrm_tf_session_resc_alloc_input {
35692 /* The HWRM command request type. */
35695 * The completion ring to send the completion event on. This should
35696 * be the NQ ID returned from the `nq_alloc` HWRM command.
35698 uint16_t cmpl_ring;
35700 * The sequence ID is used by the driver for tracking multiple
35701 * commands. This ID is treated as opaque data by the firmware and
35702 * the value is returned in the `hwrm_resp_hdr` upon completion.
35706 * The target ID of the command:
35707 * * 0x0-0xFFF8 - The function ID
35708 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35709 * * 0xFFFD - Reserved for user-space HWRM interface
35712 uint16_t target_id;
35714 * A physical address pointer pointing to a host buffer that the
35715 * command's response data will be written. This can be either a host
35716 * physical address (HPA) or a guest physical address (GPA) and must
35717 * point to a physically contiguous block of memory.
35719 uint64_t resp_addr;
35720 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35721 uint32_t fw_session_id;
35722 /* Control flags. */
35724 /* Indicates the flow direction. */
35725 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
35726 /* If this bit set to 0, then it indicates rx flow. */
35727 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35728 /* If this bit is set to 1, then it indicates that tx flow. */
35729 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35730 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
35731 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
35733 * Defines the array size of the provided req_addr and
35734 * resv_addr array buffers. Should be set to the number of
35739 * This is the DMA address for the request input data array
35740 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
35741 * array buffer is provided by the 'req_size' field in this
35746 * This is the DMA address for the resc output data array
35747 * buffer. Array is of tf_rm_resc_entry type. Size of the array
35748 * buffer is provided by the 'req_size' field in this
35751 uint64_t resc_addr;
35754 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
35755 struct hwrm_tf_session_resc_alloc_output {
35756 /* The specific error status for the command. */
35757 uint16_t error_code;
35758 /* The HWRM command request type. */
35760 /* The sequence ID from the original command. */
35762 /* The length of the response data in number of bytes. */
35765 * Size of the returned tf_rm_resc_entry data array. The value
35766 * cannot exceed the req_size defined by the input msg. The data
35767 * array is returned using the resv_addr specified DMA
35768 * address also provided by the input msg.
35772 uint8_t unused0[5];
35774 * This field is used in Output records to indicate that the output
35775 * is completely written to RAM. This field should be read as '1'
35776 * to indicate that the output has been completely written.
35777 * When writing a command completion or response to an internal
35778 * processor, the order of writes has to be such that this field is
35784 /*****************************
35785 * hwrm_tf_session_resc_free *
35786 *****************************/
35789 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
35790 struct hwrm_tf_session_resc_free_input {
35791 /* The HWRM command request type. */
35794 * The completion ring to send the completion event on. This should
35795 * be the NQ ID returned from the `nq_alloc` HWRM command.
35797 uint16_t cmpl_ring;
35799 * The sequence ID is used by the driver for tracking multiple
35800 * commands. This ID is treated as opaque data by the firmware and
35801 * the value is returned in the `hwrm_resp_hdr` upon completion.
35805 * The target ID of the command:
35806 * * 0x0-0xFFF8 - The function ID
35807 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35808 * * 0xFFFD - Reserved for user-space HWRM interface
35811 uint16_t target_id;
35813 * A physical address pointer pointing to a host buffer that the
35814 * command's response data will be written. This can be either a host
35815 * physical address (HPA) or a guest physical address (GPA) and must
35816 * point to a physically contiguous block of memory.
35818 uint64_t resp_addr;
35819 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35820 uint32_t fw_session_id;
35821 /* Control flags. */
35823 /* Indicates the flow direction. */
35824 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
35825 /* If this bit set to 0, then it indicates rx flow. */
35826 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35827 /* If this bit is set to 1, then it indicates that tx flow. */
35828 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35829 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
35830 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
35832 * Defines the size, in bytes, of the provided free_addr
35835 uint16_t free_size;
35837 * This is the DMA address for the free input data array
35838 * buffer. Array is of tf_rm_resc_entry type. Size of the
35839 * buffer is provided by the 'free_size' field of this
35842 uint64_t free_addr;
35845 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
35846 struct hwrm_tf_session_resc_free_output {
35847 /* The specific error status for the command. */
35848 uint16_t error_code;
35849 /* The HWRM command request type. */
35851 /* The sequence ID from the original command. */
35853 /* The length of the response data in number of bytes. */
35856 uint8_t unused0[7];
35858 * This field is used in Output records to indicate that the output
35859 * is completely written to RAM. This field should be read as '1'
35860 * to indicate that the output has been completely written.
35861 * When writing a command completion or response to an internal
35862 * processor, the order of writes has to be such that this field is
35868 /******************************
35869 * hwrm_tf_session_resc_flush *
35870 ******************************/
35873 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
35874 struct hwrm_tf_session_resc_flush_input {
35875 /* The HWRM command request type. */
35878 * The completion ring to send the completion event on. This should
35879 * be the NQ ID returned from the `nq_alloc` HWRM command.
35881 uint16_t cmpl_ring;
35883 * The sequence ID is used by the driver for tracking multiple
35884 * commands. This ID is treated as opaque data by the firmware and
35885 * the value is returned in the `hwrm_resp_hdr` upon completion.
35889 * The target ID of the command:
35890 * * 0x0-0xFFF8 - The function ID
35891 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35892 * * 0xFFFD - Reserved for user-space HWRM interface
35895 uint16_t target_id;
35897 * A physical address pointer pointing to a host buffer that the
35898 * command's response data will be written. This can be either a host
35899 * physical address (HPA) or a guest physical address (GPA) and must
35900 * point to a physically contiguous block of memory.
35902 uint64_t resp_addr;
35903 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
35904 uint32_t fw_session_id;
35905 /* Control flags. */
35907 /* Indicates the flow direction. */
35908 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
35909 /* If this bit set to 0, then it indicates rx flow. */
35910 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
35911 /* If this bit is set to 1, then it indicates that tx flow. */
35912 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
35913 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
35914 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
35916 * Defines the size, in bytes, of the provided flush_addr
35919 uint16_t flush_size;
35921 * This is the DMA address for the flush input data array
35922 * buffer. Array of tf_rm_resc_entry type. Size of the
35923 * buffer is provided by the 'flush_size' field in this
35926 uint64_t flush_addr;
35929 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
35930 struct hwrm_tf_session_resc_flush_output {
35931 /* The specific error status for the command. */
35932 uint16_t error_code;
35933 /* The HWRM command request type. */
35935 /* The sequence ID from the original command. */
35937 /* The length of the response data in number of bytes. */
35940 uint8_t unused0[7];
35942 * This field is used in Output records to indicate that the output
35943 * is completely written to RAM. This field should be read as '1'
35944 * to indicate that the output has been completely written.
35945 * When writing a command completion or response to an internal
35946 * processor, the order of writes has to be such that this field is
35952 /* TruFlow RM capability of a resource. */
35953 /* tf_rm_resc_req_entry (size:64b/8B) */
35954 struct tf_rm_resc_req_entry {
35955 /* Type of the resource, defined globally in HCAPI RM. */
35957 /* Minimum value. */
35959 /* Maximum value. */
35963 /* TruFlow RM reservation information. */
35964 /* tf_rm_resc_entry (size:64b/8B) */
35965 struct tf_rm_resc_entry {
35966 /* Type of the resource, defined globally in HCAPI RM. */
35968 /* Start offset. */
35970 /* Number of resources. */
35974 /************************
35975 * hwrm_tf_tbl_type_get *
35976 ************************/
35979 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
35980 struct hwrm_tf_tbl_type_get_input {
35981 /* The HWRM command request type. */
35984 * The completion ring to send the completion event on. This should
35985 * be the NQ ID returned from the `nq_alloc` HWRM command.
35987 uint16_t cmpl_ring;
35989 * The sequence ID is used by the driver for tracking multiple
35990 * commands. This ID is treated as opaque data by the firmware and
35991 * the value is returned in the `hwrm_resp_hdr` upon completion.
35995 * The target ID of the command:
35996 * * 0x0-0xFFF8 - The function ID
35997 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35998 * * 0xFFFD - Reserved for user-space HWRM interface
36001 uint16_t target_id;
36003 * A physical address pointer pointing to a host buffer that the
36004 * command's response data will be written. This can be either a host
36005 * physical address (HPA) or a guest physical address (GPA) and must
36006 * point to a physically contiguous block of memory.
36008 uint64_t resp_addr;
36009 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
36010 uint32_t fw_session_id;
36011 /* Control flags. */
36013 /* Indicates the flow direction. */
36014 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
36015 /* If this bit set to 0, then it indicates rx flow. */
36016 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36017 /* If this bit is set to 1, then it indicates that tx flow. */
36018 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36019 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
36020 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
36022 uint8_t unused0[2];
36024 * Type of the resource, defined globally in the
36025 * hwrm_tf_resc_type enum.
36028 /* Index of the type to retrieve. */
36032 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
36033 struct hwrm_tf_tbl_type_get_output {
36034 /* The specific error status for the command. */
36035 uint16_t error_code;
36036 /* The HWRM command request type. */
36038 /* The sequence ID from the original command. */
36040 /* The length of the response data in number of bytes. */
36042 /* Response code. */
36043 uint32_t resp_code;
36044 /* Response size. */
36048 /* Response data. */
36051 uint8_t unused1[7];
36053 * This field is used in Output records to indicate that the output
36054 * is completely written to RAM. This field should be read as '1'
36055 * to indicate that the output has been completely written.
36056 * When writing a command completion or response to an internal
36057 * processor, the order of writes has to be such that this field
36063 /************************
36064 * hwrm_tf_tbl_type_set *
36065 ************************/
36068 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
36069 struct hwrm_tf_tbl_type_set_input {
36070 /* The HWRM command request type. */
36073 * The completion ring to send the completion event on. This should
36074 * be the NQ ID returned from the `nq_alloc` HWRM command.
36076 uint16_t cmpl_ring;
36078 * The sequence ID is used by the driver for tracking multiple
36079 * commands. This ID is treated as opaque data by the firmware and
36080 * the value is returned in the `hwrm_resp_hdr` upon completion.
36084 * The target ID of the command:
36085 * * 0x0-0xFFF8 - The function ID
36086 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36087 * * 0xFFFD - Reserved for user-space HWRM interface
36090 uint16_t target_id;
36092 * A physical address pointer pointing to a host buffer that the
36093 * command's response data will be written. This can be either a host
36094 * physical address (HPA) or a guest physical address (GPA) and must
36095 * point to a physically contiguous block of memory.
36097 uint64_t resp_addr;
36098 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
36099 uint32_t fw_session_id;
36100 /* Control flags. */
36102 /* Indicates the flow direction. */
36103 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
36104 /* If this bit set to 0, then it indicates rx flow. */
36105 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36106 /* If this bit is set to 1, then it indicates that tx flow. */
36107 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36108 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
36109 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
36111 uint8_t unused0[2];
36113 * Type of the resource, defined globally in the
36114 * hwrm_tf_resc_type enum.
36117 /* Index of the type to retrieve. */
36119 /* Size of the data to set. */
36122 uint8_t unused1[6];
36123 /* Data to be set. */
36127 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
36128 struct hwrm_tf_tbl_type_set_output {
36129 /* The specific error status for the command. */
36130 uint16_t error_code;
36131 /* The HWRM command request type. */
36133 /* The sequence ID from the original command. */
36135 /* The length of the response data in number of bytes. */
36138 uint8_t unused0[7];
36140 * This field is used in Output records to indicate that the output
36141 * is completely written to RAM. This field should be read as '1'
36142 * to indicate that the output has been completely written.
36143 * When writing a command completion or response to an internal
36144 * processor, the order of writes has to be such that this field
36150 /*************************
36151 * hwrm_tf_ctxt_mem_rgtr *
36152 *************************/
36155 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
36156 struct hwrm_tf_ctxt_mem_rgtr_input {
36157 /* The HWRM command request type. */
36160 * The completion ring to send the completion event on. This should
36161 * be the NQ ID returned from the `nq_alloc` HWRM command.
36163 uint16_t cmpl_ring;
36165 * The sequence ID is used by the driver for tracking multiple
36166 * commands. This ID is treated as opaque data by the firmware and
36167 * the value is returned in the `hwrm_resp_hdr` upon completion.
36171 * The target ID of the command:
36172 * * 0x0-0xFFF8 - The function ID
36173 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36174 * * 0xFFFD - Reserved for user-space HWRM interface
36177 uint16_t target_id;
36179 * A physical address pointer pointing to a host buffer that the
36180 * command's response data will be written. This can be either a host
36181 * physical address (HPA) or a guest physical address (GPA) and must
36182 * point to a physically contiguous block of memory.
36184 uint64_t resp_addr;
36185 /* Control flags. */
36187 /* Counter PBL indirect levels. */
36188 uint8_t page_level;
36189 /* PBL pointer is physical start address. */
36190 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
36191 /* PBL pointer points to PTE table. */
36192 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
36194 * PBL pointer points to PDE table with each entry pointing
36197 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
36198 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
36199 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
36202 /* 4KB page size. */
36203 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
36204 /* 8KB page size. */
36205 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
36206 /* 64KB page size. */
36207 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
36208 /* 256KB page size. */
36209 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
36210 /* 1MB page size. */
36211 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
36212 /* 2MB page size. */
36213 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
36214 /* 4MB page size. */
36215 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
36216 /* 1GB page size. */
36217 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
36218 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
36219 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
36222 /* Pointer to the PBL, or PDL depending on number of levels */
36226 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
36227 struct hwrm_tf_ctxt_mem_rgtr_output {
36228 /* The specific error status for the command. */
36229 uint16_t error_code;
36230 /* The HWRM command request type. */
36232 /* The sequence ID from the original command. */
36234 /* The length of the response data in number of bytes. */
36237 * Id/Handle to the recently register context memory. This
36238 * handle is passed to the TF session.
36242 uint8_t unused0[5];
36244 * This field is used in Output records to indicate that the
36245 * output is completely written to RAM. This field should be
36246 * read as '1' to indicate that the output has been
36247 * completely written. When writing a command completion or
36248 * response to an internal processor, the order of writes has
36249 * to be such that this field is written last.
36254 /***************************
36255 * hwrm_tf_ctxt_mem_unrgtr *
36256 ***************************/
36259 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
36260 struct hwrm_tf_ctxt_mem_unrgtr_input {
36261 /* The HWRM command request type. */
36264 * The completion ring to send the completion event on. This should
36265 * be the NQ ID returned from the `nq_alloc` HWRM command.
36267 uint16_t cmpl_ring;
36269 * The sequence ID is used by the driver for tracking multiple
36270 * commands. This ID is treated as opaque data by the firmware and
36271 * the value is returned in the `hwrm_resp_hdr` upon completion.
36275 * The target ID of the command:
36276 * * 0x0-0xFFF8 - The function ID
36277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36278 * * 0xFFFD - Reserved for user-space HWRM interface
36281 uint16_t target_id;
36283 * A physical address pointer pointing to a host buffer that the
36284 * command's response data will be written. This can be either a host
36285 * physical address (HPA) or a guest physical address (GPA) and must
36286 * point to a physically contiguous block of memory.
36288 uint64_t resp_addr;
36290 * Id/Handle to the recently register context memory. This
36291 * handle is passed to the TF session.
36295 uint8_t unused0[6];
36298 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
36299 struct hwrm_tf_ctxt_mem_unrgtr_output {
36300 /* The specific error status for the command. */
36301 uint16_t error_code;
36302 /* The HWRM command request type. */
36304 /* The sequence ID from the original command. */
36306 /* The length of the response data in number of bytes. */
36309 uint8_t unused0[7];
36311 * This field is used in Output records to indicate that the
36312 * output is completely written to RAM. This field should be
36313 * read as '1' to indicate that the output has been
36314 * completely written. When writing a command completion or
36315 * response to an internal processor, the order of writes has
36316 * to be such that this field is written last.
36321 /************************
36322 * hwrm_tf_ext_em_qcaps *
36323 ************************/
36326 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
36327 struct hwrm_tf_ext_em_qcaps_input {
36328 /* The HWRM command request type. */
36331 * The completion ring to send the completion event on. This should
36332 * be the NQ ID returned from the `nq_alloc` HWRM command.
36334 uint16_t cmpl_ring;
36336 * The sequence ID is used by the driver for tracking multiple
36337 * commands. This ID is treated as opaque data by the firmware and
36338 * the value is returned in the `hwrm_resp_hdr` upon completion.
36342 * The target ID of the command:
36343 * * 0x0-0xFFF8 - The function ID
36344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36345 * * 0xFFFD - Reserved for user-space HWRM interface
36348 uint16_t target_id;
36350 * A physical address pointer pointing to a host buffer that the
36351 * command's response data will be written. This can be either a host
36352 * physical address (HPA) or a guest physical address (GPA) and must
36353 * point to a physically contiguous block of memory.
36355 uint64_t resp_addr;
36356 /* Control flags. */
36358 /* Indicates the flow direction. */
36359 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
36361 /* If this bit set to 0, then it indicates rx flow. */
36362 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
36364 /* If this bit is set to 1, then it indicates that tx flow. */
36365 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
36367 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
36368 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
36369 /* When set to 1, all offloaded flows will be sent to EXT EM. */
36370 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
36376 /* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
36377 struct hwrm_tf_ext_em_qcaps_output {
36378 /* The specific error status for the command. */
36379 uint16_t error_code;
36380 /* The HWRM command request type. */
36382 /* The sequence ID from the original command. */
36384 /* The length of the response data in number of bytes. */
36388 * When set to 1, indicates the the FW supports the Centralized
36389 * Memory Model. The concept designates one entity for the
36390 * memory allocation while all others ‘subscribe’ to it.
36392 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36395 * When set to 1, indicates the the FW supports the Detached
36396 * Centralized Memory Model. The memory is allocated and managed
36397 * as a separate entity. All PFs and VFs will be granted direct
36398 * or semi-direct access to the allocated memory while none of
36399 * which can interfere with the management of the memory.
36401 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
36405 /* Support flags. */
36406 uint32_t supported;
36408 * If set to 1, then EXT EM KEY0 table is supported using
36410 * If set to 0, EXT EM KEY0 table is not supported.
36412 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
36415 * If set to 1, then EXT EM KEY1 table is supported using
36417 * If set to 0, EXT EM KEY1 table is not supported.
36419 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
36422 * If set to 1, then EXT EM External Record table is supported.
36423 * If set to 0, EXT EM External Record table is not
36424 * supported. (This table includes action record, EFC
36425 * pointers, encap pointers)
36427 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
36430 * If set to 1, then EXT EM External Flow Counters table is
36432 * If set to 0, EXT EM External Flow Counters table is not
36435 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
36438 * If set to 1, then FID table used for implicit flow flush
36440 * If set to 0, then FID table used for implicit flow flush
36441 * is not supported.
36443 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
36446 * The maximum number of entries supported by EXT EM. When
36447 * configuring the host memory the number of numbers of
36448 * entries that can supported are -
36449 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
36451 * Any value that are not these values, the FW will round
36452 * down to the closest support number of entries.
36454 uint32_t max_entries_supported;
36456 * The entry size in bytes of each entry in the EXT EM
36457 * KEY0/KEY1 tables.
36459 uint16_t key_entry_size;
36461 * The entry size in bytes of each entry in the EXT EM RECORD
36464 uint16_t record_entry_size;
36465 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
36466 uint16_t efc_entry_size;
36467 /* The FID size in bytes of each entry in the EXT EM FID tables. */
36468 uint16_t fid_entry_size;
36470 uint8_t unused1[7];
36472 * This field is used in Output records to indicate that the
36473 * output is completely written to RAM. This field should be
36474 * read as '1' to indicate that the output has been
36475 * completely written. When writing a command completion or
36476 * response to an internal processor, the order of writes has
36477 * to be such that this field is written last.
36482 /*********************
36483 * hwrm_tf_ext_em_op *
36484 *********************/
36487 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
36488 struct hwrm_tf_ext_em_op_input {
36489 /* The HWRM command request type. */
36492 * The completion ring to send the completion event on. This should
36493 * be the NQ ID returned from the `nq_alloc` HWRM command.
36495 uint16_t cmpl_ring;
36497 * The sequence ID is used by the driver for tracking multiple
36498 * commands. This ID is treated as opaque data by the firmware and
36499 * the value is returned in the `hwrm_resp_hdr` upon completion.
36503 * The target ID of the command:
36504 * * 0x0-0xFFF8 - The function ID
36505 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36506 * * 0xFFFD - Reserved for user-space HWRM interface
36509 uint16_t target_id;
36511 * A physical address pointer pointing to a host buffer that the
36512 * command's response data will be written. This can be either a host
36513 * physical address (HPA) or a guest physical address (GPA) and must
36514 * point to a physically contiguous block of memory.
36516 uint64_t resp_addr;
36517 /* Control flags. */
36519 /* Indicates the flow direction. */
36520 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
36521 /* If this bit set to 0, then it indicates rx flow. */
36522 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36523 /* If this bit is set to 1, then it indicates that tx flow. */
36524 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36525 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
36526 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
36529 /* The number of EXT EM key table entries to be configured. */
36531 /* This value is reserved and should not be used. */
36532 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
36534 * To properly stop EXT EM and ensure there are no DMA's,
36535 * the caller must disable EXT EM for the given PF, using
36536 * this call. This will safely disable EXT EM and ensure
36537 * that all DMA'ed to the keys/records/efc have been
36540 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
36542 * Once the EXT EM host memory has been configured, EXT EM
36543 * options have been configured. Then the caller should
36544 * enable EXT EM for the given PF. Note once this call has
36545 * been made, then the EXT EM mechanism will be active and
36546 * DMA's will occur as packets are processed.
36548 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
36550 * Clear EXT EM settings for the given PF so that the
36551 * register values are reset back to their initial state.
36553 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
36554 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
36555 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
36560 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
36561 struct hwrm_tf_ext_em_op_output {
36562 /* The specific error status for the command. */
36563 uint16_t error_code;
36564 /* The HWRM command request type. */
36566 /* The sequence ID from the original command. */
36568 /* The length of the response data in number of bytes. */
36571 uint8_t unused0[7];
36573 * This field is used in Output records to indicate that the
36574 * output is completely written to RAM. This field should be
36575 * read as '1' to indicate that the output has been
36576 * completely written. When writing a command completion or
36577 * response to an internal processor, the order of writes has
36578 * to be such that this field is written last.
36583 /**********************
36584 * hwrm_tf_ext_em_cfg *
36585 **********************/
36588 /* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
36589 struct hwrm_tf_ext_em_cfg_input {
36590 /* The HWRM command request type. */
36593 * The completion ring to send the completion event on. This should
36594 * be the NQ ID returned from the `nq_alloc` HWRM command.
36596 uint16_t cmpl_ring;
36598 * The sequence ID is used by the driver for tracking multiple
36599 * commands. This ID is treated as opaque data by the firmware and
36600 * the value is returned in the `hwrm_resp_hdr` upon completion.
36604 * The target ID of the command:
36605 * * 0x0-0xFFF8 - The function ID
36606 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36607 * * 0xFFFD - Reserved for user-space HWRM interface
36610 uint16_t target_id;
36612 * A physical address pointer pointing to a host buffer that the
36613 * command's response data will be written. This can be either a host
36614 * physical address (HPA) or a guest physical address (GPA) and must
36615 * point to a physically contiguous block of memory.
36617 uint64_t resp_addr;
36618 /* Control flags. */
36620 /* Indicates the flow direction. */
36621 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
36623 /* If this bit set to 0, then it indicates rx flow. */
36624 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
36626 /* If this bit is set to 1, then it indicates that tx flow. */
36627 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
36629 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
36630 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
36631 /* When set to 1, all offloaded flows will be sent to EXT EM. */
36632 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
36634 /* When set to 1, secondary, 0 means primary. */
36635 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
36638 * Group_id which used by Firmware to identify memory pools belonging
36639 * to certain group.
36643 * Dynamically reconfigure EEM pending cache every 1/10th of second.
36644 * If set to 0 it will disable the EEM HW flush of the pending cache.
36646 uint8_t flush_interval;
36650 * Configured EXT EM with the given number of entries. All
36651 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
36652 * same number of entries and all tables will be configured
36653 * using this value. Current minimum value is 32k. Current
36654 * maximum value is 128M.
36656 uint32_t num_entries;
36659 /* Configured EXT EM with the given context if for KEY0 table. */
36660 uint16_t key0_ctx_id;
36661 /* Configured EXT EM with the given context if for KEY1 table. */
36662 uint16_t key1_ctx_id;
36663 /* Configured EXT EM with the given context if for RECORD table. */
36664 uint16_t record_ctx_id;
36665 /* Configured EXT EM with the given context if for EFC table. */
36666 uint16_t efc_ctx_id;
36667 /* Configured EXT EM with the given context if for EFC table. */
36668 uint16_t fid_ctx_id;
36675 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
36676 struct hwrm_tf_ext_em_cfg_output {
36677 /* The specific error status for the command. */
36678 uint16_t error_code;
36679 /* The HWRM command request type. */
36681 /* The sequence ID from the original command. */
36683 /* The length of the response data in number of bytes. */
36686 uint8_t unused0[7];
36688 * This field is used in Output records to indicate that the
36689 * output is completely written to RAM. This field should be
36690 * read as '1' to indicate that the output has been
36691 * completely written. When writing a command completion or
36692 * response to an internal processor, the order of writes has
36693 * to be such that this field is written last.
36698 /***********************
36699 * hwrm_tf_ext_em_qcfg *
36700 ***********************/
36703 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
36704 struct hwrm_tf_ext_em_qcfg_input {
36705 /* The HWRM command request type. */
36708 * The completion ring to send the completion event on. This should
36709 * be the NQ ID returned from the `nq_alloc` HWRM command.
36711 uint16_t cmpl_ring;
36713 * The sequence ID is used by the driver for tracking multiple
36714 * commands. This ID is treated as opaque data by the firmware and
36715 * the value is returned in the `hwrm_resp_hdr` upon completion.
36719 * The target ID of the command:
36720 * * 0x0-0xFFF8 - The function ID
36721 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36722 * * 0xFFFD - Reserved for user-space HWRM interface
36725 uint16_t target_id;
36727 * A physical address pointer pointing to a host buffer that the
36728 * command's response data will be written. This can be either a host
36729 * physical address (HPA) or a guest physical address (GPA) and must
36730 * point to a physically contiguous block of memory.
36732 uint64_t resp_addr;
36733 /* Control flags. */
36735 /* Indicates the flow direction. */
36736 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
36737 /* If this bit set to 0, then it indicates rx flow. */
36738 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36739 /* If this bit is set to 1, then it indicates that tx flow. */
36740 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36741 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
36742 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
36747 /* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
36748 struct hwrm_tf_ext_em_qcfg_output {
36749 /* The specific error status for the command. */
36750 uint16_t error_code;
36751 /* The HWRM command request type. */
36753 /* The sequence ID from the original command. */
36755 /* The length of the response data in number of bytes. */
36757 /* Control flags. */
36759 /* Indicates the flow direction. */
36760 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
36762 /* If this bit set to 0, then it indicates rx flow. */
36763 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
36765 /* If this bit is set to 1, then it indicates that tx flow. */
36766 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
36768 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
36769 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
36770 /* When set to 1, all offloaded flows will be sent to EXT EM. */
36771 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
36773 /* The number of entries the FW has configured for EXT EM. */
36774 uint32_t num_entries;
36775 /* Configured EXT EM with the given context if for KEY0 table. */
36776 uint16_t key0_ctx_id;
36777 /* Configured EXT EM with the given context if for KEY1 table. */
36778 uint16_t key1_ctx_id;
36779 /* Configured EXT EM with the given context if for RECORD table. */
36780 uint16_t record_ctx_id;
36781 /* Configured EXT EM with the given context if for EFC table. */
36782 uint16_t efc_ctx_id;
36783 /* Configured EXT EM with the given context if for EFC table. */
36784 uint16_t fid_ctx_id;
36786 uint8_t unused0[5];
36788 * This field is used in Output records to indicate that the
36789 * output is completely written to RAM. This field should be
36790 * read as '1' to indicate that the output has been
36791 * completely written. When writing a command completion or
36792 * response to an internal processor, the order of writes has
36793 * to be such that this field is written last.
36798 /*********************
36799 * hwrm_tf_em_insert *
36800 *********************/
36803 /* hwrm_tf_em_insert_input (size:832b/104B) */
36804 struct hwrm_tf_em_insert_input {
36805 /* The HWRM command request type. */
36808 * The completion ring to send the completion event on. This should
36809 * be the NQ ID returned from the `nq_alloc` HWRM command.
36811 uint16_t cmpl_ring;
36813 * The sequence ID is used by the driver for tracking multiple
36814 * commands. This ID is treated as opaque data by the firmware and
36815 * the value is returned in the `hwrm_resp_hdr` upon completion.
36819 * The target ID of the command:
36820 * * 0x0-0xFFF8 - The function ID
36821 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36822 * * 0xFFFD - Reserved for user-space HWRM interface
36825 uint16_t target_id;
36827 * A physical address pointer pointing to a host buffer that the
36828 * command's response data will be written. This can be either a host
36829 * physical address (HPA) or a guest physical address (GPA) and must
36830 * point to a physically contiguous block of memory.
36832 uint64_t resp_addr;
36833 /* Firmware Session Id. */
36834 uint32_t fw_session_id;
36835 /* Control Flags. */
36837 /* Indicates the flow direction. */
36838 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
36839 /* If this bit set to 0, then it indicates rx flow. */
36840 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36841 /* If this bit is set to 1, then it indicates that tx flow. */
36842 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36843 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
36844 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
36845 /* Reported match strength. */
36847 /* Index to action. */
36848 uint32_t action_ptr;
36849 /* Index of EM record. */
36850 uint32_t em_record_idx;
36851 /* EM Key value. */
36852 uint64_t em_key[8];
36853 /* Number of bits in em_key. */
36854 uint16_t em_key_bitlen;
36856 uint16_t unused0[3];
36859 /* hwrm_tf_em_insert_output (size:128b/16B) */
36860 struct hwrm_tf_em_insert_output {
36861 /* The specific error status for the command. */
36862 uint16_t error_code;
36863 /* The HWRM command request type. */
36865 /* The sequence ID from the original command. */
36867 /* The length of the response data in number of bytes. */
36869 /* EM record pointer index. */
36870 uint16_t rptr_index;
36871 /* EM record offset 0~3. */
36872 uint8_t rptr_entry;
36873 /* Number of word entries consumed by the key. */
36874 uint8_t num_of_entries;
36879 /*********************
36880 * hwrm_tf_em_delete *
36881 *********************/
36884 /* hwrm_tf_em_delete_input (size:832b/104B) */
36885 struct hwrm_tf_em_delete_input {
36886 /* The HWRM command request type. */
36889 * The completion ring to send the completion event on. This should
36890 * be the NQ ID returned from the `nq_alloc` HWRM command.
36892 uint16_t cmpl_ring;
36894 * The sequence ID is used by the driver for tracking multiple
36895 * commands. This ID is treated as opaque data by the firmware and
36896 * the value is returned in the `hwrm_resp_hdr` upon completion.
36900 * The target ID of the command:
36901 * * 0x0-0xFFF8 - The function ID
36902 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36903 * * 0xFFFD - Reserved for user-space HWRM interface
36906 uint16_t target_id;
36908 * A physical address pointer pointing to a host buffer that the
36909 * command's response data will be written. This can be either a host
36910 * physical address (HPA) or a guest physical address (GPA) and must
36911 * point to a physically contiguous block of memory.
36913 uint64_t resp_addr;
36915 uint32_t fw_session_id;
36916 /* Control flags. */
36918 /* Indicates the flow direction. */
36919 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
36920 /* If this bit set to 0, then it indicates rx flow. */
36921 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36922 /* If this bit is set to 1, then it indicates that tx flow. */
36923 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36924 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
36925 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
36928 /* EM internal flow hanndle. */
36929 uint64_t flow_handle;
36931 uint64_t em_key[8];
36932 /* Number of bits in em_key. */
36933 uint16_t em_key_bitlen;
36935 uint16_t unused1[3];
36938 /* hwrm_tf_em_delete_output (size:128b/16B) */
36939 struct hwrm_tf_em_delete_output {
36940 /* The specific error status for the command. */
36941 uint16_t error_code;
36942 /* The HWRM command request type. */
36944 /* The sequence ID from the original command. */
36946 /* The length of the response data in number of bytes. */
36948 /* Original stack allocation index. */
36951 uint16_t unused0[3];
36954 /********************
36955 * hwrm_tf_tcam_set *
36956 ********************/
36959 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
36960 struct hwrm_tf_tcam_set_input {
36961 /* The HWRM command request type. */
36964 * The completion ring to send the completion event on. This should
36965 * be the NQ ID returned from the `nq_alloc` HWRM command.
36967 uint16_t cmpl_ring;
36969 * The sequence ID is used by the driver for tracking multiple
36970 * commands. This ID is treated as opaque data by the firmware and
36971 * the value is returned in the `hwrm_resp_hdr` upon completion.
36975 * The target ID of the command:
36976 * * 0x0-0xFFF8 - The function ID
36977 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36978 * * 0xFFFD - Reserved for user-space HWRM interface
36981 uint16_t target_id;
36983 * A physical address pointer pointing to a host buffer that the
36984 * command's response data will be written. This can be either a host
36985 * physical address (HPA) or a guest physical address (GPA) and must
36986 * point to a physically contiguous block of memory.
36988 uint64_t resp_addr;
36989 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
36990 uint32_t fw_session_id;
36991 /* Control flags. */
36993 /* Indicates the flow direction. */
36994 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
36995 /* If this bit set to 0, then it indicates rx flow. */
36996 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
36997 /* If this bit is set to 1, then it indicates that tx flow. */
36998 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
36999 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
37000 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
37002 * Indicate device data is being sent via DMA, the device
37003 * data is packing does not change.
37005 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
37007 * TCAM type of the resource, defined globally in the
37008 * hwrm_tf_resc_type enum.
37011 /* Index of TCAM entry. */
37013 /* Number of bytes in the TCAM key. */
37015 /* Number of bytes in the TCAM result. */
37016 uint8_t result_size;
37018 * Offset from which the mask bytes start in the device data
37019 * array, key offset is always 0.
37021 uint8_t mask_offset;
37022 /* Offset from which the result bytes start in the device data array. */
37023 uint8_t result_offset;
37025 uint8_t unused0[6];
37027 * TCAM key located at offset 0, mask located at mask_offsec
37028 * and result at result_offsec for the device.
37030 uint8_t dev_data[88];
37033 /* hwrm_tf_tcam_set_output (size:128b/16B) */
37034 struct hwrm_tf_tcam_set_output {
37035 /* The specific error status for the command. */
37036 uint16_t error_code;
37037 /* The HWRM command request type. */
37039 /* The sequence ID from the original command. */
37041 /* The length of the response data in number of bytes. */
37044 uint8_t unused0[7];
37046 * This field is used in Output records to indicate that the
37047 * output is completely written to RAM. This field should be
37048 * read as '1' to indicate that the output has been
37049 * completely written. When writing a command completion or
37050 * response to an internal processor, the order of writes has
37051 * to be such that this field is written last.
37056 /********************
37057 * hwrm_tf_tcam_get *
37058 ********************/
37061 /* hwrm_tf_tcam_get_input (size:256b/32B) */
37062 struct hwrm_tf_tcam_get_input {
37063 /* The HWRM command request type. */
37066 * The completion ring to send the completion event on. This should
37067 * be the NQ ID returned from the `nq_alloc` HWRM command.
37069 uint16_t cmpl_ring;
37071 * The sequence ID is used by the driver for tracking multiple
37072 * commands. This ID is treated as opaque data by the firmware and
37073 * the value is returned in the `hwrm_resp_hdr` upon completion.
37077 * The target ID of the command:
37078 * * 0x0-0xFFF8 - The function ID
37079 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37080 * * 0xFFFD - Reserved for user-space HWRM interface
37083 uint16_t target_id;
37085 * A physical address pointer pointing to a host buffer that the
37086 * command's response data will be written. This can be either a host
37087 * physical address (HPA) or a guest physical address (GPA) and must
37088 * point to a physically contiguous block of memory.
37090 uint64_t resp_addr;
37091 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37092 uint32_t fw_session_id;
37093 /* Control flags. */
37095 /* Indicates the flow direction. */
37096 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
37097 /* If this bit set to 0, then it indicates rx flow. */
37098 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37099 /* If this bit is set to 1, then it indicates that tx flow. */
37100 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37101 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
37102 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
37104 * TCAM type of the resource, defined globally in the
37105 * hwrm_tf_resc_type enum.
37108 /* Index of a TCAM entry. */
37114 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
37115 struct hwrm_tf_tcam_get_output {
37116 /* The specific error status for the command. */
37117 uint16_t error_code;
37118 /* The HWRM command request type. */
37120 /* The sequence ID from the original command. */
37122 /* The length of the response data in number of bytes. */
37124 /* Number of bytes in the TCAM key. */
37126 /* Number of bytes in the TCAM entry. */
37127 uint8_t result_size;
37128 /* Offset from which the mask bytes start in the device data array. */
37129 uint8_t mask_offset;
37130 /* Offset from which the result bytes start in the device data array. */
37131 uint8_t result_offset;
37133 uint8_t unused0[4];
37135 * TCAM key located at offset 0, mask located at mask_offsec
37136 * and result at result_offsec for the device.
37138 uint8_t dev_data[272];
37140 uint8_t unused1[7];
37142 * This field is used in Output records to indicate that the
37143 * output is completely written to RAM. This field should be
37144 * read as '1' to indicate that the output has been
37145 * completely written. When writing a command completion or
37146 * response to an internal processor, the order of writes has
37147 * to be such that this field is written last.
37152 /*********************
37153 * hwrm_tf_tcam_move *
37154 *********************/
37157 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
37158 struct hwrm_tf_tcam_move_input {
37159 /* The HWRM command request type. */
37162 * The completion ring to send the completion event on. This should
37163 * be the NQ ID returned from the `nq_alloc` HWRM command.
37165 uint16_t cmpl_ring;
37167 * The sequence ID is used by the driver for tracking multiple
37168 * commands. This ID is treated as opaque data by the firmware and
37169 * the value is returned in the `hwrm_resp_hdr` upon completion.
37173 * The target ID of the command:
37174 * * 0x0-0xFFF8 - The function ID
37175 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37176 * * 0xFFFD - Reserved for user-space HWRM interface
37179 uint16_t target_id;
37181 * A physical address pointer pointing to a host buffer that the
37182 * command's response data will be written. This can be either a host
37183 * physical address (HPA) or a guest physical address (GPA) and must
37184 * point to a physically contiguous block of memory.
37186 uint64_t resp_addr;
37187 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37188 uint32_t fw_session_id;
37189 /* Control flags. */
37191 /* Indicates the flow direction. */
37192 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
37193 /* If this bit set to 0, then it indicates rx flow. */
37194 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37195 /* If this bit is set to 1, then it indicates that tx flow. */
37196 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37197 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
37198 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
37200 * TCAM type of the resource, defined globally in the
37201 * hwrm_tf_resc_type enum.
37204 /* Number of TCAM index pairs to be swapped for the device. */
37208 /* TCAM index pairs to be swapped for the device. */
37209 uint16_t idx_pairs[48];
37212 /* hwrm_tf_tcam_move_output (size:128b/16B) */
37213 struct hwrm_tf_tcam_move_output {
37214 /* The specific error status for the command. */
37215 uint16_t error_code;
37216 /* The HWRM command request type. */
37218 /* The sequence ID from the original command. */
37220 /* The length of the response data in number of bytes. */
37223 uint8_t unused0[7];
37225 * This field is used in Output records to indicate that the
37226 * output is completely written to RAM. This field should be
37227 * read as '1' to indicate that the output has been
37228 * completely written. When writing a command completion or
37229 * response to an internal processor, the order of writes has
37230 * to be such that this field is written last.
37235 /*********************
37236 * hwrm_tf_tcam_free *
37237 *********************/
37240 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
37241 struct hwrm_tf_tcam_free_input {
37242 /* The HWRM command request type. */
37245 * The completion ring to send the completion event on. This should
37246 * be the NQ ID returned from the `nq_alloc` HWRM command.
37248 uint16_t cmpl_ring;
37250 * The sequence ID is used by the driver for tracking multiple
37251 * commands. This ID is treated as opaque data by the firmware and
37252 * the value is returned in the `hwrm_resp_hdr` upon completion.
37256 * The target ID of the command:
37257 * * 0x0-0xFFF8 - The function ID
37258 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37259 * * 0xFFFD - Reserved for user-space HWRM interface
37262 uint16_t target_id;
37264 * A physical address pointer pointing to a host buffer that the
37265 * command's response data will be written. This can be either a host
37266 * physical address (HPA) or a guest physical address (GPA) and must
37267 * point to a physically contiguous block of memory.
37269 uint64_t resp_addr;
37270 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37271 uint32_t fw_session_id;
37272 /* Control flags. */
37274 /* Indicates the flow direction. */
37275 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
37276 /* If this bit set to 0, then it indicates rx flow. */
37277 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37278 /* If this bit is set to 1, then it indicates that tx flow. */
37279 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37280 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
37281 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
37283 * TCAM type of the resource, defined globally in the
37284 * hwrm_tf_resc_type enum.
37287 /* Number of TCAM index to be deleted for the device. */
37291 /* TCAM index list to be deleted for the device. */
37292 uint16_t idx_list[48];
37295 /* hwrm_tf_tcam_free_output (size:128b/16B) */
37296 struct hwrm_tf_tcam_free_output {
37297 /* The specific error status for the command. */
37298 uint16_t error_code;
37299 /* The HWRM command request type. */
37301 /* The sequence ID from the original command. */
37303 /* The length of the response data in number of bytes. */
37306 uint8_t unused0[7];
37308 * This field is used in Output records to indicate that the
37309 * output is completely written to RAM. This field should be
37310 * read as '1' to indicate that the output has been
37311 * completely written. When writing a command completion or
37312 * response to an internal processor, the order of writes has
37313 * to be such that this field is written last.
37318 /******************************
37319 * hwrm_tunnel_dst_port_query *
37320 ******************************/
37323 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
37324 struct hwrm_tunnel_dst_port_query_input {
37325 /* The HWRM command request type. */
37328 * The completion ring to send the completion event on. This should
37329 * be the NQ ID returned from the `nq_alloc` HWRM command.
37331 uint16_t cmpl_ring;
37333 * The sequence ID is used by the driver for tracking multiple
37334 * commands. This ID is treated as opaque data by the firmware and
37335 * the value is returned in the `hwrm_resp_hdr` upon completion.
37339 * The target ID of the command:
37340 * * 0x0-0xFFF8 - The function ID
37341 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37342 * * 0xFFFD - Reserved for user-space HWRM interface
37345 uint16_t target_id;
37347 * A physical address pointer pointing to a host buffer that the
37348 * command's response data will be written. This can be either a host
37349 * physical address (HPA) or a guest physical address (GPA) and must
37350 * point to a physically contiguous block of memory.
37352 uint64_t resp_addr;
37354 uint8_t tunnel_type;
37355 /* Virtual eXtensible Local Area Network (VXLAN) */
37356 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
37358 /* Generic Network Virtualization Encapsulation (Geneve) */
37359 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
37361 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37362 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37364 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
37365 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37367 /* Use fixed layer 2 ether type of 0xFFFF */
37368 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
37370 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
37371 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37373 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
37374 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
37375 uint8_t unused_0[7];
37378 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
37379 struct hwrm_tunnel_dst_port_query_output {
37380 /* The specific error status for the command. */
37381 uint16_t error_code;
37382 /* The HWRM command request type. */
37384 /* The sequence ID from the original command. */
37386 /* The length of the response data in number of bytes. */
37389 * This field represents the identifier of L4 destination port
37390 * used for the given tunnel type. This field is valid for
37391 * specific tunnel types that use layer 4 (e.g. UDP)
37392 * transports for tunneling.
37394 uint16_t tunnel_dst_port_id;
37396 * This field represents the value of L4 destination port
37397 * identified by tunnel_dst_port_id. This field is valid for
37398 * specific tunnel types that use layer 4 (e.g. UDP)
37399 * transports for tunneling.
37400 * This field is in network byte order.
37402 * A value of 0 means that the destination port is not
37405 uint16_t tunnel_dst_port_val;
37406 uint8_t unused_0[3];
37408 * This field is used in Output records to indicate that the output
37409 * is completely written to RAM. This field should be read as '1'
37410 * to indicate that the output has been completely written.
37411 * When writing a command completion or response to an internal processor,
37412 * the order of writes has to be such that this field is written last.
37417 /******************************
37418 * hwrm_tunnel_dst_port_alloc *
37419 ******************************/
37422 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
37423 struct hwrm_tunnel_dst_port_alloc_input {
37424 /* The HWRM command request type. */
37427 * The completion ring to send the completion event on. This should
37428 * be the NQ ID returned from the `nq_alloc` HWRM command.
37430 uint16_t cmpl_ring;
37432 * The sequence ID is used by the driver for tracking multiple
37433 * commands. This ID is treated as opaque data by the firmware and
37434 * the value is returned in the `hwrm_resp_hdr` upon completion.
37438 * The target ID of the command:
37439 * * 0x0-0xFFF8 - The function ID
37440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37441 * * 0xFFFD - Reserved for user-space HWRM interface
37444 uint16_t target_id;
37446 * A physical address pointer pointing to a host buffer that the
37447 * command's response data will be written. This can be either a host
37448 * physical address (HPA) or a guest physical address (GPA) and must
37449 * point to a physically contiguous block of memory.
37451 uint64_t resp_addr;
37453 uint8_t tunnel_type;
37454 /* Virtual eXtensible Local Area Network (VXLAN) */
37455 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
37457 /* Generic Network Virtualization Encapsulation (Geneve) */
37458 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
37460 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37461 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37463 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
37464 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37466 /* Use fixed layer 2 ether type of 0xFFFF */
37467 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
37469 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
37470 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37472 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
37473 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
37476 * This field represents the value of L4 destination port used
37477 * for the given tunnel type. This field is valid for
37478 * specific tunnel types that use layer 4 (e.g. UDP)
37479 * transports for tunneling.
37481 * This field is in network byte order.
37483 * A value of 0 shall fail the command.
37485 uint16_t tunnel_dst_port_val;
37486 uint8_t unused_1[4];
37489 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
37490 struct hwrm_tunnel_dst_port_alloc_output {
37491 /* The specific error status for the command. */
37492 uint16_t error_code;
37493 /* The HWRM command request type. */
37495 /* The sequence ID from the original command. */
37497 /* The length of the response data in number of bytes. */
37500 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
37501 * types that has l4 destination port parameters.
37503 uint16_t tunnel_dst_port_id;
37504 uint8_t unused_0[5];
37506 * This field is used in Output records to indicate that the output
37507 * is completely written to RAM. This field should be read as '1'
37508 * to indicate that the output has been completely written.
37509 * When writing a command completion or response to an internal processor,
37510 * the order of writes has to be such that this field is written last.
37515 /*****************************
37516 * hwrm_tunnel_dst_port_free *
37517 *****************************/
37520 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
37521 struct hwrm_tunnel_dst_port_free_input {
37522 /* The HWRM command request type. */
37525 * The completion ring to send the completion event on. This should
37526 * be the NQ ID returned from the `nq_alloc` HWRM command.
37528 uint16_t cmpl_ring;
37530 * The sequence ID is used by the driver for tracking multiple
37531 * commands. This ID is treated as opaque data by the firmware and
37532 * the value is returned in the `hwrm_resp_hdr` upon completion.
37536 * The target ID of the command:
37537 * * 0x0-0xFFF8 - The function ID
37538 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37539 * * 0xFFFD - Reserved for user-space HWRM interface
37542 uint16_t target_id;
37544 * A physical address pointer pointing to a host buffer that the
37545 * command's response data will be written. This can be either a host
37546 * physical address (HPA) or a guest physical address (GPA) and must
37547 * point to a physically contiguous block of memory.
37549 uint64_t resp_addr;
37551 uint8_t tunnel_type;
37552 /* Virtual eXtensible Local Area Network (VXLAN) */
37553 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
37555 /* Generic Network Virtualization Encapsulation (Geneve) */
37556 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
37558 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37559 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37561 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
37562 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37564 /* Use fixed layer 2 ether type of 0xFFFF */
37565 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
37567 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
37568 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37570 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
37571 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
37574 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
37575 * types that has l4 destination port parameters.
37577 uint16_t tunnel_dst_port_id;
37578 uint8_t unused_1[4];
37581 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
37582 struct hwrm_tunnel_dst_port_free_output {
37583 /* The specific error status for the command. */
37584 uint16_t error_code;
37585 /* The HWRM command request type. */
37587 /* The sequence ID from the original command. */
37589 /* The length of the response data in number of bytes. */
37591 uint8_t unused_1[7];
37593 * This field is used in Output records to indicate that the output
37594 * is completely written to RAM. This field should be read as '1'
37595 * to indicate that the output has been completely written.
37596 * When writing a command completion or response to an internal processor,
37597 * the order of writes has to be such that this field is written last.
37602 /* Periodic statistics context DMA to host. */
37603 /* ctx_hw_stats (size:1280b/160B) */
37604 struct ctx_hw_stats {
37605 /* Number of received unicast packets */
37606 uint64_t rx_ucast_pkts;
37607 /* Number of received multicast packets */
37608 uint64_t rx_mcast_pkts;
37609 /* Number of received broadcast packets */
37610 uint64_t rx_bcast_pkts;
37611 /* Number of discarded packets on receive path */
37612 uint64_t rx_discard_pkts;
37613 /* Number of packets on receive path with error */
37614 uint64_t rx_error_pkts;
37615 /* Number of received bytes for unicast traffic */
37616 uint64_t rx_ucast_bytes;
37617 /* Number of received bytes for multicast traffic */
37618 uint64_t rx_mcast_bytes;
37619 /* Number of received bytes for broadcast traffic */
37620 uint64_t rx_bcast_bytes;
37621 /* Number of transmitted unicast packets */
37622 uint64_t tx_ucast_pkts;
37623 /* Number of transmitted multicast packets */
37624 uint64_t tx_mcast_pkts;
37625 /* Number of transmitted broadcast packets */
37626 uint64_t tx_bcast_pkts;
37627 /* Number of packets on transmit path with error */
37628 uint64_t tx_error_pkts;
37629 /* Number of discarded packets on transmit path */
37630 uint64_t tx_discard_pkts;
37631 /* Number of transmitted bytes for unicast traffic */
37632 uint64_t tx_ucast_bytes;
37633 /* Number of transmitted bytes for multicast traffic */
37634 uint64_t tx_mcast_bytes;
37635 /* Number of transmitted bytes for broadcast traffic */
37636 uint64_t tx_bcast_bytes;
37637 /* Number of TPA packets */
37639 /* Number of TPA bytes */
37640 uint64_t tpa_bytes;
37641 /* Number of TPA events */
37642 uint64_t tpa_events;
37643 /* Number of TPA aborts */
37644 uint64_t tpa_aborts;
37648 * Extended periodic statistics context DMA to host. On cards that
37649 * support TPA v2, additional TPA related stats exist and can be retrieved
37650 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
37652 /* ctx_hw_stats_ext (size:1344b/168B) */
37653 struct ctx_hw_stats_ext {
37654 /* Number of received unicast packets */
37655 uint64_t rx_ucast_pkts;
37656 /* Number of received multicast packets */
37657 uint64_t rx_mcast_pkts;
37658 /* Number of received broadcast packets */
37659 uint64_t rx_bcast_pkts;
37660 /* Number of discarded packets on receive path */
37661 uint64_t rx_discard_pkts;
37662 /* Number of packets on receive path with error */
37663 uint64_t rx_error_pkts;
37664 /* Number of received bytes for unicast traffic */
37665 uint64_t rx_ucast_bytes;
37666 /* Number of received bytes for multicast traffic */
37667 uint64_t rx_mcast_bytes;
37668 /* Number of received bytes for broadcast traffic */
37669 uint64_t rx_bcast_bytes;
37670 /* Number of transmitted unicast packets */
37671 uint64_t tx_ucast_pkts;
37672 /* Number of transmitted multicast packets */
37673 uint64_t tx_mcast_pkts;
37674 /* Number of transmitted broadcast packets */
37675 uint64_t tx_bcast_pkts;
37676 /* Number of packets on transmit path with error */
37677 uint64_t tx_error_pkts;
37678 /* Number of discarded packets on transmit path */
37679 uint64_t tx_discard_pkts;
37680 /* Number of transmitted bytes for unicast traffic */
37681 uint64_t tx_ucast_bytes;
37682 /* Number of transmitted bytes for multicast traffic */
37683 uint64_t tx_mcast_bytes;
37684 /* Number of transmitted bytes for broadcast traffic */
37685 uint64_t tx_bcast_bytes;
37686 /* Number of TPA eligible packets */
37687 uint64_t rx_tpa_eligible_pkt;
37688 /* Number of TPA eligible bytes */
37689 uint64_t rx_tpa_eligible_bytes;
37690 /* Number of TPA packets */
37691 uint64_t rx_tpa_pkt;
37692 /* Number of TPA bytes */
37693 uint64_t rx_tpa_bytes;
37694 /* Number of TPA errors */
37695 uint64_t rx_tpa_errors;
37698 /* Periodic Engine statistics context DMA to host. */
37699 /* ctx_eng_stats (size:512b/64B) */
37700 struct ctx_eng_stats {
37702 * Count of data bytes into the Engine.
37703 * This includes any user supplied prefix,
37704 * but does not include any predefined
37707 uint64_t eng_bytes_in;
37708 /* Count of data bytes out of the Engine. */
37709 uint64_t eng_bytes_out;
37711 * Count, in 4-byte (dword) units, of bytes
37712 * that are input as auxiliary data.
37713 * This includes the aux_cmd data.
37715 uint64_t aux_bytes_in;
37717 * Count, in 4-byte (dword) units, of bytes
37718 * that are output as auxiliary data.
37719 * This count is the buffer space for aux_data
37720 * output provided in the RQE, not the actual
37723 uint64_t aux_bytes_out;
37724 /* Count of number of commands executed. */
37727 * Count of number of error commands.
37728 * These are the commands with a
37729 * non-zero status value.
37731 uint64_t error_commands;
37733 * Compression/Encryption Engine usage,
37734 * the unit is count of clock cycles
37736 uint64_t cce_engine_usage;
37738 * De-Compression/De-cryption Engine usage,
37739 * the unit is count of clock cycles
37741 uint64_t cdd_engine_usage;
37744 /***********************
37745 * hwrm_stat_ctx_alloc *
37746 ***********************/
37749 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
37750 struct hwrm_stat_ctx_alloc_input {
37751 /* The HWRM command request type. */
37754 * The completion ring to send the completion event on. This should
37755 * be the NQ ID returned from the `nq_alloc` HWRM command.
37757 uint16_t cmpl_ring;
37759 * The sequence ID is used by the driver for tracking multiple
37760 * commands. This ID is treated as opaque data by the firmware and
37761 * the value is returned in the `hwrm_resp_hdr` upon completion.
37765 * The target ID of the command:
37766 * * 0x0-0xFFF8 - The function ID
37767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37768 * * 0xFFFD - Reserved for user-space HWRM interface
37771 uint16_t target_id;
37773 * A physical address pointer pointing to a host buffer that the
37774 * command's response data will be written. This can be either a host
37775 * physical address (HPA) or a guest physical address (GPA) and must
37776 * point to a physically contiguous block of memory.
37778 uint64_t resp_addr;
37780 * This is the address for statistic block.
37781 * > For new versions of the chip, this address should be 128B
37784 uint64_t stats_dma_addr;
37786 * The statistic block update period in ms.
37787 * e.g. 250ms, 500ms, 750ms, 1000ms.
37788 * If update_period_ms is 0, then the stats update
37789 * shall be never done and the DMA address shall not be used.
37790 * In this case, the stat block can only be read by
37791 * hwrm_stat_ctx_query command.
37792 * On Ethernet/L2 based devices:
37793 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
37794 * ctx_hw_stats_ext is used for DMA,
37796 * ctx_hw_stats is used for DMA.
37798 uint32_t update_period_ms;
37800 * This field is used to specify statistics context specific
37801 * configuration flags.
37803 uint8_t stat_ctx_flags;
37805 * When this bit is set to '1', the statistics context shall be
37806 * allocated for RoCE traffic only. In this case, traffic other
37807 * than offloaded RoCE traffic shall not be included in this
37808 * statistic context.
37809 * When this bit is set to '0', the statistics context shall be
37810 * used for network traffic or engine traffic.
37812 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
37815 * This is the size of the structure (ctx_hw_stats or
37816 * ctx_hw_stats_ext) that the driver has allocated to be used
37817 * for the periodic DMA updates.
37819 uint16_t stats_dma_length;
37822 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
37823 struct hwrm_stat_ctx_alloc_output {
37824 /* The specific error status for the command. */
37825 uint16_t error_code;
37826 /* The HWRM command request type. */
37828 /* The sequence ID from the original command. */
37830 /* The length of the response data in number of bytes. */
37832 /* This is the statistics context ID value. */
37833 uint32_t stat_ctx_id;
37834 uint8_t unused_0[3];
37836 * This field is used in Output records to indicate that the output
37837 * is completely written to RAM. This field should be read as '1'
37838 * to indicate that the output has been completely written.
37839 * When writing a command completion or response to an internal processor,
37840 * the order of writes has to be such that this field is written last.
37845 /**********************
37846 * hwrm_stat_ctx_free *
37847 **********************/
37850 /* hwrm_stat_ctx_free_input (size:192b/24B) */
37851 struct hwrm_stat_ctx_free_input {
37852 /* The HWRM command request type. */
37855 * The completion ring to send the completion event on. This should
37856 * be the NQ ID returned from the `nq_alloc` HWRM command.
37858 uint16_t cmpl_ring;
37860 * The sequence ID is used by the driver for tracking multiple
37861 * commands. This ID is treated as opaque data by the firmware and
37862 * the value is returned in the `hwrm_resp_hdr` upon completion.
37866 * The target ID of the command:
37867 * * 0x0-0xFFF8 - The function ID
37868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37869 * * 0xFFFD - Reserved for user-space HWRM interface
37872 uint16_t target_id;
37874 * A physical address pointer pointing to a host buffer that the
37875 * command's response data will be written. This can be either a host
37876 * physical address (HPA) or a guest physical address (GPA) and must
37877 * point to a physically contiguous block of memory.
37879 uint64_t resp_addr;
37880 /* ID of the statistics context that is being queried. */
37881 uint32_t stat_ctx_id;
37882 uint8_t unused_0[4];
37885 /* hwrm_stat_ctx_free_output (size:128b/16B) */
37886 struct hwrm_stat_ctx_free_output {
37887 /* The specific error status for the command. */
37888 uint16_t error_code;
37889 /* The HWRM command request type. */
37891 /* The sequence ID from the original command. */
37893 /* The length of the response data in number of bytes. */
37895 /* This is the statistics context ID value. */
37896 uint32_t stat_ctx_id;
37897 uint8_t unused_0[3];
37899 * This field is used in Output records to indicate that the output
37900 * is completely written to RAM. This field should be read as '1'
37901 * to indicate that the output has been completely written.
37902 * When writing a command completion or response to an internal processor,
37903 * the order of writes has to be such that this field is written last.
37908 /***********************
37909 * hwrm_stat_ctx_query *
37910 ***********************/
37913 /* hwrm_stat_ctx_query_input (size:192b/24B) */
37914 struct hwrm_stat_ctx_query_input {
37915 /* The HWRM command request type. */
37918 * The completion ring to send the completion event on. This should
37919 * be the NQ ID returned from the `nq_alloc` HWRM command.
37921 uint16_t cmpl_ring;
37923 * The sequence ID is used by the driver for tracking multiple
37924 * commands. This ID is treated as opaque data by the firmware and
37925 * the value is returned in the `hwrm_resp_hdr` upon completion.
37929 * The target ID of the command:
37930 * * 0x0-0xFFF8 - The function ID
37931 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37932 * * 0xFFFD - Reserved for user-space HWRM interface
37935 uint16_t target_id;
37937 * A physical address pointer pointing to a host buffer that the
37938 * command's response data will be written. This can be either a host
37939 * physical address (HPA) or a guest physical address (GPA) and must
37940 * point to a physically contiguous block of memory.
37942 uint64_t resp_addr;
37943 /* ID of the statistics context that is being queried. */
37944 uint32_t stat_ctx_id;
37947 * This bit is set to 1 when request is for a counter mask,
37948 * representing the width of each of the stats counters, rather
37949 * than counters themselves.
37951 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
37952 uint8_t unused_0[3];
37955 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
37956 struct hwrm_stat_ctx_query_output {
37957 /* The specific error status for the command. */
37958 uint16_t error_code;
37959 /* The HWRM command request type. */
37961 /* The sequence ID from the original command. */
37963 /* The length of the response data in number of bytes. */
37965 /* Number of transmitted unicast packets */
37966 uint64_t tx_ucast_pkts;
37967 /* Number of transmitted multicast packets */
37968 uint64_t tx_mcast_pkts;
37969 /* Number of transmitted broadcast packets */
37970 uint64_t tx_bcast_pkts;
37971 /* Number of transmitted packets with error */
37972 uint64_t tx_err_pkts;
37973 /* Number of dropped packets on transmit path */
37974 uint64_t tx_drop_pkts;
37975 /* Number of transmitted bytes for unicast traffic */
37976 uint64_t tx_ucast_bytes;
37977 /* Number of transmitted bytes for multicast traffic */
37978 uint64_t tx_mcast_bytes;
37979 /* Number of transmitted bytes for broadcast traffic */
37980 uint64_t tx_bcast_bytes;
37981 /* Number of received unicast packets */
37982 uint64_t rx_ucast_pkts;
37983 /* Number of received multicast packets */
37984 uint64_t rx_mcast_pkts;
37985 /* Number of received broadcast packets */
37986 uint64_t rx_bcast_pkts;
37987 /* Number of received packets with error */
37988 uint64_t rx_err_pkts;
37989 /* Number of dropped packets on receive path */
37990 uint64_t rx_drop_pkts;
37991 /* Number of received bytes for unicast traffic */
37992 uint64_t rx_ucast_bytes;
37993 /* Number of received bytes for multicast traffic */
37994 uint64_t rx_mcast_bytes;
37995 /* Number of received bytes for broadcast traffic */
37996 uint64_t rx_bcast_bytes;
37997 /* Number of aggregated unicast packets */
37998 uint64_t rx_agg_pkts;
37999 /* Number of aggregated unicast bytes */
38000 uint64_t rx_agg_bytes;
38001 /* Number of aggregation events */
38002 uint64_t rx_agg_events;
38003 /* Number of aborted aggregations */
38004 uint64_t rx_agg_aborts;
38005 uint8_t unused_0[7];
38007 * This field is used in Output records to indicate that the output
38008 * is completely written to RAM. This field should be read as '1'
38009 * to indicate that the output has been completely written.
38010 * When writing a command completion or response to an internal processor,
38011 * the order of writes has to be such that this field is written last.
38016 /***************************
38017 * hwrm_stat_ext_ctx_query *
38018 ***************************/
38021 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
38022 struct hwrm_stat_ext_ctx_query_input {
38023 /* The HWRM command request type. */
38026 * The completion ring to send the completion event on. This should
38027 * be the NQ ID returned from the `nq_alloc` HWRM command.
38029 uint16_t cmpl_ring;
38031 * The sequence ID is used by the driver for tracking multiple
38032 * commands. This ID is treated as opaque data by the firmware and
38033 * the value is returned in the `hwrm_resp_hdr` upon completion.
38037 * The target ID of the command:
38038 * * 0x0-0xFFF8 - The function ID
38039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38040 * * 0xFFFD - Reserved for user-space HWRM interface
38043 uint16_t target_id;
38045 * A physical address pointer pointing to a host buffer that the
38046 * command's response data will be written. This can be either a host
38047 * physical address (HPA) or a guest physical address (GPA) and must
38048 * point to a physically contiguous block of memory.
38050 uint64_t resp_addr;
38051 /* ID of the extended statistics context that is being queried. */
38052 uint32_t stat_ctx_id;
38055 * This bit is set to 1 when request is for a counter mask,
38056 * representing the width of each of the stats counters, rather
38057 * than counters themselves.
38059 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
38061 uint8_t unused_0[3];
38064 /* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
38065 struct hwrm_stat_ext_ctx_query_output {
38066 /* The specific error status for the command. */
38067 uint16_t error_code;
38068 /* The HWRM command request type. */
38070 /* The sequence ID from the original command. */
38072 /* The length of the response data in number of bytes. */
38074 /* Number of received unicast packets */
38075 uint64_t rx_ucast_pkts;
38076 /* Number of received multicast packets */
38077 uint64_t rx_mcast_pkts;
38078 /* Number of received broadcast packets */
38079 uint64_t rx_bcast_pkts;
38080 /* Number of discarded packets on receive path */
38081 uint64_t rx_discard_pkts;
38082 /* Number of packets on receive path with error */
38083 uint64_t rx_error_pkts;
38084 /* Number of received bytes for unicast traffic */
38085 uint64_t rx_ucast_bytes;
38086 /* Number of received bytes for multicast traffic */
38087 uint64_t rx_mcast_bytes;
38088 /* Number of received bytes for broadcast traffic */
38089 uint64_t rx_bcast_bytes;
38090 /* Number of transmitted unicast packets */
38091 uint64_t tx_ucast_pkts;
38092 /* Number of transmitted multicast packets */
38093 uint64_t tx_mcast_pkts;
38094 /* Number of transmitted broadcast packets */
38095 uint64_t tx_bcast_pkts;
38096 /* Number of packets on transmit path with error */
38097 uint64_t tx_error_pkts;
38098 /* Number of discarded packets on transmit path */
38099 uint64_t tx_discard_pkts;
38100 /* Number of transmitted bytes for unicast traffic */
38101 uint64_t tx_ucast_bytes;
38102 /* Number of transmitted bytes for multicast traffic */
38103 uint64_t tx_mcast_bytes;
38104 /* Number of transmitted bytes for broadcast traffic */
38105 uint64_t tx_bcast_bytes;
38106 /* Number of TPA eligible packets */
38107 uint64_t rx_tpa_eligible_pkt;
38108 /* Number of TPA eligible bytes */
38109 uint64_t rx_tpa_eligible_bytes;
38110 /* Number of TPA packets */
38111 uint64_t rx_tpa_pkt;
38112 /* Number of TPA bytes */
38113 uint64_t rx_tpa_bytes;
38114 /* Number of TPA errors */
38115 uint64_t rx_tpa_errors;
38116 uint8_t unused_0[7];
38118 * This field is used in Output records to indicate that the output
38119 * is completely written to RAM. This field should be read as '1'
38120 * to indicate that the output has been completely written.
38121 * When writing a command completion or response to an internal processor,
38122 * the order of writes has to be such that this field is written last.
38127 /***************************
38128 * hwrm_stat_ctx_eng_query *
38129 ***************************/
38132 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
38133 struct hwrm_stat_ctx_eng_query_input {
38134 /* The HWRM command request type. */
38137 * The completion ring to send the completion event on. This should
38138 * be the NQ ID returned from the `nq_alloc` HWRM command.
38140 uint16_t cmpl_ring;
38142 * The sequence ID is used by the driver for tracking multiple
38143 * commands. This ID is treated as opaque data by the firmware and
38144 * the value is returned in the `hwrm_resp_hdr` upon completion.
38148 * The target ID of the command:
38149 * * 0x0-0xFFF8 - The function ID
38150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38151 * * 0xFFFD - Reserved for user-space HWRM interface
38154 uint16_t target_id;
38156 * A physical address pointer pointing to a host buffer that the
38157 * command's response data will be written. This can be either a host
38158 * physical address (HPA) or a guest physical address (GPA) and must
38159 * point to a physically contiguous block of memory.
38161 uint64_t resp_addr;
38162 /* ID of the statistics context that is being queried. */
38163 uint32_t stat_ctx_id;
38164 uint8_t unused_0[4];
38167 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
38168 struct hwrm_stat_ctx_eng_query_output {
38169 /* The specific error status for the command. */
38170 uint16_t error_code;
38171 /* The HWRM command request type. */
38173 /* The sequence ID from the original command. */
38175 /* The length of the response data in number of bytes. */
38178 * Count of data bytes into the Engine.
38179 * This includes any user supplied prefix,
38180 * but does not include any predefined
38183 uint64_t eng_bytes_in;
38184 /* Count of data bytes out of the Engine. */
38185 uint64_t eng_bytes_out;
38187 * Count, in 4-byte (dword) units, of bytes
38188 * that are input as auxiliary data.
38189 * This includes the aux_cmd data.
38191 uint64_t aux_bytes_in;
38193 * Count, in 4-byte (dword) units, of bytes
38194 * that are output as auxiliary data.
38195 * This count is the buffer space for aux_data
38196 * output provided in the RQE, not the actual
38199 uint64_t aux_bytes_out;
38200 /* Count of number of commands executed. */
38203 * Count of number of error commands.
38204 * These are the commands with a
38205 * non-zero status value.
38207 uint64_t error_commands;
38209 * Compression/Encryption Engine usage,
38210 * the unit is count of clock cycles
38212 uint64_t cce_engine_usage;
38214 * De-Compression/De-cryption Engine usage,
38215 * the unit is count of clock cycles
38217 uint64_t cdd_engine_usage;
38218 uint8_t unused_0[7];
38220 * This field is used in Output records to indicate that the output
38221 * is completely written to RAM. This field should be read as '1'
38222 * to indicate that the output has been completely written.
38223 * When writing a command completion or response to an internal processor,
38224 * the order of writes has to be such that this field is written last.
38229 /***************************
38230 * hwrm_stat_ctx_clr_stats *
38231 ***************************/
38234 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
38235 struct hwrm_stat_ctx_clr_stats_input {
38236 /* The HWRM command request type. */
38239 * The completion ring to send the completion event on. This should
38240 * be the NQ ID returned from the `nq_alloc` HWRM command.
38242 uint16_t cmpl_ring;
38244 * The sequence ID is used by the driver for tracking multiple
38245 * commands. This ID is treated as opaque data by the firmware and
38246 * the value is returned in the `hwrm_resp_hdr` upon completion.
38250 * The target ID of the command:
38251 * * 0x0-0xFFF8 - The function ID
38252 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38253 * * 0xFFFD - Reserved for user-space HWRM interface
38256 uint16_t target_id;
38258 * A physical address pointer pointing to a host buffer that the
38259 * command's response data will be written. This can be either a host
38260 * physical address (HPA) or a guest physical address (GPA) and must
38261 * point to a physically contiguous block of memory.
38263 uint64_t resp_addr;
38264 /* ID of the statistics context that is being queried. */
38265 uint32_t stat_ctx_id;
38266 uint8_t unused_0[4];
38269 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
38270 struct hwrm_stat_ctx_clr_stats_output {
38271 /* The specific error status for the command. */
38272 uint16_t error_code;
38273 /* The HWRM command request type. */
38275 /* The sequence ID from the original command. */
38277 /* The length of the response data in number of bytes. */
38279 uint8_t unused_0[7];
38281 * This field is used in Output records to indicate that the output
38282 * is completely written to RAM. This field should be read as '1'
38283 * to indicate that the output has been completely written.
38284 * When writing a command completion or response to an internal processor,
38285 * the order of writes has to be such that this field is written last.
38290 /********************
38291 * hwrm_pcie_qstats *
38292 ********************/
38295 /* hwrm_pcie_qstats_input (size:256b/32B) */
38296 struct hwrm_pcie_qstats_input {
38297 /* The HWRM command request type. */
38300 * The completion ring to send the completion event on. This should
38301 * be the NQ ID returned from the `nq_alloc` HWRM command.
38303 uint16_t cmpl_ring;
38305 * The sequence ID is used by the driver for tracking multiple
38306 * commands. This ID is treated as opaque data by the firmware and
38307 * the value is returned in the `hwrm_resp_hdr` upon completion.
38311 * The target ID of the command:
38312 * * 0x0-0xFFF8 - The function ID
38313 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38314 * * 0xFFFD - Reserved for user-space HWRM interface
38317 uint16_t target_id;
38319 * A physical address pointer pointing to a host buffer that the
38320 * command's response data will be written. This can be either a host
38321 * physical address (HPA) or a guest physical address (GPA) and must
38322 * point to a physically contiguous block of memory.
38324 uint64_t resp_addr;
38326 * The size of PCIe statistics block in bytes.
38327 * Firmware will DMA the PCIe statistics to
38328 * the host with this field size in the response.
38330 uint16_t pcie_stat_size;
38331 uint8_t unused_0[6];
38333 * This is the host address where
38334 * PCIe statistics will be stored
38336 uint64_t pcie_stat_host_addr;
38339 /* hwrm_pcie_qstats_output (size:128b/16B) */
38340 struct hwrm_pcie_qstats_output {
38341 /* The specific error status for the command. */
38342 uint16_t error_code;
38343 /* The HWRM command request type. */
38345 /* The sequence ID from the original command. */
38347 /* The length of the response data in number of bytes. */
38349 /* The size of PCIe statistics block in bytes. */
38350 uint16_t pcie_stat_size;
38351 uint8_t unused_0[5];
38353 * This field is used in Output records to indicate that the output
38354 * is completely written to RAM. This field should be read as '1'
38355 * to indicate that the output has been completely written.
38356 * When writing a command completion or response to an internal processor,
38357 * the order of writes has to be such that this field is written last.
38362 /* PCIe Statistics Formats */
38363 /* pcie_ctx_hw_stats (size:768b/96B) */
38364 struct pcie_ctx_hw_stats {
38365 /* Number of physical layer receiver errors */
38366 uint64_t pcie_pl_signal_integrity;
38367 /* Number of DLLP CRC errors detected by Data Link Layer */
38368 uint64_t pcie_dl_signal_integrity;
38370 * Number of TLP LCRC and sequence number errors detected
38371 * by Data Link Layer
38373 uint64_t pcie_tl_signal_integrity;
38374 /* Number of times LTSSM entered Recovery state */
38375 uint64_t pcie_link_integrity;
38376 /* Report number of TLP bits that have been transmitted in Mbps */
38377 uint64_t pcie_tx_traffic_rate;
38378 /* Report number of TLP bits that have been received in Mbps */
38379 uint64_t pcie_rx_traffic_rate;
38380 /* Number of DLLP bytes that have been transmitted */
38381 uint64_t pcie_tx_dllp_statistics;
38382 /* Number of DLLP bytes that have been received */
38383 uint64_t pcie_rx_dllp_statistics;
38385 * Number of times spent in each phase of gen3
38388 uint64_t pcie_equalization_time;
38389 /* Records the last 16 transitions of the LTSSM */
38390 uint32_t pcie_ltssm_histogram[4];
38392 * Record the last 8 reasons on why LTSSM transitioned
38395 uint64_t pcie_recovery_histogram;
38398 /**********************
38399 * hwrm_exec_fwd_resp *
38400 **********************/
38403 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
38404 struct hwrm_exec_fwd_resp_input {
38405 /* The HWRM command request type. */
38408 * The completion ring to send the completion event on. This should
38409 * be the NQ ID returned from the `nq_alloc` HWRM command.
38411 uint16_t cmpl_ring;
38413 * The sequence ID is used by the driver for tracking multiple
38414 * commands. This ID is treated as opaque data by the firmware and
38415 * the value is returned in the `hwrm_resp_hdr` upon completion.
38419 * The target ID of the command:
38420 * * 0x0-0xFFF8 - The function ID
38421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38422 * * 0xFFFD - Reserved for user-space HWRM interface
38425 uint16_t target_id;
38427 * A physical address pointer pointing to a host buffer that the
38428 * command's response data will be written. This can be either a host
38429 * physical address (HPA) or a guest physical address (GPA) and must
38430 * point to a physically contiguous block of memory.
38432 uint64_t resp_addr;
38434 * This is an encapsulated request. This request should
38435 * be executed by the HWRM and the response should be
38436 * provided in the response buffer inside the encapsulated
38439 uint32_t encap_request[26];
38441 * This value indicates the target id of the response to
38442 * the encapsulated request.
38443 * 0x0 - 0xFFF8 - Used for function ids
38444 * 0xFFF8 - 0xFFFE - Reserved for internal processors
38447 uint16_t encap_resp_target_id;
38448 uint8_t unused_0[6];
38451 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
38452 struct hwrm_exec_fwd_resp_output {
38453 /* The specific error status for the command. */
38454 uint16_t error_code;
38455 /* The HWRM command request type. */
38457 /* The sequence ID from the original command. */
38459 /* The length of the response data in number of bytes. */
38461 uint8_t unused_0[7];
38463 * This field is used in Output records to indicate that the output
38464 * is completely written to RAM. This field should be read as '1'
38465 * to indicate that the output has been completely written.
38466 * When writing a command completion or response to an internal processor,
38467 * the order of writes has to be such that this field is written last.
38472 /************************
38473 * hwrm_reject_fwd_resp *
38474 ************************/
38477 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
38478 struct hwrm_reject_fwd_resp_input {
38479 /* The HWRM command request type. */
38482 * The completion ring to send the completion event on. This should
38483 * be the NQ ID returned from the `nq_alloc` HWRM command.
38485 uint16_t cmpl_ring;
38487 * The sequence ID is used by the driver for tracking multiple
38488 * commands. This ID is treated as opaque data by the firmware and
38489 * the value is returned in the `hwrm_resp_hdr` upon completion.
38493 * The target ID of the command:
38494 * * 0x0-0xFFF8 - The function ID
38495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38496 * * 0xFFFD - Reserved for user-space HWRM interface
38499 uint16_t target_id;
38501 * A physical address pointer pointing to a host buffer that the
38502 * command's response data will be written. This can be either a host
38503 * physical address (HPA) or a guest physical address (GPA) and must
38504 * point to a physically contiguous block of memory.
38506 uint64_t resp_addr;
38508 * This is an encapsulated request. This request should
38509 * be rejected by the HWRM and the error response should be
38510 * provided in the response buffer inside the encapsulated
38513 uint32_t encap_request[26];
38515 * This value indicates the target id of the response to
38516 * the encapsulated request.
38517 * 0x0 - 0xFFF8 - Used for function ids
38518 * 0xFFF8 - 0xFFFE - Reserved for internal processors
38521 uint16_t encap_resp_target_id;
38522 uint8_t unused_0[6];
38525 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
38526 struct hwrm_reject_fwd_resp_output {
38527 /* The specific error status for the command. */
38528 uint16_t error_code;
38529 /* The HWRM command request type. */
38531 /* The sequence ID from the original command. */
38533 /* The length of the response data in number of bytes. */
38535 uint8_t unused_0[7];
38537 * This field is used in Output records to indicate that the output
38538 * is completely written to RAM. This field should be read as '1'
38539 * to indicate that the output has been completely written.
38540 * When writing a command completion or response to an internal processor,
38541 * the order of writes has to be such that this field is written last.
38551 /* hwrm_fwd_resp_input (size:1024b/128B) */
38552 struct hwrm_fwd_resp_input {
38553 /* The HWRM command request type. */
38556 * The completion ring to send the completion event on. This should
38557 * be the NQ ID returned from the `nq_alloc` HWRM command.
38559 uint16_t cmpl_ring;
38561 * The sequence ID is used by the driver for tracking multiple
38562 * commands. This ID is treated as opaque data by the firmware and
38563 * the value is returned in the `hwrm_resp_hdr` upon completion.
38567 * The target ID of the command:
38568 * * 0x0-0xFFF8 - The function ID
38569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38570 * * 0xFFFD - Reserved for user-space HWRM interface
38573 uint16_t target_id;
38575 * A physical address pointer pointing to a host buffer that the
38576 * command's response data will be written. This can be either a host
38577 * physical address (HPA) or a guest physical address (GPA) and must
38578 * point to a physically contiguous block of memory.
38580 uint64_t resp_addr;
38582 * This value indicates the target id of the encapsulated
38584 * 0x0 - 0xFFF8 - Used for function ids
38585 * 0xFFF8 - 0xFFFE - Reserved for internal processors
38588 uint16_t encap_resp_target_id;
38590 * This value indicates the completion ring the encapsulated
38591 * response will be optionally completed on. If the value is
38592 * -1, then no CR completion shall be generated for the
38593 * encapsulated response. Any other value must be a
38594 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
38595 * is provided, then a CR completion shall be generated for
38596 * the encapsulated response.
38598 uint16_t encap_resp_cmpl_ring;
38599 /* This field indicates the length of encapsulated response. */
38600 uint16_t encap_resp_len;
38604 * This is the host address where the encapsulated response
38606 * This area must be 16B aligned and must be cleared to zero
38607 * before the original request is made.
38609 uint64_t encap_resp_addr;
38610 /* This is an encapsulated response. */
38611 uint32_t encap_resp[24];
38614 /* hwrm_fwd_resp_output (size:128b/16B) */
38615 struct hwrm_fwd_resp_output {
38616 /* The specific error status for the command. */
38617 uint16_t error_code;
38618 /* The HWRM command request type. */
38620 /* The sequence ID from the original command. */
38622 /* The length of the response data in number of bytes. */
38624 uint8_t unused_0[7];
38626 * This field is used in Output records to indicate that the output
38627 * is completely written to RAM. This field should be read as '1'
38628 * to indicate that the output has been completely written.
38629 * When writing a command completion or response to an internal processor,
38630 * the order of writes has to be such that this field is written last.
38635 /*****************************
38636 * hwrm_fwd_async_event_cmpl *
38637 *****************************/
38640 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
38641 struct hwrm_fwd_async_event_cmpl_input {
38642 /* The HWRM command request type. */
38645 * The completion ring to send the completion event on. This should
38646 * be the NQ ID returned from the `nq_alloc` HWRM command.
38648 uint16_t cmpl_ring;
38650 * The sequence ID is used by the driver for tracking multiple
38651 * commands. This ID is treated as opaque data by the firmware and
38652 * the value is returned in the `hwrm_resp_hdr` upon completion.
38656 * The target ID of the command:
38657 * * 0x0-0xFFF8 - The function ID
38658 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38659 * * 0xFFFD - Reserved for user-space HWRM interface
38662 uint16_t target_id;
38664 * A physical address pointer pointing to a host buffer that the
38665 * command's response data will be written. This can be either a host
38666 * physical address (HPA) or a guest physical address (GPA) and must
38667 * point to a physically contiguous block of memory.
38669 uint64_t resp_addr;
38671 * This value indicates the target id of the encapsulated
38672 * asynchronous event.
38673 * 0x0 - 0xFFF8 - Used for function ids
38674 * 0xFFF8 - 0xFFFE - Reserved for internal processors
38675 * 0xFFFF - Broadcast to all children VFs (only applicable when
38676 * a PF is the requester)
38678 uint16_t encap_async_event_target_id;
38679 uint8_t unused_0[6];
38680 /* This is an encapsulated asynchronous event completion. */
38681 uint32_t encap_async_event_cmpl[4];
38684 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
38685 struct hwrm_fwd_async_event_cmpl_output {
38686 /* The specific error status for the command. */
38687 uint16_t error_code;
38688 /* The HWRM command request type. */
38690 /* The sequence ID from the original command. */
38692 /* The length of the response data in number of bytes. */
38694 uint8_t unused_0[7];
38696 * This field is used in Output records to indicate that the output
38697 * is completely written to RAM. This field should be read as '1'
38698 * to indicate that the output has been completely written.
38699 * When writing a command completion or response to an internal processor,
38700 * the order of writes has to be such that this field is written last.
38705 /**************************
38706 * hwrm_nvm_raw_write_blk *
38707 **************************/
38710 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
38711 struct hwrm_nvm_raw_write_blk_input {
38712 /* The HWRM command request type. */
38715 * The completion ring to send the completion event on. This should
38716 * be the NQ ID returned from the `nq_alloc` HWRM command.
38718 uint16_t cmpl_ring;
38720 * The sequence ID is used by the driver for tracking multiple
38721 * commands. This ID is treated as opaque data by the firmware and
38722 * the value is returned in the `hwrm_resp_hdr` upon completion.
38726 * The target ID of the command:
38727 * * 0x0-0xFFF8 - The function ID
38728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38729 * * 0xFFFD - Reserved for user-space HWRM interface
38732 uint16_t target_id;
38734 * A physical address pointer pointing to a host buffer that the
38735 * command's response data will be written. This can be either a host
38736 * physical address (HPA) or a guest physical address (GPA) and must
38737 * point to a physically contiguous block of memory.
38739 uint64_t resp_addr;
38741 * 64-bit Host Source Address.
38742 * This is the location of the source data to be written.
38744 uint64_t host_src_addr;
38746 * 32-bit Destination Address.
38747 * This is the NVRAM byte-offset where the source data will be written to.
38749 uint32_t dest_addr;
38750 /* Length of data to be written, in bytes. */
38754 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
38755 struct hwrm_nvm_raw_write_blk_output {
38756 /* The specific error status for the command. */
38757 uint16_t error_code;
38758 /* The HWRM command request type. */
38760 /* The sequence ID from the original command. */
38762 /* The length of the response data in number of bytes. */
38764 uint8_t unused_0[7];
38766 * This field is used in Output records to indicate that the output
38767 * is completely written to RAM. This field should be read as '1'
38768 * to indicate that the output has been completely written.
38769 * When writing a command completion or response to an internal processor,
38770 * the order of writes has to be such that this field is written last.
38780 /* hwrm_nvm_read_input (size:320b/40B) */
38781 struct hwrm_nvm_read_input {
38782 /* The HWRM command request type. */
38785 * The completion ring to send the completion event on. This should
38786 * be the NQ ID returned from the `nq_alloc` HWRM command.
38788 uint16_t cmpl_ring;
38790 * The sequence ID is used by the driver for tracking multiple
38791 * commands. This ID is treated as opaque data by the firmware and
38792 * the value is returned in the `hwrm_resp_hdr` upon completion.
38796 * The target ID of the command:
38797 * * 0x0-0xFFF8 - The function ID
38798 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38799 * * 0xFFFD - Reserved for user-space HWRM interface
38802 uint16_t target_id;
38804 * A physical address pointer pointing to a host buffer that the
38805 * command's response data will be written. This can be either a host
38806 * physical address (HPA) or a guest physical address (GPA) and must
38807 * point to a physically contiguous block of memory.
38809 uint64_t resp_addr;
38811 * 64-bit Host Destination Address.
38812 * This is the host address where the data will be written to.
38814 uint64_t host_dest_addr;
38815 /* The 0-based index of the directory entry. */
38817 uint8_t unused_0[2];
38818 /* The NVRAM byte-offset to read from. */
38820 /* The length of the data to be read, in bytes. */
38822 uint8_t unused_1[4];
38825 /* hwrm_nvm_read_output (size:128b/16B) */
38826 struct hwrm_nvm_read_output {
38827 /* The specific error status for the command. */
38828 uint16_t error_code;
38829 /* The HWRM command request type. */
38831 /* The sequence ID from the original command. */
38833 /* The length of the response data in number of bytes. */
38835 uint8_t unused_0[7];
38837 * This field is used in Output records to indicate that the output
38838 * is completely written to RAM. This field should be read as '1'
38839 * to indicate that the output has been completely written.
38840 * When writing a command completion or response to an internal processor,
38841 * the order of writes has to be such that this field is written last.
38846 /*********************
38847 * hwrm_nvm_raw_dump *
38848 *********************/
38851 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
38852 struct hwrm_nvm_raw_dump_input {
38853 /* The HWRM command request type. */
38856 * The completion ring to send the completion event on. This should
38857 * be the NQ ID returned from the `nq_alloc` HWRM command.
38859 uint16_t cmpl_ring;
38861 * The sequence ID is used by the driver for tracking multiple
38862 * commands. This ID is treated as opaque data by the firmware and
38863 * the value is returned in the `hwrm_resp_hdr` upon completion.
38867 * The target ID of the command:
38868 * * 0x0-0xFFF8 - The function ID
38869 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38870 * * 0xFFFD - Reserved for user-space HWRM interface
38873 uint16_t target_id;
38875 * A physical address pointer pointing to a host buffer that the
38876 * command's response data will be written. This can be either a host
38877 * physical address (HPA) or a guest physical address (GPA) and must
38878 * point to a physically contiguous block of memory.
38880 uint64_t resp_addr;
38882 * 64-bit Host Destination Address.
38883 * This is the host address where the data will be written to.
38885 uint64_t host_dest_addr;
38886 /* 32-bit NVRAM byte-offset to read from. */
38888 /* Total length of NVRAM contents to be read, in bytes. */
38892 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
38893 struct hwrm_nvm_raw_dump_output {
38894 /* The specific error status for the command. */
38895 uint16_t error_code;
38896 /* The HWRM command request type. */
38898 /* The sequence ID from the original command. */
38900 /* The length of the response data in number of bytes. */
38902 uint8_t unused_0[7];
38904 * This field is used in Output records to indicate that the output
38905 * is completely written to RAM. This field should be read as '1'
38906 * to indicate that the output has been completely written.
38907 * When writing a command completion or response to an internal processor,
38908 * the order of writes has to be such that this field is written last.
38913 /****************************
38914 * hwrm_nvm_get_dir_entries *
38915 ****************************/
38918 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
38919 struct hwrm_nvm_get_dir_entries_input {
38920 /* The HWRM command request type. */
38923 * The completion ring to send the completion event on. This should
38924 * be the NQ ID returned from the `nq_alloc` HWRM command.
38926 uint16_t cmpl_ring;
38928 * The sequence ID is used by the driver for tracking multiple
38929 * commands. This ID is treated as opaque data by the firmware and
38930 * the value is returned in the `hwrm_resp_hdr` upon completion.
38934 * The target ID of the command:
38935 * * 0x0-0xFFF8 - The function ID
38936 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38937 * * 0xFFFD - Reserved for user-space HWRM interface
38940 uint16_t target_id;
38942 * A physical address pointer pointing to a host buffer that the
38943 * command's response data will be written. This can be either a host
38944 * physical address (HPA) or a guest physical address (GPA) and must
38945 * point to a physically contiguous block of memory.
38947 uint64_t resp_addr;
38949 * 64-bit Host Destination Address.
38950 * This is the host address where the directory will be written.
38952 uint64_t host_dest_addr;
38955 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
38956 struct hwrm_nvm_get_dir_entries_output {
38957 /* The specific error status for the command. */
38958 uint16_t error_code;
38959 /* The HWRM command request type. */
38961 /* The sequence ID from the original command. */
38963 /* The length of the response data in number of bytes. */
38965 uint8_t unused_0[7];
38967 * This field is used in Output records to indicate that the output
38968 * is completely written to RAM. This field should be read as '1'
38969 * to indicate that the output has been completely written.
38970 * When writing a command completion or response to an internal processor,
38971 * the order of writes has to be such that this field is written last.
38976 /*************************
38977 * hwrm_nvm_get_dir_info *
38978 *************************/
38981 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
38982 struct hwrm_nvm_get_dir_info_input {
38983 /* The HWRM command request type. */
38986 * The completion ring to send the completion event on. This should
38987 * be the NQ ID returned from the `nq_alloc` HWRM command.
38989 uint16_t cmpl_ring;
38991 * The sequence ID is used by the driver for tracking multiple
38992 * commands. This ID is treated as opaque data by the firmware and
38993 * the value is returned in the `hwrm_resp_hdr` upon completion.
38997 * The target ID of the command:
38998 * * 0x0-0xFFF8 - The function ID
38999 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39000 * * 0xFFFD - Reserved for user-space HWRM interface
39003 uint16_t target_id;
39005 * A physical address pointer pointing to a host buffer that the
39006 * command's response data will be written. This can be either a host
39007 * physical address (HPA) or a guest physical address (GPA) and must
39008 * point to a physically contiguous block of memory.
39010 uint64_t resp_addr;
39013 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
39014 struct hwrm_nvm_get_dir_info_output {
39015 /* The specific error status for the command. */
39016 uint16_t error_code;
39017 /* The HWRM command request type. */
39019 /* The sequence ID from the original command. */
39021 /* The length of the response data in number of bytes. */
39023 /* Number of directory entries in the directory. */
39025 /* Size of each directory entry, in bytes. */
39026 uint32_t entry_length;
39027 uint8_t unused_0[7];
39029 * This field is used in Output records to indicate that the output
39030 * is completely written to RAM. This field should be read as '1'
39031 * to indicate that the output has been completely written.
39032 * When writing a command completion or response to an internal processor,
39033 * the order of writes has to be such that this field is written last.
39038 /******************
39040 ******************/
39043 /* hwrm_nvm_write_input (size:384b/48B) */
39044 struct hwrm_nvm_write_input {
39045 /* The HWRM command request type. */
39048 * The completion ring to send the completion event on. This should
39049 * be the NQ ID returned from the `nq_alloc` HWRM command.
39051 uint16_t cmpl_ring;
39053 * The sequence ID is used by the driver for tracking multiple
39054 * commands. This ID is treated as opaque data by the firmware and
39055 * the value is returned in the `hwrm_resp_hdr` upon completion.
39059 * The target ID of the command:
39060 * * 0x0-0xFFF8 - The function ID
39061 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39062 * * 0xFFFD - Reserved for user-space HWRM interface
39065 uint16_t target_id;
39067 * A physical address pointer pointing to a host buffer that the
39068 * command's response data will be written. This can be either a host
39069 * physical address (HPA) or a guest physical address (GPA) and must
39070 * point to a physically contiguous block of memory.
39072 uint64_t resp_addr;
39074 * 64-bit Host Source Address.
39075 * This is where the source data is.
39077 uint64_t host_src_addr;
39078 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
39081 * Directory ordinal.
39082 * The 0-based instance of the combined Directory Entry Type and Extension.
39084 uint16_t dir_ordinal;
39085 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
39087 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
39090 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
39091 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
39093 uint32_t dir_data_length;
39098 * When this bit is '1', the original active image
39099 * will not be removed. TBD: what purpose is this?
39101 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
39104 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
39105 * If this value is less than the specified data length, it will be ignored.
39106 * The response will contain the actual allocated item length, which may be greater than the requested item length.
39107 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
39108 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
39110 uint32_t dir_item_length;
39114 /* hwrm_nvm_write_output (size:128b/16B) */
39115 struct hwrm_nvm_write_output {
39116 /* The specific error status for the command. */
39117 uint16_t error_code;
39118 /* The HWRM command request type. */
39120 /* The sequence ID from the original command. */
39122 /* The length of the response data in number of bytes. */
39125 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
39126 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
39128 uint32_t dir_item_length;
39129 /* The directory index of the created or modified item. */
39133 * This field is used in Output records to indicate that the output
39134 * is completely written to RAM. This field should be read as '1'
39135 * to indicate that the output has been completely written.
39136 * When writing a command completion or response to an internal processor,
39137 * the order of writes has to be such that this field is written last.
39142 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
39143 struct hwrm_nvm_write_cmd_err {
39145 * command specific error codes that goes to
39146 * the cmd_err field in Common HWRM Error Response.
39149 /* Unknown error */
39150 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
39151 /* Unable to complete operation due to fragmentation */
39152 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
39153 /* nvm is completely full. */
39154 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
39155 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
39156 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
39157 uint8_t unused_0[7];
39160 /*******************
39161 * hwrm_nvm_modify *
39162 *******************/
39165 /* hwrm_nvm_modify_input (size:320b/40B) */
39166 struct hwrm_nvm_modify_input {
39167 /* The HWRM command request type. */
39170 * The completion ring to send the completion event on. This should
39171 * be the NQ ID returned from the `nq_alloc` HWRM command.
39173 uint16_t cmpl_ring;
39175 * The sequence ID is used by the driver for tracking multiple
39176 * commands. This ID is treated as opaque data by the firmware and
39177 * the value is returned in the `hwrm_resp_hdr` upon completion.
39181 * The target ID of the command:
39182 * * 0x0-0xFFF8 - The function ID
39183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39184 * * 0xFFFD - Reserved for user-space HWRM interface
39187 uint16_t target_id;
39189 * A physical address pointer pointing to a host buffer that the
39190 * command's response data will be written. This can be either a host
39191 * physical address (HPA) or a guest physical address (GPA) and must
39192 * point to a physically contiguous block of memory.
39194 uint64_t resp_addr;
39196 * 64-bit Host Source Address.
39197 * This is where the modified data is.
39199 uint64_t host_src_addr;
39200 /* 16-bit directory entry index. */
39204 * This flag indicates the sender wants to modify a continuous NVRAM
39205 * area using a batch of this HWRM requests. The offset of a request
39206 * must be continuous to the end of previous request's. Firmware does
39207 * not update the directory entry until receiving the last request,
39208 * which is indicated by the batch_last flag.
39209 * This flag is set usually when a sender does not have a block of
39210 * memory that is big enough to hold the entire NVRAM data for send
39213 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
39215 * This flag can be used only when the batch_mode flag is set.
39216 * It indicates this request is the last of batch requests.
39218 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
39219 /* 32-bit NVRAM byte-offset to modify content from. */
39222 * Length of data to be modified, in bytes. The length shall
39226 uint8_t unused_1[4];
39229 /* hwrm_nvm_modify_output (size:128b/16B) */
39230 struct hwrm_nvm_modify_output {
39231 /* The specific error status for the command. */
39232 uint16_t error_code;
39233 /* The HWRM command request type. */
39235 /* The sequence ID from the original command. */
39237 /* The length of the response data in number of bytes. */
39239 uint8_t unused_0[7];
39241 * This field is used in Output records to indicate that the output
39242 * is completely written to RAM. This field should be read as '1'
39243 * to indicate that the output has been completely written.
39244 * When writing a command completion or response to an internal processor,
39245 * the order of writes has to be such that this field is written last.
39250 /***************************
39251 * hwrm_nvm_find_dir_entry *
39252 ***************************/
39255 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
39256 struct hwrm_nvm_find_dir_entry_input {
39257 /* The HWRM command request type. */
39260 * The completion ring to send the completion event on. This should
39261 * be the NQ ID returned from the `nq_alloc` HWRM command.
39263 uint16_t cmpl_ring;
39265 * The sequence ID is used by the driver for tracking multiple
39266 * commands. This ID is treated as opaque data by the firmware and
39267 * the value is returned in the `hwrm_resp_hdr` upon completion.
39271 * The target ID of the command:
39272 * * 0x0-0xFFF8 - The function ID
39273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39274 * * 0xFFFD - Reserved for user-space HWRM interface
39277 uint16_t target_id;
39279 * A physical address pointer pointing to a host buffer that the
39280 * command's response data will be written. This can be either a host
39281 * physical address (HPA) or a guest physical address (GPA) and must
39282 * point to a physically contiguous block of memory.
39284 uint64_t resp_addr;
39287 * This bit must be '1' for the dir_idx_valid field to be
39290 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
39292 /* Directory Entry Index */
39294 /* Directory Entry (Image) Type */
39297 * Directory ordinal.
39298 * The instance of this Directory Type
39300 uint16_t dir_ordinal;
39301 /* The Directory Entry Extension flags. */
39303 /* This value indicates the search option using dir_ordinal. */
39304 uint8_t opt_ordinal;
39305 /* This value indicates the search option using dir_ordinal. */
39306 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
39307 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
39308 /* Equal to specified ordinal value. */
39309 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
39310 /* Greater than or equal to specified ordinal value */
39311 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
39312 /* Greater than specified ordinal value */
39313 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
39314 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
39315 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
39316 uint8_t unused_0[3];
39319 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
39320 struct hwrm_nvm_find_dir_entry_output {
39321 /* The specific error status for the command. */
39322 uint16_t error_code;
39323 /* The HWRM command request type. */
39325 /* The sequence ID from the original command. */
39327 /* The length of the response data in number of bytes. */
39329 /* Allocated NVRAM for this directory entry, in bytes. */
39330 uint32_t dir_item_length;
39331 /* Size of the stored data for this directory entry, in bytes. */
39332 uint32_t dir_data_length;
39334 * Firmware version.
39335 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
39338 /* Directory ordinal. */
39339 uint16_t dir_ordinal;
39340 /* Directory Entry Index */
39342 uint8_t unused_0[7];
39344 * This field is used in Output records to indicate that the output
39345 * is completely written to RAM. This field should be read as '1'
39346 * to indicate that the output has been completely written.
39347 * When writing a command completion or response to an internal processor,
39348 * the order of writes has to be such that this field is written last.
39353 /****************************
39354 * hwrm_nvm_erase_dir_entry *
39355 ****************************/
39358 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
39359 struct hwrm_nvm_erase_dir_entry_input {
39360 /* The HWRM command request type. */
39363 * The completion ring to send the completion event on. This should
39364 * be the NQ ID returned from the `nq_alloc` HWRM command.
39366 uint16_t cmpl_ring;
39368 * The sequence ID is used by the driver for tracking multiple
39369 * commands. This ID is treated as opaque data by the firmware and
39370 * the value is returned in the `hwrm_resp_hdr` upon completion.
39374 * The target ID of the command:
39375 * * 0x0-0xFFF8 - The function ID
39376 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39377 * * 0xFFFD - Reserved for user-space HWRM interface
39380 uint16_t target_id;
39382 * A physical address pointer pointing to a host buffer that the
39383 * command's response data will be written. This can be either a host
39384 * physical address (HPA) or a guest physical address (GPA) and must
39385 * point to a physically contiguous block of memory.
39387 uint64_t resp_addr;
39388 /* Directory Entry Index */
39390 uint8_t unused_0[6];
39393 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
39394 struct hwrm_nvm_erase_dir_entry_output {
39395 /* The specific error status for the command. */
39396 uint16_t error_code;
39397 /* The HWRM command request type. */
39399 /* The sequence ID from the original command. */
39401 /* The length of the response data in number of bytes. */
39403 uint8_t unused_0[7];
39405 * This field is used in Output records to indicate that the output
39406 * is completely written to RAM. This field should be read as '1'
39407 * to indicate that the output has been completely written.
39408 * When writing a command completion or response to an internal processor,
39409 * the order of writes has to be such that this field is written last.
39414 /*************************
39415 * hwrm_nvm_get_dev_info *
39416 *************************/
39419 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
39420 struct hwrm_nvm_get_dev_info_input {
39421 /* The HWRM command request type. */
39424 * The completion ring to send the completion event on. This should
39425 * be the NQ ID returned from the `nq_alloc` HWRM command.
39427 uint16_t cmpl_ring;
39429 * The sequence ID is used by the driver for tracking multiple
39430 * commands. This ID is treated as opaque data by the firmware and
39431 * the value is returned in the `hwrm_resp_hdr` upon completion.
39435 * The target ID of the command:
39436 * * 0x0-0xFFF8 - The function ID
39437 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39438 * * 0xFFFD - Reserved for user-space HWRM interface
39441 uint16_t target_id;
39443 * A physical address pointer pointing to a host buffer that the
39444 * command's response data will be written. This can be either a host
39445 * physical address (HPA) or a guest physical address (GPA) and must
39446 * point to a physically contiguous block of memory.
39448 uint64_t resp_addr;
39451 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
39452 struct hwrm_nvm_get_dev_info_output {
39453 /* The specific error status for the command. */
39454 uint16_t error_code;
39455 /* The HWRM command request type. */
39457 /* The sequence ID from the original command. */
39459 /* The length of the response data in number of bytes. */
39461 /* Manufacturer ID. */
39462 uint16_t manufacturer_id;
39464 uint16_t device_id;
39465 /* Sector size of the NVRAM device. */
39466 uint32_t sector_size;
39467 /* Total size, in bytes of the NVRAM device. */
39468 uint32_t nvram_size;
39469 uint32_t reserved_size;
39470 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
39471 uint32_t available_size;
39472 /* This field represents the major version of NVM cfg */
39473 uint8_t nvm_cfg_ver_maj;
39474 /* This field represents the minor version of NVM cfg */
39475 uint8_t nvm_cfg_ver_min;
39476 /* This field represents the update version of NVM cfg */
39477 uint8_t nvm_cfg_ver_upd;
39479 * This field is used in Output records to indicate that the output
39480 * is completely written to RAM. This field should be read as '1'
39481 * to indicate that the output has been completely written.
39482 * When writing a command completion or response to an internal processor,
39483 * the order of writes has to be such that this field is written last.
39488 /**************************
39489 * hwrm_nvm_mod_dir_entry *
39490 **************************/
39493 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
39494 struct hwrm_nvm_mod_dir_entry_input {
39495 /* The HWRM command request type. */
39498 * The completion ring to send the completion event on. This should
39499 * be the NQ ID returned from the `nq_alloc` HWRM command.
39501 uint16_t cmpl_ring;
39503 * The sequence ID is used by the driver for tracking multiple
39504 * commands. This ID is treated as opaque data by the firmware and
39505 * the value is returned in the `hwrm_resp_hdr` upon completion.
39509 * The target ID of the command:
39510 * * 0x0-0xFFF8 - The function ID
39511 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39512 * * 0xFFFD - Reserved for user-space HWRM interface
39515 uint16_t target_id;
39517 * A physical address pointer pointing to a host buffer that the
39518 * command's response data will be written. This can be either a host
39519 * physical address (HPA) or a guest physical address (GPA) and must
39520 * point to a physically contiguous block of memory.
39522 uint64_t resp_addr;
39525 * This bit must be '1' for the checksum field to be
39528 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
39529 /* Directory Entry Index */
39532 * Directory ordinal.
39533 * The (0-based) instance of this Directory Type.
39535 uint16_t dir_ordinal;
39536 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
39538 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
39541 * If valid, then this field updates the checksum
39542 * value of the content in the directory entry.
39547 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
39548 struct hwrm_nvm_mod_dir_entry_output {
39549 /* The specific error status for the command. */
39550 uint16_t error_code;
39551 /* The HWRM command request type. */
39553 /* The sequence ID from the original command. */
39555 /* The length of the response data in number of bytes. */
39557 uint8_t unused_0[7];
39559 * This field is used in Output records to indicate that the output
39560 * is completely written to RAM. This field should be read as '1'
39561 * to indicate that the output has been completely written.
39562 * When writing a command completion or response to an internal processor,
39563 * the order of writes has to be such that this field is written last.
39568 /**************************
39569 * hwrm_nvm_verify_update *
39570 **************************/
39573 /* hwrm_nvm_verify_update_input (size:192b/24B) */
39574 struct hwrm_nvm_verify_update_input {
39575 /* The HWRM command request type. */
39578 * The completion ring to send the completion event on. This should
39579 * be the NQ ID returned from the `nq_alloc` HWRM command.
39581 uint16_t cmpl_ring;
39583 * The sequence ID is used by the driver for tracking multiple
39584 * commands. This ID is treated as opaque data by the firmware and
39585 * the value is returned in the `hwrm_resp_hdr` upon completion.
39589 * The target ID of the command:
39590 * * 0x0-0xFFF8 - The function ID
39591 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39592 * * 0xFFFD - Reserved for user-space HWRM interface
39595 uint16_t target_id;
39597 * A physical address pointer pointing to a host buffer that the
39598 * command's response data will be written. This can be either a host
39599 * physical address (HPA) or a guest physical address (GPA) and must
39600 * point to a physically contiguous block of memory.
39602 uint64_t resp_addr;
39603 /* Directory Entry Type, to be verified. */
39606 * Directory ordinal.
39607 * The instance of the Directory Type to be verified.
39609 uint16_t dir_ordinal;
39611 * The Directory Entry Extension flags.
39612 * The "UPDATE" extension flag must be set in this value.
39613 * A corresponding directory entry with the same type and ordinal values but *without*
39614 * the "UPDATE" extension flag must also exist. The other flags of the extension must
39615 * be identical between the active and update entries.
39618 uint8_t unused_0[2];
39621 /* hwrm_nvm_verify_update_output (size:128b/16B) */
39622 struct hwrm_nvm_verify_update_output {
39623 /* The specific error status for the command. */
39624 uint16_t error_code;
39625 /* The HWRM command request type. */
39627 /* The sequence ID from the original command. */
39629 /* The length of the response data in number of bytes. */
39631 uint8_t unused_0[7];
39633 * This field is used in Output records to indicate that the output
39634 * is completely written to RAM. This field should be read as '1'
39635 * to indicate that the output has been completely written.
39636 * When writing a command completion or response to an internal processor,
39637 * the order of writes has to be such that this field is written last.
39642 /***************************
39643 * hwrm_nvm_install_update *
39644 ***************************/
39647 /* hwrm_nvm_install_update_input (size:192b/24B) */
39648 struct hwrm_nvm_install_update_input {
39649 /* The HWRM command request type. */
39652 * The completion ring to send the completion event on. This should
39653 * be the NQ ID returned from the `nq_alloc` HWRM command.
39655 uint16_t cmpl_ring;
39657 * The sequence ID is used by the driver for tracking multiple
39658 * commands. This ID is treated as opaque data by the firmware and
39659 * the value is returned in the `hwrm_resp_hdr` upon completion.
39663 * The target ID of the command:
39664 * * 0x0-0xFFF8 - The function ID
39665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39666 * * 0xFFFD - Reserved for user-space HWRM interface
39669 uint16_t target_id;
39671 * A physical address pointer pointing to a host buffer that the
39672 * command's response data will be written. This can be either a host
39673 * physical address (HPA) or a guest physical address (GPA) and must
39674 * point to a physically contiguous block of memory.
39676 uint64_t resp_addr;
39678 * Installation type. If the value 3 through 0xffff is used,
39679 * only packaged items with that type value will be installed and
39680 * conditional installation directives for those packaged items
39681 * will be over-ridden (i.e. 'create' or 'replace' will be treated
39684 uint32_t install_type;
39686 * Perform a normal package installation. Conditional installation
39687 * directives (e.g. 'create' and 'replace') of packaged items
39688 * will be followed.
39690 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
39692 * Install all packaged items regardless of installation directive
39693 * (i.e. treat all packaged items as though they have an installation
39694 * directive of 'install').
39696 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
39697 UINT32_C(0xffffffff)
39698 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
39699 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
39701 /* If set to 1, then securely erase all unused locations in persistent storage. */
39702 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
39705 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
39706 * When combined with erase_unused_space then unspecified images will be securely erased.
39708 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
39711 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
39712 * Allow additional time for this command to complete if this bit is set to 1.
39714 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
39717 * If set to 1, FW will verify the package in the "UPDATE" NVM item
39718 * without installing it. This flag is for FW internal use only.
39719 * Users should not set this flag. The request will otherwise fail.
39721 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
39723 uint8_t unused_0[2];
39726 /* hwrm_nvm_install_update_output (size:192b/24B) */
39727 struct hwrm_nvm_install_update_output {
39728 /* The specific error status for the command. */
39729 uint16_t error_code;
39730 /* The HWRM command request type. */
39732 /* The sequence ID from the original command. */
39734 /* The length of the response data in number of bytes. */
39737 * Bit-mask of successfully installed items.
39738 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
39739 * A value of 0 indicates that no items were successfully installed.
39741 uint64_t installed_items;
39742 /* result is 8 b */
39744 /* There was no problem with the package installation. */
39745 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
39746 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
39747 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
39748 /* problem_item is 8 b */
39749 uint8_t problem_item;
39750 /* There was no problem with any packaged items. */
39751 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
39753 /* There was a problem with the NVM package itself. */
39754 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
39756 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
39757 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
39758 /* reset_required is 8 b */
39759 uint8_t reset_required;
39761 * No reset is required for installed/updated firmware or
39762 * microcode to take effect.
39764 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
39767 * A PCIe reset (e.g. system reboot) is
39768 * required for newly installed/updated firmware or
39769 * microcode to take effect.
39771 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
39774 * A controller power reset (e.g. system power-cycle) is
39775 * required for newly installed/updated firmware or
39776 * microcode to take effect. Some newly installed/updated
39777 * firmware or microcode may still take effect upon the
39780 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
39782 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
39783 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
39784 uint8_t unused_0[4];
39786 * This field is used in Output records to indicate that the output
39787 * is completely written to RAM. This field should be read as '1'
39788 * to indicate that the output has been completely written.
39789 * When writing a command completion or response to an internal processor,
39790 * the order of writes has to be such that this field is written last.
39795 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
39796 struct hwrm_nvm_install_update_cmd_err {
39798 * command specific error codes that goes to
39799 * the cmd_err field in Common HWRM Error Response.
39802 /* Unknown error */
39803 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
39804 /* Unable to complete operation due to fragmentation */
39805 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
39806 /* nvm is completely full. */
39807 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
39808 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
39809 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
39810 uint8_t unused_0[7];
39813 /******************
39815 ******************/
39818 /* hwrm_nvm_flush_input (size:128b/16B) */
39819 struct hwrm_nvm_flush_input {
39820 /* The HWRM command request type. */
39823 * The completion ring to send the completion event on. This should
39824 * be the NQ ID returned from the `nq_alloc` HWRM command.
39826 uint16_t cmpl_ring;
39828 * The sequence ID is used by the driver for tracking multiple
39829 * commands. This ID is treated as opaque data by the firmware and
39830 * the value is returned in the `hwrm_resp_hdr` upon completion.
39834 * The target ID of the command:
39835 * * 0x0-0xFFF8 - The function ID
39836 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39837 * * 0xFFFD - Reserved for user-space HWRM interface
39840 uint16_t target_id;
39842 * A physical address pointer pointing to a host buffer that the
39843 * command's response data will be written. This can be either a host
39844 * physical address (HPA) or a guest physical address (GPA) and must
39845 * point to a physically contiguous block of memory.
39847 uint64_t resp_addr;
39850 /* hwrm_nvm_flush_output (size:128b/16B) */
39851 struct hwrm_nvm_flush_output {
39852 /* The specific error status for the command. */
39853 uint16_t error_code;
39854 /* The HWRM command request type. */
39856 /* The sequence ID from the original command. */
39858 /* The length of the response data in number of bytes. */
39860 uint8_t unused_0[7];
39862 * This field is used in Output records to indicate that the output
39863 * is completely written to RAM. This field should be read as '1'
39864 * to indicate that the output has been completely written.
39865 * When writing a command completion or response to an internal processor,
39866 * the order of writes has to be such that this field is written last.
39871 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
39872 struct hwrm_nvm_flush_cmd_err {
39874 * command specific error codes that goes to
39875 * the cmd_err field in Common HWRM Error Response.
39878 /* Unknown error */
39879 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
39880 /* flush could not be performed */
39881 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
39882 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
39883 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
39884 uint8_t unused_0[7];
39887 /*************************
39888 * hwrm_nvm_get_variable *
39889 *************************/
39892 /* hwrm_nvm_get_variable_input (size:320b/40B) */
39893 struct hwrm_nvm_get_variable_input {
39894 /* The HWRM command request type. */
39897 * The completion ring to send the completion event on. This should
39898 * be the NQ ID returned from the `nq_alloc` HWRM command.
39900 uint16_t cmpl_ring;
39902 * The sequence ID is used by the driver for tracking multiple
39903 * commands. This ID is treated as opaque data by the firmware and
39904 * the value is returned in the `hwrm_resp_hdr` upon completion.
39908 * The target ID of the command:
39909 * * 0x0-0xFFF8 - The function ID
39910 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39911 * * 0xFFFD - Reserved for user-space HWRM interface
39914 uint16_t target_id;
39916 * A physical address pointer pointing to a host buffer that the
39917 * command's response data will be written. This can be either a host
39918 * physical address (HPA) or a guest physical address (GPA) and must
39919 * point to a physically contiguous block of memory.
39921 uint64_t resp_addr;
39923 * This is the host address where
39924 * nvm variable will be stored
39926 uint64_t dest_data_addr;
39927 /* size of data in bits */
39929 /* nvm cfg option number */
39930 uint16_t option_num;
39932 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
39934 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
39936 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
39937 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
39939 * Number of dimensions for this nvm configuration variable.
39940 * This value indicates how many of the indexN values to use.
39941 * A value of 0 means that none of the indexN values are valid.
39942 * A value of 1 requires at index0 is valued, a value of 2
39943 * requires that index0 and index1 are valid, and so forth
39945 uint16_t dimensions;
39946 /* index for the 1st dimensions */
39948 /* index for the 2nd dimensions */
39950 /* index for the 3rd dimensions */
39952 /* index for the 4th dimensions */
39956 * When this bit is set to 1, the factory default value will be returned,
39957 * 0 returns the operational value.
39959 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
39964 /* hwrm_nvm_get_variable_output (size:128b/16B) */
39965 struct hwrm_nvm_get_variable_output {
39966 /* The specific error status for the command. */
39967 uint16_t error_code;
39968 /* The HWRM command request type. */
39970 /* The sequence ID from the original command. */
39972 /* The length of the response data in number of bytes. */
39974 /* size of data of the actual variable retrieved in bits */
39977 * option_num is the option number for the data retrieved. It is possible in the
39978 * future that the option number returned would be different than requested. This
39979 * condition could occur if an option is deprecated and a new option id is defined
39980 * with similar characteristics, but has a slightly different definition. This
39981 * also makes it convenient for the caller to identify the variable result with
39982 * the option id from the response.
39984 uint16_t option_num;
39986 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
39988 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
39990 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
39991 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
39992 uint8_t unused_0[3];
39994 * This field is used in Output records to indicate that the output
39995 * is completely written to RAM. This field should be read as '1'
39996 * to indicate that the output has been completely written.
39997 * When writing a command completion or response to an internal processor,
39998 * the order of writes has to be such that this field is written last.
40003 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
40004 struct hwrm_nvm_get_variable_cmd_err {
40006 * command specific error codes that goes to
40007 * the cmd_err field in Common HWRM Error Response.
40010 /* Unknown error */
40011 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
40012 /* variable does not exist */
40013 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
40014 /* configuration is corrupted and the variable cannot be saved */
40015 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
40016 /* length specified is too small */
40017 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
40018 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
40019 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
40020 uint8_t unused_0[7];
40023 /*************************
40024 * hwrm_nvm_set_variable *
40025 *************************/
40028 /* hwrm_nvm_set_variable_input (size:320b/40B) */
40029 struct hwrm_nvm_set_variable_input {
40030 /* The HWRM command request type. */
40033 * The completion ring to send the completion event on. This should
40034 * be the NQ ID returned from the `nq_alloc` HWRM command.
40036 uint16_t cmpl_ring;
40038 * The sequence ID is used by the driver for tracking multiple
40039 * commands. This ID is treated as opaque data by the firmware and
40040 * the value is returned in the `hwrm_resp_hdr` upon completion.
40044 * The target ID of the command:
40045 * * 0x0-0xFFF8 - The function ID
40046 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40047 * * 0xFFFD - Reserved for user-space HWRM interface
40050 uint16_t target_id;
40052 * A physical address pointer pointing to a host buffer that the
40053 * command's response data will be written. This can be either a host
40054 * physical address (HPA) or a guest physical address (GPA) and must
40055 * point to a physically contiguous block of memory.
40057 uint64_t resp_addr;
40059 * This is the host address where
40060 * nvm variable will be copied from
40062 uint64_t src_data_addr;
40063 /* size of data in bits */
40065 /* nvm cfg option number */
40066 uint16_t option_num;
40068 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
40070 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
40072 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
40073 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
40075 * Number of dimensions for this nvm configuration variable.
40076 * This value indicates how many of the indexN values to use.
40077 * A value of 0 means that none of the indexN values are valid.
40078 * A value of 1 requires at index0 is valued, a value of 2
40079 * requires that index0 and index1 are valid, and so forth
40081 uint16_t dimensions;
40082 /* index for the 1st dimensions */
40084 /* index for the 2nd dimensions */
40086 /* index for the 3rd dimensions */
40088 /* index for the 4th dimensions */
40091 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
40092 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
40094 /* encryption method */
40095 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
40097 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
40098 /* No encryption. */
40099 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
40100 (UINT32_C(0x0) << 1)
40101 /* one-way encryption. */
40102 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
40103 (UINT32_C(0x1) << 1)
40104 /* symmetric AES256 encryption. */
40105 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
40106 (UINT32_C(0x2) << 1)
40107 /* SHA1 digest appended to plaintext contents, for authentication */
40108 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
40109 (UINT32_C(0x3) << 1)
40110 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
40111 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
40112 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
40114 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
40115 /* When this bit is 1, update the factory default region */
40116 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
40121 /* hwrm_nvm_set_variable_output (size:128b/16B) */
40122 struct hwrm_nvm_set_variable_output {
40123 /* The specific error status for the command. */
40124 uint16_t error_code;
40125 /* The HWRM command request type. */
40127 /* The sequence ID from the original command. */
40129 /* The length of the response data in number of bytes. */
40131 uint8_t unused_0[7];
40133 * This field is used in Output records to indicate that the output
40134 * is completely written to RAM. This field should be read as '1'
40135 * to indicate that the output has been completely written.
40136 * When writing a command completion or response to an internal processor,
40137 * the order of writes has to be such that this field is written last.
40142 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
40143 struct hwrm_nvm_set_variable_cmd_err {
40145 * command specific error codes that goes to
40146 * the cmd_err field in Common HWRM Error Response.
40149 /* Unknown error */
40150 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
40151 /* variable does not exist */
40152 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
40153 /* configuration is corrupted and the variable cannot be saved */
40154 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
40155 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
40156 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
40157 uint8_t unused_0[7];
40160 /****************************
40161 * hwrm_nvm_validate_option *
40162 ****************************/
40165 /* hwrm_nvm_validate_option_input (size:320b/40B) */
40166 struct hwrm_nvm_validate_option_input {
40167 /* The HWRM command request type. */
40170 * The completion ring to send the completion event on. This should
40171 * be the NQ ID returned from the `nq_alloc` HWRM command.
40173 uint16_t cmpl_ring;
40175 * The sequence ID is used by the driver for tracking multiple
40176 * commands. This ID is treated as opaque data by the firmware and
40177 * the value is returned in the `hwrm_resp_hdr` upon completion.
40181 * The target ID of the command:
40182 * * 0x0-0xFFF8 - The function ID
40183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40184 * * 0xFFFD - Reserved for user-space HWRM interface
40187 uint16_t target_id;
40189 * A physical address pointer pointing to a host buffer that the
40190 * command's response data will be written. This can be either a host
40191 * physical address (HPA) or a guest physical address (GPA) and must
40192 * point to a physically contiguous block of memory.
40194 uint64_t resp_addr;
40196 * This is the host address where
40197 * nvm variable will be copied from
40199 uint64_t src_data_addr;
40200 /* size of data in bits */
40202 /* nvm cfg option number */
40203 uint16_t option_num;
40205 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
40208 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
40210 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
40211 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
40213 * Number of dimensions for this nvm configuration variable.
40214 * This value indicates how many of the indexN values to use.
40215 * A value of 0 means that none of the indexN values are valid.
40216 * A value of 1 requires at index0 is valued, a value of 2
40217 * requires that index0 and index1 are valid, and so forth
40219 uint16_t dimensions;
40220 /* index for the 1st dimensions */
40222 /* index for the 2nd dimensions */
40224 /* index for the 3rd dimensions */
40226 /* index for the 4th dimensions */
40228 uint8_t unused_0[2];
40231 /* hwrm_nvm_validate_option_output (size:128b/16B) */
40232 struct hwrm_nvm_validate_option_output {
40233 /* The specific error status for the command. */
40234 uint16_t error_code;
40235 /* The HWRM command request type. */
40237 /* The sequence ID from the original command. */
40239 /* The length of the response data in number of bytes. */
40242 /* indicates that the value provided for the option is not matching with the saved data. */
40243 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
40244 /* indicates that the value provided for the option is matching the saved data. */
40245 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
40246 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
40247 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
40248 uint8_t unused_0[6];
40250 * This field is used in Output records to indicate that the output
40251 * is completely written to RAM. This field should be read as '1'
40252 * to indicate that the output has been completely written.
40253 * When writing a command completion or response to an internal processor,
40254 * the order of writes has to be such that this field is written last.
40259 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
40260 struct hwrm_nvm_validate_option_cmd_err {
40262 * command specific error codes that goes to
40263 * the cmd_err field in Common HWRM Error Response.
40266 /* Unknown error */
40267 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
40268 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
40269 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
40270 uint8_t unused_0[7];
40278 /* hwrm_oem_cmd_input (size:1024b/128B) */
40279 struct hwrm_oem_cmd_input {
40280 /* The HWRM command request type. */
40283 * The completion ring to send the completion event on. This should
40284 * be the NQ ID returned from the `nq_alloc` HWRM command.
40286 uint16_t cmpl_ring;
40288 * The sequence ID is used by the driver for tracking multiple
40289 * commands. This ID is treated as opaque data by the firmware and
40290 * the value is returned in the `hwrm_resp_hdr` upon completion.
40294 * The target ID of the command:
40295 * * 0x0-0xFFF8 - The function ID
40296 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40297 * * 0xFFFD - Reserved for user-space HWRM interface
40300 uint16_t target_id;
40302 * A physical address pointer pointing to a host buffer that the
40303 * command's response data will be written. This can be either a host
40304 * physical address (HPA) or a guest physical address (GPA) and must
40305 * point to a physically contiguous block of memory.
40307 uint64_t resp_addr;
40310 /* This field contains the vendor specific command data. */
40311 uint32_t oem_data[26];
40314 /* hwrm_oem_cmd_output (size:768b/96B) */
40315 struct hwrm_oem_cmd_output {
40316 /* The specific error status for the command. */
40317 uint16_t error_code;
40318 /* The HWRM command request type. */
40320 /* The sequence ID from the original command. */
40322 /* The length of the response data in number of bytes. */
40326 /* This field contains the vendor specific response data. */
40327 uint32_t oem_data[18];
40328 uint8_t unused_1[7];
40330 * This field is used in Output records to indicate that the output
40331 * is completely written to RAM. This field should be read as '1'
40332 * to indicate that the output has been completely written.
40333 * When writing a command completion or response to an internal processor,
40334 * the order of writes has to be such that this field is written last.
40341 ******************/
40344 /* hwrm_fw_reset_input (size:192b/24B) */
40345 struct hwrm_fw_reset_input {
40346 /* The HWRM command request type. */
40349 * The completion ring to send the completion event on. This should
40350 * be the NQ ID returned from the `nq_alloc` HWRM command.
40352 uint16_t cmpl_ring;
40354 * The sequence ID is used by the driver for tracking multiple
40355 * commands. This ID is treated as opaque data by the firmware and
40356 * the value is returned in the `hwrm_resp_hdr` upon completion.
40360 * The target ID of the command:
40361 * * 0x0-0xFFF8 - The function ID
40362 * * 0xFFF8-0xFFFE - Reserved for internal processors
40365 uint16_t target_id;
40367 * A physical address pointer pointing to a host buffer that the
40368 * command's response data will be written. This can be either a host
40369 * physical address (HPA) or a guest physical address (GPA) and must
40370 * point to a physically contiguous block of memory.
40372 uint64_t resp_addr;
40373 /* Type of embedded processor. */
40374 uint8_t embedded_proc_type;
40375 /* Boot Processor */
40376 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
40378 /* Management Processor */
40379 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
40381 /* Network control processor */
40382 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
40384 /* RoCE control processor */
40385 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
40388 * Host (in multi-host environment): This is only valid if requester is IPC.
40389 * Reinit host hardware resources and PCIe.
40391 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
40393 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
40394 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
40396 /* Reset all blocks of the chip (including all processors) */
40397 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
40400 * Host (in multi-host environment): This is only valid if requester is IPC.
40401 * Reinit host hardware resources.
40403 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
40405 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
40406 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
40407 /* Type of self reset. */
40408 uint8_t selfrst_status;
40409 /* No Self Reset */
40410 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
40412 /* Self Reset as soon as possible to do so safely */
40413 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
40415 /* Self Reset on PCIe Reset */
40416 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
40418 /* Self Reset immediately after notification to all clients. */
40419 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
40421 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
40422 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
40424 * Indicate which host is being reset. 0 means first host.
40425 * Only valid when embedded_proc_type is host in multihost
40431 * When this bit is '1', then the core firmware initiates
40432 * the reset only after graceful shut down of all registered instances.
40433 * If not, the device will continue with the existing firmware.
40435 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
40436 uint8_t unused_0[4];
40439 /* hwrm_fw_reset_output (size:128b/16B) */
40440 struct hwrm_fw_reset_output {
40441 /* The specific error status for the command. */
40442 uint16_t error_code;
40443 /* The HWRM command request type. */
40445 /* The sequence ID from the original command. */
40447 /* The length of the response data in number of bytes. */
40449 /* Type of self reset. */
40450 uint8_t selfrst_status;
40451 /* No Self Reset */
40452 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
40454 /* Self Reset as soon as possible to do so safely */
40455 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
40457 /* Self Reset on PCIe Reset */
40458 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
40460 /* Self Reset immediately after notification to all clients. */
40461 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
40463 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
40464 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
40465 uint8_t unused_0[6];
40467 * This field is used in Output records to indicate that the output
40468 * is completely written to RAM. This field should be read as '1'
40469 * to indicate that the output has been completely written.
40470 * When writing a command completion or response to an internal processor,
40471 * the order of writes has to be such that this field is written last.
40476 /**********************
40477 * hwrm_port_ts_query *
40478 ***********************/
40481 /* hwrm_port_ts_query_input (size:192b/24B) */
40482 struct hwrm_port_ts_query_input {
40483 /* The HWRM command request type. */
40486 * The completion ring to send the completion event on. This should
40487 * be the NQ ID returned from the `nq_alloc` HWRM command.
40489 uint16_t cmpl_ring;
40491 * The sequence ID is used by the driver for tracking multiple
40492 * commands. This ID is treated as opaque data by the firmware and
40493 * the value is returned in the `hwrm_resp_hdr` upon completion.
40497 * The target ID of the command:
40498 * * 0x0-0xFFF8 - The function ID
40499 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40500 * * 0xFFFD - Reserved for user-space HWRM interface
40503 uint16_t target_id;
40505 * A physical address pointer pointing to a host buffer that the
40506 * command's response data will be written. This can be either a host
40507 * physical address (HPA) or a guest physical address (GPA) and must
40508 * point to a physically contiguous block of memory.
40510 uint64_t resp_addr;
40513 * Enumeration denoting the RX, TX type of the resource.
40514 * This enumeration is used for resources that are similar for both
40515 * TX and RX paths of the chip.
40517 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
40519 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
40521 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
40522 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
40523 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
40525 * If set, the response includes the current value of the free
40528 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
40529 /* Port ID of port that is being queried. */
40531 uint8_t unused_0[2];
40534 /* hwrm_port_ts_query_output (size:192b/24B) */
40535 struct hwrm_port_ts_query_output {
40536 /* The specific error status for the command. */
40537 uint16_t error_code;
40538 /* The HWRM command request type. */
40540 /* The sequence ID from the original command. */
40542 /* The length of the response data in number of bytes. */
40545 * Timestamp value of PTP message captured, or current value of
40546 * free running timer.
40548 uint32_t ptp_msg_ts[2];
40549 /* Sequence ID of the PTP message captured. */
40550 uint16_t ptp_msg_seqid;
40551 uint8_t unused_0[5];
40553 * This field is used in Output records to indicate that the output
40554 * is completely written to RAM. This field should be read as '1'
40555 * to indicate that the output has been completely written.
40556 * When writing a command completion or response to an internal processor,
40557 * the order of writes has to be such that this field is written last.
40563 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
40564 * offset: 0x31001F0). Host software is expected to read from this
40565 * location for a defined signature. If it exists, the software can
40566 * assume the presence of this structure and the validity of the
40567 * FW_STATUS location in the next field.
40569 /* hcomm_status (size:64b/8B) */
40570 struct hcomm_status {
40573 * This field defines the version of the structure. The latest
40574 * version value is 1.
40576 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
40577 #define HCOMM_STATUS_VER_SFT 0
40578 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
40579 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
40581 * This field is to store the signature value to indicate the
40582 * presence of the structure.
40584 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
40585 #define HCOMM_STATUS_SIGNATURE_SFT 8
40586 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
40587 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
40588 uint32_t fw_status_loc;
40589 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
40590 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
40591 /* PCIE configuration space */
40592 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
40594 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
40596 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
40598 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
40599 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
40600 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
40602 * This offset where the fw_status register is located. The value
40603 * is generally 4-byte aligned.
40605 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
40606 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
40608 /* This is the GRC offset where the hcomm_status struct resides. */
40609 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
40611 /**************************
40612 * hwrm_cfa_counter_qcaps *
40613 **************************/
40616 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
40617 struct hwrm_cfa_counter_qcaps_input {
40618 /* The HWRM command request type. */
40621 * The completion ring to send the completion event on. This should
40622 * be the NQ ID returned from the `nq_alloc` HWRM command.
40624 uint16_t cmpl_ring;
40626 * The sequence ID is used by the driver for tracking multiple
40627 * commands. This ID is treated as opaque data by the firmware and
40628 * the value is returned in the `hwrm_resp_hdr` upon completion.
40632 * The target ID of the command:
40633 * * 0x0-0xFFF8 - The function ID
40634 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40635 * * 0xFFFD - Reserved for user-space HWRM interface
40638 uint16_t target_id;
40640 * A physical address pointer pointing to a host buffer that the
40641 * command's response data will be written. This can be either a host
40642 * physical address (HPA) or a guest physical address (GPA) and must
40643 * point to a physically contiguous block of memory.
40645 uint64_t resp_addr;
40648 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
40649 struct hwrm_cfa_counter_qcaps_output {
40650 /* The specific error status for the command. */
40651 uint16_t error_code;
40652 /* The HWRM command request type. */
40654 /* The sequence ID from the original command. */
40656 /* The length of the response data in number of bytes. */
40659 /* Enumeration denoting the supported CFA counter format. */
40660 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
40662 /* CFA counter types are not supported. */
40663 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
40665 /* 64-bit packet counters followed by 64-bit byte counters format. */
40666 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
40668 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
40669 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
40671 /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
40672 uint32_t min_rx_fc;
40673 /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
40674 uint32_t max_rx_fc;
40675 /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
40676 uint32_t min_tx_fc;
40677 /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
40678 uint32_t max_tx_fc;
40679 /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
40680 uint32_t min_rx_efc;
40681 /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
40682 uint32_t max_rx_efc;
40683 /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
40684 uint32_t min_tx_efc;
40685 /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
40686 uint32_t max_tx_efc;
40687 /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
40688 uint32_t min_rx_mdc;
40689 /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
40690 uint32_t max_rx_mdc;
40691 /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
40692 uint32_t min_tx_mdc;
40693 /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
40694 uint32_t max_tx_mdc;
40695 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
40696 uint32_t max_flow_alloc_fc;
40697 uint8_t unused_1[3];
40699 * This field is used in Output records to indicate that the output
40700 * is completely written to RAM. This field should be read as '1'
40701 * to indicate that the output has been completely written.
40702 * When writing a command completion or response to an internal processor,
40703 * the order of writes has to be such that this field is written last.
40708 /************************
40709 * hwrm_cfa_counter_cfg *
40710 ************************/
40713 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
40714 struct hwrm_cfa_counter_cfg_input {
40715 /* The HWRM command request type. */
40718 * The completion ring to send the completion event on. This should
40719 * be the NQ ID returned from the `nq_alloc` HWRM command.
40721 uint16_t cmpl_ring;
40723 * The sequence ID is used by the driver for tracking multiple
40724 * commands. This ID is treated as opaque data by the firmware and
40725 * the value is returned in the `hwrm_resp_hdr` upon completion.
40729 * The target ID of the command:
40730 * * 0x0-0xFFF8 - The function ID
40731 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40732 * * 0xFFFD - Reserved for user-space HWRM interface
40735 uint16_t target_id;
40737 * A physical address pointer pointing to a host buffer that the
40738 * command's response data will be written. This can be either a host
40739 * physical address (HPA) or a guest physical address (GPA) and must
40740 * point to a physically contiguous block of memory.
40742 uint64_t resp_addr;
40744 /* Enumeration denoting the configuration mode. */
40745 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
40747 /* Disable the configuration mode. */
40748 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
40750 /* Enable the configuration mode. */
40751 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
40753 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
40754 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
40755 /* Enumeration denoting the RX, TX type of the resource. */
40756 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
40759 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
40760 (UINT32_C(0x0) << 1)
40762 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
40763 (UINT32_C(0x1) << 1)
40764 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
40765 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
40766 /* Enumeration denoting the data transfer mode. */
40767 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
40769 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
40771 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
40772 (UINT32_C(0x0) << 2)
40774 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
40775 (UINT32_C(0x1) << 2)
40776 /* Pull on async update. */
40777 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
40778 (UINT32_C(0x2) << 2)
40779 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
40780 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
40781 uint16_t counter_type;
40782 /* Flow counters. */
40783 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
40784 /* Extended flow counters. */
40785 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
40786 /* Meter drop counters. */
40787 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
40788 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
40789 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
40790 /* Ctx memory handle to be used for the counter. */
40792 /* Counter update cadence hint (only in Push mode). */
40793 uint16_t update_tmr_ms;
40794 /* Total number of entries. */
40795 uint32_t num_entries;
40799 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
40800 struct hwrm_cfa_counter_cfg_output {
40801 /* The specific error status for the command. */
40802 uint16_t error_code;
40803 /* The HWRM command request type. */
40805 /* The sequence ID from the original command. */
40807 /* The length of the response data in number of bytes. */
40809 uint8_t unused_0[7];
40811 * This field is used in Output records to indicate that the output
40812 * is completely written to RAM. This field should be read as '1'
40813 * to indicate that the output has been completely written.
40814 * When writing a command completion or response to an internal processor,
40815 * the order of writes has to be such that this field is written last.
40820 /***************************
40821 * hwrm_cfa_counter_qstats *
40822 ***************************/
40825 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
40826 struct hwrm_cfa_counter_qstats_input {
40827 /* The HWRM command request type. */
40830 * The completion ring to send the completion event on. This should
40831 * be the NQ ID returned from the `nq_alloc` HWRM command.
40833 uint16_t cmpl_ring;
40835 * The sequence ID is used by the driver for tracking multiple
40836 * commands. This ID is treated as opaque data by the firmware and
40837 * the value is returned in the `hwrm_resp_hdr` upon completion.
40841 * The target ID of the command:
40842 * * 0x0-0xFFF8 - The function ID
40843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40844 * * 0xFFFD - Reserved for user-space HWRM interface
40847 uint16_t target_id;
40849 * A physical address pointer pointing to a host buffer that the
40850 * command's response data will be written. This can be either a host
40851 * physical address (HPA) or a guest physical address (GPA) and must
40852 * point to a physically contiguous block of memory.
40854 uint64_t resp_addr;
40856 /* Enumeration denoting the RX, TX type of the resource. */
40857 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
40859 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
40861 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
40862 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
40863 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
40864 uint16_t counter_type;
40865 uint16_t input_flow_ctx_id;
40866 uint16_t num_entries;
40867 uint16_t delta_time_ms;
40868 uint16_t meter_instance_id;
40869 uint16_t mdc_ctx_id;
40870 uint8_t unused_0[2];
40871 uint64_t expected_count;
40874 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
40875 struct hwrm_cfa_counter_qstats_output {
40876 /* The specific error status for the command. */
40877 uint16_t error_code;
40878 /* The HWRM command request type. */
40880 /* The sequence ID from the original command. */
40882 /* The length of the response data in number of bytes. */
40884 uint8_t unused_0[7];
40886 * This field is used in Output records to indicate that the output
40887 * is completely written to RAM. This field should be read as '1'
40888 * to indicate that the output has been completely written.
40889 * When writing a command completion or response to an internal processor,
40890 * the order of writes has to be such that this field is written last.
40895 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */