1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
345 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
346 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
347 #define HWRM_RING_RESET UINT32_C(0x5e)
348 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
349 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
350 #define HWRM_RING_CFG UINT32_C(0x62)
351 #define HWRM_RING_QCFG UINT32_C(0x63)
352 /* Reserved for future use. */
353 #define HWRM_RESERVED5 UINT32_C(0x64)
354 /* Reserved for future use. */
355 #define HWRM_RESERVED6 UINT32_C(0x65)
356 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
357 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
358 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
359 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
360 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
361 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
362 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
363 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
364 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
365 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
366 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
367 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
369 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
371 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
372 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
373 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
374 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
376 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
378 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
380 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
381 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
382 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
383 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
384 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
385 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
386 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
387 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
388 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
389 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
390 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
391 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
392 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
393 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
394 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
396 #define HWRM_RESERVED7 UINT32_C(0xba)
397 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
398 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
399 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
400 #define HWRM_FW_RESET UINT32_C(0xc0)
401 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
402 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
403 #define HWRM_FW_SYNC UINT32_C(0xc3)
404 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
405 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
406 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
407 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
409 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
411 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
413 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
415 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
417 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
418 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
419 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
420 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
421 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
422 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
423 #define HWRM_FWD_RESP UINT32_C(0xd2)
424 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
425 #define HWRM_OEM_CMD UINT32_C(0xd4)
426 /* Tells the fw to run PRBS test on a given port and lane. */
427 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
428 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
429 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
430 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
431 /* Tells the fw to collect dsc dump on a given port and lane. */
432 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
433 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
434 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
435 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
436 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
437 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
438 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
439 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
440 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
442 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
444 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
446 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
448 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
450 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
452 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
454 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
456 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
458 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
460 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
462 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
464 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
466 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
468 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
470 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
472 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
474 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
476 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
478 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
479 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
480 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
481 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
483 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
485 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
487 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
489 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
490 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
491 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
493 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
495 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
497 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
499 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
501 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
503 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
505 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
507 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
509 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
511 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
513 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
515 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
517 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
519 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
521 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
523 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
525 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
527 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
528 /* Experimental - DEPRECATED */
529 #define HWRM_CFA_TFLIB UINT32_C(0x125)
530 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
531 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
532 /* Engine CKV - Add a new CKEK used to encrypt keys. */
533 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
534 /* Engine CKV - Delete a previously added CKEK. */
535 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
536 /* Engine CKV - Add a new key to the key vault. */
537 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
538 /* Engine CKV - Delete a key from the key vault. */
539 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
540 /* Engine CKV - Delete all keys from the key vault. */
541 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
542 /* Engine CKV - Get random data. */
543 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
544 /* Engine CKV - Generate and encrypt a new AES key. */
545 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
546 /* Engine CKV - Configure a label index with a label value. */
547 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
548 /* Engine CKV - Query a label */
549 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
550 /* Engine - Query the available queue groups configuration. */
551 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
552 /* Engine - Query the queue groups assigned to a function. */
553 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
554 /* Engine - Query the available queue group meter profile configuration. */
555 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
556 /* Engine - Query the configuration of a queue group meter profile. */
557 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
558 /* Engine - Allocate a queue group meter profile. */
559 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
560 /* Engine - Free a queue group meter profile. */
561 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
562 /* Engine - Query the meters assigned to a queue group. */
563 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
564 /* Engine - Bind a queue group meter profile to a queue group. */
565 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
566 /* Engine - Unbind a queue group meter profile from a queue group. */
567 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
568 /* Engine - Bind a queue group to a function. */
569 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
570 /* Engine - Query the scheduling group configuration. */
571 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
572 /* Engine - Query the queue groups assigned to a scheduling group. */
573 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
574 /* Engine - Query the configuration of a scheduling group's meter profiles. */
575 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
576 /* Engine - Configure a scheduling group's meter profiles. */
577 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
578 /* Engine - Bind a queue group to a scheduling group. */
579 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
580 /* Engine - Unbind a queue group from its scheduling group. */
581 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
582 /* Engine - Query the Engine configuration. */
583 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
584 /* Engine - Configure the statistics accumulator for an Engine. */
585 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
586 /* Engine - Clear the statistics accumulator for an Engine. */
587 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
588 /* Engine - Query the statistics accumulator for an Engine. */
589 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
590 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
591 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
592 /* Engine - Allocate an Engine RQ. */
593 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
594 /* Engine - Free an Engine RQ. */
595 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
596 /* Engine - Allocate an Engine CQ. */
597 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
598 /* Engine - Free an Engine CQ. */
599 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
600 /* Engine - Allocate an NQ. */
601 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
602 /* Engine - Free an NQ. */
603 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
604 /* Engine - Set the on-die RQE credit update location. */
605 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
606 /* Engine - Query the engine function configuration. */
607 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
609 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
611 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
613 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
615 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
617 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
618 /* Configures the BW of any VF */
619 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
620 /* Queries the BW of any VF */
621 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
622 /* Queries pf ids belong to specified host(s) */
623 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
624 /* Queries extended stats per function */
625 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
626 /* Queries extended statistics context */
627 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
629 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
631 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
633 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
635 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
637 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
639 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
640 /* Returns the current value of a free running counter from the device. */
641 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
643 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
645 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
647 * Tells the fw to run the DMA read from the host and DMA write
650 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
651 /* Tells the fw to program the fru memory */
652 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
653 /* Tells the fw to read the fru memory */
654 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
656 #define HWRM_TF UINT32_C(0x2bc)
658 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
660 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
662 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
664 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
666 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
668 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
670 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
672 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
674 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
676 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
678 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
680 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
682 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
684 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
686 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
688 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
690 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
692 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
694 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
696 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
698 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
700 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
702 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
704 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
706 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
708 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
710 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
712 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
714 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
716 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
718 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
720 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
722 #define HWRM_SV UINT32_C(0x400)
724 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
726 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
728 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
730 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
731 #define HWRM_DBG_DUMP UINT32_C(0xff14)
733 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
735 #define HWRM_DBG_CFG UINT32_C(0xff16)
737 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
739 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
741 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
743 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
745 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
747 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
749 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
751 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
752 /* Send driver debug information to firmware */
753 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
754 /* Query debug capabilities of firmware */
755 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
756 /* Retrieve debug settings of firmware */
757 #define HWRM_DBG_QCFG UINT32_C(0xff21)
758 /* Set destination parameters for crashdump medium */
759 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
760 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
762 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
763 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
764 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
765 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
766 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
767 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
768 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
769 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
770 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
771 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
772 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
773 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
774 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
775 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
776 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
777 #define HWRM_NVM_READ UINT32_C(0xfffd)
778 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
779 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
780 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
781 uint16_t unused_0[3];
785 /* ret_codes (size:64b/8B) */
788 /* Request was successfully executed by the HWRM. */
789 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
790 /* The HWRM failed to execute the request. */
791 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
793 * The request contains invalid argument(s) or input
796 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
798 * The requester is not allowed to access the requested
799 * resource. This error code shall be provided in a
800 * response to a request to query or modify an existing
801 * resource that is not accessible by the requester.
803 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
805 * The HWRM is unable to allocate the requested resource.
806 * This code only applies to requests for HWRM resource
809 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
811 * Invalid combination of flags is specified in the
814 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
816 * Invalid combination of enables fields is specified in
819 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
821 * Request contains a required TLV that is not supported by
822 * the installed version of firmware.
824 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
826 * No firmware buffer available to accept the request. Driver
827 * should retry the request.
829 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
831 * This error code is only reported by firmware when some
832 * sub-option of a supported HWRM command is unsupported.
834 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
836 * This error code is only reported by firmware when the specific
837 * request is not able to process when the HOT reset in progress.
839 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
841 * This error code is only reported by firmware when the registered
842 * driver instances are not capable of hot reset.
844 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
846 * This error code is only reported by the firmware when during
847 * flow allocation when a request for a flow counter fails because
848 * the number of flow counters are exhausted.
850 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
852 * This error code is only reported by firmware when the registered
853 * driver instances requested to offloaded a flow but was unable to because
854 * the requested key's hash collides with the installed keys.
856 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
858 * This error code is only reported by firmware when the registered
859 * driver instances requested to offloaded a flow but was unable to because
860 * the same key has already been installed.
862 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
864 * Generic HWRM execution error that represents an
867 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
869 * Firmware is unable to service the request at the present time. Caller
870 * may try again later.
872 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
874 * This error code is reported by Firmware when an operation requested
875 * by the host is not allowed due to a secure lock violation.
877 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
879 * This value indicates that the HWRM response is in TLV format and
880 * should be interpreted as one or more TLVs starting with the
881 * hwrm_resp_hdr TLV. This value is not an indication of any error
882 * by itself, just an indication that the response should be parsed
883 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
885 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
887 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
888 /* Unsupported or invalid command */
889 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
890 #define HWRM_ERR_CODE_LAST \
891 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
892 uint16_t unused_0[3];
896 /* hwrm_err_output (size:128b/16B) */
897 struct hwrm_err_output {
899 * Pass/Fail or error type
901 * Note: receiver to verify the in parameters, and fail the call
902 * with an error when appropriate
905 /* This field returns the type of original request. */
907 /* This field provides original sequence number of the command. */
910 * This field is the length of the response in bytes. The
911 * last byte of the response is a valid flag that will read
912 * as '1' when the command has been completely written to
916 /* debug info for this error response. */
918 /* debug info for this error response. */
921 * In the case of an error response, command specific error
922 * code is returned in this field.
926 * This field is used in Output records to indicate that the output
927 * is completely written to RAM. This field should be read as '1'
928 * to indicate that the output has been completely written.
929 * When writing a command completion or response to an internal processor,
930 * the order of writes has to be such that this field is written last.
935 * Following is the signature for HWRM message field that indicates not
936 * applicable (All F's). Need to cast it the size of the field if needed.
938 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
939 /* hwrm_func_buf_rgtr */
940 #define HWRM_MAX_REQ_LEN 128
941 /* hwrm_cfa_flow_info */
942 #define HWRM_MAX_RESP_LEN 704
943 /* 7 bit indirection table index. */
944 #define HW_HASH_INDEX_SIZE 0x80
945 #define HW_HASH_KEY_SIZE 40
946 /* valid key for HWRM response */
947 #define HWRM_RESP_VALID_KEY 1
948 /* Reserved for BONO processor */
949 #define HWRM_TARGET_ID_BONO 0xFFF8
950 /* Reserved for KONG processor */
951 #define HWRM_TARGET_ID_KONG 0xFFF9
952 /* Reserved for APE processor */
953 #define HWRM_TARGET_ID_APE 0xFFFA
955 * This value will be used by tools for User-space HWRM Interface.
956 * When tool execute any HWRM command with this target_id, firmware
957 * will copy the response and/or data payload via register space instead
960 #define HWRM_TARGET_ID_TOOLS 0xFFFD
961 #define HWRM_VERSION_MAJOR 1
962 #define HWRM_VERSION_MINOR 10
963 #define HWRM_VERSION_UPDATE 1
964 /* non-zero means beta version */
965 #define HWRM_VERSION_RSVD 70
966 #define HWRM_VERSION_STR "1.10.1.70"
973 /* hwrm_ver_get_input (size:192b/24B) */
974 struct hwrm_ver_get_input {
975 /* The HWRM command request type. */
978 * The completion ring to send the completion event on. This should
979 * be the NQ ID returned from the `nq_alloc` HWRM command.
983 * The sequence ID is used by the driver for tracking multiple
984 * commands. This ID is treated as opaque data by the firmware and
985 * the value is returned in the `hwrm_resp_hdr` upon completion.
989 * The target ID of the command:
990 * * 0x0-0xFFF8 - The function ID
991 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
992 * * 0xFFFD - Reserved for user-space HWRM interface
997 * A physical address pointer pointing to a host buffer that the
998 * command's response data will be written. This can be either a host
999 * physical address (HPA) or a guest physical address (GPA) and must
1000 * point to a physically contiguous block of memory.
1004 * This field represents the major version of HWRM interface
1005 * specification supported by the driver HWRM implementation.
1006 * The interface major version is intended to change only when
1007 * non backward compatible changes are made to the HWRM
1008 * interface specification.
1010 uint8_t hwrm_intf_maj;
1012 * This field represents the minor version of HWRM interface
1013 * specification supported by the driver HWRM implementation.
1014 * A change in interface minor version is used to reflect
1015 * significant backward compatible modification to HWRM
1016 * interface specification.
1017 * This can be due to addition or removal of functionality.
1018 * HWRM interface specifications with the same major version
1019 * but different minor versions are compatible.
1021 uint8_t hwrm_intf_min;
1023 * This field represents the update version of HWRM interface
1024 * specification supported by the driver HWRM implementation.
1025 * The interface update version is used to reflect minor
1026 * changes or bug fixes to a released HWRM interface
1029 uint8_t hwrm_intf_upd;
1030 uint8_t unused_0[5];
1033 /* hwrm_ver_get_output (size:1408b/176B) */
1034 struct hwrm_ver_get_output {
1035 /* The specific error status for the command. */
1036 uint16_t error_code;
1037 /* The HWRM command request type. */
1039 /* The sequence ID from the original command. */
1041 /* The length of the response data in number of bytes. */
1044 * This field represents the major version of HWRM interface
1045 * specification supported by the HWRM implementation.
1046 * The interface major version is intended to change only when
1047 * non backward compatible changes are made to the HWRM
1048 * interface specification.
1049 * A HWRM implementation that is compliant with this
1050 * specification shall provide value of 1 in this field.
1052 uint8_t hwrm_intf_maj_8b;
1054 * This field represents the minor version of HWRM interface
1055 * specification supported by the HWRM implementation.
1056 * A change in interface minor version is used to reflect
1057 * significant backward compatible modification to HWRM
1058 * interface specification.
1059 * This can be due to addition or removal of functionality.
1060 * HWRM interface specifications with the same major version
1061 * but different minor versions are compatible.
1062 * A HWRM implementation that is compliant with this
1063 * specification shall provide value of 2 in this field.
1065 uint8_t hwrm_intf_min_8b;
1067 * This field represents the update version of HWRM interface
1068 * specification supported by the HWRM implementation.
1069 * The interface update version is used to reflect minor
1070 * changes or bug fixes to a released HWRM interface
1072 * A HWRM implementation that is compliant with this
1073 * specification shall provide value of 2 in this field.
1075 uint8_t hwrm_intf_upd_8b;
1076 uint8_t hwrm_intf_rsvd_8b;
1078 * This field represents the major version of HWRM firmware.
1079 * A change in firmware major version represents a major
1082 uint8_t hwrm_fw_maj_8b;
1084 * This field represents the minor version of HWRM firmware.
1085 * A change in firmware minor version represents significant
1086 * firmware functionality changes.
1088 uint8_t hwrm_fw_min_8b;
1090 * This field represents the build version of HWRM firmware.
1091 * A change in firmware build version represents bug fixes
1092 * to a released firmware.
1094 uint8_t hwrm_fw_bld_8b;
1096 * This field is a reserved field. This field can be used to
1097 * represent firmware branches or customer specific releases
1098 * tied to a specific (major,minor,update) version of the
1101 uint8_t hwrm_fw_rsvd_8b;
1103 * This field represents the major version of mgmt firmware.
1104 * A change in major version represents a major release.
1106 uint8_t mgmt_fw_maj_8b;
1108 * This field represents the minor version of mgmt firmware.
1109 * A change in minor version represents significant
1110 * functionality changes.
1112 uint8_t mgmt_fw_min_8b;
1114 * This field represents the build version of mgmt firmware.
1115 * A change in update version represents bug fixes.
1117 uint8_t mgmt_fw_bld_8b;
1119 * This field is a reserved field. This field can be used to
1120 * represent firmware branches or customer specific releases
1121 * tied to a specific (major,minor,update) version
1123 uint8_t mgmt_fw_rsvd_8b;
1125 * This field represents the major version of network
1127 * A change in major version represents a major release.
1129 uint8_t netctrl_fw_maj_8b;
1131 * This field represents the minor version of network
1133 * A change in minor version represents significant
1134 * functionality changes.
1136 uint8_t netctrl_fw_min_8b;
1138 * This field represents the build version of network
1140 * A change in update version represents bug fixes.
1142 uint8_t netctrl_fw_bld_8b;
1144 * This field is a reserved field. This field can be used to
1145 * represent firmware branches or customer specific releases
1146 * tied to a specific (major,minor,update) version
1148 uint8_t netctrl_fw_rsvd_8b;
1150 * This field is used to indicate device's capabilities and
1153 uint32_t dev_caps_cfg;
1155 * If set to 1, then secure firmware update behavior
1157 * If set to 0, then secure firmware update behavior is
1160 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1163 * If set to 1, then firmware based DCBX agent is supported.
1164 * If set to 0, then firmware based DCBX agent capability
1165 * is not supported on this device.
1167 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1170 * If set to 1, then HWRM short command format is supported.
1171 * If set to 0, then HWRM short command format is not supported.
1173 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1176 * If set to 1, then HWRM short command format is required.
1177 * If set to 0, then HWRM short command format is not required.
1179 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1182 * If set to 1, then the KONG host mailbox channel is supported.
1183 * If set to 0, then the KONG host mailbox channel is not supported.
1184 * By default, this flag should be 0 for older version of core firmware.
1186 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1189 * If set to 1, then the 64bit flow handle is supported in addition to the
1190 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1191 * supported. By default, this flag should be 0 for older version of core firmware.
1193 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1196 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1197 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1198 * If set to 0, then filter types not supported.
1199 * By default, this flag should be 0 for older version of core firmware.
1201 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1204 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1205 * If set to 0, firmware can't supported virtio vSwitch offload model.
1206 * By default, this flag should be 0 for older version of core firmware.
1208 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1211 * If set to 1, firmware is capable to support trusted VF.
1212 * If set to 0, firmware is not capable to support trusted VF.
1213 * By default, this flag should be 0 for older version of core firmware.
1215 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1218 * If set to 1, firmware is capable to support flow aging.
1219 * If set to 0, firmware is not capable to support flow aging.
1220 * By default, this flag should be 0 for older version of core firmware.
1222 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1225 * If set to 1, firmware is capable to support advanced flow counters like,
1226 * Meter drop counters and EEM counters.
1227 * If set to 0, firmware is not capable to support advanced flow counters.
1228 * By default, this flag should be 0 for older version of core firmware.
1230 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1233 * If set to 1, the firmware is able to support the use of the CFA
1234 * Extended Exact Match(EEM) feature.
1235 * If set to 0, firmware is not capable to support the use of the
1237 * By default, this flag should be 0 for older version of core firmware.
1239 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1242 * If set to 1, the firmware is able to support advance CFA flow management
1243 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1244 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1246 * By default, this flag should be 0 for older version of core firmware.
1248 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1251 * Deprecated and replaced with cfa_truflow_supported.
1252 * If set to 1, the firmware is able to support TFLIB features.
1253 * If set to 0, then the firmware doesn’t support TFLIB features.
1254 * By default, this flag should be 0 for older version of core firmware.
1256 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1259 * If set to 1, the firmware is able to support TruFlow features.
1260 * If set to 0, then the firmware doesn’t support TruFlow features.
1261 * By default, this flag should be 0 for older version of
1264 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1267 * This field represents the major version of RoCE firmware.
1268 * A change in major version represents a major release.
1270 uint8_t roce_fw_maj_8b;
1272 * This field represents the minor version of RoCE firmware.
1273 * A change in minor version represents significant
1274 * functionality changes.
1276 uint8_t roce_fw_min_8b;
1278 * This field represents the build version of RoCE firmware.
1279 * A change in update version represents bug fixes.
1281 uint8_t roce_fw_bld_8b;
1283 * This field is a reserved field. This field can be used to
1284 * represent firmware branches or customer specific releases
1285 * tied to a specific (major,minor,update) version
1287 uint8_t roce_fw_rsvd_8b;
1289 * This field represents the name of HWRM FW (ASCII chars
1290 * with NULL at the end).
1292 char hwrm_fw_name[16];
1294 * This field represents the name of mgmt FW (ASCII chars
1295 * with NULL at the end).
1297 char mgmt_fw_name[16];
1299 * This field represents the name of network control
1300 * firmware (ASCII chars with NULL at the end).
1302 char netctrl_fw_name[16];
1303 /* This field represents the active board package name. */
1304 char active_pkg_name[16];
1306 * This field represents the name of RoCE FW (ASCII chars
1307 * with NULL at the end).
1309 char roce_fw_name[16];
1310 /* This field returns the chip number. */
1312 /* This field returns the revision of chip. */
1314 /* This field returns the chip metal number. */
1316 /* This field returns the bond id of the chip. */
1317 uint8_t chip_bond_id;
1318 /* This value indicates the type of platform used for chip implementation. */
1319 uint8_t chip_platform_type;
1321 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1322 /* FPGA platform of the chip. */
1323 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1324 /* Palladium platform of the chip. */
1325 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1326 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1327 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1329 * This field returns the maximum value of request window that
1330 * is supported by the HWRM. The request window is mapped
1331 * into device address space using MMIO.
1333 uint16_t max_req_win_len;
1335 * This field returns the maximum value of response buffer in
1338 uint16_t max_resp_len;
1340 * This field returns the default request timeout value in
1343 uint16_t def_req_timeout;
1345 * This field will indicate if any subsystems is not fully
1350 * If set to 1, it will indicate to host drivers that firmware is
1351 * not ready to start full blown HWRM commands. Host drivers should
1352 * re-try HWRM_VER_GET with some timeout period. The timeout period
1353 * can be selected up to 5 seconds.
1354 * For Example, PCIe hot-plug:
1355 * Hot plug timing is system dependent. It generally takes up to
1356 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1357 * If set to 0, device is ready to accept all HWRM commands.
1359 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1361 * If set to 1, external version present.
1362 * If set to 0, external version not present.
1364 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1365 uint8_t unused_0[2];
1367 * For backward compatibility this field must be set to 1.
1368 * Older drivers might look for this field to be 1 before
1369 * processing the message.
1373 * This field represents the major version of HWRM interface
1374 * specification supported by the HWRM implementation.
1375 * The interface major version is intended to change only when
1376 * non backward compatible changes are made to the HWRM
1377 * interface specification. A HWRM implementation that is
1378 * compliant with this specification shall provide value of 1
1381 uint16_t hwrm_intf_major;
1383 * This field represents the minor version of HWRM interface
1384 * specification supported by the HWRM implementation.
1385 * A change in interface minor version is used to reflect
1386 * significant backward compatible modification to HWRM
1387 * interface specification. This can be due to addition or
1388 * removal of functionality. HWRM interface specifications
1389 * with the same major version but different minor versions are
1390 * compatible. A HWRM implementation that is compliant with
1391 * this specification shall provide value of 2 in this field.
1393 uint16_t hwrm_intf_minor;
1395 * This field represents the update version of HWRM interface
1396 * specification supported by the HWRM implementation. The
1397 * interface update version is used to reflect minor changes or
1398 * bug fixes to a released HWRM interface specification.
1399 * A HWRM implementation that is compliant with this
1400 * specification shall provide value of 2 in this field.
1402 uint16_t hwrm_intf_build;
1404 * This field represents the patch version of HWRM interface
1405 * specification supported by the HWRM implementation.
1407 uint16_t hwrm_intf_patch;
1409 * This field represents the major version of HWRM firmware.
1410 * A change in firmware major version represents a major
1413 uint16_t hwrm_fw_major;
1415 * This field represents the minor version of HWRM firmware.
1416 * A change in firmware minor version represents significant
1417 * firmware functionality changes.
1419 uint16_t hwrm_fw_minor;
1421 * This field represents the build version of HWRM firmware.
1422 * A change in firmware build version represents bug fixes to
1423 * a released firmware.
1425 uint16_t hwrm_fw_build;
1427 * This field is a reserved field.
1428 * This field can be used to represent firmware branches or customer
1429 * specific releases tied to a specific (major,minor,update) version
1430 * of the HWRM firmware.
1432 uint16_t hwrm_fw_patch;
1434 * This field represents the major version of mgmt firmware.
1435 * A change in major version represents a major release.
1437 uint16_t mgmt_fw_major;
1439 * This field represents the minor version of HWRM firmware.
1440 * A change in firmware minor version represents significant
1441 * firmware functionality changes.
1443 uint16_t mgmt_fw_minor;
1445 * This field represents the build version of mgmt firmware.
1446 * A change in update version represents bug fixes.
1448 uint16_t mgmt_fw_build;
1450 * This field is a reserved field. This field can be used to
1451 * represent firmware branches or customer specific releases
1452 * tied to a specific (major,minor,update) version.
1454 uint16_t mgmt_fw_patch;
1456 * This field represents the major version of network control
1457 * firmware. A change in major version represents
1460 uint16_t netctrl_fw_major;
1462 * This field represents the minor version of network control
1463 * firmware. A change in minor version represents significant
1464 * functionality changes.
1466 uint16_t netctrl_fw_minor;
1468 * This field represents the build version of network control
1469 * firmware. A change in update version represents bug fixes.
1471 uint16_t netctrl_fw_build;
1473 * This field is a reserved field. This field can be used to
1474 * represent firmware branches or customer specific releases
1475 * tied to a specific (major,minor,update) version
1477 uint16_t netctrl_fw_patch;
1479 * This field represents the major version of RoCE firmware.
1480 * A change in major version represents a major release.
1482 uint16_t roce_fw_major;
1484 * This field represents the minor version of RoCE firmware.
1485 * A change in minor version represents significant
1486 * functionality changes.
1488 uint16_t roce_fw_minor;
1490 * This field represents the build version of RoCE firmware.
1491 * A change in update version represents bug fixes.
1493 uint16_t roce_fw_build;
1495 * This field is a reserved field. This field can be used to
1496 * represent firmware branches or customer specific releases
1497 * tied to a specific (major,minor,update) version
1499 uint16_t roce_fw_patch;
1501 * This field returns the maximum extended request length acceptable
1502 * by the device which allows requests greater than mailbox size when
1503 * used with the short cmd request format.
1505 uint16_t max_ext_req_len;
1506 uint8_t unused_1[5];
1508 * This field is used in Output records to indicate that the output
1509 * is completely written to RAM. This field should be read as '1'
1510 * to indicate that the output has been completely written.
1511 * When writing a command completion or response to an internal processor,
1512 * the order of writes has to be such that this field is written last.
1517 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1518 struct cfa_bds_read_cmd_data_msg {
1519 /* This value selects the format for the mid-path command for the CFA. */
1522 * This is read command. From 32 to 128B can be read from a table
1523 * using this command.
1525 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1526 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1527 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1528 /* This value selects the table type to be acted upon. */
1530 /* This value selects the table type to be acted upon. */
1531 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1532 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1533 /* This command acts on the action table of the specified scope. */
1534 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1535 /* This command acts on the exact match table of the specified scope. */
1536 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1537 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1538 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1539 /* This value selects which table scope will be accessed. */
1540 uint8_t table_scope;
1541 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1542 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1544 * This value identifies the number of 32B units will be accessed. A
1545 * value of zero is invalid. Maximum value is 4.
1548 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1549 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1550 /* This is the 32B index into the selected table to access. */
1551 uint32_t table_index;
1552 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1553 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1555 * This is the 64b host address where you want the data returned to. The
1556 * data will be written to the same function as the one that owns the SQ
1557 * this command is read from. The bottom two bits of this value must be
1558 * zero. The size of the write is controlled by the data_size field.
1560 uint64_t host_address;
1563 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1564 struct cfa_bds_write_cmd_data_msg {
1565 /* This value selects the format for the mid-path command for the CFA. */
1568 * This is write command. From 32 to 128B can be written to a table
1569 * using this command.
1571 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1572 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1573 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1574 /* This value selects the table type to be acted upon. */
1575 uint8_t write_thru_table_type;
1576 /* This value selects the table type to be acted upon. */
1577 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1578 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1579 /* This command acts on the action table of the specified scope. */
1580 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1581 /* This command acts on the exact match table of the specified scope. */
1582 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1583 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1584 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1586 * Indicates write-through control. Indicates write-through when set,
1587 * or write back when cleared.
1589 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1590 /* This value selects which table scope will be accessed. */
1591 uint8_t table_scope;
1592 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1593 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1595 * This value identifies the number of 32B units will be accessed. A
1596 * value of zero is invalid. Maximum value is 4.
1599 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1600 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1601 /* This is the 32B index into the selected table to access. */
1602 uint32_t table_index;
1603 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1604 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1608 * This is the data to be written. Data length is determined by the
1609 * data_size field. The bd_cnt in the encapsulating BD must also be set
1610 * correctly to ensure that the BD is processed correctly and the full
1611 * WRITE_CMD message is extracted from the BD.
1616 /* cfa_bds_read_clr_cmd_data_msg (size:192b/24B) */
1617 struct cfa_bds_read_clr_cmd_data_msg {
1618 /* This value selects the format for the mid-path command for the CFA. */
1621 * This is read-clear command. 32B can be read from a table and
1622 * a 16b mask can be used to clear specific 16b units after the
1623 * read as an atomic operation.
1625 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1626 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1627 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1628 /* This value selects the table type to be acted upon. */
1630 /* This value selects the table type to be acted upon. */
1631 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1632 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1633 /* This command acts on the action table of the specified scope. */
1634 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1635 /* This command acts on the exact match table of the specified scope. */
1636 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1637 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1638 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1639 /* This value selects which table scope will be accessed. */
1640 uint8_t table_scope;
1641 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1642 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1644 /* This is the 32B index into the selected table to access. */
1645 uint32_t table_index;
1646 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1648 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1650 * This is the 64b host address where you want the data returned to. The
1651 * data will be written to the same function as the one that owns the SQ
1652 * this command is read from. The bottom two bits of this value must be
1653 * zero. The size of the write is controlled by the data_size field.
1655 uint64_t host_address;
1657 * This is active high clear mask for the 32B of data that this command
1658 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1659 * of data read when set to '1'.
1661 uint16_t clear_mask;
1662 uint16_t unused1[3];
1665 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1666 struct cfa_bds_em_insert_cmd_data_msg {
1667 /* This value selects the format for the mid-path command for the CFA. */
1670 * An exact match table insert will be attempted into the table.
1671 * If there is a free location in the bucket, the payload will
1672 * be written to the bucket.
1674 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1675 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1676 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1678 * Indicates write-through control. Indicates write-through when set,
1679 * or write back when cleared.
1682 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1683 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1685 * Indicates write-through control. Indicates write-through when set,
1686 * or write back when cleared.
1688 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1689 /* This value selects which table scope will be accessed. */
1690 uint8_t table_scope;
1691 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1692 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1694 * This value identifies the number of 32B units will be accessed. A
1695 * value of zero is invalid. Maximum value is 4.
1698 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1699 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1700 /* This is the 32B index into the selected table to access. */
1701 uint32_t table_index;
1702 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1704 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1706 * This is the 64b host address where you want the data returned to. The
1707 * data will be written to the same function as the one that owns the SQ
1709 uint64_t host_address;
1711 * This is the Exact Match Lookup Record. Data length is determined by
1712 * the data_size field. The bd_cnt in the encapsulating BD must also be
1717 /* cfa_bds_em_delete_cmd_data_msg (size:192b/24B) */
1718 struct cfa_bds_em_delete_cmd_data_msg {
1719 /* This value selects the format for the mid-path command for the CFA. */
1721 /* An exact match table delete will be attempted. */
1722 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1723 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1724 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1726 * Indicates write-through control. Indicates write-through when set,
1727 * or write back when cleared.
1730 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1731 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1733 * Indicates write-through control. Indicates write-through when set,
1734 * or write back when cleared.
1736 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1737 /* This value selects which table scope will be accessed. */
1738 uint8_t table_scope;
1739 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1740 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1742 * This value identifies the number of 32B units will be accessed. A
1743 * value of zero is invalid. Maximum value is 4.
1746 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1747 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1750 * This is the 64b host address where you want the data returned to. The
1751 * data will be written to the same function as the one that owns the SQ
1753 uint64_t host_address;
1755 * This is the Exact Match Lookup Record. Data length is determined by
1756 * the data_size field. The bd_cnt in the encapsulating BD must also be
1761 /* cfa_bds_invalidate_cmd_data_msg (size:64b/8B) */
1762 struct cfa_bds_invalidate_cmd_data_msg {
1763 /* This value selects the format for the mid-path command for the CFA. */
1766 * The specified table area will be invalidated. If it is needed.
1767 * again, it will be read from the backing store.
1769 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1770 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1771 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1772 /* This value selects the table type to be acted upon. */
1774 /* This value selects the table type to be acted upon. */
1775 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1776 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1777 /* This command acts on the action table of the specified scope. */
1778 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1780 /* This command acts on the exact match table of the specified scope. */
1781 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1783 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1784 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1785 /* This value selects which table scope will be accessed. */
1786 uint8_t table_scope;
1787 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1788 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1790 /* This is the 32B index into the selected table to access. */
1791 uint32_t table_index;
1792 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1794 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1797 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1798 struct cfa_bds_event_collect_cmd_data_msg {
1799 /* This value selects the format for the mid-path command for the CFA. */
1801 /* Reads notification messages from the Host Notification Queue. */
1802 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1804 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1805 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1807 /* This value selects which table scope will be accessed. */
1808 uint8_t table_scope;
1809 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1811 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1813 * This value identifies the number of 32B units will be accessed. A
1814 * value of zero is invalid. Maximum value is 4.
1817 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1818 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1821 * This is the 64b host address where you want the data returned to. The
1822 * data will be written to the same function as the one that owns the SQ
1824 uint64_t host_address;
1827 /* ce_bds_add_data_msg (size:512b/64B) */
1828 struct ce_bds_add_data_msg {
1829 uint32_t version_algorithm_kid_opcode;
1831 * This value selects the operation for the mid-path command for the
1834 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1835 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
1837 * This is the add command. Using this opcode, Host Driver can add
1838 * information required for kTLS processing. The information is
1839 * updated in the CFCK context.
1841 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
1842 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
1843 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
1845 * This field is the Crypto Context ID. The KID is used to store
1846 * information used by the associated kTLS offloaded connection.
1848 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
1850 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
1852 * Currently only two algorithms are supported, AES_GCM_128 and
1853 * AES_GCM_256. Additional bits for future growth.
1855 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
1857 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
1858 /* AES_GCM_128 Algorithm */
1859 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
1861 /* AES_GCM_256 Algorithm */
1862 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
1865 * Version number of TLS connection. HW will provide registers that
1866 * converts the 4b encoded version number to 16b of actual version
1867 * number in the TLS Header. * Initialized --> By mid-path command *
1868 * Updated --> Never though another mid-path command will result in an
1871 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
1872 UINT32_C(0xf0000000)
1873 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
1874 /* TLS1.2 Version */
1875 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
1876 (UINT32_C(0x0) << 28)
1877 /* TLS1.3 Version */
1878 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
1879 (UINT32_C(0x1) << 28)
1880 #define CE_BDS_ADD_DATA_MSG__LAST \
1881 CE_BDS_ADD_DATA_MSG__TLS1_3
1883 * Command Type in the TLS header. HW will provide registers that
1884 * converts the 3b encoded command type to 8b of actual command type in
1885 * the TLS Header. * Initialized --> By mid-path command * Updated -->
1886 * Never though another mid-path command will result in an update
1889 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
1890 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
1892 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
1893 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
1894 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
1897 * Salt is part of the nonce that is used as the Initial Vector (IV) in
1898 * AES-GCM cipher suites. These are exchanged as part of the handshake
1899 * process and is either the client_write_iv (when the client is
1900 * sending) or server_write_iv (when the server is sending). In
1901 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
1902 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
1903 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
1904 * the 12B of IV. This value is initialized by this mid-path command.
1909 * This field keeps track of the TCP sequence number that is expected as
1910 * the first byte in the next TCP packet. This field is calculated by HW
1911 * using the output of the parser. The field is initialized as part of
1912 * the Mid-path BD download/update of a kTLS connection. For every TCP
1913 * packet processed, TCE HW will update the value to Current packet TCP
1914 * sequence number + Current packet TCP Payload Length.
1916 uint32_t pkt_tcp_seq_num;
1918 * This field maintains the TCP sequence number of the first byte in the
1919 * header of the active TLS record. This field is initialized as part of
1920 * the Mid-path BD download/update of a kTLS connection. For every
1921 * record that is processed, TCE HW copies the value from the
1922 * next_tls_header_tcp_seq_num field.
1924 uint32_t tls_header_tcp_seq_num;
1926 * This is sequence number for the TLS record in a particular session.
1927 * In TLS1.2, record sequence number is part of the Associated Data (AD)
1928 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
1929 * the Initial Vector (IV). The field is initialized as part of the
1930 * mid-path BD download/update of a kTLS connection. TCE HW increments
1931 * the field after that for every record processed as it parses the TCP
1934 uint32_t record_seq_num[2];
1936 * Key used for encrypting or decrypting TLS records. The Key is
1937 * exchanged during the hand-shake protocol by the client-server and
1938 * provided to HW through this mid-path BD.
1940 uint32_t session_key[8];
1943 /* ce_bds_delete_data_msg (size:64b/8B) */
1944 struct ce_bds_delete_data_msg {
1945 uint32_t kid_opcode;
1947 * This value selects the operation for the mid-path command for the
1950 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1951 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
1953 * This is the delete command. Using this opcode, the host Driver
1954 * can remove a key context from the CFCK. If context is deleted
1955 * and packets with the same KID come through the pipeline, the
1956 * following actions are taken. For transmit packets, no crypto
1957 * operation will be performed, payload will be zero'ed out. For
1958 * receive packets, no crypto operation will be performed,
1959 * payload will be unmodified.
1961 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
1962 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
1963 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
1965 * This field is the Crypto Context ID. The KID is used to store
1966 * information used by the associated kTLS offloaded connection.
1968 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
1969 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
1973 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
1974 struct ce_bds_resync_resp_ack_msg {
1975 uint32_t resync_status_kid_opcode;
1977 * This value selects the operation for the mid-path command for the
1980 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
1981 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
1983 * This command is used by the driver as a response to the resync
1984 * request sent by the crypto engine.
1986 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
1987 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
1988 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
1990 * This field is the Crypto Context ID. The KID is used to store
1991 * information used by the associated kTLS offloaded connection.
1993 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
1994 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
1996 * This field indicates if the resync request resulted in a success or
1999 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2002 * An ACK indicates that the driver was able to find the TLS record
2003 * associated with TCP sequence number provided by the HW
2005 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2006 (UINT32_C(0x0) << 24)
2007 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2008 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2010 * This field is the echo of the TCP sequence number provided in the
2011 * resync request by the HW. If HW sent multiple resync requests, it
2012 * only tracks the latest TCP sequence number. When the response from
2013 * the Driver doesn't match the latest request, HW will drop the resync
2016 uint32_t resync_record_tcp_seq_num;
2018 * This field indicates the TLS record sequence number associated with
2019 * the resync request. HW will take this number and add the delta records
2020 * it has found since sending the resync request, update the context and
2021 * resume decrypting records.
2023 uint32_t resync_record_seq_num[2];
2026 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2027 struct ce_bds_resync_resp_nack_msg {
2028 uint32_t resync_status_kid_opcode;
2030 * This value selects the operation for the mid-path command for the
2033 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2034 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2036 * This command is used by the driver as a response to the resync
2037 * request sent by the crypto engine.
2039 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2040 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2041 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2043 * This field is the Crypto Context ID. The KID is used to store
2044 * information used by the associated kTLS offloaded connection.
2046 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2048 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2050 * This field indicates if the resync request resulted in a success or
2053 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2056 * An NAK indicates that the driver wasn't able to find the TLS
2057 * record associated with TCP sequence number provided by the HW
2059 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2060 (UINT32_C(0x1) << 24)
2061 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2062 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2064 * This field is the echo of the TCP sequence number provided in the
2065 * resync request by the HW. If HW sent multiple resync requests, it
2066 * only tracks the latest TCP sequence number. When the response from
2067 * the Driver doesn't match the latest request, HW will drop the resync
2070 uint32_t resync_record_tcp_seq_num;
2073 /* crypto_presync_bd_cmd (size:256b/32B) */
2074 struct crypto_presync_bd_cmd {
2077 * Typically, presync BDs are used for packet retransmissions. Source
2078 * port sends all the packets in order over the network to destination
2079 * port and packets get dropped in the network. The destination port
2080 * will request retranmission of dropped packets and source port driver
2081 * will send presync BD to setup the transmitter appropriately. It will
2082 * provide the start and end TCP sequence number of the data to be
2083 * transmitted. HW keeps two sets of context variable, one for in order
2084 * traffic and one for retransmission traffic. HW is designed to
2085 * transmit everything posted in the presync BD and return to in order
2086 * mode after that. No inorder context variables are updated in the
2087 * process. There is a special case where packets can be dropped
2088 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2089 * ex) and HW still needs to transmit rest of the traffic. In this
2090 * mode, driver will send a presync BD as if it is a retransmission but
2091 * at the end of the transmission, the in order variables need to be
2092 * updated. This flag is used by driver to indicate that in order
2093 * variables needs to be updated at the end of completing the task
2094 * associated with the presync BD.
2096 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2101 * This field maintains the TCP sequence number of the first byte in the
2102 * Header of the active TLS record. This field is set to 0 during
2103 * mid-path BD updates, but is set to correct value when a presync BD is
2104 * detected. For every record that is processed, the value from the
2105 * next_tls_header_tcp_seq_num field is copied.
2107 uint32_t header_tcp_seq_num;
2109 * When a retransmitted packet has a TLS authentication TAG present and
2110 * the data spans multiple TCP Packets, HW is required to read the entire
2111 * record to recalculate the TAG but only transmit what is required. This
2112 * field is the start TCP sequence number of the packet(s) that need to
2113 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2114 * add command and initialized to value provided by the driver when
2115 * Pre-sync BD is detected. This field is never updated unless another
2116 * Pre-sync BD signaling a new retransmission is scheduled.
2118 uint32_t start_tcp_seq_num;
2120 * When a retransmitted packet has a TLS authentication TAG present and
2121 * the data spans multiple TCP Packets, HW is required to read the
2122 * entire record to recalculate the TAG but only transmit what is
2123 * required. This field is the end TCP sequence number of the packet(s)
2124 * that need to be re-transmitted. This field is initialized to 0 during
2125 * Mid-path BD add command and initialized to value provided by the
2126 * driver when Pre-sync BD is detected. This field is never updated
2127 * unless another Pre-sync BD signaling a new retransmission is
2130 uint32_t end_tcp_seq_num;
2132 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2133 * with the SALT). For retans packets, this field is extracted from the
2134 * TLS record, field right after the TLS Header and stored in the
2135 * context. This field needs to be stored in context as TCP segmentation
2136 * could have split the field into multiple TCP packets. This value is
2137 * initialized to 0 when presync BD is detected by taking the value from
2138 * the first TLS header. When subsequent TLS Headers are detected, the
2139 * value is extracted from packet.
2141 uint32_t explicit_nonce[2];
2143 * This is sequence number for the TLS record in a particular session. In
2144 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2145 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2146 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2147 * download. Is initialized to correct value when a pre-sync BD is
2148 * detected. TCE HW increments the field after that for every record
2149 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2150 * delivering more retransmission instruction will also update this
2153 uint32_t record_seq_num[2];
2156 /* bd_base (size:64b/8B) */
2159 /* This value identifies the type of buffer descriptor. */
2160 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2161 #define BD_BASE_TYPE_SFT 0
2163 * Indicates that this BD is 16B long and is used for
2164 * normal L2 packet transmission.
2166 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2168 * Indicates that this BD is 1BB long and is an empty
2169 * TX BD. Not valid for use by the driver.
2171 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2173 * Indicates that this BD is 16B long and is an RX Producer
2174 * (i.e. empty) buffer descriptor.
2176 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2178 * Indicates that this BD is 16B long and is an RX
2179 * Producer Buffer BD.
2181 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2183 * Indicates that this BD is 16B long and is an
2184 * RX Producer Assembly Buffer Descriptor.
2186 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2188 * Indicates that this BD is used to issue a command to one of
2189 * the mid-path destinations.
2191 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2193 * Indicates that this BD is used to issue a cryptographic pre-
2194 * sync command through the fast path and destined for TCE.
2196 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2198 * Indicates that this BD is 32B long and is used for
2199 * normal L2 packet transmission.
2201 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2203 * Indicates that this BD is 32B long and is used for
2204 * L2 packet transmission for small packets that require
2207 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2208 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2209 uint8_t unused_1[7];
2212 /* tx_bd_short (size:128b/16B) */
2213 struct tx_bd_short {
2215 * All bits in this field must be valid on the first BD of a packet.
2216 * Only the packet_end bit must be valid for the remaining BDs
2219 uint16_t flags_type;
2220 /* This value identifies the type of buffer descriptor. */
2221 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2222 #define TX_BD_SHORT_TYPE_SFT 0
2224 * Indicates that this BD is 16B long and is used for
2225 * normal L2 packet transmission.
2227 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2228 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2230 * All bits in this field must be valid on the first BD of a packet.
2231 * Only the packet_end bit must be valid for the remaining BDs
2234 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2235 #define TX_BD_SHORT_FLAGS_SFT 6
2237 * If set to 1, the packet ends with the data in the buffer
2238 * pointed to by this descriptor. This flag must be
2239 * valid on every BD.
2241 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2243 * If set to 1, the device will not generate a completion for
2244 * this transmit packet unless there is an error in it's
2247 * is set to 0, then the packet will be completed normally.
2249 * This bit must be valid only on the first BD of a packet.
2251 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2253 * This value indicates how many 16B BD locations are consumed
2254 * in the ring by this packet.
2255 * A value of 1 indicates that this BD is the only BD (and that
2256 * it is a short BD). A value
2257 * of 3 indicates either 3 short BDs or 1 long BD and one short
2258 * BD in the packet. A value of 0 indicates
2259 * that there are 32 BD locations in the packet (the maximum).
2261 * This field is valid only on the first BD of a packet.
2263 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2264 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2266 * This value is a hint for the length of the entire packet.
2267 * It is used by the chip to optimize internal processing.
2269 * The packet will be dropped if the hint is too short.
2271 * This field is valid only on the first BD of a packet.
2273 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2274 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2275 /* indicates packet length < 512B */
2276 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2277 /* indicates 512 <= packet length < 1KB */
2278 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2279 /* indicates 1KB <= packet length < 2KB */
2280 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2281 /* indicates packet length >= 2KB */
2282 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2283 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2284 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2286 * If set to 1, the device immediately updates the Send Consumer
2287 * Index after the buffer associated with this descriptor has
2288 * been transferred via DMA to NIC memory from host memory. An
2289 * interrupt may or may not be generated according to the state
2290 * of the interrupt avoidance mechanisms. If this bit
2291 * is set to 0, then the Consumer Index is only updated as soon
2292 * as one of the host interrupt coalescing conditions has been met.
2294 * This bit must be valid on the first BD of a packet.
2296 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2298 * This is the length of the host physical buffer this BD describes
2301 * This field must be valid on all BDs of a packet.
2305 * The opaque data field is pass through to the completion and can be
2306 * used for any data that the driver wants to associate with the
2309 * This field must be valid on the first BD of a packet. If completion
2310 * coalescing is enabled on the TX ring, it is suggested that the driver
2311 * populate the opaque field to indicate the specific TX ring with which
2312 * the completion is associated, then utilize the opaque and sq_cons_idx
2313 * fields in the coalesced completion record to determine the specific
2314 * packets that are to be completed on that ring.
2318 * This is the host physical address for the portion of the packet
2319 * described by this TX BD.
2321 * This value must be valid on all BDs of a packet.
2326 /* tx_bd_long (size:128b/16B) */
2328 /* This value identifies the type of buffer descriptor. */
2329 uint16_t flags_type;
2331 * This value indicates the type of buffer descriptor.
2334 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2335 #define TX_BD_LONG_TYPE_SFT 0
2337 * Indicates that this BD is 32B long and is used for
2338 * normal L2 packet transmission.
2340 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2341 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2343 * All bits in this field must be valid on the first BD of a packet.
2344 * Only the packet_end bit must be valid for the remaining BDs
2347 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2348 #define TX_BD_LONG_FLAGS_SFT 6
2350 * If set to 1, the packet ends with the data in the buffer
2351 * pointed to by this descriptor. This flag must be
2352 * valid on every BD.
2354 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2356 * If set to 1, the device will not generate a completion for
2357 * this transmit packet unless there is an error in it's
2360 * is set to 0, then the packet will be completed normally.
2362 * This bit must be valid only on the first BD of a packet.
2364 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2366 * This value indicates how many 16B BD locations are consumed
2367 * in the ring by this packet.
2368 * A value of 1 indicates that this BD is the only BD (and that
2369 * it is a short BD). A value
2370 * of 3 indicates either 3 short BDs or 1 long BD and one short
2371 * BD in the packet. A value of 0 indicates
2372 * that there are 32 BD locations in the packet (the maximum).
2374 * This field is valid only on the first BD of a packet.
2376 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2377 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2379 * This value is a hint for the length of the entire packet.
2380 * It is used by the chip to optimize internal processing.
2382 * The packet will be dropped if the hint is too short.
2384 * This field is valid only on the first BD of a packet.
2386 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2387 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2388 /* indicates packet length < 512B */
2389 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2390 /* indicates 512 <= packet length < 1KB */
2391 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2392 /* indicates 1KB <= packet length < 2KB */
2393 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2394 /* indicates packet length >= 2KB */
2395 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2396 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2398 * If set to 1, the device immediately updates the Send Consumer
2399 * Index after the buffer associated with this descriptor has
2400 * been transferred via DMA to NIC memory from host memory. An
2401 * interrupt may or may not be generated according to the state
2402 * of the interrupt avoidance mechanisms. If this bit
2403 * is set to 0, then the Consumer Index is only updated as soon
2404 * as one of the host interrupt coalescing conditions has been met.
2406 * This bit must be valid on the first BD of a packet.
2408 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2410 * This is the length of the host physical buffer this BD describes
2413 * This field must be valid on all BDs of a packet.
2417 * The opaque data field is passed through to the completion and can be
2418 * used for any data that the driver wants to associate with the
2421 * This field must be valid on the first BD of a packet. If completion
2422 * coalescing is enabled on the TX ring, it is suggested that the driver
2423 * populate the opaque field to indicate the specific TX ring with which
2424 * the completion is associated, then utilize the opaque and sq_cons_idx
2425 * fields in the coalesced completion record to determine the specific
2426 * packets that are to be completed on that ring.
2430 * This is the host physical address for the portion of the packet
2431 * described by this TX BD.
2433 * This value must be valid on all BDs of a packet.
2438 /* Last 16 bytes of tx_bd_long. */
2439 /* tx_bd_long_hi (size:128b/16B) */
2440 struct tx_bd_long_hi {
2442 * All bits in this field must be valid on the first BD of a packet.
2443 * Their value on other BDs of the packet will be ignored.
2447 * If set to 1, the controller replaces the TCP/UPD checksum
2448 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2449 * checksum field of the encapsulated TCP/UDP packets with the
2450 * hardware calculated TCP/UDP checksum for the packet associated
2451 * with this descriptor. The flag is ignored if the LSO flag is set.
2453 * This bit must be valid on the first BD of a packet.
2455 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2457 * If set to 1, the controller replaces the IP checksum of the
2458 * normal packets, or the inner IP checksum of the encapsulated
2459 * packets with the hardware calculated IP checksum for the
2460 * packet associated with this descriptor.
2462 * This bit must be valid on the first BD of a packet.
2464 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2466 * If set to 1, the controller will not append an Ethernet CRC
2467 * to the end of the frame.
2469 * This bit must be valid on the first BD of a packet.
2471 * Packet must be 64B or longer when this flag is set. It is not
2472 * useful to use this bit with any form of TX offload such as
2473 * CSO or LSO. The intent is that the packet from the host already
2474 * has a valid Ethernet CRC on the packet.
2476 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2478 * If set to 1, the device will record the time at which the packet
2479 * was actually transmitted at the TX MAC for 2-step time sync.
2481 * This bit must be valid on the first BD of a packet.
2483 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2485 * If set to 1, The controller replaces the tunnel IP checksum
2486 * field with hardware calculated IP checksum for the IP header
2487 * of the packet associated with this descriptor.
2489 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2490 * needs to be enabled. If the global outer UDP checksum TE_NIC register
2491 * bit is set, outer UDP checksum will be calculated for the following
2493 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
2494 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
2495 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
2496 * checksum will not be calculated.
2497 * 2. Packets with lso flag set which implies inner TCP checksum calculation
2498 * as part of LSO operation.
2500 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2502 * If set to 1, the device will treat this packet with LSO(Large
2503 * Send Offload) processing for both normal or encapsulated
2504 * packets, which is a form of TCP segmentation. When this bit
2505 * is 1, the hdr_size and mss fields must be valid. The driver
2506 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2507 * tcp_udp_chksum flags since the controller will replace the
2508 * appropriate checksum fields for segmented packets.
2510 * When this bit is 1, the hdr_size and mss fields must be valid.
2512 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2514 * If set to zero when LSO is '1', then the IPID will be treated
2515 * as a 16b number and will be wrapped if it exceeds a value of
2518 * If set to one when LSO is '1', then the IPID will be treated
2519 * as a 15b number and will be wrapped if it exceeds a value 0f
2522 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2524 * If set to zero when LSO is '1', then the IPID of the tunnel
2525 * IP header will not be modified during LSO operations.
2527 * If set to one when LSO is '1', then the IPID of the tunnel
2528 * IP header will be incremented for each subsequent segment of an
2531 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2534 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2536 * If set to '1', then the RoCE ICRC will be appended to the
2537 * packet. Packet must be a valid RoCE format packet.
2539 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2541 * If set to '1', then the FCoE CRC will be appended to the
2542 * packet. Packet must be a valid FCoE format packet.
2544 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2546 * If set to '1', then the timestamp from the BD is used. If cleared
2547 * to 0, then TWE provides the timestamp.
2549 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2551 * If set to '1', this operation will cause a trace capture in each
2552 * block it passes through.
2554 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2556 * If set to '1', the device will record the time at which the packet
2557 * was actually transmitted at the TX MAC for 1-step time sync. This
2558 * bit must be valid on the first BD of a packet.
2560 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2562 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2563 * field with hardware calculated IP checksum for the IP header of the
2564 * packet associated with this descriptor. For outer UDP checksum, it
2565 * will be the following behavior for all cases independent of settings
2566 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2567 * is 0, then do not update it. If outer UDP checksum is non zero, then
2568 * the hardware should compute and update it.
2570 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2572 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2573 * header will not be modified during LSO operations. If set to one
2574 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2575 * incremented for each subsequent segment of an LSO operation. The
2576 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2579 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2581 * If set to '1', When set to 1, KTLS encryption will be enabled for
2584 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2585 uint16_t kid_or_ts_low_hdr_size;
2587 * When LSO is '1', this field must contain the offset of the
2588 * TCP payload from the beginning of the packet in as
2589 * 16b words. In case of encapsulated/tunneling packet, this field
2590 * contains the offset of the inner TCP payload from beginning of the
2591 * packet as 16-bit words.
2593 * This value must be valid on the first BD of a packet.
2595 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2596 #define TX_BD_LONG_HDR_SIZE_SFT 0
2598 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2599 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
2602 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2603 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2604 uint32_t kid_or_ts_high_mss;
2606 * This is the MSS value that will be used to do the LSO processing.
2607 * The value is the length in bytes of the TCP payload for each
2608 * segment generated by the LSO operation.
2610 * This value must be valid on the first BD of a packet.
2612 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2613 #define TX_BD_LONG_MSS_SFT 0
2615 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2616 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2617 * of this field contain the upper 13 bits of the 20-bit KID.
2619 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2620 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2622 * This value selects bits 25:16 of the CFA action to perform on the
2623 * packet. See the cfa_action field for more information.
2625 uint16_t cfa_action_high;
2626 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2627 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2629 * This value selects a CFA action to perform on the packet.
2630 * Set this value to zero if no CFA action is desired.
2632 * This value must be valid on the first BD of a packet.
2634 uint16_t cfa_action;
2636 * This value is action meta-data that defines CFA edit operations
2637 * that are done in addition to any action editing.
2640 /* When key=1, This is the VLAN tag VID value. */
2641 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2642 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2643 /* When key=1, This is the VLAN tag DE value. */
2644 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2645 /* When key=1, This is the VLAN tag PRI value. */
2646 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2647 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2648 /* When key=1, This is the VLAN tag TPID select value. */
2649 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2650 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2652 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
2654 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
2656 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
2658 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
2660 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
2661 /* Value programmed in CFA VLANTPID register. */
2662 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
2663 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2664 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2665 /* When key=1, This is the VLAN tag TPID select value. */
2666 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2667 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2669 * This field identifies the type of edit to be performed
2672 * This value must be valid on the first BD of a packet.
2674 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2675 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2677 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
2679 * - meta[17:16] - TPID select value (0 = 0x8100).
2680 * - meta[15:12] - PRI/DE value.
2681 * - meta[11:0] - VID value.
2683 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
2684 #define TX_BD_LONG_CFA_META_KEY_LAST \
2685 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
2689 * This structure is used to inform the NIC of packet data that needs to be
2690 * transmitted with additional processing that requires extra data such as
2691 * VLAN insertion plus attached inline data. This BD type may be used to
2692 * improve latency for small packets needing the additional extended features
2693 * supported by long BDs.
2695 /* tx_bd_long_inline (size:256b/32B) */
2696 struct tx_bd_long_inline {
2697 uint16_t flags_type;
2698 /* This value identifies the type of buffer descriptor. */
2699 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2700 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2702 * This type of BD is 32B long and is used for inline L2 packet
2705 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2706 #define TX_BD_LONG_INLINE_TYPE_LAST \
2707 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2709 * All bits in this field may be set on the first BD of a packet.
2710 * Only the packet_end bit may be set in non-first BDs.
2712 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2713 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2715 * If set to 1, the packet ends with the data in the buffer
2716 * pointed to by this descriptor. This flag must be
2717 * valid on every BD.
2719 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2721 * If set to 1, the device will not generate a completion for
2722 * this transmit packet unless there is an error in its processing.
2723 * If this bit is set to 0, then the packet will be completed
2726 * This bit may be set only on the first BD of a packet.
2728 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2730 * This value indicates how many 16B BD locations are consumed
2731 * in the ring by this packet, including the BD and inline
2734 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2735 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2736 /* This field is deprecated. */
2737 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2738 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2740 * If set to 1, the device immediately updates the Send Consumer
2741 * Index after the buffer associated with this descriptor has
2742 * been transferred via DMA to NIC memory from host memory. An
2743 * interrupt may or may not be generated according to the state
2744 * of the interrupt avoidance mechanisms. If this bit
2745 * is set to 0, then the Consumer Index is only updated as soon
2746 * as one of the host interrupt coalescing conditions has been met.
2748 * This bit must be valid on the first BD of a packet.
2750 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2752 * This is the length of the inline data, not including BD length, in
2754 * The maximum value is 480.
2756 * This field must be valid on all BDs of a packet.
2760 * The opaque data field is passed through to the completion and can be
2761 * used for any data that the driver wants to associate with the transmit
2762 * BD. This field must be valid on the first BD of a packet. If
2763 * completion coalescing is enabled on the TX ring, it is suggested that
2764 * the driver populate the opaque field to indicate the specific TX ring
2765 * with which the completion is associated, then utilize the opaque and
2766 * sq_cons_idx fields in the coalesced completion record to determine
2767 * the specific packets that are to be completed on that ring.
2769 * This field must be valid on the first BD of a packet.
2774 * All bits in this field must be valid on the first BD of a packet.
2775 * Their value on other BDs of the packet is ignored.
2779 * If set to 1, the controller replaces the TCP/UPD checksum
2780 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2781 * checksum field of the encapsulated TCP/UDP packets with the
2782 * hardware calculated TCP/UDP checksum for the packet associated
2783 * with this descriptor. The flag is ignored if the LSO flag is set.
2785 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2787 * If set to 1, the controller replaces the IP checksum of the
2788 * normal packets, or the inner IP checksum of the encapsulated
2789 * packets with the hardware calculated IP checksum for the
2790 * packet associated with this descriptor.
2792 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2794 * If set to 1, the controller will not append an Ethernet CRC
2795 * to the end of the frame.
2797 * Packet must be 64B or longer when this flag is set. It is not
2798 * useful to use this bit with any form of TX offload such as
2799 * CSO or LSO. The intent is that the packet from the host already
2800 * has a valid Ethernet CRC on the packet.
2802 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2804 * If set to 1, the device will record the time at which the packet
2805 * was actually transmitted at the TX MAC for 2-step time sync. This
2806 * bit must be valid on the first BD of a packet.
2808 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2810 * If set to 1, the controller replaces the tunnel IP checksum
2811 * field with hardware calculated IP checksum for the IP header
2812 * of the packet associated with this descriptor. The hardware
2813 * updates an outer UDP checksum if it is non-zero.
2815 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2817 * This bit must be 0 for BDs of this type. LSO is not supported with
2820 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2821 /* Since LSO is not supported with inline BDs, this bit is not used. */
2822 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2823 /* Since LSO is not supported with inline BDs, this bit is not used. */
2824 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2826 * If set to '1', then the RoCE ICRC will be appended to the
2827 * packet. Packet must be a valid RoCE format packet.
2829 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2831 * If set to '1', then the FCoE CRC will be appended to the
2832 * packet. Packet must be a valid FCoE format packet.
2834 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2836 * If set to '1', then the timestamp from the BD is used. If cleared
2837 * to 0, then TWE provides the timestamp.
2839 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
2841 * If set to '1', this operation will cause a trace capture in each
2842 * block it passes through.
2844 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2846 * If set to '1', the device will record the time at which the packet
2847 * was actually transmitted at the TX MAC for 1-step time sync. This
2848 * bit must be valid on the first BD of a packet.
2850 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2852 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2853 * field with hardware calculated IP checksum for the IP header of the
2854 * packet associated with this descriptor. For outer UDP checksum, it
2855 * will be the following behavior for all cases independent of settings
2856 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2857 * is 0, then do not update it. If outer UDP checksum is non zero, then
2858 * the hardware should compute and update it.
2860 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2862 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2863 * header will not be modified during LSO operations. If set to one
2864 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2865 * incremented for each subsequent segment of an LSO operation. The
2866 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2869 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
2871 * If set to '1', When set to 1, KTLS encryption will be enabled for
2874 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2876 uint8_t kid_or_ts_low;
2877 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
2879 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2880 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
2883 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
2884 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
2885 uint32_t kid_or_ts_high;
2886 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
2887 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
2889 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2890 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2891 * of this field contain the upper 13 bits of the 20-bit KID.
2893 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2894 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
2896 * This value selects bits 25:16 of the CFA action to perform on the
2897 * packet. See the cfa_action field for more information.
2899 uint16_t cfa_action_high;
2900 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2901 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
2903 * This value selects a CFA action to perform on the packet.
2904 * Set this value to zero if no CFA action is desired.
2906 * This value must be valid on the first BD of a packet.
2908 uint16_t cfa_action;
2910 * This value is action meta-data that defines CFA edit operations
2911 * that are done in addition to any action editing.
2914 /* When key = 1, this is the VLAN tag VID value. */
2915 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2916 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2917 /* When key = 1, this is the VLAN tag DE value. */
2918 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2919 /* When key = 1, this is the VLAN tag PRI value. */
2920 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2921 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2922 /* When key = 1, this is the VLAN tag TPID select value. */
2923 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2924 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2926 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2927 (UINT32_C(0x0) << 16)
2929 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2930 (UINT32_C(0x1) << 16)
2932 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2933 (UINT32_C(0x2) << 16)
2935 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2936 (UINT32_C(0x3) << 16)
2938 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2939 (UINT32_C(0x4) << 16)
2940 /* Value programmed in CFA VLANTPID register. */
2941 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2942 (UINT32_C(0x5) << 16)
2943 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2944 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2945 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2947 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2949 * This field identifies the type of edit to be performed
2952 * This value must be valid on the first BD of a packet.
2954 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2955 UINT32_C(0xf0000000)
2956 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2958 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2959 (UINT32_C(0x0) << 28)
2961 * - meta[17:16] - TPID select value (0 = 0x8100).
2962 * - meta[15:12] - PRI/DE value.
2963 * - meta[11:0] - VID value.
2965 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2966 (UINT32_C(0x1) << 28)
2967 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2968 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2971 /* tx_bd_empty (size:128b/16B) */
2972 struct tx_bd_empty {
2973 /* This value identifies the type of buffer descriptor. */
2975 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2976 #define TX_BD_EMPTY_TYPE_SFT 0
2978 * Indicates that this BD is 1BB long and is an empty
2979 * TX BD. Not valid for use by the driver.
2981 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2982 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2983 uint8_t unused_1[3];
2985 uint8_t unused_3[3];
2986 uint8_t unused_4[8];
2989 /* tx_bd_mp_cmd (size:128b/16B) */
2990 struct tx_bd_mp_cmd {
2991 /* Unless otherwise stated, sub-fields of this field are always valid. */
2992 uint16_t flags_type;
2993 /* This value identifies the type of buffer descriptor. */
2994 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
2995 #define TX_BD_MP_CMD_TYPE_SFT 0
2997 * Indicates that this BD is used to issue a command to one of
2998 * the mid-path destinations.
3000 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3001 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3002 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3003 #define TX_BD_MP_CMD_FLAGS_SFT 6
3005 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3006 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3008 * This value indicates the number of 16B BD locations (slots)
3009 * consumed in the ring by this mid-path command BD, including the
3010 * BD header and the command field.
3012 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3013 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3015 * This value defines the length of command field in bytes. The maximum
3016 * value shall be 496.
3020 * The opaque data field is pass through to the completion and can be
3021 * used for any data that the driver wants to associate with this
3022 * Tx mid-path command.
3028 /* tx_bd_presync_cmd (size:128b/16B) */
3029 struct tx_bd_presync_cmd {
3030 /* Unless otherwise stated, sub-fields of this field are always valid. */
3031 uint16_t flags_type;
3032 /* This value identifies the type of buffer descriptor. */
3033 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3034 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3036 * Indicates that this BD is used to issue a cryptographic pre-
3037 * sync command through the fast path and destined for TCE.
3039 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3040 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3041 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3042 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3043 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3045 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3046 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3048 * This value indicates the number of 16B BD locations (slots)
3049 * consumed in the ring by this pre-sync command BD, including the
3050 * BD header and the command field.
3052 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3053 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3055 * This value defines the length of command field in bytes. The maximum
3056 * value shall be 496.
3060 * The opaque data field is pass through to TCE and can be used for
3065 * This field is the Crypto Context ID to which the retransmit packet is
3066 * applied. The KID references the context fields used by the
3067 * associated kTLS offloaded connection.
3071 * The KID value of all-ones is reserved for non-KTLS packets, which
3072 * only implies that this value must not be used when filling this
3073 * field for crypto packets.
3075 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3076 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3080 /* rx_prod_pkt_bd (size:128b/16B) */
3081 struct rx_prod_pkt_bd {
3082 /* This value identifies the type of buffer descriptor. */
3083 uint16_t flags_type;
3084 /* This value identifies the type of buffer descriptor. */
3085 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3086 #define RX_PROD_PKT_BD_TYPE_SFT 0
3088 * Indicates that this BD is 16B long and is an RX Producer
3089 * (i.e. empty) buffer descriptor.
3091 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3092 #define RX_PROD_PKT_BD_TYPE_LAST \
3093 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3094 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3095 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3097 * If set to 1, the packet will be placed at the address plus
3098 * 2B. The 2 Bytes of padding will be written as zero.
3100 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3102 * If set to 1, the packet write will be padded out to the
3103 * nearest cache-line with zero value padding.
3105 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3107 * This field has been deprecated. There can be no additional
3108 * BDs for this packet from this ring.
3111 * This value is the number of additional buffers in the ring that
3112 * describe the buffer space to be consumed for this packet.
3113 * If the value is zero, then the packet must fit within the
3114 * space described by this BD. If this value is 1 or more, it
3115 * indicates how many additional "buffer" BDs are in the ring
3116 * immediately following this BD to be used for the same
3117 * network packet. Even if the packet to be placed does not need
3118 * all the additional buffers, they will be consumed anyway.
3120 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3121 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3123 * This is the length in Bytes of the host physical buffer where
3124 * data for the packet may be placed in host memory.
3128 * The opaque data field is pass through to the completion and can be
3129 * used for any data that the driver wants to associate with this
3130 * receive buffer set.
3134 * This is the host physical address where data for the packet may
3135 * be placed in host memory.
3140 /* rx_prod_bfr_bd (size:128b/16B) */
3141 struct rx_prod_bfr_bd {
3142 /* This value identifies the type of buffer descriptor. */
3143 uint16_t flags_type;
3144 /* This value identifies the type of buffer descriptor. */
3145 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3146 #define RX_PROD_BFR_BD_TYPE_SFT 0
3148 * Indicates that this BD is 16B long and is an RX
3149 * Producer Buffer BD.
3151 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3152 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3153 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3154 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3156 * This is the length in Bytes of the host physical buffer where
3157 * data for the packet may be placed in host memory.
3160 /* This field is not used. */
3163 * This is the host physical address where data for the packet may
3164 * be placed in host memory.
3169 /* rx_prod_agg_bd (size:128b/16B) */
3170 struct rx_prod_agg_bd {
3171 /* This value identifies the type of buffer descriptor. */
3172 uint16_t flags_type;
3173 /* This value identifies the type of buffer descriptor. */
3174 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3175 #define RX_PROD_AGG_BD_TYPE_SFT 0
3177 * Indicates that this BD is 16B long and is an
3178 * RX Producer Assembly Buffer Descriptor.
3180 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3181 #define RX_PROD_AGG_BD_TYPE_LAST \
3182 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3183 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3184 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3186 * If set to 1, the packet write will be padded out to the
3187 * nearest cache-line with zero value padding.
3189 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3191 * This is the length in Bytes of the host physical buffer where
3192 * data for the packet may be placed in host memory.
3196 * The opaque data field is pass through to the completion and can be
3197 * used for any data that the driver wants to associate with this
3198 * receive assembly buffer.
3202 * This is the host physical address where data for the packet may
3203 * be placed in host memory.
3208 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3209 struct cfa_cmpls_cmp_data_msg {
3210 uint32_t mp_client_dma_length_opcode_status_type;
3212 * This field represents the Mid-Path client that generated the
3215 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3216 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3217 /* Mid Path Short Completion with length = 16B. */
3218 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3220 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3221 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3222 /* This value indicates the status for the command. */
3223 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3224 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3225 /* Completed without error. */
3226 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3227 (UINT32_C(0x0) << 6)
3228 /* Indicates an unsupported CFA opcode in the command. */
3229 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3230 (UINT32_C(0x1) << 6)
3232 * Indicates a CFA command formatting error. This error can occur on
3233 * any of the supported CFA commands.
3235 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3236 (UINT32_C(0x2) << 6)
3238 * Indicates an SVIF-Table scope error. This error can occur on any
3239 * of the supported CFA commands.
3241 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3242 (UINT32_C(0x3) << 6)
3244 * Indicates that the table_index is either outside of the
3245 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3246 * the static bucket range. This error can occur on EM Insert
3247 * commands. It can also occur on Read, Read Clear, Write, and
3248 * Invalidate commands if the table_type is EM.
3250 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3251 (UINT32_C(0x4) << 6)
3253 * Cache operation responded with an error. This error can occur on
3254 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3256 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3257 (UINT32_C(0x5) << 6)
3259 * Indicates failure on EM Insert or EM Delete Command. Hash index
3260 * and hash msb are returned in table_index and hash_msb fields.
3261 * Dma_length is set to 1 if the bucket is also returned (as dma
3264 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3265 (UINT32_C(0x6) << 6)
3267 * Indicates no notifications were available on an Event Collection
3270 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3271 (UINT32_C(0x7) << 6)
3272 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3273 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3274 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3275 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3276 /* This is the opcode from the command. */
3277 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3279 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3281 * This is read command. From 32 to 128B can be read from a table
3282 * using this command.
3284 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3285 (UINT32_C(0x0) << 12)
3287 * This is write command. From 32 to 128B can be written to a table
3288 * using this command.
3290 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3291 (UINT32_C(0x1) << 12)
3293 * This is read-clear command. 32B can be read from a table and a 16b
3294 * mask can be used to clear specific 16b units after the read as an
3297 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3298 (UINT32_C(0x2) << 12)
3300 * An exact match table insert will be attempted into the table. If
3301 * there is a free location in the bucket, the payload will be
3302 * written to the bucket.
3304 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3305 (UINT32_C(0x3) << 12)
3306 /* An exact match table delete will be attempted. */
3307 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3308 (UINT32_C(0x4) << 12)
3310 * The specified table area will be invalidated. If it is needed
3311 * again, it will be read from the backing store.
3313 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3314 (UINT32_C(0x5) << 12)
3315 /* Reads notification messages from the Host Notification Queue. */
3316 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3317 (UINT32_C(0x6) << 12)
3318 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3319 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3321 * This field indicates the length of the DMA that accompanies the
3322 * completion. Specified in units of DWords (32b). Valid values are
3323 * between 0 and 128. A value of zero indicates that there is no DMA
3324 * that accompanies the completion.
3326 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3328 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3330 * This field represents the Mid-Path client that generated the
3333 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3334 UINT32_C(0xf0000000)
3335 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3336 /* TX configrable flow processing block. */
3337 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3338 (UINT32_C(0x2) << 28)
3339 /* RX configrable flow processing block. */
3340 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3341 (UINT32_C(0x3) << 28)
3342 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3343 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3345 * This is a copy of the opaque field from the mid path BD of this
3349 uint16_t hash_msb_v;
3351 * This value is written by the NIC such that it will be different for
3352 * each pass through the completion queue. The even passes will
3353 * write 1. The odd passes will write 0.
3355 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3356 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3357 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3359 * This is the upper 12b of the hash, returned on Exact Match
3360 * Insertion/Deletion Commands.
3362 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3363 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3364 /* This is the table type from the command. */
3366 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3367 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3368 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3369 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3370 /* This command acts on the action table of the specified scope. */
3371 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3372 /* This command acts on the exact match table of the specified scope. */
3373 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3374 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3375 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3376 uint8_t table_scope;
3377 /* This is the table scope from the command. */
3378 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3379 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3380 uint32_t table_index;
3382 * This is the table index from the command (if it exists). However, if
3383 * an Exact Match Insertion/Deletion command failed, then this is the
3384 * table index of the calculated static hash bucket.
3386 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3387 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3390 /* CFA Mid-Path 32B DMA Message */
3391 /* cfa_dma32b_data_msg (size:256b/32B) */
3392 struct cfa_dma32b_data_msg {
3393 /* DMA data value. */
3397 /* CFA Mid-Path 64B DMA Message */
3398 /* cfa_dma64b_data_msg (size:512b/64B) */
3399 struct cfa_dma64b_data_msg {
3400 /* DMA data value. */
3404 /* CFA Mid-Path 96B DMA Message */
3405 /* cfa_dma96b_data_msg (size:768b/96B) */
3406 struct cfa_dma96b_data_msg {
3407 /* DMA data value. */
3411 /* CFA Mid-Path 128B DMA Message */
3412 /* cfa_dma128b_data_msg (size:1024b/128B) */
3413 struct cfa_dma128b_data_msg {
3414 /* DMA data value. */
3418 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3419 struct ce_cmpls_cmp_data_msg {
3420 uint16_t status_subtype_type;
3422 * This field indicates the exact type of the completion. By
3423 * convention, the LSB identifies the length of the record in 16B
3424 * units. Even values indicate 16B records. Odd values indicate 32B
3427 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3428 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3429 /* Completion of a Mid Path Command. Length = 16B */
3430 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3431 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3432 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3434 * This value indicates the CE sub-type operation that is being
3437 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3438 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3439 /* Completion Response for a Solicited Command. */
3440 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3441 /* Error Completion (Unsolicited). */
3442 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3443 /* Re-Sync Completion (Unsolicited) */
3444 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3445 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3446 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3447 /* This value indicates the status for the command. */
3448 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3449 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3450 /* Completed without error. */
3451 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3452 (UINT32_C(0x0) << 10)
3453 /* CFCK load error. */
3454 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3455 (UINT32_C(0x1) << 10)
3456 /* FID check error. */
3457 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3458 (UINT32_C(0x2) << 10)
3459 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3460 CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
3463 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3464 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3466 * This field represents the Mid-Path client that generated the
3469 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3470 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3471 /* TX crypto engine block. */
3472 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3473 /* RX crypto engine block. */
3474 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3475 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3476 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3478 * This is a copy of the opaque field from the mid path BD of this
3485 * This value is written by the NIC such that it will be different
3486 * for each pass through the completion queue. The even passes will
3487 * write 1. The odd passes will write 0.
3489 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3491 * This field is the Crypto Context ID. The KID is used to store
3492 * information used by the associated kTLS offloaded connection.
3494 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3495 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3499 /* cmpl_base (size:128b/16B) */
3503 * This field indicates the exact type of the completion.
3504 * By convention, the LSB identifies the length of the
3505 * record in 16B units. Even values indicate 16B
3506 * records. Odd values indicate 32B
3509 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3510 #define CMPL_BASE_TYPE_SFT 0
3513 * Completion of TX packet. Length = 16B
3515 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3518 * Completion of NO-OP. Length = 16B
3520 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3522 * TX L2 coalesced completion:
3523 * Completion of coalesced TX packet. Length = 16B
3525 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3527 * TX L2 PTP completion:
3528 * Completion of PTP TX packet. Length = 32B
3530 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3532 * RX L2 TPA Start V2 Completion:
3533 * Completion of and L2 RX packet. Length = 32B
3534 * This is the new version of the RX_TPA_START completion used
3535 * in SR2 and later chips.
3537 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3539 * RX L2 V2 completion:
3540 * Completion of and L2 RX packet. Length = 32B
3541 * This is the new version of the RX_L2 completion used in SR2
3544 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3547 * Completion of and L2 RX packet. Length = 32B
3549 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3551 * RX Aggregation Buffer completion :
3552 * Completion of an L2 aggregation buffer in support of
3553 * TPA, HDS, or Jumbo packet completion. Length = 16B
3555 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3557 * RX L2 TPA Start Completion:
3558 * Completion at the beginning of a TPA operation.
3561 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3563 * RX L2 TPA End Completion:
3564 * Completion at the end of a TPA operation.
3567 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3569 * Statistics Ejection Completion:
3570 * Completion of statistics data ejection buffer.
3573 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3575 * VEE Flush Completion:
3576 * This completion is inserted manually by
3577 * the Primate and processed by the VEE hardware to ensure that
3578 * all completions on a VEE function have been processed by the
3579 * VEE hardware before FLR process is completed.
3581 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3583 * Mid Path Short Completion :
3584 * Completion of a Mid Path Command. Length = 16B
3586 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3588 * Mid Path Long Completion :
3589 * Completion of a Mid Path Command. Length = 32B
3591 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3593 * HWRM Command Completion:
3594 * Completion of an HWRM command.
3596 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3597 /* Forwarded HWRM Request */
3598 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3599 /* Forwarded HWRM Response */
3600 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3601 /* HWRM Asynchronous Event Information */
3602 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3603 /* CQ Notification */
3604 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3605 /* SRQ Threshold Event */
3606 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3607 /* DBQ Threshold Event */
3608 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3609 /* QP Async Notification */
3610 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3611 /* Function Async Notification */
3612 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3613 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3619 * This value is written by the NIC such that it will be different
3620 * for each pass through the completion queue. The even passes
3621 * will write 1. The odd passes will write 0.
3624 #define CMPL_BASE_V UINT32_C(0x1)
3625 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3626 #define CMPL_BASE_INFO3_SFT 1
3631 /* tx_cmpl (size:128b/16B) */
3633 uint16_t flags_type;
3635 * This field indicates the exact type of the completion.
3636 * By convention, the LSB identifies the length of the
3637 * record in 16B units. Even values indicate 16B
3638 * records. Odd values indicate 32B
3641 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3642 #define TX_CMPL_TYPE_SFT 0
3645 * Completion of TX packet. Length = 16B
3647 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3648 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3649 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3650 #define TX_CMPL_FLAGS_SFT 6
3652 * When this bit is '1', it indicates a packet that has an
3653 * error of some type. Type of error is indicated in
3656 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3658 * When this bit is '1', it indicates that the packet completed
3659 * was transmitted using the push acceleration data provided
3660 * by the driver. When this bit is '0', it indicates that the
3661 * packet had not push acceleration data written or was executed
3662 * as a normal packet even though push data was provided.
3664 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3665 /* unused1 is 16 b */
3668 * This is a copy of the opaque field from the first TX BD of this
3669 * transmitted packet. Note that, if the packet was described by a short
3670 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3671 * short CSO BD will appear in the bottom 16 bits of this field.
3676 * This value is written by the NIC such that it will be different
3677 * for each pass through the completion queue. The even passes
3678 * will write 1. The odd passes will write 0.
3680 #define TX_CMPL_V UINT32_C(0x1)
3681 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3682 #define TX_CMPL_ERRORS_SFT 1
3684 * This error indicates that there was some sort of problem
3685 * with the BDs for the packet.
3687 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3688 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3690 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3691 (UINT32_C(0x0) << 1)
3694 * BDs were not formatted correctly.
3696 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3697 (UINT32_C(0x2) << 1)
3698 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3699 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3701 * When this bit is '1', it indicates that the length of
3702 * the packet was zero. No packet was transmitted.
3704 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3706 * When this bit is '1', it indicates that the packet
3707 * was longer than the programmed limit in TDI. No
3708 * packet was transmitted.
3710 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3712 * When this bit is '1', it indicates that one or more of the
3713 * BDs associated with this packet generated a PCI error.
3714 * This probably means the address was not valid.
3716 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
3718 * When this bit is '1', it indicates that the packet was longer
3719 * than indicated by the hint. No packet was transmitted.
3721 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3723 * When this bit is '1', it indicates that the packet was
3724 * dropped due to Poison TLP error on one or more of the
3725 * TLPs in the PXP completion.
3727 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3729 * When this bit is '1', it indicates that the packet was dropped
3730 * due to a transient internal error in TDC. The packet or LSO can
3731 * be retried and may transmit successfully on a subsequent attempt.
3733 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3735 * When this bit is '1', it was not possible to collect a a timestamp
3736 * for a PTP completion, in which case the timestamp_hi and
3737 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3738 * completion, the timestamp_hi and timestamp_lo fields are valid.
3739 * RJRN will copy the value of this bit into the field of the same
3740 * name in all TX completions, regardless of whether such completions
3741 * are PTP completions or other TX completions.
3743 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
3744 /* unused2 is 16 b */
3746 /* unused3 is 32 b */
3750 /* tx_cmpl_coal (size:128b/16B) */
3751 struct tx_cmpl_coal {
3752 uint16_t flags_type;
3754 * This field indicates the exact type of the completion.
3755 * By convention, the LSB identifies the length of the
3756 * record in 16B units. Even values indicate 16B
3757 * records. Odd values indicate 32B
3760 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
3761 #define TX_CMPL_COAL_TYPE_SFT 0
3763 * TX L2 coalesced completion:
3764 * Completion of TX packet. Length = 16B
3766 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
3767 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
3768 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
3769 #define TX_CMPL_COAL_FLAGS_SFT 6
3771 * When this bit is '1', it indicates a packet that has an
3772 * error of some type. Type of error is indicated in
3775 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
3777 * When this bit is '1', it indicates that the packet completed
3778 * was transmitted using the push acceleration data provided
3779 * by the driver. When this bit is '0', it indicates that the
3780 * packet had not push acceleration data written or was executed
3781 * as a normal packet even though push data was provided.
3783 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
3784 /* unused1 is 16 b */
3787 * This is a copy of the opaque field from the first TX BD of the packet
3788 * which corresponds with the reported sq_cons_idx. Note that, with
3789 * coalesced completions, completions are generated for only some of the
3790 * packets. The driver will see the opaque field for only those packets.
3791 * Note that, if the packet was described by a short CSO or short CSO
3792 * inline BD, then the 16-bit opaque field from the short CSO BD will
3793 * appear in the bottom 16 bits of this field. For TX rings with
3794 * completion coalescing enabled (which would use the coalesced
3795 * completion record), it is suggested that the driver populate the
3796 * opaque field to indicate the specific TX ring with which the
3797 * completion is associated, then utilize the opaque and sq_cons_idx
3798 * fields in the coalesced completion record to determine the specific
3799 * packets that are to be completed on that ring.
3804 * This value is written by the NIC such that it will be different
3805 * for each pass through the completion queue. The even passes
3806 * will write 1. The odd passes will write 0.
3808 #define TX_CMPL_COAL_V UINT32_C(0x1)
3809 #define TX_CMPL_COAL_ERRORS_MASK \
3811 #define TX_CMPL_COAL_ERRORS_SFT 1
3813 * This error indicates that there was some sort of problem
3814 * with the BDs for the packet.
3816 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3817 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
3819 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
3820 (UINT32_C(0x0) << 1)
3823 * BDs were not formatted correctly.
3825 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
3826 (UINT32_C(0x2) << 1)
3827 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
3828 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
3830 * When this bit is '1', it indicates that the length of
3831 * the packet was zero. No packet was transmitted.
3833 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3835 * When this bit is '1', it indicates that the packet
3836 * was longer than the programmed limit in TDI. No
3837 * packet was transmitted.
3839 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3841 * When this bit is '1', it indicates that one or more of the
3842 * BDs associated with this packet generated a PCI error.
3843 * This probably means the address was not valid.
3845 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
3847 * When this bit is '1', it indicates that the packet was longer
3848 * than indicated by the hint. No packet was transmitted.
3850 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3852 * When this bit is '1', it indicates that the packet was
3853 * dropped due to Poison TLP error on one or more of the
3854 * TLPs in the PXP completion.
3856 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
3859 * When this bit is '1', it indicates that the packet was dropped
3860 * due to a transient internal error in TDC. The packet or LSO can
3861 * be retried and may transmit successfully on a subsequent attempt.
3863 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
3866 * When this bit is '1', it was not possible to collect a a timestamp
3867 * for a PTP completion, in which case the timestamp_hi and
3868 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3869 * completion, the timestamp_hi and timestamp_lo fields are valid.
3870 * RJRN will copy the value of this bit into the field of the same
3871 * name in all TX completions, regardless of whether such
3872 * completions are PTP completions or other TX completions.
3874 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
3876 /* unused2 is 16 b */
3878 uint32_t sq_cons_idx;
3880 * This value is SQ index for the start of the packet following the
3881 * last completed packet.
3883 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
3884 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
3887 /* tx_cmpl_ptp (size:128b/16B) */
3888 struct tx_cmpl_ptp {
3889 uint16_t flags_type;
3891 * This field indicates the exact type of the completion.
3892 * By convention, the LSB identifies the length of the
3893 * record in 16B units. Even values indicate 16B
3894 * records. Odd values indicate 32B
3897 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
3898 #define TX_CMPL_PTP_TYPE_SFT 0
3900 * TX L2 PTP completion:
3901 * Completion of TX packet. Length = 32B
3903 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
3904 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
3905 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
3906 #define TX_CMPL_PTP_FLAGS_SFT 6
3908 * When this bit is '1', it indicates a packet that has an
3909 * error of some type. Type of error is indicated in
3912 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
3914 * When this bit is '1', it indicates that the packet completed
3915 * was transmitted using the push acceleration data provided
3916 * by the driver. When this bit is '0', it indicates that the
3917 * packet had not push acceleration data written or was executed
3918 * as a normal packet even though push data was provided.
3920 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
3921 /* unused1 is 16 b */
3924 * This is a copy of the opaque field from the first TX BD of this
3925 * transmitted packet. Note that, if the packet was described by a short
3926 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3927 * short CSO BD will appear in the bottom 16 bits of this field.
3932 * This value is written by the NIC such that it will be different
3933 * for each pass through the completion queue. The even passes
3934 * will write 1. The odd passes will write 0.
3936 #define TX_CMPL_PTP_V UINT32_C(0x1)
3937 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
3938 #define TX_CMPL_PTP_ERRORS_SFT 1
3940 * This error indicates that there was some sort of problem
3941 * with the BDs for the packet.
3943 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3944 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
3946 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
3947 (UINT32_C(0x0) << 1)
3950 * BDs were not formatted correctly.
3952 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
3953 (UINT32_C(0x2) << 1)
3954 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
3955 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
3957 * When this bit is '1', it indicates that the length of
3958 * the packet was zero. No packet was transmitted.
3960 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3962 * When this bit is '1', it indicates that the packet
3963 * was longer than the programmed limit in TDI. No
3964 * packet was transmitted.
3966 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3968 * When this bit is '1', it indicates that one or more of the
3969 * BDs associated with this packet generated a PCI error.
3970 * This probably means the address was not valid.
3972 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
3974 * When this bit is '1', it indicates that the packet was longer
3975 * than indicated by the hint. No packet was transmitted.
3977 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3979 * When this bit is '1', it indicates that the packet was
3980 * dropped due to Poison TLP error on one or more of the
3981 * TLPs in the PXP completion.
3983 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3985 * When this bit is '1', it indicates that the packet was dropped due
3986 * to a transient internal error in TDC. The packet or LSO can be
3987 * retried and may transmit successfully on a subsequent attempt.
3989 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3991 * When this bit is '1', it was not possible to collect a a timestamp
3992 * for a PTP completion, in which case the timestamp_hi and
3993 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3994 * completion, the timestamp_hi and timestamp_lo fields are valid.
3995 * RJRN will copy the value of this bit into the field of the same
3996 * name in all TX completions, regardless of whether such
3997 * completions are PTP completions or other TX completions.
3999 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4000 /* unused2 is 16 b */
4003 * This is timestamp value (lower 32bits) read from PM for the PTP
4004 * timestamp enabled packet.
4006 uint32_t timestamp_lo;
4009 /* tx_cmpl_ptp_hi (size:128b/16B) */
4010 struct tx_cmpl_ptp_hi {
4012 * This is timestamp value (lower 32bits) read from PM for the PTP
4013 * timestamp enabled packet.
4015 uint16_t timestamp_hi[3];
4016 uint16_t reserved16;
4019 * This value is written by the NIC such that it will be different for
4020 * each pass through the completion queue.The even passes will write 1.
4021 * The odd passes will write 0
4023 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4026 /* rx_pkt_cmpl (size:128b/16B) */
4027 struct rx_pkt_cmpl {
4028 uint16_t flags_type;
4030 * This field indicates the exact type of the completion.
4031 * By convention, the LSB identifies the length of the
4032 * record in 16B units. Even values indicate 16B
4033 * records. Odd values indicate 32B
4036 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4037 #define RX_PKT_CMPL_TYPE_SFT 0
4040 * Completion of and L2 RX packet. Length = 32B
4042 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4043 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
4044 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4045 #define RX_PKT_CMPL_FLAGS_SFT 6
4047 * When this bit is '1', it indicates a packet that has an
4048 * error of some type. Type of error is indicated in
4051 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4052 /* This field indicates how the packet was placed in the buffer. */
4053 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4054 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4057 * Packet was placed using normal algorithm.
4059 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
4062 * Packet was placed using jumbo algorithm.
4064 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
4066 * Header/Data Separation:
4067 * Packet was placed using Header/Data separation algorithm.
4068 * The separation location is indicated by the itype field.
4070 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
4071 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4072 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4073 /* This bit is '1' if the RSS field in this completion is valid. */
4074 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4076 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4078 * This value indicates what the inner packet determined for the
4081 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4082 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4085 * Indicates that the packet type was not known.
4087 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4088 (UINT32_C(0x0) << 12)
4091 * Indicates that the packet was an IP packet, but further
4092 * classification was not possible.
4094 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4095 (UINT32_C(0x1) << 12)
4098 * Indicates that the packet was IP and TCP.
4099 * This indicates that the payload_offset field is valid.
4101 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4102 (UINT32_C(0x2) << 12)
4105 * Indicates that the packet was IP and UDP.
4106 * This indicates that the payload_offset field is valid.
4108 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4109 (UINT32_C(0x3) << 12)
4112 * Indicates that the packet was recognized as a FCoE.
4113 * This also indicates that the payload_offset field is valid.
4115 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4116 (UINT32_C(0x4) << 12)
4119 * Indicates that the packet was recognized as a RoCE.
4120 * This also indicates that the payload_offset field is valid.
4122 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4123 (UINT32_C(0x5) << 12)
4126 * Indicates that the packet was recognized as ICMP.
4127 * This indicates that the payload_offset field is valid.
4129 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4130 (UINT32_C(0x7) << 12)
4132 * PtP packet wo/timestamp:
4133 * Indicates that the packet was recognized as a PtP
4136 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4137 (UINT32_C(0x8) << 12)
4139 * PtP packet w/timestamp:
4140 * Indicates that the packet was recognized as a PtP
4141 * packet and that a timestamp was taken for the packet.
4143 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4144 (UINT32_C(0x9) << 12)
4145 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4146 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4148 * This is the length of the data for the packet stored in the
4149 * buffer(s) identified by the opaque value. This includes
4150 * the packet BD and any associated buffer BDs. This does not include
4151 * the length of any data places in aggregation BDs.
4155 * This is a copy of the opaque field from the RX BD this completion
4159 uint8_t agg_bufs_v1;
4161 * This value is written by the NIC such that it will be different
4162 * for each pass through the completion queue. The even passes
4163 * will write 1. The odd passes will write 0.
4165 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4167 * This value is the number of aggregation buffers that follow this
4168 * entry in the completion ring that are a part of this packet.
4169 * If the value is zero, then the packet is completely contained
4170 * in the buffer space provided for the packet in the RX ring.
4172 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4173 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4174 /* unused1 is 2 b */
4175 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4176 #define RX_PKT_CMPL_UNUSED1_SFT 6
4178 * This is the RSS hash type for the packet. The value is packed
4179 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4181 * The value of tuple_extrac_op provides the information about
4182 * what fields the hash was computed on.
4183 * * 0: The RSS hash was computed over source IP address,
4184 * destination IP address, source port, and destination port of inner
4185 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4186 * the packet headers are considered inner packet headers for the RSS
4187 * hash computation purpose.
4188 * * 1: The RSS hash was computed over source IP address and destination
4189 * IP address of inner IP header. Note: For non-tunneled packets,
4190 * the packet headers are considered inner packet headers for the RSS
4191 * hash computation purpose.
4192 * * 2: The RSS hash was computed over source IP address,
4193 * destination IP address, source port, and destination port of
4194 * IP and TCP or UDP headers of outer tunnel headers.
4195 * Note: For non-tunneled packets, this value is not applicable.
4196 * * 3: The RSS hash was computed over source IP address and
4197 * destination IP address of IP header of outer tunnel headers.
4198 * Note: For non-tunneled packets, this value is not applicable.
4200 * Note that 4-tuples values listed above are applicable
4201 * for layer 4 protocols supported and enabled for RSS in the hardware,
4202 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4203 * enabled for TCP traffic only, then the values of tuple_extract_op
4204 * corresponding to 4-tuples are only valid for TCP traffic.
4206 uint8_t rss_hash_type;
4208 * This value indicates the offset in bytes from the beginning of the packet
4209 * where the inner payload starts. This value is valid for TCP, UDP,
4210 * FCoE, and RoCE packets.
4212 * A value of zero indicates that header is 256B into the packet.
4214 uint8_t payload_offset;
4215 /* unused2 is 8 b */
4218 * This value is the RSS hash value calculated for the packet
4219 * based on the mode bits and key value in the VNIC.
4224 /* Last 16 bytes of rx_pkt_cmpl. */
4225 /* rx_pkt_cmpl_hi (size:128b/16B) */
4226 struct rx_pkt_cmpl_hi {
4229 * This indicates that the ip checksum was calculated for the
4230 * inner packet and that the ip_cs_error field indicates if there
4233 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4235 * This indicates that the TCP, UDP or ICMP checksum was
4236 * calculated for the inner packet and that the l4_cs_error field
4237 * indicates if there was an error.
4239 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4241 * This indicates that the ip checksum was calculated for the
4242 * tunnel header and that the t_ip_cs_error field indicates if there
4245 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4247 * This indicates that the UDP checksum was
4248 * calculated for the tunnel packet and that the t_l4_cs_error field
4249 * indicates if there was an error.
4251 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4252 /* This value indicates what format the metadata field is. */
4253 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4254 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4255 /* No metadata information. Value is zero. */
4256 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4257 (UINT32_C(0x0) << 4)
4259 * The metadata field contains the VLAN tag and TPID value.
4260 * - metadata[11:0] contains the vlan VID value.
4261 * - metadata[12] contains the vlan DE value.
4262 * - metadata[15:13] contains the vlan PRI value.
4263 * - metadata[31:16] contains the vlan TPID value.
4265 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4266 (UINT32_C(0x1) << 4)
4268 * If ext_meta_format is equal to 1, the metadata field
4269 * contains the lower 16b of the tunnel ID value, justified
4271 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4272 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4273 * - NVGRE = TNI[23:0] -> Tenant Network ID
4274 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4275 * - IPV4 = 0 (not populated)
4276 * - IPV6 = Flow Label[19:0]
4277 * - PPPoE = sessionID[15:0]
4278 * - MPLs = Outer label[19:0]
4279 * - UPAR = Selected[31:0] with bit mask
4281 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4282 (UINT32_C(0x2) << 4)
4284 * if ext_meta_format is equal to 1, metadata field contains
4285 * 16b metadata from the prepended header (chdr_data).
4287 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4288 (UINT32_C(0x3) << 4)
4290 * If ext_meta_format is equal to 1, the metadata field contains
4291 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4293 * - metadata[8:0] contains the outer_l3_offset.
4294 * - metadata[17:9] contains the inner_l2_offset.
4295 * - metadata[26:18] contains the inner_l3_offset.
4296 * - metadata[31:27] contains the inner_l4_size.
4298 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4299 (UINT32_C(0x4) << 4)
4300 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4301 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4303 * This field indicates the IP type for the inner-most IP header.
4304 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4305 * This value is only valid if itype indicates a packet
4306 * with an IP header.
4308 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4310 * This indicates that the complete 1's complement checksum was
4311 * calculated for the packet.
4313 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4315 * The combination of this value and meta_format indicated what
4316 * format the metadata field is.
4318 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4319 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4321 * This value is the complete 1's complement checksum calculated from
4322 * the start of the outer L3 header to the end of the packet (not
4323 * including the ethernet crc). It is valid when the
4324 * 'complete_checksum_calc' flag is set.
4326 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4327 UINT32_C(0xffff0000)
4328 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4330 * This is data from the CFA block as indicated by the meta_format
4334 /* When meta_format=1, this value is the VLAN VID. */
4335 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4336 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4337 /* When meta_format=1, this value is the VLAN DE. */
4338 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4339 /* When meta_format=1, this value is the VLAN PRI. */
4340 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4341 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4342 /* When meta_format=1, this value is the VLAN TPID. */
4343 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4344 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4347 * This value is written by the NIC such that it will be different
4348 * for each pass through the completion queue. The even passes
4349 * will write 1. The odd passes will write 0.
4351 #define RX_PKT_CMPL_V2 \
4353 #define RX_PKT_CMPL_ERRORS_MASK \
4355 #define RX_PKT_CMPL_ERRORS_SFT 1
4357 * This error indicates that there was some sort of problem with
4358 * the BDs for the packet that was found after part of the
4359 * packet was already placed. The packet should be treated as
4362 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4364 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4365 /* No buffer error */
4366 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4367 (UINT32_C(0x0) << 1)
4370 * Packet did not fit into packet buffer provided.
4371 * For regular placement, this means the packet did not fit
4372 * in the buffer provided. For HDS and jumbo placement, this
4373 * means that the packet could not be placed into 7 physical
4376 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4377 (UINT32_C(0x1) << 1)
4380 * All BDs needed for the packet were not on-chip when
4381 * the packet arrived.
4383 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4384 (UINT32_C(0x2) << 1)
4387 * BDs were not formatted correctly.
4389 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4390 (UINT32_C(0x3) << 1)
4393 * There was a bad_format error on the previous operation
4395 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4396 (UINT32_C(0x5) << 1)
4397 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4398 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4400 * This indicates that there was an error in the IP header
4403 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4406 * This indicates that there was an error in the TCP, UDP
4409 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4412 * This indicates that there was an error in the tunnel
4413 * IP header checksum.
4415 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4418 * This indicates that there was an error in the tunnel
4421 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4424 * This indicates that there was a CRC error on either an FCoE
4425 * or RoCE packet. The itype indicates the packet type.
4427 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4430 * This indicates that there was an error in the tunnel
4431 * portion of the packet when this
4432 * field is non-zero.
4434 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4436 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4438 * No additional error occurred on the tunnel portion
4439 * or the packet of the packet does not have a tunnel.
4441 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4442 (UINT32_C(0x0) << 9)
4444 * Indicates that IP header version does not match
4445 * expectation from L2 Ethertype for IPv4 and IPv6
4446 * in the tunnel header.
4448 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4449 (UINT32_C(0x1) << 9)
4451 * Indicates that header length is out of range in the
4452 * tunnel header. Valid for
4455 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4456 (UINT32_C(0x2) << 9)
4458 * Indicates that the physical packet is shorter than that
4459 * claimed by the PPPoE header length for a tunnel PPPoE
4462 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4463 (UINT32_C(0x3) << 9)
4465 * Indicates that physical packet is shorter than that claimed
4466 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4467 * tunnel packet packets.
4469 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4470 (UINT32_C(0x4) << 9)
4472 * Indicates that the physical packet is shorter than that
4473 * claimed by the tunnel UDP header length for a tunnel
4474 * UDP packet that is not fragmented.
4476 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4477 (UINT32_C(0x5) << 9)
4479 * indicates that the IPv4 TTL or IPv6 hop limit check
4480 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4481 * for IPv4, and IPv6.
4483 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4484 (UINT32_C(0x6) << 9)
4485 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4486 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4488 * This indicates that there was an error in the inner
4489 * portion of the packet when this
4490 * field is non-zero.
4492 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4494 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4496 * No additional error occurred on the tunnel portion
4497 * or the packet of the packet does not have a tunnel.
4499 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4500 (UINT32_C(0x0) << 12)
4502 * Indicates that IP header version does not match
4503 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4504 * option other than VFT was parsed on
4507 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4508 (UINT32_C(0x1) << 12)
4510 * indicates that header length is out of range. Valid for
4513 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4514 (UINT32_C(0x2) << 12)
4516 * indicates that the IPv4 TTL or IPv6 hop limit check
4517 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4519 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4520 (UINT32_C(0x3) << 12)
4522 * Indicates that physical packet is shorter than that
4523 * claimed by the l3 header length. Valid for IPv4,
4524 * IPv6 packet or RoCE packets.
4526 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4527 (UINT32_C(0x4) << 12)
4529 * Indicates that the physical packet is shorter than that
4530 * claimed by the UDP header length for a UDP packet that is
4533 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4534 (UINT32_C(0x5) << 12)
4536 * Indicates that TCP header length > IP payload. Valid for
4539 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4540 (UINT32_C(0x6) << 12)
4541 /* Indicates that TCP header length < 5. Valid for TCP. */
4542 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4543 (UINT32_C(0x7) << 12)
4545 * Indicates that TCP option headers result in a TCP header
4546 * size that does not match data offset in TCP header. Valid
4549 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4550 (UINT32_C(0x8) << 12)
4551 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4552 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4554 * This field identifies the CFA action rule that was used for this
4560 * This value holds the reordering sequence number for the packet.
4561 * If the reordering sequence is not valid, then this value is zero.
4562 * The reordering domain for the packet is in the bottom 8 to 10b of
4563 * the rss_hash value. The bottom 20b of this value contain the
4564 * ordering domain value for the packet.
4566 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4567 #define RX_PKT_CMPL_REORDER_SFT 0
4570 /* rx_pkt_v2_cmpl (size:128b/16B) */
4571 struct rx_pkt_v2_cmpl {
4572 uint16_t flags_type;
4574 * This field indicates the exact type of the completion.
4575 * By convention, the LSB identifies the length of the
4576 * record in 16B units. Even values indicate 16B
4577 * records. Odd values indicate 32B
4580 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4581 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4583 * RX L2 V2 completion:
4584 * Completion of and L2 RX packet. Length = 32B
4585 * This is the new version of the RX_L2 completion used in SR2
4588 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4589 #define RX_PKT_V2_CMPL_TYPE_LAST \
4590 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4591 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4592 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4594 * When this bit is '1', it indicates a packet that has an
4595 * error of some type. Type of error is indicated in
4598 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4599 /* This field indicates how the packet was placed in the buffer. */
4600 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4601 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4604 * Packet was placed using normal algorithm.
4606 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4607 (UINT32_C(0x0) << 7)
4610 * Packet was placed using jumbo algorithm.
4612 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4613 (UINT32_C(0x1) << 7)
4615 * Header/Data Separation:
4616 * Packet was placed using Header/Data separation algorithm.
4617 * The separation location is indicated by the itype field.
4619 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4620 (UINT32_C(0x2) << 7)
4623 * Packet was placed using truncation algorithm. The
4624 * placed (truncated) length is indicated in the payload_offset
4625 * field. The original length is indicated in the len field.
4627 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4628 (UINT32_C(0x3) << 7)
4629 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4630 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4631 /* This bit is '1' if the RSS field in this completion is valid. */
4632 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4634 * This bit is '1' if metadata has been added to the end of the
4635 * packet in host memory. Metadata starts at the first 32B boundary
4636 * after the end of the packet for regular and jumbo placement.
4637 * It starts at the first 32B boundary after the end of the header
4638 * for HDS placement. The length of the metadata is indicated in the
4641 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4643 * This value indicates what the inner packet determined for the
4646 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4647 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4650 * Indicates that the packet type was not known.
4652 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4653 (UINT32_C(0x0) << 12)
4656 * Indicates that the packet was an IP packet, but further
4657 * classification was not possible.
4659 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4660 (UINT32_C(0x1) << 12)
4663 * Indicates that the packet was IP and TCP.
4664 * This indicates that the payload_offset field is valid.
4666 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4667 (UINT32_C(0x2) << 12)
4670 * Indicates that the packet was IP and UDP.
4671 * This indicates that the payload_offset field is valid.
4673 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4674 (UINT32_C(0x3) << 12)
4677 * Indicates that the packet was recognized as a FCoE.
4678 * This also indicates that the payload_offset field is valid.
4680 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4681 (UINT32_C(0x4) << 12)
4684 * Indicates that the packet was recognized as a RoCE.
4685 * This also indicates that the payload_offset field is valid.
4687 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4688 (UINT32_C(0x5) << 12)
4691 * Indicates that the packet was recognized as ICMP.
4692 * This indicates that the payload_offset field is valid.
4694 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
4695 (UINT32_C(0x7) << 12)
4697 * PtP packet wo/timestamp:
4698 * Indicates that the packet was recognized as a PtP
4701 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4702 (UINT32_C(0x8) << 12)
4704 * PtP packet w/timestamp:
4705 * Indicates that the packet was recognized as a PtP
4706 * packet and that a timestamp was taken for the packet.
4708 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4709 (UINT32_C(0x9) << 12)
4710 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
4711 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4713 * This is the length of the data for the packet stored in the
4714 * buffer(s) identified by the opaque value. This includes
4715 * the packet BD and any associated buffer BDs. This does not include
4716 * the length of any data places in aggregation BDs.
4720 * This is a copy of the opaque field from the RX BD this completion
4724 uint8_t agg_bufs_v1;
4726 * This value is written by the NIC such that it will be different
4727 * for each pass through the completion queue. The even passes
4728 * will write 1. The odd passes will write 0.
4730 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
4732 * This value is the number of aggregation buffers that follow this
4733 * entry in the completion ring that are a part of this packet.
4734 * If the value is zero, then the packet is completely contained
4735 * in the buffer space provided for the packet in the RX ring.
4737 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4738 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
4739 /* unused1 is 2 b */
4740 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4741 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
4743 * This is the RSS hash type for the packet. The value is packed
4744 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4746 * The value of tuple_extrac_op provides the information about
4747 * what fields the hash was computed on.
4748 * * 0: The RSS hash was computed over source IP address,
4749 * destination IP address, source port, and destination port of inner
4750 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4751 * the packet headers are considered inner packet headers for the RSS
4752 * hash computation purpose.
4753 * * 1: The RSS hash was computed over source IP address and destination
4754 * IP address of inner IP header. Note: For non-tunneled packets,
4755 * the packet headers are considered inner packet headers for the RSS
4756 * hash computation purpose.
4757 * * 2: The RSS hash was computed over source IP address,
4758 * destination IP address, source port, and destination port of
4759 * IP and TCP or UDP headers of outer tunnel headers.
4760 * Note: For non-tunneled packets, this value is not applicable.
4761 * * 3: The RSS hash was computed over source IP address and
4762 * destination IP address of IP header of outer tunnel headers.
4763 * Note: For non-tunneled packets, this value is not applicable.
4765 * Note that 4-tuples values listed above are applicable
4766 * for layer 4 protocols supported and enabled for RSS in the hardware,
4767 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4768 * enabled for TCP traffic only, then the values of tuple_extract_op
4769 * corresponding to 4-tuples are only valid for TCP traffic.
4771 uint8_t rss_hash_type;
4772 uint16_t metadata1_payload_offset;
4774 * This is data from the CFA as indicated by the meta_format field.
4775 * If truncation placement is not used, this value indicates the offset
4776 * in bytes from the beginning of the packet where the inner payload
4777 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
4778 * truncation placement is used, this value represents the placed
4779 * (truncated) length of the packet.
4781 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
4782 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
4783 /* This is data from the CFA as indicated by the meta_format field. */
4784 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4785 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
4786 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4787 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4788 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4790 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4791 (UINT32_C(0x0) << 12)
4793 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4794 (UINT32_C(0x1) << 12)
4796 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4797 (UINT32_C(0x2) << 12)
4799 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4800 (UINT32_C(0x3) << 12)
4802 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4803 (UINT32_C(0x4) << 12)
4804 /* Value programmed in CFA VLANTPID register. */
4805 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4806 (UINT32_C(0x5) << 12)
4807 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
4808 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4809 /* When meta_format != 0, this value is the VLAN valid. */
4810 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4812 * This value is the RSS hash value calculated for the packet
4813 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
4814 * is set in VNIC context, this is the lower 32b of the host address
4815 * from the first BD used to place the packet.
4820 /* Last 16 bytes of RX Packet V2 Completion Record */
4821 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
4822 struct rx_pkt_v2_cmpl_hi {
4825 * When this bit is '0', the cs_ok field has the following definition:-
4826 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4827 * in the delivered packet, counted from the outer-most header group to
4828 * the inner-most header group, stopping at the first error. -
4829 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4830 * in the delivered packet, counted from the outer-most header group to
4831 * the inner-most header group, stopping at the first error. When this
4832 * bit is '1', the cs_ok field has the following definition: -
4833 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4834 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4835 * will be '1' if all the parsed header groups with an IP checksum are
4836 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4837 * header groups with an L4 checksum are valid.
4839 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
4841 /* This value indicates what format the metadata field is. */
4842 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
4844 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
4845 /* There is no metadata information. Values are zero. */
4846 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
4847 (UINT32_C(0x0) << 4)
4849 * The {metadata1, metadata0} fields contain the vtag
4850 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4851 * de, vid[11:0]} The metadata2 field contains the table scope
4852 * and action record pointer. - metadata2[25:0] contains the
4853 * action record pointer. - metadata2[31:26] contains the table
4856 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
4857 (UINT32_C(0x1) << 4)
4859 * The {metadata1, metadata0} fields contain the vtag
4861 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4862 * The metadata2 field contains the Tunnel ID
4863 * value, justified to LSB. i
4864 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4865 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4866 * - NVGRE = TNI[23:0] -> Tenant Network ID
4867 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4868 * - IPv4 = 0 (not populated)
4869 * - IPv6 = Flow Label[19:0]
4870 * - PPPoE = sessionID[15:0]
4871 * - MPLs = Outer label[19:0]
4872 * - UPAR = Selected[31:0] with bit mask
4874 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
4875 (UINT32_C(0x2) << 4)
4877 * The {metadata1, metadata0} fields contain the vtag
4879 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4880 * The metadata2 field contains the 32b metadata from the prepended
4881 * header (chdr_data).
4883 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
4884 (UINT32_C(0x3) << 4)
4886 * The {metadata1, metadata0} fields contain the vtag
4888 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4889 * The metadata2 field contains the outer_l3_offset,
4890 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4891 * - metadata2[8:0] contains the outer_l3_offset.
4892 * - metadata2[17:9] contains the inner_l2_offset.
4893 * - metadata2[26:18] contains the inner_l3_offset.
4894 * - metadata2[31:27] contains the inner_l4_size.
4896 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
4897 (UINT32_C(0x4) << 4)
4898 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
4899 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
4901 * This field indicates the IP type for the inner-most IP header.
4902 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4903 * This value is only valid if itype indicates a packet
4904 * with an IP header.
4906 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
4909 * This indicates that the complete 1's complement checksum was
4910 * calculated for the packet.
4912 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
4915 * This field indicates the status of IP and L4 CS calculations done
4916 * by the chip. The format of this field is indicated by the
4917 * cs_all_ok_mode bit.
4919 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
4921 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
4923 * This value is the complete 1's complement checksum calculated from
4924 * the start of the outer L3 header to the end of the packet (not
4925 * including the ethernet crc). It is valid when the
4926 * 'complete_checksum_calc' flag is set.
4928 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
4929 UINT32_C(0xffff0000)
4930 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4932 * This is data from the CFA block as indicated by the meta_format
4934 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
4935 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
4936 * act_rec_ptr[25:0]}
4937 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
4938 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
4939 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
4940 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
4941 * of the host address from the first BD used to place the packet.
4946 * This value is written by the NIC such that it will be different
4947 * for each pass through the completion queue. The even passes
4948 * will write 1. The odd passes will write 0.
4950 #define RX_PKT_V2_CMPL_HI_V2 \
4952 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
4954 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
4956 * This error indicates that there was some sort of problem with
4957 * the BDs for the packet that was found after part of the
4958 * packet was already placed. The packet should be treated as
4961 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
4963 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
4964 /* No buffer error */
4965 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
4966 (UINT32_C(0x0) << 1)
4968 * Did Not Fit: Packet did not fit into packet buffer provided.
4969 * For regular placement, this means the packet did not fit in
4970 * the buffer provided. For HDS and jumbo placement, this means
4971 * that the packet could not be placed into 8 physical buffers
4972 * (if fixed-size buffers are used), or that the packet could
4973 * not be placed in the number of physical buffers configured
4974 * for the VNIC (if variable-size buffers are used)
4976 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4977 (UINT32_C(0x1) << 1)
4979 * Not On Chip: All BDs needed for the packet were not on-chip
4980 * when the packet arrived. For regular placement, this error is
4981 * not valid. For HDS and jumbo placement, this means that not
4982 * enough agg BDs were posted to place the packet.
4984 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4985 (UINT32_C(0x2) << 1)
4988 * BDs were not formatted correctly.
4990 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4991 (UINT32_C(0x3) << 1)
4994 * There was a bad_format error on the previous operation
4996 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
4997 (UINT32_C(0x5) << 1)
4998 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
4999 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5001 * This indicates that there was an error in the outer tunnel
5002 * portion of the packet when this field is non-zero.
5004 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5006 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5008 * No additional error occurred on the outer tunnel portion
5009 * of the packet or the packet does not have a outer tunnel.
5011 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5012 (UINT32_C(0x0) << 4)
5014 * Indicates that IP header version does not match expectation
5015 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5017 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5018 (UINT32_C(0x1) << 4)
5020 * Indicates that header length is out of range in the outer
5021 * tunnel header. Valid for IPv4.
5023 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5024 (UINT32_C(0x2) << 4)
5026 * Indicates that physical packet is shorter than that claimed
5027 * by the outer tunnel l3 header length. Valid for IPv4, or
5028 * IPv6 outer tunnel packets.
5030 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5031 (UINT32_C(0x3) << 4)
5033 * Indicates that the physical packet is shorter than that
5034 * claimed by the outer tunnel UDP header length for a outer
5035 * tunnel UDP packet that is not fragmented.
5037 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5038 (UINT32_C(0x4) << 4)
5040 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5041 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5044 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5045 (UINT32_C(0x5) << 4)
5047 * Indicates that the IP checksum failed its check in the outer
5050 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5051 (UINT32_C(0x6) << 4)
5053 * Indicates that the L4 checksum failed its check in the outer
5056 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5057 (UINT32_C(0x7) << 4)
5058 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5059 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5061 * This indicates that there was a CRC error on either an FCoE
5062 * or RoCE packet. The itype indicates the packet type.
5064 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5067 * This indicates that there was an error in the tunnel portion
5068 * of the packet when this field is non-zero.
5070 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5072 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5074 * No additional error occurred on the tunnel portion
5075 * of the packet or the packet does not have a tunnel.
5077 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5078 (UINT32_C(0x0) << 9)
5080 * Indicates that IP header version does not match expectation
5081 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5083 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5084 (UINT32_C(0x1) << 9)
5086 * Indicates that header length is out of range in the tunnel
5087 * header. Valid for IPv4.
5089 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5090 (UINT32_C(0x2) << 9)
5092 * Indicates that physical packet is shorter than that claimed
5093 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5096 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5097 (UINT32_C(0x3) << 9)
5099 * Indicates that the physical packet is shorter than that claimed
5100 * by the tunnel UDP header length for a tunnel UDP packet that is
5103 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5104 (UINT32_C(0x4) << 9)
5106 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5107 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5109 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5110 (UINT32_C(0x5) << 9)
5112 * Indicates that the IP checksum failed its check in the tunnel
5115 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5116 (UINT32_C(0x6) << 9)
5118 * Indicates that the L4 checksum failed its check in the tunnel
5121 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5122 (UINT32_C(0x7) << 9)
5123 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5124 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5126 * This indicates that there was an error in the inner
5127 * portion of the packet when this
5128 * field is non-zero.
5130 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5132 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5134 * No additional error occurred on the tunnel portion
5135 * or the packet of the packet does not have a tunnel.
5137 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5138 (UINT32_C(0x0) << 12)
5140 * Indicates that IP header version does not match
5141 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5142 * option other than VFT was parsed on
5145 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5146 (UINT32_C(0x1) << 12)
5148 * indicates that header length is out of range. Valid for
5151 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5152 (UINT32_C(0x2) << 12)
5154 * indicates that the IPv4 TTL or IPv6 hop limit check
5155 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5157 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5158 (UINT32_C(0x3) << 12)
5160 * Indicates that physical packet is shorter than that
5161 * claimed by the l3 header length. Valid for IPv4,
5162 * IPv6 packet or RoCE packets.
5164 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5165 (UINT32_C(0x4) << 12)
5167 * Indicates that the physical packet is shorter than that
5168 * claimed by the UDP header length for a UDP packet that is
5171 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5172 (UINT32_C(0x5) << 12)
5174 * Indicates that TCP header length > IP payload. Valid for
5177 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5178 (UINT32_C(0x6) << 12)
5179 /* Indicates that TCP header length < 5. Valid for TCP. */
5180 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5181 (UINT32_C(0x7) << 12)
5183 * Indicates that TCP option headers result in a TCP header
5184 * size that does not match data offset in TCP header. Valid
5187 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5188 (UINT32_C(0x8) << 12)
5190 * Indicates that the IP checksum failed its check in the
5193 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5194 (UINT32_C(0x9) << 12)
5196 * Indicates that the L4 checksum failed its check in the
5199 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5200 (UINT32_C(0xa) << 12)
5201 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5202 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5204 * This is data from the CFA block as indicated by the meta_format
5208 /* When meta_format=1, this value is the VLAN VID. */
5209 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5210 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5211 /* When meta_format=1, this value is the VLAN DE. */
5212 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5213 /* When meta_format=1, this value is the VLAN PRI. */
5214 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5215 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5217 * The timestamp field contains the 32b timestamp for the packet from
5224 * This TPA completion structure is used on devices where the
5225 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5227 /* rx_tpa_start_cmpl (size:128b/16B) */
5228 struct rx_tpa_start_cmpl {
5229 uint16_t flags_type;
5231 * This field indicates the exact type of the completion.
5232 * By convention, the LSB identifies the length of the
5233 * record in 16B units. Even values indicate 16B
5234 * records. Odd values indicate 32B
5237 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
5238 #define RX_TPA_START_CMPL_TYPE_SFT 0
5240 * RX L2 TPA Start Completion:
5241 * Completion at the beginning of a TPA operation.
5244 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
5245 #define RX_TPA_START_CMPL_TYPE_LAST \
5246 RX_TPA_START_CMPL_TYPE_RX_TPA_START
5247 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5248 #define RX_TPA_START_CMPL_FLAGS_SFT 6
5249 /* This bit will always be '0' for TPA start completions. */
5250 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
5251 /* This field indicates how the packet was placed in the buffer. */
5252 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5253 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
5256 * TPA Packet was placed using jumbo algorithm. This means
5257 * that the first buffer will be filled with data before
5258 * moving to aggregation buffers. Each aggregation buffer
5259 * will be filled before moving to the next aggregation
5262 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5263 (UINT32_C(0x1) << 7)
5265 * Header/Data Separation:
5266 * Packet was placed using Header/Data separation algorithm.
5267 * The separation location is indicated by the itype field.
5269 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
5270 (UINT32_C(0x2) << 7)
5273 * Packet will be placed using GRO/Jumbo where the first
5274 * packet is filled with data. Subsequent packets will be
5275 * placed such that any one packet does not span two
5276 * aggregation buffers unless it starts at the beginning of
5277 * an aggregation buffer.
5279 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5280 (UINT32_C(0x5) << 7)
5282 * GRO/Header-Data Separation:
5283 * Packet will be placed using GRO/HDS where the header
5284 * is in the first packet.
5285 * Payload of each packet will be
5286 * placed such that any one packet does not span two
5287 * aggregation buffers unless it starts at the beginning of
5288 * an aggregation buffer.
5290 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5291 (UINT32_C(0x6) << 7)
5292 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
5293 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5294 /* This bit is '1' if the RSS field in this completion is valid. */
5295 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5297 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
5299 * This value indicates what the inner packet determined for the
5302 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5303 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
5306 * Indicates that the packet was IP and TCP.
5308 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
5309 (UINT32_C(0x2) << 12)
5310 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
5311 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
5313 * This value indicates the amount of packet data written to the
5314 * buffer the opaque field in this completion corresponds to.
5318 * This is a copy of the opaque field from the RX BD this completion
5323 * This value is written by the NIC such that it will be different
5324 * for each pass through the completion queue. The even passes
5325 * will write 1. The odd passes will write 0.
5329 * This value is written by the NIC such that it will be different
5330 * for each pass through the completion queue. The even passes
5331 * will write 1. The odd passes will write 0.
5333 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
5334 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
5336 * This is the RSS hash type for the packet. The value is packed
5337 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5339 * The value of tuple_extrac_op provides the information about
5340 * what fields the hash was computed on.
5341 * * 0: The RSS hash was computed over source IP address,
5342 * destination IP address, source port, and destination port of inner
5343 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5344 * the packet headers are considered inner packet headers for the RSS
5345 * hash computation purpose.
5346 * * 1: The RSS hash was computed over source IP address and destination
5347 * IP address of inner IP header. Note: For non-tunneled packets,
5348 * the packet headers are considered inner packet headers for the RSS
5349 * hash computation purpose.
5350 * * 2: The RSS hash was computed over source IP address,
5351 * destination IP address, source port, and destination port of
5352 * IP and TCP or UDP headers of outer tunnel headers.
5353 * Note: For non-tunneled packets, this value is not applicable.
5354 * * 3: The RSS hash was computed over source IP address and
5355 * destination IP address of IP header of outer tunnel headers.
5356 * Note: For non-tunneled packets, this value is not applicable.
5358 * Note that 4-tuples values listed above are applicable
5359 * for layer 4 protocols supported and enabled for RSS in the hardware,
5360 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5361 * enabled for TCP traffic only, then the values of tuple_extract_op
5362 * corresponding to 4-tuples are only valid for TCP traffic.
5364 uint8_t rss_hash_type;
5366 * This is the aggregation ID that the completion is associated
5367 * with. Use this number to correlate the TPA start completion
5368 * with the TPA end completion.
5371 /* unused2 is 9 b */
5372 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
5373 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
5375 * This is the aggregation ID that the completion is associated
5376 * with. Use this number to correlate the TPA start completion
5377 * with the TPA end completion.
5379 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
5380 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
5382 * This value is the RSS hash value calculated for the packet
5383 * based on the mode bits and key value in the VNIC.
5389 * Last 16 bytes of rx_tpa_start_cmpl.
5391 * This TPA completion structure is used on devices where the
5392 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5394 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
5395 struct rx_tpa_start_cmpl_hi {
5398 * This indicates that the ip checksum was calculated for the
5399 * inner packet and that the sum passed for all segments
5400 * included in the aggregation.
5402 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5404 * This indicates that the TCP, UDP or ICMP checksum was
5405 * calculated for the inner packet and that the sum passed
5406 * for all segments included in the aggregation.
5408 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5410 * This indicates that the ip checksum was calculated for the
5411 * tunnel header and that the sum passed for all segments
5412 * included in the aggregation.
5414 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5416 * This indicates that the UDP checksum was
5417 * calculated for the tunnel packet and that the sum passed for
5418 * all segments included in the aggregation.
5420 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5421 /* This value indicates what format the metadata field is. */
5422 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5423 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5424 /* No metadata information. Value is zero. */
5425 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
5426 (UINT32_C(0x0) << 4)
5428 * The metadata field contains the VLAN tag and TPID value.
5429 * - metadata[11:0] contains the vlan VID value.
5430 * - metadata[12] contains the vlan DE value.
5431 * - metadata[15:13] contains the vlan PRI value.
5432 * - metadata[31:16] contains the vlan TPID value.
5434 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5435 (UINT32_C(0x1) << 4)
5436 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
5437 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
5439 * This field indicates the IP type for the inner-most IP header.
5440 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5442 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5444 * This is data from the CFA block as indicated by the meta_format
5448 /* When meta_format=1, this value is the VLAN VID. */
5449 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5450 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
5451 /* When meta_format=1, this value is the VLAN DE. */
5452 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
5453 /* When meta_format=1, this value is the VLAN PRI. */
5454 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5455 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
5456 /* When meta_format=1, this value is the VLAN TPID. */
5457 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5458 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
5461 * This value is written by the NIC such that it will be different
5462 * for each pass through the completion queue. The even passes
5463 * will write 1. The odd passes will write 0.
5465 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
5467 * This field identifies the CFA action rule that was used for this
5472 * This is the size in bytes of the inner most L4 header.
5473 * This can be subtracted from the payload_offset to determine
5474 * the start of the inner most L4 header.
5476 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5478 * This is the offset from the beginning of the packet in bytes for
5479 * the outer L3 header. If there is no outer L3 header, then this
5482 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5483 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
5485 * This is the offset from the beginning of the packet in bytes for
5486 * the inner most L2 header.
5488 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5489 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
5491 * This is the offset from the beginning of the packet in bytes for
5492 * the inner most L3 header.
5494 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5495 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
5497 * This is the size in bytes of the inner most L4 header.
5498 * This can be subtracted from the payload_offset to determine
5499 * the start of the inner most L4 header.
5501 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5502 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
5506 * This TPA completion structure is used on devices where the
5507 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5508 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
5511 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
5512 struct rx_tpa_start_v2_cmpl {
5513 uint16_t flags_type;
5515 * This field indicates the exact type of the completion.
5516 * By convention, the LSB identifies the length of the
5517 * record in 16B units. Even values indicate 16B
5518 * records. Odd values indicate 32B
5521 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
5523 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
5525 * RX L2 TPA Start V2 Completion:
5526 * Completion at the beginning of a TPA operation.
5528 * This is the new version of the RX_TPA_START completion used
5529 * in SR2 and later chips.
5531 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
5533 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
5534 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
5535 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
5537 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
5539 * When this bit is '1', it indicates a packet that has an error
5540 * of some type. Type of error is indicated in error_flags.
5542 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
5544 /* This field indicates how the packet was placed in the buffer. */
5545 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
5547 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
5550 * TPA Packet was placed using jumbo algorithm. This means
5551 * that the first buffer will be filled with data before
5552 * moving to aggregation buffers. Each aggregation buffer
5553 * will be filled before moving to the next aggregation
5556 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
5557 (UINT32_C(0x1) << 7)
5559 * Header/Data Separation:
5560 * Packet was placed using Header/Data separation algorithm.
5561 * The separation location is indicated by the itype field.
5563 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
5564 (UINT32_C(0x2) << 7)
5567 * Packet will be placed using In-Order Completion/Jumbo where
5568 * the first packet of the aggregation is placed using Jumbo
5569 * Placement. Subsequent packets will be placed such that each
5570 * packet starts at the beginning of an aggregation buffer.
5572 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
5573 (UINT32_C(0x4) << 7)
5576 * Packet will be placed using GRO/Jumbo where the first
5577 * packet is filled with data. Subsequent packets will be
5578 * placed such that any one packet does not span two
5579 * aggregation buffers unless it starts at the beginning of
5580 * an aggregation buffer.
5582 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5583 (UINT32_C(0x5) << 7)
5585 * GRO/Header-Data Separation:
5586 * Packet will be placed using GRO/HDS where the header
5587 * is in the first packet.
5588 * Payload of each packet will be
5589 * placed such that any one packet does not span two
5590 * aggregation buffers unless it starts at the beginning of
5591 * an aggregation buffer.
5593 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5594 (UINT32_C(0x6) << 7)
5596 * IOC/Header-Data Separation:
5597 * Packet will be placed using In-Order Completion/HDS where
5598 * the header is in the first packet buffer. Payload of each
5599 * packet will be placed such that each packet starts at the
5600 * beginning of an aggregation buffer.
5602 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
5603 (UINT32_C(0x7) << 7)
5604 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
5605 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
5606 /* This bit is '1' if the RSS field in this completion is valid. */
5607 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
5610 * This bit is '1' if metadata has been added to the end of the
5611 * packet in host memory. Metadata starts at the first 32B boundary
5612 * after the end of the packet for regular and jumbo placement. It
5613 * starts at the first 32B boundary after the end of the header for
5614 * HDS placement. The length of the metadata is indicated in the
5617 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
5620 * This value indicates what the inner packet determined for the
5623 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
5625 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
5628 * Indicates that the packet was IP and TCP.
5630 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
5631 (UINT32_C(0x2) << 12)
5632 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
5633 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
5635 * This value indicates the amount of packet data written to the
5636 * buffer the opaque field in this completion corresponds to.
5640 * This is a copy of the opaque field from the RX BD this completion
5641 * corresponds to. If the VNIC is configured to not use an Rx BD for
5642 * the TPA Start completion, then this is a copy of the opaque field
5643 * from the first BD used to place the TPA Start packet.
5647 * This value is written by the NIC such that it will be different
5648 * for each pass through the completion queue. The even passes
5649 * will write 1. The odd passes will write 0.
5653 * This value is written by the NIC such that it will be different
5654 * for each pass through the completion queue. The even passes
5655 * will write 1. The odd passes will write 0.
5657 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
5658 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
5660 * This is the RSS hash type for the packet. The value is packed
5661 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5663 * The value of tuple_extrac_op provides the information about
5664 * what fields the hash was computed on.
5665 * * 0: The RSS hash was computed over source IP address,
5666 * destination IP address, source port, and destination port of inner
5667 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5668 * the packet headers are considered inner packet headers for the RSS
5669 * hash computation purpose.
5670 * * 1: The RSS hash was computed over source IP address and destination
5671 * IP address of inner IP header. Note: For non-tunneled packets,
5672 * the packet headers are considered inner packet headers for the RSS
5673 * hash computation purpose.
5674 * * 2: The RSS hash was computed over source IP address,
5675 * destination IP address, source port, and destination port of
5676 * IP and TCP or UDP headers of outer tunnel headers.
5677 * Note: For non-tunneled packets, this value is not applicable.
5678 * * 3: The RSS hash was computed over source IP address and
5679 * destination IP address of IP header of outer tunnel headers.
5680 * Note: For non-tunneled packets, this value is not applicable.
5682 * Note that 4-tuples values listed above are applicable
5683 * for layer 4 protocols supported and enabled for RSS in the hardware,
5684 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5685 * enabled for TCP traffic only, then the values of tuple_extract_op
5686 * corresponding to 4-tuples are only valid for TCP traffic.
5688 uint8_t rss_hash_type;
5690 * This is the aggregation ID that the completion is associated
5691 * with. Use this number to correlate the TPA start completion
5692 * with the TPA end completion.
5696 * This is the aggregation ID that the completion is associated
5697 * with. Use this number to correlate the TPA start completion
5698 * with the TPA end completion.
5700 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
5701 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
5702 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
5704 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
5705 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5706 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
5708 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5710 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5711 (UINT32_C(0x0) << 12)
5713 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5714 (UINT32_C(0x1) << 12)
5716 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5717 (UINT32_C(0x2) << 12)
5719 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5720 (UINT32_C(0x3) << 12)
5722 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5723 (UINT32_C(0x4) << 12)
5724 /* Value programmed in CFA VLANTPID register. */
5725 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5726 (UINT32_C(0x5) << 12)
5727 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
5728 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5729 /* When meta_format != 0, this value is the VLAN valid. */
5730 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
5733 * This value is the RSS hash value calculated for the packet
5734 * based on the mode bits and key value in the VNIC.
5735 * When vee_cmpl_mode is set in VNIC context, this is the lower
5736 * 32b of the host address from the first BD used to place the packet.
5742 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
5744 * This TPA completion structure is used on devices where the
5745 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5747 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
5748 struct rx_tpa_start_v2_cmpl_hi {
5750 /* This indicates that the aggregation was done using GRO rules. */
5751 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
5754 * When this bit is '0', the cs_ok field has the following definition:-
5755 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5756 * in the delivered packet, counted from the outer-most header group to
5757 * the inner-most header group, stopping at the first error. -
5758 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5759 * in the delivered packet, counted from the outer-most header group to
5760 * the inner-most header group, stopping at the first error. When this
5761 * bit is '1', the cs_ok field has the following definition: -
5762 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5763 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5764 * will be '1' if all the parsed header groups with an IP checksum are
5765 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5766 * header groups with an L4 checksum are valid.
5768 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
5770 /* This value indicates what format the metadata field is. */
5771 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
5773 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
5774 /* There is no metadata information. Values are zero. */
5775 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
5776 (UINT32_C(0x0) << 4)
5778 * The {metadata1, metadata0} fields contain the vtag
5779 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5780 * de, vid[11:0]} The metadata2 field contains the table scope
5781 * and action record pointer. - metadata2[25:0] contains the
5782 * action record pointer. - metadata2[31:26] contains the table
5785 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
5786 (UINT32_C(0x1) << 4)
5788 * The {metadata1, metadata0} fields contain the vtag
5790 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5791 * The metadata2 field contains the Tunnel ID
5792 * value, justified to LSB. i
5793 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5794 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5795 * - NVGRE = TNI[23:0] -> Tenant Network ID
5796 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5797 * - IPv4 = 0 (not populated)
5798 * - IPv6 = Flow Label[19:0]
5799 * - PPPoE = sessionID[15:0]
5800 * - MPLs = Outer label[19:0]
5801 * - UPAR = Selected[31:0] with bit mask
5803 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5804 (UINT32_C(0x2) << 4)
5806 * The {metadata1, metadata0} fields contain the vtag
5808 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5809 * The metadata2 field contains the 32b metadata from the prepended
5810 * header (chdr_data).
5812 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5813 (UINT32_C(0x3) << 4)
5815 * The {metadata1, metadata0} fields contain the vtag
5817 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5818 * The metadata2 field contains the outer_l3_offset,
5819 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5820 * - metadata2[8:0] contains the outer_l3_offset.
5821 * - metadata2[17:9] contains the inner_l2_offset.
5822 * - metadata2[26:18] contains the inner_l3_offset.
5823 * - metadata2[31:27] contains the inner_l4_size.
5825 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5826 (UINT32_C(0x4) << 4)
5827 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
5828 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5830 * This field indicates the IP type for the inner-most IP header.
5831 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5832 * This value is only valid if itype indicates a packet
5833 * with an IP header.
5835 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
5838 * This indicates that the complete 1's complement checksum was
5839 * calculated for the packet in the affregation.
5841 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5844 * This field indicates the status of IP and L4 CS calculations done
5845 * by the chip. The format of this field is indicated by the
5846 * cs_all_ok_mode bit.
5847 * CS status for TPA packets is always valid. This means that "all_ok"
5848 * status will always be set. The ok count status will be set
5849 * appropriately for the packet header, such that all existing CS
5852 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
5854 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
5856 * This value is the complete 1's complement checksum calculated from
5857 * the start of the outer L3 header to the end of the packet (not
5858 * including the ethernet crc). It is valid when the
5859 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5860 * the complete checksum is calculated for the first packet in the
5863 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5864 UINT32_C(0xffff0000)
5865 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5867 * This is data from the CFA block as indicated by the meta_format
5869 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5870 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5871 * act_rec_ptr[25:0]}
5872 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5873 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5874 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5875 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5876 * of the host address from the first BD used to place the packet.
5881 * This value is written by the NIC such that it will be different
5882 * for each pass through the completion queue. The even passes
5883 * will write 1. The odd passes will write 0.
5885 #define RX_TPA_START_V2_CMPL_V2 \
5887 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
5889 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
5891 * This error indicates that there was some sort of problem with
5892 * the BDs for the packetThe packet should be treated as
5895 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
5897 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5898 /* No buffer error */
5899 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5900 (UINT32_C(0x0) << 1)
5903 * Packet did not fit into packet buffer provided. This means
5904 * that the TPA Start packet was too big to be placed into the
5905 * per-packet maximum number of physical buffers configured for
5906 * the VNIC, or that it was too big to be placed into the
5907 * per-aggregation maximum number of physical buffers configured
5908 * for the VNIC. This error only occurs when the VNIC is
5909 * configured for variable size receive buffers.
5911 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5912 (UINT32_C(0x1) << 1)
5915 * BDs were not formatted correctly.
5917 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5918 (UINT32_C(0x3) << 1)
5921 * There was a bad_format error on the previous operation
5923 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5924 (UINT32_C(0x5) << 1)
5925 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
5926 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5928 * This is data from the CFA block as indicated by the meta_format
5932 /* When meta_format != 0, this value is the VLAN VID. */
5933 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
5934 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
5935 /* When meta_format != 0, this value is the VLAN DE. */
5936 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
5937 /* When meta_format != 0, this value is the VLAN PRI. */
5938 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
5939 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
5941 * This field contains the outer_l3_offset, inner_l2_offset,
5942 * inner_l3_offset, and inner_l4_size.
5944 * hdr_offsets[8:0] contains the outer_l3_offset.
5945 * hdr_offsets[17:9] contains the inner_l2_offset.
5946 * hdr_offsets[26:18] contains the inner_l3_offset.
5947 * hdr_offsets[31:27] contains the inner_l4_size.
5949 uint32_t hdr_offsets;
5953 * This TPA completion structure is used on devices where the
5954 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5956 /* rx_tpa_end_cmpl (size:128b/16B) */
5957 struct rx_tpa_end_cmpl {
5958 uint16_t flags_type;
5960 * This field indicates the exact type of the completion.
5961 * By convention, the LSB identifies the length of the
5962 * record in 16B units. Even values indicate 16B
5963 * records. Odd values indicate 32B
5966 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
5967 #define RX_TPA_END_CMPL_TYPE_SFT 0
5969 * RX L2 TPA End Completion:
5970 * Completion at the end of a TPA operation.
5973 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
5974 #define RX_TPA_END_CMPL_TYPE_LAST \
5975 RX_TPA_END_CMPL_TYPE_RX_TPA_END
5976 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5977 #define RX_TPA_END_CMPL_FLAGS_SFT 6
5979 * When this bit is '1', it indicates a packet that has an
5980 * error of some type. Type of error is indicated in
5983 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
5984 /* This field indicates how the packet was placed in the buffer. */
5985 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5986 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
5989 * TPA Packet was placed using jumbo algorithm. This means
5990 * that the first buffer will be filled with data before
5991 * moving to aggregation buffers. Each aggregation buffer
5992 * will be filled before moving to the next aggregation
5995 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
5996 (UINT32_C(0x1) << 7)
5998 * Header/Data Separation:
5999 * Packet was placed using Header/Data separation algorithm.
6000 * The separation location is indicated by the itype field.
6002 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
6003 (UINT32_C(0x2) << 7)
6006 * Packet will be placed using In-Order Completion/Jumbo where
6007 * the first packet of the aggregation is placed using Jumbo
6008 * Placement. Subsequent packets will be placed such that each
6009 * packet starts at the beginning of an aggregation buffer.
6011 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6012 (UINT32_C(0x4) << 7)
6015 * Packet will be placed using GRO/Jumbo where the first
6016 * packet is filled with data. Subsequent packets will be
6017 * placed such that any one packet does not span two
6018 * aggregation buffers unless it starts at the beginning of
6019 * an aggregation buffer.
6021 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6022 (UINT32_C(0x5) << 7)
6024 * GRO/Header-Data Separation:
6025 * Packet will be placed using GRO/HDS where the header
6026 * is in the first packet.
6027 * Payload of each packet will be
6028 * placed such that any one packet does not span two
6029 * aggregation buffers unless it starts at the beginning of
6030 * an aggregation buffer.
6032 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6033 (UINT32_C(0x6) << 7)
6035 * IOC/Header-Data Separation:
6036 * Packet will be placed using In-Order Completion/HDS where
6037 * the header is in the first packet buffer. Payload of each
6038 * packet will be placed such that each packet starts at the
6039 * beginning of an aggregation buffer.
6041 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6042 (UINT32_C(0x7) << 7)
6043 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
6044 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6046 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
6048 * This bit is '1' if metadata has been added to the end of the
6049 * packet in host memory. Metadata starts at the first 32B boundary
6050 * after the end of the packet for regular and jumbo placement.
6051 * It starts at the first 32B boundary after the end of the header
6052 * for HDS placement. The length of the metadata is indicated in the
6055 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6057 * This value indicates what the inner packet determined for the
6060 * Indicates that the packet was IP and TCP. This indicates
6061 * that the ip_cs field is valid and that the tcp_udp_cs
6062 * field is valid and contains the TCP checksum.
6063 * This also indicates that the payload_offset field is valid.
6065 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
6067 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
6069 * This value is zero for TPA End completions.
6070 * There is no data in the buffer that corresponds to the opaque
6071 * value in this completion.
6075 * This is a copy of the opaque field from the RX BD this completion
6080 * This value is written by the NIC such that it will be different
6081 * for each pass through the completion queue. The even passes
6082 * will write 1. The odd passes will write 0.
6084 uint8_t agg_bufs_v1;
6086 * This value is written by the NIC such that it will be different
6087 * for each pass through the completion queue. The even passes
6088 * will write 1. The odd passes will write 0.
6090 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
6092 * This value is the number of aggregation buffers that follow this
6093 * entry in the completion ring that are a part of this aggregation
6095 * If the value is zero, then the packet is completely contained
6096 * in the buffer space provided in the aggregation start completion.
6098 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
6099 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
6100 /* This value is the number of segments in the TPA operation. */
6103 * This value indicates the offset in bytes from the beginning of the packet
6104 * where the inner payload starts. This value is valid for TCP, UDP,
6105 * FCoE, and RoCE packets.
6107 * A value of zero indicates an offset of 256 bytes.
6109 uint8_t payload_offset;
6111 /* unused2 is 1 b */
6112 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
6114 * This is the aggregation ID that the completion is associated
6115 * with. Use this number to correlate the TPA start completion
6116 * with the TPA end completion.
6118 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
6119 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
6121 * For non-GRO packets, this value is the
6122 * timestamp delta between earliest and latest timestamp values for
6123 * TPA packet. If packets were not time stamped, then delta will be
6126 * For GRO packets, this field is zero except for the following
6129 * Timestamp present indication. When '0', no Timestamp
6130 * option is in the packet. When '1', then a Timestamp
6131 * option is present in the packet.
6137 * Last 16 bytes of rx_tpa_end_cmpl.
6139 * This TPA completion structure is used on devices where the
6140 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6142 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
6143 struct rx_tpa_end_cmpl_hi {
6144 uint32_t tpa_dup_acks;
6146 * This value is the number of duplicate ACKs that have been
6147 * received as part of the TPA operation.
6149 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6150 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
6152 * This value is the valid when TPA completion is active. It
6153 * indicates the length of the longest segment of the TPA operation
6154 * for LRO mode and the length of the first segment in GRO mode.
6156 * This value may be used by GRO software to re-construct the original
6157 * packet stream from the TPA packet. This is the length of all
6158 * but the last segment for GRO. In LRO mode this value may be used
6159 * to indicate MSS size to the stack.
6161 uint16_t tpa_seg_len;
6162 /* unused4 is 16 b */
6166 * This value is written by the NIC such that it will be different
6167 * for each pass through the completion queue. The even passes
6168 * will write 1. The odd passes will write 0.
6170 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
6171 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
6172 #define RX_TPA_END_CMPL_ERRORS_SFT 1
6174 * This error indicates that there was some sort of problem with
6175 * the BDs for the packet that was found after part of the
6176 * packet was already placed. The packet should be treated as
6179 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6180 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6182 * This error occurs when there is a fatal HW problem in
6183 * the chip only. It indicates that there were not
6184 * BDs on chip but that there was adequate reservation.
6185 * provided by the TPA block.
6187 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6188 (UINT32_C(0x2) << 1)
6190 * This error occurs when TPA block was not configured to
6191 * reserve adequate BDs for TPA operations on this RX
6192 * ring. All data for the TPA operation was not placed.
6194 * This error can also be generated when the number of
6195 * segments is not programmed correctly in TPA and the
6196 * 33 total aggregation buffers allowed for the TPA
6197 * operation has been exceeded.
6199 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6200 (UINT32_C(0x4) << 1)
6201 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6202 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
6203 /* unused5 is 16 b */
6206 * This is the opaque value that was completed for the TPA start
6207 * completion that corresponds to this TPA end completion.
6209 uint32_t start_opaque;
6213 * This TPA completion structure is used on devices where the
6214 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6216 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
6217 struct rx_tpa_v2_start_cmpl {
6218 uint16_t flags_type;
6220 * This field indicates the exact type of the completion.
6221 * By convention, the LSB identifies the length of the
6222 * record in 16B units. Even values indicate 16B
6223 * records. Odd values indicate 32B
6226 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
6228 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
6230 * RX L2 TPA Start Completion:
6231 * Completion at the beginning of a TPA operation.
6234 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
6236 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
6237 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
6238 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
6240 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
6241 /* This bit will always be '0' for TPA start completions. */
6242 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
6244 /* This field indicates how the packet was placed in the buffer. */
6245 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
6247 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
6250 * TPA Packet was placed using jumbo algorithm. This means
6251 * that the first buffer will be filled with data before
6252 * moving to aggregation buffers. Each aggregation buffer
6253 * will be filled before moving to the next aggregation
6256 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6257 (UINT32_C(0x1) << 7)
6259 * Header/Data Separation:
6260 * Packet was placed using Header/Data separation algorithm.
6261 * The separation location is indicated by the itype field.
6263 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
6264 (UINT32_C(0x2) << 7)
6267 * Packet will be placed using GRO/Jumbo where the first
6268 * packet is filled with data. Subsequent packets will be
6269 * placed such that any one packet does not span two
6270 * aggregation buffers unless it starts at the beginning of
6271 * an aggregation buffer.
6273 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6274 (UINT32_C(0x5) << 7)
6276 * GRO/Header-Data Separation:
6277 * Packet will be placed using GRO/HDS where the header
6278 * is in the first packet.
6279 * Payload of each packet will be
6280 * placed such that any one packet does not span two
6281 * aggregation buffers unless it starts at the beginning of
6282 * an aggregation buffer.
6284 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6285 (UINT32_C(0x6) << 7)
6286 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
6287 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6288 /* This bit is '1' if the RSS field in this completion is valid. */
6289 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
6292 * For devices that support timestamps, when this bit is cleared the
6293 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6294 * field contains the 32b timestamp for
6295 * the packet from the MAC. When this bit is set, the
6296 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6297 * field contains the outer_l3_offset, inner_l2_offset,
6298 * inner_l3_offset, and inner_l4_size.
6300 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
6303 * This value indicates what the inner packet determined for the
6306 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
6308 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
6311 * Indicates that the packet was IP and TCP.
6313 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
6314 (UINT32_C(0x2) << 12)
6315 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
6316 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
6318 * This value indicates the amount of packet data written to the
6319 * buffer the opaque field in this completion corresponds to.
6323 * This is a copy of the opaque field from the RX BD this completion
6328 * This value is written by the NIC such that it will be different
6329 * for each pass through the completion queue. The even passes
6330 * will write 1. The odd passes will write 0.
6334 * This value is written by the NIC such that it will be different
6335 * for each pass through the completion queue. The even passes
6336 * will write 1. The odd passes will write 0.
6338 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
6339 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
6341 * This is the RSS hash type for the packet. The value is packed
6342 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6344 * The value of tuple_extrac_op provides the information about
6345 * what fields the hash was computed on.
6346 * * 0: The RSS hash was computed over source IP address,
6347 * destination IP address, source port, and destination port of inner
6348 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6349 * the packet headers are considered inner packet headers for the RSS
6350 * hash computation purpose.
6351 * * 1: The RSS hash was computed over source IP address and destination
6352 * IP address of inner IP header. Note: For non-tunneled packets,
6353 * the packet headers are considered inner packet headers for the RSS
6354 * hash computation purpose.
6355 * * 2: The RSS hash was computed over source IP address,
6356 * destination IP address, source port, and destination port of
6357 * IP and TCP or UDP headers of outer tunnel headers.
6358 * Note: For non-tunneled packets, this value is not applicable.
6359 * * 3: The RSS hash was computed over source IP address and
6360 * destination IP address of IP header of outer tunnel headers.
6361 * Note: For non-tunneled packets, this value is not applicable.
6363 * Note that 4-tuples values listed above are applicable
6364 * for layer 4 protocols supported and enabled for RSS in the hardware,
6365 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6366 * enabled for TCP traffic only, then the values of tuple_extract_op
6367 * corresponding to 4-tuples are only valid for TCP traffic.
6369 uint8_t rss_hash_type;
6371 * This is the aggregation ID that the completion is associated
6372 * with. Use this number to correlate the TPA start completion
6373 * with the TPA end completion.
6377 * This value is the RSS hash value calculated for the packet
6378 * based on the mode bits and key value in the VNIC.
6384 * Last 16 bytes of rx_tpa_v2_start_cmpl.
6386 * This TPA completion structure is used on devices where the
6387 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6389 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
6390 struct rx_tpa_v2_start_cmpl_hi {
6393 * This indicates that the ip checksum was calculated for the
6394 * inner packet and that the sum passed for all segments
6395 * included in the aggregation.
6397 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
6400 * This indicates that the TCP, UDP or ICMP checksum was
6401 * calculated for the inner packet and that the sum passed
6402 * for all segments included in the aggregation.
6404 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
6407 * This indicates that the ip checksum was calculated for the
6408 * tunnel header and that the sum passed for all segments
6409 * included in the aggregation.
6411 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
6414 * This indicates that the UDP checksum was
6415 * calculated for the tunnel packet and that the sum passed for
6416 * all segments included in the aggregation.
6418 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
6420 /* This value indicates what format the metadata field is. */
6421 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
6423 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6424 /* No metadata informtaion. Value is zero. */
6425 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
6426 (UINT32_C(0x0) << 4)
6428 * The metadata field contains the VLAN tag and TPID value.
6429 * - metadata[11:0] contains the vlan VID value.
6430 * - metadata[12] contains the vlan DE value.
6431 * - metadata[15:13] contains the vlan PRI value.
6432 * - metadata[31:16] contains the vlan TPID value.
6434 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6435 (UINT32_C(0x1) << 4)
6437 * If ext_meta_format is equal to 1, the metadata field
6438 * contains the lower 16b of the tunnel ID value, justified
6440 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6441 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
6442 * - NVGRE = TNI[23:0] -> Tenant Network ID
6443 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
6444 * - IPV4 = 0 (not populated)
6445 * - IPV6 = Flow Label[19:0]
6446 * - PPPoE = sessionID[15:0]
6447 * - MPLs = Outer label[19:0]
6448 * - UPAR = Selected[31:0] with bit mask
6450 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
6451 (UINT32_C(0x2) << 4)
6453 * if ext_meta_format is equal to 1, metadata field contains
6454 * 16b metadata from the prepended header (chdr_data).
6456 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6457 (UINT32_C(0x3) << 4)
6459 * If ext_meta_format is equal to 1, the metadata field contains
6460 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
6462 * - metadata[8:0] contains the outer_l3_offset.
6463 * - metadata[17:9] contains the inner_l2_offset.
6464 * - metadata[26:18] contains the inner_l3_offset.
6465 * - metadata[31:27] contains the inner_l4_size.
6467 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6468 (UINT32_C(0x4) << 4)
6469 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
6470 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6472 * This field indicates the IP type for the inner-most IP header.
6473 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6475 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
6478 * This indicates that the complete 1's complement checksum was
6479 * calculated for the packet.
6481 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6484 * The combination of this value and meta_format indicated what
6485 * format the metadata field is.
6487 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
6489 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
6491 * This value is the complete 1's complement checksum calculated from
6492 * the start of the outer L3 header to the end of the packet (not
6493 * including the ethernet crc). It is valid when the
6494 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6495 * the complete checksum is calculated for the first packet in the
6498 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6499 UINT32_C(0xffff0000)
6500 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6502 * This is data from the CFA block as indicated by the meta_format
6506 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
6507 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6508 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
6509 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
6510 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
6511 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
6512 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6513 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
6514 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
6515 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6516 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
6519 * This value is written by the NIC such that it will be different
6520 * for each pass through the completion queue. The even passes
6521 * will write 1. The odd passes will write 0.
6523 #define RX_TPA_V2_START_CMPL_V2 \
6525 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
6527 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
6529 * This error indicates that there was some sort of problem with
6530 * the BDs for the packet that was found after part of the
6531 * packet was already placed. The packet should be treated as
6534 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
6536 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6537 /* No buffer error */
6538 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6539 (UINT32_C(0x0) << 1)
6542 * BDs were not formatted correctly.
6544 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6545 (UINT32_C(0x3) << 1)
6548 * There was a bad_format error on the previous operation
6550 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6551 (UINT32_C(0x5) << 1)
6552 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
6553 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6555 * This field identifies the CFA action rule that was used for this
6560 * For devices that support timestamps this field is overridden
6561 * with the timestamp value. When `flags.timestamp_fld_format` is
6562 * cleared, this field contains the 32b timestamp for the packet from the
6565 * When `flags.timestamp_fld_format` is set, this field contains the
6566 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
6569 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6571 * This is the offset from the beginning of the packet in bytes for
6572 * the outer L3 header. If there is no outer L3 header, then this
6575 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6576 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
6578 * This is the offset from the beginning of the packet in bytes for
6579 * the inner most L2 header.
6581 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6582 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
6584 * This is the offset from the beginning of the packet in bytes for
6585 * the inner most L3 header.
6587 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6588 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
6590 * This is the size in bytes of the inner most L4 header.
6591 * This can be subtracted from the payload_offset to determine
6592 * the start of the inner most L4 header.
6594 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6595 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
6599 * This TPA completion structure is used on devices where the
6600 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6602 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
6603 struct rx_tpa_v2_end_cmpl {
6604 uint16_t flags_type;
6606 * This field indicates the exact type of the completion.
6607 * By convention, the LSB identifies the length of the
6608 * record in 16B units. Even values indicate 16B
6609 * records. Odd values indicate 32B
6612 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
6614 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
6616 * RX L2 TPA End Completion:
6617 * Completion at the end of a TPA operation.
6620 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
6622 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
6623 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
6624 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
6626 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
6628 * When this bit is '1', it indicates a packet that has an
6629 * error of some type. Type of error is indicated in
6632 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
6634 /* This field indicates how the packet was placed in the buffer. */
6635 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
6637 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
6640 * TPA Packet was placed using jumbo algorithm. This means
6641 * that the first buffer will be filled with data before
6642 * moving to aggregation buffers. Each aggregation buffer
6643 * will be filled before moving to the next aggregation
6646 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6647 (UINT32_C(0x1) << 7)
6649 * Header/Data Separation:
6650 * Packet was placed using Header/Data separation algorithm.
6651 * The separation location is indicated by the itype field.
6653 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
6654 (UINT32_C(0x2) << 7)
6657 * Packet will be placed using GRO/Jumbo where the first
6658 * packet is filled with data. Subsequent packets will be
6659 * placed such that any one packet does not span two
6660 * aggregation buffers unless it starts at the beginning of
6661 * an aggregation buffer.
6663 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6664 (UINT32_C(0x5) << 7)
6666 * GRO/Header-Data Separation:
6667 * Packet will be placed using GRO/HDS where the header
6668 * is in the first packet.
6669 * Payload of each packet will be
6670 * placed such that any one packet does not span two
6671 * aggregation buffers unless it starts at the beginning of
6672 * an aggregation buffer.
6674 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6675 (UINT32_C(0x6) << 7)
6677 * IOC/Header-Data Separation:
6678 * Packet will be placed using In-Order Completion/HDS where
6679 * the header is in the first packet buffer. Payload of each
6680 * packet will be placed such that each packet starts at the
6681 * beginning of an aggregation buffer.
6683 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6684 (UINT32_C(0x7) << 7)
6685 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
6686 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6688 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
6691 * This bit is '1' if metadata has been added to the end of the
6692 * packet in host memory. Metadata starts at the first 32B boundary
6693 * after the end of the packet for regular and jumbo placement.
6694 * It starts at the first 32B boundary after the end of the header
6695 * for HDS placement. The length of the metadata is indicated in the
6698 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
6701 * This value indicates what the inner packet determined for the
6704 * Indicates that the packet was IP and TCP. This indicates
6705 * that the ip_cs field is valid and that the tcp_udp_cs
6706 * field is valid and contains the TCP checksum.
6707 * This also indicates that the payload_offset field is valid.
6709 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
6711 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
6713 * This value is zero for TPA End completions.
6714 * There is no data in the buffer that corresponds to the opaque
6715 * value in this completion.
6719 * This is a copy of the opaque field from the RX BD this completion
6725 * This value is written by the NIC such that it will be different
6726 * for each pass through the completion queue. The even passes
6727 * will write 1. The odd passes will write 0.
6729 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
6730 /* This value is the number of segments in the TPA operation. */
6733 * This is the aggregation ID that the completion is associated
6734 * with. Use this number to correlate the TPA start completion
6735 * with the TPA end completion.
6739 * For non-GRO packets, this value is the
6740 * timestamp delta between earliest and latest timestamp values for
6741 * TPA packet. If packets were not time stamped, then delta will be
6744 * For GRO packets, this field is zero except for the following
6747 * Timestamp present indication. When '0', no Timestamp
6748 * option is in the packet. When '1', then a Timestamp
6749 * option is present in the packet.
6755 * Last 16 bytes of rx_tpa_v2_end_cmpl.
6757 * This TPA completion structure is used on devices where the
6758 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6760 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
6761 struct rx_tpa_v2_end_cmpl_hi {
6763 * This value is the number of duplicate ACKs that have been
6764 * received as part of the TPA operation.
6766 uint16_t tpa_dup_acks;
6768 * This value is the number of duplicate ACKs that have been
6769 * received as part of the TPA operation.
6771 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6772 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
6774 * This value indicated the offset in bytes from the beginning of
6775 * the packet where the inner payload starts. This value is valid
6776 * for TCP, UDP, FCoE and RoCE packets
6778 uint8_t payload_offset;
6780 * The value is the total number of aggregation buffers that were
6781 * used in the TPA operation. All TPA aggregation buffer completions
6782 * precede the TPA End completion. If the value is zero, then the
6783 * aggregation is completely contained in the buffer space provided
6784 * in the aggregation start completion.
6785 * Note that the field is simply provided as a cross check.
6787 uint8_t tpa_agg_bufs;
6789 * This value is the valid when TPA completion is active. It
6790 * indicates the length of the longest segment of the TPA operation
6791 * for LRO mode and the length of the first segment in GRO mode.
6793 * This value may be used by GRO software to re-construct the original
6794 * packet stream from the TPA packet. This is the length of all
6795 * but the last segment for GRO. In LRO mode this value may be used
6796 * to indicate MSS size to the stack.
6798 uint16_t tpa_seg_len;
6802 * This value is written by the NIC such that it will be different
6803 * for each pass through the completion queue. The even passes
6804 * will write 1. The odd passes will write 0.
6806 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
6807 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
6809 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
6811 * This error indicates that there was some sort of problem with
6812 * the BDs for the packet that was found after part of the
6813 * packet was already placed. The packet should be treated as
6816 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
6818 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6819 /* No buffer error */
6820 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6821 (UINT32_C(0x0) << 1)
6823 * This error occurs when there is a fatal HW problem in
6824 * the chip only. It indicates that there were not
6825 * BDs on chip but that there was adequate reservation.
6826 * provided by the TPA block.
6828 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6829 (UINT32_C(0x2) << 1)
6832 * BDs were not formatted correctly.
6834 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6835 (UINT32_C(0x3) << 1)
6837 * This error occurs when TPA block was not configured to
6838 * reserve adequate BDs for TPA operations on this RX
6839 * ring. All data for the TPA operation was not placed.
6841 * This error can also be generated when the number of
6842 * segments is not programmed correctly in TPA and the
6843 * 33 total aggregation buffers allowed for the TPA
6844 * operation has been exceeded.
6846 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6847 (UINT32_C(0x4) << 1)
6850 * There was a bad_format error on the previous operation
6852 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6853 (UINT32_C(0x5) << 1)
6854 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6855 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6858 * This is the opaque value that was completed for the TPA start
6859 * completion that corresponds to this TPA end completion.
6861 uint32_t start_opaque;
6865 * This TPA completion structure is used on devices where the
6866 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6868 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
6869 struct rx_tpa_v2_abuf_cmpl {
6872 * This field indicates the exact type of the completion.
6873 * By convention, the LSB identifies the length of the
6874 * record in 16B units. Even values indicate 16B
6875 * records. Odd values indicate 32B
6878 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
6879 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
6881 * RX TPA Aggregation Buffer completion :
6882 * Completion of an L2 aggregation buffer in support of
6883 * TPA packet completion. Length = 16B
6885 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
6886 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
6887 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
6889 * This is the length of the data for the packet stored in this
6890 * aggregation buffer identified by the opaque value. This does not
6891 * include the length of any
6892 * data placed in other aggregation BDs or in the packet or buffer
6893 * BDs. This length does not include any space added due to
6894 * hdr_offset register during HDS placement mode.
6898 * This is a copy of the opaque field from the RX BD this aggregation
6899 * buffer corresponds to.
6904 * This value is written by the NIC such that it will be different
6905 * for each pass through the completion queue. The even passes
6906 * will write 1. The odd passes will write 0.
6908 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
6910 * This is the aggregation ID that the completion is associated with. Use
6911 * this number to correlate the TPA agg completion with the TPA start
6912 * completion and the TPA end completion.
6918 /* rx_abuf_cmpl (size:128b/16B) */
6919 struct rx_abuf_cmpl {
6922 * This field indicates the exact type of the completion.
6923 * By convention, the LSB identifies the length of the
6924 * record in 16B units. Even values indicate 16B
6925 * records. Odd values indicate 32B
6928 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
6929 #define RX_ABUF_CMPL_TYPE_SFT 0
6931 * RX Aggregation Buffer completion :
6932 * Completion of an L2 aggregation buffer in support of
6933 * TPA, HDS, or Jumbo packet completion. Length = 16B
6935 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
6936 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
6938 * This is the length of the data for the packet stored in this
6939 * aggregation buffer identified by the opaque value. This does not
6940 * include the length of any
6941 * data placed in other aggregation BDs or in the packet or buffer
6942 * BDs. This length does not include any space added due to
6943 * hdr_offset register during HDS placement mode.
6947 * This is a copy of the opaque field from the RX BD this aggregation
6948 * buffer corresponds to.
6953 * This value is written by the NIC such that it will be different
6954 * for each pass through the completion queue. The even passes
6955 * will write 1. The odd passes will write 0.
6957 #define RX_ABUF_CMPL_V UINT32_C(0x1)
6958 /* unused3 is 32 b */
6962 /* VEE FLUSH Completion Record (16 bytes) */
6963 /* vee_flush (size:128b/16B) */
6965 uint32_t downstream_path_type;
6967 * This field indicates the exact type of the completion.
6968 * By convention, the LSB identifies the length of the
6969 * record in 16B units. Even values indicate 16B
6970 * records. Odd values indicate 32B
6973 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
6974 #define VEE_FLUSH_TYPE_SFT 0
6976 * VEE Flush Completion:
6977 * This completion is inserted manually by the Primate and processed
6978 * by the VEE hardware to ensure that all completions on a VEE
6979 * function have been processed by the VEE hardware before FLR
6980 * process is completed.
6982 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
6983 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
6984 /* downstream_path is 1 b */
6985 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
6986 /* This completion is associated with VEE Transmit */
6987 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
6988 /* This completion is associated with VEE Receive */
6989 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
6990 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
6992 * This is an opaque value that is passed through the completion
6993 * to the VEE handler SW and is used to indicate what VEE VQ or
6994 * function has completed FLR processing.
6999 * This value is written by the NIC such that it will be different
7000 * for each pass through the completion queue. The even passes will
7001 * write 1. The odd passes will write 0.
7003 #define VEE_FLUSH_V UINT32_C(0x1)
7004 /* unused3 is 32 b */
7008 /* eject_cmpl (size:128b/16B) */
7012 * This field indicates the exact type of the completion.
7013 * By convention, the LSB identifies the length of the
7014 * record in 16B units. Even values indicate 16B
7015 * records. Odd values indicate 32B
7018 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
7019 #define EJECT_CMPL_TYPE_SFT 0
7021 * Statistics Ejection Completion:
7022 * Completion of statistics data ejection buffer.
7025 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
7026 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
7027 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7028 #define EJECT_CMPL_FLAGS_SFT 6
7030 * When this bit is '1', it indicates a packet that has an
7031 * error of some type. Type of error is indicated in
7034 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
7036 * This is the length of the statistics data stored in this
7041 * This is a copy of the opaque field from the RX BD this ejection
7042 * buffer corresponds to.
7047 * This value is written by the NIC such that it will be different
7048 * for each pass through the completion queue. The even passes
7049 * will write 1. The odd passes will write 0.
7051 #define EJECT_CMPL_V UINT32_C(0x1)
7052 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7053 #define EJECT_CMPL_ERRORS_SFT 1
7055 * This error indicates that there was some sort of problem with
7056 * the BDs for statistics ejection. The statistics ejection should
7057 * be treated as invalid
7059 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7060 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7061 /* No buffer error */
7062 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7063 (UINT32_C(0x0) << 1)
7066 * Statistics did not fit into aggregation buffer provided.
7068 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7069 (UINT32_C(0x1) << 1)
7072 * BDs were not formatted correctly.
7074 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7075 (UINT32_C(0x3) << 1)
7078 * There was a bad_format error on the previous operation
7080 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7081 (UINT32_C(0x5) << 1)
7082 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
7083 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7084 /* reserved16 is 16 b */
7085 uint16_t reserved16;
7086 /* unused3 is 32 b */
7090 /* hwrm_cmpl (size:128b/16B) */
7094 * This field indicates the exact type of the completion.
7095 * By convention, the LSB identifies the length of the
7096 * record in 16B units. Even values indicate 16B
7097 * records. Odd values indicate 32B
7100 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
7101 #define HWRM_CMPL_TYPE_SFT 0
7103 * HWRM Command Completion:
7104 * Completion of an HWRM command.
7106 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
7107 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
7108 /* This is the sequence_id of the HWRM command that has completed. */
7109 uint16_t sequence_id;
7110 /* unused2 is 32 b */
7114 * This value is written by the NIC such that it will be different
7115 * for each pass through the completion queue. The even passes
7116 * will write 1. The odd passes will write 0.
7118 #define HWRM_CMPL_V UINT32_C(0x1)
7119 /* unused4 is 32 b */
7123 /* hwrm_fwd_req_cmpl (size:128b/16B) */
7124 struct hwrm_fwd_req_cmpl {
7126 * This field indicates the exact type of the completion.
7127 * By convention, the LSB identifies the length of the
7128 * record in 16B units. Even values indicate 16B
7129 * records. Odd values indicate 32B
7132 uint16_t req_len_type;
7134 * This field indicates the exact type of the completion.
7135 * By convention, the LSB identifies the length of the
7136 * record in 16B units. Even values indicate 16B
7137 * records. Odd values indicate 32B
7140 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
7141 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
7142 /* Forwarded HWRM Request */
7143 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
7144 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
7145 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
7146 /* Length of forwarded request in bytes. */
7147 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
7148 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
7150 * Source ID of this request.
7151 * Typically used in forwarding requests and responses.
7152 * 0x0 - 0xFFF8 - Used for function ids
7153 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7157 /* unused1 is 32 b */
7159 /* Address of forwarded request. */
7160 uint32_t req_buf_addr_v[2];
7162 * This value is written by the NIC such that it will be different
7163 * for each pass through the completion queue. The even passes
7164 * will write 1. The odd passes will write 0.
7166 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
7167 /* Address of forwarded request. */
7168 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7169 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
7172 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
7173 struct hwrm_fwd_resp_cmpl {
7176 * This field indicates the exact type of the completion.
7177 * By convention, the LSB identifies the length of the
7178 * record in 16B units. Even values indicate 16B
7179 * records. Odd values indicate 32B
7182 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
7183 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
7184 /* Forwarded HWRM Response */
7185 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
7186 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
7187 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
7189 * Source ID of this response.
7190 * Typically used in forwarding requests and responses.
7191 * 0x0 - 0xFFF8 - Used for function ids
7192 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7196 /* Length of forwarded response in bytes. */
7198 /* unused2 is 16 b */
7200 /* Address of forwarded request. */
7201 uint32_t resp_buf_addr_v[2];
7203 * This value is written by the NIC such that it will be different
7204 * for each pass through the completion queue. The even passes
7205 * will write 1. The odd passes will write 0.
7207 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
7208 /* Address of forwarded request. */
7209 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7210 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
7213 /* hwrm_async_event_cmpl (size:128b/16B) */
7214 struct hwrm_async_event_cmpl {
7217 * This field indicates the exact type of the completion.
7218 * By convention, the LSB identifies the length of the
7219 * record in 16B units. Even values indicate 16B
7220 * records. Odd values indicate 32B
7223 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
7224 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
7225 /* HWRM Asynchronous Event Information */
7226 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
7227 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
7228 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
7229 /* Identifiers of events. */
7231 /* Link status changed */
7232 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
7234 /* Link MTU changed */
7235 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
7237 /* Link speed changed */
7238 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
7240 /* DCB Configuration changed */
7241 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
7243 /* Port connection not allowed */
7244 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7246 /* Link speed configuration was not allowed */
7247 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7249 /* Link speed configuration change */
7250 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7252 /* Port PHY configuration change */
7253 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
7255 /* Reset notification to clients */
7256 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
7258 /* Master function selection event */
7259 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
7262 * An event signifying that a ring has been disabled by
7265 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
7267 /* Function driver unloaded */
7268 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
7270 /* Function driver loaded */
7271 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
7273 /* Function FLR related processing has completed */
7274 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7276 /* PF driver unloaded */
7277 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
7279 /* PF driver loaded */
7280 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
7282 /* VF Function Level Reset (FLR) */
7283 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
7285 /* VF MAC Address Change */
7286 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
7288 /* PF-VF communication channel status change. */
7289 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7291 /* VF Configuration Change */
7292 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
7294 /* LLFC/PFC Configuration Change */
7295 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
7297 /* Default VNIC Configuration Change */
7298 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
7301 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
7304 * A debug notification being posted to the driver. These
7305 * notifications are purely for diagnostic purpose and should not be
7306 * used for functional purpose. The driver is not supposed to act
7307 * on these messages except to log/record it.
7309 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
7312 * An EEM flow cached memory flush for all flows request event being
7313 * posted to the PF driver.
7315 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7318 * An EEM flow cache memory flush completion event being posted to the
7319 * firmware by the PF driver. This is indication that host EEM flush
7320 * has completed by the PF.
7322 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7325 * A tcp flag action change event being posted to the PF or trusted VF
7326 * driver by the firmware. The PF or trusted VF driver should query
7327 * the firmware for the new TCP flag action update after receiving
7330 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7333 * An EEM flow active event being posted to the PF or trusted VF driver
7334 * by the firmware. The PF or trusted VF driver should update the
7335 * flow's aging timer after receiving this async event.
7337 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
7340 * A eem cfg change event being posted to the trusted VF driver by the
7341 * firmware if the parent PF EEM configuration changed.
7343 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
7347 * TFLIB unique default VNIC Configuration Change
7349 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
7353 * TFLIB unique link status changed
7355 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
7358 * An event signifying completion for HWRM_FW_STATE_QUIESCE
7359 * (completion, timeout, or error)
7361 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
7364 * An event signifying a HWRM command is in progress and its
7365 * response will be deferred. This event is used on crypto controllers
7368 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
7371 * An event signifying that a PFC WatchDog configuration
7372 * has changed on any port / cos.
7374 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
7376 /* Maximum Registrable event id. */
7377 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
7380 * A trace log message. This contains firmware trace logs string
7381 * embedded in the asynchronous message. This is an experimental
7382 * event, not meant for production use at this time.
7384 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
7387 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
7389 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
7390 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
7391 /* Event specific data */
7392 uint32_t event_data2;
7395 * This value is written by the NIC such that it will be different
7396 * for each pass through the completion queue. The even passes
7397 * will write 1. The odd passes will write 0.
7399 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
7401 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
7402 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
7403 /* 8-lsb timestamp from POR (100-msec resolution) */
7404 uint8_t timestamp_lo;
7405 /* 16-lsb timestamp from POR (100-msec resolution) */
7406 uint16_t timestamp_hi;
7407 /* Event specific data */
7408 uint32_t event_data1;
7411 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
7412 struct hwrm_async_event_cmpl_link_status_change {
7415 * This field indicates the exact type of the completion.
7416 * By convention, the LSB identifies the length of the
7417 * record in 16B units. Even values indicate 16B
7418 * records. Odd values indicate 32B
7421 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
7423 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
7424 /* HWRM Asynchronous Event Information */
7425 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7427 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
7428 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7429 /* Identifiers of events. */
7431 /* Link status changed */
7432 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
7434 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
7435 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
7436 /* Event specific data */
7437 uint32_t event_data2;
7440 * This value is written by the NIC such that it will be different
7441 * for each pass through the completion queue. The even passes
7442 * will write 1. The odd passes will write 0.
7444 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
7447 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
7449 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
7450 /* 8-lsb timestamp from POR (100-msec resolution) */
7451 uint8_t timestamp_lo;
7452 /* 16-lsb timestamp from POR (100-msec resolution) */
7453 uint16_t timestamp_hi;
7454 /* Event specific data */
7455 uint32_t event_data1;
7456 /* Indicates link status change */
7457 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
7460 * If this bit set to 0, then it indicates that the link
7461 * was up and it went down.
7463 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
7466 * If this bit is set to 1, then it indicates that the link
7467 * was down and it went up.
7469 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
7471 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
7472 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
7473 /* Indicates the physical port this link status change occur */
7474 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
7476 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
7479 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7481 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7483 /* Indicates the physical function this event occurred on. */
7484 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
7486 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
7490 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
7491 struct hwrm_async_event_cmpl_link_mtu_change {
7494 * This field indicates the exact type of the completion.
7495 * By convention, the LSB identifies the length of the
7496 * record in 16B units. Even values indicate 16B
7497 * records. Odd values indicate 32B
7500 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
7502 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
7503 /* HWRM Asynchronous Event Information */
7504 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7506 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
7507 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
7508 /* Identifiers of events. */
7510 /* Link MTU changed */
7511 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
7513 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
7514 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
7515 /* Event specific data */
7516 uint32_t event_data2;
7519 * This value is written by the NIC such that it will be different
7520 * for each pass through the completion queue. The even passes
7521 * will write 1. The odd passes will write 0.
7523 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
7525 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
7527 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
7528 /* 8-lsb timestamp from POR (100-msec resolution) */
7529 uint8_t timestamp_lo;
7530 /* 16-lsb timestamp from POR (100-msec resolution) */
7531 uint16_t timestamp_hi;
7532 /* Event specific data */
7533 uint32_t event_data1;
7534 /* The new MTU of the link in bytes. */
7535 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
7537 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
7540 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
7541 struct hwrm_async_event_cmpl_link_speed_change {
7544 * This field indicates the exact type of the completion.
7545 * By convention, the LSB identifies the length of the
7546 * record in 16B units. Even values indicate 16B
7547 * records. Odd values indicate 32B
7550 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
7552 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
7553 /* HWRM Asynchronous Event Information */
7554 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7556 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
7557 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
7558 /* Identifiers of events. */
7560 /* Link speed changed */
7561 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
7563 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
7564 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
7565 /* Event specific data */
7566 uint32_t event_data2;
7569 * This value is written by the NIC such that it will be different
7570 * for each pass through the completion queue. The even passes
7571 * will write 1. The odd passes will write 0.
7573 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
7576 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
7578 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
7579 /* 8-lsb timestamp from POR (100-msec resolution) */
7580 uint8_t timestamp_lo;
7581 /* 16-lsb timestamp from POR (100-msec resolution) */
7582 uint16_t timestamp_hi;
7583 /* Event specific data */
7584 uint32_t event_data1;
7586 * When this bit is '1', the link was forced to the
7587 * force_link_speed value.
7589 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
7591 /* The new link speed in 100 Mbps units. */
7592 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
7594 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
7596 /* 100Mb link speed */
7597 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
7598 (UINT32_C(0x1) << 1)
7599 /* 1Gb link speed */
7600 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
7601 (UINT32_C(0xa) << 1)
7602 /* 2Gb link speed */
7603 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
7604 (UINT32_C(0x14) << 1)
7605 /* 25Gb link speed */
7606 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
7607 (UINT32_C(0x19) << 1)
7608 /* 10Gb link speed */
7609 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
7610 (UINT32_C(0x64) << 1)
7611 /* 20Mb link speed */
7612 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
7613 (UINT32_C(0xc8) << 1)
7614 /* 25Gb link speed */
7615 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
7616 (UINT32_C(0xfa) << 1)
7617 /* 40Gb link speed */
7618 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
7619 (UINT32_C(0x190) << 1)
7620 /* 50Gb link speed */
7621 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
7622 (UINT32_C(0x1f4) << 1)
7623 /* 100Gb link speed */
7624 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
7625 (UINT32_C(0x3e8) << 1)
7626 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
7627 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
7629 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7630 UINT32_C(0xffff0000)
7631 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7635 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
7636 struct hwrm_async_event_cmpl_dcb_config_change {
7639 * This field indicates the exact type of the completion.
7640 * By convention, the LSB identifies the length of the
7641 * record in 16B units. Even values indicate 16B
7642 * records. Odd values indicate 32B
7645 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
7647 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
7648 /* HWRM Asynchronous Event Information */
7649 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7651 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
7652 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7653 /* Identifiers of events. */
7655 /* DCB Configuration changed */
7656 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
7658 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
7659 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
7660 /* Event specific data */
7661 uint32_t event_data2;
7662 /* ETS configuration change */
7663 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
7665 /* PFC configuration change */
7666 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
7668 /* APP configuration change */
7669 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
7673 * This value is written by the NIC such that it will be different
7674 * for each pass through the completion queue. The even passes
7675 * will write 1. The odd passes will write 0.
7677 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
7680 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
7682 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
7683 /* 8-lsb timestamp from POR (100-msec resolution) */
7684 uint8_t timestamp_lo;
7685 /* 16-lsb timestamp from POR (100-msec resolution) */
7686 uint16_t timestamp_hi;
7687 /* Event specific data */
7688 uint32_t event_data1;
7690 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7692 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7694 /* Priority recommended for RoCE traffic */
7695 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
7697 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
7700 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
7701 (UINT32_C(0xff) << 16)
7702 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
7703 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
7704 /* Priority recommended for L2 traffic */
7705 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
7706 UINT32_C(0xff000000)
7707 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
7710 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
7711 (UINT32_C(0xff) << 24)
7712 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
7713 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
7716 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
7717 struct hwrm_async_event_cmpl_port_conn_not_allowed {
7720 * This field indicates the exact type of the completion.
7721 * By convention, the LSB identifies the length of the
7722 * record in 16B units. Even values indicate 16B
7723 * records. Odd values indicate 32B
7726 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
7728 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
7730 /* HWRM Asynchronous Event Information */
7731 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7733 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
7734 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7735 /* Identifiers of events. */
7737 /* Port connection not allowed */
7738 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7740 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
7741 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
7742 /* Event specific data */
7743 uint32_t event_data2;
7746 * This value is written by the NIC such that it will be different
7747 * for each pass through the completion queue. The even passes
7748 * will write 1. The odd passes will write 0.
7750 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
7753 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
7755 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
7756 /* 8-lsb timestamp from POR (100-msec resolution) */
7757 uint8_t timestamp_lo;
7758 /* 16-lsb timestamp from POR (100-msec resolution) */
7759 uint16_t timestamp_hi;
7760 /* Event specific data */
7761 uint32_t event_data1;
7763 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7765 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7768 * This value indicates the current port level enforcement policy
7769 * for the optics module when there is an optical module mismatch
7770 * and port is not connected.
7772 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
7774 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
7776 /* No enforcement */
7777 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
7778 (UINT32_C(0x0) << 16)
7779 /* Disable Transmit side Laser. */
7780 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
7781 (UINT32_C(0x1) << 16)
7782 /* Raise a warning message. */
7783 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
7784 (UINT32_C(0x2) << 16)
7785 /* Power down the module. */
7786 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
7787 (UINT32_C(0x3) << 16)
7788 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
7789 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
7792 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
7793 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
7796 * This field indicates the exact type of the completion.
7797 * By convention, the LSB identifies the length of the
7798 * record in 16B units. Even values indicate 16B
7799 * records. Odd values indicate 32B
7802 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
7804 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
7806 /* HWRM Asynchronous Event Information */
7807 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7809 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
7810 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7811 /* Identifiers of events. */
7813 /* Link speed configuration was not allowed */
7814 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7816 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
7817 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
7818 /* Event specific data */
7819 uint32_t event_data2;
7822 * This value is written by the NIC such that it will be different
7823 * for each pass through the completion queue. The even passes
7824 * will write 1. The odd passes will write 0.
7826 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
7829 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
7831 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
7832 /* 8-lsb timestamp from POR (100-msec resolution) */
7833 uint8_t timestamp_lo;
7834 /* 16-lsb timestamp from POR (100-msec resolution) */
7835 uint16_t timestamp_hi;
7836 /* Event specific data */
7837 uint32_t event_data1;
7839 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7841 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7845 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
7846 struct hwrm_async_event_cmpl_link_speed_cfg_change {
7849 * This field indicates the exact type of the completion.
7850 * By convention, the LSB identifies the length of the
7851 * record in 16B units. Even values indicate 16B
7852 * records. Odd values indicate 32B
7855 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
7857 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
7859 /* HWRM Asynchronous Event Information */
7860 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7862 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
7863 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7864 /* Identifiers of events. */
7866 /* Link speed configuration change */
7867 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7869 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
7870 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
7871 /* Event specific data */
7872 uint32_t event_data2;
7875 * This value is written by the NIC such that it will be different
7876 * for each pass through the completion queue. The even passes
7877 * will write 1. The odd passes will write 0.
7879 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
7882 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
7884 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
7885 /* 8-lsb timestamp from POR (100-msec resolution) */
7886 uint8_t timestamp_lo;
7887 /* 16-lsb timestamp from POR (100-msec resolution) */
7888 uint16_t timestamp_hi;
7889 /* Event specific data */
7890 uint32_t event_data1;
7892 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7894 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7897 * If set to 1, it indicates that the supported link speeds
7898 * configuration on the port has changed.
7899 * If set to 0, then there is no change in supported link speeds
7902 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
7905 * If set to 1, it indicates that the link speed configuration
7906 * on the port has become illegal or invalid.
7907 * If set to 0, then the link speed configuration on the port is
7910 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
7914 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
7915 struct hwrm_async_event_cmpl_port_phy_cfg_change {
7918 * This field indicates the exact type of the completion.
7919 * By convention, the LSB identifies the length of the
7920 * record in 16B units. Even values indicate 16B
7921 * records. Odd values indicate 32B
7924 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
7926 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
7928 /* HWRM Asynchronous Event Information */
7929 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7931 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
7932 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7933 /* Identifiers of events. */
7935 /* Port PHY configuration change */
7936 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
7938 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
7939 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
7940 /* Event specific data */
7941 uint32_t event_data2;
7944 * This value is written by the NIC such that it will be different
7945 * for each pass through the completion queue. The even passes
7946 * will write 1. The odd passes will write 0.
7948 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
7951 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
7953 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
7954 /* 8-lsb timestamp from POR (100-msec resolution) */
7955 uint8_t timestamp_lo;
7956 /* 16-lsb timestamp from POR (100-msec resolution) */
7957 uint16_t timestamp_hi;
7958 /* Event specific data */
7959 uint32_t event_data1;
7961 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7963 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7966 * If set to 1, it indicates that the FEC
7967 * configuration on the port has changed.
7968 * If set to 0, then there is no change in FEC configuration.
7970 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
7973 * If set to 1, it indicates that the EEE configuration
7974 * on the port has changed.
7975 * If set to 0, then there is no change in EEE configuration
7978 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
7981 * If set to 1, it indicates that the pause configuration
7982 * on the PHY has changed.
7983 * If set to 0, then there is no change in the pause
7984 * configuration on the PHY.
7986 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
7990 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
7991 struct hwrm_async_event_cmpl_reset_notify {
7994 * This field indicates the exact type of the completion.
7995 * By convention, the LSB identifies the length of the
7996 * record in 16B units. Even values indicate 16B
7997 * records. Odd values indicate 32B
8000 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
8002 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
8003 /* HWRM Asynchronous Event Information */
8004 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
8006 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
8007 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
8008 /* Identifiers of events. */
8010 /* Notify clients of imminent reset. */
8011 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
8013 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
8014 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
8015 /* Event specific data. The data is for internal debug use only. */
8016 uint32_t event_data2;
8019 * This value is written by the NIC such that it will be different
8020 * for each pass through the completion queue. The even passes
8021 * will write 1. The odd passes will write 0.
8023 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
8025 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
8026 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
8028 * 8-lsb timestamp (100-msec resolution)
8029 * The Minimum time required for the Firmware readiness after sending this
8030 * notification to the driver instances.
8032 uint8_t timestamp_lo;
8034 * 16-lsb timestamp (100-msec resolution)
8035 * The Maximum Firmware Reset bail out value in the order of 100
8036 * milli seconds. The driver instances will use this value to re-initiate the
8037 * registration process again if the core firmware didn’t set the ready
8040 uint16_t timestamp_hi;
8041 /* Event specific data */
8042 uint32_t event_data1;
8043 /* Indicates driver action requested */
8044 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
8046 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
8049 * If set to 1, it indicates that the l2 client should
8050 * stop sending in band traffic to Nitro.
8051 * if set to 0, there is no change in L2 client behavior.
8053 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
8056 * If set to 1, it indicates that the L2 client should
8057 * bring down the interface.
8058 * If set to 0, then there is no change in L2 client behavior.
8060 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
8062 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
8063 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
8064 /* Indicates reason for reset. */
8065 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
8067 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
8069 /* A management client has requested reset. */
8070 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
8071 (UINT32_C(0x1) << 8)
8072 /* A fatal firmware exception has occurred. */
8073 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
8074 (UINT32_C(0x2) << 8)
8075 /* A non-fatal firmware exception has occurred. */
8076 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
8077 (UINT32_C(0x3) << 8)
8078 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
8079 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
8081 * Minimum time before driver should attempt access - units 100ms ticks.
8084 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
8085 UINT32_C(0xffff0000)
8086 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
8090 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
8091 struct hwrm_async_event_cmpl_error_recovery {
8094 * This field indicates the exact type of the completion.
8095 * By convention, the LSB identifies the length of the
8096 * record in 16B units. Even values indicate 16B
8097 * records. Odd values indicate 32B
8100 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
8102 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
8103 /* HWRM Asynchronous Event Information */
8104 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
8106 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
8107 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
8108 /* Identifiers of events. */
8111 * This async notification message can be used for selecting or
8112 * deselecting master function for error recovery,
8113 * and to communicate to all the functions whether error recovery
8114 * was enabled/disabled.
8116 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
8118 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
8119 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
8120 /* Event specific data */
8121 uint32_t event_data2;
8124 * This value is written by the NIC such that it will be different
8125 * for each pass through the completion queue. The even passes
8126 * will write 1. The odd passes will write 0.
8128 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
8130 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
8131 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
8132 /* 8-lsb timestamp (100-msec resolution) */
8133 uint8_t timestamp_lo;
8134 /* 16-lsb timestamp (100-msec resolution) */
8135 uint16_t timestamp_hi;
8136 /* Event specific data */
8137 uint32_t event_data1;
8138 /* Indicates driver action requested */
8139 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
8141 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
8144 * If set to 1, this function is selected as Master function.
8145 * This function has responsibility to do 'chip reset' when it
8146 * detects a fatal error. If set to 0, master function functionality
8147 * is disabled on this function.
8149 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
8152 * If set to 1, error recovery is enabled.
8153 * If set to 0, error recovery is disabled.
8155 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
8159 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
8160 struct hwrm_async_event_cmpl_ring_monitor_msg {
8163 * This field indicates the exact type of the completion.
8164 * By convention, the LSB identifies the length of the
8165 * record in 16B units. Even values indicate 16B
8166 * records. Odd values indicate 32B
8169 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
8171 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
8172 /* HWRM Asynchronous Event Information */
8173 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
8175 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
8176 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
8177 /* Identifiers of events. */
8179 /* Ring Monitor Message. */
8180 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
8182 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
8183 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
8184 /* Event specific data */
8185 uint32_t event_data2;
8186 /* Type of Ring disabled. */
8187 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
8189 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
8191 /* tx ring disabled. */
8192 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
8194 /* rx ring disabled. */
8195 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
8197 /* cmpl ring disabled. */
8198 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
8200 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
8201 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
8204 * This value is written by the NIC such that it will be different
8205 * for each pass through the completion queue. The even passes
8206 * will write 1. The odd passes will write 0.
8208 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
8210 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
8212 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
8213 /* 8-lsb timestamp from POR (100-msec resolution) */
8214 uint8_t timestamp_lo;
8215 /* 16-lsb timestamp from POR (100-msec resolution) */
8216 uint16_t timestamp_hi;
8218 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
8219 * then this field will indicate the ring id.
8221 uint32_t event_data1;
8224 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
8225 struct hwrm_async_event_cmpl_func_drvr_unload {
8228 * This field indicates the exact type of the completion.
8229 * By convention, the LSB identifies the length of the
8230 * record in 16B units. Even values indicate 16B
8231 * records. Odd values indicate 32B
8234 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
8236 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
8237 /* HWRM Asynchronous Event Information */
8238 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8240 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
8241 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8242 /* Identifiers of events. */
8244 /* Function driver unloaded */
8245 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
8247 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
8248 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
8249 /* Event specific data */
8250 uint32_t event_data2;
8253 * This value is written by the NIC such that it will be different
8254 * for each pass through the completion queue. The even passes
8255 * will write 1. The odd passes will write 0.
8257 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
8259 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
8261 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
8262 /* 8-lsb timestamp from POR (100-msec resolution) */
8263 uint8_t timestamp_lo;
8264 /* 16-lsb timestamp from POR (100-msec resolution) */
8265 uint16_t timestamp_hi;
8266 /* Event specific data */
8267 uint32_t event_data1;
8269 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8271 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
8275 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
8276 struct hwrm_async_event_cmpl_func_drvr_load {
8279 * This field indicates the exact type of the completion.
8280 * By convention, the LSB identifies the length of the
8281 * record in 16B units. Even values indicate 16B
8282 * records. Odd values indicate 32B
8285 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
8287 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
8288 /* HWRM Asynchronous Event Information */
8289 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8291 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
8292 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8293 /* Identifiers of events. */
8295 /* Function driver loaded */
8296 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
8298 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
8299 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
8300 /* Event specific data */
8301 uint32_t event_data2;
8304 * This value is written by the NIC such that it will be different
8305 * for each pass through the completion queue. The even passes
8306 * will write 1. The odd passes will write 0.
8308 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
8310 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8311 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
8312 /* 8-lsb timestamp from POR (100-msec resolution) */
8313 uint8_t timestamp_lo;
8314 /* 16-lsb timestamp from POR (100-msec resolution) */
8315 uint16_t timestamp_hi;
8316 /* Event specific data */
8317 uint32_t event_data1;
8319 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8324 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
8325 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
8328 * This field indicates the exact type of the completion.
8329 * By convention, the LSB identifies the length of the
8330 * record in 16B units. Even values indicate 16B
8331 * records. Odd values indicate 32B
8334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
8336 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
8338 /* HWRM Asynchronous Event Information */
8339 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
8341 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
8342 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
8343 /* Identifiers of events. */
8345 /* Function FLR related processing has completed */
8346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
8348 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
8349 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
8350 /* Event specific data */
8351 uint32_t event_data2;
8354 * This value is written by the NIC such that it will be different
8355 * for each pass through the completion queue. The even passes
8356 * will write 1. The odd passes will write 0.
8358 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
8361 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
8363 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
8364 /* 8-lsb timestamp from POR (100-msec resolution) */
8365 uint8_t timestamp_lo;
8366 /* 16-lsb timestamp from POR (100-msec resolution) */
8367 uint16_t timestamp_hi;
8368 /* Event specific data */
8369 uint32_t event_data1;
8371 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
8373 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
8377 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
8378 struct hwrm_async_event_cmpl_pf_drvr_unload {
8381 * This field indicates the exact type of the completion.
8382 * By convention, the LSB identifies the length of the
8383 * record in 16B units. Even values indicate 16B
8384 * records. Odd values indicate 32B
8387 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
8389 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
8390 /* HWRM Asynchronous Event Information */
8391 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8393 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
8394 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8395 /* Identifiers of events. */
8397 /* PF driver unloaded */
8398 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
8400 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
8401 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
8402 /* Event specific data */
8403 uint32_t event_data2;
8406 * This value is written by the NIC such that it will be different
8407 * for each pass through the completion queue. The even passes
8408 * will write 1. The odd passes will write 0.
8410 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
8412 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
8413 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
8414 /* 8-lsb timestamp from POR (100-msec resolution) */
8415 uint8_t timestamp_lo;
8416 /* 16-lsb timestamp from POR (100-msec resolution) */
8417 uint16_t timestamp_hi;
8418 /* Event specific data */
8419 uint32_t event_data1;
8421 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8423 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
8424 /* Indicates the physical port this pf belongs to */
8425 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
8427 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
8430 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
8431 struct hwrm_async_event_cmpl_pf_drvr_load {
8434 * This field indicates the exact type of the completion.
8435 * By convention, the LSB identifies the length of the
8436 * record in 16B units. Even values indicate 16B
8437 * records. Odd values indicate 32B
8440 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
8442 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
8443 /* HWRM Asynchronous Event Information */
8444 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8446 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
8447 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8448 /* Identifiers of events. */
8450 /* PF driver loaded */
8451 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
8453 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
8454 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
8455 /* Event specific data */
8456 uint32_t event_data2;
8459 * This value is written by the NIC such that it will be different
8460 * for each pass through the completion queue. The even passes
8461 * will write 1. The odd passes will write 0.
8463 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
8465 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8466 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
8467 /* 8-lsb timestamp from POR (100-msec resolution) */
8468 uint8_t timestamp_lo;
8469 /* 16-lsb timestamp from POR (100-msec resolution) */
8470 uint16_t timestamp_hi;
8471 /* Event specific data */
8472 uint32_t event_data1;
8474 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8476 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8477 /* Indicates the physical port this pf belongs to */
8478 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
8480 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
8483 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
8484 struct hwrm_async_event_cmpl_vf_flr {
8487 * This field indicates the exact type of the completion.
8488 * By convention, the LSB identifies the length of the
8489 * record in 16B units. Even values indicate 16B
8490 * records. Odd values indicate 32B
8493 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
8495 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
8496 /* HWRM Asynchronous Event Information */
8497 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
8499 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
8500 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
8501 /* Identifiers of events. */
8503 /* VF Function Level Reset (FLR) */
8504 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
8505 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
8506 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
8507 /* Event specific data */
8508 uint32_t event_data2;
8511 * This value is written by the NIC such that it will be different
8512 * for each pass through the completion queue. The even passes
8513 * will write 1. The odd passes will write 0.
8515 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
8517 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
8518 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
8519 /* 8-lsb timestamp from POR (100-msec resolution) */
8520 uint8_t timestamp_lo;
8521 /* 16-lsb timestamp from POR (100-msec resolution) */
8522 uint16_t timestamp_hi;
8523 /* Event specific data */
8524 uint32_t event_data1;
8526 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
8528 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
8529 /* Indicates the physical function this event occurred on. */
8530 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
8532 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
8535 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
8536 struct hwrm_async_event_cmpl_vf_mac_addr_change {
8539 * This field indicates the exact type of the completion.
8540 * By convention, the LSB identifies the length of the
8541 * record in 16B units. Even values indicate 16B
8542 * records. Odd values indicate 32B
8545 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
8547 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
8548 /* HWRM Asynchronous Event Information */
8549 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8551 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
8552 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
8553 /* Identifiers of events. */
8555 /* VF MAC Address Change */
8556 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
8558 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
8559 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
8560 /* Event specific data */
8561 uint32_t event_data2;
8564 * This value is written by the NIC such that it will be different
8565 * for each pass through the completion queue. The even passes
8566 * will write 1. The odd passes will write 0.
8568 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
8571 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
8573 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
8574 /* 8-lsb timestamp from POR (100-msec resolution) */
8575 uint8_t timestamp_lo;
8576 /* 16-lsb timestamp from POR (100-msec resolution) */
8577 uint16_t timestamp_hi;
8578 /* Event specific data */
8579 uint32_t event_data1;
8581 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
8583 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
8587 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
8588 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
8591 * This field indicates the exact type of the completion.
8592 * By convention, the LSB identifies the length of the
8593 * record in 16B units. Even values indicate 16B
8594 * records. Odd values indicate 32B
8597 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
8599 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
8601 /* HWRM Asynchronous Event Information */
8602 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8604 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
8605 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
8606 /* Identifiers of events. */
8608 /* PF-VF communication channel status change. */
8609 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
8611 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
8612 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
8613 /* Event specific data */
8614 uint32_t event_data2;
8617 * This value is written by the NIC such that it will be different
8618 * for each pass through the completion queue. The even passes
8619 * will write 1. The odd passes will write 0.
8621 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
8624 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
8626 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
8627 /* 8-lsb timestamp from POR (100-msec resolution) */
8628 uint8_t timestamp_lo;
8629 /* 16-lsb timestamp from POR (100-msec resolution) */
8630 uint16_t timestamp_hi;
8631 /* Event specific data */
8632 uint32_t event_data1;
8634 * If this bit is set to 1, then it indicates that the PF-VF
8635 * communication was lost and it is established.
8636 * If this bit set to 0, then it indicates that the PF-VF
8637 * communication was established and it is lost.
8639 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
8643 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
8644 struct hwrm_async_event_cmpl_vf_cfg_change {
8647 * This field indicates the exact type of the completion.
8648 * By convention, the LSB identifies the length of the
8649 * record in 16B units. Even values indicate 16B
8650 * records. Odd values indicate 32B
8653 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
8655 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
8656 /* HWRM Asynchronous Event Information */
8657 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8659 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
8660 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8661 /* Identifiers of events. */
8663 /* VF Configuration Change */
8664 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
8666 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
8667 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
8668 /* Event specific data */
8669 uint32_t event_data2;
8672 * This value is written by the NIC such that it will be different
8673 * for each pass through the completion queue. The even passes
8674 * will write 1. The odd passes will write 0.
8676 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
8678 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
8679 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
8680 /* 8-lsb timestamp from POR (100-msec resolution) */
8681 uint8_t timestamp_lo;
8682 /* 16-lsb timestamp from POR (100-msec resolution) */
8683 uint16_t timestamp_hi;
8685 * Each flag provided in this field indicates a specific VF
8686 * configuration change. At least one of these flags shall be set to 1
8687 * when an asynchronous event completion of this type is provided
8690 uint32_t event_data1;
8692 * If this bit is set to 1, then the value of MTU
8693 * was changed on this VF.
8694 * If set to 0, then this bit should be ignored.
8696 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
8699 * If this bit is set to 1, then the value of MRU
8700 * was changed on this VF.
8701 * If set to 0, then this bit should be ignored.
8703 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
8706 * If this bit is set to 1, then the value of default MAC
8707 * address was changed on this VF.
8708 * If set to 0, then this bit should be ignored.
8710 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
8713 * If this bit is set to 1, then the value of default VLAN
8714 * was changed on this VF.
8715 * If set to 0, then this bit should be ignored.
8717 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
8720 * If this bit is set to 1, then the value of trusted VF enable
8721 * was changed on this VF.
8722 * If set to 0, then this bit should be ignored.
8724 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
8728 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
8729 struct hwrm_async_event_cmpl_llfc_pfc_change {
8732 * This field indicates the exact type of the completion.
8733 * By convention, the LSB identifies the length of the
8734 * record in 16B units. Even values indicate 16B
8735 * records. Odd values indicate 32B
8738 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
8740 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
8741 /* HWRM Asynchronous Event Information */
8742 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8744 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
8745 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8746 /* unused1 is 10 b */
8747 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
8749 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
8750 /* Identifiers of events. */
8752 /* LLFC/PFC Configuration Change */
8753 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
8755 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
8756 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
8757 /* Event specific data */
8758 uint32_t event_data2;
8761 * This value is written by the NIC such that it will be different
8762 * for each pass through the completion queue. The even passes
8763 * will write 1. The odd passes will write 0.
8765 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
8767 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
8769 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
8770 /* 8-lsb timestamp from POR (100-msec resolution) */
8771 uint8_t timestamp_lo;
8772 /* 16-lsb timestamp from POR (100-msec resolution) */
8773 uint16_t timestamp_hi;
8774 /* Event specific data */
8775 uint32_t event_data1;
8776 /* Indicates llfc pfc status change */
8777 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
8779 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
8782 * If this field set to 1, then it indicates that llfc is
8785 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
8788 * If this field is set to 2, then it indicates that pfc
8791 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
8793 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
8794 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
8795 /* Indicates the physical port this llfc pfc change occur */
8796 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
8798 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
8801 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8803 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8807 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
8808 struct hwrm_async_event_cmpl_default_vnic_change {
8811 * This field indicates the exact type of the completion.
8812 * By convention, the LSB identifies the length of the
8813 * record in 16B units. Even values indicate 16B
8814 * records. Odd values indicate 32B
8817 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
8819 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
8821 /* HWRM Asynchronous Event Information */
8822 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8824 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
8825 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8826 /* unused1 is 10 b */
8827 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
8829 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
8831 /* Identifiers of events. */
8833 /* Notification of a default vnic allocation or free */
8834 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
8836 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
8837 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
8838 /* Event specific data */
8839 uint32_t event_data2;
8842 * This value is written by the NIC such that it will be different
8843 * for each pass through the completion queue. The even passes
8844 * will write 1. The odd passes will write 0.
8846 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
8849 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
8851 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
8852 /* 8-lsb timestamp from POR (100-msec resolution) */
8853 uint8_t timestamp_lo;
8854 /* 16-lsb timestamp from POR (100-msec resolution) */
8855 uint16_t timestamp_hi;
8856 /* Event specific data */
8857 uint32_t event_data1;
8858 /* Indicates default vnic configuration change */
8859 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
8861 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
8864 * If this field is set to 1, then it indicates that
8865 * a default VNIC has been allocate.
8867 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
8870 * If this field is set to 2, then it indicates that
8871 * a default VNIC has been freed.
8873 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
8875 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
8876 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
8877 /* Indicates the physical function this event occurred on. */
8878 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
8880 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
8882 /* Indicates the virtual function this event occurred on */
8883 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
8885 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
8889 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
8890 struct hwrm_async_event_cmpl_hw_flow_aged {
8893 * This field indicates the exact type of the completion.
8894 * By convention, the LSB identifies the length of the
8895 * record in 16B units. Even values indicate 16B
8896 * records. Odd values indicate 32B
8899 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
8901 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
8902 /* HWRM Asynchronous Event Information */
8903 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
8905 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
8906 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
8907 /* Identifiers of events. */
8909 /* Notification of a hw flow aged */
8910 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
8912 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
8913 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
8914 /* Event specific data */
8915 uint32_t event_data2;
8918 * This value is written by the NIC such that it will be different
8919 * for each pass through the completion queue. The even passes
8920 * will write 1. The odd passes will write 0.
8922 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
8924 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
8925 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
8926 /* 8-lsb timestamp from POR (100-msec resolution) */
8927 uint8_t timestamp_lo;
8928 /* 16-lsb timestamp from POR (100-msec resolution) */
8929 uint16_t timestamp_hi;
8930 /* Event specific data */
8931 uint32_t event_data1;
8932 /* Indicates flow ID this event occurred on. */
8933 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
8934 UINT32_C(0x7fffffff)
8935 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
8937 /* Indicates flow direction this event occurred on. */
8938 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
8939 UINT32_C(0x80000000)
8941 * If this bit set to 0, then it indicates that the aged
8942 * event was rx flow.
8944 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
8945 (UINT32_C(0x0) << 31)
8947 * If this bit is set to 1, then it indicates that the aged
8948 * event was tx flow.
8950 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
8951 (UINT32_C(0x1) << 31)
8952 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
8953 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
8956 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
8957 struct hwrm_async_event_cmpl_eem_cache_flush_req {
8960 * This field indicates the exact type of the completion.
8961 * By convention, the LSB identifies the length of the
8962 * record in 16B units. Even values indicate 16B
8963 * records. Odd values indicate 32B
8966 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
8968 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
8970 /* HWRM Asynchronous Event Information */
8971 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
8973 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
8974 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
8975 /* Identifiers of events. */
8977 /* Notification of a eem_cache_flush request */
8978 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
8980 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
8981 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
8982 /* Event specific data */
8983 uint32_t event_data2;
8986 * This value is written by the NIC such that it will be different
8987 * for each pass through the completion queue. The even passes
8988 * will write 1. The odd passes will write 0.
8990 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
8993 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
8995 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
8996 /* 8-lsb timestamp from POR (100-msec resolution) */
8997 uint8_t timestamp_lo;
8998 /* 16-lsb timestamp from POR (100-msec resolution) */
8999 uint16_t timestamp_hi;
9000 /* Event specific data */
9001 uint32_t event_data1;
9004 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
9005 struct hwrm_async_event_cmpl_eem_cache_flush_done {
9008 * This field indicates the exact type of the completion.
9009 * By convention, the LSB identifies the length of the
9010 * record in 16B units. Even values indicate 16B
9011 * records. Odd values indicate 32B
9014 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
9016 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
9018 /* HWRM Asynchronous Event Information */
9019 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
9021 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
9022 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
9023 /* Identifiers of events. */
9026 * Notification of a host eem_cache_flush has completed. This event
9027 * is generated by the host driver.
9029 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9031 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
9032 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
9033 /* Event specific data */
9034 uint32_t event_data2;
9037 * This value is written by the NIC such that it will be different
9038 * for each pass through the completion queue. The even passes
9039 * will write 1. The odd passes will write 0.
9041 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
9044 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
9046 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
9047 /* 8-lsb timestamp from POR (100-msec resolution) */
9048 uint8_t timestamp_lo;
9049 /* 16-lsb timestamp from POR (100-msec resolution) */
9050 uint16_t timestamp_hi;
9051 /* Event specific data */
9052 uint32_t event_data1;
9053 /* Indicates function ID that this event occurred on. */
9054 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
9056 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
9060 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
9061 struct hwrm_async_event_cmpl_tcp_flag_action_change {
9064 * This field indicates the exact type of the completion.
9065 * By convention, the LSB identifies the length of the
9066 * record in 16B units. Even values indicate 16B
9067 * records. Odd values indicate 32B
9070 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
9072 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
9074 /* HWRM Asynchronous Event Information */
9075 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9077 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
9078 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
9079 /* Identifiers of events. */
9081 /* Notification of tcp flag action change */
9082 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9084 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
9085 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
9086 /* Event specific data */
9087 uint32_t event_data2;
9090 * This value is written by the NIC such that it will be different
9091 * for each pass through the completion queue. The even passes
9092 * will write 1. The odd passes will write 0.
9094 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
9097 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
9099 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
9100 /* 8-lsb timestamp from POR (100-msec resolution) */
9101 uint8_t timestamp_lo;
9102 /* 16-lsb timestamp from POR (100-msec resolution) */
9103 uint16_t timestamp_hi;
9104 /* Event specific data */
9105 uint32_t event_data1;
9108 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
9109 struct hwrm_async_event_cmpl_eem_flow_active {
9112 * This field indicates the exact type of the completion.
9113 * By convention, the LSB identifies the length of the
9114 * record in 16B units. Even values indicate 16B
9115 * records. Odd values indicate 32B
9118 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
9120 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
9121 /* HWRM Asynchronous Event Information */
9122 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
9124 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
9125 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
9126 /* Identifiers of events. */
9128 /* Notification of an active eem flow */
9129 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
9131 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
9132 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
9133 /* Event specific data */
9134 uint32_t event_data2;
9135 /* Indicates the 2nd global id this event occurred on. */
9136 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
9137 UINT32_C(0x3fffffff)
9138 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
9141 * Indicates flow direction of the flow identified by
9144 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
9145 UINT32_C(0x40000000)
9146 /* If this bit is set to 0, then it indicates that this rx flow. */
9147 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
9148 (UINT32_C(0x0) << 30)
9149 /* If this bit is set to 1, then it indicates that this tx flow. */
9150 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
9151 (UINT32_C(0x1) << 30)
9152 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
9153 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
9156 * This value is written by the NIC such that it will be different
9157 * for each pass through the completion queue. The even passes
9158 * will write 1. The odd passes will write 0.
9160 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
9162 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
9164 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
9165 /* 8-lsb timestamp from POR (100-msec resolution) */
9166 uint8_t timestamp_lo;
9167 /* 16-lsb timestamp from POR (100-msec resolution) */
9168 uint16_t timestamp_hi;
9169 /* Event specific data */
9170 uint32_t event_data1;
9171 /* Indicates the 1st global id this event occurred on. */
9172 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
9173 UINT32_C(0x3fffffff)
9174 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
9177 * Indicates flow direction of the flow identified by the
9180 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
9181 UINT32_C(0x40000000)
9182 /* If this bit is set to 0, then it indicates that this is rx flow. */
9183 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
9184 (UINT32_C(0x0) << 30)
9185 /* If this bit is set to 1, then it indicates that this is tx flow. */
9186 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
9187 (UINT32_C(0x1) << 30)
9188 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
9189 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
9191 * Indicates EEM flow aging mode this event occurred on. If
9192 * this bit is set to 0, the event_data1 is the EEM global
9193 * ID. If this bit is set to 1, the event_data1 is the number
9194 * of global ID in the context memory.
9196 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
9197 UINT32_C(0x80000000)
9198 /* EEM flow aging mode 0. */
9199 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
9200 (UINT32_C(0x0) << 31)
9201 /* EEM flow aging mode 1. */
9202 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
9203 (UINT32_C(0x1) << 31)
9204 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
9205 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
9208 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
9209 struct hwrm_async_event_cmpl_eem_cfg_change {
9212 * This field indicates the exact type of the completion.
9213 * By convention, the LSB identifies the length of the
9214 * record in 16B units. Even values indicate 16B
9215 * records. Odd values indicate 32B
9218 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
9220 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
9221 /* HWRM Asynchronous Event Information */
9222 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9224 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
9225 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9226 /* Identifiers of events. */
9228 /* Notification of EEM configuration change */
9229 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
9231 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
9232 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
9233 /* Event specific data */
9234 uint32_t event_data2;
9237 * This value is written by the NIC such that it will be different
9238 * for each pass through the completion queue. The even passes
9239 * will write 1. The odd passes will write 0.
9241 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
9243 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9244 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
9245 /* 8-lsb timestamp from POR (100-msec resolution) */
9246 uint8_t timestamp_lo;
9247 /* 16-lsb timestamp from POR (100-msec resolution) */
9248 uint16_t timestamp_hi;
9249 /* Event specific data */
9250 uint32_t event_data1;
9252 * Value of 1 to indicate EEM TX configuration is enabled. Value of
9253 * 0 to indicate the EEM TX configuration is disabled.
9255 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
9258 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
9259 * to indicate the EEM RX configuration is disabled.
9261 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
9265 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
9266 struct hwrm_async_event_cmpl_quiesce_done {
9269 * This field indicates the exact type of the completion.
9270 * By convention, the LSB identifies the length of the
9271 * record in 16B units. Even values indicate 16B
9272 * records. Odd values indicate 32B
9275 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
9277 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
9278 /* HWRM Asynchronous Event Information */
9279 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
9281 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
9282 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
9283 /* Identifiers of events. */
9285 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
9286 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
9288 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
9289 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
9290 /* Event specific data */
9291 uint32_t event_data2;
9292 /* Status of HWRM_FW_STATE_QUIESCE completion */
9293 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
9295 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
9298 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9299 * completed successfully.
9301 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
9304 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
9307 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
9310 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9311 * encountered an error.
9313 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
9315 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
9316 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
9318 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
9320 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
9323 * Additional information about internal hardware state related to
9324 * idle/quiesce state. QUIESCE may succeed per quiesce_status
9325 * regardless of idle_state_flags. If QUIESCE fails, the host may
9326 * inspect idle_state_flags to determine whether a retry is warranted.
9328 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
9330 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
9333 * Failure to quiesce is caused by host not updating the NQ consumer
9336 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
9338 /* Flag 1 indicating partial non-idle state. */
9339 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
9341 /* Flag 2 indicating partial non-idle state. */
9342 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
9344 /* Flag 3 indicating partial non-idle state. */
9345 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
9349 * This value is written by the NIC such that it will be different
9350 * for each pass through the completion queue. The even passes
9351 * will write 1. The odd passes will write 0.
9353 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
9355 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
9356 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
9357 /* 8-lsb timestamp from POR (100-msec resolution) */
9358 uint8_t timestamp_lo;
9359 /* 16-lsb timestamp from POR (100-msec resolution) */
9360 uint16_t timestamp_hi;
9361 /* Event specific data */
9362 uint32_t event_data1;
9363 /* Time stamp for error event */
9364 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
9368 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
9369 struct hwrm_async_event_cmpl_deferred_response {
9372 * This field indicates the exact type of the completion.
9373 * By convention, the LSB identifies the length of the
9374 * record in 16B units. Even values indicate 16B
9375 * records. Odd values indicate 32B
9378 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
9380 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
9381 /* HWRM Asynchronous Event Information */
9382 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
9384 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
9385 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
9386 /* Identifiers of events. */
9389 * An event signifying a HWRM command is in progress and its
9390 * response will be deferred
9392 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
9394 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
9395 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
9396 /* Event specific data */
9397 uint32_t event_data2;
9399 * The PF's mailbox is clear to issue another command.
9400 * A command with this seq_id is still in progress
9401 * and will return a regular HWRM completion when done.
9402 * 'event_data1' field, if non-zero, contains the estimated
9403 * execution time for the command.
9405 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
9407 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
9411 * This value is written by the NIC such that it will be different
9412 * for each pass through the completion queue. The even passes
9413 * will write 1. The odd passes will write 0.
9415 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
9418 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
9420 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
9421 /* 8-lsb timestamp from POR (100-msec resolution) */
9422 uint8_t timestamp_lo;
9423 /* 16-lsb timestamp from POR (100-msec resolution) */
9424 uint16_t timestamp_hi;
9425 /* Estimated remaining time of command execution in ms (if not zero) */
9426 uint32_t event_data1;
9429 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
9430 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
9433 * This field indicates the exact type of the completion.
9434 * By convention, the LSB identifies the length of the
9435 * record in 16B units. Even values indicate 16B
9436 * records. Odd values indicate 32B
9439 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
9441 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
9443 /* HWRM Asynchronous Event Information */
9444 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9446 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
9447 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9448 /* Identifiers of events. */
9450 /* PFC watchdog configuration change for given port/cos */
9451 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9453 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
9454 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
9455 /* Event specific data */
9456 uint32_t event_data2;
9459 * This value is written by the NIC such that it will be different
9460 * for each pass through the completion queue. The even passes
9461 * will write 1. The odd passes will write 0.
9463 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
9466 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
9468 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
9469 /* 8-lsb timestamp from POR (100-msec resolution) */
9470 uint8_t timestamp_lo;
9471 /* 16-lsb timestamp from POR (100-msec resolution) */
9472 uint16_t timestamp_hi;
9473 /* Event specific data */
9474 uint32_t event_data1;
9476 * 1 in bit position X indicates PFC watchdog should
9479 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
9481 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
9483 /* 1 means PFC WD for COS0 is on, 0 - off. */
9484 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
9486 /* 1 means PFC WD for COS1 is on, 0 - off. */
9487 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
9489 /* 1 means PFC WD for COS2 is on, 0 - off. */
9490 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
9492 /* 1 means PFC WD for COS3 is on, 0 - off. */
9493 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
9495 /* 1 means PFC WD for COS4 is on, 0 - off. */
9496 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
9498 /* 1 means PFC WD for COS5 is on, 0 - off. */
9499 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
9501 /* 1 means PFC WD for COS6 is on, 0 - off. */
9502 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
9504 /* 1 means PFC WD for COS7 is on, 0 - off. */
9505 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
9508 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9510 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9514 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
9515 struct hwrm_async_event_cmpl_fw_trace_msg {
9518 * This field indicates the exact type of the completion.
9519 * By convention, the LSB identifies the length of the
9520 * record in 16B units. Even values indicate 16B
9521 * records. Odd values indicate 32B
9524 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
9526 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
9527 /* HWRM Asynchronous Event Information */
9528 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
9530 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
9531 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
9532 /* Identifiers of events. */
9534 /* Firmware trace log message */
9535 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
9537 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
9538 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
9539 /* Trace byte 0 to 3 */
9540 uint32_t event_data2;
9542 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
9544 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
9546 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
9548 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
9550 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
9552 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
9554 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
9555 UINT32_C(0xff000000)
9556 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
9559 * This value is written by the NIC such that it will be different
9560 * for each pass through the completion queue. The even passes
9561 * will write 1. The odd passes will write 0.
9563 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
9565 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
9566 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
9568 uint8_t timestamp_lo;
9569 /* Indicates if the string is partial or complete. */
9570 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
9572 /* Complete string */
9573 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
9575 /* Partial string */
9576 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
9578 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
9579 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
9580 /* Indicates the firmware that sent the trace message. */
9581 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
9583 /* Primary firmware */
9584 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
9585 (UINT32_C(0x0) << 1)
9586 /* Secondary firmware */
9587 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
9588 (UINT32_C(0x1) << 1)
9589 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
9590 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
9591 /* Trace byte 4 to 5 */
9592 uint16_t timestamp_hi;
9594 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
9596 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
9598 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
9600 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
9601 /* Trace byte 6 to 9 */
9602 uint32_t event_data1;
9604 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
9606 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
9608 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
9610 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
9612 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
9614 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
9616 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
9617 UINT32_C(0xff000000)
9618 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
9621 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
9622 struct hwrm_async_event_cmpl_hwrm_error {
9625 * This field indicates the exact type of the completion.
9626 * By convention, the LSB identifies the length of the
9627 * record in 16B units. Even values indicate 16B
9628 * records. Odd values indicate 32B
9631 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
9633 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
9634 /* HWRM Asynchronous Event Information */
9635 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
9637 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
9638 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
9639 /* Identifiers of events. */
9642 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
9644 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
9645 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
9646 /* Event specific data */
9647 uint32_t event_data2;
9648 /* Severity of HWRM Error */
9649 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
9651 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
9653 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
9655 /* Non-fatal Error */
9656 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
9659 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
9661 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
9662 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
9665 * This value is written by the NIC such that it will be different
9666 * for each pass through the completion queue. The even passes
9667 * will write 1. The odd passes will write 0.
9669 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
9671 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
9672 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
9673 /* 8-lsb timestamp from POR (100-msec resolution) */
9674 uint8_t timestamp_lo;
9675 /* 16-lsb timestamp from POR (100-msec resolution) */
9676 uint16_t timestamp_hi;
9677 /* Event specific data */
9678 uint32_t event_data1;
9679 /* Time stamp for error event */
9680 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
9684 /* metadata_base_msg (size:64b/8B) */
9685 struct metadata_base_msg {
9686 uint16_t md_type_link;
9687 /* This field classifies the data present in the meta-data. */
9688 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
9689 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
9690 /* Meta data fields are not valid */
9691 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
9693 * This setting is used when packets are coming in-order. Depending on
9694 * the state of the receive context, the meta-data will carry different
9697 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
9699 * With this setting HW passes the TCP sequence number of the TLS
9700 * record that it is requesting a resync on in the meta data.
9702 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
9703 #define METADATA_BASE_MSG_MD_TYPE_LAST \
9704 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9706 * This field indicates where the next metadata block starts. It is
9707 * counted in 16B units. A value of zero indicates that there is no
9710 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
9711 #define METADATA_BASE_MSG_LINK_SFT 5
9716 /* tls_metadata_base_msg (size:64b/8B) */
9717 struct tls_metadata_base_msg {
9718 uint32_t md_type_link_flags_kid_lo;
9719 /* This field classifies the data present in the meta-data. */
9720 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
9722 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
9724 * This setting is used when packets are coming in-order. Depending on
9725 * the state of the receive context, the meta-data will carry different
9728 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
9731 * With this setting HW passes the TCP sequence number of the TLS
9732 * record that it is requesting a resync on in the meta data.
9734 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
9736 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
9737 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9739 * This field indicates where the next metadata block starts. It is
9740 * counted in 16B units. A value of zero indicates that there is no
9743 #define TLS_METADATA_BASE_MSG_LINK_MASK \
9745 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
9746 /* These are flags present in the metadata. */
9747 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
9749 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
9751 * A value of 1 implies that the packet was decrypted by HW. Otherwise
9752 * the packet is passed on as it came in on the wire.
9754 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
9757 * This field indicates the state of the ghash field passed in the
9760 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
9762 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
9764 * This enumeration states that the ghash is not valid in the
9767 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
9768 (UINT32_C(0x0) << 10)
9770 * This enumeration indicates that this pkt contains the record's
9771 * tag and this pkt was received ooo, the partial_ghash field
9772 * contains the ghash.
9774 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
9775 (UINT32_C(0x1) << 10)
9777 * This enumeration indicates that the current record's tag wasn't
9778 * seen and the chip is moving on to the next record, the
9779 * partial_ghash field contains the ghash.
9781 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
9782 (UINT32_C(0x2) << 10)
9783 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
9784 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
9785 /* This field indicates the status of tag authentication. */
9786 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
9788 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
9790 * This enumeration is set when there is no tags present in the
9793 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
9794 (UINT32_C(0x0) << 12)
9796 * This enumeration states that there is at least one tag in the
9797 * packet and every tag is valid.
9799 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
9800 (UINT32_C(0x1) << 12)
9802 * This enumeration states that there is at least one tag in the
9803 * packet and at least one of the tag is invalid. The entire packet
9804 * is sent decrypted to the host.
9806 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
9807 (UINT32_C(0x2) << 12)
9808 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
9809 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
9811 * A value of 1 indicates that this packet contains a record that
9812 * starts in the packet and extends beyond the packet.
9814 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
9817 * This value indicates the lower 7-bit of the Crypto Key ID
9818 * associated with this operation.
9820 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
9821 UINT32_C(0xfe000000)
9822 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
9825 * This value indicates the upper 13-bit of the Crypto Key ID
9826 * associated with this operation.
9828 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
9829 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
9833 /* tls_metadata_insync_msg (size:192b/24B) */
9834 struct tls_metadata_insync_msg {
9835 uint32_t md_type_link_flags_kid_lo;
9836 /* This field classifies the data present in the meta-data. */
9837 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
9839 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
9841 * This setting is used when packets are coming in-order. Depending on
9842 * the state of the receive context, the meta-data will carry different
9845 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
9847 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
9848 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
9850 * This field indicates where the next metadata block starts. It is
9851 * counted in 16B units. A value of zero indicates that there is no
9854 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
9856 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
9857 /* These are flags present in the metadata. */
9858 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
9860 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
9862 * A value of 1 implies that the packet was decrypted by HW. Otherwise
9863 * the packet is passed on as it came in on the wire.
9865 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
9868 * This field indicates the state of the ghash field passed in the
9871 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
9873 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
9875 * This enumeration states that the ghash is not valid in the
9878 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
9879 (UINT32_C(0x0) << 10)
9881 * This enumeration indicates that this pkt contains the record's
9882 * tag and this pkt was received ooo, the partial_ghash field
9883 * contains the ghash.
9885 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
9886 (UINT32_C(0x1) << 10)
9888 * This enumeration indicates that the current record's tag wasn't
9889 * seen and the chip is moving on to the next record, the
9890 * partial_ghash field contains the ghash.
9892 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
9893 (UINT32_C(0x2) << 10)
9894 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
9895 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
9896 /* This field indicates the status of tag authentication. */
9897 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
9899 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
9901 * This enumeration is set when there is no tags present in the
9904 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
9905 (UINT32_C(0x0) << 12)
9907 * This enumeration states that there is at least one tag in the
9908 * packet and every tag is valid.
9910 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
9911 (UINT32_C(0x1) << 12)
9913 * This enumeration states that there is at least one tag in the
9914 * packet and at least one of the tag is invalid. The entire packet
9915 * is sent decrypted to the host.
9917 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
9918 (UINT32_C(0x2) << 12)
9919 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
9920 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
9922 * A value of 1 indicates that this packet contains a record that
9923 * starts in the packet and extends beyond the packet.
9925 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
9928 * This value indicates the lower 7-bit of the Crypto Key ID
9929 * associated with this operation.
9931 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
9932 UINT32_C(0xfe000000)
9933 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
9936 * This value indicates the upper 13-bit of the Crypto Key ID
9937 * associated with this operation.
9939 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
9940 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
9942 * This field is only valid when md_type is set to tls_insync. This field
9943 * indicates the offset within the current TCP packet where the TLS header
9944 * starts. If there are multiple TLS headers in the packet, this provides
9945 * the offset of the last TLS header.
9947 * The field is calculated by subtracting TCP sequence number of the first
9948 * byte of the TCP payload of the packet from the TCP sequence number of
9949 * the last TLS header in the packet.
9951 uint16_t tls_header_offset;
9953 * This is the sequence Number of the record that was processed by the HW.
9954 * If there are multiple records in a packet, this would be the sequence
9955 * number of the last record.
9957 uint64_t record_seq_num;
9959 * This field contains cumulative partial GHASH value of all the packets
9960 * decrypted by the HW associated with a TLS record. This field is valid
9961 * on when packets belonging to have arrived out-of-order and HW could
9962 * not decrypt every packet and authenticate the record. Partial GHASH is
9963 * only sent out with packet having the TAG field.
9965 uint64_t partial_ghash;
9968 /* tls_metadata_resync_msg (size:256b/32B) */
9969 struct tls_metadata_resync_msg {
9970 uint32_t md_type_link_flags_kid_lo;
9971 /* This field classifies the data present in the meta-data. */
9972 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
9974 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
9976 * With this setting HW passes the TCP sequence number of the TLS
9977 * record that it is requesting a resync on in the meta data.
9979 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
9981 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
9982 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
9984 * This field indicates where the next metadata block starts. It is
9985 * counted in 16B units. A value of zero indicates that there is no
9988 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
9990 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
9991 /* These are flags present in the metadata. */
9992 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
9994 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
9996 * A value of 1 implies that the packet was decrypted by HW. Otherwise
9997 * the packet is passed on as it came in on the wire.
9999 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
10002 * This field indicates the state of the ghash field passed in the
10005 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
10007 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
10009 * This enumeration states that the ghash is not valid in the
10012 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
10013 (UINT32_C(0x0) << 10)
10014 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
10015 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
10016 /* This field indicates the status of tag authentication. */
10017 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10019 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10021 * This enumeration is set when there is no tags present in the
10024 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10025 (UINT32_C(0x0) << 12)
10026 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10027 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
10029 * A value of 1 indicates that this packet contains a record that
10030 * starts in the packet and extends beyond the packet.
10032 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10035 * This value indicates the lower 7-bit of the Crypto Key ID
10036 * associated with this operation.
10038 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
10039 UINT32_C(0xfe000000)
10040 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
10043 * This value indicates the upper 13-bit of the Crypto Key ID
10044 * associated with this operation.
10046 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10047 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
10048 /* This field is unused in this context. */
10049 uint16_t metadata_0;
10051 * This field indicates the TCP sequence number of the TLS record that HW
10052 * is requesting a resync on from the Driver. HW will keep a count of the
10053 * TLS records it found after this record (delta_records). Driver will
10054 * provide the TLS Record Sequence Number associated with the record. HW
10055 * will add the delta_records to the Record Sequence Number provided by
10056 * the driver and get back on sync.
10058 uint32_t resync_record_tcp_seq_num;
10060 /* This field is unused in this context. */
10061 uint64_t metadata_2;
10062 /* This field is unused in this context. */
10063 uint64_t metadata_3;
10066 /*******************
10067 * hwrm_func_reset *
10068 *******************/
10071 /* hwrm_func_reset_input (size:192b/24B) */
10072 struct hwrm_func_reset_input {
10073 /* The HWRM command request type. */
10076 * The completion ring to send the completion event on. This should
10077 * be the NQ ID returned from the `nq_alloc` HWRM command.
10079 uint16_t cmpl_ring;
10081 * The sequence ID is used by the driver for tracking multiple
10082 * commands. This ID is treated as opaque data by the firmware and
10083 * the value is returned in the `hwrm_resp_hdr` upon completion.
10087 * The target ID of the command:
10088 * * 0x0-0xFFF8 - The function ID
10089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10090 * * 0xFFFD - Reserved for user-space HWRM interface
10093 uint16_t target_id;
10095 * A physical address pointer pointing to a host buffer that the
10096 * command's response data will be written. This can be either a host
10097 * physical address (HPA) or a guest physical address (GPA) and must
10098 * point to a physically contiguous block of memory.
10100 uint64_t resp_addr;
10103 * This bit must be '1' for the vf_id_valid field to be
10106 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
10108 * The ID of the VF that this PF is trying to reset.
10109 * Only the parent PF shall be allowed to reset a child VF.
10111 * A parent PF driver shall use this field only when a specific child VF
10112 * is requested to be reset.
10115 /* This value indicates the level of a function reset. */
10116 uint8_t func_reset_level;
10118 * Reset the caller function and its children VFs (if any). If no
10119 * children functions exist, then reset the caller function only.
10121 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
10123 /* Reset the caller function only */
10124 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
10127 * Reset all children VFs of the caller function driver if the
10128 * caller is a PF driver.
10129 * It is an error to specify this level by a VF driver.
10130 * It is an error to specify this level by a PF driver with
10133 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
10136 * Reset a specific VF of the caller function driver if the caller
10137 * is the parent PF driver.
10138 * It is an error to specify this level by a VF driver.
10139 * It is an error to specify this level by a PF driver that is not
10140 * the parent of the VF that is being requested to reset.
10142 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
10144 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
10145 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
10149 /* hwrm_func_reset_output (size:128b/16B) */
10150 struct hwrm_func_reset_output {
10151 /* The specific error status for the command. */
10152 uint16_t error_code;
10153 /* The HWRM command request type. */
10155 /* The sequence ID from the original command. */
10157 /* The length of the response data in number of bytes. */
10159 uint8_t unused_0[7];
10161 * This field is used in Output records to indicate that the output
10162 * is completely written to RAM. This field should be read as '1'
10163 * to indicate that the output has been completely written.
10164 * When writing a command completion or response to an internal processor,
10165 * the order of writes has to be such that this field is written last.
10170 /********************
10171 * hwrm_func_getfid *
10172 ********************/
10175 /* hwrm_func_getfid_input (size:192b/24B) */
10176 struct hwrm_func_getfid_input {
10177 /* The HWRM command request type. */
10180 * The completion ring to send the completion event on. This should
10181 * be the NQ ID returned from the `nq_alloc` HWRM command.
10183 uint16_t cmpl_ring;
10185 * The sequence ID is used by the driver for tracking multiple
10186 * commands. This ID is treated as opaque data by the firmware and
10187 * the value is returned in the `hwrm_resp_hdr` upon completion.
10191 * The target ID of the command:
10192 * * 0x0-0xFFF8 - The function ID
10193 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10194 * * 0xFFFD - Reserved for user-space HWRM interface
10197 uint16_t target_id;
10199 * A physical address pointer pointing to a host buffer that the
10200 * command's response data will be written. This can be either a host
10201 * physical address (HPA) or a guest physical address (GPA) and must
10202 * point to a physically contiguous block of memory.
10204 uint64_t resp_addr;
10207 * This bit must be '1' for the pci_id field to be
10210 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
10212 * This value is the PCI ID of the queried function.
10213 * If ARI is enabled, then it is
10214 * Bus Number (8b):Function Number(8b). Otherwise, it is
10215 * Bus Number (8b):Device Number (5b):Function Number(3b).
10218 uint8_t unused_0[2];
10221 /* hwrm_func_getfid_output (size:128b/16B) */
10222 struct hwrm_func_getfid_output {
10223 /* The specific error status for the command. */
10224 uint16_t error_code;
10225 /* The HWRM command request type. */
10227 /* The sequence ID from the original command. */
10229 /* The length of the response data in number of bytes. */
10232 * FID value. This value is used to identify operations on the PCI
10233 * bus as belonging to a particular PCI function.
10236 uint8_t unused_0[5];
10238 * This field is used in Output records to indicate that the output
10239 * is completely written to RAM. This field should be read as '1'
10240 * to indicate that the output has been completely written.
10241 * When writing a command completion or response to an internal processor,
10242 * the order of writes has to be such that this field is written last.
10247 /**********************
10248 * hwrm_func_vf_alloc *
10249 **********************/
10252 /* hwrm_func_vf_alloc_input (size:192b/24B) */
10253 struct hwrm_func_vf_alloc_input {
10254 /* The HWRM command request type. */
10257 * The completion ring to send the completion event on. This should
10258 * be the NQ ID returned from the `nq_alloc` HWRM command.
10260 uint16_t cmpl_ring;
10262 * The sequence ID is used by the driver for tracking multiple
10263 * commands. This ID is treated as opaque data by the firmware and
10264 * the value is returned in the `hwrm_resp_hdr` upon completion.
10268 * The target ID of the command:
10269 * * 0x0-0xFFF8 - The function ID
10270 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10271 * * 0xFFFD - Reserved for user-space HWRM interface
10274 uint16_t target_id;
10276 * A physical address pointer pointing to a host buffer that the
10277 * command's response data will be written. This can be either a host
10278 * physical address (HPA) or a guest physical address (GPA) and must
10279 * point to a physically contiguous block of memory.
10281 uint64_t resp_addr;
10284 * This bit must be '1' for the first_vf_id field to be
10287 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10289 * This value is used to identify a Virtual Function (VF).
10290 * The scope of VF ID is local within a PF.
10292 uint16_t first_vf_id;
10293 /* The number of virtual functions requested. */
10297 /* hwrm_func_vf_alloc_output (size:128b/16B) */
10298 struct hwrm_func_vf_alloc_output {
10299 /* The specific error status for the command. */
10300 uint16_t error_code;
10301 /* The HWRM command request type. */
10303 /* The sequence ID from the original command. */
10305 /* The length of the response data in number of bytes. */
10307 /* The ID of the first VF allocated. */
10308 uint16_t first_vf_id;
10309 uint8_t unused_0[5];
10311 * This field is used in Output records to indicate that the output
10312 * is completely written to RAM. This field should be read as '1'
10313 * to indicate that the output has been completely written.
10314 * When writing a command completion or response to an internal processor,
10315 * the order of writes has to be such that this field is written last.
10320 /*********************
10321 * hwrm_func_vf_free *
10322 *********************/
10325 /* hwrm_func_vf_free_input (size:192b/24B) */
10326 struct hwrm_func_vf_free_input {
10327 /* The HWRM command request type. */
10330 * The completion ring to send the completion event on. This should
10331 * be the NQ ID returned from the `nq_alloc` HWRM command.
10333 uint16_t cmpl_ring;
10335 * The sequence ID is used by the driver for tracking multiple
10336 * commands. This ID is treated as opaque data by the firmware and
10337 * the value is returned in the `hwrm_resp_hdr` upon completion.
10341 * The target ID of the command:
10342 * * 0x0-0xFFF8 - The function ID
10343 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10344 * * 0xFFFD - Reserved for user-space HWRM interface
10347 uint16_t target_id;
10349 * A physical address pointer pointing to a host buffer that the
10350 * command's response data will be written. This can be either a host
10351 * physical address (HPA) or a guest physical address (GPA) and must
10352 * point to a physically contiguous block of memory.
10354 uint64_t resp_addr;
10357 * This bit must be '1' for the first_vf_id field to be
10360 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10362 * This value is used to identify a Virtual Function (VF).
10363 * The scope of VF ID is local within a PF.
10365 uint16_t first_vf_id;
10367 * The number of virtual functions requested.
10368 * 0xFFFF - Cleanup all children of this PF.
10373 /* hwrm_func_vf_free_output (size:128b/16B) */
10374 struct hwrm_func_vf_free_output {
10375 /* The specific error status for the command. */
10376 uint16_t error_code;
10377 /* The HWRM command request type. */
10379 /* The sequence ID from the original command. */
10381 /* The length of the response data in number of bytes. */
10383 uint8_t unused_0[7];
10385 * This field is used in Output records to indicate that the output
10386 * is completely written to RAM. This field should be read as '1'
10387 * to indicate that the output has been completely written.
10388 * When writing a command completion or response to an internal processor,
10389 * the order of writes has to be such that this field is written last.
10394 /********************
10395 * hwrm_func_vf_cfg *
10396 ********************/
10399 /* hwrm_func_vf_cfg_input (size:448b/56B) */
10400 struct hwrm_func_vf_cfg_input {
10401 /* The HWRM command request type. */
10404 * The completion ring to send the completion event on. This should
10405 * be the NQ ID returned from the `nq_alloc` HWRM command.
10407 uint16_t cmpl_ring;
10409 * The sequence ID is used by the driver for tracking multiple
10410 * commands. This ID is treated as opaque data by the firmware and
10411 * the value is returned in the `hwrm_resp_hdr` upon completion.
10415 * The target ID of the command:
10416 * * 0x0-0xFFF8 - The function ID
10417 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10418 * * 0xFFFD - Reserved for user-space HWRM interface
10421 uint16_t target_id;
10423 * A physical address pointer pointing to a host buffer that the
10424 * command's response data will be written. This can be either a host
10425 * physical address (HPA) or a guest physical address (GPA) and must
10426 * point to a physically contiguous block of memory.
10428 uint64_t resp_addr;
10431 * This bit must be '1' for the mtu field to be
10434 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
10437 * This bit must be '1' for the guest_vlan field to be
10440 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
10443 * This bit must be '1' for the async_event_cr field to be
10446 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10449 * This bit must be '1' for the dflt_mac_addr field to be
10452 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10455 * This bit must be '1' for the num_rsscos_ctxs field to be
10458 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10461 * This bit must be '1' for the num_cmpl_rings field to be
10464 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10467 * This bit must be '1' for the num_tx_rings field to be
10470 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10473 * This bit must be '1' for the num_rx_rings field to be
10476 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10479 * This bit must be '1' for the num_l2_ctxs field to be
10482 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10485 * This bit must be '1' for the num_vnics field to be
10488 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
10491 * This bit must be '1' for the num_stat_ctxs field to be
10494 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10497 * This bit must be '1' for the num_hw_ring_grps field to be
10500 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10503 * The maximum transmission unit requested on the function.
10504 * The HWRM should make sure that the mtu of
10505 * the function does not exceed the mtu of the physical
10506 * port that this function is associated with.
10508 * In addition to requesting mtu per function, it is
10509 * possible to configure mtu per transmit ring.
10510 * By default, the mtu of each transmit ring associated
10511 * with a function is equal to the mtu of the function.
10512 * The HWRM should make sure that the mtu of each transmit
10513 * ring that is assigned to a function has a valid mtu.
10517 * The guest VLAN for the function being configured.
10518 * This field's format is same as 802.1Q Tag's
10519 * Tag Control Information (TCI) format that includes both
10520 * Priority Code Point (PCP) and VLAN Identifier (VID).
10522 uint16_t guest_vlan;
10524 * ID of the target completion ring for receiving asynchronous
10525 * event completions. If this field is not valid, then the
10526 * HWRM shall use the default completion ring of the function
10527 * that is being configured as the target completion ring for
10528 * providing any asynchronous event completions for that
10530 * If this field is valid, then the HWRM shall use the
10531 * completion ring identified by this ID as the target
10532 * completion ring for providing any asynchronous event
10533 * completions for the function that is being configured.
10535 uint16_t async_event_cr;
10537 * This value is the current MAC address requested by the VF
10538 * driver to be configured on this VF. A value of
10539 * 00-00-00-00-00-00 indicates no MAC address configuration
10540 * is requested by the VF driver.
10541 * The parent PF driver may reject or overwrite this
10544 uint8_t dflt_mac_addr[6];
10547 * This bit requests that the firmware test to see if all the assets
10548 * requested in this command (i.e. number of TX rings) are available.
10549 * The firmware will return an error if the requested assets are
10550 * not available. The firwmare will NOT reserve the assets if they
10553 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10556 * This bit requests that the firmware test to see if all the assets
10557 * requested in this command (i.e. number of RX rings) are available.
10558 * The firmware will return an error if the requested assets are
10559 * not available. The firwmare will NOT reserve the assets if they
10562 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10565 * This bit requests that the firmware test to see if all the assets
10566 * requested in this command (i.e. number of CMPL rings) are available.
10567 * The firmware will return an error if the requested assets are
10568 * not available. The firwmare will NOT reserve the assets if they
10571 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10574 * This bit requests that the firmware test to see if all the assets
10575 * requested in this command (i.e. number of RSS ctx) are available.
10576 * The firmware will return an error if the requested assets are
10577 * not available. The firwmare will NOT reserve the assets if they
10580 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10583 * This bit requests that the firmware test to see if all the assets
10584 * requested in this command (i.e. number of ring groups) are available.
10585 * The firmware will return an error if the requested assets are
10586 * not available. The firwmare will NOT reserve the assets if they
10589 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10592 * This bit requests that the firmware test to see if all the assets
10593 * requested in this command (i.e. number of stat ctx) are available.
10594 * The firmware will return an error if the requested assets are
10595 * not available. The firwmare will NOT reserve the assets if they
10598 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10601 * This bit requests that the firmware test to see if all the assets
10602 * requested in this command (i.e. number of VNICs) are available.
10603 * The firmware will return an error if the requested assets are
10604 * not available. The firwmare will NOT reserve the assets if they
10607 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10610 * This bit requests that the firmware test to see if all the assets
10611 * requested in this command (i.e. number of L2 ctx) are available.
10612 * The firmware will return an error if the requested assets are
10613 * not available. The firwmare will NOT reserve the assets if they
10616 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10619 * If this bit is set to 1, the VF driver is requesting FW to enable
10620 * PPP TX PUSH feature on all the TX rings specified in the
10621 * num_tx_rings field. By default, the PPP TX push feature is
10622 * disabled for all the TX rings of the VF. This flag is ignored if
10623 * the num_tx_rings field is not specified or the VF doesn't support
10624 * PPP tx push feature.
10626 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10629 * If this bit is set to 1, the VF driver is requesting FW to disable
10630 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
10631 * ignored if the VF doesn't support PPP tx push feature.
10633 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
10635 /* The number of RSS/COS contexts requested for the VF. */
10636 uint16_t num_rsscos_ctxs;
10637 /* The number of completion rings requested for the VF. */
10638 uint16_t num_cmpl_rings;
10639 /* The number of transmit rings requested for the VF. */
10640 uint16_t num_tx_rings;
10641 /* The number of receive rings requested for the VF. */
10642 uint16_t num_rx_rings;
10643 /* The number of L2 contexts requested for the VF. */
10644 uint16_t num_l2_ctxs;
10645 /* The number of vnics requested for the VF. */
10646 uint16_t num_vnics;
10647 /* The number of statistic contexts requested for the VF. */
10648 uint16_t num_stat_ctxs;
10649 /* The number of HW ring groups requested for the VF. */
10650 uint16_t num_hw_ring_grps;
10651 uint8_t unused_0[4];
10654 /* hwrm_func_vf_cfg_output (size:128b/16B) */
10655 struct hwrm_func_vf_cfg_output {
10656 /* The specific error status for the command. */
10657 uint16_t error_code;
10658 /* The HWRM command request type. */
10660 /* The sequence ID from the original command. */
10662 /* The length of the response data in number of bytes. */
10664 uint8_t unused_0[7];
10666 * This field is used in Output records to indicate that the output
10667 * is completely written to RAM. This field should be read as '1'
10668 * to indicate that the output has been completely written.
10669 * When writing a command completion or response to an internal processor,
10670 * the order of writes has to be such that this field is written last.
10675 /*******************
10676 * hwrm_func_qcaps *
10677 *******************/
10680 /* hwrm_func_qcaps_input (size:192b/24B) */
10681 struct hwrm_func_qcaps_input {
10682 /* The HWRM command request type. */
10685 * The completion ring to send the completion event on. This should
10686 * be the NQ ID returned from the `nq_alloc` HWRM command.
10688 uint16_t cmpl_ring;
10690 * The sequence ID is used by the driver for tracking multiple
10691 * commands. This ID is treated as opaque data by the firmware and
10692 * the value is returned in the `hwrm_resp_hdr` upon completion.
10696 * The target ID of the command:
10697 * * 0x0-0xFFF8 - The function ID
10698 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10699 * * 0xFFFD - Reserved for user-space HWRM interface
10702 uint16_t target_id;
10704 * A physical address pointer pointing to a host buffer that the
10705 * command's response data will be written. This can be either a host
10706 * physical address (HPA) or a guest physical address (GPA) and must
10707 * point to a physically contiguous block of memory.
10709 uint64_t resp_addr;
10711 * Function ID of the function that is being queried.
10712 * 0xFF... (All Fs) if the query is for the requesting
10714 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
10715 * to be used by a trusted VF to query its parent PF.
10718 uint8_t unused_0[6];
10721 /* hwrm_func_qcaps_output (size:704b/88B) */
10722 struct hwrm_func_qcaps_output {
10723 /* The specific error status for the command. */
10724 uint16_t error_code;
10725 /* The HWRM command request type. */
10727 /* The sequence ID from the original command. */
10729 /* The length of the response data in number of bytes. */
10732 * FID value. This value is used to identify operations on the PCI
10733 * bus as belonging to a particular PCI function.
10737 * Port ID of port that this function is associated with.
10738 * Valid only for the PF.
10739 * 0xFF... (All Fs) if this function is not associated with
10741 * 0xFF... (All Fs) if this function is called from a VF.
10745 /* If 1, then Push mode is supported on this function. */
10746 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
10749 * If 1, then the global MSI-X auto-masking is enabled for the
10752 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
10755 * If 1, then the Precision Time Protocol (PTP) processing
10756 * is supported on this function.
10757 * The HWRM should enable PTP on only a single Physical
10758 * Function (PF) per port.
10760 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
10763 * If 1, then RDMA over Converged Ethernet (RoCE) v1
10764 * is supported on this function.
10766 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
10769 * If 1, then RDMA over Converged Ethernet (RoCE) v2
10770 * is supported on this function.
10772 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
10775 * If 1, then control and configuration of WoL magic packet
10776 * are supported on this function.
10778 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
10781 * If 1, then control and configuration of bitmap pattern
10782 * packet are supported on this function.
10784 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
10787 * If set to 1, then the control and configuration of rate limit
10788 * of an allocated TX ring on the queried function is supported.
10790 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
10793 * If 1, then control and configuration of minimum and
10794 * maximum bandwidths are supported on the queried function.
10796 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
10799 * If the query is for a VF, then this flag shall be ignored.
10800 * If this query is for a PF and this flag is set to 1,
10801 * then the PF has the capability to set the rate limits
10802 * on the TX rings of its children VFs.
10803 * If this query is for a PF and this flag is set to 0, then
10804 * the PF does not have the capability to set the rate limits
10805 * on the TX rings of its children VFs.
10807 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
10810 * If the query is for a VF, then this flag shall be ignored.
10811 * If this query is for a PF and this flag is set to 1,
10812 * then the PF has the capability to set the minimum and/or
10813 * maximum bandwidths for its children VFs.
10814 * If this query is for a PF and this flag is set to 0, then
10815 * the PF does not have the capability to set the minimum or
10816 * maximum bandwidths for its children VFs.
10818 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
10821 * Standard TX Ring mode is used for the allocation of TX ring
10822 * and underlying scheduling resources that allow bandwidth
10823 * reservation and limit settings on the queried function.
10824 * If set to 1, then standard TX ring mode is supported
10825 * on the queried function.
10826 * If set to 0, then standard TX ring mode is not available
10827 * on the queried function.
10829 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
10832 * If the query is for a VF, then this flag shall be ignored,
10833 * If this query is for a PF and this flag is set to 1,
10834 * then the PF has the capability to detect GENEVE tunnel
10837 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
10840 * If the query is for a VF, then this flag shall be ignored,
10841 * If this query is for a PF and this flag is set to 1,
10842 * then the PF has the capability to detect NVGRE tunnel
10845 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
10848 * If the query is for a VF, then this flag shall be ignored,
10849 * If this query is for a PF and this flag is set to 1,
10850 * then the PF has the capability to detect GRE tunnel
10853 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
10856 * If the query is for a VF, then this flag shall be ignored,
10857 * If this query is for a PF and this flag is set to 1,
10858 * then the PF has the capability to detect MPLS tunnel
10861 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
10864 * If the query is for a VF, then this flag shall be ignored,
10865 * If this query is for a PF and this flag is set to 1,
10866 * then the PF has the capability to support pcie stats.
10868 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
10871 * If the query is for a VF, then this flag shall be ignored,
10872 * If this query is for a PF and this flag is set to 1,
10873 * then the PF has the capability to adopt the VF's belonging
10876 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
10879 * If the query is for a VF, then this flag shall be ignored,
10880 * If this query is for a PF and this flag is set to 1,
10881 * then the PF has the administrative privilege to configure another PF
10883 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
10886 * If the query is for a VF, then this flag shall be ignored.
10887 * If this query is for a PF and this flag is set to 1, then
10888 * the PF will know that the firmware has the capability to track
10889 * the virtual link status.
10891 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
10894 * If 1, then this function supports the push mode that uses
10895 * write combine buffers and the long inline tx buffer descriptor.
10897 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
10900 * If 1, then FW has capability to allocate TX rings dynamically
10901 * in ring alloc even if PF reserved pool is zero.
10902 * This bit will be used only for PFs.
10904 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
10907 * When this bit is '1', it indicates that core firmware is
10908 * capable of Hot Reset.
10910 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
10913 * This flag will be set to 1 by the FW if FW supports adapter error
10916 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
10919 * If the query is for a VF, then this flag shall be ignored.
10920 * If this query is for a PF and this flag is set to 1, then
10921 * the PF has the capability to support extended stats.
10923 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
10924 UINT32_C(0x1000000)
10926 * If the query is for a VF, then this flag shall be ignored.
10927 * If this query is for a PF and this flag is set to 1, then host
10928 * must initiate reset or reload (or fastboot) the firmware image
10929 * upon detection of device shutdown state.
10931 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
10932 UINT32_C(0x2000000)
10934 * If the query is for a VF, then this flag (always set to 0) shall
10935 * be ignored. If this query is for a PF and this flag is set to 1,
10936 * host, when registered for the default vnic change async event,
10937 * receives async notification whenever a default vnic state is
10938 * changed for any of child or adopted VFs.
10940 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
10941 UINT32_C(0x4000000)
10942 /* If set to 1, then the vlan acceleration for TX is disabled. */
10943 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
10944 UINT32_C(0x8000000)
10946 * When this bit is '1', it indicates that core firmware supports
10947 * DBG_COREDUMP_XXX commands.
10949 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
10950 UINT32_C(0x10000000)
10952 * When this bit is '1', it indicates that core firmware supports
10953 * DBG_CRASHDUMP_XXX commands.
10955 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
10956 UINT32_C(0x20000000)
10958 * If the query is for a VF, then this flag should be ignored.
10959 * If the query is for a PF and this flag is set to 1, then
10960 * the PF has the capability to support retrieval of
10961 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
10962 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
10963 * If this flag is set to 1, only that (supported) command should
10964 * be used for retrieval of PFC related statistics (rather than
10965 * hwrm_port_qstats_ext command, which could previously be used).
10967 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
10968 UINT32_C(0x40000000)
10970 * When this bit is '1', it indicates that core firmware supports
10971 * DBG_QCAPS command
10973 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
10974 UINT32_C(0x80000000)
10976 * This value is current MAC address configured for this
10977 * function. A value of 00-00-00-00-00-00 indicates no
10978 * MAC address is currently configured.
10980 uint8_t mac_address[6];
10982 * The maximum number of RSS/COS contexts that can be
10983 * allocated to the function.
10985 uint16_t max_rsscos_ctx;
10987 * The maximum number of completion rings that can be
10988 * allocated to the function.
10990 uint16_t max_cmpl_rings;
10992 * The maximum number of transmit rings that can be
10993 * allocated to the function.
10995 uint16_t max_tx_rings;
10997 * The maximum number of receive rings that can be
10998 * allocated to the function.
11000 uint16_t max_rx_rings;
11002 * The maximum number of L2 contexts that can be
11003 * allocated to the function.
11005 uint16_t max_l2_ctxs;
11007 * The maximum number of VNICs that can be
11008 * allocated to the function.
11010 uint16_t max_vnics;
11012 * The identifier for the first VF enabled on a PF. This
11013 * is valid only on the PF with SR-IOV enabled.
11014 * 0xFF... (All Fs) if this command is called on a PF with
11015 * SR-IOV disabled or on a VF.
11017 uint16_t first_vf_id;
11019 * The maximum number of VFs that can be
11020 * allocated to the function. This is valid only on the
11021 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
11022 * command is called on a PF with SR-IOV disabled or
11027 * The maximum number of statistic contexts that can be
11028 * allocated to the function.
11030 uint16_t max_stat_ctx;
11032 * The maximum number of Encapsulation records that can be
11033 * offloaded by this function.
11035 uint32_t max_encap_records;
11037 * The maximum number of decapsulation records that can
11038 * be offloaded by this function.
11040 uint32_t max_decap_records;
11042 * The maximum number of Exact Match (EM) flows that can be
11043 * offloaded by this function on the TX side.
11045 uint32_t max_tx_em_flows;
11047 * The maximum number of Wildcard Match (WM) flows that can
11048 * be offloaded by this function on the TX side.
11050 uint32_t max_tx_wm_flows;
11052 * The maximum number of Exact Match (EM) flows that can be
11053 * offloaded by this function on the RX side.
11055 uint32_t max_rx_em_flows;
11057 * The maximum number of Wildcard Match (WM) flows that can
11058 * be offloaded by this function on the RX side.
11060 uint32_t max_rx_wm_flows;
11062 * The maximum number of multicast filters that can
11063 * be supported by this function on the RX side.
11065 uint32_t max_mcast_filters;
11067 * The maximum value of flow_id that can be supported
11068 * in completion records.
11070 uint32_t max_flow_id;
11072 * The maximum number of HW ring groups that can be
11073 * supported on this function.
11075 uint32_t max_hw_ring_grps;
11077 * The maximum number of strict priority transmit rings
11078 * that can be allocated to the function.
11079 * This number indicates the maximum number of TX rings
11080 * that can be assigned strict priorities out of the
11081 * maximum number of TX rings that can be allocated
11082 * (max_tx_rings) to the function.
11084 uint16_t max_sp_tx_rings;
11085 uint8_t unused_0[2];
11086 uint32_t flags_ext;
11088 * If 1, the device can be configured to set the ECN bits in the
11089 * IP header of received packets if the receive queue length
11090 * exceeds a given threshold.
11092 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
11095 * If 1, the device can report the number of received packets
11096 * that it marked as having experienced congestion.
11098 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
11101 * If 1, the device can report extended hw statistics (including
11102 * additional tpa statistics).
11104 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
11107 * If set to 1, then the core firmware has support to enable/
11108 * disable hot reset support for interface dynamically through
11111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
11113 /* If 1, the proxy mode is supported on this function */
11114 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
11117 * If 1, the tx rings source interface override feature is supported
11118 * on this function.
11120 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
11123 * If 1, the device supports scheduler queues. SCHQs can be managed
11124 * using RING_SCHQ_ALLOC/CFG/FREE commands.
11126 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
11129 * If set to 1, then this function supports the TX push mode that
11130 * uses ping-pong buffers from the push pages.
11132 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
11134 /* The maximum number of SCHQs supported by this device. */
11136 uint8_t mpc_chnls_cap;
11138 * When this bit is '1', it indicates that HW and firmware
11139 * supports the use of a MPC channel with destination set
11140 * to the TX crypto engine block.
11142 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
11144 * When this bit is '1', it indicates that HW and firmware
11145 * supports the use of a MPC channel with destination set
11146 * to the RX crypto engine block.
11148 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
11150 * When this bit is '1', it indicates that HW and firmware
11151 * supports the use of a MPC channel with destination set
11152 * to the TX configurable flow processing block.
11154 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
11156 * When this bit is '1', it indicates that HW and firmware
11157 * supports the use of a MPC channel with destination set
11158 * to the RX configurable flow processing block.
11160 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
11162 * When this bit is '1', it indicates that HW and firmware
11163 * supports the use of a MPC channel with destination set
11164 * to the primate processor block.
11166 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
11169 * This field is used in Output records to indicate that the output
11170 * is completely written to RAM. This field should be read as '1'
11171 * to indicate that the output has been completely written.
11172 * When writing a command completion or response to an internal processor,
11173 * the order of writes has to be such that this field is written last.
11178 /******************
11180 ******************/
11183 /* hwrm_func_qcfg_input (size:192b/24B) */
11184 struct hwrm_func_qcfg_input {
11185 /* The HWRM command request type. */
11188 * The completion ring to send the completion event on. This should
11189 * be the NQ ID returned from the `nq_alloc` HWRM command.
11191 uint16_t cmpl_ring;
11193 * The sequence ID is used by the driver for tracking multiple
11194 * commands. This ID is treated as opaque data by the firmware and
11195 * the value is returned in the `hwrm_resp_hdr` upon completion.
11199 * The target ID of the command:
11200 * * 0x0-0xFFF8 - The function ID
11201 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11202 * * 0xFFFD - Reserved for user-space HWRM interface
11205 uint16_t target_id;
11207 * A physical address pointer pointing to a host buffer that the
11208 * command's response data will be written. This can be either a host
11209 * physical address (HPA) or a guest physical address (GPA) and must
11210 * point to a physically contiguous block of memory.
11212 uint64_t resp_addr;
11214 * Function ID of the function that is being queried.
11215 * 0xFF... (All Fs) if the query is for the requesting
11217 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
11218 * to be used by a trusted VF to query its parent PF.
11221 uint8_t unused_0[6];
11224 /* hwrm_func_qcfg_output (size:768b/96B) */
11225 struct hwrm_func_qcfg_output {
11226 /* The specific error status for the command. */
11227 uint16_t error_code;
11228 /* The HWRM command request type. */
11230 /* The sequence ID from the original command. */
11232 /* The length of the response data in number of bytes. */
11235 * FID value. This value is used to identify operations on the PCI
11236 * bus as belonging to a particular PCI function.
11240 * Port ID of port that this function is associated with.
11241 * 0xFF... (All Fs) if this function is not associated with
11246 * This value is the current VLAN setting for this
11247 * function. The value of 0 for this field indicates
11248 * no priority tagging or VLAN is used.
11249 * This field's format is same as 802.1Q Tag's
11250 * Tag Control Information (TCI) format that includes both
11251 * Priority Code Point (PCP) and VLAN Identifier (VID).
11256 * If 1, then magic packet based Out-Of-Box WoL is enabled on
11257 * the port associated with this function.
11259 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
11262 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
11263 * on the port associated with this function.
11265 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
11268 * If set to 1, then FW based DCBX agent is enabled and running on
11269 * the port associated with this function.
11270 * If set to 0, then DCBX agent is not running in the firmware.
11272 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
11275 * Standard TX Ring mode is used for the allocation of TX ring
11276 * and underlying scheduling resources that allow bandwidth
11277 * reservation and limit settings on the queried function.
11278 * If set to 1, then standard TX ring mode is enabled
11279 * on the queried function.
11280 * If set to 0, then the standard TX ring mode is disabled
11281 * on the queried function. In this extended TX ring resource
11282 * mode, the minimum and maximum bandwidth settings are not
11283 * supported to allow the allocation of TX rings to span multiple
11286 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
11289 * If set to 1 then FW based LLDP agent is enabled and running on
11290 * the port associated with this function.
11291 * If set to 0 then the LLDP agent is not running in the firmware.
11293 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
11296 * If set to 1, then multi-host mode is active for this function.
11297 * If set to 0, then multi-host mode is inactive for this function
11298 * or not applicable for this device.
11300 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
11303 * If the function that is being queried is a PF, then the HWRM shall
11304 * set this field to 0 and the HWRM client shall ignore this field.
11305 * If the function that is being queried is a VF, then the HWRM shall
11306 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
11307 * shall set this field to 0.
11309 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
11312 * If set to 1, then secure mode is enabled for this function or device.
11313 * If set to 0, then secure mode is disabled (or normal mode) for this
11314 * function or device.
11316 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
11319 * If set to 1, then this PF is enabled with a preboot driver that
11320 * requires access to the legacy L2 ring model and legacy 32b
11321 * doorbells. If set to 0, then this PF is not allowed to use
11322 * the legacy L2 rings. This feature is not allowed on VFs and
11323 * is only relevant for devices that require a context backing
11326 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
11329 * If set to 1, then the firmware and all currently registered driver
11330 * instances support hot reset. The hot reset support will be updated
11331 * dynamically based on the driver interface advertisement.
11332 * If set to 0, then the adapter is not currently able to initiate
11335 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
11338 * If set to 1, then the PPP tx push mode is enabled for all the
11339 * reserved TX rings of this function. If set to 0, then PPP tx push
11340 * mode is disabled for all the reserved TX rings of this function.
11342 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
11345 * If set to 1, then the firmware will notify driver using async
11346 * event when a ring is disabled due to a Hardware error.
11348 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
11351 * This value is current MAC address configured for this
11352 * function. A value of 00-00-00-00-00-00 indicates no
11353 * MAC address is currently configured.
11355 uint8_t mac_address[6];
11357 * This value is current PCI ID of this
11358 * function. If ARI is enabled, then it is
11359 * Bus Number (8b):Function Number(8b). Otherwise, it is
11360 * Bus Number (8b):Device Number (4b):Function Number(4b).
11361 * If multi-host mode is active, the 4 lsb will indicate
11362 * the PF index for this function.
11366 * The number of RSS/COS contexts currently
11367 * allocated to the function.
11369 uint16_t alloc_rsscos_ctx;
11371 * The number of completion rings currently allocated to
11372 * the function. This does not include the rings allocated
11373 * to any children functions if any.
11375 uint16_t alloc_cmpl_rings;
11377 * The number of transmit rings currently allocated to
11378 * the function. This does not include the rings allocated
11379 * to any children functions if any.
11381 uint16_t alloc_tx_rings;
11383 * The number of receive rings currently allocated to
11384 * the function. This does not include the rings allocated
11385 * to any children functions if any.
11387 uint16_t alloc_rx_rings;
11388 /* The allocated number of L2 contexts to the function. */
11389 uint16_t alloc_l2_ctx;
11390 /* The allocated number of vnics to the function. */
11391 uint16_t alloc_vnics;
11393 * The maximum transmission unit of the function.
11394 * If the reported mtu value is non-zero then it will used for the
11395 * rings allocated on this function. otherwise the default
11396 * value is used if ring MTU is not specified.
11400 * The maximum receive unit of the function.
11401 * For vnics allocated on this function, this default
11402 * value is used if vnic MRU is not specified.
11405 /* The statistics context assigned to a function. */
11406 uint16_t stat_ctx_id;
11408 * The HWRM shall return Unknown value for this field
11409 * when this command is used to query VF's configuration.
11411 uint8_t port_partition_type;
11412 /* Single physical function */
11413 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
11414 /* Multiple physical functions */
11415 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
11416 /* Network Partitioning 1.0 */
11417 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
11418 /* Network Partitioning 1.5 */
11419 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
11420 /* Network Partitioning 2.0 */
11421 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
11423 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
11425 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
11426 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
11428 * This field will indicate number of physical functions on this port_partition.
11429 * HWRM shall return unavail (i.e. value of 0) for this field
11430 * when this command is used to query VF's configuration or
11431 * from older firmware that doesn't support this field.
11433 uint8_t port_pf_cnt;
11434 /* number of PFs is not available */
11435 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
11436 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
11437 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
11439 * The default VNIC ID assigned to a function that is
11442 uint16_t dflt_vnic_id;
11443 uint16_t max_mtu_configured;
11445 * Minimum BW allocated for this function.
11446 * The HWRM will translate this value into byte counter and
11447 * time interval used for the scheduler inside the device.
11448 * A value of 0 indicates the minimum bandwidth is not
11452 /* The bandwidth value. */
11453 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
11454 UINT32_C(0xfffffff)
11455 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
11456 /* The granularity of the value (bits or bytes). */
11457 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
11458 UINT32_C(0x10000000)
11459 /* Value is in bits. */
11460 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
11461 (UINT32_C(0x0) << 28)
11462 /* Value is in bytes. */
11463 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
11464 (UINT32_C(0x1) << 28)
11465 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
11466 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
11467 /* bw_value_unit is 3 b */
11468 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
11469 UINT32_C(0xe0000000)
11470 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
11471 /* Value is in Mb or MB (base 10). */
11472 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
11473 (UINT32_C(0x0) << 29)
11474 /* Value is in Kb or KB (base 10). */
11475 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
11476 (UINT32_C(0x2) << 29)
11477 /* Value is in bits or bytes. */
11478 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
11479 (UINT32_C(0x4) << 29)
11480 /* Value is in Gb or GB (base 10). */
11481 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
11482 (UINT32_C(0x6) << 29)
11483 /* Value is in 1/100th of a percentage of total bandwidth. */
11484 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
11485 (UINT32_C(0x1) << 29)
11487 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
11488 (UINT32_C(0x7) << 29)
11489 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
11490 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
11492 * Maximum BW allocated for this function.
11493 * The HWRM will translate this value into byte counter and
11494 * time interval used for the scheduler inside the device.
11495 * A value of 0 indicates that the maximum bandwidth is not
11499 /* The bandwidth value. */
11500 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
11501 UINT32_C(0xfffffff)
11502 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
11503 /* The granularity of the value (bits or bytes). */
11504 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
11505 UINT32_C(0x10000000)
11506 /* Value is in bits. */
11507 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
11508 (UINT32_C(0x0) << 28)
11509 /* Value is in bytes. */
11510 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
11511 (UINT32_C(0x1) << 28)
11512 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
11513 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
11514 /* bw_value_unit is 3 b */
11515 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
11516 UINT32_C(0xe0000000)
11517 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
11518 /* Value is in Mb or MB (base 10). */
11519 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
11520 (UINT32_C(0x0) << 29)
11521 /* Value is in Kb or KB (base 10). */
11522 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
11523 (UINT32_C(0x2) << 29)
11524 /* Value is in bits or bytes. */
11525 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
11526 (UINT32_C(0x4) << 29)
11527 /* Value is in Gb or GB (base 10). */
11528 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
11529 (UINT32_C(0x6) << 29)
11530 /* Value is in 1/100th of a percentage of total bandwidth. */
11531 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
11532 (UINT32_C(0x1) << 29)
11534 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
11535 (UINT32_C(0x7) << 29)
11536 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
11537 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
11539 * This value indicates the Edge virtual bridge mode for the
11540 * domain that this function belongs to.
11543 /* No Edge Virtual Bridging (EVB) */
11544 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
11545 /* Virtual Ethernet Bridge (VEB) */
11546 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
11547 /* Virtual Ethernet Port Aggregator (VEPA) */
11548 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
11549 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
11550 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
11553 * This value indicates the PCIE device cache line size.
11554 * The cache line size allows the DMA writes to terminate and
11555 * start at the cache boundary.
11557 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
11559 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
11560 /* Cache Line Size 64 bytes */
11561 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
11563 /* Cache Line Size 128 bytes */
11564 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
11566 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
11567 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
11568 /* This value is the virtual link admin state setting. */
11569 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
11571 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
11572 /* Admin link state is in forced down mode. */
11573 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
11574 (UINT32_C(0x0) << 2)
11575 /* Admin link state is in forced up mode. */
11576 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
11577 (UINT32_C(0x1) << 2)
11578 /* Admin link state is in auto mode - follows the physical link state. */
11579 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
11580 (UINT32_C(0x2) << 2)
11581 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
11582 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
11583 /* Reserved for future. */
11584 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
11586 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
11588 * The number of VFs that are allocated to the function.
11589 * This is valid only on the PF with SR-IOV enabled.
11590 * 0xFF... (All Fs) if this command is called on a PF with
11591 * SR-IOV disabled or on a VF.
11593 uint16_t alloc_vfs;
11595 * The number of allocated multicast filters for this
11596 * function on the RX side.
11598 uint32_t alloc_mcast_filters;
11600 * The number of allocated HW ring groups for this
11603 uint32_t alloc_hw_ring_grps;
11605 * The number of strict priority transmit rings out of
11606 * currently allocated TX rings to the function
11607 * (alloc_tx_rings).
11609 uint16_t alloc_sp_tx_rings;
11611 * The number of statistics contexts
11612 * currently reserved for the function.
11614 uint16_t alloc_stat_ctx;
11616 * This field specifies how many NQs are reserved for the PF.
11617 * Remaining NQs that belong to the PF are available for VFs.
11618 * Once a PF has created VFs, it cannot change how many NQs are
11619 * reserved for itself (since the NQs must be contiguous in HW).
11621 uint16_t alloc_msix;
11623 * The number of registered VF’s associated with the PF. This field
11624 * should be ignored when the request received on the VF interface.
11625 * This field will be updated on the PF interface to initiate
11626 * the unregister request on PF in the HOT Reset Process.
11628 uint16_t registered_vfs;
11630 * The size of the doorbell BAR in KBytes reserved for L2 including
11631 * any area that is shared between L2 and RoCE. The L2 driver
11632 * should only map the L2 portion of the doorbell BAR. Any rounding
11633 * of the BAR size to the native CPU page size should be performed
11634 * by the driver. If the value is zero, no special partitioning
11635 * of the doorbell BAR between L2 and RoCE is required.
11637 uint16_t l2_doorbell_bar_size_kb;
11640 * For backward compatibility this field must be set to 1.
11641 * Older drivers might look for this field to be 1 before
11642 * processing the message.
11646 * This GRC address location is used by the Host driver interfaces to poll
11647 * the adapter ready state to re-initiate the registration process again
11648 * after receiving the RESET Notify event.
11650 uint32_t reset_addr_poll;
11652 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
11653 * this value to find out the doorbell page offset from the BAR.
11655 uint16_t legacy_l2_db_size_kb;
11656 uint16_t svif_info;
11658 * This field specifies the source virtual interface of the function being
11659 * queried. Drivers can use this to program svif field in the L2 context
11662 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
11663 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
11664 /* This field specifies whether svif is valid or not */
11665 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
11668 * When this bit is '1', it indicates that a MPC channel with
11669 * destination set to the TX crypto engine block is enabled.
11671 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
11674 * When this bit is '1', it indicates that a MPC channel with
11675 * destination set to the RX crypto engine block is enabled.
11677 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
11680 * When this bit is '1', it indicates that a MPC channel with
11681 * destination set to the TX configurable flow processing block is
11684 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
11687 * When this bit is '1', it indicates that a MPC channel with
11688 * destination set to the RX configurable flow processing block is
11691 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
11694 * When this bit is '1', it indicates that a MPC channel with
11695 * destination set to the primate processor block is enabled.
11697 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
11699 uint8_t unused_2[6];
11701 * This field is used in Output records to indicate that the output
11702 * is completely written to RAM. This field should be read as '1'
11703 * to indicate that the output has been completely written.
11704 * When writing a command completion or response to an internal processor,
11705 * the order of writes has to be such that this field is written last.
11715 /* hwrm_func_cfg_input (size:768b/96B) */
11716 struct hwrm_func_cfg_input {
11717 /* The HWRM command request type. */
11720 * The completion ring to send the completion event on. This should
11721 * be the NQ ID returned from the `nq_alloc` HWRM command.
11723 uint16_t cmpl_ring;
11725 * The sequence ID is used by the driver for tracking multiple
11726 * commands. This ID is treated as opaque data by the firmware and
11727 * the value is returned in the `hwrm_resp_hdr` upon completion.
11731 * The target ID of the command:
11732 * * 0x0-0xFFF8 - The function ID
11733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11734 * * 0xFFFD - Reserved for user-space HWRM interface
11737 uint16_t target_id;
11739 * A physical address pointer pointing to a host buffer that the
11740 * command's response data will be written. This can be either a host
11741 * physical address (HPA) or a guest physical address (GPA) and must
11742 * point to a physically contiguous block of memory.
11744 uint64_t resp_addr;
11746 * Function ID of the function that is being
11748 * If set to 0xFF... (All Fs), then the configuration is
11749 * for the requesting function.
11753 * This field specifies how many NQs will be reserved for the PF.
11754 * Remaining NQs that belong to the PF become available for VFs.
11755 * Once a PF has created VFs, it cannot change how many NQs are
11756 * reserved for itself (since the NQs must be contiguous in HW).
11761 * When this bit is '1', the function is disabled with
11762 * source MAC address check.
11763 * This is an anti-spoofing check. If this flag is set,
11764 * then the function shall be configured to disallow
11765 * transmission of frames with the source MAC address that
11766 * is configured for this function.
11768 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
11771 * When this bit is '1', the function is enabled with
11772 * source MAC address check.
11773 * This is an anti-spoofing check. If this flag is set,
11774 * then the function shall be configured to allow
11775 * transmission of frames with the source MAC address that
11776 * is configured for this function.
11778 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
11781 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
11783 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
11785 * Standard TX Ring mode is used for the allocation of TX ring
11786 * and underlying scheduling resources that allow bandwidth
11787 * reservation and limit settings on the queried function.
11788 * If set to 1, then standard TX ring mode is requested to be
11789 * enabled on the function being configured.
11791 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
11794 * Standard TX Ring mode is used for the allocation of TX ring
11795 * and underlying scheduling resources that allow bandwidth
11796 * reservation and limit settings on the queried function.
11797 * If set to 1, then the standard TX ring mode is requested to
11798 * be disabled on the function being configured. In this extended
11799 * TX ring resource mode, the minimum and maximum bandwidth settings
11800 * are not supported to allow the allocation of TX rings to
11801 * span multiple scheduler nodes.
11803 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
11806 * If this bit is set, virtual mac address configured
11807 * in this command will be persistent over warm boot.
11809 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
11812 * This bit only applies to the VF. If this bit is set, the statistic
11813 * context counters will not be cleared when the statistic context is freed
11814 * or a function reset is called on VF. This bit will be cleared when the PF
11815 * is unloaded or a function reset is called on the PF.
11817 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
11820 * This bit requests that the firmware test to see if all the assets
11821 * requested in this command (i.e. number of TX rings) are available.
11822 * The firmware will return an error if the requested assets are
11823 * not available. The firwmare will NOT reserve the assets if they
11826 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
11829 * This bit requests that the firmware test to see if all the assets
11830 * requested in this command (i.e. number of RX rings) are available.
11831 * The firmware will return an error if the requested assets are
11832 * not available. The firwmare will NOT reserve the assets if they
11835 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
11838 * This bit requests that the firmware test to see if all the assets
11839 * requested in this command (i.e. number of CMPL rings) are available.
11840 * The firmware will return an error if the requested assets are
11841 * not available. The firwmare will NOT reserve the assets if they
11844 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
11847 * This bit requests that the firmware test to see if all the assets
11848 * requested in this command (i.e. number of RSS ctx) are available.
11849 * The firmware will return an error if the requested assets are
11850 * not available. The firwmare will NOT reserve the assets if they
11853 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
11856 * This bit requests that the firmware test to see if all the assets
11857 * requested in this command (i.e. number of ring groups) are available.
11858 * The firmware will return an error if the requested assets are
11859 * not available. The firwmare will NOT reserve the assets if they
11862 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
11865 * This bit requests that the firmware test to see if all the assets
11866 * requested in this command (i.e. number of stat ctx) are available.
11867 * The firmware will return an error if the requested assets are
11868 * not available. The firwmare will NOT reserve the assets if they
11871 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
11874 * This bit requests that the firmware test to see if all the assets
11875 * requested in this command (i.e. number of VNICs) are available.
11876 * The firmware will return an error if the requested assets are
11877 * not available. The firwmare will NOT reserve the assets if they
11880 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
11883 * This bit requests that the firmware test to see if all the assets
11884 * requested in this command (i.e. number of L2 ctx) are available.
11885 * The firmware will return an error if the requested assets are
11886 * not available. The firwmare will NOT reserve the assets if they
11889 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
11892 * This configuration change can be initiated by a PF driver. This
11893 * configuration request shall be targeted to a VF. From local host
11894 * resident HWRM clients, only the parent PF driver shall be allowed
11895 * to initiate this change on one of its children VFs. If this bit is
11896 * set to 1, then the VF that is being configured is requested to be
11899 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
11902 * When this bit it set, even if PF reserved pool size is zero,
11903 * FW will allow driver to create TX rings in ring alloc,
11904 * by reserving TX ring, S3 node dynamically.
11906 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
11909 * This bit requests that the firmware test to see if all the assets
11910 * requested in this command (i.e. number of NQ rings) are available.
11911 * The firmware will return an error if the requested assets are
11912 * not available. The firwmare will NOT reserve the assets if they
11915 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
11918 * This configuration change can be initiated by a PF driver. This
11919 * configuration request shall be targeted to a VF. From local host
11920 * resident HWRM clients, only the parent PF driver shall be allowed
11921 * to initiate this change on one of its children VFs. If this bit is
11922 * set to 1, then the VF that is being configured is requested to be
11925 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
11926 UINT32_C(0x1000000)
11928 * This bit is used by preboot drivers on a PF that require access
11929 * to the legacy L2 ring model and legacy 32b doorbells. This
11930 * feature is not allowed on VFs and is only relevant for devices
11931 * that require a context backing store.
11933 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
11934 UINT32_C(0x2000000)
11936 * If this bit is set to 0, then the interface does not support hot
11937 * reset capability which it advertised with the hot_reset_support
11938 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
11939 * flag to 0, adapter cannot do the hot reset. In this state, if the
11940 * firmware receives a hot reset request, firmware must fail the
11941 * request. If this bit is set to 1, then interface is renabling the
11942 * hot reset capability.
11944 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
11945 UINT32_C(0x4000000)
11947 * If this bit is set to 1, the PF driver is requesting FW
11948 * to enable PPP TX PUSH feature on all the TX rings specified in
11949 * the num_tx_rings field. By default, the PPP TX push feature is
11950 * disabled for all the TX rings of the function. This flag is
11951 * ignored if num_tx_rings field is not specified or the function
11952 * doesn't support PPP tx push feature.
11954 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
11955 UINT32_C(0x8000000)
11957 * If this bit is set to 1, the PF driver is requesting FW
11958 * to disable PPP TX PUSH feature on all the TX rings specified in
11959 * the num_tx_rings field. This flag is ignored if num_tx_rings
11960 * field is not specified or the function doesn't support PPP tx
11963 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
11964 UINT32_C(0x10000000)
11967 * This bit must be '1' for the mtu field to be
11970 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
11973 * This bit must be '1' for the mru field to be
11976 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
11979 * This bit must be '1' for the num_rsscos_ctxs field to be
11982 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
11985 * This bit must be '1' for the num_cmpl_rings field to be
11988 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
11991 * This bit must be '1' for the num_tx_rings field to be
11994 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
11997 * This bit must be '1' for the num_rx_rings field to be
12000 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
12003 * This bit must be '1' for the num_l2_ctxs field to be
12006 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
12009 * This bit must be '1' for the num_vnics field to be
12012 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
12015 * This bit must be '1' for the num_stat_ctxs field to be
12018 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
12021 * This bit must be '1' for the dflt_mac_addr field to be
12024 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
12027 * This bit must be '1' for the dflt_vlan field to be
12030 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
12033 * This bit must be '1' for the dflt_ip_addr field to be
12036 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
12039 * This bit must be '1' for the min_bw field to be
12042 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
12045 * This bit must be '1' for the max_bw field to be
12048 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
12051 * This bit must be '1' for the async_event_cr field to be
12054 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
12057 * This bit must be '1' for the vlan_antispoof_mode field to be
12060 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
12063 * This bit must be '1' for the allowed_vlan_pris field to be
12066 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
12069 * This bit must be '1' for the evb_mode field to be
12072 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
12075 * This bit must be '1' for the num_mcast_filters field to be
12078 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
12081 * This bit must be '1' for the num_hw_ring_grps field to be
12084 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
12087 * This bit must be '1' for the cache_linesize field to be
12090 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
12093 * This bit must be '1' for the num_msix field to be
12096 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
12099 * This bit must be '1' for the link admin state field to be
12102 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
12105 * This bit must be '1' for the hot_reset_if_en_dis field to be
12108 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
12111 * This bit must be '1' for the schq_id field to be
12114 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
12115 UINT32_C(0x1000000)
12117 * This bit must be '1' for the mpc_chnls field to be
12120 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
12121 UINT32_C(0x2000000)
12123 * The maximum transmission unit of the function.
12124 * The HWRM should make sure that the mtu of
12125 * the function does not exceed the mtu of the physical
12126 * port that this function is associated with.
12128 * In addition to configuring mtu per function, it is
12129 * possible to configure mtu per transmit ring.
12130 * By default, the mtu of each transmit ring associated
12131 * with a function is equal to the mtu of the function.
12132 * The HWRM should make sure that the mtu of each transmit
12133 * ring that is assigned to a function has a valid mtu.
12137 * The maximum receive unit of the function.
12138 * The HWRM should make sure that the mru of
12139 * the function does not exceed the mru of the physical
12140 * port that this function is associated with.
12142 * In addition to configuring mru per function, it is
12143 * possible to configure mru per vnic.
12144 * By default, the mru of each vnic associated
12145 * with a function is equal to the mru of the function.
12146 * The HWRM should make sure that the mru of each vnic
12147 * that is assigned to a function has a valid mru.
12151 * The number of RSS/COS contexts requested for the
12154 uint16_t num_rsscos_ctxs;
12156 * The number of completion rings requested for the
12157 * function. This does not include the rings allocated
12158 * to any children functions if any.
12160 uint16_t num_cmpl_rings;
12162 * The number of transmit rings requested for the function.
12163 * This does not include the rings allocated to any
12164 * children functions if any.
12166 uint16_t num_tx_rings;
12168 * The number of receive rings requested for the function.
12169 * This does not include the rings allocated
12170 * to any children functions if any.
12172 uint16_t num_rx_rings;
12173 /* The requested number of L2 contexts for the function. */
12174 uint16_t num_l2_ctxs;
12175 /* The requested number of vnics for the function. */
12176 uint16_t num_vnics;
12177 /* The requested number of statistic contexts for the function. */
12178 uint16_t num_stat_ctxs;
12180 * The number of HW ring groups that should
12181 * be reserved for this function.
12183 uint16_t num_hw_ring_grps;
12184 /* The default MAC address for the function being configured. */
12185 uint8_t dflt_mac_addr[6];
12187 * The default VLAN for the function being configured.
12188 * This field's format is same as 802.1Q Tag's
12189 * Tag Control Information (TCI) format that includes both
12190 * Priority Code Point (PCP) and VLAN Identifier (VID).
12192 uint16_t dflt_vlan;
12194 * The default IP address for the function being configured.
12195 * This address is only used in enabling source property check.
12197 uint32_t dflt_ip_addr[4];
12199 * Minimum BW allocated for this function.
12200 * The HWRM will translate this value into byte counter and
12201 * time interval used for the scheduler inside the device.
12204 /* The bandwidth value. */
12205 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
12206 UINT32_C(0xfffffff)
12207 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
12208 /* The granularity of the value (bits or bytes). */
12209 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
12210 UINT32_C(0x10000000)
12211 /* Value is in bits. */
12212 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
12213 (UINT32_C(0x0) << 28)
12214 /* Value is in bytes. */
12215 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
12216 (UINT32_C(0x1) << 28)
12217 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
12218 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
12219 /* bw_value_unit is 3 b */
12220 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
12221 UINT32_C(0xe0000000)
12222 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
12223 /* Value is in Mb or MB (base 10). */
12224 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
12225 (UINT32_C(0x0) << 29)
12226 /* Value is in Kb or KB (base 10). */
12227 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
12228 (UINT32_C(0x2) << 29)
12229 /* Value is in bits or bytes. */
12230 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
12231 (UINT32_C(0x4) << 29)
12232 /* Value is in Gb or GB (base 10). */
12233 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
12234 (UINT32_C(0x6) << 29)
12235 /* Value is in 1/100th of a percentage of total bandwidth. */
12236 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12237 (UINT32_C(0x1) << 29)
12239 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
12240 (UINT32_C(0x7) << 29)
12241 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
12242 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
12244 * Maximum BW allocated for this function.
12245 * The HWRM will translate this value into byte counter and
12246 * time interval used for the scheduler inside the device.
12249 /* The bandwidth value. */
12250 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
12251 UINT32_C(0xfffffff)
12252 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
12253 /* The granularity of the value (bits or bytes). */
12254 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
12255 UINT32_C(0x10000000)
12256 /* Value is in bits. */
12257 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
12258 (UINT32_C(0x0) << 28)
12259 /* Value is in bytes. */
12260 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
12261 (UINT32_C(0x1) << 28)
12262 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
12263 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
12264 /* bw_value_unit is 3 b */
12265 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
12266 UINT32_C(0xe0000000)
12267 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
12268 /* Value is in Mb or MB (base 10). */
12269 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
12270 (UINT32_C(0x0) << 29)
12271 /* Value is in Kb or KB (base 10). */
12272 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
12273 (UINT32_C(0x2) << 29)
12274 /* Value is in bits or bytes. */
12275 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
12276 (UINT32_C(0x4) << 29)
12277 /* Value is in Gb or GB (base 10). */
12278 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
12279 (UINT32_C(0x6) << 29)
12280 /* Value is in 1/100th of a percentage of total bandwidth. */
12281 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12282 (UINT32_C(0x1) << 29)
12284 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
12285 (UINT32_C(0x7) << 29)
12286 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
12287 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
12289 * ID of the target completion ring for receiving asynchronous
12290 * event completions. If this field is not valid, then the
12291 * HWRM shall use the default completion ring of the function
12292 * that is being configured as the target completion ring for
12293 * providing any asynchronous event completions for that
12295 * If this field is valid, then the HWRM shall use the
12296 * completion ring identified by this ID as the target
12297 * completion ring for providing any asynchronous event
12298 * completions for the function that is being configured.
12300 uint16_t async_event_cr;
12301 /* VLAN Anti-spoofing mode. */
12302 uint8_t vlan_antispoof_mode;
12303 /* No VLAN anti-spoofing checks are enabled */
12304 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
12306 /* Validate VLAN against the configured VLAN(s) */
12307 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
12309 /* Insert VLAN if it does not exist, otherwise discard */
12310 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
12312 /* Insert VLAN if it does not exist, override VLAN if it exists */
12313 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
12315 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
12316 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
12318 * This bit field defines VLAN PRIs that are allowed on
12320 * If nth bit is set, then VLAN PRI n is allowed on this
12323 uint8_t allowed_vlan_pris;
12325 * The HWRM shall allow a PF driver to change EVB mode for the
12326 * partition it belongs to.
12327 * The HWRM shall not allow a VF driver to change the EVB mode.
12328 * The HWRM shall take into account the switching of EVB mode
12329 * from one to another and reconfigure hardware resources as
12331 * The switching from VEB to VEPA mode requires
12332 * the disabling of the loopback traffic. Additionally,
12333 * source knock outs are handled differently in VEB and VEPA
12337 /* No Edge Virtual Bridging (EVB) */
12338 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
12339 /* Virtual Ethernet Bridge (VEB) */
12340 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
12341 /* Virtual Ethernet Port Aggregator (VEPA) */
12342 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
12343 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
12344 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
12347 * This value indicates the PCIE device cache line size.
12348 * The cache line size allows the DMA writes to terminate and
12349 * start at the cache boundary.
12351 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
12353 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
12354 /* Cache Line Size 64 bytes */
12355 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
12357 /* Cache Line Size 128 bytes */
12358 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
12360 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
12361 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
12362 /* This value is the virtual link admin state setting. */
12363 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
12365 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
12366 /* Admin state is forced down. */
12367 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
12368 (UINT32_C(0x0) << 2)
12369 /* Admin state is forced up. */
12370 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
12371 (UINT32_C(0x1) << 2)
12372 /* Admin state is in auto mode - is to follow the physical link state. */
12373 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
12374 (UINT32_C(0x2) << 2)
12375 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
12376 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
12377 /* Reserved for future. */
12378 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
12380 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
12382 * The number of multicast filters that should
12383 * be reserved for this function on the RX side.
12385 uint16_t num_mcast_filters;
12386 /* Used by a PF driver to associate a SCHQ with a VF. */
12388 uint16_t mpc_chnls;
12390 * When this bit is '1', the caller requests to enable a MPC
12391 * channel with destination to the TX crypto engine block.
12392 * When this bit is ‘0’, this flag has no effect.
12394 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
12396 * When this bit is '1', the caller requests to disable a MPC
12397 * channel with destination to the TX crypto engine block.
12398 * When this bit is ‘0’, this flag has no effect.
12400 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
12402 * When this bit is '1', the caller requests to enable a MPC
12403 * channel with destination to the RX crypto engine block.
12404 * When this bit is ‘0’, this flag has no effect.
12406 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
12408 * When this bit is '1', the caller requests to disable a MPC
12409 * channel with destination to the RX crypto engine block.
12410 * When this bit is ‘0’, this flag has no effect.
12412 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
12414 * When this bit is '1', the caller requests to enable a MPC
12415 * channel with destination to the TX configurable flow processing
12416 * block. When this bit is ‘0’, this flag has no effect.
12418 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
12421 * When this bit is '1', the caller requests to disable a MPC
12422 * channel with destination to the TX configurable flow processing
12423 * block. When this bit is ‘0’, this flag has no effect.
12425 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
12428 * When this bit is '1', the caller requests to enable a MPC
12429 * channel with destination to the RX configurable flow processing
12430 * block. When this bit is ‘0’, this flag has no effect.
12432 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
12435 * When this bit is '1', the caller requests to disable a MPC
12436 * channel with destination to the RX configurable flow processing
12437 * block. When this bit is ‘0’, this flag has no effect.
12439 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
12442 * When this bit is '1', the caller requests to enable a MPC
12443 * channel with destination to the primate processor block.
12444 * When this bit is ‘0’, this flag has no effect.
12446 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
12449 * When this bit is '1', the caller requests to disable a MPC
12450 * channel with destination to the primate processor block.
12451 * When this bit is ‘0’, this flag has no effect.
12453 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
12455 uint8_t unused_0[4];
12458 /* hwrm_func_cfg_output (size:128b/16B) */
12459 struct hwrm_func_cfg_output {
12460 /* The specific error status for the command. */
12461 uint16_t error_code;
12462 /* The HWRM command request type. */
12464 /* The sequence ID from the original command. */
12466 /* The length of the response data in number of bytes. */
12468 uint8_t unused_0[7];
12470 * This field is used in Output records to indicate that the output
12471 * is completely written to RAM. This field should be read as '1'
12472 * to indicate that the output has been completely written.
12473 * When writing a command completion or response to an internal processor,
12474 * the order of writes has to be such that this field is written last.
12479 /********************
12480 * hwrm_func_qstats *
12481 ********************/
12484 /* hwrm_func_qstats_input (size:192b/24B) */
12485 struct hwrm_func_qstats_input {
12486 /* The HWRM command request type. */
12489 * The completion ring to send the completion event on. This should
12490 * be the NQ ID returned from the `nq_alloc` HWRM command.
12492 uint16_t cmpl_ring;
12494 * The sequence ID is used by the driver for tracking multiple
12495 * commands. This ID is treated as opaque data by the firmware and
12496 * the value is returned in the `hwrm_resp_hdr` upon completion.
12500 * The target ID of the command:
12501 * * 0x0-0xFFF8 - The function ID
12502 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12503 * * 0xFFFD - Reserved for user-space HWRM interface
12506 uint16_t target_id;
12508 * A physical address pointer pointing to a host buffer that the
12509 * command's response data will be written. This can be either a host
12510 * physical address (HPA) or a guest physical address (GPA) and must
12511 * point to a physically contiguous block of memory.
12513 uint64_t resp_addr;
12515 * Function ID of the function that is being queried.
12516 * 0xFF... (All Fs) if the query is for the requesting
12518 * A privileged PF can query for other function's statistics.
12521 /* This flags indicates the type of statistics request. */
12523 /* This value is not used to avoid backward compatibility issues. */
12524 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12526 * flags should be set to 1 when request is for only RoCE statistics.
12527 * This will be honored only if the caller_fid is a privileged PF.
12528 * In all other cases FID and caller_fid should be the same.
12530 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12532 * flags should be set to 2 when request is for the counter mask,
12533 * representing the width of each of the stats counters, rather
12534 * than counters themselves.
12536 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12537 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
12538 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
12539 uint8_t unused_0[5];
12542 /* hwrm_func_qstats_output (size:1408b/176B) */
12543 struct hwrm_func_qstats_output {
12544 /* The specific error status for the command. */
12545 uint16_t error_code;
12546 /* The HWRM command request type. */
12548 /* The sequence ID from the original command. */
12550 /* The length of the response data in number of bytes. */
12552 /* Number of transmitted unicast packets on the function. */
12553 uint64_t tx_ucast_pkts;
12554 /* Number of transmitted multicast packets on the function. */
12555 uint64_t tx_mcast_pkts;
12556 /* Number of transmitted broadcast packets on the function. */
12557 uint64_t tx_bcast_pkts;
12559 * Number of transmitted packets that were discarded due to
12560 * internal NIC resource problems. For transmit, this
12561 * can only happen if TMP is configured to allow dropping
12562 * in HOL blocking conditions, which is not a normal
12565 uint64_t tx_discard_pkts;
12567 * Number of dropped packets on transmit path on the function.
12568 * These are packets that have been marked for drop by
12569 * the TE CFA block or are packets that exceeded the
12570 * transmit MTU limit for the function.
12572 uint64_t tx_drop_pkts;
12573 /* Number of transmitted bytes for unicast traffic on the function. */
12574 uint64_t tx_ucast_bytes;
12575 /* Number of transmitted bytes for multicast traffic on the function. */
12576 uint64_t tx_mcast_bytes;
12577 /* Number of transmitted bytes for broadcast traffic on the function. */
12578 uint64_t tx_bcast_bytes;
12579 /* Number of received unicast packets on the function. */
12580 uint64_t rx_ucast_pkts;
12581 /* Number of received multicast packets on the function. */
12582 uint64_t rx_mcast_pkts;
12583 /* Number of received broadcast packets on the function. */
12584 uint64_t rx_bcast_pkts;
12586 * Number of received packets that were discarded on the function
12587 * due to resource limitations. This can happen for 3 reasons.
12588 * # The BD used for the packet has a bad format.
12589 * # There were no BDs available in the ring for the packet.
12590 * # There were no BDs available on-chip for the packet.
12592 uint64_t rx_discard_pkts;
12594 * Number of dropped packets on received path on the function.
12595 * These are packets that have been marked for drop by the
12598 uint64_t rx_drop_pkts;
12599 /* Number of received bytes for unicast traffic on the function. */
12600 uint64_t rx_ucast_bytes;
12601 /* Number of received bytes for multicast traffic on the function. */
12602 uint64_t rx_mcast_bytes;
12603 /* Number of received bytes for broadcast traffic on the function. */
12604 uint64_t rx_bcast_bytes;
12605 /* Number of aggregated unicast packets on the function. */
12606 uint64_t rx_agg_pkts;
12607 /* Number of aggregated unicast bytes on the function. */
12608 uint64_t rx_agg_bytes;
12609 /* Number of aggregation events on the function. */
12610 uint64_t rx_agg_events;
12611 /* Number of aborted aggregations on the function. */
12612 uint64_t rx_agg_aborts;
12613 uint8_t unused_0[7];
12615 * This field is used in Output records to indicate that the output
12616 * is completely written to RAM. This field should be read as '1'
12617 * to indicate that the output has been completely written.
12618 * When writing a command completion or response to an internal processor,
12619 * the order of writes has to be such that this field is written last.
12624 /************************
12625 * hwrm_func_qstats_ext *
12626 ************************/
12629 /* hwrm_func_qstats_ext_input (size:256b/32B) */
12630 struct hwrm_func_qstats_ext_input {
12631 /* The HWRM command request type. */
12634 * The completion ring to send the completion event on. This should
12635 * be the NQ ID returned from the `nq_alloc` HWRM command.
12637 uint16_t cmpl_ring;
12639 * The sequence ID is used by the driver for tracking multiple
12640 * commands. This ID is treated as opaque data by the firmware and
12641 * the value is returned in the `hwrm_resp_hdr` upon completion.
12645 * The target ID of the command:
12646 * * 0x0-0xFFF8 - The function ID
12647 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12648 * * 0xFFFD - Reserved for user-space HWRM interface
12651 uint16_t target_id;
12653 * A physical address pointer pointing to a host buffer that the
12654 * command's response data will be written. This can be either a host
12655 * physical address (HPA) or a guest physical address (GPA) and must
12656 * point to a physically contiguous block of memory.
12658 uint64_t resp_addr;
12660 * Function ID of the function that is being queried.
12661 * 0xFF... (All Fs) if the query is for the requesting
12663 * A privileged PF can query for other function's statistics.
12666 /* This flags indicates the type of statistics request. */
12668 /* This value is not used to avoid backward compatibility issues. */
12669 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12671 * flags should be set to 1 when request is for only RoCE statistics.
12672 * This will be honored only if the caller_fid is a privileged PF.
12673 * In all other cases FID and caller_fid should be the same.
12675 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12677 * flags should be set to 2 when request is for the counter mask
12678 * representing the width of each of the stats counters, rather
12679 * than counters themselves.
12681 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12682 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
12683 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
12684 uint8_t unused_0[1];
12687 * This bit must be '1' for the schq_id and traffic_class fields to
12690 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
12691 /* Specifies the SCHQ for which to gather statistics */
12694 * Specifies the traffic class for which to gather statistics. Valid
12695 * values are 0 through (max_configurable_queues - 1), where
12696 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
12698 uint16_t traffic_class;
12699 uint8_t unused_1[4];
12702 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
12703 struct hwrm_func_qstats_ext_output {
12704 /* The specific error status for the command. */
12705 uint16_t error_code;
12706 /* The HWRM command request type. */
12708 /* The sequence ID from the original command. */
12710 /* The length of the response data in number of bytes. */
12712 /* Number of received unicast packets */
12713 uint64_t rx_ucast_pkts;
12714 /* Number of received multicast packets */
12715 uint64_t rx_mcast_pkts;
12716 /* Number of received broadcast packets */
12717 uint64_t rx_bcast_pkts;
12718 /* Number of discarded packets on received path */
12719 uint64_t rx_discard_pkts;
12720 /* Number of packets on receive path with error */
12721 uint64_t rx_error_pkts;
12722 /* Number of received bytes for unicast traffic */
12723 uint64_t rx_ucast_bytes;
12724 /* Number of received bytes for multicast traffic */
12725 uint64_t rx_mcast_bytes;
12726 /* Number of received bytes for broadcast traffic */
12727 uint64_t rx_bcast_bytes;
12728 /* Number of transmitted unicast packets */
12729 uint64_t tx_ucast_pkts;
12730 /* Number of transmitted multicast packets */
12731 uint64_t tx_mcast_pkts;
12732 /* Number of transmitted broadcast packets */
12733 uint64_t tx_bcast_pkts;
12734 /* Number of packets on transmit path with error */
12735 uint64_t tx_error_pkts;
12736 /* Number of discarded packets on transmit path */
12737 uint64_t tx_discard_pkts;
12738 /* Number of transmitted bytes for unicast traffic */
12739 uint64_t tx_ucast_bytes;
12740 /* Number of transmitted bytes for multicast traffic */
12741 uint64_t tx_mcast_bytes;
12742 /* Number of transmitted bytes for broadcast traffic */
12743 uint64_t tx_bcast_bytes;
12744 /* Number of TPA eligible packets */
12745 uint64_t rx_tpa_eligible_pkt;
12746 /* Number of TPA eligible bytes */
12747 uint64_t rx_tpa_eligible_bytes;
12748 /* Number of TPA packets */
12749 uint64_t rx_tpa_pkt;
12750 /* Number of TPA bytes */
12751 uint64_t rx_tpa_bytes;
12752 /* Number of TPA errors */
12753 uint64_t rx_tpa_errors;
12754 /* Number of TPA errors */
12755 uint64_t rx_tpa_events;
12756 uint8_t unused_0[7];
12758 * This field is used in Output records to indicate that the output
12759 * is completely written to RAM. This field should be read as '1'
12760 * to indicate that the output has been completely written.
12761 * When writing a command completion or response to an internal processor,
12762 * the order of writes has to be such that this field is written last.
12767 /***********************
12768 * hwrm_func_clr_stats *
12769 ***********************/
12772 /* hwrm_func_clr_stats_input (size:192b/24B) */
12773 struct hwrm_func_clr_stats_input {
12774 /* The HWRM command request type. */
12777 * The completion ring to send the completion event on. This should
12778 * be the NQ ID returned from the `nq_alloc` HWRM command.
12780 uint16_t cmpl_ring;
12782 * The sequence ID is used by the driver for tracking multiple
12783 * commands. This ID is treated as opaque data by the firmware and
12784 * the value is returned in the `hwrm_resp_hdr` upon completion.
12788 * The target ID of the command:
12789 * * 0x0-0xFFF8 - The function ID
12790 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12791 * * 0xFFFD - Reserved for user-space HWRM interface
12794 uint16_t target_id;
12796 * A physical address pointer pointing to a host buffer that the
12797 * command's response data will be written. This can be either a host
12798 * physical address (HPA) or a guest physical address (GPA) and must
12799 * point to a physically contiguous block of memory.
12801 uint64_t resp_addr;
12803 * Function ID of the function.
12804 * 0xFF... (All Fs) if the query is for the requesting
12808 uint8_t unused_0[6];
12811 /* hwrm_func_clr_stats_output (size:128b/16B) */
12812 struct hwrm_func_clr_stats_output {
12813 /* The specific error status for the command. */
12814 uint16_t error_code;
12815 /* The HWRM command request type. */
12817 /* The sequence ID from the original command. */
12819 /* The length of the response data in number of bytes. */
12821 uint8_t unused_0[7];
12823 * This field is used in Output records to indicate that the output
12824 * is completely written to RAM. This field should be read as '1'
12825 * to indicate that the output has been completely written.
12826 * When writing a command completion or response to an internal processor,
12827 * the order of writes has to be such that this field is written last.
12832 /**************************
12833 * hwrm_func_vf_resc_free *
12834 **************************/
12837 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
12838 struct hwrm_func_vf_resc_free_input {
12839 /* The HWRM command request type. */
12842 * The completion ring to send the completion event on. This should
12843 * be the NQ ID returned from the `nq_alloc` HWRM command.
12845 uint16_t cmpl_ring;
12847 * The sequence ID is used by the driver for tracking multiple
12848 * commands. This ID is treated as opaque data by the firmware and
12849 * the value is returned in the `hwrm_resp_hdr` upon completion.
12853 * The target ID of the command:
12854 * * 0x0-0xFFF8 - The function ID
12855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12856 * * 0xFFFD - Reserved for user-space HWRM interface
12859 uint16_t target_id;
12861 * A physical address pointer pointing to a host buffer that the
12862 * command's response data will be written. This can be either a host
12863 * physical address (HPA) or a guest physical address (GPA) and must
12864 * point to a physically contiguous block of memory.
12866 uint64_t resp_addr;
12868 * This value is used to identify a Virtual Function (VF).
12869 * The scope of VF ID is local within a PF.
12872 uint8_t unused_0[6];
12875 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
12876 struct hwrm_func_vf_resc_free_output {
12877 /* The specific error status for the command. */
12878 uint16_t error_code;
12879 /* The HWRM command request type. */
12881 /* The sequence ID from the original command. */
12883 /* The length of the response data in number of bytes. */
12885 uint8_t unused_0[7];
12887 * This field is used in Output records to indicate that the output
12888 * is completely written to RAM. This field should be read as '1'
12889 * to indicate that the output has been completely written.
12890 * When writing a command completion or response to an internal processor,
12891 * the order of writes has to be such that this field is written last.
12896 /**********************
12897 * hwrm_func_drv_rgtr *
12898 **********************/
12901 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
12902 struct hwrm_func_drv_rgtr_input {
12903 /* The HWRM command request type. */
12906 * The completion ring to send the completion event on. This should
12907 * be the NQ ID returned from the `nq_alloc` HWRM command.
12909 uint16_t cmpl_ring;
12911 * The sequence ID is used by the driver for tracking multiple
12912 * commands. This ID is treated as opaque data by the firmware and
12913 * the value is returned in the `hwrm_resp_hdr` upon completion.
12917 * The target ID of the command:
12918 * * 0x0-0xFFF8 - The function ID
12919 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12920 * * 0xFFFD - Reserved for user-space HWRM interface
12923 uint16_t target_id;
12925 * A physical address pointer pointing to a host buffer that the
12926 * command's response data will be written. This can be either a host
12927 * physical address (HPA) or a guest physical address (GPA) and must
12928 * point to a physically contiguous block of memory.
12930 uint64_t resp_addr;
12933 * When this bit is '1', the function driver is requesting
12934 * all requests from its children VF drivers to be
12935 * forwarded to itself.
12936 * This flag can only be set by the PF driver.
12937 * If a VF driver sets this flag, it should be ignored
12940 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
12943 * When this bit is '1', the function is requesting none of
12944 * the requests from its children VF drivers to be
12945 * forwarded to itself.
12946 * This flag can only be set by the PF driver.
12947 * If a VF driver sets this flag, it should be ignored
12950 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
12953 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
12954 * fields shall be ignored and ver_maj, ver_min, ver_upd
12955 * and ver_patch shall be used for the driver version information.
12956 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
12957 * fields shall be used for the driver version information and
12958 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
12960 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
12963 * When this bit is '1', the function is indicating support of
12964 * 64bit flow handle. The firmware that only supports 64bit flow
12965 * handle should check this bit before allowing processing of
12966 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
12967 * with 64bit flow handle support can only be compatible with drivers
12968 * that support 64bit flow handle. The legacy drivers that don't support
12969 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
12970 * running with new firmware that only supports 64bit flow handle. The new
12971 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
12972 * status to the legacy driver when encounters these commands.
12974 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
12977 * When this bit is '1', the function is indicating support of
12978 * Hot Reset. The driver interface will destroy the resources,
12979 * unregister the function and register again up on receiving
12980 * the RESET_NOTIFY Async notification from the core firmware.
12981 * The core firmware will this use flag and trigger the Hot Reset
12982 * process only if all the registered driver instances are capable
12985 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
12988 * When this bit is 1, the function is indicating the support of the
12989 * error recovery capability. Error recovery support will be used by
12990 * firmware only if all the driver instances support error recovery
12991 * process. By setting this bit, driver is indicating support for
12992 * corresponding async event completion message. These will be
12993 * delivered to the driver even if they did not register for it.
12994 * If supported, after receiving reset notify async event with fatal
12995 * flag set in event data1, then all the drivers have to tear down
12996 * their resources without sending any HWRM commands to FW.
12998 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
13001 * When this bit is 1, the function is indicating the support of the
13002 * Master capability. The Firmware will use this capability to select the
13003 * Master function. The master function will be used to initiate
13004 * designated functionality like error recovery etc… If none of the
13005 * registered PF’s or trusted VF’s indicate this support, then
13006 * firmware will select the 1st registered PF as Master capable instance.
13008 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
13012 * This bit must be '1' for the os_type field to be
13015 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
13018 * This bit must be '1' for the ver field to be
13021 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
13024 * This bit must be '1' for the timestamp field to be
13027 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
13030 * This bit must be '1' for the vf_req_fwd field to be
13033 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
13036 * This bit must be '1' for the async_event_fwd field to be
13039 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
13041 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13044 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13045 /* Other OS not listed below. */
13046 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
13048 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13050 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13052 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13054 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
13056 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13057 /* VMware ESXi OS. */
13058 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
13059 /* Microsoft Windows 8 64-bit OS. */
13060 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13061 /* Microsoft Windows Server 2012 R2 OS. */
13062 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13064 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13065 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
13066 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
13067 /* This is the 8bit major version of the driver. */
13068 uint8_t ver_maj_8b;
13069 /* This is the 8bit minor version of the driver. */
13070 uint8_t ver_min_8b;
13071 /* This is the 8bit update version of the driver. */
13072 uint8_t ver_upd_8b;
13073 uint8_t unused_0[3];
13075 * This is a 32-bit timestamp provided by the driver for
13077 * The timestamp is in multiples of 1ms.
13079 uint32_t timestamp;
13080 uint8_t unused_1[4];
13082 * This is a 256-bit bit mask provided by the PF driver for
13083 * letting the HWRM know what commands issued by the VF driver
13084 * to the HWRM should be forwarded to the PF driver.
13085 * Nth bit refers to the Nth req_type.
13087 * Setting Nth bit to 1 indicates that requests from the
13088 * VF driver with req_type equal to N shall be forwarded to
13089 * the parent PF driver.
13091 * This field is not valid for the VF driver.
13093 uint32_t vf_req_fwd[8];
13095 * This is a 256-bit bit mask provided by the function driver
13096 * (PF or VF driver) to indicate the list of asynchronous event
13097 * completions to be forwarded.
13099 * Nth bit refers to the Nth event_id.
13101 * Setting Nth bit to 1 by the function driver shall result in
13102 * the HWRM forwarding asynchronous event completion with
13103 * event_id equal to N.
13105 * If all bits are set to 0 (value of 0), then the HWRM shall
13106 * not forward any asynchronous event completion to this
13109 uint32_t async_event_fwd[8];
13110 /* This is the 16bit major version of the driver. */
13112 /* This is the 16bit minor version of the driver. */
13114 /* This is the 16bit update version of the driver. */
13116 /* This is the 16bit patch version of the driver. */
13117 uint16_t ver_patch;
13120 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
13121 struct hwrm_func_drv_rgtr_output {
13122 /* The specific error status for the command. */
13123 uint16_t error_code;
13124 /* The HWRM command request type. */
13126 /* The sequence ID from the original command. */
13128 /* The length of the response data in number of bytes. */
13132 * When this bit is '1', it indicates that the
13133 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
13135 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
13137 uint8_t unused_0[3];
13139 * This field is used in Output records to indicate that the output
13140 * is completely written to RAM. This field should be read as '1'
13141 * to indicate that the output has been completely written.
13142 * When writing a command completion or response to an internal processor,
13143 * the order of writes has to be such that this field is written last.
13148 /************************
13149 * hwrm_func_drv_unrgtr *
13150 ************************/
13153 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
13154 struct hwrm_func_drv_unrgtr_input {
13155 /* The HWRM command request type. */
13158 * The completion ring to send the completion event on. This should
13159 * be the NQ ID returned from the `nq_alloc` HWRM command.
13161 uint16_t cmpl_ring;
13163 * The sequence ID is used by the driver for tracking multiple
13164 * commands. This ID is treated as opaque data by the firmware and
13165 * the value is returned in the `hwrm_resp_hdr` upon completion.
13169 * The target ID of the command:
13170 * * 0x0-0xFFF8 - The function ID
13171 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13172 * * 0xFFFD - Reserved for user-space HWRM interface
13175 uint16_t target_id;
13177 * A physical address pointer pointing to a host buffer that the
13178 * command's response data will be written. This can be either a host
13179 * physical address (HPA) or a guest physical address (GPA) and must
13180 * point to a physically contiguous block of memory.
13182 uint64_t resp_addr;
13185 * When this bit is '1', the function driver is notifying
13186 * the HWRM to prepare for the shutdown.
13188 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
13190 uint8_t unused_0[4];
13193 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
13194 struct hwrm_func_drv_unrgtr_output {
13195 /* The specific error status for the command. */
13196 uint16_t error_code;
13197 /* The HWRM command request type. */
13199 /* The sequence ID from the original command. */
13201 /* The length of the response data in number of bytes. */
13203 uint8_t unused_0[7];
13205 * This field is used in Output records to indicate that the output
13206 * is completely written to RAM. This field should be read as '1'
13207 * to indicate that the output has been completely written.
13208 * When writing a command completion or response to an internal processor,
13209 * the order of writes has to be such that this field is written last.
13214 /**********************
13215 * hwrm_func_buf_rgtr *
13216 **********************/
13219 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
13220 struct hwrm_func_buf_rgtr_input {
13221 /* The HWRM command request type. */
13224 * The completion ring to send the completion event on. This should
13225 * be the NQ ID returned from the `nq_alloc` HWRM command.
13227 uint16_t cmpl_ring;
13229 * The sequence ID is used by the driver for tracking multiple
13230 * commands. This ID is treated as opaque data by the firmware and
13231 * the value is returned in the `hwrm_resp_hdr` upon completion.
13235 * The target ID of the command:
13236 * * 0x0-0xFFF8 - The function ID
13237 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13238 * * 0xFFFD - Reserved for user-space HWRM interface
13241 uint16_t target_id;
13243 * A physical address pointer pointing to a host buffer that the
13244 * command's response data will be written. This can be either a host
13245 * physical address (HPA) or a guest physical address (GPA) and must
13246 * point to a physically contiguous block of memory.
13248 uint64_t resp_addr;
13251 * This bit must be '1' for the vf_id field to be
13254 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13256 * This bit must be '1' for the err_buf_addr field to be
13259 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
13261 * This value is used to identify a Virtual Function (VF).
13262 * The scope of VF ID is local within a PF.
13266 * This field represents the number of pages used for request
13269 uint16_t req_buf_num_pages;
13271 * This field represents the page size used for request
13274 uint16_t req_buf_page_size;
13276 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
13278 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
13280 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
13282 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
13284 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
13286 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
13288 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
13289 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
13290 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
13291 /* The length of the request buffer per VF in bytes. */
13292 uint16_t req_buf_len;
13293 /* The length of the response buffer in bytes. */
13294 uint16_t resp_buf_len;
13295 uint8_t unused_0[2];
13296 /* This field represents the page address of page #0. */
13297 uint64_t req_buf_page_addr0;
13298 /* This field represents the page address of page #1. */
13299 uint64_t req_buf_page_addr1;
13300 /* This field represents the page address of page #2. */
13301 uint64_t req_buf_page_addr2;
13302 /* This field represents the page address of page #3. */
13303 uint64_t req_buf_page_addr3;
13304 /* This field represents the page address of page #4. */
13305 uint64_t req_buf_page_addr4;
13306 /* This field represents the page address of page #5. */
13307 uint64_t req_buf_page_addr5;
13308 /* This field represents the page address of page #6. */
13309 uint64_t req_buf_page_addr6;
13310 /* This field represents the page address of page #7. */
13311 uint64_t req_buf_page_addr7;
13312 /* This field represents the page address of page #8. */
13313 uint64_t req_buf_page_addr8;
13314 /* This field represents the page address of page #9. */
13315 uint64_t req_buf_page_addr9;
13317 * This field is used to receive the error reporting from
13318 * the chipset. Only applicable for PFs.
13320 uint64_t error_buf_addr;
13322 * This field is used to receive the response forwarded by the
13325 uint64_t resp_buf_addr;
13328 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
13329 struct hwrm_func_buf_rgtr_output {
13330 /* The specific error status for the command. */
13331 uint16_t error_code;
13332 /* The HWRM command request type. */
13334 /* The sequence ID from the original command. */
13336 /* The length of the response data in number of bytes. */
13338 uint8_t unused_0[7];
13340 * This field is used in Output records to indicate that the output
13341 * is completely written to RAM. This field should be read as '1'
13342 * to indicate that the output has been completely written.
13343 * When writing a command completion or response to an internal processor,
13344 * the order of writes has to be such that this field is written last.
13349 /************************
13350 * hwrm_func_buf_unrgtr *
13351 ************************/
13354 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
13355 struct hwrm_func_buf_unrgtr_input {
13356 /* The HWRM command request type. */
13359 * The completion ring to send the completion event on. This should
13360 * be the NQ ID returned from the `nq_alloc` HWRM command.
13362 uint16_t cmpl_ring;
13364 * The sequence ID is used by the driver for tracking multiple
13365 * commands. This ID is treated as opaque data by the firmware and
13366 * the value is returned in the `hwrm_resp_hdr` upon completion.
13370 * The target ID of the command:
13371 * * 0x0-0xFFF8 - The function ID
13372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13373 * * 0xFFFD - Reserved for user-space HWRM interface
13376 uint16_t target_id;
13378 * A physical address pointer pointing to a host buffer that the
13379 * command's response data will be written. This can be either a host
13380 * physical address (HPA) or a guest physical address (GPA) and must
13381 * point to a physically contiguous block of memory.
13383 uint64_t resp_addr;
13386 * This bit must be '1' for the vf_id field to be
13389 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13391 * This value is used to identify a Virtual Function (VF).
13392 * The scope of VF ID is local within a PF.
13395 uint8_t unused_0[2];
13398 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
13399 struct hwrm_func_buf_unrgtr_output {
13400 /* The specific error status for the command. */
13401 uint16_t error_code;
13402 /* The HWRM command request type. */
13404 /* The sequence ID from the original command. */
13406 /* The length of the response data in number of bytes. */
13408 uint8_t unused_0[7];
13410 * This field is used in Output records to indicate that the output
13411 * is completely written to RAM. This field should be read as '1'
13412 * to indicate that the output has been completely written.
13413 * When writing a command completion or response to an internal processor,
13414 * the order of writes has to be such that this field is written last.
13419 /**********************
13420 * hwrm_func_drv_qver *
13421 **********************/
13424 /* hwrm_func_drv_qver_input (size:192b/24B) */
13425 struct hwrm_func_drv_qver_input {
13426 /* The HWRM command request type. */
13429 * The completion ring to send the completion event on. This should
13430 * be the NQ ID returned from the `nq_alloc` HWRM command.
13432 uint16_t cmpl_ring;
13434 * The sequence ID is used by the driver for tracking multiple
13435 * commands. This ID is treated as opaque data by the firmware and
13436 * the value is returned in the `hwrm_resp_hdr` upon completion.
13440 * The target ID of the command:
13441 * * 0x0-0xFFF8 - The function ID
13442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13443 * * 0xFFFD - Reserved for user-space HWRM interface
13446 uint16_t target_id;
13448 * A physical address pointer pointing to a host buffer that the
13449 * command's response data will be written. This can be either a host
13450 * physical address (HPA) or a guest physical address (GPA) and must
13451 * point to a physically contiguous block of memory.
13453 uint64_t resp_addr;
13454 /* Reserved for future use. */
13457 * Function ID of the function that is being queried.
13458 * 0xFF... (All Fs) if the query is for the requesting
13462 uint8_t unused_0[2];
13465 /* hwrm_func_drv_qver_output (size:256b/32B) */
13466 struct hwrm_func_drv_qver_output {
13467 /* The specific error status for the command. */
13468 uint16_t error_code;
13469 /* The HWRM command request type. */
13471 /* The sequence ID from the original command. */
13473 /* The length of the response data in number of bytes. */
13475 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13478 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13479 /* Other OS not listed below. */
13480 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
13482 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13484 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13486 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13488 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
13490 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13491 /* VMware ESXi OS. */
13492 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
13493 /* Microsoft Windows 8 64-bit OS. */
13494 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13495 /* Microsoft Windows Server 2012 R2 OS. */
13496 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13498 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13499 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
13500 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
13501 /* This is the 8bit major version of the driver. */
13502 uint8_t ver_maj_8b;
13503 /* This is the 8bit minor version of the driver. */
13504 uint8_t ver_min_8b;
13505 /* This is the 8bit update version of the driver. */
13506 uint8_t ver_upd_8b;
13507 uint8_t unused_0[3];
13508 /* This is the 16bit major version of the driver. */
13510 /* This is the 16bit minor version of the driver. */
13512 /* This is the 16bit update version of the driver. */
13514 /* This is the 16bit patch version of the driver. */
13515 uint16_t ver_patch;
13516 uint8_t unused_1[7];
13518 * This field is used in Output records to indicate that the output
13519 * is completely written to RAM. This field should be read as '1'
13520 * to indicate that the output has been completely written.
13521 * When writing a command completion or response to an internal processor,
13522 * the order of writes has to be such that this field is written last.
13527 /****************************
13528 * hwrm_func_resource_qcaps *
13529 ****************************/
13532 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
13533 struct hwrm_func_resource_qcaps_input {
13534 /* The HWRM command request type. */
13537 * The completion ring to send the completion event on. This should
13538 * be the NQ ID returned from the `nq_alloc` HWRM command.
13540 uint16_t cmpl_ring;
13542 * The sequence ID is used by the driver for tracking multiple
13543 * commands. This ID is treated as opaque data by the firmware and
13544 * the value is returned in the `hwrm_resp_hdr` upon completion.
13548 * The target ID of the command:
13549 * * 0x0-0xFFF8 - The function ID
13550 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13551 * * 0xFFFD - Reserved for user-space HWRM interface
13554 uint16_t target_id;
13556 * A physical address pointer pointing to a host buffer that the
13557 * command's response data will be written. This can be either a host
13558 * physical address (HPA) or a guest physical address (GPA) and must
13559 * point to a physically contiguous block of memory.
13561 uint64_t resp_addr;
13563 * Function ID of the function that is being queried.
13564 * 0xFF... (All Fs) if the query is for the requesting
13568 uint8_t unused_0[6];
13571 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
13572 struct hwrm_func_resource_qcaps_output {
13573 /* The specific error status for the command. */
13574 uint16_t error_code;
13575 /* The HWRM command request type. */
13577 /* The sequence ID from the original command. */
13579 /* The length of the response data in number of bytes. */
13581 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
13583 /* Maximum guaranteed number of MSI-X vectors supported by function */
13585 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
13586 uint16_t vf_reservation_strategy;
13587 /* The PF driver should evenly divide its remaining resources among all VFs. */
13588 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
13590 /* The PF driver should only reserve minimal resources for each VF. */
13591 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
13594 * The PF driver should not reserve any resources for each VF until the
13595 * the VF interface is brought up.
13597 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
13599 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
13600 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
13601 /* Minimum guaranteed number of RSS/COS contexts */
13602 uint16_t min_rsscos_ctx;
13603 /* Maximum non-guaranteed number of RSS/COS contexts */
13604 uint16_t max_rsscos_ctx;
13605 /* Minimum guaranteed number of completion rings */
13606 uint16_t min_cmpl_rings;
13607 /* Maximum non-guaranteed number of completion rings */
13608 uint16_t max_cmpl_rings;
13609 /* Minimum guaranteed number of transmit rings */
13610 uint16_t min_tx_rings;
13611 /* Maximum non-guaranteed number of transmit rings */
13612 uint16_t max_tx_rings;
13613 /* Minimum guaranteed number of receive rings */
13614 uint16_t min_rx_rings;
13615 /* Maximum non-guaranteed number of receive rings */
13616 uint16_t max_rx_rings;
13617 /* Minimum guaranteed number of L2 contexts */
13618 uint16_t min_l2_ctxs;
13619 /* Maximum non-guaranteed number of L2 contexts */
13620 uint16_t max_l2_ctxs;
13621 /* Minimum guaranteed number of VNICs */
13622 uint16_t min_vnics;
13623 /* Maximum non-guaranteed number of VNICs */
13624 uint16_t max_vnics;
13625 /* Minimum guaranteed number of statistic contexts */
13626 uint16_t min_stat_ctx;
13627 /* Maximum non-guaranteed number of statistic contexts */
13628 uint16_t max_stat_ctx;
13629 /* Minimum guaranteed number of ring groups */
13630 uint16_t min_hw_ring_grps;
13631 /* Maximum non-guaranteed number of ring groups */
13632 uint16_t max_hw_ring_grps;
13634 * Maximum number of inputs into the transmit scheduler for this function.
13635 * The number of TX rings assigned to the function cannot exceed this value.
13637 uint16_t max_tx_scheduler_inputs;
13640 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
13641 * feature to reserve all minimum resources when minimum >= 1, otherwise
13642 * returns an error.
13644 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
13646 uint8_t unused_0[5];
13648 * This field is used in Output records to indicate that the output
13649 * is completely written to RAM. This field should be read as '1'
13650 * to indicate that the output has been completely written.
13651 * When writing a command completion or response to an internal processor,
13652 * the order of writes has to be such that this field is written last.
13657 /*****************************
13658 * hwrm_func_vf_resource_cfg *
13659 *****************************/
13662 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
13663 struct hwrm_func_vf_resource_cfg_input {
13664 /* The HWRM command request type. */
13667 * The completion ring to send the completion event on. This should
13668 * be the NQ ID returned from the `nq_alloc` HWRM command.
13670 uint16_t cmpl_ring;
13672 * The sequence ID is used by the driver for tracking multiple
13673 * commands. This ID is treated as opaque data by the firmware and
13674 * the value is returned in the `hwrm_resp_hdr` upon completion.
13678 * The target ID of the command:
13679 * * 0x0-0xFFF8 - The function ID
13680 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13681 * * 0xFFFD - Reserved for user-space HWRM interface
13684 uint16_t target_id;
13686 * A physical address pointer pointing to a host buffer that the
13687 * command's response data will be written. This can be either a host
13688 * physical address (HPA) or a guest physical address (GPA) and must
13689 * point to a physically contiguous block of memory.
13691 uint64_t resp_addr;
13692 /* VF ID that is being configured by PF */
13694 /* Maximum guaranteed number of MSI-X vectors for the function */
13696 /* Minimum guaranteed number of RSS/COS contexts */
13697 uint16_t min_rsscos_ctx;
13698 /* Maximum non-guaranteed number of RSS/COS contexts */
13699 uint16_t max_rsscos_ctx;
13700 /* Minimum guaranteed number of completion rings */
13701 uint16_t min_cmpl_rings;
13702 /* Maximum non-guaranteed number of completion rings */
13703 uint16_t max_cmpl_rings;
13704 /* Minimum guaranteed number of transmit rings */
13705 uint16_t min_tx_rings;
13706 /* Maximum non-guaranteed number of transmit rings */
13707 uint16_t max_tx_rings;
13708 /* Minimum guaranteed number of receive rings */
13709 uint16_t min_rx_rings;
13710 /* Maximum non-guaranteed number of receive rings */
13711 uint16_t max_rx_rings;
13712 /* Minimum guaranteed number of L2 contexts */
13713 uint16_t min_l2_ctxs;
13714 /* Maximum non-guaranteed number of L2 contexts */
13715 uint16_t max_l2_ctxs;
13716 /* Minimum guaranteed number of VNICs */
13717 uint16_t min_vnics;
13718 /* Maximum non-guaranteed number of VNICs */
13719 uint16_t max_vnics;
13720 /* Minimum guaranteed number of statistic contexts */
13721 uint16_t min_stat_ctx;
13722 /* Maximum non-guaranteed number of statistic contexts */
13723 uint16_t max_stat_ctx;
13724 /* Minimum guaranteed number of ring groups */
13725 uint16_t min_hw_ring_grps;
13726 /* Maximum non-guaranteed number of ring groups */
13727 uint16_t max_hw_ring_grps;
13730 * If this bit is set, all minimum resources requested should be
13731 * reserved if minimum >= 1, otherwise return error. In case of
13732 * error, keep all existing reservations before the call.
13734 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
13736 uint8_t unused_0[2];
13739 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
13740 struct hwrm_func_vf_resource_cfg_output {
13741 /* The specific error status for the command. */
13742 uint16_t error_code;
13743 /* The HWRM command request type. */
13745 /* The sequence ID from the original command. */
13747 /* The length of the response data in number of bytes. */
13749 /* Reserved number of RSS/COS contexts */
13750 uint16_t reserved_rsscos_ctx;
13751 /* Reserved number of completion rings */
13752 uint16_t reserved_cmpl_rings;
13753 /* Reserved number of transmit rings */
13754 uint16_t reserved_tx_rings;
13755 /* Reserved number of receive rings */
13756 uint16_t reserved_rx_rings;
13757 /* Reserved number of L2 contexts */
13758 uint16_t reserved_l2_ctxs;
13759 /* Reserved number of VNICs */
13760 uint16_t reserved_vnics;
13761 /* Reserved number of statistic contexts */
13762 uint16_t reserved_stat_ctx;
13763 /* Reserved number of ring groups */
13764 uint16_t reserved_hw_ring_grps;
13765 uint8_t unused_0[7];
13767 * This field is used in Output records to indicate that the output
13768 * is completely written to RAM. This field should be read as '1'
13769 * to indicate that the output has been completely written.
13770 * When writing a command completion or response to an internal processor,
13771 * the order of writes has to be such that this field is written last.
13776 /*********************************
13777 * hwrm_func_backing_store_qcaps *
13778 *********************************/
13781 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
13782 struct hwrm_func_backing_store_qcaps_input {
13783 /* The HWRM command request type. */
13786 * The completion ring to send the completion event on. This should
13787 * be the NQ ID returned from the `nq_alloc` HWRM command.
13789 uint16_t cmpl_ring;
13791 * The sequence ID is used by the driver for tracking multiple
13792 * commands. This ID is treated as opaque data by the firmware and
13793 * the value is returned in the `hwrm_resp_hdr` upon completion.
13797 * The target ID of the command:
13798 * * 0x0-0xFFF8 - The function ID
13799 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13800 * * 0xFFFD - Reserved for user-space HWRM interface
13803 uint16_t target_id;
13805 * A physical address pointer pointing to a host buffer that the
13806 * command's response data will be written. This can be either a host
13807 * physical address (HPA) or a guest physical address (GPA) and must
13808 * point to a physically contiguous block of memory.
13810 uint64_t resp_addr;
13813 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
13814 struct hwrm_func_backing_store_qcaps_output {
13815 /* The specific error status for the command. */
13816 uint16_t error_code;
13817 /* The HWRM command request type. */
13819 /* The sequence ID from the original command. */
13821 /* The length of the response data in number of bytes. */
13823 /* Maximum number of QP context entries supported for this function. */
13824 uint32_t qp_max_entries;
13826 * Minimum number of QP context entries that are needed to be reserved
13827 * for QP1 for the PF and its VFs. PF drivers must allocate at least
13828 * this many QP context entries, even if RoCE will not be used.
13830 uint16_t qp_min_qp1_entries;
13831 /* Maximum number of QP context entries that can be used for L2. */
13832 uint16_t qp_max_l2_entries;
13833 /* Number of bytes that must be allocated for each context entry. */
13834 uint16_t qp_entry_size;
13835 /* Maximum number of SRQ context entries that can be used for L2. */
13836 uint16_t srq_max_l2_entries;
13837 /* Maximum number of SRQ context entries supported for this function. */
13838 uint32_t srq_max_entries;
13839 /* Number of bytes that must be allocated for each context entry. */
13840 uint16_t srq_entry_size;
13841 /* Maximum number of CQ context entries that can be used for L2. */
13842 uint16_t cq_max_l2_entries;
13843 /* Maximum number of CQ context entries supported for this function. */
13844 uint32_t cq_max_entries;
13845 /* Number of bytes that must be allocated for each context entry. */
13846 uint16_t cq_entry_size;
13847 /* Maximum number of VNIC context entries supported for this function. */
13848 uint16_t vnic_max_vnic_entries;
13849 /* Maximum number of Ring table context entries supported for this function. */
13850 uint16_t vnic_max_ring_table_entries;
13851 /* Number of bytes that must be allocated for each context entry. */
13852 uint16_t vnic_entry_size;
13853 /* Maximum number of statistic context entries supported for this function. */
13854 uint32_t stat_max_entries;
13855 /* Number of bytes that must be allocated for each context entry. */
13856 uint16_t stat_entry_size;
13857 /* Number of bytes that must be allocated for each context entry. */
13858 uint16_t tqm_entry_size;
13859 /* Minimum number of TQM context entries required per ring. */
13860 uint32_t tqm_min_entries_per_ring;
13862 * Maximum number of TQM context entries supported per ring. This is
13863 * actually a recommended TQM queue size based on worst case usage of
13866 * TQM fastpath rings should be sized large enough to accommodate the
13867 * maximum number of QPs (either L2 or RoCE, or both if shared)
13868 * that can be enqueued to the TQM ring.
13870 * TQM slowpath rings should be sized as follows:
13872 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
13875 * num_vnics is the number of VNICs allocated in the VNIC backing store
13876 * num_l2_tx_rings is the number of L2 rings in the QP backing store
13877 * num_roce_qps is the number of RoCE QPs in the QP backing store
13878 * tqm_min_size is tqm_min_entries_per_ring reported by
13879 * HWRM_FUNC_BACKING_STORE_QCAPS
13881 * Note that TQM ring sizes cannot be extended while the system is
13882 * operational. If a PF driver needs to extend a TQM ring, it needs
13883 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
13884 * the backing store.
13886 uint32_t tqm_max_entries_per_ring;
13888 * Maximum number of MR plus AV context entries supported for this
13891 uint32_t mrav_max_entries;
13892 /* Number of bytes that must be allocated for each context entry. */
13893 uint16_t mrav_entry_size;
13894 /* Number of bytes that must be allocated for each context entry. */
13895 uint16_t tim_entry_size;
13896 /* Maximum number of Timer context entries supported for this function. */
13897 uint32_t tim_max_entries;
13899 * When this field is zero, the 32b `mrav_num_entries` field in the
13900 * `backing_store_cfg` and `backing_store_qcfg` commands represents
13901 * the total number of MR plus AV entries allowed in the MR/AV backing
13904 * When this field is non-zero, the 32b `mrav_num_entries` field in
13905 * the `backing_store_cfg` and `backing_store_qcfg` commands is
13906 * logically divided into two 16b fields. Bits `[31:16]` represents
13907 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
13908 * Both of these values are represented in a unit granularity
13909 * specified by this field. For example, if this field is 16 and
13910 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
13911 * is 8192 and the number of AV entries is 4096.
13913 uint16_t mrav_num_entries_units;
13915 * The number of entries specified for any TQM ring must be a
13916 * multiple of this value to prevent any resource allocation
13919 uint8_t tqm_entries_multiple;
13921 * Initializer to be used by drivers
13922 * to initialize context memory to ensure
13923 * context subsystem flags an error for an attack
13924 * before the first time context load.
13926 uint8_t ctx_kind_initializer;
13927 /* Reserved for future. */
13929 /* Reserved for future. */
13932 * Count of TQM fastpath rings to be used for allocating backing store.
13933 * Backing store configuration must be specified for each TQM ring from
13934 * this count in `backing_store_cfg`.
13936 uint8_t tqm_fp_rings_count;
13938 * This field is used in Output records to indicate that the output
13939 * is completely written to RAM. This field should be read as '1'
13940 * to indicate that the output has been completely written.
13941 * When writing a command completion or response to an internal processor,
13942 * the order of writes has to be such that this field is written last.
13947 /*******************************
13948 * hwrm_func_backing_store_cfg *
13949 *******************************/
13952 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
13953 struct hwrm_func_backing_store_cfg_input {
13954 /* The HWRM command request type. */
13957 * The completion ring to send the completion event on. This should
13958 * be the NQ ID returned from the `nq_alloc` HWRM command.
13960 uint16_t cmpl_ring;
13962 * The sequence ID is used by the driver for tracking multiple
13963 * commands. This ID is treated as opaque data by the firmware and
13964 * the value is returned in the `hwrm_resp_hdr` upon completion.
13968 * The target ID of the command:
13969 * * 0x0-0xFFF8 - The function ID
13970 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13971 * * 0xFFFD - Reserved for user-space HWRM interface
13974 uint16_t target_id;
13976 * A physical address pointer pointing to a host buffer that the
13977 * command's response data will be written. This can be either a host
13978 * physical address (HPA) or a guest physical address (GPA) and must
13979 * point to a physically contiguous block of memory.
13981 uint64_t resp_addr;
13984 * When set, the firmware only uses on-chip resources and does not
13985 * expect any backing store to be provided by the host driver. This
13986 * mode provides minimal L2 functionality (e.g. limited L2 resources,
13989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
13992 * When set, the 32b `mrav_num_entries` field is logically divided
13993 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
13995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
13999 * This bit must be '1' for the qp fields to be
14002 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
14005 * This bit must be '1' for the srq fields to be
14008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
14011 * This bit must be '1' for the cq fields to be
14014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
14017 * This bit must be '1' for the vnic fields to be
14020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
14023 * This bit must be '1' for the stat fields to be
14026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
14029 * This bit must be '1' for the tqm_sp fields to be
14032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
14035 * This bit must be '1' for the tqm_ring0 fields to be
14038 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
14041 * This bit must be '1' for the tqm_ring1 fields to be
14044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
14047 * This bit must be '1' for the tqm_ring2 fields to be
14050 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
14053 * This bit must be '1' for the tqm_ring3 fields to be
14056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
14059 * This bit must be '1' for the tqm_ring4 fields to be
14062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
14065 * This bit must be '1' for the tqm_ring5 fields to be
14068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
14071 * This bit must be '1' for the tqm_ring6 fields to be
14074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
14077 * This bit must be '1' for the tqm_ring7 fields to be
14080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
14083 * This bit must be '1' for the mrav fields to be
14086 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
14089 * This bit must be '1' for the tim fields to be
14092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
14094 /* QPC page size and level. */
14095 uint8_t qpc_pg_size_qpc_lvl;
14096 /* QPC PBL indirect levels. */
14097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
14099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
14100 /* PBL pointer is physical start address. */
14101 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
14103 /* PBL pointer points to PTE table. */
14104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
14106 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
14109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
14110 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
14111 /* QPC page size. */
14112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
14114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
14116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
14117 (UINT32_C(0x0) << 4)
14119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
14120 (UINT32_C(0x1) << 4)
14122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
14123 (UINT32_C(0x2) << 4)
14125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
14126 (UINT32_C(0x3) << 4)
14128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
14129 (UINT32_C(0x4) << 4)
14131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
14132 (UINT32_C(0x5) << 4)
14133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
14134 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
14135 /* SRQ page size and level. */
14136 uint8_t srq_pg_size_srq_lvl;
14137 /* SRQ PBL indirect levels. */
14138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
14140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
14141 /* PBL pointer is physical start address. */
14142 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
14144 /* PBL pointer points to PTE table. */
14145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
14147 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
14150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
14151 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
14152 /* SRQ page size. */
14153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
14155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
14157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
14158 (UINT32_C(0x0) << 4)
14160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
14161 (UINT32_C(0x1) << 4)
14163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
14164 (UINT32_C(0x2) << 4)
14166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
14167 (UINT32_C(0x3) << 4)
14169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
14170 (UINT32_C(0x4) << 4)
14172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
14173 (UINT32_C(0x5) << 4)
14174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
14175 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
14176 /* CQ page size and level. */
14177 uint8_t cq_pg_size_cq_lvl;
14178 /* CQ PBL indirect levels. */
14179 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
14181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
14182 /* PBL pointer is physical start address. */
14183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
14185 /* PBL pointer points to PTE table. */
14186 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
14188 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
14191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
14192 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
14193 /* CQ page size. */
14194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
14196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
14198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
14199 (UINT32_C(0x0) << 4)
14201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
14202 (UINT32_C(0x1) << 4)
14204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
14205 (UINT32_C(0x2) << 4)
14207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
14208 (UINT32_C(0x3) << 4)
14210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
14211 (UINT32_C(0x4) << 4)
14213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
14214 (UINT32_C(0x5) << 4)
14215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
14216 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
14217 /* VNIC page size and level. */
14218 uint8_t vnic_pg_size_vnic_lvl;
14219 /* VNIC PBL indirect levels. */
14220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
14222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
14223 /* PBL pointer is physical start address. */
14224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
14226 /* PBL pointer points to PTE table. */
14227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
14229 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
14232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
14233 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
14234 /* VNIC page size. */
14235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
14237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
14239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
14240 (UINT32_C(0x0) << 4)
14242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
14243 (UINT32_C(0x1) << 4)
14245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
14246 (UINT32_C(0x2) << 4)
14248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
14249 (UINT32_C(0x3) << 4)
14251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
14252 (UINT32_C(0x4) << 4)
14254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
14255 (UINT32_C(0x5) << 4)
14256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
14257 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
14258 /* Stat page size and level. */
14259 uint8_t stat_pg_size_stat_lvl;
14260 /* Stat PBL indirect levels. */
14261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
14263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
14264 /* PBL pointer is physical start address. */
14265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
14267 /* PBL pointer points to PTE table. */
14268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
14270 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
14273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
14274 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
14275 /* Stat page size. */
14276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
14278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
14280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
14281 (UINT32_C(0x0) << 4)
14283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
14284 (UINT32_C(0x1) << 4)
14286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
14287 (UINT32_C(0x2) << 4)
14289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
14290 (UINT32_C(0x3) << 4)
14292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
14293 (UINT32_C(0x4) << 4)
14295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
14296 (UINT32_C(0x5) << 4)
14297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
14298 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
14299 /* TQM slow path page size and level. */
14300 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
14301 /* TQM slow path PBL indirect levels. */
14302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
14304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
14305 /* PBL pointer is physical start address. */
14306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
14308 /* PBL pointer points to PTE table. */
14309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
14311 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
14314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
14315 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
14316 /* TQM slow path page size. */
14317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
14319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
14321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
14322 (UINT32_C(0x0) << 4)
14324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
14325 (UINT32_C(0x1) << 4)
14327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
14328 (UINT32_C(0x2) << 4)
14330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
14331 (UINT32_C(0x3) << 4)
14333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
14334 (UINT32_C(0x4) << 4)
14336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
14337 (UINT32_C(0x5) << 4)
14338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
14339 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
14340 /* TQM ring 0 page size and level. */
14341 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
14342 /* TQM ring 0 PBL indirect levels. */
14343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
14345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
14346 /* PBL pointer is physical start address. */
14347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
14349 /* PBL pointer points to PTE table. */
14350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
14352 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
14355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
14356 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
14357 /* TQM ring 0 page size. */
14358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
14360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
14362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
14363 (UINT32_C(0x0) << 4)
14365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
14366 (UINT32_C(0x1) << 4)
14368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
14369 (UINT32_C(0x2) << 4)
14371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
14372 (UINT32_C(0x3) << 4)
14374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
14375 (UINT32_C(0x4) << 4)
14377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
14378 (UINT32_C(0x5) << 4)
14379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
14380 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
14381 /* TQM ring 1 page size and level. */
14382 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
14383 /* TQM ring 1 PBL indirect levels. */
14384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
14386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
14387 /* PBL pointer is physical start address. */
14388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
14390 /* PBL pointer points to PTE table. */
14391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
14393 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
14396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
14397 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
14398 /* TQM ring 1 page size. */
14399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
14401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
14403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
14404 (UINT32_C(0x0) << 4)
14406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
14407 (UINT32_C(0x1) << 4)
14409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
14410 (UINT32_C(0x2) << 4)
14412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
14413 (UINT32_C(0x3) << 4)
14415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
14416 (UINT32_C(0x4) << 4)
14418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
14419 (UINT32_C(0x5) << 4)
14420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
14421 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
14422 /* TQM ring 2 page size and level. */
14423 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
14424 /* TQM ring 2 PBL indirect levels. */
14425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
14427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
14428 /* PBL pointer is physical start address. */
14429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
14431 /* PBL pointer points to PTE table. */
14432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
14434 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
14437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
14438 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
14439 /* TQM ring 2 page size. */
14440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
14442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
14444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
14445 (UINT32_C(0x0) << 4)
14447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
14448 (UINT32_C(0x1) << 4)
14450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
14451 (UINT32_C(0x2) << 4)
14453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
14454 (UINT32_C(0x3) << 4)
14456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
14457 (UINT32_C(0x4) << 4)
14459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
14460 (UINT32_C(0x5) << 4)
14461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
14462 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
14463 /* TQM ring 3 page size and level. */
14464 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
14465 /* TQM ring 3 PBL indirect levels. */
14466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
14468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
14469 /* PBL pointer is physical start address. */
14470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
14472 /* PBL pointer points to PTE table. */
14473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
14475 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
14478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
14479 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
14480 /* TQM ring 3 page size. */
14481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
14483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
14485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
14486 (UINT32_C(0x0) << 4)
14488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
14489 (UINT32_C(0x1) << 4)
14491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
14492 (UINT32_C(0x2) << 4)
14494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
14495 (UINT32_C(0x3) << 4)
14497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
14498 (UINT32_C(0x4) << 4)
14500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
14501 (UINT32_C(0x5) << 4)
14502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
14503 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
14504 /* TQM ring 4 page size and level. */
14505 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
14506 /* TQM ring 4 PBL indirect levels. */
14507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
14509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
14510 /* PBL pointer is physical start address. */
14511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
14513 /* PBL pointer points to PTE table. */
14514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
14516 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
14519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
14520 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
14521 /* TQM ring 4 page size. */
14522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
14524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
14526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
14527 (UINT32_C(0x0) << 4)
14529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
14530 (UINT32_C(0x1) << 4)
14532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
14533 (UINT32_C(0x2) << 4)
14535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
14536 (UINT32_C(0x3) << 4)
14538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
14539 (UINT32_C(0x4) << 4)
14541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
14542 (UINT32_C(0x5) << 4)
14543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
14544 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
14545 /* TQM ring 5 page size and level. */
14546 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
14547 /* TQM ring 5 PBL indirect levels. */
14548 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
14550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
14551 /* PBL pointer is physical start address. */
14552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
14554 /* PBL pointer points to PTE table. */
14555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
14557 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
14560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
14561 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
14562 /* TQM ring 5 page size. */
14563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
14565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
14567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
14568 (UINT32_C(0x0) << 4)
14570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
14571 (UINT32_C(0x1) << 4)
14573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
14574 (UINT32_C(0x2) << 4)
14576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
14577 (UINT32_C(0x3) << 4)
14579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
14580 (UINT32_C(0x4) << 4)
14582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
14583 (UINT32_C(0x5) << 4)
14584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
14585 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
14586 /* TQM ring 6 page size and level. */
14587 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
14588 /* TQM ring 6 PBL indirect levels. */
14589 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
14591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
14592 /* PBL pointer is physical start address. */
14593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
14595 /* PBL pointer points to PTE table. */
14596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
14598 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
14601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
14602 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
14603 /* TQM ring 6 page size. */
14604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
14606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
14608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
14609 (UINT32_C(0x0) << 4)
14611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
14612 (UINT32_C(0x1) << 4)
14614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
14615 (UINT32_C(0x2) << 4)
14617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
14618 (UINT32_C(0x3) << 4)
14620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
14621 (UINT32_C(0x4) << 4)
14623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
14624 (UINT32_C(0x5) << 4)
14625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
14626 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
14627 /* TQM ring 7 page size and level. */
14628 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
14629 /* TQM ring 7 PBL indirect levels. */
14630 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
14632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
14633 /* PBL pointer is physical start address. */
14634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
14636 /* PBL pointer points to PTE table. */
14637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
14639 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14640 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
14642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
14643 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
14644 /* TQM ring 7 page size. */
14645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
14647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
14649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
14650 (UINT32_C(0x0) << 4)
14652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
14653 (UINT32_C(0x1) << 4)
14655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
14656 (UINT32_C(0x2) << 4)
14658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
14659 (UINT32_C(0x3) << 4)
14661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
14662 (UINT32_C(0x4) << 4)
14664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
14665 (UINT32_C(0x5) << 4)
14666 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
14667 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
14668 /* MR/AV page size and level. */
14669 uint8_t mrav_pg_size_mrav_lvl;
14670 /* MR/AV PBL indirect levels. */
14671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
14673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
14674 /* PBL pointer is physical start address. */
14675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
14677 /* PBL pointer points to PTE table. */
14678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
14680 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
14683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
14684 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
14685 /* MR/AV page size. */
14686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
14688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
14690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
14691 (UINT32_C(0x0) << 4)
14693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
14694 (UINT32_C(0x1) << 4)
14696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
14697 (UINT32_C(0x2) << 4)
14699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
14700 (UINT32_C(0x3) << 4)
14702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
14703 (UINT32_C(0x4) << 4)
14705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
14706 (UINT32_C(0x5) << 4)
14707 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
14708 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
14709 /* Timer page size and level. */
14710 uint8_t tim_pg_size_tim_lvl;
14711 /* Timer PBL indirect levels. */
14712 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
14714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
14715 /* PBL pointer is physical start address. */
14716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
14718 /* PBL pointer points to PTE table. */
14719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
14721 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
14724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
14725 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
14726 /* Timer page size. */
14727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
14729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
14731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
14732 (UINT32_C(0x0) << 4)
14734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
14735 (UINT32_C(0x1) << 4)
14737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
14738 (UINT32_C(0x2) << 4)
14740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
14741 (UINT32_C(0x3) << 4)
14743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
14744 (UINT32_C(0x4) << 4)
14746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
14747 (UINT32_C(0x5) << 4)
14748 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
14749 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
14750 /* QP page directory. */
14751 uint64_t qpc_page_dir;
14752 /* SRQ page directory. */
14753 uint64_t srq_page_dir;
14754 /* CQ page directory. */
14755 uint64_t cq_page_dir;
14756 /* VNIC page directory. */
14757 uint64_t vnic_page_dir;
14758 /* Stat page directory. */
14759 uint64_t stat_page_dir;
14760 /* TQM slowpath page directory. */
14761 uint64_t tqm_sp_page_dir;
14762 /* TQM ring 0 page directory. */
14763 uint64_t tqm_ring0_page_dir;
14764 /* TQM ring 1 page directory. */
14765 uint64_t tqm_ring1_page_dir;
14766 /* TQM ring 2 page directory. */
14767 uint64_t tqm_ring2_page_dir;
14768 /* TQM ring 3 page directory. */
14769 uint64_t tqm_ring3_page_dir;
14770 /* TQM ring 4 page directory. */
14771 uint64_t tqm_ring4_page_dir;
14772 /* TQM ring 5 page directory. */
14773 uint64_t tqm_ring5_page_dir;
14774 /* TQM ring 6 page directory. */
14775 uint64_t tqm_ring6_page_dir;
14776 /* TQM ring 7 page directory. */
14777 uint64_t tqm_ring7_page_dir;
14778 /* MR/AV page directory. */
14779 uint64_t mrav_page_dir;
14780 /* Timer page directory. */
14781 uint64_t tim_page_dir;
14782 /* Number of QPs. */
14783 uint32_t qp_num_entries;
14784 /* Number of SRQs. */
14785 uint32_t srq_num_entries;
14786 /* Number of CQs. */
14787 uint32_t cq_num_entries;
14788 /* Number of Stats. */
14789 uint32_t stat_num_entries;
14791 * Number of TQM slowpath entries.
14793 * TQM slowpath rings should be sized as follows:
14795 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
14798 * num_vnics is the number of VNICs allocated in the VNIC backing store
14799 * num_l2_tx_rings is the number of L2 rings in the QP backing store
14800 * num_roce_qps is the number of RoCE QPs in the QP backing store
14801 * tqm_min_size is tqm_min_entries_per_ring reported by
14802 * HWRM_FUNC_BACKING_STORE_QCAPS
14804 * Note that TQM ring sizes cannot be extended while the system is
14805 * operational. If a PF driver needs to extend a TQM ring, it needs
14806 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14807 * the backing store.
14809 uint32_t tqm_sp_num_entries;
14811 * Number of TQM ring 0 entries.
14813 * TQM fastpath rings should be sized large enough to accommodate the
14814 * maximum number of QPs (either L2 or RoCE, or both if shared)
14815 * that can be enqueued to the TQM ring.
14817 * Note that TQM ring sizes cannot be extended while the system is
14818 * operational. If a PF driver needs to extend a TQM ring, it needs
14819 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14820 * the backing store.
14822 uint32_t tqm_ring0_num_entries;
14824 * Number of TQM ring 1 entries.
14826 * TQM fastpath rings should be sized large enough to accommodate the
14827 * maximum number of QPs (either L2 or RoCE, or both if shared)
14828 * that can be enqueued to the TQM ring.
14830 * Note that TQM ring sizes cannot be extended while the system is
14831 * operational. If a PF driver needs to extend a TQM ring, it needs
14832 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14833 * the backing store.
14835 uint32_t tqm_ring1_num_entries;
14837 * Number of TQM ring 2 entries.
14839 * TQM fastpath rings should be sized large enough to accommodate the
14840 * maximum number of QPs (either L2 or RoCE, or both if shared)
14841 * that can be enqueued to the TQM ring.
14843 * Note that TQM ring sizes cannot be extended while the system is
14844 * operational. If a PF driver needs to extend a TQM ring, it needs
14845 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14846 * the backing store.
14848 uint32_t tqm_ring2_num_entries;
14850 * Number of TQM ring 3 entries.
14852 * TQM fastpath rings should be sized large enough to accommodate the
14853 * maximum number of QPs (either L2 or RoCE, or both if shared)
14854 * that can be enqueued to the TQM ring.
14856 * Note that TQM ring sizes cannot be extended while the system is
14857 * operational. If a PF driver needs to extend a TQM ring, it needs
14858 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14859 * the backing store.
14861 uint32_t tqm_ring3_num_entries;
14863 * Number of TQM ring 4 entries.
14865 * TQM fastpath rings should be sized large enough to accommodate the
14866 * maximum number of QPs (either L2 or RoCE, or both if shared)
14867 * that can be enqueued to the TQM ring.
14869 * Note that TQM ring sizes cannot be extended while the system is
14870 * operational. If a PF driver needs to extend a TQM ring, it needs
14871 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14872 * the backing store.
14874 uint32_t tqm_ring4_num_entries;
14876 * Number of TQM ring 5 entries.
14878 * TQM fastpath rings should be sized large enough to accommodate the
14879 * maximum number of QPs (either L2 or RoCE, or both if shared)
14880 * that can be enqueued to the TQM ring.
14882 * Note that TQM ring sizes cannot be extended while the system is
14883 * operational. If a PF driver needs to extend a TQM ring, it needs
14884 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14885 * the backing store.
14887 uint32_t tqm_ring5_num_entries;
14889 * Number of TQM ring 6 entries.
14891 * TQM fastpath rings should be sized large enough to accommodate the
14892 * maximum number of QPs (either L2 or RoCE, or both if shared)
14893 * that can be enqueued to the TQM ring.
14895 * Note that TQM ring sizes cannot be extended while the system is
14896 * operational. If a PF driver needs to extend a TQM ring, it needs
14897 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14898 * the backing store.
14900 uint32_t tqm_ring6_num_entries;
14902 * Number of TQM ring 7 entries.
14904 * TQM fastpath rings should be sized large enough to accommodate the
14905 * maximum number of QPs (either L2 or RoCE, or both if shared)
14906 * that can be enqueued to the TQM ring.
14908 * Note that TQM ring sizes cannot be extended while the system is
14909 * operational. If a PF driver needs to extend a TQM ring, it needs
14910 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14911 * the backing store.
14913 uint32_t tqm_ring7_num_entries;
14915 * If the MR/AV split reservation flag is not set, then this field
14916 * represents the total number of MR plus AV entries. For versions
14917 * of firmware that support the split reservation, when it is not
14918 * specified half of the entries will be reserved for MRs and the
14919 * other half for AVs.
14921 * If the MR/AV split reservation flag is set, then this
14922 * field is logically divided into two 16b fields. Bits `[31:16]`
14923 * represents the `mr_num_entries` and bits `[15:0]` represents
14924 * `av_num_entries`. The granularity of these values is defined by
14925 * the `mrav_num_entries_unit` field returned by the
14926 * `backing_store_qcaps` command.
14928 uint32_t mrav_num_entries;
14929 /* Number of Timer entries. */
14930 uint32_t tim_num_entries;
14931 /* Number of entries to reserve for QP1 */
14932 uint16_t qp_num_qp1_entries;
14933 /* Number of entries to reserve for L2 */
14934 uint16_t qp_num_l2_entries;
14935 /* Number of bytes that have been allocated for each context entry. */
14936 uint16_t qp_entry_size;
14937 /* Number of entries to reserve for L2 */
14938 uint16_t srq_num_l2_entries;
14939 /* Number of bytes that have been allocated for each context entry. */
14940 uint16_t srq_entry_size;
14941 /* Number of entries to reserve for L2 */
14942 uint16_t cq_num_l2_entries;
14943 /* Number of bytes that have been allocated for each context entry. */
14944 uint16_t cq_entry_size;
14945 /* Number of entries to reserve for VNIC entries */
14946 uint16_t vnic_num_vnic_entries;
14947 /* Number of entries to reserve for Ring table entries */
14948 uint16_t vnic_num_ring_table_entries;
14949 /* Number of bytes that have been allocated for each context entry. */
14950 uint16_t vnic_entry_size;
14951 /* Number of bytes that have been allocated for each context entry. */
14952 uint16_t stat_entry_size;
14953 /* Number of bytes that have been allocated for each context entry. */
14954 uint16_t tqm_entry_size;
14955 /* Number of bytes that have been allocated for each context entry. */
14956 uint16_t mrav_entry_size;
14957 /* Number of bytes that have been allocated for each context entry. */
14958 uint16_t tim_entry_size;
14961 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
14962 struct hwrm_func_backing_store_cfg_output {
14963 /* The specific error status for the command. */
14964 uint16_t error_code;
14965 /* The HWRM command request type. */
14967 /* The sequence ID from the original command. */
14969 /* The length of the response data in number of bytes. */
14971 uint8_t unused_0[7];
14973 * This field is used in Output records to indicate that the output
14974 * is completely written to RAM. This field should be read as '1'
14975 * to indicate that the output has been completely written.
14976 * When writing a command completion or response to an internal processor,
14977 * the order of writes has to be such that this field is written last.
14982 /********************************
14983 * hwrm_func_backing_store_qcfg *
14984 ********************************/
14987 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
14988 struct hwrm_func_backing_store_qcfg_input {
14989 /* The HWRM command request type. */
14992 * The completion ring to send the completion event on. This should
14993 * be the NQ ID returned from the `nq_alloc` HWRM command.
14995 uint16_t cmpl_ring;
14997 * The sequence ID is used by the driver for tracking multiple
14998 * commands. This ID is treated as opaque data by the firmware and
14999 * the value is returned in the `hwrm_resp_hdr` upon completion.
15003 * The target ID of the command:
15004 * * 0x0-0xFFF8 - The function ID
15005 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15006 * * 0xFFFD - Reserved for user-space HWRM interface
15009 uint16_t target_id;
15011 * A physical address pointer pointing to a host buffer that the
15012 * command's response data will be written. This can be either a host
15013 * physical address (HPA) or a guest physical address (GPA) and must
15014 * point to a physically contiguous block of memory.
15016 uint64_t resp_addr;
15019 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
15020 struct hwrm_func_backing_store_qcfg_output {
15021 /* The specific error status for the command. */
15022 uint16_t error_code;
15023 /* The HWRM command request type. */
15025 /* The sequence ID from the original command. */
15027 /* The length of the response data in number of bytes. */
15031 * When set, the firmware only uses on-chip resources and does not
15032 * expect any backing store to be provided by the host driver. This
15033 * mode provides minimal L2 functionality (e.g. limited L2 resources,
15036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
15039 * When set, the 32b `mrav_num_entries` field is logically divided
15040 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
15042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
15044 uint8_t unused_0[4];
15046 * This bit must be '1' for the qp fields to be
15049 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
15052 * This bit must be '1' for the srq fields to be
15055 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
15058 * This bit must be '1' for the cq fields to be
15061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
15064 * This bit must be '1' for the vnic fields to be
15067 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
15070 * This bit must be '1' for the stat fields to be
15073 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
15076 * This bit must be '1' for the tqm_sp fields to be
15079 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
15082 * This bit must be '1' for the tqm_ring0 fields to be
15085 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
15088 * This bit must be '1' for the tqm_ring1 fields to be
15091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
15094 * This bit must be '1' for the tqm_ring2 fields to be
15097 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
15100 * This bit must be '1' for the tqm_ring3 fields to be
15103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
15106 * This bit must be '1' for the tqm_ring4 fields to be
15109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
15112 * This bit must be '1' for the tqm_ring5 fields to be
15115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
15118 * This bit must be '1' for the tqm_ring6 fields to be
15121 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
15124 * This bit must be '1' for the tqm_ring7 fields to be
15127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
15130 * This bit must be '1' for the mrav fields to be
15133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
15136 * This bit must be '1' for the tim fields to be
15139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
15141 /* QPC page size and level. */
15142 uint8_t qpc_pg_size_qpc_lvl;
15143 /* QPC PBL indirect levels. */
15144 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
15146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
15147 /* PBL pointer is physical start address. */
15148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
15150 /* PBL pointer points to PTE table. */
15151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
15153 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
15156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
15157 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
15158 /* QPC page size. */
15159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
15161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
15163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
15164 (UINT32_C(0x0) << 4)
15166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
15167 (UINT32_C(0x1) << 4)
15169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
15170 (UINT32_C(0x2) << 4)
15172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
15173 (UINT32_C(0x3) << 4)
15175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
15176 (UINT32_C(0x4) << 4)
15178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
15179 (UINT32_C(0x5) << 4)
15180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
15181 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
15182 /* SRQ page size and level. */
15183 uint8_t srq_pg_size_srq_lvl;
15184 /* SRQ PBL indirect levels. */
15185 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
15187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
15188 /* PBL pointer is physical start address. */
15189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
15191 /* PBL pointer points to PTE table. */
15192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
15194 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15195 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
15197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
15198 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
15199 /* SRQ page size. */
15200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
15202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
15204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
15205 (UINT32_C(0x0) << 4)
15207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
15208 (UINT32_C(0x1) << 4)
15210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
15211 (UINT32_C(0x2) << 4)
15213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
15214 (UINT32_C(0x3) << 4)
15216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
15217 (UINT32_C(0x4) << 4)
15219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
15220 (UINT32_C(0x5) << 4)
15221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
15222 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
15223 /* CQ page size and level. */
15224 uint8_t cq_pg_size_cq_lvl;
15225 /* CQ PBL indirect levels. */
15226 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
15228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
15229 /* PBL pointer is physical start address. */
15230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
15232 /* PBL pointer points to PTE table. */
15233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
15235 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15236 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
15238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
15239 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
15240 /* CQ page size. */
15241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
15243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
15245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
15246 (UINT32_C(0x0) << 4)
15248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
15249 (UINT32_C(0x1) << 4)
15251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
15252 (UINT32_C(0x2) << 4)
15254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
15255 (UINT32_C(0x3) << 4)
15257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
15258 (UINT32_C(0x4) << 4)
15260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
15261 (UINT32_C(0x5) << 4)
15262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
15263 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
15264 /* VNIC page size and level. */
15265 uint8_t vnic_pg_size_vnic_lvl;
15266 /* VNIC PBL indirect levels. */
15267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
15269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
15270 /* PBL pointer is physical start address. */
15271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
15273 /* PBL pointer points to PTE table. */
15274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
15276 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15277 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
15279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
15280 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
15281 /* VNIC page size. */
15282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
15284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
15286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
15287 (UINT32_C(0x0) << 4)
15289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
15290 (UINT32_C(0x1) << 4)
15292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
15293 (UINT32_C(0x2) << 4)
15295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
15296 (UINT32_C(0x3) << 4)
15298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
15299 (UINT32_C(0x4) << 4)
15301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
15302 (UINT32_C(0x5) << 4)
15303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
15304 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
15305 /* Stat page size and level. */
15306 uint8_t stat_pg_size_stat_lvl;
15307 /* Stat PBL indirect levels. */
15308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
15310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
15311 /* PBL pointer is physical start address. */
15312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
15314 /* PBL pointer points to PTE table. */
15315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
15317 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
15320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
15321 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
15322 /* Stat page size. */
15323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
15325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
15327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
15328 (UINT32_C(0x0) << 4)
15330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
15331 (UINT32_C(0x1) << 4)
15333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
15334 (UINT32_C(0x2) << 4)
15336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
15337 (UINT32_C(0x3) << 4)
15339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
15340 (UINT32_C(0x4) << 4)
15342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
15343 (UINT32_C(0x5) << 4)
15344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
15345 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
15346 /* TQM slow path page size and level. */
15347 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
15348 /* TQM slow path PBL indirect levels. */
15349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
15351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
15352 /* PBL pointer is physical start address. */
15353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
15355 /* PBL pointer points to PTE table. */
15356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
15358 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
15361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
15362 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
15363 /* TQM slow path page size. */
15364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
15366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
15368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
15369 (UINT32_C(0x0) << 4)
15371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
15372 (UINT32_C(0x1) << 4)
15374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
15375 (UINT32_C(0x2) << 4)
15377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
15378 (UINT32_C(0x3) << 4)
15380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
15381 (UINT32_C(0x4) << 4)
15383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
15384 (UINT32_C(0x5) << 4)
15385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
15386 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
15387 /* TQM ring 0 page size and level. */
15388 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
15389 /* TQM ring 0 PBL indirect levels. */
15390 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
15392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
15393 /* PBL pointer is physical start address. */
15394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
15396 /* PBL pointer points to PTE table. */
15397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
15399 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15400 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
15402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
15403 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
15404 /* TQM ring 0 page size. */
15405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
15407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
15409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
15410 (UINT32_C(0x0) << 4)
15412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
15413 (UINT32_C(0x1) << 4)
15415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
15416 (UINT32_C(0x2) << 4)
15418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
15419 (UINT32_C(0x3) << 4)
15421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
15422 (UINT32_C(0x4) << 4)
15424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
15425 (UINT32_C(0x5) << 4)
15426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
15427 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
15428 /* TQM ring 1 page size and level. */
15429 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
15430 /* TQM ring 1 PBL indirect levels. */
15431 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
15433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
15434 /* PBL pointer is physical start address. */
15435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
15437 /* PBL pointer points to PTE table. */
15438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
15440 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
15443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
15444 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
15445 /* TQM ring 1 page size. */
15446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
15448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
15450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
15451 (UINT32_C(0x0) << 4)
15453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
15454 (UINT32_C(0x1) << 4)
15456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
15457 (UINT32_C(0x2) << 4)
15459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
15460 (UINT32_C(0x3) << 4)
15462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
15463 (UINT32_C(0x4) << 4)
15465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
15466 (UINT32_C(0x5) << 4)
15467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
15468 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
15469 /* TQM ring 2 page size and level. */
15470 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
15471 /* TQM ring 2 PBL indirect levels. */
15472 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
15474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
15475 /* PBL pointer is physical start address. */
15476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
15478 /* PBL pointer points to PTE table. */
15479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
15481 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
15484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
15485 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
15486 /* TQM ring 2 page size. */
15487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
15489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
15491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
15492 (UINT32_C(0x0) << 4)
15494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
15495 (UINT32_C(0x1) << 4)
15497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
15498 (UINT32_C(0x2) << 4)
15500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
15501 (UINT32_C(0x3) << 4)
15503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
15504 (UINT32_C(0x4) << 4)
15506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
15507 (UINT32_C(0x5) << 4)
15508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
15509 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
15510 /* TQM ring 3 page size and level. */
15511 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
15512 /* TQM ring 3 PBL indirect levels. */
15513 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
15515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
15516 /* PBL pointer is physical start address. */
15517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
15519 /* PBL pointer points to PTE table. */
15520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
15522 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
15525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
15526 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
15527 /* TQM ring 3 page size. */
15528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
15530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
15532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
15533 (UINT32_C(0x0) << 4)
15535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
15536 (UINT32_C(0x1) << 4)
15538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
15539 (UINT32_C(0x2) << 4)
15541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
15542 (UINT32_C(0x3) << 4)
15544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
15545 (UINT32_C(0x4) << 4)
15547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
15548 (UINT32_C(0x5) << 4)
15549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
15550 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
15551 /* TQM ring 4 page size and level. */
15552 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
15553 /* TQM ring 4 PBL indirect levels. */
15554 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
15556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
15557 /* PBL pointer is physical start address. */
15558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
15560 /* PBL pointer points to PTE table. */
15561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
15563 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
15566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
15567 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
15568 /* TQM ring 4 page size. */
15569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
15571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
15573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
15574 (UINT32_C(0x0) << 4)
15576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
15577 (UINT32_C(0x1) << 4)
15579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
15580 (UINT32_C(0x2) << 4)
15582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
15583 (UINT32_C(0x3) << 4)
15585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
15586 (UINT32_C(0x4) << 4)
15588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
15589 (UINT32_C(0x5) << 4)
15590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
15591 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
15592 /* TQM ring 5 page size and level. */
15593 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
15594 /* TQM ring 5 PBL indirect levels. */
15595 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
15597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
15598 /* PBL pointer is physical start address. */
15599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
15601 /* PBL pointer points to PTE table. */
15602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
15604 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
15607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
15608 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
15609 /* TQM ring 5 page size. */
15610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
15612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
15614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
15615 (UINT32_C(0x0) << 4)
15617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
15618 (UINT32_C(0x1) << 4)
15620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
15621 (UINT32_C(0x2) << 4)
15623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
15624 (UINT32_C(0x3) << 4)
15626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
15627 (UINT32_C(0x4) << 4)
15629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
15630 (UINT32_C(0x5) << 4)
15631 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
15632 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
15633 /* TQM ring 6 page size and level. */
15634 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
15635 /* TQM ring 6 PBL indirect levels. */
15636 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
15638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
15639 /* PBL pointer is physical start address. */
15640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
15642 /* PBL pointer points to PTE table. */
15643 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
15645 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15646 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
15648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
15649 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
15650 /* TQM ring 6 page size. */
15651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
15653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
15655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
15656 (UINT32_C(0x0) << 4)
15658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
15659 (UINT32_C(0x1) << 4)
15661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
15662 (UINT32_C(0x2) << 4)
15664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
15665 (UINT32_C(0x3) << 4)
15667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
15668 (UINT32_C(0x4) << 4)
15670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
15671 (UINT32_C(0x5) << 4)
15672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
15673 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
15674 /* TQM ring 7 page size and level. */
15675 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
15676 /* TQM ring 7 PBL indirect levels. */
15677 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
15679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
15680 /* PBL pointer is physical start address. */
15681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
15683 /* PBL pointer points to PTE table. */
15684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
15686 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
15689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
15690 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
15691 /* TQM ring 7 page size. */
15692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
15694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
15696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
15697 (UINT32_C(0x0) << 4)
15699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
15700 (UINT32_C(0x1) << 4)
15702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
15703 (UINT32_C(0x2) << 4)
15705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
15706 (UINT32_C(0x3) << 4)
15708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
15709 (UINT32_C(0x4) << 4)
15711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
15712 (UINT32_C(0x5) << 4)
15713 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
15714 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
15715 /* MR/AV page size and level. */
15716 uint8_t mrav_pg_size_mrav_lvl;
15717 /* MR/AV PBL indirect levels. */
15718 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
15720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
15721 /* PBL pointer is physical start address. */
15722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
15724 /* PBL pointer points to PTE table. */
15725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
15727 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15728 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
15730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
15731 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
15732 /* MR/AV page size. */
15733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
15735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
15737 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
15738 (UINT32_C(0x0) << 4)
15740 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
15741 (UINT32_C(0x1) << 4)
15743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
15744 (UINT32_C(0x2) << 4)
15746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
15747 (UINT32_C(0x3) << 4)
15749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
15750 (UINT32_C(0x4) << 4)
15752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
15753 (UINT32_C(0x5) << 4)
15754 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
15755 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
15756 /* Timer page size and level. */
15757 uint8_t tim_pg_size_tim_lvl;
15758 /* Timer PBL indirect levels. */
15759 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
15761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
15762 /* PBL pointer is physical start address. */
15763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
15765 /* PBL pointer points to PTE table. */
15766 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
15768 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
15771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
15772 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
15773 /* Timer page size. */
15774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
15776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
15778 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
15779 (UINT32_C(0x0) << 4)
15781 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
15782 (UINT32_C(0x1) << 4)
15784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
15785 (UINT32_C(0x2) << 4)
15787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
15788 (UINT32_C(0x3) << 4)
15790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
15791 (UINT32_C(0x4) << 4)
15793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
15794 (UINT32_C(0x5) << 4)
15795 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
15796 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
15797 /* QP page directory. */
15798 uint64_t qpc_page_dir;
15799 /* SRQ page directory. */
15800 uint64_t srq_page_dir;
15801 /* CQ page directory. */
15802 uint64_t cq_page_dir;
15803 /* VNIC page directory. */
15804 uint64_t vnic_page_dir;
15805 /* Stat page directory. */
15806 uint64_t stat_page_dir;
15807 /* TQM slowpath page directory. */
15808 uint64_t tqm_sp_page_dir;
15809 /* TQM ring 0 page directory. */
15810 uint64_t tqm_ring0_page_dir;
15811 /* TQM ring 1 page directory. */
15812 uint64_t tqm_ring1_page_dir;
15813 /* TQM ring 2 page directory. */
15814 uint64_t tqm_ring2_page_dir;
15815 /* TQM ring 3 page directory. */
15816 uint64_t tqm_ring3_page_dir;
15817 /* TQM ring 4 page directory. */
15818 uint64_t tqm_ring4_page_dir;
15819 /* TQM ring 5 page directory. */
15820 uint64_t tqm_ring5_page_dir;
15821 /* TQM ring 6 page directory. */
15822 uint64_t tqm_ring6_page_dir;
15823 /* TQM ring 7 page directory. */
15824 uint64_t tqm_ring7_page_dir;
15825 /* MR/AV page directory. */
15826 uint64_t mrav_page_dir;
15827 /* Timer page directory. */
15828 uint64_t tim_page_dir;
15829 /* Number of entries to reserve for QP1 */
15830 uint16_t qp_num_qp1_entries;
15831 /* Number of entries to reserve for L2 */
15832 uint16_t qp_num_l2_entries;
15833 /* Number of QPs. */
15834 uint32_t qp_num_entries;
15835 /* Number of SRQs. */
15836 uint32_t srq_num_entries;
15837 /* Number of entries to reserve for L2 */
15838 uint16_t srq_num_l2_entries;
15839 /* Number of entries to reserve for L2 */
15840 uint16_t cq_num_l2_entries;
15841 /* Number of CQs. */
15842 uint32_t cq_num_entries;
15843 /* Number of entries to reserve for VNIC entries */
15844 uint16_t vnic_num_vnic_entries;
15845 /* Number of entries to reserve for Ring table entries */
15846 uint16_t vnic_num_ring_table_entries;
15847 /* Number of Stats. */
15848 uint32_t stat_num_entries;
15849 /* Number of TQM slowpath entries. */
15850 uint32_t tqm_sp_num_entries;
15851 /* Number of TQM ring 0 entries. */
15852 uint32_t tqm_ring0_num_entries;
15853 /* Number of TQM ring 1 entries. */
15854 uint32_t tqm_ring1_num_entries;
15855 /* Number of TQM ring 2 entries. */
15856 uint32_t tqm_ring2_num_entries;
15857 /* Number of TQM ring 3 entries. */
15858 uint32_t tqm_ring3_num_entries;
15859 /* Number of TQM ring 4 entries. */
15860 uint32_t tqm_ring4_num_entries;
15861 /* Number of TQM ring 5 entries. */
15862 uint32_t tqm_ring5_num_entries;
15863 /* Number of TQM ring 6 entries. */
15864 uint32_t tqm_ring6_num_entries;
15865 /* Number of TQM ring 7 entries. */
15866 uint32_t tqm_ring7_num_entries;
15868 * If the MR/AV split reservation flag is not set, then this field
15869 * represents the total number of MR plus AV entries. For versions
15870 * of firmware that support the split reservation, when it is not
15871 * specified half of the entries will be reserved for MRs and the
15872 * other half for AVs.
15874 * If the MR/AV split reservation flag is set, then this
15875 * field is logically divided into two 16b fields. Bits `[31:16]`
15876 * represents the `mr_num_entries` and bits `[15:0]` represents
15877 * `av_num_entries`. The granularity of these values is defined by
15878 * the `mrav_num_entries_unit` field returned by the
15879 * `backing_store_qcaps` command.
15881 uint32_t mrav_num_entries;
15882 /* Number of Timer entries. */
15883 uint32_t tim_num_entries;
15884 uint8_t unused_1[7];
15886 * This field is used in Output records to indicate that the output
15887 * is completely written to RAM. This field should be read as 1
15888 * to indicate that the output has been completely written.
15889 * When writing a command completion or response to an internal
15890 * processor, the order of writes has to be such that this field
15896 /****************************
15897 * hwrm_error_recovery_qcfg *
15898 ****************************/
15901 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
15902 struct hwrm_error_recovery_qcfg_input {
15903 /* The HWRM command request type. */
15906 * The completion ring to send the completion event on. This should
15907 * be the NQ ID returned from the `nq_alloc` HWRM command.
15909 uint16_t cmpl_ring;
15911 * The sequence ID is used by the driver for tracking multiple
15912 * commands. This ID is treated as opaque data by the firmware and
15913 * the value is returned in the `hwrm_resp_hdr` upon completion.
15917 * The target ID of the command:
15918 * * 0x0-0xFFF8 - The function ID
15919 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15920 * * 0xFFFD - Reserved for user-space HWRM interface
15923 uint16_t target_id;
15925 * A physical address pointer pointing to a host buffer that the
15926 * command's response data will be written. This can be either a host
15927 * physical address (HPA) or a guest physical address (GPA) and must
15928 * point to a physically contiguous block of memory.
15930 uint64_t resp_addr;
15931 uint8_t unused_0[8];
15934 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
15935 struct hwrm_error_recovery_qcfg_output {
15936 /* The specific error status for the command. */
15937 uint16_t error_code;
15938 /* The HWRM command request type. */
15940 /* The sequence ID from the original command. */
15942 /* The length of the response data in number of bytes. */
15946 * When this flag is set to 1, error recovery will be initiated
15947 * through master function driver.
15949 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
15951 * When this flag is set to 1, error recovery will be performed
15952 * through Co processor.
15954 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
15956 * Driver Polling frequency. This value is in units of 100msec.
15957 * Typical value would be 10 to indicate 1sec.
15958 * Drivers can poll FW health status, Heartbeat, reset_counter with
15961 uint32_t driver_polling_freq;
15963 * This value is in units of 100msec.
15964 * Typical value would be 30 to indicate 3sec.
15965 * Master function wait period from detecting a fatal error to
15966 * initiating reset. In this time period Master PF expects every
15967 * active driver will detect fatal error.
15969 uint32_t master_func_wait_period;
15971 * This value is in units of 100msec.
15972 * Typical value would be 50 to indicate 5sec.
15973 * Normal function wait period from fatal error detection to
15974 * polling FW health status. In this time period, drivers should not
15975 * do any PCIe MMIO transaction and should not send any HWRM commands.
15977 uint32_t normal_func_wait_period;
15979 * This value is in units of 100msec.
15980 * Typical value would be 20 to indicate 2sec.
15981 * This field indicates that, master function wait period after chip
15982 * reset. After this time, master function should reinitialize with
15985 uint32_t master_func_wait_period_after_reset;
15987 * This value is in units of 100msec.
15988 * Typical value would be 60 to indicate 6sec.
15989 * This field is applicable to both master and normal functions.
15990 * Even after chip reset, if FW status not changed to ready,
15991 * then all the functions can poll for this much time and bailout.
15993 uint32_t max_bailout_time_after_reset;
15995 * FW health status register.
15996 * Lower 2 bits indicates address space location and upper 30 bits
15997 * indicates upper 30bits of the register address.
15998 * A value of 0xFFFF-FFFF indicates this register does not exist.
16000 uint32_t fw_health_status_reg;
16001 /* Lower 2 bits indicates address space location. */
16002 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
16004 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
16007 * If value is 0, this register is located in PCIe config space.
16008 * Drivers have to map appropriate window to access this
16011 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
16014 * If value is 1, this register is located in GRC address space.
16015 * Drivers have to map appropriate window to access this
16018 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
16021 * If value is 2, this register is located in first BAR address
16022 * space. Drivers have to map appropriate window to access this
16025 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
16028 * If value is 3, this register is located in second BAR address
16029 * space. Drivers have to map appropriate window to access this
16030 * Drivers have to map appropriate window to access this
16033 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
16035 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
16036 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
16037 /* Upper 30bits of the register address. */
16038 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
16039 UINT32_C(0xfffffffc)
16040 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
16043 * FW HeartBeat register.
16044 * Lower 2 bits indicates address space location and upper 30 bits
16045 * indicates actual address.
16046 * A value of 0xFFFF-FFFF indicates this register does not exist.
16048 uint32_t fw_heartbeat_reg;
16049 /* Lower 2 bits indicates address space location. */
16050 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
16052 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
16055 * If value is 0, this register is located in PCIe config space.
16056 * Drivers have to map appropriate window to access this
16059 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
16062 * If value is 1, this register is located in GRC address space.
16063 * Drivers have to map appropriate window to access this
16066 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
16069 * If value is 2, this register is located in first BAR address
16070 * space. Drivers have to map appropriate window to access this
16073 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
16076 * If value is 3, this register is located in second BAR address
16077 * space. Drivers have to map appropriate window to access this
16080 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
16082 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
16083 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
16084 /* Upper 30bits of the register address. */
16085 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
16086 UINT32_C(0xfffffffc)
16087 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
16090 * FW reset counter.
16091 * Lower 2 bits indicates address space location and upper 30 bits
16092 * indicates actual address.
16093 * A value of 0xFFFF-FFFF indicates this register does not exist.
16095 uint32_t fw_reset_cnt_reg;
16096 /* Lower 2 bits indicates address space location. */
16097 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
16099 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
16102 * If value is 0, this register is located in PCIe config space.
16103 * Drivers have to map appropriate window to access this
16106 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
16109 * If value is 1, this register is located in GRC address space.
16110 * Drivers have to map appropriate window to access this
16113 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
16116 * If value is 2, this register is located in first BAR address
16117 * space. Drivers have to map appropriate window to access this
16120 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
16123 * If value is 3, this register is located in second BAR address
16124 * space. Drivers have to map appropriate window to access this
16127 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
16129 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
16130 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
16131 /* Upper 30bits of the register address. */
16132 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
16133 UINT32_C(0xfffffffc)
16134 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
16137 * Reset Inprogress Register address for PFs.
16138 * Lower 2 bits indicates address space location and upper 30 bits
16139 * indicates actual address.
16140 * A value of 0xFFFF-FFFF indicates this register does not exist.
16142 uint32_t reset_inprogress_reg;
16143 /* Lower 2 bits indicates address space location. */
16144 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
16146 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
16149 * If value is 0, this register is located in PCIe config space.
16150 * Drivers have to map appropriate window to access this
16153 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
16156 * If value is 1, this register is located in GRC address space.
16157 * Drivers have to map appropriate window to access this
16160 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
16163 * If value is 2, this register is located in first BAR address
16164 * space. Drivers have to map appropriate window to access this
16167 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
16170 * If value is 3, this register is located in second BAR address
16171 * space. Drivers have to map appropriate window to access this
16174 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
16176 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
16177 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
16178 /* Upper 30bits of the register address. */
16179 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
16180 UINT32_C(0xfffffffc)
16181 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
16183 /* This field indicates the mask value for reset_inprogress_reg. */
16184 uint32_t reset_inprogress_reg_mask;
16185 uint8_t unused_0[3];
16187 * Array of registers and value count to reset the Chip
16188 * Each array count has reset_reg, reset_reg_val, delay_after_reset
16189 * in TLV format. Depending upon Chip type, number of reset registers
16190 * will vary. Drivers have to write reset_reg_val in the reset_reg
16191 * location in the same sequence in order to recover from a fatal
16194 uint8_t reg_array_cnt;
16197 * Lower 2 bits indicates address space location and upper 30 bits
16198 * indicates actual address.
16199 * A value of 0xFFFF-FFFF indicates this register does not exist.
16201 uint32_t reset_reg[16];
16202 /* Lower 2 bits indicates address space location. */
16203 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
16205 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
16207 * If value is 0, this register is located in PCIe config space.
16208 * Drivers have to map appropriate window to access this
16211 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
16214 * If value is 1, this register is located in GRC address space.
16215 * Drivers have to map appropriate window to access this
16218 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
16221 * If value is 2, this register is located in first BAR address
16222 * space. Drivers have to map appropriate window to access this
16225 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
16228 * If value is 3, this register is located in second BAR address
16229 * space. Drivers have to map appropriate window to access this
16232 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
16234 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
16235 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
16236 /* Upper 30bits of the register address. */
16237 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
16238 UINT32_C(0xfffffffc)
16239 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
16240 /* Value to be written in reset_reg to reset the controller. */
16241 uint32_t reset_reg_val[16];
16243 * This value is in units of 1msec.
16244 * Typical value would be 10 to indicate 10msec.
16245 * Some of the operations like Core reset require delay before
16246 * accessing PCIE MMIO register space.
16247 * If this value is non-zero, drivers have to wait for
16248 * this much time after writing reset_reg_val in reset_reg.
16250 uint8_t delay_after_reset[16];
16252 * Error recovery counter.
16253 * Lower 2 bits indicates address space location and upper 30 bits
16254 * indicates actual address.
16255 * A value of 0xFFFF-FFFF indicates this register does not exist.
16257 uint32_t err_recovery_cnt_reg;
16258 /* Lower 2 bits indicates address space location. */
16259 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
16261 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
16264 * If value is 0, this register is located in PCIe config space.
16265 * Drivers have to map appropriate window to access this
16268 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
16271 * If value is 1, this register is located in GRC address space.
16272 * Drivers have to map appropriate window to access this
16275 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
16278 * If value is 2, this register is located in first BAR address
16279 * space. Drivers have to map appropriate window to access this
16282 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
16285 * If value is 3, this register is located in second BAR address
16286 * space. Drivers have to map appropriate window to access this
16289 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
16291 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
16292 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
16293 /* Upper 30bits of the register address. */
16294 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
16295 UINT32_C(0xfffffffc)
16296 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
16298 uint8_t unused_1[3];
16300 * This field is used in Output records to indicate that the output
16301 * is completely written to RAM. This field should be read as '1'
16302 * to indicate that the output has been completely written.
16303 * When writing a command completion or response to an internal
16304 * processor, the order of writes has to be such that this field
16310 /***********************
16311 * hwrm_func_vlan_qcfg *
16312 ***********************/
16315 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
16316 struct hwrm_func_vlan_qcfg_input {
16317 /* The HWRM command request type. */
16320 * The completion ring to send the completion event on. This should
16321 * be the NQ ID returned from the `nq_alloc` HWRM command.
16323 uint16_t cmpl_ring;
16325 * The sequence ID is used by the driver for tracking multiple
16326 * commands. This ID is treated as opaque data by the firmware and
16327 * the value is returned in the `hwrm_resp_hdr` upon completion.
16331 * The target ID of the command:
16332 * * 0x0-0xFFF8 - The function ID
16333 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16334 * * 0xFFFD - Reserved for user-space HWRM interface
16337 uint16_t target_id;
16339 * A physical address pointer pointing to a host buffer that the
16340 * command's response data will be written. This can be either a host
16341 * physical address (HPA) or a guest physical address (GPA) and must
16342 * point to a physically contiguous block of memory.
16344 uint64_t resp_addr;
16346 * Function ID of the function that is being
16348 * If set to 0xFF... (All Fs), then the configuration is
16349 * for the requesting function.
16352 uint8_t unused_0[6];
16355 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
16356 struct hwrm_func_vlan_qcfg_output {
16357 /* The specific error status for the command. */
16358 uint16_t error_code;
16359 /* The HWRM command request type. */
16361 /* The sequence ID from the original command. */
16363 /* The length of the response data in number of bytes. */
16366 /* S-TAG VLAN identifier configured for the function. */
16368 /* S-TAG PCP value configured for the function. */
16372 * S-TAG TPID value configured for the function. This field is specified in
16373 * network byte order.
16375 uint16_t stag_tpid;
16376 /* C-TAG VLAN identifier configured for the function. */
16378 /* C-TAG PCP value configured for the function. */
16382 * C-TAG TPID value configured for the function. This field is specified in
16383 * network byte order.
16385 uint16_t ctag_tpid;
16390 uint8_t unused_3[3];
16392 * This field is used in Output records to indicate that the output
16393 * is completely written to RAM. This field should be read as '1'
16394 * to indicate that the output has been completely written.
16395 * When writing a command completion or response to an internal processor,
16396 * the order of writes has to be such that this field is written last.
16401 /**********************
16402 * hwrm_func_vlan_cfg *
16403 **********************/
16406 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
16407 struct hwrm_func_vlan_cfg_input {
16408 /* The HWRM command request type. */
16411 * The completion ring to send the completion event on. This should
16412 * be the NQ ID returned from the `nq_alloc` HWRM command.
16414 uint16_t cmpl_ring;
16416 * The sequence ID is used by the driver for tracking multiple
16417 * commands. This ID is treated as opaque data by the firmware and
16418 * the value is returned in the `hwrm_resp_hdr` upon completion.
16422 * The target ID of the command:
16423 * * 0x0-0xFFF8 - The function ID
16424 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16425 * * 0xFFFD - Reserved for user-space HWRM interface
16428 uint16_t target_id;
16430 * A physical address pointer pointing to a host buffer that the
16431 * command's response data will be written. This can be either a host
16432 * physical address (HPA) or a guest physical address (GPA) and must
16433 * point to a physically contiguous block of memory.
16435 uint64_t resp_addr;
16437 * Function ID of the function that is being
16439 * If set to 0xFF... (All Fs), then the configuration is
16440 * for the requesting function.
16443 uint8_t unused_0[2];
16446 * This bit must be '1' for the stag_vid field to be
16449 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
16451 * This bit must be '1' for the ctag_vid field to be
16454 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
16456 * This bit must be '1' for the stag_pcp field to be
16459 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
16461 * This bit must be '1' for the ctag_pcp field to be
16464 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
16466 * This bit must be '1' for the stag_tpid field to be
16469 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
16471 * This bit must be '1' for the ctag_tpid field to be
16474 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
16475 /* S-TAG VLAN identifier configured for the function. */
16477 /* S-TAG PCP value configured for the function. */
16481 * S-TAG TPID value configured for the function. This field is specified in
16482 * network byte order.
16484 uint16_t stag_tpid;
16485 /* C-TAG VLAN identifier configured for the function. */
16487 /* C-TAG PCP value configured for the function. */
16491 * C-TAG TPID value configured for the function. This field is specified in
16492 * network byte order.
16494 uint16_t ctag_tpid;
16499 uint8_t unused_3[4];
16502 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
16503 struct hwrm_func_vlan_cfg_output {
16504 /* The specific error status for the command. */
16505 uint16_t error_code;
16506 /* The HWRM command request type. */
16508 /* The sequence ID from the original command. */
16510 /* The length of the response data in number of bytes. */
16512 uint8_t unused_0[7];
16514 * This field is used in Output records to indicate that the output
16515 * is completely written to RAM. This field should be read as '1'
16516 * to indicate that the output has been completely written.
16517 * When writing a command completion or response to an internal processor,
16518 * the order of writes has to be such that this field is written last.
16523 /*******************************
16524 * hwrm_func_vf_vnic_ids_query *
16525 *******************************/
16528 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
16529 struct hwrm_func_vf_vnic_ids_query_input {
16530 /* The HWRM command request type. */
16533 * The completion ring to send the completion event on. This should
16534 * be the NQ ID returned from the `nq_alloc` HWRM command.
16536 uint16_t cmpl_ring;
16538 * The sequence ID is used by the driver for tracking multiple
16539 * commands. This ID is treated as opaque data by the firmware and
16540 * the value is returned in the `hwrm_resp_hdr` upon completion.
16544 * The target ID of the command:
16545 * * 0x0-0xFFF8 - The function ID
16546 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16547 * * 0xFFFD - Reserved for user-space HWRM interface
16550 uint16_t target_id;
16552 * A physical address pointer pointing to a host buffer that the
16553 * command's response data will be written. This can be either a host
16554 * physical address (HPA) or a guest physical address (GPA) and must
16555 * point to a physically contiguous block of memory.
16557 uint64_t resp_addr;
16559 * This value is used to identify a Virtual Function (VF).
16560 * The scope of VF ID is local within a PF.
16563 uint8_t unused_0[2];
16564 /* Max number of vnic ids in vnic id table */
16565 uint32_t max_vnic_id_cnt;
16566 /* This is the address for VF VNIC ID table */
16567 uint64_t vnic_id_tbl_addr;
16570 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
16571 struct hwrm_func_vf_vnic_ids_query_output {
16572 /* The specific error status for the command. */
16573 uint16_t error_code;
16574 /* The HWRM command request type. */
16576 /* The sequence ID from the original command. */
16578 /* The length of the response data in number of bytes. */
16581 * Actual number of vnic ids
16583 * Each VNIC ID is written as a 32-bit number.
16585 uint32_t vnic_id_cnt;
16586 uint8_t unused_0[3];
16588 * This field is used in Output records to indicate that the output
16589 * is completely written to RAM. This field should be read as '1'
16590 * to indicate that the output has been completely written.
16591 * When writing a command completion or response to an internal processor,
16592 * the order of writes has to be such that this field is written last.
16597 /***********************
16598 * hwrm_func_vf_bw_cfg *
16599 ***********************/
16602 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
16603 struct hwrm_func_vf_bw_cfg_input {
16604 /* The HWRM command request type. */
16607 * The completion ring to send the completion event on. This should
16608 * be the NQ ID returned from the `nq_alloc` HWRM command.
16610 uint16_t cmpl_ring;
16612 * The sequence ID is used by the driver for tracking multiple
16613 * commands. This ID is treated as opaque data by the firmware and
16614 * the value is returned in the `hwrm_resp_hdr` upon completion.
16618 * The target ID of the command:
16619 * * 0x0-0xFFF8 - The function ID
16620 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16621 * * 0xFFFD - Reserved for user-space HWRM interface
16624 uint16_t target_id;
16626 * A physical address pointer pointing to a host buffer that the
16627 * command's response data will be written. This can be either a host
16628 * physical address (HPA) or a guest physical address (GPA) and must
16629 * point to a physically contiguous block of memory.
16631 uint64_t resp_addr;
16633 * The number of VF functions that are being configured.
16634 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
16637 uint16_t unused[3];
16638 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
16640 /* The physical VF id the adjustment will be made to. */
16641 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
16642 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
16644 * This field configures the rate scale percentage of the VF as specified
16645 * by the physical VF id.
16647 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
16648 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
16649 /* 0% of the max tx rate */
16650 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
16651 (UINT32_C(0x0) << 12)
16652 /* 6.66% of the max tx rate */
16653 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
16654 (UINT32_C(0x1) << 12)
16655 /* 13.33% of the max tx rate */
16656 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
16657 (UINT32_C(0x2) << 12)
16658 /* 20% of the max tx rate */
16659 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
16660 (UINT32_C(0x3) << 12)
16661 /* 26.66% of the max tx rate */
16662 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
16663 (UINT32_C(0x4) << 12)
16664 /* 33% of the max tx rate */
16665 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
16666 (UINT32_C(0x5) << 12)
16667 /* 40% of the max tx rate */
16668 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
16669 (UINT32_C(0x6) << 12)
16670 /* 46.66% of the max tx rate */
16671 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
16672 (UINT32_C(0x7) << 12)
16673 /* 53.33% of the max tx rate */
16674 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
16675 (UINT32_C(0x8) << 12)
16676 /* 60% of the max tx rate */
16677 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
16678 (UINT32_C(0x9) << 12)
16679 /* 66.66% of the max tx rate */
16680 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
16681 (UINT32_C(0xa) << 12)
16682 /* 53.33% of the max tx rate */
16683 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
16684 (UINT32_C(0xb) << 12)
16685 /* 80% of the max tx rate */
16686 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
16687 (UINT32_C(0xc) << 12)
16688 /* 86.66% of the max tx rate */
16689 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
16690 (UINT32_C(0xd) << 12)
16691 /* 93.33% of the max tx rate */
16692 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
16693 (UINT32_C(0xe) << 12)
16694 /* 100% of the max tx rate */
16695 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
16696 (UINT32_C(0xf) << 12)
16697 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
16698 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
16701 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
16702 struct hwrm_func_vf_bw_cfg_output {
16703 /* The specific error status for the command. */
16704 uint16_t error_code;
16705 /* The HWRM command request type. */
16707 /* The sequence ID from the original command. */
16709 /* The length of the response data in number of bytes. */
16711 uint8_t unused_0[7];
16713 * This field is used in Output records to indicate that the output
16714 * is completely written to RAM. This field should be read as '1'
16715 * to indicate that the output has been completely written.
16716 * When writing a command completion or response to an internal processor,
16717 * the order of writes has to be such that this field is written last.
16722 /************************
16723 * hwrm_func_vf_bw_qcfg *
16724 ************************/
16727 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
16728 struct hwrm_func_vf_bw_qcfg_input {
16729 /* The HWRM command request type. */
16732 * The completion ring to send the completion event on. This should
16733 * be the NQ ID returned from the `nq_alloc` HWRM command.
16735 uint16_t cmpl_ring;
16737 * The sequence ID is used by the driver for tracking multiple
16738 * commands. This ID is treated as opaque data by the firmware and
16739 * the value is returned in the `hwrm_resp_hdr` upon completion.
16743 * The target ID of the command:
16744 * * 0x0-0xFFF8 - The function ID
16745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16746 * * 0xFFFD - Reserved for user-space HWRM interface
16749 uint16_t target_id;
16751 * A physical address pointer pointing to a host buffer that the
16752 * command's response data will be written. This can be either a host
16753 * physical address (HPA) or a guest physical address (GPA) and must
16754 * point to a physically contiguous block of memory.
16756 uint64_t resp_addr;
16758 * The number of VF functions that are being queried.
16759 * The inline response space allows the host to query up to 50 VFs'
16760 * rate scale percentage
16763 uint16_t unused[3];
16764 /* These 16-bit fields contain the VF fid */
16766 /* The physical VF id of interest */
16767 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
16768 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
16771 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
16772 struct hwrm_func_vf_bw_qcfg_output {
16773 /* The specific error status for the command. */
16774 uint16_t error_code;
16775 /* The HWRM command request type. */
16777 /* The sequence ID from the original command. */
16779 /* The length of the response data in number of bytes. */
16782 * The number of VF functions that are being queried.
16783 * The inline response space allows the host to query up to 50 VFs' rate
16787 uint16_t unused[3];
16788 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
16790 /* The physical VF id the adjustment will be made to. */
16791 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
16792 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
16794 * This field configures the rate scale percentage of the VF as specified
16795 * by the physical VF id.
16797 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
16798 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
16799 /* 0% of the max tx rate */
16800 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
16801 (UINT32_C(0x0) << 12)
16802 /* 6.66% of the max tx rate */
16803 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
16804 (UINT32_C(0x1) << 12)
16805 /* 13.33% of the max tx rate */
16806 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
16807 (UINT32_C(0x2) << 12)
16808 /* 20% of the max tx rate */
16809 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
16810 (UINT32_C(0x3) << 12)
16811 /* 26.66% of the max tx rate */
16812 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
16813 (UINT32_C(0x4) << 12)
16814 /* 33% of the max tx rate */
16815 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
16816 (UINT32_C(0x5) << 12)
16817 /* 40% of the max tx rate */
16818 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
16819 (UINT32_C(0x6) << 12)
16820 /* 46.66% of the max tx rate */
16821 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
16822 (UINT32_C(0x7) << 12)
16823 /* 53.33% of the max tx rate */
16824 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
16825 (UINT32_C(0x8) << 12)
16826 /* 60% of the max tx rate */
16827 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
16828 (UINT32_C(0x9) << 12)
16829 /* 66.66% of the max tx rate */
16830 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
16831 (UINT32_C(0xa) << 12)
16832 /* 53.33% of the max tx rate */
16833 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
16834 (UINT32_C(0xb) << 12)
16835 /* 80% of the max tx rate */
16836 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
16837 (UINT32_C(0xc) << 12)
16838 /* 86.66% of the max tx rate */
16839 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
16840 (UINT32_C(0xd) << 12)
16841 /* 93.33% of the max tx rate */
16842 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
16843 (UINT32_C(0xe) << 12)
16844 /* 100% of the max tx rate */
16845 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
16846 (UINT32_C(0xf) << 12)
16847 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
16848 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
16849 uint8_t unused_0[7];
16851 * This field is used in Output records to indicate that the output
16852 * is completely written to RAM. This field should be read as '1'
16853 * to indicate that the output has been completely written.
16854 * When writing a command completion or response to an internal processor,
16855 * the order of writes has to be such that this field is written last.
16860 /***************************
16861 * hwrm_func_drv_if_change *
16862 ***************************/
16865 /* hwrm_func_drv_if_change_input (size:192b/24B) */
16866 struct hwrm_func_drv_if_change_input {
16867 /* The HWRM command request type. */
16870 * The completion ring to send the completion event on. This should
16871 * be the NQ ID returned from the `nq_alloc` HWRM command.
16873 uint16_t cmpl_ring;
16875 * The sequence ID is used by the driver for tracking multiple
16876 * commands. This ID is treated as opaque data by the firmware and
16877 * the value is returned in the `hwrm_resp_hdr` upon completion.
16881 * The target ID of the command:
16882 * * 0x0-0xFFF8 - The function ID
16883 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16884 * * 0xFFFD - Reserved for user-space HWRM interface
16887 uint16_t target_id;
16889 * A physical address pointer pointing to a host buffer that the
16890 * command's response data will be written. This can be either a host
16891 * physical address (HPA) or a guest physical address (GPA) and must
16892 * point to a physically contiguous block of memory.
16894 uint64_t resp_addr;
16897 * When this bit is '1', the function driver is indicating
16898 * that the IF state is changing to UP state. The call should
16899 * be made at the beginning of the driver's open call before
16900 * resources are allocated. After making the call, the driver
16901 * should check the response to see if any resources may have
16902 * changed (see the response below). If the driver fails
16903 * the open call, the driver should make this call again with
16904 * this bit cleared to indicate that the IF state is not UP.
16905 * During the driver's close call when the IF state is changing
16906 * to DOWN, the driver should make this call with the bit cleared
16907 * after all resources have been freed.
16909 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
16913 /* hwrm_func_drv_if_change_output (size:128b/16B) */
16914 struct hwrm_func_drv_if_change_output {
16915 /* The specific error status for the command. */
16916 uint16_t error_code;
16917 /* The HWRM command request type. */
16919 /* The sequence ID from the original command. */
16921 /* The length of the response data in number of bytes. */
16925 * When this bit is '1', it indicates that the resources reserved
16926 * for this function may have changed. The driver should check
16927 * resource capabilities and reserve resources again before
16928 * allocating resources.
16930 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
16933 * When this bit is '1', it indicates that the firmware got changed / reset.
16934 * The driver should do complete re-initialization when that bit is set.
16936 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
16938 uint8_t unused_0[3];
16940 * This field is used in Output records to indicate that the output
16941 * is completely written to RAM. This field should be read as '1'
16942 * to indicate that the output has been completely written.
16943 * When writing a command completion or response to an internal processor,
16944 * the order of writes has to be such that this field is written last.
16949 /*******************************
16950 * hwrm_func_host_pf_ids_query *
16951 *******************************/
16954 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
16955 struct hwrm_func_host_pf_ids_query_input {
16956 /* The HWRM command request type. */
16959 * The completion ring to send the completion event on. This should
16960 * be the NQ ID returned from the `nq_alloc` HWRM command.
16962 uint16_t cmpl_ring;
16964 * The sequence ID is used by the driver for tracking multiple
16965 * commands. This ID is treated as opaque data by the firmware and
16966 * the value is returned in the `hwrm_resp_hdr` upon completion.
16970 * The target ID of the command:
16971 * * 0x0-0xFFF8 - The function ID
16972 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16973 * * 0xFFFD - Reserved for user-space HWRM interface
16976 uint16_t target_id;
16978 * A physical address pointer pointing to a host buffer that the
16979 * command's response data will be written. This can be either a host
16980 * physical address (HPA) or a guest physical address (GPA) and must
16981 * point to a physically contiguous block of memory.
16983 uint64_t resp_addr;
16986 * # If this bit is set to '1', the query will contain PF(s)
16987 * belongs to SOC host.
16989 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
16991 * # If this bit is set to '1', the query will contain PF(s)
16992 * belongs to EP0 host.
16994 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
16996 * # If this bit is set to '1', the query will contain PF(s)
16997 * belongs to EP1 host.
16999 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
17001 * # If this bit is set to '1', the query will contain PF(s)
17002 * belongs to EP2 host.
17004 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
17006 * # If this bit is set to '1', the query will contain PF(s)
17007 * belongs to EP3 host.
17009 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
17011 * This provides a filter of what PF(s) will be returned in the
17016 * all available PF(s) belong to the host(s) (defined in the
17017 * host field). This includes the hidden PFs.
17019 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
17021 * all available PF(s) belong to the host(s) (defined in the
17022 * host field) that is available for L2 traffic.
17024 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
17026 * all available PF(s) belong to the host(s) (defined in the
17027 * host field) that is available for ROCE traffic.
17029 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
17030 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
17031 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
17032 uint8_t unused_1[6];
17035 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
17036 struct hwrm_func_host_pf_ids_query_output {
17037 /* The specific error status for the command. */
17038 uint16_t error_code;
17039 /* The HWRM command request type. */
17041 /* The sequence ID from the original command. */
17043 /* The length of the response data in number of bytes. */
17045 /* This provides the first PF ID of the device. */
17046 uint16_t first_pf_id;
17047 uint16_t pf_ordinal_mask;
17049 * When this bit is '1', it indicates first PF belongs to one of
17050 * the hosts defined in the input request.
17052 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
17055 * When this bit is '1', it indicates 2nd PF belongs to one of the
17056 * hosts defined in the input request.
17058 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
17061 * When this bit is '1', it indicates 3rd PF belongs to one of the
17062 * hosts defined in the input request.
17064 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
17067 * When this bit is '1', it indicates 4th PF belongs to one of the
17068 * hosts defined in the input request.
17070 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
17073 * When this bit is '1', it indicates 5th PF belongs to one of the
17074 * hosts defined in the input request.
17076 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
17079 * When this bit is '1', it indicates 6th PF belongs to one of the
17080 * hosts defined in the input request.
17082 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
17085 * When this bit is '1', it indicates 7th PF belongs to one of the
17086 * hosts defined in the input request.
17088 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
17091 * When this bit is '1', it indicates 8th PF belongs to one of the
17092 * hosts defined in the input request.
17094 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
17097 * When this bit is '1', it indicates 9th PF belongs to one of the
17098 * hosts defined in the input request.
17100 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
17103 * When this bit is '1', it indicates 10th PF belongs to one of the
17104 * hosts defined in the input request.
17106 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
17109 * When this bit is '1', it indicates 11th PF belongs to one of the
17110 * hosts defined in the input request.
17112 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
17115 * When this bit is '1', it indicates 12th PF belongs to one of the
17116 * hosts defined in the input request.
17118 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
17121 * When this bit is '1', it indicates 13th PF belongs to one of the
17122 * hosts defined in the input request.
17124 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
17127 * When this bit is '1', it indicates 14th PF belongs to one of the
17128 * hosts defined in the input request.
17130 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
17133 * When this bit is '1', it indicates 15th PF belongs to one of the
17134 * hosts defined in the input request.
17136 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
17139 * When this bit is '1', it indicates 16th PF belongs to one of the
17140 * hosts defined in the input request.
17142 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
17144 uint8_t unused_1[3];
17146 * This field is used in Output records to indicate that the output
17147 * is completely written to RAM. This field should be read as '1'
17148 * to indicate that the output has been completely written.
17149 * When writing a command completion or response to an internal processor,
17150 * the order of writes has to be such that this field is written last.
17155 /*********************
17156 * hwrm_port_phy_cfg *
17157 *********************/
17160 /* hwrm_port_phy_cfg_input (size:448b/56B) */
17161 struct hwrm_port_phy_cfg_input {
17162 /* The HWRM command request type. */
17165 * The completion ring to send the completion event on. This should
17166 * be the NQ ID returned from the `nq_alloc` HWRM command.
17168 uint16_t cmpl_ring;
17170 * The sequence ID is used by the driver for tracking multiple
17171 * commands. This ID is treated as opaque data by the firmware and
17172 * the value is returned in the `hwrm_resp_hdr` upon completion.
17176 * The target ID of the command:
17177 * * 0x0-0xFFF8 - The function ID
17178 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17179 * * 0xFFFD - Reserved for user-space HWRM interface
17182 uint16_t target_id;
17184 * A physical address pointer pointing to a host buffer that the
17185 * command's response data will be written. This can be either a host
17186 * physical address (HPA) or a guest physical address (GPA) and must
17187 * point to a physically contiguous block of memory.
17189 uint64_t resp_addr;
17192 * When this bit is set to '1', the PHY for the port shall
17195 * # If this bit is set to 1, then the HWRM shall reset the
17196 * PHY after applying PHY configuration changes specified
17198 * # In order to guarantee that PHY configuration changes
17199 * specified in this command take effect, the HWRM
17200 * client should set this flag to 1.
17201 * # If this bit is not set to 1, then the HWRM may reset
17202 * the PHY depending on the current PHY configuration and
17203 * settings specified in this command.
17205 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
17207 /* deprecated bit. Do not use!!! */
17208 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
17211 * When this bit is set to '1', and the force_pam4_link_speed
17212 * bit in the 'enables' field is '0', the link shall be forced
17213 * to the force_link_speed value.
17215 * When this bit is set to '1', and the force_pam4_link_speed
17216 * bit in the 'enables' field is '1', the link shall be forced
17217 * to the force_pam4_link_speed value.
17219 * When this bit is set to '1', the HWRM client should
17220 * not enable any of the auto negotiation related
17221 * fields represented by auto_XXX fields in this command.
17222 * When this bit is set to '1' and the HWRM client has
17223 * enabled a auto_XXX field in this command, then the
17224 * HWRM shall ignore the enabled auto_XXX field.
17226 * When this bit is set to zero, the link
17227 * shall be allowed to autoneg.
17229 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
17232 * When this bit is set to '1', the auto-negotiation process
17233 * shall be restarted on the link.
17235 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
17238 * When this bit is set to '1', Energy Efficient Ethernet
17239 * (EEE) is requested to be enabled on this link.
17240 * If EEE is not supported on this port, then this flag
17241 * shall be ignored by the HWRM.
17243 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
17246 * When this bit is set to '1', Energy Efficient Ethernet
17247 * (EEE) is requested to be disabled on this link.
17248 * If EEE is not supported on this port, then this flag
17249 * shall be ignored by the HWRM.
17251 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
17254 * When this bit is set to '1' and EEE is enabled on this
17255 * link, then TX LPI is requested to be enabled on the link.
17256 * If EEE is not supported on this port, then this flag
17257 * shall be ignored by the HWRM.
17258 * If EEE is disabled on this port, then this flag shall be
17259 * ignored by the HWRM.
17261 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
17264 * When this bit is set to '1' and EEE is enabled on this
17265 * link, then TX LPI is requested to be disabled on the link.
17266 * If EEE is not supported on this port, then this flag
17267 * shall be ignored by the HWRM.
17268 * If EEE is disabled on this port, then this flag shall be
17269 * ignored by the HWRM.
17271 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
17274 * When set to 1, then the HWRM shall enable FEC autonegotitation
17275 * on this port if supported. When enabled, at least one of the
17276 * FEC modes must be advertised by enabling the fec_clause_74_enable,
17277 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
17278 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
17279 * of the FEC mode is currently enabled, the HWRM shall choose
17280 * a default advertisement setting.
17281 * The default advertisement setting can be queried by calling
17282 * hwrm_port_phy_qcfg. Note that the link speed must be
17283 * in autonegotiation mode for FEC autonegotiation to take effect.
17284 * When set to 0, then this flag shall be ignored.
17285 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
17288 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
17291 * When set to 1, then the HWRM shall disable FEC autonegotiation
17292 * on this port and use forced FEC mode. In forced FEC mode, one
17293 * or more FEC forced settings under the same clause can be set.
17294 * When set to 0, then this flag shall be ignored.
17295 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
17298 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
17301 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
17302 * on this port if supported, by advertising FEC CLAUSE 74 if
17303 * FEC autonegotiation is enabled or force enabled otherwise.
17304 * When set to 0, then this flag shall be ignored.
17305 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
17308 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
17311 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
17312 * on this port if supported, by not advertising FEC CLAUSE 74 if
17313 * FEC autonegotiation is enabled or force disabled otherwise.
17314 * When set to 0, then this flag shall be ignored.
17315 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
17318 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
17321 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
17322 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
17323 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
17324 * or force enabled otherwise. In forced FEC mode, this flag
17325 * will only take effect if the speed is NRZ. Additional
17326 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
17327 * in forced FEC mode.
17328 * When set to 0, then this flag shall be ignored.
17329 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
17332 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
17335 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
17336 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
17337 * not advertising RS(528,514) if FEC autonegotiation is enabled or
17338 * force disabled otherwise. When set to 0, then this flag shall be
17339 * ignored. If FEC RS(528,514) is not supported, then the HWRM
17340 * shall ignore this flag.
17342 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
17345 * When this bit is set to '1', the link shall be forced to
17348 * # When this bit is set to '1", all other
17349 * command input settings related to the link speed shall
17351 * Once the link state is forced down, it can be
17352 * explicitly cleared from that state by setting this flag
17354 * # If this flag is set to '0', then the link shall be
17355 * cleared from forced down state if the link is in forced
17357 * There may be conditions (e.g. out-of-band or sideband
17358 * configuration changes for the link) outside the scope
17359 * of the HWRM implementation that may clear forced down
17362 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
17365 * When set to 1, then the HWRM shall enable FEC RS544_1XN
17366 * on this port if supported, by advertising FEC RS544_1XN if
17367 * FEC autonegotiation is enabled or force enabled otherwise.
17368 * In forced mode, this flag will only take effect if the speed is
17369 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
17370 * HWRM shall choose one of the RS544 modes.
17371 * When set to 0, then this flag shall be ignored.
17372 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
17375 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
17378 * When set to 1, then the HWRM shall disable FEC RS544_1XN
17379 * on this port if supported, by not advertising FEC RS544_1XN if
17380 * FEC autonegotiation is enabled or force disabled otherwise.
17381 * When set to 0, then this flag shall be ignored.
17382 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
17385 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
17388 * When set to 1, then the HWRM shall enable FEC RS(544,514)
17389 * on this port if supported, by advertising FEC RS(544,514) if
17390 * FEC autonegotiation is enabled or force enabled otherwise.
17391 * In forced mode, this flag will only take effect if the speed is
17392 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
17393 * HWRM shall choose one of the RS544 modes.
17394 * When set to 0, then this flag shall be ignored.
17395 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
17398 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
17401 * When set to 1, then the HWRM shall disable FEC RS(544,514)
17402 * on this port if supported, by not advertising FEC RS(544,514) if
17403 * FEC autonegotiation is enabled or force disabled otherwise.
17404 * When set to 0, then this flag shall be ignored.
17405 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
17408 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
17411 * When set to 1, then the HWRM shall enable FEC RS272_1XN
17412 * on this port if supported, by advertising FEC RS272_1XN if
17413 * FEC autonegotiation is enabled or force enabled otherwise.
17414 * In forced mode, this flag will only take effect if the speed is
17415 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
17416 * HWRM shall choose one of the RS272 modes. Note that RS272
17417 * and RS544 modes cannot be set at the same time in forced FEC mode.
17418 * When set to 0, then this flag shall be ignored.
17419 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
17422 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
17425 * When set to 1, then the HWRM shall disable FEC RS272_1XN
17426 * on this port if supported, by not advertising FEC RS272_1XN if
17427 * FEC autonegotiation is enabled or force disabled otherwise.
17428 * When set to 0, then this flag shall be ignored.
17429 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
17432 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
17435 * When set to 1, then the HWRM shall enable FEC RS(272,257)
17436 * on this port if supported, by advertising FEC RS(272,257) if
17437 * FEC autonegotiation is enabled or force enabled otherwise.
17438 * In forced mode, this flag will only take effect if the speed is
17439 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
17440 * HWRM shall choose one of the RS272 modes. Note that RS272
17441 * and RS544 modes cannot be set at the same time in forced FEC mode.
17442 * When set to 0, then this flag shall be ignored.
17443 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
17446 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
17449 * When set to 1, then the HWRM shall disable FEC RS(272,257)
17450 * on this port if supported, by not advertising FEC RS(272,257) if
17451 * FEC autonegotiation is enabled or force disabled otherwise.
17452 * When set to 0, then this flag shall be ignored.
17453 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
17456 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
17460 * This bit must be '1' for the auto_mode field to be
17463 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
17466 * This bit must be '1' for the auto_duplex field to be
17469 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
17472 * This bit must be '1' for the auto_pause field to be
17475 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
17478 * This bit must be '1' for the auto_link_speed field to be
17481 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
17484 * This bit must be '1' for the auto_link_speed_mask field to be
17487 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
17490 * This bit must be '1' for the wirespeed field to be
17493 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
17496 * This bit must be '1' for the lpbk field to be
17499 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
17502 * This bit must be '1' for the preemphasis field to be
17505 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
17508 * This bit must be '1' for the force_pause field to be
17511 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
17514 * This bit must be '1' for the eee_link_speed_mask field to be
17517 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
17520 * This bit must be '1' for the tx_lpi_timer field to be
17523 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
17526 * This bit must be '1' for the force_pam4_link_speed field to be
17529 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
17532 * This bit must be '1' for the auto_pam4_link_speed_mask field to
17535 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
17537 /* Port ID of port that is to be configured. */
17540 * This is the speed that will be used if the force
17541 * bit is '1'. If unsupported speed is selected, an error
17542 * will be generated.
17544 uint16_t force_link_speed;
17545 /* 100Mb link speed */
17546 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
17547 /* 1Gb link speed */
17548 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
17549 /* 2Gb link speed */
17550 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
17551 /* 25Gb link speed */
17552 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
17553 /* 10Gb link speed */
17554 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
17555 /* 20Mb link speed */
17556 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
17557 /* 25Gb link speed */
17558 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
17559 /* 40Gb link speed */
17560 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
17561 /* 50Gb link speed */
17562 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
17563 /* 100Gb link speed */
17564 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
17565 /* 10Mb link speed */
17566 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
17567 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
17568 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
17570 * This value is used to identify what autoneg mode is
17571 * used when the link speed is not being forced.
17574 /* Disable autoneg or autoneg disabled. No speeds are selected. */
17575 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
17576 /* Select all possible speeds for autoneg mode. */
17577 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
17579 * Select only the auto_link_speed speed for autoneg mode. This mode has
17580 * been DEPRECATED. An HWRM client should not use this mode.
17582 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
17584 * Select the auto_link_speed or any speed below that speed for autoneg.
17585 * This mode has been DEPRECATED. An HWRM client should not use this mode.
17587 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
17589 * Select the speeds based on the corresponding link speed mask values
17590 * that are provided. The included speeds are specified in the
17591 * auto_link_speed and auto_pam4_link_speed fields.
17593 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
17594 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
17595 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
17597 * This is the duplex setting that will be used if the autoneg_mode
17598 * is "one_speed" or "one_or_below".
17600 uint8_t auto_duplex;
17601 /* Half Duplex will be requested. */
17602 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
17603 /* Full duplex will be requested. */
17604 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
17605 /* Both Half and Full dupex will be requested. */
17606 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
17607 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
17608 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
17610 * This value is used to configure the pause that will be
17611 * used for autonegotiation.
17612 * Add text on the usage of auto_pause and force_pause.
17614 uint8_t auto_pause;
17616 * When this bit is '1', Generation of tx pause messages
17617 * has been requested. Disabled otherwise.
17619 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
17622 * When this bit is '1', Reception of rx pause messages
17623 * has been requested. Disabled otherwise.
17625 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
17628 * When set to 1, the advertisement of pause is enabled.
17630 * # When the auto_mode is not set to none and this flag is
17631 * set to 1, then the auto_pause bits on this port are being
17632 * advertised and autoneg pause results are being interpreted.
17633 * # When the auto_mode is not set to none and this
17634 * flag is set to 0, the pause is forced as indicated in
17635 * force_pause, and also advertised as auto_pause bits, but
17636 * the autoneg results are not interpreted since the pause
17637 * configuration is being forced.
17638 * # When the auto_mode is set to none and this flag is set to
17639 * 1, auto_pause bits should be ignored and should be set to 0.
17641 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
17645 * This is the speed that will be used if the autoneg_mode
17646 * is "one_speed" or "one_or_below". If an unsupported speed
17647 * is selected, an error will be generated.
17649 uint16_t auto_link_speed;
17650 /* 100Mb link speed */
17651 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
17652 /* 1Gb link speed */
17653 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
17654 /* 2Gb link speed */
17655 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
17656 /* 25Gb link speed */
17657 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
17658 /* 10Gb link speed */
17659 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
17660 /* 20Mb link speed */
17661 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
17662 /* 25Gb link speed */
17663 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
17664 /* 40Gb link speed */
17665 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
17666 /* 50Gb link speed */
17667 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
17668 /* 100Gb link speed */
17669 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
17670 /* 10Mb link speed */
17671 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
17672 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
17673 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
17675 * This is a mask of link speeds that will be used if
17676 * autoneg_mode is "mask". If unsupported speed is enabled
17677 * an error will be generated.
17679 uint16_t auto_link_speed_mask;
17680 /* 100Mb link speed (Half-duplex) */
17681 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
17683 /* 100Mb link speed (Full-duplex) */
17684 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
17686 /* 1Gb link speed (Half-duplex) */
17687 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
17689 /* 1Gb link speed (Full-duplex) */
17690 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
17692 /* 2Gb link speed */
17693 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
17695 /* 25Gb link speed */
17696 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
17698 /* 10Gb link speed */
17699 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
17701 /* 20Gb link speed */
17702 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
17704 /* 25Gb link speed */
17705 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
17707 /* 40Gb link speed */
17708 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
17710 /* 50Gb link speed */
17711 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
17713 /* 100Gb link speed */
17714 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
17716 /* 10Mb link speed (Half-duplex) */
17717 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
17719 /* 10Mb link speed (Full-duplex) */
17720 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
17722 /* This value controls the wirespeed feature. */
17724 /* Wirespeed feature is disabled. */
17725 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
17726 /* Wirespeed feature is enabled. */
17727 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
17728 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
17729 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
17730 /* This value controls the loopback setting for the PHY. */
17732 /* No loopback is selected. Normal operation. */
17733 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
17735 * The HW will be configured with local loopback such that
17736 * host data is sent back to the host without modification.
17738 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
17740 * The HW will be configured with remote loopback such that
17741 * port logic will send packets back out the transmitter that
17744 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
17746 * The HW will be configured with external loopback such that
17747 * host data is sent on the transmitter and based on the external
17748 * loopback connection the data will be received without modification.
17750 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
17751 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
17752 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
17754 * This value is used to configure the pause that will be
17755 * used for force mode.
17757 uint8_t force_pause;
17759 * When this bit is '1', Generation of tx pause messages
17760 * is supported. Disabled otherwise.
17762 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
17764 * When this bit is '1', Reception of rx pause messages
17765 * is supported. Disabled otherwise.
17767 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
17770 * This value controls the pre-emphasis to be used for the
17771 * link. Driver should not set this value (use
17772 * enable.preemphasis = 0) unless driver is sure of setting.
17773 * Normally HWRM FW will determine proper pre-emphasis.
17775 uint32_t preemphasis;
17777 * Setting for link speed mask that is used to
17778 * advertise speeds during autonegotiation when EEE is enabled.
17779 * This field is valid only when EEE is enabled.
17780 * The speeds specified in this field shall be a subset of
17781 * speeds specified in auto_link_speed_mask.
17782 * If EEE is enabled,then at least one speed shall be provided
17785 uint16_t eee_link_speed_mask;
17787 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
17789 /* 100Mb link speed (Full-duplex) */
17790 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
17793 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
17795 /* 1Gb link speed (Full-duplex) */
17796 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
17799 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
17802 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
17804 /* 10Gb link speed */
17805 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
17808 * This is the speed that will be used if the force and force_pam4
17809 * bits are '1'. If unsupported speed is selected, an error
17810 * will be generated.
17812 uint16_t force_pam4_link_speed;
17813 /* 50Gb link speed */
17814 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
17816 /* 100Gb link speed */
17817 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
17819 /* 200Gb link speed */
17820 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
17822 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
17823 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
17825 * Requested setting of TX LPI timer in microseconds.
17826 * This field is valid only when EEE is enabled and TX LPI is
17829 uint32_t tx_lpi_timer;
17830 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
17831 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
17832 /* This field specifies which PAM4 speeds are enabled for auto mode. */
17833 uint16_t auto_link_pam4_speed_mask;
17834 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
17836 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
17838 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
17840 uint8_t unused_2[2];
17843 /* hwrm_port_phy_cfg_output (size:128b/16B) */
17844 struct hwrm_port_phy_cfg_output {
17845 /* The specific error status for the command. */
17846 uint16_t error_code;
17847 /* The HWRM command request type. */
17849 /* The sequence ID from the original command. */
17851 /* The length of the response data in number of bytes. */
17853 uint8_t unused_0[7];
17855 * This field is used in Output records to indicate that the output
17856 * is completely written to RAM. This field should be read as '1'
17857 * to indicate that the output has been completely written.
17858 * When writing a command completion or response to an internal processor,
17859 * the order of writes has to be such that this field is written last.
17864 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
17865 struct hwrm_port_phy_cfg_cmd_err {
17867 * command specific error codes that goes to
17868 * the cmd_err field in Common HWRM Error Response.
17871 /* Unknown error */
17872 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
17873 /* Unable to complete operation due to invalid speed */
17874 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
17876 * retry the command since the phy is not ready.
17877 * retry count is returned in opaque_0.
17878 * This is only valid for the first command and
17879 * this value will not change for successive calls.
17880 * but if a 0 is returned at any time then this should
17881 * be treated as an un recoverable failure,
17883 * retry interval in milli seconds is returned in opaque_1.
17884 * This specifies the time that user should wait before
17885 * issuing the next port_phy_cfg command.
17887 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
17888 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
17889 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
17890 uint8_t unused_0[7];
17893 /**********************
17894 * hwrm_port_phy_qcfg *
17895 **********************/
17898 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
17899 struct hwrm_port_phy_qcfg_input {
17900 /* The HWRM command request type. */
17903 * The completion ring to send the completion event on. This should
17904 * be the NQ ID returned from the `nq_alloc` HWRM command.
17906 uint16_t cmpl_ring;
17908 * The sequence ID is used by the driver for tracking multiple
17909 * commands. This ID is treated as opaque data by the firmware and
17910 * the value is returned in the `hwrm_resp_hdr` upon completion.
17914 * The target ID of the command:
17915 * * 0x0-0xFFF8 - The function ID
17916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17917 * * 0xFFFD - Reserved for user-space HWRM interface
17920 uint16_t target_id;
17922 * A physical address pointer pointing to a host buffer that the
17923 * command's response data will be written. This can be either a host
17924 * physical address (HPA) or a guest physical address (GPA) and must
17925 * point to a physically contiguous block of memory.
17927 uint64_t resp_addr;
17928 /* Port ID of port that is to be queried. */
17930 uint8_t unused_0[6];
17933 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
17934 struct hwrm_port_phy_qcfg_output {
17935 /* The specific error status for the command. */
17936 uint16_t error_code;
17937 /* The HWRM command request type. */
17939 /* The sequence ID from the original command. */
17941 /* The length of the response data in number of bytes. */
17943 /* This value indicates the current link status. */
17945 /* There is no link or cable detected. */
17946 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
17947 /* There is no link, but a cable has been detected. */
17948 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
17949 /* There is a link. */
17950 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
17951 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
17952 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
17953 uint8_t active_fec_signal_mode;
17955 * This value indicates the current link signaling mode of the
17958 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
17960 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
17961 /* NRZ signaling */
17962 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
17964 /* PAM4 signaling */
17965 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
17967 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
17968 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
17969 /* This value indicates the current active FEC mode. */
17970 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
17972 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
17973 /* No active FEC */
17974 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
17975 (UINT32_C(0x0) << 4)
17976 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
17977 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
17978 (UINT32_C(0x1) << 4)
17979 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
17980 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
17981 (UINT32_C(0x2) << 4)
17982 /* FEC RS544_1XN active, autonegoatiated or forced. */
17983 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
17984 (UINT32_C(0x3) << 4)
17985 /* FEC RS(544,528) active, autonegoatiated or forced. */
17986 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
17987 (UINT32_C(0x4) << 4)
17988 /* FEC RS272_1XN active, autonegotiated or forced. */
17989 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
17990 (UINT32_C(0x5) << 4)
17991 /* FEC RS(272,257) active, autonegoatiated or forced. */
17992 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
17993 (UINT32_C(0x6) << 4)
17994 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
17995 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
17997 * This value indicates the current link speed of the connection.
17998 * The signal_mode field indicates if the link is using
17999 * NRZ or PAM4 signaling.
18001 uint16_t link_speed;
18002 /* 100Mb link speed */
18003 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
18004 /* 1Gb link speed */
18005 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
18006 /* 2Gb link speed */
18007 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
18008 /* 25Gb link speed */
18009 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
18010 /* 10Gb link speed */
18011 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
18012 /* 20Mb link speed */
18013 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
18014 /* 25Gb link speed */
18015 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
18016 /* 40Gb link speed */
18017 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
18018 /* 50Gb link speed */
18019 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
18020 /* 100Gb link speed */
18021 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
18022 /* 200Gb link speed */
18023 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
18024 /* 10Mb link speed */
18025 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
18026 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
18027 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
18029 * This value is indicates the duplex of the current
18032 uint8_t duplex_cfg;
18033 /* Half Duplex connection. */
18034 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
18035 /* Full duplex connection. */
18036 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
18037 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
18038 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
18040 * This value is used to indicate the current
18041 * pause configuration. When autoneg is enabled, this value
18042 * represents the autoneg results of pause configuration.
18046 * When this bit is '1', Generation of tx pause messages
18047 * is supported. Disabled otherwise.
18049 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
18051 * When this bit is '1', Reception of rx pause messages
18052 * is supported. Disabled otherwise.
18054 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
18056 * The supported speeds for the port. This is a bit mask.
18057 * For each speed that is supported, the corresponding
18058 * bit will be set to '1'.
18060 uint16_t support_speeds;
18061 /* 100Mb link speed (Half-duplex) */
18062 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
18064 /* 100Mb link speed (Full-duplex) */
18065 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
18067 /* 1Gb link speed (Half-duplex) */
18068 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
18070 /* 1Gb link speed (Full-duplex) */
18071 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
18073 /* 2Gb link speed */
18074 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
18076 /* 25Gb link speed */
18077 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
18079 /* 10Gb link speed */
18080 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
18082 /* 20Gb link speed */
18083 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
18085 /* 25Gb link speed */
18086 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
18088 /* 40Gb link speed */
18089 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
18091 /* 50Gb link speed */
18092 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
18094 /* 100Gb link speed */
18095 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
18097 /* 10Mb link speed (Half-duplex) */
18098 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
18100 /* 10Mb link speed (Full-duplex) */
18101 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
18104 * Current setting of forced link speed.
18105 * When the link speed is not being forced, this
18106 * value shall be set to 0.
18108 uint16_t force_link_speed;
18109 /* 100Mb link speed */
18110 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
18111 /* 1Gb link speed */
18112 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
18113 /* 2Gb link speed */
18114 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
18115 /* 25Gb link speed */
18116 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
18117 /* 10Gb link speed */
18118 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
18119 /* 20Mb link speed */
18120 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
18121 /* 25Gb link speed */
18122 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
18123 /* 40Gb link speed */
18124 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
18126 /* 50Gb link speed */
18127 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
18129 /* 100Gb link speed */
18130 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
18132 /* 10Mb link speed */
18133 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
18135 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
18136 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
18137 /* Current setting of auto negotiation mode. */
18139 /* Disable autoneg or autoneg disabled. No speeds are selected. */
18140 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
18141 /* Select all possible speeds for autoneg mode. */
18142 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
18144 * Select only the auto_link_speed speed for autoneg mode. This mode has
18145 * been DEPRECATED. An HWRM client should not use this mode.
18147 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
18149 * Select the auto_link_speed or any speed below that speed for autoneg.
18150 * This mode has been DEPRECATED. An HWRM client should not use this mode.
18152 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
18154 * Select the speeds based on the corresponding link speed mask value
18155 * that is provided.
18157 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
18158 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
18159 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
18161 * Current setting of pause autonegotiation.
18162 * Move autoneg_pause flag here.
18164 uint8_t auto_pause;
18166 * When this bit is '1', Generation of tx pause messages
18167 * has been requested. Disabled otherwise.
18169 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
18172 * When this bit is '1', Reception of rx pause messages
18173 * has been requested. Disabled otherwise.
18175 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
18178 * When set to 1, the advertisement of pause is enabled.
18180 * # When the auto_mode is not set to none and this flag is
18181 * set to 1, then the auto_pause bits on this port are being
18182 * advertised and autoneg pause results are being interpreted.
18183 * # When the auto_mode is not set to none and this
18184 * flag is set to 0, the pause is forced as indicated in
18185 * force_pause, and also advertised as auto_pause bits, but
18186 * the autoneg results are not interpreted since the pause
18187 * configuration is being forced.
18188 * # When the auto_mode is set to none and this flag is set to
18189 * 1, auto_pause bits should be ignored and should be set to 0.
18191 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
18194 * Current setting for auto_link_speed. This field is only
18195 * valid when auto_mode is set to "one_speed" or "one_or_below".
18197 uint16_t auto_link_speed;
18198 /* 100Mb link speed */
18199 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
18200 /* 1Gb link speed */
18201 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
18202 /* 2Gb link speed */
18203 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
18204 /* 25Gb link speed */
18205 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
18206 /* 10Gb link speed */
18207 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
18208 /* 20Mb link speed */
18209 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
18210 /* 25Gb link speed */
18211 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
18212 /* 40Gb link speed */
18213 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
18214 /* 50Gb link speed */
18215 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
18216 /* 100Gb link speed */
18217 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
18218 /* 10Mb link speed */
18219 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
18221 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
18222 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
18224 * Current setting for auto_link_speed_mask that is used to
18225 * advertise speeds during autonegotiation.
18226 * This field is only valid when auto_mode is set to "mask".
18227 * The speeds specified in this field shall be a subset of
18228 * supported speeds on this port.
18230 uint16_t auto_link_speed_mask;
18231 /* 100Mb link speed (Half-duplex) */
18232 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
18234 /* 100Mb link speed (Full-duplex) */
18235 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
18237 /* 1Gb link speed (Half-duplex) */
18238 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
18240 /* 1Gb link speed (Full-duplex) */
18241 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
18243 /* 2Gb link speed */
18244 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
18246 /* 25Gb link speed */
18247 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
18249 /* 10Gb link speed */
18250 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
18252 /* 20Gb link speed */
18253 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
18255 /* 25Gb link speed */
18256 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
18258 /* 40Gb link speed */
18259 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
18261 /* 50Gb link speed */
18262 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
18264 /* 100Gb link speed */
18265 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
18267 /* 10Mb link speed (Half-duplex) */
18268 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
18270 /* 10Mb link speed (Full-duplex) */
18271 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
18273 /* Current setting for wirespeed. */
18275 /* Wirespeed feature is disabled. */
18276 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
18277 /* Wirespeed feature is enabled. */
18278 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
18279 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
18280 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
18281 /* Current setting for loopback. */
18283 /* No loopback is selected. Normal operation. */
18284 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
18286 * The HW will be configured with local loopback such that
18287 * host data is sent back to the host without modification.
18289 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
18291 * The HW will be configured with remote loopback such that
18292 * port logic will send packets back out the transmitter that
18295 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
18297 * The HW will be configured with external loopback such that
18298 * host data is sent on the transmitter and based on the external
18299 * loopback connection the data will be received without modification.
18301 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
18302 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
18303 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
18305 * Current setting of forced pause.
18306 * When the pause configuration is not being forced, then
18307 * this value shall be set to 0.
18309 uint8_t force_pause;
18311 * When this bit is '1', Generation of tx pause messages
18312 * is supported. Disabled otherwise.
18314 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
18316 * When this bit is '1', Reception of rx pause messages
18317 * is supported. Disabled otherwise.
18319 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
18321 * This value indicates the current status of the optics module on
18324 uint8_t module_status;
18325 /* Module is inserted and accepted */
18326 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
18328 /* Module is rejected and transmit side Laser is disabled. */
18329 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
18331 /* Module mismatch warning. */
18332 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
18334 /* Module is rejected and powered down. */
18335 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
18337 /* Module is not inserted. */
18338 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
18340 /* Module is powered down because of over current fault. */
18341 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
18343 /* Module status is not applicable. */
18344 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
18346 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
18347 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
18348 /* Current setting for preemphasis. */
18349 uint32_t preemphasis;
18350 /* This field represents the major version of the PHY. */
18352 /* This field represents the minor version of the PHY. */
18354 /* This field represents the build version of the PHY. */
18356 /* This value represents a PHY type. */
18359 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
18362 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
18364 /* BASE-KR4 (Deprecated) */
18365 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
18368 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
18371 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
18373 /* BASE-KR2 (Deprecated) */
18374 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
18377 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
18380 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
18383 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
18385 /* EEE capable BASE-T */
18386 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
18388 /* SGMII connected external PHY */
18389 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
18391 /* 25G_BASECR_CA_L */
18392 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
18394 /* 25G_BASECR_CA_S */
18395 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
18397 /* 25G_BASECR_CA_N */
18398 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
18401 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
18404 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
18407 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
18410 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
18413 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
18415 /* 100G_BASESR10 */
18416 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
18419 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
18422 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
18425 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
18428 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
18430 /* 40G_ACTIVE_CABLE */
18431 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
18434 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
18437 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
18440 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
18443 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
18446 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
18449 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
18452 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
18454 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
18455 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
18456 /* This value represents a media type. */
18457 uint8_t media_type;
18459 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
18461 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
18462 /* Direct Attached Copper */
18463 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
18465 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
18466 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
18467 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
18468 /* This value represents a transceiver type. */
18469 uint8_t xcvr_pkg_type;
18470 /* PHY and MAC are in the same package */
18471 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
18473 /* PHY and MAC are in different packages */
18474 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
18476 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
18477 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
18478 uint8_t eee_config_phy_addr;
18479 /* This field represents PHY address. */
18480 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
18482 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
18484 * This field represents flags related to EEE configuration.
18485 * These EEE configuration flags are valid only when the
18486 * auto_mode is not set to none (in other words autonegotiation
18489 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
18491 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
18493 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
18494 * Speeds for autoneg with EEE mode enabled
18495 * are based on eee_link_speed_mask.
18497 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
18500 * This flag is valid only when eee_enabled is set to 1.
18502 * # If eee_enabled is set to 0, then EEE mode is disabled
18503 * and this flag shall be ignored.
18504 * # If eee_enabled is set to 1 and this flag is set to 1,
18505 * then Energy Efficient Ethernet (EEE) mode is enabled
18507 * # If eee_enabled is set to 1 and this flag is set to 0,
18508 * then Energy Efficient Ethernet (EEE) mode is enabled
18509 * but is currently not in use.
18511 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
18514 * This flag is valid only when eee_enabled is set to 1.
18516 * # If eee_enabled is set to 0, then EEE mode is disabled
18517 * and this flag shall be ignored.
18518 * # If eee_enabled is set to 1 and this flag is set to 1,
18519 * then Energy Efficient Ethernet (EEE) mode is enabled
18520 * and TX LPI is enabled.
18521 * # If eee_enabled is set to 1 and this flag is set to 0,
18522 * then Energy Efficient Ethernet (EEE) mode is enabled
18523 * but TX LPI is disabled.
18525 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
18528 * When set to 1, the parallel detection is used to determine
18529 * the speed of the link partner.
18531 * Parallel detection is used when a autonegotiation capable
18532 * device is connected to a link parter that is not capable
18533 * of autonegotiation.
18535 uint8_t parallel_detect;
18537 * When set to 1, the parallel detection is used to determine
18538 * the speed of the link partner.
18540 * Parallel detection is used when a autonegotiation capable
18541 * device is connected to a link parter that is not capable
18542 * of autonegotiation.
18544 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
18546 * The advertised speeds for the port by the link partner.
18547 * Each advertised speed will be set to '1'.
18549 uint16_t link_partner_adv_speeds;
18550 /* 100Mb link speed (Half-duplex) */
18551 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
18553 /* 100Mb link speed (Full-duplex) */
18554 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
18556 /* 1Gb link speed (Half-duplex) */
18557 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
18559 /* 1Gb link speed (Full-duplex) */
18560 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
18562 /* 2Gb link speed */
18563 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
18565 /* 25Gb link speed */
18566 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
18568 /* 10Gb link speed */
18569 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
18571 /* 20Gb link speed */
18572 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
18574 /* 25Gb link speed */
18575 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
18577 /* 40Gb link speed */
18578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
18580 /* 50Gb link speed */
18581 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
18583 /* 100Gb link speed */
18584 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
18586 /* 10Mb link speed (Half-duplex) */
18587 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
18589 /* 10Mb link speed (Full-duplex) */
18590 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
18593 * The advertised autoneg for the port by the link partner.
18594 * This field is deprecated and should be set to 0.
18596 uint8_t link_partner_adv_auto_mode;
18597 /* Disable autoneg or autoneg disabled. No speeds are selected. */
18598 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
18600 /* Select all possible speeds for autoneg mode. */
18601 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
18604 * Select only the auto_link_speed speed for autoneg mode. This mode has
18605 * been DEPRECATED. An HWRM client should not use this mode.
18607 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
18610 * Select the auto_link_speed or any speed below that speed for autoneg.
18611 * This mode has been DEPRECATED. An HWRM client should not use this mode.
18613 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
18616 * Select the speeds based on the corresponding link speed mask value
18617 * that is provided.
18619 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
18621 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
18622 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
18623 /* The advertised pause settings on the port by the link partner. */
18624 uint8_t link_partner_adv_pause;
18626 * When this bit is '1', Generation of tx pause messages
18627 * is supported. Disabled otherwise.
18629 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
18632 * When this bit is '1', Reception of rx pause messages
18633 * is supported. Disabled otherwise.
18635 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
18638 * Current setting for link speed mask that is used to
18639 * advertise speeds during autonegotiation when EEE is enabled.
18640 * This field is valid only when eee_enabled flags is set to 1.
18641 * The speeds specified in this field shall be a subset of
18642 * speeds specified in auto_link_speed_mask.
18644 uint16_t adv_eee_link_speed_mask;
18646 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
18648 /* 100Mb link speed (Full-duplex) */
18649 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
18652 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
18654 /* 1Gb link speed (Full-duplex) */
18655 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
18658 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
18661 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
18663 /* 10Gb link speed */
18664 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
18667 * Current setting for link speed mask that is advertised by
18668 * the link partner when EEE is enabled.
18669 * This field is valid only when eee_enabled flags is set to 1.
18671 uint16_t link_partner_adv_eee_link_speed_mask;
18673 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
18675 /* 100Mb link speed (Full-duplex) */
18676 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
18679 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
18681 /* 1Gb link speed (Full-duplex) */
18682 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
18685 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
18688 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
18690 /* 10Gb link speed */
18691 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
18693 uint32_t xcvr_identifier_type_tx_lpi_timer;
18695 * Current setting of TX LPI timer in microseconds.
18696 * This field is valid only when_eee_enabled flag is set to 1
18697 * and tx_lpi_enabled is set to 1.
18699 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
18701 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
18702 /* This value represents transceiver identifier type. */
18703 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
18704 UINT32_C(0xff000000)
18705 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
18707 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
18708 (UINT32_C(0x0) << 24)
18709 /* SFP/SFP+/SFP28 */
18710 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
18711 (UINT32_C(0x3) << 24)
18713 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
18714 (UINT32_C(0xc) << 24)
18716 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
18717 (UINT32_C(0xd) << 24)
18719 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
18720 (UINT32_C(0x11) << 24)
18721 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
18722 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
18724 * This value represents the current configuration of
18725 * Forward Error Correction (FEC) on the port.
18729 * When set to 1, then FEC is not supported on this port. If this flag
18730 * is set to 1, then all other FEC configuration flags shall be ignored.
18731 * When set to 0, then FEC is supported as indicated by other
18732 * configuration flags.
18734 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
18737 * When set to 1, then FEC autonegotiation is supported on this port.
18738 * When set to 0, then FEC autonegotiation is not supported on this port.
18740 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
18743 * When set to 1, then FEC autonegotiation is enabled on this port.
18744 * When set to 0, then FEC autonegotiation is disabled if supported.
18745 * This flag should be ignored if FEC autonegotiation is not supported on this port.
18747 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
18750 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
18751 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
18753 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
18756 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
18757 * port. This means that FEC CLAUSE 74 is either advertised if
18758 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
18759 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
18760 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
18762 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
18765 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
18766 * NRZ) is supported on this port.
18767 * When set to 0, then FEC RS(528,418) is not supported on this port.
18769 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
18772 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
18773 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
18774 * either advertised if FEC autonegotiation is enabled or FEC
18775 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
18776 * is disabled if supported.
18777 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
18779 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
18782 * When set to 1, then FEC RS544_1XN is supported on this port.
18783 * When set to 0, then FEC RS544_1XN is not supported on this port.
18785 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
18788 * When set to 1, then RS544_1XN is enabled on this
18789 * port. This means that FEC RS544_1XN is either advertised if
18790 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
18791 * When set to 0, then FEC RS544_1XN is disabled if supported.
18792 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
18794 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
18797 * When set to 1, then FEC RS(544,514) is supported on this port.
18798 * When set to 0, then FEC RS(544,514) is not supported on this port.
18800 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
18803 * When set to 1, then RS(544,514) is enabled on this
18804 * port. This means that FEC RS(544,514) is either advertised if
18805 * FEC autonegotiation is enabled or FEC RS(544,514) is force
18806 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
18807 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
18809 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
18812 * When set to 1, then FEC RS272_1XN is supported on this port.
18813 * When set to 0, then FEC RS272_1XN is not supported on this port.
18815 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
18818 * When set to 1, then RS272_1XN is enabled on this
18819 * port. This means that FEC RS272_1XN is either advertised if
18820 * FEC autonegotiation is enabled or FEC RS272_1XN is force
18821 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
18822 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
18824 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
18827 * When set to 1, then FEC RS(272,514) is supported on this port.
18828 * When set to 0, then FEC RS(272,514) is not supported on this port.
18830 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
18833 * When set to 1, then RS(272,257) is enabled on this
18834 * port. This means that FEC RS(272,257) is either advertised if
18835 * FEC autonegotiation is enabled or FEC RS(272,257) is force
18836 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
18837 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
18839 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
18842 * This value is indicates the duplex of the current
18843 * connection state.
18845 uint8_t duplex_state;
18846 /* Half Duplex connection. */
18847 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
18848 /* Full duplex connection. */
18849 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
18850 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
18851 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
18852 /* Option flags fields. */
18853 uint8_t option_flags;
18854 /* When this bit is '1', Media auto detect is enabled. */
18855 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
18858 * Up to 16 bytes of null padded ASCII string representing
18860 * If the string is set to null, then the vendor name is not
18863 char phy_vendor_name[16];
18865 * Up to 16 bytes of null padded ASCII string that
18866 * identifies vendor specific part number of the PHY.
18867 * If the string is set to null, then the vendor specific
18868 * part number is not available.
18870 char phy_vendor_partnumber[16];
18872 * The supported PAM4 speeds for the port. This is a bit mask.
18873 * For each speed that is supported, the corresponding
18874 * bit will be set to '1'.
18876 uint16_t support_pam4_speeds;
18877 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
18879 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
18881 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
18884 * Current setting of forced PAM4 link speed.
18885 * When the link speed is not being forced, this
18886 * value shall be set to 0.
18888 uint16_t force_pam4_link_speed;
18889 /* 50Gb link speed */
18890 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
18892 /* 100Gb link speed */
18893 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
18895 /* 200Gb link speed */
18896 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
18898 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
18899 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
18901 * Current setting for auto_pam4_link_speed_mask that is used to
18902 * advertise speeds during autonegotiation.
18903 * This field is only valid when auto_mode is set to "mask".
18904 * The speeds specified in this field shall be a subset of
18905 * supported speeds on this port.
18907 uint16_t auto_pam4_link_speed_mask;
18908 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
18910 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
18912 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
18915 * The advertised PAM4 speeds for the port by the link partner.
18916 * Each advertised speed will be set to '1'.
18918 uint8_t link_partner_pam4_adv_speeds;
18919 /* 50Gb link speed */
18920 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
18922 /* 100Gb link speed */
18923 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
18925 /* 200Gb link speed */
18926 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
18929 * This field is used in Output records to indicate that the output
18930 * is completely written to RAM. This field should be read as '1'
18931 * to indicate that the output has been completely written.
18932 * When writing a command completion or response to an internal processor,
18933 * the order of writes has to be such that this field is written last.
18938 /*********************
18939 * hwrm_port_mac_cfg *
18940 *********************/
18943 /* hwrm_port_mac_cfg_input (size:384b/48B) */
18944 struct hwrm_port_mac_cfg_input {
18945 /* The HWRM command request type. */
18948 * The completion ring to send the completion event on. This should
18949 * be the NQ ID returned from the `nq_alloc` HWRM command.
18951 uint16_t cmpl_ring;
18953 * The sequence ID is used by the driver for tracking multiple
18954 * commands. This ID is treated as opaque data by the firmware and
18955 * the value is returned in the `hwrm_resp_hdr` upon completion.
18959 * The target ID of the command:
18960 * * 0x0-0xFFF8 - The function ID
18961 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18962 * * 0xFFFD - Reserved for user-space HWRM interface
18965 uint16_t target_id;
18967 * A physical address pointer pointing to a host buffer that the
18968 * command's response data will be written. This can be either a host
18969 * physical address (HPA) or a guest physical address (GPA) and must
18970 * point to a physically contiguous block of memory.
18972 uint64_t resp_addr;
18974 * In this field, there are a number of CoS mappings related flags
18975 * that are used to configure CoS mappings and their corresponding
18976 * priorities in the hardware.
18977 * For the priorities of CoS mappings, the HWRM uses the following
18978 * priority order (high to low) by default:
18981 * # tunnel_vlan_pri
18984 * A subset of CoS mappings can be enabled.
18985 * If a priority is not specified for an enabled CoS mapping, the
18986 * priority will be assigned in the above order for the enabled CoS
18987 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
18988 * enabled and their priorities are not specified, the following
18989 * priority order (high to low) will be used by the HWRM:
18994 * vlan_pri CoS mapping together with default CoS with lower priority
18995 * are enabled by default by the HWRM.
18999 * When this bit is '1', this command will configure
19000 * the MAC to match the current link state of the PHY.
19001 * If the link is not established on the PHY, then this
19002 * bit has no effect.
19004 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
19007 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
19008 * is requested to be enabled.
19010 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
19013 * When this bit is set to '1', tunnel VLAN PRI field to
19014 * CoS mapping is requested to be enabled.
19016 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
19019 * When this bit is set to '1', the IP DSCP to CoS mapping is
19020 * requested to be enabled.
19022 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
19025 * When this bit is '1', the HWRM is requested to
19026 * enable timestamp capture capability on the receive side
19029 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
19032 * When this bit is '1', the HWRM is requested to
19033 * disable timestamp capture capability on the receive side
19036 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
19039 * When this bit is '1', the HWRM is requested to
19040 * enable timestamp capture capability on the transmit side
19043 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
19046 * When this bit is '1', the HWRM is requested to
19047 * disable timestamp capture capability on the transmit side
19050 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
19053 * When this bit is '1', the Out-Of-Box WoL is requested to
19054 * be enabled on this port.
19056 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
19059 * When this bit is '1', the Out-Of-Box WoL is requested to
19060 * be disabled on this port.
19062 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
19065 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
19066 * is requested to be disabled.
19068 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
19071 * When this bit is set to '1', tunnel VLAN PRI field to
19072 * CoS mapping is requested to be disabled.
19074 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
19077 * When this bit is set to '1', the IP DSCP to CoS mapping is
19078 * requested to be disabled.
19080 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
19083 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
19084 * bit is set, then the device uses one step Tx timestamping.
19085 * This bit is temporary and used for experimental purposes.
19087 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
19091 * This bit must be '1' for the ipg field to be
19094 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
19097 * This bit must be '1' for the lpbk field to be
19100 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
19103 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
19106 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
19109 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
19112 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
19115 * This bit must be '1' for the dscp2cos_map_pri field to be
19118 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
19121 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
19124 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
19127 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
19130 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
19133 * This bit must be '1' for the cos_field_cfg field to be
19136 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
19139 * This bit must be '1' for the ptp_freq_adj_ppb field to be
19142 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
19144 /* Port ID of port that is to be configured. */
19147 * This value is used to configure the minimum IPG that will
19148 * be sent between packets by this port.
19151 /* This value controls the loopback setting for the MAC. */
19153 /* No loopback is selected. Normal operation. */
19154 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
19156 * The HW will be configured with local loopback such that
19157 * host data is sent back to the host without modification.
19159 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
19161 * The HW will be configured with remote loopback such that
19162 * port logic will send packets back out the transmitter that
19165 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
19166 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
19167 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
19169 * This value controls the priority setting of VLAN PRI to CoS
19170 * mapping based on VLAN Tags of inner packet headers of
19171 * tunneled packets or packet headers of non-tunneled packets.
19173 * # Each XXX_pri variable shall have a unique priority value
19174 * when it is being specified.
19175 * # When comparing priorities of mappings, higher value
19176 * indicates higher priority.
19177 * For example, a value of 0-3 is returned where 0 is being
19178 * the lowest priority and 3 is being the highest priority.
19180 uint8_t vlan_pri2cos_map_pri;
19181 /* Reserved field. */
19184 * This value controls the priority setting of VLAN PRI to CoS
19185 * mapping based on VLAN Tags of tunneled header.
19186 * This mapping only applies when tunneled headers
19189 * # Each XXX_pri variable shall have a unique priority value
19190 * when it is being specified.
19191 * # When comparing priorities of mappings, higher value
19192 * indicates higher priority.
19193 * For example, a value of 0-3 is returned where 0 is being
19194 * the lowest priority and 3 is being the highest priority.
19196 uint8_t tunnel_pri2cos_map_pri;
19198 * This value controls the priority setting of IP DSCP to CoS
19199 * mapping based on inner IP header of tunneled packets or
19200 * IP header of non-tunneled packets.
19202 * # Each XXX_pri variable shall have a unique priority value
19203 * when it is being specified.
19204 * # When comparing priorities of mappings, higher value
19205 * indicates higher priority.
19206 * For example, a value of 0-3 is returned where 0 is being
19207 * the lowest priority and 3 is being the highest priority.
19209 uint8_t dscp2pri_map_pri;
19211 * This is a 16-bit bit mask that is used to request a
19212 * specific configuration of time stamp capture of PTP messages
19213 * on the receive side of this port.
19214 * This field shall be ignored if the ptp_rx_ts_capture_enable
19215 * flag is not set in this command.
19216 * Otherwise, if bit 'i' is set, then the HWRM is being
19217 * requested to configure the receive side of the port to
19218 * capture the time stamp of every received PTP message
19219 * with messageType field value set to i.
19221 uint16_t rx_ts_capture_ptp_msg_type;
19223 * This is a 16-bit bit mask that is used to request a
19224 * specific configuration of time stamp capture of PTP messages
19225 * on the transmit side of this port.
19226 * This field shall be ignored if the ptp_tx_ts_capture_enable
19227 * flag is not set in this command.
19228 * Otherwise, if bit 'i' is set, then the HWRM is being
19229 * requested to configure the transmit side of the port to
19230 * capture the time stamp of every transmitted PTP message
19231 * with messageType field value set to i.
19233 uint16_t tx_ts_capture_ptp_msg_type;
19234 /* Configuration of CoS fields. */
19235 uint8_t cos_field_cfg;
19237 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
19240 * This field is used to specify selection of VLAN PRI value
19241 * based on whether one or two VLAN Tags are present in
19242 * the inner packet headers of tunneled packets or
19243 * non-tunneled packets.
19244 * This field is valid only if inner VLAN PRI to CoS mapping
19246 * If VLAN PRI to CoS mapping is not enabled, then this
19247 * field shall be ignored.
19249 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
19251 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
19254 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
19255 * present in the inner packet headers
19257 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
19258 (UINT32_C(0x0) << 1)
19260 * Select outer VLAN Tag PRI when 2 VLAN Tags are
19261 * present in the inner packet headers.
19262 * No VLAN PRI shall be selected for this configuration
19263 * if only one VLAN Tag is present in the inner
19266 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
19267 (UINT32_C(0x1) << 1)
19269 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
19270 * are present in the inner packet headers
19272 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
19273 (UINT32_C(0x2) << 1)
19275 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
19276 (UINT32_C(0x3) << 1)
19277 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
19278 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
19280 * This field is used to specify selection of tunnel VLAN
19281 * PRI value based on whether one or two VLAN Tags are
19282 * present in tunnel headers.
19283 * This field is valid only if tunnel VLAN PRI to CoS mapping
19285 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
19286 * field shall be ignored.
19288 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
19290 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
19293 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
19294 * present in the tunnel packet headers
19296 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
19297 (UINT32_C(0x0) << 3)
19299 * Select outer VLAN Tag PRI when 2 VLAN Tags are
19300 * present in the tunnel packet headers.
19301 * No tunnel VLAN PRI shall be selected for this
19302 * configuration if only one VLAN Tag is present in
19303 * the tunnel packet headers.
19305 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
19306 (UINT32_C(0x1) << 3)
19308 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
19309 * are present in the tunnel packet headers
19311 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
19312 (UINT32_C(0x2) << 3)
19314 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
19315 (UINT32_C(0x3) << 3)
19316 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
19317 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
19319 * This field shall be used to provide default CoS value
19320 * that has been configured on this port.
19321 * This field is valid only if default CoS mapping
19323 * If default CoS mapping is not enabled, then this
19324 * field shall be ignored.
19326 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
19328 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
19330 uint8_t unused_0[3];
19332 * This signed field specifies by how much to adjust the frequency
19333 * of sync timer updates (measured in parts per billion).
19335 int32_t ptp_freq_adj_ppb;
19336 uint8_t unused_1[4];
19339 /* hwrm_port_mac_cfg_output (size:128b/16B) */
19340 struct hwrm_port_mac_cfg_output {
19341 /* The specific error status for the command. */
19342 uint16_t error_code;
19343 /* The HWRM command request type. */
19345 /* The sequence ID from the original command. */
19347 /* The length of the response data in number of bytes. */
19350 * This is the configured maximum length of Ethernet packet
19351 * payload that is allowed to be received on the port.
19352 * This value does not include the number of bytes used by
19353 * Ethernet header and trailer (CRC).
19357 * This is the configured maximum length of Ethernet packet
19358 * payload that is allowed to be transmitted on the port.
19359 * This value does not include the number of bytes used by
19360 * Ethernet header and trailer (CRC).
19363 /* Current configuration of the IPG value. */
19365 /* Current value of the loopback value. */
19367 /* No loopback is selected. Normal operation. */
19368 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
19370 * The HW will be configured with local loopback such that
19371 * host data is sent back to the host without modification.
19373 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
19375 * The HW will be configured with remote loopback such that
19376 * port logic will send packets back out the transmitter that
19379 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
19380 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
19381 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
19384 * This field is used in Output records to indicate that the output
19385 * is completely written to RAM. This field should be read as '1'
19386 * to indicate that the output has been completely written.
19387 * When writing a command completion or response to an internal processor,
19388 * the order of writes has to be such that this field is written last.
19393 /**********************
19394 * hwrm_port_mac_qcfg *
19395 **********************/
19398 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
19399 struct hwrm_port_mac_qcfg_input {
19400 /* The HWRM command request type. */
19403 * The completion ring to send the completion event on. This should
19404 * be the NQ ID returned from the `nq_alloc` HWRM command.
19406 uint16_t cmpl_ring;
19408 * The sequence ID is used by the driver for tracking multiple
19409 * commands. This ID is treated as opaque data by the firmware and
19410 * the value is returned in the `hwrm_resp_hdr` upon completion.
19414 * The target ID of the command:
19415 * * 0x0-0xFFF8 - The function ID
19416 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19417 * * 0xFFFD - Reserved for user-space HWRM interface
19420 uint16_t target_id;
19422 * A physical address pointer pointing to a host buffer that the
19423 * command's response data will be written. This can be either a host
19424 * physical address (HPA) or a guest physical address (GPA) and must
19425 * point to a physically contiguous block of memory.
19427 uint64_t resp_addr;
19428 /* Port ID of port that is to be configured. */
19430 uint8_t unused_0[6];
19433 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
19434 struct hwrm_port_mac_qcfg_output {
19435 /* The specific error status for the command. */
19436 uint16_t error_code;
19437 /* The HWRM command request type. */
19439 /* The sequence ID from the original command. */
19441 /* The length of the response data in number of bytes. */
19444 * This is the configured maximum length of Ethernet packet
19445 * payload that is allowed to be received on the port.
19446 * This value does not include the number of bytes used by the
19447 * Ethernet header and trailer (CRC).
19451 * This is the configured maximum length of Ethernet packet
19452 * payload that is allowed to be transmitted on the port.
19453 * This value does not include the number of bytes used by the
19454 * Ethernet header and trailer (CRC).
19458 * The minimum IPG that will
19459 * be sent between packets by this port.
19462 /* The loopback setting for the MAC. */
19464 /* No loopback is selected. Normal operation. */
19465 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
19467 * The HW will be configured with local loopback such that
19468 * host data is sent back to the host without modification.
19470 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
19472 * The HW will be configured with remote loopback such that
19473 * port logic will send packets back out the transmitter that
19476 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
19477 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
19478 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
19480 * Priority setting for VLAN PRI to CoS mapping.
19481 * # Each XXX_pri variable shall have a unique priority value
19482 * when it is being used.
19483 * # When comparing priorities of mappings, higher value
19484 * indicates higher priority.
19485 * For example, a value of 0-3 is returned where 0 is being
19486 * the lowest priority and 3 is being the highest priority.
19487 * # If the correspoding CoS mapping is not enabled, then this
19488 * field should be ignored.
19489 * # This value indicates the normalized priority value retained
19492 uint8_t vlan_pri2cos_map_pri;
19494 * In this field, a number of CoS mappings related flags
19495 * are used to indicate configured CoS mappings.
19499 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
19502 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
19505 * When this bit is set to '1', tunnel VLAN PRI field to
19506 * CoS mapping is enabled.
19508 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
19511 * When this bit is set to '1', the IP DSCP to CoS mapping is
19514 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
19517 * When this bit is '1', the Out-Of-Box WoL is enabled on this
19520 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
19522 /* When this bit is '1', PTP is enabled for RX on this port. */
19523 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
19525 /* When this bit is '1', PTP is enabled for TX on this port. */
19526 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
19529 * Priority setting for tunnel VLAN PRI to CoS mapping.
19530 * # Each XXX_pri variable shall have a unique priority value
19531 * when it is being used.
19532 * # When comparing priorities of mappings, higher value
19533 * indicates higher priority.
19534 * For example, a value of 0-3 is returned where 0 is being
19535 * the lowest priority and 3 is being the highest priority.
19536 * # If the correspoding CoS mapping is not enabled, then this
19537 * field should be ignored.
19538 * # This value indicates the normalized priority value retained
19541 uint8_t tunnel_pri2cos_map_pri;
19543 * Priority setting for DSCP to PRI mapping.
19544 * # Each XXX_pri variable shall have a unique priority value
19545 * when it is being used.
19546 * # When comparing priorities of mappings, higher value
19547 * indicates higher priority.
19548 * For example, a value of 0-3 is returned where 0 is being
19549 * the lowest priority and 3 is being the highest priority.
19550 * # If the correspoding CoS mapping is not enabled, then this
19551 * field should be ignored.
19552 * # This value indicates the normalized priority value retained
19555 uint8_t dscp2pri_map_pri;
19557 * This is a 16-bit bit mask that represents the
19558 * current configuration of time stamp capture of PTP messages
19559 * on the receive side of this port.
19560 * If bit 'i' is set, then the receive side of the port
19561 * is configured to capture the time stamp of every
19562 * received PTP message with messageType field value set
19564 * If all bits are set to 0 (i.e. field value set 0),
19565 * then the receive side of the port is not configured
19566 * to capture timestamp for PTP messages.
19567 * If all bits are set to 1, then the receive side of the
19568 * port is configured to capture timestamp for all PTP
19571 uint16_t rx_ts_capture_ptp_msg_type;
19573 * This is a 16-bit bit mask that represents the
19574 * current configuration of time stamp capture of PTP messages
19575 * on the transmit side of this port.
19576 * If bit 'i' is set, then the transmit side of the port
19577 * is configured to capture the time stamp of every
19578 * received PTP message with messageType field value set
19580 * If all bits are set to 0 (i.e. field value set 0),
19581 * then the transmit side of the port is not configured
19582 * to capture timestamp for PTP messages.
19583 * If all bits are set to 1, then the transmit side of the
19584 * port is configured to capture timestamp for all PTP
19587 uint16_t tx_ts_capture_ptp_msg_type;
19588 /* Configuration of CoS fields. */
19589 uint8_t cos_field_cfg;
19591 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
19594 * This field is used for selecting VLAN PRI value
19595 * based on whether one or two VLAN Tags are present in
19596 * the inner packet headers of tunneled packets or
19597 * non-tunneled packets.
19599 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
19601 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
19604 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
19605 * present in the inner packet headers
19607 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
19608 (UINT32_C(0x0) << 1)
19610 * Select outer VLAN Tag PRI when 2 VLAN Tags are
19611 * present in the inner packet headers.
19612 * No VLAN PRI is selected for this configuration
19613 * if only one VLAN Tag is present in the inner
19616 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
19617 (UINT32_C(0x1) << 1)
19619 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
19620 * are present in the inner packet headers
19622 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
19623 (UINT32_C(0x2) << 1)
19625 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
19626 (UINT32_C(0x3) << 1)
19627 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
19628 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
19630 * This field is used for selecting tunnel VLAN PRI value
19631 * based on whether one or two VLAN Tags are present in
19632 * the tunnel headers of tunneled packets. This selection
19633 * does not apply to non-tunneled packets.
19635 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
19637 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
19640 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
19641 * present in the tunnel packet headers
19643 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
19644 (UINT32_C(0x0) << 3)
19646 * Select outer VLAN Tag PRI when 2 VLAN Tags are
19647 * present in the tunnel packet headers.
19648 * No VLAN PRI is selected for this configuration
19649 * if only one VLAN Tag is present in the tunnel
19652 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
19653 (UINT32_C(0x1) << 3)
19655 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
19656 * are present in the tunnel packet headers
19658 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
19659 (UINT32_C(0x2) << 3)
19661 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
19662 (UINT32_C(0x3) << 3)
19663 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
19664 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
19666 * This field is used to provide default CoS value that
19667 * has been configured on this port.
19669 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
19671 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
19674 uint16_t port_svif_info;
19676 * This field specifies the source virtual interface of the port being
19677 * queried. Drivers can use this to program port svif field in the
19680 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
19682 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
19683 /* This field specifies whether port_svif is valid or not */
19684 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
19686 uint8_t unused_2[5];
19688 * This field is used in Output records to indicate that the output
19689 * is completely written to RAM. This field should be read as '1'
19690 * to indicate that the output has been completely written.
19691 * When writing a command completion or response to an internal processor,
19692 * the order of writes has to be such that this field is written last.
19697 /**************************
19698 * hwrm_port_mac_ptp_qcfg *
19699 **************************/
19702 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
19703 struct hwrm_port_mac_ptp_qcfg_input {
19704 /* The HWRM command request type. */
19707 * The completion ring to send the completion event on. This should
19708 * be the NQ ID returned from the `nq_alloc` HWRM command.
19710 uint16_t cmpl_ring;
19712 * The sequence ID is used by the driver for tracking multiple
19713 * commands. This ID is treated as opaque data by the firmware and
19714 * the value is returned in the `hwrm_resp_hdr` upon completion.
19718 * The target ID of the command:
19719 * * 0x0-0xFFF8 - The function ID
19720 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19721 * * 0xFFFD - Reserved for user-space HWRM interface
19724 uint16_t target_id;
19726 * A physical address pointer pointing to a host buffer that the
19727 * command's response data will be written. This can be either a host
19728 * physical address (HPA) or a guest physical address (GPA) and must
19729 * point to a physically contiguous block of memory.
19731 uint64_t resp_addr;
19732 /* Port ID of port that is being queried. */
19734 uint8_t unused_0[6];
19737 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
19738 struct hwrm_port_mac_ptp_qcfg_output {
19739 /* The specific error status for the command. */
19740 uint16_t error_code;
19741 /* The HWRM command request type. */
19743 /* The sequence ID from the original command. */
19745 /* The length of the response data in number of bytes. */
19748 * In this field, a number of PTP related flags
19749 * are used to indicate configured PTP capabilities.
19753 * When this bit is set to '1', the PTP related registers are
19754 * directly accessible by the host.
19756 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
19759 * When this bit is set to '1', the device supports one-step
19762 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
19765 * When this bit is set to '1', the PTP information is accessible
19766 * via HWRM commands.
19768 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
19770 uint8_t unused_0[3];
19771 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
19772 uint32_t rx_ts_reg_off_lower;
19773 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
19774 uint32_t rx_ts_reg_off_upper;
19775 /* Offset of the PTP register for the sequence ID for RX. */
19776 uint32_t rx_ts_reg_off_seq_id;
19777 /* Offset of the first PTP source ID for RX. */
19778 uint32_t rx_ts_reg_off_src_id_0;
19779 /* Offset of the second PTP source ID for RX. */
19780 uint32_t rx_ts_reg_off_src_id_1;
19781 /* Offset of the third PTP source ID for RX. */
19782 uint32_t rx_ts_reg_off_src_id_2;
19783 /* Offset of the domain ID for RX. */
19784 uint32_t rx_ts_reg_off_domain_id;
19785 /* Offset of the PTP FIFO register for RX. */
19786 uint32_t rx_ts_reg_off_fifo;
19787 /* Offset of the PTP advance FIFO register for RX. */
19788 uint32_t rx_ts_reg_off_fifo_adv;
19789 /* PTP timestamp granularity for RX. */
19790 uint32_t rx_ts_reg_off_granularity;
19791 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
19792 uint32_t tx_ts_reg_off_lower;
19793 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
19794 uint32_t tx_ts_reg_off_upper;
19795 /* Offset of the PTP register for the sequence ID for TX. */
19796 uint32_t tx_ts_reg_off_seq_id;
19797 /* Offset of the PTP FIFO register for TX. */
19798 uint32_t tx_ts_reg_off_fifo;
19799 /* PTP timestamp granularity for TX. */
19800 uint32_t tx_ts_reg_off_granularity;
19801 uint8_t unused_1[7];
19803 * This field is used in Output records to indicate that the output
19804 * is completely written to RAM. This field should be read as '1'
19805 * to indicate that the output has been completely written.
19806 * When writing a command completion or response to an internal processor,
19807 * the order of writes has to be such that this field is written last.
19812 /* Port Tx Statistics Format */
19813 /* tx_port_stats (size:3264b/408B) */
19814 struct tx_port_stats {
19815 /* Total Number of 64 Bytes frames transmitted */
19816 uint64_t tx_64b_frames;
19817 /* Total Number of 65-127 Bytes frames transmitted */
19818 uint64_t tx_65b_127b_frames;
19819 /* Total Number of 128-255 Bytes frames transmitted */
19820 uint64_t tx_128b_255b_frames;
19821 /* Total Number of 256-511 Bytes frames transmitted */
19822 uint64_t tx_256b_511b_frames;
19823 /* Total Number of 512-1023 Bytes frames transmitted */
19824 uint64_t tx_512b_1023b_frames;
19825 /* Total Number of 1024-1518 Bytes frames transmitted */
19826 uint64_t tx_1024b_1518b_frames;
19828 * Total Number of each good VLAN (exludes FCS errors)
19829 * frame transmitted which is 1519 to 1522 bytes in length
19830 * inclusive (excluding framing bits but including FCS bytes).
19832 uint64_t tx_good_vlan_frames;
19833 /* Total Number of 1519-2047 Bytes frames transmitted */
19834 uint64_t tx_1519b_2047b_frames;
19835 /* Total Number of 2048-4095 Bytes frames transmitted */
19836 uint64_t tx_2048b_4095b_frames;
19837 /* Total Number of 4096-9216 Bytes frames transmitted */
19838 uint64_t tx_4096b_9216b_frames;
19839 /* Total Number of 9217-16383 Bytes frames transmitted */
19840 uint64_t tx_9217b_16383b_frames;
19841 /* Total Number of good frames transmitted */
19842 uint64_t tx_good_frames;
19843 /* Total Number of frames transmitted */
19844 uint64_t tx_total_frames;
19845 /* Total number of unicast frames transmitted */
19846 uint64_t tx_ucast_frames;
19847 /* Total number of multicast frames transmitted */
19848 uint64_t tx_mcast_frames;
19849 /* Total number of broadcast frames transmitted */
19850 uint64_t tx_bcast_frames;
19851 /* Total number of PAUSE control frames transmitted */
19852 uint64_t tx_pause_frames;
19854 * Total number of PFC/per-priority PAUSE
19855 * control frames transmitted
19857 uint64_t tx_pfc_frames;
19858 /* Total number of jabber frames transmitted */
19859 uint64_t tx_jabber_frames;
19860 /* Total number of frames transmitted with FCS error */
19861 uint64_t tx_fcs_err_frames;
19862 /* Total number of control frames transmitted */
19863 uint64_t tx_control_frames;
19864 /* Total number of over-sized frames transmitted */
19865 uint64_t tx_oversz_frames;
19866 /* Total number of frames with single deferral */
19867 uint64_t tx_single_dfrl_frames;
19868 /* Total number of frames with multiple deferrals */
19869 uint64_t tx_multi_dfrl_frames;
19870 /* Total number of frames with single collision */
19871 uint64_t tx_single_coll_frames;
19872 /* Total number of frames with multiple collisions */
19873 uint64_t tx_multi_coll_frames;
19874 /* Total number of frames with late collisions */
19875 uint64_t tx_late_coll_frames;
19876 /* Total number of frames with excessive collisions */
19877 uint64_t tx_excessive_coll_frames;
19878 /* Total number of fragmented frames transmitted */
19879 uint64_t tx_frag_frames;
19880 /* Total number of transmit errors */
19882 /* Total number of single VLAN tagged frames transmitted */
19883 uint64_t tx_tagged_frames;
19884 /* Total number of double VLAN tagged frames transmitted */
19885 uint64_t tx_dbl_tagged_frames;
19886 /* Total number of runt frames transmitted */
19887 uint64_t tx_runt_frames;
19888 /* Total number of TX FIFO under runs */
19889 uint64_t tx_fifo_underruns;
19891 * Total number of PFC frames with PFC enabled bit for
19892 * Pri 0 transmitted
19894 uint64_t tx_pfc_ena_frames_pri0;
19896 * Total number of PFC frames with PFC enabled bit for
19897 * Pri 1 transmitted
19899 uint64_t tx_pfc_ena_frames_pri1;
19901 * Total number of PFC frames with PFC enabled bit for
19902 * Pri 2 transmitted
19904 uint64_t tx_pfc_ena_frames_pri2;
19906 * Total number of PFC frames with PFC enabled bit for
19907 * Pri 3 transmitted
19909 uint64_t tx_pfc_ena_frames_pri3;
19911 * Total number of PFC frames with PFC enabled bit for
19912 * Pri 4 transmitted
19914 uint64_t tx_pfc_ena_frames_pri4;
19916 * Total number of PFC frames with PFC enabled bit for
19917 * Pri 5 transmitted
19919 uint64_t tx_pfc_ena_frames_pri5;
19921 * Total number of PFC frames with PFC enabled bit for
19922 * Pri 6 transmitted
19924 uint64_t tx_pfc_ena_frames_pri6;
19926 * Total number of PFC frames with PFC enabled bit for
19927 * Pri 7 transmitted
19929 uint64_t tx_pfc_ena_frames_pri7;
19930 /* Total number of EEE LPI Events on TX */
19931 uint64_t tx_eee_lpi_events;
19932 /* EEE LPI Duration Counter on TX */
19933 uint64_t tx_eee_lpi_duration;
19935 * Total number of Link Level Flow Control (LLFC) messages
19938 uint64_t tx_llfc_logical_msgs;
19939 /* Total number of HCFC messages transmitted */
19940 uint64_t tx_hcfc_msgs;
19941 /* Total number of TX collisions */
19942 uint64_t tx_total_collisions;
19943 /* Total number of transmitted bytes */
19945 /* Total number of end-to-end HOL frames */
19946 uint64_t tx_xthol_frames;
19947 /* Total Tx Drops per Port reported by STATS block */
19948 uint64_t tx_stat_discard;
19949 /* Total Tx Error Drops per Port reported by STATS block */
19950 uint64_t tx_stat_error;
19953 /* Port Rx Statistics Format */
19954 /* rx_port_stats (size:4224b/528B) */
19955 struct rx_port_stats {
19956 /* Total Number of 64 Bytes frames received */
19957 uint64_t rx_64b_frames;
19958 /* Total Number of 65-127 Bytes frames received */
19959 uint64_t rx_65b_127b_frames;
19960 /* Total Number of 128-255 Bytes frames received */
19961 uint64_t rx_128b_255b_frames;
19962 /* Total Number of 256-511 Bytes frames received */
19963 uint64_t rx_256b_511b_frames;
19964 /* Total Number of 512-1023 Bytes frames received */
19965 uint64_t rx_512b_1023b_frames;
19966 /* Total Number of 1024-1518 Bytes frames received */
19967 uint64_t rx_1024b_1518b_frames;
19969 * Total Number of each good VLAN (exludes FCS errors)
19970 * frame received which is 1519 to 1522 bytes in length
19971 * inclusive (excluding framing bits but including FCS bytes).
19973 uint64_t rx_good_vlan_frames;
19974 /* Total Number of 1519-2047 Bytes frames received */
19975 uint64_t rx_1519b_2047b_frames;
19976 /* Total Number of 2048-4095 Bytes frames received */
19977 uint64_t rx_2048b_4095b_frames;
19978 /* Total Number of 4096-9216 Bytes frames received */
19979 uint64_t rx_4096b_9216b_frames;
19980 /* Total Number of 9217-16383 Bytes frames received */
19981 uint64_t rx_9217b_16383b_frames;
19982 /* Total number of frames received */
19983 uint64_t rx_total_frames;
19984 /* Total number of unicast frames received */
19985 uint64_t rx_ucast_frames;
19986 /* Total number of multicast frames received */
19987 uint64_t rx_mcast_frames;
19988 /* Total number of broadcast frames received */
19989 uint64_t rx_bcast_frames;
19990 /* Total number of received frames with FCS error */
19991 uint64_t rx_fcs_err_frames;
19992 /* Total number of control frames received */
19993 uint64_t rx_ctrl_frames;
19994 /* Total number of PAUSE frames received */
19995 uint64_t rx_pause_frames;
19996 /* Total number of PFC frames received */
19997 uint64_t rx_pfc_frames;
19999 * Total number of frames received with an unsupported
20002 uint64_t rx_unsupported_opcode_frames;
20004 * Total number of frames received with an unsupported
20005 * DA for pause and PFC
20007 uint64_t rx_unsupported_da_pausepfc_frames;
20008 /* Total number of frames received with an unsupported SA */
20009 uint64_t rx_wrong_sa_frames;
20010 /* Total number of received packets with alignment error */
20011 uint64_t rx_align_err_frames;
20012 /* Total number of received frames with out-of-range length */
20013 uint64_t rx_oor_len_frames;
20014 /* Total number of received frames with error termination */
20015 uint64_t rx_code_err_frames;
20017 * Total number of received frames with a false carrier is
20018 * detected during idle, as defined by RX_ER samples active
20019 * and RXD is 0xE. The event is reported along with the
20020 * statistics generated on the next received frame. Only
20021 * one false carrier condition can be detected and logged
20024 * Carrier event, valid for 10M/100M speed modes only.
20026 uint64_t rx_false_carrier_frames;
20027 /* Total number of over-sized frames received */
20028 uint64_t rx_ovrsz_frames;
20029 /* Total number of jabber packets received */
20030 uint64_t rx_jbr_frames;
20031 /* Total number of received frames with MTU error */
20032 uint64_t rx_mtu_err_frames;
20033 /* Total number of received frames with CRC match */
20034 uint64_t rx_match_crc_frames;
20035 /* Total number of frames received promiscuously */
20036 uint64_t rx_promiscuous_frames;
20038 * Total number of received frames with one or two VLAN
20041 uint64_t rx_tagged_frames;
20042 /* Total number of received frames with two VLAN tags */
20043 uint64_t rx_double_tagged_frames;
20044 /* Total number of truncated frames received */
20045 uint64_t rx_trunc_frames;
20046 /* Total number of good frames (without errors) received */
20047 uint64_t rx_good_frames;
20049 * Total number of received PFC frames with transition from
20050 * XON to XOFF on Pri 0
20052 uint64_t rx_pfc_xon2xoff_frames_pri0;
20054 * Total number of received PFC frames with transition from
20055 * XON to XOFF on Pri 1
20057 uint64_t rx_pfc_xon2xoff_frames_pri1;
20059 * Total number of received PFC frames with transition from
20060 * XON to XOFF on Pri 2
20062 uint64_t rx_pfc_xon2xoff_frames_pri2;
20064 * Total number of received PFC frames with transition from
20065 * XON to XOFF on Pri 3
20067 uint64_t rx_pfc_xon2xoff_frames_pri3;
20069 * Total number of received PFC frames with transition from
20070 * XON to XOFF on Pri 4
20072 uint64_t rx_pfc_xon2xoff_frames_pri4;
20074 * Total number of received PFC frames with transition from
20075 * XON to XOFF on Pri 5
20077 uint64_t rx_pfc_xon2xoff_frames_pri5;
20079 * Total number of received PFC frames with transition from
20080 * XON to XOFF on Pri 6
20082 uint64_t rx_pfc_xon2xoff_frames_pri6;
20084 * Total number of received PFC frames with transition from
20085 * XON to XOFF on Pri 7
20087 uint64_t rx_pfc_xon2xoff_frames_pri7;
20089 * Total number of received PFC frames with PFC enabled
20092 uint64_t rx_pfc_ena_frames_pri0;
20094 * Total number of received PFC frames with PFC enabled
20097 uint64_t rx_pfc_ena_frames_pri1;
20099 * Total number of received PFC frames with PFC enabled
20102 uint64_t rx_pfc_ena_frames_pri2;
20104 * Total number of received PFC frames with PFC enabled
20107 uint64_t rx_pfc_ena_frames_pri3;
20109 * Total number of received PFC frames with PFC enabled
20112 uint64_t rx_pfc_ena_frames_pri4;
20114 * Total number of received PFC frames with PFC enabled
20117 uint64_t rx_pfc_ena_frames_pri5;
20119 * Total number of received PFC frames with PFC enabled
20122 uint64_t rx_pfc_ena_frames_pri6;
20124 * Total number of received PFC frames with PFC enabled
20127 uint64_t rx_pfc_ena_frames_pri7;
20128 /* Total Number of frames received with SCH CRC error */
20129 uint64_t rx_sch_crc_err_frames;
20130 /* Total Number of under-sized frames received */
20131 uint64_t rx_undrsz_frames;
20132 /* Total Number of fragmented frames received */
20133 uint64_t rx_frag_frames;
20134 /* Total number of RX EEE LPI Events */
20135 uint64_t rx_eee_lpi_events;
20136 /* EEE LPI Duration Counter on RX */
20137 uint64_t rx_eee_lpi_duration;
20139 * Total number of physical type Link Level Flow Control
20140 * (LLFC) messages received
20142 uint64_t rx_llfc_physical_msgs;
20144 * Total number of logical type Link Level Flow Control
20145 * (LLFC) messages received
20147 uint64_t rx_llfc_logical_msgs;
20149 * Total number of logical type Link Level Flow Control
20150 * (LLFC) messages received with CRC error
20152 uint64_t rx_llfc_msgs_with_crc_err;
20153 /* Total number of HCFC messages received */
20154 uint64_t rx_hcfc_msgs;
20155 /* Total number of HCFC messages received with CRC error */
20156 uint64_t rx_hcfc_msgs_with_crc_err;
20157 /* Total number of received bytes */
20159 /* Total number of bytes received in runt frames */
20160 uint64_t rx_runt_bytes;
20161 /* Total number of runt frames received */
20162 uint64_t rx_runt_frames;
20163 /* Total Rx Discards per Port reported by STATS block */
20164 uint64_t rx_stat_discard;
20165 uint64_t rx_stat_err;
20168 /********************
20169 * hwrm_port_qstats *
20170 ********************/
20173 /* hwrm_port_qstats_input (size:320b/40B) */
20174 struct hwrm_port_qstats_input {
20175 /* The HWRM command request type. */
20178 * The completion ring to send the completion event on. This should
20179 * be the NQ ID returned from the `nq_alloc` HWRM command.
20181 uint16_t cmpl_ring;
20183 * The sequence ID is used by the driver for tracking multiple
20184 * commands. This ID is treated as opaque data by the firmware and
20185 * the value is returned in the `hwrm_resp_hdr` upon completion.
20189 * The target ID of the command:
20190 * * 0x0-0xFFF8 - The function ID
20191 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20192 * * 0xFFFD - Reserved for user-space HWRM interface
20195 uint16_t target_id;
20197 * A physical address pointer pointing to a host buffer that the
20198 * command's response data will be written. This can be either a host
20199 * physical address (HPA) or a guest physical address (GPA) and must
20200 * point to a physically contiguous block of memory.
20202 uint64_t resp_addr;
20203 /* Port ID of port that is being queried. */
20206 /* This value is not used to avoid backward compatibility issues. */
20207 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
20209 * This bit is set to 1 when request is for a counter mask,
20210 * representing the width of each of the stats counters, rather
20211 * than counters themselves.
20213 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
20214 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
20215 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
20216 uint8_t unused_0[5];
20218 * This is the host address where
20219 * Tx port statistics will be stored
20221 uint64_t tx_stat_host_addr;
20223 * This is the host address where
20224 * Rx port statistics will be stored
20226 uint64_t rx_stat_host_addr;
20229 /* hwrm_port_qstats_output (size:128b/16B) */
20230 struct hwrm_port_qstats_output {
20231 /* The specific error status for the command. */
20232 uint16_t error_code;
20233 /* The HWRM command request type. */
20235 /* The sequence ID from the original command. */
20237 /* The length of the response data in number of bytes. */
20239 /* The size of TX port statistics block in bytes. */
20240 uint16_t tx_stat_size;
20241 /* The size of RX port statistics block in bytes. */
20242 uint16_t rx_stat_size;
20243 uint8_t unused_0[3];
20245 * This field is used in Output records to indicate that the output
20246 * is completely written to RAM. This field should be read as '1'
20247 * to indicate that the output has been completely written.
20248 * When writing a command completion or response to an internal processor,
20249 * the order of writes has to be such that this field is written last.
20254 /* Port Tx Statistics extended Format */
20255 /* tx_port_stats_ext (size:2048b/256B) */
20256 struct tx_port_stats_ext {
20257 /* Total number of tx bytes count on cos queue 0 */
20258 uint64_t tx_bytes_cos0;
20259 /* Total number of tx bytes count on cos queue 1 */
20260 uint64_t tx_bytes_cos1;
20261 /* Total number of tx bytes count on cos queue 2 */
20262 uint64_t tx_bytes_cos2;
20263 /* Total number of tx bytes count on cos queue 3 */
20264 uint64_t tx_bytes_cos3;
20265 /* Total number of tx bytes count on cos queue 4 */
20266 uint64_t tx_bytes_cos4;
20267 /* Total number of tx bytes count on cos queue 5 */
20268 uint64_t tx_bytes_cos5;
20269 /* Total number of tx bytes count on cos queue 6 */
20270 uint64_t tx_bytes_cos6;
20271 /* Total number of tx bytes count on cos queue 7 */
20272 uint64_t tx_bytes_cos7;
20273 /* Total number of tx packets count on cos queue 0 */
20274 uint64_t tx_packets_cos0;
20275 /* Total number of tx packets count on cos queue 1 */
20276 uint64_t tx_packets_cos1;
20277 /* Total number of tx packets count on cos queue 2 */
20278 uint64_t tx_packets_cos2;
20279 /* Total number of tx packets count on cos queue 3 */
20280 uint64_t tx_packets_cos3;
20281 /* Total number of tx packets count on cos queue 4 */
20282 uint64_t tx_packets_cos4;
20283 /* Total number of tx packets count on cos queue 5 */
20284 uint64_t tx_packets_cos5;
20285 /* Total number of tx packets count on cos queue 6 */
20286 uint64_t tx_packets_cos6;
20287 /* Total number of tx packets count on cos queue 7 */
20288 uint64_t tx_packets_cos7;
20289 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
20290 uint64_t pfc_pri0_tx_duration_us;
20291 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
20292 uint64_t pfc_pri0_tx_transitions;
20293 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
20294 uint64_t pfc_pri1_tx_duration_us;
20295 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
20296 uint64_t pfc_pri1_tx_transitions;
20297 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
20298 uint64_t pfc_pri2_tx_duration_us;
20299 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
20300 uint64_t pfc_pri2_tx_transitions;
20301 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
20302 uint64_t pfc_pri3_tx_duration_us;
20303 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
20304 uint64_t pfc_pri3_tx_transitions;
20305 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
20306 uint64_t pfc_pri4_tx_duration_us;
20307 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
20308 uint64_t pfc_pri4_tx_transitions;
20309 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
20310 uint64_t pfc_pri5_tx_duration_us;
20311 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
20312 uint64_t pfc_pri5_tx_transitions;
20313 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
20314 uint64_t pfc_pri6_tx_duration_us;
20315 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
20316 uint64_t pfc_pri6_tx_transitions;
20317 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
20318 uint64_t pfc_pri7_tx_duration_us;
20319 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
20320 uint64_t pfc_pri7_tx_transitions;
20323 /* Port Rx Statistics extended Format */
20324 /* rx_port_stats_ext (size:3648b/456B) */
20325 struct rx_port_stats_ext {
20326 /* Number of times link state changed to down */
20327 uint64_t link_down_events;
20328 /* Number of times the idle rings with pause bit are found */
20329 uint64_t continuous_pause_events;
20330 /* Number of times the active rings pause bit resumed back */
20331 uint64_t resume_pause_events;
20332 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
20333 uint64_t continuous_roce_pause_events;
20334 /* Number of times, the ROCE cos queue PFC is enabled back */
20335 uint64_t resume_roce_pause_events;
20336 /* Total number of rx bytes count on cos queue 0 */
20337 uint64_t rx_bytes_cos0;
20338 /* Total number of rx bytes count on cos queue 1 */
20339 uint64_t rx_bytes_cos1;
20340 /* Total number of rx bytes count on cos queue 2 */
20341 uint64_t rx_bytes_cos2;
20342 /* Total number of rx bytes count on cos queue 3 */
20343 uint64_t rx_bytes_cos3;
20344 /* Total number of rx bytes count on cos queue 4 */
20345 uint64_t rx_bytes_cos4;
20346 /* Total number of rx bytes count on cos queue 5 */
20347 uint64_t rx_bytes_cos5;
20348 /* Total number of rx bytes count on cos queue 6 */
20349 uint64_t rx_bytes_cos6;
20350 /* Total number of rx bytes count on cos queue 7 */
20351 uint64_t rx_bytes_cos7;
20352 /* Total number of rx packets count on cos queue 0 */
20353 uint64_t rx_packets_cos0;
20354 /* Total number of rx packets count on cos queue 1 */
20355 uint64_t rx_packets_cos1;
20356 /* Total number of rx packets count on cos queue 2 */
20357 uint64_t rx_packets_cos2;
20358 /* Total number of rx packets count on cos queue 3 */
20359 uint64_t rx_packets_cos3;
20360 /* Total number of rx packets count on cos queue 4 */
20361 uint64_t rx_packets_cos4;
20362 /* Total number of rx packets count on cos queue 5 */
20363 uint64_t rx_packets_cos5;
20364 /* Total number of rx packets count on cos queue 6 */
20365 uint64_t rx_packets_cos6;
20366 /* Total number of rx packets count on cos queue 7 */
20367 uint64_t rx_packets_cos7;
20368 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
20369 uint64_t pfc_pri0_rx_duration_us;
20370 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
20371 uint64_t pfc_pri0_rx_transitions;
20372 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
20373 uint64_t pfc_pri1_rx_duration_us;
20374 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
20375 uint64_t pfc_pri1_rx_transitions;
20376 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
20377 uint64_t pfc_pri2_rx_duration_us;
20378 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
20379 uint64_t pfc_pri2_rx_transitions;
20380 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
20381 uint64_t pfc_pri3_rx_duration_us;
20382 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
20383 uint64_t pfc_pri3_rx_transitions;
20384 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
20385 uint64_t pfc_pri4_rx_duration_us;
20386 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
20387 uint64_t pfc_pri4_rx_transitions;
20388 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
20389 uint64_t pfc_pri5_rx_duration_us;
20390 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
20391 uint64_t pfc_pri5_rx_transitions;
20392 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
20393 uint64_t pfc_pri6_rx_duration_us;
20394 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
20395 uint64_t pfc_pri6_rx_transitions;
20396 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
20397 uint64_t pfc_pri7_rx_duration_us;
20398 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
20399 uint64_t pfc_pri7_rx_transitions;
20400 /* Total number of received bits */
20402 /* The number of events where the port receive buffer was over 85% full */
20403 uint64_t rx_buffer_passed_threshold;
20405 * The number of symbol errors that wasn't corrected by FEC correction
20408 uint64_t rx_pcs_symbol_err;
20409 /* The number of corrected bits on the port according to active FEC */
20410 uint64_t rx_corrected_bits;
20411 /* Total number of rx discard bytes count on cos queue 0 */
20412 uint64_t rx_discard_bytes_cos0;
20413 /* Total number of rx discard bytes count on cos queue 1 */
20414 uint64_t rx_discard_bytes_cos1;
20415 /* Total number of rx discard bytes count on cos queue 2 */
20416 uint64_t rx_discard_bytes_cos2;
20417 /* Total number of rx discard bytes count on cos queue 3 */
20418 uint64_t rx_discard_bytes_cos3;
20419 /* Total number of rx discard bytes count on cos queue 4 */
20420 uint64_t rx_discard_bytes_cos4;
20421 /* Total number of rx discard bytes count on cos queue 5 */
20422 uint64_t rx_discard_bytes_cos5;
20423 /* Total number of rx discard bytes count on cos queue 6 */
20424 uint64_t rx_discard_bytes_cos6;
20425 /* Total number of rx discard bytes count on cos queue 7 */
20426 uint64_t rx_discard_bytes_cos7;
20427 /* Total number of rx discard packets count on cos queue 0 */
20428 uint64_t rx_discard_packets_cos0;
20429 /* Total number of rx discard packets count on cos queue 1 */
20430 uint64_t rx_discard_packets_cos1;
20431 /* Total number of rx discard packets count on cos queue 2 */
20432 uint64_t rx_discard_packets_cos2;
20433 /* Total number of rx discard packets count on cos queue 3 */
20434 uint64_t rx_discard_packets_cos3;
20435 /* Total number of rx discard packets count on cos queue 4 */
20436 uint64_t rx_discard_packets_cos4;
20437 /* Total number of rx discard packets count on cos queue 5 */
20438 uint64_t rx_discard_packets_cos5;
20439 /* Total number of rx discard packets count on cos queue 6 */
20440 uint64_t rx_discard_packets_cos6;
20441 /* Total number of rx discard packets count on cos queue 7 */
20442 uint64_t rx_discard_packets_cos7;
20446 * Port Rx Statistics extended PFC WatchDog Format.
20447 * StormDetect and StormRevert event determination is based
20448 * on an integration period and a percentage threshold.
20449 * StormDetect event - when percentage of XOFF frames received
20450 * within an integration period exceeds the configured threshold.
20451 * StormRevert event - when percentage of XON frames received
20452 * within an integration period exceeds the configured threshold.
20453 * Actual number of XOFF/XON frames for the events to be triggered
20454 * depends on both configured integration period and sampling rate.
20455 * The statistics in this structure represent counts of specified
20456 * events from the moment the feature (PFC WatchDog) is enabled via
20457 * hwrm_queue_pfc_enable_cfg call.
20459 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
20460 struct rx_port_stats_ext_pfc_wd {
20462 * Total number of PFC WatchDog StormDetect events detected
20465 uint64_t rx_pfc_watchdog_storms_detected_pri0;
20467 * Total number of PFC WatchDog StormDetect events detected
20470 uint64_t rx_pfc_watchdog_storms_detected_pri1;
20472 * Total number of PFC WatchDog StormDetect events detected
20475 uint64_t rx_pfc_watchdog_storms_detected_pri2;
20477 * Total number of PFC WatchDog StormDetect events detected
20480 uint64_t rx_pfc_watchdog_storms_detected_pri3;
20482 * Total number of PFC WatchDog StormDetect events detected
20485 uint64_t rx_pfc_watchdog_storms_detected_pri4;
20487 * Total number of PFC WatchDog StormDetect events detected
20490 uint64_t rx_pfc_watchdog_storms_detected_pri5;
20492 * Total number of PFC WatchDog StormDetect events detected
20495 uint64_t rx_pfc_watchdog_storms_detected_pri6;
20497 * Total number of PFC WatchDog StormDetect events detected
20500 uint64_t rx_pfc_watchdog_storms_detected_pri7;
20502 * Total number of PFC WatchDog StormRevert events detected
20505 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
20507 * Total number of PFC WatchDog StormRevert events detected
20510 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
20512 * Total number of PFC WatchDog StormRevert events detected
20515 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
20517 * Total number of PFC WatchDog StormRevert events detected
20520 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
20522 * Total number of PFC WatchDog StormRevert events detected
20525 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
20527 * Total number of PFC WatchDog StormRevert events detected
20530 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
20532 * Total number of PFC WatchDog StormRevert events detected
20535 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
20537 * Total number of PFC WatchDog StormRevert events detected
20540 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
20542 * Total number of packets received during PFC watchdog storm
20545 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
20547 * Total number of packets received during PFC watchdog storm
20550 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
20552 * Total number of packets received during PFC watchdog storm
20555 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
20557 * Total number of packets received during PFC watchdog storm
20560 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
20562 * Total number of packets received during PFC watchdog storm
20565 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
20567 * Total number of packets received during PFC watchdog storm
20570 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
20572 * Total number of packets received during PFC watchdog storm
20575 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
20577 * Total number of packets received during PFC watchdog storm
20580 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
20582 * Total number of bytes received during PFC watchdog storm
20585 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
20587 * Total number of bytes received during PFC watchdog storm
20590 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
20592 * Total number of bytes received during PFC watchdog storm
20595 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
20597 * Total number of bytes received during PFC watchdog storm
20600 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
20602 * Total number of bytes received during PFC watchdog storm
20605 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
20607 * Total number of bytes received during PFC watchdog storm
20610 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
20612 * Total number of bytes received during PFC watchdog storm
20615 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
20617 * Total number of bytes received during PFC watchdog storm
20620 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
20622 * Total number of packets dropped on rx during PFC watchdog storm
20625 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
20627 * Total number of packets dropped on rx during PFC watchdog storm
20630 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
20632 * Total number of packets dropped on rx during PFC watchdog storm
20635 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
20637 * Total number of packets dropped on rx during PFC watchdog storm
20640 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
20642 * Total number of packets dropped on rx during PFC watchdog storm
20645 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
20647 * Total number of packets dropped on rx during PFC watchdog storm
20650 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
20652 * Total number of packets dropped on rx during PFC watchdog storm
20655 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
20657 * Total number of packets dropped on rx during PFC watchdog storm
20660 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
20662 * Total number of bytes dropped on rx during PFC watchdog storm
20665 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
20667 * Total number of bytes dropped on rx during PFC watchdog storm
20670 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
20672 * Total number of bytes dropped on rx during PFC watchdog storm
20675 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
20677 * Total number of bytes dropped on rx during PFC watchdog storm
20680 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
20682 * Total number of bytes dropped on rx during PFC watchdog storm
20685 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
20687 * Total number of bytes dropped on rx during PFC watchdog storm
20690 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
20692 * Total number of bytes dropped on rx during PFC watchdog storm
20695 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
20697 * Total number of bytes dropped on rx during PFC watchdog storm
20700 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
20702 * Number of packets received during last PFC watchdog storm
20705 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
20707 * Number of packets received during last PFC watchdog storm
20710 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
20712 * Number of packets received during last PFC watchdog storm
20715 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
20717 * Number of packets received during last PFC watchdog storm
20720 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
20722 * Number of packets received during last PFC watchdog storm
20725 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
20727 * Number of packets received during last PFC watchdog storm
20730 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
20732 * Number of packets received during last PFC watchdog storm
20735 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
20737 * Number of packets received during last PFC watchdog storm
20740 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
20742 * Number of bytes received during last PFC watchdog storm
20745 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
20747 * Number of bytes received during last PFC watchdog storm
20750 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
20752 * Number of bytes received during last PFC watchdog storm
20755 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
20757 * Number of bytes received during last PFC watchdog storm
20760 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
20762 * Number of bytes received during last PFC watchdog storm
20765 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
20767 * Number of bytes received during last PFC watchdog storm
20770 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
20772 * Number of bytes received during last PFC watchdog storm
20775 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
20777 * Number of bytes received during last PFC watchdog storm
20780 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
20782 * Number of packets dropped on rx during last PFC watchdog storm
20785 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
20787 * Number of packets dropped on rx during last PFC watchdog storm
20790 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
20792 * Number of packets dropped on rx during last PFC watchdog storm
20795 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
20797 * Number of packets dropped on rx during last PFC watchdog storm
20800 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
20802 * Number of packets dropped on rx during last PFC watchdog storm
20805 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
20807 * Number of packets dropped on rx during last PFC watchdog storm
20810 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
20812 * Number of packets dropped on rx during last PFC watchdog storm
20815 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
20817 * Number of packets dropped on rx during last PFC watchdog storm
20820 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
20822 * Total number of bytes dropped on rx during PFC watchdog storm
20825 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
20827 * Number of bytes dropped on rx during last PFC watchdog storm
20830 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
20832 * Number of bytes dropped on rx during last PFC watchdog storm
20835 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
20837 * Number of bytes dropped on rx during last PFC watchdog storm
20840 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
20842 * Number of bytes dropped on rx during last PFC watchdog storm
20845 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
20847 * Number of bytes dropped on rx during last PFC watchdog storm
20850 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
20852 * Number of bytes dropped on rx during last PFC watchdog storm
20855 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
20857 * Number of bytes dropped on rx during last PFC watchdog storm
20860 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
20863 /************************
20864 * hwrm_port_qstats_ext *
20865 ************************/
20868 /* hwrm_port_qstats_ext_input (size:320b/40B) */
20869 struct hwrm_port_qstats_ext_input {
20870 /* The HWRM command request type. */
20873 * The completion ring to send the completion event on. This should
20874 * be the NQ ID returned from the `nq_alloc` HWRM command.
20876 uint16_t cmpl_ring;
20878 * The sequence ID is used by the driver for tracking multiple
20879 * commands. This ID is treated as opaque data by the firmware and
20880 * the value is returned in the `hwrm_resp_hdr` upon completion.
20884 * The target ID of the command:
20885 * * 0x0-0xFFF8 - The function ID
20886 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20887 * * 0xFFFD - Reserved for user-space HWRM interface
20890 uint16_t target_id;
20892 * A physical address pointer pointing to a host buffer that the
20893 * command's response data will be written. This can be either a host
20894 * physical address (HPA) or a guest physical address (GPA) and must
20895 * point to a physically contiguous block of memory.
20897 uint64_t resp_addr;
20898 /* Port ID of port that is being queried. */
20901 * The size of TX port extended
20902 * statistics block in bytes.
20904 uint16_t tx_stat_size;
20906 * The size of RX port extended
20907 * statistics block in bytes
20909 uint16_t rx_stat_size;
20911 /* This value is not used to avoid backward compatibility issues. */
20912 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
20914 * This bit is set to 1 when request is for the counter mask,
20915 * representing width of each of the stats counters, rather than
20916 * counters themselves.
20918 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
20919 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
20920 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
20923 * This is the host address where
20924 * Tx port statistics will be stored
20926 uint64_t tx_stat_host_addr;
20928 * This is the host address where
20929 * Rx port statistics will be stored
20931 uint64_t rx_stat_host_addr;
20934 /* hwrm_port_qstats_ext_output (size:128b/16B) */
20935 struct hwrm_port_qstats_ext_output {
20936 /* The specific error status for the command. */
20937 uint16_t error_code;
20938 /* The HWRM command request type. */
20940 /* The sequence ID from the original command. */
20942 /* The length of the response data in number of bytes. */
20944 /* The size of TX port statistics block in bytes. */
20945 uint16_t tx_stat_size;
20946 /* The size of RX port statistics block in bytes. */
20947 uint16_t rx_stat_size;
20948 /* Total number of active cos queues available. */
20949 uint16_t total_active_cos_queues;
20952 * If set to 1, then this field indicates that clear
20953 * roce specific counters is supported.
20955 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
20958 * This field is used in Output records to indicate that the output
20959 * is completely written to RAM. This field should be read as '1'
20960 * to indicate that the output has been completely written.
20961 * When writing a command completion or response to an internal processor,
20962 * the order of writes has to be such that this field is written last.
20967 /*******************************
20968 * hwrm_port_qstats_ext_pfc_wd *
20969 *******************************/
20972 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
20973 struct hwrm_port_qstats_ext_pfc_wd_input {
20974 /* The HWRM command request type. */
20977 * The completion ring to send the completion event on. This should
20978 * be the NQ ID returned from the `nq_alloc` HWRM command.
20980 uint16_t cmpl_ring;
20982 * The sequence ID is used by the driver for tracking multiple
20983 * commands. This ID is treated as opaque data by the firmware and
20984 * the value is returned in the `hwrm_resp_hdr` upon completion.
20988 * The target ID of the command:
20989 * * 0x0-0xFFF8 - The function ID
20990 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20991 * * 0xFFFD - Reserved for user-space HWRM interface
20994 uint16_t target_id;
20996 * A physical address pointer pointing to a host buffer that the
20997 * command's response data will be written. This can be either a host
20998 * physical address (HPA) or a guest physical address (GPA) and must
20999 * point to a physically contiguous block of memory.
21001 uint64_t resp_addr;
21002 /* Port ID of port that is being queried. */
21005 * The size of rx_port_stats_ext_pfc_wd
21008 uint16_t pfc_wd_stat_size;
21009 uint8_t unused_0[4];
21011 * This is the host address where
21012 * rx_port_stats_ext_pfc_wd will be stored
21014 uint64_t pfc_wd_stat_host_addr;
21017 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
21018 struct hwrm_port_qstats_ext_pfc_wd_output {
21019 /* The specific error status for the command. */
21020 uint16_t error_code;
21021 /* The HWRM command request type. */
21023 /* The sequence ID from the original command. */
21025 /* The length of the response data in number of bytes. */
21028 * The size of rx_port_stats_ext_pfc_wd
21029 * statistics block in bytes.
21031 uint16_t pfc_wd_stat_size;
21034 * This field is used in Output records to indicate that the output
21035 * is completely written to RAM. This field should be read as '1'
21036 * to indicate that the output has been completely written.
21037 * When writing a command completion or response to an internal processor,
21038 * the order of writes has to be such that this field is written last.
21041 uint8_t unused_0[4];
21044 /*************************
21045 * hwrm_port_lpbk_qstats *
21046 *************************/
21049 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
21050 struct hwrm_port_lpbk_qstats_input {
21051 /* The HWRM command request type. */
21054 * The completion ring to send the completion event on. This should
21055 * be the NQ ID returned from the `nq_alloc` HWRM command.
21057 uint16_t cmpl_ring;
21059 * The sequence ID is used by the driver for tracking multiple
21060 * commands. This ID is treated as opaque data by the firmware and
21061 * the value is returned in the `hwrm_resp_hdr` upon completion.
21065 * The target ID of the command:
21066 * * 0x0-0xFFF8 - The function ID
21067 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21068 * * 0xFFFD - Reserved for user-space HWRM interface
21071 uint16_t target_id;
21073 * A physical address pointer pointing to a host buffer that the
21074 * command's response data will be written. This can be either a host
21075 * physical address (HPA) or a guest physical address (GPA) and must
21076 * point to a physically contiguous block of memory.
21078 uint64_t resp_addr;
21081 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
21082 struct hwrm_port_lpbk_qstats_output {
21083 /* The specific error status for the command. */
21084 uint16_t error_code;
21085 /* The HWRM command request type. */
21087 /* The sequence ID from the original command. */
21089 /* The length of the response data in number of bytes. */
21091 /* Number of transmitted unicast frames */
21092 uint64_t lpbk_ucast_frames;
21093 /* Number of transmitted multicast frames */
21094 uint64_t lpbk_mcast_frames;
21095 /* Number of transmitted broadcast frames */
21096 uint64_t lpbk_bcast_frames;
21097 /* Number of transmitted bytes for unicast traffic */
21098 uint64_t lpbk_ucast_bytes;
21099 /* Number of transmitted bytes for multicast traffic */
21100 uint64_t lpbk_mcast_bytes;
21101 /* Number of transmitted bytes for broadcast traffic */
21102 uint64_t lpbk_bcast_bytes;
21103 /* Total Tx Drops for loopback traffic reported by STATS block */
21104 uint64_t tx_stat_discard;
21105 /* Total Tx Error Drops for loopback traffic reported by STATS block */
21106 uint64_t tx_stat_error;
21107 /* Total Rx Drops for loopback traffic reported by STATS block */
21108 uint64_t rx_stat_discard;
21109 /* Total Rx Error Drops for loopback traffic reported by STATS block */
21110 uint64_t rx_stat_error;
21111 uint8_t unused_0[7];
21113 * This field is used in Output records to indicate that the output
21114 * is completely written to RAM. This field should be read as '1'
21115 * to indicate that the output has been completely written.
21116 * When writing a command completion or response to an internal processor,
21117 * the order of writes has to be such that this field is written last.
21122 /************************
21123 * hwrm_port_ecn_qstats *
21124 ************************/
21127 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
21128 struct hwrm_port_ecn_qstats_input {
21129 /* The HWRM command request type. */
21132 * The completion ring to send the completion event on. This should
21133 * be the NQ ID returned from the `nq_alloc` HWRM command.
21135 uint16_t cmpl_ring;
21137 * The sequence ID is used by the driver for tracking multiple
21138 * commands. This ID is treated as opaque data by the firmware and
21139 * the value is returned in the `hwrm_resp_hdr` upon completion.
21143 * The target ID of the command:
21144 * * 0x0-0xFFF8 - The function ID
21145 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21146 * * 0xFFFD - Reserved for user-space HWRM interface
21149 uint16_t target_id;
21151 * A physical address pointer pointing to a host buffer that the
21152 * command's response data will be written. This can be either a host
21153 * physical address (HPA) or a guest physical address (GPA) and must
21154 * point to a physically contiguous block of memory.
21156 uint64_t resp_addr;
21158 * Port ID of port that is being queried. Unused if NIC is in
21163 * Size of the DMA buffer the caller has allocated for the firmware to
21166 uint16_t ecn_stat_buf_size;
21168 /* This value is not used to avoid backward compatibility issues. */
21169 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
21171 * This bit is set to 1 when request is for a counter mask,
21172 * representing the width of each of the stats counters, rather
21173 * than counters themselves.
21175 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
21176 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
21177 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
21178 uint8_t unused_0[3];
21180 * This is the host address where
21181 * ECN port statistics will be stored
21183 uint64_t ecn_stat_host_addr;
21186 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
21187 struct hwrm_port_ecn_qstats_output {
21188 /* The specific error status for the command. */
21189 uint16_t error_code;
21190 /* The HWRM command request type. */
21192 /* The sequence ID from the original command. */
21194 /* The length of the response data in number of bytes. */
21196 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
21197 uint16_t ecn_stat_buf_size;
21199 * Bitmask that indicates which CoS queues have ECN marking enabled.
21200 * Bit i corresponds to CoS queue i.
21203 uint8_t unused_0[4];
21205 * This field is used in Output records to indicate that the output
21206 * is completely written to RAM. This field should be read as '1'
21207 * to indicate that the output has been completely written.
21208 * When writing a command completion or response to an internal processor,
21209 * the order of writes has to be such that this field is written last.
21214 /* ECN mark statistics format */
21215 /* port_stats_ecn (size:512b/64B) */
21216 struct port_stats_ecn {
21218 * Number of packets marked in CoS queue 0.
21219 * Or, if the driver requested counter masks, a mask to indicate the size
21222 uint64_t mark_cnt_cos0;
21224 * Number of packets marked in CoS queue 1.
21225 * Or, if the driver requested counter masks, a mask to indicate the size
21228 uint64_t mark_cnt_cos1;
21230 * Number of packets marked in CoS queue 2.
21231 * Or, if the driver requested counter masks, a mask to indicate the size
21234 uint64_t mark_cnt_cos2;
21236 * Number of packets marked in CoS queue 3.
21237 * Or, if the driver requested counter masks, a mask to indicate the size
21240 uint64_t mark_cnt_cos3;
21242 * Number of packets marked in CoS queue 4.
21243 * Or, if the driver requested counter masks, a mask to indicate the size
21246 uint64_t mark_cnt_cos4;
21248 * Number of packets marked in CoS queue 5.
21249 * Or, if the driver requested counter masks, a mask to indicate the size
21252 uint64_t mark_cnt_cos5;
21254 * Number of packets marked in CoS queue 6.
21255 * Or, if the driver requested counter masks, a mask to indicate the size
21258 uint64_t mark_cnt_cos6;
21260 * Number of packets marked in CoS queue 7.
21261 * Or, if the driver requested counter masks, a mask to indicate the size
21264 uint64_t mark_cnt_cos7;
21267 /***********************
21268 * hwrm_port_clr_stats *
21269 ***********************/
21272 /* hwrm_port_clr_stats_input (size:192b/24B) */
21273 struct hwrm_port_clr_stats_input {
21274 /* The HWRM command request type. */
21277 * The completion ring to send the completion event on. This should
21278 * be the NQ ID returned from the `nq_alloc` HWRM command.
21280 uint16_t cmpl_ring;
21282 * The sequence ID is used by the driver for tracking multiple
21283 * commands. This ID is treated as opaque data by the firmware and
21284 * the value is returned in the `hwrm_resp_hdr` upon completion.
21288 * The target ID of the command:
21289 * * 0x0-0xFFF8 - The function ID
21290 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21291 * * 0xFFFD - Reserved for user-space HWRM interface
21294 uint16_t target_id;
21296 * A physical address pointer pointing to a host buffer that the
21297 * command's response data will be written. This can be either a host
21298 * physical address (HPA) or a guest physical address (GPA) and must
21299 * point to a physically contiguous block of memory.
21301 uint64_t resp_addr;
21302 /* Port ID of port that is being queried. */
21306 * If set to 1, then this field indicates clear the following RoCE
21307 * specific counters.
21308 * RoCE associated TX/RX cos counters
21309 * CNP associated TX/RX cos counters
21310 * RoCE/CNP specific TX/RX flow counters
21311 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
21312 * This flag is honored only when RoCE is enabled on that port.
21314 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
21315 uint8_t unused_0[5];
21318 /* hwrm_port_clr_stats_output (size:128b/16B) */
21319 struct hwrm_port_clr_stats_output {
21320 /* The specific error status for the command. */
21321 uint16_t error_code;
21322 /* The HWRM command request type. */
21324 /* The sequence ID from the original command. */
21326 /* The length of the response data in number of bytes. */
21328 uint8_t unused_0[7];
21330 * This field is used in Output records to indicate that the output
21331 * is completely written to RAM. This field should be read as '1'
21332 * to indicate that the output has been completely written.
21333 * When writing a command completion or response to an internal processor,
21334 * the order of writes has to be such that this field is written last.
21339 /***********************
21340 * hwrm_port_phy_qcaps *
21341 ***********************/
21344 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
21345 struct hwrm_port_phy_qcaps_input {
21346 /* The HWRM command request type. */
21349 * The completion ring to send the completion event on. This should
21350 * be the NQ ID returned from the `nq_alloc` HWRM command.
21352 uint16_t cmpl_ring;
21354 * The sequence ID is used by the driver for tracking multiple
21355 * commands. This ID is treated as opaque data by the firmware and
21356 * the value is returned in the `hwrm_resp_hdr` upon completion.
21360 * The target ID of the command:
21361 * * 0x0-0xFFF8 - The function ID
21362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21363 * * 0xFFFD - Reserved for user-space HWRM interface
21366 uint16_t target_id;
21368 * A physical address pointer pointing to a host buffer that the
21369 * command's response data will be written. This can be either a host
21370 * physical address (HPA) or a guest physical address (GPA) and must
21371 * point to a physically contiguous block of memory.
21373 uint64_t resp_addr;
21374 /* Port ID of port that is being queried. */
21376 uint8_t unused_0[6];
21379 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
21380 struct hwrm_port_phy_qcaps_output {
21381 /* The specific error status for the command. */
21382 uint16_t error_code;
21383 /* The HWRM command request type. */
21385 /* The sequence ID from the original command. */
21387 /* The length of the response data in number of bytes. */
21389 /* PHY capability flags */
21392 * If set to 1, then this field indicates that the
21393 * link is capable of supporting EEE.
21395 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
21398 * If set to 1, then this field indicates that the
21399 * PHY is capable of supporting external loopback.
21401 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
21404 * If set to 1, then this field indicates that the
21405 * PHY is capable of supporting loopback in autoneg mode.
21407 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
21410 * Indicates if the configuration of shared PHY settings is supported.
21411 * In cases where a physical port is shared by multiple functions
21412 * (e.g. NPAR, multihost, etc), the configuration of PHY
21413 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
21414 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
21416 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
21419 * If set to 1, it indicates that the port counters and extended
21420 * port counters will not reset when the firmware shuts down or
21421 * resets the PHY. These counters will only be reset during power
21422 * cycle or by calling HWRM_PORT_CLR_STATS.
21423 * If set to 0, the state of the counters is unspecified when
21424 * firmware shuts down or resets the PHY.
21426 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
21429 * If set to 1, then this field indicates that the
21430 * local loopback is not supported on this controller.
21432 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
21435 * Reserved field. The HWRM shall set this field to 0.
21436 * An HWRM client shall ignore this field.
21438 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
21440 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \
21442 /* Number of front panel ports for this device. */
21444 /* Not supported or unknown */
21445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
21446 /* single port device */
21447 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
21448 /* 2-port device */
21449 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
21450 /* 3-port device */
21451 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
21452 /* 4-port device */
21453 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
21454 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
21455 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
21457 * This is a bit mask to indicate what speeds are supported
21458 * as forced speeds on this link.
21459 * For each speed that can be forced on this link, the
21460 * corresponding mask bit shall be set to '1'.
21462 uint16_t supported_speeds_force_mode;
21463 /* 100Mb link speed (Half-duplex) */
21464 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
21466 /* 100Mb link speed (Full-duplex) */
21467 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
21469 /* 1Gb link speed (Half-duplex) */
21470 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
21472 /* 1Gb link speed (Full-duplex) */
21473 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
21475 /* 2Gb link speed */
21476 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
21478 /* 25Gb link speed */
21479 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
21481 /* 10Gb link speed */
21482 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
21484 /* 20Gb link speed */
21485 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
21487 /* 25Gb link speed */
21488 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
21490 /* 40Gb link speed */
21491 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
21493 /* 50Gb link speed */
21494 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
21496 /* 100Gb link speed */
21497 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
21499 /* 10Mb link speed (Half-duplex) */
21500 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
21502 /* 10Mb link speed (Full-duplex) */
21503 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
21506 * This is a bit mask to indicate what speeds are supported
21507 * for autonegotiation on this link.
21508 * For each speed that can be autonegotiated on this link, the
21509 * corresponding mask bit shall be set to '1'.
21511 uint16_t supported_speeds_auto_mode;
21512 /* 100Mb link speed (Half-duplex) */
21513 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
21515 /* 100Mb link speed (Full-duplex) */
21516 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
21518 /* 1Gb link speed (Half-duplex) */
21519 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
21521 /* 1Gb link speed (Full-duplex) */
21522 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
21524 /* 2Gb link speed */
21525 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
21527 /* 25Gb link speed */
21528 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
21530 /* 10Gb link speed */
21531 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
21533 /* 20Gb link speed */
21534 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
21536 /* 25Gb link speed */
21537 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
21539 /* 40Gb link speed */
21540 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
21542 /* 50Gb link speed */
21543 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
21545 /* 100Gb link speed */
21546 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
21548 /* 10Mb link speed (Half-duplex) */
21549 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
21551 /* 10Mb link speed (Full-duplex) */
21552 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
21555 * This is a bit mask to indicate what speeds are supported
21556 * for EEE on this link.
21557 * For each speed that can be autonegotiated when EEE is enabled
21558 * on this link, the corresponding mask bit shall be set to '1'.
21559 * This field is only valid when the eee_suppotred is set to '1'.
21561 uint16_t supported_speeds_eee_mode;
21563 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
21565 /* 100Mb link speed (Full-duplex) */
21566 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
21569 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
21571 /* 1Gb link speed (Full-duplex) */
21572 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
21575 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
21578 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
21580 /* 10Gb link speed */
21581 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
21583 uint32_t tx_lpi_timer_low;
21585 * The lowest value of TX LPI timer that can be set on this link
21586 * when EEE is enabled. This value is in microseconds.
21587 * This field is valid only when_eee_supported is set to '1'.
21589 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
21591 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
21593 * Reserved field. The HWRM shall set this field to 0.
21594 * An HWRM client shall ignore this field.
21596 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
21597 UINT32_C(0xff000000)
21598 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
21599 uint32_t valid_tx_lpi_timer_high;
21601 * The highest value of TX LPI timer that can be set on this link
21602 * when EEE is enabled. This value is in microseconds.
21603 * This field is valid only when_eee_supported is set to '1'.
21605 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
21607 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
21609 * Reserved field. The HWRM shall set this field to 0.
21610 * An HWRM client shall ignore this field.
21612 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
21613 UINT32_C(0xff000000)
21614 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
21616 * This field is used to advertise which PAM4 speeds are supported
21619 uint16_t supported_pam4_speeds_auto_mode;
21620 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
21622 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
21624 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
21627 * This field is used to advertise which PAM4 speeds are supported
21630 uint16_t supported_pam4_speeds_force_mode;
21631 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
21633 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
21635 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
21637 uint8_t unused_0[3];
21639 * This field is used in Output records to indicate that the output
21640 * is completely written to RAM. This field should be read as '1'
21641 * to indicate that the output has been completely written.
21642 * When writing a command completion or response to an internal processor,
21643 * the order of writes has to be such that this field is written last.
21648 /****************************
21649 * hwrm_port_phy_mdio_write *
21650 ****************************/
21653 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
21654 struct hwrm_port_phy_mdio_write_input {
21655 /* The HWRM command request type. */
21658 * The completion ring to send the completion event on. This should
21659 * be the NQ ID returned from the `nq_alloc` HWRM command.
21661 uint16_t cmpl_ring;
21663 * The sequence ID is used by the driver for tracking multiple
21664 * commands. This ID is treated as opaque data by the firmware and
21665 * the value is returned in the `hwrm_resp_hdr` upon completion.
21669 * The target ID of the command:
21670 * * 0x0-0xFFF8 - The function ID
21671 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21672 * * 0xFFFD - Reserved for user-space HWRM interface
21675 uint16_t target_id;
21677 * A physical address pointer pointing to a host buffer that the
21678 * command's response data will be written. This can be either a host
21679 * physical address (HPA) or a guest physical address (GPA) and must
21680 * point to a physically contiguous block of memory.
21682 uint64_t resp_addr;
21683 /* Reserved for future use. */
21684 uint32_t unused_0[2];
21685 /* Port ID of port. */
21687 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
21689 /* 8-bit device address. */
21691 /* 16-bit register address. */
21693 /* 16-bit register data. */
21696 * When this bit is set to 1 a Clause 45 mdio access is done.
21697 * when this bit is set to 0 a Clause 22 mdio access is done.
21701 uint8_t unused_1[7];
21704 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
21705 struct hwrm_port_phy_mdio_write_output {
21706 /* The specific error status for the command. */
21707 uint16_t error_code;
21708 /* The HWRM command request type. */
21710 /* The sequence ID from the original command. */
21712 /* The length of the response data in number of bytes. */
21714 uint8_t unused_0[7];
21716 * This field is used in Output records to indicate that the output
21717 * is completely written to RAM. This field should be read as '1'
21718 * to indicate that the output has been completely written.
21719 * When writing a command completion or response to an internal processor,
21720 * the order of writes has to be such that this field is written last.
21725 /***************************
21726 * hwrm_port_phy_mdio_read *
21727 ***************************/
21730 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
21731 struct hwrm_port_phy_mdio_read_input {
21732 /* The HWRM command request type. */
21735 * The completion ring to send the completion event on. This should
21736 * be the NQ ID returned from the `nq_alloc` HWRM command.
21738 uint16_t cmpl_ring;
21740 * The sequence ID is used by the driver for tracking multiple
21741 * commands. This ID is treated as opaque data by the firmware and
21742 * the value is returned in the `hwrm_resp_hdr` upon completion.
21746 * The target ID of the command:
21747 * * 0x0-0xFFF8 - The function ID
21748 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21749 * * 0xFFFD - Reserved for user-space HWRM interface
21752 uint16_t target_id;
21754 * A physical address pointer pointing to a host buffer that the
21755 * command's response data will be written. This can be either a host
21756 * physical address (HPA) or a guest physical address (GPA) and must
21757 * point to a physically contiguous block of memory.
21759 uint64_t resp_addr;
21760 /* Reserved for future use. */
21761 uint32_t unused_0[2];
21762 /* Port ID of port. */
21764 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
21766 /* 8-bit device address. */
21768 /* 16-bit register address. */
21771 * When this bit is set to 1 a Clause 45 mdio access is done.
21772 * when this bit is set to 0 a Clause 22 mdio access is done.
21779 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
21780 struct hwrm_port_phy_mdio_read_output {
21781 /* The specific error status for the command. */
21782 uint16_t error_code;
21783 /* The HWRM command request type. */
21785 /* The sequence ID from the original command. */
21787 /* The length of the response data in number of bytes. */
21789 /* 16-bit register data. */
21791 uint8_t unused_0[5];
21793 * This field is used in Output records to indicate that the output
21794 * is completely written to RAM. This field should be read as '1'
21795 * to indicate that the output has been completely written.
21796 * When writing a command completion or response to an internal processor,
21797 * the order of writes has to be such that this field is written last.
21802 /*********************
21803 * hwrm_port_led_cfg *
21804 *********************/
21807 /* hwrm_port_led_cfg_input (size:512b/64B) */
21808 struct hwrm_port_led_cfg_input {
21809 /* The HWRM command request type. */
21812 * The completion ring to send the completion event on. This should
21813 * be the NQ ID returned from the `nq_alloc` HWRM command.
21815 uint16_t cmpl_ring;
21817 * The sequence ID is used by the driver for tracking multiple
21818 * commands. This ID is treated as opaque data by the firmware and
21819 * the value is returned in the `hwrm_resp_hdr` upon completion.
21823 * The target ID of the command:
21824 * * 0x0-0xFFF8 - The function ID
21825 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21826 * * 0xFFFD - Reserved for user-space HWRM interface
21829 uint16_t target_id;
21831 * A physical address pointer pointing to a host buffer that the
21832 * command's response data will be written. This can be either a host
21833 * physical address (HPA) or a guest physical address (GPA) and must
21834 * point to a physically contiguous block of memory.
21836 uint64_t resp_addr;
21839 * This bit must be '1' for the led0_id field to be
21842 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
21845 * This bit must be '1' for the led0_state field to be
21848 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
21851 * This bit must be '1' for the led0_color field to be
21854 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
21857 * This bit must be '1' for the led0_blink_on field to be
21860 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
21863 * This bit must be '1' for the led0_blink_off field to be
21866 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
21869 * This bit must be '1' for the led0_group_id field to be
21872 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
21875 * This bit must be '1' for the led1_id field to be
21878 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
21881 * This bit must be '1' for the led1_state field to be
21884 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
21887 * This bit must be '1' for the led1_color field to be
21890 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
21893 * This bit must be '1' for the led1_blink_on field to be
21896 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
21899 * This bit must be '1' for the led1_blink_off field to be
21902 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
21905 * This bit must be '1' for the led1_group_id field to be
21908 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
21911 * This bit must be '1' for the led2_id field to be
21914 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
21917 * This bit must be '1' for the led2_state field to be
21920 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
21923 * This bit must be '1' for the led2_color field to be
21926 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
21929 * This bit must be '1' for the led2_blink_on field to be
21932 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
21935 * This bit must be '1' for the led2_blink_off field to be
21938 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
21941 * This bit must be '1' for the led2_group_id field to be
21944 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
21947 * This bit must be '1' for the led3_id field to be
21950 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
21953 * This bit must be '1' for the led3_state field to be
21956 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
21959 * This bit must be '1' for the led3_color field to be
21962 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
21965 * This bit must be '1' for the led3_blink_on field to be
21968 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
21971 * This bit must be '1' for the led3_blink_off field to be
21974 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
21977 * This bit must be '1' for the led3_group_id field to be
21980 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
21982 /* Port ID of port whose LEDs are configured. */
21985 * The number of LEDs that are being configured.
21986 * Up to 4 LEDs can be configured with this command.
21989 /* Reserved field. */
21991 /* An identifier for the LED #0. */
21993 /* The requested state of the LED #0. */
21994 uint8_t led0_state;
21995 /* Default state of the LED */
21996 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
21998 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
22000 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
22002 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
22003 /* Blink Alternately */
22004 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
22005 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
22006 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
22007 /* The requested color of LED #0. */
22008 uint8_t led0_color;
22010 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
22012 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
22014 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
22015 /* Green or Amber */
22016 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
22017 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
22018 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
22021 * If the LED #0 state is "blink" or "blinkalt", then
22022 * this field represents the requested time in milliseconds
22023 * to keep LED on between cycles.
22025 uint16_t led0_blink_on;
22027 * If the LED #0 state is "blink" or "blinkalt", then
22028 * this field represents the requested time in milliseconds
22029 * to keep LED off between cycles.
22031 uint16_t led0_blink_off;
22033 * An identifier for the group of LEDs that LED #0 belongs
22035 * If set to 0, then the LED #0 shall not be grouped and
22036 * shall be treated as an individual resource.
22037 * For all other non-zero values of this field, LED #0 shall
22038 * be grouped together with the LEDs with the same group ID
22041 uint8_t led0_group_id;
22042 /* Reserved field. */
22044 /* An identifier for the LED #1. */
22046 /* The requested state of the LED #1. */
22047 uint8_t led1_state;
22048 /* Default state of the LED */
22049 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
22051 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
22053 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
22055 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
22056 /* Blink Alternately */
22057 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
22058 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
22059 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
22060 /* The requested color of LED #1. */
22061 uint8_t led1_color;
22063 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
22065 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
22067 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
22068 /* Green or Amber */
22069 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
22070 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
22071 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
22074 * If the LED #1 state is "blink" or "blinkalt", then
22075 * this field represents the requested time in milliseconds
22076 * to keep LED on between cycles.
22078 uint16_t led1_blink_on;
22080 * If the LED #1 state is "blink" or "blinkalt", then
22081 * this field represents the requested time in milliseconds
22082 * to keep LED off between cycles.
22084 uint16_t led1_blink_off;
22086 * An identifier for the group of LEDs that LED #1 belongs
22088 * If set to 0, then the LED #1 shall not be grouped and
22089 * shall be treated as an individual resource.
22090 * For all other non-zero values of this field, LED #1 shall
22091 * be grouped together with the LEDs with the same group ID
22094 uint8_t led1_group_id;
22095 /* Reserved field. */
22097 /* An identifier for the LED #2. */
22099 /* The requested state of the LED #2. */
22100 uint8_t led2_state;
22101 /* Default state of the LED */
22102 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
22104 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
22106 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
22108 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
22109 /* Blink Alternately */
22110 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
22111 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
22112 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
22113 /* The requested color of LED #2. */
22114 uint8_t led2_color;
22116 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
22118 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
22120 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
22121 /* Green or Amber */
22122 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
22123 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
22124 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
22127 * If the LED #2 state is "blink" or "blinkalt", then
22128 * this field represents the requested time in milliseconds
22129 * to keep LED on between cycles.
22131 uint16_t led2_blink_on;
22133 * If the LED #2 state is "blink" or "blinkalt", then
22134 * this field represents the requested time in milliseconds
22135 * to keep LED off between cycles.
22137 uint16_t led2_blink_off;
22139 * An identifier for the group of LEDs that LED #2 belongs
22141 * If set to 0, then the LED #2 shall not be grouped and
22142 * shall be treated as an individual resource.
22143 * For all other non-zero values of this field, LED #2 shall
22144 * be grouped together with the LEDs with the same group ID
22147 uint8_t led2_group_id;
22148 /* Reserved field. */
22150 /* An identifier for the LED #3. */
22152 /* The requested state of the LED #3. */
22153 uint8_t led3_state;
22154 /* Default state of the LED */
22155 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
22157 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
22159 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
22161 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
22162 /* Blink Alternately */
22163 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
22164 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
22165 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
22166 /* The requested color of LED #3. */
22167 uint8_t led3_color;
22169 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
22171 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
22173 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
22174 /* Green or Amber */
22175 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
22176 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
22177 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
22180 * If the LED #3 state is "blink" or "blinkalt", then
22181 * this field represents the requested time in milliseconds
22182 * to keep LED on between cycles.
22184 uint16_t led3_blink_on;
22186 * If the LED #3 state is "blink" or "blinkalt", then
22187 * this field represents the requested time in milliseconds
22188 * to keep LED off between cycles.
22190 uint16_t led3_blink_off;
22192 * An identifier for the group of LEDs that LED #3 belongs
22194 * If set to 0, then the LED #3 shall not be grouped and
22195 * shall be treated as an individual resource.
22196 * For all other non-zero values of this field, LED #3 shall
22197 * be grouped together with the LEDs with the same group ID
22200 uint8_t led3_group_id;
22201 /* Reserved field. */
22205 /* hwrm_port_led_cfg_output (size:128b/16B) */
22206 struct hwrm_port_led_cfg_output {
22207 /* The specific error status for the command. */
22208 uint16_t error_code;
22209 /* The HWRM command request type. */
22211 /* The sequence ID from the original command. */
22213 /* The length of the response data in number of bytes. */
22215 uint8_t unused_0[7];
22217 * This field is used in Output records to indicate that the output
22218 * is completely written to RAM. This field should be read as '1'
22219 * to indicate that the output has been completely written.
22220 * When writing a command completion or response to an internal processor,
22221 * the order of writes has to be such that this field is written last.
22226 /**********************
22227 * hwrm_port_led_qcfg *
22228 **********************/
22231 /* hwrm_port_led_qcfg_input (size:192b/24B) */
22232 struct hwrm_port_led_qcfg_input {
22233 /* The HWRM command request type. */
22236 * The completion ring to send the completion event on. This should
22237 * be the NQ ID returned from the `nq_alloc` HWRM command.
22239 uint16_t cmpl_ring;
22241 * The sequence ID is used by the driver for tracking multiple
22242 * commands. This ID is treated as opaque data by the firmware and
22243 * the value is returned in the `hwrm_resp_hdr` upon completion.
22247 * The target ID of the command:
22248 * * 0x0-0xFFF8 - The function ID
22249 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22250 * * 0xFFFD - Reserved for user-space HWRM interface
22253 uint16_t target_id;
22255 * A physical address pointer pointing to a host buffer that the
22256 * command's response data will be written. This can be either a host
22257 * physical address (HPA) or a guest physical address (GPA) and must
22258 * point to a physically contiguous block of memory.
22260 uint64_t resp_addr;
22261 /* Port ID of port whose LED configuration is being queried. */
22263 uint8_t unused_0[6];
22266 /* hwrm_port_led_qcfg_output (size:448b/56B) */
22267 struct hwrm_port_led_qcfg_output {
22268 /* The specific error status for the command. */
22269 uint16_t error_code;
22270 /* The HWRM command request type. */
22272 /* The sequence ID from the original command. */
22274 /* The length of the response data in number of bytes. */
22277 * The number of LEDs that are configured on this port.
22278 * Up to 4 LEDs can be returned in the response.
22281 /* An identifier for the LED #0. */
22283 /* The type of LED #0. */
22286 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
22288 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
22290 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
22291 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
22292 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
22293 /* The current state of the LED #0. */
22294 uint8_t led0_state;
22295 /* Default state of the LED */
22296 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
22298 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
22300 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
22302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
22303 /* Blink Alternately */
22304 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
22305 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
22306 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
22307 /* The color of LED #0. */
22308 uint8_t led0_color;
22310 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
22312 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
22314 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
22315 /* Green or Amber */
22316 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
22317 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
22318 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
22321 * If the LED #0 state is "blink" or "blinkalt", then
22322 * this field represents the requested time in milliseconds
22323 * to keep LED on between cycles.
22325 uint16_t led0_blink_on;
22327 * If the LED #0 state is "blink" or "blinkalt", then
22328 * this field represents the requested time in milliseconds
22329 * to keep LED off between cycles.
22331 uint16_t led0_blink_off;
22333 * An identifier for the group of LEDs that LED #0 belongs
22335 * If set to 0, then the LED #0 is not grouped.
22336 * For all other non-zero values of this field, LED #0 is
22337 * grouped together with the LEDs with the same group ID
22340 uint8_t led0_group_id;
22341 /* An identifier for the LED #1. */
22343 /* The type of LED #1. */
22346 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
22348 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
22350 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
22351 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
22352 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
22353 /* The current state of the LED #1. */
22354 uint8_t led1_state;
22355 /* Default state of the LED */
22356 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
22358 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
22360 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
22362 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
22363 /* Blink Alternately */
22364 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
22365 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
22366 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
22367 /* The color of LED #1. */
22368 uint8_t led1_color;
22370 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
22372 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
22374 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
22375 /* Green or Amber */
22376 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
22377 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
22378 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
22381 * If the LED #1 state is "blink" or "blinkalt", then
22382 * this field represents the requested time in milliseconds
22383 * to keep LED on between cycles.
22385 uint16_t led1_blink_on;
22387 * If the LED #1 state is "blink" or "blinkalt", then
22388 * this field represents the requested time in milliseconds
22389 * to keep LED off between cycles.
22391 uint16_t led1_blink_off;
22393 * An identifier for the group of LEDs that LED #1 belongs
22395 * If set to 0, then the LED #1 is not grouped.
22396 * For all other non-zero values of this field, LED #1 is
22397 * grouped together with the LEDs with the same group ID
22400 uint8_t led1_group_id;
22401 /* An identifier for the LED #2. */
22403 /* The type of LED #2. */
22406 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
22408 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
22410 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
22411 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
22412 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
22413 /* The current state of the LED #2. */
22414 uint8_t led2_state;
22415 /* Default state of the LED */
22416 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
22418 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
22420 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
22422 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
22423 /* Blink Alternately */
22424 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
22425 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
22426 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
22427 /* The color of LED #2. */
22428 uint8_t led2_color;
22430 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
22432 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
22434 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
22435 /* Green or Amber */
22436 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
22437 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
22438 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
22441 * If the LED #2 state is "blink" or "blinkalt", then
22442 * this field represents the requested time in milliseconds
22443 * to keep LED on between cycles.
22445 uint16_t led2_blink_on;
22447 * If the LED #2 state is "blink" or "blinkalt", then
22448 * this field represents the requested time in milliseconds
22449 * to keep LED off between cycles.
22451 uint16_t led2_blink_off;
22453 * An identifier for the group of LEDs that LED #2 belongs
22455 * If set to 0, then the LED #2 is not grouped.
22456 * For all other non-zero values of this field, LED #2 is
22457 * grouped together with the LEDs with the same group ID
22460 uint8_t led2_group_id;
22461 /* An identifier for the LED #3. */
22463 /* The type of LED #3. */
22466 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
22468 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
22470 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
22471 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
22472 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
22473 /* The current state of the LED #3. */
22474 uint8_t led3_state;
22475 /* Default state of the LED */
22476 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
22478 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
22480 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
22482 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
22483 /* Blink Alternately */
22484 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
22485 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
22486 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
22487 /* The color of LED #3. */
22488 uint8_t led3_color;
22490 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
22492 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
22494 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
22495 /* Green or Amber */
22496 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
22497 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
22498 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
22501 * If the LED #3 state is "blink" or "blinkalt", then
22502 * this field represents the requested time in milliseconds
22503 * to keep LED on between cycles.
22505 uint16_t led3_blink_on;
22507 * If the LED #3 state is "blink" or "blinkalt", then
22508 * this field represents the requested time in milliseconds
22509 * to keep LED off between cycles.
22511 uint16_t led3_blink_off;
22513 * An identifier for the group of LEDs that LED #3 belongs
22515 * If set to 0, then the LED #3 is not grouped.
22516 * For all other non-zero values of this field, LED #3 is
22517 * grouped together with the LEDs with the same group ID
22520 uint8_t led3_group_id;
22521 uint8_t unused_4[6];
22523 * This field is used in Output records to indicate that the output
22524 * is completely written to RAM. This field should be read as '1'
22525 * to indicate that the output has been completely written.
22526 * When writing a command completion or response to an internal processor,
22527 * the order of writes has to be such that this field is written last.
22532 /***********************
22533 * hwrm_port_led_qcaps *
22534 ***********************/
22537 /* hwrm_port_led_qcaps_input (size:192b/24B) */
22538 struct hwrm_port_led_qcaps_input {
22539 /* The HWRM command request type. */
22542 * The completion ring to send the completion event on. This should
22543 * be the NQ ID returned from the `nq_alloc` HWRM command.
22545 uint16_t cmpl_ring;
22547 * The sequence ID is used by the driver for tracking multiple
22548 * commands. This ID is treated as opaque data by the firmware and
22549 * the value is returned in the `hwrm_resp_hdr` upon completion.
22553 * The target ID of the command:
22554 * * 0x0-0xFFF8 - The function ID
22555 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22556 * * 0xFFFD - Reserved for user-space HWRM interface
22559 uint16_t target_id;
22561 * A physical address pointer pointing to a host buffer that the
22562 * command's response data will be written. This can be either a host
22563 * physical address (HPA) or a guest physical address (GPA) and must
22564 * point to a physically contiguous block of memory.
22566 uint64_t resp_addr;
22567 /* Port ID of port whose LED configuration is being queried. */
22569 uint8_t unused_0[6];
22572 /* hwrm_port_led_qcaps_output (size:384b/48B) */
22573 struct hwrm_port_led_qcaps_output {
22574 /* The specific error status for the command. */
22575 uint16_t error_code;
22576 /* The HWRM command request type. */
22578 /* The sequence ID from the original command. */
22580 /* The length of the response data in number of bytes. */
22583 * The number of LEDs that are configured on this port.
22584 * Up to 4 LEDs can be returned in the response.
22587 /* Reserved for future use. */
22589 /* An identifier for the LED #0. */
22591 /* The type of LED #0. */
22594 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
22596 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
22598 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
22599 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
22600 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
22602 * An identifier for the group of LEDs that LED #0 belongs
22604 * If set to 0, then the LED #0 cannot be grouped.
22605 * For all other non-zero values of this field, LED #0 is
22606 * grouped together with the LEDs with the same group ID
22609 uint8_t led0_group_id;
22611 /* The states supported by LED #0. */
22612 uint16_t led0_state_caps;
22614 * If set to 1, this LED is enabled.
22615 * If set to 0, this LED is disabled.
22617 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
22620 * If set to 1, off state is supported on this LED.
22621 * If set to 0, off state is not supported on this LED.
22623 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
22626 * If set to 1, on state is supported on this LED.
22627 * If set to 0, on state is not supported on this LED.
22629 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
22632 * If set to 1, blink state is supported on this LED.
22633 * If set to 0, blink state is not supported on this LED.
22635 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
22638 * If set to 1, blink_alt state is supported on this LED.
22639 * If set to 0, blink_alt state is not supported on this LED.
22641 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
22643 /* The colors supported by LED #0. */
22644 uint16_t led0_color_caps;
22646 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
22649 * If set to 1, Amber color is supported on this LED.
22650 * If set to 0, Amber color is not supported on this LED.
22652 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
22655 * If set to 1, Green color is supported on this LED.
22656 * If set to 0, Green color is not supported on this LED.
22658 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
22660 /* An identifier for the LED #1. */
22662 /* The type of LED #1. */
22665 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
22667 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
22669 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
22670 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
22671 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
22673 * An identifier for the group of LEDs that LED #1 belongs
22675 * If set to 0, then the LED #0 cannot be grouped.
22676 * For all other non-zero values of this field, LED #0 is
22677 * grouped together with the LEDs with the same group ID
22680 uint8_t led1_group_id;
22682 /* The states supported by LED #1. */
22683 uint16_t led1_state_caps;
22685 * If set to 1, this LED is enabled.
22686 * If set to 0, this LED is disabled.
22688 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
22691 * If set to 1, off state is supported on this LED.
22692 * If set to 0, off state is not supported on this LED.
22694 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
22697 * If set to 1, on state is supported on this LED.
22698 * If set to 0, on state is not supported on this LED.
22700 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
22703 * If set to 1, blink state is supported on this LED.
22704 * If set to 0, blink state is not supported on this LED.
22706 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
22709 * If set to 1, blink_alt state is supported on this LED.
22710 * If set to 0, blink_alt state is not supported on this LED.
22712 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
22714 /* The colors supported by LED #1. */
22715 uint16_t led1_color_caps;
22717 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
22720 * If set to 1, Amber color is supported on this LED.
22721 * If set to 0, Amber color is not supported on this LED.
22723 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
22726 * If set to 1, Green color is supported on this LED.
22727 * If set to 0, Green color is not supported on this LED.
22729 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
22731 /* An identifier for the LED #2. */
22733 /* The type of LED #2. */
22736 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
22738 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
22740 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
22741 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
22742 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
22744 * An identifier for the group of LEDs that LED #0 belongs
22746 * If set to 0, then the LED #0 cannot be grouped.
22747 * For all other non-zero values of this field, LED #0 is
22748 * grouped together with the LEDs with the same group ID
22751 uint8_t led2_group_id;
22753 /* The states supported by LED #2. */
22754 uint16_t led2_state_caps;
22756 * If set to 1, this LED is enabled.
22757 * If set to 0, this LED is disabled.
22759 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
22762 * If set to 1, off state is supported on this LED.
22763 * If set to 0, off state is not supported on this LED.
22765 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
22768 * If set to 1, on state is supported on this LED.
22769 * If set to 0, on state is not supported on this LED.
22771 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
22774 * If set to 1, blink state is supported on this LED.
22775 * If set to 0, blink state is not supported on this LED.
22777 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
22780 * If set to 1, blink_alt state is supported on this LED.
22781 * If set to 0, blink_alt state is not supported on this LED.
22783 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
22785 /* The colors supported by LED #2. */
22786 uint16_t led2_color_caps;
22788 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
22791 * If set to 1, Amber color is supported on this LED.
22792 * If set to 0, Amber color is not supported on this LED.
22794 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
22797 * If set to 1, Green color is supported on this LED.
22798 * If set to 0, Green color is not supported on this LED.
22800 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
22802 /* An identifier for the LED #3. */
22804 /* The type of LED #3. */
22807 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
22809 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
22811 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
22812 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
22813 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
22815 * An identifier for the group of LEDs that LED #3 belongs
22817 * If set to 0, then the LED #0 cannot be grouped.
22818 * For all other non-zero values of this field, LED #0 is
22819 * grouped together with the LEDs with the same group ID
22822 uint8_t led3_group_id;
22824 /* The states supported by LED #3. */
22825 uint16_t led3_state_caps;
22827 * If set to 1, this LED is enabled.
22828 * If set to 0, this LED is disabled.
22830 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
22833 * If set to 1, off state is supported on this LED.
22834 * If set to 0, off state is not supported on this LED.
22836 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
22839 * If set to 1, on state is supported on this LED.
22840 * If set to 0, on state is not supported on this LED.
22842 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
22845 * If set to 1, blink state is supported on this LED.
22846 * If set to 0, blink state is not supported on this LED.
22848 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
22851 * If set to 1, blink_alt state is supported on this LED.
22852 * If set to 0, blink_alt state is not supported on this LED.
22854 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
22856 /* The colors supported by LED #3. */
22857 uint16_t led3_color_caps;
22859 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
22862 * If set to 1, Amber color is supported on this LED.
22863 * If set to 0, Amber color is not supported on this LED.
22865 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
22868 * If set to 1, Green color is supported on this LED.
22869 * If set to 0, Green color is not supported on this LED.
22871 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
22873 uint8_t unused_4[3];
22875 * This field is used in Output records to indicate that the output
22876 * is completely written to RAM. This field should be read as '1'
22877 * to indicate that the output has been completely written.
22878 * When writing a command completion or response to an internal processor,
22879 * the order of writes has to be such that this field is written last.
22884 /***********************
22885 * hwrm_port_prbs_test *
22886 ***********************/
22889 /* hwrm_port_prbs_test_input (size:384b/48B) */
22890 struct hwrm_port_prbs_test_input {
22891 /* The HWRM command request type. */
22894 * The completion ring to send the completion event on. This should
22895 * be the NQ ID returned from the `nq_alloc` HWRM command.
22897 uint16_t cmpl_ring;
22899 * The sequence ID is used by the driver for tracking multiple
22900 * commands. This ID is treated as opaque data by the firmware and
22901 * the value is returned in the `hwrm_resp_hdr` upon completion.
22905 * The target ID of the command:
22906 * * 0x0-0xFFF8 - The function ID
22907 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22908 * * 0xFFFD - Reserved for user-space HWRM interface
22911 uint16_t target_id;
22913 * A physical address pointer pointing to a host buffer that the
22914 * command's response data will be written. This can be either a host
22915 * physical address (HPA) or a guest physical address (GPA) and must
22916 * point to a physically contiguous block of memory.
22918 uint64_t resp_addr;
22919 /* Host address data is to DMA'd to. */
22920 uint64_t resp_data_addr;
22922 * Size of the buffer pointed to by resp_data_addr. The firmware may
22923 * use this entire buffer or less than the entire buffer, but never more.
22928 /* Port ID of port where PRBS test to be run. */
22930 /* Polynomial selection for PRBS test. */
22933 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
22935 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
22937 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
22939 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
22941 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
22943 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
22945 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
22947 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
22948 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
22949 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
22951 * Configuration bits for PRBS test.
22952 * Use enable bit to start/stop test.
22953 * Use tx/rx lane map bits to run test on specific lanes,
22954 * if set to 0 test will be run on all lanes.
22956 uint16_t prbs_config;
22958 * Set 0 to stop test currently in progress
22959 * Set 1 to start test with configuration provided.
22961 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
22964 * If set to 1, tx_lane_map bitmap should have lane bits set.
22965 * If set to 0, test will be run on all lanes for this port.
22967 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
22970 * If set to 1, rx_lane_map bitmap should have lane bits set.
22971 * If set to 0, test will be run on all lanes for this port.
22973 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
22975 /* Duration in seconds to run the PRBS test. */
22978 * If tx_lane_map_valid is set to 1, this field is a bitmap
22979 * of tx lanes to run PRBS test. bit0 = lane0,
22980 * bit1 = lane1 ..bit31 = lane31
22982 uint32_t tx_lane_map;
22984 * If rx_lane_map_valid is set to 1, this field is a bitmap
22985 * of rx lanes to run PRBS test. bit0 = lane0,
22986 * bit1 = lane1 ..bit31 = lane31
22988 uint32_t rx_lane_map;
22991 /* hwrm_port_prbs_test_output (size:128b/16B) */
22992 struct hwrm_port_prbs_test_output {
22993 /* The specific error status for the command. */
22994 uint16_t error_code;
22995 /* The HWRM command request type. */
22997 /* The sequence ID from the original command. */
22999 /* The length of the response data in number of bytes. */
23001 /* Total length of stored data. */
23002 uint16_t total_data_len;
23004 uint8_t unused_1[3];
23006 * This field is used in Output records to indicate that the output
23007 * is completely written to RAM. This field should be read as '1'
23008 * to indicate that the output has been completely written.
23009 * When writing a command completion or response to an internal processor,
23010 * the order of writes has to be such that this field is written last.
23015 /**********************
23016 * hwrm_port_dsc_dump *
23017 **********************/
23020 /* hwrm_port_dsc_dump_input (size:320b/40B) */
23021 struct hwrm_port_dsc_dump_input {
23022 /* The HWRM command request type. */
23025 * The completion ring to send the completion event on. This should
23026 * be the NQ ID returned from the `nq_alloc` HWRM command.
23028 uint16_t cmpl_ring;
23030 * The sequence ID is used by the driver for tracking multiple
23031 * commands. This ID is treated as opaque data by the firmware and
23032 * the value is returned in the `hwrm_resp_hdr` upon completion.
23036 * The target ID of the command:
23037 * * 0x0-0xFFF8 - The function ID
23038 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23039 * * 0xFFFD - Reserved for user-space HWRM interface
23042 uint16_t target_id;
23044 * A physical address pointer pointing to a host buffer that the
23045 * command's response data will be written. This can be either a host
23046 * physical address (HPA) or a guest physical address (GPA) and must
23047 * point to a physically contiguous block of memory.
23049 uint64_t resp_addr;
23050 /* Host address where response diagnostic data is returned. */
23051 uint64_t resp_data_addr;
23053 * Size of the buffer pointed to by resp_data_addr. The firmware
23054 * may use this entire buffer or less than the entire buffer, but
23060 /* Port ID of port where dsc dump to be collected. */
23062 /* Diag level specified by the user */
23063 uint16_t diag_level;
23064 /* SRDS_DIAG_LANE */
23065 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
23067 /* SRDS_DIAG_CORE */
23068 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
23070 /* SRDS_DIAG_EVENT */
23071 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
23073 /* SRDS_DIAG_EYE */
23074 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
23076 /* SRDS_DIAG_REG_CORE */
23077 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
23079 /* SRDS_DIAG_REG_LANE */
23080 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
23082 /* SRDS_DIAG_UC_CORE */
23083 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
23085 /* SRDS_DIAG_UC_LANE */
23086 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
23088 /* SRDS_DIAG_LANE_DEBUG */
23089 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
23091 /* SRDS_DIAG_BER_VERT */
23092 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
23094 /* SRDS_DIAG_BER_HORZ */
23095 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
23097 /* SRDS_DIAG_EVENT_SAFE */
23098 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
23100 /* SRDS_DIAG_TIMESTAMP */
23101 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
23103 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
23104 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
23106 * This field is a lane number
23107 * on which to collect the dsc dump
23109 uint16_t lane_number;
23111 * Configuration bits.
23112 * Use enable bit to start dsc dump or retrieve dump
23114 uint16_t dsc_dump_config;
23116 * Set 0 to retrieve the dsc dump
23117 * Set 1 to start the dsc dump
23119 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
23123 /* hwrm_port_dsc_dump_output (size:128b/16B) */
23124 struct hwrm_port_dsc_dump_output {
23125 /* The specific error status for the command. */
23126 uint16_t error_code;
23127 /* The HWRM command request type. */
23129 /* The sequence ID from the original command. */
23131 /* The length of the response data in number of bytes. */
23133 /* Total length of stored data. */
23134 uint16_t total_data_len;
23136 uint8_t unused_1[3];
23138 * This field is used in Output records to indicate that the output
23139 * is completely written to RAM. This field should be read as '1'
23140 * to indicate that the output has been completely written.
23141 * When writing a command completion or response to an internal processor,
23142 * the order of writes has to be such that this field is written last.
23147 /******************************
23148 * hwrm_port_sfp_sideband_cfg *
23149 ******************************/
23152 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
23153 struct hwrm_port_sfp_sideband_cfg_input {
23154 /* The HWRM command request type. */
23157 * The completion ring to send the completion event on. This should
23158 * be the NQ ID returned from the `nq_alloc` HWRM command.
23160 uint16_t cmpl_ring;
23162 * The sequence ID is used by the driver for tracking multiple
23163 * commands. This ID is treated as opaque data by the firmware and
23164 * the value is returned in the `hwrm_resp_hdr` upon completion.
23168 * The target ID of the command:
23169 * * 0x0-0xFFF8 - The function ID
23170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23171 * * 0xFFFD - Reserved for user-space HWRM interface
23174 uint16_t target_id;
23176 * A physical address pointer pointing to a host buffer that the
23177 * command's response data will be written. This can be either a host
23178 * physical address (HPA) or a guest physical address (GPA) and must
23179 * point to a physically contiguous block of memory.
23181 uint64_t resp_addr;
23182 /* Port ID of port that is to be queried. */
23184 uint8_t unused_0[6];
23186 * This bitfield is used to specify which bits from the 'flags'
23187 * fields are being configured by the caller.
23190 /* This bit must be '1' for rs0 to be configured. */
23191 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
23193 /* This bit must be '1' for rs1 to be configured. */
23194 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
23196 /* This bit must be '1' for tx_disable to be configured. */
23197 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
23200 * This bit must be '1' for mod_sel to be configured.
23201 * Valid only on QSFP modules
23203 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
23205 /* This bit must be '1' for reset_l to be configured. */
23206 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
23208 /* This bit must be '1' for lp_mode to be configured. */
23209 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
23211 /* This bit must be '1' for pwr_disable to be configured. */
23212 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
23215 * Only bits that have corresponding bits in the 'enables'
23216 * bitfield are processed by the firmware, all other bits
23217 * of 'flags' are ignored.
23221 * This bit along with rs1 configures the current speed of the dual
23222 * rate module. If these pins are GNDed then the speed can be changed
23223 * by driectly writing to EEPROM.
23225 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
23228 * This bit along with rs0 configures the current speed of the dual
23229 * rate module. If these pins are GNDed then the speed can be changed
23230 * by driectly writing to EEPROM.
23232 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
23235 * When this bit is set to '1', tx_disable is set.
23236 * On a 1G BASE-T module, if this bit is set,
23237 * module PHY registers will not be accessible.
23239 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
23242 * When this bit is set to '1', this module is selected.
23243 * Valid only on QSFP modules
23245 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
23248 * If reset_l is set to 0, Module will be taken out of reset
23249 * and other signals will be set to their requested state once
23250 * the module is out of reset.
23251 * Valid only on QSFP modules
23253 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
23256 * When this bit is set to '1', the module will be configured
23257 * in low power mode.
23258 * Valid only on QSFP modules
23260 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
23262 /* When this bit is set to '1', the module will be powered down. */
23263 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
23267 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
23268 struct hwrm_port_sfp_sideband_cfg_output {
23269 /* The specific error status for the command. */
23270 uint16_t error_code;
23271 /* The HWRM command request type. */
23273 /* The sequence ID from the original command. */
23275 /* The length of the response data in number of bytes. */
23279 * This field is used in Output records to indicate that the output
23280 * is completely written to RAM. This field should be read as '1'
23281 * to indicate that the output has been completely written. When
23282 * writing a command completion or response to an internal processor,
23283 * the order of writes has to be such that this field is written last.
23288 /*******************************
23289 * hwrm_port_sfp_sideband_qcfg *
23290 *******************************/
23293 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
23294 struct hwrm_port_sfp_sideband_qcfg_input {
23295 /* The HWRM command request type. */
23298 * The completion ring to send the completion event on. This should
23299 * be the NQ ID returned from the `nq_alloc` HWRM command.
23301 uint16_t cmpl_ring;
23303 * The sequence ID is used by the driver for tracking multiple
23304 * commands. This ID is treated as opaque data by the firmware and
23305 * the value is returned in the `hwrm_resp_hdr` upon completion.
23309 * The target ID of the command:
23310 * * 0x0-0xFFF8 - The function ID
23311 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23312 * * 0xFFFD - Reserved for user-space HWRM interface
23315 uint16_t target_id;
23317 * A physical address pointer pointing to a host buffer that the
23318 * command's response data will be written. This can be either a host
23319 * physical address (HPA) or a guest physical address (GPA) and must
23320 * point to a physically contiguous block of memory.
23322 uint64_t resp_addr;
23323 /* Port ID of port that is to be queried. */
23325 uint8_t unused_0[6];
23328 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
23329 struct hwrm_port_sfp_sideband_qcfg_output {
23330 /* The specific error status for the command. */
23331 uint16_t error_code;
23332 /* The HWRM command request type. */
23334 /* The sequence ID from the original command. */
23336 /* The length of the response data in number of bytes. */
23339 * Bitmask indicating which sideband signals are valid.
23340 * This is based on the board and nvm cfg that is present on the board.
23342 uint32_t supported_mask;
23343 uint32_t sideband_signals;
23344 /* When this bit is set to '1', the Module is absent. */
23345 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
23348 * When this bit is set to '1', there is no valid signal on RX.
23349 * This signal is a filtered version of Signal Detect.
23351 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
23354 * This bit along with rs1 indiactes the current speed of the dual
23355 * rate module.If these pins are grounded then the speed can be
23356 * changed by driectky writing to EEPROM.
23358 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
23361 * This bit along with rs0 indiactes the current speed of the dual
23362 * rate module.If these pins are grounded then the speed can be
23363 * changed by driectky writing to EEPROM.
23365 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
23368 * When this bit is set to '1', tx_disable is set.
23369 * On a 1G BASE-T module, if this bit is set, module PHY
23370 * registers will not be accessible.
23372 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
23374 /* When this bit is set to '1', tx_fault is set. */
23375 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
23378 * When this bit is set to '1', module is selected.
23379 * Valid only on QSFP modules
23381 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
23384 * When this bit is set to '0', the module is held in reset.
23385 * if reset_l is set to 1,first module is taken out of reset
23386 * and other signals will be set to their requested state.
23387 * Valid only on QSFP modules.
23389 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
23392 * When this bit is set to '1', the module is in low power mode.
23393 * Valid only on QSFP modules
23395 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
23397 /* When this bit is set to '1', module is in power down state. */
23398 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
23402 * This field is used in Output records to indicate that the output
23403 * is completely written to RAM. This field should be read as '1'
23404 * to indicate that the output has been completely written. When
23405 * writing a command completion or response to an internal processor,
23406 * the order of writes has to be such that this field is written last.
23411 /**********************************
23412 * hwrm_port_phy_mdio_bus_acquire *
23413 **********************************/
23416 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
23417 struct hwrm_port_phy_mdio_bus_acquire_input {
23418 /* The HWRM command request type. */
23421 * The completion ring to send the completion event on. This should
23422 * be the NQ ID returned from the `nq_alloc` HWRM command.
23424 uint16_t cmpl_ring;
23426 * The sequence ID is used by the driver for tracking multiple
23427 * commands. This ID is treated as opaque data by the firmware and
23428 * the value is returned in the `hwrm_resp_hdr` upon completion.
23432 * The target ID of the command:
23433 * * 0x0-0xFFF8 - The function ID
23434 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23435 * * 0xFFFD - Reserved for user-space HWRM interface
23438 uint16_t target_id;
23440 * A physical address pointer pointing to a host buffer that the
23441 * command's response data will be written. This can be either a host
23442 * physical address (HPA) or a guest physical address (GPA) and must
23443 * point to a physically contiguous block of memory.
23445 uint64_t resp_addr;
23446 /* Port ID of the port. */
23449 * client_id of the client requesting BUS access.
23450 * Any value from 0x10 to 0xFFFF can be used.
23451 * Client should make sure that the returned client_id
23452 * in response matches the client_id in request.
23453 * 0-0xF are reserved for internal use.
23455 uint16_t client_id;
23457 * Timeout in milli seconds, MDIO BUS will be released automatically
23458 * after this time, if another mdio acquire command is not received
23459 * within the timeout window from the same client.
23460 * A 0xFFFF will hold the bus until this bus is released.
23462 uint16_t mdio_bus_timeout;
23463 uint8_t unused_0[2];
23466 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
23467 struct hwrm_port_phy_mdio_bus_acquire_output {
23468 /* The specific error status for the command. */
23469 uint16_t error_code;
23470 /* The HWRM command request type. */
23472 /* The sequence ID from the original command. */
23474 /* The length of the response data in number of bytes. */
23478 * client_id of the module holding the BUS.
23479 * 0-0xF are reserved for internal use.
23481 uint16_t client_id;
23482 uint8_t unused_1[3];
23484 * This field is used in Output records to indicate that the output
23485 * is completely written to RAM. This field should be read as '1'
23486 * to indicate that the output has been completely written.
23487 * When writing a command completion or response to an internal processor,
23488 * the order of writes has to be such that this field is written last.
23493 /**********************************
23494 * hwrm_port_phy_mdio_bus_release *
23495 **********************************/
23498 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
23499 struct hwrm_port_phy_mdio_bus_release_input {
23500 /* The HWRM command request type. */
23503 * The completion ring to send the completion event on. This should
23504 * be the NQ ID returned from the `nq_alloc` HWRM command.
23506 uint16_t cmpl_ring;
23508 * The sequence ID is used by the driver for tracking multiple
23509 * commands. This ID is treated as opaque data by the firmware and
23510 * the value is returned in the `hwrm_resp_hdr` upon completion.
23514 * The target ID of the command:
23515 * * 0x0-0xFFF8 - The function ID
23516 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23517 * * 0xFFFD - Reserved for user-space HWRM interface
23520 uint16_t target_id;
23522 * A physical address pointer pointing to a host buffer that the
23523 * command's response data will be written. This can be either a host
23524 * physical address (HPA) or a guest physical address (GPA) and must
23525 * point to a physically contiguous block of memory.
23527 uint64_t resp_addr;
23528 /* Port ID of the port. */
23531 * client_id of the client requesting BUS release.
23532 * A client should not release any other clients BUS.
23534 uint16_t client_id;
23535 uint8_t unused_0[4];
23538 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
23539 struct hwrm_port_phy_mdio_bus_release_output {
23540 /* The specific error status for the command. */
23541 uint16_t error_code;
23542 /* The HWRM command request type. */
23544 /* The sequence ID from the original command. */
23546 /* The length of the response data in number of bytes. */
23549 /* The BUS is released if client_id matches the client_id in request. */
23550 uint16_t clients_id;
23551 uint8_t unused_1[3];
23553 * This field is used in Output records to indicate that the output
23554 * is completely written to RAM. This field should be read as '1'
23555 * to indicate that the output has been completely written.
23556 * When writing a command completion or response to an internal processor,
23557 * the order of writes has to be such that this field is written last.
23562 /************************
23563 * hwrm_port_tx_fir_cfg *
23564 ************************/
23567 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
23568 struct hwrm_port_tx_fir_cfg_input {
23569 /* The HWRM command request type. */
23572 * The completion ring to send the completion event on. This should
23573 * be the NQ ID returned from the `nq_alloc` HWRM command.
23575 uint16_t cmpl_ring;
23577 * The sequence ID is used by the driver for tracking multiple
23578 * commands. This ID is treated as opaque data by the firmware and
23579 * the value is returned in the `hwrm_resp_hdr` upon completion.
23583 * The target ID of the command:
23584 * * 0x0-0xFFF8 - The function ID
23585 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23586 * * 0xFFFD - Reserved for user-space HWRM interface
23589 uint16_t target_id;
23591 * A physical address pointer pointing to a host buffer that the
23592 * command's response data will be written. This can be either a host
23593 * physical address (HPA) or a guest physical address (GPA) and must
23594 * point to a physically contiguous block of memory.
23596 uint64_t resp_addr;
23597 /* Modulation types of TX FIR: NRZ, PAM4. */
23600 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
23602 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
23603 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
23604 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
23605 /* The lane mask of the lane TX FIR will be configured. */
23607 uint8_t unused_0[2];
23608 /* Value1 of TX FIR, required for NRZ or PAM4. */
23609 uint32_t txfir_val_1;
23610 /* Value2 of TX FIR, required for NRZ or PAM4. */
23611 uint32_t txfir_val_2;
23612 /* Value3 of TX FIR, required for PAM4. */
23613 uint32_t txfir_val_3;
23614 /* Value4 of TX FIR, required for PAM4. */
23615 uint32_t txfir_val_4;
23616 uint8_t unused_1[4];
23619 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
23620 struct hwrm_port_tx_fir_cfg_output {
23621 /* The specific error status for the command. */
23622 uint16_t error_code;
23623 /* The HWRM command request type. */
23625 /* The sequence ID from the original command. */
23627 /* The length of the response data in number of bytes. */
23631 * This field is used in Output records to indicate that the output
23632 * is completely written to RAM. This field should be read as '1'
23633 * to indicate that the output has been completely written.
23634 * When writing a command completion or response to an internal processor,
23635 * the order of writes has to be such that this field is written last.
23640 /*************************
23641 * hwrm_port_tx_fir_qcfg *
23642 *************************/
23645 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
23646 struct hwrm_port_tx_fir_qcfg_input {
23647 /* The HWRM command request type. */
23650 * The completion ring to send the completion event on. This should
23651 * be the NQ ID returned from the `nq_alloc` HWRM command.
23653 uint16_t cmpl_ring;
23655 * The sequence ID is used by the driver for tracking multiple
23656 * commands. This ID is treated as opaque data by the firmware and
23657 * the value is returned in the `hwrm_resp_hdr` upon completion.
23661 * The target ID of the command:
23662 * * 0x0-0xFFF8 - The function ID
23663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23664 * * 0xFFFD - Reserved for user-space HWRM interface
23667 uint16_t target_id;
23669 * A physical address pointer pointing to a host buffer that the
23670 * command's response data will be written. This can be either a host
23671 * physical address (HPA) or a guest physical address (GPA) and must
23672 * point to a physically contiguous block of memory.
23674 uint64_t resp_addr;
23675 /* Modulation types of TX FIR: NRZ, PAM4. */
23678 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
23680 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
23681 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
23682 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
23683 /* The ID of the lane TX FIR will be queried. */
23688 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
23689 struct hwrm_port_tx_fir_qcfg_output {
23690 /* The specific error status for the command. */
23691 uint16_t error_code;
23692 /* The HWRM command request type. */
23694 /* The sequence ID from the original command. */
23696 /* The length of the response data in number of bytes. */
23698 /* Value1 of TX FIR, required for NRZ or PAM4. */
23699 uint32_t txfir_val_1;
23700 /* Value2 of TX FIR, required for NRZ or PAM4. */
23701 uint32_t txfir_val_2;
23702 /* Value3 of TX FIR, required for PAM4. */
23703 uint32_t txfir_val_3;
23704 /* Value4 of TX FIR, required for PAM4. */
23705 uint32_t txfir_val_4;
23708 * This field is used in Output records to indicate that the output
23709 * is completely written to RAM. This field should be read as '1'
23710 * to indicate that the output has been completely written.
23711 * When writing a command completion or response to an internal processor,
23712 * the order of writes has to be such that this field is written last.
23717 /***********************
23718 * hwrm_queue_qportcfg *
23719 ***********************/
23722 /* hwrm_queue_qportcfg_input (size:192b/24B) */
23723 struct hwrm_queue_qportcfg_input {
23724 /* The HWRM command request type. */
23727 * The completion ring to send the completion event on. This should
23728 * be the NQ ID returned from the `nq_alloc` HWRM command.
23730 uint16_t cmpl_ring;
23732 * The sequence ID is used by the driver for tracking multiple
23733 * commands. This ID is treated as opaque data by the firmware and
23734 * the value is returned in the `hwrm_resp_hdr` upon completion.
23738 * The target ID of the command:
23739 * * 0x0-0xFFF8 - The function ID
23740 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23741 * * 0xFFFD - Reserved for user-space HWRM interface
23744 uint16_t target_id;
23746 * A physical address pointer pointing to a host buffer that the
23747 * command's response data will be written. This can be either a host
23748 * physical address (HPA) or a guest physical address (GPA) and must
23749 * point to a physically contiguous block of memory.
23751 uint64_t resp_addr;
23754 * Enumeration denoting the RX, TX type of the resource.
23755 * This enumeration is used for resources that are similar for both
23756 * TX and RX paths of the chip.
23758 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
23760 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
23762 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
23763 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
23764 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
23766 * Port ID of port for which the queue configuration is being
23767 * queried. This field is only required when sent by IPC.
23771 * Drivers will set this capability when it can use
23772 * queue_idx_service_profile to map the queues to application.
23774 uint8_t drv_qmap_cap;
23776 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
23778 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
23779 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
23780 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
23784 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
23785 struct hwrm_queue_qportcfg_output {
23786 /* The specific error status for the command. */
23787 uint16_t error_code;
23788 /* The HWRM command request type. */
23790 /* The sequence ID from the original command. */
23792 /* The length of the response data in number of bytes. */
23795 * The maximum number of queues that can be configured on this
23797 * Valid values range from 1 through 8.
23799 uint8_t max_configurable_queues;
23801 * The maximum number of lossless queues that can be configured
23803 * Valid values range from 0 through 8.
23805 uint8_t max_configurable_lossless_queues;
23807 * Bitmask indicating which queues can be configured by the
23808 * hwrm_queue_cfg command.
23810 * Each bit represents a specific queue where bit 0 represents
23811 * queue 0 and bit 7 represents queue 7.
23812 * # A value of 0 indicates that the queue is not configurable
23813 * by the hwrm_queue_cfg command.
23814 * # A value of 1 indicates that the queue is configurable.
23815 * # A hwrm_queue_cfg command shall return error when trying to
23816 * configure a queue not configurable.
23818 uint8_t queue_cfg_allowed;
23819 /* Information about queue configuration. */
23820 uint8_t queue_cfg_info;
23822 * If this flag is set to '1', then the queues are
23823 * configured asymmetrically on TX and RX sides.
23824 * If this flag is set to '0', then the queues are
23825 * configured symmetrically on TX and RX sides. For
23826 * symmetric configuration, the queue configuration
23827 * including queue ids and service profiles on the
23828 * TX side is the same as the corresponding queue
23829 * configuration on the RX side.
23831 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
23834 * Bitmask indicating which queues can be configured by the
23835 * hwrm_queue_pfcenable_cfg command.
23837 * Each bit represents a specific priority where bit 0 represents
23838 * priority 0 and bit 7 represents priority 7.
23839 * # A value of 0 indicates that the priority is not configurable by
23840 * the hwrm_queue_pfcenable_cfg command.
23841 * # A value of 1 indicates that the priority is configurable.
23842 * # A hwrm_queue_pfcenable_cfg command shall return error when
23843 * trying to configure a priority that is not configurable.
23845 uint8_t queue_pfcenable_cfg_allowed;
23847 * Bitmask indicating which queues can be configured by the
23848 * hwrm_queue_pri2cos_cfg command.
23850 * Each bit represents a specific queue where bit 0 represents
23851 * queue 0 and bit 7 represents queue 7.
23852 * # A value of 0 indicates that the queue is not configurable
23853 * by the hwrm_queue_pri2cos_cfg command.
23854 * # A value of 1 indicates that the queue is configurable.
23855 * # A hwrm_queue_pri2cos_cfg command shall return error when
23856 * trying to configure a queue that is not configurable.
23858 uint8_t queue_pri2cos_cfg_allowed;
23860 * Bitmask indicating which queues can be configured by the
23861 * hwrm_queue_pri2cos_cfg command.
23863 * Each bit represents a specific queue where bit 0 represents
23864 * queue 0 and bit 7 represents queue 7.
23865 * # A value of 0 indicates that the queue is not configurable
23866 * by the hwrm_queue_pri2cos_cfg command.
23867 * # A value of 1 indicates that the queue is configurable.
23868 * # A hwrm_queue_pri2cos_cfg command shall return error when
23869 * trying to configure a queue not configurable.
23871 uint8_t queue_cos2bw_cfg_allowed;
23873 * ID of CoS Queue 0.
23876 * # This ID can be used on any subsequent call to an hwrm command
23877 * that takes a queue id.
23878 * # IDs must always be queried by this command before any use
23879 * by the driver or software.
23880 * # The CoS queue index is obtained by applying modulo 10 to the
23881 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
23882 * The CoS queue index is used to reference port statistics for the
23884 * # A value of 0xff indicates that the queue is not available.
23885 * # Available queues may not be in sequential order.
23888 /* This value is applicable to CoS queues only. */
23889 uint8_t queue_id0_service_profile;
23890 /* Lossy (best-effort) */
23891 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
23893 /* Lossless (legacy) */
23894 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
23896 /* Lossless RoCE */
23897 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
23899 /* Lossy RoCE CNP */
23900 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
23903 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
23905 /* Set to 0xFF... (All Fs) if there is no service profile specified */
23906 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
23908 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
23909 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
23911 * ID of CoS Queue 1.
23914 * # This ID can be used on any subsequent call to an hwrm command
23915 * that takes a queue id.
23916 * # IDs must always be queried by this command before any use
23917 * by the driver or software.
23918 * # The CoS queue index is obtained by applying modulo 10 to the
23919 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
23920 * The CoS queue index is used to reference port statistics for the
23922 * # A value of 0xff indicates that the queue is not available.
23923 * # Available queues may not be in sequential order.
23926 /* This value is applicable to CoS queues only. */
23927 uint8_t queue_id1_service_profile;
23928 /* Lossy (best-effort) */
23929 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
23931 /* Lossless (legacy) */
23932 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
23934 /* Lossless RoCE */
23935 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
23937 /* Lossy RoCE CNP */
23938 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
23941 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
23943 /* Set to 0xFF... (All Fs) if there is no service profile specified */
23944 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
23946 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
23947 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
23949 * ID of CoS Queue 2.
23952 * # This ID can be used on any subsequent call to an hwrm command
23953 * that takes a queue id.
23954 * # IDs must always be queried by this command before any use
23955 * by the driver or software.
23956 * # The CoS queue index is obtained by applying modulo 10 to the
23957 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
23958 * The CoS queue index is used to reference port statistics for the
23960 * # A value of 0xff indicates that the queue is not available.
23961 * # Available queues may not be in sequential order.
23964 /* This value is applicable to CoS queues only. */
23965 uint8_t queue_id2_service_profile;
23966 /* Lossy (best-effort) */
23967 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
23969 /* Lossless (legacy) */
23970 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
23972 /* Lossless RoCE */
23973 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
23975 /* Lossy RoCE CNP */
23976 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
23979 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
23981 /* Set to 0xFF... (All Fs) if there is no service profile specified */
23982 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
23984 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
23985 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
23987 * ID of CoS Queue 3.
23990 * # This ID can be used on any subsequent call to an hwrm command
23991 * that takes a queue id.
23992 * # IDs must always be queried by this command before any use
23993 * by the driver or software.
23994 * # The CoS queue index is obtained by applying modulo 10 to the
23995 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
23996 * The CoS queue index is used to reference port statistics for the
23998 * # A value of 0xff indicates that the queue is not available.
23999 * # Available queues may not be in sequential order.
24002 /* This value is applicable to CoS queues only. */
24003 uint8_t queue_id3_service_profile;
24004 /* Lossy (best-effort) */
24005 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
24007 /* Lossless (legacy) */
24008 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
24010 /* Lossless RoCE */
24011 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
24013 /* Lossy RoCE CNP */
24014 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
24017 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
24019 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24020 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
24022 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
24023 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
24025 * ID of CoS Queue 4.
24028 * # This ID can be used on any subsequent call to an hwrm command
24029 * that takes a queue id.
24030 * # IDs must always be queried by this command before any use
24031 * by the driver or software.
24032 * # The CoS queue index is obtained by applying modulo 10 to the
24033 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
24034 * The CoS queue index is used to reference port statistics for the
24036 * # A value of 0xff indicates that the queue is not available.
24037 * # Available queues may not be in sequential order.
24040 /* This value is applicable to CoS queues only. */
24041 uint8_t queue_id4_service_profile;
24042 /* Lossy (best-effort) */
24043 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
24045 /* Lossless (legacy) */
24046 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
24048 /* Lossless RoCE */
24049 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
24051 /* Lossy RoCE CNP */
24052 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
24055 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
24057 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24058 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
24060 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
24061 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
24063 * ID of CoS Queue 5.
24066 * # This ID can be used on any subsequent call to an hwrm command
24067 * that takes a queue id.
24068 * # IDs must always be queried by this command before any use
24069 * by the driver or software.
24070 * # The CoS queue index is obtained by applying modulo 10 to the
24071 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
24072 * The CoS queue index is used to reference port statistics for the
24074 * # A value of 0xff indicates that the queue is not available.
24075 * # Available queues may not be in sequential order.
24078 /* This value is applicable to CoS queues only. */
24079 uint8_t queue_id5_service_profile;
24080 /* Lossy (best-effort) */
24081 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
24083 /* Lossless (legacy) */
24084 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
24086 /* Lossless RoCE */
24087 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
24089 /* Lossy RoCE CNP */
24090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
24093 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
24095 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24096 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
24098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
24099 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
24101 * ID of CoS Queue 6.
24104 * # This ID can be used on any subsequent call to an hwrm command
24105 * that takes a queue id.
24106 * # IDs must always be queried by this command before any use
24107 * by the driver or software.
24108 * # The CoS queue index is obtained by applying modulo 10 to the
24109 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
24110 * The CoS queue index is used to reference port statistics for the
24112 * # A value of 0xff indicates that the queue is not available.
24113 * # Available queues may not be in sequential order.
24116 /* This value is applicable to CoS queues only. */
24117 uint8_t queue_id6_service_profile;
24118 /* Lossy (best-effort) */
24119 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
24121 /* Lossless (legacy) */
24122 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
24124 /* Lossless RoCE */
24125 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
24127 /* Lossy RoCE CNP */
24128 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
24131 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
24133 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24134 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
24136 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
24137 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
24139 * ID of CoS Queue 7.
24142 * # This ID can be used on any subsequent call to an hwrm command
24143 * that takes a queue id.
24144 * # IDs must always be queried by this command before any use
24145 * by the driver or software.
24146 * # The CoS queue index is obtained by applying modulo 10 to the
24147 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
24148 * The CoS queue index is used to reference port statistics for the
24150 * # A value of 0xff indicates that the queue is not available.
24151 * # Available queues may not be in sequential order.
24154 /* This value is applicable to CoS queues only. */
24155 uint8_t queue_id7_service_profile;
24156 /* Lossy (best-effort) */
24157 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
24159 /* Lossless (legacy) */
24160 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
24162 /* Lossless RoCE */
24163 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
24165 /* Lossy RoCE CNP */
24166 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
24169 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
24171 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24172 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
24174 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
24175 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
24178 * Up to 16 bytes of null padded ASCII string describing this queue.
24179 * The queue name includes a CoS queue index and, in some cases, text
24180 * that distinguishes the queue from other queues in the group.
24182 char qid0_name[16];
24183 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24184 char qid1_name[16];
24185 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24186 char qid2_name[16];
24187 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24188 char qid3_name[16];
24189 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24190 char qid4_name[16];
24191 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24192 char qid5_name[16];
24193 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24194 char qid6_name[16];
24195 /* Up to 16 bytes of null padded ASCII string describing this queue. */
24196 char qid7_name[16];
24197 uint8_t unused_1[7];
24199 * This field is used in Output records to indicate that the output
24200 * is completely written to RAM. This field should be read as '1'
24201 * to indicate that the output has been completely written.
24202 * When writing a command completion or response to an internal processor,
24203 * the order of writes has to be such that this field is written last.
24208 /*******************
24209 * hwrm_queue_qcfg *
24210 *******************/
24213 /* hwrm_queue_qcfg_input (size:192b/24B) */
24214 struct hwrm_queue_qcfg_input {
24215 /* The HWRM command request type. */
24218 * The completion ring to send the completion event on. This should
24219 * be the NQ ID returned from the `nq_alloc` HWRM command.
24221 uint16_t cmpl_ring;
24223 * The sequence ID is used by the driver for tracking multiple
24224 * commands. This ID is treated as opaque data by the firmware and
24225 * the value is returned in the `hwrm_resp_hdr` upon completion.
24229 * The target ID of the command:
24230 * * 0x0-0xFFF8 - The function ID
24231 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24232 * * 0xFFFD - Reserved for user-space HWRM interface
24235 uint16_t target_id;
24237 * A physical address pointer pointing to a host buffer that the
24238 * command's response data will be written. This can be either a host
24239 * physical address (HPA) or a guest physical address (GPA) and must
24240 * point to a physically contiguous block of memory.
24242 uint64_t resp_addr;
24245 * Enumeration denoting the RX, TX type of the resource.
24246 * This enumeration is used for resources that are similar for both
24247 * TX and RX paths of the chip.
24249 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
24251 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24253 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24254 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
24255 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
24256 /* Queue ID of the queue. */
24260 /* hwrm_queue_qcfg_output (size:128b/16B) */
24261 struct hwrm_queue_qcfg_output {
24262 /* The specific error status for the command. */
24263 uint16_t error_code;
24264 /* The HWRM command request type. */
24266 /* The sequence ID from the original command. */
24268 /* The length of the response data in number of bytes. */
24271 * This value is the estimate packet length used in the
24274 uint32_t queue_len;
24275 /* This value is applicable to CoS queues only. */
24276 uint8_t service_profile;
24277 /* Lossy (best-effort) */
24278 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
24280 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
24281 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24282 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
24283 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
24284 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
24285 /* Information about queue configuration. */
24286 uint8_t queue_cfg_info;
24288 * If this flag is set to '1', then the queue is
24289 * configured asymmetrically on TX and RX sides.
24290 * If this flag is set to '0', then this queue is
24291 * configured symmetrically on TX and RX sides.
24293 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
24297 * This field is used in Output records to indicate that the output
24298 * is completely written to RAM. This field should be read as '1'
24299 * to indicate that the output has been completely written.
24300 * When writing a command completion or response to an internal processor,
24301 * the order of writes has to be such that this field is written last.
24306 /******************
24308 ******************/
24311 /* hwrm_queue_cfg_input (size:320b/40B) */
24312 struct hwrm_queue_cfg_input {
24313 /* The HWRM command request type. */
24316 * The completion ring to send the completion event on. This should
24317 * be the NQ ID returned from the `nq_alloc` HWRM command.
24319 uint16_t cmpl_ring;
24321 * The sequence ID is used by the driver for tracking multiple
24322 * commands. This ID is treated as opaque data by the firmware and
24323 * the value is returned in the `hwrm_resp_hdr` upon completion.
24327 * The target ID of the command:
24328 * * 0x0-0xFFF8 - The function ID
24329 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24330 * * 0xFFFD - Reserved for user-space HWRM interface
24333 uint16_t target_id;
24335 * A physical address pointer pointing to a host buffer that the
24336 * command's response data will be written. This can be either a host
24337 * physical address (HPA) or a guest physical address (GPA) and must
24338 * point to a physically contiguous block of memory.
24340 uint64_t resp_addr;
24343 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
24344 * This enumeration is used for resources that are similar for both
24345 * TX and RX paths of the chip.
24347 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
24348 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
24350 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24352 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24353 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
24354 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
24355 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
24356 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
24359 * This bit must be '1' for the dflt_len field to be
24362 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
24364 * This bit must be '1' for the service_profile field to be
24367 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
24368 /* Queue ID of queue that is to be configured by this function. */
24371 * This value is a the estimate packet length used in the
24373 * Set to 0xFF... (All Fs) to not adjust this value.
24376 /* This value is applicable to CoS queues only. */
24377 uint8_t service_profile;
24378 /* Lossy (best-effort) */
24379 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
24381 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
24382 /* Set to 0xFF... (All Fs) if there is no service profile specified */
24383 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
24384 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
24385 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
24386 uint8_t unused_0[7];
24389 /* hwrm_queue_cfg_output (size:128b/16B) */
24390 struct hwrm_queue_cfg_output {
24391 /* The specific error status for the command. */
24392 uint16_t error_code;
24393 /* The HWRM command request type. */
24395 /* The sequence ID from the original command. */
24397 /* The length of the response data in number of bytes. */
24399 uint8_t unused_0[7];
24401 * This field is used in Output records to indicate that the output
24402 * is completely written to RAM. This field should be read as '1'
24403 * to indicate that the output has been completely written.
24404 * When writing a command completion or response to an internal processor,
24405 * the order of writes has to be such that this field is written last.
24410 /*****************************
24411 * hwrm_queue_pfcenable_qcfg *
24412 *****************************/
24415 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
24416 struct hwrm_queue_pfcenable_qcfg_input {
24417 /* The HWRM command request type. */
24420 * The completion ring to send the completion event on. This should
24421 * be the NQ ID returned from the `nq_alloc` HWRM command.
24423 uint16_t cmpl_ring;
24425 * The sequence ID is used by the driver for tracking multiple
24426 * commands. This ID is treated as opaque data by the firmware and
24427 * the value is returned in the `hwrm_resp_hdr` upon completion.
24431 * The target ID of the command:
24432 * * 0x0-0xFFF8 - The function ID
24433 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24434 * * 0xFFFD - Reserved for user-space HWRM interface
24437 uint16_t target_id;
24439 * A physical address pointer pointing to a host buffer that the
24440 * command's response data will be written. This can be either a host
24441 * physical address (HPA) or a guest physical address (GPA) and must
24442 * point to a physically contiguous block of memory.
24444 uint64_t resp_addr;
24446 * Port ID of port for which the table is being configured.
24447 * The HWRM needs to check whether this function is allowed
24448 * to configure pri2cos mapping on this port.
24451 uint8_t unused_0[6];
24454 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
24455 struct hwrm_queue_pfcenable_qcfg_output {
24456 /* The specific error status for the command. */
24457 uint16_t error_code;
24458 /* The HWRM command request type. */
24460 /* The sequence ID from the original command. */
24462 /* The length of the response data in number of bytes. */
24465 /* If set to 1, then PFC is enabled on PRI 0. */
24466 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
24468 /* If set to 1, then PFC is enabled on PRI 1. */
24469 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
24471 /* If set to 1, then PFC is enabled on PRI 2. */
24472 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
24474 /* If set to 1, then PFC is enabled on PRI 3. */
24475 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
24477 /* If set to 1, then PFC is enabled on PRI 4. */
24478 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
24480 /* If set to 1, then PFC is enabled on PRI 5. */
24481 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
24483 /* If set to 1, then PFC is enabled on PRI 6. */
24484 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
24486 /* If set to 1, then PFC is enabled on PRI 7. */
24487 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
24489 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
24490 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
24492 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
24493 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
24495 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
24496 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
24498 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
24499 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
24501 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
24502 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
24504 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
24505 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
24507 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
24508 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
24510 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
24511 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
24513 uint8_t unused_0[3];
24515 * This field is used in Output records to indicate that the output
24516 * is completely written to RAM. This field should be read as '1'
24517 * to indicate that the output has been completely written.
24518 * When writing a command completion or response to an internal processor,
24519 * the order of writes has to be such that this field is written last.
24524 /****************************
24525 * hwrm_queue_pfcenable_cfg *
24526 ****************************/
24529 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
24530 struct hwrm_queue_pfcenable_cfg_input {
24531 /* The HWRM command request type. */
24534 * The completion ring to send the completion event on. This should
24535 * be the NQ ID returned from the `nq_alloc` HWRM command.
24537 uint16_t cmpl_ring;
24539 * The sequence ID is used by the driver for tracking multiple
24540 * commands. This ID is treated as opaque data by the firmware and
24541 * the value is returned in the `hwrm_resp_hdr` upon completion.
24545 * The target ID of the command:
24546 * * 0x0-0xFFF8 - The function ID
24547 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24548 * * 0xFFFD - Reserved for user-space HWRM interface
24551 uint16_t target_id;
24553 * A physical address pointer pointing to a host buffer that the
24554 * command's response data will be written. This can be either a host
24555 * physical address (HPA) or a guest physical address (GPA) and must
24556 * point to a physically contiguous block of memory.
24558 uint64_t resp_addr;
24560 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
24561 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
24563 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
24564 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
24566 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
24567 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
24569 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
24570 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
24572 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
24573 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
24575 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
24576 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
24578 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
24579 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
24581 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
24582 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
24584 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
24585 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
24587 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
24588 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
24590 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
24591 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
24593 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
24594 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
24596 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
24597 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
24599 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
24600 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
24602 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
24603 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
24605 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
24606 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
24609 * Port ID of port for which the table is being configured.
24610 * The HWRM needs to check whether this function is allowed
24611 * to configure pri2cos mapping on this port.
24614 uint8_t unused_0[2];
24617 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
24618 struct hwrm_queue_pfcenable_cfg_output {
24619 /* The specific error status for the command. */
24620 uint16_t error_code;
24621 /* The HWRM command request type. */
24623 /* The sequence ID from the original command. */
24625 /* The length of the response data in number of bytes. */
24627 uint8_t unused_0[7];
24629 * This field is used in Output records to indicate that the output
24630 * is completely written to RAM. This field should be read as '1'
24631 * to indicate that the output has been completely written.
24632 * When writing a command completion or response to an internal processor,
24633 * the order of writes has to be such that this field is written last.
24638 /***************************
24639 * hwrm_queue_pri2cos_qcfg *
24640 ***************************/
24643 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
24644 struct hwrm_queue_pri2cos_qcfg_input {
24645 /* The HWRM command request type. */
24648 * The completion ring to send the completion event on. This should
24649 * be the NQ ID returned from the `nq_alloc` HWRM command.
24651 uint16_t cmpl_ring;
24653 * The sequence ID is used by the driver for tracking multiple
24654 * commands. This ID is treated as opaque data by the firmware and
24655 * the value is returned in the `hwrm_resp_hdr` upon completion.
24659 * The target ID of the command:
24660 * * 0x0-0xFFF8 - The function ID
24661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24662 * * 0xFFFD - Reserved for user-space HWRM interface
24665 uint16_t target_id;
24667 * A physical address pointer pointing to a host buffer that the
24668 * command's response data will be written. This can be either a host
24669 * physical address (HPA) or a guest physical address (GPA) and must
24670 * point to a physically contiguous block of memory.
24672 uint64_t resp_addr;
24675 * Enumeration denoting the RX, TX type of the resource.
24676 * This enumeration is used for resources that are similar for both
24677 * TX and RX paths of the chip.
24679 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
24681 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24683 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24684 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
24685 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
24687 * When this bit is set to '0', the query is
24688 * for PRI from tunnel headers.
24689 * When this bit is set to '1', the query is
24690 * for PRI from inner packet headers.
24692 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
24694 * Port ID of port for which the table is being configured.
24695 * The HWRM needs to check whether this function is allowed
24696 * to configure pri2cos mapping on this port.
24699 uint8_t unused_0[3];
24702 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
24703 struct hwrm_queue_pri2cos_qcfg_output {
24704 /* The specific error status for the command. */
24705 uint16_t error_code;
24706 /* The HWRM command request type. */
24708 /* The sequence ID from the original command. */
24710 /* The length of the response data in number of bytes. */
24713 * CoS Queue assigned to priority 0. This value can only
24714 * be changed before traffic has started.
24715 * A value of 0xff indicates that no CoS queue is assigned to the
24716 * specified priority.
24718 uint8_t pri0_cos_queue_id;
24720 * CoS Queue assigned to priority 1. This value can only
24721 * be changed before traffic has started.
24722 * A value of 0xff indicates that no CoS queue is assigned to the
24723 * specified priority.
24725 uint8_t pri1_cos_queue_id;
24727 * CoS Queue assigned to priority 2. This value can only
24728 * be changed before traffic has started.
24729 * A value of 0xff indicates that no CoS queue is assigned to the
24730 * specified priority.
24732 uint8_t pri2_cos_queue_id;
24734 * CoS Queue assigned to priority 3. This value can only
24735 * be changed before traffic has started.
24736 * A value of 0xff indicates that no CoS queue is assigned to the
24737 * specified priority.
24739 uint8_t pri3_cos_queue_id;
24741 * CoS Queue assigned to priority 4. This value can only
24742 * be changed before traffic has started.
24743 * A value of 0xff indicates that no CoS queue is assigned to the
24744 * specified priority.
24746 uint8_t pri4_cos_queue_id;
24748 * CoS Queue assigned to priority 5. This value can only
24749 * be changed before traffic has started.
24750 * A value of 0xff indicates that no CoS queue is assigned to the
24751 * specified priority.
24753 uint8_t pri5_cos_queue_id;
24755 * CoS Queue assigned to priority 6. This value can only
24756 * be changed before traffic has started.
24757 * A value of 0xff indicates that no CoS queue is assigned to the
24758 * specified priority.
24760 uint8_t pri6_cos_queue_id;
24762 * CoS Queue assigned to priority 7. This value can only
24763 * be changed before traffic has started.
24764 * A value of 0xff indicates that no CoS queue is assigned to the
24765 * specified priority.
24767 uint8_t pri7_cos_queue_id;
24768 /* Information about queue configuration. */
24769 uint8_t queue_cfg_info;
24771 * If this flag is set to '1', then the PRI to CoS
24772 * configuration is asymmetric on TX and RX sides.
24773 * If this flag is set to '0', then PRI to CoS configuration
24774 * is symmetric on TX and RX sides.
24776 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
24778 uint8_t unused_0[6];
24780 * This field is used in Output records to indicate that the output
24781 * is completely written to RAM. This field should be read as '1'
24782 * to indicate that the output has been completely written.
24783 * When writing a command completion or response to an internal processor,
24784 * the order of writes has to be such that this field is written last.
24789 /**************************
24790 * hwrm_queue_pri2cos_cfg *
24791 **************************/
24794 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
24795 struct hwrm_queue_pri2cos_cfg_input {
24796 /* The HWRM command request type. */
24799 * The completion ring to send the completion event on. This should
24800 * be the NQ ID returned from the `nq_alloc` HWRM command.
24802 uint16_t cmpl_ring;
24804 * The sequence ID is used by the driver for tracking multiple
24805 * commands. This ID is treated as opaque data by the firmware and
24806 * the value is returned in the `hwrm_resp_hdr` upon completion.
24810 * The target ID of the command:
24811 * * 0x0-0xFFF8 - The function ID
24812 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24813 * * 0xFFFD - Reserved for user-space HWRM interface
24816 uint16_t target_id;
24818 * A physical address pointer pointing to a host buffer that the
24819 * command's response data will be written. This can be either a host
24820 * physical address (HPA) or a guest physical address (GPA) and must
24821 * point to a physically contiguous block of memory.
24823 uint64_t resp_addr;
24826 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
24827 * This enumeration is used for resources that are similar for both
24828 * TX and RX paths of the chip.
24830 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
24831 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
24833 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24835 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24836 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
24837 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
24838 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
24839 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
24841 * When this bit is set to '0', the mapping is requested
24842 * for PRI from tunnel headers.
24843 * When this bit is set to '1', the mapping is requested
24844 * for PRI from inner packet headers.
24846 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
24849 * This bit must be '1' for the pri0_cos_queue_id field to be
24852 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
24855 * This bit must be '1' for the pri1_cos_queue_id field to be
24858 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
24861 * This bit must be '1' for the pri2_cos_queue_id field to be
24864 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
24867 * This bit must be '1' for the pri3_cos_queue_id field to be
24870 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
24873 * This bit must be '1' for the pri4_cos_queue_id field to be
24876 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
24879 * This bit must be '1' for the pri5_cos_queue_id field to be
24882 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
24885 * This bit must be '1' for the pri6_cos_queue_id field to be
24888 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
24891 * This bit must be '1' for the pri7_cos_queue_id field to be
24894 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
24897 * Port ID of port for which the table is being configured.
24898 * The HWRM needs to check whether this function is allowed
24899 * to configure pri2cos mapping on this port.
24903 * CoS Queue assigned to priority 0. This value can only
24904 * be changed before traffic has started.
24906 uint8_t pri0_cos_queue_id;
24908 * CoS Queue assigned to priority 1. This value can only
24909 * be changed before traffic has started.
24911 uint8_t pri1_cos_queue_id;
24913 * CoS Queue assigned to priority 2 This value can only
24914 * be changed before traffic has started.
24916 uint8_t pri2_cos_queue_id;
24918 * CoS Queue assigned to priority 3. This value can only
24919 * be changed before traffic has started.
24921 uint8_t pri3_cos_queue_id;
24923 * CoS Queue assigned to priority 4. This value can only
24924 * be changed before traffic has started.
24926 uint8_t pri4_cos_queue_id;
24928 * CoS Queue assigned to priority 5. This value can only
24929 * be changed before traffic has started.
24931 uint8_t pri5_cos_queue_id;
24933 * CoS Queue assigned to priority 6. This value can only
24934 * be changed before traffic has started.
24936 uint8_t pri6_cos_queue_id;
24938 * CoS Queue assigned to priority 7. This value can only
24939 * be changed before traffic has started.
24941 uint8_t pri7_cos_queue_id;
24942 uint8_t unused_0[7];
24945 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
24946 struct hwrm_queue_pri2cos_cfg_output {
24947 /* The specific error status for the command. */
24948 uint16_t error_code;
24949 /* The HWRM command request type. */
24951 /* The sequence ID from the original command. */
24953 /* The length of the response data in number of bytes. */
24955 uint8_t unused_0[7];
24957 * This field is used in Output records to indicate that the output
24958 * is completely written to RAM. This field should be read as '1'
24959 * to indicate that the output has been completely written.
24960 * When writing a command completion or response to an internal processor,
24961 * the order of writes has to be such that this field is written last.
24966 /**************************
24967 * hwrm_queue_cos2bw_qcfg *
24968 **************************/
24971 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
24972 struct hwrm_queue_cos2bw_qcfg_input {
24973 /* The HWRM command request type. */
24976 * The completion ring to send the completion event on. This should
24977 * be the NQ ID returned from the `nq_alloc` HWRM command.
24979 uint16_t cmpl_ring;
24981 * The sequence ID is used by the driver for tracking multiple
24982 * commands. This ID is treated as opaque data by the firmware and
24983 * the value is returned in the `hwrm_resp_hdr` upon completion.
24987 * The target ID of the command:
24988 * * 0x0-0xFFF8 - The function ID
24989 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24990 * * 0xFFFD - Reserved for user-space HWRM interface
24993 uint16_t target_id;
24995 * A physical address pointer pointing to a host buffer that the
24996 * command's response data will be written. This can be either a host
24997 * physical address (HPA) or a guest physical address (GPA) and must
24998 * point to a physically contiguous block of memory.
25000 uint64_t resp_addr;
25002 * Port ID of port for which the table is being configured.
25003 * The HWRM needs to check whether this function is allowed
25004 * to configure TC BW assignment on this port.
25007 uint8_t unused_0[6];
25010 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
25011 struct hwrm_queue_cos2bw_qcfg_output {
25012 /* The specific error status for the command. */
25013 uint16_t error_code;
25014 /* The HWRM command request type. */
25016 /* The sequence ID from the original command. */
25018 /* The length of the response data in number of bytes. */
25020 /* ID of CoS Queue 0. */
25025 * Minimum BW allocated to CoS Queue.
25026 * The HWRM will translate this value into byte counter and
25027 * time interval used for this COS inside the device.
25029 uint32_t queue_id0_min_bw;
25030 /* The bandwidth value. */
25031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
25032 UINT32_C(0xfffffff)
25033 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
25035 /* The granularity of the value (bits or bytes). */
25036 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
25037 UINT32_C(0x10000000)
25038 /* Value is in bits. */
25039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
25040 (UINT32_C(0x0) << 28)
25041 /* Value is in bytes. */
25042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
25043 (UINT32_C(0x1) << 28)
25044 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
25045 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
25046 /* bw_value_unit is 3 b */
25047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
25048 UINT32_C(0xe0000000)
25049 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
25051 /* Value is in Mb or MB (base 10). */
25052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
25053 (UINT32_C(0x0) << 29)
25054 /* Value is in Kb or KB (base 10). */
25055 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
25056 (UINT32_C(0x2) << 29)
25057 /* Value is in bits or bytes. */
25058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
25059 (UINT32_C(0x4) << 29)
25060 /* Value is in Gb or GB (base 10). */
25061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
25062 (UINT32_C(0x6) << 29)
25063 /* Value is in 1/100th of a percentage of total bandwidth. */
25064 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25065 (UINT32_C(0x1) << 29)
25067 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
25068 (UINT32_C(0x7) << 29)
25069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
25070 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
25072 * Maximum BW allocated to CoS Queue.
25073 * The HWRM will translate this value into byte counter and
25074 * time interval used for this COS inside the device.
25076 uint32_t queue_id0_max_bw;
25077 /* The bandwidth value. */
25078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
25079 UINT32_C(0xfffffff)
25080 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
25082 /* The granularity of the value (bits or bytes). */
25083 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
25084 UINT32_C(0x10000000)
25085 /* Value is in bits. */
25086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
25087 (UINT32_C(0x0) << 28)
25088 /* Value is in bytes. */
25089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
25090 (UINT32_C(0x1) << 28)
25091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
25092 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
25093 /* bw_value_unit is 3 b */
25094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
25095 UINT32_C(0xe0000000)
25096 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
25098 /* Value is in Mb or MB (base 10). */
25099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
25100 (UINT32_C(0x0) << 29)
25101 /* Value is in Kb or KB (base 10). */
25102 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
25103 (UINT32_C(0x2) << 29)
25104 /* Value is in bits or bytes. */
25105 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
25106 (UINT32_C(0x4) << 29)
25107 /* Value is in Gb or GB (base 10). */
25108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
25109 (UINT32_C(0x6) << 29)
25110 /* Value is in 1/100th of a percentage of total bandwidth. */
25111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25112 (UINT32_C(0x1) << 29)
25114 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
25115 (UINT32_C(0x7) << 29)
25116 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
25117 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
25118 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25119 uint8_t queue_id0_tsa_assign;
25120 /* Strict Priority */
25121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
25123 /* Enhanced Transmission Selection */
25124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
25127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
25130 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
25133 * Priority level for strict priority. Valid only when the
25134 * tsa_assign is 0 - Strict Priority (SP)
25135 * 0..7 - Valid values.
25136 * 8..255 - Reserved.
25138 uint8_t queue_id0_pri_lvl;
25140 * Weight used to allocate remaining BW for this COS after
25141 * servicing guaranteed bandwidths for all COS.
25143 uint8_t queue_id0_bw_weight;
25144 /* ID of CoS Queue 1. */
25147 * Minimum BW allocated to CoS Queue.
25148 * The HWRM will translate this value into byte counter and
25149 * time interval used for this COS inside the device.
25151 uint32_t queue_id1_min_bw;
25152 /* The bandwidth value. */
25153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
25154 UINT32_C(0xfffffff)
25155 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
25157 /* The granularity of the value (bits or bytes). */
25158 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
25159 UINT32_C(0x10000000)
25160 /* Value is in bits. */
25161 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
25162 (UINT32_C(0x0) << 28)
25163 /* Value is in bytes. */
25164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
25165 (UINT32_C(0x1) << 28)
25166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
25167 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
25168 /* bw_value_unit is 3 b */
25169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
25170 UINT32_C(0xe0000000)
25171 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
25173 /* Value is in Mb or MB (base 10). */
25174 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
25175 (UINT32_C(0x0) << 29)
25176 /* Value is in Kb or KB (base 10). */
25177 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
25178 (UINT32_C(0x2) << 29)
25179 /* Value is in bits or bytes. */
25180 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
25181 (UINT32_C(0x4) << 29)
25182 /* Value is in Gb or GB (base 10). */
25183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
25184 (UINT32_C(0x6) << 29)
25185 /* Value is in 1/100th of a percentage of total bandwidth. */
25186 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25187 (UINT32_C(0x1) << 29)
25189 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
25190 (UINT32_C(0x7) << 29)
25191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
25192 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
25194 * Maximum BW allocated to CoS queue.
25195 * The HWRM will translate this value into byte counter and
25196 * time interval used for this COS inside the device.
25198 uint32_t queue_id1_max_bw;
25199 /* The bandwidth value. */
25200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
25201 UINT32_C(0xfffffff)
25202 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
25204 /* The granularity of the value (bits or bytes). */
25205 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
25206 UINT32_C(0x10000000)
25207 /* Value is in bits. */
25208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
25209 (UINT32_C(0x0) << 28)
25210 /* Value is in bytes. */
25211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
25212 (UINT32_C(0x1) << 28)
25213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
25214 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
25215 /* bw_value_unit is 3 b */
25216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
25217 UINT32_C(0xe0000000)
25218 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
25220 /* Value is in Mb or MB (base 10). */
25221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
25222 (UINT32_C(0x0) << 29)
25223 /* Value is in Kb or KB (base 10). */
25224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
25225 (UINT32_C(0x2) << 29)
25226 /* Value is in bits or bytes. */
25227 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
25228 (UINT32_C(0x4) << 29)
25229 /* Value is in Gb or GB (base 10). */
25230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
25231 (UINT32_C(0x6) << 29)
25232 /* Value is in 1/100th of a percentage of total bandwidth. */
25233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25234 (UINT32_C(0x1) << 29)
25236 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
25237 (UINT32_C(0x7) << 29)
25238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
25239 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
25240 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25241 uint8_t queue_id1_tsa_assign;
25242 /* Strict Priority */
25243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
25245 /* Enhanced Transmission Selection */
25246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
25249 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
25252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
25255 * Priority level for strict priority. Valid only when the
25256 * tsa_assign is 0 - Strict Priority (SP)
25257 * 0..7 - Valid values.
25258 * 8..255 - Reserved.
25260 uint8_t queue_id1_pri_lvl;
25262 * Weight used to allocate remaining BW for this COS after
25263 * servicing guaranteed bandwidths for all COS.
25265 uint8_t queue_id1_bw_weight;
25266 /* ID of CoS Queue 2. */
25269 * Minimum BW allocated to CoS Queue.
25270 * The HWRM will translate this value into byte counter and
25271 * time interval used for this COS inside the device.
25273 uint32_t queue_id2_min_bw;
25274 /* The bandwidth value. */
25275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
25276 UINT32_C(0xfffffff)
25277 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
25279 /* The granularity of the value (bits or bytes). */
25280 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
25281 UINT32_C(0x10000000)
25282 /* Value is in bits. */
25283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
25284 (UINT32_C(0x0) << 28)
25285 /* Value is in bytes. */
25286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
25287 (UINT32_C(0x1) << 28)
25288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
25289 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
25290 /* bw_value_unit is 3 b */
25291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
25292 UINT32_C(0xe0000000)
25293 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
25295 /* Value is in Mb or MB (base 10). */
25296 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
25297 (UINT32_C(0x0) << 29)
25298 /* Value is in Kb or KB (base 10). */
25299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
25300 (UINT32_C(0x2) << 29)
25301 /* Value is in bits or bytes. */
25302 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
25303 (UINT32_C(0x4) << 29)
25304 /* Value is in Gb or GB (base 10). */
25305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
25306 (UINT32_C(0x6) << 29)
25307 /* Value is in 1/100th of a percentage of total bandwidth. */
25308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25309 (UINT32_C(0x1) << 29)
25311 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
25312 (UINT32_C(0x7) << 29)
25313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
25314 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
25316 * Maximum BW allocated to CoS queue.
25317 * The HWRM will translate this value into byte counter and
25318 * time interval used for this COS inside the device.
25320 uint32_t queue_id2_max_bw;
25321 /* The bandwidth value. */
25322 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
25323 UINT32_C(0xfffffff)
25324 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
25326 /* The granularity of the value (bits or bytes). */
25327 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
25328 UINT32_C(0x10000000)
25329 /* Value is in bits. */
25330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
25331 (UINT32_C(0x0) << 28)
25332 /* Value is in bytes. */
25333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
25334 (UINT32_C(0x1) << 28)
25335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
25336 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
25337 /* bw_value_unit is 3 b */
25338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
25339 UINT32_C(0xe0000000)
25340 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
25342 /* Value is in Mb or MB (base 10). */
25343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
25344 (UINT32_C(0x0) << 29)
25345 /* Value is in Kb or KB (base 10). */
25346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
25347 (UINT32_C(0x2) << 29)
25348 /* Value is in bits or bytes. */
25349 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
25350 (UINT32_C(0x4) << 29)
25351 /* Value is in Gb or GB (base 10). */
25352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
25353 (UINT32_C(0x6) << 29)
25354 /* Value is in 1/100th of a percentage of total bandwidth. */
25355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25356 (UINT32_C(0x1) << 29)
25358 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
25359 (UINT32_C(0x7) << 29)
25360 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
25361 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
25362 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25363 uint8_t queue_id2_tsa_assign;
25364 /* Strict Priority */
25365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
25367 /* Enhanced Transmission Selection */
25368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
25371 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
25374 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
25377 * Priority level for strict priority. Valid only when the
25378 * tsa_assign is 0 - Strict Priority (SP)
25379 * 0..7 - Valid values.
25380 * 8..255 - Reserved.
25382 uint8_t queue_id2_pri_lvl;
25384 * Weight used to allocate remaining BW for this COS after
25385 * servicing guaranteed bandwidths for all COS.
25387 uint8_t queue_id2_bw_weight;
25388 /* ID of CoS Queue 3. */
25391 * Minimum BW allocated to CoS Queue.
25392 * The HWRM will translate this value into byte counter and
25393 * time interval used for this COS inside the device.
25395 uint32_t queue_id3_min_bw;
25396 /* The bandwidth value. */
25397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
25398 UINT32_C(0xfffffff)
25399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
25401 /* The granularity of the value (bits or bytes). */
25402 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
25403 UINT32_C(0x10000000)
25404 /* Value is in bits. */
25405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
25406 (UINT32_C(0x0) << 28)
25407 /* Value is in bytes. */
25408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
25409 (UINT32_C(0x1) << 28)
25410 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
25411 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
25412 /* bw_value_unit is 3 b */
25413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
25414 UINT32_C(0xe0000000)
25415 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
25417 /* Value is in Mb or MB (base 10). */
25418 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
25419 (UINT32_C(0x0) << 29)
25420 /* Value is in Kb or KB (base 10). */
25421 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
25422 (UINT32_C(0x2) << 29)
25423 /* Value is in bits or bytes. */
25424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
25425 (UINT32_C(0x4) << 29)
25426 /* Value is in Gb or GB (base 10). */
25427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
25428 (UINT32_C(0x6) << 29)
25429 /* Value is in 1/100th of a percentage of total bandwidth. */
25430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25431 (UINT32_C(0x1) << 29)
25433 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
25434 (UINT32_C(0x7) << 29)
25435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
25436 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
25438 * Maximum BW allocated to CoS queue.
25439 * The HWRM will translate this value into byte counter and
25440 * time interval used for this COS inside the device.
25442 uint32_t queue_id3_max_bw;
25443 /* The bandwidth value. */
25444 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
25445 UINT32_C(0xfffffff)
25446 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
25448 /* The granularity of the value (bits or bytes). */
25449 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
25450 UINT32_C(0x10000000)
25451 /* Value is in bits. */
25452 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
25453 (UINT32_C(0x0) << 28)
25454 /* Value is in bytes. */
25455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
25456 (UINT32_C(0x1) << 28)
25457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
25458 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
25459 /* bw_value_unit is 3 b */
25460 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
25461 UINT32_C(0xe0000000)
25462 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
25464 /* Value is in Mb or MB (base 10). */
25465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
25466 (UINT32_C(0x0) << 29)
25467 /* Value is in Kb or KB (base 10). */
25468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
25469 (UINT32_C(0x2) << 29)
25470 /* Value is in bits or bytes. */
25471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
25472 (UINT32_C(0x4) << 29)
25473 /* Value is in Gb or GB (base 10). */
25474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
25475 (UINT32_C(0x6) << 29)
25476 /* Value is in 1/100th of a percentage of total bandwidth. */
25477 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25478 (UINT32_C(0x1) << 29)
25480 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
25481 (UINT32_C(0x7) << 29)
25482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
25483 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
25484 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25485 uint8_t queue_id3_tsa_assign;
25486 /* Strict Priority */
25487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
25489 /* Enhanced Transmission Selection */
25490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
25493 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
25496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
25499 * Priority level for strict priority. Valid only when the
25500 * tsa_assign is 0 - Strict Priority (SP)
25501 * 0..7 - Valid values.
25502 * 8..255 - Reserved.
25504 uint8_t queue_id3_pri_lvl;
25506 * Weight used to allocate remaining BW for this COS after
25507 * servicing guaranteed bandwidths for all COS.
25509 uint8_t queue_id3_bw_weight;
25510 /* ID of CoS Queue 4. */
25513 * Minimum BW allocated to CoS Queue.
25514 * The HWRM will translate this value into byte counter and
25515 * time interval used for this COS inside the device.
25517 uint32_t queue_id4_min_bw;
25518 /* The bandwidth value. */
25519 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
25520 UINT32_C(0xfffffff)
25521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
25523 /* The granularity of the value (bits or bytes). */
25524 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
25525 UINT32_C(0x10000000)
25526 /* Value is in bits. */
25527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
25528 (UINT32_C(0x0) << 28)
25529 /* Value is in bytes. */
25530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
25531 (UINT32_C(0x1) << 28)
25532 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
25533 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
25534 /* bw_value_unit is 3 b */
25535 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
25536 UINT32_C(0xe0000000)
25537 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
25539 /* Value is in Mb or MB (base 10). */
25540 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
25541 (UINT32_C(0x0) << 29)
25542 /* Value is in Kb or KB (base 10). */
25543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
25544 (UINT32_C(0x2) << 29)
25545 /* Value is in bits or bytes. */
25546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
25547 (UINT32_C(0x4) << 29)
25548 /* Value is in Gb or GB (base 10). */
25549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
25550 (UINT32_C(0x6) << 29)
25551 /* Value is in 1/100th of a percentage of total bandwidth. */
25552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25553 (UINT32_C(0x1) << 29)
25555 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
25556 (UINT32_C(0x7) << 29)
25557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
25558 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
25560 * Maximum BW allocated to CoS queue.
25561 * The HWRM will translate this value into byte counter and
25562 * time interval used for this COS inside the device.
25564 uint32_t queue_id4_max_bw;
25565 /* The bandwidth value. */
25566 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
25567 UINT32_C(0xfffffff)
25568 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
25570 /* The granularity of the value (bits or bytes). */
25571 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
25572 UINT32_C(0x10000000)
25573 /* Value is in bits. */
25574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
25575 (UINT32_C(0x0) << 28)
25576 /* Value is in bytes. */
25577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
25578 (UINT32_C(0x1) << 28)
25579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
25580 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
25581 /* bw_value_unit is 3 b */
25582 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
25583 UINT32_C(0xe0000000)
25584 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
25586 /* Value is in Mb or MB (base 10). */
25587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
25588 (UINT32_C(0x0) << 29)
25589 /* Value is in Kb or KB (base 10). */
25590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
25591 (UINT32_C(0x2) << 29)
25592 /* Value is in bits or bytes. */
25593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
25594 (UINT32_C(0x4) << 29)
25595 /* Value is in Gb or GB (base 10). */
25596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
25597 (UINT32_C(0x6) << 29)
25598 /* Value is in 1/100th of a percentage of total bandwidth. */
25599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25600 (UINT32_C(0x1) << 29)
25602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
25603 (UINT32_C(0x7) << 29)
25604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
25605 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
25606 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25607 uint8_t queue_id4_tsa_assign;
25608 /* Strict Priority */
25609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
25611 /* Enhanced Transmission Selection */
25612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
25615 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
25618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
25621 * Priority level for strict priority. Valid only when the
25622 * tsa_assign is 0 - Strict Priority (SP)
25623 * 0..7 - Valid values.
25624 * 8..255 - Reserved.
25626 uint8_t queue_id4_pri_lvl;
25628 * Weight used to allocate remaining BW for this COS after
25629 * servicing guaranteed bandwidths for all COS.
25631 uint8_t queue_id4_bw_weight;
25632 /* ID of CoS Queue 5. */
25635 * Minimum BW allocated to CoS Queue.
25636 * The HWRM will translate this value into byte counter and
25637 * time interval used for this COS inside the device.
25639 uint32_t queue_id5_min_bw;
25640 /* The bandwidth value. */
25641 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
25642 UINT32_C(0xfffffff)
25643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
25645 /* The granularity of the value (bits or bytes). */
25646 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
25647 UINT32_C(0x10000000)
25648 /* Value is in bits. */
25649 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
25650 (UINT32_C(0x0) << 28)
25651 /* Value is in bytes. */
25652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
25653 (UINT32_C(0x1) << 28)
25654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
25655 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
25656 /* bw_value_unit is 3 b */
25657 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
25658 UINT32_C(0xe0000000)
25659 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
25661 /* Value is in Mb or MB (base 10). */
25662 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
25663 (UINT32_C(0x0) << 29)
25664 /* Value is in Kb or KB (base 10). */
25665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
25666 (UINT32_C(0x2) << 29)
25667 /* Value is in bits or bytes. */
25668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
25669 (UINT32_C(0x4) << 29)
25670 /* Value is in Gb or GB (base 10). */
25671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
25672 (UINT32_C(0x6) << 29)
25673 /* Value is in 1/100th of a percentage of total bandwidth. */
25674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25675 (UINT32_C(0x1) << 29)
25677 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
25678 (UINT32_C(0x7) << 29)
25679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
25680 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
25682 * Maximum BW allocated to CoS queue.
25683 * The HWRM will translate this value into byte counter and
25684 * time interval used for this COS inside the device.
25686 uint32_t queue_id5_max_bw;
25687 /* The bandwidth value. */
25688 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
25689 UINT32_C(0xfffffff)
25690 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
25692 /* The granularity of the value (bits or bytes). */
25693 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
25694 UINT32_C(0x10000000)
25695 /* Value is in bits. */
25696 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
25697 (UINT32_C(0x0) << 28)
25698 /* Value is in bytes. */
25699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
25700 (UINT32_C(0x1) << 28)
25701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
25702 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
25703 /* bw_value_unit is 3 b */
25704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
25705 UINT32_C(0xe0000000)
25706 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
25708 /* Value is in Mb or MB (base 10). */
25709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
25710 (UINT32_C(0x0) << 29)
25711 /* Value is in Kb or KB (base 10). */
25712 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
25713 (UINT32_C(0x2) << 29)
25714 /* Value is in bits or bytes. */
25715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
25716 (UINT32_C(0x4) << 29)
25717 /* Value is in Gb or GB (base 10). */
25718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
25719 (UINT32_C(0x6) << 29)
25720 /* Value is in 1/100th of a percentage of total bandwidth. */
25721 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25722 (UINT32_C(0x1) << 29)
25724 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
25725 (UINT32_C(0x7) << 29)
25726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
25727 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
25728 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25729 uint8_t queue_id5_tsa_assign;
25730 /* Strict Priority */
25731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
25733 /* Enhanced Transmission Selection */
25734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
25737 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
25740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
25743 * Priority level for strict priority. Valid only when the
25744 * tsa_assign is 0 - Strict Priority (SP)
25745 * 0..7 - Valid values.
25746 * 8..255 - Reserved.
25748 uint8_t queue_id5_pri_lvl;
25750 * Weight used to allocate remaining BW for this COS after
25751 * servicing guaranteed bandwidths for all COS.
25753 uint8_t queue_id5_bw_weight;
25754 /* ID of CoS Queue 6. */
25757 * Minimum BW allocated to CoS Queue.
25758 * The HWRM will translate this value into byte counter and
25759 * time interval used for this COS inside the device.
25761 uint32_t queue_id6_min_bw;
25762 /* The bandwidth value. */
25763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
25764 UINT32_C(0xfffffff)
25765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
25767 /* The granularity of the value (bits or bytes). */
25768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
25769 UINT32_C(0x10000000)
25770 /* Value is in bits. */
25771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
25772 (UINT32_C(0x0) << 28)
25773 /* Value is in bytes. */
25774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
25775 (UINT32_C(0x1) << 28)
25776 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
25777 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
25778 /* bw_value_unit is 3 b */
25779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
25780 UINT32_C(0xe0000000)
25781 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
25783 /* Value is in Mb or MB (base 10). */
25784 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
25785 (UINT32_C(0x0) << 29)
25786 /* Value is in Kb or KB (base 10). */
25787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
25788 (UINT32_C(0x2) << 29)
25789 /* Value is in bits or bytes. */
25790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
25791 (UINT32_C(0x4) << 29)
25792 /* Value is in Gb or GB (base 10). */
25793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
25794 (UINT32_C(0x6) << 29)
25795 /* Value is in 1/100th of a percentage of total bandwidth. */
25796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25797 (UINT32_C(0x1) << 29)
25799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
25800 (UINT32_C(0x7) << 29)
25801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
25802 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
25804 * Maximum BW allocated to CoS queue.
25805 * The HWRM will translate this value into byte counter and
25806 * time interval used for this COS inside the device.
25808 uint32_t queue_id6_max_bw;
25809 /* The bandwidth value. */
25810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
25811 UINT32_C(0xfffffff)
25812 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
25814 /* The granularity of the value (bits or bytes). */
25815 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
25816 UINT32_C(0x10000000)
25817 /* Value is in bits. */
25818 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
25819 (UINT32_C(0x0) << 28)
25820 /* Value is in bytes. */
25821 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
25822 (UINT32_C(0x1) << 28)
25823 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
25824 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
25825 /* bw_value_unit is 3 b */
25826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
25827 UINT32_C(0xe0000000)
25828 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
25830 /* Value is in Mb or MB (base 10). */
25831 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
25832 (UINT32_C(0x0) << 29)
25833 /* Value is in Kb or KB (base 10). */
25834 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
25835 (UINT32_C(0x2) << 29)
25836 /* Value is in bits or bytes. */
25837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
25838 (UINT32_C(0x4) << 29)
25839 /* Value is in Gb or GB (base 10). */
25840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
25841 (UINT32_C(0x6) << 29)
25842 /* Value is in 1/100th of a percentage of total bandwidth. */
25843 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25844 (UINT32_C(0x1) << 29)
25846 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
25847 (UINT32_C(0x7) << 29)
25848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
25849 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
25850 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25851 uint8_t queue_id6_tsa_assign;
25852 /* Strict Priority */
25853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
25855 /* Enhanced Transmission Selection */
25856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
25859 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
25862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
25865 * Priority level for strict priority. Valid only when the
25866 * tsa_assign is 0 - Strict Priority (SP)
25867 * 0..7 - Valid values.
25868 * 8..255 - Reserved.
25870 uint8_t queue_id6_pri_lvl;
25872 * Weight used to allocate remaining BW for this COS after
25873 * servicing guaranteed bandwidths for all COS.
25875 uint8_t queue_id6_bw_weight;
25876 /* ID of CoS Queue 7. */
25879 * Minimum BW allocated to CoS Queue.
25880 * The HWRM will translate this value into byte counter and
25881 * time interval used for this COS inside the device.
25883 uint32_t queue_id7_min_bw;
25884 /* The bandwidth value. */
25885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
25886 UINT32_C(0xfffffff)
25887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
25889 /* The granularity of the value (bits or bytes). */
25890 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
25891 UINT32_C(0x10000000)
25892 /* Value is in bits. */
25893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
25894 (UINT32_C(0x0) << 28)
25895 /* Value is in bytes. */
25896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
25897 (UINT32_C(0x1) << 28)
25898 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
25899 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
25900 /* bw_value_unit is 3 b */
25901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
25902 UINT32_C(0xe0000000)
25903 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
25905 /* Value is in Mb or MB (base 10). */
25906 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
25907 (UINT32_C(0x0) << 29)
25908 /* Value is in Kb or KB (base 10). */
25909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
25910 (UINT32_C(0x2) << 29)
25911 /* Value is in bits or bytes. */
25912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
25913 (UINT32_C(0x4) << 29)
25914 /* Value is in Gb or GB (base 10). */
25915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
25916 (UINT32_C(0x6) << 29)
25917 /* Value is in 1/100th of a percentage of total bandwidth. */
25918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
25919 (UINT32_C(0x1) << 29)
25921 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
25922 (UINT32_C(0x7) << 29)
25923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
25924 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
25926 * Maximum BW allocated to CoS queue.
25927 * The HWRM will translate this value into byte counter and
25928 * time interval used for this COS inside the device.
25930 uint32_t queue_id7_max_bw;
25931 /* The bandwidth value. */
25932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
25933 UINT32_C(0xfffffff)
25934 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
25936 /* The granularity of the value (bits or bytes). */
25937 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
25938 UINT32_C(0x10000000)
25939 /* Value is in bits. */
25940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
25941 (UINT32_C(0x0) << 28)
25942 /* Value is in bytes. */
25943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
25944 (UINT32_C(0x1) << 28)
25945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
25946 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
25947 /* bw_value_unit is 3 b */
25948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
25949 UINT32_C(0xe0000000)
25950 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
25952 /* Value is in Mb or MB (base 10). */
25953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
25954 (UINT32_C(0x0) << 29)
25955 /* Value is in Kb or KB (base 10). */
25956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
25957 (UINT32_C(0x2) << 29)
25958 /* Value is in bits or bytes. */
25959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
25960 (UINT32_C(0x4) << 29)
25961 /* Value is in Gb or GB (base 10). */
25962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
25963 (UINT32_C(0x6) << 29)
25964 /* Value is in 1/100th of a percentage of total bandwidth. */
25965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
25966 (UINT32_C(0x1) << 29)
25968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
25969 (UINT32_C(0x7) << 29)
25970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
25971 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
25972 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
25973 uint8_t queue_id7_tsa_assign;
25974 /* Strict Priority */
25975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
25977 /* Enhanced Transmission Selection */
25978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
25981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
25984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
25987 * Priority level for strict priority. Valid only when the
25988 * tsa_assign is 0 - Strict Priority (SP)
25989 * 0..7 - Valid values.
25990 * 8..255 - Reserved.
25992 uint8_t queue_id7_pri_lvl;
25994 * Weight used to allocate remaining BW for this COS after
25995 * servicing guaranteed bandwidths for all COS.
25997 uint8_t queue_id7_bw_weight;
25998 uint8_t unused_2[4];
26000 * This field is used in Output records to indicate that the output
26001 * is completely written to RAM. This field should be read as '1'
26002 * to indicate that the output has been completely written.
26003 * When writing a command completion or response to an internal processor,
26004 * the order of writes has to be such that this field is written last.
26009 /*************************
26010 * hwrm_queue_cos2bw_cfg *
26011 *************************/
26014 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
26015 struct hwrm_queue_cos2bw_cfg_input {
26016 /* The HWRM command request type. */
26019 * The completion ring to send the completion event on. This should
26020 * be the NQ ID returned from the `nq_alloc` HWRM command.
26022 uint16_t cmpl_ring;
26024 * The sequence ID is used by the driver for tracking multiple
26025 * commands. This ID is treated as opaque data by the firmware and
26026 * the value is returned in the `hwrm_resp_hdr` upon completion.
26030 * The target ID of the command:
26031 * * 0x0-0xFFF8 - The function ID
26032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26033 * * 0xFFFD - Reserved for user-space HWRM interface
26036 uint16_t target_id;
26038 * A physical address pointer pointing to a host buffer that the
26039 * command's response data will be written. This can be either a host
26040 * physical address (HPA) or a guest physical address (GPA) and must
26041 * point to a physically contiguous block of memory.
26043 uint64_t resp_addr;
26047 * If this bit is set to 1, then all queue_id0 related
26048 * parameters in this command are valid.
26050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
26053 * If this bit is set to 1, then all queue_id1 related
26054 * parameters in this command are valid.
26056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
26059 * If this bit is set to 1, then all queue_id2 related
26060 * parameters in this command are valid.
26062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
26065 * If this bit is set to 1, then all queue_id3 related
26066 * parameters in this command are valid.
26068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
26071 * If this bit is set to 1, then all queue_id4 related
26072 * parameters in this command are valid.
26074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
26077 * If this bit is set to 1, then all queue_id5 related
26078 * parameters in this command are valid.
26080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
26083 * If this bit is set to 1, then all queue_id6 related
26084 * parameters in this command are valid.
26086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
26089 * If this bit is set to 1, then all queue_id7 related
26090 * parameters in this command are valid.
26092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
26095 * Port ID of port for which the table is being configured.
26096 * The HWRM needs to check whether this function is allowed
26097 * to configure TC BW assignment on this port.
26100 /* ID of CoS Queue 0. */
26104 * Minimum BW allocated to CoS Queue.
26105 * The HWRM will translate this value into byte counter and
26106 * time interval used for this COS inside the device.
26108 uint32_t queue_id0_min_bw;
26109 /* The bandwidth value. */
26110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
26111 UINT32_C(0xfffffff)
26112 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
26114 /* The granularity of the value (bits or bytes). */
26115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
26116 UINT32_C(0x10000000)
26117 /* Value is in bits. */
26118 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
26119 (UINT32_C(0x0) << 28)
26120 /* Value is in bytes. */
26121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
26122 (UINT32_C(0x1) << 28)
26123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
26124 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
26125 /* bw_value_unit is 3 b */
26126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
26127 UINT32_C(0xe0000000)
26128 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
26130 /* Value is in Mb or MB (base 10). */
26131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
26132 (UINT32_C(0x0) << 29)
26133 /* Value is in Kb or KB (base 10). */
26134 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
26135 (UINT32_C(0x2) << 29)
26136 /* Value is in bits or bytes. */
26137 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
26138 (UINT32_C(0x4) << 29)
26139 /* Value is in Gb or GB (base 10). */
26140 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
26141 (UINT32_C(0x6) << 29)
26142 /* Value is in 1/100th of a percentage of total bandwidth. */
26143 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26144 (UINT32_C(0x1) << 29)
26146 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
26147 (UINT32_C(0x7) << 29)
26148 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
26149 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
26151 * Maximum BW allocated to CoS Queue.
26152 * The HWRM will translate this value into byte counter and
26153 * time interval used for this COS inside the device.
26155 uint32_t queue_id0_max_bw;
26156 /* The bandwidth value. */
26157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
26158 UINT32_C(0xfffffff)
26159 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
26161 /* The granularity of the value (bits or bytes). */
26162 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
26163 UINT32_C(0x10000000)
26164 /* Value is in bits. */
26165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
26166 (UINT32_C(0x0) << 28)
26167 /* Value is in bytes. */
26168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
26169 (UINT32_C(0x1) << 28)
26170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
26171 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
26172 /* bw_value_unit is 3 b */
26173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
26174 UINT32_C(0xe0000000)
26175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
26177 /* Value is in Mb or MB (base 10). */
26178 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
26179 (UINT32_C(0x0) << 29)
26180 /* Value is in Kb or KB (base 10). */
26181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
26182 (UINT32_C(0x2) << 29)
26183 /* Value is in bits or bytes. */
26184 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
26185 (UINT32_C(0x4) << 29)
26186 /* Value is in Gb or GB (base 10). */
26187 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
26188 (UINT32_C(0x6) << 29)
26189 /* Value is in 1/100th of a percentage of total bandwidth. */
26190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26191 (UINT32_C(0x1) << 29)
26193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
26194 (UINT32_C(0x7) << 29)
26195 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
26196 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
26197 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26198 uint8_t queue_id0_tsa_assign;
26199 /* Strict Priority */
26200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
26202 /* Enhanced Transmission Selection */
26203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
26206 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
26209 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
26212 * Priority level for strict priority. Valid only when the
26213 * tsa_assign is 0 - Strict Priority (SP)
26214 * 0..7 - Valid values.
26215 * 8..255 - Reserved.
26217 uint8_t queue_id0_pri_lvl;
26219 * Weight used to allocate remaining BW for this COS after
26220 * servicing guaranteed bandwidths for all COS.
26222 uint8_t queue_id0_bw_weight;
26223 /* ID of CoS Queue 1. */
26226 * Minimum BW allocated to CoS Queue.
26227 * The HWRM will translate this value into byte counter and
26228 * time interval used for this COS inside the device.
26230 uint32_t queue_id1_min_bw;
26231 /* The bandwidth value. */
26232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
26233 UINT32_C(0xfffffff)
26234 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
26236 /* The granularity of the value (bits or bytes). */
26237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
26238 UINT32_C(0x10000000)
26239 /* Value is in bits. */
26240 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
26241 (UINT32_C(0x0) << 28)
26242 /* Value is in bytes. */
26243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
26244 (UINT32_C(0x1) << 28)
26245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
26246 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
26247 /* bw_value_unit is 3 b */
26248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
26249 UINT32_C(0xe0000000)
26250 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
26252 /* Value is in Mb or MB (base 10). */
26253 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
26254 (UINT32_C(0x0) << 29)
26255 /* Value is in Kb or KB (base 10). */
26256 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
26257 (UINT32_C(0x2) << 29)
26258 /* Value is in bits or bytes. */
26259 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
26260 (UINT32_C(0x4) << 29)
26261 /* Value is in Gb or GB (base 10). */
26262 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
26263 (UINT32_C(0x6) << 29)
26264 /* Value is in 1/100th of a percentage of total bandwidth. */
26265 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26266 (UINT32_C(0x1) << 29)
26268 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
26269 (UINT32_C(0x7) << 29)
26270 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
26271 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
26273 * Maximum BW allocated to CoS queue.
26274 * The HWRM will translate this value into byte counter and
26275 * time interval used for this COS inside the device.
26277 uint32_t queue_id1_max_bw;
26278 /* The bandwidth value. */
26279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
26280 UINT32_C(0xfffffff)
26281 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
26283 /* The granularity of the value (bits or bytes). */
26284 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
26285 UINT32_C(0x10000000)
26286 /* Value is in bits. */
26287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
26288 (UINT32_C(0x0) << 28)
26289 /* Value is in bytes. */
26290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
26291 (UINT32_C(0x1) << 28)
26292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
26293 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
26294 /* bw_value_unit is 3 b */
26295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
26296 UINT32_C(0xe0000000)
26297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
26299 /* Value is in Mb or MB (base 10). */
26300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
26301 (UINT32_C(0x0) << 29)
26302 /* Value is in Kb or KB (base 10). */
26303 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
26304 (UINT32_C(0x2) << 29)
26305 /* Value is in bits or bytes. */
26306 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
26307 (UINT32_C(0x4) << 29)
26308 /* Value is in Gb or GB (base 10). */
26309 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
26310 (UINT32_C(0x6) << 29)
26311 /* Value is in 1/100th of a percentage of total bandwidth. */
26312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26313 (UINT32_C(0x1) << 29)
26315 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
26316 (UINT32_C(0x7) << 29)
26317 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
26318 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
26319 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26320 uint8_t queue_id1_tsa_assign;
26321 /* Strict Priority */
26322 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
26324 /* Enhanced Transmission Selection */
26325 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
26328 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
26331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
26334 * Priority level for strict priority. Valid only when the
26335 * tsa_assign is 0 - Strict Priority (SP)
26336 * 0..7 - Valid values.
26337 * 8..255 - Reserved.
26339 uint8_t queue_id1_pri_lvl;
26341 * Weight used to allocate remaining BW for this COS after
26342 * servicing guaranteed bandwidths for all COS.
26344 uint8_t queue_id1_bw_weight;
26345 /* ID of CoS Queue 2. */
26348 * Minimum BW allocated to CoS Queue.
26349 * The HWRM will translate this value into byte counter and
26350 * time interval used for this COS inside the device.
26352 uint32_t queue_id2_min_bw;
26353 /* The bandwidth value. */
26354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
26355 UINT32_C(0xfffffff)
26356 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
26358 /* The granularity of the value (bits or bytes). */
26359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
26360 UINT32_C(0x10000000)
26361 /* Value is in bits. */
26362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
26363 (UINT32_C(0x0) << 28)
26364 /* Value is in bytes. */
26365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
26366 (UINT32_C(0x1) << 28)
26367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
26368 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
26369 /* bw_value_unit is 3 b */
26370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
26371 UINT32_C(0xe0000000)
26372 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
26374 /* Value is in Mb or MB (base 10). */
26375 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
26376 (UINT32_C(0x0) << 29)
26377 /* Value is in Kb or KB (base 10). */
26378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
26379 (UINT32_C(0x2) << 29)
26380 /* Value is in bits or bytes. */
26381 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
26382 (UINT32_C(0x4) << 29)
26383 /* Value is in Gb or GB (base 10). */
26384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
26385 (UINT32_C(0x6) << 29)
26386 /* Value is in 1/100th of a percentage of total bandwidth. */
26387 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26388 (UINT32_C(0x1) << 29)
26390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
26391 (UINT32_C(0x7) << 29)
26392 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
26393 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
26395 * Maximum BW allocated to CoS queue.
26396 * The HWRM will translate this value into byte counter and
26397 * time interval used for this COS inside the device.
26399 uint32_t queue_id2_max_bw;
26400 /* The bandwidth value. */
26401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
26402 UINT32_C(0xfffffff)
26403 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
26405 /* The granularity of the value (bits or bytes). */
26406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
26407 UINT32_C(0x10000000)
26408 /* Value is in bits. */
26409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
26410 (UINT32_C(0x0) << 28)
26411 /* Value is in bytes. */
26412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
26413 (UINT32_C(0x1) << 28)
26414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
26415 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
26416 /* bw_value_unit is 3 b */
26417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
26418 UINT32_C(0xe0000000)
26419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
26421 /* Value is in Mb or MB (base 10). */
26422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
26423 (UINT32_C(0x0) << 29)
26424 /* Value is in Kb or KB (base 10). */
26425 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
26426 (UINT32_C(0x2) << 29)
26427 /* Value is in bits or bytes. */
26428 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
26429 (UINT32_C(0x4) << 29)
26430 /* Value is in Gb or GB (base 10). */
26431 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
26432 (UINT32_C(0x6) << 29)
26433 /* Value is in 1/100th of a percentage of total bandwidth. */
26434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26435 (UINT32_C(0x1) << 29)
26437 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
26438 (UINT32_C(0x7) << 29)
26439 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
26440 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
26441 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26442 uint8_t queue_id2_tsa_assign;
26443 /* Strict Priority */
26444 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
26446 /* Enhanced Transmission Selection */
26447 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
26450 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
26453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
26456 * Priority level for strict priority. Valid only when the
26457 * tsa_assign is 0 - Strict Priority (SP)
26458 * 0..7 - Valid values.
26459 * 8..255 - Reserved.
26461 uint8_t queue_id2_pri_lvl;
26463 * Weight used to allocate remaining BW for this COS after
26464 * servicing guaranteed bandwidths for all COS.
26466 uint8_t queue_id2_bw_weight;
26467 /* ID of CoS Queue 3. */
26470 * Minimum BW allocated to CoS Queue.
26471 * The HWRM will translate this value into byte counter and
26472 * time interval used for this COS inside the device.
26474 uint32_t queue_id3_min_bw;
26475 /* The bandwidth value. */
26476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
26477 UINT32_C(0xfffffff)
26478 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
26480 /* The granularity of the value (bits or bytes). */
26481 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
26482 UINT32_C(0x10000000)
26483 /* Value is in bits. */
26484 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
26485 (UINT32_C(0x0) << 28)
26486 /* Value is in bytes. */
26487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
26488 (UINT32_C(0x1) << 28)
26489 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
26490 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
26491 /* bw_value_unit is 3 b */
26492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
26493 UINT32_C(0xe0000000)
26494 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
26496 /* Value is in Mb or MB (base 10). */
26497 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
26498 (UINT32_C(0x0) << 29)
26499 /* Value is in Kb or KB (base 10). */
26500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
26501 (UINT32_C(0x2) << 29)
26502 /* Value is in bits or bytes. */
26503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
26504 (UINT32_C(0x4) << 29)
26505 /* Value is in Gb or GB (base 10). */
26506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
26507 (UINT32_C(0x6) << 29)
26508 /* Value is in 1/100th of a percentage of total bandwidth. */
26509 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26510 (UINT32_C(0x1) << 29)
26512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
26513 (UINT32_C(0x7) << 29)
26514 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
26515 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
26517 * Maximum BW allocated to CoS queue.
26518 * The HWRM will translate this value into byte counter and
26519 * time interval used for this COS inside the device.
26521 uint32_t queue_id3_max_bw;
26522 /* The bandwidth value. */
26523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
26524 UINT32_C(0xfffffff)
26525 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
26527 /* The granularity of the value (bits or bytes). */
26528 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
26529 UINT32_C(0x10000000)
26530 /* Value is in bits. */
26531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
26532 (UINT32_C(0x0) << 28)
26533 /* Value is in bytes. */
26534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
26535 (UINT32_C(0x1) << 28)
26536 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
26537 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
26538 /* bw_value_unit is 3 b */
26539 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
26540 UINT32_C(0xe0000000)
26541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
26543 /* Value is in Mb or MB (base 10). */
26544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
26545 (UINT32_C(0x0) << 29)
26546 /* Value is in Kb or KB (base 10). */
26547 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
26548 (UINT32_C(0x2) << 29)
26549 /* Value is in bits or bytes. */
26550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
26551 (UINT32_C(0x4) << 29)
26552 /* Value is in Gb or GB (base 10). */
26553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
26554 (UINT32_C(0x6) << 29)
26555 /* Value is in 1/100th of a percentage of total bandwidth. */
26556 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26557 (UINT32_C(0x1) << 29)
26559 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
26560 (UINT32_C(0x7) << 29)
26561 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
26562 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
26563 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26564 uint8_t queue_id3_tsa_assign;
26565 /* Strict Priority */
26566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
26568 /* Enhanced Transmission Selection */
26569 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
26572 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
26575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
26578 * Priority level for strict priority. Valid only when the
26579 * tsa_assign is 0 - Strict Priority (SP)
26580 * 0..7 - Valid values.
26581 * 8..255 - Reserved.
26583 uint8_t queue_id3_pri_lvl;
26585 * Weight used to allocate remaining BW for this COS after
26586 * servicing guaranteed bandwidths for all COS.
26588 uint8_t queue_id3_bw_weight;
26589 /* ID of CoS Queue 4. */
26592 * Minimum BW allocated to CoS Queue.
26593 * The HWRM will translate this value into byte counter and
26594 * time interval used for this COS inside the device.
26596 uint32_t queue_id4_min_bw;
26597 /* The bandwidth value. */
26598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
26599 UINT32_C(0xfffffff)
26600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
26602 /* The granularity of the value (bits or bytes). */
26603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
26604 UINT32_C(0x10000000)
26605 /* Value is in bits. */
26606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
26607 (UINT32_C(0x0) << 28)
26608 /* Value is in bytes. */
26609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
26610 (UINT32_C(0x1) << 28)
26611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
26612 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
26613 /* bw_value_unit is 3 b */
26614 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
26615 UINT32_C(0xe0000000)
26616 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
26618 /* Value is in Mb or MB (base 10). */
26619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
26620 (UINT32_C(0x0) << 29)
26621 /* Value is in Kb or KB (base 10). */
26622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
26623 (UINT32_C(0x2) << 29)
26624 /* Value is in bits or bytes. */
26625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
26626 (UINT32_C(0x4) << 29)
26627 /* Value is in Gb or GB (base 10). */
26628 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
26629 (UINT32_C(0x6) << 29)
26630 /* Value is in 1/100th of a percentage of total bandwidth. */
26631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26632 (UINT32_C(0x1) << 29)
26634 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
26635 (UINT32_C(0x7) << 29)
26636 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
26637 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
26639 * Maximum BW allocated to CoS queue.
26640 * The HWRM will translate this value into byte counter and
26641 * time interval used for this COS inside the device.
26643 uint32_t queue_id4_max_bw;
26644 /* The bandwidth value. */
26645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
26646 UINT32_C(0xfffffff)
26647 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
26649 /* The granularity of the value (bits or bytes). */
26650 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
26651 UINT32_C(0x10000000)
26652 /* Value is in bits. */
26653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
26654 (UINT32_C(0x0) << 28)
26655 /* Value is in bytes. */
26656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
26657 (UINT32_C(0x1) << 28)
26658 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
26659 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
26660 /* bw_value_unit is 3 b */
26661 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
26662 UINT32_C(0xe0000000)
26663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
26665 /* Value is in Mb or MB (base 10). */
26666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
26667 (UINT32_C(0x0) << 29)
26668 /* Value is in Kb or KB (base 10). */
26669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
26670 (UINT32_C(0x2) << 29)
26671 /* Value is in bits or bytes. */
26672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
26673 (UINT32_C(0x4) << 29)
26674 /* Value is in Gb or GB (base 10). */
26675 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
26676 (UINT32_C(0x6) << 29)
26677 /* Value is in 1/100th of a percentage of total bandwidth. */
26678 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26679 (UINT32_C(0x1) << 29)
26681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
26682 (UINT32_C(0x7) << 29)
26683 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
26684 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
26685 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26686 uint8_t queue_id4_tsa_assign;
26687 /* Strict Priority */
26688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
26690 /* Enhanced Transmission Selection */
26691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
26694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
26697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
26700 * Priority level for strict priority. Valid only when the
26701 * tsa_assign is 0 - Strict Priority (SP)
26702 * 0..7 - Valid values.
26703 * 8..255 - Reserved.
26705 uint8_t queue_id4_pri_lvl;
26707 * Weight used to allocate remaining BW for this COS after
26708 * servicing guaranteed bandwidths for all COS.
26710 uint8_t queue_id4_bw_weight;
26711 /* ID of CoS Queue 5. */
26714 * Minimum BW allocated to CoS Queue.
26715 * The HWRM will translate this value into byte counter and
26716 * time interval used for this COS inside the device.
26718 uint32_t queue_id5_min_bw;
26719 /* The bandwidth value. */
26720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
26721 UINT32_C(0xfffffff)
26722 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
26724 /* The granularity of the value (bits or bytes). */
26725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
26726 UINT32_C(0x10000000)
26727 /* Value is in bits. */
26728 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
26729 (UINT32_C(0x0) << 28)
26730 /* Value is in bytes. */
26731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
26732 (UINT32_C(0x1) << 28)
26733 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
26734 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
26735 /* bw_value_unit is 3 b */
26736 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
26737 UINT32_C(0xe0000000)
26738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
26740 /* Value is in Mb or MB (base 10). */
26741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
26742 (UINT32_C(0x0) << 29)
26743 /* Value is in Kb or KB (base 10). */
26744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
26745 (UINT32_C(0x2) << 29)
26746 /* Value is in bits or bytes. */
26747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
26748 (UINT32_C(0x4) << 29)
26749 /* Value is in Gb or GB (base 10). */
26750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
26751 (UINT32_C(0x6) << 29)
26752 /* Value is in 1/100th of a percentage of total bandwidth. */
26753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26754 (UINT32_C(0x1) << 29)
26756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
26757 (UINT32_C(0x7) << 29)
26758 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
26759 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
26761 * Maximum BW allocated to CoS queue.
26762 * The HWRM will translate this value into byte counter and
26763 * time interval used for this COS inside the device.
26765 uint32_t queue_id5_max_bw;
26766 /* The bandwidth value. */
26767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
26768 UINT32_C(0xfffffff)
26769 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
26771 /* The granularity of the value (bits or bytes). */
26772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
26773 UINT32_C(0x10000000)
26774 /* Value is in bits. */
26775 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
26776 (UINT32_C(0x0) << 28)
26777 /* Value is in bytes. */
26778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
26779 (UINT32_C(0x1) << 28)
26780 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
26781 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
26782 /* bw_value_unit is 3 b */
26783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
26784 UINT32_C(0xe0000000)
26785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
26787 /* Value is in Mb or MB (base 10). */
26788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
26789 (UINT32_C(0x0) << 29)
26790 /* Value is in Kb or KB (base 10). */
26791 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
26792 (UINT32_C(0x2) << 29)
26793 /* Value is in bits or bytes. */
26794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
26795 (UINT32_C(0x4) << 29)
26796 /* Value is in Gb or GB (base 10). */
26797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
26798 (UINT32_C(0x6) << 29)
26799 /* Value is in 1/100th of a percentage of total bandwidth. */
26800 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26801 (UINT32_C(0x1) << 29)
26803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
26804 (UINT32_C(0x7) << 29)
26805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
26806 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
26807 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26808 uint8_t queue_id5_tsa_assign;
26809 /* Strict Priority */
26810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
26812 /* Enhanced Transmission Selection */
26813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
26816 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
26819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
26822 * Priority level for strict priority. Valid only when the
26823 * tsa_assign is 0 - Strict Priority (SP)
26824 * 0..7 - Valid values.
26825 * 8..255 - Reserved.
26827 uint8_t queue_id5_pri_lvl;
26829 * Weight used to allocate remaining BW for this COS after
26830 * servicing guaranteed bandwidths for all COS.
26832 uint8_t queue_id5_bw_weight;
26833 /* ID of CoS Queue 6. */
26836 * Minimum BW allocated to CoS Queue.
26837 * The HWRM will translate this value into byte counter and
26838 * time interval used for this COS inside the device.
26840 uint32_t queue_id6_min_bw;
26841 /* The bandwidth value. */
26842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
26843 UINT32_C(0xfffffff)
26844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
26846 /* The granularity of the value (bits or bytes). */
26847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
26848 UINT32_C(0x10000000)
26849 /* Value is in bits. */
26850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
26851 (UINT32_C(0x0) << 28)
26852 /* Value is in bytes. */
26853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
26854 (UINT32_C(0x1) << 28)
26855 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
26856 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
26857 /* bw_value_unit is 3 b */
26858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
26859 UINT32_C(0xe0000000)
26860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
26862 /* Value is in Mb or MB (base 10). */
26863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
26864 (UINT32_C(0x0) << 29)
26865 /* Value is in Kb or KB (base 10). */
26866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
26867 (UINT32_C(0x2) << 29)
26868 /* Value is in bits or bytes. */
26869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
26870 (UINT32_C(0x4) << 29)
26871 /* Value is in Gb or GB (base 10). */
26872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
26873 (UINT32_C(0x6) << 29)
26874 /* Value is in 1/100th of a percentage of total bandwidth. */
26875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26876 (UINT32_C(0x1) << 29)
26878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
26879 (UINT32_C(0x7) << 29)
26880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
26881 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
26883 * Maximum BW allocated to CoS queue.
26884 * The HWRM will translate this value into byte counter and
26885 * time interval used for this COS inside the device.
26887 uint32_t queue_id6_max_bw;
26888 /* The bandwidth value. */
26889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
26890 UINT32_C(0xfffffff)
26891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
26893 /* The granularity of the value (bits or bytes). */
26894 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
26895 UINT32_C(0x10000000)
26896 /* Value is in bits. */
26897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
26898 (UINT32_C(0x0) << 28)
26899 /* Value is in bytes. */
26900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
26901 (UINT32_C(0x1) << 28)
26902 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
26903 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
26904 /* bw_value_unit is 3 b */
26905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
26906 UINT32_C(0xe0000000)
26907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
26909 /* Value is in Mb or MB (base 10). */
26910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
26911 (UINT32_C(0x0) << 29)
26912 /* Value is in Kb or KB (base 10). */
26913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
26914 (UINT32_C(0x2) << 29)
26915 /* Value is in bits or bytes. */
26916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
26917 (UINT32_C(0x4) << 29)
26918 /* Value is in Gb or GB (base 10). */
26919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
26920 (UINT32_C(0x6) << 29)
26921 /* Value is in 1/100th of a percentage of total bandwidth. */
26922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26923 (UINT32_C(0x1) << 29)
26925 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
26926 (UINT32_C(0x7) << 29)
26927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
26928 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
26929 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26930 uint8_t queue_id6_tsa_assign;
26931 /* Strict Priority */
26932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
26934 /* Enhanced Transmission Selection */
26935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
26938 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
26941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
26944 * Priority level for strict priority. Valid only when the
26945 * tsa_assign is 0 - Strict Priority (SP)
26946 * 0..7 - Valid values.
26947 * 8..255 - Reserved.
26949 uint8_t queue_id6_pri_lvl;
26951 * Weight used to allocate remaining BW for this COS after
26952 * servicing guaranteed bandwidths for all COS.
26954 uint8_t queue_id6_bw_weight;
26955 /* ID of CoS Queue 7. */
26958 * Minimum BW allocated to CoS Queue.
26959 * The HWRM will translate this value into byte counter and
26960 * time interval used for this COS inside the device.
26962 uint32_t queue_id7_min_bw;
26963 /* The bandwidth value. */
26964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
26965 UINT32_C(0xfffffff)
26966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
26968 /* The granularity of the value (bits or bytes). */
26969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
26970 UINT32_C(0x10000000)
26971 /* Value is in bits. */
26972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
26973 (UINT32_C(0x0) << 28)
26974 /* Value is in bytes. */
26975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
26976 (UINT32_C(0x1) << 28)
26977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
26978 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
26979 /* bw_value_unit is 3 b */
26980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
26981 UINT32_C(0xe0000000)
26982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
26984 /* Value is in Mb or MB (base 10). */
26985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
26986 (UINT32_C(0x0) << 29)
26987 /* Value is in Kb or KB (base 10). */
26988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
26989 (UINT32_C(0x2) << 29)
26990 /* Value is in bits or bytes. */
26991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
26992 (UINT32_C(0x4) << 29)
26993 /* Value is in Gb or GB (base 10). */
26994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
26995 (UINT32_C(0x6) << 29)
26996 /* Value is in 1/100th of a percentage of total bandwidth. */
26997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26998 (UINT32_C(0x1) << 29)
27000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
27001 (UINT32_C(0x7) << 29)
27002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
27003 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
27005 * Maximum BW allocated to CoS queue.
27006 * The HWRM will translate this value into byte counter and
27007 * time interval used for this COS inside the device.
27009 uint32_t queue_id7_max_bw;
27010 /* The bandwidth value. */
27011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
27012 UINT32_C(0xfffffff)
27013 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
27015 /* The granularity of the value (bits or bytes). */
27016 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
27017 UINT32_C(0x10000000)
27018 /* Value is in bits. */
27019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
27020 (UINT32_C(0x0) << 28)
27021 /* Value is in bytes. */
27022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
27023 (UINT32_C(0x1) << 28)
27024 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
27025 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
27026 /* bw_value_unit is 3 b */
27027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
27028 UINT32_C(0xe0000000)
27029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
27031 /* Value is in Mb or MB (base 10). */
27032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
27033 (UINT32_C(0x0) << 29)
27034 /* Value is in Kb or KB (base 10). */
27035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
27036 (UINT32_C(0x2) << 29)
27037 /* Value is in bits or bytes. */
27038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
27039 (UINT32_C(0x4) << 29)
27040 /* Value is in Gb or GB (base 10). */
27041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
27042 (UINT32_C(0x6) << 29)
27043 /* Value is in 1/100th of a percentage of total bandwidth. */
27044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27045 (UINT32_C(0x1) << 29)
27047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
27048 (UINT32_C(0x7) << 29)
27049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
27050 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
27051 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27052 uint8_t queue_id7_tsa_assign;
27053 /* Strict Priority */
27054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
27056 /* Enhanced Transmission Selection */
27057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
27060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
27063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
27066 * Priority level for strict priority. Valid only when the
27067 * tsa_assign is 0 - Strict Priority (SP)
27068 * 0..7 - Valid values.
27069 * 8..255 - Reserved.
27071 uint8_t queue_id7_pri_lvl;
27073 * Weight used to allocate remaining BW for this COS after
27074 * servicing guaranteed bandwidths for all COS.
27076 uint8_t queue_id7_bw_weight;
27077 uint8_t unused_1[5];
27080 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
27081 struct hwrm_queue_cos2bw_cfg_output {
27082 /* The specific error status for the command. */
27083 uint16_t error_code;
27084 /* The HWRM command request type. */
27086 /* The sequence ID from the original command. */
27088 /* The length of the response data in number of bytes. */
27090 uint8_t unused_0[7];
27092 * This field is used in Output records to indicate that the output
27093 * is completely written to RAM. This field should be read as '1'
27094 * to indicate that the output has been completely written.
27095 * When writing a command completion or response to an internal processor,
27096 * the order of writes has to be such that this field is written last.
27101 /*************************
27102 * hwrm_queue_dscp_qcaps *
27103 *************************/
27106 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
27107 struct hwrm_queue_dscp_qcaps_input {
27108 /* The HWRM command request type. */
27111 * The completion ring to send the completion event on. This should
27112 * be the NQ ID returned from the `nq_alloc` HWRM command.
27114 uint16_t cmpl_ring;
27116 * The sequence ID is used by the driver for tracking multiple
27117 * commands. This ID is treated as opaque data by the firmware and
27118 * the value is returned in the `hwrm_resp_hdr` upon completion.
27122 * The target ID of the command:
27123 * * 0x0-0xFFF8 - The function ID
27124 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27125 * * 0xFFFD - Reserved for user-space HWRM interface
27128 uint16_t target_id;
27130 * A physical address pointer pointing to a host buffer that the
27131 * command's response data will be written. This can be either a host
27132 * physical address (HPA) or a guest physical address (GPA) and must
27133 * point to a physically contiguous block of memory.
27135 uint64_t resp_addr;
27137 * Port ID of port for which the table is being configured.
27138 * The HWRM needs to check whether this function is allowed
27139 * to configure pri2cos mapping on this port.
27142 uint8_t unused_0[7];
27145 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
27146 struct hwrm_queue_dscp_qcaps_output {
27147 /* The specific error status for the command. */
27148 uint16_t error_code;
27149 /* The HWRM command request type. */
27151 /* The sequence ID from the original command. */
27153 /* The length of the response data in number of bytes. */
27155 /* The number of bits provided by the hardware for the DSCP value. */
27156 uint8_t num_dscp_bits;
27158 /* Max number of DSCP-MASK-PRI entries supported. */
27159 uint16_t max_entries;
27160 uint8_t unused_1[3];
27162 * This field is used in Output records to indicate that the output
27163 * is completely written to RAM. This field should be read as '1'
27164 * to indicate that the output has been completely written.
27165 * When writing a command completion or response to an internal processor,
27166 * the order of writes has to be such that this field is written last.
27171 /****************************
27172 * hwrm_queue_dscp2pri_qcfg *
27173 ****************************/
27176 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
27177 struct hwrm_queue_dscp2pri_qcfg_input {
27178 /* The HWRM command request type. */
27181 * The completion ring to send the completion event on. This should
27182 * be the NQ ID returned from the `nq_alloc` HWRM command.
27184 uint16_t cmpl_ring;
27186 * The sequence ID is used by the driver for tracking multiple
27187 * commands. This ID is treated as opaque data by the firmware and
27188 * the value is returned in the `hwrm_resp_hdr` upon completion.
27192 * The target ID of the command:
27193 * * 0x0-0xFFF8 - The function ID
27194 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27195 * * 0xFFFD - Reserved for user-space HWRM interface
27198 uint16_t target_id;
27200 * A physical address pointer pointing to a host buffer that the
27201 * command's response data will be written. This can be either a host
27202 * physical address (HPA) or a guest physical address (GPA) and must
27203 * point to a physically contiguous block of memory.
27205 uint64_t resp_addr;
27207 * This is the host address where the 24-bits DSCP-MASK-PRI
27208 * tuple(s) will be copied to.
27210 uint64_t dest_data_addr;
27212 * Port ID of port for which the table is being configured.
27213 * The HWRM needs to check whether this function is allowed
27214 * to configure pri2cos mapping on this port.
27218 /* Size of the buffer pointed to by dest_data_addr. */
27219 uint16_t dest_data_buffer_size;
27220 uint8_t unused_1[4];
27223 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
27224 struct hwrm_queue_dscp2pri_qcfg_output {
27225 /* The specific error status for the command. */
27226 uint16_t error_code;
27227 /* The HWRM command request type. */
27229 /* The sequence ID from the original command. */
27231 /* The length of the response data in number of bytes. */
27234 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
27235 * by the dest_data_addr.
27237 uint16_t entry_cnt;
27239 * This is the default PRI which un-initialized DSCP values are
27242 uint8_t default_pri;
27243 uint8_t unused_0[4];
27245 * This field is used in Output records to indicate that the output
27246 * is completely written to RAM. This field should be read as '1'
27247 * to indicate that the output has been completely written.
27248 * When writing a command completion or response to an internal processor,
27249 * the order of writes has to be such that this field is written last.
27254 /***************************
27255 * hwrm_queue_dscp2pri_cfg *
27256 ***************************/
27259 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
27260 struct hwrm_queue_dscp2pri_cfg_input {
27261 /* The HWRM command request type. */
27264 * The completion ring to send the completion event on. This should
27265 * be the NQ ID returned from the `nq_alloc` HWRM command.
27267 uint16_t cmpl_ring;
27269 * The sequence ID is used by the driver for tracking multiple
27270 * commands. This ID is treated as opaque data by the firmware and
27271 * the value is returned in the `hwrm_resp_hdr` upon completion.
27275 * The target ID of the command:
27276 * * 0x0-0xFFF8 - The function ID
27277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27278 * * 0xFFFD - Reserved for user-space HWRM interface
27281 uint16_t target_id;
27283 * A physical address pointer pointing to a host buffer that the
27284 * command's response data will be written. This can be either a host
27285 * physical address (HPA) or a guest physical address (GPA) and must
27286 * point to a physically contiguous block of memory.
27288 uint64_t resp_addr;
27290 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
27291 * will be copied from.
27293 uint64_t src_data_addr;
27295 /* use_hw_default_pri is 1 b */
27296 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
27300 * This bit must be '1' for the default_pri field to be
27303 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
27306 * Port ID of port for which the table is being configured.
27307 * The HWRM needs to check whether this function is allowed
27308 * to configure pri2cos mapping on this port.
27312 * This is the default PRI which un-initialized DSCP values will be
27315 uint8_t default_pri;
27317 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
27318 * to by src_data_addr.
27320 uint16_t entry_cnt;
27321 uint8_t unused_0[4];
27324 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
27325 struct hwrm_queue_dscp2pri_cfg_output {
27326 /* The specific error status for the command. */
27327 uint16_t error_code;
27328 /* The HWRM command request type. */
27330 /* The sequence ID from the original command. */
27332 /* The length of the response data in number of bytes. */
27334 uint8_t unused_0[7];
27336 * This field is used in Output records to indicate that the output
27337 * is completely written to RAM. This field should be read as '1'
27338 * to indicate that the output has been completely written.
27339 * When writing a command completion or response to an internal processor,
27340 * the order of writes has to be such that this field is written last.
27345 /*************************
27346 * hwrm_queue_mpls_qcaps *
27347 *************************/
27350 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
27351 struct hwrm_queue_mpls_qcaps_input {
27352 /* The HWRM command request type. */
27355 * The completion ring to send the completion event on. This should
27356 * be the NQ ID returned from the `nq_alloc` HWRM command.
27358 uint16_t cmpl_ring;
27360 * The sequence ID is used by the driver for tracking multiple
27361 * commands. This ID is treated as opaque data by the firmware and
27362 * the value is returned in the `hwrm_resp_hdr` upon completion.
27366 * The target ID of the command:
27367 * * 0x0-0xFFF8 - The function ID
27368 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27369 * * 0xFFFD - Reserved for user-space HWRM interface
27372 uint16_t target_id;
27374 * A physical address pointer pointing to a host buffer that the
27375 * command's response data will be written. This can be either a host
27376 * physical address (HPA) or a guest physical address (GPA) and must
27377 * point to a physically contiguous block of memory.
27379 uint64_t resp_addr;
27381 * Port ID of port for which the table is being configured.
27382 * The HWRM needs to check whether this function is allowed
27383 * to configure MPLS TC(EXP) to pri mapping on this port.
27386 uint8_t unused_0[7];
27389 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
27390 struct hwrm_queue_mpls_qcaps_output {
27391 /* The specific error status for the command. */
27392 uint16_t error_code;
27393 /* The HWRM command request type. */
27395 /* The sequence ID from the original command. */
27397 /* The length of the response data in number of bytes. */
27400 * Bitmask indicating which queues can be configured by the
27401 * hwrm_queue_mplstc2pri_cfg command.
27403 * Each bit represents a specific pri where bit 0 represents
27404 * pri 0 and bit 7 represents pri 7.
27405 * # A value of 0 indicates that the pri is not configurable
27406 * by the hwrm_queue_mplstc2pri_cfg command.
27407 * # A value of 1 indicates that the pri is configurable.
27408 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
27409 * trying to configure a pri that is not configurable.
27411 uint8_t queue_mplstc2pri_cfg_allowed;
27413 * This is the default PRI which un-initialized MPLS values will be
27416 uint8_t hw_default_pri;
27417 uint8_t unused_0[5];
27419 * This field is used in Output records to indicate that the output
27420 * is completely written to RAM. This field should be read as '1'
27421 * to indicate that the output has been completely written.
27422 * When writing a command completion or response to an internal processor,
27423 * the order of writes has to be such that this field is written last.
27428 /******************************
27429 * hwrm_queue_mplstc2pri_qcfg *
27430 ******************************/
27433 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
27434 struct hwrm_queue_mplstc2pri_qcfg_input {
27435 /* The HWRM command request type. */
27438 * The completion ring to send the completion event on. This should
27439 * be the NQ ID returned from the `nq_alloc` HWRM command.
27441 uint16_t cmpl_ring;
27443 * The sequence ID is used by the driver for tracking multiple
27444 * commands. This ID is treated as opaque data by the firmware and
27445 * the value is returned in the `hwrm_resp_hdr` upon completion.
27449 * The target ID of the command:
27450 * * 0x0-0xFFF8 - The function ID
27451 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27452 * * 0xFFFD - Reserved for user-space HWRM interface
27455 uint16_t target_id;
27457 * A physical address pointer pointing to a host buffer that the
27458 * command's response data will be written. This can be either a host
27459 * physical address (HPA) or a guest physical address (GPA) and must
27460 * point to a physically contiguous block of memory.
27462 uint64_t resp_addr;
27464 * Port ID of port for which the table is being configured.
27465 * The HWRM needs to check whether this function is allowed
27466 * to configure MPLS TC(EXP) to pri mapping on this port.
27469 uint8_t unused_0[7];
27472 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
27473 struct hwrm_queue_mplstc2pri_qcfg_output {
27474 /* The specific error status for the command. */
27475 uint16_t error_code;
27476 /* The HWRM command request type. */
27478 /* The sequence ID from the original command. */
27480 /* The length of the response data in number of bytes. */
27483 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
27484 * before traffic has started.
27485 * A value of 0xff indicates that no pri is assigned to the
27488 uint8_t tc0_pri_queue_id;
27490 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
27491 * before traffic has started.
27492 * A value of 0xff indicates that no pri is assigned to the
27495 uint8_t tc1_pri_queue_id;
27497 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
27498 * before traffic has started.
27499 * A value of 0xff indicates that no pri is assigned to the
27502 uint8_t tc2_pri_queue_id;
27504 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
27505 * before traffic has started.
27506 * A value of 0xff indicates that no pri is assigned to the
27509 uint8_t tc3_pri_queue_id;
27511 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
27512 * before traffic has started.
27513 * A value of 0xff indicates that no pri is assigned to the
27516 uint8_t tc4_pri_queue_id;
27518 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
27519 * before traffic has started.
27520 * A value of 0xff indicates that no pri is assigned to the
27523 uint8_t tc5_pri_queue_id;
27525 * pri assigned to MPLS TC(EXP) 6. This value can only
27526 * be changed before traffic has started.
27527 * A value of 0xff indicates that no pri is assigned to the
27530 uint8_t tc6_pri_queue_id;
27532 * pri assigned to MPLS TC(EXP) 7. This value can only
27533 * be changed before traffic has started.
27534 * A value of 0xff indicates that no pri is assigned to the
27537 uint8_t tc7_pri_queue_id;
27538 uint8_t unused_0[7];
27540 * This field is used in Output records to indicate that the output
27541 * is completely written to RAM. This field should be read as '1'
27542 * to indicate that the output has been completely written.
27543 * When writing a command completion or response to an internal processor,
27544 * the order of writes has to be such that this field is written last.
27549 /*****************************
27550 * hwrm_queue_mplstc2pri_cfg *
27551 *****************************/
27554 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
27555 struct hwrm_queue_mplstc2pri_cfg_input {
27556 /* The HWRM command request type. */
27559 * The completion ring to send the completion event on. This should
27560 * be the NQ ID returned from the `nq_alloc` HWRM command.
27562 uint16_t cmpl_ring;
27564 * The sequence ID is used by the driver for tracking multiple
27565 * commands. This ID is treated as opaque data by the firmware and
27566 * the value is returned in the `hwrm_resp_hdr` upon completion.
27570 * The target ID of the command:
27571 * * 0x0-0xFFF8 - The function ID
27572 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27573 * * 0xFFFD - Reserved for user-space HWRM interface
27576 uint16_t target_id;
27578 * A physical address pointer pointing to a host buffer that the
27579 * command's response data will be written. This can be either a host
27580 * physical address (HPA) or a guest physical address (GPA) and must
27581 * point to a physically contiguous block of memory.
27583 uint64_t resp_addr;
27586 * This bit must be '1' for the mplstc0_pri_queue_id field to be
27589 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
27592 * This bit must be '1' for the mplstc1_pri_queue_id field to be
27595 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
27598 * This bit must be '1' for the mplstc2_pri_queue_id field to be
27601 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
27604 * This bit must be '1' for the mplstc3_pri_queue_id field to be
27607 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
27610 * This bit must be '1' for the mplstc4_pri_queue_id field to be
27613 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
27616 * This bit must be '1' for the mplstc5_pri_queue_id field to be
27619 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
27622 * This bit must be '1' for the mplstc6_pri_queue_id field to be
27625 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
27628 * This bit must be '1' for the mplstc7_pri_queue_id field to be
27631 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
27634 * Port ID of port for which the table is being configured.
27635 * The HWRM needs to check whether this function is allowed
27636 * to configure MPLS TC(EXP)to pri mapping on this port.
27639 uint8_t unused_0[3];
27641 * pri assigned to MPLS TC(EXP) 0. This value can only
27642 * be changed before traffic has started.
27644 uint8_t tc0_pri_queue_id;
27646 * pri assigned to MPLS TC(EXP) 1. This value can only
27647 * be changed before traffic has started.
27649 uint8_t tc1_pri_queue_id;
27651 * pri assigned to MPLS TC(EXP) 2 This value can only
27652 * be changed before traffic has started.
27654 uint8_t tc2_pri_queue_id;
27656 * pri assigned to MPLS TC(EXP) 3. This value can only
27657 * be changed before traffic has started.
27659 uint8_t tc3_pri_queue_id;
27661 * pri assigned to MPLS TC(EXP) 4. This value can only
27662 * be changed before traffic has started.
27664 uint8_t tc4_pri_queue_id;
27666 * pri assigned to MPLS TC(EXP) 5. This value can only
27667 * be changed before traffic has started.
27669 uint8_t tc5_pri_queue_id;
27671 * pri assigned to MPLS TC(EXP) 6. This value can only
27672 * be changed before traffic has started.
27674 uint8_t tc6_pri_queue_id;
27676 * pri assigned to MPLS TC(EXP) 7. This value can only
27677 * be changed before traffic has started.
27679 uint8_t tc7_pri_queue_id;
27682 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
27683 struct hwrm_queue_mplstc2pri_cfg_output {
27684 /* The specific error status for the command. */
27685 uint16_t error_code;
27686 /* The HWRM command request type. */
27688 /* The sequence ID from the original command. */
27690 /* The length of the response data in number of bytes. */
27692 uint8_t unused_0[7];
27694 * This field is used in Output records to indicate that the output
27695 * is completely written to RAM. This field should be read as '1'
27696 * to indicate that the output has been completely written.
27697 * When writing a command completion or response to an internal processor,
27698 * the order of writes has to be such that this field is written last.
27703 /*******************
27704 * hwrm_vnic_alloc *
27705 *******************/
27708 /* hwrm_vnic_alloc_input (size:192b/24B) */
27709 struct hwrm_vnic_alloc_input {
27710 /* The HWRM command request type. */
27713 * The completion ring to send the completion event on. This should
27714 * be the NQ ID returned from the `nq_alloc` HWRM command.
27716 uint16_t cmpl_ring;
27718 * The sequence ID is used by the driver for tracking multiple
27719 * commands. This ID is treated as opaque data by the firmware and
27720 * the value is returned in the `hwrm_resp_hdr` upon completion.
27724 * The target ID of the command:
27725 * * 0x0-0xFFF8 - The function ID
27726 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27727 * * 0xFFFD - Reserved for user-space HWRM interface
27730 uint16_t target_id;
27732 * A physical address pointer pointing to a host buffer that the
27733 * command's response data will be written. This can be either a host
27734 * physical address (HPA) or a guest physical address (GPA) and must
27735 * point to a physically contiguous block of memory.
27737 uint64_t resp_addr;
27740 * When this bit is '1', this VNIC is requested to
27741 * be the default VNIC for this function.
27743 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
27744 uint8_t unused_0[4];
27747 /* hwrm_vnic_alloc_output (size:128b/16B) */
27748 struct hwrm_vnic_alloc_output {
27749 /* The specific error status for the command. */
27750 uint16_t error_code;
27751 /* The HWRM command request type. */
27753 /* The sequence ID from the original command. */
27755 /* The length of the response data in number of bytes. */
27757 /* Logical vnic ID */
27759 uint8_t unused_0[3];
27761 * This field is used in Output records to indicate that the output
27762 * is completely written to RAM. This field should be read as '1'
27763 * to indicate that the output has been completely written.
27764 * When writing a command completion or response to an internal processor,
27765 * the order of writes has to be such that this field is written last.
27770 /******************
27772 ******************/
27775 /* hwrm_vnic_free_input (size:192b/24B) */
27776 struct hwrm_vnic_free_input {
27777 /* The HWRM command request type. */
27780 * The completion ring to send the completion event on. This should
27781 * be the NQ ID returned from the `nq_alloc` HWRM command.
27783 uint16_t cmpl_ring;
27785 * The sequence ID is used by the driver for tracking multiple
27786 * commands. This ID is treated as opaque data by the firmware and
27787 * the value is returned in the `hwrm_resp_hdr` upon completion.
27791 * The target ID of the command:
27792 * * 0x0-0xFFF8 - The function ID
27793 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27794 * * 0xFFFD - Reserved for user-space HWRM interface
27797 uint16_t target_id;
27799 * A physical address pointer pointing to a host buffer that the
27800 * command's response data will be written. This can be either a host
27801 * physical address (HPA) or a guest physical address (GPA) and must
27802 * point to a physically contiguous block of memory.
27804 uint64_t resp_addr;
27805 /* Logical vnic ID */
27807 uint8_t unused_0[4];
27810 /* hwrm_vnic_free_output (size:128b/16B) */
27811 struct hwrm_vnic_free_output {
27812 /* The specific error status for the command. */
27813 uint16_t error_code;
27814 /* The HWRM command request type. */
27816 /* The sequence ID from the original command. */
27818 /* The length of the response data in number of bytes. */
27820 uint8_t unused_0[7];
27822 * This field is used in Output records to indicate that the output
27823 * is completely written to RAM. This field should be read as '1'
27824 * to indicate that the output has been completely written.
27825 * When writing a command completion or response to an internal processor,
27826 * the order of writes has to be such that this field is written last.
27836 /* hwrm_vnic_cfg_input (size:384b/48B) */
27837 struct hwrm_vnic_cfg_input {
27838 /* The HWRM command request type. */
27841 * The completion ring to send the completion event on. This should
27842 * be the NQ ID returned from the `nq_alloc` HWRM command.
27844 uint16_t cmpl_ring;
27846 * The sequence ID is used by the driver for tracking multiple
27847 * commands. This ID is treated as opaque data by the firmware and
27848 * the value is returned in the `hwrm_resp_hdr` upon completion.
27852 * The target ID of the command:
27853 * * 0x0-0xFFF8 - The function ID
27854 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27855 * * 0xFFFD - Reserved for user-space HWRM interface
27858 uint16_t target_id;
27860 * A physical address pointer pointing to a host buffer that the
27861 * command's response data will be written. This can be either a host
27862 * physical address (HPA) or a guest physical address (GPA) and must
27863 * point to a physically contiguous block of memory.
27865 uint64_t resp_addr;
27868 * When this bit is '1', the VNIC is requested to
27869 * be the default VNIC for the function.
27871 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
27874 * When this bit is '1', the VNIC is being configured to
27875 * strip VLAN in the RX path.
27876 * If set to '0', then VLAN stripping is disabled on
27879 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
27882 * When this bit is '1', the VNIC is being configured to
27883 * buffer receive packets in the hardware until the host
27884 * posts new receive buffers.
27885 * If set to '0', then bd_stall is being configured to be
27886 * disabled on this VNIC.
27888 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
27891 * When this bit is '1', the VNIC is being configured to
27892 * receive both RoCE and non-RoCE traffic.
27893 * If set to '0', then this VNIC is not configured to be
27894 * operating in dual VNIC mode.
27896 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
27899 * When this flag is set to '1', the VNIC is requested to
27900 * be configured to receive only RoCE traffic.
27901 * If this flag is set to '0', then this flag shall be
27902 * ignored by the HWRM.
27903 * If roce_dual_vnic_mode flag is set to '1'
27904 * or roce_mirroring_capable_vnic_mode flag to 1,
27905 * then the HWRM client shall not set this flag to '1'.
27907 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
27910 * When a VNIC uses one destination ring group for certain
27911 * application (e.g. Receive Flow Steering) where
27912 * exact match is used to direct packets to a VNIC with one
27913 * destination ring group only, there is no need to configure
27914 * RSS indirection table for that VNIC as only one destination
27915 * ring group is used.
27917 * This flag is used to enable a mode where
27918 * RSS is enabled in the VNIC using a RSS context
27919 * for computing RSS hash but the RSS indirection table is
27920 * not configured using hwrm_vnic_rss_cfg.
27922 * If this mode is enabled, then the driver should not program
27923 * RSS indirection table for the RSS context that is used for
27924 * computing RSS hash only.
27926 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
27929 * When this bit is '1', the VNIC is being configured to
27930 * receive both RoCE and non-RoCE traffic, but forward only the
27931 * RoCE traffic further. Also, RoCE traffic can be mirrored to
27934 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
27938 * This bit must be '1' for the dflt_ring_grp field to be
27941 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
27944 * This bit must be '1' for the rss_rule field to be
27947 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
27950 * This bit must be '1' for the cos_rule field to be
27953 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
27956 * This bit must be '1' for the lb_rule field to be
27959 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
27962 * This bit must be '1' for the mru field to be
27965 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
27968 * This bit must be '1' for the default_rx_ring_id field to be
27971 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
27974 * This bit must be '1' for the default_cmpl_ring_id field to be
27977 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
27979 /* This bit must be '1' for the queue_id field to be configured. */
27980 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
27982 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
27983 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
27985 /* Logical vnic ID */
27988 * Default Completion ring for the VNIC. This ring will
27989 * be chosen if packet does not match any RSS rules and if
27990 * there is no COS rule.
27992 uint16_t dflt_ring_grp;
27994 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
27995 * there is no RSS rule.
27999 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
28000 * there is no COS rule.
28004 * RSS ID for load balancing rule/table structure.
28005 * 0xFF... (All Fs) if there is no LB rule.
28009 * The maximum receive unit of the vnic.
28010 * Each vnic is associated with a function.
28011 * The vnic mru value overwrites the mru setting of the
28012 * associated function.
28013 * The HWRM shall make sure that vnic mru does not exceed
28014 * the mru of the port the function is associated with.
28018 * Default Rx ring for the VNIC. This ring will
28019 * be chosen if packet does not match any RSS rules.
28020 * The aggregation ring associated with the Rx ring is
28021 * implied based on the Rx ring specified when the
28022 * aggregation ring was allocated.
28024 uint16_t default_rx_ring_id;
28026 * Default completion ring for the VNIC. This ring will
28027 * be chosen if packet does not match any RSS rules.
28029 uint16_t default_cmpl_ring_id;
28031 * When specified, only incoming packets classified to the specified CoS
28032 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
28033 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
28034 * ntuple filters with VNIC destination specified are invalid since they
28035 * conflict with the CoS to VNIC steering rules in this mode.
28037 * If this field is not specified, packet to VNIC steering will be
28038 * subject to the standard L2 filter rules and any additional ntuple
28039 * filter rules with destination VNIC specified.
28043 * If the device supports the RX V2 and RX TPA start V2 completion
28044 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
28045 * used to specify the two RX checksum modes supported by these
28046 * completion records.
28048 uint8_t rx_csum_v2_mode;
28050 * When configured with this checksum mode, the number of header
28051 * groups in the delivered packet with a valid IP checksum and
28052 * the number of header groups in the delivered packet with a valid
28053 * L4 checksum are reported. Valid checksums are counted from the
28054 * outermost header group to the innermost header group, stopping at
28055 * the first error. This is the default checksum mode supported if
28056 * the driver doesn't explicitly configure the RX checksum mode.
28058 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
28060 * When configured with this checksum mode, the checksum status is
28061 * reported using 'all ok' mode. In the RX completion record, one
28062 * bit indicates if the IP checksum is valid for all the parsed
28063 * header groups with an IP checksum. Another bit indicates if the
28064 * L4 checksum is valid for all the parsed header groups with an L4
28065 * checksum. The number of header groups that were parsed by the
28066 * chip and passed in the delivered packet is also reported.
28068 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
28070 * Any rx_csum_v2_mode value larger than or equal to this is not
28073 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
28074 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
28075 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
28076 uint8_t unused0[5];
28079 /* hwrm_vnic_cfg_output (size:128b/16B) */
28080 struct hwrm_vnic_cfg_output {
28081 /* The specific error status for the command. */
28082 uint16_t error_code;
28083 /* The HWRM command request type. */
28085 /* The sequence ID from the original command. */
28087 /* The length of the response data in number of bytes. */
28089 uint8_t unused_0[7];
28091 * This field is used in Output records to indicate that the output
28092 * is completely written to RAM. This field should be read as '1'
28093 * to indicate that the output has been completely written.
28094 * When writing a command completion or response to an internal processor,
28095 * the order of writes has to be such that this field is written last.
28100 /******************
28102 ******************/
28105 /* hwrm_vnic_qcfg_input (size:256b/32B) */
28106 struct hwrm_vnic_qcfg_input {
28107 /* The HWRM command request type. */
28110 * The completion ring to send the completion event on. This should
28111 * be the NQ ID returned from the `nq_alloc` HWRM command.
28113 uint16_t cmpl_ring;
28115 * The sequence ID is used by the driver for tracking multiple
28116 * commands. This ID is treated as opaque data by the firmware and
28117 * the value is returned in the `hwrm_resp_hdr` upon completion.
28121 * The target ID of the command:
28122 * * 0x0-0xFFF8 - The function ID
28123 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28124 * * 0xFFFD - Reserved for user-space HWRM interface
28127 uint16_t target_id;
28129 * A physical address pointer pointing to a host buffer that the
28130 * command's response data will be written. This can be either a host
28131 * physical address (HPA) or a guest physical address (GPA) and must
28132 * point to a physically contiguous block of memory.
28134 uint64_t resp_addr;
28137 * This bit must be '1' for the vf_id_valid field to be
28140 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
28141 /* Logical vnic ID */
28143 /* ID of Virtual Function whose VNIC resource is being queried. */
28145 uint8_t unused_0[6];
28148 /* hwrm_vnic_qcfg_output (size:256b/32B) */
28149 struct hwrm_vnic_qcfg_output {
28150 /* The specific error status for the command. */
28151 uint16_t error_code;
28152 /* The HWRM command request type. */
28154 /* The sequence ID from the original command. */
28156 /* The length of the response data in number of bytes. */
28158 /* Default Completion ring for the VNIC. */
28159 uint16_t dflt_ring_grp;
28161 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
28162 * there is no RSS rule.
28166 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
28167 * there is no COS rule.
28171 * RSS ID for load balancing rule/table structure.
28172 * 0xFF... (All Fs) if there is no LB rule.
28175 /* The maximum receive unit of the vnic. */
28177 uint8_t unused_0[2];
28180 * When this bit is '1', the VNIC is the default VNIC for
28183 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
28186 * When this bit is '1', the VNIC is configured to
28187 * strip VLAN in the RX path.
28188 * If set to '0', then VLAN stripping is disabled on
28191 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
28194 * When this bit is '1', the VNIC is configured to
28195 * buffer receive packets in the hardware until the host
28196 * posts new receive buffers.
28197 * If set to '0', then bd_stall is disabled on
28200 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
28203 * When this bit is '1', the VNIC is configured to
28204 * receive both RoCE and non-RoCE traffic.
28205 * If set to '0', then this VNIC is not configured to
28206 * operate in dual VNIC mode.
28208 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
28211 * When this flag is set to '1', the VNIC is configured to
28212 * receive only RoCE traffic.
28213 * When this flag is set to '0', the VNIC is not configured
28214 * to receive only RoCE traffic.
28215 * If roce_dual_vnic_mode flag and this flag both are set
28216 * to '1', then it is an invalid configuration of the
28217 * VNIC. The HWRM should not allow that type of
28218 * mis-configuration by HWRM clients.
28220 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
28223 * When a VNIC uses one destination ring group for certain
28224 * application (e.g. Receive Flow Steering) where
28225 * exact match is used to direct packets to a VNIC with one
28226 * destination ring group only, there is no need to configure
28227 * RSS indirection table for that VNIC as only one destination
28228 * ring group is used.
28230 * When this bit is set to '1', then the VNIC is enabled in a
28231 * mode where RSS is enabled in the VNIC using a RSS context
28232 * for computing RSS hash but the RSS indirection table is
28235 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
28238 * When this bit is '1', the VNIC is configured to
28239 * receive both RoCE and non-RoCE traffic, but forward only
28240 * RoCE traffic further. Also RoCE traffic can be mirrored to
28243 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
28246 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
28247 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
28248 * queue association.
28252 * If the device supports the RX V2 and RX TPA start V2 completion
28253 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
28254 * used to specify the current RX checksum mode configured for all the
28255 * RX rings of a VNIC.
28257 uint8_t rx_csum_v2_mode;
28259 * This value indicates that the VNIC is configured to use the
28260 * default RX checksum mode for all the rings associated with this
28263 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
28265 * This value indicates that the VNIC is configured to use the RX
28266 * checksum ‘all_ok’ mode for all the rings associated with this
28269 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
28271 * Any rx_csum_v2_mode value larger than or equal to this is not
28274 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
28275 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
28276 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
28277 uint8_t unused_1[4];
28279 * This field is used in Output records to indicate that the output
28280 * is completely written to RAM. This field should be read as '1'
28281 * to indicate that the output has been completely written.
28282 * When writing a command completion or response to an internal processor,
28283 * the order of writes has to be such that this field is written last.
28288 /*******************
28289 * hwrm_vnic_qcaps *
28290 *******************/
28293 /* hwrm_vnic_qcaps_input (size:192b/24B) */
28294 struct hwrm_vnic_qcaps_input {
28295 /* The HWRM command request type. */
28298 * The completion ring to send the completion event on. This should
28299 * be the NQ ID returned from the `nq_alloc` HWRM command.
28301 uint16_t cmpl_ring;
28303 * The sequence ID is used by the driver for tracking multiple
28304 * commands. This ID is treated as opaque data by the firmware and
28305 * the value is returned in the `hwrm_resp_hdr` upon completion.
28309 * The target ID of the command:
28310 * * 0x0-0xFFF8 - The function ID
28311 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28312 * * 0xFFFD - Reserved for user-space HWRM interface
28315 uint16_t target_id;
28317 * A physical address pointer pointing to a host buffer that the
28318 * command's response data will be written. This can be either a host
28319 * physical address (HPA) or a guest physical address (GPA) and must
28320 * point to a physically contiguous block of memory.
28322 uint64_t resp_addr;
28324 uint8_t unused_0[4];
28327 /* hwrm_vnic_qcaps_output (size:192b/24B) */
28328 struct hwrm_vnic_qcaps_output {
28329 /* The specific error status for the command. */
28330 uint16_t error_code;
28331 /* The HWRM command request type. */
28333 /* The sequence ID from the original command. */
28335 /* The length of the response data in number of bytes. */
28337 /* The maximum receive unit that is settable on a vnic. */
28339 uint8_t unused_0[2];
28342 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
28345 * When this bit is '1', the capability of stripping VLAN in
28346 * the RX path is supported on VNIC(s).
28347 * If set to '0', then VLAN stripping capability is
28348 * not supported on VNIC(s).
28350 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
28353 * When this bit is '1', the capability to buffer receive
28354 * packets in the hardware until the host posts new receive buffers
28355 * is supported on VNIC(s).
28356 * If set to '0', then bd_stall capability is not supported
28359 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
28362 * When this bit is '1', the capability to
28363 * receive both RoCE and non-RoCE traffic on VNIC(s) is
28365 * If set to '0', then the capability to receive
28366 * both RoCE and non-RoCE traffic on VNIC(s) is
28369 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
28372 * When this bit is set to '1', the capability to configure
28373 * a VNIC to receive only RoCE traffic is supported.
28374 * When this flag is set to '0', the VNIC capability to
28375 * configure to receive only RoCE traffic is not supported.
28377 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
28380 * When this bit is set to '1', then the capability to enable
28381 * a VNIC in a mode where RSS context without configuring
28382 * RSS indirection table is supported (for RSS hash computation).
28383 * When this bit is set to '0', then a VNIC can not be configured
28384 * with a mode to enable RSS context without configuring RSS
28385 * indirection table.
28387 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
28390 * When this bit is '1', the capability to
28391 * mirror the the RoCE traffic is supported.
28392 * If set to '0', then the capability to mirror the
28393 * RoCE traffic is not supported.
28395 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
28398 * When this bit is '1', the outermost RSS hashing capability
28399 * is supported. If set to '0', then the outermost RSS hashing
28400 * capability is not supported.
28402 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
28405 * When this bit is '1', it indicates that firmware supports the
28406 * ability to steer incoming packets from one CoS queue to one
28407 * VNIC. This optional feature can then be enabled
28408 * using HWRM_VNIC_CFG on any VNIC. This feature is only
28409 * available when NVM option “enable_cos_classfication” is set
28410 * to 1. If set to '0', firmware does not support this feature.
28412 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
28415 * When this bit is '1', it indicates that HW and firmware supports
28416 * the use of RX V2 and RX TPA start V2 completion records for all
28417 * the RX rings of a VNIC. Once set, this feature is mandatory to
28418 * be used for the RX rings of the VNIC. Additionally, two new RX
28419 * checksum features supported by these ompletion records can be
28420 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
28421 * HW and the firmware does not support this feature.
28423 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
28426 * This field advertises the maximum concurrent TPA aggregations
28427 * supported by the VNIC on new devices that support TPA v2.
28428 * '0' means that TPA v2 is not supported.
28430 uint16_t max_aggs_supported;
28431 uint8_t unused_1[5];
28433 * This field is used in Output records to indicate that the output
28434 * is completely written to RAM. This field should be read as '1'
28435 * to indicate that the output has been completely written.
28436 * When writing a command completion or response to an internal processor,
28437 * the order of writes has to be such that this field is written last.
28442 /*********************
28443 * hwrm_vnic_tpa_cfg *
28444 *********************/
28447 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
28448 struct hwrm_vnic_tpa_cfg_input {
28449 /* The HWRM command request type. */
28452 * The completion ring to send the completion event on. This should
28453 * be the NQ ID returned from the `nq_alloc` HWRM command.
28455 uint16_t cmpl_ring;
28457 * The sequence ID is used by the driver for tracking multiple
28458 * commands. This ID is treated as opaque data by the firmware and
28459 * the value is returned in the `hwrm_resp_hdr` upon completion.
28463 * The target ID of the command:
28464 * * 0x0-0xFFF8 - The function ID
28465 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28466 * * 0xFFFD - Reserved for user-space HWRM interface
28469 uint16_t target_id;
28471 * A physical address pointer pointing to a host buffer that the
28472 * command's response data will be written. This can be either a host
28473 * physical address (HPA) or a guest physical address (GPA) and must
28474 * point to a physically contiguous block of memory.
28476 uint64_t resp_addr;
28479 * When this bit is '1', the VNIC shall be configured to
28480 * perform transparent packet aggregation (TPA) of
28481 * non-tunneled TCP packets.
28483 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
28486 * When this bit is '1', the VNIC shall be configured to
28487 * perform transparent packet aggregation (TPA) of
28488 * tunneled TCP packets.
28490 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
28493 * When this bit is '1', the VNIC shall be configured to
28494 * perform transparent packet aggregation (TPA) according
28495 * to Windows Receive Segment Coalescing (RSC) rules.
28497 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
28500 * When this bit is '1', the VNIC shall be configured to
28501 * perform transparent packet aggregation (TPA) according
28502 * to Linux Generic Receive Offload (GRO) rules.
28504 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
28507 * When this bit is '1', the VNIC shall be configured to
28508 * perform transparent packet aggregation (TPA) for TCP
28509 * packets with IP ECN set to non-zero.
28511 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
28514 * When this bit is '1', the VNIC shall be configured to
28515 * perform transparent packet aggregation (TPA) for
28516 * GRE tunneled TCP packets only if all packets have the
28517 * same GRE sequence.
28519 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
28522 * When this bit is '1' and the GRO mode is enabled,
28523 * the VNIC shall be configured to
28524 * perform transparent packet aggregation (TPA) for
28525 * TCP/IPv4 packets with consecutively increasing IPIDs.
28526 * In other words, the last packet that is being
28527 * aggregated to an already existing aggregation context
28528 * shall have IPID 1 more than the IPID of the last packet
28529 * that was aggregated in that aggregation context.
28531 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
28534 * When this bit is '1' and the GRO mode is enabled,
28535 * the VNIC shall be configured to
28536 * perform transparent packet aggregation (TPA) for
28537 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
28540 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
28543 * When this bit is '1' and the GRO mode is enabled,
28544 * the VNIC shall DMA payload data using GRO rules.
28545 * When this bit is '0', the VNIC shall DMA payload data
28546 * using the more efficient LRO rules of filling all
28547 * aggregation buffers.
28549 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
28553 * This bit must be '1' for the max_agg_segs field to be
28556 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
28558 * This bit must be '1' for the max_aggs field to be
28561 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
28563 * This bit must be '1' for the max_agg_timer field to be
28566 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
28567 /* deprecated bit. Do not use!!! */
28568 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
28569 /* Logical vnic ID */
28572 * This is the maximum number of TCP segments that can
28573 * be aggregated (unit is Log2). Max value is 31. On new
28574 * devices supporting TPA v2, the unit is multiples of 4 and
28575 * valid values are > 0 and <= 63.
28577 uint16_t max_agg_segs;
28579 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
28581 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
28583 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
28585 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
28586 /* Any segment size larger than this is not valid */
28587 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
28588 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
28589 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
28591 * This is the maximum number of aggregations this VNIC is
28592 * allowed (unit is Log2). Max value is 7. On new devices
28593 * supporting TPA v2, this is in unit of 1 and must be > 0
28594 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
28595 * to enable TPA v2.
28598 /* 1 aggregation */
28599 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
28600 /* 2 aggregations */
28601 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
28602 /* 4 aggregations */
28603 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
28604 /* 8 aggregations */
28605 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
28606 /* 16 aggregations */
28607 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
28608 /* Any aggregation size larger than this is not valid */
28609 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
28610 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
28611 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
28612 uint8_t unused_0[2];
28614 * This is the maximum amount of time allowed for
28615 * an aggregation context to complete after it was initiated.
28617 uint32_t max_agg_timer;
28619 * This is the minimum amount of payload length required to
28620 * start an aggregation context. This field is deprecated and
28621 * should be set to 0. The minimum length is set by firmware
28622 * and can be queried using hwrm_vnic_tpa_qcfg.
28624 uint32_t min_agg_len;
28627 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
28628 struct hwrm_vnic_tpa_cfg_output {
28629 /* The specific error status for the command. */
28630 uint16_t error_code;
28631 /* The HWRM command request type. */
28633 /* The sequence ID from the original command. */
28635 /* The length of the response data in number of bytes. */
28637 uint8_t unused_0[7];
28639 * This field is used in Output records to indicate that the output
28640 * is completely written to RAM. This field should be read as '1'
28641 * to indicate that the output has been completely written.
28642 * When writing a command completion or response to an internal processor,
28643 * the order of writes has to be such that this field is written last.
28648 /*********************
28649 * hwrm_vnic_rss_cfg *
28650 *********************/
28653 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
28654 struct hwrm_vnic_rss_cfg_input {
28655 /* The HWRM command request type. */
28658 * The completion ring to send the completion event on. This should
28659 * be the NQ ID returned from the `nq_alloc` HWRM command.
28661 uint16_t cmpl_ring;
28663 * The sequence ID is used by the driver for tracking multiple
28664 * commands. This ID is treated as opaque data by the firmware and
28665 * the value is returned in the `hwrm_resp_hdr` upon completion.
28669 * The target ID of the command:
28670 * * 0x0-0xFFF8 - The function ID
28671 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28672 * * 0xFFFD - Reserved for user-space HWRM interface
28675 uint16_t target_id;
28677 * A physical address pointer pointing to a host buffer that the
28678 * command's response data will be written. This can be either a host
28679 * physical address (HPA) or a guest physical address (GPA) and must
28680 * point to a physically contiguous block of memory.
28682 uint64_t resp_addr;
28683 uint32_t hash_type;
28685 * When this bit is '1', the RSS hash shall be computed
28686 * over source and destination IPv4 addresses of IPv4
28689 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
28691 * When this bit is '1', the RSS hash shall be computed
28692 * over source/destination IPv4 addresses and
28693 * source/destination ports of TCP/IPv4 packets.
28695 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
28697 * When this bit is '1', the RSS hash shall be computed
28698 * over source/destination IPv4 addresses and
28699 * source/destination ports of UDP/IPv4 packets.
28701 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
28703 * When this bit is '1', the RSS hash shall be computed
28704 * over source and destination IPv4 addresses of IPv6
28707 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
28709 * When this bit is '1', the RSS hash shall be computed
28710 * over source/destination IPv6 addresses and
28711 * source/destination ports of TCP/IPv6 packets.
28713 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
28715 * When this bit is '1', the RSS hash shall be computed
28716 * over source/destination IPv6 addresses and
28717 * source/destination ports of UDP/IPv6 packets.
28719 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
28720 /* VNIC ID of VNIC associated with RSS table being configured. */
28723 * Specifies which VNIC ring table pair to configure.
28724 * Valid values range from 0 to 7.
28726 uint8_t ring_table_pair_index;
28727 /* Flags to specify different RSS hash modes. */
28728 uint8_t hash_mode_flags;
28730 * When this bit is '1', it indicates using current RSS
28731 * hash mode setting configured in the device.
28733 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
28736 * When this bit is '1', it indicates requesting support of
28737 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
28738 * l4.src, l4.dest} for tunnel packets. For none-tunnel
28739 * packets, the RSS hash is computed over the normal
28740 * src/dest l3 and src/dest l4 headers.
28742 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
28745 * When this bit is '1', it indicates requesting support of
28746 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
28747 * tunnel packets. For none-tunnel packets, the RSS hash is
28748 * computed over the normal src/dest l3 headers.
28750 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
28753 * When this bit is '1', it indicates requesting support of
28754 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
28755 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
28756 * packets, the RSS hash is computed over the normal
28757 * src/dest l3 and src/dest l4 headers.
28759 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
28762 * When this bit is '1', it indicates requesting support of
28763 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
28764 * tunnel packets. For none-tunnel packets, the RSS hash is
28765 * computed over the normal src/dest l3 headers.
28767 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
28769 /* This is the address for rss ring group table */
28770 uint64_t ring_grp_tbl_addr;
28771 /* This is the address for rss hash key table */
28772 uint64_t hash_key_tbl_addr;
28773 /* Index to the rss indirection table. */
28774 uint16_t rss_ctx_idx;
28775 uint8_t unused_1[6];
28778 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
28779 struct hwrm_vnic_rss_cfg_output {
28780 /* The specific error status for the command. */
28781 uint16_t error_code;
28782 /* The HWRM command request type. */
28784 /* The sequence ID from the original command. */
28786 /* The length of the response data in number of bytes. */
28788 uint8_t unused_0[7];
28790 * This field is used in Output records to indicate that the output
28791 * is completely written to RAM. This field should be read as '1'
28792 * to indicate that the output has been completely written.
28793 * When writing a command completion or response to an internal processor,
28794 * the order of writes has to be such that this field is written last.
28799 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
28800 struct hwrm_vnic_rss_cfg_cmd_err {
28802 * command specific error codes that goes to
28803 * the cmd_err field in Common HWRM Error Response.
28806 /* Unknown error */
28807 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
28810 * Unable to change global RSS mode to outer due to all active
28811 * interfaces are not ready to support outer RSS hashing.
28813 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
28815 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
28816 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
28817 uint8_t unused_0[7];
28820 /**********************
28821 * hwrm_vnic_rss_qcfg *
28822 **********************/
28825 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
28826 struct hwrm_vnic_rss_qcfg_input {
28827 /* The HWRM command request type. */
28830 * The completion ring to send the completion event on. This should
28831 * be the NQ ID returned from the `nq_alloc` HWRM command.
28833 uint16_t cmpl_ring;
28835 * The sequence ID is used by the driver for tracking multiple
28836 * commands. This ID is treated as opaque data by the firmware and
28837 * the value is returned in the `hwrm_resp_hdr` upon completion.
28841 * The target ID of the command:
28842 * * 0x0-0xFFF8 - The function ID
28843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28844 * * 0xFFFD - Reserved for user-space HWRM interface
28847 uint16_t target_id;
28849 * A physical address pointer pointing to a host buffer that the
28850 * command's response data will be written. This can be either a host
28851 * physical address (HPA) or a guest physical address (GPA) and must
28852 * point to a physically contiguous block of memory.
28854 uint64_t resp_addr;
28855 /* Index to the rss indirection table. */
28856 uint16_t rss_ctx_idx;
28857 uint8_t unused_0[6];
28860 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
28861 struct hwrm_vnic_rss_qcfg_output {
28862 /* The specific error status for the command. */
28863 uint16_t error_code;
28864 /* The HWRM command request type. */
28866 /* The sequence ID from the original command. */
28868 /* The length of the response data in number of bytes. */
28870 uint32_t hash_type;
28872 * When this bit is '1', the RSS hash shall be computed
28873 * over source and destination IPv4 addresses of IPv4
28876 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
28878 * When this bit is '1', the RSS hash shall be computed
28879 * over source/destination IPv4 addresses and
28880 * source/destination ports of TCP/IPv4 packets.
28882 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
28884 * When this bit is '1', the RSS hash shall be computed
28885 * over source/destination IPv4 addresses and
28886 * source/destination ports of UDP/IPv4 packets.
28888 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
28890 * When this bit is '1', the RSS hash shall be computed
28891 * over source and destination IPv4 addresses of IPv6
28894 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
28896 * When this bit is '1', the RSS hash shall be computed
28897 * over source/destination IPv6 addresses and
28898 * source/destination ports of TCP/IPv6 packets.
28900 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
28902 * When this bit is '1', the RSS hash shall be computed
28903 * over source/destination IPv6 addresses and
28904 * source/destination ports of UDP/IPv6 packets.
28906 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
28907 uint8_t unused_0[4];
28908 /* This is the value of rss hash key */
28909 uint32_t hash_key[10];
28910 /* Flags to specify different RSS hash modes. */
28911 uint8_t hash_mode_flags;
28913 * When this bit is '1', it indicates using current RSS
28914 * hash mode setting configured in the device.
28916 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
28919 * When this bit is '1', it indicates requesting support of
28920 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
28921 * l4.src, l4.dest} for tunnel packets. For none-tunnel
28922 * packets, the RSS hash is computed over the normal
28923 * src/dest l3 and src/dest l4 headers.
28925 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
28928 * When this bit is '1', it indicates requesting support of
28929 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
28930 * tunnel packets. For none-tunnel packets, the RSS hash is
28931 * computed over the normal src/dest l3 headers.
28933 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
28936 * When this bit is '1', it indicates requesting support of
28937 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
28938 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
28939 * packets, the RSS hash is computed over the normal
28940 * src/dest l3 and src/dest l4 headers.
28942 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
28945 * When this bit is '1', it indicates requesting support of
28946 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
28947 * tunnel packets. For none-tunnel packets, the RSS hash is
28948 * computed over the normal src/dest l3 headers.
28950 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
28952 uint8_t unused_1[6];
28954 * This field is used in Output records to indicate that the output
28955 * is completely written to RAM. This field should be read as '1'
28956 * to indicate that the output has been completely written.
28957 * When writing a command completion or response to an internal processor,
28958 * the order of writes has to be such that this field is written last.
28963 /**************************
28964 * hwrm_vnic_plcmodes_cfg *
28965 **************************/
28968 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
28969 struct hwrm_vnic_plcmodes_cfg_input {
28970 /* The HWRM command request type. */
28973 * The completion ring to send the completion event on. This should
28974 * be the NQ ID returned from the `nq_alloc` HWRM command.
28976 uint16_t cmpl_ring;
28978 * The sequence ID is used by the driver for tracking multiple
28979 * commands. This ID is treated as opaque data by the firmware and
28980 * the value is returned in the `hwrm_resp_hdr` upon completion.
28984 * The target ID of the command:
28985 * * 0x0-0xFFF8 - The function ID
28986 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28987 * * 0xFFFD - Reserved for user-space HWRM interface
28990 uint16_t target_id;
28992 * A physical address pointer pointing to a host buffer that the
28993 * command's response data will be written. This can be either a host
28994 * physical address (HPA) or a guest physical address (GPA) and must
28995 * point to a physically contiguous block of memory.
28997 uint64_t resp_addr;
29000 * When this bit is '1', the VNIC shall be configured to
29001 * use regular placement algorithm.
29002 * By default, the regular placement algorithm shall be
29003 * enabled on the VNIC.
29005 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
29008 * When this bit is '1', the VNIC shall be configured
29009 * use the jumbo placement algorithm.
29011 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
29014 * When this bit is '1', the VNIC shall be configured
29015 * to enable Header-Data split for IPv4 packets according
29016 * to the following rules:
29017 * # If the packet is identified as TCP/IPv4, then the
29018 * packet is split at the beginning of the TCP payload.
29019 * # If the packet is identified as UDP/IPv4, then the
29020 * packet is split at the beginning of UDP payload.
29021 * # If the packet is identified as non-TCP and non-UDP
29022 * IPv4 packet, then the packet is split at the beginning
29023 * of the upper layer protocol header carried in the IPv4
29026 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
29029 * When this bit is '1', the VNIC shall be configured
29030 * to enable Header-Data split for IPv6 packets according
29031 * to the following rules:
29032 * # If the packet is identified as TCP/IPv6, then the
29033 * packet is split at the beginning of the TCP payload.
29034 * # If the packet is identified as UDP/IPv6, then the
29035 * packet is split at the beginning of UDP payload.
29036 * # If the packet is identified as non-TCP and non-UDP
29037 * IPv6 packet, then the packet is split at the beginning
29038 * of the upper layer protocol header carried in the IPv6
29041 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
29044 * When this bit is '1', the VNIC shall be configured
29045 * to enable Header-Data split for FCoE packets at the
29046 * beginning of FC payload.
29048 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
29051 * When this bit is '1', the VNIC shall be configured
29052 * to enable Header-Data split for RoCE packets at the
29053 * beginning of RoCE payload (after BTH/GRH headers).
29055 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
29058 * When this bit is '1', the VNIC shall be configured use the virtio
29059 * placement algorithm. This feature can only be configured when
29060 * proxy mode is supported on the function.
29062 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
29066 * This bit must be '1' for the jumbo_thresh_valid field to be
29069 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
29072 * This bit must be '1' for the hds_offset_valid field to be
29075 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
29078 * This bit must be '1' for the hds_threshold_valid field to be
29081 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
29084 * This bit must be '1' for the max_bds_valid field to be
29087 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
29089 /* Logical vnic ID */
29092 * When jumbo placement algorithm is enabled, this value
29093 * is used to determine the threshold for jumbo placement.
29094 * Packets with length larger than this value will be
29095 * placed according to the jumbo placement algorithm.
29097 uint16_t jumbo_thresh;
29099 * This value is used to determine the offset into
29100 * packet buffer where the split data (payload) will be
29101 * placed according to one of HDS placement algorithm.
29103 * The lengths of packet buffers provided for split data
29104 * shall be larger than this value.
29106 uint16_t hds_offset;
29108 * When one of the HDS placement algorithm is enabled, this
29109 * value is used to determine the threshold for HDS
29111 * Packets with length larger than this value will be
29112 * placed according to the HDS placement algorithm.
29113 * This value shall be in multiple of 4 bytes.
29115 uint16_t hds_threshold;
29117 * When virtio placement algorithm is enabled, this
29118 * value is used to determine the the maximum number of BDs
29119 * that can be used to place an Rx Packet.
29120 * If an incoming packet does not fit in the buffers described
29121 * by the max BDs, the packet will be dropped and an error
29122 * will be reported in the completion. Valid values for this
29123 * field are between 1 and 8. If the VNIC uses header-data-
29124 * separation and/or TPA with buffer spanning enabled, valid
29125 * values for this field are between 2 and 8.
29126 * This feature can only be configured when proxy mode is
29127 * supported on the function.
29130 uint8_t unused_0[4];
29133 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
29134 struct hwrm_vnic_plcmodes_cfg_output {
29135 /* The specific error status for the command. */
29136 uint16_t error_code;
29137 /* The HWRM command request type. */
29139 /* The sequence ID from the original command. */
29141 /* The length of the response data in number of bytes. */
29143 uint8_t unused_0[7];
29145 * This field is used in Output records to indicate that the output
29146 * is completely written to RAM. This field should be read as '1'
29147 * to indicate that the output has been completely written.
29148 * When writing a command completion or response to an internal
29149 * processor, the order of writes has to be such that this field is
29155 /***************************
29156 * hwrm_vnic_plcmodes_qcfg *
29157 ***************************/
29160 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
29161 struct hwrm_vnic_plcmodes_qcfg_input {
29162 /* The HWRM command request type. */
29165 * The completion ring to send the completion event on. This should
29166 * be the NQ ID returned from the `nq_alloc` HWRM command.
29168 uint16_t cmpl_ring;
29170 * The sequence ID is used by the driver for tracking multiple
29171 * commands. This ID is treated as opaque data by the firmware and
29172 * the value is returned in the `hwrm_resp_hdr` upon completion.
29176 * The target ID of the command:
29177 * * 0x0-0xFFF8 - The function ID
29178 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29179 * * 0xFFFD - Reserved for user-space HWRM interface
29182 uint16_t target_id;
29184 * A physical address pointer pointing to a host buffer that the
29185 * command's response data will be written. This can be either a host
29186 * physical address (HPA) or a guest physical address (GPA) and must
29187 * point to a physically contiguous block of memory.
29189 uint64_t resp_addr;
29190 /* Logical vnic ID */
29192 uint8_t unused_0[4];
29195 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
29196 struct hwrm_vnic_plcmodes_qcfg_output {
29197 /* The specific error status for the command. */
29198 uint16_t error_code;
29199 /* The HWRM command request type. */
29201 /* The sequence ID from the original command. */
29203 /* The length of the response data in number of bytes. */
29207 * When this bit is '1', the VNIC is configured to
29208 * use regular placement algorithm.
29210 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
29213 * When this bit is '1', the VNIC is configured to
29214 * use the jumbo placement algorithm.
29216 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
29219 * When this bit is '1', the VNIC is configured
29220 * to enable Header-Data split for IPv4 packets.
29222 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
29225 * When this bit is '1', the VNIC is configured
29226 * to enable Header-Data split for IPv6 packets.
29228 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
29231 * When this bit is '1', the VNIC is configured
29232 * to enable Header-Data split for FCoE packets.
29234 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
29237 * When this bit is '1', the VNIC is configured
29238 * to enable Header-Data split for RoCE packets.
29240 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
29243 * When this bit is '1', the VNIC is configured
29244 * to be the default VNIC of the requesting function.
29246 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
29249 * When this bit is '1', the VNIC is configured to use the virtio
29250 * placement algorithm. This feature can only be configured when
29251 * proxy mode is supported on the function.
29253 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
29256 * When jumbo placement algorithm is enabled, this value
29257 * is used to determine the threshold for jumbo placement.
29258 * Packets with length larger than this value will be
29259 * placed according to the jumbo placement algorithm.
29261 uint16_t jumbo_thresh;
29263 * This value is used to determine the offset into
29264 * packet buffer where the split data (payload) will be
29265 * placed according to one of HDS placement algorithm.
29267 * The lengths of packet buffers provided for split data
29268 * shall be larger than this value.
29270 uint16_t hds_offset;
29272 * When one of the HDS placement algorithm is enabled, this
29273 * value is used to determine the threshold for HDS
29275 * Packets with length larger than this value will be
29276 * placed according to the HDS placement algorithm.
29277 * This value shall be in multiple of 4 bytes.
29279 uint16_t hds_threshold;
29281 * When virtio placement algorithm is enabled, this
29282 * value is used to determine the the maximum number of BDs
29283 * that can be used to place an Rx Packet.
29284 * If an incoming packet does not fit in the buffers described
29285 * by the max BDs, the packet will be dropped and an error
29286 * will be reported in the completion. Valid values for this
29287 * field are between 1 and 8. If the VNIC uses header-data-
29288 * separation and/or TPA with buffer spanning enabled, valid
29289 * values for this field are between 2 and 8.
29290 * This feature can only be configured when proxy mode is supported
29294 uint8_t unused_0[3];
29296 * This field is used in Output records to indicate that the output
29297 * is completely written to RAM. This field should be read as '1'
29298 * to indicate that the output has been completely written.
29299 * When writing a command completion or response to an internal
29300 * processor, the order of writes has to be such that this field is
29306 /**********************************
29307 * hwrm_vnic_rss_cos_lb_ctx_alloc *
29308 **********************************/
29311 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
29312 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
29313 /* The HWRM command request type. */
29316 * The completion ring to send the completion event on. This should
29317 * be the NQ ID returned from the `nq_alloc` HWRM command.
29319 uint16_t cmpl_ring;
29321 * The sequence ID is used by the driver for tracking multiple
29322 * commands. This ID is treated as opaque data by the firmware and
29323 * the value is returned in the `hwrm_resp_hdr` upon completion.
29327 * The target ID of the command:
29328 * * 0x0-0xFFF8 - The function ID
29329 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29330 * * 0xFFFD - Reserved for user-space HWRM interface
29333 uint16_t target_id;
29335 * A physical address pointer pointing to a host buffer that the
29336 * command's response data will be written. This can be either a host
29337 * physical address (HPA) or a guest physical address (GPA) and must
29338 * point to a physically contiguous block of memory.
29340 uint64_t resp_addr;
29343 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
29344 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
29345 /* The specific error status for the command. */
29346 uint16_t error_code;
29347 /* The HWRM command request type. */
29349 /* The sequence ID from the original command. */
29351 /* The length of the response data in number of bytes. */
29353 /* rss_cos_lb_ctx_id is 16 b */
29354 uint16_t rss_cos_lb_ctx_id;
29355 uint8_t unused_0[5];
29357 * This field is used in Output records to indicate that the output
29358 * is completely written to RAM. This field should be read as '1'
29359 * to indicate that the output has been completely written.
29360 * When writing a command completion or response to an internal processor,
29361 * the order of writes has to be such that this field is written last.
29366 /*********************************
29367 * hwrm_vnic_rss_cos_lb_ctx_free *
29368 *********************************/
29371 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
29372 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
29373 /* The HWRM command request type. */
29376 * The completion ring to send the completion event on. This should
29377 * be the NQ ID returned from the `nq_alloc` HWRM command.
29379 uint16_t cmpl_ring;
29381 * The sequence ID is used by the driver for tracking multiple
29382 * commands. This ID is treated as opaque data by the firmware and
29383 * the value is returned in the `hwrm_resp_hdr` upon completion.
29387 * The target ID of the command:
29388 * * 0x0-0xFFF8 - The function ID
29389 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29390 * * 0xFFFD - Reserved for user-space HWRM interface
29393 uint16_t target_id;
29395 * A physical address pointer pointing to a host buffer that the
29396 * command's response data will be written. This can be either a host
29397 * physical address (HPA) or a guest physical address (GPA) and must
29398 * point to a physically contiguous block of memory.
29400 uint64_t resp_addr;
29401 /* rss_cos_lb_ctx_id is 16 b */
29402 uint16_t rss_cos_lb_ctx_id;
29403 uint8_t unused_0[6];
29406 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
29407 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
29408 /* The specific error status for the command. */
29409 uint16_t error_code;
29410 /* The HWRM command request type. */
29412 /* The sequence ID from the original command. */
29414 /* The length of the response data in number of bytes. */
29416 uint8_t unused_0[7];
29418 * This field is used in Output records to indicate that the output
29419 * is completely written to RAM. This field should be read as '1'
29420 * to indicate that the output has been completely written.
29421 * When writing a command completion or response to an internal processor,
29422 * the order of writes has to be such that this field is written last.
29427 /*******************
29428 * hwrm_ring_alloc *
29429 *******************/
29432 /* hwrm_ring_alloc_input (size:704b/88B) */
29433 struct hwrm_ring_alloc_input {
29434 /* The HWRM command request type. */
29437 * The completion ring to send the completion event on. This should
29438 * be the NQ ID returned from the `nq_alloc` HWRM command.
29440 uint16_t cmpl_ring;
29442 * The sequence ID is used by the driver for tracking multiple
29443 * commands. This ID is treated as opaque data by the firmware and
29444 * the value is returned in the `hwrm_resp_hdr` upon completion.
29448 * The target ID of the command:
29449 * * 0x0-0xFFF8 - The function ID
29450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29451 * * 0xFFFD - Reserved for user-space HWRM interface
29454 uint16_t target_id;
29456 * A physical address pointer pointing to a host buffer that the
29457 * command's response data will be written. This can be either a host
29458 * physical address (HPA) or a guest physical address (GPA) and must
29459 * point to a physically contiguous block of memory.
29461 uint64_t resp_addr;
29464 * This bit must be '1' for the ring_arb_cfg field to be
29467 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
29470 * This bit must be '1' for the stat_ctx_id_valid field to be
29473 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
29476 * This bit must be '1' for the max_bw_valid field to be
29479 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
29482 * This bit must be '1' for the rx_ring_id field to be
29485 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
29488 * This bit must be '1' for the nq_ring_id field to be
29491 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
29494 * This bit must be '1' for the rx_buf_size field to be
29497 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
29500 * This bit must be '1' for the schq_id field to be
29503 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
29506 * This bit must be '1' for the mpc_chnls_type field to be
29509 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
29513 /* L2 Completion Ring (CR) */
29514 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
29516 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
29518 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
29519 /* RoCE Notification Completion Ring (ROCE_CR) */
29520 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
29521 /* RX Aggregation Ring */
29522 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
29523 /* Notification Queue */
29524 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
29525 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
29526 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
29528 /* Ring allocation flags. */
29531 * For Rx rings, the incoming packet data can be placed at either
29532 * a 0B or 2B offset from the start of the Rx packet buffer. When
29533 * '1', the received packet will be padded with 2B of zeros at the
29534 * front of the packet. Note that this flag is only used for
29535 * Rx rings and is ignored for all other rings included Rx
29536 * Aggregation rings.
29538 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
29540 * This value is a pointer to the page table for the
29543 uint64_t page_tbl_addr;
29544 /* First Byte Offset of the first entry in the first page. */
29547 * Actual page size in 2^page_size. The supported range is increments
29548 * in powers of 2 from 16 bytes to 1GB.
29550 * Page size is 16 B.
29552 * Page size is 4 KB.
29554 * Page size is 8 KB.
29556 * Page size is 64 KB.
29558 * Page size is 2 MB.
29560 * Page size is 4 MB.
29562 * Page size is 1 GB.
29566 * This value indicates the depth of page table.
29567 * For this version of the specification, value other than 0 or
29568 * 1 shall be considered as an invalid value.
29569 * When the page_tbl_depth = 0, then it is treated as a
29570 * special case with the following.
29571 * 1. FBO and page size fields are not valid.
29572 * 2. page_tbl_addr is the physical address of the first
29573 * element of the ring.
29575 uint8_t page_tbl_depth;
29576 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
29579 * Number of 16B units in the ring. Minimum size for
29580 * a ring is 16 16B entries.
29584 * Logical ring number for the ring to be allocated.
29585 * This value determines the position in the doorbell
29586 * area where the update to the ring will be made.
29588 * For completion rings, this value is also the MSI-X
29589 * vector number for the function the completion ring is
29592 uint16_t logical_id;
29594 * This field is used only when ring_type is a TX ring.
29595 * This value indicates what completion ring the TX ring
29596 * is associated with.
29598 uint16_t cmpl_ring_id;
29600 * This field is used only when ring_type is a TX ring.
29601 * This value indicates what CoS queue the TX ring
29602 * is associated with.
29606 * When allocating a Rx ring or Rx aggregation ring, this field
29607 * specifies the size of the buffer descriptors posted to the ring.
29609 uint16_t rx_buf_size;
29611 * When allocating an Rx aggregation ring, this field
29612 * specifies the associated Rx ring ID.
29614 uint16_t rx_ring_id;
29616 * When allocating a completion ring, this field
29617 * specifies the associated NQ ring ID.
29619 uint16_t nq_ring_id;
29621 * This field is used only when ring_type is a TX ring.
29622 * This field is used to configure arbitration related
29623 * parameters for a TX ring.
29625 uint16_t ring_arb_cfg;
29626 /* Arbitration policy used for the ring. */
29627 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
29629 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
29631 * Use strict priority for the TX ring.
29632 * Priority value is specified in arb_policy_param
29634 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
29637 * Use weighted fair queue arbitration for the TX ring.
29638 * Weight is specified in arb_policy_param
29640 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
29642 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
29643 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
29644 /* Reserved field. */
29645 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
29647 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
29649 * Arbitration policy specific parameter.
29650 * # For strict priority arbitration policy, this field
29651 * represents a priority value. If set to 0, then the priority
29652 * is not specified and the HWRM is allowed to select
29653 * any priority for this TX ring.
29654 * # For weighted fair queue arbitration policy, this field
29655 * represents a weight value. If set to 0, then the weight
29656 * is not specified and the HWRM is allowed to select
29657 * any weight for this TX ring.
29659 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
29661 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
29664 * This field is reserved for the future use.
29665 * It shall be set to 0.
29667 uint32_t reserved3;
29669 * This field is used only when ring_type is a TX ring.
29670 * This input indicates what statistics context this ring
29671 * should be associated with.
29673 uint32_t stat_ctx_id;
29675 * This field is reserved for the future use.
29676 * It shall be set to 0.
29678 uint32_t reserved4;
29680 * This field is used only when ring_type is a TX ring
29681 * to specify maximum BW allocated to the TX ring.
29682 * The HWRM will translate this value into byte counter and
29683 * time interval used for this ring inside the device.
29686 /* The bandwidth value. */
29687 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
29688 UINT32_C(0xfffffff)
29689 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
29690 /* The granularity of the value (bits or bytes). */
29691 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
29692 UINT32_C(0x10000000)
29693 /* Value is in bits. */
29694 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
29695 (UINT32_C(0x0) << 28)
29696 /* Value is in bytes. */
29697 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
29698 (UINT32_C(0x1) << 28)
29699 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
29700 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
29701 /* bw_value_unit is 3 b */
29702 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
29703 UINT32_C(0xe0000000)
29704 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
29705 /* Value is in Mb or MB (base 10). */
29706 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
29707 (UINT32_C(0x0) << 29)
29708 /* Value is in Kb or KB (base 10). */
29709 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
29710 (UINT32_C(0x2) << 29)
29711 /* Value is in bits or bytes. */
29712 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
29713 (UINT32_C(0x4) << 29)
29714 /* Value is in Gb or GB (base 10). */
29715 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
29716 (UINT32_C(0x6) << 29)
29717 /* Value is in 1/100th of a percentage of total bandwidth. */
29718 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29719 (UINT32_C(0x1) << 29)
29721 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
29722 (UINT32_C(0x7) << 29)
29723 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
29724 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
29726 * This field is used only when ring_type is a Completion ring.
29727 * This value indicates what interrupt mode should be used
29728 * on this completion ring.
29729 * Note: In the legacy interrupt mode, no more than 16
29730 * completion rings are allowed.
29734 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
29736 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
29738 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
29739 /* No Interrupt - Polled mode */
29740 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
29741 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
29742 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
29743 /* Midpath channel type */
29744 uint8_t mpc_chnls_type;
29746 * Indicate the TX ring alloc MPC channel type is a MPC channel
29747 * with destination to the TX crypto engine block.
29749 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
29751 * Indicate the RX ring alloc MPC channel type is a MPC channel
29752 * with destination to the RX crypto engine block.
29754 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
29756 * Indicate the RX ring alloc MPC channel type is a MPC channel
29757 * with destination to the TX configurable flow processing block.
29759 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
29761 * Indicate the RX ring alloc MPC channel type is a MPC channel
29762 * with destination to the RX configurable flow processing block.
29764 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
29766 * Indicate the RX ring alloc MPC channel type is a MPC channel
29767 * with destination to the primate processor block.
29769 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
29770 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
29771 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
29772 uint8_t unused_4[2];
29774 * The cq_handle is specified when allocating a completion ring. For
29775 * devices that support NQs, this cq_handle will be included in the
29776 * NQE to specify which CQ should be read to retrieve the completion
29779 uint64_t cq_handle;
29782 /* hwrm_ring_alloc_output (size:128b/16B) */
29783 struct hwrm_ring_alloc_output {
29784 /* The specific error status for the command. */
29785 uint16_t error_code;
29786 /* The HWRM command request type. */
29788 /* The sequence ID from the original command. */
29790 /* The length of the response data in number of bytes. */
29793 * Physical number of ring allocated.
29794 * This value shall be unique for a ring type.
29797 /* Logical number of ring allocated. */
29798 uint16_t logical_ring_id;
29799 uint8_t unused_0[3];
29801 * This field is used in Output records to indicate that the output
29802 * is completely written to RAM. This field should be read as '1'
29803 * to indicate that the output has been completely written.
29804 * When writing a command completion or response to an internal processor,
29805 * the order of writes has to be such that this field is written last.
29810 /******************
29812 ******************/
29815 /* hwrm_ring_free_input (size:192b/24B) */
29816 struct hwrm_ring_free_input {
29817 /* The HWRM command request type. */
29820 * The completion ring to send the completion event on. This should
29821 * be the NQ ID returned from the `nq_alloc` HWRM command.
29823 uint16_t cmpl_ring;
29825 * The sequence ID is used by the driver for tracking multiple
29826 * commands. This ID is treated as opaque data by the firmware and
29827 * the value is returned in the `hwrm_resp_hdr` upon completion.
29831 * The target ID of the command:
29832 * * 0x0-0xFFF8 - The function ID
29833 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29834 * * 0xFFFD - Reserved for user-space HWRM interface
29837 uint16_t target_id;
29839 * A physical address pointer pointing to a host buffer that the
29840 * command's response data will be written. This can be either a host
29841 * physical address (HPA) or a guest physical address (GPA) and must
29842 * point to a physically contiguous block of memory.
29844 uint64_t resp_addr;
29847 /* L2 Completion Ring (CR) */
29848 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
29850 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
29852 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
29853 /* RoCE Notification Completion Ring (ROCE_CR) */
29854 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
29855 /* RX Aggregation Ring */
29856 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
29857 /* Notification Queue */
29858 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
29859 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
29860 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
29862 /* Physical number of ring allocated. */
29864 uint8_t unused_1[4];
29867 /* hwrm_ring_free_output (size:128b/16B) */
29868 struct hwrm_ring_free_output {
29869 /* The specific error status for the command. */
29870 uint16_t error_code;
29871 /* The HWRM command request type. */
29873 /* The sequence ID from the original command. */
29875 /* The length of the response data in number of bytes. */
29877 uint8_t unused_0[7];
29879 * This field is used in Output records to indicate that the output
29880 * is completely written to RAM. This field should be read as '1'
29881 * to indicate that the output has been completely written.
29882 * When writing a command completion or response to an internal processor,
29883 * the order of writes has to be such that this field is written last.
29888 /*******************
29889 * hwrm_ring_reset *
29890 *******************/
29893 /* hwrm_ring_reset_input (size:192b/24B) */
29894 struct hwrm_ring_reset_input {
29895 /* The HWRM command request type. */
29898 * The completion ring to send the completion event on. This should
29899 * be the NQ ID returned from the `nq_alloc` HWRM command.
29901 uint16_t cmpl_ring;
29903 * The sequence ID is used by the driver for tracking multiple
29904 * commands. This ID is treated as opaque data by the firmware and
29905 * the value is returned in the `hwrm_resp_hdr` upon completion.
29909 * The target ID of the command:
29910 * * 0x0-0xFFF8 - The function ID
29911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29912 * * 0xFFFD - Reserved for user-space HWRM interface
29915 uint16_t target_id;
29917 * A physical address pointer pointing to a host buffer that the
29918 * command's response data will be written. This can be either a host
29919 * physical address (HPA) or a guest physical address (GPA) and must
29920 * point to a physically contiguous block of memory.
29922 uint64_t resp_addr;
29925 /* L2 Completion Ring (CR) */
29926 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
29928 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
29930 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
29931 /* RoCE Notification Completion Ring (ROCE_CR) */
29932 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
29934 * Rx Ring Group. This is to reset rx and aggregation in an atomic
29935 * operation. Completion ring associated with this ring group is
29938 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
29939 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
29940 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
29943 * Physical number of the ring. When ring type is rx_ring_grp, ring id
29944 * actually refers to ring group id.
29947 uint8_t unused_1[4];
29950 /* hwrm_ring_reset_output (size:128b/16B) */
29951 struct hwrm_ring_reset_output {
29952 /* The specific error status for the command. */
29953 uint16_t error_code;
29954 /* The HWRM command request type. */
29956 /* The sequence ID from the original command. */
29958 /* The length of the response data in number of bytes. */
29960 uint8_t unused_0[4];
29961 /* Position of consumer index after ring reset completes. */
29962 uint8_t consumer_idx[3];
29964 * This field is used in Output records to indicate that the output
29965 * is completely written to RAM. This field should be read as '1'
29966 * to indicate that the output has been completely written.
29967 * When writing a command completion or response to an internal processor,
29968 * the order of writes has to be such that this field is written last.
29978 /* hwrm_ring_cfg_input (size:256b/32B) */
29979 struct hwrm_ring_cfg_input {
29980 /* The HWRM command request type. */
29983 * The completion ring to send the completion event on. This should
29984 * be the NQ ID returned from the `nq_alloc` HWRM command.
29986 uint16_t cmpl_ring;
29988 * The sequence ID is used by the driver for tracking multiple
29989 * commands. This ID is treated as opaque data by the firmware and
29990 * the value is returned in the `hwrm_resp_hdr` upon completion.
29994 * The target ID of the command:
29995 * * 0x0-0xFFF8 - The function ID
29996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29997 * * 0xFFFD - Reserved for user-space HWRM interface
30000 uint16_t target_id;
30002 * A physical address pointer pointing to a host buffer that the
30003 * command's response data will be written. This can be either a host
30004 * physical address (HPA) or a guest physical address (GPA) and must
30005 * point to a physically contiguous block of memory.
30007 uint64_t resp_addr;
30011 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
30013 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
30014 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
30015 HWRM_RING_CFG_INPUT_RING_TYPE_RX
30017 /* Physical number of the ring. */
30019 /* Ring config enable bits. */
30022 * For Rx rings, the incoming packet data can be placed at either
30023 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
30025 * When '1', the received packet will be padded with 2B, 10B or 12B
30026 * of zeros at the front of the packet. The exact offset is specified
30027 * by rx_sop_pad_bytes parameter.
30028 * When '0', the received packet will not be padded.
30029 * Note that this flag is only used for Rx rings and is ignored
30030 * for all other rings included Rx Aggregation rings.
30032 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
30035 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
30036 * When rings are allocated, the PCI function on which driver issues
30037 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
30038 * the buffer descriptors (BDs) from those rings is assumed to issue
30039 * packet payload DMA using same PCI function. When proxy mode is
30040 * enabled, hardware can perform payload DMA using another PCI
30041 * function on same or different host.
30042 * When set to '0', the PCI function on which driver issues
30043 * HWRM_RING_CFG command is used for host payload DMA operation.
30044 * When set to '1', the host PCI function specified by proxy_fid is
30045 * used for host payload DMA operation.
30047 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
30050 * Tx ring packet source interface override, for Tx rings only.
30051 * When TX rings are allocated, the PCI function on which driver
30052 * issues HWRM_RING_CFG is assumed to be source interface of
30053 * packets sent from TX ring.
30054 * When set to '1', the host PCI function specified by proxy_fid
30055 * is used as source interface of the transmitted packets.
30057 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
30059 /* The schq_id field is valid */
30060 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
30062 /* Update completion ring ID associated with Tx or Rx ring. */
30063 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
30066 * Proxy function FID value.
30067 * This value is only used when either proxy_mode_enable flag or
30068 * tx_proxy_svif_override is set to '1'.
30069 * When proxy_mode_enable is set to '1', it identifies a host PCI
30070 * function used for host payload DMA operations.
30071 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
30072 * function as source interface for all transmitted packets from
30075 uint16_t proxy_fid;
30077 * Identifies the new scheduler queue (SCHQ) to associate with the
30078 * ring. Only valid for Tx rings.
30079 * A value of zero indicates that the Tx ring should be associated
30080 * with the default scheduler queue (SCHQ).
30084 * This field is valid for TX or Rx rings. This value identifies the
30085 * new completion ring ID to associate with the TX or Rx ring.
30087 uint16_t cmpl_ring_id;
30089 * Rx SOP padding amount in bytes.
30090 * This value is only used when rx_sop_pad_enable flag is set to '1'.
30092 uint8_t rx_sop_pad_bytes;
30093 uint8_t unused_1[3];
30096 /* hwrm_ring_cfg_output (size:128b/16B) */
30097 struct hwrm_ring_cfg_output {
30098 /* The specific error status for the command. */
30099 uint16_t error_code;
30100 /* The HWRM command request type. */
30102 /* The sequence ID from the original command. */
30104 /* The length of the response data in number of bytes. */
30106 uint8_t unused_0[7];
30108 * This field is used in Output records to indicate that the output
30109 * is completely written to RAM. This field should be read as '1'
30110 * to indicate that the output has been completely written.
30111 * When writing a command completion or response to an internal
30112 * processor, the order of writes has to be such that this field is
30118 /******************
30120 ******************/
30123 /* hwrm_ring_qcfg_input (size:192b/24B) */
30124 struct hwrm_ring_qcfg_input {
30125 /* The HWRM command request type. */
30128 * The completion ring to send the completion event on. This should
30129 * be the NQ ID returned from the `nq_alloc` HWRM command.
30131 uint16_t cmpl_ring;
30133 * The sequence ID is used by the driver for tracking multiple
30134 * commands. This ID is treated as opaque data by the firmware and
30135 * the value is returned in the `hwrm_resp_hdr` upon completion.
30139 * The target ID of the command:
30140 * * 0x0-0xFFF8 - The function ID
30141 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30142 * * 0xFFFD - Reserved for user-space HWRM interface
30145 uint16_t target_id;
30147 * A physical address pointer pointing to a host buffer that the
30148 * command's response data will be written. This can be either a host
30149 * physical address (HPA) or a guest physical address (GPA) and must
30150 * point to a physically contiguous block of memory.
30152 uint64_t resp_addr;
30156 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
30158 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
30159 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
30160 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
30161 uint8_t unused_0[5];
30162 /* Physical number of the ring. */
30166 /* hwrm_ring_qcfg_output (size:192b/24B) */
30167 struct hwrm_ring_qcfg_output {
30168 /* The specific error status for the command. */
30169 uint16_t error_code;
30170 /* The HWRM command request type. */
30172 /* The sequence ID from the original command. */
30174 /* The length of the response data in number of bytes. */
30176 /* Ring config enable bits. */
30179 * For Rx rings, the incoming packet data can be placed at either
30180 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
30182 * When '1', the received packet will be padded with 2B, 10B or 12B
30183 * of zeros at the front of the packet. The exact offset is specified
30184 * by rx_sop_pad_bytes parameter.
30185 * When '0', the received packet will not be padded.
30186 * Note that this flag is only used for Rx rings and is ignored
30187 * for all other rings included Rx Aggregation rings.
30189 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
30192 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
30193 * When rings are allocated, the PCI function on which driver issues
30194 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
30195 * the buffer descriptors (BDs) from those rings is assumed to issue
30196 * packet payload DMA using same PCI function. When proxy mode is
30197 * enabled, hardware can perform payload DMA using another PCI
30198 * function on same or different host.
30199 * When set to '0', the PCI function on which driver issues
30200 * HWRM_RING_CFG command is used for host payload DMA operation.
30201 * When set to '1', the host PCI function specified by proxy_fid is
30202 * used for host payload DMA operation.
30204 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
30207 * Tx ring packet source interface override, for Tx rings only.
30208 * When TX rings are allocated, the PCI function on which driver
30209 * issues HWRM_RING_CFG is assumed to be source interface of
30210 * packets sent from TX ring.
30211 * When set to '1', the host PCI function specified by proxy_fid is
30212 * used as source interface of the transmitted packets.
30214 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
30217 * Proxy function FID value.
30218 * This value is only used when either proxy_mode_enable flag or
30219 * tx_proxy_svif_override is set to '1'.
30220 * When proxy_mode_enable is set to '1', it identifies a host PCI
30221 * function used for host payload DMA operations.
30222 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
30223 * function as source interface for all transmitted packets from the TX
30226 uint16_t proxy_fid;
30228 * Identifies the new scheduler queue (SCHQ) to associate with the
30229 * ring. Only valid for Tx rings.
30230 * A value of zero indicates that the Tx ring should be associated with
30231 * the default scheduler queue (SCHQ).
30235 * This field is used when ring_type is a TX or Rx ring.
30236 * This value indicates what completion ring the TX or Rx ring
30237 * is associated with.
30239 uint16_t cmpl_ring_id;
30241 * Rx SOP padding amount in bytes.
30242 * This value is only used when rx_sop_pad_enable flag is set to '1'.
30244 uint8_t rx_sop_pad_bytes;
30245 uint8_t unused_0[6];
30247 * This field is used in Output records to indicate that the output
30248 * is completely written to RAM. This field should be read as '1'
30249 * to indicate that the output has been completely written.
30250 * When writing a command completion or response to an internal
30251 * processor, the order of writes has to be such that this field is
30257 /**************************
30258 * hwrm_ring_aggint_qcaps *
30259 **************************/
30262 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
30263 struct hwrm_ring_aggint_qcaps_input {
30264 /* The HWRM command request type. */
30267 * The completion ring to send the completion event on. This should
30268 * be the NQ ID returned from the `nq_alloc` HWRM command.
30270 uint16_t cmpl_ring;
30272 * The sequence ID is used by the driver for tracking multiple
30273 * commands. This ID is treated as opaque data by the firmware and
30274 * the value is returned in the `hwrm_resp_hdr` upon completion.
30278 * The target ID of the command:
30279 * * 0x0-0xFFF8 - The function ID
30280 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30281 * * 0xFFFD - Reserved for user-space HWRM interface
30284 uint16_t target_id;
30286 * A physical address pointer pointing to a host buffer that the
30287 * command's response data will be written. This can be either a host
30288 * physical address (HPA) or a guest physical address (GPA) and must
30289 * point to a physically contiguous block of memory.
30291 uint64_t resp_addr;
30294 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
30295 struct hwrm_ring_aggint_qcaps_output {
30296 /* The specific error status for the command. */
30297 uint16_t error_code;
30298 /* The HWRM command request type. */
30300 /* The sequence ID from the original command. */
30302 /* The length of the response data in number of bytes. */
30304 uint32_t cmpl_params;
30306 * When this bit is set to '1', int_lat_tmr_min can be configured
30307 * on completion rings.
30309 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
30312 * When this bit is set to '1', int_lat_tmr_max can be configured
30313 * on completion rings.
30315 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
30318 * When this bit is set to '1', timer_reset can be enabled
30319 * on completion rings.
30321 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
30324 * When this bit is set to '1', ring_idle can be enabled
30325 * on completion rings.
30327 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
30330 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
30331 * on completion rings.
30333 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
30336 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
30337 * on completion rings.
30339 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
30342 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
30343 * on completion rings.
30345 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
30348 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
30349 * on completion rings.
30351 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
30354 * When this bit is set to '1', num_cmpl_aggr_int can be configured
30355 * on completion rings.
30357 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
30359 uint32_t nq_params;
30361 * When this bit is set to '1', int_lat_tmr_min can be configured
30362 * on notification queues.
30364 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
30366 /* Minimum value for num_cmpl_dma_aggr */
30367 uint16_t num_cmpl_dma_aggr_min;
30368 /* Maximum value for num_cmpl_dma_aggr */
30369 uint16_t num_cmpl_dma_aggr_max;
30370 /* Minimum value for num_cmpl_dma_aggr_during_int */
30371 uint16_t num_cmpl_dma_aggr_during_int_min;
30372 /* Maximum value for num_cmpl_dma_aggr_during_int */
30373 uint16_t num_cmpl_dma_aggr_during_int_max;
30374 /* Minimum value for cmpl_aggr_dma_tmr */
30375 uint16_t cmpl_aggr_dma_tmr_min;
30376 /* Maximum value for cmpl_aggr_dma_tmr */
30377 uint16_t cmpl_aggr_dma_tmr_max;
30378 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
30379 uint16_t cmpl_aggr_dma_tmr_during_int_min;
30380 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
30381 uint16_t cmpl_aggr_dma_tmr_during_int_max;
30382 /* Minimum value for int_lat_tmr_min */
30383 uint16_t int_lat_tmr_min_min;
30384 /* Maximum value for int_lat_tmr_min */
30385 uint16_t int_lat_tmr_min_max;
30386 /* Minimum value for int_lat_tmr_max */
30387 uint16_t int_lat_tmr_max_min;
30388 /* Maximum value for int_lat_tmr_max */
30389 uint16_t int_lat_tmr_max_max;
30390 /* Minimum value for num_cmpl_aggr_int */
30391 uint16_t num_cmpl_aggr_int_min;
30392 /* Maximum value for num_cmpl_aggr_int */
30393 uint16_t num_cmpl_aggr_int_max;
30394 /* The units for timer parameters, in nanoseconds. */
30395 uint16_t timer_units;
30396 uint8_t unused_0[1];
30398 * This field is used in Output records to indicate that the output
30399 * is completely written to RAM. This field should be read as '1'
30400 * to indicate that the output has been completely written.
30401 * When writing a command completion or response to an internal processor,
30402 * the order of writes has to be such that this field is written last.
30407 /**************************************
30408 * hwrm_ring_cmpl_ring_qaggint_params *
30409 **************************************/
30412 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
30413 struct hwrm_ring_cmpl_ring_qaggint_params_input {
30414 /* The HWRM command request type. */
30417 * The completion ring to send the completion event on. This should
30418 * be the NQ ID returned from the `nq_alloc` HWRM command.
30420 uint16_t cmpl_ring;
30422 * The sequence ID is used by the driver for tracking multiple
30423 * commands. This ID is treated as opaque data by the firmware and
30424 * the value is returned in the `hwrm_resp_hdr` upon completion.
30428 * The target ID of the command:
30429 * * 0x0-0xFFF8 - The function ID
30430 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30431 * * 0xFFFD - Reserved for user-space HWRM interface
30434 uint16_t target_id;
30436 * A physical address pointer pointing to a host buffer that the
30437 * command's response data will be written. This can be either a host
30438 * physical address (HPA) or a guest physical address (GPA) and must
30439 * point to a physically contiguous block of memory.
30441 uint64_t resp_addr;
30442 /* Physical number of completion ring. */
30445 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
30447 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
30449 * Set this flag to 1 when querying parameters on a notification
30450 * queue. Set this flag to 0 when querying parameters on a
30451 * completion queue or completion ring.
30453 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
30455 uint8_t unused_0[4];
30458 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
30459 struct hwrm_ring_cmpl_ring_qaggint_params_output {
30460 /* The specific error status for the command. */
30461 uint16_t error_code;
30462 /* The HWRM command request type. */
30464 /* The sequence ID from the original command. */
30466 /* The length of the response data in number of bytes. */
30470 * When this bit is set to '1', interrupt max
30471 * timer is reset whenever a completion is received.
30473 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
30476 * When this bit is set to '1', ring idle mode
30477 * aggregation will be enabled.
30479 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
30482 * Number of completions to aggregate before DMA
30483 * during the normal mode.
30485 uint16_t num_cmpl_dma_aggr;
30487 * Number of completions to aggregate before DMA
30488 * during the interrupt mode.
30490 uint16_t num_cmpl_dma_aggr_during_int;
30492 * Timer used to aggregate completions before
30493 * DMA during the normal mode (not in interrupt mode).
30495 uint16_t cmpl_aggr_dma_tmr;
30497 * Timer used to aggregate completions before
30498 * DMA when in interrupt mode.
30500 uint16_t cmpl_aggr_dma_tmr_during_int;
30501 /* Minimum time between two interrupts. */
30502 uint16_t int_lat_tmr_min;
30504 * Maximum wait time spent aggregating
30505 * completions before signaling the interrupt after the
30506 * interrupt is enabled.
30508 uint16_t int_lat_tmr_max;
30510 * Minimum number of completions aggregated before signaling
30513 uint16_t num_cmpl_aggr_int;
30514 uint8_t unused_0[7];
30516 * This field is used in Output records to indicate that the output
30517 * is completely written to RAM. This field should be read as '1'
30518 * to indicate that the output has been completely written.
30519 * When writing a command completion or response to an internal processor,
30520 * the order of writes has to be such that this field is written last.
30525 /*****************************************
30526 * hwrm_ring_cmpl_ring_cfg_aggint_params *
30527 *****************************************/
30530 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
30531 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
30532 /* The HWRM command request type. */
30535 * The completion ring to send the completion event on. This should
30536 * be the NQ ID returned from the `nq_alloc` HWRM command.
30538 uint16_t cmpl_ring;
30540 * The sequence ID is used by the driver for tracking multiple
30541 * commands. This ID is treated as opaque data by the firmware and
30542 * the value is returned in the `hwrm_resp_hdr` upon completion.
30546 * The target ID of the command:
30547 * * 0x0-0xFFF8 - The function ID
30548 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30549 * * 0xFFFD - Reserved for user-space HWRM interface
30552 uint16_t target_id;
30554 * A physical address pointer pointing to a host buffer that the
30555 * command's response data will be written. This can be either a host
30556 * physical address (HPA) or a guest physical address (GPA) and must
30557 * point to a physically contiguous block of memory.
30559 uint64_t resp_addr;
30560 /* Physical number of completion ring. */
30564 * When this bit is set to '1', interrupt latency max
30565 * timer is reset whenever a completion is received.
30567 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
30570 * When this bit is set to '1', ring idle mode
30571 * aggregation will be enabled.
30573 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
30576 * Set this flag to 1 when configuring parameters on a
30577 * notification queue. Set this flag to 0 when configuring
30578 * parameters on a completion queue or completion ring.
30580 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
30583 * Number of completions to aggregate before DMA
30584 * during the normal mode.
30586 uint16_t num_cmpl_dma_aggr;
30588 * Number of completions to aggregate before DMA
30589 * during the interrupt mode.
30591 uint16_t num_cmpl_dma_aggr_during_int;
30593 * Timer used to aggregate completions before
30594 * DMA during the normal mode (not in interrupt mode).
30596 uint16_t cmpl_aggr_dma_tmr;
30598 * Timer used to aggregate completions before
30599 * DMA while in interrupt mode.
30601 uint16_t cmpl_aggr_dma_tmr_during_int;
30602 /* Minimum time between two interrupts. */
30603 uint16_t int_lat_tmr_min;
30605 * Maximum wait time spent aggregating
30606 * completions before signaling the interrupt after the
30607 * interrupt is enabled.
30609 uint16_t int_lat_tmr_max;
30611 * Minimum number of completions aggregated before signaling
30614 uint16_t num_cmpl_aggr_int;
30616 * Bitfield that indicates which parameters are to be applied. Only
30617 * required when configuring devices with notification queues, and
30618 * used in that case to set certain parameters on completion queues
30619 * and others on notification queues.
30623 * This bit must be '1' for the num_cmpl_dma_aggr field to be
30626 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
30629 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
30632 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
30635 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
30638 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
30641 * This bit must be '1' for the int_lat_tmr_min field to be
30644 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
30647 * This bit must be '1' for the int_lat_tmr_max field to be
30650 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
30653 * This bit must be '1' for the num_cmpl_aggr_int field to be
30656 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
30658 uint8_t unused_0[4];
30661 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
30662 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
30663 /* The specific error status for the command. */
30664 uint16_t error_code;
30665 /* The HWRM command request type. */
30667 /* The sequence ID from the original command. */
30669 /* The length of the response data in number of bytes. */
30671 uint8_t unused_0[7];
30673 * This field is used in Output records to indicate that the output
30674 * is completely written to RAM. This field should be read as '1'
30675 * to indicate that the output has been completely written.
30676 * When writing a command completion or response to an internal processor,
30677 * the order of writes has to be such that this field is written last.
30682 /***********************
30683 * hwrm_ring_grp_alloc *
30684 ***********************/
30687 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
30688 struct hwrm_ring_grp_alloc_input {
30689 /* The HWRM command request type. */
30692 * The completion ring to send the completion event on. This should
30693 * be the NQ ID returned from the `nq_alloc` HWRM command.
30695 uint16_t cmpl_ring;
30697 * The sequence ID is used by the driver for tracking multiple
30698 * commands. This ID is treated as opaque data by the firmware and
30699 * the value is returned in the `hwrm_resp_hdr` upon completion.
30703 * The target ID of the command:
30704 * * 0x0-0xFFF8 - The function ID
30705 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30706 * * 0xFFFD - Reserved for user-space HWRM interface
30709 uint16_t target_id;
30711 * A physical address pointer pointing to a host buffer that the
30712 * command's response data will be written. This can be either a host
30713 * physical address (HPA) or a guest physical address (GPA) and must
30714 * point to a physically contiguous block of memory.
30716 uint64_t resp_addr;
30718 * This value identifies the CR associated with the ring
30723 * This value identifies the main RR associated with the ring
30728 * This value identifies the aggregation RR associated with
30729 * the ring group. If this value is 0xFF... (All Fs), then no
30730 * Aggregation ring will be set.
30734 * This value identifies the statistics context associated
30735 * with the ring group.
30740 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
30741 struct hwrm_ring_grp_alloc_output {
30742 /* The specific error status for the command. */
30743 uint16_t error_code;
30744 /* The HWRM command request type. */
30746 /* The sequence ID from the original command. */
30748 /* The length of the response data in number of bytes. */
30751 * This is the ring group ID value. Use this value to program
30752 * the default ring group for the VNIC or as table entries
30753 * in an RSS/COS context.
30755 uint32_t ring_group_id;
30756 uint8_t unused_0[3];
30758 * This field is used in Output records to indicate that the output
30759 * is completely written to RAM. This field should be read as '1'
30760 * to indicate that the output has been completely written.
30761 * When writing a command completion or response to an internal processor,
30762 * the order of writes has to be such that this field is written last.
30767 /**********************
30768 * hwrm_ring_grp_free *
30769 **********************/
30772 /* hwrm_ring_grp_free_input (size:192b/24B) */
30773 struct hwrm_ring_grp_free_input {
30774 /* The HWRM command request type. */
30777 * The completion ring to send the completion event on. This should
30778 * be the NQ ID returned from the `nq_alloc` HWRM command.
30780 uint16_t cmpl_ring;
30782 * The sequence ID is used by the driver for tracking multiple
30783 * commands. This ID is treated as opaque data by the firmware and
30784 * the value is returned in the `hwrm_resp_hdr` upon completion.
30788 * The target ID of the command:
30789 * * 0x0-0xFFF8 - The function ID
30790 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30791 * * 0xFFFD - Reserved for user-space HWRM interface
30794 uint16_t target_id;
30796 * A physical address pointer pointing to a host buffer that the
30797 * command's response data will be written. This can be either a host
30798 * physical address (HPA) or a guest physical address (GPA) and must
30799 * point to a physically contiguous block of memory.
30801 uint64_t resp_addr;
30802 /* This is the ring group ID value. */
30803 uint32_t ring_group_id;
30804 uint8_t unused_0[4];
30807 /* hwrm_ring_grp_free_output (size:128b/16B) */
30808 struct hwrm_ring_grp_free_output {
30809 /* The specific error status for the command. */
30810 uint16_t error_code;
30811 /* The HWRM command request type. */
30813 /* The sequence ID from the original command. */
30815 /* The length of the response data in number of bytes. */
30817 uint8_t unused_0[7];
30819 * This field is used in Output records to indicate that the output
30820 * is completely written to RAM. This field should be read as '1'
30821 * to indicate that the output has been completely written.
30822 * When writing a command completion or response to an internal processor,
30823 * the order of writes has to be such that this field is written last.
30828 /************************
30829 * hwrm_ring_schq_alloc *
30830 ************************/
30833 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
30834 struct hwrm_ring_schq_alloc_input {
30835 /* The HWRM command request type. */
30838 * The completion ring to send the completion event on. This should
30839 * be the NQ ID returned from the `nq_alloc` HWRM command.
30841 uint16_t cmpl_ring;
30843 * The sequence ID is used by the driver for tracking multiple
30844 * commands. This ID is treated as opaque data by the firmware and
30845 * the value is returned in the `hwrm_resp_hdr` upon completion.
30849 * The target ID of the command:
30850 * * 0x0-0xFFF8 - The function ID
30851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30852 * * 0xFFFD - Reserved for user-space HWRM interface
30855 uint16_t target_id;
30857 * A physical address pointer pointing to a host buffer that the
30858 * command's response data will be written. This can be either a host
30859 * physical address (HPA) or a guest physical address (GPA) and must
30860 * point to a physically contiguous block of memory.
30862 uint64_t resp_addr;
30865 * This bit must be '1' for the tqm_ring0 fields to be
30868 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
30870 * This bit must be '1' for the tqm_ring1 fields to be
30873 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
30875 * This bit must be '1' for the tqm_ring2 fields to be
30878 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
30880 * This bit must be '1' for the tqm_ring3 fields to be
30883 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
30885 * This bit must be '1' for the tqm_ring4 fields to be
30888 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
30890 * This bit must be '1' for the tqm_ring5 fields to be
30893 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
30895 * This bit must be '1' for the tqm_ring6 fields to be
30898 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
30900 * This bit must be '1' for the tqm_ring7 fields to be
30903 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
30904 /* Reserved for future use. */
30906 /* TQM ring 0 page size and level. */
30907 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
30908 /* TQM ring 0 PBL indirect levels. */
30909 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
30911 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
30912 /* PBL pointer is physical start address. */
30913 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
30915 /* PBL pointer points to PTE table. */
30916 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
30919 * PBL pointer points to PDE table with each entry pointing to PTE
30922 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
30924 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
30925 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
30926 /* TQM ring 0 page size. */
30927 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
30929 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
30931 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
30932 (UINT32_C(0x0) << 4)
30934 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
30935 (UINT32_C(0x1) << 4)
30937 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
30938 (UINT32_C(0x2) << 4)
30940 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
30941 (UINT32_C(0x3) << 4)
30943 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
30944 (UINT32_C(0x4) << 4)
30946 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
30947 (UINT32_C(0x5) << 4)
30948 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
30949 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
30950 /* TQM ring 1 page size and level. */
30951 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
30952 /* TQM ring 1 PBL indirect levels. */
30953 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
30955 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
30956 /* PBL pointer is physical start address. */
30957 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
30959 /* PBL pointer points to PTE table. */
30960 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
30963 * PBL pointer points to PDE table with each entry pointing to PTE
30966 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
30968 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
30969 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
30970 /* TQM ring 1 page size. */
30971 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
30973 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
30975 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
30976 (UINT32_C(0x0) << 4)
30978 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
30979 (UINT32_C(0x1) << 4)
30981 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
30982 (UINT32_C(0x2) << 4)
30984 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
30985 (UINT32_C(0x3) << 4)
30987 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
30988 (UINT32_C(0x4) << 4)
30990 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
30991 (UINT32_C(0x5) << 4)
30992 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
30993 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
30994 /* TQM ring 2 page size and level. */
30995 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
30996 /* TQM ring 2 PBL indirect levels. */
30997 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
30999 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
31000 /* PBL pointer is physical start address. */
31001 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
31003 /* PBL pointer points to PTE table. */
31004 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
31007 * PBL pointer points to PDE table with each entry pointing to PTE
31010 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
31012 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
31013 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
31014 /* TQM ring 2 page size. */
31015 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
31017 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
31019 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
31020 (UINT32_C(0x0) << 4)
31022 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
31023 (UINT32_C(0x1) << 4)
31025 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
31026 (UINT32_C(0x2) << 4)
31028 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
31029 (UINT32_C(0x3) << 4)
31031 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
31032 (UINT32_C(0x4) << 4)
31034 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
31035 (UINT32_C(0x5) << 4)
31036 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
31037 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
31038 /* TQM ring 3 page size and level. */
31039 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
31040 /* TQM ring 3 PBL indirect levels. */
31041 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
31043 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
31044 /* PBL pointer is physical start address. */
31045 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
31047 /* PBL pointer points to PTE table. */
31048 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
31051 * PBL pointer points to PDE table with each entry pointing to PTE
31054 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
31056 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
31057 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
31058 /* TQM ring 3 page size. */
31059 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
31061 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
31063 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
31064 (UINT32_C(0x0) << 4)
31066 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
31067 (UINT32_C(0x1) << 4)
31069 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
31070 (UINT32_C(0x2) << 4)
31072 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
31073 (UINT32_C(0x3) << 4)
31075 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
31076 (UINT32_C(0x4) << 4)
31078 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
31079 (UINT32_C(0x5) << 4)
31080 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
31081 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
31082 /* TQM ring 4 page size and level. */
31083 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
31084 /* TQM ring 4 PBL indirect levels. */
31085 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
31087 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
31088 /* PBL pointer is physical start address. */
31089 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
31091 /* PBL pointer points to PTE table. */
31092 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
31095 * PBL pointer points to PDE table with each entry pointing to PTE
31098 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
31100 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
31101 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
31102 /* TQM ring 4 page size. */
31103 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
31105 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
31107 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
31108 (UINT32_C(0x0) << 4)
31110 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
31111 (UINT32_C(0x1) << 4)
31113 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
31114 (UINT32_C(0x2) << 4)
31116 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
31117 (UINT32_C(0x3) << 4)
31119 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
31120 (UINT32_C(0x4) << 4)
31122 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
31123 (UINT32_C(0x5) << 4)
31124 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
31125 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
31126 /* TQM ring 5 page size and level. */
31127 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
31128 /* TQM ring 5 PBL indirect levels. */
31129 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
31131 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
31132 /* PBL pointer is physical start address. */
31133 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
31135 /* PBL pointer points to PTE table. */
31136 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
31139 * PBL pointer points to PDE table with each entry pointing to PTE
31142 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
31144 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
31145 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
31146 /* TQM ring 5 page size. */
31147 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
31149 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
31151 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
31152 (UINT32_C(0x0) << 4)
31154 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
31155 (UINT32_C(0x1) << 4)
31157 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
31158 (UINT32_C(0x2) << 4)
31160 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
31161 (UINT32_C(0x3) << 4)
31163 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
31164 (UINT32_C(0x4) << 4)
31166 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
31167 (UINT32_C(0x5) << 4)
31168 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
31169 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
31170 /* TQM ring 6 page size and level. */
31171 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
31172 /* TQM ring 6 PBL indirect levels. */
31173 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
31175 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
31176 /* PBL pointer is physical start address. */
31177 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
31179 /* PBL pointer points to PTE table. */
31180 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
31183 * PBL pointer points to PDE table with each entry pointing to PTE
31186 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
31188 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
31189 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
31190 /* TQM ring 6 page size. */
31191 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
31193 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
31195 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
31196 (UINT32_C(0x0) << 4)
31198 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
31199 (UINT32_C(0x1) << 4)
31201 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
31202 (UINT32_C(0x2) << 4)
31204 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
31205 (UINT32_C(0x3) << 4)
31207 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
31208 (UINT32_C(0x4) << 4)
31210 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
31211 (UINT32_C(0x5) << 4)
31212 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
31213 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
31214 /* TQM ring 7 page size and level. */
31215 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
31216 /* TQM ring 7 PBL indirect levels. */
31217 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
31219 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
31220 /* PBL pointer is physical start address. */
31221 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
31223 /* PBL pointer points to PTE table. */
31224 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
31227 * PBL pointer points to PDE table with each entry pointing to PTE
31230 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
31232 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
31233 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
31234 /* TQM ring 7 page size. */
31235 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
31237 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
31239 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
31240 (UINT32_C(0x0) << 4)
31242 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
31243 (UINT32_C(0x1) << 4)
31245 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
31246 (UINT32_C(0x2) << 4)
31248 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
31249 (UINT32_C(0x3) << 4)
31251 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
31252 (UINT32_C(0x4) << 4)
31254 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
31255 (UINT32_C(0x5) << 4)
31256 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
31257 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
31258 /* TQM ring 0 page directory. */
31259 uint64_t tqm_ring0_page_dir;
31260 /* TQM ring 1 page directory. */
31261 uint64_t tqm_ring1_page_dir;
31262 /* TQM ring 2 page directory. */
31263 uint64_t tqm_ring2_page_dir;
31264 /* TQM ring 3 page directory. */
31265 uint64_t tqm_ring3_page_dir;
31266 /* TQM ring 4 page directory. */
31267 uint64_t tqm_ring4_page_dir;
31268 /* TQM ring 5 page directory. */
31269 uint64_t tqm_ring5_page_dir;
31270 /* TQM ring 6 page directory. */
31271 uint64_t tqm_ring6_page_dir;
31272 /* TQM ring 7 page directory. */
31273 uint64_t tqm_ring7_page_dir;
31275 * Number of TQM ring 0 entries.
31277 * TQM fastpath rings should be sized large enough to accommodate the
31278 * maximum number of QPs (either L2 or RoCE, or both if shared)
31279 * that can be enqueued to the TQM ring.
31281 * Note that TQM ring sizes cannot be extended while the system is
31282 * operational. If a PF driver needs to extend a TQM ring, it needs
31283 * to delete the SCHQ and then reallocate it.
31285 uint32_t tqm_ring0_num_entries;
31287 * Number of TQM ring 1 entries.
31289 * TQM fastpath rings should be sized large enough to accommodate the
31290 * maximum number of QPs (either L2 or RoCE, or both if shared)
31291 * that can be enqueued to the TQM ring.
31293 * Note that TQM ring sizes cannot be extended while the system is
31294 * operational. If a PF driver needs to extend a TQM ring, it needs
31295 * to delete the SCHQ and then reallocate it.
31297 uint32_t tqm_ring1_num_entries;
31299 * Number of TQM ring 2 entries.
31301 * TQM fastpath rings should be sized large enough to accommodate the
31302 * maximum number of QPs (either L2 or RoCE, or both if shared)
31303 * that can be enqueued to the TQM ring.
31305 * Note that TQM ring sizes cannot be extended while the system is
31306 * operational. If a PF driver needs to extend a TQM ring, it needs
31307 * to delete the SCHQ and then reallocate it.
31309 uint32_t tqm_ring2_num_entries;
31311 * Number of TQM ring 3 entries.
31313 * TQM fastpath rings should be sized large enough to accommodate the
31314 * maximum number of QPs (either L2 or RoCE, or both if shared)
31315 * that can be enqueued to the TQM ring.
31317 * Note that TQM ring sizes cannot be extended while the system is
31318 * operational. If a PF driver needs to extend a TQM ring, it needs
31319 * to delete the SCHQ and then reallocate it.
31321 uint32_t tqm_ring3_num_entries;
31323 * Number of TQM ring 4 entries.
31325 * TQM fastpath rings should be sized large enough to accommodate the
31326 * maximum number of QPs (either L2 or RoCE, or both if shared)
31327 * that can be enqueued to the TQM ring.
31329 * Note that TQM ring sizes cannot be extended while the system is
31330 * operational. If a PF driver needs to extend a TQM ring, it needs
31331 * to delete the SCHQ and then reallocate it.
31333 uint32_t tqm_ring4_num_entries;
31335 * Number of TQM ring 5 entries.
31337 * TQM fastpath rings should be sized large enough to accommodate the
31338 * maximum number of QPs (either L2 or RoCE, or both if shared)
31339 * that can be enqueued to the TQM ring.
31341 * Note that TQM ring sizes cannot be extended while the system is
31342 * operational. If a PF driver needs to extend a TQM ring, it needs
31343 * to delete the SCHQ and then reallocate it.
31345 uint32_t tqm_ring5_num_entries;
31347 * Number of TQM ring 6 entries.
31349 * TQM fastpath rings should be sized large enough to accommodate the
31350 * maximum number of QPs (either L2 or RoCE, or both if shared)
31351 * that can be enqueued to the TQM ring.
31353 * Note that TQM ring sizes cannot be extended while the system is
31354 * operational. If a PF driver needs to extend a TQM ring, it needs
31355 * to delete the SCHQ and then reallocate it.
31357 uint32_t tqm_ring6_num_entries;
31359 * Number of TQM ring 7 entries.
31361 * TQM fastpath rings should be sized large enough to accommodate the
31362 * maximum number of QPs (either L2 or RoCE, or both if shared)
31363 * that can be enqueued to the TQM ring.
31365 * Note that TQM ring sizes cannot be extended while the system is
31366 * operational. If a PF driver needs to extend a TQM ring, it needs
31367 * to delete the SCHQ and then reallocate it.
31369 uint32_t tqm_ring7_num_entries;
31370 /* Number of bytes that have been allocated for each context entry. */
31371 uint16_t tqm_entry_size;
31372 uint8_t unused_0[6];
31375 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
31376 struct hwrm_ring_schq_alloc_output {
31377 /* The specific error status for the command. */
31378 uint16_t error_code;
31379 /* The HWRM command request type. */
31381 /* The sequence ID from the original command. */
31383 /* The length of the response data in number of bytes. */
31386 * This is an identifier for the SCHQ to be used in other HWRM commands
31387 * that need to reference this SCHQ. This value is greater than zero
31388 * (i.e. a schq_id of zero references the default SCHQ).
31391 uint8_t unused_0[5];
31393 * This field is used in Output records to indicate that the output
31394 * is completely written to RAM. This field should be read as '1'
31395 * to indicate that the output has been completely written.
31396 * When writing a command completion or response to an internal processor,
31397 * the order of writes has to be such that this field is written last.
31402 /**********************
31403 * hwrm_ring_schq_cfg *
31404 **********************/
31407 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
31408 struct hwrm_ring_schq_cfg_input {
31409 /* The HWRM command request type. */
31412 * The completion ring to send the completion event on. This should
31413 * be the NQ ID returned from the `nq_alloc` HWRM command.
31415 uint16_t cmpl_ring;
31417 * The sequence ID is used by the driver for tracking multiple
31418 * commands. This ID is treated as opaque data by the firmware and
31419 * the value is returned in the `hwrm_resp_hdr` upon completion.
31423 * The target ID of the command:
31424 * * 0x0-0xFFF8 - The function ID
31425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31426 * * 0xFFFD - Reserved for user-space HWRM interface
31429 uint16_t target_id;
31431 * A physical address pointer pointing to a host buffer that the
31432 * command's response data will be written. This can be either a host
31433 * physical address (HPA) or a guest physical address (GPA) and must
31434 * point to a physically contiguous block of memory.
31436 uint64_t resp_addr;
31438 * Identifies the SCHQ being configured. A schq_id of zero refers to
31439 * the default SCHQ.
31443 * This field is an 8 bit bitmap that indicates which TCs are enabled
31444 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
31447 uint8_t tc_enabled;
31450 /* The tc_max_bw array and the max_bw parameters are valid */
31451 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
31453 /* The tc_min_bw array is valid */
31454 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
31456 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31457 uint32_t max_bw_tc0;
31458 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31459 uint32_t max_bw_tc1;
31460 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31461 uint32_t max_bw_tc2;
31462 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31463 uint32_t max_bw_tc3;
31464 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31465 uint32_t max_bw_tc4;
31466 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31467 uint32_t max_bw_tc5;
31468 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31469 uint32_t max_bw_tc6;
31470 /* Maximum bandwidth of the traffic class, specified in Mbps. */
31471 uint32_t max_bw_tc7;
31473 * Bandwidth reservation for the traffic class, specified in Mbps.
31474 * A value of zero signifies that traffic belonging to this class
31475 * shares the bandwidth reservation for the same traffic class of
31476 * the default SCHQ.
31478 uint32_t min_bw_tc0;
31480 * Bandwidth reservation for the traffic class, specified in Mbps.
31481 * A value of zero signifies that traffic belonging to this class
31482 * shares the bandwidth reservation for the same traffic class of
31483 * the default SCHQ.
31485 uint32_t min_bw_tc1;
31487 * Bandwidth reservation for the traffic class, specified in Mbps.
31488 * A value of zero signifies that traffic belonging to this class
31489 * shares the bandwidth reservation for the same traffic class of
31490 * the default SCHQ.
31492 uint32_t min_bw_tc2;
31494 * Bandwidth reservation for the traffic class, specified in Mbps.
31495 * A value of zero signifies that traffic belonging to this class
31496 * shares the bandwidth reservation for the same traffic class of
31497 * the default SCHQ.
31499 uint32_t min_bw_tc3;
31501 * Bandwidth reservation for the traffic class, specified in Mbps.
31502 * A value of zero signifies that traffic belonging to this class
31503 * shares the bandwidth reservation for the same traffic class of
31504 * the default SCHQ.
31506 uint32_t min_bw_tc4;
31508 * Bandwidth reservation for the traffic class, specified in Mbps.
31509 * A value of zero signifies that traffic belonging to this class
31510 * shares the bandwidth reservation for the same traffic class of
31511 * the default SCHQ.
31513 uint32_t min_bw_tc5;
31515 * Bandwidth reservation for the traffic class, specified in Mbps.
31516 * A value of zero signifies that traffic belonging to this class
31517 * shares the bandwidth reservation for the same traffic class of
31518 * the default SCHQ.
31520 uint32_t min_bw_tc6;
31522 * Bandwidth reservation for the traffic class, specified in Mbps.
31523 * A value of zero signifies that traffic belonging to this class
31524 * shares the bandwidth reservation for the same traffic class of
31525 * the default SCHQ.
31527 uint32_t min_bw_tc7;
31529 * Indicates the max bandwidth for all enabled traffic classes in
31530 * this SCHQ, specified in Mbps.
31533 uint8_t unused_1[4];
31536 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
31537 struct hwrm_ring_schq_cfg_output {
31538 /* The specific error status for the command. */
31539 uint16_t error_code;
31540 /* The HWRM command request type. */
31542 /* The sequence ID from the original command. */
31544 /* The length of the response data in number of bytes. */
31546 uint8_t unused_0[7];
31548 * This field is used in Output records to indicate that the output
31549 * is completely written to RAM. This field should be read as '1'
31550 * to indicate that the output has been completely written.
31551 * When writing a command completion or response to an internal processor,
31552 * the order of writes has to be such that this field is written last.
31557 /***********************
31558 * hwrm_ring_schq_free *
31559 ***********************/
31562 /* hwrm_ring_schq_free_input (size:192b/24B) */
31563 struct hwrm_ring_schq_free_input {
31564 /* The HWRM command request type. */
31567 * The completion ring to send the completion event on. This should
31568 * be the NQ ID returned from the `nq_alloc` HWRM command.
31570 uint16_t cmpl_ring;
31572 * The sequence ID is used by the driver for tracking multiple
31573 * commands. This ID is treated as opaque data by the firmware and
31574 * the value is returned in the `hwrm_resp_hdr` upon completion.
31578 * The target ID of the command:
31579 * * 0x0-0xFFF8 - The function ID
31580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31581 * * 0xFFFD - Reserved for user-space HWRM interface
31584 uint16_t target_id;
31586 * A physical address pointer pointing to a host buffer that the
31587 * command's response data will be written. This can be either a host
31588 * physical address (HPA) or a guest physical address (GPA) and must
31589 * point to a physically contiguous block of memory.
31591 uint64_t resp_addr;
31592 /* Identifies the SCHQ being freed. */
31594 uint8_t unused_0[6];
31597 /* hwrm_ring_schq_free_output (size:128b/16B) */
31598 struct hwrm_ring_schq_free_output {
31599 /* The specific error status for the command. */
31600 uint16_t error_code;
31601 /* The HWRM command request type. */
31603 /* The sequence ID from the original command. */
31605 /* The length of the response data in number of bytes. */
31607 uint8_t unused_0[7];
31609 * This field is used in Output records to indicate that the output
31610 * is completely written to RAM. This field should be read as '1'
31611 * to indicate that the output has been completely written.
31612 * When writing a command completion or response to an internal processor,
31613 * the order of writes has to be such that this field is written last.
31618 * special reserved flow ID to identify per function default
31619 * flows for vSwitch offload
31621 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
31623 * special reserved flow ID to identify per function RoCEv1
31626 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
31628 * special reserved flow ID to identify per function RoCEv2
31631 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
31633 * special reserved flow ID to identify per function RoCEv2
31636 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
31638 /****************************
31639 * hwrm_cfa_l2_filter_alloc *
31640 ****************************/
31643 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
31644 struct hwrm_cfa_l2_filter_alloc_input {
31645 /* The HWRM command request type. */
31648 * The completion ring to send the completion event on. This should
31649 * be the NQ ID returned from the `nq_alloc` HWRM command.
31651 uint16_t cmpl_ring;
31653 * The sequence ID is used by the driver for tracking multiple
31654 * commands. This ID is treated as opaque data by the firmware and
31655 * the value is returned in the `hwrm_resp_hdr` upon completion.
31659 * The target ID of the command:
31660 * * 0x0-0xFFF8 - The function ID
31661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31662 * * 0xFFFD - Reserved for user-space HWRM interface
31665 uint16_t target_id;
31667 * A physical address pointer pointing to a host buffer that the
31668 * command's response data will be written. This can be either a host
31669 * physical address (HPA) or a guest physical address (GPA) and must
31670 * point to a physically contiguous block of memory.
31672 uint64_t resp_addr;
31675 * Enumeration denoting the RX, TX type of the resource.
31676 * This enumeration is used for resources that are similar for both
31677 * TX and RX paths of the chip.
31679 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
31682 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
31685 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
31687 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
31688 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
31689 /* Setting of this flag indicates the applicability to the loopback path. */
31690 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
31693 * Setting of this flag indicates drop action. If this flag is not set,
31694 * then it should be considered accept action.
31696 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
31699 * If this flag is set, all t_l2_* fields are invalid
31700 * and they should not be specified.
31701 * If this flag is set, then l2_* fields refer to
31702 * fields of outermost L2 header.
31704 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
31707 * Enumeration denoting NO_ROCE_L2 to support old drivers.
31708 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
31710 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
31712 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
31713 /* To support old drivers */
31714 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
31715 (UINT32_C(0x0) << 4)
31716 /* Only L2 traffic */
31717 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
31718 (UINT32_C(0x1) << 4)
31719 /* Roce & L2 traffic */
31720 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
31721 (UINT32_C(0x2) << 4)
31722 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
31723 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
31725 * Setting of this flag indicates that no XDP filter is created with
31727 * 0 - legacy behavior, XDP filter is created with L2 filter
31728 * 1 - XDP filter won't be created with L2 filter
31730 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
31733 * Setting this flag to 1 indicate the L2 fields in this command
31734 * pertain to source fields. Setting this flag to 0 indicate the
31735 * L2 fields in this command pertain to the destination fields
31736 * and this is the default/legacy behavior.
31738 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
31742 * This bit must be '1' for the l2_addr field to be
31745 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
31748 * This bit must be '1' for the l2_addr_mask field to be
31751 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
31754 * This bit must be '1' for the l2_ovlan field to be
31757 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
31760 * This bit must be '1' for the l2_ovlan_mask field to be
31763 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
31766 * This bit must be '1' for the l2_ivlan field to be
31769 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
31772 * This bit must be '1' for the l2_ivlan_mask field to be
31775 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
31778 * This bit must be '1' for the t_l2_addr field to be
31781 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
31784 * This bit must be '1' for the t_l2_addr_mask field to be
31787 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
31790 * This bit must be '1' for the t_l2_ovlan field to be
31793 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
31796 * This bit must be '1' for the t_l2_ovlan_mask field to be
31799 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
31802 * This bit must be '1' for the t_l2_ivlan field to be
31805 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
31808 * This bit must be '1' for the t_l2_ivlan_mask field to be
31811 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
31814 * This bit must be '1' for the src_type field to be
31817 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
31820 * This bit must be '1' for the src_id field to be
31823 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
31826 * This bit must be '1' for the tunnel_type field to be
31829 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31832 * This bit must be '1' for the dst_id field to be
31835 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
31838 * This bit must be '1' for the mirror_vnic_id field to be
31841 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31844 * This bit must be '1' for the num_vlans field to be
31847 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
31850 * This bit must be '1' for the t_num_vlans field to be
31853 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
31856 * This value sets the match value for the L2 MAC address.
31857 * Destination MAC address for RX path.
31858 * Source MAC address for TX path.
31860 uint8_t l2_addr[6];
31861 /* This value sets the match value for the number of VLANs. */
31864 * This value sets the match value for the number of VLANs
31865 * in the tunnel headers.
31867 uint8_t t_num_vlans;
31869 * This value sets the mask value for the L2 address.
31870 * A value of 0 will mask the corresponding bit from
31873 uint8_t l2_addr_mask[6];
31874 /* This value sets VLAN ID value for outer VLAN. */
31877 * This value sets the mask value for the ovlan id.
31878 * A value of 0 will mask the corresponding bit from
31881 uint16_t l2_ovlan_mask;
31882 /* This value sets VLAN ID value for inner VLAN. */
31885 * This value sets the mask value for the ivlan id.
31886 * A value of 0 will mask the corresponding bit from
31889 uint16_t l2_ivlan_mask;
31890 uint8_t unused_1[2];
31892 * This value sets the match value for the tunnel
31894 * Destination MAC address for RX path.
31895 * Source MAC address for TX path.
31897 uint8_t t_l2_addr[6];
31898 uint8_t unused_2[2];
31900 * This value sets the mask value for the tunnel L2
31902 * A value of 0 will mask the corresponding bit from
31905 uint8_t t_l2_addr_mask[6];
31906 /* This value sets VLAN ID value for tunnel outer VLAN. */
31907 uint16_t t_l2_ovlan;
31909 * This value sets the mask value for the tunnel ovlan id.
31910 * A value of 0 will mask the corresponding bit from
31913 uint16_t t_l2_ovlan_mask;
31914 /* This value sets VLAN ID value for tunnel inner VLAN. */
31915 uint16_t t_l2_ivlan;
31917 * This value sets the mask value for the tunnel ivlan id.
31918 * A value of 0 will mask the corresponding bit from
31921 uint16_t t_l2_ivlan_mask;
31922 /* This value identifies the type of source of the packet. */
31925 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
31926 /* Physical function */
31927 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
31928 /* Virtual function */
31929 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
31930 /* Virtual NIC of a function */
31931 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
31932 /* Embedded processor for CFA management */
31933 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
31934 /* Embedded processor for OOB management */
31935 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
31936 /* Embedded processor for RoCE */
31937 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
31938 /* Embedded processor for network proxy functions */
31939 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
31940 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
31941 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
31944 * This value is the id of the source.
31945 * For a network port, it represents port_id.
31946 * For a physical function, it represents fid.
31947 * For a virtual function, it represents vf_id.
31948 * For a vnic, it represents vnic_id.
31949 * For embedded processors, this id is not valid.
31952 * 1. The function ID is implied if it src_id is
31953 * not provided for a src_type that is either
31957 uint8_t tunnel_type;
31959 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
31961 /* Virtual eXtensible Local Area Network (VXLAN) */
31962 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
31964 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31965 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
31967 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31968 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
31971 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
31973 /* Generic Network Virtualization Encapsulation (Geneve) */
31974 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
31976 /* Multi-Protocol Label Switching (MPLS) */
31977 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
31979 /* Stateless Transport Tunnel (STT) */
31980 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
31982 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31983 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
31985 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31986 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31988 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31989 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31991 /* Use fixed layer 2 ether type of 0xFFFF */
31992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
31994 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31995 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31997 /* Any tunneled traffic */
31998 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32000 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32001 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32004 * If set, this value shall represent the
32005 * Logical VNIC ID of the destination VNIC for the RX
32006 * path and network port id of the destination port for
32011 * Logical VNIC ID of the VNIC where traffic is
32014 uint16_t mirror_vnic_id;
32016 * This hint is provided to help in placing
32017 * the filter in the filter table.
32020 /* No preference */
32021 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
32023 /* Above the given filter */
32024 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
32026 /* Below the given filter */
32027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
32029 /* As high as possible */
32030 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
32032 /* As low as possible */
32033 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
32035 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
32036 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
32040 * This is the ID of the filter that goes along with
32043 * This field is valid only for the following values.
32044 * 1 - Above the given filter
32045 * 2 - Below the given filter
32047 uint64_t l2_filter_id_hint;
32050 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
32051 struct hwrm_cfa_l2_filter_alloc_output {
32052 /* The specific error status for the command. */
32053 uint16_t error_code;
32054 /* The HWRM command request type. */
32056 /* The sequence ID from the original command. */
32058 /* The length of the response data in number of bytes. */
32061 * This value identifies a set of CFA data structures used for an L2
32064 uint64_t l2_filter_id;
32066 * The flow id value in bit 0-29 is the actual ID of the flow
32067 * associated with this filter and it shall be used to match
32068 * and associate the flow identifier returned in completion
32069 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32070 * shall indicate no valid flow id.
32073 /* Indicate the flow id value. */
32074 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32075 UINT32_C(0x3fffffff)
32076 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32077 /* Indicate type of the flow. */
32078 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
32079 UINT32_C(0x40000000)
32081 * If this bit set to 0, then it indicates that the flow is
32084 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32085 (UINT32_C(0x0) << 30)
32087 * If this bit is set to 1, then it indicates that the flow is
32090 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32091 (UINT32_C(0x1) << 30)
32092 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32093 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32094 /* Indicate the flow direction. */
32095 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
32096 UINT32_C(0x80000000)
32097 /* If this bit set to 0, then it indicates rx flow. */
32098 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32099 (UINT32_C(0x0) << 31)
32100 /* If this bit is set to 1, then it indicates that tx flow. */
32101 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32102 (UINT32_C(0x1) << 31)
32103 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32104 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32105 uint8_t unused_0[3];
32107 * This field is used in Output records to indicate that the output
32108 * is completely written to RAM. This field should be read as '1'
32109 * to indicate that the output has been completely written.
32110 * When writing a command completion or response to an internal processor,
32111 * the order of writes has to be such that this field is written last.
32116 /***************************
32117 * hwrm_cfa_l2_filter_free *
32118 ***************************/
32121 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
32122 struct hwrm_cfa_l2_filter_free_input {
32123 /* The HWRM command request type. */
32126 * The completion ring to send the completion event on. This should
32127 * be the NQ ID returned from the `nq_alloc` HWRM command.
32129 uint16_t cmpl_ring;
32131 * The sequence ID is used by the driver for tracking multiple
32132 * commands. This ID is treated as opaque data by the firmware and
32133 * the value is returned in the `hwrm_resp_hdr` upon completion.
32137 * The target ID of the command:
32138 * * 0x0-0xFFF8 - The function ID
32139 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32140 * * 0xFFFD - Reserved for user-space HWRM interface
32143 uint16_t target_id;
32145 * A physical address pointer pointing to a host buffer that the
32146 * command's response data will be written. This can be either a host
32147 * physical address (HPA) or a guest physical address (GPA) and must
32148 * point to a physically contiguous block of memory.
32150 uint64_t resp_addr;
32152 * This value identifies a set of CFA data structures used for an L2
32155 uint64_t l2_filter_id;
32158 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
32159 struct hwrm_cfa_l2_filter_free_output {
32160 /* The specific error status for the command. */
32161 uint16_t error_code;
32162 /* The HWRM command request type. */
32164 /* The sequence ID from the original command. */
32166 /* The length of the response data in number of bytes. */
32168 uint8_t unused_0[7];
32170 * This field is used in Output records to indicate that the output
32171 * is completely written to RAM. This field should be read as '1'
32172 * to indicate that the output has been completely written.
32173 * When writing a command completion or response to an internal processor,
32174 * the order of writes has to be such that this field is written last.
32179 /**************************
32180 * hwrm_cfa_l2_filter_cfg *
32181 **************************/
32184 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
32185 struct hwrm_cfa_l2_filter_cfg_input {
32186 /* The HWRM command request type. */
32189 * The completion ring to send the completion event on. This should
32190 * be the NQ ID returned from the `nq_alloc` HWRM command.
32192 uint16_t cmpl_ring;
32194 * The sequence ID is used by the driver for tracking multiple
32195 * commands. This ID is treated as opaque data by the firmware and
32196 * the value is returned in the `hwrm_resp_hdr` upon completion.
32200 * The target ID of the command:
32201 * * 0x0-0xFFF8 - The function ID
32202 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32203 * * 0xFFFD - Reserved for user-space HWRM interface
32206 uint16_t target_id;
32208 * A physical address pointer pointing to a host buffer that the
32209 * command's response data will be written. This can be either a host
32210 * physical address (HPA) or a guest physical address (GPA) and must
32211 * point to a physically contiguous block of memory.
32213 uint64_t resp_addr;
32216 * Enumeration denoting the RX, TX type of the resource.
32217 * This enumeration is used for resources that are similar for both
32218 * TX and RX paths of the chip.
32220 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
32223 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
32226 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
32228 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
32229 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
32231 * Setting of this flag indicates drop action. If this flag is not set,
32232 * then it should be considered accept action.
32234 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
32237 * Enumeration denoting NO_ROCE_L2 to support old drivers.
32238 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
32240 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
32242 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
32243 /* To support old drivers */
32244 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
32245 (UINT32_C(0x0) << 2)
32246 /* Only L2 traffic */
32247 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
32248 (UINT32_C(0x1) << 2)
32249 /* Roce & L2 traffic */
32250 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
32251 (UINT32_C(0x2) << 2)
32252 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
32253 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
32256 * This bit must be '1' for the dst_id field to be
32259 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
32262 * This bit must be '1' for the new_mirror_vnic_id field to be
32265 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
32268 * This value identifies a set of CFA data structures used for an L2
32271 uint64_t l2_filter_id;
32273 * If set, this value shall represent the
32274 * Logical VNIC ID of the destination VNIC for the RX
32275 * path and network port id of the destination port for
32280 * New Logical VNIC ID of the VNIC where traffic is
32283 uint32_t new_mirror_vnic_id;
32286 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
32287 struct hwrm_cfa_l2_filter_cfg_output {
32288 /* The specific error status for the command. */
32289 uint16_t error_code;
32290 /* The HWRM command request type. */
32292 /* The sequence ID from the original command. */
32294 /* The length of the response data in number of bytes. */
32296 uint8_t unused_0[7];
32298 * This field is used in Output records to indicate that the output
32299 * is completely written to RAM. This field should be read as '1'
32300 * to indicate that the output has been completely written.
32301 * When writing a command completion or response to an internal processor,
32302 * the order of writes has to be such that this field is written last.
32307 /***************************
32308 * hwrm_cfa_l2_set_rx_mask *
32309 ***************************/
32312 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
32313 struct hwrm_cfa_l2_set_rx_mask_input {
32314 /* The HWRM command request type. */
32317 * The completion ring to send the completion event on. This should
32318 * be the NQ ID returned from the `nq_alloc` HWRM command.
32320 uint16_t cmpl_ring;
32322 * The sequence ID is used by the driver for tracking multiple
32323 * commands. This ID is treated as opaque data by the firmware and
32324 * the value is returned in the `hwrm_resp_hdr` upon completion.
32328 * The target ID of the command:
32329 * * 0x0-0xFFF8 - The function ID
32330 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32331 * * 0xFFFD - Reserved for user-space HWRM interface
32334 uint16_t target_id;
32336 * A physical address pointer pointing to a host buffer that the
32337 * command's response data will be written. This can be either a host
32338 * physical address (HPA) or a guest physical address (GPA) and must
32339 * point to a physically contiguous block of memory.
32341 uint64_t resp_addr;
32346 * When this bit is '1', the function is requested to accept
32347 * multi-cast packets specified by the multicast addr table.
32349 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
32352 * When this bit is '1', the function is requested to accept
32353 * all multi-cast packets.
32355 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
32358 * When this bit is '1', the function is requested to accept
32359 * broadcast packets.
32361 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
32364 * When this bit is '1', the function is requested to be
32365 * put in the promiscuous mode.
32367 * The HWRM should accept any function to set up
32368 * promiscuous mode.
32370 * The HWRM shall follow the semantics below for the
32371 * promiscuous mode support.
32372 * # When partitioning is not enabled on a port
32373 * (i.e. single PF on the port), then the PF shall
32374 * be allowed to be in the promiscuous mode. When the
32375 * PF is in the promiscuous mode, then it shall
32376 * receive all host bound traffic on that port.
32377 * # When partitioning is enabled on a port
32378 * (i.e. multiple PFs per port) and a PF on that
32379 * port is in the promiscuous mode, then the PF
32380 * receives all traffic within that partition as
32381 * identified by a unique identifier for the
32382 * PF (e.g. S-Tag). If a unique outer VLAN
32383 * for the PF is specified, then the setting of
32384 * promiscuous mode on that PF shall result in the
32385 * PF receiving all host bound traffic with matching
32387 * # A VF shall can be set in the promiscuous mode.
32388 * In the promiscuous mode, the VF does not receive any
32389 * traffic unless a unique outer VLAN for the
32390 * VF is specified. If a unique outer VLAN
32391 * for the VF is specified, then the setting of
32392 * promiscuous mode on that VF shall result in the
32393 * VF receiving all host bound traffic with the
32394 * matching outer VLAN.
32395 * # The HWRM shall allow the setting of promiscuous
32396 * mode on a function independently from the
32397 * promiscuous mode settings on other functions.
32399 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
32402 * If this flag is set, the corresponding RX
32403 * filters shall be set up to cover multicast/broadcast
32404 * filters for the outermost Layer 2 destination MAC
32407 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
32410 * If this flag is set, the corresponding RX
32411 * filters shall be set up to cover multicast/broadcast
32412 * filters for the VLAN-tagged packets that match the
32413 * TPID and VID fields of VLAN tags in the VLAN tag
32414 * table specified in this command.
32416 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
32419 * If this flag is set, the corresponding RX
32420 * filters shall be set up to cover multicast/broadcast
32421 * filters for non-VLAN tagged packets and VLAN-tagged
32422 * packets that match the TPID and VID fields of VLAN
32423 * tags in the VLAN tag table specified in this command.
32425 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
32428 * If this flag is set, the corresponding RX
32429 * filters shall be set up to cover multicast/broadcast
32430 * filters for non-VLAN tagged packets and VLAN-tagged
32431 * packets matching any VLAN tag.
32433 * If this flag is set, then the HWRM shall ignore
32434 * VLAN tags specified in vlan_tag_tbl.
32436 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
32437 * flags is set, then the HWRM shall ignore
32438 * VLAN tags specified in vlan_tag_tbl.
32440 * The HWRM client shall set at most one flag out of
32441 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
32443 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
32445 /* This is the address for mcast address tbl. */
32446 uint64_t mc_tbl_addr;
32448 * This value indicates how many entries in mc_tbl are valid.
32449 * Each entry is 6 bytes.
32451 uint32_t num_mc_entries;
32452 uint8_t unused_0[4];
32454 * This is the address for VLAN tag table.
32455 * Each VLAN entry in the table is 4 bytes of a VLAN tag
32456 * including TPID, PCP, DEI, and VID fields in network byte
32459 uint64_t vlan_tag_tbl_addr;
32461 * This value indicates how many entries in vlan_tag_tbl are
32462 * valid. Each entry is 4 bytes.
32464 uint32_t num_vlan_tags;
32465 uint8_t unused_1[4];
32468 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
32469 struct hwrm_cfa_l2_set_rx_mask_output {
32470 /* The specific error status for the command. */
32471 uint16_t error_code;
32472 /* The HWRM command request type. */
32474 /* The sequence ID from the original command. */
32476 /* The length of the response data in number of bytes. */
32478 uint8_t unused_0[7];
32480 * This field is used in Output records to indicate that the output
32481 * is completely written to RAM. This field should be read as '1'
32482 * to indicate that the output has been completely written.
32483 * When writing a command completion or response to an internal processor,
32484 * the order of writes has to be such that this field is written last.
32489 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
32490 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
32492 * command specific error codes that goes to
32493 * the cmd_err field in Common HWRM Error Response.
32496 /* Unknown error */
32497 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
32499 /* Unable to complete operation due to conflict with Ntuple Filter */
32500 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
32502 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
32503 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
32504 uint8_t unused_0[7];
32507 /*******************************
32508 * hwrm_cfa_vlan_antispoof_cfg *
32509 *******************************/
32512 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
32513 struct hwrm_cfa_vlan_antispoof_cfg_input {
32514 /* The HWRM command request type. */
32517 * The completion ring to send the completion event on. This should
32518 * be the NQ ID returned from the `nq_alloc` HWRM command.
32520 uint16_t cmpl_ring;
32522 * The sequence ID is used by the driver for tracking multiple
32523 * commands. This ID is treated as opaque data by the firmware and
32524 * the value is returned in the `hwrm_resp_hdr` upon completion.
32528 * The target ID of the command:
32529 * * 0x0-0xFFF8 - The function ID
32530 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32531 * * 0xFFFD - Reserved for user-space HWRM interface
32534 uint16_t target_id;
32536 * A physical address pointer pointing to a host buffer that the
32537 * command's response data will be written. This can be either a host
32538 * physical address (HPA) or a guest physical address (GPA) and must
32539 * point to a physically contiguous block of memory.
32541 uint64_t resp_addr;
32543 * Function ID of the function that is being configured.
32544 * Only valid for a VF FID configured by the PF.
32547 uint8_t unused_0[2];
32548 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
32549 uint32_t num_vlan_entries;
32551 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
32552 * antispoof table. Each table entry contains the 16-bit TPID
32553 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
32554 * all in network order to match hwrm_cfa_l2_set_rx_mask.
32555 * For an individual VLAN entry, the mask value should be 0xfff
32556 * for the 12-bit VLAN ID.
32558 uint64_t vlan_tag_mask_tbl_addr;
32561 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
32562 struct hwrm_cfa_vlan_antispoof_cfg_output {
32563 /* The specific error status for the command. */
32564 uint16_t error_code;
32565 /* The HWRM command request type. */
32567 /* The sequence ID from the original command. */
32569 /* The length of the response data in number of bytes. */
32571 uint8_t unused_0[7];
32573 * This field is used in Output records to indicate that the output
32574 * is completely written to RAM. This field should be read as '1'
32575 * to indicate that the output has been completely written.
32576 * When writing a command completion or response to an internal processor,
32577 * the order of writes has to be such that this field is written last.
32582 /********************************
32583 * hwrm_cfa_vlan_antispoof_qcfg *
32584 ********************************/
32587 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
32588 struct hwrm_cfa_vlan_antispoof_qcfg_input {
32589 /* The HWRM command request type. */
32592 * The completion ring to send the completion event on. This should
32593 * be the NQ ID returned from the `nq_alloc` HWRM command.
32595 uint16_t cmpl_ring;
32597 * The sequence ID is used by the driver for tracking multiple
32598 * commands. This ID is treated as opaque data by the firmware and
32599 * the value is returned in the `hwrm_resp_hdr` upon completion.
32603 * The target ID of the command:
32604 * * 0x0-0xFFF8 - The function ID
32605 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32606 * * 0xFFFD - Reserved for user-space HWRM interface
32609 uint16_t target_id;
32611 * A physical address pointer pointing to a host buffer that the
32612 * command's response data will be written. This can be either a host
32613 * physical address (HPA) or a guest physical address (GPA) and must
32614 * point to a physically contiguous block of memory.
32616 uint64_t resp_addr;
32618 * Function ID of the function that is being queried.
32619 * Only valid for a VF FID queried by the PF.
32622 uint8_t unused_0[2];
32624 * Maximum number of VLAN entries the firmware is allowed to DMA
32625 * to vlan_tag_mask_tbl.
32627 uint32_t max_vlan_entries;
32629 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
32630 * antispoof table to which firmware will DMA to. Each table
32631 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
32632 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
32633 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
32634 * the mask value should be 0xfff for the 12-bit VLAN ID.
32636 uint64_t vlan_tag_mask_tbl_addr;
32639 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
32640 struct hwrm_cfa_vlan_antispoof_qcfg_output {
32641 /* The specific error status for the command. */
32642 uint16_t error_code;
32643 /* The HWRM command request type. */
32645 /* The sequence ID from the original command. */
32647 /* The length of the response data in number of bytes. */
32649 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
32650 uint32_t num_vlan_entries;
32651 uint8_t unused_0[3];
32653 * This field is used in Output records to indicate that the output
32654 * is completely written to RAM. This field should be read as '1'
32655 * to indicate that the output has been completely written.
32656 * When writing a command completion or response to an internal processor,
32657 * the order of writes has to be such that this field is written last.
32662 /********************************
32663 * hwrm_cfa_tunnel_filter_alloc *
32664 ********************************/
32667 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
32668 struct hwrm_cfa_tunnel_filter_alloc_input {
32669 /* The HWRM command request type. */
32672 * The completion ring to send the completion event on. This should
32673 * be the NQ ID returned from the `nq_alloc` HWRM command.
32675 uint16_t cmpl_ring;
32677 * The sequence ID is used by the driver for tracking multiple
32678 * commands. This ID is treated as opaque data by the firmware and
32679 * the value is returned in the `hwrm_resp_hdr` upon completion.
32683 * The target ID of the command:
32684 * * 0x0-0xFFF8 - The function ID
32685 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32686 * * 0xFFFD - Reserved for user-space HWRM interface
32689 uint16_t target_id;
32691 * A physical address pointer pointing to a host buffer that the
32692 * command's response data will be written. This can be either a host
32693 * physical address (HPA) or a guest physical address (GPA) and must
32694 * point to a physically contiguous block of memory.
32696 uint64_t resp_addr;
32698 /* Setting of this flag indicates the applicability to the loopback path. */
32699 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
32703 * This bit must be '1' for the l2_filter_id field to be
32706 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
32709 * This bit must be '1' for the l2_addr field to be
32712 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
32715 * This bit must be '1' for the l2_ivlan field to be
32718 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
32721 * This bit must be '1' for the l3_addr field to be
32724 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
32727 * This bit must be '1' for the l3_addr_type field to be
32730 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
32733 * This bit must be '1' for the t_l3_addr_type field to be
32736 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
32739 * This bit must be '1' for the t_l3_addr field to be
32742 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
32745 * This bit must be '1' for the tunnel_type field to be
32748 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
32751 * This bit must be '1' for the vni field to be
32754 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
32757 * This bit must be '1' for the dst_vnic_id field to be
32760 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
32763 * This bit must be '1' for the mirror_vnic_id field to be
32766 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
32769 * This value identifies a set of CFA data structures used for an L2
32772 uint64_t l2_filter_id;
32774 * This value sets the match value for the inner L2
32776 * Destination MAC address for RX path.
32777 * Source MAC address for TX path.
32779 uint8_t l2_addr[6];
32781 * This value sets VLAN ID value for inner VLAN.
32782 * Only 12-bits of VLAN ID are used in setting the filter.
32786 * The value of inner destination IP address to be used in filtering.
32787 * For IPv4, first four bytes represent the IP address.
32789 uint32_t l3_addr[4];
32791 * The value of tunnel destination IP address to be used in filtering.
32792 * For IPv4, first four bytes represent the IP address.
32794 uint32_t t_l3_addr[4];
32796 * This value indicates the type of inner IP address.
32799 * All others are invalid.
32801 uint8_t l3_addr_type;
32803 * This value indicates the type of tunnel IP address.
32806 * All others are invalid.
32808 uint8_t t_l3_addr_type;
32810 uint8_t tunnel_type;
32812 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
32814 /* Virtual eXtensible Local Area Network (VXLAN) */
32815 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32817 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
32818 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
32820 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
32821 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
32824 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
32826 /* Generic Network Virtualization Encapsulation (Geneve) */
32827 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32829 /* Multi-Protocol Label Switching (MPLS) */
32830 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
32832 /* Stateless Transport Tunnel (STT) */
32833 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
32835 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
32836 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
32838 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32839 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32841 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32842 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32844 /* Use fixed layer 2 ether type of 0xFFFF */
32845 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32847 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32848 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32850 /* Any tunneled traffic */
32851 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
32853 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32854 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
32856 * tunnel_flags allows the user to indicate the tunnel tag detection
32857 * for the tunnel type specified in tunnel_type.
32859 uint8_t tunnel_flags;
32861 * If the tunnel_type is geneve, then this bit indicates if we
32862 * need to match the geneve OAM packet.
32863 * If the tunnel_type is nvgre or gre, then this bit indicates if
32864 * we need to detect checksum present bit in geneve header.
32865 * If the tunnel_type is mpls, then this bit indicates if we need
32866 * to match mpls packet with explicit IPV4/IPV6 null header.
32868 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
32871 * If the tunnel_type is geneve, then this bit indicates if we
32872 * need to detect the critical option bit set in the oam packet.
32873 * If the tunnel_type is nvgre or gre, then this bit indicates
32874 * if we need to match nvgre packets with key present bit set in
32876 * If the tunnel_type is mpls, then this bit indicates if we
32877 * need to match mpls packet with S bit from inner/second label.
32879 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
32882 * If the tunnel_type is geneve, then this bit indicates if we
32883 * need to match geneve packet with extended header bit set in
32885 * If the tunnel_type is nvgre or gre, then this bit indicates
32886 * if we need to match nvgre packets with sequence number
32887 * present bit set in gre header.
32888 * If the tunnel_type is mpls, then this bit indicates if we
32889 * need to match mpls packet with S bit from out/first label.
32891 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
32894 * Virtual Network Identifier (VNI). Only valid with
32895 * tunnel_types VXLAN, NVGRE, and Geneve.
32896 * Only lower 24-bits of VNI field are used
32897 * in setting up the filter.
32900 /* Logical VNIC ID of the destination VNIC. */
32901 uint32_t dst_vnic_id;
32903 * Logical VNIC ID of the VNIC where traffic is
32906 uint32_t mirror_vnic_id;
32909 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
32910 struct hwrm_cfa_tunnel_filter_alloc_output {
32911 /* The specific error status for the command. */
32912 uint16_t error_code;
32913 /* The HWRM command request type. */
32915 /* The sequence ID from the original command. */
32917 /* The length of the response data in number of bytes. */
32919 /* This value is an opaque id into CFA data structures. */
32920 uint64_t tunnel_filter_id;
32922 * The flow id value in bit 0-29 is the actual ID of the flow
32923 * associated with this filter and it shall be used to match
32924 * and associate the flow identifier returned in completion
32925 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32926 * shall indicate no valid flow id.
32929 /* Indicate the flow id value. */
32930 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32931 UINT32_C(0x3fffffff)
32932 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32933 /* Indicate type of the flow. */
32934 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
32935 UINT32_C(0x40000000)
32937 * If this bit set to 0, then it indicates that the flow is
32940 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32941 (UINT32_C(0x0) << 30)
32943 * If this bit is set to 1, then it indicates that the flow is
32946 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32947 (UINT32_C(0x1) << 30)
32948 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32949 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32950 /* Indicate the flow direction. */
32951 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
32952 UINT32_C(0x80000000)
32953 /* If this bit set to 0, then it indicates rx flow. */
32954 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32955 (UINT32_C(0x0) << 31)
32956 /* If this bit is set to 1, then it indicates that tx flow. */
32957 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32958 (UINT32_C(0x1) << 31)
32959 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32960 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32961 uint8_t unused_0[3];
32963 * This field is used in Output records to indicate that the output
32964 * is completely written to RAM. This field should be read as '1'
32965 * to indicate that the output has been completely written.
32966 * When writing a command completion or response to an internal processor,
32967 * the order of writes has to be such that this field is written last.
32972 /*******************************
32973 * hwrm_cfa_tunnel_filter_free *
32974 *******************************/
32977 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
32978 struct hwrm_cfa_tunnel_filter_free_input {
32979 /* The HWRM command request type. */
32982 * The completion ring to send the completion event on. This should
32983 * be the NQ ID returned from the `nq_alloc` HWRM command.
32985 uint16_t cmpl_ring;
32987 * The sequence ID is used by the driver for tracking multiple
32988 * commands. This ID is treated as opaque data by the firmware and
32989 * the value is returned in the `hwrm_resp_hdr` upon completion.
32993 * The target ID of the command:
32994 * * 0x0-0xFFF8 - The function ID
32995 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32996 * * 0xFFFD - Reserved for user-space HWRM interface
32999 uint16_t target_id;
33001 * A physical address pointer pointing to a host buffer that the
33002 * command's response data will be written. This can be either a host
33003 * physical address (HPA) or a guest physical address (GPA) and must
33004 * point to a physically contiguous block of memory.
33006 uint64_t resp_addr;
33007 /* This value is an opaque id into CFA data structures. */
33008 uint64_t tunnel_filter_id;
33011 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
33012 struct hwrm_cfa_tunnel_filter_free_output {
33013 /* The specific error status for the command. */
33014 uint16_t error_code;
33015 /* The HWRM command request type. */
33017 /* The sequence ID from the original command. */
33019 /* The length of the response data in number of bytes. */
33021 uint8_t unused_0[7];
33023 * This field is used in Output records to indicate that the output
33024 * is completely written to RAM. This field should be read as '1'
33025 * to indicate that the output has been completely written.
33026 * When writing a command completion or response to an internal processor,
33027 * the order of writes has to be such that this field is written last.
33032 /***************************************
33033 * hwrm_cfa_redirect_tunnel_type_alloc *
33034 ***************************************/
33037 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
33038 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
33039 /* The HWRM command request type. */
33042 * The completion ring to send the completion event on. This should
33043 * be the NQ ID returned from the `nq_alloc` HWRM command.
33045 uint16_t cmpl_ring;
33047 * The sequence ID is used by the driver for tracking multiple
33048 * commands. This ID is treated as opaque data by the firmware and
33049 * the value is returned in the `hwrm_resp_hdr` upon completion.
33053 * The target ID of the command:
33054 * * 0x0-0xFFF8 - The function ID
33055 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33056 * * 0xFFFD - Reserved for user-space HWRM interface
33059 uint16_t target_id;
33061 * A physical address pointer pointing to a host buffer that the
33062 * command's response data will be written. This can be either a host
33063 * physical address (HPA) or a guest physical address (GPA) and must
33064 * point to a physically contiguous block of memory.
33066 uint64_t resp_addr;
33067 /* The destination function id, to whom the traffic is redirected. */
33070 uint8_t tunnel_type;
33072 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33074 /* Virtual eXtensible Local Area Network (VXLAN) */
33075 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33077 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33078 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33080 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33081 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33084 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33086 /* Generic Network Virtualization Encapsulation (Geneve) */
33087 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33089 /* Multi-Protocol Label Switching (MPLS) */
33090 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33092 /* Stateless Transport Tunnel (STT) */
33093 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
33095 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33098 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33101 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33102 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33104 /* Use fixed layer 2 ether type of 0xFFFF */
33105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33107 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33110 /* Any tunneled traffic */
33111 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33113 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33114 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33115 /* Tunnel alloc flags. */
33117 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
33118 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
33120 uint8_t unused_0[4];
33123 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
33124 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
33125 /* The specific error status for the command. */
33126 uint16_t error_code;
33127 /* The HWRM command request type. */
33129 /* The sequence ID from the original command. */
33131 /* The length of the response data in number of bytes. */
33133 uint8_t unused_0[7];
33135 * This field is used in Output records to indicate that the output
33136 * is completely written to RAM. This field should be read as '1'
33137 * to indicate that the output has been completely written.
33138 * When writing a command completion or response to an internal processor,
33139 * the order of writes has to be such that this field is written last.
33144 /**************************************
33145 * hwrm_cfa_redirect_tunnel_type_free *
33146 **************************************/
33149 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
33150 struct hwrm_cfa_redirect_tunnel_type_free_input {
33151 /* The HWRM command request type. */
33154 * The completion ring to send the completion event on. This should
33155 * be the NQ ID returned from the `nq_alloc` HWRM command.
33157 uint16_t cmpl_ring;
33159 * The sequence ID is used by the driver for tracking multiple
33160 * commands. This ID is treated as opaque data by the firmware and
33161 * the value is returned in the `hwrm_resp_hdr` upon completion.
33165 * The target ID of the command:
33166 * * 0x0-0xFFF8 - The function ID
33167 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33168 * * 0xFFFD - Reserved for user-space HWRM interface
33171 uint16_t target_id;
33173 * A physical address pointer pointing to a host buffer that the
33174 * command's response data will be written. This can be either a host
33175 * physical address (HPA) or a guest physical address (GPA) and must
33176 * point to a physically contiguous block of memory.
33178 uint64_t resp_addr;
33179 /* The destination function id, to whom the traffic is redirected. */
33182 uint8_t tunnel_type;
33184 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
33186 /* Virtual eXtensible Local Area Network (VXLAN) */
33187 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
33189 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33190 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
33192 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33193 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
33196 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
33198 /* Generic Network Virtualization Encapsulation (Geneve) */
33199 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
33201 /* Multi-Protocol Label Switching (MPLS) */
33202 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
33204 /* Stateless Transport Tunnel (STT) */
33205 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
33207 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33208 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
33210 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33211 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33213 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33214 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33216 /* Use fixed layer 2 ether type of 0xFFFF */
33217 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
33219 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33220 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33222 /* Any tunneled traffic */
33223 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
33226 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
33227 uint8_t unused_0[5];
33230 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
33231 struct hwrm_cfa_redirect_tunnel_type_free_output {
33232 /* The specific error status for the command. */
33233 uint16_t error_code;
33234 /* The HWRM command request type. */
33236 /* The sequence ID from the original command. */
33238 /* The length of the response data in number of bytes. */
33240 uint8_t unused_0[7];
33242 * This field is used in Output records to indicate that the output
33243 * is completely written to RAM. This field should be read as '1'
33244 * to indicate that the output has been completely written.
33245 * When writing a command completion or response to an internal processor,
33246 * the order of writes has to be such that this field is written last.
33251 /**************************************
33252 * hwrm_cfa_redirect_tunnel_type_info *
33253 **************************************/
33256 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
33257 struct hwrm_cfa_redirect_tunnel_type_info_input {
33258 /* The HWRM command request type. */
33261 * The completion ring to send the completion event on. This should
33262 * be the NQ ID returned from the `nq_alloc` HWRM command.
33264 uint16_t cmpl_ring;
33266 * The sequence ID is used by the driver for tracking multiple
33267 * commands. This ID is treated as opaque data by the firmware and
33268 * the value is returned in the `hwrm_resp_hdr` upon completion.
33272 * The target ID of the command:
33273 * * 0x0-0xFFF8 - The function ID
33274 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33275 * * 0xFFFD - Reserved for user-space HWRM interface
33278 uint16_t target_id;
33280 * A physical address pointer pointing to a host buffer that the
33281 * command's response data will be written. This can be either a host
33282 * physical address (HPA) or a guest physical address (GPA) and must
33283 * point to a physically contiguous block of memory.
33285 uint64_t resp_addr;
33286 /* The source function id. */
33289 uint8_t tunnel_type;
33291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
33293 /* Virtual eXtensible Local Area Network (VXLAN) */
33294 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
33296 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33297 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
33299 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33300 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
33303 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
33305 /* Generic Network Virtualization Encapsulation (Geneve) */
33306 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
33308 /* Multi-Protocol Label Switching (MPLS) */
33309 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
33311 /* Stateless Transport Tunnel (STT) */
33312 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
33314 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33315 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
33317 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33318 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33320 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33321 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33323 /* Use fixed layer 2 ether type of 0xFFFF */
33324 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
33326 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33327 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33329 /* Any tunneled traffic */
33330 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33332 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
33333 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
33334 uint8_t unused_0[5];
33337 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
33338 struct hwrm_cfa_redirect_tunnel_type_info_output {
33339 /* The specific error status for the command. */
33340 uint16_t error_code;
33341 /* The HWRM command request type. */
33343 /* The sequence ID from the original command. */
33345 /* The length of the response data in number of bytes. */
33347 /* The destination function id, to whom the traffic is redirected. */
33349 uint8_t unused_0[5];
33351 * This field is used in Output records to indicate that the output
33352 * is completely written to RAM. This field should be read as '1'
33353 * to indicate that the output has been completely written.
33354 * When writing a command completion or response to an internal processor,
33355 * the order of writes has to be such that this field is written last.
33360 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
33361 struct hwrm_vxlan_ipv4_hdr {
33362 /* IPv4 version and header length. */
33364 /* IPv4 header length */
33365 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
33366 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
33368 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
33369 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
33370 /* IPv4 type of service. */
33372 /* IPv4 identification. */
33374 /* IPv4 flags and offset. */
33375 uint16_t flags_frag_offset;
33378 /* IPv4 protocol. */
33380 /* IPv4 source address. */
33381 uint32_t src_ip_addr;
33382 /* IPv4 destination address. */
33383 uint32_t dest_ip_addr;
33386 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
33387 struct hwrm_vxlan_ipv6_hdr {
33388 /* IPv6 version, traffic class and flow label. */
33389 uint32_t ver_tc_flow_label;
33390 /* IPv6 version shift */
33391 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
33393 /* IPv6 version mask */
33394 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
33395 UINT32_C(0xf0000000)
33396 /* IPv6 TC shift */
33397 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
33400 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
33401 UINT32_C(0xff00000)
33402 /* IPv6 flow label shift */
33403 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
33405 /* IPv6 flow label mask */
33406 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
33408 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
33409 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
33410 /* IPv6 payload length. */
33411 uint16_t payload_len;
33412 /* IPv6 next header. */
33416 /* IPv6 source address. */
33417 uint32_t src_ip_addr[4];
33418 /* IPv6 destination address. */
33419 uint32_t dest_ip_addr[4];
33422 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
33423 struct hwrm_cfa_encap_data_vxlan {
33424 /* Source MAC address. */
33425 uint8_t src_mac_addr[6];
33428 /* Destination MAC address. */
33429 uint8_t dst_mac_addr[6];
33430 /* Number of VLAN tags. */
33431 uint8_t num_vlan_tags;
33434 /* Outer VLAN TPID. */
33435 uint16_t ovlan_tpid;
33436 /* Outer VLAN TCI. */
33437 uint16_t ovlan_tci;
33438 /* Inner VLAN TPID. */
33439 uint16_t ivlan_tpid;
33440 /* Inner VLAN TCI. */
33441 uint16_t ivlan_tci;
33442 /* L3 header fields. */
33444 /* IP version mask. */
33445 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
33446 /* IP version 4. */
33447 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
33448 /* IP version 6. */
33449 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
33450 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
33451 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
33452 /* UDP source port. */
33454 /* UDP destination port. */
33456 /* VXLAN Network Identifier. */
33458 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
33459 uint8_t hdr_rsvd0[3];
33460 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
33462 /* VXLAN header flags field. */
33467 /*******************************
33468 * hwrm_cfa_encap_record_alloc *
33469 *******************************/
33472 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
33473 struct hwrm_cfa_encap_record_alloc_input {
33474 /* The HWRM command request type. */
33477 * The completion ring to send the completion event on. This should
33478 * be the NQ ID returned from the `nq_alloc` HWRM command.
33480 uint16_t cmpl_ring;
33482 * The sequence ID is used by the driver for tracking multiple
33483 * commands. This ID is treated as opaque data by the firmware and
33484 * the value is returned in the `hwrm_resp_hdr` upon completion.
33488 * The target ID of the command:
33489 * * 0x0-0xFFF8 - The function ID
33490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33491 * * 0xFFFD - Reserved for user-space HWRM interface
33494 uint16_t target_id;
33496 * A physical address pointer pointing to a host buffer that the
33497 * command's response data will be written. This can be either a host
33498 * physical address (HPA) or a guest physical address (GPA) and must
33499 * point to a physically contiguous block of memory.
33501 uint64_t resp_addr;
33503 /* Setting of this flag indicates the applicability to the loopback path. */
33504 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
33507 * Setting of this flag indicates this encap record is external encap record.
33508 * Resetting of this flag indicates this flag is internal encap record and
33509 * this is the default setting.
33511 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
33513 /* Encapsulation Type. */
33514 uint8_t encap_type;
33515 /* Virtual eXtensible Local Area Network (VXLAN) */
33516 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
33518 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33519 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
33521 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
33522 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
33525 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
33527 /* Generic Network Virtualization Encapsulation (Geneve) */
33528 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
33530 /* Multi-Protocol Label Switching (MPLS) */
33531 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
33534 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
33536 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33537 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
33539 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33540 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
33542 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33543 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
33545 /* Use fixed layer 2 ether type of 0xFFFF */
33546 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
33548 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33549 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
33551 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
33552 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
33553 uint8_t unused_0[3];
33554 /* This value is encap data used for the given encap type. */
33555 uint32_t encap_data[20];
33558 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
33559 struct hwrm_cfa_encap_record_alloc_output {
33560 /* The specific error status for the command. */
33561 uint16_t error_code;
33562 /* The HWRM command request type. */
33564 /* The sequence ID from the original command. */
33566 /* The length of the response data in number of bytes. */
33568 /* This value is an opaque id into CFA data structures. */
33569 uint32_t encap_record_id;
33570 uint8_t unused_0[3];
33572 * This field is used in Output records to indicate that the output
33573 * is completely written to RAM. This field should be read as '1'
33574 * to indicate that the output has been completely written.
33575 * When writing a command completion or response to an internal processor,
33576 * the order of writes has to be such that this field is written last.
33581 /******************************
33582 * hwrm_cfa_encap_record_free *
33583 ******************************/
33586 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
33587 struct hwrm_cfa_encap_record_free_input {
33588 /* The HWRM command request type. */
33591 * The completion ring to send the completion event on. This should
33592 * be the NQ ID returned from the `nq_alloc` HWRM command.
33594 uint16_t cmpl_ring;
33596 * The sequence ID is used by the driver for tracking multiple
33597 * commands. This ID is treated as opaque data by the firmware and
33598 * the value is returned in the `hwrm_resp_hdr` upon completion.
33602 * The target ID of the command:
33603 * * 0x0-0xFFF8 - The function ID
33604 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33605 * * 0xFFFD - Reserved for user-space HWRM interface
33608 uint16_t target_id;
33610 * A physical address pointer pointing to a host buffer that the
33611 * command's response data will be written. This can be either a host
33612 * physical address (HPA) or a guest physical address (GPA) and must
33613 * point to a physically contiguous block of memory.
33615 uint64_t resp_addr;
33616 /* This value is an opaque id into CFA data structures. */
33617 uint32_t encap_record_id;
33618 uint8_t unused_0[4];
33621 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
33622 struct hwrm_cfa_encap_record_free_output {
33623 /* The specific error status for the command. */
33624 uint16_t error_code;
33625 /* The HWRM command request type. */
33627 /* The sequence ID from the original command. */
33629 /* The length of the response data in number of bytes. */
33631 uint8_t unused_0[7];
33633 * This field is used in Output records to indicate that the output
33634 * is completely written to RAM. This field should be read as '1'
33635 * to indicate that the output has been completely written.
33636 * When writing a command completion or response to an internal processor,
33637 * the order of writes has to be such that this field is written last.
33642 /********************************
33643 * hwrm_cfa_ntuple_filter_alloc *
33644 ********************************/
33647 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
33648 struct hwrm_cfa_ntuple_filter_alloc_input {
33649 /* The HWRM command request type. */
33652 * The completion ring to send the completion event on. This should
33653 * be the NQ ID returned from the `nq_alloc` HWRM command.
33655 uint16_t cmpl_ring;
33657 * The sequence ID is used by the driver for tracking multiple
33658 * commands. This ID is treated as opaque data by the firmware and
33659 * the value is returned in the `hwrm_resp_hdr` upon completion.
33663 * The target ID of the command:
33664 * * 0x0-0xFFF8 - The function ID
33665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33666 * * 0xFFFD - Reserved for user-space HWRM interface
33669 uint16_t target_id;
33671 * A physical address pointer pointing to a host buffer that the
33672 * command's response data will be written. This can be either a host
33673 * physical address (HPA) or a guest physical address (GPA) and must
33674 * point to a physically contiguous block of memory.
33676 uint64_t resp_addr;
33678 /* Setting of this flag indicates the applicability to the loopback path. */
33679 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
33682 * Setting of this flag indicates drop action. If this flag is not set,
33683 * then it should be considered accept action.
33685 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
33688 * Setting of this flag indicates that a meter is expected to be attached
33689 * to this flow. This hint can be used when choosing the action record
33690 * format required for the flow.
33692 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
33695 * Setting of this flag indicates that the dst_id field contains function ID.
33696 * If this is not set it indicates dest_id is VNIC or VPORT.
33698 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
33701 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
33702 * If this is not set it indicates no specific arp opcode matching.
33704 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
33707 * Setting of this flag indicates that the dst_id field contains RFS ring
33708 * table index. If this is not set it indicates dst_id is VNIC or VPORT
33709 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
33712 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
33716 * This bit must be '1' for the l2_filter_id field to be
33719 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
33722 * This bit must be '1' for the ethertype field to be
33725 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
33728 * This bit must be '1' for the tunnel_type field to be
33731 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33734 * This bit must be '1' for the src_macaddr field to be
33737 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
33740 * This bit must be '1' for the ipaddr_type field to be
33743 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
33746 * This bit must be '1' for the src_ipaddr field to be
33749 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
33752 * This bit must be '1' for the src_ipaddr_mask field to be
33755 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
33758 * This bit must be '1' for the dst_ipaddr field to be
33761 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
33764 * This bit must be '1' for the dst_ipaddr_mask field to be
33767 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
33770 * This bit must be '1' for the ip_protocol field to be
33773 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
33776 * This bit must be '1' for the src_port field to be
33779 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
33782 * This bit must be '1' for the src_port_mask field to be
33785 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
33788 * This bit must be '1' for the dst_port field to be
33791 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
33794 * This bit must be '1' for the dst_port_mask field to be
33797 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
33800 * This bit must be '1' for the pri_hint field to be
33803 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
33806 * This bit must be '1' for the ntuple_filter_id field to be
33809 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
33812 * This bit must be '1' for the dst_id field to be
33815 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33818 * This bit must be '1' for the mirror_vnic_id field to be
33821 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33824 * This bit must be '1' for the dst_macaddr field to be
33827 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
33829 /* This flag is deprecated. */
33830 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
33833 * This value identifies a set of CFA data structures used for an L2
33836 uint64_t l2_filter_id;
33838 * This value indicates the source MAC address in
33839 * the Ethernet header.
33841 uint8_t src_macaddr[6];
33842 /* This value indicates the ethertype in the Ethernet header. */
33843 uint16_t ethertype;
33845 * This value indicates the type of IP address.
33848 * All others are invalid.
33850 uint8_t ip_addr_type;
33852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
33855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
33858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
33860 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
33861 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
33863 * The value of protocol filed in IP header.
33864 * Applies to UDP and TCP traffic.
33868 uint8_t ip_protocol;
33870 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
33873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
33876 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
33878 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
33879 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
33881 * If set, this value shall represent the
33882 * Logical VNIC ID of the destination VNIC for the RX
33883 * path and network port id of the destination port for
33888 * Logical VNIC ID of the VNIC where traffic is
33891 uint16_t mirror_vnic_id;
33893 * This value indicates the tunnel type for this filter.
33894 * If this field is not specified, then the filter shall
33895 * apply to both non-tunneled and tunneled packets.
33896 * If this field conflicts with the tunnel_type specified
33897 * in the l2_filter_id, then the HWRM shall return an
33898 * error for this command.
33900 uint8_t tunnel_type;
33902 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33904 /* Virtual eXtensible Local Area Network (VXLAN) */
33905 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33907 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33908 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33910 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33911 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33914 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33916 /* Generic Network Virtualization Encapsulation (Geneve) */
33917 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33919 /* Multi-Protocol Label Switching (MPLS) */
33920 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33922 /* Stateless Transport Tunnel (STT) */
33923 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33925 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33926 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33928 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33929 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33931 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33932 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33934 /* Use fixed layer 2 ether type of 0xFFFF */
33935 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33937 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33938 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33940 /* Any tunneled traffic */
33941 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33943 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33944 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33946 * This hint is provided to help in placing
33947 * the filter in the filter table.
33950 /* No preference */
33951 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
33953 /* Above the given filter */
33954 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
33956 /* Below the given filter */
33957 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
33959 /* As high as possible */
33960 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
33962 /* As low as possible */
33963 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
33965 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
33966 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
33968 * The value of source IP address to be used in filtering.
33969 * For IPv4, first four bytes represent the IP address.
33971 uint32_t src_ipaddr[4];
33973 * The value of source IP address mask to be used in
33975 * For IPv4, first four bytes represent the IP address mask.
33977 uint32_t src_ipaddr_mask[4];
33979 * The value of destination IP address to be used in filtering.
33980 * For IPv4, first four bytes represent the IP address.
33982 uint32_t dst_ipaddr[4];
33984 * The value of destination IP address mask to be used in
33986 * For IPv4, first four bytes represent the IP address mask.
33988 uint32_t dst_ipaddr_mask[4];
33990 * The value of source port to be used in filtering.
33991 * Applies to UDP and TCP traffic.
33995 * The value of source port mask to be used in filtering.
33996 * Applies to UDP and TCP traffic.
33998 uint16_t src_port_mask;
34000 * The value of destination port to be used in filtering.
34001 * Applies to UDP and TCP traffic.
34005 * The value of destination port mask to be used in
34007 * Applies to UDP and TCP traffic.
34009 uint16_t dst_port_mask;
34011 * This is the ID of the filter that goes along with
34014 uint64_t ntuple_filter_id_hint;
34017 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
34018 struct hwrm_cfa_ntuple_filter_alloc_output {
34019 /* The specific error status for the command. */
34020 uint16_t error_code;
34021 /* The HWRM command request type. */
34023 /* The sequence ID from the original command. */
34025 /* The length of the response data in number of bytes. */
34027 /* This value is an opaque id into CFA data structures. */
34028 uint64_t ntuple_filter_id;
34030 * The flow id value in bit 0-29 is the actual ID of the flow
34031 * associated with this filter and it shall be used to match
34032 * and associate the flow identifier returned in completion
34033 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34034 * shall indicate no valid flow id.
34037 /* Indicate the flow id value. */
34038 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34039 UINT32_C(0x3fffffff)
34040 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34041 /* Indicate type of the flow. */
34042 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
34043 UINT32_C(0x40000000)
34045 * If this bit set to 0, then it indicates that the flow is
34048 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34049 (UINT32_C(0x0) << 30)
34051 * If this bit is set to 1, then it indicates that the flow is
34054 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34055 (UINT32_C(0x1) << 30)
34056 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34057 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34058 /* Indicate the flow direction. */
34059 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
34060 UINT32_C(0x80000000)
34061 /* If this bit set to 0, then it indicates rx flow. */
34062 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34063 (UINT32_C(0x0) << 31)
34064 /* If this bit is set to 1, then it indicates that tx flow. */
34065 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34066 (UINT32_C(0x1) << 31)
34067 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34068 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34069 uint8_t unused_0[3];
34071 * This field is used in Output records to indicate that the output
34072 * is completely written to RAM. This field should be read as '1'
34073 * to indicate that the output has been completely written.
34074 * When writing a command completion or response to an internal processor,
34075 * the order of writes has to be such that this field is written last.
34080 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
34081 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
34083 * command specific error codes that goes to
34084 * the cmd_err field in Common HWRM Error Response.
34087 /* Unknown error */
34088 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
34090 /* Unable to complete operation due to conflict with Rx Mask VLAN */
34091 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
34093 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
34094 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
34095 uint8_t unused_0[7];
34098 /*******************************
34099 * hwrm_cfa_ntuple_filter_free *
34100 *******************************/
34103 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
34104 struct hwrm_cfa_ntuple_filter_free_input {
34105 /* The HWRM command request type. */
34108 * The completion ring to send the completion event on. This should
34109 * be the NQ ID returned from the `nq_alloc` HWRM command.
34111 uint16_t cmpl_ring;
34113 * The sequence ID is used by the driver for tracking multiple
34114 * commands. This ID is treated as opaque data by the firmware and
34115 * the value is returned in the `hwrm_resp_hdr` upon completion.
34119 * The target ID of the command:
34120 * * 0x0-0xFFF8 - The function ID
34121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34122 * * 0xFFFD - Reserved for user-space HWRM interface
34125 uint16_t target_id;
34127 * A physical address pointer pointing to a host buffer that the
34128 * command's response data will be written. This can be either a host
34129 * physical address (HPA) or a guest physical address (GPA) and must
34130 * point to a physically contiguous block of memory.
34132 uint64_t resp_addr;
34133 /* This value is an opaque id into CFA data structures. */
34134 uint64_t ntuple_filter_id;
34137 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
34138 struct hwrm_cfa_ntuple_filter_free_output {
34139 /* The specific error status for the command. */
34140 uint16_t error_code;
34141 /* The HWRM command request type. */
34143 /* The sequence ID from the original command. */
34145 /* The length of the response data in number of bytes. */
34147 uint8_t unused_0[7];
34149 * This field is used in Output records to indicate that the output
34150 * is completely written to RAM. This field should be read as '1'
34151 * to indicate that the output has been completely written.
34152 * When writing a command completion or response to an internal processor,
34153 * the order of writes has to be such that this field is written last.
34158 /******************************
34159 * hwrm_cfa_ntuple_filter_cfg *
34160 ******************************/
34163 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
34164 struct hwrm_cfa_ntuple_filter_cfg_input {
34165 /* The HWRM command request type. */
34168 * The completion ring to send the completion event on. This should
34169 * be the NQ ID returned from the `nq_alloc` HWRM command.
34171 uint16_t cmpl_ring;
34173 * The sequence ID is used by the driver for tracking multiple
34174 * commands. This ID is treated as opaque data by the firmware and
34175 * the value is returned in the `hwrm_resp_hdr` upon completion.
34179 * The target ID of the command:
34180 * * 0x0-0xFFF8 - The function ID
34181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34182 * * 0xFFFD - Reserved for user-space HWRM interface
34185 uint16_t target_id;
34187 * A physical address pointer pointing to a host buffer that the
34188 * command's response data will be written. This can be either a host
34189 * physical address (HPA) or a guest physical address (GPA) and must
34190 * point to a physically contiguous block of memory.
34192 uint64_t resp_addr;
34195 * This bit must be '1' for the new_dst_id field to be
34198 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
34201 * This bit must be '1' for the new_mirror_vnic_id field to be
34204 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
34207 * This bit must be '1' for the new_meter_instance_id field to be
34210 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
34214 * Setting this bit to 1 indicates that dest_id field contains FID.
34215 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
34217 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
34220 * Setting of this flag indicates that the new_dst_id field contains
34221 * RFS ring table index. If this is not set it indicates new_dst_id is
34222 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
34223 * can’t be set at the same time.
34225 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
34227 /* This value is an opaque id into CFA data structures. */
34228 uint64_t ntuple_filter_id;
34230 * If set, this value shall represent the new
34231 * Logical VNIC ID of the destination VNIC for the RX
34232 * path and new network port id of the destination port for
34235 uint32_t new_dst_id;
34237 * New Logical VNIC ID of the VNIC where traffic is
34240 uint32_t new_mirror_vnic_id;
34242 * New meter to attach to the flow. Specifying the
34243 * invalid instance ID is used to remove any existing
34244 * meter from the flow.
34246 uint16_t new_meter_instance_id;
34248 * A value of 0xfff is considered invalid and implies the
34249 * instance is not configured.
34251 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
34253 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
34254 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
34255 uint8_t unused_1[6];
34258 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
34259 struct hwrm_cfa_ntuple_filter_cfg_output {
34260 /* The specific error status for the command. */
34261 uint16_t error_code;
34262 /* The HWRM command request type. */
34264 /* The sequence ID from the original command. */
34266 /* The length of the response data in number of bytes. */
34268 uint8_t unused_0[7];
34270 * This field is used in Output records to indicate that the output
34271 * is completely written to RAM. This field should be read as '1'
34272 * to indicate that the output has been completely written.
34273 * When writing a command completion or response to an internal processor,
34274 * the order of writes has to be such that this field is written last.
34279 /**************************
34280 * hwrm_cfa_em_flow_alloc *
34281 **************************/
34284 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
34285 struct hwrm_cfa_em_flow_alloc_input {
34286 /* The HWRM command request type. */
34289 * The completion ring to send the completion event on. This should
34290 * be the NQ ID returned from the `nq_alloc` HWRM command.
34292 uint16_t cmpl_ring;
34294 * The sequence ID is used by the driver for tracking multiple
34295 * commands. This ID is treated as opaque data by the firmware and
34296 * the value is returned in the `hwrm_resp_hdr` upon completion.
34300 * The target ID of the command:
34301 * * 0x0-0xFFF8 - The function ID
34302 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34303 * * 0xFFFD - Reserved for user-space HWRM interface
34306 uint16_t target_id;
34308 * A physical address pointer pointing to a host buffer that the
34309 * command's response data will be written. This can be either a host
34310 * physical address (HPA) or a guest physical address (GPA) and must
34311 * point to a physically contiguous block of memory.
34313 uint64_t resp_addr;
34316 * Enumeration denoting the RX, TX type of the resource.
34317 * This enumeration is used for resources that are similar for both
34318 * TX and RX paths of the chip.
34320 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
34322 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34324 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34325 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
34326 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
34328 * Setting of this flag indicates enabling of a byte counter for a given
34331 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
34333 * Setting of this flag indicates enabling of a packet counter for a given
34336 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
34337 /* Setting of this flag indicates de-capsulation action for the given flow. */
34338 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
34339 /* Setting of this flag indicates encapsulation action for the given flow. */
34340 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
34342 * Setting of this flag indicates drop action. If this flag is not set,
34343 * then it should be considered accept action.
34345 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
34347 * Setting of this flag indicates that a meter is expected to be attached
34348 * to this flow. This hint can be used when choosing the action record
34349 * format required for the flow.
34351 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
34354 * This bit must be '1' for the l2_filter_id field to be
34357 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
34360 * This bit must be '1' for the tunnel_type field to be
34363 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
34366 * This bit must be '1' for the tunnel_id field to be
34369 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
34372 * This bit must be '1' for the src_macaddr field to be
34375 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
34378 * This bit must be '1' for the dst_macaddr field to be
34381 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
34384 * This bit must be '1' for the ovlan_vid field to be
34387 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
34390 * This bit must be '1' for the ivlan_vid field to be
34393 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
34396 * This bit must be '1' for the ethertype field to be
34399 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
34402 * This bit must be '1' for the src_ipaddr field to be
34405 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
34408 * This bit must be '1' for the dst_ipaddr field to be
34411 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
34414 * This bit must be '1' for the ipaddr_type field to be
34417 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
34420 * This bit must be '1' for the ip_protocol field to be
34423 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
34426 * This bit must be '1' for the src_port field to be
34429 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
34432 * This bit must be '1' for the dst_port field to be
34435 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
34438 * This bit must be '1' for the dst_id field to be
34441 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
34444 * This bit must be '1' for the mirror_vnic_id field to be
34447 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
34450 * This bit must be '1' for the encap_record_id field to be
34453 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
34456 * This bit must be '1' for the meter_instance_id field to be
34459 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
34462 * This value identifies a set of CFA data structures used for an L2
34465 uint64_t l2_filter_id;
34467 uint8_t tunnel_type;
34469 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34471 /* Virtual eXtensible Local Area Network (VXLAN) */
34472 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34474 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34475 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34477 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34478 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34481 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34483 /* Generic Network Virtualization Encapsulation (Geneve) */
34484 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34486 /* Multi-Protocol Label Switching (MPLS) */
34487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34489 /* Stateless Transport Tunnel (STT) */
34490 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
34492 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34493 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34495 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34496 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34498 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34499 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34501 /* Use fixed layer 2 ether type of 0xFFFF */
34502 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34504 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34505 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34507 /* Any tunneled traffic */
34508 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34510 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34511 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34512 uint8_t unused_0[3];
34514 * Tunnel identifier.
34515 * Virtual Network Identifier (VNI). Only valid with
34516 * tunnel_types VXLAN, NVGRE, and Geneve.
34517 * Only lower 24-bits of VNI field are used
34518 * in setting up the filter.
34520 uint32_t tunnel_id;
34522 * This value indicates the source MAC address in
34523 * the Ethernet header.
34525 uint8_t src_macaddr[6];
34526 /* The meter instance to attach to the flow. */
34527 uint16_t meter_instance_id;
34529 * A value of 0xfff is considered invalid and implies the
34530 * instance is not configured.
34532 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
34534 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
34535 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
34537 * This value indicates the destination MAC address in
34538 * the Ethernet header.
34540 uint8_t dst_macaddr[6];
34542 * This value indicates the VLAN ID of the outer VLAN tag
34543 * in the Ethernet header.
34545 uint16_t ovlan_vid;
34547 * This value indicates the VLAN ID of the inner VLAN tag
34548 * in the Ethernet header.
34550 uint16_t ivlan_vid;
34551 /* This value indicates the ethertype in the Ethernet header. */
34552 uint16_t ethertype;
34554 * This value indicates the type of IP address.
34557 * All others are invalid.
34559 uint8_t ip_addr_type;
34561 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
34563 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
34565 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
34566 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
34567 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
34569 * The value of protocol filed in IP header.
34570 * Applies to UDP and TCP traffic.
34574 uint8_t ip_protocol;
34576 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
34578 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
34580 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
34581 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
34582 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
34583 uint8_t unused_1[2];
34585 * The value of source IP address to be used in filtering.
34586 * For IPv4, first four bytes represent the IP address.
34588 uint32_t src_ipaddr[4];
34590 * big_endian = True
34591 * The value of destination IP address to be used in filtering.
34592 * For IPv4, first four bytes represent the IP address.
34594 uint32_t dst_ipaddr[4];
34596 * The value of source port to be used in filtering.
34597 * Applies to UDP and TCP traffic.
34601 * The value of destination port to be used in filtering.
34602 * Applies to UDP and TCP traffic.
34606 * If set, this value shall represent the
34607 * Logical VNIC ID of the destination VNIC for the RX
34608 * path and network port id of the destination port for
34613 * Logical VNIC ID of the VNIC where traffic is
34616 uint16_t mirror_vnic_id;
34617 /* Logical ID of the encapsulation record. */
34618 uint32_t encap_record_id;
34619 uint8_t unused_2[4];
34622 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
34623 struct hwrm_cfa_em_flow_alloc_output {
34624 /* The specific error status for the command. */
34625 uint16_t error_code;
34626 /* The HWRM command request type. */
34628 /* The sequence ID from the original command. */
34630 /* The length of the response data in number of bytes. */
34632 /* This value is an opaque id into CFA data structures. */
34633 uint64_t em_filter_id;
34635 * The flow id value in bit 0-29 is the actual ID of the flow
34636 * associated with this filter and it shall be used to match
34637 * and associate the flow identifier returned in completion
34638 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34639 * shall indicate no valid flow id.
34642 /* Indicate the flow id value. */
34643 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34644 UINT32_C(0x3fffffff)
34645 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34646 /* Indicate type of the flow. */
34647 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
34648 UINT32_C(0x40000000)
34650 * If this bit set to 0, then it indicates that the flow is
34653 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34654 (UINT32_C(0x0) << 30)
34656 * If this bit is set to 1, then it indicates that the flow is
34659 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34660 (UINT32_C(0x1) << 30)
34661 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34662 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34663 /* Indicate the flow direction. */
34664 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
34665 UINT32_C(0x80000000)
34666 /* If this bit set to 0, then it indicates rx flow. */
34667 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34668 (UINT32_C(0x0) << 31)
34669 /* If this bit is set to 1, then it indicates that tx flow. */
34670 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34671 (UINT32_C(0x1) << 31)
34672 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34673 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34674 uint8_t unused_0[3];
34676 * This field is used in Output records to indicate that the output
34677 * is completely written to RAM. This field should be read as '1'
34678 * to indicate that the output has been completely written.
34679 * When writing a command completion or response to an internal processor,
34680 * the order of writes has to be such that this field is written last.
34685 /*************************
34686 * hwrm_cfa_em_flow_free *
34687 *************************/
34690 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
34691 struct hwrm_cfa_em_flow_free_input {
34692 /* The HWRM command request type. */
34695 * The completion ring to send the completion event on. This should
34696 * be the NQ ID returned from the `nq_alloc` HWRM command.
34698 uint16_t cmpl_ring;
34700 * The sequence ID is used by the driver for tracking multiple
34701 * commands. This ID is treated as opaque data by the firmware and
34702 * the value is returned in the `hwrm_resp_hdr` upon completion.
34706 * The target ID of the command:
34707 * * 0x0-0xFFF8 - The function ID
34708 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34709 * * 0xFFFD - Reserved for user-space HWRM interface
34712 uint16_t target_id;
34714 * A physical address pointer pointing to a host buffer that the
34715 * command's response data will be written. This can be either a host
34716 * physical address (HPA) or a guest physical address (GPA) and must
34717 * point to a physically contiguous block of memory.
34719 uint64_t resp_addr;
34720 /* This value is an opaque id into CFA data structures. */
34721 uint64_t em_filter_id;
34724 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
34725 struct hwrm_cfa_em_flow_free_output {
34726 /* The specific error status for the command. */
34727 uint16_t error_code;
34728 /* The HWRM command request type. */
34730 /* The sequence ID from the original command. */
34732 /* The length of the response data in number of bytes. */
34734 uint8_t unused_0[7];
34736 * This field is used in Output records to indicate that the output
34737 * is completely written to RAM. This field should be read as '1'
34738 * to indicate that the output has been completely written.
34739 * When writing a command completion or response to an internal processor,
34740 * the order of writes has to be such that this field is written last.
34745 /************************
34746 * hwrm_cfa_meter_qcaps *
34747 ************************/
34750 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
34751 struct hwrm_cfa_meter_qcaps_input {
34752 /* The HWRM command request type. */
34755 * The completion ring to send the completion event on. This should
34756 * be the NQ ID returned from the `nq_alloc` HWRM command.
34758 uint16_t cmpl_ring;
34760 * The sequence ID is used by the driver for tracking multiple
34761 * commands. This ID is treated as opaque data by the firmware and
34762 * the value is returned in the `hwrm_resp_hdr` upon completion.
34766 * The target ID of the command:
34767 * * 0x0-0xFFF8 - The function ID
34768 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34769 * * 0xFFFD - Reserved for user-space HWRM interface
34772 uint16_t target_id;
34774 * A physical address pointer pointing to a host buffer that the
34775 * command's response data will be written. This can be either a host
34776 * physical address (HPA) or a guest physical address (GPA) and must
34777 * point to a physically contiguous block of memory.
34779 uint64_t resp_addr;
34782 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
34783 struct hwrm_cfa_meter_qcaps_output {
34784 /* The specific error status for the command. */
34785 uint16_t error_code;
34786 /* The HWRM command request type. */
34788 /* The sequence ID from the original command. */
34790 /* The length of the response data in number of bytes. */
34794 * Enumeration denoting the clock at which the Meter is running with.
34795 * This enumeration is used for resources that are similar for both
34796 * TX and RX paths of the chip.
34798 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
34799 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
34801 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
34803 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
34804 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
34805 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
34806 uint8_t unused_0[4];
34808 * The minimum guaranteed number of tx meter profiles supported
34809 * for this function.
34811 uint16_t min_tx_profile;
34813 * The maximum non-guaranteed number of tx meter profiles supported
34814 * for this function.
34816 uint16_t max_tx_profile;
34818 * The minimum guaranteed number of rx meter profiles supported
34819 * for this function.
34821 uint16_t min_rx_profile;
34823 * The maximum non-guaranteed number of rx meter profiles supported
34824 * for this function.
34826 uint16_t max_rx_profile;
34828 * The minimum guaranteed number of tx meter instances supported
34829 * for this function.
34831 uint16_t min_tx_instance;
34833 * The maximum non-guaranteed number of tx meter instances supported
34834 * for this function.
34836 uint16_t max_tx_instance;
34838 * The minimum guaranteed number of rx meter instances supported
34839 * for this function.
34841 uint16_t min_rx_instance;
34843 * The maximum non-guaranteed number of rx meter instances supported
34844 * for this function.
34846 uint16_t max_rx_instance;
34847 uint8_t unused_1[7];
34849 * This field is used in Output records to indicate that the output
34850 * is completely written to RAM. This field should be read as '1'
34851 * to indicate that the output has been completely written.
34852 * When writing a command completion or response to an internal processor,
34853 * the order of writes has to be such that this field is written last.
34858 /********************************
34859 * hwrm_cfa_meter_profile_alloc *
34860 ********************************/
34863 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
34864 struct hwrm_cfa_meter_profile_alloc_input {
34865 /* The HWRM command request type. */
34868 * The completion ring to send the completion event on. This should
34869 * be the NQ ID returned from the `nq_alloc` HWRM command.
34871 uint16_t cmpl_ring;
34873 * The sequence ID is used by the driver for tracking multiple
34874 * commands. This ID is treated as opaque data by the firmware and
34875 * the value is returned in the `hwrm_resp_hdr` upon completion.
34879 * The target ID of the command:
34880 * * 0x0-0xFFF8 - The function ID
34881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34882 * * 0xFFFD - Reserved for user-space HWRM interface
34885 uint16_t target_id;
34887 * A physical address pointer pointing to a host buffer that the
34888 * command's response data will be written. This can be either a host
34889 * physical address (HPA) or a guest physical address (GPA) and must
34890 * point to a physically contiguous block of memory.
34892 uint64_t resp_addr;
34895 * Enumeration denoting the RX, TX type of the resource.
34896 * This enumeration is used for resources that are similar for both
34897 * TX and RX paths of the chip.
34899 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
34901 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
34904 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
34906 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
34907 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
34908 /* The meter algorithm type. */
34909 uint8_t meter_type;
34910 /* RFC 2697 (srTCM) */
34911 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
34913 /* RFC 2698 (trTCM) */
34914 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
34916 /* RFC 4115 (trTCM) */
34917 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
34919 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
34920 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
34922 * This field is reserved for the future use.
34923 * It shall be set to 0.
34925 uint16_t reserved1;
34927 * This field is reserved for the future use.
34928 * It shall be set to 0.
34930 uint32_t reserved2;
34931 /* A meter rate specified in bytes-per-second. */
34932 uint32_t commit_rate;
34933 /* The bandwidth value. */
34934 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
34935 UINT32_C(0xfffffff)
34936 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
34938 /* The granularity of the value (bits or bytes). */
34939 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
34940 UINT32_C(0x10000000)
34941 /* Value is in bits. */
34942 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
34943 (UINT32_C(0x0) << 28)
34944 /* Value is in bytes. */
34945 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
34946 (UINT32_C(0x1) << 28)
34947 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
34948 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
34949 /* bw_value_unit is 3 b */
34950 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
34951 UINT32_C(0xe0000000)
34952 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
34954 /* Value is in Mb or MB (base 10). */
34955 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
34956 (UINT32_C(0x0) << 29)
34957 /* Value is in Kb or KB (base 10). */
34958 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
34959 (UINT32_C(0x2) << 29)
34960 /* Value is in bits or bytes. */
34961 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
34962 (UINT32_C(0x4) << 29)
34963 /* Value is in Gb or GB (base 10). */
34964 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
34965 (UINT32_C(0x6) << 29)
34966 /* Value is in 1/100th of a percentage of total bandwidth. */
34967 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
34968 (UINT32_C(0x1) << 29)
34970 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
34971 (UINT32_C(0x7) << 29)
34972 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
34973 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
34974 /* A meter burst size specified in bytes. */
34975 uint32_t commit_burst;
34976 /* The bandwidth value. */
34977 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
34978 UINT32_C(0xfffffff)
34979 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
34981 /* The granularity of the value (bits or bytes). */
34982 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
34983 UINT32_C(0x10000000)
34984 /* Value is in bits. */
34985 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
34986 (UINT32_C(0x0) << 28)
34987 /* Value is in bytes. */
34988 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
34989 (UINT32_C(0x1) << 28)
34990 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
34991 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
34992 /* bw_value_unit is 3 b */
34993 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
34994 UINT32_C(0xe0000000)
34995 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
34997 /* Value is in Mb or MB (base 10). */
34998 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
34999 (UINT32_C(0x0) << 29)
35000 /* Value is in Kb or KB (base 10). */
35001 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
35002 (UINT32_C(0x2) << 29)
35003 /* Value is in bits or bytes. */
35004 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
35005 (UINT32_C(0x4) << 29)
35006 /* Value is in Gb or GB (base 10). */
35007 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
35008 (UINT32_C(0x6) << 29)
35009 /* Value is in 1/100th of a percentage of total bandwidth. */
35010 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
35011 (UINT32_C(0x1) << 29)
35012 /* Invalid value */
35013 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
35014 (UINT32_C(0x7) << 29)
35015 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
35016 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
35017 /* A meter rate specified in bytes-per-second. */
35018 uint32_t excess_peak_rate;
35019 /* The bandwidth value. */
35020 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
35021 UINT32_C(0xfffffff)
35022 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
35024 /* The granularity of the value (bits or bytes). */
35025 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
35026 UINT32_C(0x10000000)
35027 /* Value is in bits. */
35028 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
35029 (UINT32_C(0x0) << 28)
35030 /* Value is in bytes. */
35031 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
35032 (UINT32_C(0x1) << 28)
35033 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
35034 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
35035 /* bw_value_unit is 3 b */
35036 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
35037 UINT32_C(0xe0000000)
35038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
35040 /* Value is in Mb or MB (base 10). */
35041 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
35042 (UINT32_C(0x0) << 29)
35043 /* Value is in Kb or KB (base 10). */
35044 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
35045 (UINT32_C(0x2) << 29)
35046 /* Value is in bits or bytes. */
35047 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
35048 (UINT32_C(0x4) << 29)
35049 /* Value is in Gb or GB (base 10). */
35050 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
35051 (UINT32_C(0x6) << 29)
35052 /* Value is in 1/100th of a percentage of total bandwidth. */
35053 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
35054 (UINT32_C(0x1) << 29)
35056 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
35057 (UINT32_C(0x7) << 29)
35058 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
35059 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
35060 /* A meter burst size specified in bytes. */
35061 uint32_t excess_peak_burst;
35062 /* The bandwidth value. */
35063 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
35064 UINT32_C(0xfffffff)
35065 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
35067 /* The granularity of the value (bits or bytes). */
35068 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
35069 UINT32_C(0x10000000)
35070 /* Value is in bits. */
35071 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
35072 (UINT32_C(0x0) << 28)
35073 /* Value is in bytes. */
35074 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
35075 (UINT32_C(0x1) << 28)
35076 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
35077 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
35078 /* bw_value_unit is 3 b */
35079 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
35080 UINT32_C(0xe0000000)
35081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
35083 /* Value is in Mb or MB (base 10). */
35084 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
35085 (UINT32_C(0x0) << 29)
35086 /* Value is in Kb or KB (base 10). */
35087 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
35088 (UINT32_C(0x2) << 29)
35089 /* Value is in bits or bytes. */
35090 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
35091 (UINT32_C(0x4) << 29)
35092 /* Value is in Gb or GB (base 10). */
35093 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
35094 (UINT32_C(0x6) << 29)
35095 /* Value is in 1/100th of a percentage of total bandwidth. */
35096 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
35097 (UINT32_C(0x1) << 29)
35099 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
35100 (UINT32_C(0x7) << 29)
35101 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
35102 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
35105 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
35106 struct hwrm_cfa_meter_profile_alloc_output {
35107 /* The specific error status for the command. */
35108 uint16_t error_code;
35109 /* The HWRM command request type. */
35111 /* The sequence ID from the original command. */
35113 /* The length of the response data in number of bytes. */
35115 /* This value identifies a meter profile in CFA. */
35116 uint16_t meter_profile_id;
35118 * A value of 0xfff is considered invalid and implies the
35119 * profile is not configured.
35121 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
35123 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
35124 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
35125 uint8_t unused_0[5];
35127 * This field is used in Output records to indicate that the output
35128 * is completely written to RAM. This field should be read as '1'
35129 * to indicate that the output has been completely written.
35130 * When writing a command completion or response to an internal processor,
35131 * the order of writes has to be such that this field is written last.
35136 /*******************************
35137 * hwrm_cfa_meter_profile_free *
35138 *******************************/
35141 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
35142 struct hwrm_cfa_meter_profile_free_input {
35143 /* The HWRM command request type. */
35146 * The completion ring to send the completion event on. This should
35147 * be the NQ ID returned from the `nq_alloc` HWRM command.
35149 uint16_t cmpl_ring;
35151 * The sequence ID is used by the driver for tracking multiple
35152 * commands. This ID is treated as opaque data by the firmware and
35153 * the value is returned in the `hwrm_resp_hdr` upon completion.
35157 * The target ID of the command:
35158 * * 0x0-0xFFF8 - The function ID
35159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35160 * * 0xFFFD - Reserved for user-space HWRM interface
35163 uint16_t target_id;
35165 * A physical address pointer pointing to a host buffer that the
35166 * command's response data will be written. This can be either a host
35167 * physical address (HPA) or a guest physical address (GPA) and must
35168 * point to a physically contiguous block of memory.
35170 uint64_t resp_addr;
35173 * Enumeration denoting the RX, TX type of the resource.
35174 * This enumeration is used for resources that are similar for both
35175 * TX and RX paths of the chip.
35177 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
35179 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
35182 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
35184 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
35185 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
35187 /* This value identifies a meter profile in CFA. */
35188 uint16_t meter_profile_id;
35190 * A value of 0xfff is considered invalid and implies the
35191 * profile is not configured.
35193 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
35195 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
35196 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
35197 uint8_t unused_1[4];
35200 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
35201 struct hwrm_cfa_meter_profile_free_output {
35202 /* The specific error status for the command. */
35203 uint16_t error_code;
35204 /* The HWRM command request type. */
35206 /* The sequence ID from the original command. */
35208 /* The length of the response data in number of bytes. */
35210 uint8_t unused_0[7];
35212 * This field is used in Output records to indicate that the output
35213 * is completely written to RAM. This field should be read as '1'
35214 * to indicate that the output has been completely written.
35215 * When writing a command completion or response to an internal processor,
35216 * the order of writes has to be such that this field is written last.
35221 /******************************
35222 * hwrm_cfa_meter_profile_cfg *
35223 ******************************/
35226 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
35227 struct hwrm_cfa_meter_profile_cfg_input {
35228 /* The HWRM command request type. */
35231 * The completion ring to send the completion event on. This should
35232 * be the NQ ID returned from the `nq_alloc` HWRM command.
35234 uint16_t cmpl_ring;
35236 * The sequence ID is used by the driver for tracking multiple
35237 * commands. This ID is treated as opaque data by the firmware and
35238 * the value is returned in the `hwrm_resp_hdr` upon completion.
35242 * The target ID of the command:
35243 * * 0x0-0xFFF8 - The function ID
35244 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35245 * * 0xFFFD - Reserved for user-space HWRM interface
35248 uint16_t target_id;
35250 * A physical address pointer pointing to a host buffer that the
35251 * command's response data will be written. This can be either a host
35252 * physical address (HPA) or a guest physical address (GPA) and must
35253 * point to a physically contiguous block of memory.
35255 uint64_t resp_addr;
35258 * Enumeration denoting the RX, TX type of the resource.
35259 * This enumeration is used for resources that are similar for both
35260 * TX and RX paths of the chip.
35262 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
35264 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
35266 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
35267 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
35268 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
35269 /* The meter algorithm type. */
35270 uint8_t meter_type;
35271 /* RFC 2697 (srTCM) */
35272 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
35274 /* RFC 2698 (trTCM) */
35275 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
35277 /* RFC 4115 (trTCM) */
35278 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
35280 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
35281 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
35282 /* This value identifies a meter profile in CFA. */
35283 uint16_t meter_profile_id;
35285 * A value of 0xfff is considered invalid and implies the
35286 * profile is not configured.
35288 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
35290 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
35291 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
35293 * This field is reserved for the future use.
35294 * It shall be set to 0.
35297 /* A meter rate specified in bytes-per-second. */
35298 uint32_t commit_rate;
35299 /* The bandwidth value. */
35300 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
35301 UINT32_C(0xfffffff)
35302 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
35304 /* The granularity of the value (bits or bytes). */
35305 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
35306 UINT32_C(0x10000000)
35307 /* Value is in bits. */
35308 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
35309 (UINT32_C(0x0) << 28)
35310 /* Value is in bytes. */
35311 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
35312 (UINT32_C(0x1) << 28)
35313 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
35314 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
35315 /* bw_value_unit is 3 b */
35316 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
35317 UINT32_C(0xe0000000)
35318 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
35320 /* Value is in Mb or MB (base 10). */
35321 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
35322 (UINT32_C(0x0) << 29)
35323 /* Value is in Kb or KB (base 10). */
35324 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
35325 (UINT32_C(0x2) << 29)
35326 /* Value is in bits or bytes. */
35327 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
35328 (UINT32_C(0x4) << 29)
35329 /* Value is in Gb or GB (base 10). */
35330 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
35331 (UINT32_C(0x6) << 29)
35332 /* Value is in 1/100th of a percentage of total bandwidth. */
35333 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
35334 (UINT32_C(0x1) << 29)
35336 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
35337 (UINT32_C(0x7) << 29)
35338 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
35339 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
35340 /* A meter burst size specified in bytes. */
35341 uint32_t commit_burst;
35342 /* The bandwidth value. */
35343 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
35344 UINT32_C(0xfffffff)
35345 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
35347 /* The granularity of the value (bits or bytes). */
35348 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
35349 UINT32_C(0x10000000)
35350 /* Value is in bits. */
35351 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
35352 (UINT32_C(0x0) << 28)
35353 /* Value is in bytes. */
35354 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
35355 (UINT32_C(0x1) << 28)
35356 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
35357 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
35358 /* bw_value_unit is 3 b */
35359 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
35360 UINT32_C(0xe0000000)
35361 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
35363 /* Value is in Mb or MB (base 10). */
35364 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
35365 (UINT32_C(0x0) << 29)
35366 /* Value is in Kb or KB (base 10). */
35367 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
35368 (UINT32_C(0x2) << 29)
35369 /* Value is in bits or bytes. */
35370 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
35371 (UINT32_C(0x4) << 29)
35372 /* Value is in Gb or GB (base 10). */
35373 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
35374 (UINT32_C(0x6) << 29)
35375 /* Value is in 1/100th of a percentage of total bandwidth. */
35376 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
35377 (UINT32_C(0x1) << 29)
35378 /* Invalid value */
35379 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
35380 (UINT32_C(0x7) << 29)
35381 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
35382 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
35383 /* A meter rate specified in bytes-per-second. */
35384 uint32_t excess_peak_rate;
35385 /* The bandwidth value. */
35386 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
35387 UINT32_C(0xfffffff)
35388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
35390 /* The granularity of the value (bits or bytes). */
35391 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
35392 UINT32_C(0x10000000)
35393 /* Value is in bits. */
35394 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
35395 (UINT32_C(0x0) << 28)
35396 /* Value is in bytes. */
35397 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
35398 (UINT32_C(0x1) << 28)
35399 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
35400 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
35401 /* bw_value_unit is 3 b */
35402 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
35403 UINT32_C(0xe0000000)
35404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
35406 /* Value is in Mb or MB (base 10). */
35407 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
35408 (UINT32_C(0x0) << 29)
35409 /* Value is in Kb or KB (base 10). */
35410 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
35411 (UINT32_C(0x2) << 29)
35412 /* Value is in bits or bytes. */
35413 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
35414 (UINT32_C(0x4) << 29)
35415 /* Value is in Gb or GB (base 10). */
35416 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
35417 (UINT32_C(0x6) << 29)
35418 /* Value is in 1/100th of a percentage of total bandwidth. */
35419 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
35420 (UINT32_C(0x1) << 29)
35422 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
35423 (UINT32_C(0x7) << 29)
35424 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
35425 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
35426 /* A meter burst size specified in bytes. */
35427 uint32_t excess_peak_burst;
35428 /* The bandwidth value. */
35429 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
35430 UINT32_C(0xfffffff)
35431 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
35433 /* The granularity of the value (bits or bytes). */
35434 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
35435 UINT32_C(0x10000000)
35436 /* Value is in bits. */
35437 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
35438 (UINT32_C(0x0) << 28)
35439 /* Value is in bytes. */
35440 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
35441 (UINT32_C(0x1) << 28)
35442 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
35443 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
35444 /* bw_value_unit is 3 b */
35445 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
35446 UINT32_C(0xe0000000)
35447 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
35449 /* Value is in Mb or MB (base 10). */
35450 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
35451 (UINT32_C(0x0) << 29)
35452 /* Value is in Kb or KB (base 10). */
35453 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
35454 (UINT32_C(0x2) << 29)
35455 /* Value is in bits or bytes. */
35456 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
35457 (UINT32_C(0x4) << 29)
35458 /* Value is in Gb or GB (base 10). */
35459 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
35460 (UINT32_C(0x6) << 29)
35461 /* Value is in 1/100th of a percentage of total bandwidth. */
35462 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
35463 (UINT32_C(0x1) << 29)
35465 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
35466 (UINT32_C(0x7) << 29)
35467 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
35468 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
35471 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
35472 struct hwrm_cfa_meter_profile_cfg_output {
35473 /* The specific error status for the command. */
35474 uint16_t error_code;
35475 /* The HWRM command request type. */
35477 /* The sequence ID from the original command. */
35479 /* The length of the response data in number of bytes. */
35481 uint8_t unused_0[7];
35483 * This field is used in Output records to indicate that the output
35484 * is completely written to RAM. This field should be read as '1'
35485 * to indicate that the output has been completely written.
35486 * When writing a command completion or response to an internal processor,
35487 * the order of writes has to be such that this field is written last.
35492 /*********************************
35493 * hwrm_cfa_meter_instance_alloc *
35494 *********************************/
35497 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
35498 struct hwrm_cfa_meter_instance_alloc_input {
35499 /* The HWRM command request type. */
35502 * The completion ring to send the completion event on. This should
35503 * be the NQ ID returned from the `nq_alloc` HWRM command.
35505 uint16_t cmpl_ring;
35507 * The sequence ID is used by the driver for tracking multiple
35508 * commands. This ID is treated as opaque data by the firmware and
35509 * the value is returned in the `hwrm_resp_hdr` upon completion.
35513 * The target ID of the command:
35514 * * 0x0-0xFFF8 - The function ID
35515 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35516 * * 0xFFFD - Reserved for user-space HWRM interface
35519 uint16_t target_id;
35521 * A physical address pointer pointing to a host buffer that the
35522 * command's response data will be written. This can be either a host
35523 * physical address (HPA) or a guest physical address (GPA) and must
35524 * point to a physically contiguous block of memory.
35526 uint64_t resp_addr;
35529 * Enumeration denoting the RX, TX type of the resource.
35530 * This enumeration is used for resources that are similar for both
35531 * TX and RX paths of the chip.
35533 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
35536 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
35539 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
35541 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
35542 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
35544 /* This value identifies a meter profile in CFA. */
35545 uint16_t meter_profile_id;
35547 * A value of 0xffff is considered invalid and implies the
35548 * profile is not configured.
35550 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
35552 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
35553 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
35554 uint8_t unused_1[4];
35557 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
35558 struct hwrm_cfa_meter_instance_alloc_output {
35559 /* The specific error status for the command. */
35560 uint16_t error_code;
35561 /* The HWRM command request type. */
35563 /* The sequence ID from the original command. */
35565 /* The length of the response data in number of bytes. */
35567 /* This value identifies a meter instance in CFA. */
35568 uint16_t meter_instance_id;
35570 * A value of 0xffff is considered invalid and implies the
35571 * instance is not configured.
35573 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
35575 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
35576 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
35577 uint8_t unused_0[5];
35579 * This field is used in Output records to indicate that the output
35580 * is completely written to RAM. This field should be read as '1'
35581 * to indicate that the output has been completely written.
35582 * When writing a command completion or response to an internal processor,
35583 * the order of writes has to be such that this field is written last.
35588 /*******************************
35589 * hwrm_cfa_meter_instance_cfg *
35590 *******************************/
35593 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
35594 struct hwrm_cfa_meter_instance_cfg_input {
35595 /* The HWRM command request type. */
35598 * The completion ring to send the completion event on. This should
35599 * be the NQ ID returned from the `nq_alloc` HWRM command.
35601 uint16_t cmpl_ring;
35603 * The sequence ID is used by the driver for tracking multiple
35604 * commands. This ID is treated as opaque data by the firmware and
35605 * the value is returned in the `hwrm_resp_hdr` upon completion.
35609 * The target ID of the command:
35610 * * 0x0-0xFFF8 - The function ID
35611 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35612 * * 0xFFFD - Reserved for user-space HWRM interface
35615 uint16_t target_id;
35617 * A physical address pointer pointing to a host buffer that the
35618 * command's response data will be written. This can be either a host
35619 * physical address (HPA) or a guest physical address (GPA) and must
35620 * point to a physically contiguous block of memory.
35622 uint64_t resp_addr;
35625 * Enumeration denoting the RX, TX type of the resource.
35626 * This enumeration is used for resources that are similar for both
35627 * TX and RX paths of the chip.
35629 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
35631 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
35634 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
35636 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
35637 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
35640 * This value identifies a new meter profile to be associated with
35641 * the meter instance specified in this command.
35643 uint16_t meter_profile_id;
35645 * A value of 0xffff is considered invalid and implies the
35646 * profile is not configured.
35648 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
35650 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
35651 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
35653 * This value identifies the ID of a meter instance that needs to be updated with
35654 * a new meter profile specified in this command.
35656 uint16_t meter_instance_id;
35657 uint8_t unused_1[2];
35660 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
35661 struct hwrm_cfa_meter_instance_cfg_output {
35662 /* The specific error status for the command. */
35663 uint16_t error_code;
35664 /* The HWRM command request type. */
35666 /* The sequence ID from the original command. */
35668 /* The length of the response data in number of bytes. */
35670 uint8_t unused_0[7];
35672 * This field is used in Output records to indicate that the output
35673 * is completely written to RAM. This field should be read as '1'
35674 * to indicate that the output has been completely written.
35675 * When writing a command completion or response to an internal processor,
35676 * the order of writes has to be such that this field is written last.
35681 /********************************
35682 * hwrm_cfa_meter_instance_free *
35683 ********************************/
35686 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
35687 struct hwrm_cfa_meter_instance_free_input {
35688 /* The HWRM command request type. */
35691 * The completion ring to send the completion event on. This should
35692 * be the NQ ID returned from the `nq_alloc` HWRM command.
35694 uint16_t cmpl_ring;
35696 * The sequence ID is used by the driver for tracking multiple
35697 * commands. This ID is treated as opaque data by the firmware and
35698 * the value is returned in the `hwrm_resp_hdr` upon completion.
35702 * The target ID of the command:
35703 * * 0x0-0xFFF8 - The function ID
35704 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35705 * * 0xFFFD - Reserved for user-space HWRM interface
35708 uint16_t target_id;
35710 * A physical address pointer pointing to a host buffer that the
35711 * command's response data will be written. This can be either a host
35712 * physical address (HPA) or a guest physical address (GPA) and must
35713 * point to a physically contiguous block of memory.
35715 uint64_t resp_addr;
35718 * Enumeration denoting the RX, TX type of the resource.
35719 * This enumeration is used for resources that are similar for both
35720 * TX and RX paths of the chip.
35722 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
35724 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
35727 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
35729 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
35730 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
35732 /* This value identifies a meter instance in CFA. */
35733 uint16_t meter_instance_id;
35735 * A value of 0xfff is considered invalid and implies the
35736 * instance is not configured.
35738 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
35740 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
35741 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
35742 uint8_t unused_1[4];
35745 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
35746 struct hwrm_cfa_meter_instance_free_output {
35747 /* The specific error status for the command. */
35748 uint16_t error_code;
35749 /* The HWRM command request type. */
35751 /* The sequence ID from the original command. */
35753 /* The length of the response data in number of bytes. */
35755 uint8_t unused_0[7];
35757 * This field is used in Output records to indicate that the output
35758 * is completely written to RAM. This field should be read as '1'
35759 * to indicate that the output has been completely written.
35760 * When writing a command completion or response to an internal processor,
35761 * the order of writes has to be such that this field is written last.
35766 /*******************************
35767 * hwrm_cfa_decap_filter_alloc *
35768 *******************************/
35771 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
35772 struct hwrm_cfa_decap_filter_alloc_input {
35773 /* The HWRM command request type. */
35776 * The completion ring to send the completion event on. This should
35777 * be the NQ ID returned from the `nq_alloc` HWRM command.
35779 uint16_t cmpl_ring;
35781 * The sequence ID is used by the driver for tracking multiple
35782 * commands. This ID is treated as opaque data by the firmware and
35783 * the value is returned in the `hwrm_resp_hdr` upon completion.
35787 * The target ID of the command:
35788 * * 0x0-0xFFF8 - The function ID
35789 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35790 * * 0xFFFD - Reserved for user-space HWRM interface
35793 uint16_t target_id;
35795 * A physical address pointer pointing to a host buffer that the
35796 * command's response data will be written. This can be either a host
35797 * physical address (HPA) or a guest physical address (GPA) and must
35798 * point to a physically contiguous block of memory.
35800 uint64_t resp_addr;
35802 /* ovs_tunnel is 1 b */
35803 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
35807 * This bit must be '1' for the tunnel_type field to be
35810 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
35813 * This bit must be '1' for the tunnel_id field to be
35816 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
35819 * This bit must be '1' for the src_macaddr field to be
35822 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
35825 * This bit must be '1' for the dst_macaddr field to be
35828 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
35831 * This bit must be '1' for the ovlan_vid field to be
35834 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
35837 * This bit must be '1' for the ivlan_vid field to be
35840 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
35843 * This bit must be '1' for the t_ovlan_vid field to be
35846 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
35849 * This bit must be '1' for the t_ivlan_vid field to be
35852 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
35855 * This bit must be '1' for the ethertype field to be
35858 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
35861 * This bit must be '1' for the src_ipaddr field to be
35864 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
35867 * This bit must be '1' for the dst_ipaddr field to be
35870 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
35873 * This bit must be '1' for the ipaddr_type field to be
35876 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
35879 * This bit must be '1' for the ip_protocol field to be
35882 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
35885 * This bit must be '1' for the src_port field to be
35888 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
35891 * This bit must be '1' for the dst_port field to be
35894 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
35897 * This bit must be '1' for the dst_id field to be
35900 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
35903 * This bit must be '1' for the mirror_vnic_id field to be
35906 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
35909 * Tunnel identifier.
35910 * Virtual Network Identifier (VNI). Only valid with
35911 * tunnel_types VXLAN, NVGRE, and Geneve.
35912 * Only lower 24-bits of VNI field are used
35913 * in setting up the filter.
35915 uint32_t tunnel_id;
35917 uint8_t tunnel_type;
35919 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
35921 /* Virtual eXtensible Local Area Network (VXLAN) */
35922 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
35924 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35925 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
35927 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35928 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
35931 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
35933 /* Generic Network Virtualization Encapsulation (Geneve) */
35934 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
35936 /* Multi-Protocol Label Switching (MPLS) */
35937 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
35939 /* Stateless Transport Tunnel (STT) */
35940 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
35942 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35943 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
35945 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35946 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35948 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35949 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35951 /* Use fixed layer 2 ether type of 0xFFFF */
35952 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35954 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35955 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35957 /* Any tunneled traffic */
35958 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35960 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35961 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35965 * This value indicates the source MAC address in
35966 * the Ethernet header.
35968 uint8_t src_macaddr[6];
35969 uint8_t unused_2[2];
35971 * This value indicates the destination MAC address in
35972 * the Ethernet header.
35974 uint8_t dst_macaddr[6];
35976 * This value indicates the VLAN ID of the outer VLAN tag
35977 * in the Ethernet header.
35979 uint16_t ovlan_vid;
35981 * This value indicates the VLAN ID of the inner VLAN tag
35982 * in the Ethernet header.
35984 uint16_t ivlan_vid;
35986 * This value indicates the VLAN ID of the outer VLAN tag
35987 * in the tunnel Ethernet header.
35989 uint16_t t_ovlan_vid;
35991 * This value indicates the VLAN ID of the inner VLAN tag
35992 * in the tunnel Ethernet header.
35994 uint16_t t_ivlan_vid;
35995 /* This value indicates the ethertype in the Ethernet header. */
35996 uint16_t ethertype;
35998 * This value indicates the type of IP address.
36001 * All others are invalid.
36003 uint8_t ip_addr_type;
36005 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
36008 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
36011 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
36013 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
36014 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
36016 * The value of protocol filed in IP header.
36017 * Applies to UDP and TCP traffic.
36021 uint8_t ip_protocol;
36023 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
36026 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
36029 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
36031 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
36032 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
36036 * The value of source IP address to be used in filtering.
36037 * For IPv4, first four bytes represent the IP address.
36039 uint32_t src_ipaddr[4];
36041 * The value of destination IP address to be used in filtering.
36042 * For IPv4, first four bytes represent the IP address.
36044 uint32_t dst_ipaddr[4];
36046 * The value of source port to be used in filtering.
36047 * Applies to UDP and TCP traffic.
36051 * The value of destination port to be used in filtering.
36052 * Applies to UDP and TCP traffic.
36056 * If set, this value shall represent the
36057 * Logical VNIC ID of the destination VNIC for the RX
36062 * If set, this value shall represent the L2 context that matches the L2
36063 * information of the decap filter.
36065 uint16_t l2_ctxt_ref_id;
36068 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
36069 struct hwrm_cfa_decap_filter_alloc_output {
36070 /* The specific error status for the command. */
36071 uint16_t error_code;
36072 /* The HWRM command request type. */
36074 /* The sequence ID from the original command. */
36076 /* The length of the response data in number of bytes. */
36078 /* This value is an opaque id into CFA data structures. */
36079 uint32_t decap_filter_id;
36080 uint8_t unused_0[3];
36082 * This field is used in Output records to indicate that the output
36083 * is completely written to RAM. This field should be read as '1'
36084 * to indicate that the output has been completely written.
36085 * When writing a command completion or response to an internal processor,
36086 * the order of writes has to be such that this field is written last.
36091 /******************************
36092 * hwrm_cfa_decap_filter_free *
36093 ******************************/
36096 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
36097 struct hwrm_cfa_decap_filter_free_input {
36098 /* The HWRM command request type. */
36101 * The completion ring to send the completion event on. This should
36102 * be the NQ ID returned from the `nq_alloc` HWRM command.
36104 uint16_t cmpl_ring;
36106 * The sequence ID is used by the driver for tracking multiple
36107 * commands. This ID is treated as opaque data by the firmware and
36108 * the value is returned in the `hwrm_resp_hdr` upon completion.
36112 * The target ID of the command:
36113 * * 0x0-0xFFF8 - The function ID
36114 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36115 * * 0xFFFD - Reserved for user-space HWRM interface
36118 uint16_t target_id;
36120 * A physical address pointer pointing to a host buffer that the
36121 * command's response data will be written. This can be either a host
36122 * physical address (HPA) or a guest physical address (GPA) and must
36123 * point to a physically contiguous block of memory.
36125 uint64_t resp_addr;
36126 /* This value is an opaque id into CFA data structures. */
36127 uint32_t decap_filter_id;
36128 uint8_t unused_0[4];
36131 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
36132 struct hwrm_cfa_decap_filter_free_output {
36133 /* The specific error status for the command. */
36134 uint16_t error_code;
36135 /* The HWRM command request type. */
36137 /* The sequence ID from the original command. */
36139 /* The length of the response data in number of bytes. */
36141 uint8_t unused_0[7];
36143 * This field is used in Output records to indicate that the output
36144 * is completely written to RAM. This field should be read as '1'
36145 * to indicate that the output has been completely written.
36146 * When writing a command completion or response to an internal processor,
36147 * the order of writes has to be such that this field is written last.
36152 /***********************
36153 * hwrm_cfa_flow_alloc *
36154 ***********************/
36157 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
36158 struct hwrm_cfa_flow_alloc_input {
36159 /* The HWRM command request type. */
36162 * The completion ring to send the completion event on. This should
36163 * be the NQ ID returned from the `nq_alloc` HWRM command.
36165 uint16_t cmpl_ring;
36167 * The sequence ID is used by the driver for tracking multiple
36168 * commands. This ID is treated as opaque data by the firmware and
36169 * the value is returned in the `hwrm_resp_hdr` upon completion.
36173 * The target ID of the command:
36174 * * 0x0-0xFFF8 - The function ID
36175 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36176 * * 0xFFFD - Reserved for user-space HWRM interface
36179 uint16_t target_id;
36181 * A physical address pointer pointing to a host buffer that the
36182 * command's response data will be written. This can be either a host
36183 * physical address (HPA) or a guest physical address (GPA) and must
36184 * point to a physically contiguous block of memory.
36186 uint64_t resp_addr;
36188 /* tunnel is 1 b */
36189 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
36191 /* num_vlan is 2 b */
36192 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
36194 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
36196 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
36197 (UINT32_C(0x0) << 1)
36199 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
36200 (UINT32_C(0x1) << 1)
36202 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
36203 (UINT32_C(0x2) << 1)
36204 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
36205 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
36206 /* Enumeration denoting the Flow Type. */
36207 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
36209 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
36211 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
36212 (UINT32_C(0x0) << 3)
36214 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
36215 (UINT32_C(0x1) << 3)
36217 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
36218 (UINT32_C(0x2) << 3)
36219 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
36220 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
36222 * when set to 1, indicates TX flow offload for function specified in src_fid and
36223 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
36224 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
36225 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
36226 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
36227 * belong to the children VFs of the same PF to indicate VM to VM flow.
36229 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
36232 * when set to 1, indicates RX flow offload for function specified in dst_fid and
36233 * the src_fid should be set to invalid value.
36235 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
36238 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
36239 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
36240 * This flag is only valid when the flow direction is RX.
36242 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
36244 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
36245 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
36252 /* Tunnel handle valid when tunnel flag is set. */
36253 uint32_t tunnel_handle;
36254 uint16_t action_flags;
36256 * Setting of this flag indicates drop action. If this flag is not set,
36257 * then it should be considered accept action.
36259 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
36261 /* recycle is 1 b */
36262 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
36265 * Setting of this flag indicates drop action. If this flag is not set,
36266 * then it should be considered accept action.
36268 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
36271 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
36273 /* tunnel is 1 b */
36274 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
36276 /* nat_src is 1 b */
36277 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
36279 /* nat_dest is 1 b */
36280 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
36282 /* nat_ipv4_address is 1 b */
36283 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
36285 /* l2_header_rewrite is 1 b */
36286 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
36288 /* ttl_decrement is 1 b */
36289 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
36292 * If set to 1 and flow direction is TX, it indicates decap of L2 header
36293 * and encap of tunnel header. If set to 1 and flow direction is RX, it
36294 * indicates decap of tunnel header and encap L2 header. The type of tunnel
36295 * is specified in the tunnel_type field.
36297 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
36299 /* If set to 1, flow aging is enabled for this flow. */
36300 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
36303 * If set to 1 an attempt will be made to try to offload this flow to the
36304 * most optimal flow table resource. If set to 0, the flow will be
36305 * placed to the default flow table resource.
36307 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
36310 * If set to 1 there will be no attempt to allocate an on-chip try to
36311 * offload this flow. If set to 0, which will keep compatibility with the
36312 * older drivers, will cause the FW to attempt to allocate an on-chip flow
36313 * counter for the newly created flow. This will keep the existing behavior
36314 * with EM flows which always had an associated flow counter.
36316 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
36319 * Tx Flow: pf or vf fid.
36323 /* VLAN tpid, valid when push_vlan flag is set. */
36324 uint16_t l2_rewrite_vlan_tpid;
36325 /* VLAN tci, valid when push_vlan flag is set. */
36326 uint16_t l2_rewrite_vlan_tci;
36327 /* Meter id, valid when meter flag is set. */
36328 uint16_t act_meter_id;
36329 /* Flow with the same l2 context tcam key. */
36330 uint16_t ref_flow_handle;
36331 /* This value sets the match value for the ethertype. */
36332 uint16_t ethertype;
36333 /* valid when num tags is 1 or 2. */
36334 uint16_t outer_vlan_tci;
36335 /* This value sets the match value for the Destination MAC address. */
36337 /* valid when num tags is 2. */
36338 uint16_t inner_vlan_tci;
36339 /* This value sets the match value for the Source MAC address. */
36341 /* The bit length of destination IP address mask. */
36342 uint8_t ip_dst_mask_len;
36343 /* The bit length of source IP address mask. */
36344 uint8_t ip_src_mask_len;
36345 /* The value of destination IPv4/IPv6 address. */
36346 uint32_t ip_dst[4];
36347 /* The source IPv4/IPv6 address. */
36348 uint32_t ip_src[4];
36350 * The value of source port.
36351 * Applies to UDP and TCP traffic.
36353 uint16_t l4_src_port;
36355 * The value of source port mask.
36356 * Applies to UDP and TCP traffic.
36358 uint16_t l4_src_port_mask;
36360 * The value of destination port.
36361 * Applies to UDP and TCP traffic.
36363 uint16_t l4_dst_port;
36365 * The value of destination port mask.
36366 * Applies to UDP and TCP traffic.
36368 uint16_t l4_dst_port_mask;
36370 * NAT IPv4/6 address based on address type flag.
36371 * 0 values are ignored.
36373 uint32_t nat_ip_address[4];
36374 /* L2 header re-write Destination MAC address. */
36375 uint16_t l2_rewrite_dmac[3];
36377 * The NAT source/destination port based on direction flag.
36378 * Applies to UDP and TCP traffic.
36379 * 0 values are ignored.
36382 /* L2 header re-write Source MAC address. */
36383 uint16_t l2_rewrite_smac[3];
36384 /* The value of ip protocol. */
36387 uint8_t tunnel_type;
36389 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
36391 /* Virtual eXtensible Local Area Network (VXLAN) */
36392 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
36394 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36395 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
36397 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36398 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
36401 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
36403 /* Generic Network Virtualization Encapsulation (Geneve) */
36404 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
36406 /* Multi-Protocol Label Switching (MPLS) */
36407 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
36409 /* Stateless Transport Tunnel (STT) */
36410 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
36412 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36413 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
36415 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36416 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36418 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
36419 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36421 /* Use fixed layer 2 ether type of 0xFFFF */
36422 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
36424 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
36425 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36427 /* Any tunneled traffic */
36428 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36430 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
36431 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
36434 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
36435 struct hwrm_cfa_flow_alloc_output {
36436 /* The specific error status for the command. */
36437 uint16_t error_code;
36438 /* The HWRM command request type. */
36440 /* The sequence ID from the original command. */
36442 /* The length of the response data in number of bytes. */
36444 /* Flow record index. */
36445 uint16_t flow_handle;
36446 uint8_t unused_0[2];
36448 * The flow id value in bit 0-29 is the actual ID of the flow
36449 * associated with this filter and it shall be used to match
36450 * and associate the flow identifier returned in completion
36451 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
36452 * shall indicate no valid flow id.
36455 /* Indicate the flow id value. */
36456 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
36457 UINT32_C(0x3fffffff)
36458 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
36459 /* Indicate type of the flow. */
36460 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
36461 UINT32_C(0x40000000)
36463 * If this bit set to 0, then it indicates that the flow is
36466 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
36467 (UINT32_C(0x0) << 30)
36469 * If this bit is set to 1, then it indicates that the flow is
36472 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
36473 (UINT32_C(0x1) << 30)
36474 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
36475 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
36476 /* Indicate the flow direction. */
36477 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
36478 UINT32_C(0x80000000)
36479 /* If this bit set to 0, then it indicates rx flow. */
36480 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
36481 (UINT32_C(0x0) << 31)
36482 /* If this bit is set to 1, then it indicates that tx flow. */
36483 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
36484 (UINT32_C(0x1) << 31)
36485 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
36486 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
36487 /* This value identifies a set of CFA data structures used for a flow. */
36488 uint64_t ext_flow_handle;
36489 uint32_t flow_counter_id;
36490 uint8_t unused_1[3];
36492 * This field is used in Output records to indicate that the output
36493 * is completely written to RAM. This field should be read as '1'
36494 * to indicate that the output has been completely written.
36495 * When writing a command completion or response to an internal processor,
36496 * the order of writes has to be such that this field is written last.
36501 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
36502 struct hwrm_cfa_flow_alloc_cmd_err {
36504 * command specific error codes that goes to
36505 * the cmd_err field in Common HWRM Error Response.
36508 /* Unknown error */
36509 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
36510 /* No more L2 Context TCAM */
36511 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
36512 /* No more action records */
36513 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
36514 /* No more flow counters */
36515 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
36516 /* No more wild-card TCAM */
36517 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
36518 /* Hash collsion in exact match tables */
36519 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
36520 /* Key is already installed */
36521 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
36522 /* Flow Context DB is out of resource */
36523 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
36524 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
36525 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
36526 uint8_t unused_0[7];
36529 /**********************
36530 * hwrm_cfa_flow_free *
36531 **********************/
36534 /* hwrm_cfa_flow_free_input (size:256b/32B) */
36535 struct hwrm_cfa_flow_free_input {
36536 /* The HWRM command request type. */
36539 * The completion ring to send the completion event on. This should
36540 * be the NQ ID returned from the `nq_alloc` HWRM command.
36542 uint16_t cmpl_ring;
36544 * The sequence ID is used by the driver for tracking multiple
36545 * commands. This ID is treated as opaque data by the firmware and
36546 * the value is returned in the `hwrm_resp_hdr` upon completion.
36550 * The target ID of the command:
36551 * * 0x0-0xFFF8 - The function ID
36552 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36553 * * 0xFFFD - Reserved for user-space HWRM interface
36556 uint16_t target_id;
36558 * A physical address pointer pointing to a host buffer that the
36559 * command's response data will be written. This can be either a host
36560 * physical address (HPA) or a guest physical address (GPA) and must
36561 * point to a physically contiguous block of memory.
36563 uint64_t resp_addr;
36564 /* Flow record index. */
36565 uint16_t flow_handle;
36567 /* Flow counter id to be freed. */
36568 uint32_t flow_counter_id;
36569 /* This value identifies a set of CFA data structures used for a flow. */
36570 uint64_t ext_flow_handle;
36573 /* hwrm_cfa_flow_free_output (size:256b/32B) */
36574 struct hwrm_cfa_flow_free_output {
36575 /* The specific error status for the command. */
36576 uint16_t error_code;
36577 /* The HWRM command request type. */
36579 /* The sequence ID from the original command. */
36581 /* The length of the response data in number of bytes. */
36583 /* packet is 64 b */
36587 uint8_t unused_0[7];
36589 * This field is used in Output records to indicate that the output
36590 * is completely written to RAM. This field should be read as '1'
36591 * to indicate that the output has been completely written.
36592 * When writing a command completion or response to an internal processor,
36593 * the order of writes has to be such that this field is written last.
36598 /* hwrm_cfa_flow_action_data (size:960b/120B) */
36599 struct hwrm_cfa_flow_action_data {
36600 uint16_t action_flags;
36601 /* Setting of this flag indicates accept action. */
36602 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
36604 /* Setting of this flag indicates recycle action. */
36605 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
36607 /* Setting of this flag indicates drop action. */
36608 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
36610 /* Setting of this flag indicates meter action. */
36611 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
36613 /* Setting of this flag indicates tunnel action. */
36614 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
36617 * If set to 1 and flow direction is TX, it indicates decap of L2 header
36618 * and encap of tunnel header. If set to 1 and flow direction is RX, it
36619 * indicates decap of tunnel header and encap L2 header.
36621 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
36623 /* Setting of this flag indicates ttl decrement action. */
36624 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
36626 /* If set to 1, flow aging is enabled for this flow. */
36627 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
36629 /* Setting of this flag indicates encap action. */
36630 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
36632 /* Setting of this flag indicates decap action. */
36633 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
36636 uint16_t act_meter_id;
36639 /* vport number. */
36641 /* The NAT source/destination. */
36643 uint16_t unused_0[3];
36644 /* NAT IPv4/IPv6 address. */
36645 uint32_t nat_ip_address[4];
36646 /* Encapsulation Type. */
36647 uint8_t encap_type;
36648 /* Virtual eXtensible Local Area Network (VXLAN) */
36649 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
36650 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36651 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
36652 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
36653 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
36655 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
36656 /* Generic Network Virtualization Encapsulation (Geneve) */
36657 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
36658 /* Multi-Protocol Label Switching (MPLS) */
36659 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
36661 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
36662 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36663 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
36664 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36665 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
36666 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
36667 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
36668 /* Use fixed layer 2 ether type of 0xFFFF */
36669 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
36670 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
36671 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
36672 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
36673 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
36675 /* This value is encap data for the associated encap type. */
36676 uint32_t encap_data[20];
36679 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
36680 struct hwrm_cfa_flow_tunnel_hdr_data {
36682 uint8_t tunnel_type;
36684 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
36686 /* Virtual eXtensible Local Area Network (VXLAN) */
36687 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
36689 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36690 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
36692 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36693 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
36696 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
36698 /* Generic Network Virtualization Encapsulation (Geneve) */
36699 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
36701 /* Multi-Protocol Label Switching (MPLS) */
36702 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
36704 /* Stateless Transport Tunnel (STT) */
36705 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
36707 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36708 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
36710 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36711 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
36713 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
36714 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
36716 /* Use fixed layer 2 ether type of 0xFFFF */
36717 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
36719 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
36720 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
36722 /* Any tunneled traffic */
36723 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
36725 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
36726 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
36729 * Tunnel identifier.
36730 * Virtual Network Identifier (VNI).
36732 uint32_t tunnel_id;
36735 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
36736 struct hwrm_cfa_flow_l4_key_data {
36737 /* The value of source port. */
36738 uint16_t l4_src_port;
36739 /* The value of destination port. */
36740 uint16_t l4_dst_port;
36744 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
36745 struct hwrm_cfa_flow_l3_key_data {
36746 /* The value of ip protocol. */
36747 uint8_t ip_protocol;
36748 uint8_t unused_0[7];
36749 /* The value of destination IPv4/IPv6 address. */
36750 uint32_t ip_dst[4];
36751 /* The source IPv4/IPv6 address. */
36752 uint32_t ip_src[4];
36753 /* NAT IPv4/IPv6 address. */
36754 uint32_t nat_ip_address[4];
36755 uint32_t unused[2];
36758 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
36759 struct hwrm_cfa_flow_l2_key_data {
36760 /* Destination MAC address. */
36763 /* Source MAC address. */
36766 /* L2 header re-write Destination MAC address. */
36767 uint16_t l2_rewrite_dmac[3];
36769 /* L2 header re-write Source MAC address. */
36770 uint16_t l2_rewrite_smac[3];
36772 uint16_t ethertype;
36773 /* Number of VLAN tags. */
36774 uint16_t num_vlan_tags;
36776 uint16_t l2_rewrite_vlan_tpid;
36778 uint16_t l2_rewrite_vlan_tci;
36779 uint8_t unused_3[2];
36780 /* Outer VLAN TPID. */
36781 uint16_t ovlan_tpid;
36782 /* Outer VLAN TCI. */
36783 uint16_t ovlan_tci;
36784 /* Inner VLAN TPID. */
36785 uint16_t ivlan_tpid;
36786 /* Inner VLAN TCI. */
36787 uint16_t ivlan_tci;
36791 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
36792 struct hwrm_cfa_flow_key_data {
36793 /* Flow associated tunnel L2 header key info. */
36794 uint32_t t_l2_key_data[14];
36795 /* Flow associated tunnel L2 header mask info. */
36796 uint32_t t_l2_key_mask[14];
36797 /* Flow associated tunnel L3 header key info. */
36798 uint32_t t_l3_key_data[16];
36799 /* Flow associated tunnel L3 header mask info. */
36800 uint32_t t_l3_key_mask[16];
36801 /* Flow associated tunnel L4 header key info. */
36802 uint32_t t_l4_key_data[2];
36803 /* Flow associated tunnel L4 header mask info. */
36804 uint32_t t_l4_key_mask[2];
36805 /* Flow associated tunnel header info. */
36806 uint32_t tunnel_hdr[2];
36807 /* Flow associated L2 header key info. */
36808 uint32_t l2_key_data[14];
36809 /* Flow associated L2 header mask info. */
36810 uint32_t l2_key_mask[14];
36811 /* Flow associated L3 header key info. */
36812 uint32_t l3_key_data[16];
36813 /* Flow associated L3 header mask info. */
36814 uint32_t l3_key_mask[16];
36815 /* Flow associated L4 header key info. */
36816 uint32_t l4_key_data[2];
36817 /* Flow associated L4 header mask info. */
36818 uint32_t l4_key_mask[2];
36821 /**********************
36822 * hwrm_cfa_flow_info *
36823 **********************/
36826 /* hwrm_cfa_flow_info_input (size:256b/32B) */
36827 struct hwrm_cfa_flow_info_input {
36828 /* The HWRM command request type. */
36831 * The completion ring to send the completion event on. This should
36832 * be the NQ ID returned from the `nq_alloc` HWRM command.
36834 uint16_t cmpl_ring;
36836 * The sequence ID is used by the driver for tracking multiple
36837 * commands. This ID is treated as opaque data by the firmware and
36838 * the value is returned in the `hwrm_resp_hdr` upon completion.
36842 * The target ID of the command:
36843 * * 0x0-0xFFF8 - The function ID
36844 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36845 * * 0xFFFD - Reserved for user-space HWRM interface
36848 uint16_t target_id;
36850 * A physical address pointer pointing to a host buffer that the
36851 * command's response data will be written. This can be either a host
36852 * physical address (HPA) or a guest physical address (GPA) and must
36853 * point to a physically contiguous block of memory.
36855 uint64_t resp_addr;
36856 /* Flow record index. */
36857 uint16_t flow_handle;
36858 /* Max flow handle */
36859 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
36861 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
36862 /* CNP flow handle */
36863 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
36865 /* RoCEv1 flow handle */
36866 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
36868 /* RoCEv2 flow handle */
36869 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
36871 /* Direction rx = 1 */
36872 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
36874 uint8_t unused_0[6];
36875 /* This value identifies a set of CFA data structures used for a flow. */
36876 uint64_t ext_flow_handle;
36879 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
36880 struct hwrm_cfa_flow_info_output {
36881 /* The specific error status for the command. */
36882 uint16_t error_code;
36883 /* The HWRM command request type. */
36885 /* The sequence ID from the original command. */
36887 /* The length of the response data in number of bytes. */
36890 /* When set to 1, indicates the configuration is the TX flow. */
36891 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
36892 /* When set to 1, indicates the configuration is the RX flow. */
36893 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
36894 /* profile is 8 b */
36896 /* src_fid is 16 b */
36898 /* dst_fid is 16 b */
36900 /* l2_ctxt_id is 16 b */
36901 uint16_t l2_ctxt_id;
36902 /* em_info is 64 b */
36904 /* tcam_info is 64 b */
36905 uint64_t tcam_info;
36906 /* vfp_tcam_info is 64 b */
36907 uint64_t vfp_tcam_info;
36908 /* ar_id is 16 b */
36910 /* flow_handle is 16 b */
36911 uint16_t flow_handle;
36912 /* tunnel_handle is 32 b */
36913 uint32_t tunnel_handle;
36914 /* The flow aging timer for the flow, the unit is 100 milliseconds */
36915 uint16_t flow_timer;
36916 uint8_t unused_0[6];
36917 /* Flow associated L2, L3 and L4 headers info. */
36918 uint32_t flow_key_data[130];
36919 /* Flow associated action record info. */
36920 uint32_t flow_action_info[30];
36921 uint8_t unused_1[7];
36923 * This field is used in Output records to indicate that the output
36924 * is completely written to RAM. This field should be read as '1'
36925 * to indicate that the output has been completely written.
36926 * When writing a command completion or response to an internal processor,
36927 * the order of writes has to be such that this field is written last.
36932 /***********************
36933 * hwrm_cfa_flow_flush *
36934 ***********************/
36937 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
36938 struct hwrm_cfa_flow_flush_input {
36939 /* The HWRM command request type. */
36942 * The completion ring to send the completion event on. This should
36943 * be the NQ ID returned from the `nq_alloc` HWRM command.
36945 uint16_t cmpl_ring;
36947 * The sequence ID is used by the driver for tracking multiple
36948 * commands. This ID is treated as opaque data by the firmware and
36949 * the value is returned in the `hwrm_resp_hdr` upon completion.
36953 * The target ID of the command:
36954 * * 0x0-0xFFF8 - The function ID
36955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36956 * * 0xFFFD - Reserved for user-space HWRM interface
36959 uint16_t target_id;
36961 * A physical address pointer pointing to a host buffer that the
36962 * command's response data will be written. This can be either a host
36963 * physical address (HPA) or a guest physical address (GPA) and must
36964 * point to a physically contiguous block of memory.
36966 uint64_t resp_addr;
36967 /* flags is 32 b */
36970 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
36971 * fields are valid. The flow flush operation should only flush the flows from the
36972 * flow table specified. This flag is set to 0 by older driver. For older firmware,
36973 * setting this flag has no effect.
36975 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
36978 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
36979 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
36980 * setting this flag has no effect.
36982 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
36985 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
36986 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
36988 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
36990 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
36991 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
36992 UINT32_C(0x8000000)
36994 * This specifies the size of flow handle entries provided by the driver
36995 * in the flow table specified below. Only two flow handle size enums are defined.
36997 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
36998 UINT32_C(0xc0000000)
36999 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
37001 /* The flow handle is 16bit */
37002 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
37003 (UINT32_C(0x0) << 30)
37004 /* The flow handle is 64bit */
37005 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
37006 (UINT32_C(0x1) << 30)
37007 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
37008 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
37009 /* Specify page size of the flow table memory. */
37011 /* The page size is 4K */
37012 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
37013 /* The page size is 8K */
37014 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
37015 /* The page size is 64K */
37016 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
37017 /* The page size is 256K */
37018 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
37019 /* The page size is 1M */
37020 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
37021 /* The page size is 2M */
37022 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
37023 /* The page size is 4M */
37024 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
37025 /* The page size is 1G */
37026 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
37027 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
37028 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
37029 /* FLow table memory indirect levels. */
37030 uint8_t page_level;
37031 /* PBL pointer is physical start address. */
37032 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
37033 /* PBL pointer points to PTE table. */
37034 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
37035 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
37036 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
37037 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
37038 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
37039 /* number of flows in the flow table */
37040 uint16_t num_flows;
37041 /* Pointer to the PBL, or PDL depending on number of levels */
37045 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
37046 struct hwrm_cfa_flow_flush_output {
37047 /* The specific error status for the command. */
37048 uint16_t error_code;
37049 /* The HWRM command request type. */
37051 /* The sequence ID from the original command. */
37053 /* The length of the response data in number of bytes. */
37055 uint8_t unused_0[7];
37057 * This field is used in Output records to indicate that the output
37058 * is completely written to RAM. This field should be read as '1'
37059 * to indicate that the output has been completely written.
37060 * When writing a command completion or response to an internal processor,
37061 * the order of writes has to be such that this field is written last.
37066 /***********************
37067 * hwrm_cfa_flow_stats *
37068 ***********************/
37071 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
37072 struct hwrm_cfa_flow_stats_input {
37073 /* The HWRM command request type. */
37076 * The completion ring to send the completion event on. This should
37077 * be the NQ ID returned from the `nq_alloc` HWRM command.
37079 uint16_t cmpl_ring;
37081 * The sequence ID is used by the driver for tracking multiple
37082 * commands. This ID is treated as opaque data by the firmware and
37083 * the value is returned in the `hwrm_resp_hdr` upon completion.
37087 * The target ID of the command:
37088 * * 0x0-0xFFF8 - The function ID
37089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37090 * * 0xFFFD - Reserved for user-space HWRM interface
37093 uint16_t target_id;
37095 * A physical address pointer pointing to a host buffer that the
37096 * command's response data will be written. This can be either a host
37097 * physical address (HPA) or a guest physical address (GPA) and must
37098 * point to a physically contiguous block of memory.
37100 uint64_t resp_addr;
37102 uint16_t num_flows;
37104 uint16_t flow_handle_0;
37106 uint16_t flow_handle_1;
37108 uint16_t flow_handle_2;
37110 uint16_t flow_handle_3;
37112 uint16_t flow_handle_4;
37114 uint16_t flow_handle_5;
37116 uint16_t flow_handle_6;
37118 uint16_t flow_handle_7;
37120 uint16_t flow_handle_8;
37122 uint16_t flow_handle_9;
37123 uint8_t unused_0[2];
37124 /* Flow ID of a flow. */
37125 uint32_t flow_id_0;
37126 /* Flow ID of a flow. */
37127 uint32_t flow_id_1;
37128 /* Flow ID of a flow. */
37129 uint32_t flow_id_2;
37130 /* Flow ID of a flow. */
37131 uint32_t flow_id_3;
37132 /* Flow ID of a flow. */
37133 uint32_t flow_id_4;
37134 /* Flow ID of a flow. */
37135 uint32_t flow_id_5;
37136 /* Flow ID of a flow. */
37137 uint32_t flow_id_6;
37138 /* Flow ID of a flow. */
37139 uint32_t flow_id_7;
37140 /* Flow ID of a flow. */
37141 uint32_t flow_id_8;
37142 /* Flow ID of a flow. */
37143 uint32_t flow_id_9;
37146 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
37147 struct hwrm_cfa_flow_stats_output {
37148 /* The specific error status for the command. */
37149 uint16_t error_code;
37150 /* The HWRM command request type. */
37152 /* The sequence ID from the original command. */
37154 /* The length of the response data in number of bytes. */
37156 /* packet_0 is 64 b */
37158 /* packet_1 is 64 b */
37160 /* packet_2 is 64 b */
37162 /* packet_3 is 64 b */
37164 /* packet_4 is 64 b */
37166 /* packet_5 is 64 b */
37168 /* packet_6 is 64 b */
37170 /* packet_7 is 64 b */
37172 /* packet_8 is 64 b */
37174 /* packet_9 is 64 b */
37176 /* byte_0 is 64 b */
37178 /* byte_1 is 64 b */
37180 /* byte_2 is 64 b */
37182 /* byte_3 is 64 b */
37184 /* byte_4 is 64 b */
37186 /* byte_5 is 64 b */
37188 /* byte_6 is 64 b */
37190 /* byte_7 is 64 b */
37192 /* byte_8 is 64 b */
37194 /* byte_9 is 64 b */
37196 uint8_t unused_0[7];
37198 * This field is used in Output records to indicate that the output
37199 * is completely written to RAM. This field should be read as '1'
37200 * to indicate that the output has been completely written.
37201 * When writing a command completion or response to an internal processor,
37202 * the order of writes has to be such that this field is written last.
37207 /***********************************
37208 * hwrm_cfa_flow_aging_timer_reset *
37209 ***********************************/
37212 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
37213 struct hwrm_cfa_flow_aging_timer_reset_input {
37214 /* The HWRM command request type. */
37217 * The completion ring to send the completion event on. This should
37218 * be the NQ ID returned from the `nq_alloc` HWRM command.
37220 uint16_t cmpl_ring;
37222 * The sequence ID is used by the driver for tracking multiple
37223 * commands. This ID is treated as opaque data by the firmware and
37224 * the value is returned in the `hwrm_resp_hdr` upon completion.
37228 * The target ID of the command:
37229 * * 0x0-0xFFF8 - The function ID
37230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37231 * * 0xFFFD - Reserved for user-space HWRM interface
37234 uint16_t target_id;
37236 * A physical address pointer pointing to a host buffer that the
37237 * command's response data will be written. This can be either a host
37238 * physical address (HPA) or a guest physical address (GPA) and must
37239 * point to a physically contiguous block of memory.
37241 uint64_t resp_addr;
37242 /* Flow record index. */
37243 uint16_t flow_handle;
37244 uint8_t unused_0[2];
37246 * New flow timer value for the flow specified in the ext_flow_handle.
37247 * The flow timer unit is 100ms.
37249 uint32_t flow_timer;
37250 /* This value identifies a set of CFA data structures used for a flow. */
37251 uint64_t ext_flow_handle;
37254 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
37255 struct hwrm_cfa_flow_aging_timer_reset_output {
37256 /* The specific error status for the command. */
37257 uint16_t error_code;
37258 /* The HWRM command request type. */
37260 /* The sequence ID from the original command. */
37262 /* The length of the response data in number of bytes. */
37264 uint8_t unused_0[7];
37266 * This field is used in Output records to indicate that the output
37267 * is completely written to RAM. This field should be read as '1'
37268 * to indicate that the output has been completely written.
37269 * When writing a command completion or response to an internal processor,
37270 * the order of writes has to be such that this field is written last.
37275 /***************************
37276 * hwrm_cfa_flow_aging_cfg *
37277 ***************************/
37280 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
37281 struct hwrm_cfa_flow_aging_cfg_input {
37282 /* The HWRM command request type. */
37285 * The completion ring to send the completion event on. This should
37286 * be the NQ ID returned from the `nq_alloc` HWRM command.
37288 uint16_t cmpl_ring;
37290 * The sequence ID is used by the driver for tracking multiple
37291 * commands. This ID is treated as opaque data by the firmware and
37292 * the value is returned in the `hwrm_resp_hdr` upon completion.
37296 * The target ID of the command:
37297 * * 0x0-0xFFF8 - The function ID
37298 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37299 * * 0xFFFD - Reserved for user-space HWRM interface
37302 uint16_t target_id;
37304 * A physical address pointer pointing to a host buffer that the
37305 * command's response data will be written. This can be either a host
37306 * physical address (HPA) or a guest physical address (GPA) and must
37307 * point to a physically contiguous block of memory.
37309 uint64_t resp_addr;
37310 /* The bit field to enable per flow aging configuration. */
37312 /* This bit must be '1' for the tcp flow timer field to be configured */
37313 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
37315 /* This bit must be '1' for the tcp finish timer field to be configured */
37316 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
37318 /* This bit must be '1' for the udp flow timer field to be configured */
37319 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
37321 /* This bit must be '1' for the eem dma interval field to be configured */
37322 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
37324 /* This bit must be '1' for the eem notice interval field to be configured */
37325 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
37327 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
37328 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
37330 /* This bit must be '1' for the eem context memory ID field to be configured */
37331 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
37333 /* This bit must be '1' for the eem context memory type field to be configured */
37334 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
37337 /* Enumeration denoting the RX, TX type of the resource. */
37338 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37340 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37342 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37343 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
37344 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
37345 /* Enumeration denoting the enable, disable eem flow aging configuration. */
37346 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
37348 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
37349 (UINT32_C(0x0) << 1)
37351 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
37352 (UINT32_C(0x1) << 1)
37353 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
37354 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
37356 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
37357 uint32_t tcp_flow_timer;
37358 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
37359 uint32_t tcp_fin_timer;
37360 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
37361 uint32_t udp_flow_timer;
37362 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
37363 uint16_t eem_dma_interval;
37364 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
37365 uint16_t eem_notice_interval;
37366 /* The maximum entries number in the eem context memory. */
37367 uint32_t eem_ctx_max_entries;
37368 /* The context memory ID for eem flow aging. */
37369 uint16_t eem_ctx_id;
37370 uint16_t eem_ctx_mem_type;
37371 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
37372 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
37374 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
37375 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
37376 uint8_t unused_1[4];
37379 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
37380 struct hwrm_cfa_flow_aging_cfg_output {
37381 /* The specific error status for the command. */
37382 uint16_t error_code;
37383 /* The HWRM command request type. */
37385 /* The sequence ID from the original command. */
37387 /* The length of the response data in number of bytes. */
37389 uint8_t unused_0[7];
37391 * This field is used in Output records to indicate that the output
37392 * is completely written to RAM. This field should be read as '1'
37393 * to indicate that the output has been completely written.
37394 * When writing a command completion or response to an internal processor,
37395 * the order of writes has to be such that this field is written last.
37400 /****************************
37401 * hwrm_cfa_flow_aging_qcfg *
37402 ****************************/
37405 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
37406 struct hwrm_cfa_flow_aging_qcfg_input {
37407 /* The HWRM command request type. */
37410 * The completion ring to send the completion event on. This should
37411 * be the NQ ID returned from the `nq_alloc` HWRM command.
37413 uint16_t cmpl_ring;
37415 * The sequence ID is used by the driver for tracking multiple
37416 * commands. This ID is treated as opaque data by the firmware and
37417 * the value is returned in the `hwrm_resp_hdr` upon completion.
37421 * The target ID of the command:
37422 * * 0x0-0xFFF8 - The function ID
37423 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37424 * * 0xFFFD - Reserved for user-space HWRM interface
37427 uint16_t target_id;
37429 * A physical address pointer pointing to a host buffer that the
37430 * command's response data will be written. This can be either a host
37431 * physical address (HPA) or a guest physical address (GPA) and must
37432 * point to a physically contiguous block of memory.
37434 uint64_t resp_addr;
37435 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
37437 /* Enumeration denoting the RX, TX type of the resource. */
37438 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37440 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37442 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37443 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
37444 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
37445 uint8_t unused_0[7];
37448 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
37449 struct hwrm_cfa_flow_aging_qcfg_output {
37450 /* The specific error status for the command. */
37451 uint16_t error_code;
37452 /* The HWRM command request type. */
37454 /* The sequence ID from the original command. */
37456 /* The length of the response data in number of bytes. */
37458 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
37459 uint32_t tcp_flow_timer;
37460 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
37461 uint32_t tcp_fin_timer;
37462 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
37463 uint32_t udp_flow_timer;
37464 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
37465 uint16_t eem_dma_interval;
37466 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
37467 uint16_t eem_notice_interval;
37468 /* The maximum entries number in the eem context memory. */
37469 uint32_t eem_ctx_max_entries;
37470 /* The context memory ID for eem flow aging. */
37471 uint16_t eem_ctx_id;
37472 /* The context memory type for eem flow aging. */
37473 uint16_t eem_ctx_mem_type;
37474 uint8_t unused_0[7];
37476 * This field is used in Output records to indicate that the output
37477 * is completely written to RAM. This field should be read as '1'
37478 * to indicate that the output has been completely written.
37479 * When writing a command completion or response to an internal processor,
37480 * the order of writes has to be such that this field is written last.
37485 /*****************************
37486 * hwrm_cfa_flow_aging_qcaps *
37487 *****************************/
37490 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
37491 struct hwrm_cfa_flow_aging_qcaps_input {
37492 /* The HWRM command request type. */
37495 * The completion ring to send the completion event on. This should
37496 * be the NQ ID returned from the `nq_alloc` HWRM command.
37498 uint16_t cmpl_ring;
37500 * The sequence ID is used by the driver for tracking multiple
37501 * commands. This ID is treated as opaque data by the firmware and
37502 * the value is returned in the `hwrm_resp_hdr` upon completion.
37506 * The target ID of the command:
37507 * * 0x0-0xFFF8 - The function ID
37508 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37509 * * 0xFFFD - Reserved for user-space HWRM interface
37512 uint16_t target_id;
37514 * A physical address pointer pointing to a host buffer that the
37515 * command's response data will be written. This can be either a host
37516 * physical address (HPA) or a guest physical address (GPA) and must
37517 * point to a physically contiguous block of memory.
37519 uint64_t resp_addr;
37520 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
37522 /* Enumeration denoting the RX, TX type of the resource. */
37523 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
37525 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37527 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37528 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
37529 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
37530 uint8_t unused_0[7];
37533 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
37534 struct hwrm_cfa_flow_aging_qcaps_output {
37535 /* The specific error status for the command. */
37536 uint16_t error_code;
37537 /* The HWRM command request type. */
37539 /* The sequence ID from the original command. */
37541 /* The length of the response data in number of bytes. */
37543 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
37544 uint32_t max_tcp_flow_timer;
37545 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
37546 uint32_t max_tcp_fin_timer;
37547 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
37548 uint32_t max_udp_flow_timer;
37549 /* The maximum aging flows that HW can support. */
37550 uint32_t max_aging_flows;
37551 uint8_t unused_0[7];
37553 * This field is used in Output records to indicate that the output
37554 * is completely written to RAM. This field should be read as '1'
37555 * to indicate that the output has been completely written.
37556 * When writing a command completion or response to an internal processor,
37557 * the order of writes has to be such that this field is written last.
37562 /**********************************
37563 * hwrm_cfa_tcp_flag_process_qcfg *
37564 **********************************/
37567 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
37568 struct hwrm_cfa_tcp_flag_process_qcfg_input {
37569 /* The HWRM command request type. */
37572 * The completion ring to send the completion event on. This should
37573 * be the NQ ID returned from the `nq_alloc` HWRM command.
37575 uint16_t cmpl_ring;
37577 * The sequence ID is used by the driver for tracking multiple
37578 * commands. This ID is treated as opaque data by the firmware and
37579 * the value is returned in the `hwrm_resp_hdr` upon completion.
37583 * The target ID of the command:
37584 * * 0x0-0xFFF8 - The function ID
37585 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37586 * * 0xFFFD - Reserved for user-space HWRM interface
37589 uint16_t target_id;
37591 * A physical address pointer pointing to a host buffer that the
37592 * command's response data will be written. This can be either a host
37593 * physical address (HPA) or a guest physical address (GPA) and must
37594 * point to a physically contiguous block of memory.
37596 uint64_t resp_addr;
37599 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
37600 struct hwrm_cfa_tcp_flag_process_qcfg_output {
37601 /* The specific error status for the command. */
37602 uint16_t error_code;
37603 /* The HWRM command request type. */
37605 /* The sequence ID from the original command. */
37607 /* The length of the response data in number of bytes. */
37609 /* The port 0 RX mirror action record ID. */
37610 uint16_t rx_ar_id_port0;
37611 /* The port 1 RX mirror action record ID. */
37612 uint16_t rx_ar_id_port1;
37613 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
37614 uint16_t tx_ar_id_port0;
37615 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
37616 uint16_t tx_ar_id_port1;
37617 uint8_t unused_0[7];
37619 * This field is used in Output records to indicate that the output
37620 * is completely written to RAM. This field should be read as '1'
37621 * to indicate that the output has been completely written.
37622 * When writing a command completion or response to an internal processor,
37623 * the order of writes has to be such that this field is written last.
37628 /**************************
37629 * hwrm_cfa_vf_pair_alloc *
37630 **************************/
37633 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
37634 struct hwrm_cfa_vf_pair_alloc_input {
37635 /* The HWRM command request type. */
37638 * The completion ring to send the completion event on. This should
37639 * be the NQ ID returned from the `nq_alloc` HWRM command.
37641 uint16_t cmpl_ring;
37643 * The sequence ID is used by the driver for tracking multiple
37644 * commands. This ID is treated as opaque data by the firmware and
37645 * the value is returned in the `hwrm_resp_hdr` upon completion.
37649 * The target ID of the command:
37650 * * 0x0-0xFFF8 - The function ID
37651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37652 * * 0xFFFD - Reserved for user-space HWRM interface
37655 uint16_t target_id;
37657 * A physical address pointer pointing to a host buffer that the
37658 * command's response data will be written. This can be either a host
37659 * physical address (HPA) or a guest physical address (GPA) and must
37660 * point to a physically contiguous block of memory.
37662 uint64_t resp_addr;
37663 /* Logical VF number (range: 0 -> MAX_VFS -1). */
37665 /* Logical VF number (range: 0 -> MAX_VFS -1). */
37667 uint8_t unused_0[4];
37668 /* VF Pair name (32 byte string). */
37669 char pair_name[32];
37672 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
37673 struct hwrm_cfa_vf_pair_alloc_output {
37674 /* The specific error status for the command. */
37675 uint16_t error_code;
37676 /* The HWRM command request type. */
37678 /* The sequence ID from the original command. */
37680 /* The length of the response data in number of bytes. */
37682 uint8_t unused_0[7];
37684 * This field is used in Output records to indicate that the output
37685 * is completely written to RAM. This field should be read as '1'
37686 * to indicate that the output has been completely written.
37687 * When writing a command completion or response to an internal processor,
37688 * the order of writes has to be such that this field is written last.
37693 /*************************
37694 * hwrm_cfa_vf_pair_free *
37695 *************************/
37698 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
37699 struct hwrm_cfa_vf_pair_free_input {
37700 /* The HWRM command request type. */
37703 * The completion ring to send the completion event on. This should
37704 * be the NQ ID returned from the `nq_alloc` HWRM command.
37706 uint16_t cmpl_ring;
37708 * The sequence ID is used by the driver for tracking multiple
37709 * commands. This ID is treated as opaque data by the firmware and
37710 * the value is returned in the `hwrm_resp_hdr` upon completion.
37714 * The target ID of the command:
37715 * * 0x0-0xFFF8 - The function ID
37716 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37717 * * 0xFFFD - Reserved for user-space HWRM interface
37720 uint16_t target_id;
37722 * A physical address pointer pointing to a host buffer that the
37723 * command's response data will be written. This can be either a host
37724 * physical address (HPA) or a guest physical address (GPA) and must
37725 * point to a physically contiguous block of memory.
37727 uint64_t resp_addr;
37728 /* VF Pair name (32 byte string). */
37729 char pair_name[32];
37732 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
37733 struct hwrm_cfa_vf_pair_free_output {
37734 /* The specific error status for the command. */
37735 uint16_t error_code;
37736 /* The HWRM command request type. */
37738 /* The sequence ID from the original command. */
37740 /* The length of the response data in number of bytes. */
37742 uint8_t unused_0[7];
37744 * This field is used in Output records to indicate that the output
37745 * is completely written to RAM. This field should be read as '1'
37746 * to indicate that the output has been completely written.
37747 * When writing a command completion or response to an internal processor,
37748 * the order of writes has to be such that this field is written last.
37753 /*************************
37754 * hwrm_cfa_vf_pair_info *
37755 *************************/
37758 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
37759 struct hwrm_cfa_vf_pair_info_input {
37760 /* The HWRM command request type. */
37763 * The completion ring to send the completion event on. This should
37764 * be the NQ ID returned from the `nq_alloc` HWRM command.
37766 uint16_t cmpl_ring;
37768 * The sequence ID is used by the driver for tracking multiple
37769 * commands. This ID is treated as opaque data by the firmware and
37770 * the value is returned in the `hwrm_resp_hdr` upon completion.
37774 * The target ID of the command:
37775 * * 0x0-0xFFF8 - The function ID
37776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37777 * * 0xFFFD - Reserved for user-space HWRM interface
37780 uint16_t target_id;
37782 * A physical address pointer pointing to a host buffer that the
37783 * command's response data will be written. This can be either a host
37784 * physical address (HPA) or a guest physical address (GPA) and must
37785 * point to a physically contiguous block of memory.
37787 uint64_t resp_addr;
37789 /* If this flag is set, lookup by name else lookup by index. */
37790 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
37791 /* vf pair table index. */
37792 uint16_t vf_pair_index;
37793 uint8_t unused_0[2];
37794 /* VF Pair name (32 byte string). */
37795 char vf_pair_name[32];
37798 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
37799 struct hwrm_cfa_vf_pair_info_output {
37800 /* The specific error status for the command. */
37801 uint16_t error_code;
37802 /* The HWRM command request type. */
37804 /* The sequence ID from the original command. */
37806 /* The length of the response data in number of bytes. */
37808 /* vf pair table index. */
37809 uint16_t next_vf_pair_index;
37810 /* vf pair member a's vf_fid. */
37812 /* vf pair member a's Linux logical VF number. */
37813 uint16_t vf_a_index;
37814 /* vf pair member b's vf_fid. */
37816 /* vf pair member a's Linux logical VF number. */
37817 uint16_t vf_b_index;
37818 /* vf pair state. */
37819 uint8_t pair_state;
37820 /* Pair has been allocated */
37821 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
37822 /* Both pair members are active */
37823 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
37824 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
37825 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
37826 uint8_t unused_0[5];
37827 /* VF Pair name (32 byte string). */
37828 char pair_name[32];
37829 uint8_t unused_1[7];
37831 * This field is used in Output records to indicate that the output
37832 * is completely written to RAM. This field should be read as '1'
37833 * to indicate that the output has been completely written.
37834 * When writing a command completion or response to an internal processor,
37835 * the order of writes has to be such that this field is written last.
37840 /***********************
37841 * hwrm_cfa_pair_alloc *
37842 ***********************/
37845 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
37846 struct hwrm_cfa_pair_alloc_input {
37847 /* The HWRM command request type. */
37850 * The completion ring to send the completion event on. This should
37851 * be the NQ ID returned from the `nq_alloc` HWRM command.
37853 uint16_t cmpl_ring;
37855 * The sequence ID is used by the driver for tracking multiple
37856 * commands. This ID is treated as opaque data by the firmware and
37857 * the value is returned in the `hwrm_resp_hdr` upon completion.
37861 * The target ID of the command:
37862 * * 0x0-0xFFF8 - The function ID
37863 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37864 * * 0xFFFD - Reserved for user-space HWRM interface
37867 uint16_t target_id;
37869 * A physical address pointer pointing to a host buffer that the
37870 * command's response data will be written. This can be either a host
37871 * physical address (HPA) or a guest physical address (GPA) and must
37872 * point to a physically contiguous block of memory.
37874 uint64_t resp_addr;
37876 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
37877 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
37879 uint16_t pair_mode;
37880 /* Pair between VF on local host with PF or VF on specified host. */
37881 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
37883 /* Pair between REP on local host with PF or VF on specified host. */
37884 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
37886 /* Pair between REP on local host with REP on specified host. */
37887 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
37889 /* Pair for the proxy interface. */
37890 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
37892 /* Pair for the PF interface. */
37893 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
37895 /* Modify existing rep2fn pair and move pair to new PF. */
37896 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
37898 /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
37899 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
37901 /* Truflow pair between REP on local host with PF or VF on specified host. */
37902 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
37904 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
37905 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
37906 /* Logical VF number (range: 0 -> MAX_VFS -1). */
37908 /* Logical Host (0xff-local host). */
37910 /* Logical PF (0xff-PF for command channel). */
37912 /* Logical VF number (range: 0 -> MAX_VFS -1). */
37914 /* Loopback port (0xff-internal loopback), valid for mode-3. */
37916 /* Priority used for encap of loopback packets valid for mode-3. */
37918 /* New PF for rep2fn modify, valid for mode 5. */
37919 uint16_t new_pf_fid;
37922 * This bit must be '1' for the q_ab field to be
37925 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
37927 * This bit must be '1' for the q_ba field to be
37930 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
37932 * This bit must be '1' for the fc_ab field to be
37935 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
37937 * This bit must be '1' for the fc_ba field to be
37940 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
37941 /* VF Pair name (32 byte string). */
37942 char pair_name[32];
37944 * The q_ab value specifies the logical index of the TX/RX CoS
37945 * queue to be assigned for traffic in the A to B direction of
37946 * the interface pair. The default value is 0.
37950 * The q_ba value specifies the logical index of the TX/RX CoS
37951 * queue to be assigned for traffic in the B to A direction of
37952 * the interface pair. The default value is 1.
37956 * Specifies whether RX ring flow control is disabled (0) or enabled
37957 * (1) in the A to B direction. The default value is 0, meaning that
37958 * packets will be dropped when the B-side RX rings are full.
37962 * Specifies whether RX ring flow control is disabled (0) or enabled
37963 * (1) in the B to A direction. The default value is 1, meaning that
37964 * the RX CoS queue will be flow controlled when the A-side RX rings
37968 uint8_t unused_1[4];
37971 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
37972 struct hwrm_cfa_pair_alloc_output {
37973 /* The specific error status for the command. */
37974 uint16_t error_code;
37975 /* The HWRM command request type. */
37977 /* The sequence ID from the original command. */
37979 /* The length of the response data in number of bytes. */
37981 /* Only valid for modes 1 and 2. */
37982 uint16_t rx_cfa_code_a;
37983 /* Only valid for modes 1 and 2. */
37984 uint16_t tx_cfa_action_a;
37985 /* Only valid for mode 2. */
37986 uint16_t rx_cfa_code_b;
37987 /* Only valid for mode 2. */
37988 uint16_t tx_cfa_action_b;
37989 uint8_t unused_0[7];
37991 * This field is used in Output records to indicate that the output
37992 * is completely written to RAM. This field should be read as '1'
37993 * to indicate that the output has been completely written.
37994 * When writing a command completion or response to an internal processor,
37995 * the order of writes has to be such that this field is written last.
38000 /**********************
38001 * hwrm_cfa_pair_free *
38002 **********************/
38005 /* hwrm_cfa_pair_free_input (size:448b/56B) */
38006 struct hwrm_cfa_pair_free_input {
38007 /* The HWRM command request type. */
38010 * The completion ring to send the completion event on. This should
38011 * be the NQ ID returned from the `nq_alloc` HWRM command.
38013 uint16_t cmpl_ring;
38015 * The sequence ID is used by the driver for tracking multiple
38016 * commands. This ID is treated as opaque data by the firmware and
38017 * the value is returned in the `hwrm_resp_hdr` upon completion.
38021 * The target ID of the command:
38022 * * 0x0-0xFFF8 - The function ID
38023 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38024 * * 0xFFFD - Reserved for user-space HWRM interface
38027 uint16_t target_id;
38029 * A physical address pointer pointing to a host buffer that the
38030 * command's response data will be written. This can be either a host
38031 * physical address (HPA) or a guest physical address (GPA) and must
38032 * point to a physically contiguous block of memory.
38034 uint64_t resp_addr;
38035 /* VF Pair name (32 byte string). */
38036 char pair_name[32];
38037 /* Logical PF (0xff-PF for command channel). */
38039 uint8_t unused_0[3];
38040 /* Logical VF number (range: 0 -> MAX_VFS -1). */
38043 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
38044 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
38046 uint16_t pair_mode;
38047 /* Pair between VF on local host with PF or VF on specified host. */
38048 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
38049 /* Pair between REP on local host with PF or VF on specified host. */
38050 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
38051 /* Pair between REP on local host with REP on specified host. */
38052 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
38053 /* Pair for the proxy interface. */
38054 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
38055 /* Pair for the PF interface. */
38056 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
38057 /* Modify existing rep2fn pair and move pair to new PF. */
38058 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
38059 /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
38060 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
38061 /* Truflow pair between REP on local host with PF or VF on specified host. */
38062 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
38063 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
38064 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
38067 /* hwrm_cfa_pair_free_output (size:128b/16B) */
38068 struct hwrm_cfa_pair_free_output {
38069 /* The specific error status for the command. */
38070 uint16_t error_code;
38071 /* The HWRM command request type. */
38073 /* The sequence ID from the original command. */
38075 /* The length of the response data in number of bytes. */
38077 uint8_t unused_0[7];
38079 * This field is used in Output records to indicate that the output
38080 * is completely written to RAM. This field should be read as '1'
38081 * to indicate that the output has been completely written.
38082 * When writing a command completion or response to an internal processor,
38083 * the order of writes has to be such that this field is written last.
38088 /**********************
38089 * hwrm_cfa_pair_info *
38090 **********************/
38093 /* hwrm_cfa_pair_info_input (size:448b/56B) */
38094 struct hwrm_cfa_pair_info_input {
38095 /* The HWRM command request type. */
38098 * The completion ring to send the completion event on. This should
38099 * be the NQ ID returned from the `nq_alloc` HWRM command.
38101 uint16_t cmpl_ring;
38103 * The sequence ID is used by the driver for tracking multiple
38104 * commands. This ID is treated as opaque data by the firmware and
38105 * the value is returned in the `hwrm_resp_hdr` upon completion.
38109 * The target ID of the command:
38110 * * 0x0-0xFFF8 - The function ID
38111 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38112 * * 0xFFFD - Reserved for user-space HWRM interface
38115 uint16_t target_id;
38117 * A physical address pointer pointing to a host buffer that the
38118 * command's response data will be written. This can be either a host
38119 * physical address (HPA) or a guest physical address (GPA) and must
38120 * point to a physically contiguous block of memory.
38122 uint64_t resp_addr;
38124 /* If this flag is set, lookup by name else lookup by index. */
38125 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
38126 /* If this flag is set, lookup by PF id and VF id. */
38127 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
38128 /* Pair table index. */
38129 uint16_t pair_index;
38130 /* Pair pf index. */
38132 /* Pair vf index. */
38134 /* Pair name (32 byte string). */
38135 char pair_name[32];
38138 /* hwrm_cfa_pair_info_output (size:576b/72B) */
38139 struct hwrm_cfa_pair_info_output {
38140 /* The specific error status for the command. */
38141 uint16_t error_code;
38142 /* The HWRM command request type. */
38144 /* The sequence ID from the original command. */
38146 /* The length of the response data in number of bytes. */
38148 /* Pair table index. */
38149 uint16_t next_pair_index;
38150 /* Pair member a's fid. */
38152 /* Logical host number. */
38153 uint8_t host_a_index;
38154 /* Logical PF number. */
38155 uint8_t pf_a_index;
38156 /* Pair member a's Linux logical VF number. */
38157 uint16_t vf_a_index;
38159 uint16_t rx_cfa_code_a;
38160 /* Tx CFA action. */
38161 uint16_t tx_cfa_action_a;
38162 /* Pair member b's fid. */
38164 /* Logical host number. */
38165 uint8_t host_b_index;
38166 /* Logical PF number. */
38167 uint8_t pf_b_index;
38168 /* Pair member a's Linux logical VF number. */
38169 uint16_t vf_b_index;
38171 uint16_t rx_cfa_code_b;
38172 /* Tx CFA action. */
38173 uint16_t tx_cfa_action_b;
38174 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
38176 /* Pair between VF on local host with PF or VF on specified host. */
38177 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
38178 /* Pair between REP on local host with PF or VF on specified host. */
38179 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
38180 /* Pair between REP on local host with REP on specified host. */
38181 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
38182 /* Pair for the proxy interface. */
38183 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
38184 /* Pair for the PF interface. */
38185 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
38186 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
38187 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
38189 uint8_t pair_state;
38190 /* Pair has been allocated */
38191 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
38192 /* Both pair members are active */
38193 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
38194 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
38195 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
38196 /* Pair name (32 byte string). */
38197 char pair_name[32];
38198 uint8_t unused_0[7];
38200 * This field is used in Output records to indicate that the output
38201 * is completely written to RAM. This field should be read as '1'
38202 * to indicate that the output has been completely written.
38203 * When writing a command completion or response to an internal processor,
38204 * the order of writes has to be such that this field is written last.
38209 /**********************
38210 * hwrm_cfa_vfr_alloc *
38211 **********************/
38214 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
38215 struct hwrm_cfa_vfr_alloc_input {
38216 /* The HWRM command request type. */
38219 * The completion ring to send the completion event on. This should
38220 * be the NQ ID returned from the `nq_alloc` HWRM command.
38222 uint16_t cmpl_ring;
38224 * The sequence ID is used by the driver for tracking multiple
38225 * commands. This ID is treated as opaque data by the firmware and
38226 * the value is returned in the `hwrm_resp_hdr` upon completion.
38230 * The target ID of the command:
38231 * * 0x0-0xFFF8 - The function ID
38232 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38233 * * 0xFFFD - Reserved for user-space HWRM interface
38236 uint16_t target_id;
38238 * A physical address pointer pointing to a host buffer that the
38239 * command's response data will be written. This can be either a host
38240 * physical address (HPA) or a guest physical address (GPA) and must
38241 * point to a physically contiguous block of memory.
38243 uint64_t resp_addr;
38244 /* Logical VF number (range: 0 -> MAX_VFS -1). */
38247 * This field is reserved for the future use.
38248 * It shall be set to 0.
38251 uint8_t unused_0[4];
38252 /* VF Representor name (32 byte string). */
38256 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
38257 struct hwrm_cfa_vfr_alloc_output {
38258 /* The specific error status for the command. */
38259 uint16_t error_code;
38260 /* The HWRM command request type. */
38262 /* The sequence ID from the original command. */
38264 /* The length of the response data in number of bytes. */
38267 uint16_t rx_cfa_code;
38268 /* Tx CFA action. */
38269 uint16_t tx_cfa_action;
38270 uint8_t unused_0[3];
38272 * This field is used in Output records to indicate that the output
38273 * is completely written to RAM. This field should be read as '1'
38274 * to indicate that the output has been completely written.
38275 * When writing a command completion or response to an internal processor,
38276 * the order of writes has to be such that this field is written last.
38281 /*********************
38282 * hwrm_cfa_vfr_free *
38283 *********************/
38286 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
38287 struct hwrm_cfa_vfr_free_input {
38288 /* The HWRM command request type. */
38291 * The completion ring to send the completion event on. This should
38292 * be the NQ ID returned from the `nq_alloc` HWRM command.
38294 uint16_t cmpl_ring;
38296 * The sequence ID is used by the driver for tracking multiple
38297 * commands. This ID is treated as opaque data by the firmware and
38298 * the value is returned in the `hwrm_resp_hdr` upon completion.
38302 * The target ID of the command:
38303 * * 0x0-0xFFF8 - The function ID
38304 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38305 * * 0xFFFD - Reserved for user-space HWRM interface
38308 uint16_t target_id;
38310 * A physical address pointer pointing to a host buffer that the
38311 * command's response data will be written. This can be either a host
38312 * physical address (HPA) or a guest physical address (GPA) and must
38313 * point to a physically contiguous block of memory.
38315 uint64_t resp_addr;
38316 /* VF Representor name (32 byte string). */
38318 /* Logical VF number (range: 0 -> MAX_VFS -1). */
38321 * This field is reserved for the future use.
38322 * It shall be set to 0.
38325 uint8_t unused_0[4];
38328 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
38329 struct hwrm_cfa_vfr_free_output {
38330 /* The specific error status for the command. */
38331 uint16_t error_code;
38332 /* The HWRM command request type. */
38334 /* The sequence ID from the original command. */
38336 /* The length of the response data in number of bytes. */
38338 uint8_t unused_0[7];
38340 * This field is used in Output records to indicate that the output
38341 * is completely written to RAM. This field should be read as '1'
38342 * to indicate that the output has been completely written.
38343 * When writing a command completion or response to an internal processor,
38344 * the order of writes has to be such that this field is written last.
38349 /***************************************
38350 * hwrm_cfa_redirect_query_tunnel_type *
38351 ***************************************/
38354 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
38355 struct hwrm_cfa_redirect_query_tunnel_type_input {
38356 /* The HWRM command request type. */
38359 * The completion ring to send the completion event on. This should
38360 * be the NQ ID returned from the `nq_alloc` HWRM command.
38362 uint16_t cmpl_ring;
38364 * The sequence ID is used by the driver for tracking multiple
38365 * commands. This ID is treated as opaque data by the firmware and
38366 * the value is returned in the `hwrm_resp_hdr` upon completion.
38370 * The target ID of the command:
38371 * * 0x0-0xFFF8 - The function ID
38372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38373 * * 0xFFFD - Reserved for user-space HWRM interface
38376 uint16_t target_id;
38378 * A physical address pointer pointing to a host buffer that the
38379 * command's response data will be written. This can be either a host
38380 * physical address (HPA) or a guest physical address (GPA) and must
38381 * point to a physically contiguous block of memory.
38383 uint64_t resp_addr;
38384 /* The source function id. */
38386 uint8_t unused_0[6];
38389 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
38390 struct hwrm_cfa_redirect_query_tunnel_type_output {
38391 /* The specific error status for the command. */
38392 uint16_t error_code;
38393 /* The HWRM command request type. */
38395 /* The sequence ID from the original command. */
38397 /* The length of the response data in number of bytes. */
38400 uint32_t tunnel_mask;
38402 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
38404 /* Virtual eXtensible Local Area Network (VXLAN) */
38405 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
38407 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38408 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
38410 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38411 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
38414 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
38416 /* Generic Network Virtualization Encapsulation (Geneve) */
38417 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
38419 /* Multi-Protocol Label Switching (MPLS) */
38420 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
38422 /* Stateless Transport Tunnel (STT) */
38423 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
38425 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38426 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
38428 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38429 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
38431 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
38432 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
38434 /* Any tunneled traffic */
38435 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
38437 /* Use fixed layer 2 ether type of 0xFFFF */
38438 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
38440 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
38441 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
38443 uint8_t unused_0[3];
38445 * This field is used in Output records to indicate that the output
38446 * is completely written to RAM. This field should be read as '1'
38447 * to indicate that the output has been completely written.
38448 * When writing a command completion or response to an internal processor,
38449 * the order of writes has to be such that this field is written last.
38454 /*************************
38455 * hwrm_cfa_ctx_mem_rgtr *
38456 *************************/
38459 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
38460 struct hwrm_cfa_ctx_mem_rgtr_input {
38461 /* The HWRM command request type. */
38464 * The completion ring to send the completion event on. This should
38465 * be the NQ ID returned from the `nq_alloc` HWRM command.
38467 uint16_t cmpl_ring;
38469 * The sequence ID is used by the driver for tracking multiple
38470 * commands. This ID is treated as opaque data by the firmware and
38471 * the value is returned in the `hwrm_resp_hdr` upon completion.
38475 * The target ID of the command:
38476 * * 0x0-0xFFF8 - The function ID
38477 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38478 * * 0xFFFD - Reserved for user-space HWRM interface
38481 uint16_t target_id;
38483 * A physical address pointer pointing to a host buffer that the
38484 * command's response data will be written. This can be either a host
38485 * physical address (HPA) or a guest physical address (GPA) and must
38486 * point to a physically contiguous block of memory.
38488 uint64_t resp_addr;
38490 /* Counter PBL indirect levels. */
38491 uint8_t page_level;
38492 /* PBL pointer is physical start address. */
38493 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
38494 /* PBL pointer points to PTE table. */
38495 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
38496 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
38497 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
38498 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
38499 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
38502 /* 4KB page size. */
38503 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
38504 /* 8KB page size. */
38505 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
38506 /* 64KB page size. */
38507 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
38508 /* 256KB page size. */
38509 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
38510 /* 1MB page size. */
38511 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
38512 /* 2MB page size. */
38513 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
38514 /* 4MB page size. */
38515 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
38516 /* 1GB page size. */
38517 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
38518 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
38519 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
38521 /* Pointer to the PBL, or PDL depending on number of levels */
38525 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
38526 struct hwrm_cfa_ctx_mem_rgtr_output {
38527 /* The specific error status for the command. */
38528 uint16_t error_code;
38529 /* The HWRM command request type. */
38531 /* The sequence ID from the original command. */
38533 /* The length of the response data in number of bytes. */
38536 * Id/Handle to the recently register context memory. This handle is passed
38537 * to the CFA feature.
38540 uint8_t unused_0[5];
38542 * This field is used in Output records to indicate that the output
38543 * is completely written to RAM. This field should be read as '1'
38544 * to indicate that the output has been completely written.
38545 * When writing a command completion or response to an internal processor,
38546 * the order of writes has to be such that this field is written last.
38551 /***************************
38552 * hwrm_cfa_ctx_mem_unrgtr *
38553 ***************************/
38556 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
38557 struct hwrm_cfa_ctx_mem_unrgtr_input {
38558 /* The HWRM command request type. */
38561 * The completion ring to send the completion event on. This should
38562 * be the NQ ID returned from the `nq_alloc` HWRM command.
38564 uint16_t cmpl_ring;
38566 * The sequence ID is used by the driver for tracking multiple
38567 * commands. This ID is treated as opaque data by the firmware and
38568 * the value is returned in the `hwrm_resp_hdr` upon completion.
38572 * The target ID of the command:
38573 * * 0x0-0xFFF8 - The function ID
38574 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38575 * * 0xFFFD - Reserved for user-space HWRM interface
38578 uint16_t target_id;
38580 * A physical address pointer pointing to a host buffer that the
38581 * command's response data will be written. This can be either a host
38582 * physical address (HPA) or a guest physical address (GPA) and must
38583 * point to a physically contiguous block of memory.
38585 uint64_t resp_addr;
38587 * Id/Handle to the recently register context memory. This handle is passed
38588 * to the CFA feature.
38591 uint8_t unused_0[6];
38594 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
38595 struct hwrm_cfa_ctx_mem_unrgtr_output {
38596 /* The specific error status for the command. */
38597 uint16_t error_code;
38598 /* The HWRM command request type. */
38600 /* The sequence ID from the original command. */
38602 /* The length of the response data in number of bytes. */
38604 uint8_t unused_0[7];
38606 * This field is used in Output records to indicate that the output
38607 * is completely written to RAM. This field should be read as '1'
38608 * to indicate that the output has been completely written.
38609 * When writing a command completion or response to an internal processor,
38610 * the order of writes has to be such that this field is written last.
38615 /*************************
38616 * hwrm_cfa_ctx_mem_qctx *
38617 *************************/
38620 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
38621 struct hwrm_cfa_ctx_mem_qctx_input {
38622 /* The HWRM command request type. */
38625 * The completion ring to send the completion event on. This should
38626 * be the NQ ID returned from the `nq_alloc` HWRM command.
38628 uint16_t cmpl_ring;
38630 * The sequence ID is used by the driver for tracking multiple
38631 * commands. This ID is treated as opaque data by the firmware and
38632 * the value is returned in the `hwrm_resp_hdr` upon completion.
38636 * The target ID of the command:
38637 * * 0x0-0xFFF8 - The function ID
38638 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38639 * * 0xFFFD - Reserved for user-space HWRM interface
38642 uint16_t target_id;
38644 * A physical address pointer pointing to a host buffer that the
38645 * command's response data will be written. This can be either a host
38646 * physical address (HPA) or a guest physical address (GPA) and must
38647 * point to a physically contiguous block of memory.
38649 uint64_t resp_addr;
38651 * Id/Handle to the recently register context memory. This handle is passed
38652 * to the CFA feature.
38655 uint8_t unused_0[6];
38658 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
38659 struct hwrm_cfa_ctx_mem_qctx_output {
38660 /* The specific error status for the command. */
38661 uint16_t error_code;
38662 /* The HWRM command request type. */
38664 /* The sequence ID from the original command. */
38666 /* The length of the response data in number of bytes. */
38669 /* Counter PBL indirect levels. */
38670 uint8_t page_level;
38671 /* PBL pointer is physical start address. */
38672 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
38673 /* PBL pointer points to PTE table. */
38674 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
38675 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
38676 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
38677 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
38678 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
38681 /* 4KB page size. */
38682 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
38683 /* 8KB page size. */
38684 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
38685 /* 64KB page size. */
38686 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
38687 /* 256KB page size. */
38688 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
38689 /* 1MB page size. */
38690 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
38691 /* 2MB page size. */
38692 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
38693 /* 4MB page size. */
38694 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
38695 /* 1GB page size. */
38696 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
38697 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
38698 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
38699 uint8_t unused_0[4];
38700 /* Pointer to the PBL, or PDL depending on number of levels */
38702 uint8_t unused_1[7];
38704 * This field is used in Output records to indicate that the output
38705 * is completely written to RAM. This field should be read as '1'
38706 * to indicate that the output has been completely written.
38707 * When writing a command completion or response to an internal processor,
38708 * the order of writes has to be such that this field is written last.
38713 /**************************
38714 * hwrm_cfa_ctx_mem_qcaps *
38715 **************************/
38718 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
38719 struct hwrm_cfa_ctx_mem_qcaps_input {
38720 /* The HWRM command request type. */
38723 * The completion ring to send the completion event on. This should
38724 * be the NQ ID returned from the `nq_alloc` HWRM command.
38726 uint16_t cmpl_ring;
38728 * The sequence ID is used by the driver for tracking multiple
38729 * commands. This ID is treated as opaque data by the firmware and
38730 * the value is returned in the `hwrm_resp_hdr` upon completion.
38734 * The target ID of the command:
38735 * * 0x0-0xFFF8 - The function ID
38736 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38737 * * 0xFFFD - Reserved for user-space HWRM interface
38740 uint16_t target_id;
38742 * A physical address pointer pointing to a host buffer that the
38743 * command's response data will be written. This can be either a host
38744 * physical address (HPA) or a guest physical address (GPA) and must
38745 * point to a physically contiguous block of memory.
38747 uint64_t resp_addr;
38750 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
38751 struct hwrm_cfa_ctx_mem_qcaps_output {
38752 /* The specific error status for the command. */
38753 uint16_t error_code;
38754 /* The HWRM command request type. */
38756 /* The sequence ID from the original command. */
38758 /* The length of the response data in number of bytes. */
38760 /* Indicates the maximum number of context memory which can be registered. */
38761 uint16_t max_entries;
38762 uint8_t unused_0[5];
38764 * This field is used in Output records to indicate that the output
38765 * is completely written to RAM. This field should be read as '1'
38766 * to indicate that the output has been completely written.
38767 * When writing a command completion or response to an internal processor,
38768 * the order of writes has to be such that this field is written last.
38773 /**************************
38774 * hwrm_cfa_counter_qcaps *
38775 **************************/
38778 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
38779 struct hwrm_cfa_counter_qcaps_input {
38780 /* The HWRM command request type. */
38783 * The completion ring to send the completion event on. This should
38784 * be the NQ ID returned from the `nq_alloc` HWRM command.
38786 uint16_t cmpl_ring;
38788 * The sequence ID is used by the driver for tracking multiple
38789 * commands. This ID is treated as opaque data by the firmware and
38790 * the value is returned in the `hwrm_resp_hdr` upon completion.
38794 * The target ID of the command:
38795 * * 0x0-0xFFF8 - The function ID
38796 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38797 * * 0xFFFD - Reserved for user-space HWRM interface
38800 uint16_t target_id;
38802 * A physical address pointer pointing to a host buffer that the
38803 * command's response data will be written. This can be either a host
38804 * physical address (HPA) or a guest physical address (GPA) and must
38805 * point to a physically contiguous block of memory.
38807 uint64_t resp_addr;
38810 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
38811 struct hwrm_cfa_counter_qcaps_output {
38812 /* The specific error status for the command. */
38813 uint16_t error_code;
38814 /* The HWRM command request type. */
38816 /* The sequence ID from the original command. */
38818 /* The length of the response data in number of bytes. */
38821 /* Enumeration denoting the supported CFA counter format. */
38822 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
38824 /* CFA counter types are not supported. */
38825 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
38827 /* 64-bit packet counters followed by 64-bit byte counters format. */
38828 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
38830 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
38831 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
38834 * Minimum guaranteed number of flow counters supported for this function,
38837 uint32_t min_rx_fc;
38839 * Maximum non-guaranteed number of flow counters supported for this function,
38842 uint32_t max_rx_fc;
38844 * Minimum guaranteed number of flow counters supported for this function,
38847 uint32_t min_tx_fc;
38849 * Maximum non-guaranteed number of flow counters supported for this function,
38852 uint32_t max_tx_fc;
38854 * Minimum guaranteed number of extension flow counters supported for this
38855 * function, in RX direction.
38857 uint32_t min_rx_efc;
38859 * Maximum non-guaranteed number of extension flow counters supported for
38860 * this function, in RX direction.
38862 uint32_t max_rx_efc;
38864 * Minimum guaranteed number of extension flow counters supported for this
38865 * function, in TX direction.
38867 uint32_t min_tx_efc;
38869 * Maximum non-guaranteed number of extension flow counters supported for
38870 * this function, in TX direction.
38872 uint32_t max_tx_efc;
38874 * Minimum guaranteed number of meter drop counters supported for this
38875 * function, in RX direction.
38877 uint32_t min_rx_mdc;
38879 * Maximum non-guaranteed number of meter drop counters supported for this
38880 * function, in RX direction.
38882 uint32_t max_rx_mdc;
38884 * Minimum guaranteed number of meter drop counters supported for this
38885 * function, in TX direction.
38887 uint32_t min_tx_mdc;
38889 * Maximum non-guaranteed number of meter drop counters supported for this
38890 * function, in TX direction.
38892 uint32_t max_tx_mdc;
38893 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
38894 uint32_t max_flow_alloc_fc;
38895 uint8_t unused_1[3];
38897 * This field is used in Output records to indicate that the output
38898 * is completely written to RAM. This field should be read as '1'
38899 * to indicate that the output has been completely written.
38900 * When writing a command completion or response to an internal processor,
38901 * the order of writes has to be such that this field is written last.
38906 /************************
38907 * hwrm_cfa_counter_cfg *
38908 ************************/
38911 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
38912 struct hwrm_cfa_counter_cfg_input {
38913 /* The HWRM command request type. */
38916 * The completion ring to send the completion event on. This should
38917 * be the NQ ID returned from the `nq_alloc` HWRM command.
38919 uint16_t cmpl_ring;
38921 * The sequence ID is used by the driver for tracking multiple
38922 * commands. This ID is treated as opaque data by the firmware and
38923 * the value is returned in the `hwrm_resp_hdr` upon completion.
38927 * The target ID of the command:
38928 * * 0x0-0xFFF8 - The function ID
38929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38930 * * 0xFFFD - Reserved for user-space HWRM interface
38933 uint16_t target_id;
38935 * A physical address pointer pointing to a host buffer that the
38936 * command's response data will be written. This can be either a host
38937 * physical address (HPA) or a guest physical address (GPA) and must
38938 * point to a physically contiguous block of memory.
38940 uint64_t resp_addr;
38942 /* Enumeration denoting the configuration mode. */
38943 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
38945 /* Disable the configuration mode. */
38946 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
38948 /* Enable the configuration mode. */
38949 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
38951 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
38952 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
38953 /* Enumeration denoting the RX, TX type of the resource. */
38954 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
38957 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
38958 (UINT32_C(0x0) << 1)
38960 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
38961 (UINT32_C(0x1) << 1)
38962 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
38963 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
38964 /* Enumeration denoting the data transfer mode. */
38965 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
38967 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
38969 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
38970 (UINT32_C(0x0) << 2)
38972 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
38973 (UINT32_C(0x1) << 2)
38974 /* Pull on async update. */
38975 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
38976 (UINT32_C(0x2) << 2)
38977 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
38978 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
38979 uint16_t counter_type;
38980 /* Flow counters. */
38981 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
38982 /* Extended flow counters. */
38983 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
38984 /* Meter drop counters. */
38985 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
38986 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
38987 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
38988 /* Ctx memory handle to be used for the counter. */
38990 /* Counter update cadence hint (only in Push mode). */
38991 uint16_t update_tmr_ms;
38992 /* Total number of entries. */
38993 uint32_t num_entries;
38997 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
38998 struct hwrm_cfa_counter_cfg_output {
38999 /* The specific error status for the command. */
39000 uint16_t error_code;
39001 /* The HWRM command request type. */
39003 /* The sequence ID from the original command. */
39005 /* The length of the response data in number of bytes. */
39007 uint8_t unused_0[7];
39009 * This field is used in Output records to indicate that the output
39010 * is completely written to RAM. This field should be read as '1'
39011 * to indicate that the output has been completely written.
39012 * When writing a command completion or response to an internal processor,
39013 * the order of writes has to be such that this field is written last.
39018 /***************************
39019 * hwrm_cfa_counter_qstats *
39020 ***************************/
39023 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
39024 struct hwrm_cfa_counter_qstats_input {
39025 /* The HWRM command request type. */
39028 * The completion ring to send the completion event on. This should
39029 * be the NQ ID returned from the `nq_alloc` HWRM command.
39031 uint16_t cmpl_ring;
39033 * The sequence ID is used by the driver for tracking multiple
39034 * commands. This ID is treated as opaque data by the firmware and
39035 * the value is returned in the `hwrm_resp_hdr` upon completion.
39039 * The target ID of the command:
39040 * * 0x0-0xFFF8 - The function ID
39041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39042 * * 0xFFFD - Reserved for user-space HWRM interface
39045 uint16_t target_id;
39047 * A physical address pointer pointing to a host buffer that the
39048 * command's response data will be written. This can be either a host
39049 * physical address (HPA) or a guest physical address (GPA) and must
39050 * point to a physically contiguous block of memory.
39052 uint64_t resp_addr;
39054 /* Enumeration denoting the RX, TX type of the resource. */
39055 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
39057 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39059 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39060 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
39061 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
39062 uint16_t counter_type;
39063 uint16_t input_flow_ctx_id;
39064 uint16_t num_entries;
39065 uint16_t delta_time_ms;
39066 uint16_t meter_instance_id;
39067 uint16_t mdc_ctx_id;
39068 uint8_t unused_0[2];
39069 uint64_t expected_count;
39072 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
39073 struct hwrm_cfa_counter_qstats_output {
39074 /* The specific error status for the command. */
39075 uint16_t error_code;
39076 /* The HWRM command request type. */
39078 /* The sequence ID from the original command. */
39080 /* The length of the response data in number of bytes. */
39082 uint8_t unused_0[7];
39084 * This field is used in Output records to indicate that the output
39085 * is completely written to RAM. This field should be read as '1'
39086 * to indicate that the output has been completely written.
39087 * When writing a command completion or response to an internal processor,
39088 * the order of writes has to be such that this field is written last.
39093 /**********************
39094 * hwrm_cfa_eem_qcaps *
39095 **********************/
39098 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
39099 struct hwrm_cfa_eem_qcaps_input {
39100 /* The HWRM command request type. */
39103 * The completion ring to send the completion event on. This should
39104 * be the NQ ID returned from the `nq_alloc` HWRM command.
39106 uint16_t cmpl_ring;
39108 * The sequence ID is used by the driver for tracking multiple
39109 * commands. This ID is treated as opaque data by the firmware and
39110 * the value is returned in the `hwrm_resp_hdr` upon completion.
39114 * The target ID of the command:
39115 * * 0x0-0xFFF8 - The function ID
39116 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39117 * * 0xFFFD - Reserved for user-space HWRM interface
39120 uint16_t target_id;
39122 * A physical address pointer pointing to a host buffer that the
39123 * command's response data will be written. This can be either a host
39124 * physical address (HPA) or a guest physical address (GPA) and must
39125 * point to a physically contiguous block of memory.
39127 uint64_t resp_addr;
39130 * When set to 1, indicates the configuration will apply to TX flows
39131 * which are to be offloaded.
39132 * Note if this bit is set then the path_rx bit can't be set.
39134 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
39137 * When set to 1, indicates the configuration will apply to RX flows
39138 * which are to be offloaded.
39139 * Note if this bit is set then the path_tx bit can't be set.
39141 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
39143 /* When set to 1, all offloaded flows will be sent to EEM. */
39144 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
39149 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
39150 struct hwrm_cfa_eem_qcaps_output {
39151 /* The specific error status for the command. */
39152 uint16_t error_code;
39153 /* The HWRM command request type. */
39155 /* The sequence ID from the original command. */
39157 /* The length of the response data in number of bytes. */
39161 * When set to 1, indicates the configuration will apply to TX flows
39162 * which are to be offloaded.
39163 * Note if this bit is set then the path_rx bit can't be set.
39165 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
39168 * When set to 1, indicates the configuration will apply to RX flows
39169 * which are to be offloaded.
39170 * Note if this bit is set then the path_tx bit can't be set.
39172 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
39175 * When set to 1, indicates the FW supports the Centralized
39176 * Memory Model. The concept designates one entity for the
39177 * memory allocation while all others ‘subscribe’ to it.
39179 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
39182 * When set to 1, indicates the FW supports the Detached
39183 * Centralized Memory Model. The memory is allocated and managed
39184 * as a separate entity. All PFs and VFs will be granted direct
39185 * or semi-direct access to the allocated memory while none of
39186 * which can interfere with the management of the memory.
39188 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
39191 uint32_t supported;
39193 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
39194 * If set to 0, EEM KEY0 table is not supported.
39196 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
39199 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
39200 * If set to 0, EEM KEY1 table is not supported.
39202 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
39205 * If set to 1, then EEM External Record table is supported.
39206 * If set to 0, EEM External Record table is not supported.
39207 * (This table includes action record, EFC pointers, encap pointers)
39209 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
39212 * If set to 1, then EEM External Flow Counters table is supported.
39213 * If set to 0, EEM External Flow Counters table is not supported.
39215 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
39218 * If set to 1, then FID table used for implicit flow flush is supported.
39219 * If set to 0, then FID table used for implicit flow flush is not supported.
39221 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
39224 * The maximum number of entries supported by EEM. When configuring the host memory
39225 * the number of numbers of entries that can supported are -
39226 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
39227 * Any value that are not these values, the FW will round down to the closest support
39228 * number of entries.
39230 uint32_t max_entries_supported;
39231 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
39232 uint16_t key_entry_size;
39233 /* The entry size in bytes of each entry in the EEM RECORD tables. */
39234 uint16_t record_entry_size;
39235 /* The entry size in bytes of each entry in the EEM EFC tables. */
39236 uint16_t efc_entry_size;
39237 /* The FID size in bytes of each entry in the EEM FID tables. */
39238 uint16_t fid_entry_size;
39239 uint8_t unused_1[7];
39241 * This field is used in Output records to indicate that the output
39242 * is completely written to RAM. This field should be read as '1'
39243 * to indicate that the output has been completely written.
39244 * When writing a command completion or response to an internal processor,
39245 * the order of writes has to be such that this field is written last.
39250 /********************
39251 * hwrm_cfa_eem_cfg *
39252 ********************/
39255 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
39256 struct hwrm_cfa_eem_cfg_input {
39257 /* The HWRM command request type. */
39260 * The completion ring to send the completion event on. This should
39261 * be the NQ ID returned from the `nq_alloc` HWRM command.
39263 uint16_t cmpl_ring;
39265 * The sequence ID is used by the driver for tracking multiple
39266 * commands. This ID is treated as opaque data by the firmware and
39267 * the value is returned in the `hwrm_resp_hdr` upon completion.
39271 * The target ID of the command:
39272 * * 0x0-0xFFF8 - The function ID
39273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39274 * * 0xFFFD - Reserved for user-space HWRM interface
39277 uint16_t target_id;
39279 * A physical address pointer pointing to a host buffer that the
39280 * command's response data will be written. This can be either a host
39281 * physical address (HPA) or a guest physical address (GPA) and must
39282 * point to a physically contiguous block of memory.
39284 uint64_t resp_addr;
39287 * When set to 1, indicates the configuration will apply to TX flows
39288 * which are to be offloaded.
39289 * Note if this bit is set then the path_rx bit can't be set.
39291 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
39294 * When set to 1, indicates the configuration will apply to RX flows
39295 * which are to be offloaded.
39296 * Note if this bit is set then the path_tx bit can't be set.
39298 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
39300 /* When set to 1, all offloaded flows will be sent to EEM. */
39301 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
39303 /* When set to 1, secondary, 0 means primary. */
39304 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
39307 * Group_id which used by Firmware to identify memory pools belonging
39308 * to certain group.
39313 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
39314 * RECORD, EFC all have the same number of entries and all tables will be configured
39315 * using this value. Current minimum value is 32k. Current maximum value is 128M.
39317 uint32_t num_entries;
39319 /* Configured EEM with the given context if for KEY0 table. */
39320 uint16_t key0_ctx_id;
39321 /* Configured EEM with the given context if for KEY1 table. */
39322 uint16_t key1_ctx_id;
39323 /* Configured EEM with the given context if for RECORD table. */
39324 uint16_t record_ctx_id;
39325 /* Configured EEM with the given context if for EFC table. */
39326 uint16_t efc_ctx_id;
39327 /* Configured EEM with the given context if for EFC table. */
39328 uint16_t fid_ctx_id;
39333 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
39334 struct hwrm_cfa_eem_cfg_output {
39335 /* The specific error status for the command. */
39336 uint16_t error_code;
39337 /* The HWRM command request type. */
39339 /* The sequence ID from the original command. */
39341 /* The length of the response data in number of bytes. */
39343 uint8_t unused_0[7];
39345 * This field is used in Output records to indicate that the output
39346 * is completely written to RAM. This field should be read as '1'
39347 * to indicate that the output has been completely written.
39348 * When writing a command completion or response to an internal processor,
39349 * the order of writes has to be such that this field is written last.
39354 /*********************
39355 * hwrm_cfa_eem_qcfg *
39356 *********************/
39359 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
39360 struct hwrm_cfa_eem_qcfg_input {
39361 /* The HWRM command request type. */
39364 * The completion ring to send the completion event on. This should
39365 * be the NQ ID returned from the `nq_alloc` HWRM command.
39367 uint16_t cmpl_ring;
39369 * The sequence ID is used by the driver for tracking multiple
39370 * commands. This ID is treated as opaque data by the firmware and
39371 * the value is returned in the `hwrm_resp_hdr` upon completion.
39375 * The target ID of the command:
39376 * * 0x0-0xFFF8 - The function ID
39377 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39378 * * 0xFFFD - Reserved for user-space HWRM interface
39381 uint16_t target_id;
39383 * A physical address pointer pointing to a host buffer that the
39384 * command's response data will be written. This can be either a host
39385 * physical address (HPA) or a guest physical address (GPA) and must
39386 * point to a physically contiguous block of memory.
39388 uint64_t resp_addr;
39390 /* When set to 1, indicates the configuration is the TX flow. */
39391 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
39392 /* When set to 1, indicates the configuration is the RX flow. */
39393 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
39397 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
39398 struct hwrm_cfa_eem_qcfg_output {
39399 /* The specific error status for the command. */
39400 uint16_t error_code;
39401 /* The HWRM command request type. */
39403 /* The sequence ID from the original command. */
39405 /* The length of the response data in number of bytes. */
39408 /* When set to 1, indicates the configuration is the TX flow. */
39409 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
39411 /* When set to 1, indicates the configuration is the RX flow. */
39412 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
39414 /* When set to 1, all offloaded flows will be sent to EEM. */
39415 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
39417 /* The number of entries the FW has configured for EEM. */
39418 uint32_t num_entries;
39419 /* Configured EEM with the given context if for KEY0 table. */
39420 uint16_t key0_ctx_id;
39421 /* Configured EEM with the given context if for KEY1 table. */
39422 uint16_t key1_ctx_id;
39423 /* Configured EEM with the given context if for RECORD table. */
39424 uint16_t record_ctx_id;
39425 /* Configured EEM with the given context if for EFC table. */
39426 uint16_t efc_ctx_id;
39427 /* Configured EEM with the given context if for EFC table. */
39428 uint16_t fid_ctx_id;
39429 uint8_t unused_2[5];
39431 * This field is used in Output records to indicate that the output
39432 * is completely written to RAM. This field should be read as '1'
39433 * to indicate that the output has been completely written.
39434 * When writing a command completion or response to an internal processor,
39435 * the order of writes has to be such that this field is written last.
39440 /*******************
39441 * hwrm_cfa_eem_op *
39442 *******************/
39445 /* hwrm_cfa_eem_op_input (size:192b/24B) */
39446 struct hwrm_cfa_eem_op_input {
39447 /* The HWRM command request type. */
39450 * The completion ring to send the completion event on. This should
39451 * be the NQ ID returned from the `nq_alloc` HWRM command.
39453 uint16_t cmpl_ring;
39455 * The sequence ID is used by the driver for tracking multiple
39456 * commands. This ID is treated as opaque data by the firmware and
39457 * the value is returned in the `hwrm_resp_hdr` upon completion.
39461 * The target ID of the command:
39462 * * 0x0-0xFFF8 - The function ID
39463 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39464 * * 0xFFFD - Reserved for user-space HWRM interface
39467 uint16_t target_id;
39469 * A physical address pointer pointing to a host buffer that the
39470 * command's response data will be written. This can be either a host
39471 * physical address (HPA) or a guest physical address (GPA) and must
39472 * point to a physically contiguous block of memory.
39474 uint64_t resp_addr;
39477 * When set to 1, indicates the host memory which is passed will be
39478 * used for the TX flow offload function specified in fid.
39479 * Note if this bit is set then the path_rx bit can't be set.
39481 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
39483 * When set to 1, indicates the host memory which is passed will be
39484 * used for the RX flow offload function specified in fid.
39485 * Note if this bit is set then the path_tx bit can't be set.
39487 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
39489 /* The number of EEM key table entries to be configured. */
39491 /* This value is reserved and should not be used. */
39492 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
39494 * To properly stop EEM and ensure there are no DMA's, the caller
39495 * must disable EEM for the given PF, using this call. This will
39496 * safely disable EEM and ensure that all DMA'ed to the
39497 * keys/records/efc have been completed.
39499 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
39501 * Once the EEM host memory has been configured, EEM options have
39502 * been configured. Then the caller should enable EEM for the given
39503 * PF. Note once this call has been made, then the EEM mechanism
39504 * will be active and DMA's will occur as packets are processed.
39506 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
39508 * Clear EEM settings for the given PF so that the register values
39509 * are reset back to there initial state.
39511 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
39512 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
39513 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
39516 /* hwrm_cfa_eem_op_output (size:128b/16B) */
39517 struct hwrm_cfa_eem_op_output {
39518 /* The specific error status for the command. */
39519 uint16_t error_code;
39520 /* The HWRM command request type. */
39522 /* The sequence ID from the original command. */
39524 /* The length of the response data in number of bytes. */
39526 uint8_t unused_0[7];
39528 * This field is used in Output records to indicate that the output
39529 * is completely written to RAM. This field should be read as '1'
39530 * to indicate that the output has been completely written.
39531 * When writing a command completion or response to an internal processor,
39532 * the order of writes has to be such that this field is written last.
39537 /********************************
39538 * hwrm_cfa_adv_flow_mgnt_qcaps *
39539 ********************************/
39542 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
39543 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
39544 /* The HWRM command request type. */
39547 * The completion ring to send the completion event on. This should
39548 * be the NQ ID returned from the `nq_alloc` HWRM command.
39550 uint16_t cmpl_ring;
39552 * The sequence ID is used by the driver for tracking multiple
39553 * commands. This ID is treated as opaque data by the firmware and
39554 * the value is returned in the `hwrm_resp_hdr` upon completion.
39558 * The target ID of the command:
39559 * * 0x0-0xFFF8 - The function ID
39560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39561 * * 0xFFFD - Reserved for user-space HWRM interface
39564 uint16_t target_id;
39566 * A physical address pointer pointing to a host buffer that the
39567 * command's response data will be written. This can be either a host
39568 * physical address (HPA) or a guest physical address (GPA) and must
39569 * point to a physically contiguous block of memory.
39571 uint64_t resp_addr;
39572 uint32_t unused_0[4];
39575 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
39576 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
39577 /* The specific error status for the command. */
39578 uint16_t error_code;
39579 /* The HWRM command request type. */
39581 /* The sequence ID from the original command. */
39583 /* The length of the response data in number of bytes. */
39587 * Value of 1 to indicate firmware support 16-bit flow handle.
39588 * Value of 0 to indicate firmware not support 16-bit flow handle.
39590 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
39593 * Value of 1 to indicate firmware support 64-bit flow handle.
39594 * Value of 0 to indicate firmware not support 64-bit flow handle.
39596 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
39599 * Value of 1 to indicate firmware support flow batch delete operation through
39600 * HWRM_CFA_FLOW_FLUSH command.
39601 * Value of 0 to indicate that the firmware does not support flow batch delete
39604 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
39607 * Value of 1 to indicate that the firmware support flow reset all operation through
39608 * HWRM_CFA_FLOW_FLUSH command.
39609 * Value of 0 indicates firmware does not support flow reset all operation.
39611 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
39614 * Value of 1 to indicate that firmware supports use of FID as dest_id in
39615 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
39616 * Value of 0 indicates firmware does not support use of FID as dest_id.
39618 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
39621 * Value of 1 to indicate that firmware supports TX EEM flows.
39622 * Value of 0 indicates firmware does not support TX EEM flows.
39624 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
39627 * Value of 1 to indicate that firmware supports RX EEM flows.
39628 * Value of 0 indicates firmware does not support RX EEM flows.
39630 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
39633 * Value of 1 to indicate that firmware supports the dynamic allocation of an
39634 * on-chip flow counter which can be used for EEM flows.
39635 * Value of 0 indicates firmware does not support the dynamic allocation of an
39636 * on-chip flow counter.
39638 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
39641 * Value of 1 to indicate that firmware supports setting of
39642 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
39643 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
39645 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
39648 * Value of 1 to indicate that firmware supports untagged matching
39649 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
39650 * indicates firmware does not support untagged matching.
39652 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
39655 * Value of 1 to indicate that firmware supports XDP filter. Value
39656 * of 0 indicates firmware does not support XDP filter.
39658 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
39661 * Value of 1 to indicate that the firmware support L2 header source
39662 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
39663 * Value of 0 indicates firmware does not support L2 header source
39666 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
39669 * If set to 1, firmware is capable of supporting ARP ethertype as
39670 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
39671 * RX direction. By default, this flag should be 0 for older version
39674 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
39677 * Value of 1 to indicate that firmware supports setting of
39678 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
39679 * command. Value of 0 indicates firmware does not support
39680 * rfs_ring_tbl_idx in dst_id field.
39682 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
39685 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
39686 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
39687 * direction. By default, this flag should be 0 for older version
39690 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
39692 uint8_t unused_0[3];
39694 * This field is used in Output records to indicate that the output
39695 * is completely written to RAM. This field should be read as '1'
39696 * to indicate that the output has been completely written.
39697 * When writing a command completion or response to an internal processor,
39698 * the order of writes has to be such that this field is written last.
39703 /******************
39705 ******************/
39708 /* hwrm_cfa_tflib_input (size:1024b/128B) */
39709 struct hwrm_cfa_tflib_input {
39710 /* The HWRM command request type. */
39713 * The completion ring to send the completion event on. This should
39714 * be the NQ ID returned from the `nq_alloc` HWRM command.
39716 uint16_t cmpl_ring;
39718 * The sequence ID is used by the driver for tracking multiple
39719 * commands. This ID is treated as opaque data by the firmware and
39720 * the value is returned in the `hwrm_resp_hdr` upon completion.
39724 * The target ID of the command:
39725 * * 0x0-0xFFF8 - The function ID
39726 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39727 * * 0xFFFD - Reserved for user-space HWRM interface
39730 uint16_t target_id;
39732 * A physical address pointer pointing to a host buffer that the
39733 * command's response data will be written. This can be either a host
39734 * physical address (HPA) or a guest physical address (GPA) and must
39735 * point to a physically contiguous block of memory.
39737 uint64_t resp_addr;
39738 /* TFLIB message type. */
39740 /* TFLIB message subtype. */
39741 uint16_t tf_subtype;
39743 uint8_t unused0[4];
39744 /* TFLIB request data. */
39745 uint32_t tf_req[26];
39748 /* hwrm_cfa_tflib_output (size:5632b/704B) */
39749 struct hwrm_cfa_tflib_output {
39750 /* The specific error status for the command. */
39751 uint16_t error_code;
39752 /* The HWRM command request type. */
39754 /* The sequence ID from the original command. */
39756 /* The length of the response data in number of bytes. */
39758 /* TFLIB message type. */
39760 /* TFLIB message subtype. */
39761 uint16_t tf_subtype;
39762 /* TFLIB response code */
39763 uint32_t tf_resp_code;
39764 /* TFLIB response data. */
39765 uint32_t tf_resp[170];
39767 uint8_t unused1[7];
39769 * This field is used in Output records to indicate that the output
39770 * is completely written to RAM. This field should be read as '1'
39771 * to indicate that the output has been completely written.
39772 * When writing a command completion or response to an internal processor,
39773 * the order of writes has to be such that this field is written last.
39783 /* hwrm_tf_input (size:1024b/128B) */
39784 struct hwrm_tf_input {
39785 /* The HWRM command request type. */
39788 * The completion ring to send the completion event on. This should
39789 * be the NQ ID returned from the `nq_alloc` HWRM command.
39791 uint16_t cmpl_ring;
39793 * The sequence ID is used by the driver for tracking multiple
39794 * commands. This ID is treated as opaque data by the firmware and
39795 * the value is returned in the `hwrm_resp_hdr` upon completion.
39799 * The target ID of the command:
39800 * * 0x0-0xFFF8 - The function ID
39801 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39802 * * 0xFFFD - Reserved for user-space HWRM interface
39805 uint16_t target_id;
39807 * A physical address pointer pointing to a host buffer that the
39808 * command's response data will be written. This can be either a host
39809 * physical address (HPA) or a guest physical address (GPA) and must
39810 * point to a physically contiguous block of memory.
39812 uint64_t resp_addr;
39813 /* TF message type. */
39815 /* TF message subtype. */
39818 uint8_t unused0[4];
39819 /* TF request data. */
39823 /* hwrm_tf_output (size:5632b/704B) */
39824 struct hwrm_tf_output {
39825 /* The specific error status for the command. */
39826 uint16_t error_code;
39827 /* The HWRM command request type. */
39829 /* The sequence ID from the original command. */
39831 /* The length of the response data in number of bytes. */
39833 /* TF message type. */
39835 /* TF message subtype. */
39837 /* TF response code */
39838 uint32_t resp_code;
39839 /* TF response data. */
39840 uint32_t resp[170];
39842 uint8_t unused1[7];
39844 * This field is used in Output records to indicate that the
39845 * output is completely written to RAM. This field should be
39846 * read as '1' to indicate that the output has been
39847 * completely written. When writing a command completion or
39848 * response to an internal processor, the order of writes has
39849 * to be such that this field is written last.
39854 /***********************
39855 * hwrm_tf_version_get *
39856 ***********************/
39859 /* hwrm_tf_version_get_input (size:128b/16B) */
39860 struct hwrm_tf_version_get_input {
39861 /* The HWRM command request type. */
39864 * The completion ring to send the completion event on. This should
39865 * be the NQ ID returned from the `nq_alloc` HWRM command.
39867 uint16_t cmpl_ring;
39869 * The sequence ID is used by the driver for tracking multiple
39870 * commands. This ID is treated as opaque data by the firmware and
39871 * the value is returned in the `hwrm_resp_hdr` upon completion.
39875 * The target ID of the command:
39876 * * 0x0-0xFFF8 - The function ID
39877 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39878 * * 0xFFFD - Reserved for user-space HWRM interface
39881 uint16_t target_id;
39883 * A physical address pointer pointing to a host buffer that the
39884 * command's response data will be written. This can be either a host
39885 * physical address (HPA) or a guest physical address (GPA) and must
39886 * point to a physically contiguous block of memory.
39888 uint64_t resp_addr;
39891 /* hwrm_tf_version_get_output (size:128b/16B) */
39892 struct hwrm_tf_version_get_output {
39893 /* The specific error status for the command. */
39894 uint16_t error_code;
39895 /* The HWRM command request type. */
39897 /* The sequence ID from the original command. */
39899 /* The length of the response data in number of bytes. */
39901 /* Version Major number. */
39903 /* Version Minor number. */
39905 /* Version Update number. */
39908 uint8_t unused0[4];
39910 * This field is used in Output records to indicate that the output
39911 * is completely written to RAM. This field should be read as '1'
39912 * to indicate that the output has been completely written.
39913 * When writing a command completion or response to an internal
39914 * processor, the order of writes has to be such that this field is
39920 /************************
39921 * hwrm_tf_session_open *
39922 ************************/
39925 /* hwrm_tf_session_open_input (size:640b/80B) */
39926 struct hwrm_tf_session_open_input {
39927 /* The HWRM command request type. */
39930 * The completion ring to send the completion event on. This should
39931 * be the NQ ID returned from the `nq_alloc` HWRM command.
39933 uint16_t cmpl_ring;
39935 * The sequence ID is used by the driver for tracking multiple
39936 * commands. This ID is treated as opaque data by the firmware and
39937 * the value is returned in the `hwrm_resp_hdr` upon completion.
39941 * The target ID of the command:
39942 * * 0x0-0xFFF8 - The function ID
39943 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39944 * * 0xFFFD - Reserved for user-space HWRM interface
39947 uint16_t target_id;
39949 * A physical address pointer pointing to a host buffer that the
39950 * command's response data will be written. This can be either a host
39951 * physical address (HPA) or a guest physical address (GPA) and must
39952 * point to a physically contiguous block of memory.
39954 uint64_t resp_addr;
39955 /* Name of the session. */
39956 uint8_t session_name[64];
39959 /* hwrm_tf_session_open_output (size:192b/24B) */
39960 struct hwrm_tf_session_open_output {
39961 /* The specific error status for the command. */
39962 uint16_t error_code;
39963 /* The HWRM command request type. */
39965 /* The sequence ID from the original command. */
39967 /* The length of the response data in number of bytes. */
39970 * Unique session identifier for the session created by the
39973 uint32_t fw_session_id;
39975 * Unique session client identifier for the first client on
39976 * the newly created session.
39978 uint32_t fw_session_client_id;
39982 uint8_t unused1[3];
39984 * This field is used in Output records to indicate that the output
39985 * is completely written to RAM. This field should be read as '1'
39986 * to indicate that the output has been completely written.
39987 * When writing a command completion or response to an internal
39988 * processor, the order of writes has to be such that this field is
39994 /**************************
39995 * hwrm_tf_session_attach *
39996 **************************/
39999 /* hwrm_tf_session_attach_input (size:704b/88B) */
40000 struct hwrm_tf_session_attach_input {
40001 /* The HWRM command request type. */
40004 * The completion ring to send the completion event on. This should
40005 * be the NQ ID returned from the `nq_alloc` HWRM command.
40007 uint16_t cmpl_ring;
40009 * The sequence ID is used by the driver for tracking multiple
40010 * commands. This ID is treated as opaque data by the firmware and
40011 * the value is returned in the `hwrm_resp_hdr` upon completion.
40015 * The target ID of the command:
40016 * * 0x0-0xFFF8 - The function ID
40017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40018 * * 0xFFFD - Reserved for user-space HWRM interface
40021 uint16_t target_id;
40023 * A physical address pointer pointing to a host buffer that the
40024 * command's response data will be written. This can be either a host
40025 * physical address (HPA) or a guest physical address (GPA) and must
40026 * point to a physically contiguous block of memory.
40028 uint64_t resp_addr;
40030 * Unique session identifier for the session that the attach
40031 * request want to attach to. This value originates from the
40032 * shared session memory that the attach request opened by
40033 * way of the 'attach name' that was passed in to the core
40035 * The fw_session_id of the attach session includes PCIe bus
40036 * info to distinguish the PF and session info to identify
40037 * the associated TruFlow session.
40039 uint32_t attach_fw_session_id;
40042 /* Name of the session it self. */
40043 uint8_t session_name[64];
40046 /* hwrm_tf_session_attach_output (size:128b/16B) */
40047 struct hwrm_tf_session_attach_output {
40048 /* The specific error status for the command. */
40049 uint16_t error_code;
40050 /* The HWRM command request type. */
40052 /* The sequence ID from the original command. */
40054 /* The length of the response data in number of bytes. */
40057 * Unique session identifier for the session created by the
40058 * firmware. It includes PCIe bus info to distinguish the PF
40059 * and session info to identify the associated TruFlow
40060 * session. This fw_session_id is unique to the attach
40063 uint32_t fw_session_id;
40065 uint8_t unused0[3];
40067 * This field is used in Output records to indicate that the output
40068 * is completely written to RAM. This field should be read as '1'
40069 * to indicate that the output has been completely written.
40070 * When writing a command completion or response to an internal
40071 * processor, the order of writes has to be such that this field is
40077 /****************************
40078 * hwrm_tf_session_register *
40079 ****************************/
40082 /* hwrm_tf_session_register_input (size:704b/88B) */
40083 struct hwrm_tf_session_register_input {
40084 /* The HWRM command request type. */
40087 * The completion ring to send the completion event on. This should
40088 * be the NQ ID returned from the `nq_alloc` HWRM command.
40090 uint16_t cmpl_ring;
40092 * The sequence ID is used by the driver for tracking multiple
40093 * commands. This ID is treated as opaque data by the firmware and
40094 * the value is returned in the `hwrm_resp_hdr` upon completion.
40098 * The target ID of the command:
40099 * * 0x0-0xFFF8 - The function ID
40100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40101 * * 0xFFFD - Reserved for user-space HWRM interface
40104 uint16_t target_id;
40106 * A physical address pointer pointing to a host buffer that the
40107 * command's response data will be written. This can be either a host
40108 * physical address (HPA) or a guest physical address (GPA) and must
40109 * point to a physically contiguous block of memory.
40111 uint64_t resp_addr;
40113 * Unique session identifier for the session that the
40114 * register request want to create a new client on. This
40115 * value originates from the first open request.
40116 * The fw_session_id of the attach session includes PCIe bus
40117 * info to distinguish the PF and session info to identify
40118 * the associated TruFlow session.
40120 uint32_t fw_session_id;
40123 /* Name of the session client. */
40124 uint8_t session_client_name[64];
40127 /* hwrm_tf_session_register_output (size:128b/16B) */
40128 struct hwrm_tf_session_register_output {
40129 /* The specific error status for the command. */
40130 uint16_t error_code;
40131 /* The HWRM command request type. */
40133 /* The sequence ID from the original command. */
40135 /* The length of the response data in number of bytes. */
40138 * Unique session client identifier for the session created
40139 * by the firmware. It includes the session the client it
40140 * attached to and session client info.
40142 uint32_t fw_session_client_id;
40144 uint8_t unused0[3];
40146 * This field is used in Output records to indicate that the output
40147 * is completely written to RAM. This field should be read as '1'
40148 * to indicate that the output has been completely written.
40149 * When writing a command completion or response to an internal
40150 * processor, the order of writes has to be such that this field is
40156 /******************************
40157 * hwrm_tf_session_unregister *
40158 ******************************/
40161 /* hwrm_tf_session_unregister_input (size:192b/24B) */
40162 struct hwrm_tf_session_unregister_input {
40163 /* The HWRM command request type. */
40166 * The completion ring to send the completion event on. This should
40167 * be the NQ ID returned from the `nq_alloc` HWRM command.
40169 uint16_t cmpl_ring;
40171 * The sequence ID is used by the driver for tracking multiple
40172 * commands. This ID is treated as opaque data by the firmware and
40173 * the value is returned in the `hwrm_resp_hdr` upon completion.
40177 * The target ID of the command:
40178 * * 0x0-0xFFF8 - The function ID
40179 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40180 * * 0xFFFD - Reserved for user-space HWRM interface
40183 uint16_t target_id;
40185 * A physical address pointer pointing to a host buffer that the
40186 * command's response data will be written. This can be either a host
40187 * physical address (HPA) or a guest physical address (GPA) and must
40188 * point to a physically contiguous block of memory.
40190 uint64_t resp_addr;
40192 * Unique session identifier for the session that the
40193 * unregister request want to close a session client on.
40195 uint32_t fw_session_id;
40197 * Unique session client identifier for the session that the
40198 * unregister request want to close.
40200 uint32_t fw_session_client_id;
40203 /* hwrm_tf_session_unregister_output (size:128b/16B) */
40204 struct hwrm_tf_session_unregister_output {
40205 /* The specific error status for the command. */
40206 uint16_t error_code;
40207 /* The HWRM command request type. */
40209 /* The sequence ID from the original command. */
40211 /* The length of the response data in number of bytes. */
40214 uint8_t unused0[7];
40216 * This field is used in Output records to indicate that the output
40217 * is completely written to RAM. This field should be read as '1'
40218 * to indicate that the output has been completely written.
40219 * When writing a command completion or response to an internal
40220 * processor, the order of writes has to be such that this field is
40226 /*************************
40227 * hwrm_tf_session_close *
40228 *************************/
40231 /* hwrm_tf_session_close_input (size:192b/24B) */
40232 struct hwrm_tf_session_close_input {
40233 /* The HWRM command request type. */
40236 * The completion ring to send the completion event on. This should
40237 * be the NQ ID returned from the `nq_alloc` HWRM command.
40239 uint16_t cmpl_ring;
40241 * The sequence ID is used by the driver for tracking multiple
40242 * commands. This ID is treated as opaque data by the firmware and
40243 * the value is returned in the `hwrm_resp_hdr` upon completion.
40247 * The target ID of the command:
40248 * * 0x0-0xFFF8 - The function ID
40249 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40250 * * 0xFFFD - Reserved for user-space HWRM interface
40253 uint16_t target_id;
40255 * A physical address pointer pointing to a host buffer that the
40256 * command's response data will be written. This can be either a host
40257 * physical address (HPA) or a guest physical address (GPA) and must
40258 * point to a physically contiguous block of memory.
40260 uint64_t resp_addr;
40261 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40262 uint32_t fw_session_id;
40264 uint8_t unused0[4];
40267 /* hwrm_tf_session_close_output (size:128b/16B) */
40268 struct hwrm_tf_session_close_output {
40269 /* The specific error status for the command. */
40270 uint16_t error_code;
40271 /* The HWRM command request type. */
40273 /* The sequence ID from the original command. */
40275 /* The length of the response data in number of bytes. */
40278 uint8_t unused0[7];
40280 * This field is used in Output records to indicate that the output
40281 * is completely written to RAM. This field should be read as '1'
40282 * to indicate that the output has been completely written.
40283 * When writing a command completion or response to an internal
40284 * processor, the order of writes has to be such that this field
40290 /************************
40291 * hwrm_tf_session_qcfg *
40292 ************************/
40295 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
40296 struct hwrm_tf_session_qcfg_input {
40297 /* The HWRM command request type. */
40300 * The completion ring to send the completion event on. This should
40301 * be the NQ ID returned from the `nq_alloc` HWRM command.
40303 uint16_t cmpl_ring;
40305 * The sequence ID is used by the driver for tracking multiple
40306 * commands. This ID is treated as opaque data by the firmware and
40307 * the value is returned in the `hwrm_resp_hdr` upon completion.
40311 * The target ID of the command:
40312 * * 0x0-0xFFF8 - The function ID
40313 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40314 * * 0xFFFD - Reserved for user-space HWRM interface
40317 uint16_t target_id;
40319 * A physical address pointer pointing to a host buffer that the
40320 * command's response data will be written. This can be either a host
40321 * physical address (HPA) or a guest physical address (GPA) and must
40322 * point to a physically contiguous block of memory.
40324 uint64_t resp_addr;
40325 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40326 uint32_t fw_session_id;
40328 uint8_t unused0[4];
40331 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
40332 struct hwrm_tf_session_qcfg_output {
40333 /* The specific error status for the command. */
40334 uint16_t error_code;
40335 /* The HWRM command request type. */
40337 /* The sequence ID from the original command. */
40339 /* The length of the response data in number of bytes. */
40341 /* RX action control settings flags. */
40342 uint8_t rx_act_flags;
40344 * A value of 1 in this field indicates that Global Flow ID
40345 * reporting into cfa_code and cfa_metadata is enabled.
40347 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
40350 * A value of 1 in this field indicates that both inner and outer
40351 * are stripped and inner tag is passed.
40354 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
40357 * A value of 1 in this field indicates that the re-use of
40358 * existing tunnel L2 header SMAC is enabled for
40359 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
40361 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
40363 /* TX Action control settings flags. */
40364 uint8_t tx_act_flags;
40366 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
40369 * When set to 1 any GRE tunnels will include the
40370 * optional Key field.
40372 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
40375 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
40376 * field of the outer header is inherited from the inner header
40377 * (if present) or the fixed value as taken from the encap
40380 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
40383 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
40384 * field of the outer header is inherited from the inner header
40385 * (if present) or the fixed value as taken from the encap record.
40387 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
40390 uint8_t unused0[5];
40392 * This field is used in Output records to indicate that the output
40393 * is completely written to RAM. This field should be read as '1'
40394 * to indicate that the output has been completely written.
40395 * When writing a command completion or response to an internal
40396 * processor, the order of writes has to be such that this field
40402 /******************************
40403 * hwrm_tf_session_resc_qcaps *
40404 ******************************/
40407 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
40408 struct hwrm_tf_session_resc_qcaps_input {
40409 /* The HWRM command request type. */
40412 * The completion ring to send the completion event on. This should
40413 * be the NQ ID returned from the `nq_alloc` HWRM command.
40415 uint16_t cmpl_ring;
40417 * The sequence ID is used by the driver for tracking multiple
40418 * commands. This ID is treated as opaque data by the firmware and
40419 * the value is returned in the `hwrm_resp_hdr` upon completion.
40423 * The target ID of the command:
40424 * * 0x0-0xFFF8 - The function ID
40425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40426 * * 0xFFFD - Reserved for user-space HWRM interface
40429 uint16_t target_id;
40431 * A physical address pointer pointing to a host buffer that the
40432 * command's response data will be written. This can be either a host
40433 * physical address (HPA) or a guest physical address (GPA) and must
40434 * point to a physically contiguous block of memory.
40436 uint64_t resp_addr;
40437 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40438 uint32_t fw_session_id;
40439 /* Control flags. */
40441 /* Indicates the flow direction. */
40442 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
40443 /* If this bit set to 0, then it indicates rx flow. */
40444 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40445 /* If this bit is set to 1, then it indicates that tx flow. */
40446 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40447 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
40448 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
40450 * Defines the size of the provided qcaps_addr array
40451 * buffer. The size should be set to the Resource Manager
40452 * provided max number of qcaps entries which is device
40453 * specific. Resource Manager gets the max size from HCAPI
40456 uint16_t qcaps_size;
40458 * This is the DMA address for the qcaps output data array
40459 * buffer. Array is of tf_rm_resc_req_entry type and is
40462 uint64_t qcaps_addr;
40465 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
40466 struct hwrm_tf_session_resc_qcaps_output {
40467 /* The specific error status for the command. */
40468 uint16_t error_code;
40469 /* The HWRM command request type. */
40471 /* The sequence ID from the original command. */
40473 /* The length of the response data in number of bytes. */
40475 /* Control flags. */
40477 /* Session reservation strategy. */
40478 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
40480 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
40482 /* Static partitioning. */
40483 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
40486 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
40489 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
40492 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
40494 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
40495 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
40497 * Size of the returned qcaps_addr data array buffer. The
40498 * value cannot exceed the size defined by the input msg,
40505 uint8_t unused1[7];
40507 * This field is used in Output records to indicate that the output
40508 * is completely written to RAM. This field should be read as '1'
40509 * to indicate that the output has been completely written.
40510 * When writing a command completion or response to an internal
40511 * processor, the order of writes has to be such that this field is
40517 /******************************
40518 * hwrm_tf_session_resc_alloc *
40519 ******************************/
40522 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
40523 struct hwrm_tf_session_resc_alloc_input {
40524 /* The HWRM command request type. */
40527 * The completion ring to send the completion event on. This should
40528 * be the NQ ID returned from the `nq_alloc` HWRM command.
40530 uint16_t cmpl_ring;
40532 * The sequence ID is used by the driver for tracking multiple
40533 * commands. This ID is treated as opaque data by the firmware and
40534 * the value is returned in the `hwrm_resp_hdr` upon completion.
40538 * The target ID of the command:
40539 * * 0x0-0xFFF8 - The function ID
40540 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40541 * * 0xFFFD - Reserved for user-space HWRM interface
40544 uint16_t target_id;
40546 * A physical address pointer pointing to a host buffer that the
40547 * command's response data will be written. This can be either a host
40548 * physical address (HPA) or a guest physical address (GPA) and must
40549 * point to a physically contiguous block of memory.
40551 uint64_t resp_addr;
40552 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40553 uint32_t fw_session_id;
40554 /* Control flags. */
40556 /* Indicates the flow direction. */
40557 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
40558 /* If this bit set to 0, then it indicates rx flow. */
40559 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40560 /* If this bit is set to 1, then it indicates that tx flow. */
40561 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40562 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
40563 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
40565 * Defines the array size of the provided req_addr and
40566 * resv_addr array buffers. Should be set to the number of
40571 * This is the DMA address for the request input data array
40572 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
40573 * array buffer is provided by the 'req_size' field in this
40578 * This is the DMA address for the resc output data array
40579 * buffer. Array is of tf_rm_resc_entry type. Size of the array
40580 * buffer is provided by the 'req_size' field in this
40583 uint64_t resc_addr;
40586 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
40587 struct hwrm_tf_session_resc_alloc_output {
40588 /* The specific error status for the command. */
40589 uint16_t error_code;
40590 /* The HWRM command request type. */
40592 /* The sequence ID from the original command. */
40594 /* The length of the response data in number of bytes. */
40597 * Size of the returned tf_rm_resc_entry data array. The value
40598 * cannot exceed the req_size defined by the input msg. The data
40599 * array is returned using the resv_addr specified DMA
40600 * address also provided by the input msg.
40604 uint8_t unused0[5];
40606 * This field is used in Output records to indicate that the output
40607 * is completely written to RAM. This field should be read as '1'
40608 * to indicate that the output has been completely written.
40609 * When writing a command completion or response to an internal
40610 * processor, the order of writes has to be such that this field is
40616 /*****************************
40617 * hwrm_tf_session_resc_free *
40618 *****************************/
40621 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
40622 struct hwrm_tf_session_resc_free_input {
40623 /* The HWRM command request type. */
40626 * The completion ring to send the completion event on. This should
40627 * be the NQ ID returned from the `nq_alloc` HWRM command.
40629 uint16_t cmpl_ring;
40631 * The sequence ID is used by the driver for tracking multiple
40632 * commands. This ID is treated as opaque data by the firmware and
40633 * the value is returned in the `hwrm_resp_hdr` upon completion.
40637 * The target ID of the command:
40638 * * 0x0-0xFFF8 - The function ID
40639 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40640 * * 0xFFFD - Reserved for user-space HWRM interface
40643 uint16_t target_id;
40645 * A physical address pointer pointing to a host buffer that the
40646 * command's response data will be written. This can be either a host
40647 * physical address (HPA) or a guest physical address (GPA) and must
40648 * point to a physically contiguous block of memory.
40650 uint64_t resp_addr;
40651 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40652 uint32_t fw_session_id;
40653 /* Control flags. */
40655 /* Indicates the flow direction. */
40656 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
40657 /* If this bit set to 0, then it indicates rx flow. */
40658 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40659 /* If this bit is set to 1, then it indicates that tx flow. */
40660 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40661 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
40662 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
40664 * Defines the size, in bytes, of the provided free_addr
40667 uint16_t free_size;
40669 * This is the DMA address for the free input data array
40670 * buffer. Array is of tf_rm_resc_entry type. Size of the
40671 * buffer is provided by the 'free_size' field of this
40674 uint64_t free_addr;
40677 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
40678 struct hwrm_tf_session_resc_free_output {
40679 /* The specific error status for the command. */
40680 uint16_t error_code;
40681 /* The HWRM command request type. */
40683 /* The sequence ID from the original command. */
40685 /* The length of the response data in number of bytes. */
40688 uint8_t unused0[7];
40690 * This field is used in Output records to indicate that the output
40691 * is completely written to RAM. This field should be read as '1'
40692 * to indicate that the output has been completely written.
40693 * When writing a command completion or response to an internal
40694 * processor, the order of writes has to be such that this field is
40700 /******************************
40701 * hwrm_tf_session_resc_flush *
40702 ******************************/
40705 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
40706 struct hwrm_tf_session_resc_flush_input {
40707 /* The HWRM command request type. */
40710 * The completion ring to send the completion event on. This should
40711 * be the NQ ID returned from the `nq_alloc` HWRM command.
40713 uint16_t cmpl_ring;
40715 * The sequence ID is used by the driver for tracking multiple
40716 * commands. This ID is treated as opaque data by the firmware and
40717 * the value is returned in the `hwrm_resp_hdr` upon completion.
40721 * The target ID of the command:
40722 * * 0x0-0xFFF8 - The function ID
40723 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40724 * * 0xFFFD - Reserved for user-space HWRM interface
40727 uint16_t target_id;
40729 * A physical address pointer pointing to a host buffer that the
40730 * command's response data will be written. This can be either a host
40731 * physical address (HPA) or a guest physical address (GPA) and must
40732 * point to a physically contiguous block of memory.
40734 uint64_t resp_addr;
40735 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40736 uint32_t fw_session_id;
40737 /* Control flags. */
40739 /* Indicates the flow direction. */
40740 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
40741 /* If this bit set to 0, then it indicates rx flow. */
40742 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40743 /* If this bit is set to 1, then it indicates that tx flow. */
40744 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40745 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
40746 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
40748 * Defines the size, in bytes, of the provided flush_addr
40751 uint16_t flush_size;
40753 * This is the DMA address for the flush input data array
40754 * buffer. Array of tf_rm_resc_entry type. Size of the
40755 * buffer is provided by the 'flush_size' field in this
40758 uint64_t flush_addr;
40761 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
40762 struct hwrm_tf_session_resc_flush_output {
40763 /* The specific error status for the command. */
40764 uint16_t error_code;
40765 /* The HWRM command request type. */
40767 /* The sequence ID from the original command. */
40769 /* The length of the response data in number of bytes. */
40772 uint8_t unused0[7];
40774 * This field is used in Output records to indicate that the output
40775 * is completely written to RAM. This field should be read as '1'
40776 * to indicate that the output has been completely written.
40777 * When writing a command completion or response to an internal
40778 * processor, the order of writes has to be such that this field is
40784 /* TruFlow RM capability of a resource. */
40785 /* tf_rm_resc_req_entry (size:64b/8B) */
40786 struct tf_rm_resc_req_entry {
40787 /* Type of the resource, defined globally in HCAPI RM. */
40789 /* Minimum value. */
40791 /* Maximum value. */
40795 /* TruFlow RM reservation information. */
40796 /* tf_rm_resc_entry (size:64b/8B) */
40797 struct tf_rm_resc_entry {
40798 /* Type of the resource, defined globally in HCAPI RM. */
40800 /* Start offset. */
40802 /* Number of resources. */
40806 /************************
40807 * hwrm_tf_tbl_type_get *
40808 ************************/
40811 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
40812 struct hwrm_tf_tbl_type_get_input {
40813 /* The HWRM command request type. */
40816 * The completion ring to send the completion event on. This should
40817 * be the NQ ID returned from the `nq_alloc` HWRM command.
40819 uint16_t cmpl_ring;
40821 * The sequence ID is used by the driver for tracking multiple
40822 * commands. This ID is treated as opaque data by the firmware and
40823 * the value is returned in the `hwrm_resp_hdr` upon completion.
40827 * The target ID of the command:
40828 * * 0x0-0xFFF8 - The function ID
40829 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40830 * * 0xFFFD - Reserved for user-space HWRM interface
40833 uint16_t target_id;
40835 * A physical address pointer pointing to a host buffer that the
40836 * command's response data will be written. This can be either a host
40837 * physical address (HPA) or a guest physical address (GPA) and must
40838 * point to a physically contiguous block of memory.
40840 uint64_t resp_addr;
40841 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40842 uint32_t fw_session_id;
40843 /* Control flags. */
40845 /* Indicates the flow direction. */
40846 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
40847 /* If this bit set to 0, then it indicates rx flow. */
40848 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40849 /* If this bit is set to 1, then it indicates that tx flow. */
40850 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40851 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
40852 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
40854 uint8_t unused0[2];
40856 * Type of the resource, defined globally in the
40857 * hwrm_tf_resc_type enum.
40860 /* Index of the type to retrieve. */
40864 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
40865 struct hwrm_tf_tbl_type_get_output {
40866 /* The specific error status for the command. */
40867 uint16_t error_code;
40868 /* The HWRM command request type. */
40870 /* The sequence ID from the original command. */
40872 /* The length of the response data in number of bytes. */
40874 /* Response code. */
40875 uint32_t resp_code;
40876 /* Response size. */
40880 /* Response data. */
40883 uint8_t unused1[7];
40885 * This field is used in Output records to indicate that the output
40886 * is completely written to RAM. This field should be read as '1'
40887 * to indicate that the output has been completely written.
40888 * When writing a command completion or response to an internal
40889 * processor, the order of writes has to be such that this field
40895 /************************
40896 * hwrm_tf_tbl_type_set *
40897 ************************/
40900 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
40901 struct hwrm_tf_tbl_type_set_input {
40902 /* The HWRM command request type. */
40905 * The completion ring to send the completion event on. This should
40906 * be the NQ ID returned from the `nq_alloc` HWRM command.
40908 uint16_t cmpl_ring;
40910 * The sequence ID is used by the driver for tracking multiple
40911 * commands. This ID is treated as opaque data by the firmware and
40912 * the value is returned in the `hwrm_resp_hdr` upon completion.
40916 * The target ID of the command:
40917 * * 0x0-0xFFF8 - The function ID
40918 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40919 * * 0xFFFD - Reserved for user-space HWRM interface
40922 uint16_t target_id;
40924 * A physical address pointer pointing to a host buffer that the
40925 * command's response data will be written. This can be either a host
40926 * physical address (HPA) or a guest physical address (GPA) and must
40927 * point to a physically contiguous block of memory.
40929 uint64_t resp_addr;
40930 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
40931 uint32_t fw_session_id;
40932 /* Control flags. */
40934 /* Indicates the flow direction. */
40935 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
40936 /* If this bit set to 0, then it indicates rx flow. */
40937 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
40938 /* If this bit is set to 1, then it indicates that tx flow. */
40939 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
40940 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
40941 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
40943 uint8_t unused0[2];
40945 * Type of the resource, defined globally in the
40946 * hwrm_tf_resc_type enum.
40949 /* Index of the type to retrieve. */
40951 /* Size of the data to set. */
40954 uint8_t unused1[6];
40955 /* Data to be set. */
40959 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
40960 struct hwrm_tf_tbl_type_set_output {
40961 /* The specific error status for the command. */
40962 uint16_t error_code;
40963 /* The HWRM command request type. */
40965 /* The sequence ID from the original command. */
40967 /* The length of the response data in number of bytes. */
40970 uint8_t unused0[7];
40972 * This field is used in Output records to indicate that the output
40973 * is completely written to RAM. This field should be read as '1'
40974 * to indicate that the output has been completely written.
40975 * When writing a command completion or response to an internal
40976 * processor, the order of writes has to be such that this field
40982 /**************************
40983 * hwrm_tf_ctxt_mem_alloc *
40984 **************************/
40987 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
40988 struct hwrm_tf_ctxt_mem_alloc_input {
40989 /* The HWRM command request type. */
40992 * The completion ring to send the completion event on. This should
40993 * be the NQ ID returned from the `nq_alloc` HWRM command.
40995 uint16_t cmpl_ring;
40997 * The sequence ID is used by the driver for tracking multiple
40998 * commands. This ID is treated as opaque data by the firmware and
40999 * the value is returned in the `hwrm_resp_hdr` upon completion.
41003 * The target ID of the command:
41004 * * 0x0-0xFFF8 - The function ID
41005 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41006 * * 0xFFFD - Reserved for user-space HWRM interface
41009 uint16_t target_id;
41011 * A physical address pointer pointing to a host buffer that the
41012 * command's response data will be written. This can be either a host
41013 * physical address (HPA) or a guest physical address (GPA) and must
41014 * point to a physically contiguous block of memory.
41016 uint64_t resp_addr;
41017 /* Size in KB of memory to be allocated. */
41023 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
41024 struct hwrm_tf_ctxt_mem_alloc_output {
41025 /* The specific error status for the command. */
41026 uint16_t error_code;
41027 /* The HWRM command request type. */
41029 /* The sequence ID from the original command. */
41031 /* The length of the response data in number of bytes. */
41033 /* Pointer to the PBL, or PDL depending on number of levels */
41035 /* Counter PBL indirect levels. */
41036 uint8_t page_level;
41037 /* PBL pointer is physical start address. */
41038 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
41039 /* PBL pointer points to PTE table. */
41040 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
41042 * PBL pointer points to PDE table with each entry pointing
41045 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
41046 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
41047 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
41050 /* 4KB page size. */
41051 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
41052 /* 8KB page size. */
41053 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
41054 /* 64KB page size. */
41055 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
41056 /* 128KB page size. */
41057 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
41058 /* 256KB page size. */
41059 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
41060 /* 512KB page size. */
41061 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
41062 /* 1MB page size. */
41063 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
41064 /* 2MB page size. */
41065 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
41066 /* 4MB page size. */
41067 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
41068 /* 8MB page size. */
41069 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
41070 /* 1GB page size. */
41071 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
41072 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
41073 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
41075 uint8_t unused0[5];
41077 * This field is used in Output records to indicate that the
41078 * output is completely written to RAM. This field should be
41079 * read as '1' to indicate that the output has been
41080 * completely written. When writing a command completion or
41081 * response to an internal processor, the order of writes has
41082 * to be such that this field is written last.
41087 /*************************
41088 * hwrm_tf_ctxt_mem_free *
41089 *************************/
41092 /* hwrm_tf_ctxt_mem_free_input (size:256b/32B) */
41093 struct hwrm_tf_ctxt_mem_free_input {
41094 /* The HWRM command request type. */
41097 * The completion ring to send the completion event on. This should
41098 * be the NQ ID returned from the `nq_alloc` HWRM command.
41100 uint16_t cmpl_ring;
41102 * The sequence ID is used by the driver for tracking multiple
41103 * commands. This ID is treated as opaque data by the firmware and
41104 * the value is returned in the `hwrm_resp_hdr` upon completion.
41108 * The target ID of the command:
41109 * * 0x0-0xFFF8 - The function ID
41110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41111 * * 0xFFFD - Reserved for user-space HWRM interface
41114 uint16_t target_id;
41116 * A physical address pointer pointing to a host buffer that the
41117 * command's response data will be written. This can be either a host
41118 * physical address (HPA) or a guest physical address (GPA) and must
41119 * point to a physically contiguous block of memory.
41121 uint64_t resp_addr;
41122 /* Pointer to the PBL, or PDL depending on number of levels */
41124 /* Counter PBL indirect levels. */
41125 uint8_t page_level;
41126 /* PBL pointer is physical start address. */
41127 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
41128 /* PBL pointer points to PTE table. */
41129 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
41131 * PBL pointer points to PDE table with each entry pointing
41134 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
41135 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
41136 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
41139 /* 4KB page size. */
41140 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
41141 /* 8KB page size. */
41142 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
41143 /* 64KB page size. */
41144 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
41145 /* 128KB page size. */
41146 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
41147 /* 256KB page size. */
41148 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
41149 /* 512KB page size. */
41150 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
41151 /* 1MB page size. */
41152 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
41153 /* 2MB page size. */
41154 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
41155 /* 4MB page size. */
41156 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
41157 /* 8MB page size. */
41158 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
41159 /* 1GB page size. */
41160 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
41161 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
41162 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
41164 uint8_t unused0[6];
41167 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
41168 struct hwrm_tf_ctxt_mem_free_output {
41169 /* The specific error status for the command. */
41170 uint16_t error_code;
41171 /* The HWRM command request type. */
41173 /* The sequence ID from the original command. */
41175 /* The length of the response data in number of bytes. */
41178 uint8_t unused0[7];
41180 * This field is used in Output records to indicate that the
41181 * output is completely written to RAM. This field should be
41182 * read as '1' to indicate that the output has been
41183 * completely written. When writing a command completion or
41184 * response to an internal processor, the order of writes has
41185 * to be such that this field is written last.
41190 /*************************
41191 * hwrm_tf_ctxt_mem_rgtr *
41192 *************************/
41195 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
41196 struct hwrm_tf_ctxt_mem_rgtr_input {
41197 /* The HWRM command request type. */
41200 * The completion ring to send the completion event on. This should
41201 * be the NQ ID returned from the `nq_alloc` HWRM command.
41203 uint16_t cmpl_ring;
41205 * The sequence ID is used by the driver for tracking multiple
41206 * commands. This ID is treated as opaque data by the firmware and
41207 * the value is returned in the `hwrm_resp_hdr` upon completion.
41211 * The target ID of the command:
41212 * * 0x0-0xFFF8 - The function ID
41213 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41214 * * 0xFFFD - Reserved for user-space HWRM interface
41217 uint16_t target_id;
41219 * A physical address pointer pointing to a host buffer that the
41220 * command's response data will be written. This can be either a host
41221 * physical address (HPA) or a guest physical address (GPA) and must
41222 * point to a physically contiguous block of memory.
41224 uint64_t resp_addr;
41225 /* Control flags. */
41227 /* Counter PBL indirect levels. */
41228 uint8_t page_level;
41229 /* PBL pointer is physical start address. */
41230 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
41231 /* PBL pointer points to PTE table. */
41232 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
41234 * PBL pointer points to PDE table with each entry pointing
41237 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
41238 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
41239 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
41242 /* 4KB page size. */
41243 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
41244 /* 8KB page size. */
41245 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
41246 /* 64KB page size. */
41247 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
41248 /* 128KB page size. */
41249 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
41250 /* 256KB page size. */
41251 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
41252 /* 512KB page size. */
41253 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
41254 /* 1MB page size. */
41255 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
41256 /* 2MB page size. */
41257 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
41258 /* 4MB page size. */
41259 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
41260 /* 8MB page size. */
41261 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
41262 /* 1GB page size. */
41263 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
41264 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
41265 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
41268 /* Pointer to the PBL, or PDL depending on number of levels */
41272 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
41273 struct hwrm_tf_ctxt_mem_rgtr_output {
41274 /* The specific error status for the command. */
41275 uint16_t error_code;
41276 /* The HWRM command request type. */
41278 /* The sequence ID from the original command. */
41280 /* The length of the response data in number of bytes. */
41283 * Id/Handle to the recently register context memory. This
41284 * handle is passed to the TF session.
41288 uint8_t unused0[5];
41290 * This field is used in Output records to indicate that the
41291 * output is completely written to RAM. This field should be
41292 * read as '1' to indicate that the output has been
41293 * completely written. When writing a command completion or
41294 * response to an internal processor, the order of writes has
41295 * to be such that this field is written last.
41300 /***************************
41301 * hwrm_tf_ctxt_mem_unrgtr *
41302 ***************************/
41305 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
41306 struct hwrm_tf_ctxt_mem_unrgtr_input {
41307 /* The HWRM command request type. */
41310 * The completion ring to send the completion event on. This should
41311 * be the NQ ID returned from the `nq_alloc` HWRM command.
41313 uint16_t cmpl_ring;
41315 * The sequence ID is used by the driver for tracking multiple
41316 * commands. This ID is treated as opaque data by the firmware and
41317 * the value is returned in the `hwrm_resp_hdr` upon completion.
41321 * The target ID of the command:
41322 * * 0x0-0xFFF8 - The function ID
41323 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41324 * * 0xFFFD - Reserved for user-space HWRM interface
41327 uint16_t target_id;
41329 * A physical address pointer pointing to a host buffer that the
41330 * command's response data will be written. This can be either a host
41331 * physical address (HPA) or a guest physical address (GPA) and must
41332 * point to a physically contiguous block of memory.
41334 uint64_t resp_addr;
41336 * Id/Handle to the recently register context memory. This
41337 * handle is passed to the TF session.
41341 uint8_t unused0[6];
41344 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
41345 struct hwrm_tf_ctxt_mem_unrgtr_output {
41346 /* The specific error status for the command. */
41347 uint16_t error_code;
41348 /* The HWRM command request type. */
41350 /* The sequence ID from the original command. */
41352 /* The length of the response data in number of bytes. */
41355 uint8_t unused0[7];
41357 * This field is used in Output records to indicate that the
41358 * output is completely written to RAM. This field should be
41359 * read as '1' to indicate that the output has been
41360 * completely written. When writing a command completion or
41361 * response to an internal processor, the order of writes has
41362 * to be such that this field is written last.
41367 /************************
41368 * hwrm_tf_ext_em_qcaps *
41369 ************************/
41372 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
41373 struct hwrm_tf_ext_em_qcaps_input {
41374 /* The HWRM command request type. */
41377 * The completion ring to send the completion event on. This should
41378 * be the NQ ID returned from the `nq_alloc` HWRM command.
41380 uint16_t cmpl_ring;
41382 * The sequence ID is used by the driver for tracking multiple
41383 * commands. This ID is treated as opaque data by the firmware and
41384 * the value is returned in the `hwrm_resp_hdr` upon completion.
41388 * The target ID of the command:
41389 * * 0x0-0xFFF8 - The function ID
41390 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41391 * * 0xFFFD - Reserved for user-space HWRM interface
41394 uint16_t target_id;
41396 * A physical address pointer pointing to a host buffer that the
41397 * command's response data will be written. This can be either a host
41398 * physical address (HPA) or a guest physical address (GPA) and must
41399 * point to a physically contiguous block of memory.
41401 uint64_t resp_addr;
41402 /* Control flags. */
41404 /* Indicates the flow direction. */
41405 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
41407 /* If this bit set to 0, then it indicates rx flow. */
41408 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
41410 /* If this bit is set to 1, then it indicates that tx flow. */
41411 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
41413 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
41414 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
41415 /* When set to 1, all offloaded flows will be sent to EXT EM. */
41416 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
41422 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
41423 struct hwrm_tf_ext_em_qcaps_output {
41424 /* The specific error status for the command. */
41425 uint16_t error_code;
41426 /* The HWRM command request type. */
41428 /* The sequence ID from the original command. */
41430 /* The length of the response data in number of bytes. */
41434 * When set to 1, indicates the FW supports the Centralized
41435 * Memory Model. The concept designates one entity for the
41436 * memory allocation while all others ‘subscribe’ to it.
41438 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41441 * When set to 1, indicates the FW supports the Detached
41442 * Centralized Memory Model. The memory is allocated and managed
41443 * as a separate entity. All PFs and VFs will be granted direct
41444 * or semi-direct access to the allocated memory while none of
41445 * which can interfere with the management of the memory.
41447 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41449 /* When set to 1, indicates FW support for host based EEM memory. */
41450 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
41452 /* When set to 1, indicates FW support for on-chip based EEM memory. */
41453 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
41457 /* Support flags. */
41458 uint32_t supported;
41460 * If set to 1, then EXT EM KEY0 table is supported using
41462 * If set to 0, EXT EM KEY0 table is not supported.
41464 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
41467 * If set to 1, then EXT EM KEY1 table is supported using
41469 * If set to 0, EXT EM KEY1 table is not supported.
41471 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
41474 * If set to 1, then EXT EM External Record table is supported.
41475 * If set to 0, EXT EM External Record table is not
41476 * supported. (This table includes action record, EFC
41477 * pointers, encap pointers)
41479 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
41482 * If set to 1, then EXT EM External Flow Counters table is
41484 * If set to 0, EXT EM External Flow Counters table is not
41487 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
41490 * If set to 1, then FID table used for implicit flow flush
41492 * If set to 0, then FID table used for implicit flow flush
41493 * is not supported.
41495 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
41498 * If set to 1, then table scopes are supported.
41499 * If set to 0, then table scopes are not supported.
41501 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
41504 * The maximum number of entries supported by EXT EM. When
41505 * configuring the host memory the number of numbers of
41506 * entries that can supported are -
41507 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
41509 * Any value that are not these values, the FW will round
41510 * down to the closest support number of entries.
41512 uint32_t max_entries_supported;
41514 * The entry size in bytes of each entry in the EXT EM
41515 * KEY0/KEY1 tables.
41517 uint16_t key_entry_size;
41519 * The entry size in bytes of each entry in the EXT EM RECORD
41522 uint16_t record_entry_size;
41523 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
41524 uint16_t efc_entry_size;
41525 /* The FID size in bytes of each entry in the EXT EM FID tables. */
41526 uint16_t fid_entry_size;
41527 /* Maximum number of ctxt mem allocations allowed. */
41528 uint32_t max_ctxt_mem_allocs;
41530 * Maximum number of static buckets that can be assigned to lookup
41533 uint32_t max_static_buckets;
41535 * Maximum number of all (static and dynamic) buckets that can
41536 * be assigned to lookup table scopes.
41538 uint32_t max_total_buckets;
41540 uint8_t unused1[3];
41542 * This field is used in Output records to indicate that the
41543 * output is completely written to RAM. This field should be
41544 * read as '1' to indicate that the output has been
41545 * completely written. When writing a command completion or
41546 * response to an internal processor, the order of writes has
41547 * to be such that this field is written last.
41552 /*********************
41553 * hwrm_tf_ext_em_op *
41554 *********************/
41557 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
41558 struct hwrm_tf_ext_em_op_input {
41559 /* The HWRM command request type. */
41562 * The completion ring to send the completion event on. This should
41563 * be the NQ ID returned from the `nq_alloc` HWRM command.
41565 uint16_t cmpl_ring;
41567 * The sequence ID is used by the driver for tracking multiple
41568 * commands. This ID is treated as opaque data by the firmware and
41569 * the value is returned in the `hwrm_resp_hdr` upon completion.
41573 * The target ID of the command:
41574 * * 0x0-0xFFF8 - The function ID
41575 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41576 * * 0xFFFD - Reserved for user-space HWRM interface
41579 uint16_t target_id;
41581 * A physical address pointer pointing to a host buffer that the
41582 * command's response data will be written. This can be either a host
41583 * physical address (HPA) or a guest physical address (GPA) and must
41584 * point to a physically contiguous block of memory.
41586 uint64_t resp_addr;
41587 /* Control flags. */
41589 /* Indicates the flow direction. */
41590 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
41591 /* If this bit set to 0, then it indicates rx flow. */
41592 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
41593 /* If this bit is set to 1, then it indicates that tx flow. */
41594 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
41595 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
41596 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
41599 /* The number of EXT EM key table entries to be configured. */
41601 /* This value is reserved and should not be used. */
41602 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
41604 * To properly stop EXT EM and ensure there are no DMA's,
41605 * the caller must disable EXT EM for the given PF, using
41606 * this call. This will safely disable EXT EM and ensure
41607 * that all DMA'ed to the keys/records/efc have been
41610 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
41612 * Once the EXT EM host memory has been configured, EXT EM
41613 * options have been configured. Then the caller should
41614 * enable EXT EM for the given PF. Note once this call has
41615 * been made, then the EXT EM mechanism will be active and
41616 * DMA's will occur as packets are processed.
41618 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
41620 * Clear EXT EM settings for the given PF so that the
41621 * register values are reset back to their initial state.
41623 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
41624 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
41625 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
41630 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
41631 struct hwrm_tf_ext_em_op_output {
41632 /* The specific error status for the command. */
41633 uint16_t error_code;
41634 /* The HWRM command request type. */
41636 /* The sequence ID from the original command. */
41638 /* The length of the response data in number of bytes. */
41641 uint8_t unused0[7];
41643 * This field is used in Output records to indicate that the
41644 * output is completely written to RAM. This field should be
41645 * read as '1' to indicate that the output has been
41646 * completely written. When writing a command completion or
41647 * response to an internal processor, the order of writes has
41648 * to be such that this field is written last.
41653 /**********************
41654 * hwrm_tf_ext_em_cfg *
41655 **********************/
41658 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
41659 struct hwrm_tf_ext_em_cfg_input {
41660 /* The HWRM command request type. */
41663 * The completion ring to send the completion event on. This should
41664 * be the NQ ID returned from the `nq_alloc` HWRM command.
41666 uint16_t cmpl_ring;
41668 * The sequence ID is used by the driver for tracking multiple
41669 * commands. This ID is treated as opaque data by the firmware and
41670 * the value is returned in the `hwrm_resp_hdr` upon completion.
41674 * The target ID of the command:
41675 * * 0x0-0xFFF8 - The function ID
41676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41677 * * 0xFFFD - Reserved for user-space HWRM interface
41680 uint16_t target_id;
41682 * A physical address pointer pointing to a host buffer that the
41683 * command's response data will be written. This can be either a host
41684 * physical address (HPA) or a guest physical address (GPA) and must
41685 * point to a physically contiguous block of memory.
41687 uint64_t resp_addr;
41688 /* Control flags. */
41690 /* Indicates the flow direction. */
41691 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
41693 /* If this bit set to 0, then it indicates rx flow. */
41694 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
41696 /* If this bit is set to 1, then it indicates that tx flow. */
41697 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
41699 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
41700 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
41701 /* When set to 1, all offloaded flows will be sent to EXT EM. */
41702 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
41704 /* When set to 1, secondary, 0 means primary. */
41705 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
41708 * Group_id which used by Firmware to identify memory pools belonging
41709 * to certain group.
41713 * Dynamically reconfigure EEM pending cache every 1/10th of second.
41714 * If set to 0 it will disable the EEM HW flush of the pending cache.
41716 uint8_t flush_interval;
41720 * Configured EXT EM with the given number of entries. All
41721 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
41722 * same number of entries and all tables will be configured
41723 * using this value. Current minimum value is 32k. Current
41724 * maximum value is 128M.
41726 uint32_t num_entries;
41729 * This bit must be '1' for the group_id field to be
41732 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
41735 * This bit must be '1' for the flush_interval field to be
41738 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
41741 * This bit must be '1' for the num_entries field to be
41744 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
41747 * This bit must be '1' for the key0_ctx_id field to be
41750 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
41753 * This bit must be '1' for the key1_ctx_id field to be
41756 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
41759 * This bit must be '1' for the record_ctx_id field to be
41762 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
41765 * This bit must be '1' for the efc_ctx_id field to be
41768 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
41771 * This bit must be '1' for the fid_ctx_id field to be
41774 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
41777 * This bit must be '1' for the action_ctx_id field to be
41780 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
41783 * This bit must be '1' for the action_tbl_scope field to be
41786 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
41789 * This bit must be '1' for the lkup_ctx_id field to be
41792 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
41795 * This bit must be '1' for the lkup_tbl_scope field to be
41798 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
41801 * This bit must be '1' for the lkup_static_buckets field to be
41804 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
41807 * This bit must be '1' for the lkup_dynamic_buckets field to be
41810 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_DYNAMIC_BUCKETS \
41812 /* Configured EXT EM with the given context if for KEY0 table. */
41813 uint16_t key0_ctx_id;
41814 /* Configured EXT EM with the given context if for KEY1 table. */
41815 uint16_t key1_ctx_id;
41816 /* Configured EXT EM with the given context if for RECORD table. */
41817 uint16_t record_ctx_id;
41818 /* Configured EXT EM with the given context if for EFC table. */
41819 uint16_t efc_ctx_id;
41820 /* Configured EXT EM with the given context if for EFC table. */
41821 uint16_t fid_ctx_id;
41822 /* Context id of action table scope. */
41823 uint16_t action_ctx_id;
41824 /* Table scope id used for action record entries. */
41825 uint16_t action_tbl_scope;
41826 /* Context id of lookup table scope. */
41827 uint16_t lkup_ctx_id;
41828 /* Table scope id used for EM lookup entries. */
41829 uint16_t lkup_tbl_scope;
41833 * Number of 32B static buckets to be allocated at the beginning
41836 uint32_t lkup_static_buckets;
41837 /* Number of 32B dynamic buckets to be allocated. */
41838 uint32_t lkup_dynamic_buckets;
41843 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
41844 struct hwrm_tf_ext_em_cfg_output {
41845 /* The specific error status for the command. */
41846 uint16_t error_code;
41847 /* The HWRM command request type. */
41849 /* The sequence ID from the original command. */
41851 /* The length of the response data in number of bytes. */
41854 uint8_t unused0[7];
41856 * This field is used in Output records to indicate that the
41857 * output is completely written to RAM. This field should be
41858 * read as '1' to indicate that the output has been
41859 * completely written. When writing a command completion or
41860 * response to an internal processor, the order of writes has
41861 * to be such that this field is written last.
41866 /***********************
41867 * hwrm_tf_ext_em_qcfg *
41868 ***********************/
41871 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
41872 struct hwrm_tf_ext_em_qcfg_input {
41873 /* The HWRM command request type. */
41876 * The completion ring to send the completion event on. This should
41877 * be the NQ ID returned from the `nq_alloc` HWRM command.
41879 uint16_t cmpl_ring;
41881 * The sequence ID is used by the driver for tracking multiple
41882 * commands. This ID is treated as opaque data by the firmware and
41883 * the value is returned in the `hwrm_resp_hdr` upon completion.
41887 * The target ID of the command:
41888 * * 0x0-0xFFF8 - The function ID
41889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41890 * * 0xFFFD - Reserved for user-space HWRM interface
41893 uint16_t target_id;
41895 * A physical address pointer pointing to a host buffer that the
41896 * command's response data will be written. This can be either a host
41897 * physical address (HPA) or a guest physical address (GPA) and must
41898 * point to a physically contiguous block of memory.
41900 uint64_t resp_addr;
41901 /* Control flags. */
41903 /* Indicates the flow direction. */
41904 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
41905 /* If this bit set to 0, then it indicates rx flow. */
41906 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
41907 /* If this bit is set to 1, then it indicates that tx flow. */
41908 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
41909 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
41910 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
41915 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
41916 struct hwrm_tf_ext_em_qcfg_output {
41917 /* The specific error status for the command. */
41918 uint16_t error_code;
41919 /* The HWRM command request type. */
41921 /* The sequence ID from the original command. */
41923 /* The length of the response data in number of bytes. */
41925 /* Control flags. */
41927 /* Indicates the flow direction. */
41928 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
41930 /* If this bit set to 0, then it indicates rx flow. */
41931 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
41933 /* If this bit is set to 1, then it indicates that tx flow. */
41934 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
41936 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
41937 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
41938 /* When set to 1, all offloaded flows will be sent to EXT EM. */
41939 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
41941 /* The number of entries the FW has configured for EXT EM. */
41942 uint32_t num_entries;
41943 /* Configured EXT EM with the given context if for KEY0 table. */
41944 uint16_t key0_ctx_id;
41945 /* Configured EXT EM with the given context if for KEY1 table. */
41946 uint16_t key1_ctx_id;
41947 /* Configured EXT EM with the given context if for RECORD table. */
41948 uint16_t record_ctx_id;
41949 /* Configured EXT EM with the given context if for EFC table. */
41950 uint16_t efc_ctx_id;
41951 /* Configured EXT EM with the given context if for EFC table. */
41952 uint16_t fid_ctx_id;
41955 uint32_t supported;
41956 /* This bit must be '1' for the group_id field is set. */
41957 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
41959 /* This bit must be '1' for the flush_interval field is set. */
41960 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
41962 /* This bit must be '1' for the num_entries field is set. */
41963 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
41965 /* This bit must be '1' for the key0_ctx_id field is set. */
41966 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
41968 /* This bit must be '1' for the key1_ctx_id field is set. */
41969 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
41971 /* This bit must be '1' for the record_ctx_id field is set. */
41972 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
41974 /* This bit must be '1' for the efc_ctx_id field is set. */
41975 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
41977 /* This bit must be '1' for the fid_ctx_id field is set. */
41978 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
41980 /* This bit must be '1' for the action_ctx_id field is set. */
41981 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
41983 /* This bit must be '1' for the action_tbl_scope field is set. */
41984 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
41986 /* This bit must be '1' for the lkup_ctx_id field is set. */
41987 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
41989 /* This bit must be '1' for the lkup_tbl_scope field is set. */
41990 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
41992 /* This bit must be '1' for the lkup_static_buckets field is set. */
41993 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
41995 /* This bit must be '1' for the lkup_dynamic_buckets field is set. */
41996 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_DYNAMIC_BUCKETS \
41999 * Group id is used by firmware to identify memory pools belonging
42000 * to certain group.
42003 /* EEM pending cache flush interval in 1/10th of second. */
42004 uint8_t flush_interval;
42007 /* Context id of action table scope. */
42008 uint16_t action_ctx_id;
42009 /* Table scope id used for action record entries. */
42010 uint16_t action_tbl_scope;
42011 /* Context id of lookup table scope. */
42012 uint16_t lkup_ctx_id;
42013 /* Table scope id used for EM lookup entries. */
42014 uint16_t lkup_tbl_scope;
42016 * Number of 32B static buckets to be allocated at the beginning
42019 uint32_t lkup_static_buckets;
42020 /* Number of 32B dynamic buckets to be allocated. */
42021 uint32_t lkup_dynamic_buckets;
42023 uint8_t unused2[3];
42025 * This field is used in Output records to indicate that the
42026 * output is completely written to RAM. This field should be
42027 * read as '1' to indicate that the output has been
42028 * completely written. When writing a command completion or
42029 * response to an internal processor, the order of writes has
42030 * to be such that this field is written last.
42035 /*********************
42036 * hwrm_tf_em_insert *
42037 *********************/
42040 /* hwrm_tf_em_insert_input (size:832b/104B) */
42041 struct hwrm_tf_em_insert_input {
42042 /* The HWRM command request type. */
42045 * The completion ring to send the completion event on. This should
42046 * be the NQ ID returned from the `nq_alloc` HWRM command.
42048 uint16_t cmpl_ring;
42050 * The sequence ID is used by the driver for tracking multiple
42051 * commands. This ID is treated as opaque data by the firmware and
42052 * the value is returned in the `hwrm_resp_hdr` upon completion.
42056 * The target ID of the command:
42057 * * 0x0-0xFFF8 - The function ID
42058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42059 * * 0xFFFD - Reserved for user-space HWRM interface
42062 uint16_t target_id;
42064 * A physical address pointer pointing to a host buffer that the
42065 * command's response data will be written. This can be either a host
42066 * physical address (HPA) or a guest physical address (GPA) and must
42067 * point to a physically contiguous block of memory.
42069 uint64_t resp_addr;
42070 /* Firmware Session Id. */
42071 uint32_t fw_session_id;
42072 /* Control Flags. */
42074 /* Indicates the flow direction. */
42075 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
42076 /* If this bit set to 0, then it indicates rx flow. */
42077 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42078 /* If this bit is set to 1, then it indicates that tx flow. */
42079 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42080 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
42081 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
42082 /* Reported match strength. */
42084 /* Index to action. */
42085 uint32_t action_ptr;
42086 /* Index of EM record. */
42087 uint32_t em_record_idx;
42088 /* EM Key value. */
42089 uint64_t em_key[8];
42090 /* Number of bits in em_key. */
42091 uint16_t em_key_bitlen;
42093 uint16_t unused0[3];
42096 /* hwrm_tf_em_insert_output (size:128b/16B) */
42097 struct hwrm_tf_em_insert_output {
42098 /* The specific error status for the command. */
42099 uint16_t error_code;
42100 /* The HWRM command request type. */
42102 /* The sequence ID from the original command. */
42104 /* The length of the response data in number of bytes. */
42106 /* EM record pointer index. */
42107 uint16_t rptr_index;
42108 /* EM record offset 0~3. */
42109 uint8_t rptr_entry;
42110 /* Number of word entries consumed by the key. */
42111 uint8_t num_of_entries;
42116 /*********************
42117 * hwrm_tf_em_delete *
42118 *********************/
42121 /* hwrm_tf_em_delete_input (size:832b/104B) */
42122 struct hwrm_tf_em_delete_input {
42123 /* The HWRM command request type. */
42126 * The completion ring to send the completion event on. This should
42127 * be the NQ ID returned from the `nq_alloc` HWRM command.
42129 uint16_t cmpl_ring;
42131 * The sequence ID is used by the driver for tracking multiple
42132 * commands. This ID is treated as opaque data by the firmware and
42133 * the value is returned in the `hwrm_resp_hdr` upon completion.
42137 * The target ID of the command:
42138 * * 0x0-0xFFF8 - The function ID
42139 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42140 * * 0xFFFD - Reserved for user-space HWRM interface
42143 uint16_t target_id;
42145 * A physical address pointer pointing to a host buffer that the
42146 * command's response data will be written. This can be either a host
42147 * physical address (HPA) or a guest physical address (GPA) and must
42148 * point to a physically contiguous block of memory.
42150 uint64_t resp_addr;
42152 uint32_t fw_session_id;
42153 /* Control flags. */
42155 /* Indicates the flow direction. */
42156 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
42157 /* If this bit set to 0, then it indicates rx flow. */
42158 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42159 /* If this bit is set to 1, then it indicates that tx flow. */
42160 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42161 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
42162 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
42165 /* EM internal flow hanndle. */
42166 uint64_t flow_handle;
42168 uint64_t em_key[8];
42169 /* Number of bits in em_key. */
42170 uint16_t em_key_bitlen;
42172 uint16_t unused1[3];
42175 /* hwrm_tf_em_delete_output (size:128b/16B) */
42176 struct hwrm_tf_em_delete_output {
42177 /* The specific error status for the command. */
42178 uint16_t error_code;
42179 /* The HWRM command request type. */
42181 /* The sequence ID from the original command. */
42183 /* The length of the response data in number of bytes. */
42185 /* Original stack allocation index. */
42188 uint16_t unused0[3];
42191 /********************
42192 * hwrm_tf_tcam_set *
42193 ********************/
42196 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
42197 struct hwrm_tf_tcam_set_input {
42198 /* The HWRM command request type. */
42201 * The completion ring to send the completion event on. This should
42202 * be the NQ ID returned from the `nq_alloc` HWRM command.
42204 uint16_t cmpl_ring;
42206 * The sequence ID is used by the driver for tracking multiple
42207 * commands. This ID is treated as opaque data by the firmware and
42208 * the value is returned in the `hwrm_resp_hdr` upon completion.
42212 * The target ID of the command:
42213 * * 0x0-0xFFF8 - The function ID
42214 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42215 * * 0xFFFD - Reserved for user-space HWRM interface
42218 uint16_t target_id;
42220 * A physical address pointer pointing to a host buffer that the
42221 * command's response data will be written. This can be either a host
42222 * physical address (HPA) or a guest physical address (GPA) and must
42223 * point to a physically contiguous block of memory.
42225 uint64_t resp_addr;
42226 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42227 uint32_t fw_session_id;
42228 /* Control flags. */
42230 /* Indicates the flow direction. */
42231 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
42232 /* If this bit set to 0, then it indicates rx flow. */
42233 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42234 /* If this bit is set to 1, then it indicates that tx flow. */
42235 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42236 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
42237 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
42239 * Indicate device data is being sent via DMA, the device
42240 * data is packing does not change.
42242 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
42244 * TCAM type of the resource, defined globally in the
42245 * hwrm_tf_resc_type enum.
42248 /* Index of TCAM entry. */
42250 /* Number of bytes in the TCAM key. */
42252 /* Number of bytes in the TCAM result. */
42253 uint8_t result_size;
42255 * Offset from which the mask bytes start in the device data
42256 * array, key offset is always 0.
42258 uint8_t mask_offset;
42259 /* Offset from which the result bytes start in the device data array. */
42260 uint8_t result_offset;
42262 uint8_t unused0[6];
42264 * TCAM key located at offset 0, mask located at mask_offsec
42265 * and result at result_offsec for the device.
42267 uint8_t dev_data[88];
42270 /* hwrm_tf_tcam_set_output (size:128b/16B) */
42271 struct hwrm_tf_tcam_set_output {
42272 /* The specific error status for the command. */
42273 uint16_t error_code;
42274 /* The HWRM command request type. */
42276 /* The sequence ID from the original command. */
42278 /* The length of the response data in number of bytes. */
42281 uint8_t unused0[7];
42283 * This field is used in Output records to indicate that the
42284 * output is completely written to RAM. This field should be
42285 * read as '1' to indicate that the output has been
42286 * completely written. When writing a command completion or
42287 * response to an internal processor, the order of writes has
42288 * to be such that this field is written last.
42293 /********************
42294 * hwrm_tf_tcam_get *
42295 ********************/
42298 /* hwrm_tf_tcam_get_input (size:256b/32B) */
42299 struct hwrm_tf_tcam_get_input {
42300 /* The HWRM command request type. */
42303 * The completion ring to send the completion event on. This should
42304 * be the NQ ID returned from the `nq_alloc` HWRM command.
42306 uint16_t cmpl_ring;
42308 * The sequence ID is used by the driver for tracking multiple
42309 * commands. This ID is treated as opaque data by the firmware and
42310 * the value is returned in the `hwrm_resp_hdr` upon completion.
42314 * The target ID of the command:
42315 * * 0x0-0xFFF8 - The function ID
42316 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42317 * * 0xFFFD - Reserved for user-space HWRM interface
42320 uint16_t target_id;
42322 * A physical address pointer pointing to a host buffer that the
42323 * command's response data will be written. This can be either a host
42324 * physical address (HPA) or a guest physical address (GPA) and must
42325 * point to a physically contiguous block of memory.
42327 uint64_t resp_addr;
42328 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42329 uint32_t fw_session_id;
42330 /* Control flags. */
42332 /* Indicates the flow direction. */
42333 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
42334 /* If this bit set to 0, then it indicates rx flow. */
42335 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42336 /* If this bit is set to 1, then it indicates that tx flow. */
42337 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42338 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
42339 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
42341 * TCAM type of the resource, defined globally in the
42342 * hwrm_tf_resc_type enum.
42345 /* Index of a TCAM entry. */
42351 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
42352 struct hwrm_tf_tcam_get_output {
42353 /* The specific error status for the command. */
42354 uint16_t error_code;
42355 /* The HWRM command request type. */
42357 /* The sequence ID from the original command. */
42359 /* The length of the response data in number of bytes. */
42361 /* Number of bytes in the TCAM key. */
42363 /* Number of bytes in the TCAM entry. */
42364 uint8_t result_size;
42365 /* Offset from which the mask bytes start in the device data array. */
42366 uint8_t mask_offset;
42367 /* Offset from which the result bytes start in the device data array. */
42368 uint8_t result_offset;
42370 uint8_t unused0[4];
42372 * TCAM key located at offset 0, mask located at mask_offsec
42373 * and result at result_offsec for the device.
42375 uint8_t dev_data[272];
42377 uint8_t unused1[7];
42379 * This field is used in Output records to indicate that the
42380 * output is completely written to RAM. This field should be
42381 * read as '1' to indicate that the output has been
42382 * completely written. When writing a command completion or
42383 * response to an internal processor, the order of writes has
42384 * to be such that this field is written last.
42389 /*********************
42390 * hwrm_tf_tcam_move *
42391 *********************/
42394 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
42395 struct hwrm_tf_tcam_move_input {
42396 /* The HWRM command request type. */
42399 * The completion ring to send the completion event on. This should
42400 * be the NQ ID returned from the `nq_alloc` HWRM command.
42402 uint16_t cmpl_ring;
42404 * The sequence ID is used by the driver for tracking multiple
42405 * commands. This ID is treated as opaque data by the firmware and
42406 * the value is returned in the `hwrm_resp_hdr` upon completion.
42410 * The target ID of the command:
42411 * * 0x0-0xFFF8 - The function ID
42412 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42413 * * 0xFFFD - Reserved for user-space HWRM interface
42416 uint16_t target_id;
42418 * A physical address pointer pointing to a host buffer that the
42419 * command's response data will be written. This can be either a host
42420 * physical address (HPA) or a guest physical address (GPA) and must
42421 * point to a physically contiguous block of memory.
42423 uint64_t resp_addr;
42424 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42425 uint32_t fw_session_id;
42426 /* Control flags. */
42428 /* Indicates the flow direction. */
42429 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
42430 /* If this bit set to 0, then it indicates rx flow. */
42431 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42432 /* If this bit is set to 1, then it indicates that tx flow. */
42433 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42434 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
42435 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
42437 * TCAM type of the resource, defined globally in the
42438 * hwrm_tf_resc_type enum.
42441 /* Number of TCAM index pairs to be swapped for the device. */
42445 /* TCAM index pairs to be swapped for the device. */
42446 uint16_t idx_pairs[48];
42449 /* hwrm_tf_tcam_move_output (size:128b/16B) */
42450 struct hwrm_tf_tcam_move_output {
42451 /* The specific error status for the command. */
42452 uint16_t error_code;
42453 /* The HWRM command request type. */
42455 /* The sequence ID from the original command. */
42457 /* The length of the response data in number of bytes. */
42460 uint8_t unused0[7];
42462 * This field is used in Output records to indicate that the
42463 * output is completely written to RAM. This field should be
42464 * read as '1' to indicate that the output has been
42465 * completely written. When writing a command completion or
42466 * response to an internal processor, the order of writes has
42467 * to be such that this field is written last.
42472 /*********************
42473 * hwrm_tf_tcam_free *
42474 *********************/
42477 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
42478 struct hwrm_tf_tcam_free_input {
42479 /* The HWRM command request type. */
42482 * The completion ring to send the completion event on. This should
42483 * be the NQ ID returned from the `nq_alloc` HWRM command.
42485 uint16_t cmpl_ring;
42487 * The sequence ID is used by the driver for tracking multiple
42488 * commands. This ID is treated as opaque data by the firmware and
42489 * the value is returned in the `hwrm_resp_hdr` upon completion.
42493 * The target ID of the command:
42494 * * 0x0-0xFFF8 - The function ID
42495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42496 * * 0xFFFD - Reserved for user-space HWRM interface
42499 uint16_t target_id;
42501 * A physical address pointer pointing to a host buffer that the
42502 * command's response data will be written. This can be either a host
42503 * physical address (HPA) or a guest physical address (GPA) and must
42504 * point to a physically contiguous block of memory.
42506 uint64_t resp_addr;
42507 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42508 uint32_t fw_session_id;
42509 /* Control flags. */
42511 /* Indicates the flow direction. */
42512 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
42513 /* If this bit set to 0, then it indicates rx flow. */
42514 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42515 /* If this bit is set to 1, then it indicates that tx flow. */
42516 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42517 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
42518 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
42520 * TCAM type of the resource, defined globally in the
42521 * hwrm_tf_resc_type enum.
42524 /* Number of TCAM index to be deleted for the device. */
42528 /* TCAM index list to be deleted for the device. */
42529 uint16_t idx_list[48];
42532 /* hwrm_tf_tcam_free_output (size:128b/16B) */
42533 struct hwrm_tf_tcam_free_output {
42534 /* The specific error status for the command. */
42535 uint16_t error_code;
42536 /* The HWRM command request type. */
42538 /* The sequence ID from the original command. */
42540 /* The length of the response data in number of bytes. */
42543 uint8_t unused0[7];
42545 * This field is used in Output records to indicate that the
42546 * output is completely written to RAM. This field should be
42547 * read as '1' to indicate that the output has been
42548 * completely written. When writing a command completion or
42549 * response to an internal processor, the order of writes has
42550 * to be such that this field is written last.
42555 /**************************
42556 * hwrm_tf_global_cfg_set *
42557 **************************/
42560 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
42561 struct hwrm_tf_global_cfg_set_input {
42562 /* The HWRM command request type. */
42565 * The completion ring to send the completion event on. This should
42566 * be the NQ ID returned from the `nq_alloc` HWRM command.
42568 uint16_t cmpl_ring;
42570 * The sequence ID is used by the driver for tracking multiple
42571 * commands. This ID is treated as opaque data by the firmware and
42572 * the value is returned in the `hwrm_resp_hdr` upon completion.
42576 * The target ID of the command:
42577 * * 0x0-0xFFF8 - The function ID
42578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42579 * * 0xFFFD - Reserved for user-space HWRM interface
42582 uint16_t target_id;
42584 * A physical address pointer pointing to a host buffer that the
42585 * command's response data will be written. This can be either a host
42586 * physical address (HPA) or a guest physical address (GPA) and must
42587 * point to a physically contiguous block of memory.
42589 uint64_t resp_addr;
42590 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42591 uint32_t fw_session_id;
42592 /* Control flags. */
42594 /* Indicates the flow direction. */
42595 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
42596 /* If this bit set to 0, then it indicates rx flow. */
42597 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42598 /* If this bit is set to 1, then it indicates that tx flow. */
42599 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42600 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
42601 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
42602 /* Global Cfg type */
42604 /* Offset of the type */
42606 /* Size of the data to set in bytes */
42609 uint8_t unused0[6];
42612 /* Mask of data to set, 0 indicates no mask */
42616 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
42617 struct hwrm_tf_global_cfg_set_output {
42618 /* The specific error status for the command. */
42619 uint16_t error_code;
42620 /* The HWRM command request type. */
42622 /* The sequence ID from the original command. */
42624 /* The length of the response data in number of bytes. */
42627 uint8_t unused0[7];
42629 * This field is used in Output records to indicate that the
42630 * output is completely written to RAM. This field should be
42631 * read as '1' to indicate that the output has been
42632 * completely written. When writing a command completion or
42633 * response to an internal processor, the order of writes has
42634 * to be such that this field is written last.
42639 /**************************
42640 * hwrm_tf_global_cfg_get *
42641 **************************/
42644 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
42645 struct hwrm_tf_global_cfg_get_input {
42646 /* The HWRM command request type. */
42649 * The completion ring to send the completion event on. This should
42650 * be the NQ ID returned from the `nq_alloc` HWRM command.
42652 uint16_t cmpl_ring;
42654 * The sequence ID is used by the driver for tracking multiple
42655 * commands. This ID is treated as opaque data by the firmware and
42656 * the value is returned in the `hwrm_resp_hdr` upon completion.
42660 * The target ID of the command:
42661 * * 0x0-0xFFF8 - The function ID
42662 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42663 * * 0xFFFD - Reserved for user-space HWRM interface
42666 uint16_t target_id;
42668 * A physical address pointer pointing to a host buffer that the
42669 * command's response data will be written. This can be either a host
42670 * physical address (HPA) or a guest physical address (GPA) and must
42671 * point to a physically contiguous block of memory.
42673 uint64_t resp_addr;
42674 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42675 uint32_t fw_session_id;
42676 /* Control flags. */
42678 /* Indicates the flow direction. */
42679 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
42680 /* If this bit set to 0, then it indicates rx flow. */
42681 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42682 /* If this bit is set to 1, then it indicates that tx flow. */
42683 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42684 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
42685 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
42686 /* Global Cfg type */
42688 /* Offset of the type */
42690 /* Size of the data to set in bytes */
42693 uint8_t unused0[6];
42696 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
42697 struct hwrm_tf_global_cfg_get_output {
42698 /* The specific error status for the command. */
42699 uint16_t error_code;
42700 /* The HWRM command request type. */
42702 /* The sequence ID from the original command. */
42704 /* The length of the response data in number of bytes. */
42706 /* Size of the data read in bytes */
42709 uint8_t unused0[6];
42714 /**********************
42715 * hwrm_tf_if_tbl_get *
42716 **********************/
42719 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
42720 struct hwrm_tf_if_tbl_get_input {
42721 /* The HWRM command request type. */
42724 * The completion ring to send the completion event on. This should
42725 * be the NQ ID returned from the `nq_alloc` HWRM command.
42727 uint16_t cmpl_ring;
42729 * The sequence ID is used by the driver for tracking multiple
42730 * commands. This ID is treated as opaque data by the firmware and
42731 * the value is returned in the `hwrm_resp_hdr` upon completion.
42735 * The target ID of the command:
42736 * * 0x0-0xFFF8 - The function ID
42737 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42738 * * 0xFFFD - Reserved for user-space HWRM interface
42741 uint16_t target_id;
42743 * A physical address pointer pointing to a host buffer that the
42744 * command's response data will be written. This can be either a host
42745 * physical address (HPA) or a guest physical address (GPA) and must
42746 * point to a physically contiguous block of memory.
42748 uint64_t resp_addr;
42749 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42750 uint32_t fw_session_id;
42751 /* Control flags. */
42753 /* Indicates the flow direction. */
42754 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
42755 /* If this bit set to 0, then it indicates rx flow. */
42756 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42757 /* If this bit is set to 1, then it indicates that tx flow. */
42758 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42759 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
42760 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
42761 /* Size of the data to set. */
42764 * Type of the resource, defined globally in the
42765 * hwrm_tf_resc_type enum.
42768 /* Index of the type to retrieve. */
42772 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
42773 struct hwrm_tf_if_tbl_get_output {
42774 /* The specific error status for the command. */
42775 uint16_t error_code;
42776 /* The HWRM command request type. */
42778 /* The sequence ID from the original command. */
42780 /* The length of the response data in number of bytes. */
42782 /* Response code. */
42783 uint32_t resp_code;
42784 /* Response size. */
42788 /* Response data. */
42791 uint8_t unused1[7];
42793 * This field is used in Output records to indicate that the output
42794 * is completely written to RAM. This field should be read as '1'
42795 * to indicate that the output has been completely written.
42796 * When writing a command completion or response to an internal
42797 * processor, the order of writes has to be such that this field
42803 /***************************
42804 * hwrm_tf_if_tbl_type_set *
42805 ***************************/
42808 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
42809 struct hwrm_tf_if_tbl_set_input {
42810 /* The HWRM command request type. */
42813 * The completion ring to send the completion event on. This should
42814 * be the NQ ID returned from the `nq_alloc` HWRM command.
42816 uint16_t cmpl_ring;
42818 * The sequence ID is used by the driver for tracking multiple
42819 * commands. This ID is treated as opaque data by the firmware and
42820 * the value is returned in the `hwrm_resp_hdr` upon completion.
42824 * The target ID of the command:
42825 * * 0x0-0xFFF8 - The function ID
42826 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42827 * * 0xFFFD - Reserved for user-space HWRM interface
42830 uint16_t target_id;
42832 * A physical address pointer pointing to a host buffer that the
42833 * command's response data will be written. This can be either a host
42834 * physical address (HPA) or a guest physical address (GPA) and must
42835 * point to a physically contiguous block of memory.
42837 uint64_t resp_addr;
42838 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42839 uint32_t fw_session_id;
42840 /* Control flags. */
42842 /* Indicates the flow direction. */
42843 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
42844 /* If this bit set to 0, then it indicates rx flow. */
42845 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42846 /* If this bit is set to 1, then it indicates that tx flow. */
42847 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42848 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
42849 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
42851 uint8_t unused0[2];
42853 * Type of the resource, defined globally in the
42854 * hwrm_tf_resc_type enum.
42857 /* Index of the type to set. */
42859 /* Size of the data to set. */
42862 uint8_t unused1[6];
42863 /* Data to be set. */
42867 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
42868 struct hwrm_tf_if_tbl_set_output {
42869 /* The specific error status for the command. */
42870 uint16_t error_code;
42871 /* The HWRM command request type. */
42873 /* The sequence ID from the original command. */
42875 /* The length of the response data in number of bytes. */
42878 uint8_t unused0[7];
42880 * This field is used in Output records to indicate that the output
42881 * is completely written to RAM. This field should be read as '1'
42882 * to indicate that the output has been completely written.
42883 * When writing a command completion or response to an internal
42884 * processor, the order of writes has to be such that this field
42890 /*****************************
42891 * hwrm_tf_tbl_type_bulk_get *
42892 *****************************/
42895 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
42896 struct hwrm_tf_tbl_type_bulk_get_input {
42897 /* The HWRM command request type. */
42900 * The completion ring to send the completion event on. This should
42901 * be the NQ ID returned from the `nq_alloc` HWRM command.
42903 uint16_t cmpl_ring;
42905 * The sequence ID is used by the driver for tracking multiple
42906 * commands. This ID is treated as opaque data by the firmware and
42907 * the value is returned in the `hwrm_resp_hdr` upon completion.
42911 * The target ID of the command:
42912 * * 0x0-0xFFF8 - The function ID
42913 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42914 * * 0xFFFD - Reserved for user-space HWRM interface
42917 uint16_t target_id;
42919 * A physical address pointer pointing to a host buffer that the
42920 * command's response data will be written. This can be either a host
42921 * physical address (HPA) or a guest physical address (GPA) and must
42922 * point to a physically contiguous block of memory.
42924 uint64_t resp_addr;
42925 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42926 uint32_t fw_session_id;
42927 /* Control flags. */
42929 /* Indicates the flow direction. */
42930 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
42931 /* If this bit set to 0, then it indicates rx flow. */
42932 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42933 /* If this bit is set to 1, then it indicates that tx flow. */
42934 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42935 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
42936 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
42938 uint8_t unused0[2];
42940 * Type of the resource, defined globally in the
42941 * hwrm_tf_resc_type enum.
42944 /* Starting index of the type to retrieve. */
42945 uint32_t start_index;
42946 /* Number of entries to retrieve. */
42947 uint32_t num_entries;
42948 /* Number of entries to retrieve. */
42950 /* Host memory where data will be stored. */
42951 uint64_t host_addr;
42954 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
42955 struct hwrm_tf_tbl_type_bulk_get_output {
42956 /* The specific error status for the command. */
42957 uint16_t error_code;
42958 /* The HWRM command request type. */
42960 /* The sequence ID from the original command. */
42962 /* The length of the response data in number of bytes. */
42964 /* Response code. */
42965 uint32_t resp_code;
42966 /* Response size. */
42971 * This field is used in Output records to indicate that the output
42972 * is completely written to RAM. This field should be read as '1'
42973 * to indicate that the output has been completely written.
42974 * When writing a command completion or response to an internal
42975 * processor, the order of writes has to be such that this field
42981 /******************************
42982 * hwrm_tunnel_dst_port_query *
42983 ******************************/
42986 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
42987 struct hwrm_tunnel_dst_port_query_input {
42988 /* The HWRM command request type. */
42991 * The completion ring to send the completion event on. This should
42992 * be the NQ ID returned from the `nq_alloc` HWRM command.
42994 uint16_t cmpl_ring;
42996 * The sequence ID is used by the driver for tracking multiple
42997 * commands. This ID is treated as opaque data by the firmware and
42998 * the value is returned in the `hwrm_resp_hdr` upon completion.
43002 * The target ID of the command:
43003 * * 0x0-0xFFF8 - The function ID
43004 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43005 * * 0xFFFD - Reserved for user-space HWRM interface
43008 uint16_t target_id;
43010 * A physical address pointer pointing to a host buffer that the
43011 * command's response data will be written. This can be either a host
43012 * physical address (HPA) or a guest physical address (GPA) and must
43013 * point to a physically contiguous block of memory.
43015 uint64_t resp_addr;
43017 uint8_t tunnel_type;
43018 /* Virtual eXtensible Local Area Network (VXLAN) */
43019 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
43021 /* Generic Network Virtualization Encapsulation (Geneve) */
43022 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
43024 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
43025 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
43027 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
43028 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
43030 /* Use fixed layer 2 ether type of 0xFFFF */
43031 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
43033 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
43034 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
43036 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
43037 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
43038 uint8_t unused_0[7];
43041 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
43042 struct hwrm_tunnel_dst_port_query_output {
43043 /* The specific error status for the command. */
43044 uint16_t error_code;
43045 /* The HWRM command request type. */
43047 /* The sequence ID from the original command. */
43049 /* The length of the response data in number of bytes. */
43052 * This field represents the identifier of L4 destination port
43053 * used for the given tunnel type. This field is valid for
43054 * specific tunnel types that use layer 4 (e.g. UDP)
43055 * transports for tunneling.
43057 uint16_t tunnel_dst_port_id;
43059 * This field represents the value of L4 destination port
43060 * identified by tunnel_dst_port_id. This field is valid for
43061 * specific tunnel types that use layer 4 (e.g. UDP)
43062 * transports for tunneling.
43063 * This field is in network byte order.
43065 * A value of 0 means that the destination port is not
43068 uint16_t tunnel_dst_port_val;
43069 uint8_t unused_0[3];
43071 * This field is used in Output records to indicate that the output
43072 * is completely written to RAM. This field should be read as '1'
43073 * to indicate that the output has been completely written.
43074 * When writing a command completion or response to an internal processor,
43075 * the order of writes has to be such that this field is written last.
43080 /******************************
43081 * hwrm_tunnel_dst_port_alloc *
43082 ******************************/
43085 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
43086 struct hwrm_tunnel_dst_port_alloc_input {
43087 /* The HWRM command request type. */
43090 * The completion ring to send the completion event on. This should
43091 * be the NQ ID returned from the `nq_alloc` HWRM command.
43093 uint16_t cmpl_ring;
43095 * The sequence ID is used by the driver for tracking multiple
43096 * commands. This ID is treated as opaque data by the firmware and
43097 * the value is returned in the `hwrm_resp_hdr` upon completion.
43101 * The target ID of the command:
43102 * * 0x0-0xFFF8 - The function ID
43103 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43104 * * 0xFFFD - Reserved for user-space HWRM interface
43107 uint16_t target_id;
43109 * A physical address pointer pointing to a host buffer that the
43110 * command's response data will be written. This can be either a host
43111 * physical address (HPA) or a guest physical address (GPA) and must
43112 * point to a physically contiguous block of memory.
43114 uint64_t resp_addr;
43116 uint8_t tunnel_type;
43117 /* Virtual eXtensible Local Area Network (VXLAN) */
43118 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
43120 /* Generic Network Virtualization Encapsulation (Geneve) */
43121 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
43123 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
43124 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
43126 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
43127 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
43129 /* Use fixed layer 2 ether type of 0xFFFF */
43130 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
43132 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
43133 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
43135 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
43136 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
43139 * This field represents the value of L4 destination port used
43140 * for the given tunnel type. This field is valid for
43141 * specific tunnel types that use layer 4 (e.g. UDP)
43142 * transports for tunneling.
43144 * This field is in network byte order.
43146 * A value of 0 shall fail the command.
43148 uint16_t tunnel_dst_port_val;
43149 uint8_t unused_1[4];
43152 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
43153 struct hwrm_tunnel_dst_port_alloc_output {
43154 /* The specific error status for the command. */
43155 uint16_t error_code;
43156 /* The HWRM command request type. */
43158 /* The sequence ID from the original command. */
43160 /* The length of the response data in number of bytes. */
43163 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
43164 * types that has l4 destination port parameters.
43166 uint16_t tunnel_dst_port_id;
43167 uint8_t unused_0[5];
43169 * This field is used in Output records to indicate that the output
43170 * is completely written to RAM. This field should be read as '1'
43171 * to indicate that the output has been completely written.
43172 * When writing a command completion or response to an internal processor,
43173 * the order of writes has to be such that this field is written last.
43178 /*****************************
43179 * hwrm_tunnel_dst_port_free *
43180 *****************************/
43183 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
43184 struct hwrm_tunnel_dst_port_free_input {
43185 /* The HWRM command request type. */
43188 * The completion ring to send the completion event on. This should
43189 * be the NQ ID returned from the `nq_alloc` HWRM command.
43191 uint16_t cmpl_ring;
43193 * The sequence ID is used by the driver for tracking multiple
43194 * commands. This ID is treated as opaque data by the firmware and
43195 * the value is returned in the `hwrm_resp_hdr` upon completion.
43199 * The target ID of the command:
43200 * * 0x0-0xFFF8 - The function ID
43201 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43202 * * 0xFFFD - Reserved for user-space HWRM interface
43205 uint16_t target_id;
43207 * A physical address pointer pointing to a host buffer that the
43208 * command's response data will be written. This can be either a host
43209 * physical address (HPA) or a guest physical address (GPA) and must
43210 * point to a physically contiguous block of memory.
43212 uint64_t resp_addr;
43214 uint8_t tunnel_type;
43215 /* Virtual eXtensible Local Area Network (VXLAN) */
43216 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
43218 /* Generic Network Virtualization Encapsulation (Geneve) */
43219 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
43221 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
43222 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
43224 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
43225 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
43227 /* Use fixed layer 2 ether type of 0xFFFF */
43228 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
43230 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
43231 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
43233 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
43234 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
43237 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
43238 * types that has l4 destination port parameters.
43240 uint16_t tunnel_dst_port_id;
43241 uint8_t unused_1[4];
43244 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
43245 struct hwrm_tunnel_dst_port_free_output {
43246 /* The specific error status for the command. */
43247 uint16_t error_code;
43248 /* The HWRM command request type. */
43250 /* The sequence ID from the original command. */
43252 /* The length of the response data in number of bytes. */
43254 uint8_t unused_1[7];
43256 * This field is used in Output records to indicate that the output
43257 * is completely written to RAM. This field should be read as '1'
43258 * to indicate that the output has been completely written.
43259 * When writing a command completion or response to an internal processor,
43260 * the order of writes has to be such that this field is written last.
43265 /* Periodic statistics context DMA to host. */
43266 /* ctx_hw_stats (size:1280b/160B) */
43267 struct ctx_hw_stats {
43268 /* Number of received unicast packets */
43269 uint64_t rx_ucast_pkts;
43270 /* Number of received multicast packets */
43271 uint64_t rx_mcast_pkts;
43272 /* Number of received broadcast packets */
43273 uint64_t rx_bcast_pkts;
43274 /* Number of discarded packets on receive path */
43275 uint64_t rx_discard_pkts;
43276 /* Number of packets on receive path with error */
43277 uint64_t rx_error_pkts;
43278 /* Number of received bytes for unicast traffic */
43279 uint64_t rx_ucast_bytes;
43280 /* Number of received bytes for multicast traffic */
43281 uint64_t rx_mcast_bytes;
43282 /* Number of received bytes for broadcast traffic */
43283 uint64_t rx_bcast_bytes;
43284 /* Number of transmitted unicast packets */
43285 uint64_t tx_ucast_pkts;
43286 /* Number of transmitted multicast packets */
43287 uint64_t tx_mcast_pkts;
43288 /* Number of transmitted broadcast packets */
43289 uint64_t tx_bcast_pkts;
43290 /* Number of packets on transmit path with error */
43291 uint64_t tx_error_pkts;
43292 /* Number of discarded packets on transmit path */
43293 uint64_t tx_discard_pkts;
43294 /* Number of transmitted bytes for unicast traffic */
43295 uint64_t tx_ucast_bytes;
43296 /* Number of transmitted bytes for multicast traffic */
43297 uint64_t tx_mcast_bytes;
43298 /* Number of transmitted bytes for broadcast traffic */
43299 uint64_t tx_bcast_bytes;
43300 /* Number of TPA packets */
43302 /* Number of TPA bytes */
43303 uint64_t tpa_bytes;
43304 /* Number of TPA events */
43305 uint64_t tpa_events;
43306 /* Number of TPA aborts */
43307 uint64_t tpa_aborts;
43311 * Extended periodic statistics context DMA to host. On cards that
43312 * support TPA v2, additional TPA related stats exist and can be retrieved
43313 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
43315 /* ctx_hw_stats_ext (size:1408b/176B) */
43316 struct ctx_hw_stats_ext {
43317 /* Number of received unicast packets */
43318 uint64_t rx_ucast_pkts;
43319 /* Number of received multicast packets */
43320 uint64_t rx_mcast_pkts;
43321 /* Number of received broadcast packets */
43322 uint64_t rx_bcast_pkts;
43323 /* Number of discarded packets on receive path */
43324 uint64_t rx_discard_pkts;
43325 /* Number of packets on receive path with error */
43326 uint64_t rx_error_pkts;
43327 /* Number of received bytes for unicast traffic */
43328 uint64_t rx_ucast_bytes;
43329 /* Number of received bytes for multicast traffic */
43330 uint64_t rx_mcast_bytes;
43331 /* Number of received bytes for broadcast traffic */
43332 uint64_t rx_bcast_bytes;
43333 /* Number of transmitted unicast packets */
43334 uint64_t tx_ucast_pkts;
43335 /* Number of transmitted multicast packets */
43336 uint64_t tx_mcast_pkts;
43337 /* Number of transmitted broadcast packets */
43338 uint64_t tx_bcast_pkts;
43339 /* Number of packets on transmit path with error */
43340 uint64_t tx_error_pkts;
43341 /* Number of discarded packets on transmit path */
43342 uint64_t tx_discard_pkts;
43343 /* Number of transmitted bytes for unicast traffic */
43344 uint64_t tx_ucast_bytes;
43345 /* Number of transmitted bytes for multicast traffic */
43346 uint64_t tx_mcast_bytes;
43347 /* Number of transmitted bytes for broadcast traffic */
43348 uint64_t tx_bcast_bytes;
43349 /* Number of TPA eligible packets */
43350 uint64_t rx_tpa_eligible_pkt;
43351 /* Number of TPA eligible bytes */
43352 uint64_t rx_tpa_eligible_bytes;
43353 /* Number of TPA packets */
43354 uint64_t rx_tpa_pkt;
43355 /* Number of TPA bytes */
43356 uint64_t rx_tpa_bytes;
43357 /* Number of TPA errors */
43358 uint64_t rx_tpa_errors;
43359 /* Number of TPA events */
43360 uint64_t rx_tpa_events;
43363 /* Periodic Engine statistics context DMA to host. */
43364 /* ctx_eng_stats (size:512b/64B) */
43365 struct ctx_eng_stats {
43367 * Count of data bytes into the Engine.
43368 * This includes any user supplied prefix,
43369 * but does not include any predefined
43372 uint64_t eng_bytes_in;
43373 /* Count of data bytes out of the Engine. */
43374 uint64_t eng_bytes_out;
43376 * Count, in 4-byte (dword) units, of bytes
43377 * that are input as auxiliary data.
43378 * This includes the aux_cmd data.
43380 uint64_t aux_bytes_in;
43382 * Count, in 4-byte (dword) units, of bytes
43383 * that are output as auxiliary data.
43384 * This count is the buffer space for aux_data
43385 * output provided in the RQE, not the actual
43388 uint64_t aux_bytes_out;
43389 /* Count of number of commands executed. */
43392 * Count of number of error commands.
43393 * These are the commands with a
43394 * non-zero status value.
43396 uint64_t error_commands;
43398 * Compression/Encryption Engine usage,
43399 * the unit is count of clock cycles
43401 uint64_t cce_engine_usage;
43403 * De-Compression/De-cryption Engine usage,
43404 * the unit is count of clock cycles
43406 uint64_t cdd_engine_usage;
43409 /***********************
43410 * hwrm_stat_ctx_alloc *
43411 ***********************/
43414 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
43415 struct hwrm_stat_ctx_alloc_input {
43416 /* The HWRM command request type. */
43419 * The completion ring to send the completion event on. This should
43420 * be the NQ ID returned from the `nq_alloc` HWRM command.
43422 uint16_t cmpl_ring;
43424 * The sequence ID is used by the driver for tracking multiple
43425 * commands. This ID is treated as opaque data by the firmware and
43426 * the value is returned in the `hwrm_resp_hdr` upon completion.
43430 * The target ID of the command:
43431 * * 0x0-0xFFF8 - The function ID
43432 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43433 * * 0xFFFD - Reserved for user-space HWRM interface
43436 uint16_t target_id;
43438 * A physical address pointer pointing to a host buffer that the
43439 * command's response data will be written. This can be either a host
43440 * physical address (HPA) or a guest physical address (GPA) and must
43441 * point to a physically contiguous block of memory.
43443 uint64_t resp_addr;
43445 * This is the address for statistic block.
43446 * > For new versions of the chip, this address should be 128B
43449 uint64_t stats_dma_addr;
43451 * The statistic block update period in ms.
43452 * e.g. 250ms, 500ms, 750ms, 1000ms.
43453 * If update_period_ms is 0, then the stats update
43454 * shall be never done and the DMA address shall not be used.
43455 * In this case, the stat block can only be read by
43456 * hwrm_stat_ctx_query command.
43457 * On Ethernet/L2 based devices:
43458 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
43459 * ctx_hw_stats_ext is used for DMA,
43461 * ctx_hw_stats is used for DMA.
43463 uint32_t update_period_ms;
43465 * This field is used to specify statistics context specific
43466 * configuration flags.
43468 uint8_t stat_ctx_flags;
43470 * When this bit is set to '1', the statistics context shall be
43471 * allocated for RoCE traffic only. In this case, traffic other
43472 * than offloaded RoCE traffic shall not be included in this
43473 * statistic context.
43474 * When this bit is set to '0', the statistics context shall be
43475 * used for network traffic or engine traffic.
43477 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
43480 * This is the size of the structure (ctx_hw_stats or
43481 * ctx_hw_stats_ext) that the driver has allocated to be used
43482 * for the periodic DMA updates.
43484 uint16_t stats_dma_length;
43487 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
43488 struct hwrm_stat_ctx_alloc_output {
43489 /* The specific error status for the command. */
43490 uint16_t error_code;
43491 /* The HWRM command request type. */
43493 /* The sequence ID from the original command. */
43495 /* The length of the response data in number of bytes. */
43497 /* This is the statistics context ID value. */
43498 uint32_t stat_ctx_id;
43499 uint8_t unused_0[3];
43501 * This field is used in Output records to indicate that the output
43502 * is completely written to RAM. This field should be read as '1'
43503 * to indicate that the output has been completely written.
43504 * When writing a command completion or response to an internal processor,
43505 * the order of writes has to be such that this field is written last.
43510 /**********************
43511 * hwrm_stat_ctx_free *
43512 **********************/
43515 /* hwrm_stat_ctx_free_input (size:192b/24B) */
43516 struct hwrm_stat_ctx_free_input {
43517 /* The HWRM command request type. */
43520 * The completion ring to send the completion event on. This should
43521 * be the NQ ID returned from the `nq_alloc` HWRM command.
43523 uint16_t cmpl_ring;
43525 * The sequence ID is used by the driver for tracking multiple
43526 * commands. This ID is treated as opaque data by the firmware and
43527 * the value is returned in the `hwrm_resp_hdr` upon completion.
43531 * The target ID of the command:
43532 * * 0x0-0xFFF8 - The function ID
43533 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43534 * * 0xFFFD - Reserved for user-space HWRM interface
43537 uint16_t target_id;
43539 * A physical address pointer pointing to a host buffer that the
43540 * command's response data will be written. This can be either a host
43541 * physical address (HPA) or a guest physical address (GPA) and must
43542 * point to a physically contiguous block of memory.
43544 uint64_t resp_addr;
43545 /* ID of the statistics context that is being queried. */
43546 uint32_t stat_ctx_id;
43547 uint8_t unused_0[4];
43550 /* hwrm_stat_ctx_free_output (size:128b/16B) */
43551 struct hwrm_stat_ctx_free_output {
43552 /* The specific error status for the command. */
43553 uint16_t error_code;
43554 /* The HWRM command request type. */
43556 /* The sequence ID from the original command. */
43558 /* The length of the response data in number of bytes. */
43560 /* This is the statistics context ID value. */
43561 uint32_t stat_ctx_id;
43562 uint8_t unused_0[3];
43564 * This field is used in Output records to indicate that the output
43565 * is completely written to RAM. This field should be read as '1'
43566 * to indicate that the output has been completely written.
43567 * When writing a command completion or response to an internal processor,
43568 * the order of writes has to be such that this field is written last.
43573 /***********************
43574 * hwrm_stat_ctx_query *
43575 ***********************/
43578 /* hwrm_stat_ctx_query_input (size:192b/24B) */
43579 struct hwrm_stat_ctx_query_input {
43580 /* The HWRM command request type. */
43583 * The completion ring to send the completion event on. This should
43584 * be the NQ ID returned from the `nq_alloc` HWRM command.
43586 uint16_t cmpl_ring;
43588 * The sequence ID is used by the driver for tracking multiple
43589 * commands. This ID is treated as opaque data by the firmware and
43590 * the value is returned in the `hwrm_resp_hdr` upon completion.
43594 * The target ID of the command:
43595 * * 0x0-0xFFF8 - The function ID
43596 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43597 * * 0xFFFD - Reserved for user-space HWRM interface
43600 uint16_t target_id;
43602 * A physical address pointer pointing to a host buffer that the
43603 * command's response data will be written. This can be either a host
43604 * physical address (HPA) or a guest physical address (GPA) and must
43605 * point to a physically contiguous block of memory.
43607 uint64_t resp_addr;
43608 /* ID of the statistics context that is being queried. */
43609 uint32_t stat_ctx_id;
43612 * This bit is set to 1 when request is for a counter mask,
43613 * representing the width of each of the stats counters, rather
43614 * than counters themselves.
43616 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
43617 uint8_t unused_0[3];
43620 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
43621 struct hwrm_stat_ctx_query_output {
43622 /* The specific error status for the command. */
43623 uint16_t error_code;
43624 /* The HWRM command request type. */
43626 /* The sequence ID from the original command. */
43628 /* The length of the response data in number of bytes. */
43630 /* Number of transmitted unicast packets */
43631 uint64_t tx_ucast_pkts;
43632 /* Number of transmitted multicast packets */
43633 uint64_t tx_mcast_pkts;
43634 /* Number of transmitted broadcast packets */
43635 uint64_t tx_bcast_pkts;
43636 /* Number of packets discarded in transmit path */
43637 uint64_t tx_discard_pkts;
43638 /* Number of packets in transmit path with error */
43639 uint64_t tx_error_pkts;
43640 /* Number of transmitted bytes for unicast traffic */
43641 uint64_t tx_ucast_bytes;
43642 /* Number of transmitted bytes for multicast traffic */
43643 uint64_t tx_mcast_bytes;
43644 /* Number of transmitted bytes for broadcast traffic */
43645 uint64_t tx_bcast_bytes;
43646 /* Number of received unicast packets */
43647 uint64_t rx_ucast_pkts;
43648 /* Number of received multicast packets */
43649 uint64_t rx_mcast_pkts;
43650 /* Number of received broadcast packets */
43651 uint64_t rx_bcast_pkts;
43652 /* Number of packets discarded in receive path */
43653 uint64_t rx_discard_pkts;
43654 /* Number of packets in receive path with errors */
43655 uint64_t rx_error_pkts;
43656 /* Number of received bytes for unicast traffic */
43657 uint64_t rx_ucast_bytes;
43658 /* Number of received bytes for multicast traffic */
43659 uint64_t rx_mcast_bytes;
43660 /* Number of received bytes for broadcast traffic */
43661 uint64_t rx_bcast_bytes;
43662 /* Number of aggregated unicast packets */
43663 uint64_t rx_agg_pkts;
43664 /* Number of aggregated unicast bytes */
43665 uint64_t rx_agg_bytes;
43666 /* Number of aggregation events */
43667 uint64_t rx_agg_events;
43668 /* Number of aborted aggregations */
43669 uint64_t rx_agg_aborts;
43670 uint8_t unused_0[7];
43672 * This field is used in Output records to indicate that the output
43673 * is completely written to RAM. This field should be read as '1'
43674 * to indicate that the output has been completely written.
43675 * When writing a command completion or response to an internal processor,
43676 * the order of writes has to be such that this field is written last.
43681 /***************************
43682 * hwrm_stat_ext_ctx_query *
43683 ***************************/
43686 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
43687 struct hwrm_stat_ext_ctx_query_input {
43688 /* The HWRM command request type. */
43691 * The completion ring to send the completion event on. This should
43692 * be the NQ ID returned from the `nq_alloc` HWRM command.
43694 uint16_t cmpl_ring;
43696 * The sequence ID is used by the driver for tracking multiple
43697 * commands. This ID is treated as opaque data by the firmware and
43698 * the value is returned in the `hwrm_resp_hdr` upon completion.
43702 * The target ID of the command:
43703 * * 0x0-0xFFF8 - The function ID
43704 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43705 * * 0xFFFD - Reserved for user-space HWRM interface
43708 uint16_t target_id;
43710 * A physical address pointer pointing to a host buffer that the
43711 * command's response data will be written. This can be either a host
43712 * physical address (HPA) or a guest physical address (GPA) and must
43713 * point to a physically contiguous block of memory.
43715 uint64_t resp_addr;
43716 /* ID of the extended statistics context that is being queried. */
43717 uint32_t stat_ctx_id;
43720 * This bit is set to 1 when request is for a counter mask,
43721 * representing the width of each of the stats counters, rather
43722 * than counters themselves.
43724 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
43726 uint8_t unused_0[3];
43729 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
43730 struct hwrm_stat_ext_ctx_query_output {
43731 /* The specific error status for the command. */
43732 uint16_t error_code;
43733 /* The HWRM command request type. */
43735 /* The sequence ID from the original command. */
43737 /* The length of the response data in number of bytes. */
43739 /* Number of received unicast packets */
43740 uint64_t rx_ucast_pkts;
43741 /* Number of received multicast packets */
43742 uint64_t rx_mcast_pkts;
43743 /* Number of received broadcast packets */
43744 uint64_t rx_bcast_pkts;
43745 /* Number of discarded packets on receive path */
43746 uint64_t rx_discard_pkts;
43747 /* Number of packets on receive path with error */
43748 uint64_t rx_error_pkts;
43749 /* Number of received bytes for unicast traffic */
43750 uint64_t rx_ucast_bytes;
43751 /* Number of received bytes for multicast traffic */
43752 uint64_t rx_mcast_bytes;
43753 /* Number of received bytes for broadcast traffic */
43754 uint64_t rx_bcast_bytes;
43755 /* Number of transmitted unicast packets */
43756 uint64_t tx_ucast_pkts;
43757 /* Number of transmitted multicast packets */
43758 uint64_t tx_mcast_pkts;
43759 /* Number of transmitted broadcast packets */
43760 uint64_t tx_bcast_pkts;
43761 /* Number of packets on transmit path with error */
43762 uint64_t tx_error_pkts;
43763 /* Number of discarded packets on transmit path */
43764 uint64_t tx_discard_pkts;
43765 /* Number of transmitted bytes for unicast traffic */
43766 uint64_t tx_ucast_bytes;
43767 /* Number of transmitted bytes for multicast traffic */
43768 uint64_t tx_mcast_bytes;
43769 /* Number of transmitted bytes for broadcast traffic */
43770 uint64_t tx_bcast_bytes;
43771 /* Number of TPA eligible packets */
43772 uint64_t rx_tpa_eligible_pkt;
43773 /* Number of TPA eligible bytes */
43774 uint64_t rx_tpa_eligible_bytes;
43775 /* Number of TPA packets */
43776 uint64_t rx_tpa_pkt;
43777 /* Number of TPA bytes */
43778 uint64_t rx_tpa_bytes;
43779 /* Number of TPA errors */
43780 uint64_t rx_tpa_errors;
43781 /* Number of TPA events */
43782 uint64_t rx_tpa_events;
43783 uint8_t unused_0[7];
43785 * This field is used in Output records to indicate that the output
43786 * is completely written to RAM. This field should be read as '1'
43787 * to indicate that the output has been completely written.
43788 * When writing a command completion or response to an internal processor,
43789 * the order of writes has to be such that this field is written last.
43794 /***************************
43795 * hwrm_stat_ctx_eng_query *
43796 ***************************/
43799 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
43800 struct hwrm_stat_ctx_eng_query_input {
43801 /* The HWRM command request type. */
43804 * The completion ring to send the completion event on. This should
43805 * be the NQ ID returned from the `nq_alloc` HWRM command.
43807 uint16_t cmpl_ring;
43809 * The sequence ID is used by the driver for tracking multiple
43810 * commands. This ID is treated as opaque data by the firmware and
43811 * the value is returned in the `hwrm_resp_hdr` upon completion.
43815 * The target ID of the command:
43816 * * 0x0-0xFFF8 - The function ID
43817 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43818 * * 0xFFFD - Reserved for user-space HWRM interface
43821 uint16_t target_id;
43823 * A physical address pointer pointing to a host buffer that the
43824 * command's response data will be written. This can be either a host
43825 * physical address (HPA) or a guest physical address (GPA) and must
43826 * point to a physically contiguous block of memory.
43828 uint64_t resp_addr;
43829 /* ID of the statistics context that is being queried. */
43830 uint32_t stat_ctx_id;
43831 uint8_t unused_0[4];
43834 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
43835 struct hwrm_stat_ctx_eng_query_output {
43836 /* The specific error status for the command. */
43837 uint16_t error_code;
43838 /* The HWRM command request type. */
43840 /* The sequence ID from the original command. */
43842 /* The length of the response data in number of bytes. */
43845 * Count of data bytes into the Engine.
43846 * This includes any user supplied prefix,
43847 * but does not include any predefined
43850 uint64_t eng_bytes_in;
43851 /* Count of data bytes out of the Engine. */
43852 uint64_t eng_bytes_out;
43854 * Count, in 4-byte (dword) units, of bytes
43855 * that are input as auxiliary data.
43856 * This includes the aux_cmd data.
43858 uint64_t aux_bytes_in;
43860 * Count, in 4-byte (dword) units, of bytes
43861 * that are output as auxiliary data.
43862 * This count is the buffer space for aux_data
43863 * output provided in the RQE, not the actual
43866 uint64_t aux_bytes_out;
43867 /* Count of number of commands executed. */
43870 * Count of number of error commands.
43871 * These are the commands with a
43872 * non-zero status value.
43874 uint64_t error_commands;
43876 * Compression/Encryption Engine usage,
43877 * the unit is count of clock cycles
43879 uint64_t cce_engine_usage;
43881 * De-Compression/De-cryption Engine usage,
43882 * the unit is count of clock cycles
43884 uint64_t cdd_engine_usage;
43885 uint8_t unused_0[7];
43887 * This field is used in Output records to indicate that the output
43888 * is completely written to RAM. This field should be read as '1'
43889 * to indicate that the output has been completely written.
43890 * When writing a command completion or response to an internal processor,
43891 * the order of writes has to be such that this field is written last.
43896 /***************************
43897 * hwrm_stat_ctx_clr_stats *
43898 ***************************/
43901 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
43902 struct hwrm_stat_ctx_clr_stats_input {
43903 /* The HWRM command request type. */
43906 * The completion ring to send the completion event on. This should
43907 * be the NQ ID returned from the `nq_alloc` HWRM command.
43909 uint16_t cmpl_ring;
43911 * The sequence ID is used by the driver for tracking multiple
43912 * commands. This ID is treated as opaque data by the firmware and
43913 * the value is returned in the `hwrm_resp_hdr` upon completion.
43917 * The target ID of the command:
43918 * * 0x0-0xFFF8 - The function ID
43919 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43920 * * 0xFFFD - Reserved for user-space HWRM interface
43923 uint16_t target_id;
43925 * A physical address pointer pointing to a host buffer that the
43926 * command's response data will be written. This can be either a host
43927 * physical address (HPA) or a guest physical address (GPA) and must
43928 * point to a physically contiguous block of memory.
43930 uint64_t resp_addr;
43931 /* ID of the statistics context that is being queried. */
43932 uint32_t stat_ctx_id;
43933 uint8_t unused_0[4];
43936 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
43937 struct hwrm_stat_ctx_clr_stats_output {
43938 /* The specific error status for the command. */
43939 uint16_t error_code;
43940 /* The HWRM command request type. */
43942 /* The sequence ID from the original command. */
43944 /* The length of the response data in number of bytes. */
43946 uint8_t unused_0[7];
43948 * This field is used in Output records to indicate that the output
43949 * is completely written to RAM. This field should be read as '1'
43950 * to indicate that the output has been completely written.
43951 * When writing a command completion or response to an internal processor,
43952 * the order of writes has to be such that this field is written last.
43957 /********************
43958 * hwrm_pcie_qstats *
43959 ********************/
43962 /* hwrm_pcie_qstats_input (size:256b/32B) */
43963 struct hwrm_pcie_qstats_input {
43964 /* The HWRM command request type. */
43967 * The completion ring to send the completion event on. This should
43968 * be the NQ ID returned from the `nq_alloc` HWRM command.
43970 uint16_t cmpl_ring;
43972 * The sequence ID is used by the driver for tracking multiple
43973 * commands. This ID is treated as opaque data by the firmware and
43974 * the value is returned in the `hwrm_resp_hdr` upon completion.
43978 * The target ID of the command:
43979 * * 0x0-0xFFF8 - The function ID
43980 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43981 * * 0xFFFD - Reserved for user-space HWRM interface
43984 uint16_t target_id;
43986 * A physical address pointer pointing to a host buffer that the
43987 * command's response data will be written. This can be either a host
43988 * physical address (HPA) or a guest physical address (GPA) and must
43989 * point to a physically contiguous block of memory.
43991 uint64_t resp_addr;
43993 * The size of PCIe statistics block in bytes.
43994 * Firmware will DMA the PCIe statistics to
43995 * the host with this field size in the response.
43997 uint16_t pcie_stat_size;
43998 uint8_t unused_0[6];
44000 * This is the host address where
44001 * PCIe statistics will be stored
44003 uint64_t pcie_stat_host_addr;
44006 /* hwrm_pcie_qstats_output (size:128b/16B) */
44007 struct hwrm_pcie_qstats_output {
44008 /* The specific error status for the command. */
44009 uint16_t error_code;
44010 /* The HWRM command request type. */
44012 /* The sequence ID from the original command. */
44014 /* The length of the response data in number of bytes. */
44016 /* The size of PCIe statistics block in bytes. */
44017 uint16_t pcie_stat_size;
44018 uint8_t unused_0[5];
44020 * This field is used in Output records to indicate that the output
44021 * is completely written to RAM. This field should be read as '1'
44022 * to indicate that the output has been completely written.
44023 * When writing a command completion or response to an internal processor,
44024 * the order of writes has to be such that this field is written last.
44029 /* PCIe Statistics Formats */
44030 /* pcie_ctx_hw_stats (size:768b/96B) */
44031 struct pcie_ctx_hw_stats {
44032 /* Number of physical layer receiver errors */
44033 uint64_t pcie_pl_signal_integrity;
44034 /* Number of DLLP CRC errors detected by Data Link Layer */
44035 uint64_t pcie_dl_signal_integrity;
44037 * Number of TLP LCRC and sequence number errors detected
44038 * by Data Link Layer
44040 uint64_t pcie_tl_signal_integrity;
44041 /* Number of times LTSSM entered Recovery state */
44042 uint64_t pcie_link_integrity;
44043 /* Report number of TLP bits that have been transmitted in Mbps */
44044 uint64_t pcie_tx_traffic_rate;
44045 /* Report number of TLP bits that have been received in Mbps */
44046 uint64_t pcie_rx_traffic_rate;
44047 /* Number of DLLP bytes that have been transmitted */
44048 uint64_t pcie_tx_dllp_statistics;
44049 /* Number of DLLP bytes that have been received */
44050 uint64_t pcie_rx_dllp_statistics;
44052 * Number of times spent in each phase of gen3
44055 uint64_t pcie_equalization_time;
44056 /* Records the last 16 transitions of the LTSSM */
44057 uint32_t pcie_ltssm_histogram[4];
44059 * Record the last 8 reasons on why LTSSM transitioned
44062 uint64_t pcie_recovery_histogram;
44065 /**********************
44066 * hwrm_exec_fwd_resp *
44067 **********************/
44070 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
44071 struct hwrm_exec_fwd_resp_input {
44072 /* The HWRM command request type. */
44075 * The completion ring to send the completion event on. This should
44076 * be the NQ ID returned from the `nq_alloc` HWRM command.
44078 uint16_t cmpl_ring;
44080 * The sequence ID is used by the driver for tracking multiple
44081 * commands. This ID is treated as opaque data by the firmware and
44082 * the value is returned in the `hwrm_resp_hdr` upon completion.
44086 * The target ID of the command:
44087 * * 0x0-0xFFF8 - The function ID
44088 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44089 * * 0xFFFD - Reserved for user-space HWRM interface
44092 uint16_t target_id;
44094 * A physical address pointer pointing to a host buffer that the
44095 * command's response data will be written. This can be either a host
44096 * physical address (HPA) or a guest physical address (GPA) and must
44097 * point to a physically contiguous block of memory.
44099 uint64_t resp_addr;
44101 * This is an encapsulated request. This request should
44102 * be executed by the HWRM and the response should be
44103 * provided in the response buffer inside the encapsulated
44106 uint32_t encap_request[26];
44108 * This value indicates the target id of the response to
44109 * the encapsulated request.
44110 * 0x0 - 0xFFF8 - Used for function ids
44111 * 0xFFF8 - 0xFFFE - Reserved for internal processors
44114 uint16_t encap_resp_target_id;
44115 uint8_t unused_0[6];
44118 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
44119 struct hwrm_exec_fwd_resp_output {
44120 /* The specific error status for the command. */
44121 uint16_t error_code;
44122 /* The HWRM command request type. */
44124 /* The sequence ID from the original command. */
44126 /* The length of the response data in number of bytes. */
44128 uint8_t unused_0[7];
44130 * This field is used in Output records to indicate that the output
44131 * is completely written to RAM. This field should be read as '1'
44132 * to indicate that the output has been completely written.
44133 * When writing a command completion or response to an internal processor,
44134 * the order of writes has to be such that this field is written last.
44139 /************************
44140 * hwrm_reject_fwd_resp *
44141 ************************/
44144 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
44145 struct hwrm_reject_fwd_resp_input {
44146 /* The HWRM command request type. */
44149 * The completion ring to send the completion event on. This should
44150 * be the NQ ID returned from the `nq_alloc` HWRM command.
44152 uint16_t cmpl_ring;
44154 * The sequence ID is used by the driver for tracking multiple
44155 * commands. This ID is treated as opaque data by the firmware and
44156 * the value is returned in the `hwrm_resp_hdr` upon completion.
44160 * The target ID of the command:
44161 * * 0x0-0xFFF8 - The function ID
44162 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44163 * * 0xFFFD - Reserved for user-space HWRM interface
44166 uint16_t target_id;
44168 * A physical address pointer pointing to a host buffer that the
44169 * command's response data will be written. This can be either a host
44170 * physical address (HPA) or a guest physical address (GPA) and must
44171 * point to a physically contiguous block of memory.
44173 uint64_t resp_addr;
44175 * This is an encapsulated request. This request should
44176 * be rejected by the HWRM and the error response should be
44177 * provided in the response buffer inside the encapsulated
44180 uint32_t encap_request[26];
44182 * This value indicates the target id of the response to
44183 * the encapsulated request.
44184 * 0x0 - 0xFFF8 - Used for function ids
44185 * 0xFFF8 - 0xFFFE - Reserved for internal processors
44188 uint16_t encap_resp_target_id;
44189 uint8_t unused_0[6];
44192 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
44193 struct hwrm_reject_fwd_resp_output {
44194 /* The specific error status for the command. */
44195 uint16_t error_code;
44196 /* The HWRM command request type. */
44198 /* The sequence ID from the original command. */
44200 /* The length of the response data in number of bytes. */
44202 uint8_t unused_0[7];
44204 * This field is used in Output records to indicate that the output
44205 * is completely written to RAM. This field should be read as '1'
44206 * to indicate that the output has been completely written.
44207 * When writing a command completion or response to an internal processor,
44208 * the order of writes has to be such that this field is written last.
44218 /* hwrm_fwd_resp_input (size:1024b/128B) */
44219 struct hwrm_fwd_resp_input {
44220 /* The HWRM command request type. */
44223 * The completion ring to send the completion event on. This should
44224 * be the NQ ID returned from the `nq_alloc` HWRM command.
44226 uint16_t cmpl_ring;
44228 * The sequence ID is used by the driver for tracking multiple
44229 * commands. This ID is treated as opaque data by the firmware and
44230 * the value is returned in the `hwrm_resp_hdr` upon completion.
44234 * The target ID of the command:
44235 * * 0x0-0xFFF8 - The function ID
44236 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44237 * * 0xFFFD - Reserved for user-space HWRM interface
44240 uint16_t target_id;
44242 * A physical address pointer pointing to a host buffer that the
44243 * command's response data will be written. This can be either a host
44244 * physical address (HPA) or a guest physical address (GPA) and must
44245 * point to a physically contiguous block of memory.
44247 uint64_t resp_addr;
44249 * This value indicates the target id of the encapsulated
44251 * 0x0 - 0xFFF8 - Used for function ids
44252 * 0xFFF8 - 0xFFFE - Reserved for internal processors
44255 uint16_t encap_resp_target_id;
44257 * This value indicates the completion ring the encapsulated
44258 * response will be optionally completed on. If the value is
44259 * -1, then no CR completion shall be generated for the
44260 * encapsulated response. Any other value must be a
44261 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
44262 * is provided, then a CR completion shall be generated for
44263 * the encapsulated response.
44265 uint16_t encap_resp_cmpl_ring;
44266 /* This field indicates the length of encapsulated response. */
44267 uint16_t encap_resp_len;
44271 * This is the host address where the encapsulated response
44273 * This area must be 16B aligned and must be cleared to zero
44274 * before the original request is made.
44276 uint64_t encap_resp_addr;
44277 /* This is an encapsulated response. */
44278 uint32_t encap_resp[24];
44281 /* hwrm_fwd_resp_output (size:128b/16B) */
44282 struct hwrm_fwd_resp_output {
44283 /* The specific error status for the command. */
44284 uint16_t error_code;
44285 /* The HWRM command request type. */
44287 /* The sequence ID from the original command. */
44289 /* The length of the response data in number of bytes. */
44291 uint8_t unused_0[7];
44293 * This field is used in Output records to indicate that the output
44294 * is completely written to RAM. This field should be read as '1'
44295 * to indicate that the output has been completely written.
44296 * When writing a command completion or response to an internal processor,
44297 * the order of writes has to be such that this field is written last.
44302 /*****************************
44303 * hwrm_fwd_async_event_cmpl *
44304 *****************************/
44307 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
44308 struct hwrm_fwd_async_event_cmpl_input {
44309 /* The HWRM command request type. */
44312 * The completion ring to send the completion event on. This should
44313 * be the NQ ID returned from the `nq_alloc` HWRM command.
44315 uint16_t cmpl_ring;
44317 * The sequence ID is used by the driver for tracking multiple
44318 * commands. This ID is treated as opaque data by the firmware and
44319 * the value is returned in the `hwrm_resp_hdr` upon completion.
44323 * The target ID of the command:
44324 * * 0x0-0xFFF8 - The function ID
44325 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44326 * * 0xFFFD - Reserved for user-space HWRM interface
44329 uint16_t target_id;
44331 * A physical address pointer pointing to a host buffer that the
44332 * command's response data will be written. This can be either a host
44333 * physical address (HPA) or a guest physical address (GPA) and must
44334 * point to a physically contiguous block of memory.
44336 uint64_t resp_addr;
44338 * This value indicates the target id of the encapsulated
44339 * asynchronous event.
44340 * 0x0 - 0xFFF8 - Used for function ids
44341 * 0xFFF8 - 0xFFFE - Reserved for internal processors
44342 * 0xFFFF - Broadcast to all children VFs (only applicable when
44343 * a PF is the requester)
44345 uint16_t encap_async_event_target_id;
44346 uint8_t unused_0[6];
44347 /* This is an encapsulated asynchronous event completion. */
44348 uint32_t encap_async_event_cmpl[4];
44351 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
44352 struct hwrm_fwd_async_event_cmpl_output {
44353 /* The specific error status for the command. */
44354 uint16_t error_code;
44355 /* The HWRM command request type. */
44357 /* The sequence ID from the original command. */
44359 /* The length of the response data in number of bytes. */
44361 uint8_t unused_0[7];
44363 * This field is used in Output records to indicate that the output
44364 * is completely written to RAM. This field should be read as '1'
44365 * to indicate that the output has been completely written.
44366 * When writing a command completion or response to an internal processor,
44367 * the order of writes has to be such that this field is written last.
44372 /**************************
44373 * hwrm_nvm_raw_write_blk *
44374 **************************/
44377 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
44378 struct hwrm_nvm_raw_write_blk_input {
44379 /* The HWRM command request type. */
44382 * The completion ring to send the completion event on. This should
44383 * be the NQ ID returned from the `nq_alloc` HWRM command.
44385 uint16_t cmpl_ring;
44387 * The sequence ID is used by the driver for tracking multiple
44388 * commands. This ID is treated as opaque data by the firmware and
44389 * the value is returned in the `hwrm_resp_hdr` upon completion.
44393 * The target ID of the command:
44394 * * 0x0-0xFFF8 - The function ID
44395 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44396 * * 0xFFFD - Reserved for user-space HWRM interface
44399 uint16_t target_id;
44401 * A physical address pointer pointing to a host buffer that the
44402 * command's response data will be written. This can be either a host
44403 * physical address (HPA) or a guest physical address (GPA) and must
44404 * point to a physically contiguous block of memory.
44406 uint64_t resp_addr;
44408 * 64-bit Host Source Address.
44409 * This is the location of the source data to be written.
44411 uint64_t host_src_addr;
44413 * 32-bit Destination Address.
44414 * This is the NVRAM byte-offset where the source data will be written to.
44416 uint32_t dest_addr;
44417 /* Length of data to be written, in bytes. */
44421 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
44422 struct hwrm_nvm_raw_write_blk_output {
44423 /* The specific error status for the command. */
44424 uint16_t error_code;
44425 /* The HWRM command request type. */
44427 /* The sequence ID from the original command. */
44429 /* The length of the response data in number of bytes. */
44431 uint8_t unused_0[7];
44433 * This field is used in Output records to indicate that the output
44434 * is completely written to RAM. This field should be read as '1'
44435 * to indicate that the output has been completely written.
44436 * When writing a command completion or response to an internal processor,
44437 * the order of writes has to be such that this field is written last.
44447 /* hwrm_nvm_read_input (size:320b/40B) */
44448 struct hwrm_nvm_read_input {
44449 /* The HWRM command request type. */
44452 * The completion ring to send the completion event on. This should
44453 * be the NQ ID returned from the `nq_alloc` HWRM command.
44455 uint16_t cmpl_ring;
44457 * The sequence ID is used by the driver for tracking multiple
44458 * commands. This ID is treated as opaque data by the firmware and
44459 * the value is returned in the `hwrm_resp_hdr` upon completion.
44463 * The target ID of the command:
44464 * * 0x0-0xFFF8 - The function ID
44465 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44466 * * 0xFFFD - Reserved for user-space HWRM interface
44469 uint16_t target_id;
44471 * A physical address pointer pointing to a host buffer that the
44472 * command's response data will be written. This can be either a host
44473 * physical address (HPA) or a guest physical address (GPA) and must
44474 * point to a physically contiguous block of memory.
44476 uint64_t resp_addr;
44478 * 64-bit Host Destination Address.
44479 * This is the host address where the data will be written to.
44481 uint64_t host_dest_addr;
44482 /* The 0-based index of the directory entry. */
44484 uint8_t unused_0[2];
44485 /* The NVRAM byte-offset to read from. */
44487 /* The length of the data to be read, in bytes. */
44489 uint8_t unused_1[4];
44492 /* hwrm_nvm_read_output (size:128b/16B) */
44493 struct hwrm_nvm_read_output {
44494 /* The specific error status for the command. */
44495 uint16_t error_code;
44496 /* The HWRM command request type. */
44498 /* The sequence ID from the original command. */
44500 /* The length of the response data in number of bytes. */
44502 uint8_t unused_0[7];
44504 * This field is used in Output records to indicate that the output
44505 * is completely written to RAM. This field should be read as '1'
44506 * to indicate that the output has been completely written.
44507 * When writing a command completion or response to an internal processor,
44508 * the order of writes has to be such that this field is written last.
44513 /*********************
44514 * hwrm_nvm_raw_dump *
44515 *********************/
44518 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
44519 struct hwrm_nvm_raw_dump_input {
44520 /* The HWRM command request type. */
44523 * The completion ring to send the completion event on. This should
44524 * be the NQ ID returned from the `nq_alloc` HWRM command.
44526 uint16_t cmpl_ring;
44528 * The sequence ID is used by the driver for tracking multiple
44529 * commands. This ID is treated as opaque data by the firmware and
44530 * the value is returned in the `hwrm_resp_hdr` upon completion.
44534 * The target ID of the command:
44535 * * 0x0-0xFFF8 - The function ID
44536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44537 * * 0xFFFD - Reserved for user-space HWRM interface
44540 uint16_t target_id;
44542 * A physical address pointer pointing to a host buffer that the
44543 * command's response data will be written. This can be either a host
44544 * physical address (HPA) or a guest physical address (GPA) and must
44545 * point to a physically contiguous block of memory.
44547 uint64_t resp_addr;
44549 * 64-bit Host Destination Address.
44550 * This is the host address where the data will be written to.
44552 uint64_t host_dest_addr;
44553 /* 32-bit NVRAM byte-offset to read from. */
44555 /* Total length of NVRAM contents to be read, in bytes. */
44559 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
44560 struct hwrm_nvm_raw_dump_output {
44561 /* The specific error status for the command. */
44562 uint16_t error_code;
44563 /* The HWRM command request type. */
44565 /* The sequence ID from the original command. */
44567 /* The length of the response data in number of bytes. */
44569 uint8_t unused_0[7];
44571 * This field is used in Output records to indicate that the output
44572 * is completely written to RAM. This field should be read as '1'
44573 * to indicate that the output has been completely written.
44574 * When writing a command completion or response to an internal processor,
44575 * the order of writes has to be such that this field is written last.
44580 /****************************
44581 * hwrm_nvm_get_dir_entries *
44582 ****************************/
44585 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
44586 struct hwrm_nvm_get_dir_entries_input {
44587 /* The HWRM command request type. */
44590 * The completion ring to send the completion event on. This should
44591 * be the NQ ID returned from the `nq_alloc` HWRM command.
44593 uint16_t cmpl_ring;
44595 * The sequence ID is used by the driver for tracking multiple
44596 * commands. This ID is treated as opaque data by the firmware and
44597 * the value is returned in the `hwrm_resp_hdr` upon completion.
44601 * The target ID of the command:
44602 * * 0x0-0xFFF8 - The function ID
44603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44604 * * 0xFFFD - Reserved for user-space HWRM interface
44607 uint16_t target_id;
44609 * A physical address pointer pointing to a host buffer that the
44610 * command's response data will be written. This can be either a host
44611 * physical address (HPA) or a guest physical address (GPA) and must
44612 * point to a physically contiguous block of memory.
44614 uint64_t resp_addr;
44616 * 64-bit Host Destination Address.
44617 * This is the host address where the directory will be written.
44619 uint64_t host_dest_addr;
44622 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
44623 struct hwrm_nvm_get_dir_entries_output {
44624 /* The specific error status for the command. */
44625 uint16_t error_code;
44626 /* The HWRM command request type. */
44628 /* The sequence ID from the original command. */
44630 /* The length of the response data in number of bytes. */
44632 uint8_t unused_0[7];
44634 * This field is used in Output records to indicate that the output
44635 * is completely written to RAM. This field should be read as '1'
44636 * to indicate that the output has been completely written.
44637 * When writing a command completion or response to an internal processor,
44638 * the order of writes has to be such that this field is written last.
44643 /*************************
44644 * hwrm_nvm_get_dir_info *
44645 *************************/
44648 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
44649 struct hwrm_nvm_get_dir_info_input {
44650 /* The HWRM command request type. */
44653 * The completion ring to send the completion event on. This should
44654 * be the NQ ID returned from the `nq_alloc` HWRM command.
44656 uint16_t cmpl_ring;
44658 * The sequence ID is used by the driver for tracking multiple
44659 * commands. This ID is treated as opaque data by the firmware and
44660 * the value is returned in the `hwrm_resp_hdr` upon completion.
44664 * The target ID of the command:
44665 * * 0x0-0xFFF8 - The function ID
44666 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44667 * * 0xFFFD - Reserved for user-space HWRM interface
44670 uint16_t target_id;
44672 * A physical address pointer pointing to a host buffer that the
44673 * command's response data will be written. This can be either a host
44674 * physical address (HPA) or a guest physical address (GPA) and must
44675 * point to a physically contiguous block of memory.
44677 uint64_t resp_addr;
44680 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
44681 struct hwrm_nvm_get_dir_info_output {
44682 /* The specific error status for the command. */
44683 uint16_t error_code;
44684 /* The HWRM command request type. */
44686 /* The sequence ID from the original command. */
44688 /* The length of the response data in number of bytes. */
44690 /* Number of directory entries in the directory. */
44692 /* Size of each directory entry, in bytes. */
44693 uint32_t entry_length;
44694 uint8_t unused_0[7];
44696 * This field is used in Output records to indicate that the output
44697 * is completely written to RAM. This field should be read as '1'
44698 * to indicate that the output has been completely written.
44699 * When writing a command completion or response to an internal processor,
44700 * the order of writes has to be such that this field is written last.
44705 /******************
44707 ******************/
44710 /* hwrm_nvm_write_input (size:384b/48B) */
44711 struct hwrm_nvm_write_input {
44712 /* The HWRM command request type. */
44715 * The completion ring to send the completion event on. This should
44716 * be the NQ ID returned from the `nq_alloc` HWRM command.
44718 uint16_t cmpl_ring;
44720 * The sequence ID is used by the driver for tracking multiple
44721 * commands. This ID is treated as opaque data by the firmware and
44722 * the value is returned in the `hwrm_resp_hdr` upon completion.
44726 * The target ID of the command:
44727 * * 0x0-0xFFF8 - The function ID
44728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44729 * * 0xFFFD - Reserved for user-space HWRM interface
44732 uint16_t target_id;
44734 * A physical address pointer pointing to a host buffer that the
44735 * command's response data will be written. This can be either a host
44736 * physical address (HPA) or a guest physical address (GPA) and must
44737 * point to a physically contiguous block of memory.
44739 uint64_t resp_addr;
44741 * 64-bit Host Source Address.
44742 * This is where the source data is.
44744 uint64_t host_src_addr;
44746 * The Directory Entry Type (valid values are defined in the bnxnvm
44747 * directory_type enum defined in the file bnxnvm_defs.h).
44751 * Directory ordinal.
44752 * The 0-based instance of the combined Directory Entry Type and Extension.
44754 uint16_t dir_ordinal;
44755 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
44757 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
44760 * Length of data to write, in bytes. May be less than or equal to the allocated
44761 * size for the directory entry.
44762 * The data length stored in the directory entry will be updated to reflect
44763 * this value once the write is complete.
44765 uint32_t dir_data_length;
44770 * When this bit is '1', the original active image
44771 * will not be removed. TBD: what purpose is this?
44773 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
44776 * The requested length of the allocated NVM for the item, in bytes. This
44777 * value may be greater than or equal to the specified data length (dir_data_length).
44778 * If this value is less than the specified data length, it will be ignored.
44779 * The response will contain the actual allocated item length, which may be
44780 * greater than the requested item length.
44781 * The purpose for allocating more than the required number of bytes for
44782 * an item's data is to pre-allocate extra storage (padding) to accommodate
44783 * the potential future growth of an item (e.g. upgraded firmware with a
44784 * size increase, log growth, expanded configuration data).
44786 uint32_t dir_item_length;
44790 /* hwrm_nvm_write_output (size:128b/16B) */
44791 struct hwrm_nvm_write_output {
44792 /* The specific error status for the command. */
44793 uint16_t error_code;
44794 /* The HWRM command request type. */
44796 /* The sequence ID from the original command. */
44798 /* The length of the response data in number of bytes. */
44801 * Length of the allocated NVM for the item, in bytes. The value may be
44802 * greater than or equal to the specified data length or the requested
44804 * The actual item length used when creating a new directory entry will be
44805 * a multiple of an NVM block size.
44807 uint32_t dir_item_length;
44808 /* The directory index of the created or modified item. */
44812 * This field is used in Output records to indicate that the output
44813 * is completely written to RAM. This field should be read as '1'
44814 * to indicate that the output has been completely written.
44815 * When writing a command completion or response to an internal processor,
44816 * the order of writes has to be such that this field is written last.
44821 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
44822 struct hwrm_nvm_write_cmd_err {
44824 * command specific error codes that goes to
44825 * the cmd_err field in Common HWRM Error Response.
44828 /* Unknown error */
44829 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
44830 /* Unable to complete operation due to fragmentation */
44831 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
44832 /* nvm is completely full. */
44833 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
44834 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
44835 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
44836 uint8_t unused_0[7];
44839 /*******************
44840 * hwrm_nvm_modify *
44841 *******************/
44844 /* hwrm_nvm_modify_input (size:320b/40B) */
44845 struct hwrm_nvm_modify_input {
44846 /* The HWRM command request type. */
44849 * The completion ring to send the completion event on. This should
44850 * be the NQ ID returned from the `nq_alloc` HWRM command.
44852 uint16_t cmpl_ring;
44854 * The sequence ID is used by the driver for tracking multiple
44855 * commands. This ID is treated as opaque data by the firmware and
44856 * the value is returned in the `hwrm_resp_hdr` upon completion.
44860 * The target ID of the command:
44861 * * 0x0-0xFFF8 - The function ID
44862 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44863 * * 0xFFFD - Reserved for user-space HWRM interface
44866 uint16_t target_id;
44868 * A physical address pointer pointing to a host buffer that the
44869 * command's response data will be written. This can be either a host
44870 * physical address (HPA) or a guest physical address (GPA) and must
44871 * point to a physically contiguous block of memory.
44873 uint64_t resp_addr;
44875 * 64-bit Host Source Address.
44876 * This is where the modified data is.
44878 uint64_t host_src_addr;
44879 /* 16-bit directory entry index. */
44883 * This flag indicates the sender wants to modify a continuous NVRAM
44884 * area using a batch of this HWRM requests. The offset of a request
44885 * must be continuous to the end of previous request's. Firmware does
44886 * not update the directory entry until receiving the last request,
44887 * which is indicated by the batch_last flag.
44888 * This flag is set usually when a sender does not have a block of
44889 * memory that is big enough to hold the entire NVRAM data for send
44892 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
44894 * This flag can be used only when the batch_mode flag is set.
44895 * It indicates this request is the last of batch requests.
44897 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
44898 /* 32-bit NVRAM byte-offset to modify content from. */
44901 * Length of data to be modified, in bytes. The length shall
44905 uint8_t unused_1[4];
44908 /* hwrm_nvm_modify_output (size:128b/16B) */
44909 struct hwrm_nvm_modify_output {
44910 /* The specific error status for the command. */
44911 uint16_t error_code;
44912 /* The HWRM command request type. */
44914 /* The sequence ID from the original command. */
44916 /* The length of the response data in number of bytes. */
44918 uint8_t unused_0[7];
44920 * This field is used in Output records to indicate that the output
44921 * is completely written to RAM. This field should be read as '1'
44922 * to indicate that the output has been completely written.
44923 * When writing a command completion or response to an internal processor,
44924 * the order of writes has to be such that this field is written last.
44929 /***************************
44930 * hwrm_nvm_find_dir_entry *
44931 ***************************/
44934 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
44935 struct hwrm_nvm_find_dir_entry_input {
44936 /* The HWRM command request type. */
44939 * The completion ring to send the completion event on. This should
44940 * be the NQ ID returned from the `nq_alloc` HWRM command.
44942 uint16_t cmpl_ring;
44944 * The sequence ID is used by the driver for tracking multiple
44945 * commands. This ID is treated as opaque data by the firmware and
44946 * the value is returned in the `hwrm_resp_hdr` upon completion.
44950 * The target ID of the command:
44951 * * 0x0-0xFFF8 - The function ID
44952 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44953 * * 0xFFFD - Reserved for user-space HWRM interface
44956 uint16_t target_id;
44958 * A physical address pointer pointing to a host buffer that the
44959 * command's response data will be written. This can be either a host
44960 * physical address (HPA) or a guest physical address (GPA) and must
44961 * point to a physically contiguous block of memory.
44963 uint64_t resp_addr;
44966 * This bit must be '1' for the dir_idx_valid field to be
44969 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
44971 /* Directory Entry Index */
44973 /* Directory Entry (Image) Type */
44976 * Directory ordinal.
44977 * The instance of this Directory Type
44979 uint16_t dir_ordinal;
44980 /* The Directory Entry Extension flags. */
44982 /* This value indicates the search option using dir_ordinal. */
44983 uint8_t opt_ordinal;
44984 /* This value indicates the search option using dir_ordinal. */
44985 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
44986 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
44987 /* Equal to specified ordinal value. */
44988 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
44989 /* Greater than or equal to specified ordinal value */
44990 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
44991 /* Greater than specified ordinal value */
44992 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
44993 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
44994 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
44995 uint8_t unused_0[3];
44998 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
44999 struct hwrm_nvm_find_dir_entry_output {
45000 /* The specific error status for the command. */
45001 uint16_t error_code;
45002 /* The HWRM command request type. */
45004 /* The sequence ID from the original command. */
45006 /* The length of the response data in number of bytes. */
45008 /* Allocated NVRAM for this directory entry, in bytes. */
45009 uint32_t dir_item_length;
45010 /* Size of the stored data for this directory entry, in bytes. */
45011 uint32_t dir_data_length;
45013 * Firmware version.
45014 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
45017 /* Directory ordinal. */
45018 uint16_t dir_ordinal;
45019 /* Directory Entry Index */
45021 uint8_t unused_0[7];
45023 * This field is used in Output records to indicate that the output
45024 * is completely written to RAM. This field should be read as '1'
45025 * to indicate that the output has been completely written.
45026 * When writing a command completion or response to an internal processor,
45027 * the order of writes has to be such that this field is written last.
45032 /****************************
45033 * hwrm_nvm_erase_dir_entry *
45034 ****************************/
45037 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
45038 struct hwrm_nvm_erase_dir_entry_input {
45039 /* The HWRM command request type. */
45042 * The completion ring to send the completion event on. This should
45043 * be the NQ ID returned from the `nq_alloc` HWRM command.
45045 uint16_t cmpl_ring;
45047 * The sequence ID is used by the driver for tracking multiple
45048 * commands. This ID is treated as opaque data by the firmware and
45049 * the value is returned in the `hwrm_resp_hdr` upon completion.
45053 * The target ID of the command:
45054 * * 0x0-0xFFF8 - The function ID
45055 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45056 * * 0xFFFD - Reserved for user-space HWRM interface
45059 uint16_t target_id;
45061 * A physical address pointer pointing to a host buffer that the
45062 * command's response data will be written. This can be either a host
45063 * physical address (HPA) or a guest physical address (GPA) and must
45064 * point to a physically contiguous block of memory.
45066 uint64_t resp_addr;
45067 /* Directory Entry Index */
45069 uint8_t unused_0[6];
45072 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
45073 struct hwrm_nvm_erase_dir_entry_output {
45074 /* The specific error status for the command. */
45075 uint16_t error_code;
45076 /* The HWRM command request type. */
45078 /* The sequence ID from the original command. */
45080 /* The length of the response data in number of bytes. */
45082 uint8_t unused_0[7];
45084 * This field is used in Output records to indicate that the output
45085 * is completely written to RAM. This field should be read as '1'
45086 * to indicate that the output has been completely written.
45087 * When writing a command completion or response to an internal processor,
45088 * the order of writes has to be such that this field is written last.
45093 /*************************
45094 * hwrm_nvm_get_dev_info *
45095 *************************/
45098 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
45099 struct hwrm_nvm_get_dev_info_input {
45100 /* The HWRM command request type. */
45103 * The completion ring to send the completion event on. This should
45104 * be the NQ ID returned from the `nq_alloc` HWRM command.
45106 uint16_t cmpl_ring;
45108 * The sequence ID is used by the driver for tracking multiple
45109 * commands. This ID is treated as opaque data by the firmware and
45110 * the value is returned in the `hwrm_resp_hdr` upon completion.
45114 * The target ID of the command:
45115 * * 0x0-0xFFF8 - The function ID
45116 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45117 * * 0xFFFD - Reserved for user-space HWRM interface
45120 uint16_t target_id;
45122 * A physical address pointer pointing to a host buffer that the
45123 * command's response data will be written. This can be either a host
45124 * physical address (HPA) or a guest physical address (GPA) and must
45125 * point to a physically contiguous block of memory.
45127 uint64_t resp_addr;
45130 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
45131 struct hwrm_nvm_get_dev_info_output {
45132 /* The specific error status for the command. */
45133 uint16_t error_code;
45134 /* The HWRM command request type. */
45136 /* The sequence ID from the original command. */
45138 /* The length of the response data in number of bytes. */
45140 /* Manufacturer ID. */
45141 uint16_t manufacturer_id;
45143 uint16_t device_id;
45144 /* Sector size of the NVRAM device. */
45145 uint32_t sector_size;
45146 /* Total size, in bytes of the NVRAM device. */
45147 uint32_t nvram_size;
45148 uint32_t reserved_size;
45150 * Available size that can be used, in bytes. Available size is the
45151 * NVRAM size take away the used size and reserved size.
45153 uint32_t available_size;
45154 /* This field represents the major version of NVM cfg */
45155 uint8_t nvm_cfg_ver_maj;
45156 /* This field represents the minor version of NVM cfg */
45157 uint8_t nvm_cfg_ver_min;
45158 /* This field represents the update version of NVM cfg */
45159 uint8_t nvm_cfg_ver_upd;
45162 * If set to 1, firmware will provide various firmware version
45163 * information stored in the flash.
45165 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
45168 * This field represents the board package name stored in the flash.
45169 * (ASCII chars with NULL at the end).
45173 * This field represents the major version of HWRM firmware, stored in
45176 uint16_t hwrm_fw_major;
45178 * This field represents the minor version of HWRM firmware, stored in
45181 uint16_t hwrm_fw_minor;
45183 * This field represents the build version of HWRM firmware, stored in
45186 uint16_t hwrm_fw_build;
45188 * This field can be used to represent firmware branches or customer
45189 * specific releases tied to a specific (major, minor, build) version
45190 * of the HWRM firmware.
45192 uint16_t hwrm_fw_patch;
45194 * This field represents the major version of mgmt firmware, stored in
45197 uint16_t mgmt_fw_major;
45199 * This field represents the minor version of mgmt firmware, stored in
45202 uint16_t mgmt_fw_minor;
45204 * This field represents the build version of mgmt firmware, stored in
45207 uint16_t mgmt_fw_build;
45209 * This field can be used to represent firmware branches or customer
45210 * specific releases tied to a specific (major, minor, build) version
45211 * of the mgmt firmware.
45213 uint16_t mgmt_fw_patch;
45215 * This field represents the major version of roce firmware, stored in
45218 uint16_t roce_fw_major;
45220 * This field represents the minor version of roce firmware, stored in
45223 uint16_t roce_fw_minor;
45225 * This field represents the build version of roce firmware, stored in
45228 uint16_t roce_fw_build;
45230 * This field can be used to represent firmware branches or customer
45231 * specific releases tied to a specific (major, minor, build) version
45232 * of the roce firmware.
45234 uint16_t roce_fw_patch;
45235 uint8_t unused_0[7];
45237 * This field is used in Output records to indicate that the output
45238 * is completely written to RAM. This field should be read as '1'
45239 * to indicate that the output has been completely written.
45240 * When writing a command completion or response to an internal processor,
45241 * the order of writes has to be such that this field is written last.
45246 /**************************
45247 * hwrm_nvm_mod_dir_entry *
45248 **************************/
45251 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
45252 struct hwrm_nvm_mod_dir_entry_input {
45253 /* The HWRM command request type. */
45256 * The completion ring to send the completion event on. This should
45257 * be the NQ ID returned from the `nq_alloc` HWRM command.
45259 uint16_t cmpl_ring;
45261 * The sequence ID is used by the driver for tracking multiple
45262 * commands. This ID is treated as opaque data by the firmware and
45263 * the value is returned in the `hwrm_resp_hdr` upon completion.
45267 * The target ID of the command:
45268 * * 0x0-0xFFF8 - The function ID
45269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45270 * * 0xFFFD - Reserved for user-space HWRM interface
45273 uint16_t target_id;
45275 * A physical address pointer pointing to a host buffer that the
45276 * command's response data will be written. This can be either a host
45277 * physical address (HPA) or a guest physical address (GPA) and must
45278 * point to a physically contiguous block of memory.
45280 uint64_t resp_addr;
45283 * This bit must be '1' for the checksum field to be
45286 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
45287 /* Directory Entry Index */
45290 * Directory ordinal.
45291 * The (0-based) instance of this Directory Type.
45293 uint16_t dir_ordinal;
45295 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension
45296 * flag definitions).
45300 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag
45305 * If valid, then this field updates the checksum
45306 * value of the content in the directory entry.
45311 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
45312 struct hwrm_nvm_mod_dir_entry_output {
45313 /* The specific error status for the command. */
45314 uint16_t error_code;
45315 /* The HWRM command request type. */
45317 /* The sequence ID from the original command. */
45319 /* The length of the response data in number of bytes. */
45321 uint8_t unused_0[7];
45323 * This field is used in Output records to indicate that the output
45324 * is completely written to RAM. This field should be read as '1'
45325 * to indicate that the output has been completely written.
45326 * When writing a command completion or response to an internal processor,
45327 * the order of writes has to be such that this field is written last.
45332 /**************************
45333 * hwrm_nvm_verify_update *
45334 **************************/
45337 /* hwrm_nvm_verify_update_input (size:192b/24B) */
45338 struct hwrm_nvm_verify_update_input {
45339 /* The HWRM command request type. */
45342 * The completion ring to send the completion event on. This should
45343 * be the NQ ID returned from the `nq_alloc` HWRM command.
45345 uint16_t cmpl_ring;
45347 * The sequence ID is used by the driver for tracking multiple
45348 * commands. This ID is treated as opaque data by the firmware and
45349 * the value is returned in the `hwrm_resp_hdr` upon completion.
45353 * The target ID of the command:
45354 * * 0x0-0xFFF8 - The function ID
45355 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45356 * * 0xFFFD - Reserved for user-space HWRM interface
45359 uint16_t target_id;
45361 * A physical address pointer pointing to a host buffer that the
45362 * command's response data will be written. This can be either a host
45363 * physical address (HPA) or a guest physical address (GPA) and must
45364 * point to a physically contiguous block of memory.
45366 uint64_t resp_addr;
45367 /* Directory Entry Type, to be verified. */
45370 * Directory ordinal.
45371 * The instance of the Directory Type to be verified.
45373 uint16_t dir_ordinal;
45375 * The Directory Entry Extension flags.
45376 * The "UPDATE" extension flag must be set in this value.
45377 * A corresponding directory entry with the same type and ordinal values but *without*
45378 * the "UPDATE" extension flag must also exist. The other flags of the extension must
45379 * be identical between the active and update entries.
45382 uint8_t unused_0[2];
45385 /* hwrm_nvm_verify_update_output (size:128b/16B) */
45386 struct hwrm_nvm_verify_update_output {
45387 /* The specific error status for the command. */
45388 uint16_t error_code;
45389 /* The HWRM command request type. */
45391 /* The sequence ID from the original command. */
45393 /* The length of the response data in number of bytes. */
45395 uint8_t unused_0[7];
45397 * This field is used in Output records to indicate that the output
45398 * is completely written to RAM. This field should be read as '1'
45399 * to indicate that the output has been completely written.
45400 * When writing a command completion or response to an internal processor,
45401 * the order of writes has to be such that this field is written last.
45406 /***************************
45407 * hwrm_nvm_install_update *
45408 ***************************/
45411 /* hwrm_nvm_install_update_input (size:192b/24B) */
45412 struct hwrm_nvm_install_update_input {
45413 /* The HWRM command request type. */
45416 * The completion ring to send the completion event on. This should
45417 * be the NQ ID returned from the `nq_alloc` HWRM command.
45419 uint16_t cmpl_ring;
45421 * The sequence ID is used by the driver for tracking multiple
45422 * commands. This ID is treated as opaque data by the firmware and
45423 * the value is returned in the `hwrm_resp_hdr` upon completion.
45427 * The target ID of the command:
45428 * * 0x0-0xFFF8 - The function ID
45429 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45430 * * 0xFFFD - Reserved for user-space HWRM interface
45433 uint16_t target_id;
45435 * A physical address pointer pointing to a host buffer that the
45436 * command's response data will be written. This can be either a host
45437 * physical address (HPA) or a guest physical address (GPA) and must
45438 * point to a physically contiguous block of memory.
45440 uint64_t resp_addr;
45442 * Installation type. If the value 3 through 0xffff is used,
45443 * only packaged items with that type value will be installed and
45444 * conditional installation directives for those packaged items
45445 * will be over-ridden (i.e. 'create' or 'replace' will be treated
45448 uint32_t install_type;
45450 * Perform a normal package installation. Conditional installation
45451 * directives (e.g. 'create' and 'replace') of packaged items
45452 * will be followed.
45454 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
45456 * Install all packaged items regardless of installation directive
45457 * (i.e. treat all packaged items as though they have an installation
45458 * directive of 'install').
45460 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
45461 UINT32_C(0xffffffff)
45462 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
45463 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
45465 /* If set to 1, then securely erase all unused locations in persistent storage. */
45466 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
45469 * If set to 1, then unspecified images, images not in the package file,
45470 * will be safely deleted.
45471 * When combined with erase_unused_space then unspecified images will be
45474 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
45477 * If set to 1, FW will defragment the NVM if defragmentation is required
45479 * Allow additional time for this command to complete if this bit is set to 1.
45481 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
45484 * If set to 1, FW will verify the package in the "UPDATE" NVM item
45485 * without installing it. This flag is for FW internal use only.
45486 * Users should not set this flag. The request will otherwise fail.
45488 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
45490 uint8_t unused_0[2];
45493 /* hwrm_nvm_install_update_output (size:192b/24B) */
45494 struct hwrm_nvm_install_update_output {
45495 /* The specific error status for the command. */
45496 uint16_t error_code;
45497 /* The HWRM command request type. */
45499 /* The sequence ID from the original command. */
45501 /* The length of the response data in number of bytes. */
45504 * Bit-mask of successfully installed items.
45505 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
45506 * A value of 0 indicates that no items were successfully installed.
45508 uint64_t installed_items;
45509 /* result is 8 b */
45511 /* There was no problem with the package installation. */
45512 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
45513 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
45514 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
45515 /* problem_item is 8 b */
45516 uint8_t problem_item;
45517 /* There was no problem with any packaged items. */
45518 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
45520 /* There was a problem with the NVM package itself. */
45521 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
45523 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
45524 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
45525 /* reset_required is 8 b */
45526 uint8_t reset_required;
45528 * No reset is required for installed/updated firmware or
45529 * microcode to take effect.
45531 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
45534 * A PCIe reset (e.g. system reboot) is
45535 * required for newly installed/updated firmware or
45536 * microcode to take effect.
45538 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
45541 * A controller power reset (e.g. system power-cycle) is
45542 * required for newly installed/updated firmware or
45543 * microcode to take effect. Some newly installed/updated
45544 * firmware or microcode may still take effect upon the
45547 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
45549 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
45550 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
45551 uint8_t unused_0[4];
45553 * This field is used in Output records to indicate that the output
45554 * is completely written to RAM. This field should be read as '1'
45555 * to indicate that the output has been completely written.
45556 * When writing a command completion or response to an internal processor,
45557 * the order of writes has to be such that this field is written last.
45562 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
45563 struct hwrm_nvm_install_update_cmd_err {
45565 * command specific error codes that goes to
45566 * the cmd_err field in Common HWRM Error Response.
45569 /* Unknown error */
45570 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
45571 /* Unable to complete operation due to fragmentation */
45572 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
45573 /* nvm is completely full. */
45574 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
45575 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
45576 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
45577 uint8_t unused_0[7];
45580 /******************
45582 ******************/
45585 /* hwrm_nvm_flush_input (size:128b/16B) */
45586 struct hwrm_nvm_flush_input {
45587 /* The HWRM command request type. */
45590 * The completion ring to send the completion event on. This should
45591 * be the NQ ID returned from the `nq_alloc` HWRM command.
45593 uint16_t cmpl_ring;
45595 * The sequence ID is used by the driver for tracking multiple
45596 * commands. This ID is treated as opaque data by the firmware and
45597 * the value is returned in the `hwrm_resp_hdr` upon completion.
45601 * The target ID of the command:
45602 * * 0x0-0xFFF8 - The function ID
45603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45604 * * 0xFFFD - Reserved for user-space HWRM interface
45607 uint16_t target_id;
45609 * A physical address pointer pointing to a host buffer that the
45610 * command's response data will be written. This can be either a host
45611 * physical address (HPA) or a guest physical address (GPA) and must
45612 * point to a physically contiguous block of memory.
45614 uint64_t resp_addr;
45617 /* hwrm_nvm_flush_output (size:128b/16B) */
45618 struct hwrm_nvm_flush_output {
45619 /* The specific error status for the command. */
45620 uint16_t error_code;
45621 /* The HWRM command request type. */
45623 /* The sequence ID from the original command. */
45625 /* The length of the response data in number of bytes. */
45627 uint8_t unused_0[7];
45629 * This field is used in Output records to indicate that the output
45630 * is completely written to RAM. This field should be read as '1'
45631 * to indicate that the output has been completely written.
45632 * When writing a command completion or response to an internal processor,
45633 * the order of writes has to be such that this field is written last.
45638 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
45639 struct hwrm_nvm_flush_cmd_err {
45641 * command specific error codes that goes to
45642 * the cmd_err field in Common HWRM Error Response.
45645 /* Unknown error */
45646 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
45647 /* flush could not be performed */
45648 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
45649 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
45650 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
45651 uint8_t unused_0[7];
45654 /*************************
45655 * hwrm_nvm_get_variable *
45656 *************************/
45659 /* hwrm_nvm_get_variable_input (size:320b/40B) */
45660 struct hwrm_nvm_get_variable_input {
45661 /* The HWRM command request type. */
45664 * The completion ring to send the completion event on. This should
45665 * be the NQ ID returned from the `nq_alloc` HWRM command.
45667 uint16_t cmpl_ring;
45669 * The sequence ID is used by the driver for tracking multiple
45670 * commands. This ID is treated as opaque data by the firmware and
45671 * the value is returned in the `hwrm_resp_hdr` upon completion.
45675 * The target ID of the command:
45676 * * 0x0-0xFFF8 - The function ID
45677 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45678 * * 0xFFFD - Reserved for user-space HWRM interface
45681 uint16_t target_id;
45683 * A physical address pointer pointing to a host buffer that the
45684 * command's response data will be written. This can be either a host
45685 * physical address (HPA) or a guest physical address (GPA) and must
45686 * point to a physically contiguous block of memory.
45688 uint64_t resp_addr;
45690 * This is the host address where
45691 * nvm variable will be stored
45693 uint64_t dest_data_addr;
45694 /* size of data in bits */
45696 /* nvm cfg option number */
45697 uint16_t option_num;
45699 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
45701 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
45703 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
45704 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
45706 * Number of dimensions for this nvm configuration variable.
45707 * This value indicates how many of the indexN values to use.
45708 * A value of 0 means that none of the indexN values are valid.
45709 * A value of 1 requires at index0 is valued, a value of 2
45710 * requires that index0 and index1 are valid, and so forth
45712 uint16_t dimensions;
45713 /* index for the 1st dimensions */
45715 /* index for the 2nd dimensions */
45717 /* index for the 3rd dimensions */
45719 /* index for the 4th dimensions */
45723 * When this bit is set to 1, the factory default value will be returned,
45724 * 0 returns the operational value.
45726 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
45731 /* hwrm_nvm_get_variable_output (size:128b/16B) */
45732 struct hwrm_nvm_get_variable_output {
45733 /* The specific error status for the command. */
45734 uint16_t error_code;
45735 /* The HWRM command request type. */
45737 /* The sequence ID from the original command. */
45739 /* The length of the response data in number of bytes. */
45741 /* size of data of the actual variable retrieved in bits */
45744 * option_num is the option number for the data retrieved. It is possible in the
45745 * future that the option number returned would be different than requested. This
45746 * condition could occur if an option is deprecated and a new option id is defined
45747 * with similar characteristics, but has a slightly different definition. This
45748 * also makes it convenient for the caller to identify the variable result with
45749 * the option id from the response.
45751 uint16_t option_num;
45753 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
45755 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
45757 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
45758 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
45759 uint8_t unused_0[3];
45761 * This field is used in Output records to indicate that the output
45762 * is completely written to RAM. This field should be read as '1'
45763 * to indicate that the output has been completely written.
45764 * When writing a command completion or response to an internal processor,
45765 * the order of writes has to be such that this field is written last.
45770 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
45771 struct hwrm_nvm_get_variable_cmd_err {
45773 * command specific error codes that goes to
45774 * the cmd_err field in Common HWRM Error Response.
45777 /* Unknown error */
45778 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
45779 /* variable does not exist */
45780 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
45781 /* configuration is corrupted and the variable cannot be saved */
45782 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
45783 /* length specified is too small */
45784 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
45785 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
45786 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
45787 uint8_t unused_0[7];
45790 /*************************
45791 * hwrm_nvm_set_variable *
45792 *************************/
45795 /* hwrm_nvm_set_variable_input (size:320b/40B) */
45796 struct hwrm_nvm_set_variable_input {
45797 /* The HWRM command request type. */
45800 * The completion ring to send the completion event on. This should
45801 * be the NQ ID returned from the `nq_alloc` HWRM command.
45803 uint16_t cmpl_ring;
45805 * The sequence ID is used by the driver for tracking multiple
45806 * commands. This ID is treated as opaque data by the firmware and
45807 * the value is returned in the `hwrm_resp_hdr` upon completion.
45811 * The target ID of the command:
45812 * * 0x0-0xFFF8 - The function ID
45813 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45814 * * 0xFFFD - Reserved for user-space HWRM interface
45817 uint16_t target_id;
45819 * A physical address pointer pointing to a host buffer that the
45820 * command's response data will be written. This can be either a host
45821 * physical address (HPA) or a guest physical address (GPA) and must
45822 * point to a physically contiguous block of memory.
45824 uint64_t resp_addr;
45826 * This is the host address where
45827 * nvm variable will be copied from
45829 uint64_t src_data_addr;
45830 /* size of data in bits */
45832 /* nvm cfg option number */
45833 uint16_t option_num;
45835 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
45837 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
45839 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
45840 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
45842 * Number of dimensions for this nvm configuration variable.
45843 * This value indicates how many of the indexN values to use.
45844 * A value of 0 means that none of the indexN values are valid.
45845 * A value of 1 requires at index0 is valued, a value of 2
45846 * requires that index0 and index1 are valid, and so forth
45848 uint16_t dimensions;
45849 /* index for the 1st dimensions */
45851 /* index for the 2nd dimensions */
45853 /* index for the 3rd dimensions */
45855 /* index for the 4th dimensions */
45859 * When this bit is 1, flush internal cache after this write operation
45860 * (see hwrm_nvm_flush command.)
45862 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
45864 /* encryption method */
45865 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
45867 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
45868 /* No encryption. */
45869 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
45870 (UINT32_C(0x0) << 1)
45871 /* one-way encryption. */
45872 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
45873 (UINT32_C(0x1) << 1)
45874 /* symmetric AES256 encryption. */
45875 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
45876 (UINT32_C(0x2) << 1)
45877 /* SHA1 digest appended to plaintext contents, for authentication */
45878 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
45879 (UINT32_C(0x3) << 1)
45880 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
45881 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
45882 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
45884 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
45885 /* When this bit is 1, update the factory default region */
45886 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
45891 /* hwrm_nvm_set_variable_output (size:128b/16B) */
45892 struct hwrm_nvm_set_variable_output {
45893 /* The specific error status for the command. */
45894 uint16_t error_code;
45895 /* The HWRM command request type. */
45897 /* The sequence ID from the original command. */
45899 /* The length of the response data in number of bytes. */
45901 uint8_t unused_0[7];
45903 * This field is used in Output records to indicate that the output
45904 * is completely written to RAM. This field should be read as '1'
45905 * to indicate that the output has been completely written.
45906 * When writing a command completion or response to an internal processor,
45907 * the order of writes has to be such that this field is written last.
45912 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
45913 struct hwrm_nvm_set_variable_cmd_err {
45915 * command specific error codes that goes to
45916 * the cmd_err field in Common HWRM Error Response.
45919 /* Unknown error */
45920 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
45921 /* variable does not exist */
45922 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
45923 /* configuration is corrupted and the variable cannot be saved */
45924 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
45925 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
45926 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
45927 uint8_t unused_0[7];
45930 /****************************
45931 * hwrm_nvm_validate_option *
45932 ****************************/
45935 /* hwrm_nvm_validate_option_input (size:320b/40B) */
45936 struct hwrm_nvm_validate_option_input {
45937 /* The HWRM command request type. */
45940 * The completion ring to send the completion event on. This should
45941 * be the NQ ID returned from the `nq_alloc` HWRM command.
45943 uint16_t cmpl_ring;
45945 * The sequence ID is used by the driver for tracking multiple
45946 * commands. This ID is treated as opaque data by the firmware and
45947 * the value is returned in the `hwrm_resp_hdr` upon completion.
45951 * The target ID of the command:
45952 * * 0x0-0xFFF8 - The function ID
45953 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45954 * * 0xFFFD - Reserved for user-space HWRM interface
45957 uint16_t target_id;
45959 * A physical address pointer pointing to a host buffer that the
45960 * command's response data will be written. This can be either a host
45961 * physical address (HPA) or a guest physical address (GPA) and must
45962 * point to a physically contiguous block of memory.
45964 uint64_t resp_addr;
45966 * This is the host address where
45967 * nvm variable will be copied from
45969 uint64_t src_data_addr;
45970 /* size of data in bits */
45972 /* nvm cfg option number */
45973 uint16_t option_num;
45975 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
45978 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
45980 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
45981 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
45983 * Number of dimensions for this nvm configuration variable.
45984 * This value indicates how many of the indexN values to use.
45985 * A value of 0 means that none of the indexN values are valid.
45986 * A value of 1 requires at index0 is valued, a value of 2
45987 * requires that index0 and index1 are valid, and so forth
45989 uint16_t dimensions;
45990 /* index for the 1st dimensions */
45992 /* index for the 2nd dimensions */
45994 /* index for the 3rd dimensions */
45996 /* index for the 4th dimensions */
45998 uint8_t unused_0[2];
46001 /* hwrm_nvm_validate_option_output (size:128b/16B) */
46002 struct hwrm_nvm_validate_option_output {
46003 /* The specific error status for the command. */
46004 uint16_t error_code;
46005 /* The HWRM command request type. */
46007 /* The sequence ID from the original command. */
46009 /* The length of the response data in number of bytes. */
46012 /* indicates that the value provided for the option is not matching with the saved data. */
46013 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
46014 /* indicates that the value provided for the option is matching the saved data. */
46015 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
46016 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
46017 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
46018 uint8_t unused_0[6];
46020 * This field is used in Output records to indicate that the output
46021 * is completely written to RAM. This field should be read as '1'
46022 * to indicate that the output has been completely written.
46023 * When writing a command completion or response to an internal processor,
46024 * the order of writes has to be such that this field is written last.
46029 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
46030 struct hwrm_nvm_validate_option_cmd_err {
46032 * command specific error codes that goes to
46033 * the cmd_err field in Common HWRM Error Response.
46036 /* Unknown error */
46037 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
46038 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
46039 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
46040 uint8_t unused_0[7];
46048 /* hwrm_oem_cmd_input (size:1024b/128B) */
46049 struct hwrm_oem_cmd_input {
46050 /* The HWRM command request type. */
46053 * The completion ring to send the completion event on. This should
46054 * be the NQ ID returned from the `nq_alloc` HWRM command.
46056 uint16_t cmpl_ring;
46058 * The sequence ID is used by the driver for tracking multiple
46059 * commands. This ID is treated as opaque data by the firmware and
46060 * the value is returned in the `hwrm_resp_hdr` upon completion.
46064 * The target ID of the command:
46065 * * 0x0-0xFFF8 - The function ID
46066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46067 * * 0xFFFD - Reserved for user-space HWRM interface
46070 uint16_t target_id;
46072 * A physical address pointer pointing to a host buffer that the
46073 * command's response data will be written. This can be either a host
46074 * physical address (HPA) or a guest physical address (GPA) and must
46075 * point to a physically contiguous block of memory.
46077 uint64_t resp_addr;
46080 /* This field contains the vendor specific command data. */
46081 uint32_t oem_data[26];
46084 /* hwrm_oem_cmd_output (size:768b/96B) */
46085 struct hwrm_oem_cmd_output {
46086 /* The specific error status for the command. */
46087 uint16_t error_code;
46088 /* The HWRM command request type. */
46090 /* The sequence ID from the original command. */
46092 /* The length of the response data in number of bytes. */
46096 /* This field contains the vendor specific response data. */
46097 uint32_t oem_data[18];
46098 uint8_t unused_1[7];
46100 * This field is used in Output records to indicate that the output
46101 * is completely written to RAM. This field should be read as '1'
46102 * to indicate that the output has been completely written.
46103 * When writing a command completion or response to an internal processor,
46104 * the order of writes has to be such that this field is written last.
46111 ******************/
46114 /* hwrm_fw_reset_input (size:192b/24B) */
46115 struct hwrm_fw_reset_input {
46116 /* The HWRM command request type. */
46119 * The completion ring to send the completion event on. This should
46120 * be the NQ ID returned from the `nq_alloc` HWRM command.
46122 uint16_t cmpl_ring;
46124 * The sequence ID is used by the driver for tracking multiple
46125 * commands. This ID is treated as opaque data by the firmware and
46126 * the value is returned in the `hwrm_resp_hdr` upon completion.
46130 * The target ID of the command:
46131 * * 0x0-0xFFF8 - The function ID
46132 * * 0xFFF8-0xFFFE - Reserved for internal processors
46135 uint16_t target_id;
46137 * A physical address pointer pointing to a host buffer that the
46138 * command's response data will be written. This can be either a host
46139 * physical address (HPA) or a guest physical address (GPA) and must
46140 * point to a physically contiguous block of memory.
46142 uint64_t resp_addr;
46143 /* Type of embedded processor. */
46144 uint8_t embedded_proc_type;
46145 /* Boot Processor */
46146 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
46148 /* Management Processor */
46149 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
46151 /* Network control processor */
46152 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
46154 /* RoCE control processor */
46155 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
46158 * Host (in multi-host environment): This is only valid if requester is IPC.
46159 * Reinit host hardware resources and PCIe.
46161 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
46164 * AP processor complex (in multi-host environment). Use host_idx to
46165 * control which core is reset
46167 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
46169 /* Reset all blocks of the chip (including all processors) */
46170 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
46173 * Host (in multi-host environment): This is only valid if requester is IPC.
46174 * Reinit host hardware resources.
46176 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
46178 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
46179 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
46180 /* Type of self reset. */
46181 uint8_t selfrst_status;
46182 /* No Self Reset */
46183 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
46185 /* Self Reset as soon as possible to do so safely */
46186 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
46188 /* Self Reset on PCIe Reset */
46189 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
46191 /* Self Reset immediately after notification to all clients. */
46192 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
46194 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
46195 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
46197 * Indicate which host is being reset. 0 means first host.
46198 * Only valid when embedded_proc_type is host in multihost
46204 * When this bit is '1', then the core firmware initiates
46205 * the reset only after graceful shut down of all registered instances.
46206 * If not, the device will continue with the existing firmware.
46208 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
46209 uint8_t unused_0[4];
46212 /* hwrm_fw_reset_output (size:128b/16B) */
46213 struct hwrm_fw_reset_output {
46214 /* The specific error status for the command. */
46215 uint16_t error_code;
46216 /* The HWRM command request type. */
46218 /* The sequence ID from the original command. */
46220 /* The length of the response data in number of bytes. */
46222 /* Type of self reset. */
46223 uint8_t selfrst_status;
46224 /* No Self Reset */
46225 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
46227 /* Self Reset as soon as possible to do so safely */
46228 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
46230 /* Self Reset on PCIe Reset */
46231 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
46233 /* Self Reset immediately after notification to all clients. */
46234 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
46236 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
46237 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
46238 uint8_t unused_0[6];
46240 * This field is used in Output records to indicate that the output
46241 * is completely written to RAM. This field should be read as '1'
46242 * to indicate that the output has been completely written.
46243 * When writing a command completion or response to an internal processor,
46244 * the order of writes has to be such that this field is written last.
46249 /**********************
46250 * hwrm_port_ts_query *
46251 ***********************/
46254 /* hwrm_port_ts_query_input (size:192b/24B) */
46255 struct hwrm_port_ts_query_input {
46256 /* The HWRM command request type. */
46259 * The completion ring to send the completion event on. This should
46260 * be the NQ ID returned from the `nq_alloc` HWRM command.
46262 uint16_t cmpl_ring;
46264 * The sequence ID is used by the driver for tracking multiple
46265 * commands. This ID is treated as opaque data by the firmware and
46266 * the value is returned in the `hwrm_resp_hdr` upon completion.
46270 * The target ID of the command:
46271 * * 0x0-0xFFF8 - The function ID
46272 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46273 * * 0xFFFD - Reserved for user-space HWRM interface
46276 uint16_t target_id;
46278 * A physical address pointer pointing to a host buffer that the
46279 * command's response data will be written. This can be either a host
46280 * physical address (HPA) or a guest physical address (GPA) and must
46281 * point to a physically contiguous block of memory.
46283 uint64_t resp_addr;
46286 * Enumeration denoting the RX, TX type of the resource.
46287 * This enumeration is used for resources that are similar for both
46288 * TX and RX paths of the chip.
46290 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
46292 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
46294 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
46295 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
46296 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
46298 * If set, the response includes the current value of the free
46301 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
46302 /* Port ID of port that is being queried. */
46304 uint8_t unused_0[2];
46307 /* hwrm_port_ts_query_output (size:192b/24B) */
46308 struct hwrm_port_ts_query_output {
46309 /* The specific error status for the command. */
46310 uint16_t error_code;
46311 /* The HWRM command request type. */
46313 /* The sequence ID from the original command. */
46315 /* The length of the response data in number of bytes. */
46318 * Timestamp value of PTP message captured, or current value of
46319 * free running timer.
46321 uint32_t ptp_msg_ts[2];
46322 /* Sequence ID of the PTP message captured. */
46323 uint16_t ptp_msg_seqid;
46324 uint8_t unused_0[5];
46326 * This field is used in Output records to indicate that the output
46327 * is completely written to RAM. This field should be read as '1'
46328 * to indicate that the output has been completely written.
46329 * When writing a command completion or response to an internal processor,
46330 * the order of writes has to be such that this field is written last.
46336 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
46337 * offset: 0x31001F0). Host software is expected to read from this
46338 * location for a defined signature. If it exists, the software can
46339 * assume the presence of this structure and the validity of the
46340 * FW_STATUS location in the next field.
46342 /* hcomm_status (size:64b/8B) */
46343 struct hcomm_status {
46346 * This field defines the version of the structure. The latest
46347 * version value is 1.
46349 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
46350 #define HCOMM_STATUS_VER_SFT 0
46351 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
46352 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
46354 * This field is to store the signature value to indicate the
46355 * presence of the structure.
46357 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
46358 #define HCOMM_STATUS_SIGNATURE_SFT 8
46359 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
46360 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
46361 uint32_t fw_status_loc;
46362 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
46363 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
46364 /* PCIE configuration space */
46365 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
46367 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
46369 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
46371 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
46372 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
46373 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
46375 * This offset where the fw_status register is located. The value
46376 * is generally 4-byte aligned.
46378 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
46379 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
46381 /* This is the GRC offset where the hcomm_status struct resides. */
46382 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
46383 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */