1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2021 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
273 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
274 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
275 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
276 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
277 /* Reserved for future use. */
278 #define HWRM_RESERVED1 UINT32_C(0x10)
279 #define HWRM_FUNC_RESET UINT32_C(0x11)
280 #define HWRM_FUNC_GETFID UINT32_C(0x12)
281 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
282 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
283 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
284 #define HWRM_FUNC_QCFG UINT32_C(0x16)
285 #define HWRM_FUNC_CFG UINT32_C(0x17)
286 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
287 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
288 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
289 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
290 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
291 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
292 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
293 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
294 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
295 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
297 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
298 #define HWRM_PORT_QSTATS UINT32_C(0x23)
299 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
301 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
303 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
304 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
305 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
307 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
308 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
309 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
310 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
311 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
312 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
313 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
314 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
315 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
316 #define HWRM_QUEUE_CFG UINT32_C(0x32)
317 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
318 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
319 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
320 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
321 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
322 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
323 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
324 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
325 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
326 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 /* Updates specific fields in RX VNIC structure */
341 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
342 #define HWRM_RING_ALLOC UINT32_C(0x50)
343 #define HWRM_RING_FREE UINT32_C(0x51)
344 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
345 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
346 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
347 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
348 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
349 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
350 #define HWRM_RING_RESET UINT32_C(0x5e)
351 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
352 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
353 #define HWRM_RING_CFG UINT32_C(0x62)
354 #define HWRM_RING_QCFG UINT32_C(0x63)
355 /* Reserved for future use. */
356 #define HWRM_RESERVED5 UINT32_C(0x64)
357 /* Reserved for future use. */
358 #define HWRM_RESERVED6 UINT32_C(0x65)
359 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
360 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
361 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
362 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
363 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
364 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
365 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
366 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
367 #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
368 #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
369 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
370 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
371 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
372 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
373 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
374 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
375 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
377 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
379 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
380 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
381 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
382 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
384 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
386 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
388 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
389 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
390 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
391 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
392 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
393 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
394 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
395 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
396 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
397 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
398 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
399 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
400 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
401 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
402 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
404 #define HWRM_RESERVED7 UINT32_C(0xba)
405 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
406 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
407 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
408 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
409 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
410 #define HWRM_FW_RESET UINT32_C(0xc0)
411 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
412 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
413 #define HWRM_FW_SYNC UINT32_C(0xc3)
414 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
415 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
416 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
417 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
419 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
421 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
423 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
425 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
427 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
428 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
429 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
430 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
431 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
432 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
433 #define HWRM_FWD_RESP UINT32_C(0xd2)
434 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
435 #define HWRM_OEM_CMD UINT32_C(0xd4)
436 /* Tells the fw to run PRBS test on a given port and lane. */
437 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
438 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
439 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
440 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
441 /* Tells the fw to collect dsc dump on a given port and lane. */
442 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
443 #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
444 #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
445 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
446 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
447 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
448 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
449 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
450 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
451 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
452 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
454 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
456 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
458 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
460 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
462 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
464 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
466 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
468 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
470 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
472 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
474 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
476 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
478 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
480 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
482 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
484 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
486 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
488 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
490 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
491 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
492 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
493 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
495 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
497 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
499 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
501 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
502 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
503 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
505 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
507 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
509 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
511 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
513 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
515 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
517 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
519 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
521 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
523 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
525 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
527 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
529 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
531 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
533 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
535 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
537 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
539 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
540 /* Experimental - DEPRECATED */
541 #define HWRM_CFA_TFLIB UINT32_C(0x125)
543 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
545 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
546 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
547 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
548 /* Engine CKV - Add a new CKEK used to encrypt keys. */
549 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
550 /* Engine CKV - Delete a previously added CKEK. */
551 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
552 /* Engine CKV - Add a new key to the key vault. */
553 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
554 /* Engine CKV - Delete a key from the key vault. */
555 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
556 /* Engine CKV - Delete all keys from the key vault. */
557 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
558 /* Engine CKV - Get random data. */
559 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
560 /* Engine CKV - Generate and encrypt a new AES key. */
561 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
562 /* Engine CKV - Configure a label index with a label value. */
563 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
564 /* Engine CKV - Query a label */
565 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
566 /* Engine - Query the available queue groups configuration. */
567 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
568 /* Engine - Query the queue groups assigned to a function. */
569 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
570 /* Engine - Query the available queue group meter profile configuration. */
571 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
572 /* Engine - Query the configuration of a queue group meter profile. */
573 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
574 /* Engine - Allocate a queue group meter profile. */
575 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
576 /* Engine - Free a queue group meter profile. */
577 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
578 /* Engine - Query the meters assigned to a queue group. */
579 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
580 /* Engine - Bind a queue group meter profile to a queue group. */
581 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
582 /* Engine - Unbind a queue group meter profile from a queue group. */
583 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
584 /* Engine - Bind a queue group to a function. */
585 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
586 /* Engine - Query the scheduling group configuration. */
587 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
588 /* Engine - Query the queue groups assigned to a scheduling group. */
589 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
590 /* Engine - Query the configuration of a scheduling group's meter profiles. */
591 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
592 /* Engine - Configure a scheduling group's meter profiles. */
593 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
594 /* Engine - Bind a queue group to a scheduling group. */
595 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
596 /* Engine - Unbind a queue group from its scheduling group. */
597 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
598 /* Engine - Query the Engine configuration. */
599 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
600 /* Engine - Configure the statistics accumulator for an Engine. */
601 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
602 /* Engine - Clear the statistics accumulator for an Engine. */
603 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
604 /* Engine - Query the statistics accumulator for an Engine. */
605 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
606 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
607 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
608 /* Engine - Allocate an Engine RQ. */
609 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
610 /* Engine - Free an Engine RQ. */
611 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
612 /* Engine - Allocate an Engine CQ. */
613 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
614 /* Engine - Free an Engine CQ. */
615 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
616 /* Engine - Allocate an NQ. */
617 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
618 /* Engine - Free an NQ. */
619 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
620 /* Engine - Set the on-die RQE credit update location. */
621 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
622 /* Engine - Query the engine function configuration. */
623 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
625 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
627 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
629 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
631 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
633 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
634 /* Configures the BW of any VF */
635 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
636 /* Queries the BW of any VF */
637 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
638 /* Queries pf ids belong to specified host(s) */
639 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
640 /* Queries extended stats per function */
641 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
642 /* Queries extended statistics context */
643 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
644 /* Configure SoC packet DMA settings */
645 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
646 /* Query SoC packet DMA settings */
647 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
648 /* PTP - Queries configuration of timesync IO pins. */
649 #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
650 /* PTP - Configuration of timesync IO pins. */
651 #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
652 /* PTP - Configuration for disciplining PHC. */
653 #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
654 /* PTP - Queries for PHC timestamps. */
655 #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
656 /* PTP - Extended PTP configuration. */
657 #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
658 /* PTP - Query extended PTP configuration. */
659 #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
661 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
663 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
665 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
667 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
669 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
671 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
672 /* Returns the current value of a free running counter from the device. */
673 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
675 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
677 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
679 * Tells the fw to run the DMA read from the host and DMA write
682 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
683 /* Tells the fw to program the fru memory */
684 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
685 /* Tells the fw to read the fru memory */
686 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
687 /* Used to provision SoC software images */
688 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
689 /* Retrieves the SoC status and image provisioning information */
690 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
691 /* Tells the fw to program the seeprom memory */
692 #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
693 /* Tells the fw to read the seeprom memory */
694 #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
695 /* Tells the fw to get the health of seeprom data */
696 #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
698 * The command is used for certificate provisioning to export a
699 * Certificate Signing Request (CSR) from the device.
701 #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
703 * The command is used for certificate provisioning to import a
704 * CA-signed certificate chain to the device.
706 #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
708 * The command is used for certificate provisioning to query the
711 #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
713 * The command is used to get the hash of the NVM configuration that is
714 * calculated during firmware boot.
716 #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
718 #define HWRM_TF UINT32_C(0x2bc)
720 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
722 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
724 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
726 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
728 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
730 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
732 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
734 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
736 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
738 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
740 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
742 #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
744 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
746 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
748 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
750 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
752 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
754 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
756 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
758 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
760 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
762 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
764 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
766 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
768 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
770 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
772 #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
774 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
776 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
778 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
780 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
782 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
784 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
786 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
788 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
790 #define HWRM_SV UINT32_C(0x400)
792 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
794 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
796 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
798 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
799 #define HWRM_DBG_DUMP UINT32_C(0xff14)
801 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
803 #define HWRM_DBG_CFG UINT32_C(0xff16)
805 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
807 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
809 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
811 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
813 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
815 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
817 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
819 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
820 /* Send driver debug information to firmware */
821 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
822 /* Query debug capabilities of firmware */
823 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
824 /* Retrieve debug settings of firmware */
825 #define HWRM_DBG_QCFG UINT32_C(0xff21)
826 /* Set destination parameters for crashdump medium */
827 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
829 #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
831 #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
833 #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
835 #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
837 #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
839 #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
841 #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
843 #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
845 #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
846 #define HWRM_NVM_DEFRAG UINT32_C(0xffec)
847 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
849 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
850 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
851 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
852 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
853 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
854 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
855 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
856 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
857 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
858 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
859 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
860 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
861 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
862 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
863 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
864 #define HWRM_NVM_READ UINT32_C(0xfffd)
865 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
866 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
867 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
868 uint16_t unused_0[3];
872 /* ret_codes (size:64b/8B) */
875 /* Request was successfully executed by the HWRM. */
876 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
877 /* The HWRM failed to execute the request. */
878 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
880 * The request contains invalid argument(s) or input
883 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
885 * The requester is not allowed to access the requested
886 * resource. This error code shall be provided in a
887 * response to a request to query or modify an existing
888 * resource that is not accessible by the requester.
890 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
892 * The HWRM is unable to allocate the requested resource.
893 * This code only applies to requests for HWRM resource
896 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
898 * Invalid combination of flags is specified in the
901 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
903 * Invalid combination of enables fields is specified in
906 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
908 * Request contains a required TLV that is not supported by
909 * the installed version of firmware.
911 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
913 * No firmware buffer available to accept the request. Driver
914 * should retry the request.
916 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
918 * This error code is only reported by firmware when some
919 * sub-option of a supported HWRM command is unsupported.
921 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
923 * This error code is only reported by firmware when the specific
924 * request is not able to process when the HOT reset in progress.
926 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
928 * This error code is only reported by firmware when the registered
929 * driver instances are not capable of hot reset.
931 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
933 * This error code is only reported by the firmware when during
934 * flow allocation when a request for a flow counter fails because
935 * the number of flow counters are exhausted.
937 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
939 * This error code is only reported by firmware when the registered
940 * driver instances requested to offloaded a flow but was unable to because
941 * the requested key's hash collides with the installed keys.
943 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
945 * This error code is only reported by firmware when the registered
946 * driver instances requested to offloaded a flow but was unable to because
947 * the same key has already been installed.
949 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
951 * Generic HWRM execution error that represents an
954 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
956 * Firmware is unable to service the request at the present time. Caller
957 * may try again later.
959 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
961 * This error code is reported by Firmware when an operation requested
962 * by the host is not allowed due to a secure lock violation.
964 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
966 * This error code is reported by Firmware when an operation requested
967 * by a VF cannot be forwarded to the parent PF as required, either
968 * because the PF is down or otherwise doesn't have an appropriate
969 * async completion ring or associated forwarding buffers configured.
971 #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
973 * This value indicates that the HWRM response is in TLV format and
974 * should be interpreted as one or more TLVs starting with the
975 * hwrm_resp_hdr TLV. This value is not an indication of any error
976 * by itself, just an indication that the response should be parsed
977 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
979 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
981 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
982 /* Unsupported or invalid command */
983 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
984 #define HWRM_ERR_CODE_LAST \
985 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
986 uint16_t unused_0[3];
990 /* hwrm_err_output (size:128b/16B) */
991 struct hwrm_err_output {
993 * Pass/Fail or error type
995 * Note: receiver to verify the in parameters, and fail the call
996 * with an error when appropriate
999 /* This field returns the type of original request. */
1001 /* This field provides original sequence number of the command. */
1004 * This field is the length of the response in bytes. The
1005 * last byte of the response is a valid flag that will read
1006 * as '1' when the command has been completely written to
1010 /* debug info for this error response. */
1012 /* debug info for this error response. */
1015 * In the case of an error response, command specific error
1016 * code is returned in this field.
1020 * This field is used in Output records to indicate that the output
1021 * is completely written to RAM. This field should be read as '1'
1022 * to indicate that the output has been completely written.
1023 * When writing a command completion or response to an internal processor,
1024 * the order of writes has to be such that this field is written last.
1029 * Following is the signature for HWRM message field that indicates not
1030 * applicable (All F's). Need to cast it the size of the field if needed.
1032 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
1033 /* hwrm_func_buf_rgtr */
1034 #define HWRM_MAX_REQ_LEN 128
1035 /* hwrm_cfa_flow_info */
1036 #define HWRM_MAX_RESP_LEN 704
1037 /* 7 bit indirection table index. */
1038 #define HW_HASH_INDEX_SIZE 0x80
1039 #define HW_HASH_KEY_SIZE 40
1040 /* valid key for HWRM response */
1041 #define HWRM_RESP_VALID_KEY 1
1042 /* Reserved for BONO processor */
1043 #define HWRM_TARGET_ID_BONO 0xFFF8
1044 /* Reserved for KONG processor */
1045 #define HWRM_TARGET_ID_KONG 0xFFF9
1046 /* Reserved for APE processor */
1047 #define HWRM_TARGET_ID_APE 0xFFFA
1049 * This value will be used by tools for User-space HWRM Interface.
1050 * When tool execute any HWRM command with this target_id, firmware
1051 * will copy the response and/or data payload via register space instead
1054 #define HWRM_TARGET_ID_TOOLS 0xFFFD
1055 #define HWRM_VERSION_MAJOR 1
1056 #define HWRM_VERSION_MINOR 10
1057 #define HWRM_VERSION_UPDATE 2
1058 /* non-zero means beta version */
1059 #define HWRM_VERSION_RSVD 44
1060 #define HWRM_VERSION_STR "1.10.2.44"
1067 /* hwrm_ver_get_input (size:192b/24B) */
1068 struct hwrm_ver_get_input {
1069 /* The HWRM command request type. */
1072 * The completion ring to send the completion event on. This should
1073 * be the NQ ID returned from the `nq_alloc` HWRM command.
1077 * The sequence ID is used by the driver for tracking multiple
1078 * commands. This ID is treated as opaque data by the firmware and
1079 * the value is returned in the `hwrm_resp_hdr` upon completion.
1083 * The target ID of the command:
1084 * * 0x0-0xFFF8 - The function ID
1085 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1086 * * 0xFFFD - Reserved for user-space HWRM interface
1091 * A physical address pointer pointing to a host buffer that the
1092 * command's response data will be written. This can be either a host
1093 * physical address (HPA) or a guest physical address (GPA) and must
1094 * point to a physically contiguous block of memory.
1098 * This field represents the major version of HWRM interface
1099 * specification supported by the driver HWRM implementation.
1100 * The interface major version is intended to change only when
1101 * non backward compatible changes are made to the HWRM
1102 * interface specification.
1104 uint8_t hwrm_intf_maj;
1106 * This field represents the minor version of HWRM interface
1107 * specification supported by the driver HWRM implementation.
1108 * A change in interface minor version is used to reflect
1109 * significant backward compatible modification to HWRM
1110 * interface specification.
1111 * This can be due to addition or removal of functionality.
1112 * HWRM interface specifications with the same major version
1113 * but different minor versions are compatible.
1115 uint8_t hwrm_intf_min;
1117 * This field represents the update version of HWRM interface
1118 * specification supported by the driver HWRM implementation.
1119 * The interface update version is used to reflect minor
1120 * changes or bug fixes to a released HWRM interface
1123 uint8_t hwrm_intf_upd;
1124 uint8_t unused_0[5];
1127 /* hwrm_ver_get_output (size:1408b/176B) */
1128 struct hwrm_ver_get_output {
1129 /* The specific error status for the command. */
1130 uint16_t error_code;
1131 /* The HWRM command request type. */
1133 /* The sequence ID from the original command. */
1135 /* The length of the response data in number of bytes. */
1138 * This field represents the major version of HWRM interface
1139 * specification supported by the HWRM implementation.
1140 * The interface major version is intended to change only when
1141 * non backward compatible changes are made to the HWRM
1142 * interface specification.
1143 * A HWRM implementation that is compliant with this
1144 * specification shall provide value of 1 in this field.
1146 uint8_t hwrm_intf_maj_8b;
1148 * This field represents the minor version of HWRM interface
1149 * specification supported by the HWRM implementation.
1150 * A change in interface minor version is used to reflect
1151 * significant backward compatible modification to HWRM
1152 * interface specification.
1153 * This can be due to addition or removal of functionality.
1154 * HWRM interface specifications with the same major version
1155 * but different minor versions are compatible.
1156 * A HWRM implementation that is compliant with this
1157 * specification shall provide value of 2 in this field.
1159 uint8_t hwrm_intf_min_8b;
1161 * This field represents the update version of HWRM interface
1162 * specification supported by the HWRM implementation.
1163 * The interface update version is used to reflect minor
1164 * changes or bug fixes to a released HWRM interface
1166 * A HWRM implementation that is compliant with this
1167 * specification shall provide value of 2 in this field.
1169 uint8_t hwrm_intf_upd_8b;
1170 uint8_t hwrm_intf_rsvd_8b;
1172 * This field represents the major version of HWRM firmware.
1173 * A change in firmware major version represents a major
1176 uint8_t hwrm_fw_maj_8b;
1178 * This field represents the minor version of HWRM firmware.
1179 * A change in firmware minor version represents significant
1180 * firmware functionality changes.
1182 uint8_t hwrm_fw_min_8b;
1184 * This field represents the build version of HWRM firmware.
1185 * A change in firmware build version represents bug fixes
1186 * to a released firmware.
1188 uint8_t hwrm_fw_bld_8b;
1190 * This field is a reserved field. This field can be used to
1191 * represent firmware branches or customer specific releases
1192 * tied to a specific (major,minor,update) version of the
1195 uint8_t hwrm_fw_rsvd_8b;
1197 * This field represents the major version of mgmt firmware.
1198 * A change in major version represents a major release.
1200 uint8_t mgmt_fw_maj_8b;
1202 * This field represents the minor version of mgmt firmware.
1203 * A change in minor version represents significant
1204 * functionality changes.
1206 uint8_t mgmt_fw_min_8b;
1208 * This field represents the build version of mgmt firmware.
1209 * A change in update version represents bug fixes.
1211 uint8_t mgmt_fw_bld_8b;
1213 * This field is a reserved field. This field can be used to
1214 * represent firmware branches or customer specific releases
1215 * tied to a specific (major,minor,update) version
1217 uint8_t mgmt_fw_rsvd_8b;
1219 * This field represents the major version of network
1221 * A change in major version represents a major release.
1223 uint8_t netctrl_fw_maj_8b;
1225 * This field represents the minor version of network
1227 * A change in minor version represents significant
1228 * functionality changes.
1230 uint8_t netctrl_fw_min_8b;
1232 * This field represents the build version of network
1234 * A change in update version represents bug fixes.
1236 uint8_t netctrl_fw_bld_8b;
1238 * This field is a reserved field. This field can be used to
1239 * represent firmware branches or customer specific releases
1240 * tied to a specific (major,minor,update) version
1242 uint8_t netctrl_fw_rsvd_8b;
1244 * This field is used to indicate device's capabilities and
1247 uint32_t dev_caps_cfg;
1249 * If set to 1, then secure firmware update behavior
1251 * If set to 0, then secure firmware update behavior is
1254 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1257 * If set to 1, then firmware based DCBX agent is supported.
1258 * If set to 0, then firmware based DCBX agent capability
1259 * is not supported on this device.
1261 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1264 * If set to 1, then HWRM short command format is supported.
1265 * If set to 0, then HWRM short command format is not supported.
1267 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1270 * If set to 1, then HWRM short command format is required.
1271 * If set to 0, then HWRM short command format is not required.
1273 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1276 * If set to 1, then the KONG host mailbox channel is supported.
1277 * If set to 0, then the KONG host mailbox channel is not supported.
1278 * By default, this flag should be 0 for older version of core firmware.
1280 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1283 * If set to 1, then the 64bit flow handle is supported in addition to the
1284 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1285 * supported. By default, this flag should be 0 for older version of core firmware.
1287 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1290 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1291 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1292 * If set to 0, then filter types not supported.
1293 * By default, this flag should be 0 for older version of core firmware.
1295 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1298 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1299 * If set to 0, firmware can't supported virtio vSwitch offload model.
1300 * By default, this flag should be 0 for older version of core firmware.
1302 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1305 * If set to 1, firmware is capable to support trusted VF.
1306 * If set to 0, firmware is not capable to support trusted VF.
1307 * By default, this flag should be 0 for older version of core firmware.
1309 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1312 * If set to 1, firmware is capable to support flow aging.
1313 * If set to 0, firmware is not capable to support flow aging.
1314 * By default, this flag should be 0 for older version of core firmware.
1316 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1319 * If set to 1, firmware is capable to support advanced flow counters like,
1320 * Meter drop counters and EEM counters.
1321 * If set to 0, firmware is not capable to support advanced flow counters.
1322 * By default, this flag should be 0 for older version of core firmware.
1324 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1327 * If set to 1, the firmware is able to support the use of the CFA
1328 * Extended Exact Match(EEM) feature.
1329 * If set to 0, firmware is not capable to support the use of the
1331 * By default, this flag should be 0 for older version of core firmware.
1333 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1336 * If set to 1, the firmware is able to support advance CFA flow management
1337 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1338 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1340 * By default, this flag should be 0 for older version of core firmware.
1342 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1345 * Deprecated and replaced with cfa_truflow_supported.
1346 * If set to 1, the firmware is able to support TFLIB features.
1347 * If set to 0, then the firmware doesn’t support TFLIB features.
1348 * By default, this flag should be 0 for older version of core firmware.
1350 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1353 * If set to 1, the firmware is able to support TruFlow features.
1354 * If set to 0, then the firmware doesn’t support TruFlow features.
1355 * By default, this flag should be 0 for older version of
1358 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1361 * This field represents the major version of RoCE firmware.
1362 * A change in major version represents a major release.
1364 uint8_t roce_fw_maj_8b;
1366 * This field represents the minor version of RoCE firmware.
1367 * A change in minor version represents significant
1368 * functionality changes.
1370 uint8_t roce_fw_min_8b;
1372 * This field represents the build version of RoCE firmware.
1373 * A change in update version represents bug fixes.
1375 uint8_t roce_fw_bld_8b;
1377 * This field is a reserved field. This field can be used to
1378 * represent firmware branches or customer specific releases
1379 * tied to a specific (major,minor,update) version
1381 uint8_t roce_fw_rsvd_8b;
1383 * This field represents the name of HWRM FW (ASCII chars
1384 * with NULL at the end).
1386 char hwrm_fw_name[16];
1388 * This field represents the name of mgmt FW (ASCII chars
1389 * with NULL at the end).
1391 char mgmt_fw_name[16];
1393 * This field represents the name of network control
1394 * firmware (ASCII chars with NULL at the end).
1396 char netctrl_fw_name[16];
1397 /* This field represents the active board package name. */
1398 char active_pkg_name[16];
1400 * This field represents the name of RoCE FW (ASCII chars
1401 * with NULL at the end).
1403 char roce_fw_name[16];
1404 /* This field returns the chip number. */
1406 /* This field returns the revision of chip. */
1408 /* This field returns the chip metal number. */
1410 /* This field returns the bond id of the chip. */
1411 uint8_t chip_bond_id;
1412 /* This value indicates the type of platform used for chip implementation. */
1413 uint8_t chip_platform_type;
1415 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1416 /* FPGA platform of the chip. */
1417 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1418 /* Palladium platform of the chip. */
1419 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1420 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1421 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1423 * This field returns the maximum value of request window that
1424 * is supported by the HWRM. The request window is mapped
1425 * into device address space using MMIO.
1427 uint16_t max_req_win_len;
1429 * This field returns the maximum value of response buffer in
1432 uint16_t max_resp_len;
1434 * This field returns the default request timeout value in
1437 uint16_t def_req_timeout;
1439 * This field will indicate if any subsystems is not fully
1444 * If set to 1, it will indicate to host drivers that firmware is
1445 * not ready to start full blown HWRM commands. Host drivers should
1446 * re-try HWRM_VER_GET with some timeout period. The timeout period
1447 * can be selected up to 5 seconds. Host drivers should also check
1448 * for dev_not_rdy_backing_store to identify if flag is set due to
1449 * backing store not been available.
1450 * For Example, PCIe hot-plug:
1451 * Hot plug timing is system dependent. It generally takes up to
1452 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1453 * If set to 0, device is ready to accept all HWRM commands.
1455 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
1458 * If set to 1, external version present.
1459 * If set to 0, external version not present.
1461 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
1464 * Firmware sets this flag along with dev_not_rdy flag to indicate
1465 * host drivers that it has not completed resource initialization
1466 * required for data path operations. Host drivers should not send
1467 * any HWRM command that requires data path resources. Firmware will
1468 * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
1469 * those commands once both the flags are cleared.
1470 * If this flag and dev_not_rdy flag are set to 0, device is ready
1471 * to accept all HWRM commands.
1473 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
1475 uint8_t unused_0[2];
1477 * For backward compatibility this field must be set to 1.
1478 * Older drivers might look for this field to be 1 before
1479 * processing the message.
1483 * This field represents the major version of HWRM interface
1484 * specification supported by the HWRM implementation.
1485 * The interface major version is intended to change only when
1486 * non backward compatible changes are made to the HWRM
1487 * interface specification. A HWRM implementation that is
1488 * compliant with this specification shall provide value of 1
1491 uint16_t hwrm_intf_major;
1493 * This field represents the minor version of HWRM interface
1494 * specification supported by the HWRM implementation.
1495 * A change in interface minor version is used to reflect
1496 * significant backward compatible modification to HWRM
1497 * interface specification. This can be due to addition or
1498 * removal of functionality. HWRM interface specifications
1499 * with the same major version but different minor versions are
1500 * compatible. A HWRM implementation that is compliant with
1501 * this specification shall provide value of 2 in this field.
1503 uint16_t hwrm_intf_minor;
1505 * This field represents the update version of HWRM interface
1506 * specification supported by the HWRM implementation. The
1507 * interface update version is used to reflect minor changes or
1508 * bug fixes to a released HWRM interface specification.
1509 * A HWRM implementation that is compliant with this
1510 * specification shall provide value of 2 in this field.
1512 uint16_t hwrm_intf_build;
1514 * This field represents the patch version of HWRM interface
1515 * specification supported by the HWRM implementation.
1517 uint16_t hwrm_intf_patch;
1519 * This field represents the major version of HWRM firmware.
1520 * A change in firmware major version represents a major
1523 uint16_t hwrm_fw_major;
1525 * This field represents the minor version of HWRM firmware.
1526 * A change in firmware minor version represents significant
1527 * firmware functionality changes.
1529 uint16_t hwrm_fw_minor;
1531 * This field represents the build version of HWRM firmware.
1532 * A change in firmware build version represents bug fixes to
1533 * a released firmware.
1535 uint16_t hwrm_fw_build;
1537 * This field is a reserved field.
1538 * This field can be used to represent firmware branches or customer
1539 * specific releases tied to a specific (major,minor,update) version
1540 * of the HWRM firmware.
1542 uint16_t hwrm_fw_patch;
1544 * This field represents the major version of mgmt firmware.
1545 * A change in major version represents a major release.
1547 uint16_t mgmt_fw_major;
1549 * This field represents the minor version of HWRM firmware.
1550 * A change in firmware minor version represents significant
1551 * firmware functionality changes.
1553 uint16_t mgmt_fw_minor;
1555 * This field represents the build version of mgmt firmware.
1556 * A change in update version represents bug fixes.
1558 uint16_t mgmt_fw_build;
1560 * This field is a reserved field. This field can be used to
1561 * represent firmware branches or customer specific releases
1562 * tied to a specific (major,minor,update) version.
1564 uint16_t mgmt_fw_patch;
1566 * This field represents the major version of network control
1567 * firmware. A change in major version represents
1570 uint16_t netctrl_fw_major;
1572 * This field represents the minor version of network control
1573 * firmware. A change in minor version represents significant
1574 * functionality changes.
1576 uint16_t netctrl_fw_minor;
1578 * This field represents the build version of network control
1579 * firmware. A change in update version represents bug fixes.
1581 uint16_t netctrl_fw_build;
1583 * This field is a reserved field. This field can be used to
1584 * represent firmware branches or customer specific releases
1585 * tied to a specific (major,minor,update) version
1587 uint16_t netctrl_fw_patch;
1589 * This field represents the major version of RoCE firmware.
1590 * A change in major version represents a major release.
1592 uint16_t roce_fw_major;
1594 * This field represents the minor version of RoCE firmware.
1595 * A change in minor version represents significant
1596 * functionality changes.
1598 uint16_t roce_fw_minor;
1600 * This field represents the build version of RoCE firmware.
1601 * A change in update version represents bug fixes.
1603 uint16_t roce_fw_build;
1605 * This field is a reserved field. This field can be used to
1606 * represent firmware branches or customer specific releases
1607 * tied to a specific (major,minor,update) version
1609 uint16_t roce_fw_patch;
1611 * This field returns the maximum extended request length acceptable
1612 * by the device which allows requests greater than mailbox size when
1613 * used with the short cmd request format.
1615 uint16_t max_ext_req_len;
1617 * This field returns the maximum request timeout value in seconds.
1618 * For backward compatibility, a value of zero should be interpreted
1619 * as the default value of 40 seconds. Drivers should always honor the
1620 * maximum timeout, but are permitted to warn if a longer duration than
1621 * this default is advertised. Values larger than 40 seconds should
1622 * only be used as a stopgap measure to address a device limitation or
1623 * for the purposes of test and debugging. The long term goal is for
1624 * firmware to significantly reduce this value in the passage of time.
1626 uint16_t max_req_timeout;
1627 uint8_t unused_1[3];
1629 * This field is used in Output records to indicate that the output
1630 * is completely written to RAM. This field should be read as '1'
1631 * to indicate that the output has been completely written.
1632 * When writing a command completion or response to an internal processor,
1633 * the order of writes has to be such that this field is written last.
1638 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1639 struct cfa_bds_read_cmd_data_msg {
1640 /* This value selects the format for the mid-path command for the CFA. */
1643 * This is read command. From 32 to 128B can be read from a table
1644 * using this command.
1646 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1647 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1648 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1649 /* This value selects the table type to be acted upon. */
1651 /* This value selects the table type to be acted upon. */
1652 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1653 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1654 /* This command acts on the action table of the specified scope. */
1655 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1656 /* This command acts on the exact match table of the specified scope. */
1657 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1658 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1659 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1660 /* This value selects which table scope will be accessed. */
1661 uint8_t table_scope;
1662 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1663 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1665 * This value identifies the number of 32B units will be accessed. A
1666 * value of zero is invalid. Maximum value is 4.
1669 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1670 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1671 /* This is the 32B index into the selected table to access. */
1672 uint32_t table_index;
1673 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1674 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1676 * This is the 64b host address where you want the data returned to. The
1677 * data will be written to the same function as the one that owns the SQ
1678 * this command is read from. The bottom two bits of this value must be
1679 * zero. The size of the write is controlled by the data_size field.
1681 uint64_t host_address;
1684 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1685 struct cfa_bds_write_cmd_data_msg {
1686 /* This value selects the format for the mid-path command for the CFA. */
1689 * This is write command. From 32 to 128B can be written to a table
1690 * using this command.
1692 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1693 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1694 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1695 /* This value selects the table type to be acted upon. */
1696 uint8_t write_thru_table_type;
1697 /* This value selects the table type to be acted upon. */
1698 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1699 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1700 /* This command acts on the action table of the specified scope. */
1701 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1702 /* This command acts on the exact match table of the specified scope. */
1703 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1704 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1705 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1707 * Indicates write-through control. Indicates write-through when set,
1708 * or write back when cleared.
1710 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1711 /* This value selects which table scope will be accessed. */
1712 uint8_t table_scope;
1713 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1714 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1716 * This value identifies the number of 32B units will be accessed. A
1717 * value of zero is invalid. Maximum value is 4.
1720 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1721 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1722 /* This is the 32B index into the selected table to access. */
1723 uint32_t table_index;
1724 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1725 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1729 * This is the data to be written. Data length is determined by the
1730 * data_size field. The bd_cnt in the encapsulating BD must also be set
1731 * correctly to ensure that the BD is processed correctly and the full
1732 * WRITE_CMD message is extracted from the BD.
1737 /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
1738 struct cfa_bds_read_clr_cmd_data_msg {
1739 /* This value selects the format for the mid-path command for the CFA. */
1742 * This is read-clear command. 32B can be read from a table and
1743 * a 16b mask can be used to clear specific 16b units after the
1744 * read as an atomic operation.
1746 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1747 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1748 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1749 /* This value selects the table type to be acted upon. */
1751 /* This value selects the table type to be acted upon. */
1752 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1753 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1754 /* This command acts on the action table of the specified scope. */
1755 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1756 /* This command acts on the exact match table of the specified scope. */
1757 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1758 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1759 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1760 /* This value selects which table scope will be accessed. */
1761 uint8_t table_scope;
1762 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1763 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1765 * This value identifies the number of 32B units will be accessed.
1766 * Always set the value to 1.
1769 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1770 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
1771 /* This is the 32B index into the selected table to access. */
1772 uint32_t table_index;
1773 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1775 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1777 * This is the 64b host address where you want the data returned to. The
1778 * data will be written to the same function as the one that owns the SQ
1779 * this command is read from. The bottom two bits of this value must be
1780 * zero. The size of the write is controlled by the data_size field.
1782 uint64_t host_address;
1784 * This is active high clear mask for the 32B of data that this command
1785 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1786 * of data read when set to '1'.
1788 uint16_t clear_mask;
1789 uint16_t unused0[3];
1790 uint16_t unused1[4];
1793 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1794 struct cfa_bds_em_insert_cmd_data_msg {
1795 /* This value selects the format for the mid-path command for the CFA. */
1798 * An exact match table insert will be attempted into the table.
1799 * If there is a free location in the bucket, the payload will
1800 * be written to the bucket.
1802 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1803 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1804 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1806 * Indicates write-through control. Indicates write-through when set,
1807 * or write back when cleared.
1810 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1811 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1813 * Indicates write-through control. Indicates write-through when set,
1814 * or write back when cleared.
1816 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1817 /* This value selects which table scope will be accessed. */
1818 uint8_t table_scope;
1819 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1820 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1822 * This value identifies the number of 32B units will be accessed. A
1823 * value of zero is invalid. Maximum value is 4.
1826 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1827 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1828 /* This is the 32B index into the selected table to access. */
1829 uint32_t table_index;
1830 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1832 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1834 * This is the 64b host address where you want the data returned to. The
1835 * data will be written to the same function as the one that owns the SQ
1837 uint64_t host_address;
1839 * This is the Exact Match Lookup Record. Data length is determined by
1840 * the data_size field. The bd_cnt in the encapsulating BD must also be
1845 /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
1846 struct cfa_bds_em_delete_cmd_data_msg {
1847 /* This value selects the format for the mid-path command for the CFA. */
1849 /* An exact match table delete will be attempted. */
1850 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1851 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1852 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1854 * Indicates write-through control. Indicates write-through when set,
1855 * or write back when cleared.
1858 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1859 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1861 * Indicates write-through control. Indicates write-through when set,
1862 * or write back when cleared.
1864 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1865 /* This value selects which table scope will be accessed. */
1866 uint8_t table_scope;
1867 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1868 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1870 * This value identifies the number of 32B units will be accessed. A
1871 * value of zero is invalid. Maximum value is 4.
1874 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1875 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1878 * This is the 64b host address where you want the data returned to. The
1879 * data will be written to the same function as the one that owns the SQ
1881 uint64_t host_address;
1883 * This is the Exact Match Lookup Record. Data length is determined by
1884 * the data_size field. The bd_cnt in the encapsulating BD must also be
1887 uint32_t unused1[2];
1890 /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
1891 struct cfa_bds_invalidate_cmd_data_msg {
1892 /* This value selects the format for the mid-path command for the CFA. */
1895 * The specified table area will be invalidated. If it is needed.
1896 * again, it will be read from the backing store.
1898 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1899 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1900 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1901 /* This value selects the table type to be acted upon. */
1903 /* This value selects the table type to be acted upon. */
1904 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1905 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1906 /* This command acts on the action table of the specified scope. */
1907 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1909 /* This command acts on the exact match table of the specified scope. */
1910 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1912 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1913 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1914 /* This value selects which table scope will be accessed. */
1915 uint8_t table_scope;
1916 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1917 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1918 /* This value specifies the number of cache lines to invalidate. */
1920 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1921 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1922 /* This is the 32B index into the selected table to access. */
1923 uint32_t table_index;
1924 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1926 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1930 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1931 struct cfa_bds_event_collect_cmd_data_msg {
1932 /* This value selects the format for the mid-path command for the CFA. */
1934 /* Reads notification messages from the Host Notification Queue. */
1935 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1937 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1938 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1940 /* This value selects which table scope will be accessed. */
1941 uint8_t table_scope;
1942 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1944 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1946 * This value identifies the number of 32B units will be accessed. A
1947 * value of zero is invalid. Maximum value is 4.
1950 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1951 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1954 * This is the 64b host address where you want the data returned to. The
1955 * data will be written to the same function as the one that owns the SQ
1957 uint64_t host_address;
1960 /* ce_bds_add_data_msg (size:512b/64B) */
1961 struct ce_bds_add_data_msg {
1962 uint32_t version_algorithm_kid_opcode;
1964 * This value selects the operation for the mid-path command for the
1967 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1968 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
1970 * This is the add command. Using this opcode, Host Driver can add
1971 * information required for kTLS processing. The information is
1972 * updated in the CFCK context.
1974 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
1975 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
1976 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
1978 * This field is the Crypto Context ID. The KID is used to store
1979 * information used by the associated kTLS offloaded connection.
1981 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
1983 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
1985 * Currently only two algorithms are supported, AES_GCM_128 and
1986 * AES_GCM_256. Additional bits for future growth.
1988 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
1990 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
1991 /* AES_GCM_128 Algorithm */
1992 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
1994 /* AES_GCM_256 Algorithm */
1995 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
1998 * Version number of TLS connection. HW will provide registers that
1999 * converts the 4b encoded version number to 16b of actual version
2000 * number in the TLS Header. * Initialized --> By mid-path command *
2001 * Updated --> Never though another mid-path command will result in an
2004 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
2005 UINT32_C(0xf0000000)
2006 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
2007 /* TLS1.2 Version */
2008 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
2009 (UINT32_C(0x0) << 28)
2010 /* TLS1.3 Version */
2011 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
2012 (UINT32_C(0x1) << 28)
2013 #define CE_BDS_ADD_DATA_MSG__LAST \
2014 CE_BDS_ADD_DATA_MSG__TLS1_3
2016 * Command Type in the TLS header. HW will provide registers that
2017 * converts the 3b encoded command type to 8b of actual command type in
2018 * the TLS Header. * Initialized --> By mid-path command * Updated -->
2019 * Never though another mid-path command will result in an update
2022 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
2023 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
2025 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
2026 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
2027 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
2030 * Salt is part of the nonce that is used as the Initial Vector (IV) in
2031 * AES-GCM cipher suites. These are exchanged as part of the handshake
2032 * process and is either the client_write_iv (when the client is
2033 * sending) or server_write_iv (when the server is sending). In
2034 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
2035 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
2036 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
2037 * the 12B of IV. This value is initialized by this mid-path command.
2042 * This field keeps track of the TCP sequence number that is expected as
2043 * the first byte in the next TCP packet. This field is calculated by HW
2044 * using the output of the parser. The field is initialized as part of
2045 * the Mid-path BD download/update of a kTLS connection. For every TCP
2046 * packet processed, TCE HW will update the value to Current packet TCP
2047 * sequence number + Current packet TCP Payload Length.
2049 uint32_t pkt_tcp_seq_num;
2051 * This field maintains the TCP sequence number of the first byte in the
2052 * header of the active TLS record. This field is initialized as part of
2053 * the Mid-path BD download/update of a kTLS connection. For every
2054 * record that is processed, TCE HW copies the value from the
2055 * next_tls_header_tcp_seq_num field.
2057 uint32_t tls_header_tcp_seq_num;
2059 * This is sequence number for the TLS record in a particular session.
2060 * In TLS1.2, record sequence number is part of the Associated Data (AD)
2061 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
2062 * the Initial Vector (IV). The field is initialized as part of the
2063 * mid-path BD download/update of a kTLS connection. TCE HW increments
2064 * the field after that for every record processed as it parses the TCP
2067 uint32_t record_seq_num[2];
2069 * Key used for encrypting or decrypting TLS records. The Key is
2070 * exchanged during the hand-shake protocol by the client-server and
2071 * provided to HW through this mid-path BD.
2073 uint32_t session_key[8];
2076 /* ce_bds_delete_data_msg (size:64b/8B) */
2077 struct ce_bds_delete_data_msg {
2078 uint32_t kid_opcode;
2080 * This value selects the operation for the mid-path command for the
2083 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2084 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2086 * This is the delete command. Using this opcode, the host Driver
2087 * can remove a key context from the CFCK. If context is deleted
2088 * and packets with the same KID come through the pipeline, the
2089 * following actions are taken. For transmit packets, no crypto
2090 * operation will be performed, payload will be zero'ed out. For
2091 * receive packets, no crypto operation will be performed,
2092 * payload will be unmodified.
2094 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2095 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
2096 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
2098 * This field is the Crypto Context ID. The KID is used to store
2099 * information used by the associated kTLS offloaded connection.
2101 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2102 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
2106 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
2107 struct ce_bds_resync_resp_ack_msg {
2108 uint32_t resync_status_kid_opcode;
2110 * This value selects the operation for the mid-path command for the
2113 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2114 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2116 * This command is used by the driver as a response to the resync
2117 * request sent by the crypto engine.
2119 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2120 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
2121 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
2123 * This field is the Crypto Context ID. The KID is used to store
2124 * information used by the associated kTLS offloaded connection.
2126 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2127 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
2129 * This field indicates if the resync request resulted in a success or
2132 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2135 * An ACK indicates that the driver was able to find the TLS record
2136 * associated with TCP sequence number provided by the HW
2138 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2139 (UINT32_C(0x0) << 24)
2140 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2141 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2143 * This field is the echo of the TCP sequence number provided in the
2144 * resync request by the HW. If HW sent multiple resync requests, it
2145 * only tracks the latest TCP sequence number. When the response from
2146 * the Driver doesn't match the latest request, HW will drop the resync
2149 uint32_t resync_record_tcp_seq_num;
2151 * This field indicates the TLS record sequence number associated with
2152 * the resync request. HW will take this number and add the delta records
2153 * it has found since sending the resync request, update the context and
2154 * resume decrypting records.
2156 uint32_t resync_record_seq_num[2];
2159 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2160 struct ce_bds_resync_resp_nack_msg {
2161 uint32_t resync_status_kid_opcode;
2163 * This value selects the operation for the mid-path command for the
2166 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2167 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2169 * This command is used by the driver as a response to the resync
2170 * request sent by the crypto engine.
2172 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2173 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2174 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2176 * This field is the Crypto Context ID. The KID is used to store
2177 * information used by the associated kTLS offloaded connection.
2179 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2181 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2183 * This field indicates if the resync request resulted in a success or
2186 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2189 * An NAK indicates that the driver wasn't able to find the TLS
2190 * record associated with TCP sequence number provided by the HW
2192 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2193 (UINT32_C(0x1) << 24)
2194 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2195 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2197 * This field is the echo of the TCP sequence number provided in the
2198 * resync request by the HW. If HW sent multiple resync requests, it
2199 * only tracks the latest TCP sequence number. When the response from
2200 * the Driver doesn't match the latest request, HW will drop the resync
2203 uint32_t resync_record_tcp_seq_num;
2206 /* crypto_presync_bd_cmd (size:256b/32B) */
2207 struct crypto_presync_bd_cmd {
2210 * Typically, presync BDs are used for packet retransmissions. Source
2211 * port sends all the packets in order over the network to destination
2212 * port and packets get dropped in the network. The destination port
2213 * will request retranmission of dropped packets and source port driver
2214 * will send presync BD to setup the transmitter appropriately. It will
2215 * provide the start and end TCP sequence number of the data to be
2216 * transmitted. HW keeps two sets of context variable, one for in order
2217 * traffic and one for retransmission traffic. HW is designed to
2218 * transmit everything posted in the presync BD and return to in order
2219 * mode after that. No inorder context variables are updated in the
2220 * process. There is a special case where packets can be dropped
2221 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2222 * ex) and HW still needs to transmit rest of the traffic. In this
2223 * mode, driver will send a presync BD as if it is a retransmission but
2224 * at the end of the transmission, the in order variables need to be
2225 * updated. This flag is used by driver to indicate that in order
2226 * variables needs to be updated at the end of completing the task
2227 * associated with the presync BD.
2229 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2234 * This field maintains the TCP sequence number of the first byte in the
2235 * Header of the active TLS record. This field is set to 0 during
2236 * mid-path BD updates, but is set to correct value when a presync BD is
2237 * detected. For every record that is processed, the value from the
2238 * next_tls_header_tcp_seq_num field is copied.
2240 uint32_t header_tcp_seq_num;
2242 * When a retransmitted packet has a TLS authentication TAG present and
2243 * the data spans multiple TCP Packets, HW is required to read the entire
2244 * record to recalculate the TAG but only transmit what is required. This
2245 * field is the start TCP sequence number of the packet(s) that need to
2246 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2247 * add command and initialized to value provided by the driver when
2248 * Pre-sync BD is detected. This field is never updated unless another
2249 * Pre-sync BD signaling a new retransmission is scheduled.
2251 uint32_t start_tcp_seq_num;
2253 * When a retransmitted packet has a TLS authentication TAG present and
2254 * the data spans multiple TCP Packets, HW is required to read the
2255 * entire record to recalculate the TAG but only transmit what is
2256 * required. This field is the end TCP sequence number of the packet(s)
2257 * that need to be re-transmitted. This field is initialized to 0 during
2258 * Mid-path BD add command and initialized to value provided by the
2259 * driver when Pre-sync BD is detected. This field is never updated
2260 * unless another Pre-sync BD signaling a new retransmission is
2263 uint32_t end_tcp_seq_num;
2265 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2266 * with the SALT). For retans packets, this field is extracted from the
2267 * TLS record, field right after the TLS Header and stored in the
2268 * context. This field needs to be stored in context as TCP segmentation
2269 * could have split the field into multiple TCP packets. This value is
2270 * initialized to 0 when presync BD is detected by taking the value from
2271 * the first TLS header. When subsequent TLS Headers are detected, the
2272 * value is extracted from packet.
2274 uint32_t explicit_nonce[2];
2276 * This is sequence number for the TLS record in a particular session. In
2277 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2278 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2279 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2280 * download. Is initialized to correct value when a pre-sync BD is
2281 * detected. TCE HW increments the field after that for every record
2282 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2283 * delivering more retransmission instruction will also update this
2286 uint32_t record_seq_num[2];
2289 /* bd_base (size:64b/8B) */
2292 /* This value identifies the type of buffer descriptor. */
2293 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2294 #define BD_BASE_TYPE_SFT 0
2296 * Indicates that this BD is 16B long and is used for
2297 * normal L2 packet transmission.
2299 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2301 * Indicates that this BD is 1BB long and is an empty
2302 * TX BD. Not valid for use by the driver.
2304 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2306 * Indicates that this BD is 16B long and is an RX Producer
2307 * (i.e. empty) buffer descriptor.
2309 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2311 * Indicates that this BD is 16B long and is an RX
2312 * Producer Buffer BD.
2314 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2316 * Indicates that this BD is 16B long and is an
2317 * RX Producer Assembly Buffer Descriptor.
2319 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2321 * Indicates that this BD is used to issue a command to one of
2322 * the mid-path destinations.
2324 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2326 * Indicates that this BD is used to issue a cryptographic pre-
2327 * sync command through the fast path and destined for TCE.
2329 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2331 * Indicates that this BD is 32B long and is used for
2332 * normal L2 packet transmission.
2334 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2336 * Indicates that this BD is 32B long and is used for
2337 * L2 packet transmission for small packets that require
2340 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2341 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2342 uint8_t unused_1[7];
2345 /* tx_bd_short (size:128b/16B) */
2346 struct tx_bd_short {
2348 * All bits in this field must be valid on the first BD of a packet.
2349 * Only the packet_end bit must be valid for the remaining BDs
2352 uint16_t flags_type;
2353 /* This value identifies the type of buffer descriptor. */
2354 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2355 #define TX_BD_SHORT_TYPE_SFT 0
2357 * Indicates that this BD is 16B long and is used for
2358 * normal L2 packet transmission.
2360 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2361 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2363 * All bits in this field must be valid on the first BD of a packet.
2364 * Only the packet_end bit must be valid for the remaining BDs
2367 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2368 #define TX_BD_SHORT_FLAGS_SFT 6
2370 * If set to 1, the packet ends with the data in the buffer
2371 * pointed to by this descriptor. This flag must be
2372 * valid on every BD.
2374 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2376 * If set to 1, the device will not generate a completion for
2377 * this transmit packet unless there is an error in it's
2380 * is set to 0, then the packet will be completed normally.
2382 * This bit must be valid only on the first BD of a packet.
2384 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2386 * This value indicates how many 16B BD locations are consumed
2387 * in the ring by this packet.
2388 * A value of 1 indicates that this BD is the only BD (and that
2389 * it is a short BD). A value
2390 * of 3 indicates either 3 short BDs or 1 long BD and one short
2391 * BD in the packet. A value of 0 indicates
2392 * that there are 32 BD locations in the packet (the maximum).
2394 * This field is valid only on the first BD of a packet.
2396 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2397 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2399 * This value is a hint for the length of the entire packet.
2400 * It is used by the chip to optimize internal processing.
2402 * The packet will be dropped if the hint is too short.
2404 * This field is valid only on the first BD of a packet.
2406 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2407 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2408 /* indicates packet length < 512B */
2409 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2410 /* indicates 512 <= packet length < 1KB */
2411 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2412 /* indicates 1KB <= packet length < 2KB */
2413 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2414 /* indicates packet length >= 2KB */
2415 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2416 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2417 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2419 * If set to 1, the device immediately updates the Send Consumer
2420 * Index after the buffer associated with this descriptor has
2421 * been transferred via DMA to NIC memory from host memory. An
2422 * interrupt may or may not be generated according to the state
2423 * of the interrupt avoidance mechanisms. If this bit
2424 * is set to 0, then the Consumer Index is only updated as soon
2425 * as one of the host interrupt coalescing conditions has been met.
2427 * This bit must be valid on the first BD of a packet.
2429 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2431 * This is the length of the host physical buffer this BD describes
2434 * This field must be valid on all BDs of a packet.
2438 * The opaque data field is pass through to the completion and can be
2439 * used for any data that the driver wants to associate with the
2442 * This field must be valid on the first BD of a packet. If completion
2443 * coalescing is enabled on the TX ring, it is suggested that the driver
2444 * populate the opaque field to indicate the specific TX ring with which
2445 * the completion is associated, then utilize the opaque and sq_cons_idx
2446 * fields in the coalesced completion record to determine the specific
2447 * packets that are to be completed on that ring.
2451 * This is the host physical address for the portion of the packet
2452 * described by this TX BD.
2454 * This value must be valid on all BDs of a packet.
2459 /* tx_bd_long (size:128b/16B) */
2461 /* This value identifies the type of buffer descriptor. */
2462 uint16_t flags_type;
2464 * This value indicates the type of buffer descriptor.
2467 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2468 #define TX_BD_LONG_TYPE_SFT 0
2470 * Indicates that this BD is 32B long and is used for
2471 * normal L2 packet transmission.
2473 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2474 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2476 * All bits in this field must be valid on the first BD of a packet.
2477 * Only the packet_end bit must be valid for the remaining BDs
2480 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2481 #define TX_BD_LONG_FLAGS_SFT 6
2483 * If set to 1, the packet ends with the data in the buffer
2484 * pointed to by this descriptor. This flag must be
2485 * valid on every BD.
2487 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2489 * If set to 1, the device will not generate a completion for
2490 * this transmit packet unless there is an error in it's
2493 * is set to 0, then the packet will be completed normally.
2495 * This bit must be valid only on the first BD of a packet.
2497 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2499 * This value indicates how many 16B BD locations are consumed
2500 * in the ring by this packet.
2501 * A value of 1 indicates that this BD is the only BD (and that
2502 * it is a short BD). A value
2503 * of 3 indicates either 3 short BDs or 1 long BD and one short
2504 * BD in the packet. A value of 0 indicates
2505 * that there are 32 BD locations in the packet (the maximum).
2507 * This field is valid only on the first BD of a packet.
2509 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2510 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2512 * This value is a hint for the length of the entire packet.
2513 * It is used by the chip to optimize internal processing.
2515 * The packet will be dropped if the hint is too short.
2517 * This field is valid only on the first BD of a packet.
2519 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2520 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2521 /* indicates packet length < 512B */
2522 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2523 /* indicates 512 <= packet length < 1KB */
2524 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2525 /* indicates 1KB <= packet length < 2KB */
2526 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2527 /* indicates packet length >= 2KB */
2528 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2529 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2531 * If set to 1, the device immediately updates the Send Consumer
2532 * Index after the buffer associated with this descriptor has
2533 * been transferred via DMA to NIC memory from host memory. An
2534 * interrupt may or may not be generated according to the state
2535 * of the interrupt avoidance mechanisms. If this bit
2536 * is set to 0, then the Consumer Index is only updated as soon
2537 * as one of the host interrupt coalescing conditions has been met.
2539 * This bit must be valid on the first BD of a packet.
2541 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2543 * This is the length of the host physical buffer this BD describes
2546 * This field must be valid on all BDs of a packet.
2550 * The opaque data field is passed through to the completion and can be
2551 * used for any data that the driver wants to associate with the
2554 * This field must be valid on the first BD of a packet. If completion
2555 * coalescing is enabled on the TX ring, it is suggested that the driver
2556 * populate the opaque field to indicate the specific TX ring with which
2557 * the completion is associated, then utilize the opaque and sq_cons_idx
2558 * fields in the coalesced completion record to determine the specific
2559 * packets that are to be completed on that ring.
2563 * This is the host physical address for the portion of the packet
2564 * described by this TX BD.
2566 * This value must be valid on all BDs of a packet.
2571 /* Last 16 bytes of tx_bd_long. */
2572 /* tx_bd_long_hi (size:128b/16B) */
2573 struct tx_bd_long_hi {
2575 * All bits in this field must be valid on the first BD of a packet.
2576 * Their value on other BDs of the packet will be ignored.
2580 * If set to 1, the controller replaces the TCP/UPD checksum
2581 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2582 * checksum field of the encapsulated TCP/UDP packets with the
2583 * hardware calculated TCP/UDP checksum for the packet associated
2584 * with this descriptor. The flag is ignored if the LSO flag is set.
2586 * This bit must be valid on the first BD of a packet.
2588 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2590 * If set to 1, the controller replaces the IP checksum of the
2591 * normal packets, or the inner IP checksum of the encapsulated
2592 * packets with the hardware calculated IP checksum for the
2593 * packet associated with this descriptor.
2595 * This bit must be valid on the first BD of a packet.
2597 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2599 * If set to 1, the controller will not append an Ethernet CRC
2600 * to the end of the frame.
2602 * This bit must be valid on the first BD of a packet.
2604 * Packet must be 64B or longer when this flag is set. It is not
2605 * useful to use this bit with any form of TX offload such as
2606 * CSO or LSO. The intent is that the packet from the host already
2607 * has a valid Ethernet CRC on the packet.
2609 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2611 * If set to 1, the device will record the time at which the packet
2612 * was actually transmitted at the TX MAC for 2-step time sync.
2614 * This bit must be valid on the first BD of a packet.
2616 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2618 * If set to 1, The controller replaces the tunnel IP checksum
2619 * field with hardware calculated IP checksum for the IP header
2620 * of the packet associated with this descriptor.
2622 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2623 * needs to be enabled. If the global outer UDP checksum TE_NIC register
2624 * bit is set, outer UDP checksum will be calculated for the following
2626 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
2627 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
2628 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
2629 * checksum will not be calculated.
2630 * 2. Packets with lso flag set which implies inner TCP checksum calculation
2631 * as part of LSO operation.
2633 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2635 * If set to 1, the device will treat this packet with LSO(Large
2636 * Send Offload) processing for both normal or encapsulated
2637 * packets, which is a form of TCP segmentation. When this bit
2638 * is 1, the hdr_size and mss fields must be valid. The driver
2639 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2640 * tcp_udp_chksum flags since the controller will replace the
2641 * appropriate checksum fields for segmented packets.
2643 * When this bit is 1, the hdr_size and mss fields must be valid.
2645 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2647 * If set to zero when LSO is '1', then the IPID will be treated
2648 * as a 16b number and will be wrapped if it exceeds a value of
2651 * If set to one when LSO is '1', then the IPID will be treated
2652 * as a 15b number and will be wrapped if it exceeds a value 0f
2655 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2657 * If set to zero when LSO is '1', then the IPID of the tunnel
2658 * IP header will not be modified during LSO operations.
2660 * If set to one when LSO is '1', then the IPID of the tunnel
2661 * IP header will be incremented for each subsequent segment of an
2664 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2667 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2669 * If set to '1', then the RoCE ICRC will be appended to the
2670 * packet. Packet must be a valid RoCE format packet.
2672 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2674 * If set to '1', then the FCoE CRC will be appended to the
2675 * packet. Packet must be a valid FCoE format packet.
2677 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2679 * If set to '1', then the timestamp from the BD is used. If cleared
2680 * to 0, then TWE provides the timestamp.
2682 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2684 * If set to '1', this operation will cause a trace capture in each
2685 * block it passes through.
2687 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2689 * If set to '1', the device will record the time at which the packet
2690 * was actually transmitted at the TX MAC for 1-step time sync. This
2691 * bit must be valid on the first BD of a packet.
2693 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2695 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2696 * field with hardware calculated IP checksum for the IP header of the
2697 * packet associated with this descriptor. For outer UDP checksum, it
2698 * will be the following behavior for all cases independent of settings
2699 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2700 * is 0, then do not update it. If outer UDP checksum is non zero, then
2701 * the hardware should compute and update it.
2703 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2705 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2706 * header will not be modified during LSO operations. If set to one
2707 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2708 * incremented for each subsequent segment of an LSO operation. The
2709 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2712 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2714 * If set to '1', When set to 1, KTLS encryption will be enabled for
2717 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2718 uint16_t kid_or_ts_low_hdr_size;
2720 * When LSO is '1', this field must contain the offset of the
2721 * TCP payload from the beginning of the packet in as
2722 * 16b words. In case of encapsulated/tunneling packet, this field
2723 * contains the offset of the inner TCP payload from beginning of the
2724 * packet as 16-bit words.
2726 * This value must be valid on the first BD of a packet.
2728 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2729 #define TX_BD_LONG_HDR_SIZE_SFT 0
2731 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2732 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
2735 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2736 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2737 uint32_t kid_or_ts_high_mss;
2739 * This is the MSS value that will be used to do the LSO processing.
2740 * The value is the length in bytes of the TCP payload for each
2741 * segment generated by the LSO operation.
2743 * This value must be valid on the first BD of a packet.
2745 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2746 #define TX_BD_LONG_MSS_SFT 0
2748 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2749 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2750 * of this field contain the upper 13 bits of the 20-bit KID.
2752 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2753 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2755 * This value selects bits 25:16 of the CFA action to perform on the
2756 * packet. See the cfa_action field for more information.
2758 uint16_t cfa_action_high;
2759 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2760 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2762 * This value selects a CFA action to perform on the packet.
2763 * Set this value to zero if no CFA action is desired.
2765 * This value must be valid on the first BD of a packet.
2767 uint16_t cfa_action;
2769 * This value is action meta-data that defines CFA edit operations
2770 * that are done in addition to any action editing.
2773 /* When key=1, This is the VLAN tag VID value. */
2774 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2775 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2776 /* When key=1, This is the VLAN tag DE value. */
2777 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2778 /* When key=1, This is the VLAN tag PRI value. */
2779 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2780 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2781 /* When key=1, This is the VLAN tag TPID select value. */
2782 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2783 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2785 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
2786 (UINT32_C(0x0) << 16)
2788 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
2789 (UINT32_C(0x1) << 16)
2791 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
2792 (UINT32_C(0x2) << 16)
2794 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
2795 (UINT32_C(0x3) << 16)
2797 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
2798 (UINT32_C(0x4) << 16)
2799 /* Value programmed in CFA VLANTPID register. */
2800 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
2801 (UINT32_C(0x5) << 16)
2802 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2803 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2804 /* When key=1, This is the VLAN tag TPID select value. */
2805 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2806 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2808 * This field identifies the type of edit to be performed
2811 * This value must be valid on the first BD of a packet.
2813 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2814 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2816 #define TX_BD_LONG_CFA_META_KEY_NONE \
2817 (UINT32_C(0x0) << 28)
2819 * - meta[17:16] - TPID select value (0 = 0x8100).
2820 * - meta[15:12] - PRI/DE value.
2821 * - meta[11:0] - VID value.
2823 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
2824 (UINT32_C(0x1) << 28)
2827 * - Wh+/SR - this option is not supported.
2828 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
2829 * is set in the Lookup Table.
2830 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
2831 * en_bd_meta is set in the Lookup Table.
2833 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
2834 (UINT32_C(0x2) << 28)
2835 #define TX_BD_LONG_CFA_META_KEY_LAST \
2836 TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
2840 * This structure is used to inform the NIC of packet data that needs to be
2841 * transmitted with additional processing that requires extra data such as
2842 * VLAN insertion plus attached inline data. This BD type may be used to
2843 * improve latency for small packets needing the additional extended features
2844 * supported by long BDs.
2846 /* tx_bd_long_inline (size:256b/32B) */
2847 struct tx_bd_long_inline {
2848 uint16_t flags_type;
2849 /* This value identifies the type of buffer descriptor. */
2850 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2851 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2853 * This type of BD is 32B long and is used for inline L2 packet
2856 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2857 #define TX_BD_LONG_INLINE_TYPE_LAST \
2858 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2860 * All bits in this field may be set on the first BD of a packet.
2861 * Only the packet_end bit may be set in non-first BDs.
2863 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2864 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2866 * If set to 1, the packet ends with the data in the buffer
2867 * pointed to by this descriptor. This flag must be
2868 * valid on every BD.
2870 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2872 * If set to 1, the device will not generate a completion for
2873 * this transmit packet unless there is an error in its processing.
2874 * If this bit is set to 0, then the packet will be completed
2877 * This bit may be set only on the first BD of a packet.
2879 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2881 * This value indicates how many 16B BD locations are consumed
2882 * in the ring by this packet, including the BD and inline
2885 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2886 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2887 /* This field is deprecated. */
2888 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2889 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2891 * If set to 1, the device immediately updates the Send Consumer
2892 * Index after the buffer associated with this descriptor has
2893 * been transferred via DMA to NIC memory from host memory. An
2894 * interrupt may or may not be generated according to the state
2895 * of the interrupt avoidance mechanisms. If this bit
2896 * is set to 0, then the Consumer Index is only updated as soon
2897 * as one of the host interrupt coalescing conditions has been met.
2899 * This bit must be valid on the first BD of a packet.
2901 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2903 * This is the length of the inline data, not including BD length, in
2905 * The maximum value is 480.
2907 * This field must be valid on all BDs of a packet.
2911 * The opaque data field is passed through to the completion and can be
2912 * used for any data that the driver wants to associate with the transmit
2913 * BD. This field must be valid on the first BD of a packet. If
2914 * completion coalescing is enabled on the TX ring, it is suggested that
2915 * the driver populate the opaque field to indicate the specific TX ring
2916 * with which the completion is associated, then utilize the opaque and
2917 * sq_cons_idx fields in the coalesced completion record to determine
2918 * the specific packets that are to be completed on that ring.
2920 * This field must be valid on the first BD of a packet.
2925 * All bits in this field must be valid on the first BD of a packet.
2926 * Their value on other BDs of the packet is ignored.
2930 * If set to 1, the controller replaces the TCP/UPD checksum
2931 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2932 * checksum field of the encapsulated TCP/UDP packets with the
2933 * hardware calculated TCP/UDP checksum for the packet associated
2934 * with this descriptor. The flag is ignored if the LSO flag is set.
2936 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2938 * If set to 1, the controller replaces the IP checksum of the
2939 * normal packets, or the inner IP checksum of the encapsulated
2940 * packets with the hardware calculated IP checksum for the
2941 * packet associated with this descriptor.
2943 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2945 * If set to 1, the controller will not append an Ethernet CRC
2946 * to the end of the frame.
2948 * Packet must be 64B or longer when this flag is set. It is not
2949 * useful to use this bit with any form of TX offload such as
2950 * CSO or LSO. The intent is that the packet from the host already
2951 * has a valid Ethernet CRC on the packet.
2953 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2955 * If set to 1, the device will record the time at which the packet
2956 * was actually transmitted at the TX MAC for 2-step time sync. This
2957 * bit must be valid on the first BD of a packet.
2959 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2961 * If set to 1, the controller replaces the tunnel IP checksum
2962 * field with hardware calculated IP checksum for the IP header
2963 * of the packet associated with this descriptor. The hardware
2964 * updates an outer UDP checksum if it is non-zero.
2966 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2968 * This bit must be 0 for BDs of this type. LSO is not supported with
2971 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2972 /* Since LSO is not supported with inline BDs, this bit is not used. */
2973 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2974 /* Since LSO is not supported with inline BDs, this bit is not used. */
2975 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2977 * If set to '1', then the RoCE ICRC will be appended to the
2978 * packet. Packet must be a valid RoCE format packet.
2980 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2982 * If set to '1', then the FCoE CRC will be appended to the
2983 * packet. Packet must be a valid FCoE format packet.
2985 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2987 * If set to '1', then the timestamp from the BD is used. If cleared
2988 * to 0, then TWE provides the timestamp.
2990 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
2992 * If set to '1', this operation will cause a trace capture in each
2993 * block it passes through.
2995 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2997 * If set to '1', the device will record the time at which the packet
2998 * was actually transmitted at the TX MAC for 1-step time sync. This
2999 * bit must be valid on the first BD of a packet.
3001 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
3003 * If set to '1', the controller replaces the Outer-tunnel IP checksum
3004 * field with hardware calculated IP checksum for the IP header of the
3005 * packet associated with this descriptor. For outer UDP checksum, it
3006 * will be the following behavior for all cases independent of settings
3007 * of inner LSO and checksum offload BD flags. If outer UDP checksum
3008 * is 0, then do not update it. If outer UDP checksum is non zero, then
3009 * the hardware should compute and update it.
3011 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
3013 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
3014 * header will not be modified during LSO operations. If set to one
3015 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
3016 * incremented for each subsequent segment of an LSO operation. The
3017 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
3020 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
3022 * If set to '1', When set to 1, KTLS encryption will be enabled for
3025 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
3027 uint8_t kid_or_ts_low;
3028 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
3030 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
3031 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
3034 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
3035 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
3036 uint32_t kid_or_ts_high;
3037 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
3038 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
3040 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
3041 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
3042 * of this field contain the upper 13 bits of the 20-bit KID.
3044 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3045 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
3047 * This value selects bits 25:16 of the CFA action to perform on the
3048 * packet. See the cfa_action field for more information.
3050 uint16_t cfa_action_high;
3051 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3052 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
3054 * This value selects a CFA action to perform on the packet.
3055 * Set this value to zero if no CFA action is desired.
3057 * This value must be valid on the first BD of a packet.
3059 uint16_t cfa_action;
3061 * This value is action meta-data that defines CFA edit operations
3062 * that are done in addition to any action editing.
3065 /* When key = 1, this is the VLAN tag VID value. */
3066 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3067 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
3068 /* When key = 1, this is the VLAN tag DE value. */
3069 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
3071 /* When key = 1, this is the VLAN tag PRI value. */
3072 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
3074 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
3075 /* When key = 1, this is the VLAN tag TPID select value. */
3076 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
3078 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
3080 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
3081 (UINT32_C(0x0) << 16)
3083 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
3084 (UINT32_C(0x1) << 16)
3086 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
3087 (UINT32_C(0x2) << 16)
3089 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
3090 (UINT32_C(0x3) << 16)
3092 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
3093 (UINT32_C(0x4) << 16)
3094 /* Value programmed in CFA VLANTPID register. */
3095 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
3096 (UINT32_C(0x5) << 16)
3097 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
3098 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
3099 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
3101 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
3103 * This field identifies the type of edit to be performed
3106 * This value must be valid on the first BD of a packet.
3108 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
3109 UINT32_C(0xf0000000)
3110 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
3112 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
3113 (UINT32_C(0x0) << 28)
3115 * - meta[17:16] - TPID select value (0 = 0x8100).
3116 * - meta[15:12] - PRI/DE value.
3117 * - meta[11:0] - VID value.
3119 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
3120 (UINT32_C(0x1) << 28)
3123 * - Wh+/SR - this option is not supported.
3124 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3125 * is set in the Lookup Table.
3126 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
3127 * en_bd_meta is set in the Lookup Table.
3129 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
3130 (UINT32_C(0x2) << 28)
3131 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
3132 TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
3135 /* tx_bd_empty (size:128b/16B) */
3136 struct tx_bd_empty {
3137 /* This value identifies the type of buffer descriptor. */
3139 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
3140 #define TX_BD_EMPTY_TYPE_SFT 0
3142 * Indicates that this BD is 1BB long and is an empty
3143 * TX BD. Not valid for use by the driver.
3145 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3146 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
3147 uint8_t unused_1[3];
3149 uint8_t unused_3[3];
3150 uint8_t unused_4[8];
3153 /* tx_bd_mp_cmd (size:128b/16B) */
3154 struct tx_bd_mp_cmd {
3155 /* Unless otherwise stated, sub-fields of this field are always valid. */
3156 uint16_t flags_type;
3157 /* This value identifies the type of buffer descriptor. */
3158 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
3159 #define TX_BD_MP_CMD_TYPE_SFT 0
3161 * Indicates that this BD is used to issue a command to one of
3162 * the mid-path destinations.
3164 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3165 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3166 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3167 #define TX_BD_MP_CMD_FLAGS_SFT 6
3169 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3170 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3172 * This value indicates the number of 16B BD locations (slots)
3173 * consumed in the ring by this mid-path command BD, including the
3174 * BD header and the command field.
3176 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3177 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3179 * This value defines the length of command field in bytes. The maximum
3180 * value shall be 496.
3184 * The opaque data field is pass through to the completion and can be
3185 * used for any data that the driver wants to associate with this
3186 * Tx mid-path command.
3192 /* tx_bd_presync_cmd (size:128b/16B) */
3193 struct tx_bd_presync_cmd {
3194 /* Unless otherwise stated, sub-fields of this field are always valid. */
3195 uint16_t flags_type;
3196 /* This value identifies the type of buffer descriptor. */
3197 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3198 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3200 * Indicates that this BD is used to issue a cryptographic pre-
3201 * sync command through the fast path and destined for TCE.
3203 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3204 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3205 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3206 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3207 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3209 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3210 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3212 * This value indicates the number of 16B BD locations (slots)
3213 * consumed in the ring by this pre-sync command BD, including the
3214 * BD header and the command field.
3216 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3217 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3219 * This value defines the length of command field in bytes. The maximum
3220 * value shall be 496.
3224 * The opaque data field is pass through to TCE and can be used for
3229 * This field is the Crypto Context ID to which the retransmit packet is
3230 * applied. The KID references the context fields used by the
3231 * associated kTLS offloaded connection.
3235 * The KID value of all-ones is reserved for non-KTLS packets, which
3236 * only implies that this value must not be used when filling this
3237 * field for crypto packets.
3239 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3240 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3244 /* rx_prod_pkt_bd (size:128b/16B) */
3245 struct rx_prod_pkt_bd {
3246 /* This value identifies the type of buffer descriptor. */
3247 uint16_t flags_type;
3248 /* This value identifies the type of buffer descriptor. */
3249 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3250 #define RX_PROD_PKT_BD_TYPE_SFT 0
3252 * Indicates that this BD is 16B long and is an RX Producer
3253 * (i.e. empty) buffer descriptor.
3255 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3256 #define RX_PROD_PKT_BD_TYPE_LAST \
3257 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3258 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3259 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3261 * If set to 1, the packet will be placed at the address plus
3262 * 2B. The 2 Bytes of padding will be written as zero.
3264 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3266 * If set to 1, the packet write will be padded out to the
3267 * nearest cache-line with zero value padding.
3269 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3271 * This field has been deprecated. There can be no additional
3272 * BDs for this packet from this ring.
3275 * This value is the number of additional buffers in the ring that
3276 * describe the buffer space to be consumed for this packet.
3277 * If the value is zero, then the packet must fit within the
3278 * space described by this BD. If this value is 1 or more, it
3279 * indicates how many additional "buffer" BDs are in the ring
3280 * immediately following this BD to be used for the same
3281 * network packet. Even if the packet to be placed does not need
3282 * all the additional buffers, they will be consumed anyway.
3284 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3285 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3287 * This is the length in Bytes of the host physical buffer where
3288 * data for the packet may be placed in host memory.
3292 * The opaque data field is pass through to the completion and can be
3293 * used for any data that the driver wants to associate with this
3294 * receive buffer set.
3298 * This is the host physical address where data for the packet may
3299 * be placed in host memory.
3304 /* rx_prod_bfr_bd (size:128b/16B) */
3305 struct rx_prod_bfr_bd {
3306 /* This value identifies the type of buffer descriptor. */
3307 uint16_t flags_type;
3308 /* This value identifies the type of buffer descriptor. */
3309 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3310 #define RX_PROD_BFR_BD_TYPE_SFT 0
3312 * Indicates that this BD is 16B long and is an RX
3313 * Producer Buffer BD.
3315 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3316 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3317 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3318 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3320 * This is the length in Bytes of the host physical buffer where
3321 * data for the packet may be placed in host memory.
3324 /* This field is not used. */
3327 * This is the host physical address where data for the packet may
3328 * be placed in host memory.
3333 /* rx_prod_agg_bd (size:128b/16B) */
3334 struct rx_prod_agg_bd {
3335 /* This value identifies the type of buffer descriptor. */
3336 uint16_t flags_type;
3337 /* This value identifies the type of buffer descriptor. */
3338 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3339 #define RX_PROD_AGG_BD_TYPE_SFT 0
3341 * Indicates that this BD is 16B long and is an
3342 * RX Producer Assembly Buffer Descriptor.
3344 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3345 #define RX_PROD_AGG_BD_TYPE_LAST \
3346 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3347 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3348 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3350 * If set to 1, the packet write will be padded out to the
3351 * nearest cache-line with zero value padding.
3353 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3355 * This is the length in Bytes of the host physical buffer where
3356 * data for the packet may be placed in host memory.
3360 * The opaque data field is pass through to the completion and can be
3361 * used for any data that the driver wants to associate with this
3362 * receive assembly buffer.
3366 * This is the host physical address where data for the packet may
3367 * be placed in host memory.
3372 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3373 struct cfa_cmpls_cmp_data_msg {
3374 uint32_t mp_client_dma_length_opcode_status_type;
3376 * This field represents the Mid-Path client that generated the
3379 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3380 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3381 /* Mid Path Short Completion with length = 16B. */
3382 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3384 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3385 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3386 /* This value indicates the status for the command. */
3387 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3388 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3389 /* Completed without error. */
3390 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3391 (UINT32_C(0x0) << 6)
3392 /* Indicates an unsupported CFA opcode in the command. */
3393 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3394 (UINT32_C(0x1) << 6)
3396 * Indicates a CFA command formatting error. This error can occur on
3397 * any of the supported CFA commands.
3399 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3400 (UINT32_C(0x2) << 6)
3402 * Indicates an SVIF-Table scope error. This error can occur on any
3403 * of the supported CFA commands.
3405 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3406 (UINT32_C(0x3) << 6)
3408 * Indicates that the table_index is either outside of the
3409 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3410 * the static bucket range. This error can occur on EM Insert
3411 * commands. It can also occur on Read, Read Clear, Write, and
3412 * Invalidate commands if the table_type is EM.
3414 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3415 (UINT32_C(0x4) << 6)
3417 * Cache operation responded with an error. This error can occur on
3418 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3420 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3421 (UINT32_C(0x5) << 6)
3423 * Indicates failure on EM Insert or EM Delete Command. Hash index
3424 * and hash msb are returned in table_index and hash_msb fields.
3425 * Dma_length is set to 1 if the bucket is also returned (as dma
3428 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3429 (UINT32_C(0x6) << 6)
3431 * Indicates no notifications were available on an Event Collection
3434 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3435 (UINT32_C(0x7) << 6)
3436 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3437 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3438 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3439 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3440 /* This is the opcode from the command. */
3441 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3443 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3445 * This is read command. From 32 to 128B can be read from a table
3446 * using this command.
3448 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3449 (UINT32_C(0x0) << 12)
3451 * This is write command. From 32 to 128B can be written to a table
3452 * using this command.
3454 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3455 (UINT32_C(0x1) << 12)
3457 * This is read-clear command. 32B can be read from a table and a 16b
3458 * mask can be used to clear specific 16b units after the read as an
3461 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3462 (UINT32_C(0x2) << 12)
3464 * An exact match table insert will be attempted into the table. If
3465 * there is a free location in the bucket, the payload will be
3466 * written to the bucket.
3468 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3469 (UINT32_C(0x3) << 12)
3470 /* An exact match table delete will be attempted. */
3471 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3472 (UINT32_C(0x4) << 12)
3474 * The specified table area will be invalidated. If it is needed
3475 * again, it will be read from the backing store.
3477 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3478 (UINT32_C(0x5) << 12)
3479 /* Reads notification messages from the Host Notification Queue. */
3480 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3481 (UINT32_C(0x6) << 12)
3482 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3483 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3485 * This field indicates the length of the DMA that accompanies the
3486 * completion. Specified in units of DWords (32b). Valid values are
3487 * between 0 and 128. A value of zero indicates that there is no DMA
3488 * that accompanies the completion.
3490 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3492 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3494 * This field represents the Mid-Path client that generated the
3497 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3498 UINT32_C(0xf0000000)
3499 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3500 /* TX configrable flow processing block. */
3501 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3502 (UINT32_C(0x2) << 28)
3503 /* RX configrable flow processing block. */
3504 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3505 (UINT32_C(0x3) << 28)
3506 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3507 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3509 * This is a copy of the opaque field from the mid path BD of this
3513 uint16_t hash_msb_v;
3515 * This value is written by the NIC such that it will be different for
3516 * each pass through the completion queue. The even passes will
3517 * write 1. The odd passes will write 0.
3519 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3520 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3521 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3523 * This is the upper 12b of the hash, returned on Exact Match
3524 * Insertion/Deletion Commands.
3526 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3527 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3528 /* This is the table type from the command. */
3530 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3531 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3532 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3533 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3534 /* This command acts on the action table of the specified scope. */
3535 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3536 /* This command acts on the exact match table of the specified scope. */
3537 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3538 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3539 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3540 uint8_t table_scope;
3541 /* This is the table scope from the command. */
3542 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3543 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3544 uint32_t table_index;
3546 * This is the table index from the command (if it exists). However, if
3547 * an Exact Match Insertion/Deletion command failed, then this is the
3548 * table index of the calculated static hash bucket.
3550 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3551 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3554 /* CFA Mid-Path 32B DMA Message */
3555 /* cfa_dma32b_data_msg (size:256b/32B) */
3556 struct cfa_dma32b_data_msg {
3557 /* DMA data value. */
3561 /* CFA Mid-Path 64B DMA Message */
3562 /* cfa_dma64b_data_msg (size:512b/64B) */
3563 struct cfa_dma64b_data_msg {
3564 /* DMA data value. */
3568 /* CFA Mid-Path 96B DMA Message */
3569 /* cfa_dma96b_data_msg (size:768b/96B) */
3570 struct cfa_dma96b_data_msg {
3571 /* DMA data value. */
3575 /* CFA Mid-Path 128B DMA Message */
3576 /* cfa_dma128b_data_msg (size:1024b/128B) */
3577 struct cfa_dma128b_data_msg {
3578 /* DMA data value. */
3582 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3583 struct ce_cmpls_cmp_data_msg {
3584 uint16_t status_subtype_type;
3586 * This field indicates the exact type of the completion. By
3587 * convention, the LSB identifies the length of the record in 16B
3588 * units. Even values indicate 16B records. Odd values indicate 32B
3591 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3592 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3593 /* Completion of a Mid Path Command. Length = 16B */
3594 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3595 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3596 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3598 * This value indicates the CE sub-type operation that is being
3601 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3602 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3603 /* Completion Response for a Solicited Command. */
3604 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3605 /* Error Completion (Unsolicited). */
3606 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3607 /* Re-Sync Completion (Unsolicited) */
3608 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3609 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3610 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3611 /* This value indicates the status for the command. */
3612 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3613 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3614 /* Completed without error. */
3615 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3616 (UINT32_C(0x0) << 10)
3617 /* CFCK load error. */
3618 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3619 (UINT32_C(0x1) << 10)
3620 /* FID check error. */
3621 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3622 (UINT32_C(0x2) << 10)
3623 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3624 CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
3627 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3628 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3630 * This field represents the Mid-Path client that generated the
3633 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3634 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3635 /* TX crypto engine block. */
3636 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3637 /* RX crypto engine block. */
3638 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3639 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3640 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3642 * This is a copy of the opaque field from the mid path BD of this
3649 * This value is written by the NIC such that it will be different
3650 * for each pass through the completion queue. The even passes will
3651 * write 1. The odd passes will write 0.
3653 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3655 * This field is the Crypto Context ID. The KID is used to store
3656 * information used by the associated kTLS offloaded connection.
3658 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3659 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3663 /* cmpl_base (size:128b/16B) */
3667 * This field indicates the exact type of the completion.
3668 * By convention, the LSB identifies the length of the
3669 * record in 16B units. Even values indicate 16B
3670 * records. Odd values indicate 32B
3673 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3674 #define CMPL_BASE_TYPE_SFT 0
3677 * Completion of TX packet. Length = 16B
3679 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3682 * Completion of NO-OP. Length = 16B
3684 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3686 * TX L2 coalesced completion:
3687 * Completion of coalesced TX packet. Length = 16B
3689 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3691 * TX L2 PTP completion:
3692 * Completion of PTP TX packet. Length = 32B
3694 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3696 * RX L2 TPA Start V2 Completion:
3697 * Completion of and L2 RX packet. Length = 32B
3698 * This is the new version of the RX_TPA_START completion used
3699 * in SR2 and later chips.
3701 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3703 * RX L2 V2 completion:
3704 * Completion of and L2 RX packet. Length = 32B
3705 * This is the new version of the RX_L2 completion used in SR2
3708 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3711 * Completion of and L2 RX packet. Length = 32B
3713 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3715 * RX Aggregation Buffer completion :
3716 * Completion of an L2 aggregation buffer in support of
3717 * TPA, HDS, or Jumbo packet completion. Length = 16B
3719 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3721 * RX L2 TPA Start Completion:
3722 * Completion at the beginning of a TPA operation.
3725 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3727 * RX L2 TPA End Completion:
3728 * Completion at the end of a TPA operation.
3731 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3733 * Statistics Ejection Completion:
3734 * Completion of statistics data ejection buffer.
3737 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3739 * VEE Flush Completion:
3740 * This completion is inserted manually by
3741 * the Primate and processed by the VEE hardware to ensure that
3742 * all completions on a VEE function have been processed by the
3743 * VEE hardware before FLR process is completed.
3745 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3747 * Mid Path Short Completion :
3748 * Completion of a Mid Path Command. Length = 16B
3750 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3752 * Mid Path Long Completion :
3753 * Completion of a Mid Path Command. Length = 32B
3755 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3757 * HWRM Command Completion:
3758 * Completion of an HWRM command.
3760 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3761 /* Forwarded HWRM Request */
3762 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3763 /* Forwarded HWRM Response */
3764 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3765 /* HWRM Asynchronous Event Information */
3766 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3767 /* CQ Notification */
3768 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3769 /* SRQ Threshold Event */
3770 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3771 /* DBQ Threshold Event */
3772 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3773 /* QP Async Notification */
3774 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3775 /* Function Async Notification */
3776 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3777 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3783 * This value is written by the NIC such that it will be different
3784 * for each pass through the completion queue. The even passes
3785 * will write 1. The odd passes will write 0.
3788 #define CMPL_BASE_V UINT32_C(0x1)
3789 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3790 #define CMPL_BASE_INFO3_SFT 1
3795 /* tx_cmpl (size:128b/16B) */
3797 uint16_t flags_type;
3799 * This field indicates the exact type of the completion.
3800 * By convention, the LSB identifies the length of the
3801 * record in 16B units. Even values indicate 16B
3802 * records. Odd values indicate 32B
3805 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3806 #define TX_CMPL_TYPE_SFT 0
3809 * Completion of TX packet. Length = 16B
3811 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3812 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3813 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3814 #define TX_CMPL_FLAGS_SFT 6
3816 * When this bit is '1', it indicates a packet that has an
3817 * error of some type. Type of error is indicated in
3820 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3822 * When this bit is '1', it indicates that the packet completed
3823 * was transmitted using the push acceleration data provided
3824 * by the driver. When this bit is '0', it indicates that the
3825 * packet had not push acceleration data written or was executed
3826 * as a normal packet even though push data was provided.
3828 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3829 /* unused1 is 16 b */
3832 * This is a copy of the opaque field from the first TX BD of this
3833 * transmitted packet. Note that, if the packet was described by a short
3834 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3835 * short CSO BD will appear in the bottom 16 bits of this field.
3840 * This value is written by the NIC such that it will be different
3841 * for each pass through the completion queue. The even passes
3842 * will write 1. The odd passes will write 0.
3844 #define TX_CMPL_V UINT32_C(0x1)
3845 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3846 #define TX_CMPL_ERRORS_SFT 1
3848 * This error indicates that there was some sort of problem
3849 * with the BDs for the packet.
3851 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3852 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3854 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3855 (UINT32_C(0x0) << 1)
3858 * BDs were not formatted correctly.
3860 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3861 (UINT32_C(0x2) << 1)
3862 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3863 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3865 * When this bit is '1', it indicates that the length of
3866 * the packet was zero. No packet was transmitted.
3868 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3870 * When this bit is '1', it indicates that the packet
3871 * was longer than the programmed limit in TDI. No
3872 * packet was transmitted.
3874 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3876 * When this bit is '1', it indicates that one or more of the
3877 * BDs associated with this packet generated a PCI error.
3878 * This probably means the address was not valid.
3880 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
3882 * When this bit is '1', it indicates that the packet was longer
3883 * than indicated by the hint. No packet was transmitted.
3885 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3887 * When this bit is '1', it indicates that the packet was
3888 * dropped due to Poison TLP error on one or more of the
3889 * TLPs in the PXP completion.
3891 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3893 * When this bit is '1', it indicates that the packet was dropped
3894 * due to a transient internal error in TDC. The packet or LSO can
3895 * be retried and may transmit successfully on a subsequent attempt.
3897 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3899 * When this bit is '1', it was not possible to collect a a timestamp
3900 * for a PTP completion, in which case the timestamp_hi and
3901 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3902 * completion, the timestamp_hi and timestamp_lo fields are valid.
3903 * RJRN will copy the value of this bit into the field of the same
3904 * name in all TX completions, regardless of whether such completions
3905 * are PTP completions or other TX completions.
3907 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
3908 /* unused2 is 16 b */
3910 /* unused3 is 32 b */
3914 /* tx_cmpl_coal (size:128b/16B) */
3915 struct tx_cmpl_coal {
3916 uint16_t flags_type;
3918 * This field indicates the exact type of the completion.
3919 * By convention, the LSB identifies the length of the
3920 * record in 16B units. Even values indicate 16B
3921 * records. Odd values indicate 32B
3924 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
3925 #define TX_CMPL_COAL_TYPE_SFT 0
3927 * TX L2 coalesced completion:
3928 * Completion of TX packet. Length = 16B
3930 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
3931 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
3932 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
3933 #define TX_CMPL_COAL_FLAGS_SFT 6
3935 * When this bit is '1', it indicates a packet that has an
3936 * error of some type. Type of error is indicated in
3939 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
3941 * When this bit is '1', it indicates that the packet completed
3942 * was transmitted using the push acceleration data provided
3943 * by the driver. When this bit is '0', it indicates that the
3944 * packet had not push acceleration data written or was executed
3945 * as a normal packet even though push data was provided.
3947 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
3948 /* unused1 is 16 b */
3951 * This is a copy of the opaque field from the first TX BD of the packet
3952 * which corresponds with the reported sq_cons_idx. Note that, with
3953 * coalesced completions, completions are generated for only some of the
3954 * packets. The driver will see the opaque field for only those packets.
3955 * Note that, if the packet was described by a short CSO or short CSO
3956 * inline BD, then the 16-bit opaque field from the short CSO BD will
3957 * appear in the bottom 16 bits of this field. For TX rings with
3958 * completion coalescing enabled (which would use the coalesced
3959 * completion record), it is suggested that the driver populate the
3960 * opaque field to indicate the specific TX ring with which the
3961 * completion is associated, then utilize the opaque and sq_cons_idx
3962 * fields in the coalesced completion record to determine the specific
3963 * packets that are to be completed on that ring.
3968 * This value is written by the NIC such that it will be different
3969 * for each pass through the completion queue. The even passes
3970 * will write 1. The odd passes will write 0.
3972 #define TX_CMPL_COAL_V UINT32_C(0x1)
3973 #define TX_CMPL_COAL_ERRORS_MASK \
3975 #define TX_CMPL_COAL_ERRORS_SFT 1
3977 * This error indicates that there was some sort of problem
3978 * with the BDs for the packet.
3980 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3981 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
3983 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
3984 (UINT32_C(0x0) << 1)
3987 * BDs were not formatted correctly.
3989 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
3990 (UINT32_C(0x2) << 1)
3991 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
3992 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
3994 * When this bit is '1', it indicates that the length of
3995 * the packet was zero. No packet was transmitted.
3997 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3999 * When this bit is '1', it indicates that the packet
4000 * was longer than the programmed limit in TDI. No
4001 * packet was transmitted.
4003 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4005 * When this bit is '1', it indicates that one or more of the
4006 * BDs associated with this packet generated a PCI error.
4007 * This probably means the address was not valid.
4009 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
4011 * When this bit is '1', it indicates that the packet was longer
4012 * than indicated by the hint. No packet was transmitted.
4014 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4016 * When this bit is '1', it indicates that the packet was
4017 * dropped due to Poison TLP error on one or more of the
4018 * TLPs in the PXP completion.
4020 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
4023 * When this bit is '1', it indicates that the packet was dropped
4024 * due to a transient internal error in TDC. The packet or LSO can
4025 * be retried and may transmit successfully on a subsequent attempt.
4027 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
4030 * When this bit is '1', it was not possible to collect a a timestamp
4031 * for a PTP completion, in which case the timestamp_hi and
4032 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4033 * completion, the timestamp_hi and timestamp_lo fields are valid.
4034 * RJRN will copy the value of this bit into the field of the same
4035 * name in all TX completions, regardless of whether such
4036 * completions are PTP completions or other TX completions.
4038 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
4040 /* unused2 is 16 b */
4042 uint32_t sq_cons_idx;
4044 * This value is SQ index for the start of the packet following the
4045 * last completed packet.
4047 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
4048 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
4051 /* tx_cmpl_ptp (size:128b/16B) */
4052 struct tx_cmpl_ptp {
4053 uint16_t flags_type;
4055 * This field indicates the exact type of the completion.
4056 * By convention, the LSB identifies the length of the
4057 * record in 16B units. Even values indicate 16B
4058 * records. Odd values indicate 32B
4061 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
4062 #define TX_CMPL_PTP_TYPE_SFT 0
4064 * TX L2 PTP completion:
4065 * Completion of TX packet. Length = 32B
4067 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
4068 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
4069 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
4070 #define TX_CMPL_PTP_FLAGS_SFT 6
4072 * When this bit is '1', it indicates a packet that has an
4073 * error of some type. Type of error is indicated in
4076 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
4078 * When this bit is '1', it indicates that the packet completed
4079 * was transmitted using the push acceleration data provided
4080 * by the driver. When this bit is '0', it indicates that the
4081 * packet had not push acceleration data written or was executed
4082 * as a normal packet even though push data was provided.
4084 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
4085 /* unused1 is 16 b */
4088 * This is a copy of the opaque field from the first TX BD of this
4089 * transmitted packet. Note that, if the packet was described by a short
4090 * CSO or short CSO inline BD, then the 16-bit opaque field from the
4091 * short CSO BD will appear in the bottom 16 bits of this field.
4096 * This value is written by the NIC such that it will be different
4097 * for each pass through the completion queue. The even passes
4098 * will write 1. The odd passes will write 0.
4100 #define TX_CMPL_PTP_V UINT32_C(0x1)
4101 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
4102 #define TX_CMPL_PTP_ERRORS_SFT 1
4104 * This error indicates that there was some sort of problem
4105 * with the BDs for the packet.
4107 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4108 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
4110 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
4111 (UINT32_C(0x0) << 1)
4114 * BDs were not formatted correctly.
4116 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
4117 (UINT32_C(0x2) << 1)
4118 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
4119 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
4121 * When this bit is '1', it indicates that the length of
4122 * the packet was zero. No packet was transmitted.
4124 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4126 * When this bit is '1', it indicates that the packet
4127 * was longer than the programmed limit in TDI. No
4128 * packet was transmitted.
4130 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4132 * When this bit is '1', it indicates that one or more of the
4133 * BDs associated with this packet generated a PCI error.
4134 * This probably means the address was not valid.
4136 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
4138 * When this bit is '1', it indicates that the packet was longer
4139 * than indicated by the hint. No packet was transmitted.
4141 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4143 * When this bit is '1', it indicates that the packet was
4144 * dropped due to Poison TLP error on one or more of the
4145 * TLPs in the PXP completion.
4147 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4149 * When this bit is '1', it indicates that the packet was dropped due
4150 * to a transient internal error in TDC. The packet or LSO can be
4151 * retried and may transmit successfully on a subsequent attempt.
4153 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4155 * When this bit is '1', it was not possible to collect a a timestamp
4156 * for a PTP completion, in which case the timestamp_hi and
4157 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4158 * completion, the timestamp_hi and timestamp_lo fields are valid.
4159 * RJRN will copy the value of this bit into the field of the same
4160 * name in all TX completions, regardless of whether such
4161 * completions are PTP completions or other TX completions.
4163 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4164 /* unused2 is 16 b */
4167 * This is timestamp value (lower 32bits) read from PM for the PTP
4168 * timestamp enabled packet.
4170 uint32_t timestamp_lo;
4173 /* tx_cmpl_ptp_hi (size:128b/16B) */
4174 struct tx_cmpl_ptp_hi {
4176 * This is timestamp value (lower 32bits) read from PM for the PTP
4177 * timestamp enabled packet.
4179 uint16_t timestamp_hi[3];
4180 uint16_t reserved16;
4183 * This value is written by the NIC such that it will be different for
4184 * each pass through the completion queue.The even passes will write 1.
4185 * The odd passes will write 0
4187 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4190 /* rx_pkt_cmpl (size:128b/16B) */
4191 struct rx_pkt_cmpl {
4192 uint16_t flags_type;
4194 * This field indicates the exact type of the completion.
4195 * By convention, the LSB identifies the length of the
4196 * record in 16B units. Even values indicate 16B
4197 * records. Odd values indicate 32B
4200 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4201 #define RX_PKT_CMPL_TYPE_SFT 0
4204 * Completion of and L2 RX packet. Length = 32B
4206 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4207 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
4208 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4209 #define RX_PKT_CMPL_FLAGS_SFT 6
4211 * When this bit is '1', it indicates a packet that has an
4212 * error of some type. Type of error is indicated in
4215 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4216 /* This field indicates how the packet was placed in the buffer. */
4217 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4218 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4221 * Packet was placed using normal algorithm.
4223 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
4226 * Packet was placed using jumbo algorithm.
4228 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
4230 * Header/Data Separation:
4231 * Packet was placed using Header/Data separation algorithm.
4232 * The separation location is indicated by the itype field.
4234 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
4235 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4236 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4237 /* This bit is '1' if the RSS field in this completion is valid. */
4238 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4240 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4242 * This value indicates what the inner packet determined for the
4245 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4246 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4249 * Indicates that the packet type was not known.
4251 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4252 (UINT32_C(0x0) << 12)
4255 * Indicates that the packet was an IP packet, but further
4256 * classification was not possible.
4258 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4259 (UINT32_C(0x1) << 12)
4262 * Indicates that the packet was IP and TCP.
4263 * This indicates that the payload_offset field is valid.
4265 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4266 (UINT32_C(0x2) << 12)
4269 * Indicates that the packet was IP and UDP.
4270 * This indicates that the payload_offset field is valid.
4272 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4273 (UINT32_C(0x3) << 12)
4276 * Indicates that the packet was recognized as a FCoE.
4277 * This also indicates that the payload_offset field is valid.
4279 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4280 (UINT32_C(0x4) << 12)
4283 * Indicates that the packet was recognized as a RoCE.
4284 * This also indicates that the payload_offset field is valid.
4286 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4287 (UINT32_C(0x5) << 12)
4290 * Indicates that the packet was recognized as ICMP.
4291 * This indicates that the payload_offset field is valid.
4293 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4294 (UINT32_C(0x7) << 12)
4296 * PtP packet wo/timestamp:
4297 * Indicates that the packet was recognized as a PtP
4300 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4301 (UINT32_C(0x8) << 12)
4303 * PtP packet w/timestamp:
4304 * Indicates that the packet was recognized as a PtP
4305 * packet and that a timestamp was taken for the packet.
4307 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4308 (UINT32_C(0x9) << 12)
4309 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4310 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4312 * This is the length of the data for the packet stored in the
4313 * buffer(s) identified by the opaque value. This includes
4314 * the packet BD and any associated buffer BDs. This does not include
4315 * the length of any data places in aggregation BDs.
4319 * This is a copy of the opaque field from the RX BD this completion
4323 uint8_t agg_bufs_v1;
4325 * This value is written by the NIC such that it will be different
4326 * for each pass through the completion queue. The even passes
4327 * will write 1. The odd passes will write 0.
4329 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4331 * This value is the number of aggregation buffers that follow this
4332 * entry in the completion ring that are a part of this packet.
4333 * If the value is zero, then the packet is completely contained
4334 * in the buffer space provided for the packet in the RX ring.
4336 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4337 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4338 /* unused1 is 2 b */
4339 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4340 #define RX_PKT_CMPL_UNUSED1_SFT 6
4342 * This is the RSS hash type for the packet. The value is packed
4343 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4345 * The value of tuple_extrac_op provides the information about
4346 * what fields the hash was computed on.
4347 * * 0: The RSS hash was computed over source IP address,
4348 * destination IP address, source port, and destination port of inner
4349 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4350 * the packet headers are considered inner packet headers for the RSS
4351 * hash computation purpose.
4352 * * 1: The RSS hash was computed over source IP address and destination
4353 * IP address of inner IP header. Note: For non-tunneled packets,
4354 * the packet headers are considered inner packet headers for the RSS
4355 * hash computation purpose.
4356 * * 2: The RSS hash was computed over source IP address,
4357 * destination IP address, source port, and destination port of
4358 * IP and TCP or UDP headers of outer tunnel headers.
4359 * Note: For non-tunneled packets, this value is not applicable.
4360 * * 3: The RSS hash was computed over source IP address and
4361 * destination IP address of IP header of outer tunnel headers.
4362 * Note: For non-tunneled packets, this value is not applicable.
4364 * Note that 4-tuples values listed above are applicable
4365 * for layer 4 protocols supported and enabled for RSS in the hardware,
4366 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4367 * enabled for TCP traffic only, then the values of tuple_extract_op
4368 * corresponding to 4-tuples are only valid for TCP traffic.
4370 uint8_t rss_hash_type;
4372 * This value indicates the offset in bytes from the beginning of the packet
4373 * where the inner payload starts. This value is valid for TCP, UDP,
4374 * FCoE, and RoCE packets.
4376 * A value of zero indicates that header is 256B into the packet.
4378 uint8_t payload_offset;
4379 /* unused2 is 8 b */
4382 * This value is the RSS hash value calculated for the packet
4383 * based on the mode bits and key value in the VNIC.
4388 /* Last 16 bytes of rx_pkt_cmpl. */
4389 /* rx_pkt_cmpl_hi (size:128b/16B) */
4390 struct rx_pkt_cmpl_hi {
4393 * This indicates that the ip checksum was calculated for the
4394 * inner packet and that the ip_cs_error field indicates if there
4397 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4399 * This indicates that the TCP, UDP or ICMP checksum was
4400 * calculated for the inner packet and that the l4_cs_error field
4401 * indicates if there was an error.
4403 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4405 * This indicates that the ip checksum was calculated for the
4406 * tunnel header and that the t_ip_cs_error field indicates if there
4409 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4411 * This indicates that the UDP checksum was
4412 * calculated for the tunnel packet and that the t_l4_cs_error field
4413 * indicates if there was an error.
4415 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4416 /* This value indicates what format the metadata field is. */
4417 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4418 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4419 /* No metadata information. Value is zero. */
4420 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4421 (UINT32_C(0x0) << 4)
4423 * The metadata field contains the VLAN tag and TPID value.
4424 * - metadata[11:0] contains the vlan VID value.
4425 * - metadata[12] contains the vlan DE value.
4426 * - metadata[15:13] contains the vlan PRI value.
4427 * - metadata[31:16] contains the vlan TPID value.
4429 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4430 (UINT32_C(0x1) << 4)
4432 * If ext_meta_format is equal to 1, the metadata field
4433 * contains the lower 16b of the tunnel ID value, justified
4435 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4436 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4437 * - NVGRE = TNI[23:0] -> Tenant Network ID
4438 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4439 * - IPV4 = 0 (not populated)
4440 * - IPV6 = Flow Label[19:0]
4441 * - PPPoE = sessionID[15:0]
4442 * - MPLs = Outer label[19:0]
4443 * - UPAR = Selected[31:0] with bit mask
4445 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4446 (UINT32_C(0x2) << 4)
4448 * if ext_meta_format is equal to 1, metadata field contains
4449 * 16b metadata from the prepended header (chdr_data).
4451 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4452 (UINT32_C(0x3) << 4)
4454 * If ext_meta_format is equal to 1, the metadata field contains
4455 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4457 * - metadata[8:0] contains the outer_l3_offset.
4458 * - metadata[17:9] contains the inner_l2_offset.
4459 * - metadata[26:18] contains the inner_l3_offset.
4460 * - metadata[31:27] contains the inner_l4_size.
4462 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4463 (UINT32_C(0x4) << 4)
4464 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4465 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4467 * This field indicates the IP type for the inner-most IP header.
4468 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4469 * This value is only valid if itype indicates a packet
4470 * with an IP header.
4472 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4474 * This indicates that the complete 1's complement checksum was
4475 * calculated for the packet.
4477 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4479 * The combination of this value and meta_format indicated what
4480 * format the metadata field is.
4482 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4483 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4485 * This value is the complete 1's complement checksum calculated from
4486 * the start of the outer L3 header to the end of the packet (not
4487 * including the ethernet crc). It is valid when the
4488 * 'complete_checksum_calc' flag is set.
4490 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4491 UINT32_C(0xffff0000)
4492 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4494 * This is data from the CFA block as indicated by the meta_format
4498 /* When meta_format=1, this value is the VLAN VID. */
4499 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4500 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4501 /* When meta_format=1, this value is the VLAN DE. */
4502 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4503 /* When meta_format=1, this value is the VLAN PRI. */
4504 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4505 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4506 /* When meta_format=1, this value is the VLAN TPID. */
4507 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4508 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4511 * This value is written by the NIC such that it will be different
4512 * for each pass through the completion queue. The even passes
4513 * will write 1. The odd passes will write 0.
4515 #define RX_PKT_CMPL_V2 \
4517 #define RX_PKT_CMPL_ERRORS_MASK \
4519 #define RX_PKT_CMPL_ERRORS_SFT 1
4521 * This error indicates that there was some sort of problem with
4522 * the BDs for the packet that was found after part of the
4523 * packet was already placed. The packet should be treated as
4526 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4528 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4529 /* No buffer error */
4530 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4531 (UINT32_C(0x0) << 1)
4534 * Packet did not fit into packet buffer provided.
4535 * For regular placement, this means the packet did not fit
4536 * in the buffer provided. For HDS and jumbo placement, this
4537 * means that the packet could not be placed into 7 physical
4540 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4541 (UINT32_C(0x1) << 1)
4544 * All BDs needed for the packet were not on-chip when
4545 * the packet arrived.
4547 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4548 (UINT32_C(0x2) << 1)
4551 * BDs were not formatted correctly.
4553 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4554 (UINT32_C(0x3) << 1)
4557 * There was a bad_format error on the previous operation
4559 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4560 (UINT32_C(0x5) << 1)
4561 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4562 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4564 * This indicates that there was an error in the IP header
4567 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4570 * This indicates that there was an error in the TCP, UDP
4573 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4576 * This indicates that there was an error in the tunnel
4577 * IP header checksum.
4579 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4582 * This indicates that there was an error in the tunnel
4585 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4588 * This indicates that there was a CRC error on either an FCoE
4589 * or RoCE packet. The itype indicates the packet type.
4591 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4594 * This indicates that there was an error in the tunnel
4595 * portion of the packet when this
4596 * field is non-zero.
4598 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4600 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4602 * No additional error occurred on the tunnel portion
4603 * or the packet of the packet does not have a tunnel.
4605 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4606 (UINT32_C(0x0) << 9)
4608 * Indicates that IP header version does not match
4609 * expectation from L2 Ethertype for IPv4 and IPv6
4610 * in the tunnel header.
4612 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4613 (UINT32_C(0x1) << 9)
4615 * Indicates that header length is out of range in the
4616 * tunnel header. Valid for
4619 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4620 (UINT32_C(0x2) << 9)
4622 * Indicates that the physical packet is shorter than that
4623 * claimed by the PPPoE header length for a tunnel PPPoE
4626 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4627 (UINT32_C(0x3) << 9)
4629 * Indicates that physical packet is shorter than that claimed
4630 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4631 * tunnel packet packets.
4633 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4634 (UINT32_C(0x4) << 9)
4636 * Indicates that the physical packet is shorter than that
4637 * claimed by the tunnel UDP header length for a tunnel
4638 * UDP packet that is not fragmented.
4640 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4641 (UINT32_C(0x5) << 9)
4643 * indicates that the IPv4 TTL or IPv6 hop limit check
4644 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4645 * for IPv4, and IPv6.
4647 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4648 (UINT32_C(0x6) << 9)
4649 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4650 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4652 * This indicates that there was an error in the inner
4653 * portion of the packet when this
4654 * field is non-zero.
4656 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4658 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4660 * No additional error occurred on the tunnel portion
4661 * or the packet of the packet does not have a tunnel.
4663 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4664 (UINT32_C(0x0) << 12)
4666 * Indicates that IP header version does not match
4667 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4668 * option other than VFT was parsed on
4671 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4672 (UINT32_C(0x1) << 12)
4674 * indicates that header length is out of range. Valid for
4677 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4678 (UINT32_C(0x2) << 12)
4680 * indicates that the IPv4 TTL or IPv6 hop limit check
4681 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4683 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4684 (UINT32_C(0x3) << 12)
4686 * Indicates that physical packet is shorter than that
4687 * claimed by the l3 header length. Valid for IPv4,
4688 * IPv6 packet or RoCE packets.
4690 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4691 (UINT32_C(0x4) << 12)
4693 * Indicates that the physical packet is shorter than that
4694 * claimed by the UDP header length for a UDP packet that is
4697 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4698 (UINT32_C(0x5) << 12)
4700 * Indicates that TCP header length > IP payload. Valid for
4703 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4704 (UINT32_C(0x6) << 12)
4705 /* Indicates that TCP header length < 5. Valid for TCP. */
4706 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4707 (UINT32_C(0x7) << 12)
4709 * Indicates that TCP option headers result in a TCP header
4710 * size that does not match data offset in TCP header. Valid
4713 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4714 (UINT32_C(0x8) << 12)
4715 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4716 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4718 * This field identifies the CFA action rule that was used for this
4724 * This value holds the reordering sequence number for the packet.
4725 * If the reordering sequence is not valid, then this value is zero.
4726 * The reordering domain for the packet is in the bottom 8 to 10b of
4727 * the rss_hash value. The bottom 20b of this value contain the
4728 * ordering domain value for the packet.
4730 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4731 #define RX_PKT_CMPL_REORDER_SFT 0
4734 /* rx_pkt_v2_cmpl (size:128b/16B) */
4735 struct rx_pkt_v2_cmpl {
4736 uint16_t flags_type;
4738 * This field indicates the exact type of the completion.
4739 * By convention, the LSB identifies the length of the
4740 * record in 16B units. Even values indicate 16B
4741 * records. Odd values indicate 32B
4744 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4745 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4747 * RX L2 V2 completion:
4748 * Completion of and L2 RX packet. Length = 32B
4749 * This is the new version of the RX_L2 completion used in SR2
4752 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4753 #define RX_PKT_V2_CMPL_TYPE_LAST \
4754 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4755 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4756 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4758 * When this bit is '1', it indicates a packet that has an
4759 * error of some type. Type of error is indicated in
4762 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4763 /* This field indicates how the packet was placed in the buffer. */
4764 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4765 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4768 * Packet was placed using normal algorithm.
4770 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4771 (UINT32_C(0x0) << 7)
4774 * Packet was placed using jumbo algorithm.
4776 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4777 (UINT32_C(0x1) << 7)
4779 * Header/Data Separation:
4780 * Packet was placed using Header/Data separation algorithm.
4781 * The separation location is indicated by the itype field.
4783 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4784 (UINT32_C(0x2) << 7)
4787 * Packet was placed using truncation algorithm. The
4788 * placed (truncated) length is indicated in the payload_offset
4789 * field. The original length is indicated in the len field.
4791 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4792 (UINT32_C(0x3) << 7)
4793 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4794 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4795 /* This bit is '1' if the RSS field in this completion is valid. */
4796 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4798 * This bit is '1' if metadata has been added to the end of the
4799 * packet in host memory. Metadata starts at the first 32B boundary
4800 * after the end of the packet for regular and jumbo placement.
4801 * It starts at the first 32B boundary after the end of the header
4802 * for HDS placement. The length of the metadata is indicated in the
4805 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4807 * This value indicates what the inner packet determined for the
4810 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4811 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4814 * Indicates that the packet type was not known.
4816 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4817 (UINT32_C(0x0) << 12)
4820 * Indicates that the packet was an IP packet, but further
4821 * classification was not possible.
4823 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4824 (UINT32_C(0x1) << 12)
4827 * Indicates that the packet was IP and TCP.
4828 * This indicates that the payload_offset field is valid.
4830 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4831 (UINT32_C(0x2) << 12)
4834 * Indicates that the packet was IP and UDP.
4835 * This indicates that the payload_offset field is valid.
4837 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4838 (UINT32_C(0x3) << 12)
4841 * Indicates that the packet was recognized as a FCoE.
4842 * This also indicates that the payload_offset field is valid.
4844 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4845 (UINT32_C(0x4) << 12)
4848 * Indicates that the packet was recognized as a RoCE.
4849 * This also indicates that the payload_offset field is valid.
4851 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4852 (UINT32_C(0x5) << 12)
4855 * Indicates that the packet was recognized as ICMP.
4856 * This indicates that the payload_offset field is valid.
4858 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
4859 (UINT32_C(0x7) << 12)
4861 * PtP packet wo/timestamp:
4862 * Indicates that the packet was recognized as a PtP
4865 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4866 (UINT32_C(0x8) << 12)
4868 * PtP packet w/timestamp:
4869 * Indicates that the packet was recognized as a PtP
4870 * packet and that a timestamp was taken for the packet.
4872 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4873 (UINT32_C(0x9) << 12)
4874 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
4875 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4877 * This is the length of the data for the packet stored in the
4878 * buffer(s) identified by the opaque value. This includes
4879 * the packet BD and any associated buffer BDs. This does not include
4880 * the length of any data places in aggregation BDs.
4884 * This is a copy of the opaque field from the RX BD this completion
4888 uint8_t agg_bufs_v1;
4890 * This value is written by the NIC such that it will be different
4891 * for each pass through the completion queue. The even passes
4892 * will write 1. The odd passes will write 0.
4894 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
4896 * This value is the number of aggregation buffers that follow this
4897 * entry in the completion ring that are a part of this packet.
4898 * If the value is zero, then the packet is completely contained
4899 * in the buffer space provided for the packet in the RX ring.
4901 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4902 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
4903 /* unused1 is 2 b */
4904 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4905 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
4907 * This is the RSS hash type for the packet. The value is packed
4908 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4910 * The value of tuple_extrac_op provides the information about
4911 * what fields the hash was computed on.
4912 * * 0: The RSS hash was computed over source IP address,
4913 * destination IP address, source port, and destination port of inner
4914 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4915 * the packet headers are considered inner packet headers for the RSS
4916 * hash computation purpose.
4917 * * 1: The RSS hash was computed over source IP address and destination
4918 * IP address of inner IP header. Note: For non-tunneled packets,
4919 * the packet headers are considered inner packet headers for the RSS
4920 * hash computation purpose.
4921 * * 2: The RSS hash was computed over source IP address,
4922 * destination IP address, source port, and destination port of
4923 * IP and TCP or UDP headers of outer tunnel headers.
4924 * Note: For non-tunneled packets, this value is not applicable.
4925 * * 3: The RSS hash was computed over source IP address and
4926 * destination IP address of IP header of outer tunnel headers.
4927 * Note: For non-tunneled packets, this value is not applicable.
4929 * Note that 4-tuples values listed above are applicable
4930 * for layer 4 protocols supported and enabled for RSS in the hardware,
4931 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4932 * enabled for TCP traffic only, then the values of tuple_extract_op
4933 * corresponding to 4-tuples are only valid for TCP traffic.
4935 uint8_t rss_hash_type;
4936 uint16_t metadata1_payload_offset;
4938 * This is data from the CFA as indicated by the meta_format field.
4939 * If truncation placement is not used, this value indicates the offset
4940 * in bytes from the beginning of the packet where the inner payload
4941 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
4942 * truncation placement is used, this value represents the placed
4943 * (truncated) length of the packet.
4945 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
4946 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
4947 /* This is data from the CFA as indicated by the meta_format field. */
4948 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4949 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
4950 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4951 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4952 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4954 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4955 (UINT32_C(0x0) << 12)
4957 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4958 (UINT32_C(0x1) << 12)
4960 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4961 (UINT32_C(0x2) << 12)
4963 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4964 (UINT32_C(0x3) << 12)
4966 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4967 (UINT32_C(0x4) << 12)
4968 /* Value programmed in CFA VLANTPID register. */
4969 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4970 (UINT32_C(0x5) << 12)
4971 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
4972 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4973 /* When meta_format != 0, this value is the VLAN valid. */
4974 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4976 * This value is the RSS hash value calculated for the packet
4977 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
4978 * is set in VNIC context, this is the lower 32b of the host address
4979 * from the first BD used to place the packet.
4984 /* Last 16 bytes of RX Packet V2 Completion Record */
4985 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
4986 struct rx_pkt_v2_cmpl_hi {
4989 * When this bit is '0', the cs_ok field has the following definition:-
4990 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4991 * in the delivered packet, counted from the outer-most header group to
4992 * the inner-most header group, stopping at the first error. -
4993 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4994 * in the delivered packet, counted from the outer-most header group to
4995 * the inner-most header group, stopping at the first error. When this
4996 * bit is '1', the cs_ok field has the following definition: -
4997 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4998 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4999 * will be '1' if all the parsed header groups with an IP checksum are
5000 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5001 * header groups with an L4 checksum are valid.
5003 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
5005 /* This value indicates what format the metadata field is. */
5006 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
5008 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
5009 /* There is no metadata information. Values are zero. */
5010 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
5011 (UINT32_C(0x0) << 4)
5013 * The {metadata1, metadata0} fields contain the vtag
5014 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5015 * de, vid[11:0]} The metadata2 field contains the table scope
5016 * and action record pointer. - metadata2[25:0] contains the
5017 * action record pointer. - metadata2[31:26] contains the table
5020 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
5021 (UINT32_C(0x1) << 4)
5023 * The {metadata1, metadata0} fields contain the vtag
5025 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5026 * The metadata2 field contains the Tunnel ID
5027 * value, justified to LSB. i
5028 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5029 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5030 * - NVGRE = TNI[23:0] -> Tenant Network ID
5031 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5032 * - IPv4 = 0 (not populated)
5033 * - IPv6 = Flow Label[19:0]
5034 * - PPPoE = sessionID[15:0]
5035 * - MPLs = Outer label[19:0]
5036 * - UPAR = Selected[31:0] with bit mask
5038 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
5039 (UINT32_C(0x2) << 4)
5041 * The {metadata1, metadata0} fields contain the vtag
5043 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5044 * The metadata2 field contains the 32b metadata from the prepended
5045 * header (chdr_data).
5047 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
5048 (UINT32_C(0x3) << 4)
5050 * The {metadata1, metadata0} fields contain the vtag
5052 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5053 * The metadata2 field contains the outer_l3_offset,
5054 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5055 * - metadata2[8:0] contains the outer_l3_offset.
5056 * - metadata2[17:9] contains the inner_l2_offset.
5057 * - metadata2[26:18] contains the inner_l3_offset.
5058 * - metadata2[31:27] contains the inner_l4_size.
5060 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
5061 (UINT32_C(0x4) << 4)
5062 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
5063 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
5065 * This field indicates the IP type for the inner-most IP header.
5066 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5067 * This value is only valid if itype indicates a packet
5068 * with an IP header.
5070 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
5073 * This indicates that the complete 1's complement checksum was
5074 * calculated for the packet.
5076 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
5079 * This field indicates the status of IP and L4 CS calculations done
5080 * by the chip. The format of this field is indicated by the
5081 * cs_all_ok_mode bit.
5083 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
5085 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
5087 * This value is the complete 1's complement checksum calculated from
5088 * the start of the outer L3 header to the end of the packet (not
5089 * including the ethernet crc). It is valid when the
5090 * 'complete_checksum_calc' flag is set.
5092 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5093 UINT32_C(0xffff0000)
5094 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5096 * This is data from the CFA block as indicated by the meta_format
5098 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5099 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5100 * act_rec_ptr[25:0]}
5101 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5102 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5103 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5104 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5105 * of the host address from the first BD used to place the packet.
5110 * This value is written by the NIC such that it will be different
5111 * for each pass through the completion queue. The even passes
5112 * will write 1. The odd passes will write 0.
5114 #define RX_PKT_V2_CMPL_HI_V2 \
5116 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
5118 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
5120 * This error indicates that there was some sort of problem with
5121 * the BDs for the packet that was found after part of the
5122 * packet was already placed. The packet should be treated as
5125 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
5127 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
5128 /* No buffer error */
5129 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
5130 (UINT32_C(0x0) << 1)
5132 * Did Not Fit: Packet did not fit into packet buffer provided.
5133 * For regular placement, this means the packet did not fit in
5134 * the buffer provided. For HDS and jumbo placement, this means
5135 * that the packet could not be placed into 8 physical buffers
5136 * (if fixed-size buffers are used), or that the packet could
5137 * not be placed in the number of physical buffers configured
5138 * for the VNIC (if variable-size buffers are used)
5140 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5141 (UINT32_C(0x1) << 1)
5143 * Not On Chip: All BDs needed for the packet were not on-chip
5144 * when the packet arrived. For regular placement, this error is
5145 * not valid. For HDS and jumbo placement, this means that not
5146 * enough agg BDs were posted to place the packet.
5148 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5149 (UINT32_C(0x2) << 1)
5152 * BDs were not formatted correctly.
5154 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5155 (UINT32_C(0x3) << 1)
5158 * There was a bad_format error on the previous operation
5160 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
5161 (UINT32_C(0x5) << 1)
5162 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
5163 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5165 * This indicates that there was an error in the outer tunnel
5166 * portion of the packet when this field is non-zero.
5168 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5170 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5172 * No additional error occurred on the outer tunnel portion
5173 * of the packet or the packet does not have a outer tunnel.
5175 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5176 (UINT32_C(0x0) << 4)
5178 * Indicates that IP header version does not match expectation
5179 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5181 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5182 (UINT32_C(0x1) << 4)
5184 * Indicates that header length is out of range in the outer
5185 * tunnel header. Valid for IPv4.
5187 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5188 (UINT32_C(0x2) << 4)
5190 * Indicates that physical packet is shorter than that claimed
5191 * by the outer tunnel l3 header length. Valid for IPv4, or
5192 * IPv6 outer tunnel packets.
5194 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5195 (UINT32_C(0x3) << 4)
5197 * Indicates that the physical packet is shorter than that
5198 * claimed by the outer tunnel UDP header length for a outer
5199 * tunnel UDP packet that is not fragmented.
5201 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5202 (UINT32_C(0x4) << 4)
5204 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5205 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5208 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5209 (UINT32_C(0x5) << 4)
5211 * Indicates that the IP checksum failed its check in the outer
5214 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5215 (UINT32_C(0x6) << 4)
5217 * Indicates that the L4 checksum failed its check in the outer
5220 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5221 (UINT32_C(0x7) << 4)
5222 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5223 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5225 * This indicates that there was a CRC error on either an FCoE
5226 * or RoCE packet. The itype indicates the packet type.
5228 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5231 * This indicates that there was an error in the tunnel portion
5232 * of the packet when this field is non-zero.
5234 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5236 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5238 * No additional error occurred on the tunnel portion
5239 * of the packet or the packet does not have a tunnel.
5241 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5242 (UINT32_C(0x0) << 9)
5244 * Indicates that IP header version does not match expectation
5245 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5247 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5248 (UINT32_C(0x1) << 9)
5250 * Indicates that header length is out of range in the tunnel
5251 * header. Valid for IPv4.
5253 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5254 (UINT32_C(0x2) << 9)
5256 * Indicates that physical packet is shorter than that claimed
5257 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5260 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5261 (UINT32_C(0x3) << 9)
5263 * Indicates that the physical packet is shorter than that claimed
5264 * by the tunnel UDP header length for a tunnel UDP packet that is
5267 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5268 (UINT32_C(0x4) << 9)
5270 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5271 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5273 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5274 (UINT32_C(0x5) << 9)
5276 * Indicates that the IP checksum failed its check in the tunnel
5279 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5280 (UINT32_C(0x6) << 9)
5282 * Indicates that the L4 checksum failed its check in the tunnel
5285 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5286 (UINT32_C(0x7) << 9)
5287 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5288 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5290 * This indicates that there was an error in the inner
5291 * portion of the packet when this
5292 * field is non-zero.
5294 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5296 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5298 * No additional error occurred on the tunnel portion
5299 * or the packet of the packet does not have a tunnel.
5301 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5302 (UINT32_C(0x0) << 12)
5304 * Indicates that IP header version does not match
5305 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5306 * option other than VFT was parsed on
5309 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5310 (UINT32_C(0x1) << 12)
5312 * indicates that header length is out of range. Valid for
5315 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5316 (UINT32_C(0x2) << 12)
5318 * indicates that the IPv4 TTL or IPv6 hop limit check
5319 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5321 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5322 (UINT32_C(0x3) << 12)
5324 * Indicates that physical packet is shorter than that
5325 * claimed by the l3 header length. Valid for IPv4,
5326 * IPv6 packet or RoCE packets.
5328 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5329 (UINT32_C(0x4) << 12)
5331 * Indicates that the physical packet is shorter than that
5332 * claimed by the UDP header length for a UDP packet that is
5335 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5336 (UINT32_C(0x5) << 12)
5338 * Indicates that TCP header length > IP payload. Valid for
5341 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5342 (UINT32_C(0x6) << 12)
5343 /* Indicates that TCP header length < 5. Valid for TCP. */
5344 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5345 (UINT32_C(0x7) << 12)
5347 * Indicates that TCP option headers result in a TCP header
5348 * size that does not match data offset in TCP header. Valid
5351 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5352 (UINT32_C(0x8) << 12)
5354 * Indicates that the IP checksum failed its check in the
5357 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5358 (UINT32_C(0x9) << 12)
5360 * Indicates that the L4 checksum failed its check in the
5363 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5364 (UINT32_C(0xa) << 12)
5365 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5366 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5368 * This is data from the CFA block as indicated by the meta_format
5372 /* When meta_format=1, this value is the VLAN VID. */
5373 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5374 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5375 /* When meta_format=1, this value is the VLAN DE. */
5376 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5377 /* When meta_format=1, this value is the VLAN PRI. */
5378 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5379 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5381 * The timestamp field contains the 32b timestamp for the packet from
5388 * This TPA completion structure is used on devices where the
5389 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5391 /* rx_tpa_start_cmpl (size:128b/16B) */
5392 struct rx_tpa_start_cmpl {
5393 uint16_t flags_type;
5395 * This field indicates the exact type of the completion.
5396 * By convention, the LSB identifies the length of the
5397 * record in 16B units. Even values indicate 16B
5398 * records. Odd values indicate 32B
5401 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
5402 #define RX_TPA_START_CMPL_TYPE_SFT 0
5404 * RX L2 TPA Start Completion:
5405 * Completion at the beginning of a TPA operation.
5408 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
5409 #define RX_TPA_START_CMPL_TYPE_LAST \
5410 RX_TPA_START_CMPL_TYPE_RX_TPA_START
5411 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5412 #define RX_TPA_START_CMPL_FLAGS_SFT 6
5413 /* This bit will always be '0' for TPA start completions. */
5414 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
5415 /* This field indicates how the packet was placed in the buffer. */
5416 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5417 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
5420 * TPA Packet was placed using jumbo algorithm. This means
5421 * that the first buffer will be filled with data before
5422 * moving to aggregation buffers. Each aggregation buffer
5423 * will be filled before moving to the next aggregation
5426 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5427 (UINT32_C(0x1) << 7)
5429 * Header/Data Separation:
5430 * Packet was placed using Header/Data separation algorithm.
5431 * The separation location is indicated by the itype field.
5433 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
5434 (UINT32_C(0x2) << 7)
5437 * Packet will be placed using GRO/Jumbo where the first
5438 * packet is filled with data. Subsequent packets will be
5439 * placed such that any one packet does not span two
5440 * aggregation buffers unless it starts at the beginning of
5441 * an aggregation buffer.
5443 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5444 (UINT32_C(0x5) << 7)
5446 * GRO/Header-Data Separation:
5447 * Packet will be placed using GRO/HDS where the header
5448 * is in the first packet.
5449 * Payload of each packet will be
5450 * placed such that any one packet does not span two
5451 * aggregation buffers unless it starts at the beginning of
5452 * an aggregation buffer.
5454 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5455 (UINT32_C(0x6) << 7)
5456 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
5457 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5458 /* This bit is '1' if the RSS field in this completion is valid. */
5459 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5461 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
5463 * This value indicates what the inner packet determined for the
5466 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5467 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
5470 * Indicates that the packet was IP and TCP.
5472 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
5473 (UINT32_C(0x2) << 12)
5474 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
5475 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
5477 * This value indicates the amount of packet data written to the
5478 * buffer the opaque field in this completion corresponds to.
5482 * This is a copy of the opaque field from the RX BD this completion
5487 * This value is written by the NIC such that it will be different
5488 * for each pass through the completion queue. The even passes
5489 * will write 1. The odd passes will write 0.
5493 * This value is written by the NIC such that it will be different
5494 * for each pass through the completion queue. The even passes
5495 * will write 1. The odd passes will write 0.
5497 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
5498 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
5500 * This is the RSS hash type for the packet. The value is packed
5501 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5503 * The value of tuple_extrac_op provides the information about
5504 * what fields the hash was computed on.
5505 * * 0: The RSS hash was computed over source IP address,
5506 * destination IP address, source port, and destination port of inner
5507 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5508 * the packet headers are considered inner packet headers for the RSS
5509 * hash computation purpose.
5510 * * 1: The RSS hash was computed over source IP address and destination
5511 * IP address of inner IP header. Note: For non-tunneled packets,
5512 * the packet headers are considered inner packet headers for the RSS
5513 * hash computation purpose.
5514 * * 2: The RSS hash was computed over source IP address,
5515 * destination IP address, source port, and destination port of
5516 * IP and TCP or UDP headers of outer tunnel headers.
5517 * Note: For non-tunneled packets, this value is not applicable.
5518 * * 3: The RSS hash was computed over source IP address and
5519 * destination IP address of IP header of outer tunnel headers.
5520 * Note: For non-tunneled packets, this value is not applicable.
5522 * Note that 4-tuples values listed above are applicable
5523 * for layer 4 protocols supported and enabled for RSS in the hardware,
5524 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5525 * enabled for TCP traffic only, then the values of tuple_extract_op
5526 * corresponding to 4-tuples are only valid for TCP traffic.
5528 uint8_t rss_hash_type;
5530 * This is the aggregation ID that the completion is associated
5531 * with. Use this number to correlate the TPA start completion
5532 * with the TPA end completion.
5535 /* unused2 is 9 b */
5536 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
5537 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
5539 * This is the aggregation ID that the completion is associated
5540 * with. Use this number to correlate the TPA start completion
5541 * with the TPA end completion.
5543 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
5544 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
5546 * This value is the RSS hash value calculated for the packet
5547 * based on the mode bits and key value in the VNIC.
5553 * Last 16 bytes of rx_tpa_start_cmpl.
5555 * This TPA completion structure is used on devices where the
5556 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5558 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
5559 struct rx_tpa_start_cmpl_hi {
5562 * This indicates that the ip checksum was calculated for the
5563 * inner packet and that the sum passed for all segments
5564 * included in the aggregation.
5566 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5568 * This indicates that the TCP, UDP or ICMP checksum was
5569 * calculated for the inner packet and that the sum passed
5570 * for all segments included in the aggregation.
5572 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5574 * This indicates that the ip checksum was calculated for the
5575 * tunnel header and that the sum passed for all segments
5576 * included in the aggregation.
5578 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5580 * This indicates that the UDP checksum was
5581 * calculated for the tunnel packet and that the sum passed for
5582 * all segments included in the aggregation.
5584 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5585 /* This value indicates what format the metadata field is. */
5586 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5587 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5588 /* No metadata information. Value is zero. */
5589 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
5590 (UINT32_C(0x0) << 4)
5592 * The metadata field contains the VLAN tag and TPID value.
5593 * - metadata[11:0] contains the vlan VID value.
5594 * - metadata[12] contains the vlan DE value.
5595 * - metadata[15:13] contains the vlan PRI value.
5596 * - metadata[31:16] contains the vlan TPID value.
5598 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5599 (UINT32_C(0x1) << 4)
5600 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
5601 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
5603 * This field indicates the IP type for the inner-most IP header.
5604 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5606 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5608 * This is data from the CFA block as indicated by the meta_format
5612 /* When meta_format=1, this value is the VLAN VID. */
5613 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5614 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
5615 /* When meta_format=1, this value is the VLAN DE. */
5616 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
5617 /* When meta_format=1, this value is the VLAN PRI. */
5618 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5619 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
5620 /* When meta_format=1, this value is the VLAN TPID. */
5621 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5622 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
5625 * This value is written by the NIC such that it will be different
5626 * for each pass through the completion queue. The even passes
5627 * will write 1. The odd passes will write 0.
5629 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
5631 * This field identifies the CFA action rule that was used for this
5636 * This is the size in bytes of the inner most L4 header.
5637 * This can be subtracted from the payload_offset to determine
5638 * the start of the inner most L4 header.
5640 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5642 * This is the offset from the beginning of the packet in bytes for
5643 * the outer L3 header. If there is no outer L3 header, then this
5646 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5647 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
5649 * This is the offset from the beginning of the packet in bytes for
5650 * the inner most L2 header.
5652 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5653 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
5655 * This is the offset from the beginning of the packet in bytes for
5656 * the inner most L3 header.
5658 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5659 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
5661 * This is the size in bytes of the inner most L4 header.
5662 * This can be subtracted from the payload_offset to determine
5663 * the start of the inner most L4 header.
5665 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5666 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
5670 * This TPA completion structure is used on devices where the
5671 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5672 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
5675 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
5676 struct rx_tpa_start_v2_cmpl {
5677 uint16_t flags_type;
5679 * This field indicates the exact type of the completion.
5680 * By convention, the LSB identifies the length of the
5681 * record in 16B units. Even values indicate 16B
5682 * records. Odd values indicate 32B
5685 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
5687 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
5689 * RX L2 TPA Start V2 Completion:
5690 * Completion at the beginning of a TPA operation.
5692 * This is the new version of the RX_TPA_START completion used
5693 * in SR2 and later chips.
5695 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
5697 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
5698 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
5699 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
5701 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
5703 * When this bit is '1', it indicates a packet that has an error
5704 * of some type. Type of error is indicated in error_flags.
5706 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
5708 /* This field indicates how the packet was placed in the buffer. */
5709 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
5711 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
5714 * TPA Packet was placed using jumbo algorithm. This means
5715 * that the first buffer will be filled with data before
5716 * moving to aggregation buffers. Each aggregation buffer
5717 * will be filled before moving to the next aggregation
5720 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
5721 (UINT32_C(0x1) << 7)
5723 * Header/Data Separation:
5724 * Packet was placed using Header/Data separation algorithm.
5725 * The separation location is indicated by the itype field.
5727 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
5728 (UINT32_C(0x2) << 7)
5731 * Packet will be placed using In-Order Completion/Jumbo where
5732 * the first packet of the aggregation is placed using Jumbo
5733 * Placement. Subsequent packets will be placed such that each
5734 * packet starts at the beginning of an aggregation buffer.
5736 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
5737 (UINT32_C(0x4) << 7)
5740 * Packet will be placed using GRO/Jumbo where the first
5741 * packet is filled with data. Subsequent packets will be
5742 * placed such that any one packet does not span two
5743 * aggregation buffers unless it starts at the beginning of
5744 * an aggregation buffer.
5746 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5747 (UINT32_C(0x5) << 7)
5749 * GRO/Header-Data Separation:
5750 * Packet will be placed using GRO/HDS where the header
5751 * is in the first packet.
5752 * Payload of each packet will be
5753 * placed such that any one packet does not span two
5754 * aggregation buffers unless it starts at the beginning of
5755 * an aggregation buffer.
5757 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5758 (UINT32_C(0x6) << 7)
5760 * IOC/Header-Data Separation:
5761 * Packet will be placed using In-Order Completion/HDS where
5762 * the header is in the first packet buffer. Payload of each
5763 * packet will be placed such that each packet starts at the
5764 * beginning of an aggregation buffer.
5766 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
5767 (UINT32_C(0x7) << 7)
5768 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
5769 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
5770 /* This bit is '1' if the RSS field in this completion is valid. */
5771 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
5774 * This bit is '1' if metadata has been added to the end of the
5775 * packet in host memory. Metadata starts at the first 32B boundary
5776 * after the end of the packet for regular and jumbo placement. It
5777 * starts at the first 32B boundary after the end of the header for
5778 * HDS placement. The length of the metadata is indicated in the
5781 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
5784 * This value indicates what the inner packet determined for the
5787 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
5789 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
5792 * Indicates that the packet was IP and TCP.
5794 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
5795 (UINT32_C(0x2) << 12)
5796 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
5797 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
5799 * This value indicates the amount of packet data written to the
5800 * buffer the opaque field in this completion corresponds to.
5804 * This is a copy of the opaque field from the RX BD this completion
5805 * corresponds to. If the VNIC is configured to not use an Rx BD for
5806 * the TPA Start completion, then this is a copy of the opaque field
5807 * from the first BD used to place the TPA Start packet.
5811 * This value is written by the NIC such that it will be different
5812 * for each pass through the completion queue. The even passes
5813 * will write 1. The odd passes will write 0.
5817 * This value is written by the NIC such that it will be different
5818 * for each pass through the completion queue. The even passes
5819 * will write 1. The odd passes will write 0.
5821 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
5822 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
5824 * This is the RSS hash type for the packet. The value is packed
5825 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5827 * The value of tuple_extrac_op provides the information about
5828 * what fields the hash was computed on.
5829 * * 0: The RSS hash was computed over source IP address,
5830 * destination IP address, source port, and destination port of inner
5831 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5832 * the packet headers are considered inner packet headers for the RSS
5833 * hash computation purpose.
5834 * * 1: The RSS hash was computed over source IP address and destination
5835 * IP address of inner IP header. Note: For non-tunneled packets,
5836 * the packet headers are considered inner packet headers for the RSS
5837 * hash computation purpose.
5838 * * 2: The RSS hash was computed over source IP address,
5839 * destination IP address, source port, and destination port of
5840 * IP and TCP or UDP headers of outer tunnel headers.
5841 * Note: For non-tunneled packets, this value is not applicable.
5842 * * 3: The RSS hash was computed over source IP address and
5843 * destination IP address of IP header of outer tunnel headers.
5844 * Note: For non-tunneled packets, this value is not applicable.
5846 * Note that 4-tuples values listed above are applicable
5847 * for layer 4 protocols supported and enabled for RSS in the hardware,
5848 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5849 * enabled for TCP traffic only, then the values of tuple_extract_op
5850 * corresponding to 4-tuples are only valid for TCP traffic.
5852 uint8_t rss_hash_type;
5854 * This is the aggregation ID that the completion is associated
5855 * with. Use this number to correlate the TPA start completion
5856 * with the TPA end completion.
5860 * This is the aggregation ID that the completion is associated
5861 * with. Use this number to correlate the TPA start completion
5862 * with the TPA end completion.
5864 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
5865 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
5866 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
5868 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
5869 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5870 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
5872 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5874 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5875 (UINT32_C(0x0) << 12)
5877 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5878 (UINT32_C(0x1) << 12)
5880 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5881 (UINT32_C(0x2) << 12)
5883 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5884 (UINT32_C(0x3) << 12)
5886 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5887 (UINT32_C(0x4) << 12)
5888 /* Value programmed in CFA VLANTPID register. */
5889 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5890 (UINT32_C(0x5) << 12)
5891 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
5892 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5893 /* When meta_format != 0, this value is the VLAN valid. */
5894 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
5897 * This value is the RSS hash value calculated for the packet
5898 * based on the mode bits and key value in the VNIC.
5899 * When vee_cmpl_mode is set in VNIC context, this is the lower
5900 * 32b of the host address from the first BD used to place the packet.
5906 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
5908 * This TPA completion structure is used on devices where the
5909 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5911 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
5912 struct rx_tpa_start_v2_cmpl_hi {
5914 /* This indicates that the aggregation was done using GRO rules. */
5915 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
5918 * When this bit is '0', the cs_ok field has the following definition:-
5919 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5920 * in the delivered packet, counted from the outer-most header group to
5921 * the inner-most header group, stopping at the first error. -
5922 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5923 * in the delivered packet, counted from the outer-most header group to
5924 * the inner-most header group, stopping at the first error. When this
5925 * bit is '1', the cs_ok field has the following definition: -
5926 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5927 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5928 * will be '1' if all the parsed header groups with an IP checksum are
5929 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5930 * header groups with an L4 checksum are valid.
5932 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
5934 /* This value indicates what format the metadata field is. */
5935 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
5937 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
5938 /* There is no metadata information. Values are zero. */
5939 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
5940 (UINT32_C(0x0) << 4)
5942 * The {metadata1, metadata0} fields contain the vtag
5943 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5944 * de, vid[11:0]} The metadata2 field contains the table scope
5945 * and action record pointer. - metadata2[25:0] contains the
5946 * action record pointer. - metadata2[31:26] contains the table
5949 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
5950 (UINT32_C(0x1) << 4)
5952 * The {metadata1, metadata0} fields contain the vtag
5954 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5955 * The metadata2 field contains the Tunnel ID
5956 * value, justified to LSB. i
5957 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5958 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5959 * - NVGRE = TNI[23:0] -> Tenant Network ID
5960 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5961 * - IPv4 = 0 (not populated)
5962 * - IPv6 = Flow Label[19:0]
5963 * - PPPoE = sessionID[15:0]
5964 * - MPLs = Outer label[19:0]
5965 * - UPAR = Selected[31:0] with bit mask
5967 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5968 (UINT32_C(0x2) << 4)
5970 * The {metadata1, metadata0} fields contain the vtag
5972 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5973 * The metadata2 field contains the 32b metadata from the prepended
5974 * header (chdr_data).
5976 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5977 (UINT32_C(0x3) << 4)
5979 * The {metadata1, metadata0} fields contain the vtag
5981 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5982 * The metadata2 field contains the outer_l3_offset,
5983 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5984 * - metadata2[8:0] contains the outer_l3_offset.
5985 * - metadata2[17:9] contains the inner_l2_offset.
5986 * - metadata2[26:18] contains the inner_l3_offset.
5987 * - metadata2[31:27] contains the inner_l4_size.
5989 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5990 (UINT32_C(0x4) << 4)
5991 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
5992 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5994 * This field indicates the IP type for the inner-most IP header.
5995 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5996 * This value is only valid if itype indicates a packet
5997 * with an IP header.
5999 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
6002 * This indicates that the complete 1's complement checksum was
6003 * calculated for the packet in the affregation.
6005 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6008 * This field indicates the status of IP and L4 CS calculations done
6009 * by the chip. The format of this field is indicated by the
6010 * cs_all_ok_mode bit.
6011 * CS status for TPA packets is always valid. This means that "all_ok"
6012 * status will always be set. The ok count status will be set
6013 * appropriately for the packet header, such that all existing CS
6016 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
6018 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
6020 * This value is the complete 1's complement checksum calculated from
6021 * the start of the outer L3 header to the end of the packet (not
6022 * including the ethernet crc). It is valid when the
6023 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6024 * the complete checksum is calculated for the first packet in the
6027 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6028 UINT32_C(0xffff0000)
6029 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6031 * This is data from the CFA block as indicated by the meta_format
6033 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6034 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6035 * act_rec_ptr[25:0]}
6036 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6037 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6038 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6039 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
6040 * of the host address from the first BD used to place the packet.
6045 * This value is written by the NIC such that it will be different
6046 * for each pass through the completion queue. The even passes
6047 * will write 1. The odd passes will write 0.
6049 #define RX_TPA_START_V2_CMPL_V2 \
6051 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
6053 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
6055 * This error indicates that there was some sort of problem with
6056 * the BDs for the packetThe packet should be treated as
6059 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
6061 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6062 /* No buffer error */
6063 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6064 (UINT32_C(0x0) << 1)
6067 * Packet did not fit into packet buffer provided. This means
6068 * that the TPA Start packet was too big to be placed into the
6069 * per-packet maximum number of physical buffers configured for
6070 * the VNIC, or that it was too big to be placed into the
6071 * per-aggregation maximum number of physical buffers configured
6072 * for the VNIC. This error only occurs when the VNIC is
6073 * configured for variable size receive buffers.
6075 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
6076 (UINT32_C(0x1) << 1)
6079 * BDs were not formatted correctly.
6081 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6082 (UINT32_C(0x3) << 1)
6085 * There was a bad_format error on the previous operation
6087 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6088 (UINT32_C(0x5) << 1)
6089 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
6090 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6092 * This is data from the CFA block as indicated by the meta_format
6096 /* When meta_format != 0, this value is the VLAN VID. */
6097 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
6098 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
6099 /* When meta_format != 0, this value is the VLAN DE. */
6100 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
6101 /* When meta_format != 0, this value is the VLAN PRI. */
6102 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
6103 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
6105 * This field contains the outer_l3_offset, inner_l2_offset,
6106 * inner_l3_offset, and inner_l4_size.
6108 * hdr_offsets[8:0] contains the outer_l3_offset.
6109 * hdr_offsets[17:9] contains the inner_l2_offset.
6110 * hdr_offsets[26:18] contains the inner_l3_offset.
6111 * hdr_offsets[31:27] contains the inner_l4_size.
6113 uint32_t hdr_offsets;
6117 * This TPA completion structure is used on devices where the
6118 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6120 /* rx_tpa_end_cmpl (size:128b/16B) */
6121 struct rx_tpa_end_cmpl {
6122 uint16_t flags_type;
6124 * This field indicates the exact type of the completion.
6125 * By convention, the LSB identifies the length of the
6126 * record in 16B units. Even values indicate 16B
6127 * records. Odd values indicate 32B
6130 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
6131 #define RX_TPA_END_CMPL_TYPE_SFT 0
6133 * RX L2 TPA End Completion:
6134 * Completion at the end of a TPA operation.
6137 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
6138 #define RX_TPA_END_CMPL_TYPE_LAST \
6139 RX_TPA_END_CMPL_TYPE_RX_TPA_END
6140 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6141 #define RX_TPA_END_CMPL_FLAGS_SFT 6
6143 * When this bit is '1', it indicates a packet that has an
6144 * error of some type. Type of error is indicated in
6147 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
6148 /* This field indicates how the packet was placed in the buffer. */
6149 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6150 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
6153 * TPA Packet was placed using jumbo algorithm. This means
6154 * that the first buffer will be filled with data before
6155 * moving to aggregation buffers. Each aggregation buffer
6156 * will be filled before moving to the next aggregation
6159 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6160 (UINT32_C(0x1) << 7)
6162 * Header/Data Separation:
6163 * Packet was placed using Header/Data separation algorithm.
6164 * The separation location is indicated by the itype field.
6166 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
6167 (UINT32_C(0x2) << 7)
6170 * Packet will be placed using In-Order Completion/Jumbo where
6171 * the first packet of the aggregation is placed using Jumbo
6172 * Placement. Subsequent packets will be placed such that each
6173 * packet starts at the beginning of an aggregation buffer.
6175 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6176 (UINT32_C(0x4) << 7)
6179 * Packet will be placed using GRO/Jumbo where the first
6180 * packet is filled with data. Subsequent packets will be
6181 * placed such that any one packet does not span two
6182 * aggregation buffers unless it starts at the beginning of
6183 * an aggregation buffer.
6185 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6186 (UINT32_C(0x5) << 7)
6188 * GRO/Header-Data Separation:
6189 * Packet will be placed using GRO/HDS where the header
6190 * is in the first packet.
6191 * Payload of each packet will be
6192 * placed such that any one packet does not span two
6193 * aggregation buffers unless it starts at the beginning of
6194 * an aggregation buffer.
6196 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6197 (UINT32_C(0x6) << 7)
6199 * IOC/Header-Data Separation:
6200 * Packet will be placed using In-Order Completion/HDS where
6201 * the header is in the first packet buffer. Payload of each
6202 * packet will be placed such that each packet starts at the
6203 * beginning of an aggregation buffer.
6205 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6206 (UINT32_C(0x7) << 7)
6207 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
6208 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6210 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
6212 * This bit is '1' if metadata has been added to the end of the
6213 * packet in host memory. Metadata starts at the first 32B boundary
6214 * after the end of the packet for regular and jumbo placement.
6215 * It starts at the first 32B boundary after the end of the header
6216 * for HDS placement. The length of the metadata is indicated in the
6219 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6221 * This value indicates what the inner packet determined for the
6224 * Indicates that the packet was IP and TCP. This indicates
6225 * that the ip_cs field is valid and that the tcp_udp_cs
6226 * field is valid and contains the TCP checksum.
6227 * This also indicates that the payload_offset field is valid.
6229 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
6231 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
6233 * This value is zero for TPA End completions.
6234 * There is no data in the buffer that corresponds to the opaque
6235 * value in this completion.
6239 * This is a copy of the opaque field from the RX BD this completion
6244 * This value is written by the NIC such that it will be different
6245 * for each pass through the completion queue. The even passes
6246 * will write 1. The odd passes will write 0.
6248 uint8_t agg_bufs_v1;
6250 * This value is written by the NIC such that it will be different
6251 * for each pass through the completion queue. The even passes
6252 * will write 1. The odd passes will write 0.
6254 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
6256 * This value is the number of aggregation buffers that follow this
6257 * entry in the completion ring that are a part of this aggregation
6259 * If the value is zero, then the packet is completely contained
6260 * in the buffer space provided in the aggregation start completion.
6262 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
6263 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
6264 /* This value is the number of segments in the TPA operation. */
6267 * This value indicates the offset in bytes from the beginning of the packet
6268 * where the inner payload starts. This value is valid for TCP, UDP,
6269 * FCoE, and RoCE packets.
6271 * A value of zero indicates an offset of 256 bytes.
6273 uint8_t payload_offset;
6275 /* unused2 is 1 b */
6276 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
6278 * This is the aggregation ID that the completion is associated
6279 * with. Use this number to correlate the TPA start completion
6280 * with the TPA end completion.
6282 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
6283 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
6285 * For non-GRO packets, this value is the
6286 * timestamp delta between earliest and latest timestamp values for
6287 * TPA packet. If packets were not time stamped, then delta will be
6290 * For GRO packets, this field is zero except for the following
6293 * Timestamp present indication. When '0', no Timestamp
6294 * option is in the packet. When '1', then a Timestamp
6295 * option is present in the packet.
6301 * Last 16 bytes of rx_tpa_end_cmpl.
6303 * This TPA completion structure is used on devices where the
6304 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6306 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
6307 struct rx_tpa_end_cmpl_hi {
6308 uint32_t tpa_dup_acks;
6310 * This value is the number of duplicate ACKs that have been
6311 * received as part of the TPA operation.
6313 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6314 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
6316 * This value is the valid when TPA completion is active. It
6317 * indicates the length of the longest segment of the TPA operation
6318 * for LRO mode and the length of the first segment in GRO mode.
6320 * This value may be used by GRO software to re-construct the original
6321 * packet stream from the TPA packet. This is the length of all
6322 * but the last segment for GRO. In LRO mode this value may be used
6323 * to indicate MSS size to the stack.
6325 uint16_t tpa_seg_len;
6326 /* unused4 is 16 b */
6330 * This value is written by the NIC such that it will be different
6331 * for each pass through the completion queue. The even passes
6332 * will write 1. The odd passes will write 0.
6334 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
6335 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
6336 #define RX_TPA_END_CMPL_ERRORS_SFT 1
6338 * This error indicates that there was some sort of problem with
6339 * the BDs for the packet that was found after part of the
6340 * packet was already placed. The packet should be treated as
6343 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6344 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6346 * This error occurs when there is a fatal HW problem in
6347 * the chip only. It indicates that there were not
6348 * BDs on chip but that there was adequate reservation.
6349 * provided by the TPA block.
6351 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6352 (UINT32_C(0x2) << 1)
6354 * This error occurs when TPA block was not configured to
6355 * reserve adequate BDs for TPA operations on this RX
6356 * ring. All data for the TPA operation was not placed.
6358 * This error can also be generated when the number of
6359 * segments is not programmed correctly in TPA and the
6360 * 33 total aggregation buffers allowed for the TPA
6361 * operation has been exceeded.
6363 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6364 (UINT32_C(0x4) << 1)
6365 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6366 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
6367 /* unused5 is 16 b */
6370 * This is the opaque value that was completed for the TPA start
6371 * completion that corresponds to this TPA end completion.
6373 uint32_t start_opaque;
6377 * This TPA completion structure is used on devices where the
6378 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6380 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
6381 struct rx_tpa_v2_start_cmpl {
6382 uint16_t flags_type;
6384 * This field indicates the exact type of the completion.
6385 * By convention, the LSB identifies the length of the
6386 * record in 16B units. Even values indicate 16B
6387 * records. Odd values indicate 32B
6390 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
6392 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
6394 * RX L2 TPA Start Completion:
6395 * Completion at the beginning of a TPA operation.
6398 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
6400 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
6401 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
6402 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
6404 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
6405 /* This bit will always be '0' for TPA start completions. */
6406 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
6408 /* This field indicates how the packet was placed in the buffer. */
6409 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
6411 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
6414 * TPA Packet was placed using jumbo algorithm. This means
6415 * that the first buffer will be filled with data before
6416 * moving to aggregation buffers. Each aggregation buffer
6417 * will be filled before moving to the next aggregation
6420 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6421 (UINT32_C(0x1) << 7)
6423 * Header/Data Separation:
6424 * Packet was placed using Header/Data separation algorithm.
6425 * The separation location is indicated by the itype field.
6427 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
6428 (UINT32_C(0x2) << 7)
6431 * Packet will be placed using GRO/Jumbo where the first
6432 * packet is filled with data. Subsequent packets will be
6433 * placed such that any one packet does not span two
6434 * aggregation buffers unless it starts at the beginning of
6435 * an aggregation buffer.
6437 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6438 (UINT32_C(0x5) << 7)
6440 * GRO/Header-Data Separation:
6441 * Packet will be placed using GRO/HDS where the header
6442 * is in the first packet.
6443 * Payload of each packet will be
6444 * placed such that any one packet does not span two
6445 * aggregation buffers unless it starts at the beginning of
6446 * an aggregation buffer.
6448 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6449 (UINT32_C(0x6) << 7)
6450 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
6451 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6452 /* This bit is '1' if the RSS field in this completion is valid. */
6453 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
6456 * For devices that support timestamps, when this bit is cleared the
6457 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6458 * field contains the 32b timestamp for
6459 * the packet from the MAC. When this bit is set, the
6460 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6461 * field contains the outer_l3_offset, inner_l2_offset,
6462 * inner_l3_offset, and inner_l4_size.
6464 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
6467 * This value indicates what the inner packet determined for the
6470 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
6472 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
6475 * Indicates that the packet was IP and TCP.
6477 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
6478 (UINT32_C(0x2) << 12)
6479 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
6480 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
6482 * This value indicates the amount of packet data written to the
6483 * buffer the opaque field in this completion corresponds to.
6487 * This is a copy of the opaque field from the RX BD this completion
6492 * This value is written by the NIC such that it will be different
6493 * for each pass through the completion queue. The even passes
6494 * will write 1. The odd passes will write 0.
6498 * This value is written by the NIC such that it will be different
6499 * for each pass through the completion queue. The even passes
6500 * will write 1. The odd passes will write 0.
6502 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
6503 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
6505 * This is the RSS hash type for the packet. The value is packed
6506 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6508 * The value of tuple_extrac_op provides the information about
6509 * what fields the hash was computed on.
6510 * * 0: The RSS hash was computed over source IP address,
6511 * destination IP address, source port, and destination port of inner
6512 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6513 * the packet headers are considered inner packet headers for the RSS
6514 * hash computation purpose.
6515 * * 1: The RSS hash was computed over source IP address and destination
6516 * IP address of inner IP header. Note: For non-tunneled packets,
6517 * the packet headers are considered inner packet headers for the RSS
6518 * hash computation purpose.
6519 * * 2: The RSS hash was computed over source IP address,
6520 * destination IP address, source port, and destination port of
6521 * IP and TCP or UDP headers of outer tunnel headers.
6522 * Note: For non-tunneled packets, this value is not applicable.
6523 * * 3: The RSS hash was computed over source IP address and
6524 * destination IP address of IP header of outer tunnel headers.
6525 * Note: For non-tunneled packets, this value is not applicable.
6527 * Note that 4-tuples values listed above are applicable
6528 * for layer 4 protocols supported and enabled for RSS in the hardware,
6529 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6530 * enabled for TCP traffic only, then the values of tuple_extract_op
6531 * corresponding to 4-tuples are only valid for TCP traffic.
6533 uint8_t rss_hash_type;
6535 * This is the aggregation ID that the completion is associated
6536 * with. Use this number to correlate the TPA start completion
6537 * with the TPA end completion.
6541 * This value is the RSS hash value calculated for the packet
6542 * based on the mode bits and key value in the VNIC.
6548 * Last 16 bytes of rx_tpa_v2_start_cmpl.
6550 * This TPA completion structure is used on devices where the
6551 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6553 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
6554 struct rx_tpa_v2_start_cmpl_hi {
6557 * This indicates that the ip checksum was calculated for the
6558 * inner packet and that the sum passed for all segments
6559 * included in the aggregation.
6561 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
6564 * This indicates that the TCP, UDP or ICMP checksum was
6565 * calculated for the inner packet and that the sum passed
6566 * for all segments included in the aggregation.
6568 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
6571 * This indicates that the ip checksum was calculated for the
6572 * tunnel header and that the sum passed for all segments
6573 * included in the aggregation.
6575 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
6578 * This indicates that the UDP checksum was
6579 * calculated for the tunnel packet and that the sum passed for
6580 * all segments included in the aggregation.
6582 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
6584 /* This value indicates what format the metadata field is. */
6585 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
6587 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6588 /* No metadata informtaion. Value is zero. */
6589 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
6590 (UINT32_C(0x0) << 4)
6592 * The metadata field contains the VLAN tag and TPID value.
6593 * - metadata[11:0] contains the vlan VID value.
6594 * - metadata[12] contains the vlan DE value.
6595 * - metadata[15:13] contains the vlan PRI value.
6596 * - metadata[31:16] contains the vlan TPID value.
6598 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6599 (UINT32_C(0x1) << 4)
6601 * If ext_meta_format is equal to 1, the metadata field
6602 * contains the lower 16b of the tunnel ID value, justified
6604 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6605 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
6606 * - NVGRE = TNI[23:0] -> Tenant Network ID
6607 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
6608 * - IPV4 = 0 (not populated)
6609 * - IPV6 = Flow Label[19:0]
6610 * - PPPoE = sessionID[15:0]
6611 * - MPLs = Outer label[19:0]
6612 * - UPAR = Selected[31:0] with bit mask
6614 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
6615 (UINT32_C(0x2) << 4)
6617 * if ext_meta_format is equal to 1, metadata field contains
6618 * 16b metadata from the prepended header (chdr_data).
6620 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6621 (UINT32_C(0x3) << 4)
6623 * If ext_meta_format is equal to 1, the metadata field contains
6624 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
6626 * - metadata[8:0] contains the outer_l3_offset.
6627 * - metadata[17:9] contains the inner_l2_offset.
6628 * - metadata[26:18] contains the inner_l3_offset.
6629 * - metadata[31:27] contains the inner_l4_size.
6631 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6632 (UINT32_C(0x4) << 4)
6633 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
6634 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6636 * This field indicates the IP type for the inner-most IP header.
6637 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6639 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
6642 * This indicates that the complete 1's complement checksum was
6643 * calculated for the packet.
6645 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6648 * The combination of this value and meta_format indicated what
6649 * format the metadata field is.
6651 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
6653 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
6655 * This value is the complete 1's complement checksum calculated from
6656 * the start of the outer L3 header to the end of the packet (not
6657 * including the ethernet crc). It is valid when the
6658 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6659 * the complete checksum is calculated for the first packet in the
6662 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6663 UINT32_C(0xffff0000)
6664 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6666 * This is data from the CFA block as indicated by the meta_format
6670 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
6671 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6672 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
6673 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
6674 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
6675 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
6676 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6677 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
6678 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
6679 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6680 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
6683 * This value is written by the NIC such that it will be different
6684 * for each pass through the completion queue. The even passes
6685 * will write 1. The odd passes will write 0.
6687 #define RX_TPA_V2_START_CMPL_V2 \
6689 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
6691 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
6693 * This error indicates that there was some sort of problem with
6694 * the BDs for the packet that was found after part of the
6695 * packet was already placed. The packet should be treated as
6698 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
6700 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6701 /* No buffer error */
6702 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6703 (UINT32_C(0x0) << 1)
6706 * BDs were not formatted correctly.
6708 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6709 (UINT32_C(0x3) << 1)
6712 * There was a bad_format error on the previous operation
6714 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6715 (UINT32_C(0x5) << 1)
6716 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
6717 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6719 * This field identifies the CFA action rule that was used for this
6724 * For devices that support timestamps this field is overridden
6725 * with the timestamp value. When `flags.timestamp_fld_format` is
6726 * cleared, this field contains the 32b timestamp for the packet from the
6729 * When `flags.timestamp_fld_format` is set, this field contains the
6730 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
6733 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6735 * This is the offset from the beginning of the packet in bytes for
6736 * the outer L3 header. If there is no outer L3 header, then this
6739 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6740 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
6742 * This is the offset from the beginning of the packet in bytes for
6743 * the inner most L2 header.
6745 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6746 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
6748 * This is the offset from the beginning of the packet in bytes for
6749 * the inner most L3 header.
6751 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6752 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
6754 * This is the size in bytes of the inner most L4 header.
6755 * This can be subtracted from the payload_offset to determine
6756 * the start of the inner most L4 header.
6758 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6759 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
6763 * This TPA completion structure is used on devices where the
6764 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6766 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
6767 struct rx_tpa_v2_end_cmpl {
6768 uint16_t flags_type;
6770 * This field indicates the exact type of the completion.
6771 * By convention, the LSB identifies the length of the
6772 * record in 16B units. Even values indicate 16B
6773 * records. Odd values indicate 32B
6776 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
6778 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
6780 * RX L2 TPA End Completion:
6781 * Completion at the end of a TPA operation.
6784 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
6786 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
6787 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
6788 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
6790 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
6792 * When this bit is '1', it indicates a packet that has an
6793 * error of some type. Type of error is indicated in
6796 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
6798 /* This field indicates how the packet was placed in the buffer. */
6799 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
6801 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
6804 * TPA Packet was placed using jumbo algorithm. This means
6805 * that the first buffer will be filled with data before
6806 * moving to aggregation buffers. Each aggregation buffer
6807 * will be filled before moving to the next aggregation
6810 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6811 (UINT32_C(0x1) << 7)
6813 * Header/Data Separation:
6814 * Packet was placed using Header/Data separation algorithm.
6815 * The separation location is indicated by the itype field.
6817 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
6818 (UINT32_C(0x2) << 7)
6821 * Packet will be placed using GRO/Jumbo where the first
6822 * packet is filled with data. Subsequent packets will be
6823 * placed such that any one packet does not span two
6824 * aggregation buffers unless it starts at the beginning of
6825 * an aggregation buffer.
6827 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6828 (UINT32_C(0x5) << 7)
6830 * GRO/Header-Data Separation:
6831 * Packet will be placed using GRO/HDS where the header
6832 * is in the first packet.
6833 * Payload of each packet will be
6834 * placed such that any one packet does not span two
6835 * aggregation buffers unless it starts at the beginning of
6836 * an aggregation buffer.
6838 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6839 (UINT32_C(0x6) << 7)
6841 * IOC/Header-Data Separation:
6842 * Packet will be placed using In-Order Completion/HDS where
6843 * the header is in the first packet buffer. Payload of each
6844 * packet will be placed such that each packet starts at the
6845 * beginning of an aggregation buffer.
6847 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6848 (UINT32_C(0x7) << 7)
6849 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
6850 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6852 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
6855 * This bit is '1' if metadata has been added to the end of the
6856 * packet in host memory. Metadata starts at the first 32B boundary
6857 * after the end of the packet for regular and jumbo placement.
6858 * It starts at the first 32B boundary after the end of the header
6859 * for HDS placement. The length of the metadata is indicated in the
6862 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
6865 * This value indicates what the inner packet determined for the
6868 * Indicates that the packet was IP and TCP. This indicates
6869 * that the ip_cs field is valid and that the tcp_udp_cs
6870 * field is valid and contains the TCP checksum.
6871 * This also indicates that the payload_offset field is valid.
6873 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
6875 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
6877 * This value is zero for TPA End completions.
6878 * There is no data in the buffer that corresponds to the opaque
6879 * value in this completion.
6883 * This is a copy of the opaque field from the RX BD this completion
6889 * This value is written by the NIC such that it will be different
6890 * for each pass through the completion queue. The even passes
6891 * will write 1. The odd passes will write 0.
6893 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
6894 /* This value is the number of segments in the TPA operation. */
6897 * This is the aggregation ID that the completion is associated
6898 * with. Use this number to correlate the TPA start completion
6899 * with the TPA end completion.
6903 * For non-GRO packets, this value is the
6904 * timestamp delta between earliest and latest timestamp values for
6905 * TPA packet. If packets were not time stamped, then delta will be
6908 * For GRO packets, this field is zero except for the following
6911 * Timestamp present indication. When '0', no Timestamp
6912 * option is in the packet. When '1', then a Timestamp
6913 * option is present in the packet.
6919 * Last 16 bytes of rx_tpa_v2_end_cmpl.
6921 * This TPA completion structure is used on devices where the
6922 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6924 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
6925 struct rx_tpa_v2_end_cmpl_hi {
6927 * This value is the number of duplicate ACKs that have been
6928 * received as part of the TPA operation.
6930 uint16_t tpa_dup_acks;
6932 * This value is the number of duplicate ACKs that have been
6933 * received as part of the TPA operation.
6935 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6936 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
6938 * This value indicated the offset in bytes from the beginning of
6939 * the packet where the inner payload starts. This value is valid
6940 * for TCP, UDP, FCoE and RoCE packets
6942 uint8_t payload_offset;
6944 * The value is the total number of aggregation buffers that were
6945 * used in the TPA operation. All TPA aggregation buffer completions
6946 * precede the TPA End completion. If the value is zero, then the
6947 * aggregation is completely contained in the buffer space provided
6948 * in the aggregation start completion.
6949 * Note that the field is simply provided as a cross check.
6951 uint8_t tpa_agg_bufs;
6953 * This value is the valid when TPA completion is active. It
6954 * indicates the length of the longest segment of the TPA operation
6955 * for LRO mode and the length of the first segment in GRO mode.
6957 * This value may be used by GRO software to re-construct the original
6958 * packet stream from the TPA packet. This is the length of all
6959 * but the last segment for GRO. In LRO mode this value may be used
6960 * to indicate MSS size to the stack.
6962 uint16_t tpa_seg_len;
6966 * This value is written by the NIC such that it will be different
6967 * for each pass through the completion queue. The even passes
6968 * will write 1. The odd passes will write 0.
6970 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
6971 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
6973 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
6975 * This error indicates that there was some sort of problem with
6976 * the BDs for the packet that was found after part of the
6977 * packet was already placed. The packet should be treated as
6980 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
6982 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6983 /* No buffer error */
6984 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6985 (UINT32_C(0x0) << 1)
6987 * This error occurs when there is a fatal HW problem in
6988 * the chip only. It indicates that there were not
6989 * BDs on chip but that there was adequate reservation.
6990 * provided by the TPA block.
6992 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6993 (UINT32_C(0x2) << 1)
6996 * BDs were not formatted correctly.
6998 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6999 (UINT32_C(0x3) << 1)
7001 * This error occurs when TPA block was not configured to
7002 * reserve adequate BDs for TPA operations on this RX
7003 * ring. All data for the TPA operation was not placed.
7005 * This error can also be generated when the number of
7006 * segments is not programmed correctly in TPA and the
7007 * 33 total aggregation buffers allowed for the TPA
7008 * operation has been exceeded.
7010 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
7011 (UINT32_C(0x4) << 1)
7014 * There was a bad_format error on the previous operation
7016 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7017 (UINT32_C(0x5) << 1)
7018 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
7019 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7022 * This is the opaque value that was completed for the TPA start
7023 * completion that corresponds to this TPA end completion.
7025 uint32_t start_opaque;
7029 * This TPA completion structure is used on devices where the
7030 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
7032 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
7033 struct rx_tpa_v2_abuf_cmpl {
7036 * This field indicates the exact type of the completion.
7037 * By convention, the LSB identifies the length of the
7038 * record in 16B units. Even values indicate 16B
7039 * records. Odd values indicate 32B
7042 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7043 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
7045 * RX TPA Aggregation Buffer completion :
7046 * Completion of an L2 aggregation buffer in support of
7047 * TPA packet completion. Length = 16B
7049 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
7050 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
7051 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
7053 * This is the length of the data for the packet stored in this
7054 * aggregation buffer identified by the opaque value. This does not
7055 * include the length of any
7056 * data placed in other aggregation BDs or in the packet or buffer
7057 * BDs. This length does not include any space added due to
7058 * hdr_offset register during HDS placement mode.
7062 * This is a copy of the opaque field from the RX BD this aggregation
7063 * buffer corresponds to.
7068 * This value is written by the NIC such that it will be different
7069 * for each pass through the completion queue. The even passes
7070 * will write 1. The odd passes will write 0.
7072 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
7074 * This is the aggregation ID that the completion is associated with. Use
7075 * this number to correlate the TPA agg completion with the TPA start
7076 * completion and the TPA end completion.
7082 /* rx_abuf_cmpl (size:128b/16B) */
7083 struct rx_abuf_cmpl {
7086 * This field indicates the exact type of the completion.
7087 * By convention, the LSB identifies the length of the
7088 * record in 16B units. Even values indicate 16B
7089 * records. Odd values indicate 32B
7092 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7093 #define RX_ABUF_CMPL_TYPE_SFT 0
7095 * RX Aggregation Buffer completion :
7096 * Completion of an L2 aggregation buffer in support of
7097 * TPA, HDS, or Jumbo packet completion. Length = 16B
7099 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
7100 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
7102 * This is the length of the data for the packet stored in this
7103 * aggregation buffer identified by the opaque value. This does not
7104 * include the length of any
7105 * data placed in other aggregation BDs or in the packet or buffer
7106 * BDs. This length does not include any space added due to
7107 * hdr_offset register during HDS placement mode.
7111 * This is a copy of the opaque field from the RX BD this aggregation
7112 * buffer corresponds to.
7117 * This value is written by the NIC such that it will be different
7118 * for each pass through the completion queue. The even passes
7119 * will write 1. The odd passes will write 0.
7121 #define RX_ABUF_CMPL_V UINT32_C(0x1)
7122 /* unused3 is 32 b */
7126 /* VEE FLUSH Completion Record (16 bytes) */
7127 /* vee_flush (size:128b/16B) */
7129 uint32_t downstream_path_type;
7131 * This field indicates the exact type of the completion.
7132 * By convention, the LSB identifies the length of the
7133 * record in 16B units. Even values indicate 16B
7134 * records. Odd values indicate 32B
7137 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
7138 #define VEE_FLUSH_TYPE_SFT 0
7140 * VEE Flush Completion:
7141 * This completion is inserted manually by the Primate and processed
7142 * by the VEE hardware to ensure that all completions on a VEE
7143 * function have been processed by the VEE hardware before FLR
7144 * process is completed.
7146 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
7147 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
7148 /* downstream_path is 1 b */
7149 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
7150 /* This completion is associated with VEE Transmit */
7151 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
7152 /* This completion is associated with VEE Receive */
7153 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
7154 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
7156 * This is an opaque value that is passed through the completion
7157 * to the VEE handler SW and is used to indicate what VEE VQ or
7158 * function has completed FLR processing.
7163 * This value is written by the NIC such that it will be different
7164 * for each pass through the completion queue. The even passes will
7165 * write 1. The odd passes will write 0.
7167 #define VEE_FLUSH_V UINT32_C(0x1)
7168 /* unused3 is 32 b */
7172 /* eject_cmpl (size:128b/16B) */
7176 * This field indicates the exact type of the completion.
7177 * By convention, the LSB identifies the length of the
7178 * record in 16B units. Even values indicate 16B
7179 * records. Odd values indicate 32B
7182 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
7183 #define EJECT_CMPL_TYPE_SFT 0
7185 * Statistics Ejection Completion:
7186 * Completion of statistics data ejection buffer.
7189 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
7190 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
7191 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7192 #define EJECT_CMPL_FLAGS_SFT 6
7194 * When this bit is '1', it indicates a packet that has an
7195 * error of some type. Type of error is indicated in
7198 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
7200 * This is the length of the statistics data stored in this
7205 * This is a copy of the opaque field from the RX BD this ejection
7206 * buffer corresponds to.
7211 * This value is written by the NIC such that it will be different
7212 * for each pass through the completion queue. The even passes
7213 * will write 1. The odd passes will write 0.
7215 #define EJECT_CMPL_V UINT32_C(0x1)
7216 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7217 #define EJECT_CMPL_ERRORS_SFT 1
7219 * This error indicates that there was some sort of problem with
7220 * the BDs for statistics ejection. The statistics ejection should
7221 * be treated as invalid
7223 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7224 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7225 /* No buffer error */
7226 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7227 (UINT32_C(0x0) << 1)
7230 * Statistics did not fit into aggregation buffer provided.
7232 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7233 (UINT32_C(0x1) << 1)
7236 * BDs were not formatted correctly.
7238 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7239 (UINT32_C(0x3) << 1)
7242 * There was a bad_format error on the previous operation
7244 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7245 (UINT32_C(0x5) << 1)
7246 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
7247 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7248 /* reserved16 is 16 b */
7249 uint16_t reserved16;
7250 /* unused3 is 32 b */
7254 /* hwrm_cmpl (size:128b/16B) */
7258 * This field indicates the exact type of the completion.
7259 * By convention, the LSB identifies the length of the
7260 * record in 16B units. Even values indicate 16B
7261 * records. Odd values indicate 32B
7264 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
7265 #define HWRM_CMPL_TYPE_SFT 0
7267 * HWRM Command Completion:
7268 * Completion of an HWRM command.
7270 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
7271 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
7272 /* This is the sequence_id of the HWRM command that has completed. */
7273 uint16_t sequence_id;
7274 /* unused2 is 32 b */
7278 * This value is written by the NIC such that it will be different
7279 * for each pass through the completion queue. The even passes
7280 * will write 1. The odd passes will write 0.
7282 #define HWRM_CMPL_V UINT32_C(0x1)
7283 /* unused4 is 32 b */
7287 /* hwrm_fwd_req_cmpl (size:128b/16B) */
7288 struct hwrm_fwd_req_cmpl {
7290 * This field indicates the exact type of the completion.
7291 * By convention, the LSB identifies the length of the
7292 * record in 16B units. Even values indicate 16B
7293 * records. Odd values indicate 32B
7296 uint16_t req_len_type;
7298 * This field indicates the exact type of the completion.
7299 * By convention, the LSB identifies the length of the
7300 * record in 16B units. Even values indicate 16B
7301 * records. Odd values indicate 32B
7304 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
7305 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
7306 /* Forwarded HWRM Request */
7307 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
7308 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
7309 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
7310 /* Length of forwarded request in bytes. */
7311 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
7312 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
7314 * Source ID of this request.
7315 * Typically used in forwarding requests and responses.
7316 * 0x0 - 0xFFF8 - Used for function ids
7317 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7321 /* unused1 is 32 b */
7323 /* Address of forwarded request. */
7324 uint32_t req_buf_addr_v[2];
7326 * This value is written by the NIC such that it will be different
7327 * for each pass through the completion queue. The even passes
7328 * will write 1. The odd passes will write 0.
7330 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
7331 /* Address of forwarded request. */
7332 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7333 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
7336 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
7337 struct hwrm_fwd_resp_cmpl {
7340 * This field indicates the exact type of the completion.
7341 * By convention, the LSB identifies the length of the
7342 * record in 16B units. Even values indicate 16B
7343 * records. Odd values indicate 32B
7346 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
7347 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
7348 /* Forwarded HWRM Response */
7349 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
7350 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
7351 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
7353 * Source ID of this response.
7354 * Typically used in forwarding requests and responses.
7355 * 0x0 - 0xFFF8 - Used for function ids
7356 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7360 /* Length of forwarded response in bytes. */
7362 /* unused2 is 16 b */
7364 /* Address of forwarded request. */
7365 uint32_t resp_buf_addr_v[2];
7367 * This value is written by the NIC such that it will be different
7368 * for each pass through the completion queue. The even passes
7369 * will write 1. The odd passes will write 0.
7371 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
7372 /* Address of forwarded request. */
7373 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7374 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
7377 /* hwrm_async_event_cmpl (size:128b/16B) */
7378 struct hwrm_async_event_cmpl {
7381 * This field indicates the exact type of the completion.
7382 * By convention, the LSB identifies the length of the
7383 * record in 16B units. Even values indicate 16B
7384 * records. Odd values indicate 32B
7387 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
7388 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
7389 /* HWRM Asynchronous Event Information */
7390 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
7391 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
7392 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
7393 /* Identifiers of events. */
7395 /* Link status changed */
7396 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
7398 /* Link MTU changed */
7399 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
7401 /* Link speed changed */
7402 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
7404 /* DCB Configuration changed */
7405 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
7407 /* Port connection not allowed */
7408 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7410 /* Link speed configuration was not allowed */
7411 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7413 /* Link speed configuration change */
7414 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7416 /* Port PHY configuration change */
7417 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
7419 /* Reset notification to clients */
7420 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
7422 /* Master function selection event */
7423 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
7426 * An event signifying that a ring has been disabled by
7429 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
7431 /* Function driver unloaded */
7432 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
7434 /* Function driver loaded */
7435 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
7437 /* Function FLR related processing has completed */
7438 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7440 /* PF driver unloaded */
7441 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
7443 /* PF driver loaded */
7444 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
7446 /* VF Function Level Reset (FLR) */
7447 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
7449 /* VF MAC Address Change */
7450 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
7452 /* PF-VF communication channel status change. */
7453 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7455 /* VF Configuration Change */
7456 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
7458 /* LLFC/PFC Configuration Change */
7459 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
7461 /* Default VNIC Configuration Change */
7462 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
7465 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
7468 * A debug notification being posted to the driver. These
7469 * notifications are purely for diagnostic purpose and should not be
7470 * used for functional purpose. The driver is not supposed to act
7471 * on these messages except to log/record it.
7473 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
7476 * An EEM flow cached memory flush for all flows request event being
7477 * posted to the PF driver.
7479 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7482 * An EEM flow cache memory flush completion event being posted to the
7483 * firmware by the PF driver. This is indication that host EEM flush
7484 * has completed by the PF.
7486 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7489 * A tcp flag action change event being posted to the PF or trusted VF
7490 * driver by the firmware. The PF or trusted VF driver should query
7491 * the firmware for the new TCP flag action update after receiving
7494 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7497 * An EEM flow active event being posted to the PF or trusted VF driver
7498 * by the firmware. The PF or trusted VF driver should update the
7499 * flow's aging timer after receiving this async event.
7501 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
7504 * A eem cfg change event being posted to the trusted VF driver by the
7505 * firmware if the parent PF EEM configuration changed.
7507 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
7511 * TFLIB unique default VNIC Configuration Change
7513 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
7517 * TFLIB unique link status changed
7519 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
7522 * An event signifying completion for HWRM_FW_STATE_QUIESCE
7523 * (completion, timeout, or error)
7525 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
7528 * An event signifying a HWRM command is in progress and its
7529 * response will be deferred. This event is used on crypto controllers
7532 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
7535 * An event signifying that a PFC WatchDog configuration
7536 * has changed on any port / cos.
7538 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
7541 * An echo request from the firmware. An echo response is expected by
7544 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
7547 * An event from firmware indicating who has been selected as the
7548 * PHC Master or secondary. Also indicates the last time a failover
7551 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER \
7554 * An event from firmware showing the last PPS timestamp that has been
7557 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \
7560 * An event from firmware indicating that an error has occurred.
7561 * The driver should log the event so that an administrator can be
7562 * aware that a problem has occurred that may need attention.
7564 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \
7566 /* Maximum Registrable event id. */
7567 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
7570 * A trace log message. This contains firmware trace logs string
7571 * embedded in the asynchronous message. This is an experimental
7572 * event, not meant for production use at this time.
7574 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
7577 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
7579 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
7580 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
7581 /* Event specific data */
7582 uint32_t event_data2;
7585 * This value is written by the NIC such that it will be different
7586 * for each pass through the completion queue. The even passes
7587 * will write 1. The odd passes will write 0.
7589 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
7591 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
7592 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
7593 /* 8-lsb timestamp from POR (100-msec resolution) */
7594 uint8_t timestamp_lo;
7595 /* 16-lsb timestamp from POR (100-msec resolution) */
7596 uint16_t timestamp_hi;
7597 /* Event specific data */
7598 uint32_t event_data1;
7601 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
7602 struct hwrm_async_event_cmpl_link_status_change {
7605 * This field indicates the exact type of the completion.
7606 * By convention, the LSB identifies the length of the
7607 * record in 16B units. Even values indicate 16B
7608 * records. Odd values indicate 32B
7611 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
7613 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
7614 /* HWRM Asynchronous Event Information */
7615 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7617 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
7618 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7619 /* Identifiers of events. */
7621 /* Link status changed */
7622 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
7624 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
7625 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
7626 /* Event specific data */
7627 uint32_t event_data2;
7630 * This value is written by the NIC such that it will be different
7631 * for each pass through the completion queue. The even passes
7632 * will write 1. The odd passes will write 0.
7634 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
7637 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
7639 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
7640 /* 8-lsb timestamp from POR (100-msec resolution) */
7641 uint8_t timestamp_lo;
7642 /* 16-lsb timestamp from POR (100-msec resolution) */
7643 uint16_t timestamp_hi;
7644 /* Event specific data */
7645 uint32_t event_data1;
7646 /* Indicates link status change */
7647 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
7650 * If this bit set to 0, then it indicates that the link
7651 * was up and it went down.
7653 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
7656 * If this bit is set to 1, then it indicates that the link
7657 * was down and it went up.
7659 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
7661 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
7662 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
7663 /* Indicates the physical port this link status change occur */
7664 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
7666 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
7669 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7671 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7673 /* Indicates the physical function this event occurred on. */
7674 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
7676 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
7680 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
7681 struct hwrm_async_event_cmpl_link_mtu_change {
7684 * This field indicates the exact type of the completion.
7685 * By convention, the LSB identifies the length of the
7686 * record in 16B units. Even values indicate 16B
7687 * records. Odd values indicate 32B
7690 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
7692 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
7693 /* HWRM Asynchronous Event Information */
7694 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7696 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
7697 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
7698 /* Identifiers of events. */
7700 /* Link MTU changed */
7701 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
7703 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
7704 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
7705 /* Event specific data */
7706 uint32_t event_data2;
7709 * This value is written by the NIC such that it will be different
7710 * for each pass through the completion queue. The even passes
7711 * will write 1. The odd passes will write 0.
7713 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
7715 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
7717 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
7718 /* 8-lsb timestamp from POR (100-msec resolution) */
7719 uint8_t timestamp_lo;
7720 /* 16-lsb timestamp from POR (100-msec resolution) */
7721 uint16_t timestamp_hi;
7722 /* Event specific data */
7723 uint32_t event_data1;
7724 /* The new MTU of the link in bytes. */
7725 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
7727 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
7730 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
7731 struct hwrm_async_event_cmpl_link_speed_change {
7734 * This field indicates the exact type of the completion.
7735 * By convention, the LSB identifies the length of the
7736 * record in 16B units. Even values indicate 16B
7737 * records. Odd values indicate 32B
7740 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
7742 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
7743 /* HWRM Asynchronous Event Information */
7744 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7746 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
7747 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
7748 /* Identifiers of events. */
7750 /* Link speed changed */
7751 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
7753 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
7754 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
7755 /* Event specific data */
7756 uint32_t event_data2;
7759 * This value is written by the NIC such that it will be different
7760 * for each pass through the completion queue. The even passes
7761 * will write 1. The odd passes will write 0.
7763 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
7766 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
7768 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
7769 /* 8-lsb timestamp from POR (100-msec resolution) */
7770 uint8_t timestamp_lo;
7771 /* 16-lsb timestamp from POR (100-msec resolution) */
7772 uint16_t timestamp_hi;
7773 /* Event specific data */
7774 uint32_t event_data1;
7776 * When this bit is '1', the link was forced to the
7777 * force_link_speed value.
7779 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
7781 /* The new link speed in 100 Mbps units. */
7782 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
7784 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
7786 /* 100Mb link speed */
7787 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
7788 (UINT32_C(0x1) << 1)
7789 /* 1Gb link speed */
7790 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
7791 (UINT32_C(0xa) << 1)
7792 /* 2Gb link speed */
7793 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
7794 (UINT32_C(0x14) << 1)
7795 /* 25Gb link speed */
7796 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
7797 (UINT32_C(0x19) << 1)
7798 /* 10Gb link speed */
7799 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
7800 (UINT32_C(0x64) << 1)
7801 /* 20Mb link speed */
7802 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
7803 (UINT32_C(0xc8) << 1)
7804 /* 25Gb link speed */
7805 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
7806 (UINT32_C(0xfa) << 1)
7807 /* 40Gb link speed */
7808 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
7809 (UINT32_C(0x190) << 1)
7810 /* 50Gb link speed */
7811 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
7812 (UINT32_C(0x1f4) << 1)
7813 /* 100Gb link speed */
7814 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
7815 (UINT32_C(0x3e8) << 1)
7816 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
7817 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
7819 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7820 UINT32_C(0xffff0000)
7821 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7825 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
7826 struct hwrm_async_event_cmpl_dcb_config_change {
7829 * This field indicates the exact type of the completion.
7830 * By convention, the LSB identifies the length of the
7831 * record in 16B units. Even values indicate 16B
7832 * records. Odd values indicate 32B
7835 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
7837 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
7838 /* HWRM Asynchronous Event Information */
7839 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7841 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
7842 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7843 /* Identifiers of events. */
7845 /* DCB Configuration changed */
7846 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
7848 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
7849 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
7850 /* Event specific data */
7851 uint32_t event_data2;
7852 /* ETS configuration change */
7853 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
7855 /* PFC configuration change */
7856 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
7858 /* APP configuration change */
7859 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
7861 /* DSCP configuration change */
7862 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \
7866 * This value is written by the NIC such that it will be different
7867 * for each pass through the completion queue. The even passes
7868 * will write 1. The odd passes will write 0.
7870 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
7873 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
7875 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
7876 /* 8-lsb timestamp from POR (100-msec resolution) */
7877 uint8_t timestamp_lo;
7878 /* 16-lsb timestamp from POR (100-msec resolution) */
7879 uint16_t timestamp_hi;
7880 /* Event specific data */
7881 uint32_t event_data1;
7883 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7885 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7887 /* Priority recommended for RoCE traffic */
7888 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
7890 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
7893 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
7894 (UINT32_C(0xff) << 16)
7895 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
7896 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
7897 /* Priority recommended for L2 traffic */
7898 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
7899 UINT32_C(0xff000000)
7900 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
7903 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
7904 (UINT32_C(0xff) << 24)
7905 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
7906 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
7909 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
7910 struct hwrm_async_event_cmpl_port_conn_not_allowed {
7913 * This field indicates the exact type of the completion.
7914 * By convention, the LSB identifies the length of the
7915 * record in 16B units. Even values indicate 16B
7916 * records. Odd values indicate 32B
7919 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
7921 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
7923 /* HWRM Asynchronous Event Information */
7924 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7926 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
7927 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7928 /* Identifiers of events. */
7930 /* Port connection not allowed */
7931 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7933 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
7934 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
7935 /* Event specific data */
7936 uint32_t event_data2;
7939 * This value is written by the NIC such that it will be different
7940 * for each pass through the completion queue. The even passes
7941 * will write 1. The odd passes will write 0.
7943 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
7946 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
7948 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
7949 /* 8-lsb timestamp from POR (100-msec resolution) */
7950 uint8_t timestamp_lo;
7951 /* 16-lsb timestamp from POR (100-msec resolution) */
7952 uint16_t timestamp_hi;
7953 /* Event specific data */
7954 uint32_t event_data1;
7956 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7958 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7961 * This value indicates the current port level enforcement policy
7962 * for the optics module when there is an optical module mismatch
7963 * and port is not connected.
7965 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
7967 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
7969 /* No enforcement */
7970 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
7971 (UINT32_C(0x0) << 16)
7972 /* Disable Transmit side Laser. */
7973 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
7974 (UINT32_C(0x1) << 16)
7975 /* Raise a warning message. */
7976 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
7977 (UINT32_C(0x2) << 16)
7978 /* Power down the module. */
7979 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
7980 (UINT32_C(0x3) << 16)
7981 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
7982 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
7985 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
7986 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
7989 * This field indicates the exact type of the completion.
7990 * By convention, the LSB identifies the length of the
7991 * record in 16B units. Even values indicate 16B
7992 * records. Odd values indicate 32B
7995 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
7997 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
7999 /* HWRM Asynchronous Event Information */
8000 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
8002 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
8003 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
8004 /* Identifiers of events. */
8006 /* Link speed configuration was not allowed */
8007 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
8009 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
8010 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
8011 /* Event specific data */
8012 uint32_t event_data2;
8015 * This value is written by the NIC such that it will be different
8016 * for each pass through the completion queue. The even passes
8017 * will write 1. The odd passes will write 0.
8019 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
8022 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
8024 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
8025 /* 8-lsb timestamp from POR (100-msec resolution) */
8026 uint8_t timestamp_lo;
8027 /* 16-lsb timestamp from POR (100-msec resolution) */
8028 uint16_t timestamp_hi;
8029 /* Event specific data */
8030 uint32_t event_data1;
8032 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
8034 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
8038 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
8039 struct hwrm_async_event_cmpl_link_speed_cfg_change {
8042 * This field indicates the exact type of the completion.
8043 * By convention, the LSB identifies the length of the
8044 * record in 16B units. Even values indicate 16B
8045 * records. Odd values indicate 32B
8048 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
8050 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
8052 /* HWRM Asynchronous Event Information */
8053 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8055 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
8056 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8057 /* Identifiers of events. */
8059 /* Link speed configuration change */
8060 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
8062 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
8063 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
8064 /* Event specific data */
8065 uint32_t event_data2;
8068 * This value is written by the NIC such that it will be different
8069 * for each pass through the completion queue. The even passes
8070 * will write 1. The odd passes will write 0.
8072 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
8075 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
8077 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
8078 /* 8-lsb timestamp from POR (100-msec resolution) */
8079 uint8_t timestamp_lo;
8080 /* 16-lsb timestamp from POR (100-msec resolution) */
8081 uint16_t timestamp_hi;
8082 /* Event specific data */
8083 uint32_t event_data1;
8085 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8087 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8090 * If set to 1, it indicates that the supported link speeds
8091 * configuration on the port has changed.
8092 * If set to 0, then there is no change in supported link speeds
8095 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
8098 * If set to 1, it indicates that the link speed configuration
8099 * on the port has become illegal or invalid.
8100 * If set to 0, then the link speed configuration on the port is
8103 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
8107 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
8108 struct hwrm_async_event_cmpl_port_phy_cfg_change {
8111 * This field indicates the exact type of the completion.
8112 * By convention, the LSB identifies the length of the
8113 * record in 16B units. Even values indicate 16B
8114 * records. Odd values indicate 32B
8117 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
8119 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
8121 /* HWRM Asynchronous Event Information */
8122 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8124 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
8125 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8126 /* Identifiers of events. */
8128 /* Port PHY configuration change */
8129 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
8131 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
8132 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
8133 /* Event specific data */
8134 uint32_t event_data2;
8137 * This value is written by the NIC such that it will be different
8138 * for each pass through the completion queue. The even passes
8139 * will write 1. The odd passes will write 0.
8141 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
8144 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
8146 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
8147 /* 8-lsb timestamp from POR (100-msec resolution) */
8148 uint8_t timestamp_lo;
8149 /* 16-lsb timestamp from POR (100-msec resolution) */
8150 uint16_t timestamp_hi;
8151 /* Event specific data */
8152 uint32_t event_data1;
8154 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8156 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8159 * If set to 1, it indicates that the FEC
8160 * configuration on the port has changed.
8161 * If set to 0, then there is no change in FEC configuration.
8163 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
8166 * If set to 1, it indicates that the EEE configuration
8167 * on the port has changed.
8168 * If set to 0, then there is no change in EEE configuration
8171 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
8174 * If set to 1, it indicates that the pause configuration
8175 * on the PHY has changed.
8176 * If set to 0, then there is no change in the pause
8177 * configuration on the PHY.
8179 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
8183 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
8184 struct hwrm_async_event_cmpl_reset_notify {
8187 * This field indicates the exact type of the completion.
8188 * By convention, the LSB identifies the length of the
8189 * record in 16B units. Even values indicate 16B
8190 * records. Odd values indicate 32B
8193 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
8195 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
8196 /* HWRM Asynchronous Event Information */
8197 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
8199 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
8200 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
8201 /* Identifiers of events. */
8203 /* Notify clients of imminent reset. */
8204 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
8206 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
8207 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
8208 /* Event specific data. The data is for internal debug use only. */
8209 uint32_t event_data2;
8211 * These bits indicate the status as being reported by the firmware.
8212 * This value is exactly the same as status code in fw_status register.
8213 * If the status code is equal to 0x8000, then the reset is initiated
8214 * by the Host using the FW_RESET command when the FW is in a healthy
8215 * state. If the status code is not equal to 0x8000, then the reset is
8216 * initiated by the FW to recover from the error or FATAL state.
8218 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
8220 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
8224 * This value is written by the NIC such that it will be different
8225 * for each pass through the completion queue. The even passes
8226 * will write 1. The odd passes will write 0.
8228 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
8230 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
8231 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
8233 * 8-lsb timestamp (100-msec resolution)
8234 * The Minimum time required for the Firmware readiness after sending this
8235 * notification to the driver instances.
8237 uint8_t timestamp_lo;
8239 * 16-lsb timestamp (100-msec resolution)
8240 * The Maximum Firmware Reset bail out value in the order of 100
8241 * milli seconds. The driver instances will use this value to re-initiate the
8242 * registration process again if the core firmware didn’t set the ready
8245 uint16_t timestamp_hi;
8246 /* Event specific data */
8247 uint32_t event_data1;
8248 /* Indicates driver action requested */
8249 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
8251 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
8254 * If set to 1, it indicates that the l2 client should
8255 * stop sending in band traffic to Nitro.
8256 * if set to 0, there is no change in L2 client behavior.
8258 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
8261 * If set to 1, it indicates that the L2 client should
8262 * bring down the interface.
8263 * If set to 0, then there is no change in L2 client behavior.
8265 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
8267 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
8268 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
8269 /* Indicates reason for reset. */
8270 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
8272 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
8274 /* A management client has requested reset. */
8275 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
8276 (UINT32_C(0x1) << 8)
8277 /* A fatal firmware exception has occurred. */
8278 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
8279 (UINT32_C(0x2) << 8)
8280 /* A non-fatal firmware exception has occurred. */
8281 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
8282 (UINT32_C(0x3) << 8)
8284 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
8285 (UINT32_C(0x4) << 8)
8286 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
8287 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET
8289 * Minimum time before driver should attempt access - units 100ms ticks.
8292 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
8293 UINT32_C(0xffff0000)
8294 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
8298 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
8299 struct hwrm_async_event_cmpl_error_recovery {
8302 * This field indicates the exact type of the completion.
8303 * By convention, the LSB identifies the length of the
8304 * record in 16B units. Even values indicate 16B
8305 * records. Odd values indicate 32B
8308 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
8310 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
8311 /* HWRM Asynchronous Event Information */
8312 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
8314 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
8315 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
8316 /* Identifiers of events. */
8319 * This async notification message can be used for selecting or
8320 * deselecting master function for error recovery,
8321 * and to communicate to all the functions whether error recovery
8322 * was enabled/disabled.
8324 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
8326 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
8327 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
8328 /* Event specific data */
8329 uint32_t event_data2;
8332 * This value is written by the NIC such that it will be different
8333 * for each pass through the completion queue. The even passes
8334 * will write 1. The odd passes will write 0.
8336 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
8338 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
8339 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
8340 /* 8-lsb timestamp (100-msec resolution) */
8341 uint8_t timestamp_lo;
8342 /* 16-lsb timestamp (100-msec resolution) */
8343 uint16_t timestamp_hi;
8344 /* Event specific data */
8345 uint32_t event_data1;
8346 /* Indicates driver action requested */
8347 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
8349 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
8352 * If set to 1, this function is selected as Master function.
8353 * This function has responsibility to do 'chip reset' when it
8354 * detects a fatal error. If set to 0, master function functionality
8355 * is disabled on this function.
8357 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
8360 * If set to 1, error recovery is enabled.
8361 * If set to 0, error recovery is disabled.
8363 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
8367 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
8368 struct hwrm_async_event_cmpl_ring_monitor_msg {
8371 * This field indicates the exact type of the completion.
8372 * By convention, the LSB identifies the length of the
8373 * record in 16B units. Even values indicate 16B
8374 * records. Odd values indicate 32B
8377 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
8379 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
8380 /* HWRM Asynchronous Event Information */
8381 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
8383 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
8384 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
8385 /* Identifiers of events. */
8387 /* Ring Monitor Message. */
8388 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
8390 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
8391 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
8392 /* Event specific data */
8393 uint32_t event_data2;
8394 /* Type of Ring disabled. */
8395 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
8397 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
8399 /* tx ring disabled. */
8400 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
8402 /* rx ring disabled. */
8403 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
8405 /* cmpl ring disabled. */
8406 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
8408 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
8409 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
8412 * This value is written by the NIC such that it will be different
8413 * for each pass through the completion queue. The even passes
8414 * will write 1. The odd passes will write 0.
8416 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
8418 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
8420 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
8421 /* 8-lsb timestamp from POR (100-msec resolution) */
8422 uint8_t timestamp_lo;
8423 /* 16-lsb timestamp from POR (100-msec resolution) */
8424 uint16_t timestamp_hi;
8426 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
8427 * then this field will indicate the ring id.
8429 uint32_t event_data1;
8432 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
8433 struct hwrm_async_event_cmpl_func_drvr_unload {
8436 * This field indicates the exact type of the completion.
8437 * By convention, the LSB identifies the length of the
8438 * record in 16B units. Even values indicate 16B
8439 * records. Odd values indicate 32B
8442 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
8444 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
8445 /* HWRM Asynchronous Event Information */
8446 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8448 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
8449 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8450 /* Identifiers of events. */
8452 /* Function driver unloaded */
8453 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
8455 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
8456 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
8457 /* Event specific data */
8458 uint32_t event_data2;
8461 * This value is written by the NIC such that it will be different
8462 * for each pass through the completion queue. The even passes
8463 * will write 1. The odd passes will write 0.
8465 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
8467 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
8469 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
8470 /* 8-lsb timestamp from POR (100-msec resolution) */
8471 uint8_t timestamp_lo;
8472 /* 16-lsb timestamp from POR (100-msec resolution) */
8473 uint16_t timestamp_hi;
8474 /* Event specific data */
8475 uint32_t event_data1;
8477 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8479 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
8483 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
8484 struct hwrm_async_event_cmpl_func_drvr_load {
8487 * This field indicates the exact type of the completion.
8488 * By convention, the LSB identifies the length of the
8489 * record in 16B units. Even values indicate 16B
8490 * records. Odd values indicate 32B
8493 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
8495 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
8496 /* HWRM Asynchronous Event Information */
8497 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8499 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
8500 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8501 /* Identifiers of events. */
8503 /* Function driver loaded */
8504 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
8506 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
8507 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
8508 /* Event specific data */
8509 uint32_t event_data2;
8512 * This value is written by the NIC such that it will be different
8513 * for each pass through the completion queue. The even passes
8514 * will write 1. The odd passes will write 0.
8516 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
8518 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8519 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
8520 /* 8-lsb timestamp from POR (100-msec resolution) */
8521 uint8_t timestamp_lo;
8522 /* 16-lsb timestamp from POR (100-msec resolution) */
8523 uint16_t timestamp_hi;
8524 /* Event specific data */
8525 uint32_t event_data1;
8527 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8529 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8532 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
8533 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
8536 * This field indicates the exact type of the completion.
8537 * By convention, the LSB identifies the length of the
8538 * record in 16B units. Even values indicate 16B
8539 * records. Odd values indicate 32B
8542 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
8544 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
8546 /* HWRM Asynchronous Event Information */
8547 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
8549 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
8550 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
8551 /* Identifiers of events. */
8553 /* Function FLR related processing has completed */
8554 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
8556 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
8557 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
8558 /* Event specific data */
8559 uint32_t event_data2;
8562 * This value is written by the NIC such that it will be different
8563 * for each pass through the completion queue. The even passes
8564 * will write 1. The odd passes will write 0.
8566 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
8569 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
8571 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
8572 /* 8-lsb timestamp from POR (100-msec resolution) */
8573 uint8_t timestamp_lo;
8574 /* 16-lsb timestamp from POR (100-msec resolution) */
8575 uint16_t timestamp_hi;
8576 /* Event specific data */
8577 uint32_t event_data1;
8579 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
8581 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
8585 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
8586 struct hwrm_async_event_cmpl_pf_drvr_unload {
8589 * This field indicates the exact type of the completion.
8590 * By convention, the LSB identifies the length of the
8591 * record in 16B units. Even values indicate 16B
8592 * records. Odd values indicate 32B
8595 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
8597 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
8598 /* HWRM Asynchronous Event Information */
8599 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8601 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
8602 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8603 /* Identifiers of events. */
8605 /* PF driver unloaded */
8606 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
8608 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
8609 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
8610 /* Event specific data */
8611 uint32_t event_data2;
8614 * This value is written by the NIC such that it will be different
8615 * for each pass through the completion queue. The even passes
8616 * will write 1. The odd passes will write 0.
8618 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
8620 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
8621 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
8622 /* 8-lsb timestamp from POR (100-msec resolution) */
8623 uint8_t timestamp_lo;
8624 /* 16-lsb timestamp from POR (100-msec resolution) */
8625 uint16_t timestamp_hi;
8626 /* Event specific data */
8627 uint32_t event_data1;
8629 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8631 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
8632 /* Indicates the physical port this pf belongs to */
8633 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
8635 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
8638 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
8639 struct hwrm_async_event_cmpl_pf_drvr_load {
8642 * This field indicates the exact type of the completion.
8643 * By convention, the LSB identifies the length of the
8644 * record in 16B units. Even values indicate 16B
8645 * records. Odd values indicate 32B
8648 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
8650 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
8651 /* HWRM Asynchronous Event Information */
8652 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8654 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
8655 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8656 /* Identifiers of events. */
8658 /* PF driver loaded */
8659 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
8661 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
8662 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
8663 /* Event specific data */
8664 uint32_t event_data2;
8667 * This value is written by the NIC such that it will be different
8668 * for each pass through the completion queue. The even passes
8669 * will write 1. The odd passes will write 0.
8671 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
8673 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8674 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
8675 /* 8-lsb timestamp from POR (100-msec resolution) */
8676 uint8_t timestamp_lo;
8677 /* 16-lsb timestamp from POR (100-msec resolution) */
8678 uint16_t timestamp_hi;
8679 /* Event specific data */
8680 uint32_t event_data1;
8682 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8684 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8685 /* Indicates the physical port this pf belongs to */
8686 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
8688 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
8691 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
8692 struct hwrm_async_event_cmpl_vf_flr {
8695 * This field indicates the exact type of the completion.
8696 * By convention, the LSB identifies the length of the
8697 * record in 16B units. Even values indicate 16B
8698 * records. Odd values indicate 32B
8701 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
8703 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
8704 /* HWRM Asynchronous Event Information */
8705 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
8707 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
8708 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
8709 /* Identifiers of events. */
8711 /* VF Function Level Reset (FLR) */
8712 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
8713 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
8714 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
8715 /* Event specific data */
8716 uint32_t event_data2;
8719 * This value is written by the NIC such that it will be different
8720 * for each pass through the completion queue. The even passes
8721 * will write 1. The odd passes will write 0.
8723 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
8725 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
8726 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
8727 /* 8-lsb timestamp from POR (100-msec resolution) */
8728 uint8_t timestamp_lo;
8729 /* 16-lsb timestamp from POR (100-msec resolution) */
8730 uint16_t timestamp_hi;
8731 /* Event specific data */
8732 uint32_t event_data1;
8734 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
8736 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
8737 /* Indicates the physical function this event occurred on. */
8738 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
8740 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
8743 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
8744 struct hwrm_async_event_cmpl_vf_mac_addr_change {
8747 * This field indicates the exact type of the completion.
8748 * By convention, the LSB identifies the length of the
8749 * record in 16B units. Even values indicate 16B
8750 * records. Odd values indicate 32B
8753 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
8755 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
8756 /* HWRM Asynchronous Event Information */
8757 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8759 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
8760 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
8761 /* Identifiers of events. */
8763 /* VF MAC Address Change */
8764 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
8766 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
8767 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
8768 /* Event specific data */
8769 uint32_t event_data2;
8772 * This value is written by the NIC such that it will be different
8773 * for each pass through the completion queue. The even passes
8774 * will write 1. The odd passes will write 0.
8776 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
8779 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
8781 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
8782 /* 8-lsb timestamp from POR (100-msec resolution) */
8783 uint8_t timestamp_lo;
8784 /* 16-lsb timestamp from POR (100-msec resolution) */
8785 uint16_t timestamp_hi;
8786 /* Event specific data */
8787 uint32_t event_data1;
8789 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
8791 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
8795 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
8796 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
8799 * This field indicates the exact type of the completion.
8800 * By convention, the LSB identifies the length of the
8801 * record in 16B units. Even values indicate 16B
8802 * records. Odd values indicate 32B
8805 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
8807 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
8809 /* HWRM Asynchronous Event Information */
8810 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8812 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
8813 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
8814 /* Identifiers of events. */
8816 /* PF-VF communication channel status change. */
8817 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
8819 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
8820 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
8821 /* Event specific data */
8822 uint32_t event_data2;
8825 * This value is written by the NIC such that it will be different
8826 * for each pass through the completion queue. The even passes
8827 * will write 1. The odd passes will write 0.
8829 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
8832 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
8834 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
8835 /* 8-lsb timestamp from POR (100-msec resolution) */
8836 uint8_t timestamp_lo;
8837 /* 16-lsb timestamp from POR (100-msec resolution) */
8838 uint16_t timestamp_hi;
8839 /* Event specific data */
8840 uint32_t event_data1;
8842 * If this bit is set to 1, then it indicates that the PF-VF
8843 * communication was lost and it is established.
8844 * If this bit set to 0, then it indicates that the PF-VF
8845 * communication was established and it is lost.
8847 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
8851 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
8852 struct hwrm_async_event_cmpl_vf_cfg_change {
8855 * This field indicates the exact type of the completion.
8856 * By convention, the LSB identifies the length of the
8857 * record in 16B units. Even values indicate 16B
8858 * records. Odd values indicate 32B
8861 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
8863 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
8864 /* HWRM Asynchronous Event Information */
8865 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8867 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
8868 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8869 /* Identifiers of events. */
8871 /* VF Configuration Change */
8872 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
8874 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
8875 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
8876 /* Event specific data */
8877 uint32_t event_data2;
8879 * This value indicates the VF ID of the VF whose configuration
8880 * is changing if this async. event is sent to the parent PF.
8881 * The firmware supports sending this to the parent PF if the
8882 * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1.
8883 * This value is undefined when the async. event is sent to the
8886 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \
8888 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
8891 * This value is written by the NIC such that it will be different
8892 * for each pass through the completion queue. The even passes
8893 * will write 1. The odd passes will write 0.
8895 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
8897 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
8898 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
8899 /* 8-lsb timestamp from POR (100-msec resolution) */
8900 uint8_t timestamp_lo;
8901 /* 16-lsb timestamp from POR (100-msec resolution) */
8902 uint16_t timestamp_hi;
8904 * Each flag provided in this field indicates a specific VF
8905 * configuration change. At least one of these flags shall be set to 1
8906 * when an asynchronous event completion of this type is provided
8909 uint32_t event_data1;
8911 * If this bit is set to 1, then the value of MTU
8912 * was changed on this VF.
8913 * If set to 0, then this bit should be ignored.
8915 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
8918 * If this bit is set to 1, then the value of MRU
8919 * was changed on this VF.
8920 * If set to 0, then this bit should be ignored.
8922 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
8925 * If this bit is set to 1, then the value of default MAC
8926 * address was changed on this VF.
8927 * If set to 0, then this bit should be ignored.
8929 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
8932 * If this bit is set to 1, then the value of default VLAN
8933 * was changed on this VF.
8934 * If set to 0, then this bit should be ignored.
8936 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
8939 * If this bit is set to 1, then the value of trusted VF enable
8940 * was changed on this VF.
8941 * If set to 0, then this bit should be ignored.
8943 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
8947 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
8948 struct hwrm_async_event_cmpl_llfc_pfc_change {
8951 * This field indicates the exact type of the completion.
8952 * By convention, the LSB identifies the length of the
8953 * record in 16B units. Even values indicate 16B
8954 * records. Odd values indicate 32B
8957 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
8959 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
8960 /* HWRM Asynchronous Event Information */
8961 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8963 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
8964 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8965 /* unused1 is 10 b */
8966 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
8968 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
8969 /* Identifiers of events. */
8971 /* LLFC/PFC Configuration Change */
8972 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
8974 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
8975 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
8976 /* Event specific data */
8977 uint32_t event_data2;
8980 * This value is written by the NIC such that it will be different
8981 * for each pass through the completion queue. The even passes
8982 * will write 1. The odd passes will write 0.
8984 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
8986 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
8988 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
8989 /* 8-lsb timestamp from POR (100-msec resolution) */
8990 uint8_t timestamp_lo;
8991 /* 16-lsb timestamp from POR (100-msec resolution) */
8992 uint16_t timestamp_hi;
8993 /* Event specific data */
8994 uint32_t event_data1;
8995 /* Indicates llfc pfc status change */
8996 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
8998 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
9001 * If this field set to 1, then it indicates that llfc is
9004 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
9007 * If this field is set to 2, then it indicates that pfc
9010 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
9012 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
9013 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
9014 /* Indicates the physical port this llfc pfc change occur */
9015 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
9017 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
9020 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9022 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9026 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
9027 struct hwrm_async_event_cmpl_default_vnic_change {
9030 * This field indicates the exact type of the completion.
9031 * By convention, the LSB identifies the length of the
9032 * record in 16B units. Even values indicate 16B
9033 * records. Odd values indicate 32B
9036 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
9038 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
9040 /* HWRM Asynchronous Event Information */
9041 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9043 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
9044 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
9045 /* unused1 is 10 b */
9046 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
9048 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
9050 /* Identifiers of events. */
9052 /* Notification of a default vnic allocation or free */
9053 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
9055 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
9056 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
9057 /* Event specific data */
9058 uint32_t event_data2;
9061 * This value is written by the NIC such that it will be different
9062 * for each pass through the completion queue. The even passes
9063 * will write 1. The odd passes will write 0.
9065 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
9068 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
9070 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
9071 /* 8-lsb timestamp from POR (100-msec resolution) */
9072 uint8_t timestamp_lo;
9073 /* 16-lsb timestamp from POR (100-msec resolution) */
9074 uint16_t timestamp_hi;
9075 /* Event specific data */
9076 uint32_t event_data1;
9077 /* Indicates default vnic configuration change */
9078 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
9080 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
9083 * If this field is set to 1, then it indicates that
9084 * a default VNIC has been allocate.
9086 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
9089 * If this field is set to 2, then it indicates that
9090 * a default VNIC has been freed.
9092 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
9094 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
9095 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
9096 /* Indicates the physical function this event occurred on. */
9097 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
9099 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
9101 /* Indicates the virtual function this event occurred on */
9102 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
9104 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
9108 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
9109 struct hwrm_async_event_cmpl_hw_flow_aged {
9112 * This field indicates the exact type of the completion.
9113 * By convention, the LSB identifies the length of the
9114 * record in 16B units. Even values indicate 16B
9115 * records. Odd values indicate 32B
9118 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
9120 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
9121 /* HWRM Asynchronous Event Information */
9122 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
9124 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
9125 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
9126 /* Identifiers of events. */
9128 /* Notification of a hw flow aged */
9129 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
9131 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
9132 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
9133 /* Event specific data */
9134 uint32_t event_data2;
9137 * This value is written by the NIC such that it will be different
9138 * for each pass through the completion queue. The even passes
9139 * will write 1. The odd passes will write 0.
9141 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
9143 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
9144 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
9145 /* 8-lsb timestamp from POR (100-msec resolution) */
9146 uint8_t timestamp_lo;
9147 /* 16-lsb timestamp from POR (100-msec resolution) */
9148 uint16_t timestamp_hi;
9149 /* Event specific data */
9150 uint32_t event_data1;
9151 /* Indicates flow ID this event occurred on. */
9152 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
9153 UINT32_C(0x7fffffff)
9154 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
9156 /* Indicates flow direction this event occurred on. */
9157 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
9158 UINT32_C(0x80000000)
9160 * If this bit set to 0, then it indicates that the aged
9161 * event was rx flow.
9163 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
9164 (UINT32_C(0x0) << 31)
9166 * If this bit is set to 1, then it indicates that the aged
9167 * event was tx flow.
9169 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
9170 (UINT32_C(0x1) << 31)
9171 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
9172 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
9175 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
9176 struct hwrm_async_event_cmpl_eem_cache_flush_req {
9179 * This field indicates the exact type of the completion.
9180 * By convention, the LSB identifies the length of the
9181 * record in 16B units. Even values indicate 16B
9182 * records. Odd values indicate 32B
9185 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
9187 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
9189 /* HWRM Asynchronous Event Information */
9190 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
9192 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
9193 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
9194 /* Identifiers of events. */
9196 /* Notification of a eem_cache_flush request */
9197 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
9199 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
9200 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
9201 /* Event specific data */
9202 uint32_t event_data2;
9205 * This value is written by the NIC such that it will be different
9206 * for each pass through the completion queue. The even passes
9207 * will write 1. The odd passes will write 0.
9209 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
9212 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
9214 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
9215 /* 8-lsb timestamp from POR (100-msec resolution) */
9216 uint8_t timestamp_lo;
9217 /* 16-lsb timestamp from POR (100-msec resolution) */
9218 uint16_t timestamp_hi;
9219 /* Event specific data */
9220 uint32_t event_data1;
9223 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
9224 struct hwrm_async_event_cmpl_eem_cache_flush_done {
9227 * This field indicates the exact type of the completion.
9228 * By convention, the LSB identifies the length of the
9229 * record in 16B units. Even values indicate 16B
9230 * records. Odd values indicate 32B
9233 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
9235 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
9237 /* HWRM Asynchronous Event Information */
9238 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
9240 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
9241 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
9242 /* Identifiers of events. */
9245 * Notification of a host eem_cache_flush has completed. This event
9246 * is generated by the host driver.
9248 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9250 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
9251 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
9252 /* Event specific data */
9253 uint32_t event_data2;
9256 * This value is written by the NIC such that it will be different
9257 * for each pass through the completion queue. The even passes
9258 * will write 1. The odd passes will write 0.
9260 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
9263 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
9265 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
9266 /* 8-lsb timestamp from POR (100-msec resolution) */
9267 uint8_t timestamp_lo;
9268 /* 16-lsb timestamp from POR (100-msec resolution) */
9269 uint16_t timestamp_hi;
9270 /* Event specific data */
9271 uint32_t event_data1;
9272 /* Indicates function ID that this event occurred on. */
9273 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
9275 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
9279 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
9280 struct hwrm_async_event_cmpl_tcp_flag_action_change {
9283 * This field indicates the exact type of the completion.
9284 * By convention, the LSB identifies the length of the
9285 * record in 16B units. Even values indicate 16B
9286 * records. Odd values indicate 32B
9289 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
9291 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
9293 /* HWRM Asynchronous Event Information */
9294 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9296 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
9297 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
9298 /* Identifiers of events. */
9300 /* Notification of tcp flag action change */
9301 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9303 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
9304 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
9305 /* Event specific data */
9306 uint32_t event_data2;
9309 * This value is written by the NIC such that it will be different
9310 * for each pass through the completion queue. The even passes
9311 * will write 1. The odd passes will write 0.
9313 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
9316 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
9318 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
9319 /* 8-lsb timestamp from POR (100-msec resolution) */
9320 uint8_t timestamp_lo;
9321 /* 16-lsb timestamp from POR (100-msec resolution) */
9322 uint16_t timestamp_hi;
9323 /* Event specific data */
9324 uint32_t event_data1;
9327 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
9328 struct hwrm_async_event_cmpl_eem_flow_active {
9331 * This field indicates the exact type of the completion.
9332 * By convention, the LSB identifies the length of the
9333 * record in 16B units. Even values indicate 16B
9334 * records. Odd values indicate 32B
9337 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
9339 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
9340 /* HWRM Asynchronous Event Information */
9341 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
9343 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
9344 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
9345 /* Identifiers of events. */
9347 /* Notification of an active eem flow */
9348 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
9350 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
9351 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
9352 /* Event specific data */
9353 uint32_t event_data2;
9354 /* Indicates the 2nd global id this event occurred on. */
9355 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
9356 UINT32_C(0x3fffffff)
9357 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
9360 * Indicates flow direction of the flow identified by
9363 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
9364 UINT32_C(0x40000000)
9365 /* If this bit is set to 0, then it indicates that this rx flow. */
9366 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
9367 (UINT32_C(0x0) << 30)
9368 /* If this bit is set to 1, then it indicates that this tx flow. */
9369 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
9370 (UINT32_C(0x1) << 30)
9371 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
9372 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
9375 * This value is written by the NIC such that it will be different
9376 * for each pass through the completion queue. The even passes
9377 * will write 1. The odd passes will write 0.
9379 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
9381 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
9383 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
9384 /* 8-lsb timestamp from POR (100-msec resolution) */
9385 uint8_t timestamp_lo;
9386 /* 16-lsb timestamp from POR (100-msec resolution) */
9387 uint16_t timestamp_hi;
9388 /* Event specific data */
9389 uint32_t event_data1;
9390 /* Indicates the 1st global id this event occurred on. */
9391 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
9392 UINT32_C(0x3fffffff)
9393 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
9396 * Indicates flow direction of the flow identified by the
9399 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
9400 UINT32_C(0x40000000)
9401 /* If this bit is set to 0, then it indicates that this is rx flow. */
9402 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
9403 (UINT32_C(0x0) << 30)
9404 /* If this bit is set to 1, then it indicates that this is tx flow. */
9405 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
9406 (UINT32_C(0x1) << 30)
9407 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
9408 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
9410 * Indicates EEM flow aging mode this event occurred on. If
9411 * this bit is set to 0, the event_data1 is the EEM global
9412 * ID. If this bit is set to 1, the event_data1 is the number
9413 * of global ID in the context memory.
9415 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
9416 UINT32_C(0x80000000)
9417 /* EEM flow aging mode 0. */
9418 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
9419 (UINT32_C(0x0) << 31)
9420 /* EEM flow aging mode 1. */
9421 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
9422 (UINT32_C(0x1) << 31)
9423 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
9424 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
9427 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
9428 struct hwrm_async_event_cmpl_eem_cfg_change {
9431 * This field indicates the exact type of the completion.
9432 * By convention, the LSB identifies the length of the
9433 * record in 16B units. Even values indicate 16B
9434 * records. Odd values indicate 32B
9437 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
9439 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
9440 /* HWRM Asynchronous Event Information */
9441 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9443 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
9444 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9445 /* Identifiers of events. */
9447 /* Notification of EEM configuration change */
9448 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
9450 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
9451 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
9452 /* Event specific data */
9453 uint32_t event_data2;
9456 * This value is written by the NIC such that it will be different
9457 * for each pass through the completion queue. The even passes
9458 * will write 1. The odd passes will write 0.
9460 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
9462 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9463 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
9464 /* 8-lsb timestamp from POR (100-msec resolution) */
9465 uint8_t timestamp_lo;
9466 /* 16-lsb timestamp from POR (100-msec resolution) */
9467 uint16_t timestamp_hi;
9468 /* Event specific data */
9469 uint32_t event_data1;
9471 * Value of 1 to indicate EEM TX configuration is enabled. Value of
9472 * 0 to indicate the EEM TX configuration is disabled.
9474 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
9477 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
9478 * to indicate the EEM RX configuration is disabled.
9480 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
9484 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
9485 struct hwrm_async_event_cmpl_quiesce_done {
9488 * This field indicates the exact type of the completion.
9489 * By convention, the LSB identifies the length of the
9490 * record in 16B units. Even values indicate 16B
9491 * records. Odd values indicate 32B
9494 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
9496 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
9497 /* HWRM Asynchronous Event Information */
9498 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
9500 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
9501 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
9502 /* Identifiers of events. */
9504 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
9505 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
9507 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
9508 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
9509 /* Event specific data */
9510 uint32_t event_data2;
9511 /* Status of HWRM_FW_STATE_QUIESCE completion */
9512 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
9514 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
9517 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9518 * completed successfully.
9520 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
9523 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
9526 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
9529 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9530 * encountered an error.
9532 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
9534 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
9535 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
9537 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
9539 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
9542 * Additional information about internal hardware state related to
9543 * idle/quiesce state. QUIESCE may succeed per quiesce_status
9544 * regardless of idle_state_flags. If QUIESCE fails, the host may
9545 * inspect idle_state_flags to determine whether a retry is warranted.
9547 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
9549 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
9552 * Failure to quiesce is caused by host not updating the NQ consumer
9555 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
9557 /* Flag 1 indicating partial non-idle state. */
9558 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
9560 /* Flag 2 indicating partial non-idle state. */
9561 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
9563 /* Flag 3 indicating partial non-idle state. */
9564 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
9568 * This value is written by the NIC such that it will be different
9569 * for each pass through the completion queue. The even passes
9570 * will write 1. The odd passes will write 0.
9572 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
9574 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
9575 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
9576 /* 8-lsb timestamp from POR (100-msec resolution) */
9577 uint8_t timestamp_lo;
9578 /* 16-lsb timestamp from POR (100-msec resolution) */
9579 uint16_t timestamp_hi;
9580 /* Event specific data */
9581 uint32_t event_data1;
9582 /* Time stamp for error event */
9583 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
9587 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
9588 struct hwrm_async_event_cmpl_deferred_response {
9591 * This field indicates the exact type of the completion.
9592 * By convention, the LSB identifies the length of the
9593 * record in 16B units. Even values indicate 16B
9594 * records. Odd values indicate 32B
9597 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
9599 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
9600 /* HWRM Asynchronous Event Information */
9601 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
9603 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
9604 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
9605 /* Identifiers of events. */
9608 * An event signifying a HWRM command is in progress and its
9609 * response will be deferred
9611 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
9613 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
9614 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
9615 /* Event specific data */
9616 uint32_t event_data2;
9618 * The PF's mailbox is clear to issue another command.
9619 * A command with this seq_id is still in progress
9620 * and will return a regular HWRM completion when done.
9621 * 'event_data1' field, if non-zero, contains the estimated
9622 * execution time for the command.
9624 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
9626 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
9630 * This value is written by the NIC such that it will be different
9631 * for each pass through the completion queue. The even passes
9632 * will write 1. The odd passes will write 0.
9634 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
9637 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
9639 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
9640 /* 8-lsb timestamp from POR (100-msec resolution) */
9641 uint8_t timestamp_lo;
9642 /* 16-lsb timestamp from POR (100-msec resolution) */
9643 uint16_t timestamp_hi;
9644 /* Estimated remaining time of command execution in ms (if not zero) */
9645 uint32_t event_data1;
9648 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
9649 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
9652 * This field indicates the exact type of the completion.
9653 * By convention, the LSB identifies the length of the
9654 * record in 16B units. Even values indicate 16B
9655 * records. Odd values indicate 32B
9658 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
9660 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
9662 /* HWRM Asynchronous Event Information */
9663 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9665 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
9666 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9667 /* Identifiers of events. */
9669 /* PFC watchdog configuration change for given port/cos */
9670 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9672 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
9673 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
9674 /* Event specific data */
9675 uint32_t event_data2;
9678 * This value is written by the NIC such that it will be different
9679 * for each pass through the completion queue. The even passes
9680 * will write 1. The odd passes will write 0.
9682 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
9685 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
9687 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
9688 /* 8-lsb timestamp from POR (100-msec resolution) */
9689 uint8_t timestamp_lo;
9690 /* 16-lsb timestamp from POR (100-msec resolution) */
9691 uint16_t timestamp_hi;
9692 /* Event specific data */
9693 uint32_t event_data1;
9695 * 1 in bit position X indicates PFC watchdog should
9698 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
9700 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
9702 /* 1 means PFC WD for COS0 is on, 0 - off. */
9703 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
9705 /* 1 means PFC WD for COS1 is on, 0 - off. */
9706 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
9708 /* 1 means PFC WD for COS2 is on, 0 - off. */
9709 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
9711 /* 1 means PFC WD for COS3 is on, 0 - off. */
9712 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
9714 /* 1 means PFC WD for COS4 is on, 0 - off. */
9715 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
9717 /* 1 means PFC WD for COS5 is on, 0 - off. */
9718 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
9720 /* 1 means PFC WD for COS6 is on, 0 - off. */
9721 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
9723 /* 1 means PFC WD for COS7 is on, 0 - off. */
9724 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
9727 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9729 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9733 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
9734 struct hwrm_async_event_cmpl_echo_request {
9737 * This field indicates the exact type of the completion.
9738 * By convention, the LSB identifies the length of the
9739 * record in 16B units. Even values indicate 16B
9740 * records. Odd values indicate 32B
9743 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
9745 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
9746 /* HWRM Asynchronous Event Information */
9747 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
9749 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
9750 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
9751 /* Identifiers of events. */
9754 * An echo request from the firmware. An echo response is expected by
9757 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
9759 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
9760 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
9761 /* Event specific data that should be provided in the echo response */
9762 uint32_t event_data2;
9765 * This value is written by the NIC such that it will be different
9766 * for each pass through the completion queue. The even passes
9767 * will write 1. The odd passes will write 0.
9769 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
9771 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
9772 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
9773 /* 8-lsb timestamp from POR (100-msec resolution) */
9774 uint8_t timestamp_lo;
9775 /* 16-lsb timestamp from POR (100-msec resolution) */
9776 uint16_t timestamp_hi;
9777 /* Event specific data that should be provided in the echo response */
9778 uint32_t event_data1;
9781 /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
9782 struct hwrm_async_event_cmpl_phc_master {
9785 * This field indicates the exact type of the completion.
9786 * By convention, the LSB identifies the length of the
9787 * record in 16B units. Even values indicate 16B
9788 * records. Odd values indicate 32B
9791 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK \
9793 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0
9794 /* HWRM Asynchronous Event Information */
9795 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT \
9797 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST \
9798 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
9799 /* Identifiers of events. */
9802 * This async event is used to notify driver of changes
9803 * in PHC master. Only one master function can configure
9806 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER \
9808 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST \
9809 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
9810 /* Event specific data */
9811 uint32_t event_data2;
9812 /* This field provides the current master function. */
9813 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK \
9815 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT \
9817 /* This field provides the current secondary function. */
9818 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK \
9819 UINT32_C(0xffff0000)
9820 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT \
9824 * This value is written by the NIC such that it will be different
9825 * for each pass through the completion queue. The even passes
9826 * will write 1. The odd passes will write 0.
9828 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_V UINT32_C(0x1)
9830 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK UINT32_C(0xfe)
9831 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
9832 /* 8-lsb timestamp (100-msec resolution) */
9833 uint8_t timestamp_lo;
9834 /* 16-lsb timestamp (100-msec resolution) */
9835 uint16_t timestamp_hi;
9836 /* Event specific data */
9837 uint32_t event_data1;
9838 /* Indicates to the driver the type of PHC event. */
9839 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK \
9841 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT \
9844 * Indicates PHC Master selection event. The master fid is
9845 * specified in event_data2.phc_master_fid.
9847 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER \
9850 * Indicates PHC Secondary selection event. The secondary fid is
9851 * specified in event_data2.phc_sec_fid.
9853 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY \
9856 * Indicates PHC failover event. Failover happens from
9857 * event_data2.phc_master_fid to event_data2.phc_sec_fid.
9859 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER \
9861 #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST \
9862 HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
9865 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
9866 struct hwrm_async_event_cmpl_pps_timestamp {
9869 * This field indicates the exact type of the completion.
9870 * By convention, the LSB identifies the length of the
9871 * record in 16B units. Even values indicate 16B
9872 * records. Odd values indicate 32B
9875 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \
9877 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
9878 /* HWRM Asynchronous Event Information */
9879 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \
9881 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \
9882 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
9883 /* Identifiers of events. */
9886 * This async notification message can be used to inform
9887 * driver of the latest PPS timestamp that has been latched.
9888 * When driver enables PPS event, Firmware will generate
9889 * PPS timestamps every second, Firmware informs driver
9890 * of this timestamp through the async event.
9892 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \
9894 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \
9895 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
9896 /* Event specific data */
9897 uint32_t event_data2;
9898 /* Indicates the PPS event type */
9899 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \
9901 /* This is an internal event. */
9902 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \
9904 /* This is an external event. */
9905 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \
9907 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \
9908 HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
9910 * Indicates the pin number on which the event is
9913 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \
9915 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \
9918 * Contains bits[47:32] of the upper PPS timestamp.
9919 * Lower 32 bits are in event_data1. Together they
9920 * provide the 48 bit PPS timestamp.
9922 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \
9924 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \
9928 * This value is written by the NIC such that it will be different
9929 * for each pass through the completion queue. The even passes
9930 * will write 1. The odd passes will write 0.
9932 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
9934 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
9935 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
9936 /* 8-lsb timestamp (100-msec resolution) */
9937 uint8_t timestamp_lo;
9938 /* 16-lsb timestamp (100-msec resolution) */
9939 uint16_t timestamp_hi;
9940 /* Contains the lower 32 bits of the PPS timestamp. */
9941 uint32_t event_data1;
9942 /* Contains the lower 32 bit PPS timestamp */
9943 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \
9944 UINT32_C(0xffffffff)
9945 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \
9949 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */
9950 struct hwrm_async_event_cmpl_error_report {
9953 * This field indicates the exact type of the completion.
9954 * By convention, the LSB identifies the length of the
9955 * record in 16B units. Even values indicate 16B
9956 * records. Odd values indicate 32B
9959 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \
9961 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
9962 /* HWRM Asynchronous Event Information */
9963 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \
9965 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \
9966 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
9967 /* Identifiers of events. */
9970 * This async notification message is used to inform
9971 * the driver that an error has occurred which may need
9972 * the attention of the administrator.
9974 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \
9976 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \
9977 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
9978 /* Event specific data. */
9979 uint32_t event_data2;
9982 * This value is written by the NIC such that it will be different
9983 * for each pass through the completion queue. The even passes
9984 * will write 1. The odd passes will write 0.
9986 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
9988 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
9989 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
9990 /* 8-lsb timestamp (100-msec resolution) */
9991 uint8_t timestamp_lo;
9992 /* 16-lsb timestamp (100-msec resolution) */
9993 uint16_t timestamp_hi;
9994 /* Event specific data */
9995 uint32_t event_data1;
9997 * Indicates the type of error being reported. See section on Error
9998 * Report event error_types for details on each error.
10000 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \
10002 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
10005 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
10006 struct hwrm_async_event_cmpl_fw_trace_msg {
10009 * This field indicates the exact type of the completion.
10010 * By convention, the LSB identifies the length of the
10011 * record in 16B units. Even values indicate 16B
10012 * records. Odd values indicate 32B
10015 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
10017 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
10018 /* HWRM Asynchronous Event Information */
10019 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
10021 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
10022 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
10023 /* Identifiers of events. */
10025 /* Firmware trace log message */
10026 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
10028 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
10029 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
10030 /* Trace byte 0 to 3 */
10031 uint32_t event_data2;
10033 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
10035 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
10037 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
10039 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
10041 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
10043 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
10045 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
10046 UINT32_C(0xff000000)
10047 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
10050 * This value is written by the NIC such that it will be different
10051 * for each pass through the completion queue. The even passes
10052 * will write 1. The odd passes will write 0.
10054 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
10055 /* opaque is 7 b */
10056 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
10057 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
10059 uint8_t timestamp_lo;
10060 /* Indicates if the string is partial or complete. */
10061 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
10063 /* Complete string */
10064 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
10066 /* Partial string */
10067 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
10069 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
10070 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
10071 /* Indicates the firmware that sent the trace message. */
10072 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
10074 /* Primary firmware */
10075 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
10076 (UINT32_C(0x0) << 1)
10077 /* Secondary firmware */
10078 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
10079 (UINT32_C(0x1) << 1)
10080 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
10081 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
10082 /* Trace byte 4 to 5 */
10083 uint16_t timestamp_hi;
10085 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
10087 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
10089 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
10091 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
10092 /* Trace byte 6 to 9 */
10093 uint32_t event_data1;
10095 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
10097 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
10099 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
10101 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
10103 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
10105 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
10107 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
10108 UINT32_C(0xff000000)
10109 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
10112 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
10113 struct hwrm_async_event_cmpl_hwrm_error {
10116 * This field indicates the exact type of the completion.
10117 * By convention, the LSB identifies the length of the
10118 * record in 16B units. Even values indicate 16B
10119 * records. Odd values indicate 32B
10122 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
10124 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
10125 /* HWRM Asynchronous Event Information */
10126 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
10128 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
10129 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
10130 /* Identifiers of events. */
10133 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
10135 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
10136 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
10137 /* Event specific data */
10138 uint32_t event_data2;
10139 /* Severity of HWRM Error */
10140 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
10142 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
10144 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
10146 /* Non-fatal Error */
10147 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
10150 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
10152 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
10153 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
10156 * This value is written by the NIC such that it will be different
10157 * for each pass through the completion queue. The even passes
10158 * will write 1. The odd passes will write 0.
10160 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
10161 /* opaque is 7 b */
10162 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
10163 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
10164 /* 8-lsb timestamp from POR (100-msec resolution) */
10165 uint8_t timestamp_lo;
10166 /* 16-lsb timestamp from POR (100-msec resolution) */
10167 uint16_t timestamp_hi;
10168 /* Event specific data */
10169 uint32_t event_data1;
10170 /* Time stamp for error event */
10171 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
10175 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
10176 struct hwrm_async_event_cmpl_error_report_base {
10179 * This field indicates the exact type of the completion.
10180 * By convention, the LSB identifies the length of the
10181 * record in 16B units. Even values indicate 16B
10182 * records. Odd values indicate 32B
10185 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \
10187 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
10188 /* HWRM Asynchronous Event Information */
10189 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \
10191 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \
10192 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
10193 /* Identifiers of events. */
10196 * This async notification message is used to inform
10197 * the driver that an error has occurred which may need
10198 * the attention of the administrator.
10200 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \
10202 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \
10203 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
10204 /* Event specific data. */
10205 uint32_t event_data2;
10208 * This value is written by the NIC such that it will be different
10209 * for each pass through the completion queue. The even passes
10210 * will write 1. The odd passes will write 0.
10212 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \
10214 /* opaque is 7 b */
10215 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \
10217 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
10218 /* 8-lsb timestamp (100-msec resolution) */
10219 uint8_t timestamp_lo;
10220 /* 16-lsb timestamp (100-msec resolution) */
10221 uint16_t timestamp_hi;
10222 /* Event specific data */
10223 uint32_t event_data1;
10224 /* Indicates the type of error being reported. */
10225 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \
10227 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \
10230 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \
10233 * The NIC was subjected to an extended pause storm which caused it
10234 * to disable flow control in order to avoid stalling the Tx path.
10236 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
10239 * The NIC received an interrupt storm on a TSIO pin being used as
10240 * PPS_IN which caused it to disable the interrupt. The signal
10241 * should be fixed to be a proper 1 PPS signal before re-enabling
10242 * it. The pin number on which this signal was received is stored
10243 * in event_data2 as pin_id.
10245 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
10247 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \
10248 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
10251 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
10252 struct hwrm_async_event_cmpl_error_report_pause_storm {
10255 * This field indicates the exact type of the completion.
10256 * By convention, the LSB identifies the length of the
10257 * record in 16B units. Even values indicate 16B
10258 * records. Odd values indicate 32B
10261 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \
10263 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \
10265 /* HWRM Asynchronous Event Information */
10266 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \
10268 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \
10269 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
10270 /* Identifiers of events. */
10273 * This async notification message is used to inform
10274 * the driver that an error has occurred which may need
10275 * the attention of the administrator.
10277 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \
10279 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \
10280 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
10281 /* Event specific data. */
10282 uint32_t event_data2;
10285 * This value is written by the NIC such that it will be different
10286 * for each pass through the completion queue. The even passes
10287 * will write 1. The odd passes will write 0.
10289 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \
10291 /* opaque is 7 b */
10292 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \
10294 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
10295 /* 8-lsb timestamp (100-msec resolution) */
10296 uint8_t timestamp_lo;
10297 /* 16-lsb timestamp (100-msec resolution) */
10298 uint16_t timestamp_hi;
10299 /* Event specific data */
10300 uint32_t event_data1;
10301 /* Indicates the type of error being reported. */
10302 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \
10304 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \
10307 * The NIC was subjected to an extended pause storm which caused it
10308 * to disable flow control in order to avoid stalling the Tx path.
10310 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
10312 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \
10313 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
10316 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
10317 struct hwrm_async_event_cmpl_error_report_invalid_signal {
10320 * This field indicates the exact type of the completion.
10321 * By convention, the LSB identifies the length of the
10322 * record in 16B units. Even values indicate 16B
10323 * records. Odd values indicate 32B
10326 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \
10328 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \
10330 /* HWRM Asynchronous Event Information */
10331 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \
10333 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \
10334 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
10335 /* Identifiers of events. */
10338 * This async notification message is used to inform
10339 * the driver that an error has occurred which may need
10340 * the attention of the administrator.
10342 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \
10344 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \
10345 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
10346 /* Event specific data. */
10347 uint32_t event_data2;
10348 /* Indicates the TSIO pin on which invalid signal is detected. */
10349 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \
10351 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \
10355 * This value is written by the NIC such that it will be different
10356 * for each pass through the completion queue. The even passes
10357 * will write 1. The odd passes will write 0.
10359 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \
10361 /* opaque is 7 b */
10362 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \
10364 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
10365 /* 8-lsb timestamp (100-msec resolution) */
10366 uint8_t timestamp_lo;
10367 /* 16-lsb timestamp (100-msec resolution) */
10368 uint16_t timestamp_hi;
10369 /* Event specific data */
10370 uint32_t event_data1;
10371 /* Indicates the type of error being reported. */
10372 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \
10374 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \
10377 * The NIC received an interrupt storm on a TSIO pin being used as
10378 * PPS_IN which caused it to disable the interrupt. The signal
10379 * should be fixed to be a proper 1 PPS signal before re-enabling
10380 * it. The pin number on which this signal was received is stored
10381 * in event_data2 as pin_id.
10383 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
10385 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \
10386 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
10389 /* metadata_base_msg (size:64b/8B) */
10390 struct metadata_base_msg {
10391 uint16_t md_type_link;
10392 /* This field classifies the data present in the meta-data. */
10393 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
10394 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
10395 /* Meta data fields are not valid */
10396 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
10398 * This setting is used when packets are coming in-order. Depending on
10399 * the state of the receive context, the meta-data will carry different
10402 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
10404 * With this setting HW passes the TCP sequence number of the TLS
10405 * record that it is requesting a resync on in the meta data.
10407 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
10408 #define METADATA_BASE_MSG_MD_TYPE_LAST \
10409 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
10411 * This field indicates where the next metadata block starts. It is
10412 * counted in 16B units. A value of zero indicates that there is no
10415 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
10416 #define METADATA_BASE_MSG_LINK_SFT 5
10421 /* tls_metadata_base_msg (size:64b/8B) */
10422 struct tls_metadata_base_msg {
10423 uint32_t md_type_link_flags_kid_lo;
10424 /* This field classifies the data present in the meta-data. */
10425 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
10427 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
10429 * This setting is used when packets are coming in-order. Depending on
10430 * the state of the receive context, the meta-data will carry different
10433 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
10436 * With this setting HW passes the TCP sequence number of the TLS
10437 * record that it is requesting a resync on in the meta data.
10439 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
10441 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
10442 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
10444 * This field indicates where the next metadata block starts. It is
10445 * counted in 16B units. A value of zero indicates that there is no
10448 #define TLS_METADATA_BASE_MSG_LINK_MASK \
10450 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
10451 /* These are flags present in the metadata. */
10452 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
10453 UINT32_C(0x1fffe00)
10454 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
10456 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10457 * the packet is passed on as it came in on the wire.
10459 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
10462 * This field indicates the state of the ghash field passed in the
10465 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
10467 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
10469 * This enumeration states that the ghash is not valid in the
10472 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
10473 (UINT32_C(0x0) << 10)
10475 * This enumeration indicates that this pkt contains the record's
10476 * tag and this pkt was received ooo, the partial_ghash field
10477 * contains the ghash.
10479 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
10480 (UINT32_C(0x1) << 10)
10482 * This enumeration indicates that the current record's tag wasn't
10483 * seen and the chip is moving on to the next record, the
10484 * partial_ghash field contains the ghash.
10486 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
10487 (UINT32_C(0x2) << 10)
10488 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
10489 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
10490 /* This field indicates the status of tag authentication. */
10491 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10493 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10495 * This enumeration is set when there is no tags present in the
10498 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10499 (UINT32_C(0x0) << 12)
10501 * This enumeration states that there is at least one tag in the
10502 * packet and every tag is valid.
10504 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10505 (UINT32_C(0x1) << 12)
10507 * This enumeration states that there is at least one tag in the
10508 * packet and at least one of the tag is invalid. The entire packet
10509 * is sent decrypted to the host.
10511 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10512 (UINT32_C(0x2) << 12)
10513 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10514 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10516 * A value of 1 indicates that this packet contains a record that
10517 * starts in the packet and extends beyond the packet.
10519 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
10522 * This value indicates the lower 7-bit of the Crypto Key ID
10523 * associated with this operation.
10525 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
10526 UINT32_C(0xfe000000)
10527 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
10530 * This value indicates the upper 13-bit of the Crypto Key ID
10531 * associated with this operation.
10533 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
10534 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
10538 /* tls_metadata_insync_msg (size:192b/24B) */
10539 struct tls_metadata_insync_msg {
10540 uint32_t md_type_link_flags_kid_lo;
10541 /* This field classifies the data present in the meta-data. */
10542 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
10544 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
10546 * This setting is used when packets are coming in-order. Depending on
10547 * the state of the receive context, the meta-data will carry different
10550 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
10552 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
10553 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
10555 * This field indicates where the next metadata block starts. It is
10556 * counted in 16B units. A value of zero indicates that there is no
10559 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
10561 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
10562 /* These are flags present in the metadata. */
10563 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
10564 UINT32_C(0x1fffe00)
10565 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
10567 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10568 * the packet is passed on as it came in on the wire.
10570 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
10573 * This field indicates the state of the ghash field passed in the
10576 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
10578 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
10580 * This enumeration states that the ghash is not valid in the
10583 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
10584 (UINT32_C(0x0) << 10)
10586 * This enumeration indicates that this pkt contains the record's
10587 * tag and this pkt was received ooo, the partial_ghash field
10588 * contains the ghash.
10590 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
10591 (UINT32_C(0x1) << 10)
10593 * This enumeration indicates that the current record's tag wasn't
10594 * seen and the chip is moving on to the next record, the
10595 * partial_ghash field contains the ghash.
10597 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
10598 (UINT32_C(0x2) << 10)
10599 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
10600 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
10601 /* This field indicates the status of tag authentication. */
10602 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10604 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10606 * This enumeration is set when there is no tags present in the
10609 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10610 (UINT32_C(0x0) << 12)
10612 * This enumeration states that there is at least one tag in the
10613 * packet and every tag is valid.
10615 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10616 (UINT32_C(0x1) << 12)
10618 * This enumeration states that there is at least one tag in the
10619 * packet and at least one of the tag is invalid. The entire packet
10620 * is sent decrypted to the host.
10622 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10623 (UINT32_C(0x2) << 12)
10624 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10625 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10627 * A value of 1 indicates that this packet contains a record that
10628 * starts in the packet and extends beyond the packet.
10630 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10633 * This value indicates the lower 7-bit of the Crypto Key ID
10634 * associated with this operation.
10636 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
10637 UINT32_C(0xfe000000)
10638 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
10641 * This value indicates the upper 13-bit of the Crypto Key ID
10642 * associated with this operation.
10644 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10645 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
10647 * This field is only valid when md_type is set to tls_insync. This field
10648 * indicates the offset within the current TCP packet where the TLS header
10649 * starts. If there are multiple TLS headers in the packet, this provides
10650 * the offset of the last TLS header.
10652 * The field is calculated by subtracting TCP sequence number of the first
10653 * byte of the TCP payload of the packet from the TCP sequence number of
10654 * the last TLS header in the packet.
10656 uint16_t tls_header_offset;
10658 * This is the sequence Number of the record that was processed by the HW.
10659 * If there are multiple records in a packet, this would be the sequence
10660 * number of the last record.
10662 uint64_t record_seq_num;
10664 * This field contains cumulative partial GHASH value of all the packets
10665 * decrypted by the HW associated with a TLS record. This field is valid
10666 * on when packets belonging to have arrived out-of-order and HW could
10667 * not decrypt every packet and authenticate the record. Partial GHASH is
10668 * only sent out with packet having the TAG field.
10670 uint64_t partial_ghash;
10673 /* tls_metadata_resync_msg (size:256b/32B) */
10674 struct tls_metadata_resync_msg {
10675 uint32_t md_type_link_flags_kid_lo;
10676 /* This field classifies the data present in the meta-data. */
10677 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
10679 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
10681 * With this setting HW passes the TCP sequence number of the TLS
10682 * record that it is requesting a resync on in the meta data.
10684 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
10686 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
10687 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
10689 * This field indicates where the next metadata block starts. It is
10690 * counted in 16B units. A value of zero indicates that there is no
10693 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
10695 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
10696 /* These are flags present in the metadata. */
10697 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
10698 UINT32_C(0x1fffe00)
10699 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
10701 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10702 * the packet is passed on as it came in on the wire.
10704 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
10707 * This field indicates the state of the ghash field passed in the
10710 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
10712 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
10714 * This enumeration states that the ghash is not valid in the
10717 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
10718 (UINT32_C(0x0) << 10)
10719 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
10720 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
10721 /* This field indicates the status of tag authentication. */
10722 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10724 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10726 * This enumeration is set when there is no tags present in the
10729 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10730 (UINT32_C(0x0) << 12)
10731 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10732 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
10734 * A value of 1 indicates that this packet contains a record that
10735 * starts in the packet and extends beyond the packet.
10737 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10740 * This value indicates the lower 7-bit of the Crypto Key ID
10741 * associated with this operation.
10743 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
10744 UINT32_C(0xfe000000)
10745 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
10748 * This value indicates the upper 13-bit of the Crypto Key ID
10749 * associated with this operation.
10751 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10752 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
10753 /* This field is unused in this context. */
10754 uint16_t metadata_0;
10756 * This field indicates the TCP sequence number of the TLS record that HW
10757 * is requesting a resync on from the Driver. HW will keep a count of the
10758 * TLS records it found after this record (delta_records). Driver will
10759 * provide the TLS Record Sequence Number associated with the record. HW
10760 * will add the delta_records to the Record Sequence Number provided by
10761 * the driver and get back on sync.
10763 uint32_t resync_record_tcp_seq_num;
10765 /* This field is unused in this context. */
10766 uint64_t metadata_2;
10767 /* This field is unused in this context. */
10768 uint64_t metadata_3;
10771 /*******************
10772 * hwrm_func_reset *
10773 *******************/
10776 /* hwrm_func_reset_input (size:192b/24B) */
10777 struct hwrm_func_reset_input {
10778 /* The HWRM command request type. */
10781 * The completion ring to send the completion event on. This should
10782 * be the NQ ID returned from the `nq_alloc` HWRM command.
10784 uint16_t cmpl_ring;
10786 * The sequence ID is used by the driver for tracking multiple
10787 * commands. This ID is treated as opaque data by the firmware and
10788 * the value is returned in the `hwrm_resp_hdr` upon completion.
10792 * The target ID of the command:
10793 * * 0x0-0xFFF8 - The function ID
10794 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10795 * * 0xFFFD - Reserved for user-space HWRM interface
10798 uint16_t target_id;
10800 * A physical address pointer pointing to a host buffer that the
10801 * command's response data will be written. This can be either a host
10802 * physical address (HPA) or a guest physical address (GPA) and must
10803 * point to a physically contiguous block of memory.
10805 uint64_t resp_addr;
10808 * This bit must be '1' for the vf_id_valid field to be
10811 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
10813 * The ID of the VF that this PF is trying to reset.
10814 * Only the parent PF shall be allowed to reset a child VF.
10816 * A parent PF driver shall use this field only when a specific child VF
10817 * is requested to be reset.
10820 /* This value indicates the level of a function reset. */
10821 uint8_t func_reset_level;
10823 * Reset the caller function and its children VFs (if any). If no
10824 * children functions exist, then reset the caller function only.
10826 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
10828 /* Reset the caller function only */
10829 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
10832 * Reset all children VFs of the caller function driver if the
10833 * caller is a PF driver.
10834 * It is an error to specify this level by a VF driver.
10835 * It is an error to specify this level by a PF driver with
10838 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
10841 * Reset a specific VF of the caller function driver if the caller
10842 * is the parent PF driver.
10843 * It is an error to specify this level by a VF driver.
10844 * It is an error to specify this level by a PF driver that is not
10845 * the parent of the VF that is being requested to reset.
10847 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
10849 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
10850 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
10854 /* hwrm_func_reset_output (size:128b/16B) */
10855 struct hwrm_func_reset_output {
10856 /* The specific error status for the command. */
10857 uint16_t error_code;
10858 /* The HWRM command request type. */
10860 /* The sequence ID from the original command. */
10862 /* The length of the response data in number of bytes. */
10864 uint8_t unused_0[7];
10866 * This field is used in Output records to indicate that the output
10867 * is completely written to RAM. This field should be read as '1'
10868 * to indicate that the output has been completely written.
10869 * When writing a command completion or response to an internal processor,
10870 * the order of writes has to be such that this field is written last.
10875 /********************
10876 * hwrm_func_getfid *
10877 ********************/
10880 /* hwrm_func_getfid_input (size:192b/24B) */
10881 struct hwrm_func_getfid_input {
10882 /* The HWRM command request type. */
10885 * The completion ring to send the completion event on. This should
10886 * be the NQ ID returned from the `nq_alloc` HWRM command.
10888 uint16_t cmpl_ring;
10890 * The sequence ID is used by the driver for tracking multiple
10891 * commands. This ID is treated as opaque data by the firmware and
10892 * the value is returned in the `hwrm_resp_hdr` upon completion.
10896 * The target ID of the command:
10897 * * 0x0-0xFFF8 - The function ID
10898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10899 * * 0xFFFD - Reserved for user-space HWRM interface
10902 uint16_t target_id;
10904 * A physical address pointer pointing to a host buffer that the
10905 * command's response data will be written. This can be either a host
10906 * physical address (HPA) or a guest physical address (GPA) and must
10907 * point to a physically contiguous block of memory.
10909 uint64_t resp_addr;
10912 * This bit must be '1' for the pci_id field to be
10915 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
10917 * This value is the PCI ID of the queried function.
10918 * If ARI is enabled, then it is
10919 * Bus Number (8b):Function Number(8b). Otherwise, it is
10920 * Bus Number (8b):Device Number (5b):Function Number(3b).
10923 uint8_t unused_0[2];
10926 /* hwrm_func_getfid_output (size:128b/16B) */
10927 struct hwrm_func_getfid_output {
10928 /* The specific error status for the command. */
10929 uint16_t error_code;
10930 /* The HWRM command request type. */
10932 /* The sequence ID from the original command. */
10934 /* The length of the response data in number of bytes. */
10937 * FID value. This value is used to identify operations on the PCI
10938 * bus as belonging to a particular PCI function.
10941 uint8_t unused_0[5];
10943 * This field is used in Output records to indicate that the output
10944 * is completely written to RAM. This field should be read as '1'
10945 * to indicate that the output has been completely written.
10946 * When writing a command completion or response to an internal processor,
10947 * the order of writes has to be such that this field is written last.
10952 /**********************
10953 * hwrm_func_vf_alloc *
10954 **********************/
10957 /* hwrm_func_vf_alloc_input (size:192b/24B) */
10958 struct hwrm_func_vf_alloc_input {
10959 /* The HWRM command request type. */
10962 * The completion ring to send the completion event on. This should
10963 * be the NQ ID returned from the `nq_alloc` HWRM command.
10965 uint16_t cmpl_ring;
10967 * The sequence ID is used by the driver for tracking multiple
10968 * commands. This ID is treated as opaque data by the firmware and
10969 * the value is returned in the `hwrm_resp_hdr` upon completion.
10973 * The target ID of the command:
10974 * * 0x0-0xFFF8 - The function ID
10975 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10976 * * 0xFFFD - Reserved for user-space HWRM interface
10979 uint16_t target_id;
10981 * A physical address pointer pointing to a host buffer that the
10982 * command's response data will be written. This can be either a host
10983 * physical address (HPA) or a guest physical address (GPA) and must
10984 * point to a physically contiguous block of memory.
10986 uint64_t resp_addr;
10989 * This bit must be '1' for the first_vf_id field to be
10992 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10994 * This value is used to identify a Virtual Function (VF).
10995 * The scope of VF ID is local within a PF.
10997 uint16_t first_vf_id;
10998 /* The number of virtual functions requested. */
11002 /* hwrm_func_vf_alloc_output (size:128b/16B) */
11003 struct hwrm_func_vf_alloc_output {
11004 /* The specific error status for the command. */
11005 uint16_t error_code;
11006 /* The HWRM command request type. */
11008 /* The sequence ID from the original command. */
11010 /* The length of the response data in number of bytes. */
11012 /* The ID of the first VF allocated. */
11013 uint16_t first_vf_id;
11014 uint8_t unused_0[5];
11016 * This field is used in Output records to indicate that the output
11017 * is completely written to RAM. This field should be read as '1'
11018 * to indicate that the output has been completely written.
11019 * When writing a command completion or response to an internal processor,
11020 * the order of writes has to be such that this field is written last.
11025 /*********************
11026 * hwrm_func_vf_free *
11027 *********************/
11030 /* hwrm_func_vf_free_input (size:192b/24B) */
11031 struct hwrm_func_vf_free_input {
11032 /* The HWRM command request type. */
11035 * The completion ring to send the completion event on. This should
11036 * be the NQ ID returned from the `nq_alloc` HWRM command.
11038 uint16_t cmpl_ring;
11040 * The sequence ID is used by the driver for tracking multiple
11041 * commands. This ID is treated as opaque data by the firmware and
11042 * the value is returned in the `hwrm_resp_hdr` upon completion.
11046 * The target ID of the command:
11047 * * 0x0-0xFFF8 - The function ID
11048 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11049 * * 0xFFFD - Reserved for user-space HWRM interface
11052 uint16_t target_id;
11054 * A physical address pointer pointing to a host buffer that the
11055 * command's response data will be written. This can be either a host
11056 * physical address (HPA) or a guest physical address (GPA) and must
11057 * point to a physically contiguous block of memory.
11059 uint64_t resp_addr;
11062 * This bit must be '1' for the first_vf_id field to be
11065 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
11067 * This value is used to identify a Virtual Function (VF).
11068 * The scope of VF ID is local within a PF.
11070 uint16_t first_vf_id;
11072 * The number of virtual functions requested.
11073 * 0xFFFF - Cleanup all children of this PF.
11078 /* hwrm_func_vf_free_output (size:128b/16B) */
11079 struct hwrm_func_vf_free_output {
11080 /* The specific error status for the command. */
11081 uint16_t error_code;
11082 /* The HWRM command request type. */
11084 /* The sequence ID from the original command. */
11086 /* The length of the response data in number of bytes. */
11088 uint8_t unused_0[7];
11090 * This field is used in Output records to indicate that the output
11091 * is completely written to RAM. This field should be read as '1'
11092 * to indicate that the output has been completely written.
11093 * When writing a command completion or response to an internal processor,
11094 * the order of writes has to be such that this field is written last.
11099 /********************
11100 * hwrm_func_vf_cfg *
11101 ********************/
11104 /* hwrm_func_vf_cfg_input (size:448b/56B) */
11105 struct hwrm_func_vf_cfg_input {
11106 /* The HWRM command request type. */
11109 * The completion ring to send the completion event on. This should
11110 * be the NQ ID returned from the `nq_alloc` HWRM command.
11112 uint16_t cmpl_ring;
11114 * The sequence ID is used by the driver for tracking multiple
11115 * commands. This ID is treated as opaque data by the firmware and
11116 * the value is returned in the `hwrm_resp_hdr` upon completion.
11120 * The target ID of the command:
11121 * * 0x0-0xFFF8 - The function ID
11122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11123 * * 0xFFFD - Reserved for user-space HWRM interface
11126 uint16_t target_id;
11128 * A physical address pointer pointing to a host buffer that the
11129 * command's response data will be written. This can be either a host
11130 * physical address (HPA) or a guest physical address (GPA) and must
11131 * point to a physically contiguous block of memory.
11133 uint64_t resp_addr;
11136 * This bit must be '1' for the mtu field to be
11139 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
11142 * This bit must be '1' for the guest_vlan field to be
11145 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
11148 * This bit must be '1' for the async_event_cr field to be
11151 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
11154 * This bit must be '1' for the dflt_mac_addr field to be
11157 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
11160 * This bit must be '1' for the num_rsscos_ctxs field to be
11163 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
11166 * This bit must be '1' for the num_cmpl_rings field to be
11169 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
11172 * This bit must be '1' for the num_tx_rings field to be
11175 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
11178 * This bit must be '1' for the num_rx_rings field to be
11181 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
11184 * This bit must be '1' for the num_l2_ctxs field to be
11187 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
11190 * This bit must be '1' for the num_vnics field to be
11193 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
11196 * This bit must be '1' for the num_stat_ctxs field to be
11199 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
11202 * This bit must be '1' for the num_hw_ring_grps field to be
11205 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
11208 * The maximum transmission unit requested on the function.
11209 * The HWRM should make sure that the mtu of
11210 * the function does not exceed the mtu of the physical
11211 * port that this function is associated with.
11213 * In addition to requesting mtu per function, it is
11214 * possible to configure mtu per transmit ring.
11215 * By default, the mtu of each transmit ring associated
11216 * with a function is equal to the mtu of the function.
11217 * The HWRM should make sure that the mtu of each transmit
11218 * ring that is assigned to a function has a valid mtu.
11222 * The guest VLAN for the function being configured.
11223 * This field's format is same as 802.1Q Tag's
11224 * Tag Control Information (TCI) format that includes both
11225 * Priority Code Point (PCP) and VLAN Identifier (VID).
11227 uint16_t guest_vlan;
11229 * ID of the target completion ring for receiving asynchronous
11230 * event completions. If this field is not valid, then the
11231 * HWRM shall use the default completion ring of the function
11232 * that is being configured as the target completion ring for
11233 * providing any asynchronous event completions for that
11235 * If this field is valid, then the HWRM shall use the
11236 * completion ring identified by this ID as the target
11237 * completion ring for providing any asynchronous event
11238 * completions for the function that is being configured.
11240 uint16_t async_event_cr;
11242 * This value is the current MAC address requested by the VF
11243 * driver to be configured on this VF. A value of
11244 * 00-00-00-00-00-00 indicates no MAC address configuration
11245 * is requested by the VF driver.
11246 * The parent PF driver may reject or overwrite this
11249 uint8_t dflt_mac_addr[6];
11252 * This bit requests that the firmware test to see if all the assets
11253 * requested in this command (i.e. number of TX rings) are available.
11254 * The firmware will return an error if the requested assets are
11255 * not available. The firwmare will NOT reserve the assets if they
11258 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
11261 * This bit requests that the firmware test to see if all the assets
11262 * requested in this command (i.e. number of RX rings) are available.
11263 * The firmware will return an error if the requested assets are
11264 * not available. The firwmare will NOT reserve the assets if they
11267 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
11270 * This bit requests that the firmware test to see if all the assets
11271 * requested in this command (i.e. number of CMPL rings) are available.
11272 * The firmware will return an error if the requested assets are
11273 * not available. The firwmare will NOT reserve the assets if they
11276 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
11279 * This bit requests that the firmware test to see if all the assets
11280 * requested in this command (i.e. number of RSS ctx) are available.
11281 * The firmware will return an error if the requested assets are
11282 * not available. The firwmare will NOT reserve the assets if they
11285 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
11288 * This bit requests that the firmware test to see if all the assets
11289 * requested in this command (i.e. number of ring groups) are available.
11290 * The firmware will return an error if the requested assets are
11291 * not available. The firwmare will NOT reserve the assets if they
11294 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
11297 * This bit requests that the firmware test to see if all the assets
11298 * requested in this command (i.e. number of stat ctx) are available.
11299 * The firmware will return an error if the requested assets are
11300 * not available. The firwmare will NOT reserve the assets if they
11303 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
11306 * This bit requests that the firmware test to see if all the assets
11307 * requested in this command (i.e. number of VNICs) are available.
11308 * The firmware will return an error if the requested assets are
11309 * not available. The firwmare will NOT reserve the assets if they
11312 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
11315 * This bit requests that the firmware test to see if all the assets
11316 * requested in this command (i.e. number of L2 ctx) are available.
11317 * The firmware will return an error if the requested assets are
11318 * not available. The firwmare will NOT reserve the assets if they
11321 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
11324 * If this bit is set to 1, the VF driver is requesting FW to enable
11325 * PPP TX PUSH feature on all the TX rings specified in the
11326 * num_tx_rings field. By default, the PPP TX push feature is
11327 * disabled for all the TX rings of the VF. This flag is ignored if
11328 * the num_tx_rings field is not specified or the VF doesn't support
11329 * PPP tx push feature.
11331 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
11334 * If this bit is set to 1, the VF driver is requesting FW to disable
11335 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
11336 * ignored if the VF doesn't support PPP tx push feature.
11338 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
11340 /* The number of RSS/COS contexts requested for the VF. */
11341 uint16_t num_rsscos_ctxs;
11342 /* The number of completion rings requested for the VF. */
11343 uint16_t num_cmpl_rings;
11344 /* The number of transmit rings requested for the VF. */
11345 uint16_t num_tx_rings;
11346 /* The number of receive rings requested for the VF. */
11347 uint16_t num_rx_rings;
11348 /* The number of L2 contexts requested for the VF. */
11349 uint16_t num_l2_ctxs;
11350 /* The number of vnics requested for the VF. */
11351 uint16_t num_vnics;
11352 /* The number of statistic contexts requested for the VF. */
11353 uint16_t num_stat_ctxs;
11354 /* The number of HW ring groups requested for the VF. */
11355 uint16_t num_hw_ring_grps;
11356 uint8_t unused_0[4];
11359 /* hwrm_func_vf_cfg_output (size:128b/16B) */
11360 struct hwrm_func_vf_cfg_output {
11361 /* The specific error status for the command. */
11362 uint16_t error_code;
11363 /* The HWRM command request type. */
11365 /* The sequence ID from the original command. */
11367 /* The length of the response data in number of bytes. */
11369 uint8_t unused_0[7];
11371 * This field is used in Output records to indicate that the output
11372 * is completely written to RAM. This field should be read as '1'
11373 * to indicate that the output has been completely written.
11374 * When writing a command completion or response to an internal processor,
11375 * the order of writes has to be such that this field is written last.
11380 /*******************
11381 * hwrm_func_qcaps *
11382 *******************/
11385 /* hwrm_func_qcaps_input (size:192b/24B) */
11386 struct hwrm_func_qcaps_input {
11387 /* The HWRM command request type. */
11390 * The completion ring to send the completion event on. This should
11391 * be the NQ ID returned from the `nq_alloc` HWRM command.
11393 uint16_t cmpl_ring;
11395 * The sequence ID is used by the driver for tracking multiple
11396 * commands. This ID is treated as opaque data by the firmware and
11397 * the value is returned in the `hwrm_resp_hdr` upon completion.
11401 * The target ID of the command:
11402 * * 0x0-0xFFF8 - The function ID
11403 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11404 * * 0xFFFD - Reserved for user-space HWRM interface
11407 uint16_t target_id;
11409 * A physical address pointer pointing to a host buffer that the
11410 * command's response data will be written. This can be either a host
11411 * physical address (HPA) or a guest physical address (GPA) and must
11412 * point to a physically contiguous block of memory.
11414 uint64_t resp_addr;
11416 * Function ID of the function that is being queried.
11417 * 0xFF... (All Fs) if the query is for the requesting
11419 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
11420 * to be used by a trusted VF to query its parent PF.
11423 uint8_t unused_0[6];
11426 /* hwrm_func_qcaps_output (size:704b/88B) */
11427 struct hwrm_func_qcaps_output {
11428 /* The specific error status for the command. */
11429 uint16_t error_code;
11430 /* The HWRM command request type. */
11432 /* The sequence ID from the original command. */
11434 /* The length of the response data in number of bytes. */
11437 * FID value. This value is used to identify operations on the PCI
11438 * bus as belonging to a particular PCI function.
11442 * Port ID of port that this function is associated with.
11443 * Valid only for the PF.
11444 * 0xFF... (All Fs) if this function is not associated with
11446 * 0xFF... (All Fs) if this function is called from a VF.
11450 /* If 1, then Push mode is supported on this function. */
11451 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
11454 * If 1, then the global MSI-X auto-masking is enabled for the
11457 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
11460 * If 1, then the Precision Time Protocol (PTP) processing
11461 * is supported on this function.
11462 * The HWRM should enable PTP on only a single Physical
11463 * Function (PF) per port.
11465 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
11468 * If 1, then RDMA over Converged Ethernet (RoCE) v1
11469 * is supported on this function.
11471 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
11474 * If 1, then RDMA over Converged Ethernet (RoCE) v2
11475 * is supported on this function.
11477 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
11480 * If 1, then control and configuration of WoL magic packet
11481 * are supported on this function.
11483 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
11486 * If 1, then control and configuration of bitmap pattern
11487 * packet are supported on this function.
11489 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
11492 * If set to 1, then the control and configuration of rate limit
11493 * of an allocated TX ring on the queried function is supported.
11495 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
11498 * If 1, then control and configuration of minimum and
11499 * maximum bandwidths are supported on the queried function.
11501 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
11504 * If the query is for a VF, then this flag shall be ignored.
11505 * If this query is for a PF and this flag is set to 1,
11506 * then the PF has the capability to set the rate limits
11507 * on the TX rings of its children VFs.
11508 * If this query is for a PF and this flag is set to 0, then
11509 * the PF does not have the capability to set the rate limits
11510 * on the TX rings of its children VFs.
11512 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
11515 * If the query is for a VF, then this flag shall be ignored.
11516 * If this query is for a PF and this flag is set to 1,
11517 * then the PF has the capability to set the minimum and/or
11518 * maximum bandwidths for its children VFs.
11519 * If this query is for a PF and this flag is set to 0, then
11520 * the PF does not have the capability to set the minimum or
11521 * maximum bandwidths for its children VFs.
11523 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
11526 * Standard TX Ring mode is used for the allocation of TX ring
11527 * and underlying scheduling resources that allow bandwidth
11528 * reservation and limit settings on the queried function.
11529 * If set to 1, then standard TX ring mode is supported
11530 * on the queried function.
11531 * If set to 0, then standard TX ring mode is not available
11532 * on the queried function.
11534 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
11537 * If the query is for a VF, then this flag shall be ignored,
11538 * If this query is for a PF and this flag is set to 1,
11539 * then the PF has the capability to detect GENEVE tunnel
11542 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
11545 * If the query is for a VF, then this flag shall be ignored,
11546 * If this query is for a PF and this flag is set to 1,
11547 * then the PF has the capability to detect NVGRE tunnel
11550 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
11553 * If the query is for a VF, then this flag shall be ignored,
11554 * If this query is for a PF and this flag is set to 1,
11555 * then the PF has the capability to detect GRE tunnel
11558 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
11561 * If the query is for a VF, then this flag shall be ignored,
11562 * If this query is for a PF and this flag is set to 1,
11563 * then the PF has the capability to detect MPLS tunnel
11566 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
11569 * If the query is for a VF, then this flag shall be ignored,
11570 * If this query is for a PF and this flag is set to 1,
11571 * then the PF has the capability to support pcie stats.
11573 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
11576 * If the query is for a VF, then this flag shall be ignored,
11577 * If this query is for a PF and this flag is set to 1,
11578 * then the PF has the capability to adopt the VF's belonging
11581 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
11584 * If the query is for a VF, then this flag shall be ignored,
11585 * If this query is for a PF and this flag is set to 1,
11586 * then the PF has the administrative privilege to configure another PF
11588 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
11591 * If the query is for a VF, then this flag shall be ignored.
11592 * If this query is for a PF and this flag is set to 1, then
11593 * the PF will know that the firmware has the capability to track
11594 * the virtual link status.
11596 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
11599 * If 1, then this function supports the push mode that uses
11600 * write combine buffers and the long inline tx buffer descriptor.
11602 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
11605 * If 1, then FW has capability to allocate TX rings dynamically
11606 * in ring alloc even if PF reserved pool is zero.
11607 * This bit will be used only for PFs.
11609 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
11612 * When this bit is '1', it indicates that core firmware is
11613 * capable of Hot Reset.
11615 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
11618 * This flag will be set to 1 by the FW if FW supports adapter error
11621 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
11624 * If the query is for a VF, then this flag shall be ignored.
11625 * If this query is for a PF and this flag is set to 1, then
11626 * the PF has the capability to support extended stats.
11628 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
11629 UINT32_C(0x1000000)
11631 * If the query is for a VF, then this flag shall be ignored.
11632 * If this query is for a PF and this flag is set to 1, then host
11633 * must initiate reset or reload (or fastboot) the firmware image
11634 * upon detection of device shutdown state.
11636 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
11637 UINT32_C(0x2000000)
11639 * If the query is for a VF, then this flag (always set to 0) shall
11640 * be ignored. If this query is for a PF and this flag is set to 1,
11641 * host, when registered for the default vnic change async event,
11642 * receives async notification whenever a default vnic state is
11643 * changed for any of child or adopted VFs.
11645 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
11646 UINT32_C(0x4000000)
11647 /* If set to 1, then the vlan acceleration for TX is disabled. */
11648 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
11649 UINT32_C(0x8000000)
11651 * When this bit is '1', it indicates that core firmware supports
11652 * DBG_COREDUMP_XXX commands.
11654 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
11655 UINT32_C(0x10000000)
11657 * When this bit is '1', it indicates that core firmware supports
11658 * DBG_CRASHDUMP_XXX commands.
11660 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
11661 UINT32_C(0x20000000)
11663 * If the query is for a VF, then this flag should be ignored.
11664 * If the query is for a PF and this flag is set to 1, then
11665 * the PF has the capability to support retrieval of
11666 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
11667 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
11668 * If this flag is set to 1, only that (supported) command should
11669 * be used for retrieval of PFC related statistics (rather than
11670 * hwrm_port_qstats_ext command, which could previously be used).
11672 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
11673 UINT32_C(0x40000000)
11675 * When this bit is '1', it indicates that core firmware supports
11676 * DBG_QCAPS command
11678 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
11679 UINT32_C(0x80000000)
11681 * This value is current MAC address configured for this
11682 * function. A value of 00-00-00-00-00-00 indicates no
11683 * MAC address is currently configured.
11685 uint8_t mac_address[6];
11687 * The maximum number of RSS/COS contexts that can be
11688 * allocated to the function.
11690 uint16_t max_rsscos_ctx;
11692 * The maximum number of completion rings that can be
11693 * allocated to the function.
11695 uint16_t max_cmpl_rings;
11697 * The maximum number of transmit rings that can be
11698 * allocated to the function.
11700 uint16_t max_tx_rings;
11702 * The maximum number of receive rings that can be
11703 * allocated to the function.
11705 uint16_t max_rx_rings;
11707 * The maximum number of L2 contexts that can be
11708 * allocated to the function.
11710 uint16_t max_l2_ctxs;
11712 * The maximum number of VNICs that can be
11713 * allocated to the function.
11715 uint16_t max_vnics;
11717 * The identifier for the first VF enabled on a PF. This
11718 * is valid only on the PF with SR-IOV enabled.
11719 * 0xFF... (All Fs) if this command is called on a PF with
11720 * SR-IOV disabled or on a VF.
11722 uint16_t first_vf_id;
11724 * The maximum number of VFs that can be
11725 * allocated to the function. This is valid only on the
11726 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
11727 * command is called on a PF with SR-IOV disabled or
11732 * The maximum number of statistic contexts that can be
11733 * allocated to the function.
11735 uint16_t max_stat_ctx;
11737 * The maximum number of Encapsulation records that can be
11738 * offloaded by this function.
11740 uint32_t max_encap_records;
11742 * The maximum number of decapsulation records that can
11743 * be offloaded by this function.
11745 uint32_t max_decap_records;
11747 * The maximum number of Exact Match (EM) flows that can be
11748 * offloaded by this function on the TX side.
11750 uint32_t max_tx_em_flows;
11752 * The maximum number of Wildcard Match (WM) flows that can
11753 * be offloaded by this function on the TX side.
11755 uint32_t max_tx_wm_flows;
11757 * The maximum number of Exact Match (EM) flows that can be
11758 * offloaded by this function on the RX side.
11760 uint32_t max_rx_em_flows;
11762 * The maximum number of Wildcard Match (WM) flows that can
11763 * be offloaded by this function on the RX side.
11765 uint32_t max_rx_wm_flows;
11767 * The maximum number of multicast filters that can
11768 * be supported by this function on the RX side.
11770 uint32_t max_mcast_filters;
11772 * The maximum value of flow_id that can be supported
11773 * in completion records.
11775 uint32_t max_flow_id;
11777 * The maximum number of HW ring groups that can be
11778 * supported on this function.
11780 uint32_t max_hw_ring_grps;
11782 * The maximum number of strict priority transmit rings
11783 * that can be allocated to the function.
11784 * This number indicates the maximum number of TX rings
11785 * that can be assigned strict priorities out of the
11786 * maximum number of TX rings that can be allocated
11787 * (max_tx_rings) to the function.
11789 uint16_t max_sp_tx_rings;
11790 uint8_t unused_0[2];
11791 uint32_t flags_ext;
11793 * If 1, the device can be configured to set the ECN bits in the
11794 * IP header of received packets if the receive queue length
11795 * exceeds a given threshold.
11797 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
11800 * If 1, the device can report the number of received packets
11801 * that it marked as having experienced congestion.
11803 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
11806 * If 1, the device can report extended hw statistics (including
11807 * additional tpa statistics).
11809 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
11812 * If set to 1, then the core firmware has support to enable/
11813 * disable hot reset support for interface dynamically through
11816 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
11818 /* If 1, the proxy mode is supported on this function */
11819 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
11822 * If 1, the tx rings source interface override feature is supported
11823 * on this function.
11825 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
11828 * If 1, the device supports scheduler queues. SCHQs can be managed
11829 * using RING_SCHQ_ALLOC/CFG/FREE commands.
11831 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
11834 * If set to 1, then this function supports the TX push mode that
11835 * uses ping-pong buffers from the push pages.
11837 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
11840 * If set to 1, then this function doesn't have the privilege to
11841 * configure the EVB mode of the port it uses.
11843 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
11846 * If set to 1, then the HW and FW support the SoC packet DMA
11847 * datapath between SoC and NIC. This function can act as the
11848 * HWRM communication transport agent on behalf of the SoC SPD
11849 * software module. This capability is only advertised to the
11852 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
11855 * If set to 1, then this function supports FW_LIVEPATCH for
11856 * firmware livepatch commands.
11858 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
11861 * When this bit is '1', it indicates that core firmware is
11862 * capable of fast Reset.
11864 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
11867 * When this bit is '1', it indicates that firmware and hardware
11868 * are capable of updating tx_metadata via hwrm_ring_cfg command.
11870 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
11873 * If set to 1, then the device can report the action
11874 * needed to activate set nvm options.
11876 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
11879 * When this bit is '1', it indicates that the BD metadata feature
11880 * is supported for this function.
11882 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
11885 * When this bit is '1', it indicates that the echo request feature
11886 * is supported for this function. If the driver registers for the
11887 * echo request asynchronous event, then the firmware can send an
11888 * unsolicited echo request to the driver and expect an echo
11891 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
11894 * When this bit is '1', it indicates that core firmware supports
11895 * NPAR 1.2 on this function.
11897 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \
11899 /* When this bit is '1', it indicates that PTM feature is supported. */
11900 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \
11902 /* When this bit is '1', it indicates that PPS feature is supported. */
11903 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \
11906 * When this bit is '1', it indicates that VF config. change
11907 * async event is supported on the parent PF if the async.
11908 * event is registered by the PF.
11910 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \
11913 * When this bit is '1', the NIC supports configuration of
11914 * partition_min_bw and partition_max_bw.
11916 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \
11919 * When this bit is '1', the FW supports configuration of
11920 * PCP and TPID values of the default VLAN.
11922 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \
11924 /* When this bit is '1', it indicates that HW and FW support KTLS. */
11925 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \
11928 * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG
11929 * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions
11930 * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive
11933 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \
11935 /* The maximum number of SCHQs supported by this device. */
11937 uint8_t mpc_chnls_cap;
11939 * When this bit is '1', it indicates that HW and firmware
11940 * supports the use of a MPC channel with destination set
11941 * to the TX crypto engine block.
11943 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
11945 * When this bit is '1', it indicates that HW and firmware
11946 * supports the use of a MPC channel with destination set
11947 * to the RX crypto engine block.
11949 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
11951 * When this bit is '1', it indicates that HW and firmware
11952 * supports the use of a MPC channel with destination set
11953 * to the TX configurable flow processing block.
11955 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
11957 * When this bit is '1', it indicates that HW and firmware
11958 * supports the use of a MPC channel with destination set
11959 * to the RX configurable flow processing block.
11961 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
11963 * When this bit is '1', it indicates that HW and firmware
11964 * supports the use of a MPC channel with destination set
11965 * to the primate processor block.
11967 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
11970 * This field is used in Output records to indicate that the output
11971 * is completely written to RAM. This field should be read as '1'
11972 * to indicate that the output has been completely written.
11973 * When writing a command completion or response to an internal
11974 * processor, the order of writes has to be such that this field is
11980 /******************
11982 ******************/
11985 /* hwrm_func_qcfg_input (size:192b/24B) */
11986 struct hwrm_func_qcfg_input {
11987 /* The HWRM command request type. */
11990 * The completion ring to send the completion event on. This should
11991 * be the NQ ID returned from the `nq_alloc` HWRM command.
11993 uint16_t cmpl_ring;
11995 * The sequence ID is used by the driver for tracking multiple
11996 * commands. This ID is treated as opaque data by the firmware and
11997 * the value is returned in the `hwrm_resp_hdr` upon completion.
12001 * The target ID of the command:
12002 * * 0x0-0xFFF8 - The function ID
12003 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12004 * * 0xFFFD - Reserved for user-space HWRM interface
12007 uint16_t target_id;
12009 * A physical address pointer pointing to a host buffer that the
12010 * command's response data will be written. This can be either a host
12011 * physical address (HPA) or a guest physical address (GPA) and must
12012 * point to a physically contiguous block of memory.
12014 uint64_t resp_addr;
12016 * Function ID of the function that is being queried.
12017 * 0xFF... (All Fs) if the query is for the requesting
12019 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
12020 * to be used by a trusted VF to query its parent PF.
12023 uint8_t unused_0[6];
12026 /* hwrm_func_qcfg_output (size:832b/104B) */
12027 struct hwrm_func_qcfg_output {
12028 /* The specific error status for the command. */
12029 uint16_t error_code;
12030 /* The HWRM command request type. */
12032 /* The sequence ID from the original command. */
12034 /* The length of the response data in number of bytes. */
12037 * FID value. This value is used to identify operations on the PCI
12038 * bus as belonging to a particular PCI function.
12042 * Port ID of port that this function is associated with.
12043 * 0xFF... (All Fs) if this function is not associated with
12048 * This value is the current VLAN setting for this
12049 * function. The value of 0 for this field indicates
12050 * no priority tagging or VLAN is used.
12051 * This field's format is same as 802.1Q Tag's
12052 * Tag Control Information (TCI) format that includes both
12053 * Priority Code Point (PCP) and VLAN Identifier (VID).
12058 * If 1, then magic packet based Out-Of-Box WoL is enabled on
12059 * the port associated with this function.
12061 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
12064 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
12065 * on the port associated with this function.
12067 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
12070 * If set to 1, then FW based DCBX agent is enabled and running on
12071 * the port associated with this function.
12072 * If set to 0, then DCBX agent is not running in the firmware.
12074 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
12077 * Standard TX Ring mode is used for the allocation of TX ring
12078 * and underlying scheduling resources that allow bandwidth
12079 * reservation and limit settings on the queried function.
12080 * If set to 1, then standard TX ring mode is enabled
12081 * on the queried function.
12082 * If set to 0, then the standard TX ring mode is disabled
12083 * on the queried function. In this extended TX ring resource
12084 * mode, the minimum and maximum bandwidth settings are not
12085 * supported to allow the allocation of TX rings to span multiple
12088 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
12091 * If set to 1 then FW based LLDP agent is enabled and running on
12092 * the port associated with this function.
12093 * If set to 0 then the LLDP agent is not running in the firmware.
12095 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
12098 * If set to 1, then multi-host mode is active for this function.
12099 * The NIC is attached to two or more independent host systems
12100 * through two or more PCIe endpoints.
12101 * If set to 0, then multi-host mode is inactive for this function
12102 * or not applicable for this device.
12104 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
12107 * If the function that is being queried is a PF, then the HWRM shall
12108 * set this field to 0 and the HWRM client shall ignore this field.
12109 * If the function that is being queried is a VF, then the HWRM shall
12110 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
12111 * shall set this field to 0.
12113 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
12116 * If set to 1, then secure mode is enabled for this function or device.
12117 * If set to 0, then secure mode is disabled (or normal mode) for this
12118 * function or device.
12120 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
12123 * If set to 1, then this PF is enabled with a preboot driver that
12124 * requires access to the legacy L2 ring model and legacy 32b
12125 * doorbells. If set to 0, then this PF is not allowed to use
12126 * the legacy L2 rings. This feature is not allowed on VFs and
12127 * is only relevant for devices that require a context backing
12130 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
12133 * If set to 1, then the firmware and all currently registered driver
12134 * instances support hot reset. The hot reset support will be updated
12135 * dynamically based on the driver interface advertisement.
12136 * If set to 0, then the adapter is not currently able to initiate
12139 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
12142 * If set to 1, then the PPP tx push mode is enabled for all the
12143 * reserved TX rings of this function. If set to 0, then PPP tx push
12144 * mode is disabled for all the reserved TX rings of this function.
12146 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
12149 * If set to 1, then the firmware will notify driver using async
12150 * event when a ring is disabled due to a Hardware error.
12152 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
12155 * If set to 1, then the firmware and all currently registered driver
12156 * instances support fast reset. The fast reset support will be
12157 * updated dynamically based on the driver interface advertisement.
12158 * If set to 0, then the adapter is not currently able to initiate
12161 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
12164 * If set to 1, then multi-root mode is active for this function.
12165 * The NIC is attached to a single host with a single operating
12166 * system, but through two or more PCIe endpoints.
12167 * If set to 0, then multi-root mode is inactive for this function
12168 * or not applicable for this device.
12170 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
12173 * This flag indicates RDMA support for child VFS of
12174 * a physical function.
12175 * If set to 1, RoCE is supported on all child VFs.
12176 * If set to 0, RoCE is disabled on all child VFs.
12178 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \
12181 * This value is current MAC address configured for this
12182 * function. A value of 00-00-00-00-00-00 indicates no
12183 * MAC address is currently configured.
12185 uint8_t mac_address[6];
12187 * This value is current PCI ID of this
12188 * function. If ARI is enabled, then it is
12189 * Bus Number (8b):Function Number(8b). Otherwise, it is
12190 * Bus Number (8b):Device Number (4b):Function Number(4b).
12191 * If multi-host mode is active, the 4 lsb will indicate
12192 * the PF index for this function.
12196 * The number of RSS/COS contexts currently
12197 * allocated to the function.
12199 uint16_t alloc_rsscos_ctx;
12201 * The number of completion rings currently allocated to
12202 * the function. This does not include the rings allocated
12203 * to any children functions if any.
12205 uint16_t alloc_cmpl_rings;
12207 * The number of transmit rings currently allocated to
12208 * the function. This does not include the rings allocated
12209 * to any children functions if any.
12211 uint16_t alloc_tx_rings;
12213 * The number of receive rings currently allocated to
12214 * the function. This does not include the rings allocated
12215 * to any children functions if any.
12217 uint16_t alloc_rx_rings;
12218 /* The allocated number of L2 contexts to the function. */
12219 uint16_t alloc_l2_ctx;
12220 /* The allocated number of vnics to the function. */
12221 uint16_t alloc_vnics;
12223 * The maximum transmission unit of the function
12224 * configured by the admin pf.
12225 * If the reported mtu value is non-zero then it will be used for the
12226 * rings allocated on this function, otherwise the default
12227 * value is used if ring MTU is not specified.
12228 * The driver cannot use any MTU bigger than this value
12229 * if it is non-zero.
12231 uint16_t admin_mtu;
12233 * The maximum receive unit of the function.
12234 * For vnics allocated on this function, this default
12235 * value is used if vnic MRU is not specified.
12238 /* The statistics context assigned to a function. */
12239 uint16_t stat_ctx_id;
12241 * The HWRM shall return Unknown value for this field
12242 * when this command is used to query VF's configuration.
12244 uint8_t port_partition_type;
12245 /* Single physical function */
12246 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
12247 /* Multiple physical functions */
12248 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
12249 /* Network Partitioning 1.0 */
12250 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
12251 /* Network Partitioning 1.5 */
12252 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
12253 /* Network Partitioning 2.0 */
12254 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
12255 /* Network Partitioning 1.2 */
12256 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
12258 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
12260 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
12261 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
12263 * This field will indicate number of physical functions on this port_partition.
12264 * HWRM shall return unavail (i.e. value of 0) for this field
12265 * when this command is used to query VF's configuration or
12266 * from older firmware that doesn't support this field.
12268 uint8_t port_pf_cnt;
12269 /* number of PFs is not available */
12270 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
12271 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
12272 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
12274 * The default VNIC ID assigned to a function that is
12277 uint16_t dflt_vnic_id;
12278 uint16_t max_mtu_configured;
12280 * Minimum guaranteed transmit bandwidth for this function. When
12281 * specified for a PF, does not affect traffic from the PF's child VFs.
12282 * A value of 0 indicates the minimum bandwidth is not configured.
12285 /* The bandwidth value. */
12286 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
12287 UINT32_C(0xfffffff)
12288 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
12289 /* The granularity of the value (bits or bytes). */
12290 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
12291 UINT32_C(0x10000000)
12292 /* Value is in bits. */
12293 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
12294 (UINT32_C(0x0) << 28)
12295 /* Value is in bytes. */
12296 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
12297 (UINT32_C(0x1) << 28)
12298 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
12299 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
12300 /* bw_value_unit is 3 b */
12301 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
12302 UINT32_C(0xe0000000)
12303 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
12304 /* Value is in Mb or MB (base 10). */
12305 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
12306 (UINT32_C(0x0) << 29)
12307 /* Value is in Kb or KB (base 10). */
12308 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
12309 (UINT32_C(0x2) << 29)
12310 /* Value is in bits or bytes. */
12311 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
12312 (UINT32_C(0x4) << 29)
12313 /* Value is in Gb or GB (base 10). */
12314 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
12315 (UINT32_C(0x6) << 29)
12316 /* Value is in 1/100th of a percentage of link bandwidth. */
12317 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12318 (UINT32_C(0x1) << 29)
12320 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
12321 (UINT32_C(0x7) << 29)
12322 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
12323 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
12325 * Maximum transmit rate for this function. When specified for a PF,
12326 * does not affect traffic from the PF's child VFs.
12327 * A value of 0 indicates that the maximum bandwidth is not configured.
12330 /* The bandwidth value. */
12331 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
12332 UINT32_C(0xfffffff)
12333 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
12334 /* The granularity of the value (bits or bytes). */
12335 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
12336 UINT32_C(0x10000000)
12337 /* Value is in bits. */
12338 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
12339 (UINT32_C(0x0) << 28)
12340 /* Value is in bytes. */
12341 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
12342 (UINT32_C(0x1) << 28)
12343 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
12344 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
12345 /* bw_value_unit is 3 b */
12346 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
12347 UINT32_C(0xe0000000)
12348 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
12349 /* Value is in Mb or MB (base 10). */
12350 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
12351 (UINT32_C(0x0) << 29)
12352 /* Value is in Kb or KB (base 10). */
12353 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
12354 (UINT32_C(0x2) << 29)
12355 /* Value is in bits or bytes. */
12356 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
12357 (UINT32_C(0x4) << 29)
12358 /* Value is in Gb or GB (base 10). */
12359 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
12360 (UINT32_C(0x6) << 29)
12361 /* Value is in 1/100th of a percentage of link bandwidth. */
12362 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12363 (UINT32_C(0x1) << 29)
12365 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
12366 (UINT32_C(0x7) << 29)
12367 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
12368 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
12370 * This value indicates the Edge virtual bridge mode for the
12371 * domain that this function belongs to.
12374 /* No Edge Virtual Bridging (EVB) */
12375 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
12376 /* Virtual Ethernet Bridge (VEB) */
12377 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
12378 /* Virtual Ethernet Port Aggregator (VEPA) */
12379 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
12380 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
12381 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
12384 * This value indicates the PCIE device cache line size.
12385 * The cache line size allows the DMA writes to terminate and
12386 * start at the cache boundary.
12388 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
12390 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
12391 /* Cache Line Size 64 bytes */
12392 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
12394 /* Cache Line Size 128 bytes */
12395 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
12397 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
12398 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
12399 /* This value is the virtual link admin state setting. */
12400 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
12402 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
12403 /* Admin link state is in forced down mode. */
12404 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
12405 (UINT32_C(0x0) << 2)
12406 /* Admin link state is in forced up mode. */
12407 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
12408 (UINT32_C(0x1) << 2)
12409 /* Admin link state is in auto mode - follows the physical link state. */
12410 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
12411 (UINT32_C(0x2) << 2)
12412 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
12413 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
12414 /* Reserved for future. */
12415 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
12417 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
12419 * The number of VFs that are allocated to the function.
12420 * This is valid only on the PF with SR-IOV enabled.
12421 * 0xFF... (All Fs) if this command is called on a PF with
12422 * SR-IOV disabled or on a VF.
12424 uint16_t alloc_vfs;
12426 * The number of allocated multicast filters for this
12427 * function on the RX side.
12429 uint32_t alloc_mcast_filters;
12431 * The number of allocated HW ring groups for this
12434 uint32_t alloc_hw_ring_grps;
12436 * The number of strict priority transmit rings out of
12437 * currently allocated TX rings to the function
12438 * (alloc_tx_rings).
12440 uint16_t alloc_sp_tx_rings;
12442 * The number of statistics contexts
12443 * currently reserved for the function.
12445 uint16_t alloc_stat_ctx;
12447 * This field specifies how many NQs are reserved for the PF.
12448 * Remaining NQs that belong to the PF are available for VFs.
12449 * Once a PF has created VFs, it cannot change how many NQs are
12450 * reserved for itself (since the NQs must be contiguous in HW).
12452 uint16_t alloc_msix;
12454 * The number of registered VF’s associated with the PF. This field
12455 * should be ignored when the request received on the VF interface.
12456 * This field will be updated on the PF interface to initiate
12457 * the unregister request on PF in the HOT Reset Process.
12459 uint16_t registered_vfs;
12461 * The size of the doorbell BAR in KBytes reserved for L2 including
12462 * any area that is shared between L2 and RoCE. The L2 driver
12463 * should only map the L2 portion of the doorbell BAR. Any rounding
12464 * of the BAR size to the native CPU page size should be performed
12465 * by the driver. If the value is zero, no special partitioning
12466 * of the doorbell BAR between L2 and RoCE is required.
12468 uint16_t l2_doorbell_bar_size_kb;
12471 * For backward compatibility this field must be set to 1.
12472 * Older drivers might look for this field to be 1 before
12473 * processing the message.
12477 * This GRC address location is used by the Host driver interfaces to poll
12478 * the adapter ready state to re-initiate the registration process again
12479 * after receiving the RESET Notify event.
12481 uint32_t reset_addr_poll;
12483 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
12484 * this value to find out the doorbell page offset from the BAR.
12486 uint16_t legacy_l2_db_size_kb;
12487 uint16_t svif_info;
12489 * This field specifies the source virtual interface of the function being
12490 * queried. Drivers can use this to program svif field in the L2 context
12493 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
12494 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
12495 /* This field specifies whether svif is valid or not */
12496 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
12499 * When this bit is '1', it indicates that a MPC channel with
12500 * destination set to the TX crypto engine block is enabled.
12502 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
12505 * When this bit is '1', it indicates that a MPC channel with
12506 * destination set to the RX crypto engine block is enabled.
12508 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
12511 * When this bit is '1', it indicates that a MPC channel with
12512 * destination set to the TX configurable flow processing block is
12515 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
12518 * When this bit is '1', it indicates that a MPC channel with
12519 * destination set to the RX configurable flow processing block is
12522 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
12525 * When this bit is '1', it indicates that a MPC channel with
12526 * destination set to the primate processor block is enabled.
12528 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
12530 uint8_t unused_2[3];
12532 * Minimum guaranteed bandwidth for the network partition made up
12533 * of the caller physical function and all its child virtual
12534 * functions. The rate is specified as a percentage of the bandwidth
12535 * of the link the partition is associated with. A value of 0
12536 * indicates that no minimum bandwidth is configured.
12537 * The format of this field is defined to match min_bw, even though
12538 * the partition minimum rate is always specified as a percentage.
12540 uint32_t partition_min_bw;
12541 /* The bandwidth value. */
12542 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
12543 UINT32_C(0xfffffff)
12544 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
12547 * The granularity of the value (bits or bytes). Firmware never sets
12550 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \
12551 UINT32_C(0x10000000)
12552 /* Value is in bits. */
12553 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \
12554 (UINT32_C(0x0) << 28)
12555 /* Value is in bytes. */
12556 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \
12557 (UINT32_C(0x1) << 28)
12558 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \
12559 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES
12560 /* Always percentage of link bandwidth. */
12561 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
12562 UINT32_C(0xe0000000)
12563 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
12565 /* Bandwidth value is in hundredths of a percent of link bandwidth. */
12566 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12567 (UINT32_C(0x1) << 29)
12568 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
12569 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
12571 * The maximum bandwidth that may be used by the network partition
12572 * made up of the caller physical function and all its child virtual
12573 * functions. The rate is specified as a percentage of the bandwidth
12574 * of the link the partition is associated with. A value of 0
12575 * indicates that no maximum bandwidth is configured.
12576 * The format of this field is defined to match max_bw, even though
12577 * the partition bandwidth must be specified as a percentage.
12579 uint32_t partition_max_bw;
12580 /* The bandwidth value. */
12581 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
12582 UINT32_C(0xfffffff)
12583 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
12586 * The granularity of the value (bits or bytes). Firmware never sets
12589 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \
12590 UINT32_C(0x10000000)
12591 /* Value is in bits. */
12592 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \
12593 (UINT32_C(0x0) << 28)
12594 /* Value is in bytes. */
12595 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \
12596 (UINT32_C(0x1) << 28)
12597 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \
12598 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES
12599 /* Always a percentage of link bandwidth. */
12600 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
12601 UINT32_C(0xe0000000)
12602 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
12604 /* Value is in hundredths of a percent of link bandwidth. */
12605 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12606 (UINT32_C(0x1) << 29)
12607 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
12608 HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
12610 * The maximum transmission unit of the function
12611 * configured by the host pf/vf.
12612 * If the reported mtu value is non-zero then it will be used for the
12613 * rings allocated on this function, otherwise the default
12614 * value is used if ring MTU is not specified.
12619 * This field is used in Output records to indicate that the output
12620 * is completely written to RAM. This field should be read as '1'
12621 * to indicate that the output has been completely written.
12622 * When writing a command completion or response to an internal processor,
12623 * the order of writes has to be such that this field is written last.
12633 /* hwrm_func_cfg_input (size:832b/104B) */
12634 struct hwrm_func_cfg_input {
12635 /* The HWRM command request type. */
12638 * The completion ring to send the completion event on. This should
12639 * be the NQ ID returned from the `nq_alloc` HWRM command.
12641 uint16_t cmpl_ring;
12643 * The sequence ID is used by the driver for tracking multiple
12644 * commands. This ID is treated as opaque data by the firmware and
12645 * the value is returned in the `hwrm_resp_hdr` upon completion.
12649 * The target ID of the command:
12650 * * 0x0-0xFFF8 - The function ID
12651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12652 * * 0xFFFD - Reserved for user-space HWRM interface
12655 uint16_t target_id;
12657 * A physical address pointer pointing to a host buffer that the
12658 * command's response data will be written. This can be either a host
12659 * physical address (HPA) or a guest physical address (GPA) and must
12660 * point to a physically contiguous block of memory.
12662 uint64_t resp_addr;
12664 * Function ID of the function that is being
12666 * If set to 0xFF... (All Fs), then the configuration is
12667 * for the requesting function.
12671 * This field specifies how many NQs will be reserved for the PF.
12672 * Remaining NQs that belong to the PF become available for VFs.
12673 * Once a PF has created VFs, it cannot change how many NQs are
12674 * reserved for itself (since the NQs must be contiguous in HW).
12679 * When this bit is '1', the function is disabled with
12680 * source MAC address check.
12681 * This is an anti-spoofing check. If this flag is set,
12682 * then the function shall be configured to disallow
12683 * transmission of frames with the source MAC address that
12684 * is configured for this function.
12686 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
12689 * When this bit is '1', the function is enabled with
12690 * source MAC address check.
12691 * This is an anti-spoofing check. If this flag is set,
12692 * then the function shall be configured to allow
12693 * transmission of frames with the source MAC address that
12694 * is configured for this function.
12696 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
12699 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
12701 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
12703 * Standard TX Ring mode is used for the allocation of TX ring
12704 * and underlying scheduling resources that allow bandwidth
12705 * reservation and limit settings on the queried function.
12706 * If set to 1, then standard TX ring mode is requested to be
12707 * enabled on the function being configured.
12709 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
12712 * Standard TX Ring mode is used for the allocation of TX ring
12713 * and underlying scheduling resources that allow bandwidth
12714 * reservation and limit settings on the queried function.
12715 * If set to 1, then the standard TX ring mode is requested to
12716 * be disabled on the function being configured. In this extended
12717 * TX ring resource mode, the minimum and maximum bandwidth settings
12718 * are not supported to allow the allocation of TX rings to
12719 * span multiple scheduler nodes.
12721 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
12724 * If this bit is set, virtual mac address configured
12725 * in this command will be persistent over warm boot.
12727 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
12730 * This bit only applies to the VF. If this bit is set, the statistic
12731 * context counters will not be cleared when the statistic context is freed
12732 * or a function reset is called on VF. This bit will be cleared when the PF
12733 * is unloaded or a function reset is called on the PF.
12735 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
12738 * This bit requests that the firmware test to see if all the assets
12739 * requested in this command (i.e. number of TX rings) are available.
12740 * The firmware will return an error if the requested assets are
12741 * not available. The firwmare will NOT reserve the assets if they
12744 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
12747 * This bit requests that the firmware test to see if all the assets
12748 * requested in this command (i.e. number of RX rings) are available.
12749 * The firmware will return an error if the requested assets are
12750 * not available. The firwmare will NOT reserve the assets if they
12753 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
12756 * This bit requests that the firmware test to see if all the assets
12757 * requested in this command (i.e. number of CMPL rings) are available.
12758 * The firmware will return an error if the requested assets are
12759 * not available. The firwmare will NOT reserve the assets if they
12762 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
12765 * This bit requests that the firmware test to see if all the assets
12766 * requested in this command (i.e. number of RSS ctx) are available.
12767 * The firmware will return an error if the requested assets are
12768 * not available. The firwmare will NOT reserve the assets if they
12771 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
12774 * This bit requests that the firmware test to see if all the assets
12775 * requested in this command (i.e. number of ring groups) are available.
12776 * The firmware will return an error if the requested assets are
12777 * not available. The firwmare will NOT reserve the assets if they
12780 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
12783 * This bit requests that the firmware test to see if all the assets
12784 * requested in this command (i.e. number of stat ctx) are available.
12785 * The firmware will return an error if the requested assets are
12786 * not available. The firwmare will NOT reserve the assets if they
12789 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
12792 * This bit requests that the firmware test to see if all the assets
12793 * requested in this command (i.e. number of VNICs) are available.
12794 * The firmware will return an error if the requested assets are
12795 * not available. The firwmare will NOT reserve the assets if they
12798 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
12801 * This bit requests that the firmware test to see if all the assets
12802 * requested in this command (i.e. number of L2 ctx) are available.
12803 * The firmware will return an error if the requested assets are
12804 * not available. The firwmare will NOT reserve the assets if they
12807 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
12810 * This configuration change can be initiated by a PF driver. This
12811 * configuration request shall be targeted to a VF. From local host
12812 * resident HWRM clients, only the parent PF driver shall be allowed
12813 * to initiate this change on one of its children VFs. If this bit is
12814 * set to 1, then the VF that is being configured is requested to be
12817 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
12820 * When this bit it set, even if PF reserved pool size is zero,
12821 * FW will allow driver to create TX rings in ring alloc,
12822 * by reserving TX ring, S3 node dynamically.
12824 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
12827 * This bit requests that the firmware test to see if all the assets
12828 * requested in this command (i.e. number of NQ rings) are available.
12829 * The firmware will return an error if the requested assets are
12830 * not available. The firwmare will NOT reserve the assets if they
12833 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
12836 * This configuration change can be initiated by a PF driver. This
12837 * configuration request shall be targeted to a VF. From local host
12838 * resident HWRM clients, only the parent PF driver shall be allowed
12839 * to initiate this change on one of its children VFs. If this bit is
12840 * set to 1, then the VF that is being configured is requested to be
12843 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
12844 UINT32_C(0x1000000)
12846 * This bit is used by preboot drivers on a PF that require access
12847 * to the legacy L2 ring model and legacy 32b doorbells. This
12848 * feature is not allowed on VFs and is only relevant for devices
12849 * that require a context backing store.
12851 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
12852 UINT32_C(0x2000000)
12854 * If this bit is set to 0, then the interface does not support hot
12855 * reset capability which it advertised with the hot_reset_support
12856 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
12857 * flag to 0, adapter cannot do the hot reset. In this state, if the
12858 * firmware receives a hot reset request, firmware must fail the
12859 * request. If this bit is set to 1, then interface is renabling the
12860 * hot reset capability.
12862 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
12863 UINT32_C(0x4000000)
12865 * If this bit is set to 1, the PF driver is requesting FW
12866 * to enable PPP TX PUSH feature on all the TX rings specified in
12867 * the num_tx_rings field. By default, the PPP TX push feature is
12868 * disabled for all the TX rings of the function. This flag is
12869 * ignored if num_tx_rings field is not specified or the function
12870 * doesn't support PPP tx push feature.
12872 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
12873 UINT32_C(0x8000000)
12875 * If this bit is set to 1, the PF driver is requesting FW
12876 * to disable PPP TX PUSH feature on all the TX rings specified in
12877 * the num_tx_rings field. This flag is ignored if num_tx_rings
12878 * field is not specified or the function doesn't support PPP tx
12881 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
12882 UINT32_C(0x10000000)
12884 * If this bit is set to 1, the driver is requesting FW to enable
12885 * the BD_METADATA feature for this function. The FW returns error
12886 * on this request if the TX_METADATA is enabled for this function.
12888 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
12889 UINT32_C(0x20000000)
12891 * If this bit is set to 1, the driver is requesting FW to disable
12892 * the BD_METADATA feature for this function. The FW returns error
12893 * on this request if the TX_METADATA is enabled for this function.
12895 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
12896 UINT32_C(0x40000000)
12899 * This bit must be '1' for the admin_mtu field to be
12902 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \
12905 * This bit must be '1' for the mru field to be
12908 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
12911 * This bit must be '1' for the num_rsscos_ctxs field to be
12914 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
12917 * This bit must be '1' for the num_cmpl_rings field to be
12920 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
12923 * This bit must be '1' for the num_tx_rings field to be
12926 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
12929 * This bit must be '1' for the num_rx_rings field to be
12932 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
12935 * This bit must be '1' for the num_l2_ctxs field to be
12938 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
12941 * This bit must be '1' for the num_vnics field to be
12944 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
12947 * This bit must be '1' for the num_stat_ctxs field to be
12950 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
12953 * This bit must be '1' for the dflt_mac_addr field to be
12956 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
12959 * This bit must be '1' for the dflt_vlan field to be
12962 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
12965 * This bit must be '1' for the dflt_ip_addr field to be
12968 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
12971 * This bit must be '1' for the min_bw field to be
12974 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
12977 * This bit must be '1' for the max_bw field to be
12980 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
12983 * This bit must be '1' for the async_event_cr field to be
12986 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
12989 * This bit must be '1' for the vlan_antispoof_mode field to be
12992 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
12995 * This bit must be '1' for the allowed_vlan_pris field to be
12998 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
13001 * This bit must be '1' for the evb_mode field to be
13004 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
13007 * This bit must be '1' for the num_mcast_filters field to be
13010 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
13013 * This bit must be '1' for the num_hw_ring_grps field to be
13016 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
13019 * This bit must be '1' for the cache_linesize field to be
13022 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
13025 * This bit must be '1' for the num_msix field to be
13028 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
13031 * This bit must be '1' for the link admin state field to be
13034 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
13037 * This bit must be '1' for the hot_reset_if_en_dis field to be
13040 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
13043 * This bit must be '1' for the schq_id field to be
13046 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
13047 UINT32_C(0x1000000)
13049 * This bit must be '1' for the mpc_chnls field to be
13052 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
13053 UINT32_C(0x2000000)
13055 * This bit must be '1' for the partition_min_bw field to be
13058 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \
13059 UINT32_C(0x4000000)
13061 * This bit must be '1' for the partition_max_bw field to be
13064 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \
13065 UINT32_C(0x8000000)
13067 * This bit must be '1' for the tpid field to be
13068 * configured. This bit is only valid when dflt_vlan enable
13071 #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \
13072 UINT32_C(0x10000000)
13074 * This bit must be '1' for the host_mtu field to be
13077 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \
13078 UINT32_C(0x20000000)
13080 * This field can be used by the admin PF to configure
13081 * mtu of foster PFs.
13082 * The maximum transmission unit of the function.
13083 * The HWRM should make sure that the mtu of
13084 * the function does not exceed the mtu of the physical
13085 * port that this function is associated with.
13087 * In addition to configuring mtu per function, it is
13088 * possible to configure mtu per transmit ring.
13089 * By default, the mtu of each transmit ring associated
13090 * with a function is equal to the mtu of the function.
13091 * The HWRM should make sure that the mtu of each transmit
13092 * ring that is assigned to a function has a valid mtu.
13094 uint16_t admin_mtu;
13096 * The maximum receive unit of the function.
13097 * The HWRM should make sure that the mru of
13098 * the function does not exceed the mru of the physical
13099 * port that this function is associated with.
13101 * In addition to configuring mru per function, it is
13102 * possible to configure mru per vnic.
13103 * By default, the mru of each vnic associated
13104 * with a function is equal to the mru of the function.
13105 * The HWRM should make sure that the mru of each vnic
13106 * that is assigned to a function has a valid mru.
13110 * The number of RSS/COS contexts requested for the
13113 uint16_t num_rsscos_ctxs;
13115 * The number of completion rings requested for the
13116 * function. This does not include the rings allocated
13117 * to any children functions if any.
13119 uint16_t num_cmpl_rings;
13121 * The number of transmit rings requested for the function.
13122 * This does not include the rings allocated to any
13123 * children functions if any.
13125 uint16_t num_tx_rings;
13127 * The number of receive rings requested for the function.
13128 * This does not include the rings allocated
13129 * to any children functions if any.
13131 uint16_t num_rx_rings;
13132 /* The requested number of L2 contexts for the function. */
13133 uint16_t num_l2_ctxs;
13134 /* The requested number of vnics for the function. */
13135 uint16_t num_vnics;
13136 /* The requested number of statistic contexts for the function. */
13137 uint16_t num_stat_ctxs;
13139 * The number of HW ring groups that should
13140 * be reserved for this function.
13142 uint16_t num_hw_ring_grps;
13143 /* The default MAC address for the function being configured. */
13144 uint8_t dflt_mac_addr[6];
13146 * The default VLAN for the function being configured.
13147 * This field's format is same as 802.1Q Tag's
13148 * Tag Control Information (TCI) format that includes both
13149 * Priority Code Point (PCP) and VLAN Identifier (VID).
13151 uint16_t dflt_vlan;
13153 * The default IP address for the function being configured.
13154 * This address is only used in enabling source property check.
13156 uint32_t dflt_ip_addr[4];
13158 * Minimum guaranteed transmit bandwidth for this function. When
13159 * specified for a PF, does not affect traffic from the PF's child VFs.
13160 * A value of 0 indicates the minimum bandwidth is not configured.
13163 /* The bandwidth value. */
13164 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
13165 UINT32_C(0xfffffff)
13166 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
13167 /* The granularity of the value (bits or bytes). */
13168 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
13169 UINT32_C(0x10000000)
13170 /* Value is in bits. */
13171 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
13172 (UINT32_C(0x0) << 28)
13173 /* Value is in bytes. */
13174 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
13175 (UINT32_C(0x1) << 28)
13176 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
13177 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
13178 /* bw_value_unit is 3 b */
13179 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
13180 UINT32_C(0xe0000000)
13181 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
13182 /* Value is in Mb or MB (base 10). */
13183 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
13184 (UINT32_C(0x0) << 29)
13185 /* Value is in Kb or KB (base 10). */
13186 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
13187 (UINT32_C(0x2) << 29)
13188 /* Value is in bits or bytes. */
13189 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
13190 (UINT32_C(0x4) << 29)
13191 /* Value is in Gb or GB (base 10). */
13192 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
13193 (UINT32_C(0x6) << 29)
13194 /* Value is in 1/100th of a percentage of total bandwidth. */
13195 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13196 (UINT32_C(0x1) << 29)
13198 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
13199 (UINT32_C(0x7) << 29)
13200 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
13201 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
13203 * Maximum transmit rate for this function. When specified for a PF,
13204 * does not affect traffic from the PF's child VFs.
13205 * A value of 0 indicates that the maximum bandwidth is not configured.
13208 /* The bandwidth value. */
13209 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
13210 UINT32_C(0xfffffff)
13211 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
13212 /* The granularity of the value (bits or bytes). */
13213 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
13214 UINT32_C(0x10000000)
13215 /* Value is in bits. */
13216 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
13217 (UINT32_C(0x0) << 28)
13218 /* Value is in bytes. */
13219 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
13220 (UINT32_C(0x1) << 28)
13221 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
13222 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
13223 /* bw_value_unit is 3 b */
13224 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
13225 UINT32_C(0xe0000000)
13226 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
13227 /* Value is in Mb or MB (base 10). */
13228 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
13229 (UINT32_C(0x0) << 29)
13230 /* Value is in Kb or KB (base 10). */
13231 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
13232 (UINT32_C(0x2) << 29)
13233 /* Value is in bits or bytes. */
13234 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
13235 (UINT32_C(0x4) << 29)
13236 /* Value is in Gb or GB (base 10). */
13237 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
13238 (UINT32_C(0x6) << 29)
13239 /* Value is in 1/100th of a percentage of total bandwidth. */
13240 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
13241 (UINT32_C(0x1) << 29)
13243 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
13244 (UINT32_C(0x7) << 29)
13245 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
13246 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
13248 * ID of the target completion ring for receiving asynchronous
13249 * event completions. If this field is not valid, then the
13250 * HWRM shall use the default completion ring of the function
13251 * that is being configured as the target completion ring for
13252 * providing any asynchronous event completions for that
13254 * If this field is valid, then the HWRM shall use the
13255 * completion ring identified by this ID as the target
13256 * completion ring for providing any asynchronous event
13257 * completions for the function that is being configured.
13259 uint16_t async_event_cr;
13260 /* VLAN Anti-spoofing mode. */
13261 uint8_t vlan_antispoof_mode;
13262 /* No VLAN anti-spoofing checks are enabled */
13263 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
13265 /* Validate VLAN against the configured VLAN(s) */
13266 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
13268 /* Insert VLAN if it does not exist, otherwise discard */
13269 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
13271 /* Insert VLAN if it does not exist, override VLAN if it exists */
13272 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
13274 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
13275 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
13277 * This bit field defines VLAN PRIs that are allowed on
13279 * If nth bit is set, then VLAN PRI n is allowed on this
13282 uint8_t allowed_vlan_pris;
13284 * The evb_mode is configured on a per port basis. The default evb_mode
13285 * is configured based on the NVM EVB mode setting upon firmware
13286 * initialization. The HWRM allows a PF driver to change EVB mode for a
13287 * port used by the PF only when one of the following conditions is
13289 * 1. The current operating mode is single function mode.
13290 * (ie. one PF per port)
13291 * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
13292 * EVB mode of the port used by the PAXC PF. None of the X86 PFs
13293 * should have privileges.
13294 * The HWRM doesn't permit any PFs to change the underlying EVB mode
13295 * when running as MHB or NPAR mode in performance NIC configuration.
13296 * The HWRM doesn't permit a VF driver to change the EVB mode.
13297 * Once the HWRM determines a function doesn't meet the conditions
13298 * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
13299 * flag in HWRM_FUNC_QCAPS command response for the function.
13300 * The HWRM takes into account the switching of EVB mode from one to
13301 * another and reconfigure hardware resources as reqiured. The
13302 * switching from VEB to VEPA mode requires the disabling of the
13303 * loopback traffic. Additionally, source knockouts are handled
13304 * differently in VEB and VEPA modes.
13307 /* No Edge Virtual Bridging (EVB) */
13308 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
13309 /* Virtual Ethernet Bridge (VEB) */
13310 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
13311 /* Virtual Ethernet Port Aggregator (VEPA) */
13312 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
13313 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
13314 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
13317 * This value indicates the PCIE device cache line size.
13318 * The cache line size allows the DMA writes to terminate and
13319 * start at the cache boundary.
13321 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
13323 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
13324 /* Cache Line Size 64 bytes */
13325 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
13327 /* Cache Line Size 128 bytes */
13328 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
13330 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
13331 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
13332 /* This value is the virtual link admin state setting. */
13333 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
13335 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
13336 /* Admin state is forced down. */
13337 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
13338 (UINT32_C(0x0) << 2)
13339 /* Admin state is forced up. */
13340 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
13341 (UINT32_C(0x1) << 2)
13342 /* Admin state is in auto mode - is to follow the physical link state. */
13343 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
13344 (UINT32_C(0x2) << 2)
13345 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
13346 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
13347 /* Reserved for future. */
13348 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
13350 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
13352 * The number of multicast filters that should
13353 * be reserved for this function on the RX side.
13355 uint16_t num_mcast_filters;
13356 /* Used by a PF driver to associate a SCHQ with a VF. */
13358 uint16_t mpc_chnls;
13360 * When this bit is '1', the caller requests to enable a MPC
13361 * channel with destination to the TX crypto engine block.
13362 * When this bit is ‘0’, this flag has no effect.
13364 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
13366 * When this bit is '1', the caller requests to disable a MPC
13367 * channel with destination to the TX crypto engine block.
13368 * When this bit is ‘0’, this flag has no effect.
13370 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
13372 * When this bit is '1', the caller requests to enable a MPC
13373 * channel with destination to the RX crypto engine block.
13374 * When this bit is ‘0’, this flag has no effect.
13376 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
13378 * When this bit is '1', the caller requests to disable a MPC
13379 * channel with destination to the RX crypto engine block.
13380 * When this bit is ‘0’, this flag has no effect.
13382 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
13384 * When this bit is '1', the caller requests to enable a MPC
13385 * channel with destination to the TX configurable flow processing
13386 * block. When this bit is ‘0’, this flag has no effect.
13388 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
13391 * When this bit is '1', the caller requests to disable a MPC
13392 * channel with destination to the TX configurable flow processing
13393 * block. When this bit is ‘0’, this flag has no effect.
13395 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
13398 * When this bit is '1', the caller requests to enable a MPC
13399 * channel with destination to the RX configurable flow processing
13400 * block. When this bit is ‘0’, this flag has no effect.
13402 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
13405 * When this bit is '1', the caller requests to disable a MPC
13406 * channel with destination to the RX configurable flow processing
13407 * block. When this bit is ‘0’, this flag has no effect.
13409 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
13412 * When this bit is '1', the caller requests to enable a MPC
13413 * channel with destination to the primate processor block.
13414 * When this bit is ‘0’, this flag has no effect.
13416 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
13419 * When this bit is '1', the caller requests to disable a MPC
13420 * channel with destination to the primate processor block.
13421 * When this bit is ‘0’, this flag has no effect.
13423 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
13426 * Minimum guaranteed bandwidth for the network partition made up
13427 * of the caller physical function and all its child virtual
13428 * functions. The rate is specified as a percentage of the bandwidth
13429 * of the link the partition is associated with. A value of 0
13430 * indicates that no minimum bandwidth is configured. The sum of the
13431 * minimum bandwidths for all partitions on a link must not exceed
13433 * The format of this field is defined to match min_bw, even though
13434 * it does not allow all the options for min_bw at this time.
13436 uint32_t partition_min_bw;
13437 /* The bandwidth value. */
13438 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
13439 UINT32_C(0xfffffff)
13440 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
13443 * The granularity of the value (bits or bytes). Firmware ignores
13446 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \
13447 UINT32_C(0x10000000)
13448 /* Value is in bits. */
13449 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \
13450 (UINT32_C(0x0) << 28)
13451 /* Value is in bytes. */
13452 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \
13453 (UINT32_C(0x1) << 28)
13454 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \
13455 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES
13456 /* Bandwidth units. Must be set to percent1_100. */
13457 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
13458 UINT32_C(0xe0000000)
13459 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
13461 /* Value is in hundredths of a percent of link bandwidth. */
13462 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13463 (UINT32_C(0x1) << 29)
13464 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
13465 HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
13467 * The maximum bandwidth that may be used by the network partition
13468 * made up of the caller physical function and all its child virtual
13469 * functions. The rate is specified as a percentage of the bandwidth
13470 * of the link the partition is associated with. A value of 0
13471 * indicates that no maximum bandwidth is configured.
13472 * The format of this field is defined to match max_bw, even though it
13473 * does not allow all the options for max_bw at this time.
13475 uint32_t partition_max_bw;
13476 /* The bandwidth value. */
13477 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
13478 UINT32_C(0xfffffff)
13479 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
13482 * The granularity of the value (bits or bytes). Firmware ignores
13485 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \
13486 UINT32_C(0x10000000)
13487 /* Value is in bits. */
13488 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \
13489 (UINT32_C(0x0) << 28)
13490 /* Value is in bytes. */
13491 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \
13492 (UINT32_C(0x1) << 28)
13493 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \
13494 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES
13495 /* Bandwidth units. Must be set to percent1_100. */
13496 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
13497 UINT32_C(0xe0000000)
13498 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
13500 /* Value is in hundredths of a percent of link bandwidth. */
13501 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
13502 (UINT32_C(0x1) << 29)
13503 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
13504 HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
13506 * The TPID for the function for which default VLAN
13507 * is configured. If the dflt_vlan is not specified
13508 * with the TPID, FW returns error. If the TPID is
13509 * not specified with dflt_vlan, the default TPID of
13510 * 0x8100 will be used. This field is specified in
13511 * network byte order.
13515 * This field can be used by the host PF to configure
13517 * The maximum transmission unit of the function.
13518 * The HWRM should make sure that the mtu of
13519 * the function does not exceed the mtu of the physical
13520 * port that this function is associated with.
13522 * In addition to configuring mtu per function, it is
13523 * possible to configure mtu per transmit ring.
13524 * By default, the mtu of each transmit ring associated
13525 * with a function is equal to the mtu of the function.
13526 * The HWRM should make sure that the mtu of each transmit
13527 * ring that is assigned to a function has a valid mtu.
13532 /* hwrm_func_cfg_output (size:128b/16B) */
13533 struct hwrm_func_cfg_output {
13534 /* The specific error status for the command. */
13535 uint16_t error_code;
13536 /* The HWRM command request type. */
13538 /* The sequence ID from the original command. */
13540 /* The length of the response data in number of bytes. */
13542 uint8_t unused_0[7];
13544 * This field is used in Output records to indicate that the output
13545 * is completely written to RAM. This field should be read as '1'
13546 * to indicate that the output has been completely written.
13547 * When writing a command completion or response to an internal processor,
13548 * the order of writes has to be such that this field is written last.
13553 /********************
13554 * hwrm_func_qstats *
13555 ********************/
13558 /* hwrm_func_qstats_input (size:192b/24B) */
13559 struct hwrm_func_qstats_input {
13560 /* The HWRM command request type. */
13563 * The completion ring to send the completion event on. This should
13564 * be the NQ ID returned from the `nq_alloc` HWRM command.
13566 uint16_t cmpl_ring;
13568 * The sequence ID is used by the driver for tracking multiple
13569 * commands. This ID is treated as opaque data by the firmware and
13570 * the value is returned in the `hwrm_resp_hdr` upon completion.
13574 * The target ID of the command:
13575 * * 0x0-0xFFF8 - The function ID
13576 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13577 * * 0xFFFD - Reserved for user-space HWRM interface
13580 uint16_t target_id;
13582 * A physical address pointer pointing to a host buffer that the
13583 * command's response data will be written. This can be either a host
13584 * physical address (HPA) or a guest physical address (GPA) and must
13585 * point to a physically contiguous block of memory.
13587 uint64_t resp_addr;
13589 * Function ID of the function that is being queried.
13590 * 0xFF... (All Fs) if the query is for the requesting
13592 * A privileged PF can query for other function's statistics.
13595 /* This flags indicates the type of statistics request. */
13597 /* This value is not used to avoid backward compatibility issues. */
13598 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
13600 * flags should be set to 1 when request is for only RoCE statistics.
13601 * This will be honored only if the caller_fid is a privileged PF.
13602 * In all other cases FID and caller_fid should be the same.
13604 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
13606 * flags should be set to 2 when request is for the counter mask,
13607 * representing the width of each of the stats counters, rather
13608 * than counters themselves.
13610 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
13611 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
13612 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
13613 uint8_t unused_0[5];
13616 /* hwrm_func_qstats_output (size:1408b/176B) */
13617 struct hwrm_func_qstats_output {
13618 /* The specific error status for the command. */
13619 uint16_t error_code;
13620 /* The HWRM command request type. */
13622 /* The sequence ID from the original command. */
13624 /* The length of the response data in number of bytes. */
13626 /* Number of transmitted unicast packets on the function. */
13627 uint64_t tx_ucast_pkts;
13628 /* Number of transmitted multicast packets on the function. */
13629 uint64_t tx_mcast_pkts;
13630 /* Number of transmitted broadcast packets on the function. */
13631 uint64_t tx_bcast_pkts;
13633 * Number of transmitted packets that were discarded due to
13634 * internal NIC resource problems. For transmit, this
13635 * can only happen if TMP is configured to allow dropping
13636 * in HOL blocking conditions, which is not a normal
13639 uint64_t tx_discard_pkts;
13641 * Number of dropped packets on transmit path on the function.
13642 * These are packets that have been marked for drop by
13643 * the TE CFA block or are packets that exceeded the
13644 * transmit MTU limit for the function.
13646 uint64_t tx_drop_pkts;
13647 /* Number of transmitted bytes for unicast traffic on the function. */
13648 uint64_t tx_ucast_bytes;
13649 /* Number of transmitted bytes for multicast traffic on the function. */
13650 uint64_t tx_mcast_bytes;
13651 /* Number of transmitted bytes for broadcast traffic on the function. */
13652 uint64_t tx_bcast_bytes;
13653 /* Number of received unicast packets on the function. */
13654 uint64_t rx_ucast_pkts;
13655 /* Number of received multicast packets on the function. */
13656 uint64_t rx_mcast_pkts;
13657 /* Number of received broadcast packets on the function. */
13658 uint64_t rx_bcast_pkts;
13660 * Number of received packets that were discarded on the function
13661 * due to resource limitations. This can happen for 3 reasons.
13662 * # The BD used for the packet has a bad format.
13663 * # There were no BDs available in the ring for the packet.
13664 * # There were no BDs available on-chip for the packet.
13666 uint64_t rx_discard_pkts;
13668 * Number of dropped packets on received path on the function.
13669 * These are packets that have been marked for drop by the
13672 uint64_t rx_drop_pkts;
13673 /* Number of received bytes for unicast traffic on the function. */
13674 uint64_t rx_ucast_bytes;
13675 /* Number of received bytes for multicast traffic on the function. */
13676 uint64_t rx_mcast_bytes;
13677 /* Number of received bytes for broadcast traffic on the function. */
13678 uint64_t rx_bcast_bytes;
13679 /* Number of aggregated unicast packets on the function. */
13680 uint64_t rx_agg_pkts;
13681 /* Number of aggregated unicast bytes on the function. */
13682 uint64_t rx_agg_bytes;
13683 /* Number of aggregation events on the function. */
13684 uint64_t rx_agg_events;
13685 /* Number of aborted aggregations on the function. */
13686 uint64_t rx_agg_aborts;
13687 uint8_t unused_0[7];
13689 * This field is used in Output records to indicate that the output
13690 * is completely written to RAM. This field should be read as '1'
13691 * to indicate that the output has been completely written.
13692 * When writing a command completion or response to an internal processor,
13693 * the order of writes has to be such that this field is written last.
13698 /************************
13699 * hwrm_func_qstats_ext *
13700 ************************/
13703 /* hwrm_func_qstats_ext_input (size:256b/32B) */
13704 struct hwrm_func_qstats_ext_input {
13705 /* The HWRM command request type. */
13708 * The completion ring to send the completion event on. This should
13709 * be the NQ ID returned from the `nq_alloc` HWRM command.
13711 uint16_t cmpl_ring;
13713 * The sequence ID is used by the driver for tracking multiple
13714 * commands. This ID is treated as opaque data by the firmware and
13715 * the value is returned in the `hwrm_resp_hdr` upon completion.
13719 * The target ID of the command:
13720 * * 0x0-0xFFF8 - The function ID
13721 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13722 * * 0xFFFD - Reserved for user-space HWRM interface
13725 uint16_t target_id;
13727 * A physical address pointer pointing to a host buffer that the
13728 * command's response data will be written. This can be either a host
13729 * physical address (HPA) or a guest physical address (GPA) and must
13730 * point to a physically contiguous block of memory.
13732 uint64_t resp_addr;
13734 * Function ID of the function that is being queried.
13735 * 0xFF... (All Fs) if the query is for the requesting
13737 * A privileged PF can query for other function's statistics.
13740 /* This flags indicates the type of statistics request. */
13742 /* This value is not used to avoid backward compatibility issues. */
13743 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
13745 * flags should be set to 1 when request is for only RoCE statistics.
13746 * This will be honored only if the caller_fid is a privileged PF.
13747 * In all other cases FID and caller_fid should be the same.
13749 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
13751 * flags should be set to 2 when request is for the counter mask
13752 * representing the width of each of the stats counters, rather
13753 * than counters themselves.
13755 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
13756 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
13757 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
13758 uint8_t unused_0[1];
13761 * This bit must be '1' for the schq_id and traffic_class fields to
13764 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
13765 /* Specifies the SCHQ for which to gather statistics */
13768 * Specifies the traffic class for which to gather statistics. Valid
13769 * values are 0 through (max_configurable_queues - 1), where
13770 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
13772 uint16_t traffic_class;
13773 uint8_t unused_1[4];
13776 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
13777 struct hwrm_func_qstats_ext_output {
13778 /* The specific error status for the command. */
13779 uint16_t error_code;
13780 /* The HWRM command request type. */
13782 /* The sequence ID from the original command. */
13784 /* The length of the response data in number of bytes. */
13786 /* Number of received unicast packets */
13787 uint64_t rx_ucast_pkts;
13788 /* Number of received multicast packets */
13789 uint64_t rx_mcast_pkts;
13790 /* Number of received broadcast packets */
13791 uint64_t rx_bcast_pkts;
13792 /* Number of discarded packets on received path */
13793 uint64_t rx_discard_pkts;
13794 /* Number of packets on receive path with error */
13795 uint64_t rx_error_pkts;
13796 /* Number of received bytes for unicast traffic */
13797 uint64_t rx_ucast_bytes;
13798 /* Number of received bytes for multicast traffic */
13799 uint64_t rx_mcast_bytes;
13800 /* Number of received bytes for broadcast traffic */
13801 uint64_t rx_bcast_bytes;
13802 /* Number of transmitted unicast packets */
13803 uint64_t tx_ucast_pkts;
13804 /* Number of transmitted multicast packets */
13805 uint64_t tx_mcast_pkts;
13806 /* Number of transmitted broadcast packets */
13807 uint64_t tx_bcast_pkts;
13808 /* Number of packets on transmit path with error */
13809 uint64_t tx_error_pkts;
13810 /* Number of discarded packets on transmit path */
13811 uint64_t tx_discard_pkts;
13812 /* Number of transmitted bytes for unicast traffic */
13813 uint64_t tx_ucast_bytes;
13814 /* Number of transmitted bytes for multicast traffic */
13815 uint64_t tx_mcast_bytes;
13816 /* Number of transmitted bytes for broadcast traffic */
13817 uint64_t tx_bcast_bytes;
13818 /* Number of TPA eligible packets */
13819 uint64_t rx_tpa_eligible_pkt;
13820 /* Number of TPA eligible bytes */
13821 uint64_t rx_tpa_eligible_bytes;
13822 /* Number of TPA packets */
13823 uint64_t rx_tpa_pkt;
13824 /* Number of TPA bytes */
13825 uint64_t rx_tpa_bytes;
13826 /* Number of TPA errors */
13827 uint64_t rx_tpa_errors;
13828 /* Number of TPA errors */
13829 uint64_t rx_tpa_events;
13830 uint8_t unused_0[7];
13832 * This field is used in Output records to indicate that the output
13833 * is completely written to RAM. This field should be read as '1'
13834 * to indicate that the output has been completely written.
13835 * When writing a command completion or response to an internal processor,
13836 * the order of writes has to be such that this field is written last.
13841 /***********************
13842 * hwrm_func_clr_stats *
13843 ***********************/
13846 /* hwrm_func_clr_stats_input (size:192b/24B) */
13847 struct hwrm_func_clr_stats_input {
13848 /* The HWRM command request type. */
13851 * The completion ring to send the completion event on. This should
13852 * be the NQ ID returned from the `nq_alloc` HWRM command.
13854 uint16_t cmpl_ring;
13856 * The sequence ID is used by the driver for tracking multiple
13857 * commands. This ID is treated as opaque data by the firmware and
13858 * the value is returned in the `hwrm_resp_hdr` upon completion.
13862 * The target ID of the command:
13863 * * 0x0-0xFFF8 - The function ID
13864 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13865 * * 0xFFFD - Reserved for user-space HWRM interface
13868 uint16_t target_id;
13870 * A physical address pointer pointing to a host buffer that the
13871 * command's response data will be written. This can be either a host
13872 * physical address (HPA) or a guest physical address (GPA) and must
13873 * point to a physically contiguous block of memory.
13875 uint64_t resp_addr;
13877 * Function ID of the function.
13878 * 0xFF... (All Fs) if the query is for the requesting
13882 uint8_t unused_0[6];
13885 /* hwrm_func_clr_stats_output (size:128b/16B) */
13886 struct hwrm_func_clr_stats_output {
13887 /* The specific error status for the command. */
13888 uint16_t error_code;
13889 /* The HWRM command request type. */
13891 /* The sequence ID from the original command. */
13893 /* The length of the response data in number of bytes. */
13895 uint8_t unused_0[7];
13897 * This field is used in Output records to indicate that the output
13898 * is completely written to RAM. This field should be read as '1'
13899 * to indicate that the output has been completely written.
13900 * When writing a command completion or response to an internal processor,
13901 * the order of writes has to be such that this field is written last.
13906 /**************************
13907 * hwrm_func_vf_resc_free *
13908 **************************/
13911 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
13912 struct hwrm_func_vf_resc_free_input {
13913 /* The HWRM command request type. */
13916 * The completion ring to send the completion event on. This should
13917 * be the NQ ID returned from the `nq_alloc` HWRM command.
13919 uint16_t cmpl_ring;
13921 * The sequence ID is used by the driver for tracking multiple
13922 * commands. This ID is treated as opaque data by the firmware and
13923 * the value is returned in the `hwrm_resp_hdr` upon completion.
13927 * The target ID of the command:
13928 * * 0x0-0xFFF8 - The function ID
13929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13930 * * 0xFFFD - Reserved for user-space HWRM interface
13933 uint16_t target_id;
13935 * A physical address pointer pointing to a host buffer that the
13936 * command's response data will be written. This can be either a host
13937 * physical address (HPA) or a guest physical address (GPA) and must
13938 * point to a physically contiguous block of memory.
13940 uint64_t resp_addr;
13942 * This value is used to identify a Virtual Function (VF).
13943 * The scope of VF ID is local within a PF.
13946 uint8_t unused_0[6];
13949 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
13950 struct hwrm_func_vf_resc_free_output {
13951 /* The specific error status for the command. */
13952 uint16_t error_code;
13953 /* The HWRM command request type. */
13955 /* The sequence ID from the original command. */
13957 /* The length of the response data in number of bytes. */
13959 uint8_t unused_0[7];
13961 * This field is used in Output records to indicate that the output
13962 * is completely written to RAM. This field should be read as '1'
13963 * to indicate that the output has been completely written.
13964 * When writing a command completion or response to an internal processor,
13965 * the order of writes has to be such that this field is written last.
13970 /**********************
13971 * hwrm_func_drv_rgtr *
13972 **********************/
13975 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
13976 struct hwrm_func_drv_rgtr_input {
13977 /* The HWRM command request type. */
13980 * The completion ring to send the completion event on. This should
13981 * be the NQ ID returned from the `nq_alloc` HWRM command.
13983 uint16_t cmpl_ring;
13985 * The sequence ID is used by the driver for tracking multiple
13986 * commands. This ID is treated as opaque data by the firmware and
13987 * the value is returned in the `hwrm_resp_hdr` upon completion.
13991 * The target ID of the command:
13992 * * 0x0-0xFFF8 - The function ID
13993 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13994 * * 0xFFFD - Reserved for user-space HWRM interface
13997 uint16_t target_id;
13999 * A physical address pointer pointing to a host buffer that the
14000 * command's response data will be written. This can be either a host
14001 * physical address (HPA) or a guest physical address (GPA) and must
14002 * point to a physically contiguous block of memory.
14004 uint64_t resp_addr;
14007 * When this bit is '1', the function driver is requesting
14008 * all requests from its children VF drivers to be
14009 * forwarded to itself.
14010 * This flag can only be set by the PF driver.
14011 * If a VF driver sets this flag, it should be ignored
14014 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
14017 * When this bit is '1', the function is requesting none of
14018 * the requests from its children VF drivers to be
14019 * forwarded to itself.
14020 * This flag can only be set by the PF driver.
14021 * If a VF driver sets this flag, it should be ignored
14024 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
14027 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
14028 * fields shall be ignored and ver_maj, ver_min, ver_upd
14029 * and ver_patch shall be used for the driver version information.
14030 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
14031 * fields shall be used for the driver version information and
14032 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
14034 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
14037 * When this bit is '1', the function is indicating support of
14038 * 64bit flow handle. The firmware that only supports 64bit flow
14039 * handle should check this bit before allowing processing of
14040 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
14041 * with 64bit flow handle support can only be compatible with drivers
14042 * that support 64bit flow handle. The legacy drivers that don't support
14043 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
14044 * running with new firmware that only supports 64bit flow handle. The new
14045 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
14046 * status to the legacy driver when encounters these commands.
14048 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
14051 * When this bit is '1', the function is indicating support of
14052 * Hot Reset. The driver interface will destroy the resources,
14053 * unregister the function and register again up on receiving
14054 * the RESET_NOTIFY Async notification from the core firmware.
14055 * The core firmware will this use flag and trigger the Hot Reset
14056 * process only if all the registered driver instances are capable
14059 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
14062 * When this bit is 1, the function is indicating the support of the
14063 * error recovery capability. Error recovery support will be used by
14064 * firmware only if all the driver instances support error recovery
14065 * process. By setting this bit, driver is indicating support for
14066 * corresponding async event completion message. These will be
14067 * delivered to the driver even if they did not register for it.
14068 * If supported, after receiving reset notify async event with fatal
14069 * flag set in event data1, then all the drivers have to tear down
14070 * their resources without sending any HWRM commands to FW.
14072 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
14075 * When this bit is 1, the function is indicating the support of the
14076 * Master capability. The Firmware will use this capability to select the
14077 * Master function. The master function will be used to initiate
14078 * designated functionality like error recovery etc… If none of the
14079 * registered PF’s or trusted VF’s indicate this support, then
14080 * firmware will select the 1st registered PF as Master capable instance.
14082 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
14085 * When this bit is 1, the function is indicating the support of the
14086 * fast reset capability. Fast reset support will be used by
14087 * firmware only if all the driver instances support fast reset
14088 * process. By setting this bit, driver is indicating support for
14089 * corresponding async event completion message. These will be
14090 * delivered to the driver even if they did not register for it.
14091 * If supported, after receiving reset notify async event with fast
14092 * reset flag set in event data1, then all the drivers have to tear
14093 * down their resources without sending any HWRM commands to FW.
14095 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
14098 * When this bit is 1, the function's driver is indicating the
14099 * support of handling the vnic_rss_cfg's INVALID_PARAM error
14100 * returned by firmware. Firmware returns error, if host driver
14101 * configures the invalid hash_types bit combination for a given
14104 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \
14108 * This bit must be '1' for the os_type field to be
14111 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
14114 * This bit must be '1' for the ver field to be
14117 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
14120 * This bit must be '1' for the timestamp field to be
14123 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
14126 * This bit must be '1' for the vf_req_fwd field to be
14129 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
14132 * This bit must be '1' for the async_event_fwd field to be
14135 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
14137 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
14140 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
14141 /* Other OS not listed below. */
14142 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
14144 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
14146 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
14148 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
14150 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
14152 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
14153 /* VMware ESXi OS. */
14154 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
14155 /* Microsoft Windows 8 64-bit OS. */
14156 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
14157 /* Microsoft Windows Server 2012 R2 OS. */
14158 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
14160 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
14161 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
14162 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
14163 /* This is the 8bit major version of the driver. */
14164 uint8_t ver_maj_8b;
14165 /* This is the 8bit minor version of the driver. */
14166 uint8_t ver_min_8b;
14167 /* This is the 8bit update version of the driver. */
14168 uint8_t ver_upd_8b;
14169 uint8_t unused_0[3];
14171 * This is a 32-bit timestamp provided by the driver for
14173 * The timestamp is in multiples of 1ms.
14175 uint32_t timestamp;
14176 uint8_t unused_1[4];
14178 * This is a 256-bit bit mask provided by the PF driver for
14179 * letting the HWRM know what commands issued by the VF driver
14180 * to the HWRM should be forwarded to the PF driver.
14181 * Nth bit refers to the Nth req_type.
14183 * Setting Nth bit to 1 indicates that requests from the
14184 * VF driver with req_type equal to N shall be forwarded to
14185 * the parent PF driver.
14187 * This field is not valid for the VF driver.
14189 uint32_t vf_req_fwd[8];
14191 * This is a 256-bit bit mask provided by the function driver
14192 * (PF or VF driver) to indicate the list of asynchronous event
14193 * completions to be forwarded.
14195 * Nth bit refers to the Nth event_id.
14197 * Setting Nth bit to 1 by the function driver shall result in
14198 * the HWRM forwarding asynchronous event completion with
14199 * event_id equal to N.
14201 * If all bits are set to 0 (value of 0), then the HWRM shall
14202 * not forward any asynchronous event completion to this
14205 uint32_t async_event_fwd[8];
14206 /* This is the 16bit major version of the driver. */
14208 /* This is the 16bit minor version of the driver. */
14210 /* This is the 16bit update version of the driver. */
14212 /* This is the 16bit patch version of the driver. */
14213 uint16_t ver_patch;
14216 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
14217 struct hwrm_func_drv_rgtr_output {
14218 /* The specific error status for the command. */
14219 uint16_t error_code;
14220 /* The HWRM command request type. */
14222 /* The sequence ID from the original command. */
14224 /* The length of the response data in number of bytes. */
14228 * When this bit is '1', it indicates that the
14229 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
14231 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
14233 uint8_t unused_0[3];
14235 * This field is used in Output records to indicate that the output
14236 * is completely written to RAM. This field should be read as '1'
14237 * to indicate that the output has been completely written.
14238 * When writing a command completion or response to an internal processor,
14239 * the order of writes has to be such that this field is written last.
14244 /************************
14245 * hwrm_func_drv_unrgtr *
14246 ************************/
14249 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
14250 struct hwrm_func_drv_unrgtr_input {
14251 /* The HWRM command request type. */
14254 * The completion ring to send the completion event on. This should
14255 * be the NQ ID returned from the `nq_alloc` HWRM command.
14257 uint16_t cmpl_ring;
14259 * The sequence ID is used by the driver for tracking multiple
14260 * commands. This ID is treated as opaque data by the firmware and
14261 * the value is returned in the `hwrm_resp_hdr` upon completion.
14265 * The target ID of the command:
14266 * * 0x0-0xFFF8 - The function ID
14267 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14268 * * 0xFFFD - Reserved for user-space HWRM interface
14271 uint16_t target_id;
14273 * A physical address pointer pointing to a host buffer that the
14274 * command's response data will be written. This can be either a host
14275 * physical address (HPA) or a guest physical address (GPA) and must
14276 * point to a physically contiguous block of memory.
14278 uint64_t resp_addr;
14281 * When this bit is '1', the function driver is notifying
14282 * the HWRM to prepare for the shutdown.
14284 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
14286 uint8_t unused_0[4];
14289 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
14290 struct hwrm_func_drv_unrgtr_output {
14291 /* The specific error status for the command. */
14292 uint16_t error_code;
14293 /* The HWRM command request type. */
14295 /* The sequence ID from the original command. */
14297 /* The length of the response data in number of bytes. */
14299 uint8_t unused_0[7];
14301 * This field is used in Output records to indicate that the output
14302 * is completely written to RAM. This field should be read as '1'
14303 * to indicate that the output has been completely written.
14304 * When writing a command completion or response to an internal processor,
14305 * the order of writes has to be such that this field is written last.
14310 /**********************
14311 * hwrm_func_buf_rgtr *
14312 **********************/
14315 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
14316 struct hwrm_func_buf_rgtr_input {
14317 /* The HWRM command request type. */
14320 * The completion ring to send the completion event on. This should
14321 * be the NQ ID returned from the `nq_alloc` HWRM command.
14323 uint16_t cmpl_ring;
14325 * The sequence ID is used by the driver for tracking multiple
14326 * commands. This ID is treated as opaque data by the firmware and
14327 * the value is returned in the `hwrm_resp_hdr` upon completion.
14331 * The target ID of the command:
14332 * * 0x0-0xFFF8 - The function ID
14333 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14334 * * 0xFFFD - Reserved for user-space HWRM interface
14337 uint16_t target_id;
14339 * A physical address pointer pointing to a host buffer that the
14340 * command's response data will be written. This can be either a host
14341 * physical address (HPA) or a guest physical address (GPA) and must
14342 * point to a physically contiguous block of memory.
14344 uint64_t resp_addr;
14347 * This bit must be '1' for the vf_id field to be
14350 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
14352 * This bit must be '1' for the err_buf_addr field to be
14355 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
14357 * This value is used to identify a Virtual Function (VF).
14358 * The scope of VF ID is local within a PF.
14362 * This field represents the number of pages used for request
14365 uint16_t req_buf_num_pages;
14367 * This field represents the page size used for request
14370 uint16_t req_buf_page_size;
14372 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
14374 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
14376 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
14378 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
14380 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
14382 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
14384 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
14385 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
14386 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
14387 /* The length of the request buffer per VF in bytes. */
14388 uint16_t req_buf_len;
14389 /* The length of the response buffer in bytes. */
14390 uint16_t resp_buf_len;
14391 uint8_t unused_0[2];
14392 /* This field represents the page address of page #0. */
14393 uint64_t req_buf_page_addr0;
14394 /* This field represents the page address of page #1. */
14395 uint64_t req_buf_page_addr1;
14396 /* This field represents the page address of page #2. */
14397 uint64_t req_buf_page_addr2;
14398 /* This field represents the page address of page #3. */
14399 uint64_t req_buf_page_addr3;
14400 /* This field represents the page address of page #4. */
14401 uint64_t req_buf_page_addr4;
14402 /* This field represents the page address of page #5. */
14403 uint64_t req_buf_page_addr5;
14404 /* This field represents the page address of page #6. */
14405 uint64_t req_buf_page_addr6;
14406 /* This field represents the page address of page #7. */
14407 uint64_t req_buf_page_addr7;
14408 /* This field represents the page address of page #8. */
14409 uint64_t req_buf_page_addr8;
14410 /* This field represents the page address of page #9. */
14411 uint64_t req_buf_page_addr9;
14413 * This field is used to receive the error reporting from
14414 * the chipset. Only applicable for PFs.
14416 uint64_t error_buf_addr;
14418 * This field is used to receive the response forwarded by the
14421 uint64_t resp_buf_addr;
14424 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
14425 struct hwrm_func_buf_rgtr_output {
14426 /* The specific error status for the command. */
14427 uint16_t error_code;
14428 /* The HWRM command request type. */
14430 /* The sequence ID from the original command. */
14432 /* The length of the response data in number of bytes. */
14434 uint8_t unused_0[7];
14436 * This field is used in Output records to indicate that the output
14437 * is completely written to RAM. This field should be read as '1'
14438 * to indicate that the output has been completely written.
14439 * When writing a command completion or response to an internal processor,
14440 * the order of writes has to be such that this field is written last.
14445 /************************
14446 * hwrm_func_buf_unrgtr *
14447 ************************/
14450 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
14451 struct hwrm_func_buf_unrgtr_input {
14452 /* The HWRM command request type. */
14455 * The completion ring to send the completion event on. This should
14456 * be the NQ ID returned from the `nq_alloc` HWRM command.
14458 uint16_t cmpl_ring;
14460 * The sequence ID is used by the driver for tracking multiple
14461 * commands. This ID is treated as opaque data by the firmware and
14462 * the value is returned in the `hwrm_resp_hdr` upon completion.
14466 * The target ID of the command:
14467 * * 0x0-0xFFF8 - The function ID
14468 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14469 * * 0xFFFD - Reserved for user-space HWRM interface
14472 uint16_t target_id;
14474 * A physical address pointer pointing to a host buffer that the
14475 * command's response data will be written. This can be either a host
14476 * physical address (HPA) or a guest physical address (GPA) and must
14477 * point to a physically contiguous block of memory.
14479 uint64_t resp_addr;
14482 * This bit must be '1' for the vf_id field to be
14485 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
14487 * This value is used to identify a Virtual Function (VF).
14488 * The scope of VF ID is local within a PF.
14491 uint8_t unused_0[2];
14494 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
14495 struct hwrm_func_buf_unrgtr_output {
14496 /* The specific error status for the command. */
14497 uint16_t error_code;
14498 /* The HWRM command request type. */
14500 /* The sequence ID from the original command. */
14502 /* The length of the response data in number of bytes. */
14504 uint8_t unused_0[7];
14506 * This field is used in Output records to indicate that the output
14507 * is completely written to RAM. This field should be read as '1'
14508 * to indicate that the output has been completely written.
14509 * When writing a command completion or response to an internal processor,
14510 * the order of writes has to be such that this field is written last.
14515 /**********************
14516 * hwrm_func_drv_qver *
14517 **********************/
14520 /* hwrm_func_drv_qver_input (size:192b/24B) */
14521 struct hwrm_func_drv_qver_input {
14522 /* The HWRM command request type. */
14525 * The completion ring to send the completion event on. This should
14526 * be the NQ ID returned from the `nq_alloc` HWRM command.
14528 uint16_t cmpl_ring;
14530 * The sequence ID is used by the driver for tracking multiple
14531 * commands. This ID is treated as opaque data by the firmware and
14532 * the value is returned in the `hwrm_resp_hdr` upon completion.
14536 * The target ID of the command:
14537 * * 0x0-0xFFF8 - The function ID
14538 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14539 * * 0xFFFD - Reserved for user-space HWRM interface
14542 uint16_t target_id;
14544 * A physical address pointer pointing to a host buffer that the
14545 * command's response data will be written. This can be either a host
14546 * physical address (HPA) or a guest physical address (GPA) and must
14547 * point to a physically contiguous block of memory.
14549 uint64_t resp_addr;
14550 /* Reserved for future use. */
14553 * Function ID of the function that is being queried.
14554 * 0xFF... (All Fs) if the query is for the requesting
14558 uint8_t unused_0[2];
14561 /* hwrm_func_drv_qver_output (size:256b/32B) */
14562 struct hwrm_func_drv_qver_output {
14563 /* The specific error status for the command. */
14564 uint16_t error_code;
14565 /* The HWRM command request type. */
14567 /* The sequence ID from the original command. */
14569 /* The length of the response data in number of bytes. */
14571 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
14574 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
14575 /* Other OS not listed below. */
14576 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
14578 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
14580 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
14582 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
14584 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
14586 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
14587 /* VMware ESXi OS. */
14588 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
14589 /* Microsoft Windows 8 64-bit OS. */
14590 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
14591 /* Microsoft Windows Server 2012 R2 OS. */
14592 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
14594 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
14595 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
14596 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
14597 /* This is the 8bit major version of the driver. */
14598 uint8_t ver_maj_8b;
14599 /* This is the 8bit minor version of the driver. */
14600 uint8_t ver_min_8b;
14601 /* This is the 8bit update version of the driver. */
14602 uint8_t ver_upd_8b;
14603 uint8_t unused_0[3];
14604 /* This is the 16bit major version of the driver. */
14606 /* This is the 16bit minor version of the driver. */
14608 /* This is the 16bit update version of the driver. */
14610 /* This is the 16bit patch version of the driver. */
14611 uint16_t ver_patch;
14612 uint8_t unused_1[7];
14614 * This field is used in Output records to indicate that the output
14615 * is completely written to RAM. This field should be read as '1'
14616 * to indicate that the output has been completely written.
14617 * When writing a command completion or response to an internal processor,
14618 * the order of writes has to be such that this field is written last.
14623 /****************************
14624 * hwrm_func_resource_qcaps *
14625 ****************************/
14628 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
14629 struct hwrm_func_resource_qcaps_input {
14630 /* The HWRM command request type. */
14633 * The completion ring to send the completion event on. This should
14634 * be the NQ ID returned from the `nq_alloc` HWRM command.
14636 uint16_t cmpl_ring;
14638 * The sequence ID is used by the driver for tracking multiple
14639 * commands. This ID is treated as opaque data by the firmware and
14640 * the value is returned in the `hwrm_resp_hdr` upon completion.
14644 * The target ID of the command:
14645 * * 0x0-0xFFF8 - The function ID
14646 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14647 * * 0xFFFD - Reserved for user-space HWRM interface
14650 uint16_t target_id;
14652 * A physical address pointer pointing to a host buffer that the
14653 * command's response data will be written. This can be either a host
14654 * physical address (HPA) or a guest physical address (GPA) and must
14655 * point to a physically contiguous block of memory.
14657 uint64_t resp_addr;
14659 * Function ID of the function that is being queried.
14660 * 0xFF... (All Fs) if the query is for the requesting
14664 uint8_t unused_0[6];
14667 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
14668 struct hwrm_func_resource_qcaps_output {
14669 /* The specific error status for the command. */
14670 uint16_t error_code;
14671 /* The HWRM command request type. */
14673 /* The sequence ID from the original command. */
14675 /* The length of the response data in number of bytes. */
14677 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
14679 /* Maximum guaranteed number of MSI-X vectors supported by function */
14681 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
14682 uint16_t vf_reservation_strategy;
14683 /* The PF driver should evenly divide its remaining resources among all VFs. */
14684 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
14686 /* The PF driver should only reserve minimal resources for each VF. */
14687 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
14690 * The PF driver should not reserve any resources for each VF until the
14691 * the VF interface is brought up.
14693 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
14695 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
14696 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
14697 /* Minimum guaranteed number of RSS/COS contexts */
14698 uint16_t min_rsscos_ctx;
14699 /* Maximum non-guaranteed number of RSS/COS contexts */
14700 uint16_t max_rsscos_ctx;
14701 /* Minimum guaranteed number of completion rings */
14702 uint16_t min_cmpl_rings;
14703 /* Maximum non-guaranteed number of completion rings */
14704 uint16_t max_cmpl_rings;
14705 /* Minimum guaranteed number of transmit rings */
14706 uint16_t min_tx_rings;
14707 /* Maximum non-guaranteed number of transmit rings */
14708 uint16_t max_tx_rings;
14709 /* Minimum guaranteed number of receive rings */
14710 uint16_t min_rx_rings;
14711 /* Maximum non-guaranteed number of receive rings */
14712 uint16_t max_rx_rings;
14713 /* Minimum guaranteed number of L2 contexts */
14714 uint16_t min_l2_ctxs;
14715 /* Maximum non-guaranteed number of L2 contexts */
14716 uint16_t max_l2_ctxs;
14717 /* Minimum guaranteed number of VNICs */
14718 uint16_t min_vnics;
14719 /* Maximum non-guaranteed number of VNICs */
14720 uint16_t max_vnics;
14721 /* Minimum guaranteed number of statistic contexts */
14722 uint16_t min_stat_ctx;
14723 /* Maximum non-guaranteed number of statistic contexts */
14724 uint16_t max_stat_ctx;
14725 /* Minimum guaranteed number of ring groups */
14726 uint16_t min_hw_ring_grps;
14727 /* Maximum non-guaranteed number of ring groups */
14728 uint16_t max_hw_ring_grps;
14730 * Maximum number of inputs into the transmit scheduler for this function.
14731 * The number of TX rings assigned to the function cannot exceed this value.
14733 uint16_t max_tx_scheduler_inputs;
14736 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
14737 * feature to reserve all minimum resources when minimum >= 1, otherwise
14738 * returns an error.
14740 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
14742 uint8_t unused_0[5];
14744 * This field is used in Output records to indicate that the output
14745 * is completely written to RAM. This field should be read as '1'
14746 * to indicate that the output has been completely written.
14747 * When writing a command completion or response to an internal processor,
14748 * the order of writes has to be such that this field is written last.
14753 /*****************************
14754 * hwrm_func_vf_resource_cfg *
14755 *****************************/
14758 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
14759 struct hwrm_func_vf_resource_cfg_input {
14760 /* The HWRM command request type. */
14763 * The completion ring to send the completion event on. This should
14764 * be the NQ ID returned from the `nq_alloc` HWRM command.
14766 uint16_t cmpl_ring;
14768 * The sequence ID is used by the driver for tracking multiple
14769 * commands. This ID is treated as opaque data by the firmware and
14770 * the value is returned in the `hwrm_resp_hdr` upon completion.
14774 * The target ID of the command:
14775 * * 0x0-0xFFF8 - The function ID
14776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14777 * * 0xFFFD - Reserved for user-space HWRM interface
14780 uint16_t target_id;
14782 * A physical address pointer pointing to a host buffer that the
14783 * command's response data will be written. This can be either a host
14784 * physical address (HPA) or a guest physical address (GPA) and must
14785 * point to a physically contiguous block of memory.
14787 uint64_t resp_addr;
14788 /* VF ID that is being configured by PF */
14790 /* Maximum guaranteed number of MSI-X vectors for the function */
14792 /* Minimum guaranteed number of RSS/COS contexts */
14793 uint16_t min_rsscos_ctx;
14794 /* Maximum non-guaranteed number of RSS/COS contexts */
14795 uint16_t max_rsscos_ctx;
14796 /* Minimum guaranteed number of completion rings */
14797 uint16_t min_cmpl_rings;
14798 /* Maximum non-guaranteed number of completion rings */
14799 uint16_t max_cmpl_rings;
14800 /* Minimum guaranteed number of transmit rings */
14801 uint16_t min_tx_rings;
14802 /* Maximum non-guaranteed number of transmit rings */
14803 uint16_t max_tx_rings;
14804 /* Minimum guaranteed number of receive rings */
14805 uint16_t min_rx_rings;
14806 /* Maximum non-guaranteed number of receive rings */
14807 uint16_t max_rx_rings;
14808 /* Minimum guaranteed number of L2 contexts */
14809 uint16_t min_l2_ctxs;
14810 /* Maximum non-guaranteed number of L2 contexts */
14811 uint16_t max_l2_ctxs;
14812 /* Minimum guaranteed number of VNICs */
14813 uint16_t min_vnics;
14814 /* Maximum non-guaranteed number of VNICs */
14815 uint16_t max_vnics;
14816 /* Minimum guaranteed number of statistic contexts */
14817 uint16_t min_stat_ctx;
14818 /* Maximum non-guaranteed number of statistic contexts */
14819 uint16_t max_stat_ctx;
14820 /* Minimum guaranteed number of ring groups */
14821 uint16_t min_hw_ring_grps;
14822 /* Maximum non-guaranteed number of ring groups */
14823 uint16_t max_hw_ring_grps;
14826 * If this bit is set, all minimum resources requested should be
14827 * reserved if minimum >= 1, otherwise return error. In case of
14828 * error, keep all existing reservations before the call.
14830 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
14832 uint8_t unused_0[2];
14835 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
14836 struct hwrm_func_vf_resource_cfg_output {
14837 /* The specific error status for the command. */
14838 uint16_t error_code;
14839 /* The HWRM command request type. */
14841 /* The sequence ID from the original command. */
14843 /* The length of the response data in number of bytes. */
14845 /* Reserved number of RSS/COS contexts */
14846 uint16_t reserved_rsscos_ctx;
14847 /* Reserved number of completion rings */
14848 uint16_t reserved_cmpl_rings;
14849 /* Reserved number of transmit rings */
14850 uint16_t reserved_tx_rings;
14851 /* Reserved number of receive rings */
14852 uint16_t reserved_rx_rings;
14853 /* Reserved number of L2 contexts */
14854 uint16_t reserved_l2_ctxs;
14855 /* Reserved number of VNICs */
14856 uint16_t reserved_vnics;
14857 /* Reserved number of statistic contexts */
14858 uint16_t reserved_stat_ctx;
14859 /* Reserved number of ring groups */
14860 uint16_t reserved_hw_ring_grps;
14861 uint8_t unused_0[7];
14863 * This field is used in Output records to indicate that the output
14864 * is completely written to RAM. This field should be read as '1'
14865 * to indicate that the output has been completely written.
14866 * When writing a command completion or response to an internal processor,
14867 * the order of writes has to be such that this field is written last.
14872 /*********************************
14873 * hwrm_func_backing_store_qcaps *
14874 *********************************/
14877 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
14878 struct hwrm_func_backing_store_qcaps_input {
14879 /* The HWRM command request type. */
14882 * The completion ring to send the completion event on. This should
14883 * be the NQ ID returned from the `nq_alloc` HWRM command.
14885 uint16_t cmpl_ring;
14887 * The sequence ID is used by the driver for tracking multiple
14888 * commands. This ID is treated as opaque data by the firmware and
14889 * the value is returned in the `hwrm_resp_hdr` upon completion.
14893 * The target ID of the command:
14894 * * 0x0-0xFFF8 - The function ID
14895 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14896 * * 0xFFFD - Reserved for user-space HWRM interface
14899 uint16_t target_id;
14901 * A physical address pointer pointing to a host buffer that the
14902 * command's response data will be written. This can be either a host
14903 * physical address (HPA) or a guest physical address (GPA) and must
14904 * point to a physically contiguous block of memory.
14906 uint64_t resp_addr;
14909 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
14910 struct hwrm_func_backing_store_qcaps_output {
14911 /* The specific error status for the command. */
14912 uint16_t error_code;
14913 /* The HWRM command request type. */
14915 /* The sequence ID from the original command. */
14917 /* The length of the response data in number of bytes. */
14919 /* Maximum number of QP context entries supported for this function. */
14920 uint32_t qp_max_entries;
14922 * Minimum number of QP context entries that are needed to be reserved
14923 * for QP1 for the PF and its VFs. PF drivers must allocate at least
14924 * this many QP context entries, even if RoCE will not be used.
14926 uint16_t qp_min_qp1_entries;
14927 /* Maximum number of QP context entries that can be used for L2. */
14928 uint16_t qp_max_l2_entries;
14929 /* Number of bytes that must be allocated for each context entry. */
14930 uint16_t qp_entry_size;
14931 /* Maximum number of SRQ context entries that can be used for L2. */
14932 uint16_t srq_max_l2_entries;
14933 /* Maximum number of SRQ context entries supported for this function. */
14934 uint32_t srq_max_entries;
14935 /* Number of bytes that must be allocated for each context entry. */
14936 uint16_t srq_entry_size;
14937 /* Maximum number of CQ context entries that can be used for L2. */
14938 uint16_t cq_max_l2_entries;
14939 /* Maximum number of CQ context entries supported for this function. */
14940 uint32_t cq_max_entries;
14941 /* Number of bytes that must be allocated for each context entry. */
14942 uint16_t cq_entry_size;
14943 /* Maximum number of VNIC context entries supported for this function. */
14944 uint16_t vnic_max_vnic_entries;
14945 /* Maximum number of Ring table context entries supported for this function. */
14946 uint16_t vnic_max_ring_table_entries;
14947 /* Number of bytes that must be allocated for each context entry. */
14948 uint16_t vnic_entry_size;
14949 /* Maximum number of statistic context entries supported for this function. */
14950 uint32_t stat_max_entries;
14951 /* Number of bytes that must be allocated for each context entry. */
14952 uint16_t stat_entry_size;
14953 /* Number of bytes that must be allocated for each context entry. */
14954 uint16_t tqm_entry_size;
14955 /* Minimum number of TQM context entries required per ring. */
14956 uint32_t tqm_min_entries_per_ring;
14958 * Maximum number of TQM context entries supported per ring. This is
14959 * actually a recommended TQM queue size based on worst case usage of
14962 * TQM fastpath rings should be sized large enough to accommodate the
14963 * maximum number of QPs (either L2 or RoCE, or both if shared)
14964 * that can be enqueued to the TQM ring.
14966 * TQM slowpath rings should be sized as follows:
14968 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
14971 * num_vnics is the number of VNICs allocated in the VNIC backing store
14972 * num_l2_tx_rings is the number of L2 rings in the QP backing store
14973 * num_roce_qps is the number of RoCE QPs in the QP backing store
14974 * tqm_min_size is tqm_min_entries_per_ring reported by
14975 * HWRM_FUNC_BACKING_STORE_QCAPS
14977 * Note that TQM ring sizes cannot be extended while the system is
14978 * operational. If a PF driver needs to extend a TQM ring, it needs
14979 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14980 * the backing store.
14982 uint32_t tqm_max_entries_per_ring;
14984 * Maximum number of MR plus AV context entries supported for this
14987 uint32_t mrav_max_entries;
14988 /* Number of bytes that must be allocated for each context entry. */
14989 uint16_t mrav_entry_size;
14990 /* Number of bytes that must be allocated for each context entry. */
14991 uint16_t tim_entry_size;
14992 /* Maximum number of Timer context entries supported for this function. */
14993 uint32_t tim_max_entries;
14995 * When this field is zero, the 32b `mrav_num_entries` field in the
14996 * `backing_store_cfg` and `backing_store_qcfg` commands represents
14997 * the total number of MR plus AV entries allowed in the MR/AV backing
15000 * When this field is non-zero, the 32b `mrav_num_entries` field in
15001 * the `backing_store_cfg` and `backing_store_qcfg` commands is
15002 * logically divided into two 16b fields. Bits `[31:16]` represents
15003 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
15004 * Both of these values are represented in a unit granularity
15005 * specified by this field. For example, if this field is 16 and
15006 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
15007 * is 8192 and the number of AV entries is 4096.
15009 uint16_t mrav_num_entries_units;
15011 * The number of entries specified for any TQM ring must be a
15012 * multiple of this value to prevent any resource allocation
15015 uint8_t tqm_entries_multiple;
15017 * Initializer to be used by drivers
15018 * to initialize context memory to ensure
15019 * context subsystem flags an error for an attack
15020 * before the first time context load.
15022 uint8_t ctx_kind_initializer;
15024 * Specifies which context kinds need to be initialized with the
15025 * ctx_kind_initializer.
15027 uint16_t ctx_init_mask;
15029 * If this bit is '1' then this context type should be initialized
15030 * with the ctx_kind_initializer at the specified offset.
15032 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
15035 * If this bit is '1' then this context type should be initialized
15036 * with the ctx_kind_initializer at the specified offset.
15038 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
15041 * If this bit is '1' then this context type should be initialized
15042 * with the ctx_kind_initializer at the specified offset.
15044 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
15047 * If this bit is '1' then this context type should be initialized
15048 * with the ctx_kind_initializer at the specified offset.
15050 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
15053 * If this bit is '1' then this context type should be initialized
15054 * with the ctx_kind_initializer at the specified offset.
15056 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
15059 * If this bit is '1' then this context type should be initialized
15060 * with the ctx_kind_initializer at the specified offset.
15062 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
15065 * If this bit is '1' then the Tx KTLS context type should be
15066 * initialized with the ctx_kind_initializer at the specified offset.
15068 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \
15071 * If this bit is '1' then the Rx KTLS context type should be
15072 * initialized with the ctx_kind_initializer at the specified offset.
15074 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \
15077 * Specifies the doubleword offset of ctx_kind_initializer for this
15080 uint8_t qp_init_offset;
15082 * Specifies the doubleword offset of ctx_kind_initializer for this
15085 uint8_t srq_init_offset;
15087 * Specifies the doubleword offset of ctx_kind_initializer for this
15090 uint8_t cq_init_offset;
15092 * Specifies the doubleword offset of ctx_kind_initializer for this
15095 uint8_t vnic_init_offset;
15097 * Count of TQM fastpath rings to be used for allocating backing store.
15098 * Backing store configuration must be specified for each TQM ring from
15099 * this count in `backing_store_cfg`.
15100 * Only first 8 TQM FP rings will be advertised with this field.
15102 uint8_t tqm_fp_rings_count;
15104 * Specifies the doubleword offset of ctx_kind_initializer for this
15107 uint8_t stat_init_offset;
15109 * Specifies the doubleword offset of ctx_kind_initializer for this
15112 uint8_t mrav_init_offset;
15114 * Count of TQM extended fastpath rings to be used for allocating
15115 * backing store beyond 8 rings(rings 9,10,11)
15116 * Backing store configuration must be specified for each TQM ring from
15117 * this count in `backing_store_cfg`.
15119 uint8_t tqm_fp_rings_count_ext;
15121 * Specifies the doubleword offset of ctx_kind_initializer for Tx
15122 * KTLS context type.
15124 uint8_t tkc_init_offset;
15126 * Specifies the doubleword offset of ctx_kind_initializer for Rx
15127 * KTLS context type.
15129 uint8_t rkc_init_offset;
15130 /* Tx KTLS context entry size in bytes. */
15131 uint16_t tkc_entry_size;
15132 /* Rx KTLS context entry size in bytes. */
15133 uint16_t rkc_entry_size;
15135 * Maximum number of Tx KTLS context entries supported for this
15138 uint32_t tkc_max_entries;
15140 * Maximum number of Rx KTLS context entries supported for this
15143 uint32_t rkc_max_entries;
15144 /* Reserved for future. */
15147 * This field is used in Output records to indicate that the output
15148 * is completely written to RAM. This field should be read as '1'
15149 * to indicate that the output has been completely written.
15150 * When writing a command completion or response to an internal processor,
15151 * the order of writes has to be such that this field is written last.
15156 /* tqm_fp_ring_cfg (size:128b/16B) */
15157 struct tqm_fp_ring_cfg {
15158 /* TQM ring page size and level. */
15159 uint8_t tqm_ring_pg_size_tqm_ring_lvl;
15160 /* TQM ring PBL indirect levels. */
15161 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
15163 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
15164 /* PBL pointer is physical start address. */
15165 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
15167 /* PBL pointer points to PTE table. */
15168 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
15171 * PBL pointer points to PDE table with each entry pointing to
15174 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
15176 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
15177 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
15178 /* TQM ring page size. */
15179 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
15181 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
15183 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
15184 (UINT32_C(0x0) << 4)
15186 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
15187 (UINT32_C(0x1) << 4)
15189 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
15190 (UINT32_C(0x2) << 4)
15192 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
15193 (UINT32_C(0x3) << 4)
15195 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
15196 (UINT32_C(0x4) << 4)
15198 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
15199 (UINT32_C(0x5) << 4)
15200 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
15201 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
15203 /* Number of TQM ring entries. */
15204 uint32_t tqm_ring_num_entries;
15205 /* TQM ring page directory. */
15206 uint64_t tqm_ring_page_dir;
15209 /*******************************
15210 * hwrm_func_backing_store_cfg *
15211 *******************************/
15214 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
15215 struct hwrm_func_backing_store_cfg_input {
15216 /* The HWRM command request type. */
15219 * The completion ring to send the completion event on. This should
15220 * be the NQ ID returned from the `nq_alloc` HWRM command.
15222 uint16_t cmpl_ring;
15224 * The sequence ID is used by the driver for tracking multiple
15225 * commands. This ID is treated as opaque data by the firmware and
15226 * the value is returned in the `hwrm_resp_hdr` upon completion.
15230 * The target ID of the command:
15231 * * 0x0-0xFFF8 - The function ID
15232 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15233 * * 0xFFFD - Reserved for user-space HWRM interface
15236 uint16_t target_id;
15238 * A physical address pointer pointing to a host buffer that the
15239 * command's response data will be written. This can be either a host
15240 * physical address (HPA) or a guest physical address (GPA) and must
15241 * point to a physically contiguous block of memory.
15243 uint64_t resp_addr;
15246 * When set, the firmware only uses on-chip resources and does not
15247 * expect any backing store to be provided by the host driver. This
15248 * mode provides minimal L2 functionality (e.g. limited L2 resources,
15251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
15254 * When set, the 32b `mrav_num_entries` field is logically divided
15255 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
15257 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
15261 * This bit must be '1' for the qp fields to be
15264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
15267 * This bit must be '1' for the srq fields to be
15270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
15273 * This bit must be '1' for the cq fields to be
15276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
15279 * This bit must be '1' for the vnic fields to be
15282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
15285 * This bit must be '1' for the stat fields to be
15288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
15291 * This bit must be '1' for the tqm_sp fields to be
15294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
15297 * This bit must be '1' for the tqm_ring0 fields to be
15300 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
15303 * This bit must be '1' for the tqm_ring1 fields to be
15306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
15309 * This bit must be '1' for the tqm_ring2 fields to be
15312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
15315 * This bit must be '1' for the tqm_ring3 fields to be
15318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
15321 * This bit must be '1' for the tqm_ring4 fields to be
15324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
15327 * This bit must be '1' for the tqm_ring5 fields to be
15330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
15333 * This bit must be '1' for the tqm_ring6 fields to be
15336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
15339 * This bit must be '1' for the tqm_ring7 fields to be
15342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
15345 * This bit must be '1' for the mrav fields to be
15348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
15351 * This bit must be '1' for the tim fields to be
15354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
15357 * This bit must be '1' for the tqm_ring8 fields to be
15360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
15363 * This bit must be '1' for the tqm_ring9 fields to be
15366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
15369 * This bit must be '1' for the tqm_ring10 fields to be
15372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
15375 * This bit must be '1' for the Tx KTLS context
15376 * fields to be configured.
15378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \
15381 * This bit must be '1' for the Rx KTLS context
15382 * fields to be configured.
15384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \
15386 /* QPC page size and level. */
15387 uint8_t qpc_pg_size_qpc_lvl;
15388 /* QPC PBL indirect levels. */
15389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
15391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
15392 /* PBL pointer is physical start address. */
15393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
15395 /* PBL pointer points to PTE table. */
15396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
15398 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
15401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
15402 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
15403 /* QPC page size. */
15404 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
15406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
15408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
15409 (UINT32_C(0x0) << 4)
15411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
15412 (UINT32_C(0x1) << 4)
15414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
15415 (UINT32_C(0x2) << 4)
15417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
15418 (UINT32_C(0x3) << 4)
15420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
15421 (UINT32_C(0x4) << 4)
15423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
15424 (UINT32_C(0x5) << 4)
15425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
15426 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
15427 /* SRQ page size and level. */
15428 uint8_t srq_pg_size_srq_lvl;
15429 /* SRQ PBL indirect levels. */
15430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
15432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
15433 /* PBL pointer is physical start address. */
15434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
15436 /* PBL pointer points to PTE table. */
15437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
15439 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
15442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
15443 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
15444 /* SRQ page size. */
15445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
15447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
15449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
15450 (UINT32_C(0x0) << 4)
15452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
15453 (UINT32_C(0x1) << 4)
15455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
15456 (UINT32_C(0x2) << 4)
15458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
15459 (UINT32_C(0x3) << 4)
15461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
15462 (UINT32_C(0x4) << 4)
15464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
15465 (UINT32_C(0x5) << 4)
15466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
15467 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
15468 /* CQ page size and level. */
15469 uint8_t cq_pg_size_cq_lvl;
15470 /* CQ PBL indirect levels. */
15471 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
15473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
15474 /* PBL pointer is physical start address. */
15475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
15477 /* PBL pointer points to PTE table. */
15478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
15480 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
15483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
15484 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
15485 /* CQ page size. */
15486 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
15488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
15490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
15491 (UINT32_C(0x0) << 4)
15493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
15494 (UINT32_C(0x1) << 4)
15496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
15497 (UINT32_C(0x2) << 4)
15499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
15500 (UINT32_C(0x3) << 4)
15502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
15503 (UINT32_C(0x4) << 4)
15505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
15506 (UINT32_C(0x5) << 4)
15507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
15508 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
15509 /* VNIC page size and level. */
15510 uint8_t vnic_pg_size_vnic_lvl;
15511 /* VNIC PBL indirect levels. */
15512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
15514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
15515 /* PBL pointer is physical start address. */
15516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
15518 /* PBL pointer points to PTE table. */
15519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
15521 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
15524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
15525 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
15526 /* VNIC page size. */
15527 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
15529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
15531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
15532 (UINT32_C(0x0) << 4)
15534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
15535 (UINT32_C(0x1) << 4)
15537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
15538 (UINT32_C(0x2) << 4)
15540 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
15541 (UINT32_C(0x3) << 4)
15543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
15544 (UINT32_C(0x4) << 4)
15546 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
15547 (UINT32_C(0x5) << 4)
15548 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
15549 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
15550 /* Stat page size and level. */
15551 uint8_t stat_pg_size_stat_lvl;
15552 /* Stat PBL indirect levels. */
15553 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
15555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
15556 /* PBL pointer is physical start address. */
15557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
15559 /* PBL pointer points to PTE table. */
15560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
15562 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
15565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
15566 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
15567 /* Stat page size. */
15568 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
15570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
15572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
15573 (UINT32_C(0x0) << 4)
15575 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
15576 (UINT32_C(0x1) << 4)
15578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
15579 (UINT32_C(0x2) << 4)
15581 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
15582 (UINT32_C(0x3) << 4)
15584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
15585 (UINT32_C(0x4) << 4)
15587 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
15588 (UINT32_C(0x5) << 4)
15589 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
15590 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
15591 /* TQM slow path page size and level. */
15592 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
15593 /* TQM slow path PBL indirect levels. */
15594 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
15596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
15597 /* PBL pointer is physical start address. */
15598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
15600 /* PBL pointer points to PTE table. */
15601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
15603 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
15606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
15607 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
15608 /* TQM slow path page size. */
15609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
15611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
15613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
15614 (UINT32_C(0x0) << 4)
15616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
15617 (UINT32_C(0x1) << 4)
15619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
15620 (UINT32_C(0x2) << 4)
15622 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
15623 (UINT32_C(0x3) << 4)
15625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
15626 (UINT32_C(0x4) << 4)
15628 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
15629 (UINT32_C(0x5) << 4)
15630 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
15631 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
15632 /* TQM ring 0 page size and level. */
15633 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
15634 /* TQM ring 0 PBL indirect levels. */
15635 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
15637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
15638 /* PBL pointer is physical start address. */
15639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
15641 /* PBL pointer points to PTE table. */
15642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
15644 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
15647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
15648 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
15649 /* TQM ring 0 page size. */
15650 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
15652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
15654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
15655 (UINT32_C(0x0) << 4)
15657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
15658 (UINT32_C(0x1) << 4)
15660 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
15661 (UINT32_C(0x2) << 4)
15663 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
15664 (UINT32_C(0x3) << 4)
15666 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
15667 (UINT32_C(0x4) << 4)
15669 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
15670 (UINT32_C(0x5) << 4)
15671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
15672 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
15673 /* TQM ring 1 page size and level. */
15674 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
15675 /* TQM ring 1 PBL indirect levels. */
15676 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
15678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
15679 /* PBL pointer is physical start address. */
15680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
15682 /* PBL pointer points to PTE table. */
15683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
15685 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
15688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
15689 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
15690 /* TQM ring 1 page size. */
15691 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
15693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
15695 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
15696 (UINT32_C(0x0) << 4)
15698 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
15699 (UINT32_C(0x1) << 4)
15701 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
15702 (UINT32_C(0x2) << 4)
15704 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
15705 (UINT32_C(0x3) << 4)
15707 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
15708 (UINT32_C(0x4) << 4)
15710 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
15711 (UINT32_C(0x5) << 4)
15712 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
15713 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
15714 /* TQM ring 2 page size and level. */
15715 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
15716 /* TQM ring 2 PBL indirect levels. */
15717 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
15719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
15720 /* PBL pointer is physical start address. */
15721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
15723 /* PBL pointer points to PTE table. */
15724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
15726 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
15729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
15730 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
15731 /* TQM ring 2 page size. */
15732 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
15734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
15736 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
15737 (UINT32_C(0x0) << 4)
15739 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
15740 (UINT32_C(0x1) << 4)
15742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
15743 (UINT32_C(0x2) << 4)
15745 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
15746 (UINT32_C(0x3) << 4)
15748 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
15749 (UINT32_C(0x4) << 4)
15751 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
15752 (UINT32_C(0x5) << 4)
15753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
15754 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
15755 /* TQM ring 3 page size and level. */
15756 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
15757 /* TQM ring 3 PBL indirect levels. */
15758 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
15760 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
15761 /* PBL pointer is physical start address. */
15762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
15764 /* PBL pointer points to PTE table. */
15765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
15767 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
15770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
15771 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
15772 /* TQM ring 3 page size. */
15773 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
15775 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
15777 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
15778 (UINT32_C(0x0) << 4)
15780 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
15781 (UINT32_C(0x1) << 4)
15783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
15784 (UINT32_C(0x2) << 4)
15786 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
15787 (UINT32_C(0x3) << 4)
15789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
15790 (UINT32_C(0x4) << 4)
15792 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
15793 (UINT32_C(0x5) << 4)
15794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
15795 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
15796 /* TQM ring 4 page size and level. */
15797 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
15798 /* TQM ring 4 PBL indirect levels. */
15799 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
15801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
15802 /* PBL pointer is physical start address. */
15803 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
15805 /* PBL pointer points to PTE table. */
15806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
15808 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15809 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
15811 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
15812 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
15813 /* TQM ring 4 page size. */
15814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
15816 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
15818 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
15819 (UINT32_C(0x0) << 4)
15821 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
15822 (UINT32_C(0x1) << 4)
15824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
15825 (UINT32_C(0x2) << 4)
15827 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
15828 (UINT32_C(0x3) << 4)
15830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
15831 (UINT32_C(0x4) << 4)
15833 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
15834 (UINT32_C(0x5) << 4)
15835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
15836 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
15837 /* TQM ring 5 page size and level. */
15838 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
15839 /* TQM ring 5 PBL indirect levels. */
15840 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
15842 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
15843 /* PBL pointer is physical start address. */
15844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
15846 /* PBL pointer points to PTE table. */
15847 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
15849 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15850 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
15852 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
15853 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
15854 /* TQM ring 5 page size. */
15855 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
15857 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
15859 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
15860 (UINT32_C(0x0) << 4)
15862 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
15863 (UINT32_C(0x1) << 4)
15865 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
15866 (UINT32_C(0x2) << 4)
15868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
15869 (UINT32_C(0x3) << 4)
15871 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
15872 (UINT32_C(0x4) << 4)
15874 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
15875 (UINT32_C(0x5) << 4)
15876 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
15877 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
15878 /* TQM ring 6 page size and level. */
15879 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
15880 /* TQM ring 6 PBL indirect levels. */
15881 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
15883 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
15884 /* PBL pointer is physical start address. */
15885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
15887 /* PBL pointer points to PTE table. */
15888 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
15890 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15891 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
15893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
15894 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
15895 /* TQM ring 6 page size. */
15896 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
15898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
15900 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
15901 (UINT32_C(0x0) << 4)
15903 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
15904 (UINT32_C(0x1) << 4)
15906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
15907 (UINT32_C(0x2) << 4)
15909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
15910 (UINT32_C(0x3) << 4)
15912 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
15913 (UINT32_C(0x4) << 4)
15915 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
15916 (UINT32_C(0x5) << 4)
15917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
15918 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
15919 /* TQM ring 7 page size and level. */
15920 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
15921 /* TQM ring 7 PBL indirect levels. */
15922 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
15924 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
15925 /* PBL pointer is physical start address. */
15926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
15928 /* PBL pointer points to PTE table. */
15929 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
15931 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15932 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
15934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
15935 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
15936 /* TQM ring 7 page size. */
15937 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
15939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
15941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
15942 (UINT32_C(0x0) << 4)
15944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
15945 (UINT32_C(0x1) << 4)
15947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
15948 (UINT32_C(0x2) << 4)
15950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
15951 (UINT32_C(0x3) << 4)
15953 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
15954 (UINT32_C(0x4) << 4)
15956 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
15957 (UINT32_C(0x5) << 4)
15958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
15959 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
15960 /* MR/AV page size and level. */
15961 uint8_t mrav_pg_size_mrav_lvl;
15962 /* MR/AV PBL indirect levels. */
15963 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
15965 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
15966 /* PBL pointer is physical start address. */
15967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
15969 /* PBL pointer points to PTE table. */
15970 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
15972 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15973 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
15975 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
15976 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
15977 /* MR/AV page size. */
15978 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
15980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
15982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
15983 (UINT32_C(0x0) << 4)
15985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
15986 (UINT32_C(0x1) << 4)
15988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
15989 (UINT32_C(0x2) << 4)
15991 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
15992 (UINT32_C(0x3) << 4)
15994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
15995 (UINT32_C(0x4) << 4)
15997 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
15998 (UINT32_C(0x5) << 4)
15999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
16000 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
16001 /* Timer page size and level. */
16002 uint8_t tim_pg_size_tim_lvl;
16003 /* Timer PBL indirect levels. */
16004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
16006 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
16007 /* PBL pointer is physical start address. */
16008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
16010 /* PBL pointer points to PTE table. */
16011 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
16013 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
16016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
16017 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
16018 /* Timer page size. */
16019 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
16021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
16023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
16024 (UINT32_C(0x0) << 4)
16026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
16027 (UINT32_C(0x1) << 4)
16029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
16030 (UINT32_C(0x2) << 4)
16032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
16033 (UINT32_C(0x3) << 4)
16035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
16036 (UINT32_C(0x4) << 4)
16038 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
16039 (UINT32_C(0x5) << 4)
16040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
16041 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
16042 /* QP page directory. */
16043 uint64_t qpc_page_dir;
16044 /* SRQ page directory. */
16045 uint64_t srq_page_dir;
16046 /* CQ page directory. */
16047 uint64_t cq_page_dir;
16048 /* VNIC page directory. */
16049 uint64_t vnic_page_dir;
16050 /* Stat page directory. */
16051 uint64_t stat_page_dir;
16052 /* TQM slowpath page directory. */
16053 uint64_t tqm_sp_page_dir;
16054 /* TQM ring 0 page directory. */
16055 uint64_t tqm_ring0_page_dir;
16056 /* TQM ring 1 page directory. */
16057 uint64_t tqm_ring1_page_dir;
16058 /* TQM ring 2 page directory. */
16059 uint64_t tqm_ring2_page_dir;
16060 /* TQM ring 3 page directory. */
16061 uint64_t tqm_ring3_page_dir;
16062 /* TQM ring 4 page directory. */
16063 uint64_t tqm_ring4_page_dir;
16064 /* TQM ring 5 page directory. */
16065 uint64_t tqm_ring5_page_dir;
16066 /* TQM ring 6 page directory. */
16067 uint64_t tqm_ring6_page_dir;
16068 /* TQM ring 7 page directory. */
16069 uint64_t tqm_ring7_page_dir;
16070 /* MR/AV page directory. */
16071 uint64_t mrav_page_dir;
16072 /* Timer page directory. */
16073 uint64_t tim_page_dir;
16074 /* Number of QPs. */
16075 uint32_t qp_num_entries;
16076 /* Number of SRQs. */
16077 uint32_t srq_num_entries;
16078 /* Number of CQs. */
16079 uint32_t cq_num_entries;
16080 /* Number of Stats. */
16081 uint32_t stat_num_entries;
16083 * Number of TQM slowpath entries.
16085 * TQM slowpath rings should be sized as follows:
16087 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
16090 * num_vnics is the number of VNICs allocated in the VNIC backing store
16091 * num_l2_tx_rings is the number of L2 rings in the QP backing store
16092 * num_roce_qps is the number of RoCE QPs in the QP backing store
16093 * tqm_min_size is tqm_min_entries_per_ring reported by
16094 * HWRM_FUNC_BACKING_STORE_QCAPS
16096 * Note that TQM ring sizes cannot be extended while the system is
16097 * operational. If a PF driver needs to extend a TQM ring, it needs
16098 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16099 * the backing store.
16101 uint32_t tqm_sp_num_entries;
16103 * Number of TQM ring 0 entries.
16105 * TQM fastpath rings should be sized large enough to accommodate the
16106 * maximum number of QPs (either L2 or RoCE, or both if shared)
16107 * that can be enqueued to the TQM ring.
16109 * Note that TQM ring sizes cannot be extended while the system is
16110 * operational. If a PF driver needs to extend a TQM ring, it needs
16111 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16112 * the backing store.
16114 uint32_t tqm_ring0_num_entries;
16116 * Number of TQM ring 1 entries.
16118 * TQM fastpath rings should be sized large enough to accommodate the
16119 * maximum number of QPs (either L2 or RoCE, or both if shared)
16120 * that can be enqueued to the TQM ring.
16122 * Note that TQM ring sizes cannot be extended while the system is
16123 * operational. If a PF driver needs to extend a TQM ring, it needs
16124 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16125 * the backing store.
16127 uint32_t tqm_ring1_num_entries;
16129 * Number of TQM ring 2 entries.
16131 * TQM fastpath rings should be sized large enough to accommodate the
16132 * maximum number of QPs (either L2 or RoCE, or both if shared)
16133 * that can be enqueued to the TQM ring.
16135 * Note that TQM ring sizes cannot be extended while the system is
16136 * operational. If a PF driver needs to extend a TQM ring, it needs
16137 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16138 * the backing store.
16140 uint32_t tqm_ring2_num_entries;
16142 * Number of TQM ring 3 entries.
16144 * TQM fastpath rings should be sized large enough to accommodate the
16145 * maximum number of QPs (either L2 or RoCE, or both if shared)
16146 * that can be enqueued to the TQM ring.
16148 * Note that TQM ring sizes cannot be extended while the system is
16149 * operational. If a PF driver needs to extend a TQM ring, it needs
16150 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16151 * the backing store.
16153 uint32_t tqm_ring3_num_entries;
16155 * Number of TQM ring 4 entries.
16157 * TQM fastpath rings should be sized large enough to accommodate the
16158 * maximum number of QPs (either L2 or RoCE, or both if shared)
16159 * that can be enqueued to the TQM ring.
16161 * Note that TQM ring sizes cannot be extended while the system is
16162 * operational. If a PF driver needs to extend a TQM ring, it needs
16163 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16164 * the backing store.
16166 uint32_t tqm_ring4_num_entries;
16168 * Number of TQM ring 5 entries.
16170 * TQM fastpath rings should be sized large enough to accommodate the
16171 * maximum number of QPs (either L2 or RoCE, or both if shared)
16172 * that can be enqueued to the TQM ring.
16174 * Note that TQM ring sizes cannot be extended while the system is
16175 * operational. If a PF driver needs to extend a TQM ring, it needs
16176 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16177 * the backing store.
16179 uint32_t tqm_ring5_num_entries;
16181 * Number of TQM ring 6 entries.
16183 * TQM fastpath rings should be sized large enough to accommodate the
16184 * maximum number of QPs (either L2 or RoCE, or both if shared)
16185 * that can be enqueued to the TQM ring.
16187 * Note that TQM ring sizes cannot be extended while the system is
16188 * operational. If a PF driver needs to extend a TQM ring, it needs
16189 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16190 * the backing store.
16192 uint32_t tqm_ring6_num_entries;
16194 * Number of TQM ring 7 entries.
16196 * TQM fastpath rings should be sized large enough to accommodate the
16197 * maximum number of QPs (either L2 or RoCE, or both if shared)
16198 * that can be enqueued to the TQM ring.
16200 * Note that TQM ring sizes cannot be extended while the system is
16201 * operational. If a PF driver needs to extend a TQM ring, it needs
16202 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
16203 * the backing store.
16205 uint32_t tqm_ring7_num_entries;
16207 * If the MR/AV split reservation flag is not set, then this field
16208 * represents the total number of MR plus AV entries. For versions
16209 * of firmware that support the split reservation, when it is not
16210 * specified half of the entries will be reserved for MRs and the
16211 * other half for AVs.
16213 * If the MR/AV split reservation flag is set, then this
16214 * field is logically divided into two 16b fields. Bits `[31:16]`
16215 * represents the `mr_num_entries` and bits `[15:0]` represents
16216 * `av_num_entries`. The granularity of these values is defined by
16217 * the `mrav_num_entries_unit` field returned by the
16218 * `backing_store_qcaps` command.
16220 uint32_t mrav_num_entries;
16221 /* Number of Timer entries. */
16222 uint32_t tim_num_entries;
16223 /* Number of entries to reserve for QP1 */
16224 uint16_t qp_num_qp1_entries;
16225 /* Number of entries to reserve for L2 */
16226 uint16_t qp_num_l2_entries;
16227 /* Number of bytes that have been allocated for each context entry. */
16228 uint16_t qp_entry_size;
16229 /* Number of entries to reserve for L2 */
16230 uint16_t srq_num_l2_entries;
16231 /* Number of bytes that have been allocated for each context entry. */
16232 uint16_t srq_entry_size;
16233 /* Number of entries to reserve for L2 */
16234 uint16_t cq_num_l2_entries;
16235 /* Number of bytes that have been allocated for each context entry. */
16236 uint16_t cq_entry_size;
16237 /* Number of entries to reserve for VNIC entries */
16238 uint16_t vnic_num_vnic_entries;
16239 /* Number of entries to reserve for Ring table entries */
16240 uint16_t vnic_num_ring_table_entries;
16241 /* Number of bytes that have been allocated for each context entry. */
16242 uint16_t vnic_entry_size;
16243 /* Number of bytes that have been allocated for each context entry. */
16244 uint16_t stat_entry_size;
16245 /* Number of bytes that have been allocated for each context entry. */
16246 uint16_t tqm_entry_size;
16247 /* Number of bytes that have been allocated for each context entry. */
16248 uint16_t mrav_entry_size;
16249 /* Number of bytes that have been allocated for each context entry. */
16250 uint16_t tim_entry_size;
16251 /* TQM ring page size and level. */
16252 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
16253 /* TQM ring PBL indirect levels. */
16254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
16256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
16258 /* PBL pointer is physical start address. */
16259 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
16261 /* PBL pointer points to PTE table. */
16262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
16265 * PBL pointer points to PDE table with each entry pointing to
16268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
16270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
16271 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
16272 /* TQM ring page size. */
16273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
16275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
16278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
16279 (UINT32_C(0x0) << 4)
16281 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
16282 (UINT32_C(0x1) << 4)
16284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
16285 (UINT32_C(0x2) << 4)
16287 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
16288 (UINT32_C(0x3) << 4)
16290 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
16291 (UINT32_C(0x4) << 4)
16293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
16294 (UINT32_C(0x5) << 4)
16295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
16296 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
16297 uint8_t ring8_unused[3];
16298 /* Number of TQM ring entries. */
16299 uint32_t tqm_ring8_num_entries;
16300 /* TQM ring page directory. */
16301 uint64_t tqm_ring8_page_dir;
16302 /* TQM ring page size and level. */
16303 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
16304 /* TQM ring PBL indirect levels. */
16305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
16307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
16309 /* PBL pointer is physical start address. */
16310 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
16312 /* PBL pointer points to PTE table. */
16313 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
16316 * PBL pointer points to PDE table with each entry pointing to
16319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
16321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
16322 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
16323 /* TQM ring page size. */
16324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
16326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
16329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
16330 (UINT32_C(0x0) << 4)
16332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
16333 (UINT32_C(0x1) << 4)
16335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
16336 (UINT32_C(0x2) << 4)
16338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
16339 (UINT32_C(0x3) << 4)
16341 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
16342 (UINT32_C(0x4) << 4)
16344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
16345 (UINT32_C(0x5) << 4)
16346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
16347 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
16348 uint8_t ring9_unused[3];
16349 /* Number of TQM ring entries. */
16350 uint32_t tqm_ring9_num_entries;
16351 /* TQM ring page directory. */
16352 uint64_t tqm_ring9_page_dir;
16353 /* TQM ring page size and level. */
16354 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
16355 /* TQM ring PBL indirect levels. */
16356 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
16358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
16360 /* PBL pointer is physical start address. */
16361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
16363 /* PBL pointer points to PTE table. */
16364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
16367 * PBL pointer points to PDE table with each entry pointing to
16370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
16372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
16373 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
16374 /* TQM ring page size. */
16375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
16377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
16380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
16381 (UINT32_C(0x0) << 4)
16383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
16384 (UINT32_C(0x1) << 4)
16386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
16387 (UINT32_C(0x2) << 4)
16389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
16390 (UINT32_C(0x3) << 4)
16392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
16393 (UINT32_C(0x4) << 4)
16395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
16396 (UINT32_C(0x5) << 4)
16397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
16398 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
16399 uint8_t ring10_unused[3];
16400 /* Number of TQM ring entries. */
16401 uint32_t tqm_ring10_num_entries;
16402 /* TQM ring page directory. */
16403 uint64_t tqm_ring10_page_dir;
16404 /* Number of Tx KTLS context entries allocated. */
16405 uint32_t tkc_num_entries;
16406 /* Number of Rx KTLS context entries allocated. */
16407 uint32_t rkc_num_entries;
16408 /* Tx KTLS context page directory. */
16409 uint64_t tkc_page_dir;
16410 /* Rx KTLS context page directory. */
16411 uint64_t rkc_page_dir;
16412 /* Number of bytes allocated for each Tx KTLS context entry. */
16413 uint16_t tkc_entry_size;
16414 /* Number of bytes allocated for each Rx KTLS context entry. */
16415 uint16_t rkc_entry_size;
16416 /* Tx KTLS context page size and level. */
16417 uint8_t tkc_pg_size_tkc_lvl;
16418 /* Tx KTLS context PBL indirect levels. */
16419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \
16421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0
16422 /* PBL pointer is physical start address. */
16423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \
16425 /* PBL pointer points to PTE table. */
16426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \
16428 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \
16431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \
16432 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2
16433 /* Tx KTLS context page size. */
16434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \
16436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4
16438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \
16439 (UINT32_C(0x0) << 4)
16441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \
16442 (UINT32_C(0x1) << 4)
16444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \
16445 (UINT32_C(0x2) << 4)
16447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \
16448 (UINT32_C(0x3) << 4)
16450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \
16451 (UINT32_C(0x4) << 4)
16453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \
16454 (UINT32_C(0x5) << 4)
16455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \
16456 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G
16457 /* Rx KTLS context page size and level. */
16458 uint8_t rkc_pg_size_rkc_lvl;
16459 /* Rx KTLS context PBL indirect levels. */
16460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \
16462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0
16463 /* PBL pointer is physical start address. */
16464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \
16466 /* PBL pointer points to PTE table. */
16467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \
16470 * PBL pointer points to PDE table with each entry pointing to
16473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \
16475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \
16476 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2
16477 /* Rx KTLS context page size. */
16478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \
16480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4
16482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \
16483 (UINT32_C(0x0) << 4)
16485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \
16486 (UINT32_C(0x1) << 4)
16488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \
16489 (UINT32_C(0x2) << 4)
16491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \
16492 (UINT32_C(0x3) << 4)
16494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \
16495 (UINT32_C(0x4) << 4)
16497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \
16498 (UINT32_C(0x5) << 4)
16499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \
16500 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G
16501 /* Reserved for future. */
16505 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
16506 struct hwrm_func_backing_store_cfg_output {
16507 /* The specific error status for the command. */
16508 uint16_t error_code;
16509 /* The HWRM command request type. */
16511 /* The sequence ID from the original command. */
16513 /* The length of the response data in number of bytes. */
16515 uint8_t unused_0[7];
16517 * This field is used in Output records to indicate that the output
16518 * is completely written to RAM. This field should be read as '1'
16519 * to indicate that the output has been completely written.
16520 * When writing a command completion or response to an internal processor,
16521 * the order of writes has to be such that this field is written last.
16526 /********************************
16527 * hwrm_func_backing_store_qcfg *
16528 ********************************/
16531 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
16532 struct hwrm_func_backing_store_qcfg_input {
16533 /* The HWRM command request type. */
16536 * The completion ring to send the completion event on. This should
16537 * be the NQ ID returned from the `nq_alloc` HWRM command.
16539 uint16_t cmpl_ring;
16541 * The sequence ID is used by the driver for tracking multiple
16542 * commands. This ID is treated as opaque data by the firmware and
16543 * the value is returned in the `hwrm_resp_hdr` upon completion.
16547 * The target ID of the command:
16548 * * 0x0-0xFFF8 - The function ID
16549 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16550 * * 0xFFFD - Reserved for user-space HWRM interface
16553 uint16_t target_id;
16555 * A physical address pointer pointing to a host buffer that the
16556 * command's response data will be written. This can be either a host
16557 * physical address (HPA) or a guest physical address (GPA) and must
16558 * point to a physically contiguous block of memory.
16560 uint64_t resp_addr;
16563 /* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */
16564 struct hwrm_func_backing_store_qcfg_output {
16565 /* The specific error status for the command. */
16566 uint16_t error_code;
16567 /* The HWRM command request type. */
16569 /* The sequence ID from the original command. */
16571 /* The length of the response data in number of bytes. */
16575 * When set, the firmware only uses on-chip resources and does not
16576 * expect any backing store to be provided by the host driver. This
16577 * mode provides minimal L2 functionality (e.g. limited L2 resources,
16580 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
16583 * When set, the 32b `mrav_num_entries` field is logically divided
16584 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
16586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
16590 * This bit must be '1' for the qp fields to be
16593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
16596 * This bit must be '1' for the srq fields to be
16599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
16602 * This bit must be '1' for the cq fields to be
16605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
16608 * This bit must be '1' for the vnic fields to be
16611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
16614 * This bit must be '1' for the stat fields to be
16617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
16620 * This bit must be '1' for the tqm_sp fields to be
16623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
16626 * This bit must be '1' for the tqm_ring0 fields to be
16629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
16632 * This bit must be '1' for the tqm_ring1 fields to be
16635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
16638 * This bit must be '1' for the tqm_ring2 fields to be
16641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
16644 * This bit must be '1' for the tqm_ring3 fields to be
16647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
16650 * This bit must be '1' for the tqm_ring4 fields to be
16653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
16656 * This bit must be '1' for the tqm_ring5 fields to be
16659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
16662 * This bit must be '1' for the tqm_ring6 fields to be
16665 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
16668 * This bit must be '1' for the tqm_ring7 fields to be
16671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
16674 * This bit must be '1' for the mrav fields to be
16677 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
16680 * This bit must be '1' for the tim fields to be
16683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
16686 * This bit must be '1' for the tqm_ring8 fields to be
16689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
16692 * This bit must be '1' for the tqm_ring9 fields to be
16695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
16698 * This bit must be '1' for the tqm_ring10 fields to be
16701 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
16704 * This bit must be '1' for the Tx KTLS context
16705 * fields to be configured.
16707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \
16710 * This bit must be '1' for the Rx KTLS context
16711 * fields to be configured.
16713 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \
16715 /* QPC page size and level. */
16716 uint8_t qpc_pg_size_qpc_lvl;
16717 /* QPC PBL indirect levels. */
16718 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
16720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
16721 /* PBL pointer is physical start address. */
16722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
16724 /* PBL pointer points to PTE table. */
16725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
16727 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16728 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
16730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
16731 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
16732 /* QPC page size. */
16733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
16735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
16737 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
16738 (UINT32_C(0x0) << 4)
16740 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
16741 (UINT32_C(0x1) << 4)
16743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
16744 (UINT32_C(0x2) << 4)
16746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
16747 (UINT32_C(0x3) << 4)
16749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
16750 (UINT32_C(0x4) << 4)
16752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
16753 (UINT32_C(0x5) << 4)
16754 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
16755 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
16756 /* SRQ page size and level. */
16757 uint8_t srq_pg_size_srq_lvl;
16758 /* SRQ PBL indirect levels. */
16759 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
16761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
16762 /* PBL pointer is physical start address. */
16763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
16765 /* PBL pointer points to PTE table. */
16766 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
16768 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
16771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
16772 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
16773 /* SRQ page size. */
16774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
16776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
16778 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
16779 (UINT32_C(0x0) << 4)
16781 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
16782 (UINT32_C(0x1) << 4)
16784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
16785 (UINT32_C(0x2) << 4)
16787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
16788 (UINT32_C(0x3) << 4)
16790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
16791 (UINT32_C(0x4) << 4)
16793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
16794 (UINT32_C(0x5) << 4)
16795 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
16796 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
16797 /* CQ page size and level. */
16798 uint8_t cq_pg_size_cq_lvl;
16799 /* CQ PBL indirect levels. */
16800 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
16802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
16803 /* PBL pointer is physical start address. */
16804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
16806 /* PBL pointer points to PTE table. */
16807 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
16809 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16810 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
16812 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
16813 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
16814 /* CQ page size. */
16815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
16817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
16819 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
16820 (UINT32_C(0x0) << 4)
16822 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
16823 (UINT32_C(0x1) << 4)
16825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
16826 (UINT32_C(0x2) << 4)
16828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
16829 (UINT32_C(0x3) << 4)
16831 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
16832 (UINT32_C(0x4) << 4)
16834 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
16835 (UINT32_C(0x5) << 4)
16836 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
16837 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
16838 /* VNIC page size and level. */
16839 uint8_t vnic_pg_size_vnic_lvl;
16840 /* VNIC PBL indirect levels. */
16841 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
16843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
16844 /* PBL pointer is physical start address. */
16845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
16847 /* PBL pointer points to PTE table. */
16848 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
16850 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16851 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
16853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
16854 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
16855 /* VNIC page size. */
16856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
16858 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
16860 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
16861 (UINT32_C(0x0) << 4)
16863 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
16864 (UINT32_C(0x1) << 4)
16866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
16867 (UINT32_C(0x2) << 4)
16869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
16870 (UINT32_C(0x3) << 4)
16872 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
16873 (UINT32_C(0x4) << 4)
16875 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
16876 (UINT32_C(0x5) << 4)
16877 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
16878 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
16879 /* Stat page size and level. */
16880 uint8_t stat_pg_size_stat_lvl;
16881 /* Stat PBL indirect levels. */
16882 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
16884 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
16885 /* PBL pointer is physical start address. */
16886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
16888 /* PBL pointer points to PTE table. */
16889 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
16891 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16892 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
16894 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
16895 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
16896 /* Stat page size. */
16897 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
16899 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
16901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
16902 (UINT32_C(0x0) << 4)
16904 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
16905 (UINT32_C(0x1) << 4)
16907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
16908 (UINT32_C(0x2) << 4)
16910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
16911 (UINT32_C(0x3) << 4)
16913 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
16914 (UINT32_C(0x4) << 4)
16916 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
16917 (UINT32_C(0x5) << 4)
16918 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
16919 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
16920 /* TQM slow path page size and level. */
16921 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
16922 /* TQM slow path PBL indirect levels. */
16923 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
16925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
16926 /* PBL pointer is physical start address. */
16927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
16929 /* PBL pointer points to PTE table. */
16930 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
16932 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16933 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
16935 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
16936 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
16937 /* TQM slow path page size. */
16938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
16940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
16942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
16943 (UINT32_C(0x0) << 4)
16945 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
16946 (UINT32_C(0x1) << 4)
16948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
16949 (UINT32_C(0x2) << 4)
16951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
16952 (UINT32_C(0x3) << 4)
16954 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
16955 (UINT32_C(0x4) << 4)
16957 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
16958 (UINT32_C(0x5) << 4)
16959 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
16960 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
16961 /* TQM ring 0 page size and level. */
16962 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
16963 /* TQM ring 0 PBL indirect levels. */
16964 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
16966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
16967 /* PBL pointer is physical start address. */
16968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
16970 /* PBL pointer points to PTE table. */
16971 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
16973 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16974 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
16976 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
16977 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
16978 /* TQM ring 0 page size. */
16979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
16981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
16983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
16984 (UINT32_C(0x0) << 4)
16986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
16987 (UINT32_C(0x1) << 4)
16989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
16990 (UINT32_C(0x2) << 4)
16992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
16993 (UINT32_C(0x3) << 4)
16995 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
16996 (UINT32_C(0x4) << 4)
16998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
16999 (UINT32_C(0x5) << 4)
17000 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
17001 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
17002 /* TQM ring 1 page size and level. */
17003 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
17004 /* TQM ring 1 PBL indirect levels. */
17005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
17007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
17008 /* PBL pointer is physical start address. */
17009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
17011 /* PBL pointer points to PTE table. */
17012 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
17014 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17015 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
17017 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
17018 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
17019 /* TQM ring 1 page size. */
17020 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
17022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
17024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
17025 (UINT32_C(0x0) << 4)
17027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
17028 (UINT32_C(0x1) << 4)
17030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
17031 (UINT32_C(0x2) << 4)
17033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
17034 (UINT32_C(0x3) << 4)
17036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
17037 (UINT32_C(0x4) << 4)
17039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
17040 (UINT32_C(0x5) << 4)
17041 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
17042 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
17043 /* TQM ring 2 page size and level. */
17044 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
17045 /* TQM ring 2 PBL indirect levels. */
17046 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
17048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
17049 /* PBL pointer is physical start address. */
17050 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
17052 /* PBL pointer points to PTE table. */
17053 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
17055 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17056 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
17058 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
17059 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
17060 /* TQM ring 2 page size. */
17061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
17063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
17065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
17066 (UINT32_C(0x0) << 4)
17068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
17069 (UINT32_C(0x1) << 4)
17071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
17072 (UINT32_C(0x2) << 4)
17074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
17075 (UINT32_C(0x3) << 4)
17077 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
17078 (UINT32_C(0x4) << 4)
17080 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
17081 (UINT32_C(0x5) << 4)
17082 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
17083 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
17084 /* TQM ring 3 page size and level. */
17085 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
17086 /* TQM ring 3 PBL indirect levels. */
17087 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
17089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
17090 /* PBL pointer is physical start address. */
17091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
17093 /* PBL pointer points to PTE table. */
17094 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
17096 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17097 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
17099 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
17100 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
17101 /* TQM ring 3 page size. */
17102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
17104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
17106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
17107 (UINT32_C(0x0) << 4)
17109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
17110 (UINT32_C(0x1) << 4)
17112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
17113 (UINT32_C(0x2) << 4)
17115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
17116 (UINT32_C(0x3) << 4)
17118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
17119 (UINT32_C(0x4) << 4)
17121 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
17122 (UINT32_C(0x5) << 4)
17123 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
17124 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
17125 /* TQM ring 4 page size and level. */
17126 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
17127 /* TQM ring 4 PBL indirect levels. */
17128 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
17130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
17131 /* PBL pointer is physical start address. */
17132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
17134 /* PBL pointer points to PTE table. */
17135 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
17137 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
17140 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
17141 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
17142 /* TQM ring 4 page size. */
17143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
17145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
17147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
17148 (UINT32_C(0x0) << 4)
17150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
17151 (UINT32_C(0x1) << 4)
17153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
17154 (UINT32_C(0x2) << 4)
17156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
17157 (UINT32_C(0x3) << 4)
17159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
17160 (UINT32_C(0x4) << 4)
17162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
17163 (UINT32_C(0x5) << 4)
17164 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
17165 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
17166 /* TQM ring 5 page size and level. */
17167 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
17168 /* TQM ring 5 PBL indirect levels. */
17169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
17171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
17172 /* PBL pointer is physical start address. */
17173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
17175 /* PBL pointer points to PTE table. */
17176 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
17178 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
17181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
17182 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
17183 /* TQM ring 5 page size. */
17184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
17186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
17188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
17189 (UINT32_C(0x0) << 4)
17191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
17192 (UINT32_C(0x1) << 4)
17194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
17195 (UINT32_C(0x2) << 4)
17197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
17198 (UINT32_C(0x3) << 4)
17200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
17201 (UINT32_C(0x4) << 4)
17203 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
17204 (UINT32_C(0x5) << 4)
17205 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
17206 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
17207 /* TQM ring 6 page size and level. */
17208 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
17209 /* TQM ring 6 PBL indirect levels. */
17210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
17212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
17213 /* PBL pointer is physical start address. */
17214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
17216 /* PBL pointer points to PTE table. */
17217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
17219 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
17222 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
17223 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
17224 /* TQM ring 6 page size. */
17225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
17227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
17229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
17230 (UINT32_C(0x0) << 4)
17232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
17233 (UINT32_C(0x1) << 4)
17235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
17236 (UINT32_C(0x2) << 4)
17238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
17239 (UINT32_C(0x3) << 4)
17241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
17242 (UINT32_C(0x4) << 4)
17244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
17245 (UINT32_C(0x5) << 4)
17246 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
17247 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
17248 /* TQM ring 7 page size and level. */
17249 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
17250 /* TQM ring 7 PBL indirect levels. */
17251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
17253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
17254 /* PBL pointer is physical start address. */
17255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
17257 /* PBL pointer points to PTE table. */
17258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
17260 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
17263 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
17264 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
17265 /* TQM ring 7 page size. */
17266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
17268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
17270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
17271 (UINT32_C(0x0) << 4)
17273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
17274 (UINT32_C(0x1) << 4)
17276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
17277 (UINT32_C(0x2) << 4)
17279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
17280 (UINT32_C(0x3) << 4)
17282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
17283 (UINT32_C(0x4) << 4)
17285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
17286 (UINT32_C(0x5) << 4)
17287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
17288 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
17289 /* MR/AV page size and level. */
17290 uint8_t mrav_pg_size_mrav_lvl;
17291 /* MR/AV PBL indirect levels. */
17292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
17294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
17295 /* PBL pointer is physical start address. */
17296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
17298 /* PBL pointer points to PTE table. */
17299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
17301 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
17304 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
17305 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
17306 /* MR/AV page size. */
17307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
17309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
17311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
17312 (UINT32_C(0x0) << 4)
17314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
17315 (UINT32_C(0x1) << 4)
17317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
17318 (UINT32_C(0x2) << 4)
17320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
17321 (UINT32_C(0x3) << 4)
17323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
17324 (UINT32_C(0x4) << 4)
17326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
17327 (UINT32_C(0x5) << 4)
17328 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
17329 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
17330 /* Timer page size and level. */
17331 uint8_t tim_pg_size_tim_lvl;
17332 /* Timer PBL indirect levels. */
17333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
17335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
17336 /* PBL pointer is physical start address. */
17337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
17339 /* PBL pointer points to PTE table. */
17340 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
17342 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
17343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
17345 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
17346 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
17347 /* Timer page size. */
17348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
17350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
17352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
17353 (UINT32_C(0x0) << 4)
17355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
17356 (UINT32_C(0x1) << 4)
17358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
17359 (UINT32_C(0x2) << 4)
17361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
17362 (UINT32_C(0x3) << 4)
17364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
17365 (UINT32_C(0x4) << 4)
17367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
17368 (UINT32_C(0x5) << 4)
17369 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
17370 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
17371 /* QP page directory. */
17372 uint64_t qpc_page_dir;
17373 /* SRQ page directory. */
17374 uint64_t srq_page_dir;
17375 /* CQ page directory. */
17376 uint64_t cq_page_dir;
17377 /* VNIC page directory. */
17378 uint64_t vnic_page_dir;
17379 /* Stat page directory. */
17380 uint64_t stat_page_dir;
17381 /* TQM slowpath page directory. */
17382 uint64_t tqm_sp_page_dir;
17383 /* TQM ring 0 page directory. */
17384 uint64_t tqm_ring0_page_dir;
17385 /* TQM ring 1 page directory. */
17386 uint64_t tqm_ring1_page_dir;
17387 /* TQM ring 2 page directory. */
17388 uint64_t tqm_ring2_page_dir;
17389 /* TQM ring 3 page directory. */
17390 uint64_t tqm_ring3_page_dir;
17391 /* TQM ring 4 page directory. */
17392 uint64_t tqm_ring4_page_dir;
17393 /* TQM ring 5 page directory. */
17394 uint64_t tqm_ring5_page_dir;
17395 /* TQM ring 6 page directory. */
17396 uint64_t tqm_ring6_page_dir;
17397 /* TQM ring 7 page directory. */
17398 uint64_t tqm_ring7_page_dir;
17399 /* MR/AV page directory. */
17400 uint64_t mrav_page_dir;
17401 /* Timer page directory. */
17402 uint64_t tim_page_dir;
17403 /* Number of entries to reserve for QP1 */
17404 uint16_t qp_num_qp1_entries;
17405 /* Number of entries to reserve for L2 */
17406 uint16_t qp_num_l2_entries;
17407 /* Number of QPs. */
17408 uint32_t qp_num_entries;
17409 /* Number of SRQs. */
17410 uint32_t srq_num_entries;
17411 /* Number of entries to reserve for L2 */
17412 uint16_t srq_num_l2_entries;
17413 /* Number of entries to reserve for L2 */
17414 uint16_t cq_num_l2_entries;
17415 /* Number of CQs. */
17416 uint32_t cq_num_entries;
17417 /* Number of entries to reserve for VNIC entries */
17418 uint16_t vnic_num_vnic_entries;
17419 /* Number of entries to reserve for Ring table entries */
17420 uint16_t vnic_num_ring_table_entries;
17421 /* Number of Stats. */
17422 uint32_t stat_num_entries;
17423 /* Number of TQM slowpath entries. */
17424 uint32_t tqm_sp_num_entries;
17425 /* Number of TQM ring 0 entries. */
17426 uint32_t tqm_ring0_num_entries;
17427 /* Number of TQM ring 1 entries. */
17428 uint32_t tqm_ring1_num_entries;
17429 /* Number of TQM ring 2 entries. */
17430 uint32_t tqm_ring2_num_entries;
17431 /* Number of TQM ring 3 entries. */
17432 uint32_t tqm_ring3_num_entries;
17433 /* Number of TQM ring 4 entries. */
17434 uint32_t tqm_ring4_num_entries;
17435 /* Number of TQM ring 5 entries. */
17436 uint32_t tqm_ring5_num_entries;
17437 /* Number of TQM ring 6 entries. */
17438 uint32_t tqm_ring6_num_entries;
17439 /* Number of TQM ring 7 entries. */
17440 uint32_t tqm_ring7_num_entries;
17442 * If the MR/AV split reservation flag is not set, then this field
17443 * represents the total number of MR plus AV entries. For versions
17444 * of firmware that support the split reservation, when it is not
17445 * specified half of the entries will be reserved for MRs and the
17446 * other half for AVs.
17448 * If the MR/AV split reservation flag is set, then this
17449 * field is logically divided into two 16b fields. Bits `[31:16]`
17450 * represents the `mr_num_entries` and bits `[15:0]` represents
17451 * `av_num_entries`. The granularity of these values is defined by
17452 * the `mrav_num_entries_unit` field returned by the
17453 * `backing_store_qcaps` command.
17455 uint32_t mrav_num_entries;
17456 /* Number of Timer entries. */
17457 uint32_t tim_num_entries;
17458 /* TQM ring page size and level. */
17459 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
17460 /* TQM ring PBL indirect levels. */
17461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
17463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
17465 /* PBL pointer is physical start address. */
17466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
17468 /* PBL pointer points to PTE table. */
17469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
17472 * PBL pointer points to PDE table with each entry pointing to
17475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
17477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
17478 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
17479 /* TQM ring page size. */
17480 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
17482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
17485 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
17486 (UINT32_C(0x0) << 4)
17488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
17489 (UINT32_C(0x1) << 4)
17491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
17492 (UINT32_C(0x2) << 4)
17494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
17495 (UINT32_C(0x3) << 4)
17497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
17498 (UINT32_C(0x4) << 4)
17500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
17501 (UINT32_C(0x5) << 4)
17502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
17503 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
17504 uint8_t ring8_unused[3];
17505 /* Number of TQM ring entries. */
17506 uint32_t tqm_ring8_num_entries;
17507 /* TQM ring page directory. */
17508 uint64_t tqm_ring8_page_dir;
17509 /* TQM ring page size and level. */
17510 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
17511 /* TQM ring PBL indirect levels. */
17512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
17514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
17516 /* PBL pointer is physical start address. */
17517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
17519 /* PBL pointer points to PTE table. */
17520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
17523 * PBL pointer points to PDE table with each entry pointing to
17526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
17528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
17529 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
17530 /* TQM ring page size. */
17531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
17533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
17536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
17537 (UINT32_C(0x0) << 4)
17539 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
17540 (UINT32_C(0x1) << 4)
17542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
17543 (UINT32_C(0x2) << 4)
17545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
17546 (UINT32_C(0x3) << 4)
17548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
17549 (UINT32_C(0x4) << 4)
17551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
17552 (UINT32_C(0x5) << 4)
17553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
17554 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
17555 uint8_t ring9_unused[3];
17556 /* Number of TQM ring entries. */
17557 uint32_t tqm_ring9_num_entries;
17558 /* TQM ring page directory. */
17559 uint64_t tqm_ring9_page_dir;
17560 /* TQM ring page size and level. */
17561 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
17562 /* TQM ring PBL indirect levels. */
17563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
17565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
17567 /* PBL pointer is physical start address. */
17568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
17570 /* PBL pointer points to PTE table. */
17571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
17574 * PBL pointer points to PDE table with each entry pointing to
17577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
17579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
17580 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
17581 /* TQM ring page size. */
17582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
17584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
17587 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
17588 (UINT32_C(0x0) << 4)
17590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
17591 (UINT32_C(0x1) << 4)
17593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
17594 (UINT32_C(0x2) << 4)
17596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
17597 (UINT32_C(0x3) << 4)
17599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
17600 (UINT32_C(0x4) << 4)
17602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
17603 (UINT32_C(0x5) << 4)
17604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
17605 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
17606 uint8_t ring10_unused[3];
17607 /* Number of TQM ring entries. */
17608 uint32_t tqm_ring10_num_entries;
17609 /* TQM ring page directory. */
17610 uint64_t tqm_ring10_page_dir;
17611 /* Number of Tx KTLS context entries. */
17612 uint32_t tkc_num_entries;
17613 /* Number of Rx KTLS context entries. */
17614 uint32_t rkc_num_entries;
17615 /* Tx KTLS context page directory. */
17616 uint64_t tkc_page_dir;
17617 /* Rx KTLS context page directory. */
17618 uint64_t rkc_page_dir;
17619 /* Tx KTLS context page size and level. */
17620 uint8_t tkc_pg_size_tkc_lvl;
17621 /* Tx KTLS context PBL indirect levels. */
17622 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \
17624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0
17625 /* PBL pointer is physical start address. */
17626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \
17628 /* PBL pointer points to PTE table. */
17629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \
17632 * PBL pointer points to PDE table with each entry pointing to
17635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \
17637 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \
17638 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2
17639 /* Tx KTLS context page size. */
17640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \
17642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4
17644 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \
17645 (UINT32_C(0x0) << 4)
17647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \
17648 (UINT32_C(0x1) << 4)
17650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \
17651 (UINT32_C(0x2) << 4)
17653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \
17654 (UINT32_C(0x3) << 4)
17656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \
17657 (UINT32_C(0x4) << 4)
17659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \
17660 (UINT32_C(0x5) << 4)
17661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \
17662 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G
17663 /* Rx KTLS context page size and level. */
17664 uint8_t rkc_pg_size_rkc_lvl;
17665 /* Rx KTLS context PBL indirect levels. */
17666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \
17668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0
17669 /* PBL pointer is physical start address. */
17670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \
17672 /* PBL pointer points to PTE table. */
17673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \
17676 * PBL pointer points to PDE table with each entry pointing to
17679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \
17681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \
17682 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2
17683 /* Rx KTLS context page size. */
17684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \
17686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4
17688 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \
17689 (UINT32_C(0x0) << 4)
17691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \
17692 (UINT32_C(0x1) << 4)
17694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \
17695 (UINT32_C(0x2) << 4)
17697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \
17698 (UINT32_C(0x3) << 4)
17700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \
17701 (UINT32_C(0x4) << 4)
17703 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \
17704 (UINT32_C(0x5) << 4)
17705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \
17706 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G
17707 uint8_t unused_1[5];
17709 * This field is used in Output records to indicate that the output
17710 * is completely written to RAM. This field should be read as 1
17711 * to indicate that the output has been completely written.
17712 * When writing a command completion or response to an internal
17713 * processor, the order of writes has to be such that this field
17719 /****************************
17720 * hwrm_error_recovery_qcfg *
17721 ****************************/
17724 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
17725 struct hwrm_error_recovery_qcfg_input {
17726 /* The HWRM command request type. */
17729 * The completion ring to send the completion event on. This should
17730 * be the NQ ID returned from the `nq_alloc` HWRM command.
17732 uint16_t cmpl_ring;
17734 * The sequence ID is used by the driver for tracking multiple
17735 * commands. This ID is treated as opaque data by the firmware and
17736 * the value is returned in the `hwrm_resp_hdr` upon completion.
17740 * The target ID of the command:
17741 * * 0x0-0xFFF8 - The function ID
17742 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17743 * * 0xFFFD - Reserved for user-space HWRM interface
17746 uint16_t target_id;
17748 * A physical address pointer pointing to a host buffer that the
17749 * command's response data will be written. This can be either a host
17750 * physical address (HPA) or a guest physical address (GPA) and must
17751 * point to a physically contiguous block of memory.
17753 uint64_t resp_addr;
17754 uint8_t unused_0[8];
17757 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
17758 struct hwrm_error_recovery_qcfg_output {
17759 /* The specific error status for the command. */
17760 uint16_t error_code;
17761 /* The HWRM command request type. */
17763 /* The sequence ID from the original command. */
17765 /* The length of the response data in number of bytes. */
17769 * When this flag is set to 1, error recovery will be initiated
17770 * through master function driver.
17772 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
17774 * When this flag is set to 1, error recovery will be performed
17775 * through Co processor.
17777 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
17779 * Driver Polling frequency. This value is in units of 100msec.
17780 * Typical value would be 10 to indicate 1sec.
17781 * Drivers can poll FW health status, Heartbeat, reset_counter with
17784 uint32_t driver_polling_freq;
17786 * This value is in units of 100msec.
17787 * Typical value would be 30 to indicate 3sec.
17788 * Master function wait period from detecting a fatal error to
17789 * initiating reset. In this time period Master PF expects every
17790 * active driver will detect fatal error.
17792 uint32_t master_func_wait_period;
17794 * This value is in units of 100msec.
17795 * Typical value would be 50 to indicate 5sec.
17796 * Normal function wait period from fatal error detection to
17797 * polling FW health status. In this time period, drivers should not
17798 * do any PCIe MMIO transaction and should not send any HWRM commands.
17800 uint32_t normal_func_wait_period;
17802 * This value is in units of 100msec.
17803 * Typical value would be 20 to indicate 2sec.
17804 * This field indicates that, master function wait period after chip
17805 * reset. After this time, master function should reinitialize with
17808 uint32_t master_func_wait_period_after_reset;
17810 * This value is in units of 100msec.
17811 * Typical value would be 60 to indicate 6sec.
17812 * This field is applicable to both master and normal functions.
17813 * Even after chip reset, if FW status not changed to ready,
17814 * then all the functions can poll for this much time and bailout.
17816 uint32_t max_bailout_time_after_reset;
17818 * FW health status register.
17819 * Lower 2 bits indicates address space location and upper 30 bits
17820 * indicates upper 30bits of the register address.
17821 * A value of 0xFFFF-FFFF indicates this register does not exist.
17823 uint32_t fw_health_status_reg;
17824 /* Lower 2 bits indicates address space location. */
17825 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
17827 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
17830 * If value is 0, this register is located in PCIe config space.
17831 * Drivers have to map appropriate window to access this
17834 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
17837 * If value is 1, this register is located in GRC address space.
17838 * Drivers have to map appropriate window to access this
17841 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
17844 * If value is 2, this register is located in first BAR address
17845 * space. Drivers have to map appropriate window to access this
17848 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
17851 * If value is 3, this register is located in second BAR address
17852 * space. Drivers have to map appropriate window to access this
17853 * Drivers have to map appropriate window to access this
17856 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
17858 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
17859 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
17860 /* Upper 30bits of the register address. */
17861 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
17862 UINT32_C(0xfffffffc)
17863 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
17866 * FW HeartBeat register.
17867 * Lower 2 bits indicates address space location and upper 30 bits
17868 * indicates actual address.
17869 * A value of 0xFFFF-FFFF indicates this register does not exist.
17871 uint32_t fw_heartbeat_reg;
17872 /* Lower 2 bits indicates address space location. */
17873 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
17875 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
17878 * If value is 0, this register is located in PCIe config space.
17879 * Drivers have to map appropriate window to access this
17882 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
17885 * If value is 1, this register is located in GRC address space.
17886 * Drivers have to map appropriate window to access this
17889 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
17892 * If value is 2, this register is located in first BAR address
17893 * space. Drivers have to map appropriate window to access this
17896 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
17899 * If value is 3, this register is located in second BAR address
17900 * space. Drivers have to map appropriate window to access this
17903 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
17905 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
17906 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
17907 /* Upper 30bits of the register address. */
17908 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
17909 UINT32_C(0xfffffffc)
17910 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
17913 * FW reset counter.
17914 * Lower 2 bits indicates address space location and upper 30 bits
17915 * indicates actual address.
17916 * A value of 0xFFFF-FFFF indicates this register does not exist.
17918 uint32_t fw_reset_cnt_reg;
17919 /* Lower 2 bits indicates address space location. */
17920 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
17922 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
17925 * If value is 0, this register is located in PCIe config space.
17926 * Drivers have to map appropriate window to access this
17929 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
17932 * If value is 1, this register is located in GRC address space.
17933 * Drivers have to map appropriate window to access this
17936 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
17939 * If value is 2, this register is located in first BAR address
17940 * space. Drivers have to map appropriate window to access this
17943 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
17946 * If value is 3, this register is located in second BAR address
17947 * space. Drivers have to map appropriate window to access this
17950 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
17952 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
17953 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
17954 /* Upper 30bits of the register address. */
17955 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
17956 UINT32_C(0xfffffffc)
17957 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
17960 * Reset Inprogress Register address for PFs.
17961 * Lower 2 bits indicates address space location and upper 30 bits
17962 * indicates actual address.
17963 * A value of 0xFFFF-FFFF indicates this register does not exist.
17965 uint32_t reset_inprogress_reg;
17966 /* Lower 2 bits indicates address space location. */
17967 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
17969 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
17972 * If value is 0, this register is located in PCIe config space.
17973 * Drivers have to map appropriate window to access this
17976 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
17979 * If value is 1, this register is located in GRC address space.
17980 * Drivers have to map appropriate window to access this
17983 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
17986 * If value is 2, this register is located in first BAR address
17987 * space. Drivers have to map appropriate window to access this
17990 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
17993 * If value is 3, this register is located in second BAR address
17994 * space. Drivers have to map appropriate window to access this
17997 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
17999 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
18000 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
18001 /* Upper 30bits of the register address. */
18002 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
18003 UINT32_C(0xfffffffc)
18004 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
18006 /* This field indicates the mask value for reset_inprogress_reg. */
18007 uint32_t reset_inprogress_reg_mask;
18008 uint8_t unused_0[3];
18010 * Array of registers and value count to reset the Chip
18011 * Each array count has reset_reg, reset_reg_val, delay_after_reset
18012 * in TLV format. Depending upon Chip type, number of reset registers
18013 * will vary. Drivers have to write reset_reg_val in the reset_reg
18014 * location in the same sequence in order to recover from a fatal
18017 uint8_t reg_array_cnt;
18020 * Lower 2 bits indicates address space location and upper 30 bits
18021 * indicates actual address.
18022 * A value of 0xFFFF-FFFF indicates this register does not exist.
18024 uint32_t reset_reg[16];
18025 /* Lower 2 bits indicates address space location. */
18026 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
18028 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
18030 * If value is 0, this register is located in PCIe config space.
18031 * Drivers have to map appropriate window to access this
18034 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
18037 * If value is 1, this register is located in GRC address space.
18038 * Drivers have to map appropriate window to access this
18041 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
18044 * If value is 2, this register is located in first BAR address
18045 * space. Drivers have to map appropriate window to access this
18048 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
18051 * If value is 3, this register is located in second BAR address
18052 * space. Drivers have to map appropriate window to access this
18055 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
18057 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
18058 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
18059 /* Upper 30bits of the register address. */
18060 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
18061 UINT32_C(0xfffffffc)
18062 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
18063 /* Value to be written in reset_reg to reset the controller. */
18064 uint32_t reset_reg_val[16];
18066 * This value is in units of 1msec.
18067 * Typical value would be 10 to indicate 10msec.
18068 * Some of the operations like Core reset require delay before
18069 * accessing PCIE MMIO register space.
18070 * If this value is non-zero, drivers have to wait for
18071 * this much time after writing reset_reg_val in reset_reg.
18073 uint8_t delay_after_reset[16];
18075 * Error recovery counter.
18076 * Lower 2 bits indicates address space location and upper 30 bits
18077 * indicates actual address.
18078 * A value of 0xFFFF-FFFF indicates this register does not exist.
18080 uint32_t err_recovery_cnt_reg;
18081 /* Lower 2 bits indicates address space location. */
18082 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
18084 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
18087 * If value is 0, this register is located in PCIe config space.
18088 * Drivers have to map appropriate window to access this
18091 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
18094 * If value is 1, this register is located in GRC address space.
18095 * Drivers have to map appropriate window to access this
18098 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
18101 * If value is 2, this register is located in first BAR address
18102 * space. Drivers have to map appropriate window to access this
18105 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
18108 * If value is 3, this register is located in second BAR address
18109 * space. Drivers have to map appropriate window to access this
18112 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
18114 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
18115 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
18116 /* Upper 30bits of the register address. */
18117 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
18118 UINT32_C(0xfffffffc)
18119 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
18121 uint8_t unused_1[3];
18123 * This field is used in Output records to indicate that the output
18124 * is completely written to RAM. This field should be read as '1'
18125 * to indicate that the output has been completely written.
18126 * When writing a command completion or response to an internal
18127 * processor, the order of writes has to be such that this field
18133 /***************************
18134 * hwrm_func_echo_response *
18135 ****************************/
18138 /* hwrm_func_echo_response_input (size:192b/24B) */
18139 struct hwrm_func_echo_response_input {
18140 /* The HWRM command request type. */
18143 * The completion ring to send the completion event on. This should
18144 * be the NQ ID returned from the `nq_alloc` HWRM command.
18146 uint16_t cmpl_ring;
18148 * The sequence ID is used by the driver for tracking multiple
18149 * commands. This ID is treated as opaque data by the firmware and
18150 * the value is returned in the `hwrm_resp_hdr` upon completion.
18154 * The target ID of the command:
18155 * 0x0-0xFFF8 - The function ID
18156 * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18157 * 0xFFFD - Reserved for user-space HWRM interface
18160 uint16_t target_id;
18162 * A physical address pointer pointing to a host buffer that the
18163 * command's response data will be written. This can be either a host
18164 * physical address (HPA) or a guest physical address (GPA) and must
18165 * point to a physically contiguous block of memory.
18167 uint64_t resp_addr;
18168 uint32_t event_data1;
18169 uint32_t event_data2;
18172 /* hwrm_func_echo_response_output (size:128b/16B) */
18173 struct hwrm_func_echo_response_output {
18174 /* The specific error status for the command. */
18175 uint16_t error_code;
18176 /* The HWRM command request type. */
18178 /* The sequence ID from the original command. */
18180 /* The length of the response data in number of bytes. */
18182 uint8_t unused_0[7];
18184 * This field is used in Output records to indicate that the output
18185 * is completely written to RAM. This field should be read as '1'
18186 * to indicate that the output has been completely written.
18187 * When writing a command completion or response to an internal processor,
18188 * the order of writes has to be such that this field is written last.
18193 /***********************
18194 * hwrm_func_vlan_qcfg *
18195 ***********************/
18198 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
18199 struct hwrm_func_vlan_qcfg_input {
18200 /* The HWRM command request type. */
18203 * The completion ring to send the completion event on. This should
18204 * be the NQ ID returned from the `nq_alloc` HWRM command.
18206 uint16_t cmpl_ring;
18208 * The sequence ID is used by the driver for tracking multiple
18209 * commands. This ID is treated as opaque data by the firmware and
18210 * the value is returned in the `hwrm_resp_hdr` upon completion.
18214 * The target ID of the command:
18215 * * 0x0-0xFFF8 - The function ID
18216 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18217 * * 0xFFFD - Reserved for user-space HWRM interface
18220 uint16_t target_id;
18222 * A physical address pointer pointing to a host buffer that the
18223 * command's response data will be written. This can be either a host
18224 * physical address (HPA) or a guest physical address (GPA) and must
18225 * point to a physically contiguous block of memory.
18227 uint64_t resp_addr;
18229 * Function ID of the function that is being
18231 * If set to 0xFF... (All Fs), then the configuration is
18232 * for the requesting function.
18235 uint8_t unused_0[6];
18238 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
18239 struct hwrm_func_vlan_qcfg_output {
18240 /* The specific error status for the command. */
18241 uint16_t error_code;
18242 /* The HWRM command request type. */
18244 /* The sequence ID from the original command. */
18246 /* The length of the response data in number of bytes. */
18249 /* S-TAG VLAN identifier configured for the function. */
18251 /* S-TAG PCP value configured for the function. */
18255 * S-TAG TPID value configured for the function. This field is specified in
18256 * network byte order.
18258 uint16_t stag_tpid;
18259 /* C-TAG VLAN identifier configured for the function. */
18261 /* C-TAG PCP value configured for the function. */
18265 * C-TAG TPID value configured for the function. This field is specified in
18266 * network byte order.
18268 uint16_t ctag_tpid;
18273 uint8_t unused_3[3];
18275 * This field is used in Output records to indicate that the output
18276 * is completely written to RAM. This field should be read as '1'
18277 * to indicate that the output has been completely written.
18278 * When writing a command completion or response to an internal processor,
18279 * the order of writes has to be such that this field is written last.
18284 /**********************
18285 * hwrm_func_vlan_cfg *
18286 **********************/
18289 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
18290 struct hwrm_func_vlan_cfg_input {
18291 /* The HWRM command request type. */
18294 * The completion ring to send the completion event on. This should
18295 * be the NQ ID returned from the `nq_alloc` HWRM command.
18297 uint16_t cmpl_ring;
18299 * The sequence ID is used by the driver for tracking multiple
18300 * commands. This ID is treated as opaque data by the firmware and
18301 * the value is returned in the `hwrm_resp_hdr` upon completion.
18305 * The target ID of the command:
18306 * * 0x0-0xFFF8 - The function ID
18307 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18308 * * 0xFFFD - Reserved for user-space HWRM interface
18311 uint16_t target_id;
18313 * A physical address pointer pointing to a host buffer that the
18314 * command's response data will be written. This can be either a host
18315 * physical address (HPA) or a guest physical address (GPA) and must
18316 * point to a physically contiguous block of memory.
18318 uint64_t resp_addr;
18320 * Function ID of the function that is being
18322 * If set to 0xFF... (All Fs), then the configuration is
18323 * for the requesting function.
18326 uint8_t unused_0[2];
18329 * This bit must be '1' for the stag_vid field to be
18332 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
18334 * This bit must be '1' for the ctag_vid field to be
18337 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
18339 * This bit must be '1' for the stag_pcp field to be
18342 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
18344 * This bit must be '1' for the ctag_pcp field to be
18347 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
18349 * This bit must be '1' for the stag_tpid field to be
18352 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
18354 * This bit must be '1' for the ctag_tpid field to be
18357 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
18358 /* S-TAG VLAN identifier configured for the function. */
18360 /* S-TAG PCP value configured for the function. */
18364 * S-TAG TPID value configured for the function. This field is specified in
18365 * network byte order.
18367 uint16_t stag_tpid;
18368 /* C-TAG VLAN identifier configured for the function. */
18370 /* C-TAG PCP value configured for the function. */
18374 * C-TAG TPID value configured for the function. This field is specified in
18375 * network byte order.
18377 uint16_t ctag_tpid;
18382 uint8_t unused_3[4];
18385 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
18386 struct hwrm_func_vlan_cfg_output {
18387 /* The specific error status for the command. */
18388 uint16_t error_code;
18389 /* The HWRM command request type. */
18391 /* The sequence ID from the original command. */
18393 /* The length of the response data in number of bytes. */
18395 uint8_t unused_0[7];
18397 * This field is used in Output records to indicate that the output
18398 * is completely written to RAM. This field should be read as '1'
18399 * to indicate that the output has been completely written.
18400 * When writing a command completion or response to an internal processor,
18401 * the order of writes has to be such that this field is written last.
18406 /*******************************
18407 * hwrm_func_vf_vnic_ids_query *
18408 *******************************/
18411 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
18412 struct hwrm_func_vf_vnic_ids_query_input {
18413 /* The HWRM command request type. */
18416 * The completion ring to send the completion event on. This should
18417 * be the NQ ID returned from the `nq_alloc` HWRM command.
18419 uint16_t cmpl_ring;
18421 * The sequence ID is used by the driver for tracking multiple
18422 * commands. This ID is treated as opaque data by the firmware and
18423 * the value is returned in the `hwrm_resp_hdr` upon completion.
18427 * The target ID of the command:
18428 * * 0x0-0xFFF8 - The function ID
18429 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18430 * * 0xFFFD - Reserved for user-space HWRM interface
18433 uint16_t target_id;
18435 * A physical address pointer pointing to a host buffer that the
18436 * command's response data will be written. This can be either a host
18437 * physical address (HPA) or a guest physical address (GPA) and must
18438 * point to a physically contiguous block of memory.
18440 uint64_t resp_addr;
18442 * This value is used to identify a Virtual Function (VF).
18443 * The scope of VF ID is local within a PF.
18446 uint8_t unused_0[2];
18447 /* Max number of vnic ids in vnic id table */
18448 uint32_t max_vnic_id_cnt;
18449 /* This is the address for VF VNIC ID table */
18450 uint64_t vnic_id_tbl_addr;
18453 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
18454 struct hwrm_func_vf_vnic_ids_query_output {
18455 /* The specific error status for the command. */
18456 uint16_t error_code;
18457 /* The HWRM command request type. */
18459 /* The sequence ID from the original command. */
18461 /* The length of the response data in number of bytes. */
18464 * Actual number of vnic ids
18466 * Each VNIC ID is written as a 32-bit number.
18468 uint32_t vnic_id_cnt;
18469 uint8_t unused_0[3];
18471 * This field is used in Output records to indicate that the output
18472 * is completely written to RAM. This field should be read as '1'
18473 * to indicate that the output has been completely written.
18474 * When writing a command completion or response to an internal processor,
18475 * the order of writes has to be such that this field is written last.
18480 /***********************
18481 * hwrm_func_vf_bw_cfg *
18482 ***********************/
18485 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
18486 struct hwrm_func_vf_bw_cfg_input {
18487 /* The HWRM command request type. */
18490 * The completion ring to send the completion event on. This should
18491 * be the NQ ID returned from the `nq_alloc` HWRM command.
18493 uint16_t cmpl_ring;
18495 * The sequence ID is used by the driver for tracking multiple
18496 * commands. This ID is treated as opaque data by the firmware and
18497 * the value is returned in the `hwrm_resp_hdr` upon completion.
18501 * The target ID of the command:
18502 * * 0x0-0xFFF8 - The function ID
18503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18504 * * 0xFFFD - Reserved for user-space HWRM interface
18507 uint16_t target_id;
18509 * A physical address pointer pointing to a host buffer that the
18510 * command's response data will be written. This can be either a host
18511 * physical address (HPA) or a guest physical address (GPA) and must
18512 * point to a physically contiguous block of memory.
18514 uint64_t resp_addr;
18516 * The number of VF functions that are being configured.
18517 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
18520 uint16_t unused[3];
18521 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
18523 /* The physical VF id the adjustment will be made to. */
18524 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
18525 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
18527 * This field configures the rate scale percentage of the VF as specified
18528 * by the physical VF id.
18530 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
18531 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
18532 /* 0% of the max tx rate */
18533 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
18534 (UINT32_C(0x0) << 12)
18535 /* 6.66% of the max tx rate */
18536 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
18537 (UINT32_C(0x1) << 12)
18538 /* 13.33% of the max tx rate */
18539 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
18540 (UINT32_C(0x2) << 12)
18541 /* 20% of the max tx rate */
18542 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
18543 (UINT32_C(0x3) << 12)
18544 /* 26.66% of the max tx rate */
18545 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
18546 (UINT32_C(0x4) << 12)
18547 /* 33% of the max tx rate */
18548 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
18549 (UINT32_C(0x5) << 12)
18550 /* 40% of the max tx rate */
18551 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
18552 (UINT32_C(0x6) << 12)
18553 /* 46.66% of the max tx rate */
18554 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
18555 (UINT32_C(0x7) << 12)
18556 /* 53.33% of the max tx rate */
18557 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
18558 (UINT32_C(0x8) << 12)
18559 /* 60% of the max tx rate */
18560 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
18561 (UINT32_C(0x9) << 12)
18562 /* 66.66% of the max tx rate */
18563 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
18564 (UINT32_C(0xa) << 12)
18565 /* 53.33% of the max tx rate */
18566 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
18567 (UINT32_C(0xb) << 12)
18568 /* 80% of the max tx rate */
18569 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
18570 (UINT32_C(0xc) << 12)
18571 /* 86.66% of the max tx rate */
18572 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
18573 (UINT32_C(0xd) << 12)
18574 /* 93.33% of the max tx rate */
18575 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
18576 (UINT32_C(0xe) << 12)
18577 /* 100% of the max tx rate */
18578 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
18579 (UINT32_C(0xf) << 12)
18580 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
18581 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
18584 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
18585 struct hwrm_func_vf_bw_cfg_output {
18586 /* The specific error status for the command. */
18587 uint16_t error_code;
18588 /* The HWRM command request type. */
18590 /* The sequence ID from the original command. */
18592 /* The length of the response data in number of bytes. */
18594 uint8_t unused_0[7];
18596 * This field is used in Output records to indicate that the output
18597 * is completely written to RAM. This field should be read as '1'
18598 * to indicate that the output has been completely written.
18599 * When writing a command completion or response to an internal processor,
18600 * the order of writes has to be such that this field is written last.
18605 /************************
18606 * hwrm_func_vf_bw_qcfg *
18607 ************************/
18610 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
18611 struct hwrm_func_vf_bw_qcfg_input {
18612 /* The HWRM command request type. */
18615 * The completion ring to send the completion event on. This should
18616 * be the NQ ID returned from the `nq_alloc` HWRM command.
18618 uint16_t cmpl_ring;
18620 * The sequence ID is used by the driver for tracking multiple
18621 * commands. This ID is treated as opaque data by the firmware and
18622 * the value is returned in the `hwrm_resp_hdr` upon completion.
18626 * The target ID of the command:
18627 * * 0x0-0xFFF8 - The function ID
18628 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18629 * * 0xFFFD - Reserved for user-space HWRM interface
18632 uint16_t target_id;
18634 * A physical address pointer pointing to a host buffer that the
18635 * command's response data will be written. This can be either a host
18636 * physical address (HPA) or a guest physical address (GPA) and must
18637 * point to a physically contiguous block of memory.
18639 uint64_t resp_addr;
18641 * The number of VF functions that are being queried.
18642 * The inline response space allows the host to query up to 50 VFs'
18643 * rate scale percentage
18646 uint16_t unused[3];
18647 /* These 16-bit fields contain the VF fid */
18649 /* The physical VF id of interest */
18650 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
18651 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
18654 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
18655 struct hwrm_func_vf_bw_qcfg_output {
18656 /* The specific error status for the command. */
18657 uint16_t error_code;
18658 /* The HWRM command request type. */
18660 /* The sequence ID from the original command. */
18662 /* The length of the response data in number of bytes. */
18665 * The number of VF functions that are being queried.
18666 * The inline response space allows the host to query up to 50 VFs' rate
18670 uint16_t unused[3];
18671 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
18673 /* The physical VF id the adjustment will be made to. */
18674 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
18675 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
18677 * This field configures the rate scale percentage of the VF as specified
18678 * by the physical VF id.
18680 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
18681 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
18682 /* 0% of the max tx rate */
18683 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
18684 (UINT32_C(0x0) << 12)
18685 /* 6.66% of the max tx rate */
18686 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
18687 (UINT32_C(0x1) << 12)
18688 /* 13.33% of the max tx rate */
18689 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
18690 (UINT32_C(0x2) << 12)
18691 /* 20% of the max tx rate */
18692 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
18693 (UINT32_C(0x3) << 12)
18694 /* 26.66% of the max tx rate */
18695 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
18696 (UINT32_C(0x4) << 12)
18697 /* 33% of the max tx rate */
18698 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
18699 (UINT32_C(0x5) << 12)
18700 /* 40% of the max tx rate */
18701 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
18702 (UINT32_C(0x6) << 12)
18703 /* 46.66% of the max tx rate */
18704 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
18705 (UINT32_C(0x7) << 12)
18706 /* 53.33% of the max tx rate */
18707 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
18708 (UINT32_C(0x8) << 12)
18709 /* 60% of the max tx rate */
18710 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
18711 (UINT32_C(0x9) << 12)
18712 /* 66.66% of the max tx rate */
18713 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
18714 (UINT32_C(0xa) << 12)
18715 /* 53.33% of the max tx rate */
18716 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
18717 (UINT32_C(0xb) << 12)
18718 /* 80% of the max tx rate */
18719 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
18720 (UINT32_C(0xc) << 12)
18721 /* 86.66% of the max tx rate */
18722 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
18723 (UINT32_C(0xd) << 12)
18724 /* 93.33% of the max tx rate */
18725 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
18726 (UINT32_C(0xe) << 12)
18727 /* 100% of the max tx rate */
18728 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
18729 (UINT32_C(0xf) << 12)
18730 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
18731 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
18732 uint8_t unused_0[7];
18734 * This field is used in Output records to indicate that the output
18735 * is completely written to RAM. This field should be read as '1'
18736 * to indicate that the output has been completely written.
18737 * When writing a command completion or response to an internal processor,
18738 * the order of writes has to be such that this field is written last.
18743 /***************************
18744 * hwrm_func_drv_if_change *
18745 ***************************/
18748 /* hwrm_func_drv_if_change_input (size:192b/24B) */
18749 struct hwrm_func_drv_if_change_input {
18750 /* The HWRM command request type. */
18753 * The completion ring to send the completion event on. This should
18754 * be the NQ ID returned from the `nq_alloc` HWRM command.
18756 uint16_t cmpl_ring;
18758 * The sequence ID is used by the driver for tracking multiple
18759 * commands. This ID is treated as opaque data by the firmware and
18760 * the value is returned in the `hwrm_resp_hdr` upon completion.
18764 * The target ID of the command:
18765 * * 0x0-0xFFF8 - The function ID
18766 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18767 * * 0xFFFD - Reserved for user-space HWRM interface
18770 uint16_t target_id;
18772 * A physical address pointer pointing to a host buffer that the
18773 * command's response data will be written. This can be either a host
18774 * physical address (HPA) or a guest physical address (GPA) and must
18775 * point to a physically contiguous block of memory.
18777 uint64_t resp_addr;
18780 * When this bit is '1', the function driver is indicating
18781 * that the IF state is changing to UP state. The call should
18782 * be made at the beginning of the driver's open call before
18783 * resources are allocated. After making the call, the driver
18784 * should check the response to see if any resources may have
18785 * changed (see the response below). If the driver fails
18786 * the open call, the driver should make this call again with
18787 * this bit cleared to indicate that the IF state is not UP.
18788 * During the driver's close call when the IF state is changing
18789 * to DOWN, the driver should make this call with the bit cleared
18790 * after all resources have been freed.
18792 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
18796 /* hwrm_func_drv_if_change_output (size:128b/16B) */
18797 struct hwrm_func_drv_if_change_output {
18798 /* The specific error status for the command. */
18799 uint16_t error_code;
18800 /* The HWRM command request type. */
18802 /* The sequence ID from the original command. */
18804 /* The length of the response data in number of bytes. */
18808 * When this bit is '1', it indicates that the resources reserved
18809 * for this function may have changed. The driver should check
18810 * resource capabilities and reserve resources again before
18811 * allocating resources.
18813 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
18816 * When this bit is '1', it indicates that the firmware got changed / reset.
18817 * The driver should do complete re-initialization when that bit is set.
18819 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
18821 uint8_t unused_0[3];
18823 * This field is used in Output records to indicate that the output
18824 * is completely written to RAM. This field should be read as '1'
18825 * to indicate that the output has been completely written.
18826 * When writing a command completion or response to an internal processor,
18827 * the order of writes has to be such that this field is written last.
18832 /*******************************
18833 * hwrm_func_host_pf_ids_query *
18834 *******************************/
18837 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
18838 struct hwrm_func_host_pf_ids_query_input {
18839 /* The HWRM command request type. */
18842 * The completion ring to send the completion event on. This should
18843 * be the NQ ID returned from the `nq_alloc` HWRM command.
18845 uint16_t cmpl_ring;
18847 * The sequence ID is used by the driver for tracking multiple
18848 * commands. This ID is treated as opaque data by the firmware and
18849 * the value is returned in the `hwrm_resp_hdr` upon completion.
18853 * The target ID of the command:
18854 * * 0x0-0xFFF8 - The function ID
18855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18856 * * 0xFFFD - Reserved for user-space HWRM interface
18859 uint16_t target_id;
18861 * A physical address pointer pointing to a host buffer that the
18862 * command's response data will be written. This can be either a host
18863 * physical address (HPA) or a guest physical address (GPA) and must
18864 * point to a physically contiguous block of memory.
18866 uint64_t resp_addr;
18869 * # If this bit is set to '1', the query will contain PF(s)
18870 * belongs to SOC host.
18872 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
18874 * # If this bit is set to '1', the query will contain PF(s)
18875 * belongs to EP0 host.
18877 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
18879 * # If this bit is set to '1', the query will contain PF(s)
18880 * belongs to EP1 host.
18882 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
18884 * # If this bit is set to '1', the query will contain PF(s)
18885 * belongs to EP2 host.
18887 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
18889 * # If this bit is set to '1', the query will contain PF(s)
18890 * belongs to EP3 host.
18892 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
18894 * This provides a filter of what PF(s) will be returned in the
18899 * all available PF(s) belong to the host(s) (defined in the
18900 * host field). This includes the hidden PFs.
18902 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
18904 * all available PF(s) belong to the host(s) (defined in the
18905 * host field) that is available for L2 traffic.
18907 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
18909 * all available PF(s) belong to the host(s) (defined in the
18910 * host field) that is available for ROCE traffic.
18912 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
18913 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
18914 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
18915 uint8_t unused_1[6];
18918 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
18919 struct hwrm_func_host_pf_ids_query_output {
18920 /* The specific error status for the command. */
18921 uint16_t error_code;
18922 /* The HWRM command request type. */
18924 /* The sequence ID from the original command. */
18926 /* The length of the response data in number of bytes. */
18928 /* This provides the first PF ID of the device. */
18929 uint16_t first_pf_id;
18930 uint16_t pf_ordinal_mask;
18932 * When this bit is '1', it indicates first PF belongs to one of
18933 * the hosts defined in the input request.
18935 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
18938 * When this bit is '1', it indicates 2nd PF belongs to one of the
18939 * hosts defined in the input request.
18941 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
18944 * When this bit is '1', it indicates 3rd PF belongs to one of the
18945 * hosts defined in the input request.
18947 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
18950 * When this bit is '1', it indicates 4th PF belongs to one of the
18951 * hosts defined in the input request.
18953 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
18956 * When this bit is '1', it indicates 5th PF belongs to one of the
18957 * hosts defined in the input request.
18959 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
18962 * When this bit is '1', it indicates 6th PF belongs to one of the
18963 * hosts defined in the input request.
18965 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
18968 * When this bit is '1', it indicates 7th PF belongs to one of the
18969 * hosts defined in the input request.
18971 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
18974 * When this bit is '1', it indicates 8th PF belongs to one of the
18975 * hosts defined in the input request.
18977 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
18980 * When this bit is '1', it indicates 9th PF belongs to one of the
18981 * hosts defined in the input request.
18983 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
18986 * When this bit is '1', it indicates 10th PF belongs to one of the
18987 * hosts defined in the input request.
18989 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
18992 * When this bit is '1', it indicates 11th PF belongs to one of the
18993 * hosts defined in the input request.
18995 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
18998 * When this bit is '1', it indicates 12th PF belongs to one of the
18999 * hosts defined in the input request.
19001 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
19004 * When this bit is '1', it indicates 13th PF belongs to one of the
19005 * hosts defined in the input request.
19007 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
19010 * When this bit is '1', it indicates 14th PF belongs to one of the
19011 * hosts defined in the input request.
19013 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
19016 * When this bit is '1', it indicates 15th PF belongs to one of the
19017 * hosts defined in the input request.
19019 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
19022 * When this bit is '1', it indicates 16th PF belongs to one of the
19023 * hosts defined in the input request.
19025 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
19027 uint8_t unused_1[3];
19029 * This field is used in Output records to indicate that the output
19030 * is completely written to RAM. This field should be read as '1'
19031 * to indicate that the output has been completely written.
19032 * When writing a command completion or response to an internal processor,
19033 * the order of writes has to be such that this field is written last.
19038 /*********************
19039 * hwrm_func_spd_cfg *
19040 *********************/
19043 /* hwrm_func_spd_cfg_input (size:384b/48B) */
19044 struct hwrm_func_spd_cfg_input {
19045 /* The HWRM command request type. */
19048 * The completion ring to send the completion event on. This should
19049 * be the NQ ID returned from the `nq_alloc` HWRM command.
19051 uint16_t cmpl_ring;
19053 * The sequence ID is used by the driver for tracking multiple
19054 * commands. This ID is treated as opaque data by the firmware and
19055 * the value is returned in the `hwrm_resp_hdr` upon completion.
19059 * The target ID of the command:
19060 * * 0x0-0xFFF8 - The function ID
19061 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19062 * * 0xFFFD - Reserved for user-space HWRM interface
19065 uint16_t target_id;
19067 * A physical address pointer pointing to a host buffer that the
19068 * command's response data will be written. This can be either a host
19069 * physical address (HPA) or a guest physical address (GPA) and must
19070 * point to a physically contiguous block of memory.
19072 uint64_t resp_addr;
19074 /* Set this bit is '1' to enable the SPD datapath forwarding. */
19075 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
19076 /* Set this bit is '1' to disable the SPD datapath forwarding. */
19077 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
19079 * Set this bit is '1' to enable the SPD datapath checksum
19082 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
19084 * Set this bit is '1' to disable the SPD datapath checksum
19087 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
19089 * Set this bit is '1' to enable the SPD datapath debug
19092 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
19094 * Set this bit is '1' to disable the SPD datapath debug
19097 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
19100 * This bit must be '1' for the ethertype field to be
19103 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
19106 * This bit must be '1' for the hash_mode_flags field to be
19109 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
19112 * This bit must be '1' for the hash_type field to be
19115 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
19118 * This bit must be '1' for the ring_tbl_addr field to be
19121 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
19124 * This bit must be '1' for the hash_key_tbl_addr field to be
19127 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
19130 * Ethertype value used in the encapsulated SPD packet header.
19131 * The user must choose a value that is not conflicting with
19132 * publicly defined ethertype values. By default, the ethertype
19133 * value of 0xffff is used if there is no user specified value.
19135 uint16_t ethertype;
19136 /* Flags to specify different RSS hash modes. */
19137 uint8_t hash_mode_flags;
19139 * When this bit is '1', it indicates using current RSS
19140 * hash mode setting configured in the device.
19142 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
19145 * When this bit is '1', it indicates requesting support of
19146 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19147 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19148 * packets, the RSS hash is computed over the normal
19149 * src/dest l3 and src/dest l4 headers.
19151 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19154 * When this bit is '1', it indicates requesting support of
19155 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19156 * tunnel packets. For none-tunnel packets, the RSS hash is
19157 * computed over the normal src/dest l3 headers.
19159 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19162 * When this bit is '1', it indicates requesting support of
19163 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19164 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19165 * packets, the RSS hash is computed over the normal
19166 * src/dest l3 and src/dest l4 headers.
19168 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19171 * When this bit is '1', it indicates requesting support of
19172 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19173 * tunnel packets. For none-tunnel packets, the RSS hash is
19174 * computed over the normal src/dest l3 headers.
19176 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19179 uint32_t hash_type;
19181 * When this bit is '1', the RSS hash shall be computed
19182 * over source and destination IPv4 addresses of IPv4
19185 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19187 * When this bit is '1', the RSS hash shall be computed
19188 * over source/destination IPv4 addresses and
19189 * source/destination ports of TCP/IPv4 packets.
19191 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19193 * When this bit is '1', the RSS hash shall be computed
19194 * over source/destination IPv4 addresses and
19195 * source/destination ports of UDP/IPv4 packets.
19197 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19199 * When this bit is '1', the RSS hash shall be computed
19200 * over source and destination IPv4 addresses of IPv6
19203 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19205 * When this bit is '1', the RSS hash shall be computed
19206 * over source/destination IPv6 addresses and
19207 * source/destination ports of TCP/IPv6 packets.
19209 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19211 * When this bit is '1', the RSS hash shall be computed
19212 * over source/destination IPv6 addresses and
19213 * source/destination ports of UDP/IPv6 packets.
19215 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19216 /* This is the address for rss ring group table */
19217 uint64_t ring_grp_tbl_addr;
19218 /* This is the address for rss hash key table */
19219 uint64_t hash_key_tbl_addr;
19222 /* hwrm_func_spd_cfg_output (size:128b/16B) */
19223 struct hwrm_func_spd_cfg_output {
19224 /* The specific error status for the command. */
19225 uint16_t error_code;
19226 /* The HWRM command request type. */
19228 /* The sequence ID from the original command. */
19230 /* The length of the response data in number of bytes. */
19232 uint8_t unused_0[7];
19234 * This field is used in Output records to indicate that the output
19235 * is completely written to RAM. This field should be read as '1'
19236 * to indicate that the output has been completely written.
19237 * When writing a command completion or response to an internal processor,
19238 * the order of writes has to be such that this field is written last.
19243 /**********************
19244 * hwrm_func_spd_qcfg *
19245 **********************/
19248 /* hwrm_func_spd_qcfg_input (size:128b/16B) */
19249 struct hwrm_func_spd_qcfg_input {
19250 /* The HWRM command request type. */
19253 * The completion ring to send the completion event on. This should
19254 * be the NQ ID returned from the `nq_alloc` HWRM command.
19256 uint16_t cmpl_ring;
19258 * The sequence ID is used by the driver for tracking multiple
19259 * commands. This ID is treated as opaque data by the firmware and
19260 * the value is returned in the `hwrm_resp_hdr` upon completion.
19264 * The target ID of the command:
19265 * * 0x0-0xFFF8 - The function ID
19266 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19267 * * 0xFFFD - Reserved for user-space HWRM interface
19270 uint16_t target_id;
19272 * A physical address pointer pointing to a host buffer that the
19273 * command's response data will be written. This can be either a host
19274 * physical address (HPA) or a guest physical address (GPA) and must
19275 * point to a physically contiguous block of memory.
19277 uint64_t resp_addr;
19280 /* hwrm_func_spd_qcfg_output (size:512b/64B) */
19281 struct hwrm_func_spd_qcfg_output {
19282 /* The specific error status for the command. */
19283 uint16_t error_code;
19284 /* The HWRM command request type. */
19286 /* The sequence ID from the original command. */
19288 /* The length of the response data in number of bytes. */
19292 * The SPD datapath forwarding is currently enabled when this
19293 * flag is set to '1'.
19295 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
19297 * The SPD datapath checksum feature is currently enabled when
19298 * this flag is set to '1'.
19300 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
19302 * The SPD datapath debug feature is currently enabled when
19303 * this flag is set to '1'.
19305 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
19306 uint32_t hash_type;
19308 * When this bit is '1', the RSS hash shall be computed
19309 * over source and destination IPv4 addresses of IPv4
19312 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19314 * When this bit is '1', the RSS hash shall be computed
19315 * over source/destination IPv4 addresses and
19316 * source/destination ports of TCP/IPv4 packets.
19318 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19320 * When this bit is '1', the RSS hash shall be computed
19321 * over source/destination IPv4 addresses and
19322 * source/destination ports of UDP/IPv4 packets.
19324 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19326 * When this bit is '1', the RSS hash shall be computed
19327 * over source and destination IPv4 addresses of IPv6
19330 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19332 * When this bit is '1', the RSS hash shall be computed
19333 * over source/destination IPv6 addresses and
19334 * source/destination ports of TCP/IPv6 packets.
19336 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19338 * When this bit is '1', the RSS hash shall be computed
19339 * over source/destination IPv6 addresses and
19340 * source/destination ports of UDP/IPv6 packets.
19342 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19343 /* This is the value of rss hash key */
19344 uint32_t hash_key[10];
19345 /* Flags to specify different RSS hash modes. */
19346 uint8_t hash_mode_flags;
19348 * When this bit is '1', it indicates using current RSS
19349 * hash mode setting configured in the device.
19351 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
19354 * When this bit is '1', it indicates requesting support of
19355 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19356 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19357 * packets, the RSS hash is computed over the normal
19358 * src/dest l3 and src/dest l4 headers.
19360 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19363 * When this bit is '1', it indicates requesting support of
19364 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19365 * tunnel packets. For none-tunnel packets, the RSS hash is
19366 * computed over the normal src/dest l3 headers.
19368 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19371 * When this bit is '1', it indicates requesting support of
19372 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19373 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19374 * packets, the RSS hash is computed over the normal
19375 * src/dest l3 and src/dest l4 headers.
19377 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19380 * When this bit is '1', it indicates requesting support of
19381 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19382 * tunnel packets. For none-tunnel packets, the RSS hash is
19383 * computed over the normal src/dest l3 headers.
19385 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19389 * Ethertype value used in the encapsulated SPD packet header.
19390 * The user must choose a value that is not conflicting with
19391 * publicly defined ethertype values. By default, the ethertype
19392 * value of 0xffff is used if there is no user specified value.
19394 uint16_t ethertype;
19395 uint8_t unused_2[3];
19397 * This field is used in Output records to indicate that the output
19398 * is completely written to RAM. This field should be read as '1'
19399 * to indicate that the output has been completely written.
19400 * When writing a command completion or response to an internal processor,
19401 * the order of writes has to be such that this field is written last.
19406 /*********************
19407 * hwrm_port_phy_cfg *
19408 *********************/
19411 /* hwrm_port_phy_cfg_input (size:448b/56B) */
19412 struct hwrm_port_phy_cfg_input {
19413 /* The HWRM command request type. */
19416 * The completion ring to send the completion event on. This should
19417 * be the NQ ID returned from the `nq_alloc` HWRM command.
19419 uint16_t cmpl_ring;
19421 * The sequence ID is used by the driver for tracking multiple
19422 * commands. This ID is treated as opaque data by the firmware and
19423 * the value is returned in the `hwrm_resp_hdr` upon completion.
19427 * The target ID of the command:
19428 * * 0x0-0xFFF8 - The function ID
19429 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19430 * * 0xFFFD - Reserved for user-space HWRM interface
19433 uint16_t target_id;
19435 * A physical address pointer pointing to a host buffer that the
19436 * command's response data will be written. This can be either a host
19437 * physical address (HPA) or a guest physical address (GPA) and must
19438 * point to a physically contiguous block of memory.
19440 uint64_t resp_addr;
19443 * When this bit is set to '1', the PHY for the port shall
19446 * # If this bit is set to 1, then the HWRM shall reset the
19447 * PHY after applying PHY configuration changes specified
19449 * # In order to guarantee that PHY configuration changes
19450 * specified in this command take effect, the HWRM
19451 * client should set this flag to 1.
19452 * # If this bit is not set to 1, then the HWRM may reset
19453 * the PHY depending on the current PHY configuration and
19454 * settings specified in this command.
19456 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
19458 /* deprecated bit. Do not use!!! */
19459 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
19462 * When this bit is set to '1', and the force_pam4_link_speed
19463 * bit in the 'enables' field is '0', the link shall be forced
19464 * to the force_link_speed value.
19466 * When this bit is set to '1', and the force_pam4_link_speed
19467 * bit in the 'enables' field is '1', the link shall be forced
19468 * to the force_pam4_link_speed value.
19470 * When this bit is set to '1', the HWRM client should
19471 * not enable any of the auto negotiation related
19472 * fields represented by auto_XXX fields in this command.
19473 * When this bit is set to '1' and the HWRM client has
19474 * enabled a auto_XXX field in this command, then the
19475 * HWRM shall ignore the enabled auto_XXX field.
19477 * When this bit is set to zero, the link
19478 * shall be allowed to autoneg.
19480 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
19483 * When this bit is set to '1', the auto-negotiation process
19484 * shall be restarted on the link.
19486 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
19489 * When this bit is set to '1', Energy Efficient Ethernet
19490 * (EEE) is requested to be enabled on this link.
19491 * If EEE is not supported on this port, then this flag
19492 * shall be ignored by the HWRM.
19494 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
19497 * When this bit is set to '1', Energy Efficient Ethernet
19498 * (EEE) is requested to be disabled on this link.
19499 * If EEE is not supported on this port, then this flag
19500 * shall be ignored by the HWRM.
19502 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
19505 * When this bit is set to '1' and EEE is enabled on this
19506 * link, then TX LPI is requested to be enabled on the link.
19507 * If EEE is not supported on this port, then this flag
19508 * shall be ignored by the HWRM.
19509 * If EEE is disabled on this port, then this flag shall be
19510 * ignored by the HWRM.
19512 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
19515 * When this bit is set to '1' and EEE is enabled on this
19516 * link, then TX LPI is requested to be disabled on the link.
19517 * If EEE is not supported on this port, then this flag
19518 * shall be ignored by the HWRM.
19519 * If EEE is disabled on this port, then this flag shall be
19520 * ignored by the HWRM.
19522 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
19525 * When set to 1, then the HWRM shall enable FEC autonegotitation
19526 * on this port if supported. When enabled, at least one of the
19527 * FEC modes must be advertised by enabling the fec_clause_74_enable,
19528 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
19529 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
19530 * of the FEC mode is currently enabled, the HWRM shall choose
19531 * a default advertisement setting.
19532 * The default advertisement setting can be queried by calling
19533 * hwrm_port_phy_qcfg. Note that the link speed must be
19534 * in autonegotiation mode for FEC autonegotiation to take effect.
19535 * When set to 0, then this flag shall be ignored.
19536 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
19539 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
19542 * When set to 1, then the HWRM shall disable FEC autonegotiation
19543 * on this port and use forced FEC mode. In forced FEC mode, one
19544 * or more FEC forced settings under the same clause can be set.
19545 * When set to 0, then this flag shall be ignored.
19546 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
19549 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
19552 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
19553 * on this port if supported, by advertising FEC CLAUSE 74 if
19554 * FEC autonegotiation is enabled or force enabled otherwise.
19555 * When set to 0, then this flag shall be ignored.
19556 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
19559 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
19562 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
19563 * on this port if supported, by not advertising FEC CLAUSE 74 if
19564 * FEC autonegotiation is enabled or force disabled otherwise.
19565 * When set to 0, then this flag shall be ignored.
19566 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
19569 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
19572 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
19573 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
19574 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
19575 * or force enabled otherwise. In forced FEC mode, this flag
19576 * will only take effect if the speed is NRZ. Additional
19577 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
19578 * in forced FEC mode.
19579 * When set to 0, then this flag shall be ignored.
19580 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
19583 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
19586 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
19587 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
19588 * not advertising RS(528,514) if FEC autonegotiation is enabled or
19589 * force disabled otherwise. When set to 0, then this flag shall be
19590 * ignored. If FEC RS(528,514) is not supported, then the HWRM
19591 * shall ignore this flag.
19593 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
19596 * When this bit is set to '1', the link shall be forced to
19599 * # When this bit is set to '1", all other
19600 * command input settings related to the link speed shall
19602 * Once the link state is forced down, it can be
19603 * explicitly cleared from that state by setting this flag
19605 * # If this flag is set to '0', then the link shall be
19606 * cleared from forced down state if the link is in forced
19608 * There may be conditions (e.g. out-of-band or sideband
19609 * configuration changes for the link) outside the scope
19610 * of the HWRM implementation that may clear forced down
19613 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
19616 * When set to 1, then the HWRM shall enable FEC RS544_1XN
19617 * on this port if supported, by advertising FEC RS544_1XN if
19618 * FEC autonegotiation is enabled or force enabled otherwise.
19619 * In forced mode, this flag will only take effect if the speed is
19620 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
19621 * HWRM shall choose one of the RS544 modes.
19622 * When set to 0, then this flag shall be ignored.
19623 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
19626 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
19629 * When set to 1, then the HWRM shall disable FEC RS544_1XN
19630 * on this port if supported, by not advertising FEC RS544_1XN if
19631 * FEC autonegotiation is enabled or force disabled otherwise.
19632 * When set to 0, then this flag shall be ignored.
19633 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
19636 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
19639 * When set to 1, then the HWRM shall enable FEC RS(544,514)
19640 * on this port if supported, by advertising FEC RS(544,514) if
19641 * FEC autonegotiation is enabled or force enabled otherwise.
19642 * In forced mode, this flag will only take effect if the speed is
19643 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
19644 * HWRM shall choose one of the RS544 modes.
19645 * When set to 0, then this flag shall be ignored.
19646 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
19649 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
19652 * When set to 1, then the HWRM shall disable FEC RS(544,514)
19653 * on this port if supported, by not advertising FEC RS(544,514) if
19654 * FEC autonegotiation is enabled or force disabled otherwise.
19655 * When set to 0, then this flag shall be ignored.
19656 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
19659 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
19662 * When set to 1, then the HWRM shall enable FEC RS272_1XN
19663 * on this port if supported, by advertising FEC RS272_1XN if
19664 * FEC autonegotiation is enabled or force enabled otherwise.
19665 * In forced mode, this flag will only take effect if the speed is
19666 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
19667 * HWRM shall choose one of the RS272 modes. Note that RS272
19668 * and RS544 modes cannot be set at the same time in forced FEC mode.
19669 * When set to 0, then this flag shall be ignored.
19670 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
19673 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
19676 * When set to 1, then the HWRM shall disable FEC RS272_1XN
19677 * on this port if supported, by not advertising FEC RS272_1XN if
19678 * FEC autonegotiation is enabled or force disabled otherwise.
19679 * When set to 0, then this flag shall be ignored.
19680 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
19683 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
19686 * When set to 1, then the HWRM shall enable FEC RS(272,257)
19687 * on this port if supported, by advertising FEC RS(272,257) if
19688 * FEC autonegotiation is enabled or force enabled otherwise.
19689 * In forced mode, this flag will only take effect if the speed is
19690 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
19691 * HWRM shall choose one of the RS272 modes. Note that RS272
19692 * and RS544 modes cannot be set at the same time in forced FEC mode.
19693 * When set to 0, then this flag shall be ignored.
19694 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
19697 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
19700 * When set to 1, then the HWRM shall disable FEC RS(272,257)
19701 * on this port if supported, by not advertising FEC RS(272,257) if
19702 * FEC autonegotiation is enabled or force disabled otherwise.
19703 * When set to 0, then this flag shall be ignored.
19704 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
19707 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
19711 * This bit must be '1' for the auto_mode field to be
19714 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
19717 * This bit must be '1' for the auto_duplex field to be
19720 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
19723 * This bit must be '1' for the auto_pause field to be
19726 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
19729 * This bit must be '1' for the auto_link_speed field to be
19732 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
19735 * This bit must be '1' for the auto_link_speed_mask field to be
19738 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
19741 * This bit must be '1' for the wirespeed field to be
19744 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
19747 * This bit must be '1' for the lpbk field to be
19750 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
19753 * This bit must be '1' for the preemphasis field to be
19756 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
19759 * This bit must be '1' for the force_pause field to be
19762 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
19765 * This bit must be '1' for the eee_link_speed_mask field to be
19768 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
19771 * This bit must be '1' for the tx_lpi_timer field to be
19774 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
19777 * This bit must be '1' for the force_pam4_link_speed field to be
19780 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
19783 * This bit must be '1' for the auto_pam4_link_speed_mask field to
19786 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
19788 /* Port ID of port that is to be configured. */
19791 * This is the speed that will be used if the force
19792 * bit is '1'. If unsupported speed is selected, an error
19793 * will be generated.
19795 uint16_t force_link_speed;
19796 /* 100Mb link speed */
19797 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
19798 /* 1Gb link speed */
19799 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
19800 /* 2Gb link speed */
19801 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
19802 /* 25Gb link speed */
19803 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
19804 /* 10Gb link speed */
19805 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
19806 /* 20Mb link speed */
19807 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
19808 /* 25Gb link speed */
19809 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
19810 /* 40Gb link speed */
19811 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
19812 /* 50Gb link speed */
19813 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
19814 /* 100Gb link speed */
19815 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
19816 /* 10Mb link speed */
19817 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
19818 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
19819 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
19821 * This value is used to identify what autoneg mode is
19822 * used when the link speed is not being forced.
19825 /* Disable autoneg or autoneg disabled. No speeds are selected. */
19826 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
19827 /* Select all possible speeds for autoneg mode. */
19828 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
19830 * Select only the auto_link_speed speed for autoneg mode. This mode has
19831 * been DEPRECATED. An HWRM client should not use this mode.
19833 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
19835 * Select the auto_link_speed or any speed below that speed for autoneg.
19836 * This mode has been DEPRECATED. An HWRM client should not use this mode.
19838 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
19840 * Select the speeds based on the corresponding link speed mask values
19841 * that are provided. The included speeds are specified in the
19842 * auto_link_speed and auto_pam4_link_speed fields.
19844 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
19845 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
19846 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
19848 * This is the duplex setting that will be used if the autoneg_mode
19849 * is "one_speed" or "one_or_below".
19851 uint8_t auto_duplex;
19852 /* Half Duplex will be requested. */
19853 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
19854 /* Full duplex will be requested. */
19855 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
19856 /* Both Half and Full dupex will be requested. */
19857 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
19858 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
19859 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
19861 * This value is used to configure the pause that will be
19862 * used for autonegotiation.
19863 * Add text on the usage of auto_pause and force_pause.
19865 uint8_t auto_pause;
19867 * When this bit is '1', Generation of tx pause messages
19868 * has been requested. Disabled otherwise.
19870 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
19873 * When this bit is '1', Reception of rx pause messages
19874 * has been requested. Disabled otherwise.
19876 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
19879 * When set to 1, the advertisement of pause is enabled.
19881 * # When the auto_mode is not set to none and this flag is
19882 * set to 1, then the auto_pause bits on this port are being
19883 * advertised and autoneg pause results are being interpreted.
19884 * # When the auto_mode is not set to none and this
19885 * flag is set to 0, the pause is forced as indicated in
19886 * force_pause, and also advertised as auto_pause bits, but
19887 * the autoneg results are not interpreted since the pause
19888 * configuration is being forced.
19889 * # When the auto_mode is set to none and this flag is set to
19890 * 1, auto_pause bits should be ignored and should be set to 0.
19892 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
19896 * This is the speed that will be used if the autoneg_mode
19897 * is "one_speed" or "one_or_below". If an unsupported speed
19898 * is selected, an error will be generated.
19900 uint16_t auto_link_speed;
19901 /* 100Mb link speed */
19902 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
19903 /* 1Gb link speed */
19904 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
19905 /* 2Gb link speed */
19906 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
19907 /* 25Gb link speed */
19908 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
19909 /* 10Gb link speed */
19910 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
19911 /* 20Mb link speed */
19912 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
19913 /* 25Gb link speed */
19914 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
19915 /* 40Gb link speed */
19916 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
19917 /* 50Gb link speed */
19918 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
19919 /* 100Gb link speed */
19920 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
19921 /* 10Mb link speed */
19922 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
19923 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
19924 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
19926 * This is a mask of link speeds that will be used if
19927 * autoneg_mode is "mask". If unsupported speed is enabled
19928 * an error will be generated.
19930 uint16_t auto_link_speed_mask;
19931 /* 100Mb link speed (Half-duplex) */
19932 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
19934 /* 100Mb link speed (Full-duplex) */
19935 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
19937 /* 1Gb link speed (Half-duplex) */
19938 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
19940 /* 1Gb link speed (Full-duplex) */
19941 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
19943 /* 2Gb link speed */
19944 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
19946 /* 25Gb link speed */
19947 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
19949 /* 10Gb link speed */
19950 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
19952 /* 20Gb link speed */
19953 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
19955 /* 25Gb link speed */
19956 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
19958 /* 40Gb link speed */
19959 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
19961 /* 50Gb link speed */
19962 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
19964 /* 100Gb link speed */
19965 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
19967 /* 10Mb link speed (Half-duplex) */
19968 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
19970 /* 10Mb link speed (Full-duplex) */
19971 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
19973 /* This value controls the wirespeed feature. */
19975 /* Wirespeed feature is disabled. */
19976 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
19977 /* Wirespeed feature is enabled. */
19978 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
19979 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
19980 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
19981 /* This value controls the loopback setting for the PHY. */
19983 /* No loopback is selected. Normal operation. */
19984 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
19986 * The HW will be configured with local loopback such that
19987 * host data is sent back to the host without modification.
19989 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
19991 * The HW will be configured with remote loopback such that
19992 * port logic will send packets back out the transmitter that
19995 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
19997 * The HW will be configured with external loopback such that
19998 * host data is sent on the transmitter and based on the external
19999 * loopback connection the data will be received without modification.
20001 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
20002 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
20003 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
20005 * This value is used to configure the pause that will be
20006 * used for force mode.
20008 uint8_t force_pause;
20010 * When this bit is '1', Generation of tx pause messages
20011 * is supported. Disabled otherwise.
20013 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
20015 * When this bit is '1', Reception of rx pause messages
20016 * is supported. Disabled otherwise.
20018 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
20021 * This value controls the pre-emphasis to be used for the
20022 * link. Driver should not set this value (use
20023 * enable.preemphasis = 0) unless driver is sure of setting.
20024 * Normally HWRM FW will determine proper pre-emphasis.
20026 uint32_t preemphasis;
20028 * Setting for link speed mask that is used to
20029 * advertise speeds during autonegotiation when EEE is enabled.
20030 * This field is valid only when EEE is enabled.
20031 * The speeds specified in this field shall be a subset of
20032 * speeds specified in auto_link_speed_mask.
20033 * If EEE is enabled,then at least one speed shall be provided
20036 uint16_t eee_link_speed_mask;
20038 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
20040 /* 100Mb link speed (Full-duplex) */
20041 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
20044 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
20046 /* 1Gb link speed (Full-duplex) */
20047 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
20050 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
20053 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
20055 /* 10Gb link speed */
20056 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
20059 * This is the speed that will be used if the force and force_pam4
20060 * bits are '1'. If unsupported speed is selected, an error
20061 * will be generated.
20063 uint16_t force_pam4_link_speed;
20064 /* 50Gb link speed */
20065 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
20067 /* 100Gb link speed */
20068 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
20070 /* 200Gb link speed */
20071 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
20073 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
20074 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
20076 * Requested setting of TX LPI timer in microseconds.
20077 * This field is valid only when EEE is enabled and TX LPI is
20080 uint32_t tx_lpi_timer;
20081 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
20082 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
20083 /* This field specifies which PAM4 speeds are enabled for auto mode. */
20084 uint16_t auto_link_pam4_speed_mask;
20085 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
20087 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
20089 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
20091 uint8_t unused_2[2];
20094 /* hwrm_port_phy_cfg_output (size:128b/16B) */
20095 struct hwrm_port_phy_cfg_output {
20096 /* The specific error status for the command. */
20097 uint16_t error_code;
20098 /* The HWRM command request type. */
20100 /* The sequence ID from the original command. */
20102 /* The length of the response data in number of bytes. */
20104 uint8_t unused_0[7];
20106 * This field is used in Output records to indicate that the output
20107 * is completely written to RAM. This field should be read as '1'
20108 * to indicate that the output has been completely written.
20109 * When writing a command completion or response to an internal processor,
20110 * the order of writes has to be such that this field is written last.
20115 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
20116 struct hwrm_port_phy_cfg_cmd_err {
20118 * command specific error codes that goes to
20119 * the cmd_err field in Common HWRM Error Response.
20122 /* Unknown error */
20123 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
20124 /* Unable to complete operation due to invalid speed */
20125 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
20127 * retry the command since the phy is not ready.
20128 * retry count is returned in opaque_0.
20129 * This is only valid for the first command and
20130 * this value will not change for successive calls.
20131 * but if a 0 is returned at any time then this should
20132 * be treated as an un recoverable failure,
20134 * retry interval in milli seconds is returned in opaque_1.
20135 * This specifies the time that user should wait before
20136 * issuing the next port_phy_cfg command.
20138 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
20139 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
20140 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
20141 uint8_t unused_0[7];
20144 /**********************
20145 * hwrm_port_phy_qcfg *
20146 **********************/
20149 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
20150 struct hwrm_port_phy_qcfg_input {
20151 /* The HWRM command request type. */
20154 * The completion ring to send the completion event on. This should
20155 * be the NQ ID returned from the `nq_alloc` HWRM command.
20157 uint16_t cmpl_ring;
20159 * The sequence ID is used by the driver for tracking multiple
20160 * commands. This ID is treated as opaque data by the firmware and
20161 * the value is returned in the `hwrm_resp_hdr` upon completion.
20165 * The target ID of the command:
20166 * * 0x0-0xFFF8 - The function ID
20167 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20168 * * 0xFFFD - Reserved for user-space HWRM interface
20171 uint16_t target_id;
20173 * A physical address pointer pointing to a host buffer that the
20174 * command's response data will be written. This can be either a host
20175 * physical address (HPA) or a guest physical address (GPA) and must
20176 * point to a physically contiguous block of memory.
20178 uint64_t resp_addr;
20179 /* Port ID of port that is to be queried. */
20181 uint8_t unused_0[6];
20184 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
20185 struct hwrm_port_phy_qcfg_output {
20186 /* The specific error status for the command. */
20187 uint16_t error_code;
20188 /* The HWRM command request type. */
20190 /* The sequence ID from the original command. */
20192 /* The length of the response data in number of bytes. */
20194 /* This value indicates the current link status. */
20196 /* There is no link or cable detected. */
20197 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
20198 /* There is no link, but a cable has been detected. */
20199 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
20200 /* There is a link. */
20201 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
20202 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
20203 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
20204 uint8_t active_fec_signal_mode;
20206 * This value indicates the current link signaling mode of the
20209 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
20211 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
20212 /* NRZ signaling */
20213 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
20215 /* PAM4 signaling */
20216 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
20218 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
20219 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
20220 /* This value indicates the current active FEC mode. */
20221 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
20223 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
20224 /* No active FEC */
20225 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
20226 (UINT32_C(0x0) << 4)
20227 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
20228 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
20229 (UINT32_C(0x1) << 4)
20230 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
20231 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
20232 (UINT32_C(0x2) << 4)
20233 /* FEC RS544_1XN active, autonegoatiated or forced. */
20234 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
20235 (UINT32_C(0x3) << 4)
20236 /* FEC RS(544,528) active, autonegoatiated or forced. */
20237 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
20238 (UINT32_C(0x4) << 4)
20239 /* FEC RS272_1XN active, autonegotiated or forced. */
20240 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
20241 (UINT32_C(0x5) << 4)
20242 /* FEC RS(272,257) active, autonegoatiated or forced. */
20243 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
20244 (UINT32_C(0x6) << 4)
20245 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
20246 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
20248 * This value indicates the current link speed of the connection.
20249 * The signal_mode field indicates if the link is using
20250 * NRZ or PAM4 signaling.
20252 uint16_t link_speed;
20253 /* 100Mb link speed */
20254 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
20255 /* 1Gb link speed */
20256 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
20257 /* 2Gb link speed */
20258 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
20259 /* 25Gb link speed */
20260 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
20261 /* 10Gb link speed */
20262 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
20263 /* 20Mb link speed */
20264 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
20265 /* 25Gb link speed */
20266 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
20267 /* 40Gb link speed */
20268 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
20269 /* 50Gb link speed */
20270 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
20271 /* 100Gb link speed */
20272 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
20273 /* 200Gb link speed */
20274 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
20275 /* 10Mb link speed */
20276 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
20277 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
20278 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
20280 * This value is indicates the duplex of the current
20283 uint8_t duplex_cfg;
20284 /* Half Duplex connection. */
20285 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
20286 /* Full duplex connection. */
20287 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
20288 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
20289 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
20291 * This value is used to indicate the current
20292 * pause configuration. When autoneg is enabled, this value
20293 * represents the autoneg results of pause configuration.
20297 * When this bit is '1', Generation of tx pause messages
20298 * is supported. Disabled otherwise.
20300 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
20302 * When this bit is '1', Reception of rx pause messages
20303 * is supported. Disabled otherwise.
20305 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
20307 * The supported speeds for the port. This is a bit mask.
20308 * For each speed that is supported, the corresponding
20309 * bit will be set to '1'.
20311 uint16_t support_speeds;
20312 /* 100Mb link speed (Half-duplex) */
20313 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
20315 /* 100Mb link speed (Full-duplex) */
20316 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
20318 /* 1Gb link speed (Half-duplex) */
20319 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
20321 /* 1Gb link speed (Full-duplex) */
20322 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
20324 /* 2Gb link speed */
20325 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
20327 /* 25Gb link speed */
20328 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
20330 /* 10Gb link speed */
20331 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
20333 /* 20Gb link speed */
20334 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
20336 /* 25Gb link speed */
20337 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
20339 /* 40Gb link speed */
20340 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
20342 /* 50Gb link speed */
20343 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
20345 /* 100Gb link speed */
20346 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
20348 /* 10Mb link speed (Half-duplex) */
20349 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
20351 /* 10Mb link speed (Full-duplex) */
20352 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
20355 * Current setting of forced link speed.
20356 * When the link speed is not being forced, this
20357 * value shall be set to 0.
20359 uint16_t force_link_speed;
20360 /* 100Mb link speed */
20361 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
20362 /* 1Gb link speed */
20363 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
20364 /* 2Gb link speed */
20365 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
20366 /* 25Gb link speed */
20367 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
20368 /* 10Gb link speed */
20369 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
20370 /* 20Mb link speed */
20371 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
20372 /* 25Gb link speed */
20373 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
20374 /* 40Gb link speed */
20375 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
20377 /* 50Gb link speed */
20378 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
20380 /* 100Gb link speed */
20381 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
20383 /* 10Mb link speed */
20384 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
20386 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
20387 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
20388 /* Current setting of auto negotiation mode. */
20390 /* Disable autoneg or autoneg disabled. No speeds are selected. */
20391 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
20392 /* Select all possible speeds for autoneg mode. */
20393 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
20395 * Select only the auto_link_speed speed for autoneg mode. This mode has
20396 * been DEPRECATED. An HWRM client should not use this mode.
20398 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
20400 * Select the auto_link_speed or any speed below that speed for autoneg.
20401 * This mode has been DEPRECATED. An HWRM client should not use this mode.
20403 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
20405 * Select the speeds based on the corresponding link speed mask value
20406 * that is provided.
20408 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
20409 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
20410 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
20412 * Current setting of pause autonegotiation.
20413 * Move autoneg_pause flag here.
20415 uint8_t auto_pause;
20417 * When this bit is '1', Generation of tx pause messages
20418 * has been requested. Disabled otherwise.
20420 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
20423 * When this bit is '1', Reception of rx pause messages
20424 * has been requested. Disabled otherwise.
20426 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
20429 * When set to 1, the advertisement of pause is enabled.
20431 * # When the auto_mode is not set to none and this flag is
20432 * set to 1, then the auto_pause bits on this port are being
20433 * advertised and autoneg pause results are being interpreted.
20434 * # When the auto_mode is not set to none and this
20435 * flag is set to 0, the pause is forced as indicated in
20436 * force_pause, and also advertised as auto_pause bits, but
20437 * the autoneg results are not interpreted since the pause
20438 * configuration is being forced.
20439 * # When the auto_mode is set to none and this flag is set to
20440 * 1, auto_pause bits should be ignored and should be set to 0.
20442 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
20445 * Current setting for auto_link_speed. This field is only
20446 * valid when auto_mode is set to "one_speed" or "one_or_below".
20448 uint16_t auto_link_speed;
20449 /* 100Mb link speed */
20450 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
20451 /* 1Gb link speed */
20452 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
20453 /* 2Gb link speed */
20454 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
20455 /* 25Gb link speed */
20456 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
20457 /* 10Gb link speed */
20458 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
20459 /* 20Mb link speed */
20460 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
20461 /* 25Gb link speed */
20462 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
20463 /* 40Gb link speed */
20464 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
20465 /* 50Gb link speed */
20466 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
20467 /* 100Gb link speed */
20468 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
20469 /* 10Mb link speed */
20470 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
20472 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
20473 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
20475 * Current setting for auto_link_speed_mask that is used to
20476 * advertise speeds during autonegotiation.
20477 * This field is only valid when auto_mode is set to "mask".
20478 * The speeds specified in this field shall be a subset of
20479 * supported speeds on this port.
20481 uint16_t auto_link_speed_mask;
20482 /* 100Mb link speed (Half-duplex) */
20483 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
20485 /* 100Mb link speed (Full-duplex) */
20486 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
20488 /* 1Gb link speed (Half-duplex) */
20489 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
20491 /* 1Gb link speed (Full-duplex) */
20492 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
20494 /* 2Gb link speed */
20495 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
20497 /* 25Gb link speed */
20498 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
20500 /* 10Gb link speed */
20501 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
20503 /* 20Gb link speed */
20504 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
20506 /* 25Gb link speed */
20507 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
20509 /* 40Gb link speed */
20510 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
20512 /* 50Gb link speed */
20513 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
20515 /* 100Gb link speed */
20516 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
20518 /* 10Mb link speed (Half-duplex) */
20519 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
20521 /* 10Mb link speed (Full-duplex) */
20522 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
20524 /* Current setting for wirespeed. */
20526 /* Wirespeed feature is disabled. */
20527 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
20528 /* Wirespeed feature is enabled. */
20529 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
20530 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
20531 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
20532 /* Current setting for loopback. */
20534 /* No loopback is selected. Normal operation. */
20535 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
20537 * The HW will be configured with local loopback such that
20538 * host data is sent back to the host without modification.
20540 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
20542 * The HW will be configured with remote loopback such that
20543 * port logic will send packets back out the transmitter that
20546 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
20548 * The HW will be configured with external loopback such that
20549 * host data is sent on the transmitter and based on the external
20550 * loopback connection the data will be received without modification.
20552 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
20553 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
20554 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
20556 * Current setting of forced pause.
20557 * When the pause configuration is not being forced, then
20558 * this value shall be set to 0.
20560 uint8_t force_pause;
20562 * When this bit is '1', Generation of tx pause messages
20563 * is supported. Disabled otherwise.
20565 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
20567 * When this bit is '1', Reception of rx pause messages
20568 * is supported. Disabled otherwise.
20570 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
20572 * This value indicates the current status of the optics module on
20575 uint8_t module_status;
20576 /* Module is inserted and accepted */
20577 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
20579 /* Module is rejected and transmit side Laser is disabled. */
20580 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
20582 /* Module mismatch warning. */
20583 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
20585 /* Module is rejected and powered down. */
20586 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
20588 /* Module is not inserted. */
20589 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
20591 /* Module is powered down because of over current fault. */
20592 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
20594 /* Module status is not applicable. */
20595 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
20597 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
20598 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
20599 /* Current setting for preemphasis. */
20600 uint32_t preemphasis;
20601 /* This field represents the major version of the PHY. */
20603 /* This field represents the minor version of the PHY. */
20605 /* This field represents the build version of the PHY. */
20607 /* This value represents a PHY type. */
20610 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
20613 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
20615 /* BASE-KR4 (Deprecated) */
20616 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
20619 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
20622 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
20624 /* BASE-KR2 (Deprecated) */
20625 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
20628 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
20631 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
20634 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
20636 /* EEE capable BASE-T */
20637 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
20639 /* SGMII connected external PHY */
20640 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
20642 /* 25G_BASECR_CA_L */
20643 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
20645 /* 25G_BASECR_CA_S */
20646 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
20648 /* 25G_BASECR_CA_N */
20649 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
20652 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
20655 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
20658 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
20661 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
20664 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
20666 /* 100G_BASESR10 */
20667 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
20670 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
20673 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
20676 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
20679 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
20681 /* 40G_ACTIVE_CABLE */
20682 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
20685 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
20688 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
20691 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
20694 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
20697 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
20700 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
20703 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
20705 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
20706 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
20707 /* This value represents a media type. */
20708 uint8_t media_type;
20710 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
20712 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
20713 /* Direct Attached Copper */
20714 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
20716 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
20717 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
20718 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
20719 /* This value represents a transceiver type. */
20720 uint8_t xcvr_pkg_type;
20721 /* PHY and MAC are in the same package */
20722 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
20724 /* PHY and MAC are in different packages */
20725 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
20727 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
20728 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
20729 uint8_t eee_config_phy_addr;
20730 /* This field represents PHY address. */
20731 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
20733 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
20735 * This field represents flags related to EEE configuration.
20736 * These EEE configuration flags are valid only when the
20737 * auto_mode is not set to none (in other words autonegotiation
20740 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
20742 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
20744 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
20745 * Speeds for autoneg with EEE mode enabled
20746 * are based on eee_link_speed_mask.
20748 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
20751 * This flag is valid only when eee_enabled is set to 1.
20753 * # If eee_enabled is set to 0, then EEE mode is disabled
20754 * and this flag shall be ignored.
20755 * # If eee_enabled is set to 1 and this flag is set to 1,
20756 * then Energy Efficient Ethernet (EEE) mode is enabled
20758 * # If eee_enabled is set to 1 and this flag is set to 0,
20759 * then Energy Efficient Ethernet (EEE) mode is enabled
20760 * but is currently not in use.
20762 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
20765 * This flag is valid only when eee_enabled is set to 1.
20767 * # If eee_enabled is set to 0, then EEE mode is disabled
20768 * and this flag shall be ignored.
20769 * # If eee_enabled is set to 1 and this flag is set to 1,
20770 * then Energy Efficient Ethernet (EEE) mode is enabled
20771 * and TX LPI is enabled.
20772 * # If eee_enabled is set to 1 and this flag is set to 0,
20773 * then Energy Efficient Ethernet (EEE) mode is enabled
20774 * but TX LPI is disabled.
20776 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
20779 * When set to 1, the parallel detection is used to determine
20780 * the speed of the link partner.
20782 * Parallel detection is used when a autonegotiation capable
20783 * device is connected to a link parter that is not capable
20784 * of autonegotiation.
20786 uint8_t parallel_detect;
20788 * When set to 1, the parallel detection is used to determine
20789 * the speed of the link partner.
20791 * Parallel detection is used when a autonegotiation capable
20792 * device is connected to a link parter that is not capable
20793 * of autonegotiation.
20795 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
20797 * The advertised speeds for the port by the link partner.
20798 * Each advertised speed will be set to '1'.
20800 uint16_t link_partner_adv_speeds;
20801 /* 100Mb link speed (Half-duplex) */
20802 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
20804 /* 100Mb link speed (Full-duplex) */
20805 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
20807 /* 1Gb link speed (Half-duplex) */
20808 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
20810 /* 1Gb link speed (Full-duplex) */
20811 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
20813 /* 2Gb link speed */
20814 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
20816 /* 25Gb link speed */
20817 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
20819 /* 10Gb link speed */
20820 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
20822 /* 20Gb link speed */
20823 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
20825 /* 25Gb link speed */
20826 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
20828 /* 40Gb link speed */
20829 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
20831 /* 50Gb link speed */
20832 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
20834 /* 100Gb link speed */
20835 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
20837 /* 10Mb link speed (Half-duplex) */
20838 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
20840 /* 10Mb link speed (Full-duplex) */
20841 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
20844 * The advertised autoneg for the port by the link partner.
20845 * This field is deprecated and should be set to 0.
20847 uint8_t link_partner_adv_auto_mode;
20848 /* Disable autoneg or autoneg disabled. No speeds are selected. */
20849 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
20851 /* Select all possible speeds for autoneg mode. */
20852 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
20855 * Select only the auto_link_speed speed for autoneg mode. This mode has
20856 * been DEPRECATED. An HWRM client should not use this mode.
20858 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
20861 * Select the auto_link_speed or any speed below that speed for autoneg.
20862 * This mode has been DEPRECATED. An HWRM client should not use this mode.
20864 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
20867 * Select the speeds based on the corresponding link speed mask value
20868 * that is provided.
20870 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
20872 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
20873 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
20874 /* The advertised pause settings on the port by the link partner. */
20875 uint8_t link_partner_adv_pause;
20877 * When this bit is '1', Generation of tx pause messages
20878 * is supported. Disabled otherwise.
20880 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
20883 * When this bit is '1', Reception of rx pause messages
20884 * is supported. Disabled otherwise.
20886 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
20889 * Current setting for link speed mask that is used to
20890 * advertise speeds during autonegotiation when EEE is enabled.
20891 * This field is valid only when eee_enabled flags is set to 1.
20892 * The speeds specified in this field shall be a subset of
20893 * speeds specified in auto_link_speed_mask.
20895 uint16_t adv_eee_link_speed_mask;
20897 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
20899 /* 100Mb link speed (Full-duplex) */
20900 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
20903 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
20905 /* 1Gb link speed (Full-duplex) */
20906 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
20909 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
20912 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
20914 /* 10Gb link speed */
20915 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
20918 * Current setting for link speed mask that is advertised by
20919 * the link partner when EEE is enabled.
20920 * This field is valid only when eee_enabled flags is set to 1.
20922 uint16_t link_partner_adv_eee_link_speed_mask;
20924 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
20926 /* 100Mb link speed (Full-duplex) */
20927 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
20930 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
20932 /* 1Gb link speed (Full-duplex) */
20933 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
20936 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
20939 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
20941 /* 10Gb link speed */
20942 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
20944 uint32_t xcvr_identifier_type_tx_lpi_timer;
20946 * Current setting of TX LPI timer in microseconds.
20947 * This field is valid only when_eee_enabled flag is set to 1
20948 * and tx_lpi_enabled is set to 1.
20950 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
20952 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
20953 /* This value represents transceiver identifier type. */
20954 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
20955 UINT32_C(0xff000000)
20956 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
20958 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
20959 (UINT32_C(0x0) << 24)
20960 /* SFP/SFP+/SFP28 */
20961 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
20962 (UINT32_C(0x3) << 24)
20964 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
20965 (UINT32_C(0xc) << 24)
20967 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
20968 (UINT32_C(0xd) << 24)
20970 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
20971 (UINT32_C(0x11) << 24)
20972 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
20973 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
20975 * This value represents the current configuration of
20976 * Forward Error Correction (FEC) on the port.
20980 * When set to 1, then FEC is not supported on this port. If this flag
20981 * is set to 1, then all other FEC configuration flags shall be ignored.
20982 * When set to 0, then FEC is supported as indicated by other
20983 * configuration flags.
20985 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
20988 * When set to 1, then FEC autonegotiation is supported on this port.
20989 * When set to 0, then FEC autonegotiation is not supported on this port.
20991 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
20994 * When set to 1, then FEC autonegotiation is enabled on this port.
20995 * When set to 0, then FEC autonegotiation is disabled if supported.
20996 * This flag should be ignored if FEC autonegotiation is not supported on this port.
20998 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
21001 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
21002 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
21004 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
21007 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
21008 * port. This means that FEC CLAUSE 74 is either advertised if
21009 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
21010 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
21011 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
21013 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
21016 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
21017 * NRZ) is supported on this port.
21018 * When set to 0, then FEC RS(528,418) is not supported on this port.
21020 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
21023 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
21024 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
21025 * either advertised if FEC autonegotiation is enabled or FEC
21026 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
21027 * is disabled if supported.
21028 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
21030 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
21033 * When set to 1, then FEC RS544_1XN is supported on this port.
21034 * When set to 0, then FEC RS544_1XN is not supported on this port.
21036 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
21039 * When set to 1, then RS544_1XN is enabled on this
21040 * port. This means that FEC RS544_1XN is either advertised if
21041 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
21042 * When set to 0, then FEC RS544_1XN is disabled if supported.
21043 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
21045 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
21048 * When set to 1, then FEC RS(544,514) is supported on this port.
21049 * When set to 0, then FEC RS(544,514) is not supported on this port.
21051 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
21054 * When set to 1, then RS(544,514) is enabled on this
21055 * port. This means that FEC RS(544,514) is either advertised if
21056 * FEC autonegotiation is enabled or FEC RS(544,514) is force
21057 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
21058 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
21060 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
21063 * When set to 1, then FEC RS272_1XN is supported on this port.
21064 * When set to 0, then FEC RS272_1XN is not supported on this port.
21066 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
21069 * When set to 1, then RS272_1XN is enabled on this
21070 * port. This means that FEC RS272_1XN is either advertised if
21071 * FEC autonegotiation is enabled or FEC RS272_1XN is force
21072 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
21073 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
21075 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
21078 * When set to 1, then FEC RS(272,514) is supported on this port.
21079 * When set to 0, then FEC RS(272,514) is not supported on this port.
21081 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
21084 * When set to 1, then RS(272,257) is enabled on this
21085 * port. This means that FEC RS(272,257) is either advertised if
21086 * FEC autonegotiation is enabled or FEC RS(272,257) is force
21087 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
21088 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
21090 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
21093 * This value is indicates the duplex of the current
21094 * connection state.
21096 uint8_t duplex_state;
21097 /* Half Duplex connection. */
21098 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
21099 /* Full duplex connection. */
21100 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
21101 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
21102 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
21103 /* Option flags fields. */
21104 uint8_t option_flags;
21105 /* When this bit is '1', Media auto detect is enabled. */
21106 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
21109 * When this bit is '1', active_fec_signal_mode can be
21112 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
21115 * Up to 16 bytes of null padded ASCII string representing
21117 * If the string is set to null, then the vendor name is not
21120 char phy_vendor_name[16];
21122 * Up to 16 bytes of null padded ASCII string that
21123 * identifies vendor specific part number of the PHY.
21124 * If the string is set to null, then the vendor specific
21125 * part number is not available.
21127 char phy_vendor_partnumber[16];
21129 * The supported PAM4 speeds for the port. This is a bit mask.
21130 * For each speed that is supported, the corresponding
21131 * bit will be set to '1'.
21133 uint16_t support_pam4_speeds;
21134 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
21136 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
21138 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
21141 * Current setting of forced PAM4 link speed.
21142 * When the link speed is not being forced, this
21143 * value shall be set to 0.
21145 uint16_t force_pam4_link_speed;
21146 /* 50Gb link speed */
21147 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
21149 /* 100Gb link speed */
21150 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
21152 /* 200Gb link speed */
21153 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
21155 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
21156 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
21158 * Current setting for auto_pam4_link_speed_mask that is used to
21159 * advertise speeds during autonegotiation.
21160 * This field is only valid when auto_mode is set to "mask".
21161 * The speeds specified in this field shall be a subset of
21162 * supported speeds on this port.
21164 uint16_t auto_pam4_link_speed_mask;
21165 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
21167 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
21169 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
21172 * The advertised PAM4 speeds for the port by the link partner.
21173 * Each advertised speed will be set to '1'.
21175 uint8_t link_partner_pam4_adv_speeds;
21176 /* 50Gb link speed */
21177 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
21179 /* 100Gb link speed */
21180 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
21182 /* 200Gb link speed */
21183 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
21186 * This field is used in Output records to indicate that the output
21187 * is completely written to RAM. This field should be read as '1'
21188 * to indicate that the output has been completely written.
21189 * When writing a command completion or response to an internal processor,
21190 * the order of writes has to be such that this field is written last.
21195 /*********************
21196 * hwrm_port_mac_cfg *
21197 *********************/
21200 /* hwrm_port_mac_cfg_input (size:384b/48B) */
21201 struct hwrm_port_mac_cfg_input {
21202 /* The HWRM command request type. */
21205 * The completion ring to send the completion event on. This should
21206 * be the NQ ID returned from the `nq_alloc` HWRM command.
21208 uint16_t cmpl_ring;
21210 * The sequence ID is used by the driver for tracking multiple
21211 * commands. This ID is treated as opaque data by the firmware and
21212 * the value is returned in the `hwrm_resp_hdr` upon completion.
21216 * The target ID of the command:
21217 * * 0x0-0xFFF8 - The function ID
21218 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21219 * * 0xFFFD - Reserved for user-space HWRM interface
21222 uint16_t target_id;
21224 * A physical address pointer pointing to a host buffer that the
21225 * command's response data will be written. This can be either a host
21226 * physical address (HPA) or a guest physical address (GPA) and must
21227 * point to a physically contiguous block of memory.
21229 uint64_t resp_addr;
21231 * In this field, there are a number of CoS mappings related flags
21232 * that are used to configure CoS mappings and their corresponding
21233 * priorities in the hardware.
21234 * For the priorities of CoS mappings, the HWRM uses the following
21235 * priority order (high to low) by default:
21238 * # tunnel_vlan_pri
21241 * A subset of CoS mappings can be enabled.
21242 * If a priority is not specified for an enabled CoS mapping, the
21243 * priority will be assigned in the above order for the enabled CoS
21244 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
21245 * enabled and their priorities are not specified, the following
21246 * priority order (high to low) will be used by the HWRM:
21251 * vlan_pri CoS mapping together with default CoS with lower priority
21252 * are enabled by default by the HWRM.
21256 * When this bit is '1', this command will configure
21257 * the MAC to match the current link state of the PHY.
21258 * If the link is not established on the PHY, then this
21259 * bit has no effect.
21261 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
21264 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
21265 * is requested to be enabled.
21267 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
21270 * When this bit is set to '1', tunnel VLAN PRI field to
21271 * CoS mapping is requested to be enabled.
21273 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
21276 * When this bit is set to '1', the IP DSCP to CoS mapping is
21277 * requested to be enabled.
21279 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
21282 * When this bit is '1', the HWRM is requested to
21283 * enable timestamp capture capability on the receive side
21286 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
21289 * When this bit is '1', the HWRM is requested to
21290 * disable timestamp capture capability on the receive side
21293 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
21296 * When this bit is '1', the HWRM is requested to
21297 * enable timestamp capture capability on the transmit side
21300 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
21303 * When this bit is '1', the HWRM is requested to
21304 * disable timestamp capture capability on the transmit side
21307 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
21310 * When this bit is '1', the Out-Of-Box WoL is requested to
21311 * be enabled on this port.
21313 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
21316 * When this bit is '1', the Out-Of-Box WoL is requested to
21317 * be disabled on this port.
21319 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
21322 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
21323 * is requested to be disabled.
21325 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
21328 * When this bit is set to '1', tunnel VLAN PRI field to
21329 * CoS mapping is requested to be disabled.
21331 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
21334 * When this bit is set to '1', the IP DSCP to CoS mapping is
21335 * requested to be disabled.
21337 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
21340 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
21341 * bit is set, then the device uses one step Tx timestamping.
21342 * This bit is temporary and used for experimental purposes.
21344 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
21348 * This bit must be '1' for the ipg field to be
21351 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
21354 * This bit must be '1' for the lpbk field to be
21357 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
21360 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
21363 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
21366 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
21369 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
21372 * This bit must be '1' for the dscp2cos_map_pri field to be
21375 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
21378 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
21381 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
21384 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
21387 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
21390 * This bit must be '1' for the cos_field_cfg field to be
21393 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
21396 * This bit must be '1' for the ptp_freq_adj_ppb field to be
21399 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
21401 /* Port ID of port that is to be configured. */
21404 * This value is used to configure the minimum IPG that will
21405 * be sent between packets by this port.
21408 /* This value controls the loopback setting for the MAC. */
21410 /* No loopback is selected. Normal operation. */
21411 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
21413 * The HW will be configured with local loopback such that
21414 * host data is sent back to the host without modification.
21416 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
21418 * The HW will be configured with remote loopback such that
21419 * port logic will send packets back out the transmitter that
21422 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
21423 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
21424 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
21426 * This value controls the priority setting of VLAN PRI to CoS
21427 * mapping based on VLAN Tags of inner packet headers of
21428 * tunneled packets or packet headers of non-tunneled packets.
21430 * # Each XXX_pri variable shall have a unique priority value
21431 * when it is being specified.
21432 * # When comparing priorities of mappings, higher value
21433 * indicates higher priority.
21434 * For example, a value of 0-3 is returned where 0 is being
21435 * the lowest priority and 3 is being the highest priority.
21437 uint8_t vlan_pri2cos_map_pri;
21438 /* Reserved field. */
21441 * This value controls the priority setting of VLAN PRI to CoS
21442 * mapping based on VLAN Tags of tunneled header.
21443 * This mapping only applies when tunneled headers
21446 * # Each XXX_pri variable shall have a unique priority value
21447 * when it is being specified.
21448 * # When comparing priorities of mappings, higher value
21449 * indicates higher priority.
21450 * For example, a value of 0-3 is returned where 0 is being
21451 * the lowest priority and 3 is being the highest priority.
21453 uint8_t tunnel_pri2cos_map_pri;
21455 * This value controls the priority setting of IP DSCP to CoS
21456 * mapping based on inner IP header of tunneled packets or
21457 * IP header of non-tunneled packets.
21459 * # Each XXX_pri variable shall have a unique priority value
21460 * when it is being specified.
21461 * # When comparing priorities of mappings, higher value
21462 * indicates higher priority.
21463 * For example, a value of 0-3 is returned where 0 is being
21464 * the lowest priority and 3 is being the highest priority.
21466 uint8_t dscp2pri_map_pri;
21468 * This is a 16-bit bit mask that is used to request a
21469 * specific configuration of time stamp capture of PTP messages
21470 * on the receive side of this port.
21471 * This field shall be ignored if the ptp_rx_ts_capture_enable
21472 * flag is not set in this command.
21473 * Otherwise, if bit 'i' is set, then the HWRM is being
21474 * requested to configure the receive side of the port to
21475 * capture the time stamp of every received PTP message
21476 * with messageType field value set to i.
21478 uint16_t rx_ts_capture_ptp_msg_type;
21480 * This is a 16-bit bit mask that is used to request a
21481 * specific configuration of time stamp capture of PTP messages
21482 * on the transmit side of this port.
21483 * This field shall be ignored if the ptp_tx_ts_capture_enable
21484 * flag is not set in this command.
21485 * Otherwise, if bit 'i' is set, then the HWRM is being
21486 * requested to configure the transmit side of the port to
21487 * capture the time stamp of every transmitted PTP message
21488 * with messageType field value set to i.
21490 uint16_t tx_ts_capture_ptp_msg_type;
21491 /* Configuration of CoS fields. */
21492 uint8_t cos_field_cfg;
21494 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
21497 * This field is used to specify selection of VLAN PRI value
21498 * based on whether one or two VLAN Tags are present in
21499 * the inner packet headers of tunneled packets or
21500 * non-tunneled packets.
21501 * This field is valid only if inner VLAN PRI to CoS mapping
21503 * If VLAN PRI to CoS mapping is not enabled, then this
21504 * field shall be ignored.
21506 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
21508 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
21511 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
21512 * present in the inner packet headers
21514 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
21515 (UINT32_C(0x0) << 1)
21517 * Select outer VLAN Tag PRI when 2 VLAN Tags are
21518 * present in the inner packet headers.
21519 * No VLAN PRI shall be selected for this configuration
21520 * if only one VLAN Tag is present in the inner
21523 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
21524 (UINT32_C(0x1) << 1)
21526 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
21527 * are present in the inner packet headers
21529 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
21530 (UINT32_C(0x2) << 1)
21532 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
21533 (UINT32_C(0x3) << 1)
21534 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
21535 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
21537 * This field is used to specify selection of tunnel VLAN
21538 * PRI value based on whether one or two VLAN Tags are
21539 * present in tunnel headers.
21540 * This field is valid only if tunnel VLAN PRI to CoS mapping
21542 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
21543 * field shall be ignored.
21545 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
21547 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
21550 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
21551 * present in the tunnel packet headers
21553 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
21554 (UINT32_C(0x0) << 3)
21556 * Select outer VLAN Tag PRI when 2 VLAN Tags are
21557 * present in the tunnel packet headers.
21558 * No tunnel VLAN PRI shall be selected for this
21559 * configuration if only one VLAN Tag is present in
21560 * the tunnel packet headers.
21562 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
21563 (UINT32_C(0x1) << 3)
21565 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
21566 * are present in the tunnel packet headers
21568 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
21569 (UINT32_C(0x2) << 3)
21571 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
21572 (UINT32_C(0x3) << 3)
21573 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
21574 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
21576 * This field shall be used to provide default CoS value
21577 * that has been configured on this port.
21578 * This field is valid only if default CoS mapping
21580 * If default CoS mapping is not enabled, then this
21581 * field shall be ignored.
21583 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
21585 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
21587 uint8_t unused_0[3];
21589 * This signed field specifies by how much to adjust the frequency
21590 * of sync timer updates (measured in parts per billion).
21592 int32_t ptp_freq_adj_ppb;
21593 uint8_t unused_1[4];
21596 /* hwrm_port_mac_cfg_output (size:128b/16B) */
21597 struct hwrm_port_mac_cfg_output {
21598 /* The specific error status for the command. */
21599 uint16_t error_code;
21600 /* The HWRM command request type. */
21602 /* The sequence ID from the original command. */
21604 /* The length of the response data in number of bytes. */
21607 * This is the configured maximum length of Ethernet packet
21608 * payload that is allowed to be received on the port.
21609 * This value does not include the number of bytes used by
21610 * Ethernet header and trailer (CRC).
21614 * This is the configured maximum length of Ethernet packet
21615 * payload that is allowed to be transmitted on the port.
21616 * This value does not include the number of bytes used by
21617 * Ethernet header and trailer (CRC).
21620 /* Current configuration of the IPG value. */
21622 /* Current value of the loopback value. */
21624 /* No loopback is selected. Normal operation. */
21625 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
21627 * The HW will be configured with local loopback such that
21628 * host data is sent back to the host without modification.
21630 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
21632 * The HW will be configured with remote loopback such that
21633 * port logic will send packets back out the transmitter that
21636 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
21637 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
21638 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
21641 * This field is used in Output records to indicate that the output
21642 * is completely written to RAM. This field should be read as '1'
21643 * to indicate that the output has been completely written.
21644 * When writing a command completion or response to an internal processor,
21645 * the order of writes has to be such that this field is written last.
21650 /**********************
21651 * hwrm_port_mac_qcfg *
21652 **********************/
21655 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
21656 struct hwrm_port_mac_qcfg_input {
21657 /* The HWRM command request type. */
21660 * The completion ring to send the completion event on. This should
21661 * be the NQ ID returned from the `nq_alloc` HWRM command.
21663 uint16_t cmpl_ring;
21665 * The sequence ID is used by the driver for tracking multiple
21666 * commands. This ID is treated as opaque data by the firmware and
21667 * the value is returned in the `hwrm_resp_hdr` upon completion.
21671 * The target ID of the command:
21672 * * 0x0-0xFFF8 - The function ID
21673 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21674 * * 0xFFFD - Reserved for user-space HWRM interface
21677 uint16_t target_id;
21679 * A physical address pointer pointing to a host buffer that the
21680 * command's response data will be written. This can be either a host
21681 * physical address (HPA) or a guest physical address (GPA) and must
21682 * point to a physically contiguous block of memory.
21684 uint64_t resp_addr;
21685 /* Port ID of port that is to be configured. */
21687 uint8_t unused_0[6];
21690 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
21691 struct hwrm_port_mac_qcfg_output {
21692 /* The specific error status for the command. */
21693 uint16_t error_code;
21694 /* The HWRM command request type. */
21696 /* The sequence ID from the original command. */
21698 /* The length of the response data in number of bytes. */
21701 * This is the configured maximum length of Ethernet packet
21702 * payload that is allowed to be received on the port.
21703 * This value does not include the number of bytes used by the
21704 * Ethernet header and trailer (CRC).
21708 * This is the configured maximum length of Ethernet packet
21709 * payload that is allowed to be transmitted on the port.
21710 * This value does not include the number of bytes used by the
21711 * Ethernet header and trailer (CRC).
21715 * The minimum IPG that will
21716 * be sent between packets by this port.
21719 /* The loopback setting for the MAC. */
21721 /* No loopback is selected. Normal operation. */
21722 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
21724 * The HW will be configured with local loopback such that
21725 * host data is sent back to the host without modification.
21727 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
21729 * The HW will be configured with remote loopback such that
21730 * port logic will send packets back out the transmitter that
21733 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
21734 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
21735 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
21737 * Priority setting for VLAN PRI to CoS mapping.
21738 * # Each XXX_pri variable shall have a unique priority value
21739 * when it is being used.
21740 * # When comparing priorities of mappings, higher value
21741 * indicates higher priority.
21742 * For example, a value of 0-3 is returned where 0 is being
21743 * the lowest priority and 3 is being the highest priority.
21744 * # If the correspoding CoS mapping is not enabled, then this
21745 * field should be ignored.
21746 * # This value indicates the normalized priority value retained
21749 uint8_t vlan_pri2cos_map_pri;
21751 * In this field, a number of CoS mappings related flags
21752 * are used to indicate configured CoS mappings.
21756 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
21759 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
21762 * When this bit is set to '1', tunnel VLAN PRI field to
21763 * CoS mapping is enabled.
21765 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
21768 * When this bit is set to '1', the IP DSCP to CoS mapping is
21771 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
21774 * When this bit is '1', the Out-Of-Box WoL is enabled on this
21777 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
21779 /* When this bit is '1', PTP is enabled for RX on this port. */
21780 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
21782 /* When this bit is '1', PTP is enabled for TX on this port. */
21783 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
21786 * Priority setting for tunnel VLAN PRI to CoS mapping.
21787 * # Each XXX_pri variable shall have a unique priority value
21788 * when it is being used.
21789 * # When comparing priorities of mappings, higher value
21790 * indicates higher priority.
21791 * For example, a value of 0-3 is returned where 0 is being
21792 * the lowest priority and 3 is being the highest priority.
21793 * # If the correspoding CoS mapping is not enabled, then this
21794 * field should be ignored.
21795 * # This value indicates the normalized priority value retained
21798 uint8_t tunnel_pri2cos_map_pri;
21800 * Priority setting for DSCP to PRI mapping.
21801 * # Each XXX_pri variable shall have a unique priority value
21802 * when it is being used.
21803 * # When comparing priorities of mappings, higher value
21804 * indicates higher priority.
21805 * For example, a value of 0-3 is returned where 0 is being
21806 * the lowest priority and 3 is being the highest priority.
21807 * # If the correspoding CoS mapping is not enabled, then this
21808 * field should be ignored.
21809 * # This value indicates the normalized priority value retained
21812 uint8_t dscp2pri_map_pri;
21814 * This is a 16-bit bit mask that represents the
21815 * current configuration of time stamp capture of PTP messages
21816 * on the receive side of this port.
21817 * If bit 'i' is set, then the receive side of the port
21818 * is configured to capture the time stamp of every
21819 * received PTP message with messageType field value set
21821 * If all bits are set to 0 (i.e. field value set 0),
21822 * then the receive side of the port is not configured
21823 * to capture timestamp for PTP messages.
21824 * If all bits are set to 1, then the receive side of the
21825 * port is configured to capture timestamp for all PTP
21828 uint16_t rx_ts_capture_ptp_msg_type;
21830 * This is a 16-bit bit mask that represents the
21831 * current configuration of time stamp capture of PTP messages
21832 * on the transmit side of this port.
21833 * If bit 'i' is set, then the transmit side of the port
21834 * is configured to capture the time stamp of every
21835 * received PTP message with messageType field value set
21837 * If all bits are set to 0 (i.e. field value set 0),
21838 * then the transmit side of the port is not configured
21839 * to capture timestamp for PTP messages.
21840 * If all bits are set to 1, then the transmit side of the
21841 * port is configured to capture timestamp for all PTP
21844 uint16_t tx_ts_capture_ptp_msg_type;
21845 /* Configuration of CoS fields. */
21846 uint8_t cos_field_cfg;
21848 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
21851 * This field is used for selecting VLAN PRI value
21852 * based on whether one or two VLAN Tags are present in
21853 * the inner packet headers of tunneled packets or
21854 * non-tunneled packets.
21856 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
21858 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
21861 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
21862 * present in the inner packet headers
21864 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
21865 (UINT32_C(0x0) << 1)
21867 * Select outer VLAN Tag PRI when 2 VLAN Tags are
21868 * present in the inner packet headers.
21869 * No VLAN PRI is selected for this configuration
21870 * if only one VLAN Tag is present in the inner
21873 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
21874 (UINT32_C(0x1) << 1)
21876 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
21877 * are present in the inner packet headers
21879 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
21880 (UINT32_C(0x2) << 1)
21882 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
21883 (UINT32_C(0x3) << 1)
21884 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
21885 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
21887 * This field is used for selecting tunnel VLAN PRI value
21888 * based on whether one or two VLAN Tags are present in
21889 * the tunnel headers of tunneled packets. This selection
21890 * does not apply to non-tunneled packets.
21892 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
21894 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
21897 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
21898 * present in the tunnel packet headers
21900 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
21901 (UINT32_C(0x0) << 3)
21903 * Select outer VLAN Tag PRI when 2 VLAN Tags are
21904 * present in the tunnel packet headers.
21905 * No VLAN PRI is selected for this configuration
21906 * if only one VLAN Tag is present in the tunnel
21909 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
21910 (UINT32_C(0x1) << 3)
21912 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
21913 * are present in the tunnel packet headers
21915 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
21916 (UINT32_C(0x2) << 3)
21918 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
21919 (UINT32_C(0x3) << 3)
21920 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
21921 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
21923 * This field is used to provide default CoS value that
21924 * has been configured on this port.
21926 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
21928 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
21931 uint16_t port_svif_info;
21933 * This field specifies the source virtual interface of the port being
21934 * queried. Drivers can use this to program port svif field in the
21937 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
21939 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
21940 /* This field specifies whether port_svif is valid or not */
21941 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
21943 uint8_t unused_2[5];
21945 * This field is used in Output records to indicate that the output
21946 * is completely written to RAM. This field should be read as '1'
21947 * to indicate that the output has been completely written.
21948 * When writing a command completion or response to an internal processor,
21949 * the order of writes has to be such that this field is written last.
21954 /**************************
21955 * hwrm_port_mac_ptp_qcfg *
21956 **************************/
21959 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
21960 struct hwrm_port_mac_ptp_qcfg_input {
21961 /* The HWRM command request type. */
21964 * The completion ring to send the completion event on. This should
21965 * be the NQ ID returned from the `nq_alloc` HWRM command.
21967 uint16_t cmpl_ring;
21969 * The sequence ID is used by the driver for tracking multiple
21970 * commands. This ID is treated as opaque data by the firmware and
21971 * the value is returned in the `hwrm_resp_hdr` upon completion.
21975 * The target ID of the command:
21976 * * 0x0-0xFFF8 - The function ID
21977 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21978 * * 0xFFFD - Reserved for user-space HWRM interface
21981 uint16_t target_id;
21983 * A physical address pointer pointing to a host buffer that the
21984 * command's response data will be written. This can be either a host
21985 * physical address (HPA) or a guest physical address (GPA) and must
21986 * point to a physically contiguous block of memory.
21988 uint64_t resp_addr;
21989 /* Port ID of port that is being queried. */
21991 uint8_t unused_0[6];
21994 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
21995 struct hwrm_port_mac_ptp_qcfg_output {
21996 /* The specific error status for the command. */
21997 uint16_t error_code;
21998 /* The HWRM command request type. */
22000 /* The sequence ID from the original command. */
22002 /* The length of the response data in number of bytes. */
22005 * In this field, a number of PTP related flags
22006 * are used to indicate configured PTP capabilities.
22010 * When this bit is set to '1', the PTP related registers are
22011 * directly accessible by the host.
22013 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
22016 * When this bit is set to '1', the device supports one-step
22019 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
22022 * When this bit is set to '1', the PTP information is accessible
22023 * via HWRM commands.
22025 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
22027 uint8_t unused_0[3];
22028 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
22029 uint32_t rx_ts_reg_off_lower;
22030 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
22031 uint32_t rx_ts_reg_off_upper;
22032 /* Offset of the PTP register for the sequence ID for RX. */
22033 uint32_t rx_ts_reg_off_seq_id;
22034 /* Offset of the first PTP source ID for RX. */
22035 uint32_t rx_ts_reg_off_src_id_0;
22036 /* Offset of the second PTP source ID for RX. */
22037 uint32_t rx_ts_reg_off_src_id_1;
22038 /* Offset of the third PTP source ID for RX. */
22039 uint32_t rx_ts_reg_off_src_id_2;
22040 /* Offset of the domain ID for RX. */
22041 uint32_t rx_ts_reg_off_domain_id;
22042 /* Offset of the PTP FIFO register for RX. */
22043 uint32_t rx_ts_reg_off_fifo;
22044 /* Offset of the PTP advance FIFO register for RX. */
22045 uint32_t rx_ts_reg_off_fifo_adv;
22046 /* PTP timestamp granularity for RX. */
22047 uint32_t rx_ts_reg_off_granularity;
22048 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
22049 uint32_t tx_ts_reg_off_lower;
22050 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
22051 uint32_t tx_ts_reg_off_upper;
22052 /* Offset of the PTP register for the sequence ID for TX. */
22053 uint32_t tx_ts_reg_off_seq_id;
22054 /* Offset of the PTP FIFO register for TX. */
22055 uint32_t tx_ts_reg_off_fifo;
22056 /* PTP timestamp granularity for TX. */
22057 uint32_t tx_ts_reg_off_granularity;
22058 uint8_t unused_1[7];
22060 * This field is used in Output records to indicate that the output
22061 * is completely written to RAM. This field should be read as '1'
22062 * to indicate that the output has been completely written.
22063 * When writing a command completion or response to an internal processor,
22064 * the order of writes has to be such that this field is written last.
22069 /* Port Tx Statistics Format */
22070 /* tx_port_stats (size:3264b/408B) */
22071 struct tx_port_stats {
22072 /* Total Number of 64 Bytes frames transmitted */
22073 uint64_t tx_64b_frames;
22074 /* Total Number of 65-127 Bytes frames transmitted */
22075 uint64_t tx_65b_127b_frames;
22076 /* Total Number of 128-255 Bytes frames transmitted */
22077 uint64_t tx_128b_255b_frames;
22078 /* Total Number of 256-511 Bytes frames transmitted */
22079 uint64_t tx_256b_511b_frames;
22080 /* Total Number of 512-1023 Bytes frames transmitted */
22081 uint64_t tx_512b_1023b_frames;
22082 /* Total Number of 1024-1518 Bytes frames transmitted */
22083 uint64_t tx_1024b_1518b_frames;
22085 * Total Number of each good VLAN (exludes FCS errors)
22086 * frame transmitted which is 1519 to 1522 bytes in length
22087 * inclusive (excluding framing bits but including FCS bytes).
22089 uint64_t tx_good_vlan_frames;
22090 /* Total Number of 1519-2047 Bytes frames transmitted */
22091 uint64_t tx_1519b_2047b_frames;
22092 /* Total Number of 2048-4095 Bytes frames transmitted */
22093 uint64_t tx_2048b_4095b_frames;
22094 /* Total Number of 4096-9216 Bytes frames transmitted */
22095 uint64_t tx_4096b_9216b_frames;
22096 /* Total Number of 9217-16383 Bytes frames transmitted */
22097 uint64_t tx_9217b_16383b_frames;
22098 /* Total Number of good frames transmitted */
22099 uint64_t tx_good_frames;
22100 /* Total Number of frames transmitted */
22101 uint64_t tx_total_frames;
22102 /* Total number of unicast frames transmitted */
22103 uint64_t tx_ucast_frames;
22104 /* Total number of multicast frames transmitted */
22105 uint64_t tx_mcast_frames;
22106 /* Total number of broadcast frames transmitted */
22107 uint64_t tx_bcast_frames;
22108 /* Total number of PAUSE control frames transmitted */
22109 uint64_t tx_pause_frames;
22111 * Total number of PFC/per-priority PAUSE
22112 * control frames transmitted
22114 uint64_t tx_pfc_frames;
22115 /* Total number of jabber frames transmitted */
22116 uint64_t tx_jabber_frames;
22117 /* Total number of frames transmitted with FCS error */
22118 uint64_t tx_fcs_err_frames;
22119 /* Total number of control frames transmitted */
22120 uint64_t tx_control_frames;
22121 /* Total number of over-sized frames transmitted */
22122 uint64_t tx_oversz_frames;
22123 /* Total number of frames with single deferral */
22124 uint64_t tx_single_dfrl_frames;
22125 /* Total number of frames with multiple deferrals */
22126 uint64_t tx_multi_dfrl_frames;
22127 /* Total number of frames with single collision */
22128 uint64_t tx_single_coll_frames;
22129 /* Total number of frames with multiple collisions */
22130 uint64_t tx_multi_coll_frames;
22131 /* Total number of frames with late collisions */
22132 uint64_t tx_late_coll_frames;
22133 /* Total number of frames with excessive collisions */
22134 uint64_t tx_excessive_coll_frames;
22135 /* Total number of fragmented frames transmitted */
22136 uint64_t tx_frag_frames;
22137 /* Total number of transmit errors */
22139 /* Total number of single VLAN tagged frames transmitted */
22140 uint64_t tx_tagged_frames;
22141 /* Total number of double VLAN tagged frames transmitted */
22142 uint64_t tx_dbl_tagged_frames;
22143 /* Total number of runt frames transmitted */
22144 uint64_t tx_runt_frames;
22145 /* Total number of TX FIFO under runs */
22146 uint64_t tx_fifo_underruns;
22148 * Total number of PFC frames with PFC enabled bit for
22149 * Pri 0 transmitted
22151 uint64_t tx_pfc_ena_frames_pri0;
22153 * Total number of PFC frames with PFC enabled bit for
22154 * Pri 1 transmitted
22156 uint64_t tx_pfc_ena_frames_pri1;
22158 * Total number of PFC frames with PFC enabled bit for
22159 * Pri 2 transmitted
22161 uint64_t tx_pfc_ena_frames_pri2;
22163 * Total number of PFC frames with PFC enabled bit for
22164 * Pri 3 transmitted
22166 uint64_t tx_pfc_ena_frames_pri3;
22168 * Total number of PFC frames with PFC enabled bit for
22169 * Pri 4 transmitted
22171 uint64_t tx_pfc_ena_frames_pri4;
22173 * Total number of PFC frames with PFC enabled bit for
22174 * Pri 5 transmitted
22176 uint64_t tx_pfc_ena_frames_pri5;
22178 * Total number of PFC frames with PFC enabled bit for
22179 * Pri 6 transmitted
22181 uint64_t tx_pfc_ena_frames_pri6;
22183 * Total number of PFC frames with PFC enabled bit for
22184 * Pri 7 transmitted
22186 uint64_t tx_pfc_ena_frames_pri7;
22187 /* Total number of EEE LPI Events on TX */
22188 uint64_t tx_eee_lpi_events;
22189 /* EEE LPI Duration Counter on TX */
22190 uint64_t tx_eee_lpi_duration;
22192 * Total number of Link Level Flow Control (LLFC) messages
22195 uint64_t tx_llfc_logical_msgs;
22196 /* Total number of HCFC messages transmitted */
22197 uint64_t tx_hcfc_msgs;
22198 /* Total number of TX collisions */
22199 uint64_t tx_total_collisions;
22200 /* Total number of transmitted bytes */
22202 /* Total number of end-to-end HOL frames */
22203 uint64_t tx_xthol_frames;
22204 /* Total Tx Drops per Port reported by STATS block */
22205 uint64_t tx_stat_discard;
22206 /* Total Tx Error Drops per Port reported by STATS block */
22207 uint64_t tx_stat_error;
22210 /* Port Rx Statistics Format */
22211 /* rx_port_stats (size:4224b/528B) */
22212 struct rx_port_stats {
22213 /* Total Number of 64 Bytes frames received */
22214 uint64_t rx_64b_frames;
22215 /* Total Number of 65-127 Bytes frames received */
22216 uint64_t rx_65b_127b_frames;
22217 /* Total Number of 128-255 Bytes frames received */
22218 uint64_t rx_128b_255b_frames;
22219 /* Total Number of 256-511 Bytes frames received */
22220 uint64_t rx_256b_511b_frames;
22221 /* Total Number of 512-1023 Bytes frames received */
22222 uint64_t rx_512b_1023b_frames;
22223 /* Total Number of 1024-1518 Bytes frames received */
22224 uint64_t rx_1024b_1518b_frames;
22226 * Total Number of each good VLAN (exludes FCS errors)
22227 * frame received which is 1519 to 1522 bytes in length
22228 * inclusive (excluding framing bits but including FCS bytes).
22230 uint64_t rx_good_vlan_frames;
22231 /* Total Number of 1519-2047 Bytes frames received */
22232 uint64_t rx_1519b_2047b_frames;
22233 /* Total Number of 2048-4095 Bytes frames received */
22234 uint64_t rx_2048b_4095b_frames;
22235 /* Total Number of 4096-9216 Bytes frames received */
22236 uint64_t rx_4096b_9216b_frames;
22237 /* Total Number of 9217-16383 Bytes frames received */
22238 uint64_t rx_9217b_16383b_frames;
22239 /* Total number of frames received */
22240 uint64_t rx_total_frames;
22241 /* Total number of unicast frames received */
22242 uint64_t rx_ucast_frames;
22243 /* Total number of multicast frames received */
22244 uint64_t rx_mcast_frames;
22245 /* Total number of broadcast frames received */
22246 uint64_t rx_bcast_frames;
22247 /* Total number of received frames with FCS error */
22248 uint64_t rx_fcs_err_frames;
22249 /* Total number of control frames received */
22250 uint64_t rx_ctrl_frames;
22251 /* Total number of PAUSE frames received */
22252 uint64_t rx_pause_frames;
22253 /* Total number of PFC frames received */
22254 uint64_t rx_pfc_frames;
22256 * Total number of frames received with an unsupported
22259 uint64_t rx_unsupported_opcode_frames;
22261 * Total number of frames received with an unsupported
22262 * DA for pause and PFC
22264 uint64_t rx_unsupported_da_pausepfc_frames;
22265 /* Total number of frames received with an unsupported SA */
22266 uint64_t rx_wrong_sa_frames;
22267 /* Total number of received packets with alignment error */
22268 uint64_t rx_align_err_frames;
22269 /* Total number of received frames with out-of-range length */
22270 uint64_t rx_oor_len_frames;
22271 /* Total number of received frames with error termination */
22272 uint64_t rx_code_err_frames;
22274 * Total number of received frames with a false carrier is
22275 * detected during idle, as defined by RX_ER samples active
22276 * and RXD is 0xE. The event is reported along with the
22277 * statistics generated on the next received frame. Only
22278 * one false carrier condition can be detected and logged
22281 * Carrier event, valid for 10M/100M speed modes only.
22283 uint64_t rx_false_carrier_frames;
22284 /* Total number of over-sized frames received */
22285 uint64_t rx_ovrsz_frames;
22286 /* Total number of jabber packets received */
22287 uint64_t rx_jbr_frames;
22288 /* Total number of received frames with MTU error */
22289 uint64_t rx_mtu_err_frames;
22290 /* Total number of received frames with CRC match */
22291 uint64_t rx_match_crc_frames;
22292 /* Total number of frames received promiscuously */
22293 uint64_t rx_promiscuous_frames;
22295 * Total number of received frames with one or two VLAN
22298 uint64_t rx_tagged_frames;
22299 /* Total number of received frames with two VLAN tags */
22300 uint64_t rx_double_tagged_frames;
22301 /* Total number of truncated frames received */
22302 uint64_t rx_trunc_frames;
22303 /* Total number of good frames (without errors) received */
22304 uint64_t rx_good_frames;
22306 * Total number of received PFC frames with transition from
22307 * XON to XOFF on Pri 0
22309 uint64_t rx_pfc_xon2xoff_frames_pri0;
22311 * Total number of received PFC frames with transition from
22312 * XON to XOFF on Pri 1
22314 uint64_t rx_pfc_xon2xoff_frames_pri1;
22316 * Total number of received PFC frames with transition from
22317 * XON to XOFF on Pri 2
22319 uint64_t rx_pfc_xon2xoff_frames_pri2;
22321 * Total number of received PFC frames with transition from
22322 * XON to XOFF on Pri 3
22324 uint64_t rx_pfc_xon2xoff_frames_pri3;
22326 * Total number of received PFC frames with transition from
22327 * XON to XOFF on Pri 4
22329 uint64_t rx_pfc_xon2xoff_frames_pri4;
22331 * Total number of received PFC frames with transition from
22332 * XON to XOFF on Pri 5
22334 uint64_t rx_pfc_xon2xoff_frames_pri5;
22336 * Total number of received PFC frames with transition from
22337 * XON to XOFF on Pri 6
22339 uint64_t rx_pfc_xon2xoff_frames_pri6;
22341 * Total number of received PFC frames with transition from
22342 * XON to XOFF on Pri 7
22344 uint64_t rx_pfc_xon2xoff_frames_pri7;
22346 * Total number of received PFC frames with PFC enabled
22349 uint64_t rx_pfc_ena_frames_pri0;
22351 * Total number of received PFC frames with PFC enabled
22354 uint64_t rx_pfc_ena_frames_pri1;
22356 * Total number of received PFC frames with PFC enabled
22359 uint64_t rx_pfc_ena_frames_pri2;
22361 * Total number of received PFC frames with PFC enabled
22364 uint64_t rx_pfc_ena_frames_pri3;
22366 * Total number of received PFC frames with PFC enabled
22369 uint64_t rx_pfc_ena_frames_pri4;
22371 * Total number of received PFC frames with PFC enabled
22374 uint64_t rx_pfc_ena_frames_pri5;
22376 * Total number of received PFC frames with PFC enabled
22379 uint64_t rx_pfc_ena_frames_pri6;
22381 * Total number of received PFC frames with PFC enabled
22384 uint64_t rx_pfc_ena_frames_pri7;
22385 /* Total Number of frames received with SCH CRC error */
22386 uint64_t rx_sch_crc_err_frames;
22387 /* Total Number of under-sized frames received */
22388 uint64_t rx_undrsz_frames;
22389 /* Total Number of fragmented frames received */
22390 uint64_t rx_frag_frames;
22391 /* Total number of RX EEE LPI Events */
22392 uint64_t rx_eee_lpi_events;
22393 /* EEE LPI Duration Counter on RX */
22394 uint64_t rx_eee_lpi_duration;
22396 * Total number of physical type Link Level Flow Control
22397 * (LLFC) messages received
22399 uint64_t rx_llfc_physical_msgs;
22401 * Total number of logical type Link Level Flow Control
22402 * (LLFC) messages received
22404 uint64_t rx_llfc_logical_msgs;
22406 * Total number of logical type Link Level Flow Control
22407 * (LLFC) messages received with CRC error
22409 uint64_t rx_llfc_msgs_with_crc_err;
22410 /* Total number of HCFC messages received */
22411 uint64_t rx_hcfc_msgs;
22412 /* Total number of HCFC messages received with CRC error */
22413 uint64_t rx_hcfc_msgs_with_crc_err;
22414 /* Total number of received bytes */
22416 /* Total number of bytes received in runt frames */
22417 uint64_t rx_runt_bytes;
22418 /* Total number of runt frames received */
22419 uint64_t rx_runt_frames;
22420 /* Total Rx Discards per Port reported by STATS block */
22421 uint64_t rx_stat_discard;
22422 uint64_t rx_stat_err;
22425 /********************
22426 * hwrm_port_qstats *
22427 ********************/
22430 /* hwrm_port_qstats_input (size:320b/40B) */
22431 struct hwrm_port_qstats_input {
22432 /* The HWRM command request type. */
22435 * The completion ring to send the completion event on. This should
22436 * be the NQ ID returned from the `nq_alloc` HWRM command.
22438 uint16_t cmpl_ring;
22440 * The sequence ID is used by the driver for tracking multiple
22441 * commands. This ID is treated as opaque data by the firmware and
22442 * the value is returned in the `hwrm_resp_hdr` upon completion.
22446 * The target ID of the command:
22447 * * 0x0-0xFFF8 - The function ID
22448 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22449 * * 0xFFFD - Reserved for user-space HWRM interface
22452 uint16_t target_id;
22454 * A physical address pointer pointing to a host buffer that the
22455 * command's response data will be written. This can be either a host
22456 * physical address (HPA) or a guest physical address (GPA) and must
22457 * point to a physically contiguous block of memory.
22459 uint64_t resp_addr;
22460 /* Port ID of port that is being queried. */
22463 /* This value is not used to avoid backward compatibility issues. */
22464 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
22466 * This bit is set to 1 when request is for a counter mask,
22467 * representing the width of each of the stats counters, rather
22468 * than counters themselves.
22470 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
22471 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
22472 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
22473 uint8_t unused_0[5];
22475 * This is the host address where
22476 * Tx port statistics will be stored
22478 uint64_t tx_stat_host_addr;
22480 * This is the host address where
22481 * Rx port statistics will be stored
22483 uint64_t rx_stat_host_addr;
22486 /* hwrm_port_qstats_output (size:128b/16B) */
22487 struct hwrm_port_qstats_output {
22488 /* The specific error status for the command. */
22489 uint16_t error_code;
22490 /* The HWRM command request type. */
22492 /* The sequence ID from the original command. */
22494 /* The length of the response data in number of bytes. */
22496 /* The size of TX port statistics block in bytes. */
22497 uint16_t tx_stat_size;
22498 /* The size of RX port statistics block in bytes. */
22499 uint16_t rx_stat_size;
22500 uint8_t unused_0[3];
22502 * This field is used in Output records to indicate that the output
22503 * is completely written to RAM. This field should be read as '1'
22504 * to indicate that the output has been completely written.
22505 * When writing a command completion or response to an internal processor,
22506 * the order of writes has to be such that this field is written last.
22511 /* Port Tx Statistics extended Format */
22512 /* tx_port_stats_ext (size:2048b/256B) */
22513 struct tx_port_stats_ext {
22514 /* Total number of tx bytes count on cos queue 0 */
22515 uint64_t tx_bytes_cos0;
22516 /* Total number of tx bytes count on cos queue 1 */
22517 uint64_t tx_bytes_cos1;
22518 /* Total number of tx bytes count on cos queue 2 */
22519 uint64_t tx_bytes_cos2;
22520 /* Total number of tx bytes count on cos queue 3 */
22521 uint64_t tx_bytes_cos3;
22522 /* Total number of tx bytes count on cos queue 4 */
22523 uint64_t tx_bytes_cos4;
22524 /* Total number of tx bytes count on cos queue 5 */
22525 uint64_t tx_bytes_cos5;
22526 /* Total number of tx bytes count on cos queue 6 */
22527 uint64_t tx_bytes_cos6;
22528 /* Total number of tx bytes count on cos queue 7 */
22529 uint64_t tx_bytes_cos7;
22530 /* Total number of tx packets count on cos queue 0 */
22531 uint64_t tx_packets_cos0;
22532 /* Total number of tx packets count on cos queue 1 */
22533 uint64_t tx_packets_cos1;
22534 /* Total number of tx packets count on cos queue 2 */
22535 uint64_t tx_packets_cos2;
22536 /* Total number of tx packets count on cos queue 3 */
22537 uint64_t tx_packets_cos3;
22538 /* Total number of tx packets count on cos queue 4 */
22539 uint64_t tx_packets_cos4;
22540 /* Total number of tx packets count on cos queue 5 */
22541 uint64_t tx_packets_cos5;
22542 /* Total number of tx packets count on cos queue 6 */
22543 uint64_t tx_packets_cos6;
22544 /* Total number of tx packets count on cos queue 7 */
22545 uint64_t tx_packets_cos7;
22546 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
22547 uint64_t pfc_pri0_tx_duration_us;
22548 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
22549 uint64_t pfc_pri0_tx_transitions;
22550 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
22551 uint64_t pfc_pri1_tx_duration_us;
22552 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
22553 uint64_t pfc_pri1_tx_transitions;
22554 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
22555 uint64_t pfc_pri2_tx_duration_us;
22556 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
22557 uint64_t pfc_pri2_tx_transitions;
22558 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
22559 uint64_t pfc_pri3_tx_duration_us;
22560 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
22561 uint64_t pfc_pri3_tx_transitions;
22562 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
22563 uint64_t pfc_pri4_tx_duration_us;
22564 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
22565 uint64_t pfc_pri4_tx_transitions;
22566 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
22567 uint64_t pfc_pri5_tx_duration_us;
22568 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
22569 uint64_t pfc_pri5_tx_transitions;
22570 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
22571 uint64_t pfc_pri6_tx_duration_us;
22572 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
22573 uint64_t pfc_pri6_tx_transitions;
22574 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
22575 uint64_t pfc_pri7_tx_duration_us;
22576 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
22577 uint64_t pfc_pri7_tx_transitions;
22580 /* Port Rx Statistics extended Format */
22581 /* rx_port_stats_ext (size:3648b/456B) */
22582 struct rx_port_stats_ext {
22583 /* Number of times link state changed to down */
22584 uint64_t link_down_events;
22585 /* Number of times the idle rings with pause bit are found */
22586 uint64_t continuous_pause_events;
22587 /* Number of times the active rings pause bit resumed back */
22588 uint64_t resume_pause_events;
22589 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
22590 uint64_t continuous_roce_pause_events;
22591 /* Number of times, the ROCE cos queue PFC is enabled back */
22592 uint64_t resume_roce_pause_events;
22593 /* Total number of rx bytes count on cos queue 0 */
22594 uint64_t rx_bytes_cos0;
22595 /* Total number of rx bytes count on cos queue 1 */
22596 uint64_t rx_bytes_cos1;
22597 /* Total number of rx bytes count on cos queue 2 */
22598 uint64_t rx_bytes_cos2;
22599 /* Total number of rx bytes count on cos queue 3 */
22600 uint64_t rx_bytes_cos3;
22601 /* Total number of rx bytes count on cos queue 4 */
22602 uint64_t rx_bytes_cos4;
22603 /* Total number of rx bytes count on cos queue 5 */
22604 uint64_t rx_bytes_cos5;
22605 /* Total number of rx bytes count on cos queue 6 */
22606 uint64_t rx_bytes_cos6;
22607 /* Total number of rx bytes count on cos queue 7 */
22608 uint64_t rx_bytes_cos7;
22609 /* Total number of rx packets count on cos queue 0 */
22610 uint64_t rx_packets_cos0;
22611 /* Total number of rx packets count on cos queue 1 */
22612 uint64_t rx_packets_cos1;
22613 /* Total number of rx packets count on cos queue 2 */
22614 uint64_t rx_packets_cos2;
22615 /* Total number of rx packets count on cos queue 3 */
22616 uint64_t rx_packets_cos3;
22617 /* Total number of rx packets count on cos queue 4 */
22618 uint64_t rx_packets_cos4;
22619 /* Total number of rx packets count on cos queue 5 */
22620 uint64_t rx_packets_cos5;
22621 /* Total number of rx packets count on cos queue 6 */
22622 uint64_t rx_packets_cos6;
22623 /* Total number of rx packets count on cos queue 7 */
22624 uint64_t rx_packets_cos7;
22625 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
22626 uint64_t pfc_pri0_rx_duration_us;
22627 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
22628 uint64_t pfc_pri0_rx_transitions;
22629 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
22630 uint64_t pfc_pri1_rx_duration_us;
22631 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
22632 uint64_t pfc_pri1_rx_transitions;
22633 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
22634 uint64_t pfc_pri2_rx_duration_us;
22635 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
22636 uint64_t pfc_pri2_rx_transitions;
22637 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
22638 uint64_t pfc_pri3_rx_duration_us;
22639 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
22640 uint64_t pfc_pri3_rx_transitions;
22641 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
22642 uint64_t pfc_pri4_rx_duration_us;
22643 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
22644 uint64_t pfc_pri4_rx_transitions;
22645 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
22646 uint64_t pfc_pri5_rx_duration_us;
22647 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
22648 uint64_t pfc_pri5_rx_transitions;
22649 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
22650 uint64_t pfc_pri6_rx_duration_us;
22651 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
22652 uint64_t pfc_pri6_rx_transitions;
22653 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
22654 uint64_t pfc_pri7_rx_duration_us;
22655 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
22656 uint64_t pfc_pri7_rx_transitions;
22657 /* Total number of received bits */
22659 /* The number of events where the port receive buffer was over 85% full */
22660 uint64_t rx_buffer_passed_threshold;
22662 * The number of symbol errors that wasn't corrected by FEC correction
22665 uint64_t rx_pcs_symbol_err;
22666 /* The number of corrected bits on the port according to active FEC */
22667 uint64_t rx_corrected_bits;
22668 /* Total number of rx discard bytes count on cos queue 0 */
22669 uint64_t rx_discard_bytes_cos0;
22670 /* Total number of rx discard bytes count on cos queue 1 */
22671 uint64_t rx_discard_bytes_cos1;
22672 /* Total number of rx discard bytes count on cos queue 2 */
22673 uint64_t rx_discard_bytes_cos2;
22674 /* Total number of rx discard bytes count on cos queue 3 */
22675 uint64_t rx_discard_bytes_cos3;
22676 /* Total number of rx discard bytes count on cos queue 4 */
22677 uint64_t rx_discard_bytes_cos4;
22678 /* Total number of rx discard bytes count on cos queue 5 */
22679 uint64_t rx_discard_bytes_cos5;
22680 /* Total number of rx discard bytes count on cos queue 6 */
22681 uint64_t rx_discard_bytes_cos6;
22682 /* Total number of rx discard bytes count on cos queue 7 */
22683 uint64_t rx_discard_bytes_cos7;
22684 /* Total number of rx discard packets count on cos queue 0 */
22685 uint64_t rx_discard_packets_cos0;
22686 /* Total number of rx discard packets count on cos queue 1 */
22687 uint64_t rx_discard_packets_cos1;
22688 /* Total number of rx discard packets count on cos queue 2 */
22689 uint64_t rx_discard_packets_cos2;
22690 /* Total number of rx discard packets count on cos queue 3 */
22691 uint64_t rx_discard_packets_cos3;
22692 /* Total number of rx discard packets count on cos queue 4 */
22693 uint64_t rx_discard_packets_cos4;
22694 /* Total number of rx discard packets count on cos queue 5 */
22695 uint64_t rx_discard_packets_cos5;
22696 /* Total number of rx discard packets count on cos queue 6 */
22697 uint64_t rx_discard_packets_cos6;
22698 /* Total number of rx discard packets count on cos queue 7 */
22699 uint64_t rx_discard_packets_cos7;
22703 * Port Rx Statistics extended PFC WatchDog Format.
22704 * StormDetect and StormRevert event determination is based
22705 * on an integration period and a percentage threshold.
22706 * StormDetect event - when percentage of XOFF frames received
22707 * within an integration period exceeds the configured threshold.
22708 * StormRevert event - when percentage of XON frames received
22709 * within an integration period exceeds the configured threshold.
22710 * Actual number of XOFF/XON frames for the events to be triggered
22711 * depends on both configured integration period and sampling rate.
22712 * The statistics in this structure represent counts of specified
22713 * events from the moment the feature (PFC WatchDog) is enabled via
22714 * hwrm_queue_pfc_enable_cfg call.
22716 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
22717 struct rx_port_stats_ext_pfc_wd {
22719 * Total number of PFC WatchDog StormDetect events detected
22722 uint64_t rx_pfc_watchdog_storms_detected_pri0;
22724 * Total number of PFC WatchDog StormDetect events detected
22727 uint64_t rx_pfc_watchdog_storms_detected_pri1;
22729 * Total number of PFC WatchDog StormDetect events detected
22732 uint64_t rx_pfc_watchdog_storms_detected_pri2;
22734 * Total number of PFC WatchDog StormDetect events detected
22737 uint64_t rx_pfc_watchdog_storms_detected_pri3;
22739 * Total number of PFC WatchDog StormDetect events detected
22742 uint64_t rx_pfc_watchdog_storms_detected_pri4;
22744 * Total number of PFC WatchDog StormDetect events detected
22747 uint64_t rx_pfc_watchdog_storms_detected_pri5;
22749 * Total number of PFC WatchDog StormDetect events detected
22752 uint64_t rx_pfc_watchdog_storms_detected_pri6;
22754 * Total number of PFC WatchDog StormDetect events detected
22757 uint64_t rx_pfc_watchdog_storms_detected_pri7;
22759 * Total number of PFC WatchDog StormRevert events detected
22762 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
22764 * Total number of PFC WatchDog StormRevert events detected
22767 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
22769 * Total number of PFC WatchDog StormRevert events detected
22772 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
22774 * Total number of PFC WatchDog StormRevert events detected
22777 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
22779 * Total number of PFC WatchDog StormRevert events detected
22782 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
22784 * Total number of PFC WatchDog StormRevert events detected
22787 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
22789 * Total number of PFC WatchDog StormRevert events detected
22792 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
22794 * Total number of PFC WatchDog StormRevert events detected
22797 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
22799 * Total number of packets received during PFC watchdog storm
22802 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
22804 * Total number of packets received during PFC watchdog storm
22807 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
22809 * Total number of packets received during PFC watchdog storm
22812 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
22814 * Total number of packets received during PFC watchdog storm
22817 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
22819 * Total number of packets received during PFC watchdog storm
22822 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
22824 * Total number of packets received during PFC watchdog storm
22827 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
22829 * Total number of packets received during PFC watchdog storm
22832 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
22834 * Total number of packets received during PFC watchdog storm
22837 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
22839 * Total number of bytes received during PFC watchdog storm
22842 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
22844 * Total number of bytes received during PFC watchdog storm
22847 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
22849 * Total number of bytes received during PFC watchdog storm
22852 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
22854 * Total number of bytes received during PFC watchdog storm
22857 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
22859 * Total number of bytes received during PFC watchdog storm
22862 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
22864 * Total number of bytes received during PFC watchdog storm
22867 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
22869 * Total number of bytes received during PFC watchdog storm
22872 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
22874 * Total number of bytes received during PFC watchdog storm
22877 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
22879 * Total number of packets dropped on rx during PFC watchdog storm
22882 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
22884 * Total number of packets dropped on rx during PFC watchdog storm
22887 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
22889 * Total number of packets dropped on rx during PFC watchdog storm
22892 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
22894 * Total number of packets dropped on rx during PFC watchdog storm
22897 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
22899 * Total number of packets dropped on rx during PFC watchdog storm
22902 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
22904 * Total number of packets dropped on rx during PFC watchdog storm
22907 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
22909 * Total number of packets dropped on rx during PFC watchdog storm
22912 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
22914 * Total number of packets dropped on rx during PFC watchdog storm
22917 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
22919 * Total number of bytes dropped on rx during PFC watchdog storm
22922 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
22924 * Total number of bytes dropped on rx during PFC watchdog storm
22927 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
22929 * Total number of bytes dropped on rx during PFC watchdog storm
22932 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
22934 * Total number of bytes dropped on rx during PFC watchdog storm
22937 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
22939 * Total number of bytes dropped on rx during PFC watchdog storm
22942 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
22944 * Total number of bytes dropped on rx during PFC watchdog storm
22947 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
22949 * Total number of bytes dropped on rx during PFC watchdog storm
22952 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
22954 * Total number of bytes dropped on rx during PFC watchdog storm
22957 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
22959 * Number of packets received during last PFC watchdog storm
22962 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
22964 * Number of packets received during last PFC watchdog storm
22967 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
22969 * Number of packets received during last PFC watchdog storm
22972 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
22974 * Number of packets received during last PFC watchdog storm
22977 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
22979 * Number of packets received during last PFC watchdog storm
22982 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
22984 * Number of packets received during last PFC watchdog storm
22987 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
22989 * Number of packets received during last PFC watchdog storm
22992 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
22994 * Number of packets received during last PFC watchdog storm
22997 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
22999 * Number of bytes received during last PFC watchdog storm
23002 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
23004 * Number of bytes received during last PFC watchdog storm
23007 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
23009 * Number of bytes received during last PFC watchdog storm
23012 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
23014 * Number of bytes received during last PFC watchdog storm
23017 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
23019 * Number of bytes received during last PFC watchdog storm
23022 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
23024 * Number of bytes received during last PFC watchdog storm
23027 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
23029 * Number of bytes received during last PFC watchdog storm
23032 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
23034 * Number of bytes received during last PFC watchdog storm
23037 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
23039 * Number of packets dropped on rx during last PFC watchdog storm
23042 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
23044 * Number of packets dropped on rx during last PFC watchdog storm
23047 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
23049 * Number of packets dropped on rx during last PFC watchdog storm
23052 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
23054 * Number of packets dropped on rx during last PFC watchdog storm
23057 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
23059 * Number of packets dropped on rx during last PFC watchdog storm
23062 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
23064 * Number of packets dropped on rx during last PFC watchdog storm
23067 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
23069 * Number of packets dropped on rx during last PFC watchdog storm
23072 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
23074 * Number of packets dropped on rx during last PFC watchdog storm
23077 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
23079 * Total number of bytes dropped on rx during PFC watchdog storm
23082 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
23084 * Number of bytes dropped on rx during last PFC watchdog storm
23087 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
23089 * Number of bytes dropped on rx during last PFC watchdog storm
23092 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
23094 * Number of bytes dropped on rx during last PFC watchdog storm
23097 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
23099 * Number of bytes dropped on rx during last PFC watchdog storm
23102 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
23104 * Number of bytes dropped on rx during last PFC watchdog storm
23107 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
23109 * Number of bytes dropped on rx during last PFC watchdog storm
23112 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
23114 * Number of bytes dropped on rx during last PFC watchdog storm
23117 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
23120 /************************
23121 * hwrm_port_qstats_ext *
23122 ************************/
23125 /* hwrm_port_qstats_ext_input (size:320b/40B) */
23126 struct hwrm_port_qstats_ext_input {
23127 /* The HWRM command request type. */
23130 * The completion ring to send the completion event on. This should
23131 * be the NQ ID returned from the `nq_alloc` HWRM command.
23133 uint16_t cmpl_ring;
23135 * The sequence ID is used by the driver for tracking multiple
23136 * commands. This ID is treated as opaque data by the firmware and
23137 * the value is returned in the `hwrm_resp_hdr` upon completion.
23141 * The target ID of the command:
23142 * * 0x0-0xFFF8 - The function ID
23143 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23144 * * 0xFFFD - Reserved for user-space HWRM interface
23147 uint16_t target_id;
23149 * A physical address pointer pointing to a host buffer that the
23150 * command's response data will be written. This can be either a host
23151 * physical address (HPA) or a guest physical address (GPA) and must
23152 * point to a physically contiguous block of memory.
23154 uint64_t resp_addr;
23155 /* Port ID of port that is being queried. */
23158 * The size of TX port extended
23159 * statistics block in bytes.
23161 uint16_t tx_stat_size;
23163 * The size of RX port extended
23164 * statistics block in bytes
23166 uint16_t rx_stat_size;
23168 /* This value is not used to avoid backward compatibility issues. */
23169 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
23171 * This bit is set to 1 when request is for the counter mask,
23172 * representing width of each of the stats counters, rather than
23173 * counters themselves.
23175 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
23176 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
23177 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
23180 * This is the host address where
23181 * Tx port statistics will be stored
23183 uint64_t tx_stat_host_addr;
23185 * This is the host address where
23186 * Rx port statistics will be stored
23188 uint64_t rx_stat_host_addr;
23191 /* hwrm_port_qstats_ext_output (size:128b/16B) */
23192 struct hwrm_port_qstats_ext_output {
23193 /* The specific error status for the command. */
23194 uint16_t error_code;
23195 /* The HWRM command request type. */
23197 /* The sequence ID from the original command. */
23199 /* The length of the response data in number of bytes. */
23201 /* The size of TX port statistics block in bytes. */
23202 uint16_t tx_stat_size;
23203 /* The size of RX port statistics block in bytes. */
23204 uint16_t rx_stat_size;
23205 /* Total number of active cos queues available. */
23206 uint16_t total_active_cos_queues;
23209 * If set to 1, then this field indicates that clear
23210 * roce specific counters is supported.
23212 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
23215 * This field is used in Output records to indicate that the output
23216 * is completely written to RAM. This field should be read as '1'
23217 * to indicate that the output has been completely written.
23218 * When writing a command completion or response to an internal processor,
23219 * the order of writes has to be such that this field is written last.
23224 /*******************************
23225 * hwrm_port_qstats_ext_pfc_wd *
23226 *******************************/
23229 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
23230 struct hwrm_port_qstats_ext_pfc_wd_input {
23231 /* The HWRM command request type. */
23234 * The completion ring to send the completion event on. This should
23235 * be the NQ ID returned from the `nq_alloc` HWRM command.
23237 uint16_t cmpl_ring;
23239 * The sequence ID is used by the driver for tracking multiple
23240 * commands. This ID is treated as opaque data by the firmware and
23241 * the value is returned in the `hwrm_resp_hdr` upon completion.
23245 * The target ID of the command:
23246 * * 0x0-0xFFF8 - The function ID
23247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23248 * * 0xFFFD - Reserved for user-space HWRM interface
23251 uint16_t target_id;
23253 * A physical address pointer pointing to a host buffer that the
23254 * command's response data will be written. This can be either a host
23255 * physical address (HPA) or a guest physical address (GPA) and must
23256 * point to a physically contiguous block of memory.
23258 uint64_t resp_addr;
23259 /* Port ID of port that is being queried. */
23262 * The size of rx_port_stats_ext_pfc_wd
23265 uint16_t pfc_wd_stat_size;
23266 uint8_t unused_0[4];
23268 * This is the host address where
23269 * rx_port_stats_ext_pfc_wd will be stored
23271 uint64_t pfc_wd_stat_host_addr;
23274 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
23275 struct hwrm_port_qstats_ext_pfc_wd_output {
23276 /* The specific error status for the command. */
23277 uint16_t error_code;
23278 /* The HWRM command request type. */
23280 /* The sequence ID from the original command. */
23282 /* The length of the response data in number of bytes. */
23285 * The size of rx_port_stats_ext_pfc_wd
23286 * statistics block in bytes.
23288 uint16_t pfc_wd_stat_size;
23291 * This field is used in Output records to indicate that the output
23292 * is completely written to RAM. This field should be read as '1'
23293 * to indicate that the output has been completely written.
23294 * When writing a command completion or response to an internal processor,
23295 * the order of writes has to be such that this field is written last.
23298 uint8_t unused_0[4];
23301 /*************************
23302 * hwrm_port_lpbk_qstats *
23303 *************************/
23306 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
23307 struct hwrm_port_lpbk_qstats_input {
23308 /* The HWRM command request type. */
23311 * The completion ring to send the completion event on. This should
23312 * be the NQ ID returned from the `nq_alloc` HWRM command.
23314 uint16_t cmpl_ring;
23316 * The sequence ID is used by the driver for tracking multiple
23317 * commands. This ID is treated as opaque data by the firmware and
23318 * the value is returned in the `hwrm_resp_hdr` upon completion.
23322 * The target ID of the command:
23323 * * 0x0-0xFFF8 - The function ID
23324 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23325 * * 0xFFFD - Reserved for user-space HWRM interface
23328 uint16_t target_id;
23330 * A physical address pointer pointing to a host buffer that the
23331 * command's response data will be written. This can be either a host
23332 * physical address (HPA) or a guest physical address (GPA) and must
23333 * point to a physically contiguous block of memory.
23335 uint64_t resp_addr;
23338 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
23339 struct hwrm_port_lpbk_qstats_output {
23340 /* The specific error status for the command. */
23341 uint16_t error_code;
23342 /* The HWRM command request type. */
23344 /* The sequence ID from the original command. */
23346 /* The length of the response data in number of bytes. */
23348 /* Number of transmitted unicast frames */
23349 uint64_t lpbk_ucast_frames;
23350 /* Number of transmitted multicast frames */
23351 uint64_t lpbk_mcast_frames;
23352 /* Number of transmitted broadcast frames */
23353 uint64_t lpbk_bcast_frames;
23354 /* Number of transmitted bytes for unicast traffic */
23355 uint64_t lpbk_ucast_bytes;
23356 /* Number of transmitted bytes for multicast traffic */
23357 uint64_t lpbk_mcast_bytes;
23358 /* Number of transmitted bytes for broadcast traffic */
23359 uint64_t lpbk_bcast_bytes;
23360 /* Total Tx Drops for loopback traffic reported by STATS block */
23361 uint64_t tx_stat_discard;
23362 /* Total Tx Error Drops for loopback traffic reported by STATS block */
23363 uint64_t tx_stat_error;
23364 /* Total Rx Drops for loopback traffic reported by STATS block */
23365 uint64_t rx_stat_discard;
23366 /* Total Rx Error Drops for loopback traffic reported by STATS block */
23367 uint64_t rx_stat_error;
23368 uint8_t unused_0[7];
23370 * This field is used in Output records to indicate that the output
23371 * is completely written to RAM. This field should be read as '1'
23372 * to indicate that the output has been completely written.
23373 * When writing a command completion or response to an internal processor,
23374 * the order of writes has to be such that this field is written last.
23379 /************************
23380 * hwrm_port_ecn_qstats *
23381 ************************/
23384 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
23385 struct hwrm_port_ecn_qstats_input {
23386 /* The HWRM command request type. */
23389 * The completion ring to send the completion event on. This should
23390 * be the NQ ID returned from the `nq_alloc` HWRM command.
23392 uint16_t cmpl_ring;
23394 * The sequence ID is used by the driver for tracking multiple
23395 * commands. This ID is treated as opaque data by the firmware and
23396 * the value is returned in the `hwrm_resp_hdr` upon completion.
23400 * The target ID of the command:
23401 * * 0x0-0xFFF8 - The function ID
23402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23403 * * 0xFFFD - Reserved for user-space HWRM interface
23406 uint16_t target_id;
23408 * A physical address pointer pointing to a host buffer that the
23409 * command's response data will be written. This can be either a host
23410 * physical address (HPA) or a guest physical address (GPA) and must
23411 * point to a physically contiguous block of memory.
23413 uint64_t resp_addr;
23415 * Port ID of port that is being queried. Unused if NIC is in
23420 * Size of the DMA buffer the caller has allocated for the firmware to
23423 uint16_t ecn_stat_buf_size;
23425 /* This value is not used to avoid backward compatibility issues. */
23426 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
23428 * This bit is set to 1 when request is for a counter mask,
23429 * representing the width of each of the stats counters, rather
23430 * than counters themselves.
23432 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
23433 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
23434 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
23435 uint8_t unused_0[3];
23437 * This is the host address where
23438 * ECN port statistics will be stored
23440 uint64_t ecn_stat_host_addr;
23443 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
23444 struct hwrm_port_ecn_qstats_output {
23445 /* The specific error status for the command. */
23446 uint16_t error_code;
23447 /* The HWRM command request type. */
23449 /* The sequence ID from the original command. */
23451 /* The length of the response data in number of bytes. */
23453 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
23454 uint16_t ecn_stat_buf_size;
23456 * Bitmask that indicates which CoS queues have ECN marking enabled.
23457 * Bit i corresponds to CoS queue i.
23460 uint8_t unused_0[4];
23462 * This field is used in Output records to indicate that the output
23463 * is completely written to RAM. This field should be read as '1'
23464 * to indicate that the output has been completely written.
23465 * When writing a command completion or response to an internal processor,
23466 * the order of writes has to be such that this field is written last.
23471 /* ECN mark statistics format */
23472 /* port_stats_ecn (size:512b/64B) */
23473 struct port_stats_ecn {
23475 * Number of packets marked in CoS queue 0.
23476 * Or, if the driver requested counter masks, a mask to indicate the size
23479 uint64_t mark_cnt_cos0;
23481 * Number of packets marked in CoS queue 1.
23482 * Or, if the driver requested counter masks, a mask to indicate the size
23485 uint64_t mark_cnt_cos1;
23487 * Number of packets marked in CoS queue 2.
23488 * Or, if the driver requested counter masks, a mask to indicate the size
23491 uint64_t mark_cnt_cos2;
23493 * Number of packets marked in CoS queue 3.
23494 * Or, if the driver requested counter masks, a mask to indicate the size
23497 uint64_t mark_cnt_cos3;
23499 * Number of packets marked in CoS queue 4.
23500 * Or, if the driver requested counter masks, a mask to indicate the size
23503 uint64_t mark_cnt_cos4;
23505 * Number of packets marked in CoS queue 5.
23506 * Or, if the driver requested counter masks, a mask to indicate the size
23509 uint64_t mark_cnt_cos5;
23511 * Number of packets marked in CoS queue 6.
23512 * Or, if the driver requested counter masks, a mask to indicate the size
23515 uint64_t mark_cnt_cos6;
23517 * Number of packets marked in CoS queue 7.
23518 * Or, if the driver requested counter masks, a mask to indicate the size
23521 uint64_t mark_cnt_cos7;
23524 /***********************
23525 * hwrm_port_clr_stats *
23526 ***********************/
23529 /* hwrm_port_clr_stats_input (size:192b/24B) */
23530 struct hwrm_port_clr_stats_input {
23531 /* The HWRM command request type. */
23534 * The completion ring to send the completion event on. This should
23535 * be the NQ ID returned from the `nq_alloc` HWRM command.
23537 uint16_t cmpl_ring;
23539 * The sequence ID is used by the driver for tracking multiple
23540 * commands. This ID is treated as opaque data by the firmware and
23541 * the value is returned in the `hwrm_resp_hdr` upon completion.
23545 * The target ID of the command:
23546 * * 0x0-0xFFF8 - The function ID
23547 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23548 * * 0xFFFD - Reserved for user-space HWRM interface
23551 uint16_t target_id;
23553 * A physical address pointer pointing to a host buffer that the
23554 * command's response data will be written. This can be either a host
23555 * physical address (HPA) or a guest physical address (GPA) and must
23556 * point to a physically contiguous block of memory.
23558 uint64_t resp_addr;
23559 /* Port ID of port that is being queried. */
23563 * If set to 1, then this field indicates clear the following RoCE
23564 * specific counters.
23565 * RoCE associated TX/RX cos counters
23566 * CNP associated TX/RX cos counters
23567 * RoCE/CNP specific TX/RX flow counters
23568 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
23569 * This flag is honored only when RoCE is enabled on that port.
23571 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
23572 uint8_t unused_0[5];
23575 /* hwrm_port_clr_stats_output (size:128b/16B) */
23576 struct hwrm_port_clr_stats_output {
23577 /* The specific error status for the command. */
23578 uint16_t error_code;
23579 /* The HWRM command request type. */
23581 /* The sequence ID from the original command. */
23583 /* The length of the response data in number of bytes. */
23585 uint8_t unused_0[7];
23587 * This field is used in Output records to indicate that the output
23588 * is completely written to RAM. This field should be read as '1'
23589 * to indicate that the output has been completely written.
23590 * When writing a command completion or response to an internal processor,
23591 * the order of writes has to be such that this field is written last.
23596 /***********************
23597 * hwrm_port_phy_qcaps *
23598 ***********************/
23601 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
23602 struct hwrm_port_phy_qcaps_input {
23603 /* The HWRM command request type. */
23606 * The completion ring to send the completion event on. This should
23607 * be the NQ ID returned from the `nq_alloc` HWRM command.
23609 uint16_t cmpl_ring;
23611 * The sequence ID is used by the driver for tracking multiple
23612 * commands. This ID is treated as opaque data by the firmware and
23613 * the value is returned in the `hwrm_resp_hdr` upon completion.
23617 * The target ID of the command:
23618 * * 0x0-0xFFF8 - The function ID
23619 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23620 * * 0xFFFD - Reserved for user-space HWRM interface
23623 uint16_t target_id;
23625 * A physical address pointer pointing to a host buffer that the
23626 * command's response data will be written. This can be either a host
23627 * physical address (HPA) or a guest physical address (GPA) and must
23628 * point to a physically contiguous block of memory.
23630 uint64_t resp_addr;
23631 /* Port ID of port that is being queried. */
23633 uint8_t unused_0[6];
23636 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
23637 struct hwrm_port_phy_qcaps_output {
23638 /* The specific error status for the command. */
23639 uint16_t error_code;
23640 /* The HWRM command request type. */
23642 /* The sequence ID from the original command. */
23644 /* The length of the response data in number of bytes. */
23646 /* PHY capability flags */
23649 * If set to 1, then this field indicates that the
23650 * link is capable of supporting EEE.
23652 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
23655 * If set to 1, then this field indicates that the
23656 * PHY is capable of supporting external loopback.
23658 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
23661 * If set to 1, then this field indicates that the
23662 * PHY is capable of supporting loopback in autoneg mode.
23664 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
23667 * Indicates if the configuration of shared PHY settings is supported.
23668 * In cases where a physical port is shared by multiple functions
23669 * (e.g. NPAR, multihost, etc), the configuration of PHY
23670 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
23671 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
23673 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
23676 * If set to 1, it indicates that the port counters and extended
23677 * port counters will not reset when the firmware shuts down or
23678 * resets the PHY. These counters will only be reset during power
23679 * cycle or by calling HWRM_PORT_CLR_STATS.
23680 * If set to 0, the state of the counters is unspecified when
23681 * firmware shuts down or resets the PHY.
23683 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
23686 * If set to 1, then this field indicates that the
23687 * local loopback is not supported on this controller.
23689 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
23692 * If set to 1, then this field indicates that the
23693 * PHY/Link down policy during PF shutdown is totally
23694 * controlled by the firmware. It can shutdown the link
23695 * even when there are active VFs associated with the PF.
23696 * Host PF driver can send HWRM_PHY_CFG command to bring
23697 * down the PHY even when the port is shared between VFs
23700 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
23703 * If set to 1, this field indicates that the FCS may
23704 * be disabled for a given packet via the transmit
23705 * buffer descriptor.
23707 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
23709 /* Number of front panel ports for this device. */
23711 /* Not supported or unknown */
23712 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
23713 /* single port device */
23714 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
23715 /* 2-port device */
23716 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
23717 /* 3-port device */
23718 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
23719 /* 4-port device */
23720 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
23721 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
23722 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
23724 * This is a bit mask to indicate what speeds are supported
23725 * as forced speeds on this link.
23726 * For each speed that can be forced on this link, the
23727 * corresponding mask bit shall be set to '1'.
23729 uint16_t supported_speeds_force_mode;
23730 /* 100Mb link speed (Half-duplex) */
23731 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
23733 /* 100Mb link speed (Full-duplex) */
23734 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
23736 /* 1Gb link speed (Half-duplex) */
23737 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
23739 /* 1Gb link speed (Full-duplex) */
23740 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
23742 /* 2Gb link speed */
23743 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
23745 /* 25Gb link speed */
23746 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
23748 /* 10Gb link speed */
23749 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
23751 /* 20Gb link speed */
23752 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
23754 /* 25Gb link speed */
23755 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
23757 /* 40Gb link speed */
23758 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
23760 /* 50Gb link speed */
23761 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
23763 /* 100Gb link speed */
23764 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
23766 /* 10Mb link speed (Half-duplex) */
23767 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
23769 /* 10Mb link speed (Full-duplex) */
23770 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
23773 * This is a bit mask to indicate what speeds are supported
23774 * for autonegotiation on this link.
23775 * For each speed that can be autonegotiated on this link, the
23776 * corresponding mask bit shall be set to '1'.
23778 uint16_t supported_speeds_auto_mode;
23779 /* 100Mb link speed (Half-duplex) */
23780 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
23782 /* 100Mb link speed (Full-duplex) */
23783 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
23785 /* 1Gb link speed (Half-duplex) */
23786 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
23788 /* 1Gb link speed (Full-duplex) */
23789 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
23791 /* 2Gb link speed */
23792 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
23794 /* 25Gb link speed */
23795 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
23797 /* 10Gb link speed */
23798 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
23800 /* 20Gb link speed */
23801 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
23803 /* 25Gb link speed */
23804 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
23806 /* 40Gb link speed */
23807 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
23809 /* 50Gb link speed */
23810 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
23812 /* 100Gb link speed */
23813 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
23815 /* 10Mb link speed (Half-duplex) */
23816 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
23818 /* 10Mb link speed (Full-duplex) */
23819 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
23822 * This is a bit mask to indicate what speeds are supported
23823 * for EEE on this link.
23824 * For each speed that can be autonegotiated when EEE is enabled
23825 * on this link, the corresponding mask bit shall be set to '1'.
23826 * This field is only valid when the eee_suppotred is set to '1'.
23828 uint16_t supported_speeds_eee_mode;
23830 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
23832 /* 100Mb link speed (Full-duplex) */
23833 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
23836 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
23838 /* 1Gb link speed (Full-duplex) */
23839 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
23842 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
23845 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
23847 /* 10Gb link speed */
23848 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
23850 uint32_t tx_lpi_timer_low;
23852 * The lowest value of TX LPI timer that can be set on this link
23853 * when EEE is enabled. This value is in microseconds.
23854 * This field is valid only when_eee_supported is set to '1'.
23856 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
23858 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
23860 * Reserved field. The HWRM shall set this field to 0.
23861 * An HWRM client shall ignore this field.
23863 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
23864 UINT32_C(0xff000000)
23865 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
23866 uint32_t valid_tx_lpi_timer_high;
23868 * The highest value of TX LPI timer that can be set on this link
23869 * when EEE is enabled. This value is in microseconds.
23870 * This field is valid only when_eee_supported is set to '1'.
23872 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
23874 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
23876 * Reserved field. The HWRM shall set this field to 0.
23877 * An HWRM client shall ignore this field.
23879 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
23880 UINT32_C(0xff000000)
23881 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
23883 * This field is used to advertise which PAM4 speeds are supported
23886 uint16_t supported_pam4_speeds_auto_mode;
23887 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
23889 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
23891 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
23894 * This field is used to advertise which PAM4 speeds are supported
23897 uint16_t supported_pam4_speeds_force_mode;
23898 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
23900 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
23902 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
23904 uint8_t unused_0[3];
23906 * This field is used in Output records to indicate that the output
23907 * is completely written to RAM. This field should be read as '1'
23908 * to indicate that the output has been completely written.
23909 * When writing a command completion or response to an internal processor,
23910 * the order of writes has to be such that this field is written last.
23915 /****************************
23916 * hwrm_port_phy_mdio_write *
23917 ****************************/
23920 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
23921 struct hwrm_port_phy_mdio_write_input {
23922 /* The HWRM command request type. */
23925 * The completion ring to send the completion event on. This should
23926 * be the NQ ID returned from the `nq_alloc` HWRM command.
23928 uint16_t cmpl_ring;
23930 * The sequence ID is used by the driver for tracking multiple
23931 * commands. This ID is treated as opaque data by the firmware and
23932 * the value is returned in the `hwrm_resp_hdr` upon completion.
23936 * The target ID of the command:
23937 * * 0x0-0xFFF8 - The function ID
23938 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23939 * * 0xFFFD - Reserved for user-space HWRM interface
23942 uint16_t target_id;
23944 * A physical address pointer pointing to a host buffer that the
23945 * command's response data will be written. This can be either a host
23946 * physical address (HPA) or a guest physical address (GPA) and must
23947 * point to a physically contiguous block of memory.
23949 uint64_t resp_addr;
23950 /* Reserved for future use. */
23951 uint32_t unused_0[2];
23952 /* Port ID of port. */
23954 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
23956 /* 8-bit device address. */
23958 /* 16-bit register address. */
23960 /* 16-bit register data. */
23963 * When this bit is set to 1 a Clause 45 mdio access is done.
23964 * when this bit is set to 0 a Clause 22 mdio access is done.
23968 uint8_t unused_1[7];
23971 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
23972 struct hwrm_port_phy_mdio_write_output {
23973 /* The specific error status for the command. */
23974 uint16_t error_code;
23975 /* The HWRM command request type. */
23977 /* The sequence ID from the original command. */
23979 /* The length of the response data in number of bytes. */
23981 uint8_t unused_0[7];
23983 * This field is used in Output records to indicate that the output
23984 * is completely written to RAM. This field should be read as '1'
23985 * to indicate that the output has been completely written.
23986 * When writing a command completion or response to an internal processor,
23987 * the order of writes has to be such that this field is written last.
23992 /***************************
23993 * hwrm_port_phy_mdio_read *
23994 ***************************/
23997 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
23998 struct hwrm_port_phy_mdio_read_input {
23999 /* The HWRM command request type. */
24002 * The completion ring to send the completion event on. This should
24003 * be the NQ ID returned from the `nq_alloc` HWRM command.
24005 uint16_t cmpl_ring;
24007 * The sequence ID is used by the driver for tracking multiple
24008 * commands. This ID is treated as opaque data by the firmware and
24009 * the value is returned in the `hwrm_resp_hdr` upon completion.
24013 * The target ID of the command:
24014 * * 0x0-0xFFF8 - The function ID
24015 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24016 * * 0xFFFD - Reserved for user-space HWRM interface
24019 uint16_t target_id;
24021 * A physical address pointer pointing to a host buffer that the
24022 * command's response data will be written. This can be either a host
24023 * physical address (HPA) or a guest physical address (GPA) and must
24024 * point to a physically contiguous block of memory.
24026 uint64_t resp_addr;
24027 /* Reserved for future use. */
24028 uint32_t unused_0[2];
24029 /* Port ID of port. */
24031 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
24033 /* 8-bit device address. */
24035 /* 16-bit register address. */
24038 * When this bit is set to 1 a Clause 45 mdio access is done.
24039 * when this bit is set to 0 a Clause 22 mdio access is done.
24046 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
24047 struct hwrm_port_phy_mdio_read_output {
24048 /* The specific error status for the command. */
24049 uint16_t error_code;
24050 /* The HWRM command request type. */
24052 /* The sequence ID from the original command. */
24054 /* The length of the response data in number of bytes. */
24056 /* 16-bit register data. */
24058 uint8_t unused_0[5];
24060 * This field is used in Output records to indicate that the output
24061 * is completely written to RAM. This field should be read as '1'
24062 * to indicate that the output has been completely written.
24063 * When writing a command completion or response to an internal processor,
24064 * the order of writes has to be such that this field is written last.
24069 /*********************
24070 * hwrm_port_led_cfg *
24071 *********************/
24074 /* hwrm_port_led_cfg_input (size:512b/64B) */
24075 struct hwrm_port_led_cfg_input {
24076 /* The HWRM command request type. */
24079 * The completion ring to send the completion event on. This should
24080 * be the NQ ID returned from the `nq_alloc` HWRM command.
24082 uint16_t cmpl_ring;
24084 * The sequence ID is used by the driver for tracking multiple
24085 * commands. This ID is treated as opaque data by the firmware and
24086 * the value is returned in the `hwrm_resp_hdr` upon completion.
24090 * The target ID of the command:
24091 * * 0x0-0xFFF8 - The function ID
24092 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24093 * * 0xFFFD - Reserved for user-space HWRM interface
24096 uint16_t target_id;
24098 * A physical address pointer pointing to a host buffer that the
24099 * command's response data will be written. This can be either a host
24100 * physical address (HPA) or a guest physical address (GPA) and must
24101 * point to a physically contiguous block of memory.
24103 uint64_t resp_addr;
24106 * This bit must be '1' for the led0_id field to be
24109 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
24112 * This bit must be '1' for the led0_state field to be
24115 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
24118 * This bit must be '1' for the led0_color field to be
24121 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
24124 * This bit must be '1' for the led0_blink_on field to be
24127 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
24130 * This bit must be '1' for the led0_blink_off field to be
24133 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
24136 * This bit must be '1' for the led0_group_id field to be
24139 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
24142 * This bit must be '1' for the led1_id field to be
24145 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
24148 * This bit must be '1' for the led1_state field to be
24151 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
24154 * This bit must be '1' for the led1_color field to be
24157 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
24160 * This bit must be '1' for the led1_blink_on field to be
24163 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
24166 * This bit must be '1' for the led1_blink_off field to be
24169 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
24172 * This bit must be '1' for the led1_group_id field to be
24175 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
24178 * This bit must be '1' for the led2_id field to be
24181 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
24184 * This bit must be '1' for the led2_state field to be
24187 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
24190 * This bit must be '1' for the led2_color field to be
24193 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
24196 * This bit must be '1' for the led2_blink_on field to be
24199 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
24202 * This bit must be '1' for the led2_blink_off field to be
24205 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
24208 * This bit must be '1' for the led2_group_id field to be
24211 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
24214 * This bit must be '1' for the led3_id field to be
24217 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
24220 * This bit must be '1' for the led3_state field to be
24223 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
24226 * This bit must be '1' for the led3_color field to be
24229 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
24232 * This bit must be '1' for the led3_blink_on field to be
24235 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
24238 * This bit must be '1' for the led3_blink_off field to be
24241 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
24244 * This bit must be '1' for the led3_group_id field to be
24247 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
24249 /* Port ID of port whose LEDs are configured. */
24252 * The number of LEDs that are being configured.
24253 * Up to 4 LEDs can be configured with this command.
24256 /* Reserved field. */
24258 /* An identifier for the LED #0. */
24260 /* The requested state of the LED #0. */
24261 uint8_t led0_state;
24262 /* Default state of the LED */
24263 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
24265 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
24267 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
24269 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
24270 /* Blink Alternately */
24271 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
24272 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
24273 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
24274 /* The requested color of LED #0. */
24275 uint8_t led0_color;
24277 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
24279 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
24281 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
24282 /* Green or Amber */
24283 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
24284 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
24285 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
24288 * If the LED #0 state is "blink" or "blinkalt", then
24289 * this field represents the requested time in milliseconds
24290 * to keep LED on between cycles.
24292 uint16_t led0_blink_on;
24294 * If the LED #0 state is "blink" or "blinkalt", then
24295 * this field represents the requested time in milliseconds
24296 * to keep LED off between cycles.
24298 uint16_t led0_blink_off;
24300 * An identifier for the group of LEDs that LED #0 belongs
24302 * If set to 0, then the LED #0 shall not be grouped and
24303 * shall be treated as an individual resource.
24304 * For all other non-zero values of this field, LED #0 shall
24305 * be grouped together with the LEDs with the same group ID
24308 uint8_t led0_group_id;
24309 /* Reserved field. */
24311 /* An identifier for the LED #1. */
24313 /* The requested state of the LED #1. */
24314 uint8_t led1_state;
24315 /* Default state of the LED */
24316 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
24318 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
24320 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
24322 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
24323 /* Blink Alternately */
24324 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
24325 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
24326 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
24327 /* The requested color of LED #1. */
24328 uint8_t led1_color;
24330 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
24332 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
24334 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
24335 /* Green or Amber */
24336 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
24337 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
24338 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
24341 * If the LED #1 state is "blink" or "blinkalt", then
24342 * this field represents the requested time in milliseconds
24343 * to keep LED on between cycles.
24345 uint16_t led1_blink_on;
24347 * If the LED #1 state is "blink" or "blinkalt", then
24348 * this field represents the requested time in milliseconds
24349 * to keep LED off between cycles.
24351 uint16_t led1_blink_off;
24353 * An identifier for the group of LEDs that LED #1 belongs
24355 * If set to 0, then the LED #1 shall not be grouped and
24356 * shall be treated as an individual resource.
24357 * For all other non-zero values of this field, LED #1 shall
24358 * be grouped together with the LEDs with the same group ID
24361 uint8_t led1_group_id;
24362 /* Reserved field. */
24364 /* An identifier for the LED #2. */
24366 /* The requested state of the LED #2. */
24367 uint8_t led2_state;
24368 /* Default state of the LED */
24369 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
24371 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
24373 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
24375 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
24376 /* Blink Alternately */
24377 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
24378 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
24379 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
24380 /* The requested color of LED #2. */
24381 uint8_t led2_color;
24383 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
24385 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
24387 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
24388 /* Green or Amber */
24389 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
24390 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
24391 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
24394 * If the LED #2 state is "blink" or "blinkalt", then
24395 * this field represents the requested time in milliseconds
24396 * to keep LED on between cycles.
24398 uint16_t led2_blink_on;
24400 * If the LED #2 state is "blink" or "blinkalt", then
24401 * this field represents the requested time in milliseconds
24402 * to keep LED off between cycles.
24404 uint16_t led2_blink_off;
24406 * An identifier for the group of LEDs that LED #2 belongs
24408 * If set to 0, then the LED #2 shall not be grouped and
24409 * shall be treated as an individual resource.
24410 * For all other non-zero values of this field, LED #2 shall
24411 * be grouped together with the LEDs with the same group ID
24414 uint8_t led2_group_id;
24415 /* Reserved field. */
24417 /* An identifier for the LED #3. */
24419 /* The requested state of the LED #3. */
24420 uint8_t led3_state;
24421 /* Default state of the LED */
24422 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
24424 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
24426 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
24428 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
24429 /* Blink Alternately */
24430 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
24431 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
24432 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
24433 /* The requested color of LED #3. */
24434 uint8_t led3_color;
24436 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
24438 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
24440 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
24441 /* Green or Amber */
24442 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
24443 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
24444 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
24447 * If the LED #3 state is "blink" or "blinkalt", then
24448 * this field represents the requested time in milliseconds
24449 * to keep LED on between cycles.
24451 uint16_t led3_blink_on;
24453 * If the LED #3 state is "blink" or "blinkalt", then
24454 * this field represents the requested time in milliseconds
24455 * to keep LED off between cycles.
24457 uint16_t led3_blink_off;
24459 * An identifier for the group of LEDs that LED #3 belongs
24461 * If set to 0, then the LED #3 shall not be grouped and
24462 * shall be treated as an individual resource.
24463 * For all other non-zero values of this field, LED #3 shall
24464 * be grouped together with the LEDs with the same group ID
24467 uint8_t led3_group_id;
24468 /* Reserved field. */
24472 /* hwrm_port_led_cfg_output (size:128b/16B) */
24473 struct hwrm_port_led_cfg_output {
24474 /* The specific error status for the command. */
24475 uint16_t error_code;
24476 /* The HWRM command request type. */
24478 /* The sequence ID from the original command. */
24480 /* The length of the response data in number of bytes. */
24482 uint8_t unused_0[7];
24484 * This field is used in Output records to indicate that the output
24485 * is completely written to RAM. This field should be read as '1'
24486 * to indicate that the output has been completely written.
24487 * When writing a command completion or response to an internal processor,
24488 * the order of writes has to be such that this field is written last.
24493 /**********************
24494 * hwrm_port_led_qcfg *
24495 **********************/
24498 /* hwrm_port_led_qcfg_input (size:192b/24B) */
24499 struct hwrm_port_led_qcfg_input {
24500 /* The HWRM command request type. */
24503 * The completion ring to send the completion event on. This should
24504 * be the NQ ID returned from the `nq_alloc` HWRM command.
24506 uint16_t cmpl_ring;
24508 * The sequence ID is used by the driver for tracking multiple
24509 * commands. This ID is treated as opaque data by the firmware and
24510 * the value is returned in the `hwrm_resp_hdr` upon completion.
24514 * The target ID of the command:
24515 * * 0x0-0xFFF8 - The function ID
24516 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24517 * * 0xFFFD - Reserved for user-space HWRM interface
24520 uint16_t target_id;
24522 * A physical address pointer pointing to a host buffer that the
24523 * command's response data will be written. This can be either a host
24524 * physical address (HPA) or a guest physical address (GPA) and must
24525 * point to a physically contiguous block of memory.
24527 uint64_t resp_addr;
24528 /* Port ID of port whose LED configuration is being queried. */
24530 uint8_t unused_0[6];
24533 /* hwrm_port_led_qcfg_output (size:448b/56B) */
24534 struct hwrm_port_led_qcfg_output {
24535 /* The specific error status for the command. */
24536 uint16_t error_code;
24537 /* The HWRM command request type. */
24539 /* The sequence ID from the original command. */
24541 /* The length of the response data in number of bytes. */
24544 * The number of LEDs that are configured on this port.
24545 * Up to 4 LEDs can be returned in the response.
24548 /* An identifier for the LED #0. */
24550 /* The type of LED #0. */
24553 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
24555 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
24557 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
24558 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
24559 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
24560 /* The current state of the LED #0. */
24561 uint8_t led0_state;
24562 /* Default state of the LED */
24563 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
24565 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
24567 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
24569 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
24570 /* Blink Alternately */
24571 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
24572 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
24573 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
24574 /* The color of LED #0. */
24575 uint8_t led0_color;
24577 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
24579 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
24581 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
24582 /* Green or Amber */
24583 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
24584 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
24585 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
24588 * If the LED #0 state is "blink" or "blinkalt", then
24589 * this field represents the requested time in milliseconds
24590 * to keep LED on between cycles.
24592 uint16_t led0_blink_on;
24594 * If the LED #0 state is "blink" or "blinkalt", then
24595 * this field represents the requested time in milliseconds
24596 * to keep LED off between cycles.
24598 uint16_t led0_blink_off;
24600 * An identifier for the group of LEDs that LED #0 belongs
24602 * If set to 0, then the LED #0 is not grouped.
24603 * For all other non-zero values of this field, LED #0 is
24604 * grouped together with the LEDs with the same group ID
24607 uint8_t led0_group_id;
24608 /* An identifier for the LED #1. */
24610 /* The type of LED #1. */
24613 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
24615 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
24617 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
24618 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
24619 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
24620 /* The current state of the LED #1. */
24621 uint8_t led1_state;
24622 /* Default state of the LED */
24623 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
24625 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
24627 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
24629 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
24630 /* Blink Alternately */
24631 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
24632 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
24633 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
24634 /* The color of LED #1. */
24635 uint8_t led1_color;
24637 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
24639 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
24641 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
24642 /* Green or Amber */
24643 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
24644 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
24645 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
24648 * If the LED #1 state is "blink" or "blinkalt", then
24649 * this field represents the requested time in milliseconds
24650 * to keep LED on between cycles.
24652 uint16_t led1_blink_on;
24654 * If the LED #1 state is "blink" or "blinkalt", then
24655 * this field represents the requested time in milliseconds
24656 * to keep LED off between cycles.
24658 uint16_t led1_blink_off;
24660 * An identifier for the group of LEDs that LED #1 belongs
24662 * If set to 0, then the LED #1 is not grouped.
24663 * For all other non-zero values of this field, LED #1 is
24664 * grouped together with the LEDs with the same group ID
24667 uint8_t led1_group_id;
24668 /* An identifier for the LED #2. */
24670 /* The type of LED #2. */
24673 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
24675 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
24677 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
24678 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
24679 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
24680 /* The current state of the LED #2. */
24681 uint8_t led2_state;
24682 /* Default state of the LED */
24683 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
24685 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
24687 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
24689 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
24690 /* Blink Alternately */
24691 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
24692 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
24693 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
24694 /* The color of LED #2. */
24695 uint8_t led2_color;
24697 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
24699 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
24701 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
24702 /* Green or Amber */
24703 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
24704 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
24705 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
24708 * If the LED #2 state is "blink" or "blinkalt", then
24709 * this field represents the requested time in milliseconds
24710 * to keep LED on between cycles.
24712 uint16_t led2_blink_on;
24714 * If the LED #2 state is "blink" or "blinkalt", then
24715 * this field represents the requested time in milliseconds
24716 * to keep LED off between cycles.
24718 uint16_t led2_blink_off;
24720 * An identifier for the group of LEDs that LED #2 belongs
24722 * If set to 0, then the LED #2 is not grouped.
24723 * For all other non-zero values of this field, LED #2 is
24724 * grouped together with the LEDs with the same group ID
24727 uint8_t led2_group_id;
24728 /* An identifier for the LED #3. */
24730 /* The type of LED #3. */
24733 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
24735 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
24737 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
24738 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
24739 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
24740 /* The current state of the LED #3. */
24741 uint8_t led3_state;
24742 /* Default state of the LED */
24743 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
24745 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
24747 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
24749 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
24750 /* Blink Alternately */
24751 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
24752 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
24753 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
24754 /* The color of LED #3. */
24755 uint8_t led3_color;
24757 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
24759 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
24761 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
24762 /* Green or Amber */
24763 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
24764 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
24765 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
24768 * If the LED #3 state is "blink" or "blinkalt", then
24769 * this field represents the requested time in milliseconds
24770 * to keep LED on between cycles.
24772 uint16_t led3_blink_on;
24774 * If the LED #3 state is "blink" or "blinkalt", then
24775 * this field represents the requested time in milliseconds
24776 * to keep LED off between cycles.
24778 uint16_t led3_blink_off;
24780 * An identifier for the group of LEDs that LED #3 belongs
24782 * If set to 0, then the LED #3 is not grouped.
24783 * For all other non-zero values of this field, LED #3 is
24784 * grouped together with the LEDs with the same group ID
24787 uint8_t led3_group_id;
24788 uint8_t unused_4[6];
24790 * This field is used in Output records to indicate that the output
24791 * is completely written to RAM. This field should be read as '1'
24792 * to indicate that the output has been completely written.
24793 * When writing a command completion or response to an internal processor,
24794 * the order of writes has to be such that this field is written last.
24799 /***********************
24800 * hwrm_port_led_qcaps *
24801 ***********************/
24804 /* hwrm_port_led_qcaps_input (size:192b/24B) */
24805 struct hwrm_port_led_qcaps_input {
24806 /* The HWRM command request type. */
24809 * The completion ring to send the completion event on. This should
24810 * be the NQ ID returned from the `nq_alloc` HWRM command.
24812 uint16_t cmpl_ring;
24814 * The sequence ID is used by the driver for tracking multiple
24815 * commands. This ID is treated as opaque data by the firmware and
24816 * the value is returned in the `hwrm_resp_hdr` upon completion.
24820 * The target ID of the command:
24821 * * 0x0-0xFFF8 - The function ID
24822 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24823 * * 0xFFFD - Reserved for user-space HWRM interface
24826 uint16_t target_id;
24828 * A physical address pointer pointing to a host buffer that the
24829 * command's response data will be written. This can be either a host
24830 * physical address (HPA) or a guest physical address (GPA) and must
24831 * point to a physically contiguous block of memory.
24833 uint64_t resp_addr;
24834 /* Port ID of port whose LED configuration is being queried. */
24836 uint8_t unused_0[6];
24839 /* hwrm_port_led_qcaps_output (size:384b/48B) */
24840 struct hwrm_port_led_qcaps_output {
24841 /* The specific error status for the command. */
24842 uint16_t error_code;
24843 /* The HWRM command request type. */
24845 /* The sequence ID from the original command. */
24847 /* The length of the response data in number of bytes. */
24850 * The number of LEDs that are configured on this port.
24851 * Up to 4 LEDs can be returned in the response.
24854 /* Reserved for future use. */
24856 /* An identifier for the LED #0. */
24858 /* The type of LED #0. */
24861 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
24863 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
24865 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
24866 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
24867 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
24869 * An identifier for the group of LEDs that LED #0 belongs
24871 * If set to 0, then the LED #0 cannot be grouped.
24872 * For all other non-zero values of this field, LED #0 is
24873 * grouped together with the LEDs with the same group ID
24876 uint8_t led0_group_id;
24878 /* The states supported by LED #0. */
24879 uint16_t led0_state_caps;
24881 * If set to 1, this LED is enabled.
24882 * If set to 0, this LED is disabled.
24884 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
24887 * If set to 1, off state is supported on this LED.
24888 * If set to 0, off state is not supported on this LED.
24890 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
24893 * If set to 1, on state is supported on this LED.
24894 * If set to 0, on state is not supported on this LED.
24896 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
24899 * If set to 1, blink state is supported on this LED.
24900 * If set to 0, blink state is not supported on this LED.
24902 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
24905 * If set to 1, blink_alt state is supported on this LED.
24906 * If set to 0, blink_alt state is not supported on this LED.
24908 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
24910 /* The colors supported by LED #0. */
24911 uint16_t led0_color_caps;
24913 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
24916 * If set to 1, Amber color is supported on this LED.
24917 * If set to 0, Amber color is not supported on this LED.
24919 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
24922 * If set to 1, Green color is supported on this LED.
24923 * If set to 0, Green color is not supported on this LED.
24925 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
24927 /* An identifier for the LED #1. */
24929 /* The type of LED #1. */
24932 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
24934 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
24936 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
24937 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
24938 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
24940 * An identifier for the group of LEDs that LED #1 belongs
24942 * If set to 0, then the LED #0 cannot be grouped.
24943 * For all other non-zero values of this field, LED #0 is
24944 * grouped together with the LEDs with the same group ID
24947 uint8_t led1_group_id;
24949 /* The states supported by LED #1. */
24950 uint16_t led1_state_caps;
24952 * If set to 1, this LED is enabled.
24953 * If set to 0, this LED is disabled.
24955 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
24958 * If set to 1, off state is supported on this LED.
24959 * If set to 0, off state is not supported on this LED.
24961 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
24964 * If set to 1, on state is supported on this LED.
24965 * If set to 0, on state is not supported on this LED.
24967 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
24970 * If set to 1, blink state is supported on this LED.
24971 * If set to 0, blink state is not supported on this LED.
24973 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
24976 * If set to 1, blink_alt state is supported on this LED.
24977 * If set to 0, blink_alt state is not supported on this LED.
24979 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
24981 /* The colors supported by LED #1. */
24982 uint16_t led1_color_caps;
24984 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
24987 * If set to 1, Amber color is supported on this LED.
24988 * If set to 0, Amber color is not supported on this LED.
24990 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
24993 * If set to 1, Green color is supported on this LED.
24994 * If set to 0, Green color is not supported on this LED.
24996 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
24998 /* An identifier for the LED #2. */
25000 /* The type of LED #2. */
25003 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
25005 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
25007 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
25008 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
25009 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
25011 * An identifier for the group of LEDs that LED #0 belongs
25013 * If set to 0, then the LED #0 cannot be grouped.
25014 * For all other non-zero values of this field, LED #0 is
25015 * grouped together with the LEDs with the same group ID
25018 uint8_t led2_group_id;
25020 /* The states supported by LED #2. */
25021 uint16_t led2_state_caps;
25023 * If set to 1, this LED is enabled.
25024 * If set to 0, this LED is disabled.
25026 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
25029 * If set to 1, off state is supported on this LED.
25030 * If set to 0, off state is not supported on this LED.
25032 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
25035 * If set to 1, on state is supported on this LED.
25036 * If set to 0, on state is not supported on this LED.
25038 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
25041 * If set to 1, blink state is supported on this LED.
25042 * If set to 0, blink state is not supported on this LED.
25044 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
25047 * If set to 1, blink_alt state is supported on this LED.
25048 * If set to 0, blink_alt state is not supported on this LED.
25050 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
25052 /* The colors supported by LED #2. */
25053 uint16_t led2_color_caps;
25055 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
25058 * If set to 1, Amber color is supported on this LED.
25059 * If set to 0, Amber color is not supported on this LED.
25061 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
25064 * If set to 1, Green color is supported on this LED.
25065 * If set to 0, Green color is not supported on this LED.
25067 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
25069 /* An identifier for the LED #3. */
25071 /* The type of LED #3. */
25074 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
25076 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
25078 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
25079 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
25080 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
25082 * An identifier for the group of LEDs that LED #3 belongs
25084 * If set to 0, then the LED #0 cannot be grouped.
25085 * For all other non-zero values of this field, LED #0 is
25086 * grouped together with the LEDs with the same group ID
25089 uint8_t led3_group_id;
25091 /* The states supported by LED #3. */
25092 uint16_t led3_state_caps;
25094 * If set to 1, this LED is enabled.
25095 * If set to 0, this LED is disabled.
25097 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
25100 * If set to 1, off state is supported on this LED.
25101 * If set to 0, off state is not supported on this LED.
25103 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
25106 * If set to 1, on state is supported on this LED.
25107 * If set to 0, on state is not supported on this LED.
25109 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
25112 * If set to 1, blink state is supported on this LED.
25113 * If set to 0, blink state is not supported on this LED.
25115 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
25118 * If set to 1, blink_alt state is supported on this LED.
25119 * If set to 0, blink_alt state is not supported on this LED.
25121 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
25123 /* The colors supported by LED #3. */
25124 uint16_t led3_color_caps;
25126 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
25129 * If set to 1, Amber color is supported on this LED.
25130 * If set to 0, Amber color is not supported on this LED.
25132 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
25135 * If set to 1, Green color is supported on this LED.
25136 * If set to 0, Green color is not supported on this LED.
25138 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
25140 uint8_t unused_4[3];
25142 * This field is used in Output records to indicate that the output
25143 * is completely written to RAM. This field should be read as '1'
25144 * to indicate that the output has been completely written.
25145 * When writing a command completion or response to an internal processor,
25146 * the order of writes has to be such that this field is written last.
25151 /***********************
25152 * hwrm_port_prbs_test *
25153 ***********************/
25156 /* hwrm_port_prbs_test_input (size:384b/48B) */
25157 struct hwrm_port_prbs_test_input {
25158 /* The HWRM command request type. */
25161 * The completion ring to send the completion event on. This should
25162 * be the NQ ID returned from the `nq_alloc` HWRM command.
25164 uint16_t cmpl_ring;
25166 * The sequence ID is used by the driver for tracking multiple
25167 * commands. This ID is treated as opaque data by the firmware and
25168 * the value is returned in the `hwrm_resp_hdr` upon completion.
25172 * The target ID of the command:
25173 * * 0x0-0xFFF8 - The function ID
25174 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25175 * * 0xFFFD - Reserved for user-space HWRM interface
25178 uint16_t target_id;
25180 * A physical address pointer pointing to a host buffer that the
25181 * command's response data will be written. This can be either a host
25182 * physical address (HPA) or a guest physical address (GPA) and must
25183 * point to a physically contiguous block of memory.
25185 uint64_t resp_addr;
25186 /* Host address data is to DMA'd to. */
25187 uint64_t resp_data_addr;
25189 * Size of the buffer pointed to by resp_data_addr. The firmware may
25190 * use this entire buffer or less than the entire buffer, but never more.
25195 /* Port ID of port where PRBS test to be run. */
25197 /* Polynomial selection for PRBS test. */
25200 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
25202 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
25204 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
25206 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
25208 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
25210 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
25212 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
25214 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
25215 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
25216 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
25218 * Configuration bits for PRBS test.
25219 * Use enable bit to start/stop test.
25220 * Use tx/rx lane map bits to run test on specific lanes,
25221 * if set to 0 test will be run on all lanes.
25223 uint16_t prbs_config;
25225 * Set 0 to stop test currently in progress
25226 * Set 1 to start test with configuration provided.
25228 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
25231 * If set to 1, tx_lane_map bitmap should have lane bits set.
25232 * If set to 0, test will be run on all lanes for this port.
25234 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
25237 * If set to 1, rx_lane_map bitmap should have lane bits set.
25238 * If set to 0, test will be run on all lanes for this port.
25240 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
25242 /* Duration in seconds to run the PRBS test. */
25245 * If tx_lane_map_valid is set to 1, this field is a bitmap
25246 * of tx lanes to run PRBS test. bit0 = lane0,
25247 * bit1 = lane1 ..bit31 = lane31
25249 uint32_t tx_lane_map;
25251 * If rx_lane_map_valid is set to 1, this field is a bitmap
25252 * of rx lanes to run PRBS test. bit0 = lane0,
25253 * bit1 = lane1 ..bit31 = lane31
25255 uint32_t rx_lane_map;
25258 /* hwrm_port_prbs_test_output (size:128b/16B) */
25259 struct hwrm_port_prbs_test_output {
25260 /* The specific error status for the command. */
25261 uint16_t error_code;
25262 /* The HWRM command request type. */
25264 /* The sequence ID from the original command. */
25266 /* The length of the response data in number of bytes. */
25268 /* Total length of stored data. */
25269 uint16_t total_data_len;
25271 uint8_t unused_1[3];
25273 * This field is used in Output records to indicate that the output
25274 * is completely written to RAM. This field should be read as '1'
25275 * to indicate that the output has been completely written.
25276 * When writing a command completion or response to an internal processor,
25277 * the order of writes has to be such that this field is written last.
25282 /**********************
25283 * hwrm_port_dsc_dump *
25284 **********************/
25287 /* hwrm_port_dsc_dump_input (size:320b/40B) */
25288 struct hwrm_port_dsc_dump_input {
25289 /* The HWRM command request type. */
25292 * The completion ring to send the completion event on. This should
25293 * be the NQ ID returned from the `nq_alloc` HWRM command.
25295 uint16_t cmpl_ring;
25297 * The sequence ID is used by the driver for tracking multiple
25298 * commands. This ID is treated as opaque data by the firmware and
25299 * the value is returned in the `hwrm_resp_hdr` upon completion.
25303 * The target ID of the command:
25304 * * 0x0-0xFFF8 - The function ID
25305 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25306 * * 0xFFFD - Reserved for user-space HWRM interface
25309 uint16_t target_id;
25311 * A physical address pointer pointing to a host buffer that the
25312 * command's response data will be written. This can be either a host
25313 * physical address (HPA) or a guest physical address (GPA) and must
25314 * point to a physically contiguous block of memory.
25316 uint64_t resp_addr;
25317 /* Host address where response diagnostic data is returned. */
25318 uint64_t resp_data_addr;
25320 * Size of the buffer pointed to by resp_data_addr. The firmware
25321 * may use this entire buffer or less than the entire buffer, but
25327 /* Port ID of port where dsc dump to be collected. */
25329 /* Diag level specified by the user */
25330 uint16_t diag_level;
25331 /* SRDS_DIAG_LANE */
25332 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
25334 /* SRDS_DIAG_CORE */
25335 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
25337 /* SRDS_DIAG_EVENT */
25338 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
25340 /* SRDS_DIAG_EYE */
25341 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
25343 /* SRDS_DIAG_REG_CORE */
25344 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
25346 /* SRDS_DIAG_REG_LANE */
25347 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
25349 /* SRDS_DIAG_UC_CORE */
25350 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
25352 /* SRDS_DIAG_UC_LANE */
25353 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
25355 /* SRDS_DIAG_LANE_DEBUG */
25356 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
25358 /* SRDS_DIAG_BER_VERT */
25359 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
25361 /* SRDS_DIAG_BER_HORZ */
25362 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
25364 /* SRDS_DIAG_EVENT_SAFE */
25365 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
25367 /* SRDS_DIAG_TIMESTAMP */
25368 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
25370 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
25371 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
25373 * This field is a lane number
25374 * on which to collect the dsc dump
25376 uint16_t lane_number;
25378 * Configuration bits.
25379 * Use enable bit to start dsc dump or retrieve dump
25381 uint16_t dsc_dump_config;
25383 * Set 0 to retrieve the dsc dump
25384 * Set 1 to start the dsc dump
25386 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
25390 /* hwrm_port_dsc_dump_output (size:128b/16B) */
25391 struct hwrm_port_dsc_dump_output {
25392 /* The specific error status for the command. */
25393 uint16_t error_code;
25394 /* The HWRM command request type. */
25396 /* The sequence ID from the original command. */
25398 /* The length of the response data in number of bytes. */
25400 /* Total length of stored data. */
25401 uint16_t total_data_len;
25403 uint8_t unused_1[3];
25405 * This field is used in Output records to indicate that the output
25406 * is completely written to RAM. This field should be read as '1'
25407 * to indicate that the output has been completely written.
25408 * When writing a command completion or response to an internal processor,
25409 * the order of writes has to be such that this field is written last.
25414 /******************************
25415 * hwrm_port_sfp_sideband_cfg *
25416 ******************************/
25419 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
25420 struct hwrm_port_sfp_sideband_cfg_input {
25421 /* The HWRM command request type. */
25424 * The completion ring to send the completion event on. This should
25425 * be the NQ ID returned from the `nq_alloc` HWRM command.
25427 uint16_t cmpl_ring;
25429 * The sequence ID is used by the driver for tracking multiple
25430 * commands. This ID is treated as opaque data by the firmware and
25431 * the value is returned in the `hwrm_resp_hdr` upon completion.
25435 * The target ID of the command:
25436 * * 0x0-0xFFF8 - The function ID
25437 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25438 * * 0xFFFD - Reserved for user-space HWRM interface
25441 uint16_t target_id;
25443 * A physical address pointer pointing to a host buffer that the
25444 * command's response data will be written. This can be either a host
25445 * physical address (HPA) or a guest physical address (GPA) and must
25446 * point to a physically contiguous block of memory.
25448 uint64_t resp_addr;
25449 /* Port ID of port that is to be queried. */
25451 uint8_t unused_0[6];
25453 * This bitfield is used to specify which bits from the 'flags'
25454 * fields are being configured by the caller.
25457 /* This bit must be '1' for rs0 to be configured. */
25458 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
25460 /* This bit must be '1' for rs1 to be configured. */
25461 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
25463 /* This bit must be '1' for tx_disable to be configured. */
25464 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
25467 * This bit must be '1' for mod_sel to be configured.
25468 * Valid only on QSFP modules
25470 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
25472 /* This bit must be '1' for reset_l to be configured. */
25473 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
25475 /* This bit must be '1' for lp_mode to be configured. */
25476 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
25478 /* This bit must be '1' for pwr_disable to be configured. */
25479 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
25482 * Only bits that have corresponding bits in the 'enables'
25483 * bitfield are processed by the firmware, all other bits
25484 * of 'flags' are ignored.
25488 * This bit along with rs1 configures the current speed of the dual
25489 * rate module. If these pins are GNDed then the speed can be changed
25490 * by driectly writing to EEPROM.
25492 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
25495 * This bit along with rs0 configures the current speed of the dual
25496 * rate module. If these pins are GNDed then the speed can be changed
25497 * by driectly writing to EEPROM.
25499 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
25502 * When this bit is set to '1', tx_disable is set.
25503 * On a 1G BASE-T module, if this bit is set,
25504 * module PHY registers will not be accessible.
25506 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
25509 * When this bit is set to '1', this module is selected.
25510 * Valid only on QSFP modules
25512 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
25515 * If reset_l is set to 0, Module will be taken out of reset
25516 * and other signals will be set to their requested state once
25517 * the module is out of reset.
25518 * Valid only on QSFP modules
25520 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
25523 * When this bit is set to '1', the module will be configured
25524 * in low power mode.
25525 * Valid only on QSFP modules
25527 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
25529 /* When this bit is set to '1', the module will be powered down. */
25530 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
25534 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
25535 struct hwrm_port_sfp_sideband_cfg_output {
25536 /* The specific error status for the command. */
25537 uint16_t error_code;
25538 /* The HWRM command request type. */
25540 /* The sequence ID from the original command. */
25542 /* The length of the response data in number of bytes. */
25546 * This field is used in Output records to indicate that the output
25547 * is completely written to RAM. This field should be read as '1'
25548 * to indicate that the output has been completely written. When
25549 * writing a command completion or response to an internal processor,
25550 * the order of writes has to be such that this field is written last.
25555 /*******************************
25556 * hwrm_port_sfp_sideband_qcfg *
25557 *******************************/
25560 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
25561 struct hwrm_port_sfp_sideband_qcfg_input {
25562 /* The HWRM command request type. */
25565 * The completion ring to send the completion event on. This should
25566 * be the NQ ID returned from the `nq_alloc` HWRM command.
25568 uint16_t cmpl_ring;
25570 * The sequence ID is used by the driver for tracking multiple
25571 * commands. This ID is treated as opaque data by the firmware and
25572 * the value is returned in the `hwrm_resp_hdr` upon completion.
25576 * The target ID of the command:
25577 * * 0x0-0xFFF8 - The function ID
25578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25579 * * 0xFFFD - Reserved for user-space HWRM interface
25582 uint16_t target_id;
25584 * A physical address pointer pointing to a host buffer that the
25585 * command's response data will be written. This can be either a host
25586 * physical address (HPA) or a guest physical address (GPA) and must
25587 * point to a physically contiguous block of memory.
25589 uint64_t resp_addr;
25590 /* Port ID of port that is to be queried. */
25592 uint8_t unused_0[6];
25595 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
25596 struct hwrm_port_sfp_sideband_qcfg_output {
25597 /* The specific error status for the command. */
25598 uint16_t error_code;
25599 /* The HWRM command request type. */
25601 /* The sequence ID from the original command. */
25603 /* The length of the response data in number of bytes. */
25606 * Bitmask indicating which sideband signals are valid.
25607 * This is based on the board and nvm cfg that is present on the board.
25609 uint32_t supported_mask;
25610 uint32_t sideband_signals;
25611 /* When this bit is set to '1', the Module is absent. */
25612 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
25615 * When this bit is set to '1', there is no valid signal on RX.
25616 * This signal is a filtered version of Signal Detect.
25618 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
25621 * This bit along with rs1 indiactes the current speed of the dual
25622 * rate module.If these pins are grounded then the speed can be
25623 * changed by driectky writing to EEPROM.
25625 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
25628 * This bit along with rs0 indiactes the current speed of the dual
25629 * rate module.If these pins are grounded then the speed can be
25630 * changed by driectky writing to EEPROM.
25632 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
25635 * When this bit is set to '1', tx_disable is set.
25636 * On a 1G BASE-T module, if this bit is set, module PHY
25637 * registers will not be accessible.
25639 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
25641 /* When this bit is set to '1', tx_fault is set. */
25642 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
25645 * When this bit is set to '1', module is selected.
25646 * Valid only on QSFP modules
25648 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
25651 * When this bit is set to '0', the module is held in reset.
25652 * if reset_l is set to 1,first module is taken out of reset
25653 * and other signals will be set to their requested state.
25654 * Valid only on QSFP modules.
25656 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
25659 * When this bit is set to '1', the module is in low power mode.
25660 * Valid only on QSFP modules
25662 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
25664 /* When this bit is set to '1', module is in power down state. */
25665 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
25669 * This field is used in Output records to indicate that the output
25670 * is completely written to RAM. This field should be read as '1'
25671 * to indicate that the output has been completely written. When
25672 * writing a command completion or response to an internal processor,
25673 * the order of writes has to be such that this field is written last.
25678 /**********************************
25679 * hwrm_port_phy_mdio_bus_acquire *
25680 **********************************/
25683 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
25684 struct hwrm_port_phy_mdio_bus_acquire_input {
25685 /* The HWRM command request type. */
25688 * The completion ring to send the completion event on. This should
25689 * be the NQ ID returned from the `nq_alloc` HWRM command.
25691 uint16_t cmpl_ring;
25693 * The sequence ID is used by the driver for tracking multiple
25694 * commands. This ID is treated as opaque data by the firmware and
25695 * the value is returned in the `hwrm_resp_hdr` upon completion.
25699 * The target ID of the command:
25700 * * 0x0-0xFFF8 - The function ID
25701 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25702 * * 0xFFFD - Reserved for user-space HWRM interface
25705 uint16_t target_id;
25707 * A physical address pointer pointing to a host buffer that the
25708 * command's response data will be written. This can be either a host
25709 * physical address (HPA) or a guest physical address (GPA) and must
25710 * point to a physically contiguous block of memory.
25712 uint64_t resp_addr;
25713 /* Port ID of the port. */
25716 * client_id of the client requesting BUS access.
25717 * Any value from 0x10 to 0xFFFF can be used.
25718 * Client should make sure that the returned client_id
25719 * in response matches the client_id in request.
25720 * 0-0xF are reserved for internal use.
25722 uint16_t client_id;
25724 * Timeout in milli seconds, MDIO BUS will be released automatically
25725 * after this time, if another mdio acquire command is not received
25726 * within the timeout window from the same client.
25727 * A 0xFFFF will hold the bus until this bus is released.
25729 uint16_t mdio_bus_timeout;
25730 uint8_t unused_0[2];
25733 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
25734 struct hwrm_port_phy_mdio_bus_acquire_output {
25735 /* The specific error status for the command. */
25736 uint16_t error_code;
25737 /* The HWRM command request type. */
25739 /* The sequence ID from the original command. */
25741 /* The length of the response data in number of bytes. */
25745 * client_id of the module holding the BUS.
25746 * 0-0xF are reserved for internal use.
25748 uint16_t client_id;
25749 uint8_t unused_1[3];
25751 * This field is used in Output records to indicate that the output
25752 * is completely written to RAM. This field should be read as '1'
25753 * to indicate that the output has been completely written.
25754 * When writing a command completion or response to an internal processor,
25755 * the order of writes has to be such that this field is written last.
25760 /**********************************
25761 * hwrm_port_phy_mdio_bus_release *
25762 **********************************/
25765 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
25766 struct hwrm_port_phy_mdio_bus_release_input {
25767 /* The HWRM command request type. */
25770 * The completion ring to send the completion event on. This should
25771 * be the NQ ID returned from the `nq_alloc` HWRM command.
25773 uint16_t cmpl_ring;
25775 * The sequence ID is used by the driver for tracking multiple
25776 * commands. This ID is treated as opaque data by the firmware and
25777 * the value is returned in the `hwrm_resp_hdr` upon completion.
25781 * The target ID of the command:
25782 * * 0x0-0xFFF8 - The function ID
25783 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25784 * * 0xFFFD - Reserved for user-space HWRM interface
25787 uint16_t target_id;
25789 * A physical address pointer pointing to a host buffer that the
25790 * command's response data will be written. This can be either a host
25791 * physical address (HPA) or a guest physical address (GPA) and must
25792 * point to a physically contiguous block of memory.
25794 uint64_t resp_addr;
25795 /* Port ID of the port. */
25798 * client_id of the client requesting BUS release.
25799 * A client should not release any other clients BUS.
25801 uint16_t client_id;
25802 uint8_t unused_0[4];
25805 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
25806 struct hwrm_port_phy_mdio_bus_release_output {
25807 /* The specific error status for the command. */
25808 uint16_t error_code;
25809 /* The HWRM command request type. */
25811 /* The sequence ID from the original command. */
25813 /* The length of the response data in number of bytes. */
25816 /* The BUS is released if client_id matches the client_id in request. */
25817 uint16_t clients_id;
25818 uint8_t unused_1[3];
25820 * This field is used in Output records to indicate that the output
25821 * is completely written to RAM. This field should be read as '1'
25822 * to indicate that the output has been completely written.
25823 * When writing a command completion or response to an internal processor,
25824 * the order of writes has to be such that this field is written last.
25829 /************************
25830 * hwrm_port_tx_fir_cfg *
25831 ************************/
25834 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
25835 struct hwrm_port_tx_fir_cfg_input {
25836 /* The HWRM command request type. */
25839 * The completion ring to send the completion event on. This should
25840 * be the NQ ID returned from the `nq_alloc` HWRM command.
25842 uint16_t cmpl_ring;
25844 * The sequence ID is used by the driver for tracking multiple
25845 * commands. This ID is treated as opaque data by the firmware and
25846 * the value is returned in the `hwrm_resp_hdr` upon completion.
25850 * The target ID of the command:
25851 * * 0x0-0xFFF8 - The function ID
25852 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25853 * * 0xFFFD - Reserved for user-space HWRM interface
25856 uint16_t target_id;
25858 * A physical address pointer pointing to a host buffer that the
25859 * command's response data will be written. This can be either a host
25860 * physical address (HPA) or a guest physical address (GPA) and must
25861 * point to a physically contiguous block of memory.
25863 uint64_t resp_addr;
25864 /* Modulation types of TX FIR: NRZ, PAM4. */
25867 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
25869 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
25870 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
25871 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
25872 /* The lane mask of the lane TX FIR will be configured. */
25874 uint8_t unused_0[2];
25875 /* Value1 of TX FIR, required for NRZ or PAM4. */
25876 uint32_t txfir_val_1;
25877 /* Value2 of TX FIR, required for NRZ or PAM4. */
25878 uint32_t txfir_val_2;
25879 /* Value3 of TX FIR, required for PAM4. */
25880 uint32_t txfir_val_3;
25881 /* Value4 of TX FIR, required for PAM4. */
25882 uint32_t txfir_val_4;
25883 uint8_t unused_1[4];
25886 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
25887 struct hwrm_port_tx_fir_cfg_output {
25888 /* The specific error status for the command. */
25889 uint16_t error_code;
25890 /* The HWRM command request type. */
25892 /* The sequence ID from the original command. */
25894 /* The length of the response data in number of bytes. */
25898 * This field is used in Output records to indicate that the output
25899 * is completely written to RAM. This field should be read as '1'
25900 * to indicate that the output has been completely written.
25901 * When writing a command completion or response to an internal processor,
25902 * the order of writes has to be such that this field is written last.
25907 /*************************
25908 * hwrm_port_tx_fir_qcfg *
25909 *************************/
25912 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
25913 struct hwrm_port_tx_fir_qcfg_input {
25914 /* The HWRM command request type. */
25917 * The completion ring to send the completion event on. This should
25918 * be the NQ ID returned from the `nq_alloc` HWRM command.
25920 uint16_t cmpl_ring;
25922 * The sequence ID is used by the driver for tracking multiple
25923 * commands. This ID is treated as opaque data by the firmware and
25924 * the value is returned in the `hwrm_resp_hdr` upon completion.
25928 * The target ID of the command:
25929 * * 0x0-0xFFF8 - The function ID
25930 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25931 * * 0xFFFD - Reserved for user-space HWRM interface
25934 uint16_t target_id;
25936 * A physical address pointer pointing to a host buffer that the
25937 * command's response data will be written. This can be either a host
25938 * physical address (HPA) or a guest physical address (GPA) and must
25939 * point to a physically contiguous block of memory.
25941 uint64_t resp_addr;
25942 /* Modulation types of TX FIR: NRZ, PAM4. */
25945 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
25947 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
25948 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
25949 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
25950 /* The ID of the lane TX FIR will be queried. */
25955 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
25956 struct hwrm_port_tx_fir_qcfg_output {
25957 /* The specific error status for the command. */
25958 uint16_t error_code;
25959 /* The HWRM command request type. */
25961 /* The sequence ID from the original command. */
25963 /* The length of the response data in number of bytes. */
25965 /* Value1 of TX FIR, required for NRZ or PAM4. */
25966 uint32_t txfir_val_1;
25967 /* Value2 of TX FIR, required for NRZ or PAM4. */
25968 uint32_t txfir_val_2;
25969 /* Value3 of TX FIR, required for PAM4. */
25970 uint32_t txfir_val_3;
25971 /* Value4 of TX FIR, required for PAM4. */
25972 uint32_t txfir_val_4;
25975 * This field is used in Output records to indicate that the output
25976 * is completely written to RAM. This field should be read as '1'
25977 * to indicate that the output has been completely written.
25978 * When writing a command completion or response to an internal processor,
25979 * the order of writes has to be such that this field is written last.
25984 /***********************
25985 * hwrm_queue_qportcfg *
25986 ***********************/
25989 /* hwrm_queue_qportcfg_input (size:192b/24B) */
25990 struct hwrm_queue_qportcfg_input {
25991 /* The HWRM command request type. */
25994 * The completion ring to send the completion event on. This should
25995 * be the NQ ID returned from the `nq_alloc` HWRM command.
25997 uint16_t cmpl_ring;
25999 * The sequence ID is used by the driver for tracking multiple
26000 * commands. This ID is treated as opaque data by the firmware and
26001 * the value is returned in the `hwrm_resp_hdr` upon completion.
26005 * The target ID of the command:
26006 * * 0x0-0xFFF8 - The function ID
26007 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26008 * * 0xFFFD - Reserved for user-space HWRM interface
26011 uint16_t target_id;
26013 * A physical address pointer pointing to a host buffer that the
26014 * command's response data will be written. This can be either a host
26015 * physical address (HPA) or a guest physical address (GPA) and must
26016 * point to a physically contiguous block of memory.
26018 uint64_t resp_addr;
26021 * Enumeration denoting the RX, TX type of the resource.
26022 * This enumeration is used for resources that are similar for both
26023 * TX and RX paths of the chip.
26025 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26027 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26029 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26030 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
26031 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
26033 * Port ID of port for which the queue configuration is being
26034 * queried. This field is only required when sent by IPC.
26038 * Drivers will set this capability when it can use
26039 * queue_idx_service_profile to map the queues to application.
26041 uint8_t drv_qmap_cap;
26043 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
26045 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
26046 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
26047 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
26051 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
26052 struct hwrm_queue_qportcfg_output {
26053 /* The specific error status for the command. */
26054 uint16_t error_code;
26055 /* The HWRM command request type. */
26057 /* The sequence ID from the original command. */
26059 /* The length of the response data in number of bytes. */
26062 * The maximum number of queues that can be configured on this
26064 * Valid values range from 1 through 8.
26066 uint8_t max_configurable_queues;
26068 * The maximum number of lossless queues that can be configured
26070 * Valid values range from 0 through 8.
26072 uint8_t max_configurable_lossless_queues;
26074 * Bitmask indicating which queues can be configured by the
26075 * hwrm_queue_cfg command.
26077 * Each bit represents a specific queue where bit 0 represents
26078 * queue 0 and bit 7 represents queue 7.
26079 * # A value of 0 indicates that the queue is not configurable
26080 * by the hwrm_queue_cfg command.
26081 * # A value of 1 indicates that the queue is configurable.
26082 * # A hwrm_queue_cfg command shall return error when trying to
26083 * configure a queue not configurable.
26085 uint8_t queue_cfg_allowed;
26086 /* Information about queue configuration. */
26087 uint8_t queue_cfg_info;
26089 * If this flag is set to '1', then the queues are
26090 * configured asymmetrically on TX and RX sides.
26091 * If this flag is set to '0', then the queues are
26092 * configured symmetrically on TX and RX sides. For
26093 * symmetric configuration, the queue configuration
26094 * including queue ids and service profiles on the
26095 * TX side is the same as the corresponding queue
26096 * configuration on the RX side.
26098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
26101 * Bitmask indicating which queues can be configured by the
26102 * hwrm_queue_pfcenable_cfg command.
26104 * Each bit represents a specific priority where bit 0 represents
26105 * priority 0 and bit 7 represents priority 7.
26106 * # A value of 0 indicates that the priority is not configurable by
26107 * the hwrm_queue_pfcenable_cfg command.
26108 * # A value of 1 indicates that the priority is configurable.
26109 * # A hwrm_queue_pfcenable_cfg command shall return error when
26110 * trying to configure a priority that is not configurable.
26112 uint8_t queue_pfcenable_cfg_allowed;
26114 * Bitmask indicating which queues can be configured by the
26115 * hwrm_queue_pri2cos_cfg command.
26117 * Each bit represents a specific queue where bit 0 represents
26118 * queue 0 and bit 7 represents queue 7.
26119 * # A value of 0 indicates that the queue is not configurable
26120 * by the hwrm_queue_pri2cos_cfg command.
26121 * # A value of 1 indicates that the queue is configurable.
26122 * # A hwrm_queue_pri2cos_cfg command shall return error when
26123 * trying to configure a queue that is not configurable.
26125 uint8_t queue_pri2cos_cfg_allowed;
26127 * Bitmask indicating which queues can be configured by the
26128 * hwrm_queue_pri2cos_cfg command.
26130 * Each bit represents a specific queue where bit 0 represents
26131 * queue 0 and bit 7 represents queue 7.
26132 * # A value of 0 indicates that the queue is not configurable
26133 * by the hwrm_queue_pri2cos_cfg command.
26134 * # A value of 1 indicates that the queue is configurable.
26135 * # A hwrm_queue_pri2cos_cfg command shall return error when
26136 * trying to configure a queue not configurable.
26138 uint8_t queue_cos2bw_cfg_allowed;
26140 * ID of CoS Queue 0.
26143 * # This ID can be used on any subsequent call to an hwrm command
26144 * that takes a queue id.
26145 * # IDs must always be queried by this command before any use
26146 * by the driver or software.
26147 * # The CoS queue index is obtained by applying modulo 10 to the
26148 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26149 * The CoS queue index is used to reference port statistics for the
26151 * # A value of 0xff indicates that the queue is not available.
26152 * # Available queues may not be in sequential order.
26155 /* This value specifies service profile kind for CoS queue */
26156 uint8_t queue_id0_service_profile;
26157 /* Lossy (best-effort) */
26158 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
26161 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
26163 /* Lossless RoCE (deprecated) */
26164 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
26166 /* Lossy RoCE CNP (deprecated) */
26167 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26169 /* Lossless NIC (deprecated) */
26170 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
26172 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26173 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
26175 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
26176 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
26178 * ID of CoS Queue 1.
26181 * # This ID can be used on any subsequent call to an hwrm command
26182 * that takes a queue id.
26183 * # IDs must always be queried by this command before any use
26184 * by the driver or software.
26185 * # The CoS queue index is obtained by applying modulo 10 to the
26186 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26187 * The CoS queue index is used to reference port statistics for the
26189 * # A value of 0xff indicates that the queue is not available.
26190 * # Available queues may not be in sequential order.
26193 /* This value specifies service profile kind for CoS queue */
26194 uint8_t queue_id1_service_profile;
26195 /* Lossy (best-effort) */
26196 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
26199 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
26201 /* Lossless RoCE (deprecated) */
26202 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
26204 /* Lossy RoCE CNP (deprecated) */
26205 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26207 /* Lossless NIC (deprecated) */
26208 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
26210 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26211 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
26213 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
26214 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
26216 * ID of CoS Queue 2.
26219 * # This ID can be used on any subsequent call to an hwrm command
26220 * that takes a queue id.
26221 * # IDs must always be queried by this command before any use
26222 * by the driver or software.
26223 * # The CoS queue index is obtained by applying modulo 10 to the
26224 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26225 * The CoS queue index is used to reference port statistics for the
26227 * # A value of 0xff indicates that the queue is not available.
26228 * # Available queues may not be in sequential order.
26231 /* This value specifies service profile kind for CoS queue */
26232 uint8_t queue_id2_service_profile;
26233 /* Lossy (best-effort) */
26234 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
26237 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
26239 /* Lossless RoCE (deprecated) */
26240 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
26242 /* Lossy RoCE CNP (deprecated) */
26243 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26245 /* Lossless NIC (deprecated) */
26246 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
26248 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26249 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
26251 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
26252 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
26254 * ID of CoS Queue 3.
26257 * # This ID can be used on any subsequent call to an hwrm command
26258 * that takes a queue id.
26259 * # IDs must always be queried by this command before any use
26260 * by the driver or software.
26261 * # The CoS queue index is obtained by applying modulo 10 to the
26262 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26263 * The CoS queue index is used to reference port statistics for the
26265 * # A value of 0xff indicates that the queue is not available.
26266 * # Available queues may not be in sequential order.
26269 /* This value specifies service profile kind for CoS queue */
26270 uint8_t queue_id3_service_profile;
26271 /* Lossy (best-effort) */
26272 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
26275 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
26277 /* Lossless RoCE (deprecated) */
26278 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
26280 /* Lossy RoCE CNP (deprecated) */
26281 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26283 /* Lossless NIC (deprecated) */
26284 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
26286 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26287 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
26289 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
26290 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
26292 * ID of CoS Queue 4.
26295 * # This ID can be used on any subsequent call to an hwrm command
26296 * that takes a queue id.
26297 * # IDs must always be queried by this command before any use
26298 * by the driver or software.
26299 * # The CoS queue index is obtained by applying modulo 10 to the
26300 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26301 * The CoS queue index is used to reference port statistics for the
26303 * # A value of 0xff indicates that the queue is not available.
26304 * # Available queues may not be in sequential order.
26307 /* This value specifies service profile kind for CoS queue */
26308 uint8_t queue_id4_service_profile;
26309 /* Lossy (best-effort) */
26310 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
26313 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
26315 /* Lossless RoCE (deprecated) */
26316 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
26318 /* Lossy RoCE CNP (deprecated) */
26319 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26321 /* Lossless NIC (deprecated) */
26322 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
26324 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26325 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
26327 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
26328 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
26330 * ID of CoS Queue 5.
26333 * # This ID can be used on any subsequent call to an hwrm command
26334 * that takes a queue id.
26335 * # IDs must always be queried by this command before any use
26336 * by the driver or software.
26337 * # The CoS queue index is obtained by applying modulo 10 to the
26338 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26339 * The CoS queue index is used to reference port statistics for the
26341 * # A value of 0xff indicates that the queue is not available.
26342 * # Available queues may not be in sequential order.
26345 /* This value specifies service profile kind for CoS queue */
26346 uint8_t queue_id5_service_profile;
26347 /* Lossy (best-effort) */
26348 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
26351 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
26353 /* Lossless RoCE (deprecated) */
26354 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
26356 /* Lossy RoCE CNP (deprecated) */
26357 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26359 /* Lossless NIC (deprecated) */
26360 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
26362 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26363 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
26365 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
26366 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
26368 * ID of CoS Queue 6.
26371 * # This ID can be used on any subsequent call to an hwrm command
26372 * that takes a queue id.
26373 * # IDs must always be queried by this command before any use
26374 * by the driver or software.
26375 * # The CoS queue index is obtained by applying modulo 10 to the
26376 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26377 * The CoS queue index is used to reference port statistics for the
26379 * # A value of 0xff indicates that the queue is not available.
26380 * # Available queues may not be in sequential order.
26383 /* This value specifies service profile kind for CoS queue */
26384 uint8_t queue_id6_service_profile;
26385 /* Lossy (best-effort) */
26386 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
26389 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
26391 /* Lossless RoCE (deprecated) */
26392 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
26394 /* Lossy RoCE CNP (deprecated) */
26395 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26397 /* Lossless NIC (deprecated) */
26398 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
26400 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26401 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
26403 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
26404 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
26406 * ID of CoS Queue 7.
26409 * # This ID can be used on any subsequent call to an hwrm command
26410 * that takes a queue id.
26411 * # IDs must always be queried by this command before any use
26412 * by the driver or software.
26413 * # The CoS queue index is obtained by applying modulo 10 to the
26414 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
26415 * The CoS queue index is used to reference port statistics for the
26417 * # A value of 0xff indicates that the queue is not available.
26418 * # Available queues may not be in sequential order.
26421 /* This value specifies service profile kind for CoS queue */
26422 uint8_t queue_id7_service_profile;
26423 /* Lossy (best-effort) */
26424 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
26427 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
26429 /* Lossless RoCE (deprecated) */
26430 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
26432 /* Lossy RoCE CNP (deprecated) */
26433 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
26435 /* Lossless NIC (deprecated) */
26436 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
26438 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26439 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
26441 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
26442 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
26444 * This value specifies traffic type for the service profile. We can
26445 * have a TC mapped to multiple traffic types. For example shared
26446 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26447 * A value of zero is considered as invalid.
26449 uint8_t queue_id0_service_profile_type;
26450 /* Recommended to be used for RoCE traffic only. */
26451 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
26453 /* Recommended to be used for NIC/L2 traffic only. */
26454 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
26456 /* Recommended to be used for CNP traffic only. */
26457 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
26460 * Up to 16 bytes of null padded ASCII string describing this queue.
26461 * The queue name includes a CoS queue index and, in some cases, text
26462 * that distinguishes the queue from other queues in the group.
26464 char qid0_name[16];
26465 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26466 char qid1_name[16];
26467 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26468 char qid2_name[16];
26469 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26470 char qid3_name[16];
26471 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26472 char qid4_name[16];
26473 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26474 char qid5_name[16];
26475 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26476 char qid6_name[16];
26477 /* Up to 16 bytes of null padded ASCII string describing this queue. */
26478 char qid7_name[16];
26480 * This value specifies traffic type for the service profile. We can
26481 * have a TC mapped to multiple traffic types. For example shared
26482 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26483 * A value of zero is considered as invalid.
26485 uint8_t queue_id1_service_profile_type;
26486 /* Recommended to be used for RoCE traffic only. */
26487 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
26489 /* Recommended to be used for NIC/L2 traffic only. */
26490 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
26492 /* Recommended to be used for CNP traffic only. */
26493 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
26496 * This value specifies traffic type for the service profile. We can
26497 * have a TC mapped to multiple traffic types. For example shared
26498 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26499 * A value of zero is considered as invalid.
26501 uint8_t queue_id2_service_profile_type;
26502 /* Recommended to be used for RoCE traffic only. */
26503 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
26505 /* Recommended to be used for NIC/L2 traffic only. */
26506 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
26508 /* Recommended to be used for CNP traffic only. */
26509 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
26512 * This value specifies traffic type for the service profile. We can
26513 * have a TC mapped to multiple traffic types. For example shared
26514 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26515 * A value of zero is considered as invalid.
26517 uint8_t queue_id3_service_profile_type;
26518 /* Recommended to be used for RoCE traffic only. */
26519 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
26521 /* Recommended to be used for NIC/L2 traffic only. */
26522 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
26524 /* Recommended to be used for CNP traffic only. */
26525 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
26528 * This value specifies traffic type for the service profile. We can
26529 * have a TC mapped to multiple traffic types. For example shared
26530 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26531 * A value of zero is considered as invalid.
26533 uint8_t queue_id4_service_profile_type;
26534 /* Recommended to be used for RoCE traffic only. */
26535 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
26537 /* Recommended to be used for NIC/L2 traffic only. */
26538 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
26540 /* Recommended to be used for CNP traffic only. */
26541 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
26544 * This value specifies traffic type for the service profile. We can
26545 * have a TC mapped to multiple traffic types. For example shared
26546 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26547 * A value of zero is considered as invalid.
26549 uint8_t queue_id5_service_profile_type;
26550 /* Recommended to be used for RoCE traffic only. */
26551 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
26553 /* Recommended to be used for NIC/L2 traffic only. */
26554 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
26556 /* Recommended to be used for CNP traffic only. */
26557 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
26560 * This value specifies traffic type for the service profile. We can
26561 * have a TC mapped to multiple traffic types. For example shared
26562 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26563 * A value of zero is considered as invalid.
26565 uint8_t queue_id6_service_profile_type;
26566 /* Recommended to be used for RoCE traffic only. */
26567 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
26569 /* Recommended to be used for NIC/L2 traffic only. */
26570 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
26572 /* Recommended to be used for CNP traffic only. */
26573 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
26576 * This value specifies traffic type for the service profile. We can
26577 * have a TC mapped to multiple traffic types. For example shared
26578 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
26579 * A value of zero is considered as invalid.
26581 uint8_t queue_id7_service_profile_type;
26582 /* Recommended to be used for RoCE traffic only. */
26583 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
26585 /* Recommended to be used for NIC/L2 traffic only. */
26586 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
26588 /* Recommended to be used for CNP traffic only. */
26589 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
26592 * This field is used in Output records to indicate that the output
26593 * is completely written to RAM. This field should be read as '1'
26594 * to indicate that the output has been completely written.
26595 * When writing a command completion or response to an internal processor,
26596 * the order of writes has to be such that this field is written last.
26601 /*******************
26602 * hwrm_queue_qcfg *
26603 *******************/
26606 /* hwrm_queue_qcfg_input (size:192b/24B) */
26607 struct hwrm_queue_qcfg_input {
26608 /* The HWRM command request type. */
26611 * The completion ring to send the completion event on. This should
26612 * be the NQ ID returned from the `nq_alloc` HWRM command.
26614 uint16_t cmpl_ring;
26616 * The sequence ID is used by the driver for tracking multiple
26617 * commands. This ID is treated as opaque data by the firmware and
26618 * the value is returned in the `hwrm_resp_hdr` upon completion.
26622 * The target ID of the command:
26623 * * 0x0-0xFFF8 - The function ID
26624 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26625 * * 0xFFFD - Reserved for user-space HWRM interface
26628 uint16_t target_id;
26630 * A physical address pointer pointing to a host buffer that the
26631 * command's response data will be written. This can be either a host
26632 * physical address (HPA) or a guest physical address (GPA) and must
26633 * point to a physically contiguous block of memory.
26635 uint64_t resp_addr;
26638 * Enumeration denoting the RX, TX type of the resource.
26639 * This enumeration is used for resources that are similar for both
26640 * TX and RX paths of the chip.
26642 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26644 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26646 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26647 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
26648 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
26649 /* Queue ID of the queue. */
26653 /* hwrm_queue_qcfg_output (size:128b/16B) */
26654 struct hwrm_queue_qcfg_output {
26655 /* The specific error status for the command. */
26656 uint16_t error_code;
26657 /* The HWRM command request type. */
26659 /* The sequence ID from the original command. */
26661 /* The length of the response data in number of bytes. */
26664 * This value is the estimate packet length used in the
26667 uint32_t queue_len;
26668 /* This value is applicable to CoS queues only. */
26669 uint8_t service_profile;
26670 /* Lossy (best-effort) */
26671 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
26673 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
26674 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26675 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
26676 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
26677 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
26678 /* Information about queue configuration. */
26679 uint8_t queue_cfg_info;
26681 * If this flag is set to '1', then the queue is
26682 * configured asymmetrically on TX and RX sides.
26683 * If this flag is set to '0', then this queue is
26684 * configured symmetrically on TX and RX sides.
26686 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
26690 * This field is used in Output records to indicate that the output
26691 * is completely written to RAM. This field should be read as '1'
26692 * to indicate that the output has been completely written.
26693 * When writing a command completion or response to an internal processor,
26694 * the order of writes has to be such that this field is written last.
26699 /******************
26701 ******************/
26704 /* hwrm_queue_cfg_input (size:320b/40B) */
26705 struct hwrm_queue_cfg_input {
26706 /* The HWRM command request type. */
26709 * The completion ring to send the completion event on. This should
26710 * be the NQ ID returned from the `nq_alloc` HWRM command.
26712 uint16_t cmpl_ring;
26714 * The sequence ID is used by the driver for tracking multiple
26715 * commands. This ID is treated as opaque data by the firmware and
26716 * the value is returned in the `hwrm_resp_hdr` upon completion.
26720 * The target ID of the command:
26721 * * 0x0-0xFFF8 - The function ID
26722 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26723 * * 0xFFFD - Reserved for user-space HWRM interface
26726 uint16_t target_id;
26728 * A physical address pointer pointing to a host buffer that the
26729 * command's response data will be written. This can be either a host
26730 * physical address (HPA) or a guest physical address (GPA) and must
26731 * point to a physically contiguous block of memory.
26733 uint64_t resp_addr;
26736 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
26737 * This enumeration is used for resources that are similar for both
26738 * TX and RX paths of the chip.
26740 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
26741 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
26743 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26745 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26746 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
26747 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
26748 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
26749 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
26752 * This bit must be '1' for the dflt_len field to be
26755 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
26757 * This bit must be '1' for the service_profile field to be
26760 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
26761 /* Queue ID of queue that is to be configured by this function. */
26764 * This value is a the estimate packet length used in the
26766 * Set to 0xFF... (All Fs) to not adjust this value.
26769 /* This value is applicable to CoS queues only. */
26770 uint8_t service_profile;
26771 /* Lossy (best-effort) */
26772 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
26774 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
26775 /* Set to 0xFF... (All Fs) if there is no service profile specified */
26776 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
26777 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
26778 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
26779 uint8_t unused_0[7];
26782 /* hwrm_queue_cfg_output (size:128b/16B) */
26783 struct hwrm_queue_cfg_output {
26784 /* The specific error status for the command. */
26785 uint16_t error_code;
26786 /* The HWRM command request type. */
26788 /* The sequence ID from the original command. */
26790 /* The length of the response data in number of bytes. */
26792 uint8_t unused_0[7];
26794 * This field is used in Output records to indicate that the output
26795 * is completely written to RAM. This field should be read as '1'
26796 * to indicate that the output has been completely written.
26797 * When writing a command completion or response to an internal processor,
26798 * the order of writes has to be such that this field is written last.
26803 /*****************************
26804 * hwrm_queue_pfcenable_qcfg *
26805 *****************************/
26808 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
26809 struct hwrm_queue_pfcenable_qcfg_input {
26810 /* The HWRM command request type. */
26813 * The completion ring to send the completion event on. This should
26814 * be the NQ ID returned from the `nq_alloc` HWRM command.
26816 uint16_t cmpl_ring;
26818 * The sequence ID is used by the driver for tracking multiple
26819 * commands. This ID is treated as opaque data by the firmware and
26820 * the value is returned in the `hwrm_resp_hdr` upon completion.
26824 * The target ID of the command:
26825 * * 0x0-0xFFF8 - The function ID
26826 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26827 * * 0xFFFD - Reserved for user-space HWRM interface
26830 uint16_t target_id;
26832 * A physical address pointer pointing to a host buffer that the
26833 * command's response data will be written. This can be either a host
26834 * physical address (HPA) or a guest physical address (GPA) and must
26835 * point to a physically contiguous block of memory.
26837 uint64_t resp_addr;
26839 * Port ID of port for which the table is being configured.
26840 * The HWRM needs to check whether this function is allowed
26841 * to configure pri2cos mapping on this port.
26844 uint8_t unused_0[6];
26847 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
26848 struct hwrm_queue_pfcenable_qcfg_output {
26849 /* The specific error status for the command. */
26850 uint16_t error_code;
26851 /* The HWRM command request type. */
26853 /* The sequence ID from the original command. */
26855 /* The length of the response data in number of bytes. */
26858 /* If set to 1, then PFC is enabled on PRI 0. */
26859 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
26861 /* If set to 1, then PFC is enabled on PRI 1. */
26862 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
26864 /* If set to 1, then PFC is enabled on PRI 2. */
26865 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
26867 /* If set to 1, then PFC is enabled on PRI 3. */
26868 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
26870 /* If set to 1, then PFC is enabled on PRI 4. */
26871 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
26873 /* If set to 1, then PFC is enabled on PRI 5. */
26874 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
26876 /* If set to 1, then PFC is enabled on PRI 6. */
26877 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
26879 /* If set to 1, then PFC is enabled on PRI 7. */
26880 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
26882 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
26883 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
26885 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
26886 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
26888 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
26889 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
26891 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
26892 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
26894 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
26895 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
26897 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
26898 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
26900 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
26901 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
26903 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
26904 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
26906 uint8_t unused_0[3];
26908 * This field is used in Output records to indicate that the output
26909 * is completely written to RAM. This field should be read as '1'
26910 * to indicate that the output has been completely written.
26911 * When writing a command completion or response to an internal processor,
26912 * the order of writes has to be such that this field is written last.
26917 /****************************
26918 * hwrm_queue_pfcenable_cfg *
26919 ****************************/
26922 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
26923 struct hwrm_queue_pfcenable_cfg_input {
26924 /* The HWRM command request type. */
26927 * The completion ring to send the completion event on. This should
26928 * be the NQ ID returned from the `nq_alloc` HWRM command.
26930 uint16_t cmpl_ring;
26932 * The sequence ID is used by the driver for tracking multiple
26933 * commands. This ID is treated as opaque data by the firmware and
26934 * the value is returned in the `hwrm_resp_hdr` upon completion.
26938 * The target ID of the command:
26939 * * 0x0-0xFFF8 - The function ID
26940 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26941 * * 0xFFFD - Reserved for user-space HWRM interface
26944 uint16_t target_id;
26946 * A physical address pointer pointing to a host buffer that the
26947 * command's response data will be written. This can be either a host
26948 * physical address (HPA) or a guest physical address (GPA) and must
26949 * point to a physically contiguous block of memory.
26951 uint64_t resp_addr;
26953 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
26954 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
26956 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
26957 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
26959 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
26960 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
26962 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
26963 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
26965 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
26966 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
26968 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
26969 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
26971 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
26972 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
26974 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
26975 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
26977 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
26978 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
26980 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
26981 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
26983 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
26984 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
26986 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
26987 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
26989 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
26990 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
26992 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
26993 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
26995 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
26996 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
26998 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
26999 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
27002 * Port ID of port for which the table is being configured.
27003 * The HWRM needs to check whether this function is allowed
27004 * to configure pri2cos mapping on this port.
27007 uint8_t unused_0[2];
27010 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
27011 struct hwrm_queue_pfcenable_cfg_output {
27012 /* The specific error status for the command. */
27013 uint16_t error_code;
27014 /* The HWRM command request type. */
27016 /* The sequence ID from the original command. */
27018 /* The length of the response data in number of bytes. */
27020 uint8_t unused_0[7];
27022 * This field is used in Output records to indicate that the output
27023 * is completely written to RAM. This field should be read as '1'
27024 * to indicate that the output has been completely written.
27025 * When writing a command completion or response to an internal processor,
27026 * the order of writes has to be such that this field is written last.
27031 /***************************
27032 * hwrm_queue_pri2cos_qcfg *
27033 ***************************/
27036 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
27037 struct hwrm_queue_pri2cos_qcfg_input {
27038 /* The HWRM command request type. */
27041 * The completion ring to send the completion event on. This should
27042 * be the NQ ID returned from the `nq_alloc` HWRM command.
27044 uint16_t cmpl_ring;
27046 * The sequence ID is used by the driver for tracking multiple
27047 * commands. This ID is treated as opaque data by the firmware and
27048 * the value is returned in the `hwrm_resp_hdr` upon completion.
27052 * The target ID of the command:
27053 * * 0x0-0xFFF8 - The function ID
27054 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27055 * * 0xFFFD - Reserved for user-space HWRM interface
27058 uint16_t target_id;
27060 * A physical address pointer pointing to a host buffer that the
27061 * command's response data will be written. This can be either a host
27062 * physical address (HPA) or a guest physical address (GPA) and must
27063 * point to a physically contiguous block of memory.
27065 uint64_t resp_addr;
27068 * Enumeration denoting the RX, TX type of the resource.
27069 * This enumeration is used for resources that are similar for both
27070 * TX and RX paths of the chip.
27072 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27074 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27076 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27077 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
27078 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
27080 * When this bit is set to '0', the query is
27081 * for PRI from tunnel headers.
27082 * When this bit is set to '1', the query is
27083 * for PRI from inner packet headers.
27085 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
27087 * Port ID of port for which the table is being configured.
27088 * The HWRM needs to check whether this function is allowed
27089 * to configure pri2cos mapping on this port.
27092 uint8_t unused_0[3];
27095 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
27096 struct hwrm_queue_pri2cos_qcfg_output {
27097 /* The specific error status for the command. */
27098 uint16_t error_code;
27099 /* The HWRM command request type. */
27101 /* The sequence ID from the original command. */
27103 /* The length of the response data in number of bytes. */
27106 * CoS Queue assigned to priority 0. This value can only
27107 * be changed before traffic has started.
27108 * A value of 0xff indicates that no CoS queue is assigned to the
27109 * specified priority.
27111 uint8_t pri0_cos_queue_id;
27113 * CoS Queue assigned to priority 1. This value can only
27114 * be changed before traffic has started.
27115 * A value of 0xff indicates that no CoS queue is assigned to the
27116 * specified priority.
27118 uint8_t pri1_cos_queue_id;
27120 * CoS Queue assigned to priority 2. This value can only
27121 * be changed before traffic has started.
27122 * A value of 0xff indicates that no CoS queue is assigned to the
27123 * specified priority.
27125 uint8_t pri2_cos_queue_id;
27127 * CoS Queue assigned to priority 3. This value can only
27128 * be changed before traffic has started.
27129 * A value of 0xff indicates that no CoS queue is assigned to the
27130 * specified priority.
27132 uint8_t pri3_cos_queue_id;
27134 * CoS Queue assigned to priority 4. This value can only
27135 * be changed before traffic has started.
27136 * A value of 0xff indicates that no CoS queue is assigned to the
27137 * specified priority.
27139 uint8_t pri4_cos_queue_id;
27141 * CoS Queue assigned to priority 5. This value can only
27142 * be changed before traffic has started.
27143 * A value of 0xff indicates that no CoS queue is assigned to the
27144 * specified priority.
27146 uint8_t pri5_cos_queue_id;
27148 * CoS Queue assigned to priority 6. This value can only
27149 * be changed before traffic has started.
27150 * A value of 0xff indicates that no CoS queue is assigned to the
27151 * specified priority.
27153 uint8_t pri6_cos_queue_id;
27155 * CoS Queue assigned to priority 7. This value can only
27156 * be changed before traffic has started.
27157 * A value of 0xff indicates that no CoS queue is assigned to the
27158 * specified priority.
27160 uint8_t pri7_cos_queue_id;
27161 /* Information about queue configuration. */
27162 uint8_t queue_cfg_info;
27164 * If this flag is set to '1', then the PRI to CoS
27165 * configuration is asymmetric on TX and RX sides.
27166 * If this flag is set to '0', then PRI to CoS configuration
27167 * is symmetric on TX and RX sides.
27169 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
27171 uint8_t unused_0[6];
27173 * This field is used in Output records to indicate that the output
27174 * is completely written to RAM. This field should be read as '1'
27175 * to indicate that the output has been completely written.
27176 * When writing a command completion or response to an internal processor,
27177 * the order of writes has to be such that this field is written last.
27182 /**************************
27183 * hwrm_queue_pri2cos_cfg *
27184 **************************/
27187 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
27188 struct hwrm_queue_pri2cos_cfg_input {
27189 /* The HWRM command request type. */
27192 * The completion ring to send the completion event on. This should
27193 * be the NQ ID returned from the `nq_alloc` HWRM command.
27195 uint16_t cmpl_ring;
27197 * The sequence ID is used by the driver for tracking multiple
27198 * commands. This ID is treated as opaque data by the firmware and
27199 * the value is returned in the `hwrm_resp_hdr` upon completion.
27203 * The target ID of the command:
27204 * * 0x0-0xFFF8 - The function ID
27205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27206 * * 0xFFFD - Reserved for user-space HWRM interface
27209 uint16_t target_id;
27211 * A physical address pointer pointing to a host buffer that the
27212 * command's response data will be written. This can be either a host
27213 * physical address (HPA) or a guest physical address (GPA) and must
27214 * point to a physically contiguous block of memory.
27216 uint64_t resp_addr;
27219 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
27220 * This enumeration is used for resources that are similar for both
27221 * TX and RX paths of the chip.
27223 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
27224 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
27226 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27228 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27229 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
27230 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
27231 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
27232 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
27234 * When this bit is set to '0', the mapping is requested
27235 * for PRI from tunnel headers.
27236 * When this bit is set to '1', the mapping is requested
27237 * for PRI from inner packet headers.
27239 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
27242 * This bit must be '1' for the pri0_cos_queue_id field to be
27245 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
27248 * This bit must be '1' for the pri1_cos_queue_id field to be
27251 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
27254 * This bit must be '1' for the pri2_cos_queue_id field to be
27257 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
27260 * This bit must be '1' for the pri3_cos_queue_id field to be
27263 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
27266 * This bit must be '1' for the pri4_cos_queue_id field to be
27269 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
27272 * This bit must be '1' for the pri5_cos_queue_id field to be
27275 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
27278 * This bit must be '1' for the pri6_cos_queue_id field to be
27281 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
27284 * This bit must be '1' for the pri7_cos_queue_id field to be
27287 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
27290 * Port ID of port for which the table is being configured.
27291 * The HWRM needs to check whether this function is allowed
27292 * to configure pri2cos mapping on this port.
27296 * CoS Queue assigned to priority 0. This value can only
27297 * be changed before traffic has started.
27299 uint8_t pri0_cos_queue_id;
27301 * CoS Queue assigned to priority 1. This value can only
27302 * be changed before traffic has started.
27304 uint8_t pri1_cos_queue_id;
27306 * CoS Queue assigned to priority 2 This value can only
27307 * be changed before traffic has started.
27309 uint8_t pri2_cos_queue_id;
27311 * CoS Queue assigned to priority 3. This value can only
27312 * be changed before traffic has started.
27314 uint8_t pri3_cos_queue_id;
27316 * CoS Queue assigned to priority 4. This value can only
27317 * be changed before traffic has started.
27319 uint8_t pri4_cos_queue_id;
27321 * CoS Queue assigned to priority 5. This value can only
27322 * be changed before traffic has started.
27324 uint8_t pri5_cos_queue_id;
27326 * CoS Queue assigned to priority 6. This value can only
27327 * be changed before traffic has started.
27329 uint8_t pri6_cos_queue_id;
27331 * CoS Queue assigned to priority 7. This value can only
27332 * be changed before traffic has started.
27334 uint8_t pri7_cos_queue_id;
27335 uint8_t unused_0[7];
27338 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
27339 struct hwrm_queue_pri2cos_cfg_output {
27340 /* The specific error status for the command. */
27341 uint16_t error_code;
27342 /* The HWRM command request type. */
27344 /* The sequence ID from the original command. */
27346 /* The length of the response data in number of bytes. */
27348 uint8_t unused_0[7];
27350 * This field is used in Output records to indicate that the output
27351 * is completely written to RAM. This field should be read as '1'
27352 * to indicate that the output has been completely written.
27353 * When writing a command completion or response to an internal processor,
27354 * the order of writes has to be such that this field is written last.
27359 /**************************
27360 * hwrm_queue_cos2bw_qcfg *
27361 **************************/
27364 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
27365 struct hwrm_queue_cos2bw_qcfg_input {
27366 /* The HWRM command request type. */
27369 * The completion ring to send the completion event on. This should
27370 * be the NQ ID returned from the `nq_alloc` HWRM command.
27372 uint16_t cmpl_ring;
27374 * The sequence ID is used by the driver for tracking multiple
27375 * commands. This ID is treated as opaque data by the firmware and
27376 * the value is returned in the `hwrm_resp_hdr` upon completion.
27380 * The target ID of the command:
27381 * * 0x0-0xFFF8 - The function ID
27382 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27383 * * 0xFFFD - Reserved for user-space HWRM interface
27386 uint16_t target_id;
27388 * A physical address pointer pointing to a host buffer that the
27389 * command's response data will be written. This can be either a host
27390 * physical address (HPA) or a guest physical address (GPA) and must
27391 * point to a physically contiguous block of memory.
27393 uint64_t resp_addr;
27395 * Port ID of port for which the table is being configured.
27396 * The HWRM needs to check whether this function is allowed
27397 * to configure TC BW assignment on this port.
27400 uint8_t unused_0[6];
27403 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
27404 struct hwrm_queue_cos2bw_qcfg_output {
27405 /* The specific error status for the command. */
27406 uint16_t error_code;
27407 /* The HWRM command request type. */
27409 /* The sequence ID from the original command. */
27411 /* The length of the response data in number of bytes. */
27413 /* ID of CoS Queue 0. */
27418 * Minimum BW allocated to CoS Queue.
27419 * The HWRM will translate this value into byte counter and
27420 * time interval used for this COS inside the device.
27422 uint32_t queue_id0_min_bw;
27423 /* The bandwidth value. */
27424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
27425 UINT32_C(0xfffffff)
27426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
27428 /* The granularity of the value (bits or bytes). */
27429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
27430 UINT32_C(0x10000000)
27431 /* Value is in bits. */
27432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
27433 (UINT32_C(0x0) << 28)
27434 /* Value is in bytes. */
27435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
27436 (UINT32_C(0x1) << 28)
27437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
27438 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
27439 /* bw_value_unit is 3 b */
27440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
27441 UINT32_C(0xe0000000)
27442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
27444 /* Value is in Mb or MB (base 10). */
27445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
27446 (UINT32_C(0x0) << 29)
27447 /* Value is in Kb or KB (base 10). */
27448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
27449 (UINT32_C(0x2) << 29)
27450 /* Value is in bits or bytes. */
27451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
27452 (UINT32_C(0x4) << 29)
27453 /* Value is in Gb or GB (base 10). */
27454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
27455 (UINT32_C(0x6) << 29)
27456 /* Value is in 1/100th of a percentage of total bandwidth. */
27457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27458 (UINT32_C(0x1) << 29)
27460 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
27461 (UINT32_C(0x7) << 29)
27462 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
27463 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
27465 * Maximum BW allocated to CoS Queue.
27466 * The HWRM will translate this value into byte counter and
27467 * time interval used for this COS inside the device.
27469 uint32_t queue_id0_max_bw;
27470 /* The bandwidth value. */
27471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
27472 UINT32_C(0xfffffff)
27473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
27475 /* The granularity of the value (bits or bytes). */
27476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
27477 UINT32_C(0x10000000)
27478 /* Value is in bits. */
27479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
27480 (UINT32_C(0x0) << 28)
27481 /* Value is in bytes. */
27482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
27483 (UINT32_C(0x1) << 28)
27484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
27485 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
27486 /* bw_value_unit is 3 b */
27487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
27488 UINT32_C(0xe0000000)
27489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
27491 /* Value is in Mb or MB (base 10). */
27492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
27493 (UINT32_C(0x0) << 29)
27494 /* Value is in Kb or KB (base 10). */
27495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
27496 (UINT32_C(0x2) << 29)
27497 /* Value is in bits or bytes. */
27498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
27499 (UINT32_C(0x4) << 29)
27500 /* Value is in Gb or GB (base 10). */
27501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
27502 (UINT32_C(0x6) << 29)
27503 /* Value is in 1/100th of a percentage of total bandwidth. */
27504 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27505 (UINT32_C(0x1) << 29)
27507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
27508 (UINT32_C(0x7) << 29)
27509 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
27510 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
27511 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27512 uint8_t queue_id0_tsa_assign;
27513 /* Strict Priority */
27514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
27516 /* Enhanced Transmission Selection */
27517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
27520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
27523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
27526 * Priority level for strict priority. Valid only when the
27527 * tsa_assign is 0 - Strict Priority (SP)
27528 * 0..7 - Valid values.
27529 * 8..255 - Reserved.
27531 uint8_t queue_id0_pri_lvl;
27533 * Weight used to allocate remaining BW for this COS after
27534 * servicing guaranteed bandwidths for all COS.
27536 uint8_t queue_id0_bw_weight;
27537 /* ID of CoS Queue 1. */
27540 * Minimum BW allocated to CoS Queue.
27541 * The HWRM will translate this value into byte counter and
27542 * time interval used for this COS inside the device.
27544 uint32_t queue_id1_min_bw;
27545 /* The bandwidth value. */
27546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
27547 UINT32_C(0xfffffff)
27548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
27550 /* The granularity of the value (bits or bytes). */
27551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
27552 UINT32_C(0x10000000)
27553 /* Value is in bits. */
27554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
27555 (UINT32_C(0x0) << 28)
27556 /* Value is in bytes. */
27557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
27558 (UINT32_C(0x1) << 28)
27559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
27560 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
27561 /* bw_value_unit is 3 b */
27562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
27563 UINT32_C(0xe0000000)
27564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
27566 /* Value is in Mb or MB (base 10). */
27567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
27568 (UINT32_C(0x0) << 29)
27569 /* Value is in Kb or KB (base 10). */
27570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
27571 (UINT32_C(0x2) << 29)
27572 /* Value is in bits or bytes. */
27573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
27574 (UINT32_C(0x4) << 29)
27575 /* Value is in Gb or GB (base 10). */
27576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
27577 (UINT32_C(0x6) << 29)
27578 /* Value is in 1/100th of a percentage of total bandwidth. */
27579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27580 (UINT32_C(0x1) << 29)
27582 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
27583 (UINT32_C(0x7) << 29)
27584 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
27585 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
27587 * Maximum BW allocated to CoS queue.
27588 * The HWRM will translate this value into byte counter and
27589 * time interval used for this COS inside the device.
27591 uint32_t queue_id1_max_bw;
27592 /* The bandwidth value. */
27593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
27594 UINT32_C(0xfffffff)
27595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
27597 /* The granularity of the value (bits or bytes). */
27598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
27599 UINT32_C(0x10000000)
27600 /* Value is in bits. */
27601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
27602 (UINT32_C(0x0) << 28)
27603 /* Value is in bytes. */
27604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
27605 (UINT32_C(0x1) << 28)
27606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
27607 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
27608 /* bw_value_unit is 3 b */
27609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
27610 UINT32_C(0xe0000000)
27611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
27613 /* Value is in Mb or MB (base 10). */
27614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
27615 (UINT32_C(0x0) << 29)
27616 /* Value is in Kb or KB (base 10). */
27617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
27618 (UINT32_C(0x2) << 29)
27619 /* Value is in bits or bytes. */
27620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
27621 (UINT32_C(0x4) << 29)
27622 /* Value is in Gb or GB (base 10). */
27623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
27624 (UINT32_C(0x6) << 29)
27625 /* Value is in 1/100th of a percentage of total bandwidth. */
27626 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27627 (UINT32_C(0x1) << 29)
27629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
27630 (UINT32_C(0x7) << 29)
27631 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
27632 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
27633 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27634 uint8_t queue_id1_tsa_assign;
27635 /* Strict Priority */
27636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
27638 /* Enhanced Transmission Selection */
27639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
27642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
27645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
27648 * Priority level for strict priority. Valid only when the
27649 * tsa_assign is 0 - Strict Priority (SP)
27650 * 0..7 - Valid values.
27651 * 8..255 - Reserved.
27653 uint8_t queue_id1_pri_lvl;
27655 * Weight used to allocate remaining BW for this COS after
27656 * servicing guaranteed bandwidths for all COS.
27658 uint8_t queue_id1_bw_weight;
27659 /* ID of CoS Queue 2. */
27662 * Minimum BW allocated to CoS Queue.
27663 * The HWRM will translate this value into byte counter and
27664 * time interval used for this COS inside the device.
27666 uint32_t queue_id2_min_bw;
27667 /* The bandwidth value. */
27668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
27669 UINT32_C(0xfffffff)
27670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
27672 /* The granularity of the value (bits or bytes). */
27673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
27674 UINT32_C(0x10000000)
27675 /* Value is in bits. */
27676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
27677 (UINT32_C(0x0) << 28)
27678 /* Value is in bytes. */
27679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
27680 (UINT32_C(0x1) << 28)
27681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
27682 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
27683 /* bw_value_unit is 3 b */
27684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
27685 UINT32_C(0xe0000000)
27686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
27688 /* Value is in Mb or MB (base 10). */
27689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
27690 (UINT32_C(0x0) << 29)
27691 /* Value is in Kb or KB (base 10). */
27692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
27693 (UINT32_C(0x2) << 29)
27694 /* Value is in bits or bytes. */
27695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
27696 (UINT32_C(0x4) << 29)
27697 /* Value is in Gb or GB (base 10). */
27698 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
27699 (UINT32_C(0x6) << 29)
27700 /* Value is in 1/100th of a percentage of total bandwidth. */
27701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27702 (UINT32_C(0x1) << 29)
27704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
27705 (UINT32_C(0x7) << 29)
27706 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
27707 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
27709 * Maximum BW allocated to CoS queue.
27710 * The HWRM will translate this value into byte counter and
27711 * time interval used for this COS inside the device.
27713 uint32_t queue_id2_max_bw;
27714 /* The bandwidth value. */
27715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
27716 UINT32_C(0xfffffff)
27717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
27719 /* The granularity of the value (bits or bytes). */
27720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
27721 UINT32_C(0x10000000)
27722 /* Value is in bits. */
27723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
27724 (UINT32_C(0x0) << 28)
27725 /* Value is in bytes. */
27726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
27727 (UINT32_C(0x1) << 28)
27728 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
27729 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
27730 /* bw_value_unit is 3 b */
27731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
27732 UINT32_C(0xe0000000)
27733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
27735 /* Value is in Mb or MB (base 10). */
27736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
27737 (UINT32_C(0x0) << 29)
27738 /* Value is in Kb or KB (base 10). */
27739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
27740 (UINT32_C(0x2) << 29)
27741 /* Value is in bits or bytes. */
27742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
27743 (UINT32_C(0x4) << 29)
27744 /* Value is in Gb or GB (base 10). */
27745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
27746 (UINT32_C(0x6) << 29)
27747 /* Value is in 1/100th of a percentage of total bandwidth. */
27748 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27749 (UINT32_C(0x1) << 29)
27751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
27752 (UINT32_C(0x7) << 29)
27753 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
27754 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
27755 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27756 uint8_t queue_id2_tsa_assign;
27757 /* Strict Priority */
27758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
27760 /* Enhanced Transmission Selection */
27761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
27764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
27767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
27770 * Priority level for strict priority. Valid only when the
27771 * tsa_assign is 0 - Strict Priority (SP)
27772 * 0..7 - Valid values.
27773 * 8..255 - Reserved.
27775 uint8_t queue_id2_pri_lvl;
27777 * Weight used to allocate remaining BW for this COS after
27778 * servicing guaranteed bandwidths for all COS.
27780 uint8_t queue_id2_bw_weight;
27781 /* ID of CoS Queue 3. */
27784 * Minimum BW allocated to CoS Queue.
27785 * The HWRM will translate this value into byte counter and
27786 * time interval used for this COS inside the device.
27788 uint32_t queue_id3_min_bw;
27789 /* The bandwidth value. */
27790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
27791 UINT32_C(0xfffffff)
27792 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
27794 /* The granularity of the value (bits or bytes). */
27795 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
27796 UINT32_C(0x10000000)
27797 /* Value is in bits. */
27798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
27799 (UINT32_C(0x0) << 28)
27800 /* Value is in bytes. */
27801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
27802 (UINT32_C(0x1) << 28)
27803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
27804 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
27805 /* bw_value_unit is 3 b */
27806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
27807 UINT32_C(0xe0000000)
27808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
27810 /* Value is in Mb or MB (base 10). */
27811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
27812 (UINT32_C(0x0) << 29)
27813 /* Value is in Kb or KB (base 10). */
27814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
27815 (UINT32_C(0x2) << 29)
27816 /* Value is in bits or bytes. */
27817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
27818 (UINT32_C(0x4) << 29)
27819 /* Value is in Gb or GB (base 10). */
27820 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
27821 (UINT32_C(0x6) << 29)
27822 /* Value is in 1/100th of a percentage of total bandwidth. */
27823 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27824 (UINT32_C(0x1) << 29)
27826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
27827 (UINT32_C(0x7) << 29)
27828 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
27829 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
27831 * Maximum BW allocated to CoS queue.
27832 * The HWRM will translate this value into byte counter and
27833 * time interval used for this COS inside the device.
27835 uint32_t queue_id3_max_bw;
27836 /* The bandwidth value. */
27837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
27838 UINT32_C(0xfffffff)
27839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
27841 /* The granularity of the value (bits or bytes). */
27842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
27843 UINT32_C(0x10000000)
27844 /* Value is in bits. */
27845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
27846 (UINT32_C(0x0) << 28)
27847 /* Value is in bytes. */
27848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
27849 (UINT32_C(0x1) << 28)
27850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
27851 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
27852 /* bw_value_unit is 3 b */
27853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
27854 UINT32_C(0xe0000000)
27855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
27857 /* Value is in Mb or MB (base 10). */
27858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
27859 (UINT32_C(0x0) << 29)
27860 /* Value is in Kb or KB (base 10). */
27861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
27862 (UINT32_C(0x2) << 29)
27863 /* Value is in bits or bytes. */
27864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
27865 (UINT32_C(0x4) << 29)
27866 /* Value is in Gb or GB (base 10). */
27867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
27868 (UINT32_C(0x6) << 29)
27869 /* Value is in 1/100th of a percentage of total bandwidth. */
27870 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27871 (UINT32_C(0x1) << 29)
27873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
27874 (UINT32_C(0x7) << 29)
27875 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
27876 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
27877 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27878 uint8_t queue_id3_tsa_assign;
27879 /* Strict Priority */
27880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
27882 /* Enhanced Transmission Selection */
27883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
27886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
27889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
27892 * Priority level for strict priority. Valid only when the
27893 * tsa_assign is 0 - Strict Priority (SP)
27894 * 0..7 - Valid values.
27895 * 8..255 - Reserved.
27897 uint8_t queue_id3_pri_lvl;
27899 * Weight used to allocate remaining BW for this COS after
27900 * servicing guaranteed bandwidths for all COS.
27902 uint8_t queue_id3_bw_weight;
27903 /* ID of CoS Queue 4. */
27906 * Minimum BW allocated to CoS Queue.
27907 * The HWRM will translate this value into byte counter and
27908 * time interval used for this COS inside the device.
27910 uint32_t queue_id4_min_bw;
27911 /* The bandwidth value. */
27912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
27913 UINT32_C(0xfffffff)
27914 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
27916 /* The granularity of the value (bits or bytes). */
27917 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
27918 UINT32_C(0x10000000)
27919 /* Value is in bits. */
27920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
27921 (UINT32_C(0x0) << 28)
27922 /* Value is in bytes. */
27923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
27924 (UINT32_C(0x1) << 28)
27925 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
27926 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
27927 /* bw_value_unit is 3 b */
27928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
27929 UINT32_C(0xe0000000)
27930 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
27932 /* Value is in Mb or MB (base 10). */
27933 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
27934 (UINT32_C(0x0) << 29)
27935 /* Value is in Kb or KB (base 10). */
27936 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
27937 (UINT32_C(0x2) << 29)
27938 /* Value is in bits or bytes. */
27939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
27940 (UINT32_C(0x4) << 29)
27941 /* Value is in Gb or GB (base 10). */
27942 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
27943 (UINT32_C(0x6) << 29)
27944 /* Value is in 1/100th of a percentage of total bandwidth. */
27945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27946 (UINT32_C(0x1) << 29)
27948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
27949 (UINT32_C(0x7) << 29)
27950 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
27951 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
27953 * Maximum BW allocated to CoS queue.
27954 * The HWRM will translate this value into byte counter and
27955 * time interval used for this COS inside the device.
27957 uint32_t queue_id4_max_bw;
27958 /* The bandwidth value. */
27959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
27960 UINT32_C(0xfffffff)
27961 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
27963 /* The granularity of the value (bits or bytes). */
27964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
27965 UINT32_C(0x10000000)
27966 /* Value is in bits. */
27967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
27968 (UINT32_C(0x0) << 28)
27969 /* Value is in bytes. */
27970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
27971 (UINT32_C(0x1) << 28)
27972 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
27973 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
27974 /* bw_value_unit is 3 b */
27975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
27976 UINT32_C(0xe0000000)
27977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
27979 /* Value is in Mb or MB (base 10). */
27980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
27981 (UINT32_C(0x0) << 29)
27982 /* Value is in Kb or KB (base 10). */
27983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
27984 (UINT32_C(0x2) << 29)
27985 /* Value is in bits or bytes. */
27986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
27987 (UINT32_C(0x4) << 29)
27988 /* Value is in Gb or GB (base 10). */
27989 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
27990 (UINT32_C(0x6) << 29)
27991 /* Value is in 1/100th of a percentage of total bandwidth. */
27992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27993 (UINT32_C(0x1) << 29)
27995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
27996 (UINT32_C(0x7) << 29)
27997 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
27998 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
27999 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28000 uint8_t queue_id4_tsa_assign;
28001 /* Strict Priority */
28002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
28004 /* Enhanced Transmission Selection */
28005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
28008 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
28011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
28014 * Priority level for strict priority. Valid only when the
28015 * tsa_assign is 0 - Strict Priority (SP)
28016 * 0..7 - Valid values.
28017 * 8..255 - Reserved.
28019 uint8_t queue_id4_pri_lvl;
28021 * Weight used to allocate remaining BW for this COS after
28022 * servicing guaranteed bandwidths for all COS.
28024 uint8_t queue_id4_bw_weight;
28025 /* ID of CoS Queue 5. */
28028 * Minimum BW allocated to CoS Queue.
28029 * The HWRM will translate this value into byte counter and
28030 * time interval used for this COS inside the device.
28032 uint32_t queue_id5_min_bw;
28033 /* The bandwidth value. */
28034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
28035 UINT32_C(0xfffffff)
28036 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
28038 /* The granularity of the value (bits or bytes). */
28039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
28040 UINT32_C(0x10000000)
28041 /* Value is in bits. */
28042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
28043 (UINT32_C(0x0) << 28)
28044 /* Value is in bytes. */
28045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
28046 (UINT32_C(0x1) << 28)
28047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
28048 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
28049 /* bw_value_unit is 3 b */
28050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
28051 UINT32_C(0xe0000000)
28052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
28054 /* Value is in Mb or MB (base 10). */
28055 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
28056 (UINT32_C(0x0) << 29)
28057 /* Value is in Kb or KB (base 10). */
28058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
28059 (UINT32_C(0x2) << 29)
28060 /* Value is in bits or bytes. */
28061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
28062 (UINT32_C(0x4) << 29)
28063 /* Value is in Gb or GB (base 10). */
28064 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
28065 (UINT32_C(0x6) << 29)
28066 /* Value is in 1/100th of a percentage of total bandwidth. */
28067 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28068 (UINT32_C(0x1) << 29)
28070 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
28071 (UINT32_C(0x7) << 29)
28072 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
28073 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
28075 * Maximum BW allocated to CoS queue.
28076 * The HWRM will translate this value into byte counter and
28077 * time interval used for this COS inside the device.
28079 uint32_t queue_id5_max_bw;
28080 /* The bandwidth value. */
28081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
28082 UINT32_C(0xfffffff)
28083 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
28085 /* The granularity of the value (bits or bytes). */
28086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
28087 UINT32_C(0x10000000)
28088 /* Value is in bits. */
28089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
28090 (UINT32_C(0x0) << 28)
28091 /* Value is in bytes. */
28092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
28093 (UINT32_C(0x1) << 28)
28094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
28095 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
28096 /* bw_value_unit is 3 b */
28097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
28098 UINT32_C(0xe0000000)
28099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
28101 /* Value is in Mb or MB (base 10). */
28102 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
28103 (UINT32_C(0x0) << 29)
28104 /* Value is in Kb or KB (base 10). */
28105 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
28106 (UINT32_C(0x2) << 29)
28107 /* Value is in bits or bytes. */
28108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
28109 (UINT32_C(0x4) << 29)
28110 /* Value is in Gb or GB (base 10). */
28111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
28112 (UINT32_C(0x6) << 29)
28113 /* Value is in 1/100th of a percentage of total bandwidth. */
28114 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28115 (UINT32_C(0x1) << 29)
28117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
28118 (UINT32_C(0x7) << 29)
28119 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
28120 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
28121 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28122 uint8_t queue_id5_tsa_assign;
28123 /* Strict Priority */
28124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
28126 /* Enhanced Transmission Selection */
28127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
28130 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
28133 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
28136 * Priority level for strict priority. Valid only when the
28137 * tsa_assign is 0 - Strict Priority (SP)
28138 * 0..7 - Valid values.
28139 * 8..255 - Reserved.
28141 uint8_t queue_id5_pri_lvl;
28143 * Weight used to allocate remaining BW for this COS after
28144 * servicing guaranteed bandwidths for all COS.
28146 uint8_t queue_id5_bw_weight;
28147 /* ID of CoS Queue 6. */
28150 * Minimum BW allocated to CoS Queue.
28151 * The HWRM will translate this value into byte counter and
28152 * time interval used for this COS inside the device.
28154 uint32_t queue_id6_min_bw;
28155 /* The bandwidth value. */
28156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
28157 UINT32_C(0xfffffff)
28158 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
28160 /* The granularity of the value (bits or bytes). */
28161 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
28162 UINT32_C(0x10000000)
28163 /* Value is in bits. */
28164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
28165 (UINT32_C(0x0) << 28)
28166 /* Value is in bytes. */
28167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
28168 (UINT32_C(0x1) << 28)
28169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
28170 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
28171 /* bw_value_unit is 3 b */
28172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
28173 UINT32_C(0xe0000000)
28174 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
28176 /* Value is in Mb or MB (base 10). */
28177 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
28178 (UINT32_C(0x0) << 29)
28179 /* Value is in Kb or KB (base 10). */
28180 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
28181 (UINT32_C(0x2) << 29)
28182 /* Value is in bits or bytes. */
28183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
28184 (UINT32_C(0x4) << 29)
28185 /* Value is in Gb or GB (base 10). */
28186 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
28187 (UINT32_C(0x6) << 29)
28188 /* Value is in 1/100th of a percentage of total bandwidth. */
28189 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28190 (UINT32_C(0x1) << 29)
28192 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
28193 (UINT32_C(0x7) << 29)
28194 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
28195 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
28197 * Maximum BW allocated to CoS queue.
28198 * The HWRM will translate this value into byte counter and
28199 * time interval used for this COS inside the device.
28201 uint32_t queue_id6_max_bw;
28202 /* The bandwidth value. */
28203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
28204 UINT32_C(0xfffffff)
28205 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
28207 /* The granularity of the value (bits or bytes). */
28208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
28209 UINT32_C(0x10000000)
28210 /* Value is in bits. */
28211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
28212 (UINT32_C(0x0) << 28)
28213 /* Value is in bytes. */
28214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
28215 (UINT32_C(0x1) << 28)
28216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
28217 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
28218 /* bw_value_unit is 3 b */
28219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
28220 UINT32_C(0xe0000000)
28221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
28223 /* Value is in Mb or MB (base 10). */
28224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
28225 (UINT32_C(0x0) << 29)
28226 /* Value is in Kb or KB (base 10). */
28227 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
28228 (UINT32_C(0x2) << 29)
28229 /* Value is in bits or bytes. */
28230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
28231 (UINT32_C(0x4) << 29)
28232 /* Value is in Gb or GB (base 10). */
28233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
28234 (UINT32_C(0x6) << 29)
28235 /* Value is in 1/100th of a percentage of total bandwidth. */
28236 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28237 (UINT32_C(0x1) << 29)
28239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
28240 (UINT32_C(0x7) << 29)
28241 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
28242 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
28243 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28244 uint8_t queue_id6_tsa_assign;
28245 /* Strict Priority */
28246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
28248 /* Enhanced Transmission Selection */
28249 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
28252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
28255 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
28258 * Priority level for strict priority. Valid only when the
28259 * tsa_assign is 0 - Strict Priority (SP)
28260 * 0..7 - Valid values.
28261 * 8..255 - Reserved.
28263 uint8_t queue_id6_pri_lvl;
28265 * Weight used to allocate remaining BW for this COS after
28266 * servicing guaranteed bandwidths for all COS.
28268 uint8_t queue_id6_bw_weight;
28269 /* ID of CoS Queue 7. */
28272 * Minimum BW allocated to CoS Queue.
28273 * The HWRM will translate this value into byte counter and
28274 * time interval used for this COS inside the device.
28276 uint32_t queue_id7_min_bw;
28277 /* The bandwidth value. */
28278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
28279 UINT32_C(0xfffffff)
28280 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
28282 /* The granularity of the value (bits or bytes). */
28283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
28284 UINT32_C(0x10000000)
28285 /* Value is in bits. */
28286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
28287 (UINT32_C(0x0) << 28)
28288 /* Value is in bytes. */
28289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
28290 (UINT32_C(0x1) << 28)
28291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
28292 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
28293 /* bw_value_unit is 3 b */
28294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
28295 UINT32_C(0xe0000000)
28296 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
28298 /* Value is in Mb or MB (base 10). */
28299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
28300 (UINT32_C(0x0) << 29)
28301 /* Value is in Kb or KB (base 10). */
28302 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
28303 (UINT32_C(0x2) << 29)
28304 /* Value is in bits or bytes. */
28305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
28306 (UINT32_C(0x4) << 29)
28307 /* Value is in Gb or GB (base 10). */
28308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
28309 (UINT32_C(0x6) << 29)
28310 /* Value is in 1/100th of a percentage of total bandwidth. */
28311 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28312 (UINT32_C(0x1) << 29)
28314 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
28315 (UINT32_C(0x7) << 29)
28316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
28317 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
28319 * Maximum BW allocated to CoS queue.
28320 * The HWRM will translate this value into byte counter and
28321 * time interval used for this COS inside the device.
28323 uint32_t queue_id7_max_bw;
28324 /* The bandwidth value. */
28325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
28326 UINT32_C(0xfffffff)
28327 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
28329 /* The granularity of the value (bits or bytes). */
28330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
28331 UINT32_C(0x10000000)
28332 /* Value is in bits. */
28333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
28334 (UINT32_C(0x0) << 28)
28335 /* Value is in bytes. */
28336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
28337 (UINT32_C(0x1) << 28)
28338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
28339 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
28340 /* bw_value_unit is 3 b */
28341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
28342 UINT32_C(0xe0000000)
28343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
28345 /* Value is in Mb or MB (base 10). */
28346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
28347 (UINT32_C(0x0) << 29)
28348 /* Value is in Kb or KB (base 10). */
28349 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
28350 (UINT32_C(0x2) << 29)
28351 /* Value is in bits or bytes. */
28352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
28353 (UINT32_C(0x4) << 29)
28354 /* Value is in Gb or GB (base 10). */
28355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
28356 (UINT32_C(0x6) << 29)
28357 /* Value is in 1/100th of a percentage of total bandwidth. */
28358 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28359 (UINT32_C(0x1) << 29)
28361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
28362 (UINT32_C(0x7) << 29)
28363 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
28364 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
28365 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28366 uint8_t queue_id7_tsa_assign;
28367 /* Strict Priority */
28368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
28370 /* Enhanced Transmission Selection */
28371 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
28374 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
28377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
28380 * Priority level for strict priority. Valid only when the
28381 * tsa_assign is 0 - Strict Priority (SP)
28382 * 0..7 - Valid values.
28383 * 8..255 - Reserved.
28385 uint8_t queue_id7_pri_lvl;
28387 * Weight used to allocate remaining BW for this COS after
28388 * servicing guaranteed bandwidths for all COS.
28390 uint8_t queue_id7_bw_weight;
28391 uint8_t unused_2[4];
28393 * This field is used in Output records to indicate that the output
28394 * is completely written to RAM. This field should be read as '1'
28395 * to indicate that the output has been completely written.
28396 * When writing a command completion or response to an internal processor,
28397 * the order of writes has to be such that this field is written last.
28402 /*************************
28403 * hwrm_queue_cos2bw_cfg *
28404 *************************/
28407 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
28408 struct hwrm_queue_cos2bw_cfg_input {
28409 /* The HWRM command request type. */
28412 * The completion ring to send the completion event on. This should
28413 * be the NQ ID returned from the `nq_alloc` HWRM command.
28415 uint16_t cmpl_ring;
28417 * The sequence ID is used by the driver for tracking multiple
28418 * commands. This ID is treated as opaque data by the firmware and
28419 * the value is returned in the `hwrm_resp_hdr` upon completion.
28423 * The target ID of the command:
28424 * * 0x0-0xFFF8 - The function ID
28425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28426 * * 0xFFFD - Reserved for user-space HWRM interface
28429 uint16_t target_id;
28431 * A physical address pointer pointing to a host buffer that the
28432 * command's response data will be written. This can be either a host
28433 * physical address (HPA) or a guest physical address (GPA) and must
28434 * point to a physically contiguous block of memory.
28436 uint64_t resp_addr;
28440 * If this bit is set to 1, then all queue_id0 related
28441 * parameters in this command are valid.
28443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
28446 * If this bit is set to 1, then all queue_id1 related
28447 * parameters in this command are valid.
28449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
28452 * If this bit is set to 1, then all queue_id2 related
28453 * parameters in this command are valid.
28455 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
28458 * If this bit is set to 1, then all queue_id3 related
28459 * parameters in this command are valid.
28461 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
28464 * If this bit is set to 1, then all queue_id4 related
28465 * parameters in this command are valid.
28467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
28470 * If this bit is set to 1, then all queue_id5 related
28471 * parameters in this command are valid.
28473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
28476 * If this bit is set to 1, then all queue_id6 related
28477 * parameters in this command are valid.
28479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
28482 * If this bit is set to 1, then all queue_id7 related
28483 * parameters in this command are valid.
28485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
28488 * Port ID of port for which the table is being configured.
28489 * The HWRM needs to check whether this function is allowed
28490 * to configure TC BW assignment on this port.
28493 /* ID of CoS Queue 0. */
28497 * Minimum BW allocated to CoS Queue.
28498 * The HWRM will translate this value into byte counter and
28499 * time interval used for this COS inside the device.
28501 uint32_t queue_id0_min_bw;
28502 /* The bandwidth value. */
28503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
28504 UINT32_C(0xfffffff)
28505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
28507 /* The granularity of the value (bits or bytes). */
28508 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
28509 UINT32_C(0x10000000)
28510 /* Value is in bits. */
28511 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
28512 (UINT32_C(0x0) << 28)
28513 /* Value is in bytes. */
28514 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
28515 (UINT32_C(0x1) << 28)
28516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
28517 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
28518 /* bw_value_unit is 3 b */
28519 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
28520 UINT32_C(0xe0000000)
28521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
28523 /* Value is in Mb or MB (base 10). */
28524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
28525 (UINT32_C(0x0) << 29)
28526 /* Value is in Kb or KB (base 10). */
28527 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
28528 (UINT32_C(0x2) << 29)
28529 /* Value is in bits or bytes. */
28530 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
28531 (UINT32_C(0x4) << 29)
28532 /* Value is in Gb or GB (base 10). */
28533 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
28534 (UINT32_C(0x6) << 29)
28535 /* Value is in 1/100th of a percentage of total bandwidth. */
28536 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28537 (UINT32_C(0x1) << 29)
28539 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
28540 (UINT32_C(0x7) << 29)
28541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
28542 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
28544 * Maximum BW allocated to CoS Queue.
28545 * The HWRM will translate this value into byte counter and
28546 * time interval used for this COS inside the device.
28548 uint32_t queue_id0_max_bw;
28549 /* The bandwidth value. */
28550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
28551 UINT32_C(0xfffffff)
28552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
28554 /* The granularity of the value (bits or bytes). */
28555 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
28556 UINT32_C(0x10000000)
28557 /* Value is in bits. */
28558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
28559 (UINT32_C(0x0) << 28)
28560 /* Value is in bytes. */
28561 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
28562 (UINT32_C(0x1) << 28)
28563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
28564 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
28565 /* bw_value_unit is 3 b */
28566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
28567 UINT32_C(0xe0000000)
28568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
28570 /* Value is in Mb or MB (base 10). */
28571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
28572 (UINT32_C(0x0) << 29)
28573 /* Value is in Kb or KB (base 10). */
28574 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
28575 (UINT32_C(0x2) << 29)
28576 /* Value is in bits or bytes. */
28577 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
28578 (UINT32_C(0x4) << 29)
28579 /* Value is in Gb or GB (base 10). */
28580 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
28581 (UINT32_C(0x6) << 29)
28582 /* Value is in 1/100th of a percentage of total bandwidth. */
28583 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28584 (UINT32_C(0x1) << 29)
28586 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
28587 (UINT32_C(0x7) << 29)
28588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
28589 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
28590 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28591 uint8_t queue_id0_tsa_assign;
28592 /* Strict Priority */
28593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
28595 /* Enhanced Transmission Selection */
28596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
28599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
28602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
28605 * Priority level for strict priority. Valid only when the
28606 * tsa_assign is 0 - Strict Priority (SP)
28607 * 0..7 - Valid values.
28608 * 8..255 - Reserved.
28610 uint8_t queue_id0_pri_lvl;
28612 * Weight used to allocate remaining BW for this COS after
28613 * servicing guaranteed bandwidths for all COS.
28615 uint8_t queue_id0_bw_weight;
28616 /* ID of CoS Queue 1. */
28619 * Minimum BW allocated to CoS Queue.
28620 * The HWRM will translate this value into byte counter and
28621 * time interval used for this COS inside the device.
28623 uint32_t queue_id1_min_bw;
28624 /* The bandwidth value. */
28625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
28626 UINT32_C(0xfffffff)
28627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
28629 /* The granularity of the value (bits or bytes). */
28630 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
28631 UINT32_C(0x10000000)
28632 /* Value is in bits. */
28633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
28634 (UINT32_C(0x0) << 28)
28635 /* Value is in bytes. */
28636 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
28637 (UINT32_C(0x1) << 28)
28638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
28639 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
28640 /* bw_value_unit is 3 b */
28641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
28642 UINT32_C(0xe0000000)
28643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
28645 /* Value is in Mb or MB (base 10). */
28646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
28647 (UINT32_C(0x0) << 29)
28648 /* Value is in Kb or KB (base 10). */
28649 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
28650 (UINT32_C(0x2) << 29)
28651 /* Value is in bits or bytes. */
28652 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
28653 (UINT32_C(0x4) << 29)
28654 /* Value is in Gb or GB (base 10). */
28655 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
28656 (UINT32_C(0x6) << 29)
28657 /* Value is in 1/100th of a percentage of total bandwidth. */
28658 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28659 (UINT32_C(0x1) << 29)
28661 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
28662 (UINT32_C(0x7) << 29)
28663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
28664 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
28666 * Maximum BW allocated to CoS queue.
28667 * The HWRM will translate this value into byte counter and
28668 * time interval used for this COS inside the device.
28670 uint32_t queue_id1_max_bw;
28671 /* The bandwidth value. */
28672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
28673 UINT32_C(0xfffffff)
28674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
28676 /* The granularity of the value (bits or bytes). */
28677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
28678 UINT32_C(0x10000000)
28679 /* Value is in bits. */
28680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
28681 (UINT32_C(0x0) << 28)
28682 /* Value is in bytes. */
28683 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
28684 (UINT32_C(0x1) << 28)
28685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
28686 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
28687 /* bw_value_unit is 3 b */
28688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
28689 UINT32_C(0xe0000000)
28690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
28692 /* Value is in Mb or MB (base 10). */
28693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
28694 (UINT32_C(0x0) << 29)
28695 /* Value is in Kb or KB (base 10). */
28696 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
28697 (UINT32_C(0x2) << 29)
28698 /* Value is in bits or bytes. */
28699 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
28700 (UINT32_C(0x4) << 29)
28701 /* Value is in Gb or GB (base 10). */
28702 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
28703 (UINT32_C(0x6) << 29)
28704 /* Value is in 1/100th of a percentage of total bandwidth. */
28705 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28706 (UINT32_C(0x1) << 29)
28708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
28709 (UINT32_C(0x7) << 29)
28710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
28711 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
28712 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28713 uint8_t queue_id1_tsa_assign;
28714 /* Strict Priority */
28715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
28717 /* Enhanced Transmission Selection */
28718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
28721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
28724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
28727 * Priority level for strict priority. Valid only when the
28728 * tsa_assign is 0 - Strict Priority (SP)
28729 * 0..7 - Valid values.
28730 * 8..255 - Reserved.
28732 uint8_t queue_id1_pri_lvl;
28734 * Weight used to allocate remaining BW for this COS after
28735 * servicing guaranteed bandwidths for all COS.
28737 uint8_t queue_id1_bw_weight;
28738 /* ID of CoS Queue 2. */
28741 * Minimum BW allocated to CoS Queue.
28742 * The HWRM will translate this value into byte counter and
28743 * time interval used for this COS inside the device.
28745 uint32_t queue_id2_min_bw;
28746 /* The bandwidth value. */
28747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
28748 UINT32_C(0xfffffff)
28749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
28751 /* The granularity of the value (bits or bytes). */
28752 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
28753 UINT32_C(0x10000000)
28754 /* Value is in bits. */
28755 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
28756 (UINT32_C(0x0) << 28)
28757 /* Value is in bytes. */
28758 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
28759 (UINT32_C(0x1) << 28)
28760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
28761 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
28762 /* bw_value_unit is 3 b */
28763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
28764 UINT32_C(0xe0000000)
28765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
28767 /* Value is in Mb or MB (base 10). */
28768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
28769 (UINT32_C(0x0) << 29)
28770 /* Value is in Kb or KB (base 10). */
28771 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
28772 (UINT32_C(0x2) << 29)
28773 /* Value is in bits or bytes. */
28774 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
28775 (UINT32_C(0x4) << 29)
28776 /* Value is in Gb or GB (base 10). */
28777 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
28778 (UINT32_C(0x6) << 29)
28779 /* Value is in 1/100th of a percentage of total bandwidth. */
28780 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28781 (UINT32_C(0x1) << 29)
28783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
28784 (UINT32_C(0x7) << 29)
28785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
28786 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
28788 * Maximum BW allocated to CoS queue.
28789 * The HWRM will translate this value into byte counter and
28790 * time interval used for this COS inside the device.
28792 uint32_t queue_id2_max_bw;
28793 /* The bandwidth value. */
28794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
28795 UINT32_C(0xfffffff)
28796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
28798 /* The granularity of the value (bits or bytes). */
28799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
28800 UINT32_C(0x10000000)
28801 /* Value is in bits. */
28802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
28803 (UINT32_C(0x0) << 28)
28804 /* Value is in bytes. */
28805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
28806 (UINT32_C(0x1) << 28)
28807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
28808 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
28809 /* bw_value_unit is 3 b */
28810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
28811 UINT32_C(0xe0000000)
28812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
28814 /* Value is in Mb or MB (base 10). */
28815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
28816 (UINT32_C(0x0) << 29)
28817 /* Value is in Kb or KB (base 10). */
28818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
28819 (UINT32_C(0x2) << 29)
28820 /* Value is in bits or bytes. */
28821 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
28822 (UINT32_C(0x4) << 29)
28823 /* Value is in Gb or GB (base 10). */
28824 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
28825 (UINT32_C(0x6) << 29)
28826 /* Value is in 1/100th of a percentage of total bandwidth. */
28827 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28828 (UINT32_C(0x1) << 29)
28830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
28831 (UINT32_C(0x7) << 29)
28832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
28833 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
28834 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28835 uint8_t queue_id2_tsa_assign;
28836 /* Strict Priority */
28837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
28839 /* Enhanced Transmission Selection */
28840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
28843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
28846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
28849 * Priority level for strict priority. Valid only when the
28850 * tsa_assign is 0 - Strict Priority (SP)
28851 * 0..7 - Valid values.
28852 * 8..255 - Reserved.
28854 uint8_t queue_id2_pri_lvl;
28856 * Weight used to allocate remaining BW for this COS after
28857 * servicing guaranteed bandwidths for all COS.
28859 uint8_t queue_id2_bw_weight;
28860 /* ID of CoS Queue 3. */
28863 * Minimum BW allocated to CoS Queue.
28864 * The HWRM will translate this value into byte counter and
28865 * time interval used for this COS inside the device.
28867 uint32_t queue_id3_min_bw;
28868 /* The bandwidth value. */
28869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
28870 UINT32_C(0xfffffff)
28871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
28873 /* The granularity of the value (bits or bytes). */
28874 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
28875 UINT32_C(0x10000000)
28876 /* Value is in bits. */
28877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
28878 (UINT32_C(0x0) << 28)
28879 /* Value is in bytes. */
28880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
28881 (UINT32_C(0x1) << 28)
28882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
28883 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
28884 /* bw_value_unit is 3 b */
28885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
28886 UINT32_C(0xe0000000)
28887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
28889 /* Value is in Mb or MB (base 10). */
28890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
28891 (UINT32_C(0x0) << 29)
28892 /* Value is in Kb or KB (base 10). */
28893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
28894 (UINT32_C(0x2) << 29)
28895 /* Value is in bits or bytes. */
28896 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
28897 (UINT32_C(0x4) << 29)
28898 /* Value is in Gb or GB (base 10). */
28899 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
28900 (UINT32_C(0x6) << 29)
28901 /* Value is in 1/100th of a percentage of total bandwidth. */
28902 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28903 (UINT32_C(0x1) << 29)
28905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
28906 (UINT32_C(0x7) << 29)
28907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
28908 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
28910 * Maximum BW allocated to CoS queue.
28911 * The HWRM will translate this value into byte counter and
28912 * time interval used for this COS inside the device.
28914 uint32_t queue_id3_max_bw;
28915 /* The bandwidth value. */
28916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
28917 UINT32_C(0xfffffff)
28918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
28920 /* The granularity of the value (bits or bytes). */
28921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
28922 UINT32_C(0x10000000)
28923 /* Value is in bits. */
28924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
28925 (UINT32_C(0x0) << 28)
28926 /* Value is in bytes. */
28927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
28928 (UINT32_C(0x1) << 28)
28929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
28930 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
28931 /* bw_value_unit is 3 b */
28932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
28933 UINT32_C(0xe0000000)
28934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
28936 /* Value is in Mb or MB (base 10). */
28937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
28938 (UINT32_C(0x0) << 29)
28939 /* Value is in Kb or KB (base 10). */
28940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
28941 (UINT32_C(0x2) << 29)
28942 /* Value is in bits or bytes. */
28943 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
28944 (UINT32_C(0x4) << 29)
28945 /* Value is in Gb or GB (base 10). */
28946 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
28947 (UINT32_C(0x6) << 29)
28948 /* Value is in 1/100th of a percentage of total bandwidth. */
28949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28950 (UINT32_C(0x1) << 29)
28952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
28953 (UINT32_C(0x7) << 29)
28954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
28955 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
28956 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28957 uint8_t queue_id3_tsa_assign;
28958 /* Strict Priority */
28959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
28961 /* Enhanced Transmission Selection */
28962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
28965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
28968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
28971 * Priority level for strict priority. Valid only when the
28972 * tsa_assign is 0 - Strict Priority (SP)
28973 * 0..7 - Valid values.
28974 * 8..255 - Reserved.
28976 uint8_t queue_id3_pri_lvl;
28978 * Weight used to allocate remaining BW for this COS after
28979 * servicing guaranteed bandwidths for all COS.
28981 uint8_t queue_id3_bw_weight;
28982 /* ID of CoS Queue 4. */
28985 * Minimum BW allocated to CoS Queue.
28986 * The HWRM will translate this value into byte counter and
28987 * time interval used for this COS inside the device.
28989 uint32_t queue_id4_min_bw;
28990 /* The bandwidth value. */
28991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
28992 UINT32_C(0xfffffff)
28993 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
28995 /* The granularity of the value (bits or bytes). */
28996 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
28997 UINT32_C(0x10000000)
28998 /* Value is in bits. */
28999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
29000 (UINT32_C(0x0) << 28)
29001 /* Value is in bytes. */
29002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
29003 (UINT32_C(0x1) << 28)
29004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
29005 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
29006 /* bw_value_unit is 3 b */
29007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
29008 UINT32_C(0xe0000000)
29009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
29011 /* Value is in Mb or MB (base 10). */
29012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
29013 (UINT32_C(0x0) << 29)
29014 /* Value is in Kb or KB (base 10). */
29015 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
29016 (UINT32_C(0x2) << 29)
29017 /* Value is in bits or bytes. */
29018 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
29019 (UINT32_C(0x4) << 29)
29020 /* Value is in Gb or GB (base 10). */
29021 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
29022 (UINT32_C(0x6) << 29)
29023 /* Value is in 1/100th of a percentage of total bandwidth. */
29024 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29025 (UINT32_C(0x1) << 29)
29027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
29028 (UINT32_C(0x7) << 29)
29029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
29030 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
29032 * Maximum BW allocated to CoS queue.
29033 * The HWRM will translate this value into byte counter and
29034 * time interval used for this COS inside the device.
29036 uint32_t queue_id4_max_bw;
29037 /* The bandwidth value. */
29038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
29039 UINT32_C(0xfffffff)
29040 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
29042 /* The granularity of the value (bits or bytes). */
29043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
29044 UINT32_C(0x10000000)
29045 /* Value is in bits. */
29046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
29047 (UINT32_C(0x0) << 28)
29048 /* Value is in bytes. */
29049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
29050 (UINT32_C(0x1) << 28)
29051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
29052 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
29053 /* bw_value_unit is 3 b */
29054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
29055 UINT32_C(0xe0000000)
29056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
29058 /* Value is in Mb or MB (base 10). */
29059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
29060 (UINT32_C(0x0) << 29)
29061 /* Value is in Kb or KB (base 10). */
29062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
29063 (UINT32_C(0x2) << 29)
29064 /* Value is in bits or bytes. */
29065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
29066 (UINT32_C(0x4) << 29)
29067 /* Value is in Gb or GB (base 10). */
29068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
29069 (UINT32_C(0x6) << 29)
29070 /* Value is in 1/100th of a percentage of total bandwidth. */
29071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29072 (UINT32_C(0x1) << 29)
29074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
29075 (UINT32_C(0x7) << 29)
29076 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
29077 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
29078 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29079 uint8_t queue_id4_tsa_assign;
29080 /* Strict Priority */
29081 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
29083 /* Enhanced Transmission Selection */
29084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
29087 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
29090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
29093 * Priority level for strict priority. Valid only when the
29094 * tsa_assign is 0 - Strict Priority (SP)
29095 * 0..7 - Valid values.
29096 * 8..255 - Reserved.
29098 uint8_t queue_id4_pri_lvl;
29100 * Weight used to allocate remaining BW for this COS after
29101 * servicing guaranteed bandwidths for all COS.
29103 uint8_t queue_id4_bw_weight;
29104 /* ID of CoS Queue 5. */
29107 * Minimum BW allocated to CoS Queue.
29108 * The HWRM will translate this value into byte counter and
29109 * time interval used for this COS inside the device.
29111 uint32_t queue_id5_min_bw;
29112 /* The bandwidth value. */
29113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
29114 UINT32_C(0xfffffff)
29115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
29117 /* The granularity of the value (bits or bytes). */
29118 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
29119 UINT32_C(0x10000000)
29120 /* Value is in bits. */
29121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
29122 (UINT32_C(0x0) << 28)
29123 /* Value is in bytes. */
29124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
29125 (UINT32_C(0x1) << 28)
29126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
29127 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
29128 /* bw_value_unit is 3 b */
29129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
29130 UINT32_C(0xe0000000)
29131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
29133 /* Value is in Mb or MB (base 10). */
29134 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
29135 (UINT32_C(0x0) << 29)
29136 /* Value is in Kb or KB (base 10). */
29137 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
29138 (UINT32_C(0x2) << 29)
29139 /* Value is in bits or bytes. */
29140 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
29141 (UINT32_C(0x4) << 29)
29142 /* Value is in Gb or GB (base 10). */
29143 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
29144 (UINT32_C(0x6) << 29)
29145 /* Value is in 1/100th of a percentage of total bandwidth. */
29146 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29147 (UINT32_C(0x1) << 29)
29149 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
29150 (UINT32_C(0x7) << 29)
29151 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
29152 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
29154 * Maximum BW allocated to CoS queue.
29155 * The HWRM will translate this value into byte counter and
29156 * time interval used for this COS inside the device.
29158 uint32_t queue_id5_max_bw;
29159 /* The bandwidth value. */
29160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
29161 UINT32_C(0xfffffff)
29162 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
29164 /* The granularity of the value (bits or bytes). */
29165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
29166 UINT32_C(0x10000000)
29167 /* Value is in bits. */
29168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
29169 (UINT32_C(0x0) << 28)
29170 /* Value is in bytes. */
29171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
29172 (UINT32_C(0x1) << 28)
29173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
29174 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
29175 /* bw_value_unit is 3 b */
29176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
29177 UINT32_C(0xe0000000)
29178 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
29180 /* Value is in Mb or MB (base 10). */
29181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
29182 (UINT32_C(0x0) << 29)
29183 /* Value is in Kb or KB (base 10). */
29184 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
29185 (UINT32_C(0x2) << 29)
29186 /* Value is in bits or bytes. */
29187 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
29188 (UINT32_C(0x4) << 29)
29189 /* Value is in Gb or GB (base 10). */
29190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
29191 (UINT32_C(0x6) << 29)
29192 /* Value is in 1/100th of a percentage of total bandwidth. */
29193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29194 (UINT32_C(0x1) << 29)
29196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
29197 (UINT32_C(0x7) << 29)
29198 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
29199 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
29200 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29201 uint8_t queue_id5_tsa_assign;
29202 /* Strict Priority */
29203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
29205 /* Enhanced Transmission Selection */
29206 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
29209 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
29212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
29215 * Priority level for strict priority. Valid only when the
29216 * tsa_assign is 0 - Strict Priority (SP)
29217 * 0..7 - Valid values.
29218 * 8..255 - Reserved.
29220 uint8_t queue_id5_pri_lvl;
29222 * Weight used to allocate remaining BW for this COS after
29223 * servicing guaranteed bandwidths for all COS.
29225 uint8_t queue_id5_bw_weight;
29226 /* ID of CoS Queue 6. */
29229 * Minimum BW allocated to CoS Queue.
29230 * The HWRM will translate this value into byte counter and
29231 * time interval used for this COS inside the device.
29233 uint32_t queue_id6_min_bw;
29234 /* The bandwidth value. */
29235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
29236 UINT32_C(0xfffffff)
29237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
29239 /* The granularity of the value (bits or bytes). */
29240 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
29241 UINT32_C(0x10000000)
29242 /* Value is in bits. */
29243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
29244 (UINT32_C(0x0) << 28)
29245 /* Value is in bytes. */
29246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
29247 (UINT32_C(0x1) << 28)
29248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
29249 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
29250 /* bw_value_unit is 3 b */
29251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
29252 UINT32_C(0xe0000000)
29253 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
29255 /* Value is in Mb or MB (base 10). */
29256 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
29257 (UINT32_C(0x0) << 29)
29258 /* Value is in Kb or KB (base 10). */
29259 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
29260 (UINT32_C(0x2) << 29)
29261 /* Value is in bits or bytes. */
29262 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
29263 (UINT32_C(0x4) << 29)
29264 /* Value is in Gb or GB (base 10). */
29265 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
29266 (UINT32_C(0x6) << 29)
29267 /* Value is in 1/100th of a percentage of total bandwidth. */
29268 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29269 (UINT32_C(0x1) << 29)
29271 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
29272 (UINT32_C(0x7) << 29)
29273 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
29274 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
29276 * Maximum BW allocated to CoS queue.
29277 * The HWRM will translate this value into byte counter and
29278 * time interval used for this COS inside the device.
29280 uint32_t queue_id6_max_bw;
29281 /* The bandwidth value. */
29282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
29283 UINT32_C(0xfffffff)
29284 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
29286 /* The granularity of the value (bits or bytes). */
29287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
29288 UINT32_C(0x10000000)
29289 /* Value is in bits. */
29290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
29291 (UINT32_C(0x0) << 28)
29292 /* Value is in bytes. */
29293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
29294 (UINT32_C(0x1) << 28)
29295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
29296 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
29297 /* bw_value_unit is 3 b */
29298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
29299 UINT32_C(0xe0000000)
29300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
29302 /* Value is in Mb or MB (base 10). */
29303 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
29304 (UINT32_C(0x0) << 29)
29305 /* Value is in Kb or KB (base 10). */
29306 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
29307 (UINT32_C(0x2) << 29)
29308 /* Value is in bits or bytes. */
29309 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
29310 (UINT32_C(0x4) << 29)
29311 /* Value is in Gb or GB (base 10). */
29312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
29313 (UINT32_C(0x6) << 29)
29314 /* Value is in 1/100th of a percentage of total bandwidth. */
29315 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29316 (UINT32_C(0x1) << 29)
29318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
29319 (UINT32_C(0x7) << 29)
29320 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
29321 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
29322 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29323 uint8_t queue_id6_tsa_assign;
29324 /* Strict Priority */
29325 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
29327 /* Enhanced Transmission Selection */
29328 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
29331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
29334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
29337 * Priority level for strict priority. Valid only when the
29338 * tsa_assign is 0 - Strict Priority (SP)
29339 * 0..7 - Valid values.
29340 * 8..255 - Reserved.
29342 uint8_t queue_id6_pri_lvl;
29344 * Weight used to allocate remaining BW for this COS after
29345 * servicing guaranteed bandwidths for all COS.
29347 uint8_t queue_id6_bw_weight;
29348 /* ID of CoS Queue 7. */
29351 * Minimum BW allocated to CoS Queue.
29352 * The HWRM will translate this value into byte counter and
29353 * time interval used for this COS inside the device.
29355 uint32_t queue_id7_min_bw;
29356 /* The bandwidth value. */
29357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
29358 UINT32_C(0xfffffff)
29359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
29361 /* The granularity of the value (bits or bytes). */
29362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
29363 UINT32_C(0x10000000)
29364 /* Value is in bits. */
29365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
29366 (UINT32_C(0x0) << 28)
29367 /* Value is in bytes. */
29368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
29369 (UINT32_C(0x1) << 28)
29370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
29371 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
29372 /* bw_value_unit is 3 b */
29373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
29374 UINT32_C(0xe0000000)
29375 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
29377 /* Value is in Mb or MB (base 10). */
29378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
29379 (UINT32_C(0x0) << 29)
29380 /* Value is in Kb or KB (base 10). */
29381 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
29382 (UINT32_C(0x2) << 29)
29383 /* Value is in bits or bytes. */
29384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
29385 (UINT32_C(0x4) << 29)
29386 /* Value is in Gb or GB (base 10). */
29387 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
29388 (UINT32_C(0x6) << 29)
29389 /* Value is in 1/100th of a percentage of total bandwidth. */
29390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
29391 (UINT32_C(0x1) << 29)
29393 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
29394 (UINT32_C(0x7) << 29)
29395 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
29396 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
29398 * Maximum BW allocated to CoS queue.
29399 * The HWRM will translate this value into byte counter and
29400 * time interval used for this COS inside the device.
29402 uint32_t queue_id7_max_bw;
29403 /* The bandwidth value. */
29404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
29405 UINT32_C(0xfffffff)
29406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
29408 /* The granularity of the value (bits or bytes). */
29409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
29410 UINT32_C(0x10000000)
29411 /* Value is in bits. */
29412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
29413 (UINT32_C(0x0) << 28)
29414 /* Value is in bytes. */
29415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
29416 (UINT32_C(0x1) << 28)
29417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
29418 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
29419 /* bw_value_unit is 3 b */
29420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
29421 UINT32_C(0xe0000000)
29422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
29424 /* Value is in Mb or MB (base 10). */
29425 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
29426 (UINT32_C(0x0) << 29)
29427 /* Value is in Kb or KB (base 10). */
29428 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
29429 (UINT32_C(0x2) << 29)
29430 /* Value is in bits or bytes. */
29431 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
29432 (UINT32_C(0x4) << 29)
29433 /* Value is in Gb or GB (base 10). */
29434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
29435 (UINT32_C(0x6) << 29)
29436 /* Value is in 1/100th of a percentage of total bandwidth. */
29437 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
29438 (UINT32_C(0x1) << 29)
29440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
29441 (UINT32_C(0x7) << 29)
29442 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
29443 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
29444 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
29445 uint8_t queue_id7_tsa_assign;
29446 /* Strict Priority */
29447 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
29449 /* Enhanced Transmission Selection */
29450 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
29453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
29456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
29459 * Priority level for strict priority. Valid only when the
29460 * tsa_assign is 0 - Strict Priority (SP)
29461 * 0..7 - Valid values.
29462 * 8..255 - Reserved.
29464 uint8_t queue_id7_pri_lvl;
29466 * Weight used to allocate remaining BW for this COS after
29467 * servicing guaranteed bandwidths for all COS.
29469 uint8_t queue_id7_bw_weight;
29470 uint8_t unused_1[5];
29473 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
29474 struct hwrm_queue_cos2bw_cfg_output {
29475 /* The specific error status for the command. */
29476 uint16_t error_code;
29477 /* The HWRM command request type. */
29479 /* The sequence ID from the original command. */
29481 /* The length of the response data in number of bytes. */
29483 uint8_t unused_0[7];
29485 * This field is used in Output records to indicate that the output
29486 * is completely written to RAM. This field should be read as '1'
29487 * to indicate that the output has been completely written.
29488 * When writing a command completion or response to an internal processor,
29489 * the order of writes has to be such that this field is written last.
29494 /*************************
29495 * hwrm_queue_dscp_qcaps *
29496 *************************/
29499 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
29500 struct hwrm_queue_dscp_qcaps_input {
29501 /* The HWRM command request type. */
29504 * The completion ring to send the completion event on. This should
29505 * be the NQ ID returned from the `nq_alloc` HWRM command.
29507 uint16_t cmpl_ring;
29509 * The sequence ID is used by the driver for tracking multiple
29510 * commands. This ID is treated as opaque data by the firmware and
29511 * the value is returned in the `hwrm_resp_hdr` upon completion.
29515 * The target ID of the command:
29516 * * 0x0-0xFFF8 - The function ID
29517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29518 * * 0xFFFD - Reserved for user-space HWRM interface
29521 uint16_t target_id;
29523 * A physical address pointer pointing to a host buffer that the
29524 * command's response data will be written. This can be either a host
29525 * physical address (HPA) or a guest physical address (GPA) and must
29526 * point to a physically contiguous block of memory.
29528 uint64_t resp_addr;
29530 * Port ID of port for which the table is being configured.
29531 * The HWRM needs to check whether this function is allowed
29532 * to configure pri2cos mapping on this port.
29535 uint8_t unused_0[7];
29538 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
29539 struct hwrm_queue_dscp_qcaps_output {
29540 /* The specific error status for the command. */
29541 uint16_t error_code;
29542 /* The HWRM command request type. */
29544 /* The sequence ID from the original command. */
29546 /* The length of the response data in number of bytes. */
29548 /* The number of bits provided by the hardware for the DSCP value. */
29549 uint8_t num_dscp_bits;
29551 /* Max number of DSCP-MASK-PRI entries supported. */
29552 uint16_t max_entries;
29553 uint8_t unused_1[3];
29555 * This field is used in Output records to indicate that the output
29556 * is completely written to RAM. This field should be read as '1'
29557 * to indicate that the output has been completely written.
29558 * When writing a command completion or response to an internal processor,
29559 * the order of writes has to be such that this field is written last.
29564 /****************************
29565 * hwrm_queue_dscp2pri_qcfg *
29566 ****************************/
29569 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
29570 struct hwrm_queue_dscp2pri_qcfg_input {
29571 /* The HWRM command request type. */
29574 * The completion ring to send the completion event on. This should
29575 * be the NQ ID returned from the `nq_alloc` HWRM command.
29577 uint16_t cmpl_ring;
29579 * The sequence ID is used by the driver for tracking multiple
29580 * commands. This ID is treated as opaque data by the firmware and
29581 * the value is returned in the `hwrm_resp_hdr` upon completion.
29585 * The target ID of the command:
29586 * * 0x0-0xFFF8 - The function ID
29587 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29588 * * 0xFFFD - Reserved for user-space HWRM interface
29591 uint16_t target_id;
29593 * A physical address pointer pointing to a host buffer that the
29594 * command's response data will be written. This can be either a host
29595 * physical address (HPA) or a guest physical address (GPA) and must
29596 * point to a physically contiguous block of memory.
29598 uint64_t resp_addr;
29600 * This is the host address where the 24-bits DSCP-MASK-PRI
29601 * tuple(s) will be copied to.
29603 uint64_t dest_data_addr;
29605 * Port ID of port for which the table is being configured.
29606 * The HWRM needs to check whether this function is allowed
29607 * to configure pri2cos mapping on this port.
29611 /* Size of the buffer pointed to by dest_data_addr. */
29612 uint16_t dest_data_buffer_size;
29613 uint8_t unused_1[4];
29616 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
29617 struct hwrm_queue_dscp2pri_qcfg_output {
29618 /* The specific error status for the command. */
29619 uint16_t error_code;
29620 /* The HWRM command request type. */
29622 /* The sequence ID from the original command. */
29624 /* The length of the response data in number of bytes. */
29627 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
29628 * by the dest_data_addr.
29630 uint16_t entry_cnt;
29632 * This is the default PRI which un-initialized DSCP values are
29635 uint8_t default_pri;
29636 uint8_t unused_0[4];
29638 * This field is used in Output records to indicate that the output
29639 * is completely written to RAM. This field should be read as '1'
29640 * to indicate that the output has been completely written.
29641 * When writing a command completion or response to an internal processor,
29642 * the order of writes has to be such that this field is written last.
29647 /***************************
29648 * hwrm_queue_dscp2pri_cfg *
29649 ***************************/
29652 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
29653 struct hwrm_queue_dscp2pri_cfg_input {
29654 /* The HWRM command request type. */
29657 * The completion ring to send the completion event on. This should
29658 * be the NQ ID returned from the `nq_alloc` HWRM command.
29660 uint16_t cmpl_ring;
29662 * The sequence ID is used by the driver for tracking multiple
29663 * commands. This ID is treated as opaque data by the firmware and
29664 * the value is returned in the `hwrm_resp_hdr` upon completion.
29668 * The target ID of the command:
29669 * * 0x0-0xFFF8 - The function ID
29670 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29671 * * 0xFFFD - Reserved for user-space HWRM interface
29674 uint16_t target_id;
29676 * A physical address pointer pointing to a host buffer that the
29677 * command's response data will be written. This can be either a host
29678 * physical address (HPA) or a guest physical address (GPA) and must
29679 * point to a physically contiguous block of memory.
29681 uint64_t resp_addr;
29683 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
29684 * will be copied from.
29686 uint64_t src_data_addr;
29688 /* use_hw_default_pri is 1 b */
29689 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
29693 * This bit must be '1' for the default_pri field to be
29696 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
29699 * Port ID of port for which the table is being configured.
29700 * The HWRM needs to check whether this function is allowed
29701 * to configure pri2cos mapping on this port.
29705 * This is the default PRI which un-initialized DSCP values will be
29708 uint8_t default_pri;
29710 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
29711 * to by src_data_addr.
29713 uint16_t entry_cnt;
29714 uint8_t unused_0[4];
29717 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
29718 struct hwrm_queue_dscp2pri_cfg_output {
29719 /* The specific error status for the command. */
29720 uint16_t error_code;
29721 /* The HWRM command request type. */
29723 /* The sequence ID from the original command. */
29725 /* The length of the response data in number of bytes. */
29727 uint8_t unused_0[7];
29729 * This field is used in Output records to indicate that the output
29730 * is completely written to RAM. This field should be read as '1'
29731 * to indicate that the output has been completely written.
29732 * When writing a command completion or response to an internal processor,
29733 * the order of writes has to be such that this field is written last.
29738 /*************************
29739 * hwrm_queue_mpls_qcaps *
29740 *************************/
29743 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
29744 struct hwrm_queue_mpls_qcaps_input {
29745 /* The HWRM command request type. */
29748 * The completion ring to send the completion event on. This should
29749 * be the NQ ID returned from the `nq_alloc` HWRM command.
29751 uint16_t cmpl_ring;
29753 * The sequence ID is used by the driver for tracking multiple
29754 * commands. This ID is treated as opaque data by the firmware and
29755 * the value is returned in the `hwrm_resp_hdr` upon completion.
29759 * The target ID of the command:
29760 * * 0x0-0xFFF8 - The function ID
29761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29762 * * 0xFFFD - Reserved for user-space HWRM interface
29765 uint16_t target_id;
29767 * A physical address pointer pointing to a host buffer that the
29768 * command's response data will be written. This can be either a host
29769 * physical address (HPA) or a guest physical address (GPA) and must
29770 * point to a physically contiguous block of memory.
29772 uint64_t resp_addr;
29774 * Port ID of port for which the table is being configured.
29775 * The HWRM needs to check whether this function is allowed
29776 * to configure MPLS TC(EXP) to pri mapping on this port.
29779 uint8_t unused_0[7];
29782 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
29783 struct hwrm_queue_mpls_qcaps_output {
29784 /* The specific error status for the command. */
29785 uint16_t error_code;
29786 /* The HWRM command request type. */
29788 /* The sequence ID from the original command. */
29790 /* The length of the response data in number of bytes. */
29793 * Bitmask indicating which queues can be configured by the
29794 * hwrm_queue_mplstc2pri_cfg command.
29796 * Each bit represents a specific pri where bit 0 represents
29797 * pri 0 and bit 7 represents pri 7.
29798 * # A value of 0 indicates that the pri is not configurable
29799 * by the hwrm_queue_mplstc2pri_cfg command.
29800 * # A value of 1 indicates that the pri is configurable.
29801 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
29802 * trying to configure a pri that is not configurable.
29804 uint8_t queue_mplstc2pri_cfg_allowed;
29806 * This is the default PRI which un-initialized MPLS values will be
29809 uint8_t hw_default_pri;
29810 uint8_t unused_0[5];
29812 * This field is used in Output records to indicate that the output
29813 * is completely written to RAM. This field should be read as '1'
29814 * to indicate that the output has been completely written.
29815 * When writing a command completion or response to an internal processor,
29816 * the order of writes has to be such that this field is written last.
29821 /******************************
29822 * hwrm_queue_mplstc2pri_qcfg *
29823 ******************************/
29826 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
29827 struct hwrm_queue_mplstc2pri_qcfg_input {
29828 /* The HWRM command request type. */
29831 * The completion ring to send the completion event on. This should
29832 * be the NQ ID returned from the `nq_alloc` HWRM command.
29834 uint16_t cmpl_ring;
29836 * The sequence ID is used by the driver for tracking multiple
29837 * commands. This ID is treated as opaque data by the firmware and
29838 * the value is returned in the `hwrm_resp_hdr` upon completion.
29842 * The target ID of the command:
29843 * * 0x0-0xFFF8 - The function ID
29844 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29845 * * 0xFFFD - Reserved for user-space HWRM interface
29848 uint16_t target_id;
29850 * A physical address pointer pointing to a host buffer that the
29851 * command's response data will be written. This can be either a host
29852 * physical address (HPA) or a guest physical address (GPA) and must
29853 * point to a physically contiguous block of memory.
29855 uint64_t resp_addr;
29857 * Port ID of port for which the table is being configured.
29858 * The HWRM needs to check whether this function is allowed
29859 * to configure MPLS TC(EXP) to pri mapping on this port.
29862 uint8_t unused_0[7];
29865 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
29866 struct hwrm_queue_mplstc2pri_qcfg_output {
29867 /* The specific error status for the command. */
29868 uint16_t error_code;
29869 /* The HWRM command request type. */
29871 /* The sequence ID from the original command. */
29873 /* The length of the response data in number of bytes. */
29876 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
29877 * before traffic has started.
29878 * A value of 0xff indicates that no pri is assigned to the
29881 uint8_t tc0_pri_queue_id;
29883 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
29884 * before traffic has started.
29885 * A value of 0xff indicates that no pri is assigned to the
29888 uint8_t tc1_pri_queue_id;
29890 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
29891 * before traffic has started.
29892 * A value of 0xff indicates that no pri is assigned to the
29895 uint8_t tc2_pri_queue_id;
29897 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
29898 * before traffic has started.
29899 * A value of 0xff indicates that no pri is assigned to the
29902 uint8_t tc3_pri_queue_id;
29904 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
29905 * before traffic has started.
29906 * A value of 0xff indicates that no pri is assigned to the
29909 uint8_t tc4_pri_queue_id;
29911 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
29912 * before traffic has started.
29913 * A value of 0xff indicates that no pri is assigned to the
29916 uint8_t tc5_pri_queue_id;
29918 * pri assigned to MPLS TC(EXP) 6. This value can only
29919 * be changed before traffic has started.
29920 * A value of 0xff indicates that no pri is assigned to the
29923 uint8_t tc6_pri_queue_id;
29925 * pri assigned to MPLS TC(EXP) 7. This value can only
29926 * be changed before traffic has started.
29927 * A value of 0xff indicates that no pri is assigned to the
29930 uint8_t tc7_pri_queue_id;
29931 uint8_t unused_0[7];
29933 * This field is used in Output records to indicate that the output
29934 * is completely written to RAM. This field should be read as '1'
29935 * to indicate that the output has been completely written.
29936 * When writing a command completion or response to an internal processor,
29937 * the order of writes has to be such that this field is written last.
29942 /*****************************
29943 * hwrm_queue_mplstc2pri_cfg *
29944 *****************************/
29947 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
29948 struct hwrm_queue_mplstc2pri_cfg_input {
29949 /* The HWRM command request type. */
29952 * The completion ring to send the completion event on. This should
29953 * be the NQ ID returned from the `nq_alloc` HWRM command.
29955 uint16_t cmpl_ring;
29957 * The sequence ID is used by the driver for tracking multiple
29958 * commands. This ID is treated as opaque data by the firmware and
29959 * the value is returned in the `hwrm_resp_hdr` upon completion.
29963 * The target ID of the command:
29964 * * 0x0-0xFFF8 - The function ID
29965 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29966 * * 0xFFFD - Reserved for user-space HWRM interface
29969 uint16_t target_id;
29971 * A physical address pointer pointing to a host buffer that the
29972 * command's response data will be written. This can be either a host
29973 * physical address (HPA) or a guest physical address (GPA) and must
29974 * point to a physically contiguous block of memory.
29976 uint64_t resp_addr;
29979 * This bit must be '1' for the mplstc0_pri_queue_id field to be
29982 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
29985 * This bit must be '1' for the mplstc1_pri_queue_id field to be
29988 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
29991 * This bit must be '1' for the mplstc2_pri_queue_id field to be
29994 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
29997 * This bit must be '1' for the mplstc3_pri_queue_id field to be
30000 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
30003 * This bit must be '1' for the mplstc4_pri_queue_id field to be
30006 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
30009 * This bit must be '1' for the mplstc5_pri_queue_id field to be
30012 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
30015 * This bit must be '1' for the mplstc6_pri_queue_id field to be
30018 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
30021 * This bit must be '1' for the mplstc7_pri_queue_id field to be
30024 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
30027 * Port ID of port for which the table is being configured.
30028 * The HWRM needs to check whether this function is allowed
30029 * to configure MPLS TC(EXP)to pri mapping on this port.
30032 uint8_t unused_0[3];
30034 * pri assigned to MPLS TC(EXP) 0. This value can only
30035 * be changed before traffic has started.
30037 uint8_t tc0_pri_queue_id;
30039 * pri assigned to MPLS TC(EXP) 1. This value can only
30040 * be changed before traffic has started.
30042 uint8_t tc1_pri_queue_id;
30044 * pri assigned to MPLS TC(EXP) 2 This value can only
30045 * be changed before traffic has started.
30047 uint8_t tc2_pri_queue_id;
30049 * pri assigned to MPLS TC(EXP) 3. This value can only
30050 * be changed before traffic has started.
30052 uint8_t tc3_pri_queue_id;
30054 * pri assigned to MPLS TC(EXP) 4. This value can only
30055 * be changed before traffic has started.
30057 uint8_t tc4_pri_queue_id;
30059 * pri assigned to MPLS TC(EXP) 5. This value can only
30060 * be changed before traffic has started.
30062 uint8_t tc5_pri_queue_id;
30064 * pri assigned to MPLS TC(EXP) 6. This value can only
30065 * be changed before traffic has started.
30067 uint8_t tc6_pri_queue_id;
30069 * pri assigned to MPLS TC(EXP) 7. This value can only
30070 * be changed before traffic has started.
30072 uint8_t tc7_pri_queue_id;
30075 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
30076 struct hwrm_queue_mplstc2pri_cfg_output {
30077 /* The specific error status for the command. */
30078 uint16_t error_code;
30079 /* The HWRM command request type. */
30081 /* The sequence ID from the original command. */
30083 /* The length of the response data in number of bytes. */
30085 uint8_t unused_0[7];
30087 * This field is used in Output records to indicate that the output
30088 * is completely written to RAM. This field should be read as '1'
30089 * to indicate that the output has been completely written.
30090 * When writing a command completion or response to an internal processor,
30091 * the order of writes has to be such that this field is written last.
30096 /****************************
30097 * hwrm_queue_vlanpri_qcaps *
30098 ****************************/
30101 /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
30102 struct hwrm_queue_vlanpri_qcaps_input {
30103 /* The HWRM command request type. */
30106 * The completion ring to send the completion event on. This should
30107 * be the NQ ID returned from the `nq_alloc` HWRM command.
30109 uint16_t cmpl_ring;
30111 * The sequence ID is used by the driver for tracking multiple
30112 * commands. This ID is treated as opaque data by the firmware and
30113 * the value is returned in the `hwrm_resp_hdr` upon completion.
30117 * The target ID of the command:
30118 * * 0x0-0xFFF8 - The function ID
30119 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30120 * * 0xFFFD - Reserved for user-space HWRM interface
30123 uint16_t target_id;
30125 * A physical address pointer pointing to a host buffer that the
30126 * command's response data will be written. This can be either a host
30127 * physical address (HPA) or a guest physical address (GPA) and must
30128 * point to a physically contiguous block of memory.
30130 uint64_t resp_addr;
30132 * Port ID of port for which the table is being configured.
30133 * The HWRM needs to check whether this function is allowed
30134 * to configure VLAN priority to user priority mapping on this port.
30137 uint8_t unused_0[7];
30140 /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
30141 struct hwrm_queue_vlanpri_qcaps_output {
30142 /* The specific error status for the command. */
30143 uint16_t error_code;
30144 /* The HWRM command request type. */
30146 /* The sequence ID from the original command. */
30148 /* The length of the response data in number of bytes. */
30151 * This is the default user priority which all VLAN priority values
30152 * are mapped to if there is no VLAN priority to user priority mapping.
30154 uint8_t hw_default_pri;
30155 uint8_t unused_0[6];
30157 * This field is used in Output records to indicate that the output
30158 * is completely written to RAM. This field should be read as '1'
30159 * to indicate that the output has been completely written.
30160 * When writing a command completion or response to an internal processor,
30161 * the order of writes has to be such that this field is written last.
30166 /*******************************
30167 * hwrm_queue_vlanpri2pri_qcfg *
30168 *******************************/
30171 /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
30172 struct hwrm_queue_vlanpri2pri_qcfg_input {
30173 /* The HWRM command request type. */
30176 * The completion ring to send the completion event on. This should
30177 * be the NQ ID returned from the `nq_alloc` HWRM command.
30179 uint16_t cmpl_ring;
30181 * The sequence ID is used by the driver for tracking multiple
30182 * commands. This ID is treated as opaque data by the firmware and
30183 * the value is returned in the `hwrm_resp_hdr` upon completion.
30187 * The target ID of the command:
30188 * * 0x0-0xFFF8 - The function ID
30189 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30190 * * 0xFFFD - Reserved for user-space HWRM interface
30193 uint16_t target_id;
30195 * A physical address pointer pointing to a host buffer that the
30196 * command's response data will be written. This can be either a host
30197 * physical address (HPA) or a guest physical address (GPA) and must
30198 * point to a physically contiguous block of memory.
30200 uint64_t resp_addr;
30202 * Port ID of port for which the table is being configured.
30203 * The HWRM needs to check whether this function is allowed
30204 * to configure VLAN priority to user priority mapping on this port.
30207 uint8_t unused_0[7];
30210 /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
30211 struct hwrm_queue_vlanpri2pri_qcfg_output {
30212 /* The specific error status for the command. */
30213 uint16_t error_code;
30214 /* The HWRM command request type. */
30216 /* The sequence ID from the original command. */
30218 /* The length of the response data in number of bytes. */
30221 * User priority assigned to VLAN priority 0. A value of 0xff
30222 * indicates that no user priority is assigned. The default user
30223 * priority will be used.
30225 uint8_t vlanpri0_user_pri_id;
30227 * User priority assigned to VLAN priority 1. A value of 0xff
30228 * indicates that no user priority is assigned. The default user
30229 * priority will be used.
30231 uint8_t vlanpri1_user_pri_id;
30233 * User priority assigned to VLAN priority 2. A value of 0xff
30234 * indicates that no user priority is assigned. The default user
30235 * priority will be used.
30237 uint8_t vlanpri2_user_pri_id;
30239 * User priority assigned to VLAN priority 3. A value of 0xff
30240 * indicates that no user priority is assigned. The default user
30241 * priority will be used.
30243 uint8_t vlanpri3_user_pri_id;
30245 * User priority assigned to VLAN priority 4. A value of 0xff
30246 * indicates that no user priority is assigned. The default user
30247 * priority will be used.
30249 uint8_t vlanpri4_user_pri_id;
30251 * User priority assigned to VLAN priority 5. A value of 0xff
30252 * indicates that no user priority is assigned. The default user
30253 * priority will be used.
30255 uint8_t vlanpri5_user_pri_id;
30257 * User priority assigned to VLAN priority 6. A value of 0xff
30258 * indicates that no user priority is assigned. The default user
30259 * priority will be used.
30261 uint8_t vlanpri6_user_pri_id;
30263 * User priority assigned to VLAN priority 7. A value of 0xff
30264 * indicates that no user priority is assigned. The default user
30265 * priority will be used.
30267 uint8_t vlanpri7_user_pri_id;
30268 uint8_t unused_0[7];
30270 * This field is used in Output records to indicate that the output
30271 * is completely written to RAM. This field should be read as '1'
30272 * to indicate that the output has been completely written.
30273 * When writing a command completion or response to an internal processor,
30274 * the order of writes has to be such that this field is written last.
30279 /******************************
30280 * hwrm_queue_vlanpri2pri_cfg *
30281 ******************************/
30284 /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
30285 struct hwrm_queue_vlanpri2pri_cfg_input {
30286 /* The HWRM command request type. */
30289 * The completion ring to send the completion event on. This should
30290 * be the NQ ID returned from the `nq_alloc` HWRM command.
30292 uint16_t cmpl_ring;
30294 * The sequence ID is used by the driver for tracking multiple
30295 * commands. This ID is treated as opaque data by the firmware and
30296 * the value is returned in the `hwrm_resp_hdr` upon completion.
30300 * The target ID of the command:
30301 * * 0x0-0xFFF8 - The function ID
30302 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30303 * * 0xFFFD - Reserved for user-space HWRM interface
30306 uint16_t target_id;
30308 * A physical address pointer pointing to a host buffer that the
30309 * command's response data will be written. This can be either a host
30310 * physical address (HPA) or a guest physical address (GPA) and must
30311 * point to a physically contiguous block of memory.
30313 uint64_t resp_addr;
30316 * This bit must be '1' for the vlanpri0_user_pri_id field to be
30319 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
30322 * This bit must be '1' for the vlanpri1_user_pri_id field to be
30325 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
30328 * This bit must be '1' for the vlanpri2_user_pri_id field to be
30331 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
30334 * This bit must be '1' for the vlanpri3_user_pri_id field to be
30337 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
30340 * This bit must be '1' for the vlanpri4_user_pri_id field to be
30343 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
30346 * This bit must be '1' for the vlanpri5_user_pri_id field to be
30349 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
30352 * This bit must be '1' for the vlanpri6_user_pri_id field to be
30355 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
30358 * This bit must be '1' for the vlanpri7_user_pri_id field to be
30361 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
30364 * Port ID of port for which the table is being configured.
30365 * The HWRM needs to check whether this function is allowed
30366 * to configure VLAN priority to user priority mapping on this port.
30369 uint8_t unused_0[3];
30371 * User priority assigned to VLAN priority 0. This value can only
30372 * be changed before traffic has started.
30374 uint8_t vlanpri0_user_pri_id;
30376 * User priority assigned to VLAN priority 1. This value can only
30377 * be changed before traffic has started.
30379 uint8_t vlanpri1_user_pri_id;
30381 * User priority assigned to VLAN priority 2. This value can only
30382 * be changed before traffic has started.
30384 uint8_t vlanpri2_user_pri_id;
30386 * User priority assigned to VLAN priority 3. This value can only
30387 * be changed before traffic has started.
30389 uint8_t vlanpri3_user_pri_id;
30391 * User priority assigned to VLAN priority 4. This value can only
30392 * be changed before traffic has started.
30394 uint8_t vlanpri4_user_pri_id;
30396 * User priority assigned to VLAN priority 5. This value can only
30397 * be changed before traffic has started.
30399 uint8_t vlanpri5_user_pri_id;
30401 * User priority assigned to VLAN priority 6. This value can only
30402 * be changed before traffic has started.
30404 uint8_t vlanpri6_user_pri_id;
30406 * User priority assigned to VLAN priority 7. This value can only
30407 * be changed before traffic has started.
30409 uint8_t vlanpri7_user_pri_id;
30412 /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
30413 struct hwrm_queue_vlanpri2pri_cfg_output {
30414 /* The specific error status for the command. */
30415 uint16_t error_code;
30416 /* The HWRM command request type. */
30418 /* The sequence ID from the original command. */
30420 /* The length of the response data in number of bytes. */
30422 uint8_t unused_0[7];
30424 * This field is used in Output records to indicate that the output
30425 * is completely written to RAM. This field should be read as '1'
30426 * to indicate that the output has been completely written.
30427 * When writing a command completion or response to an internal processor,
30428 * the order of writes has to be such that this field is written last.
30433 /*******************
30434 * hwrm_vnic_alloc *
30435 *******************/
30438 /* hwrm_vnic_alloc_input (size:192b/24B) */
30439 struct hwrm_vnic_alloc_input {
30440 /* The HWRM command request type. */
30443 * The completion ring to send the completion event on. This should
30444 * be the NQ ID returned from the `nq_alloc` HWRM command.
30446 uint16_t cmpl_ring;
30448 * The sequence ID is used by the driver for tracking multiple
30449 * commands. This ID is treated as opaque data by the firmware and
30450 * the value is returned in the `hwrm_resp_hdr` upon completion.
30454 * The target ID of the command:
30455 * * 0x0-0xFFF8 - The function ID
30456 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30457 * * 0xFFFD - Reserved for user-space HWRM interface
30460 uint16_t target_id;
30462 * A physical address pointer pointing to a host buffer that the
30463 * command's response data will be written. This can be either a host
30464 * physical address (HPA) or a guest physical address (GPA) and must
30465 * point to a physically contiguous block of memory.
30467 uint64_t resp_addr;
30470 * When this bit is '1', this VNIC is requested to
30471 * be the default VNIC for this function.
30473 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
30476 * When this bit is '1', proxy VEE PF is requesting
30477 * allocation of a default VNIC on behalf of virtio-net
30478 * function given in virtio_net_fid field.
30480 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
30483 * Virtio-net function's FID.
30484 * This virtio-net function is requesting allocation of default
30485 * VNIC through proxy VEE PF.
30487 uint16_t virtio_net_fid;
30488 uint8_t unused_0[2];
30491 /* hwrm_vnic_alloc_output (size:128b/16B) */
30492 struct hwrm_vnic_alloc_output {
30493 /* The specific error status for the command. */
30494 uint16_t error_code;
30495 /* The HWRM command request type. */
30497 /* The sequence ID from the original command. */
30499 /* The length of the response data in number of bytes. */
30501 /* Logical vnic ID */
30503 uint8_t unused_0[3];
30505 * This field is used in Output records to indicate that the output
30506 * is completely written to RAM. This field should be read as '1'
30507 * to indicate that the output has been completely written.
30508 * When writing a command completion or response to an internal processor,
30509 * the order of writes has to be such that this field is written last.
30514 /********************
30515 * hwrm_vnic_update *
30516 ********************/
30519 /* hwrm_vnic_update_input (size:256b/32B) */
30520 struct hwrm_vnic_update_input {
30521 /* The HWRM command request type. */
30524 * The completion ring to send the completion event on. This should
30525 * be the NQ ID returned from the `nq_alloc` HWRM command.
30527 uint16_t cmpl_ring;
30529 * The sequence ID is used by the driver for tracking multiple
30530 * commands. This ID is treated as opaque data by the firmware and
30531 * the value is returned in the `hwrm_resp_hdr` upon completion.
30535 * The target ID of the command:
30536 * * 0x0-0xFFF8 - The function ID
30537 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30538 * * 0xFFFD - Reserved for user-space HWRM interface
30541 uint16_t target_id;
30543 * A physical address pointer pointing to a host buffer that the
30544 * command's response data will be written. This can be either a host
30545 * physical address (HPA) or a guest physical address (GPA) and must
30546 * point to a physically contiguous block of memory.
30548 uint64_t resp_addr;
30549 /* Logical vnic ID */
30553 * This bit must be '1' for the vnic_state field to be
30556 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
30559 * This bit must be '1' for the mru field to be
30562 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
30565 * This bit must be '1' for the metadata_format_type field to be
30568 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
30571 * This will update the context variable with the same name if
30572 * the corresponding enable is set.
30574 uint8_t vnic_state;
30575 /* Normal operation state for the VNIC. */
30576 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
30577 /* All packets are dropped in this state. */
30578 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
30579 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
30580 HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
30582 * The metadata format type used in all the RX packet completions
30583 * going through this VNIC.
30585 uint8_t metadata_format_type;
30586 /* No metadata information. */
30587 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
30590 * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
30593 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
30595 /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
30596 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
30598 /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
30599 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
30601 /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
30602 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
30604 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
30605 HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
30607 * The maximum receive unit of the vnic.
30608 * Each vnic is associated with a function.
30609 * The vnic mru value overwrites the mru setting of the
30610 * associated function.
30611 * The HWRM shall make sure that vnic mru does not exceed
30612 * the mru of the port the function is associated with.
30615 uint8_t unused_1[4];
30618 /* hwrm_vnic_update_output (size:128b/16B) */
30619 struct hwrm_vnic_update_output {
30620 /* The specific error status for the command. */
30621 uint16_t error_code;
30622 /* The HWRM command request type. */
30624 /* The sequence ID from the original command. */
30626 /* The length of the response data in number of bytes. */
30628 uint8_t unused_0[7];
30630 * This field is used in Output records to indicate that the output
30631 * is completely written to RAM. This field should be read as '1'
30632 * to indicate that the output has been completely written.
30633 * When writing a command completion or response to an internal
30634 * processor, the order of writes has to be such that this field is
30640 /******************
30642 ******************/
30645 /* hwrm_vnic_free_input (size:192b/24B) */
30646 struct hwrm_vnic_free_input {
30647 /* The HWRM command request type. */
30650 * The completion ring to send the completion event on. This should
30651 * be the NQ ID returned from the `nq_alloc` HWRM command.
30653 uint16_t cmpl_ring;
30655 * The sequence ID is used by the driver for tracking multiple
30656 * commands. This ID is treated as opaque data by the firmware and
30657 * the value is returned in the `hwrm_resp_hdr` upon completion.
30661 * The target ID of the command:
30662 * * 0x0-0xFFF8 - The function ID
30663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30664 * * 0xFFFD - Reserved for user-space HWRM interface
30667 uint16_t target_id;
30669 * A physical address pointer pointing to a host buffer that the
30670 * command's response data will be written. This can be either a host
30671 * physical address (HPA) or a guest physical address (GPA) and must
30672 * point to a physically contiguous block of memory.
30674 uint64_t resp_addr;
30675 /* Logical vnic ID */
30677 uint8_t unused_0[4];
30680 /* hwrm_vnic_free_output (size:128b/16B) */
30681 struct hwrm_vnic_free_output {
30682 /* The specific error status for the command. */
30683 uint16_t error_code;
30684 /* The HWRM command request type. */
30686 /* The sequence ID from the original command. */
30688 /* The length of the response data in number of bytes. */
30690 uint8_t unused_0[7];
30692 * This field is used in Output records to indicate that the output
30693 * is completely written to RAM. This field should be read as '1'
30694 * to indicate that the output has been completely written.
30695 * When writing a command completion or response to an internal processor,
30696 * the order of writes has to be such that this field is written last.
30706 /* hwrm_vnic_cfg_input (size:384b/48B) */
30707 struct hwrm_vnic_cfg_input {
30708 /* The HWRM command request type. */
30711 * The completion ring to send the completion event on. This should
30712 * be the NQ ID returned from the `nq_alloc` HWRM command.
30714 uint16_t cmpl_ring;
30716 * The sequence ID is used by the driver for tracking multiple
30717 * commands. This ID is treated as opaque data by the firmware and
30718 * the value is returned in the `hwrm_resp_hdr` upon completion.
30722 * The target ID of the command:
30723 * * 0x0-0xFFF8 - The function ID
30724 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30725 * * 0xFFFD - Reserved for user-space HWRM interface
30728 uint16_t target_id;
30730 * A physical address pointer pointing to a host buffer that the
30731 * command's response data will be written. This can be either a host
30732 * physical address (HPA) or a guest physical address (GPA) and must
30733 * point to a physically contiguous block of memory.
30735 uint64_t resp_addr;
30738 * When this bit is '1', the VNIC is requested to
30739 * be the default VNIC for the function.
30741 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
30744 * When this bit is '1', the VNIC is being configured to
30745 * strip VLAN in the RX path.
30746 * If set to '0', then VLAN stripping is disabled on
30749 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
30752 * When this bit is '1', the VNIC is being configured to
30753 * buffer receive packets in the hardware until the host
30754 * posts new receive buffers.
30755 * If set to '0', then bd_stall is being configured to be
30756 * disabled on this VNIC.
30758 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
30761 * When this bit is '1', the VNIC is being configured to
30762 * receive both RoCE and non-RoCE traffic.
30763 * If set to '0', then this VNIC is not configured to be
30764 * operating in dual VNIC mode.
30766 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
30769 * When this flag is set to '1', the VNIC is requested to
30770 * be configured to receive only RoCE traffic.
30771 * If this flag is set to '0', then this flag shall be
30772 * ignored by the HWRM.
30773 * If roce_dual_vnic_mode flag is set to '1'
30774 * or roce_mirroring_capable_vnic_mode flag to 1,
30775 * then the HWRM client shall not set this flag to '1'.
30777 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
30780 * When a VNIC uses one destination ring group for certain
30781 * application (e.g. Receive Flow Steering) where
30782 * exact match is used to direct packets to a VNIC with one
30783 * destination ring group only, there is no need to configure
30784 * RSS indirection table for that VNIC as only one destination
30785 * ring group is used.
30787 * This flag is used to enable a mode where
30788 * RSS is enabled in the VNIC using a RSS context
30789 * for computing RSS hash but the RSS indirection table is
30790 * not configured using hwrm_vnic_rss_cfg.
30792 * If this mode is enabled, then the driver should not program
30793 * RSS indirection table for the RSS context that is used for
30794 * computing RSS hash only.
30796 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
30799 * When this bit is '1', the VNIC is being configured to
30800 * receive both RoCE and non-RoCE traffic, but forward only the
30801 * RoCE traffic further. Also, RoCE traffic can be mirrored to
30804 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
30808 * This bit must be '1' for the dflt_ring_grp field to be
30811 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
30814 * This bit must be '1' for the rss_rule field to be
30817 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
30820 * This bit must be '1' for the cos_rule field to be
30823 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
30826 * This bit must be '1' for the lb_rule field to be
30829 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
30832 * This bit must be '1' for the mru field to be
30835 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
30838 * This bit must be '1' for the default_rx_ring_id field to be
30841 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
30844 * This bit must be '1' for the default_cmpl_ring_id field to be
30847 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
30849 /* This bit must be '1' for the queue_id field to be configured. */
30850 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
30852 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
30853 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
30855 /* Logical vnic ID */
30858 * Default Completion ring for the VNIC. This ring will
30859 * be chosen if packet does not match any RSS rules and if
30860 * there is no COS rule.
30862 uint16_t dflt_ring_grp;
30864 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
30865 * there is no RSS rule.
30869 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
30870 * there is no COS rule.
30874 * RSS ID for load balancing rule/table structure.
30875 * 0xFF... (All Fs) if there is no LB rule.
30879 * The maximum receive unit of the vnic.
30880 * Each vnic is associated with a function.
30881 * The vnic mru value overwrites the mru setting of the
30882 * associated function.
30883 * The HWRM shall make sure that vnic mru does not exceed
30884 * the mru of the port the function is associated with.
30888 * Default Rx ring for the VNIC. This ring will
30889 * be chosen if packet does not match any RSS rules.
30890 * The aggregation ring associated with the Rx ring is
30891 * implied based on the Rx ring specified when the
30892 * aggregation ring was allocated.
30894 uint16_t default_rx_ring_id;
30896 * Default completion ring for the VNIC. This ring will
30897 * be chosen if packet does not match any RSS rules.
30899 uint16_t default_cmpl_ring_id;
30901 * When specified, only incoming packets classified to the specified CoS
30902 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
30903 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
30904 * ntuple filters with VNIC destination specified are invalid since they
30905 * conflict with the CoS to VNIC steering rules in this mode.
30907 * If this field is not specified, packet to VNIC steering will be
30908 * subject to the standard L2 filter rules and any additional ntuple
30909 * filter rules with destination VNIC specified.
30913 * If the device supports the RX V2 and RX TPA start V2 completion
30914 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
30915 * used to specify the two RX checksum modes supported by these
30916 * completion records.
30918 uint8_t rx_csum_v2_mode;
30920 * When configured with this checksum mode, the number of header
30921 * groups in the delivered packet with a valid IP checksum and
30922 * the number of header groups in the delivered packet with a valid
30923 * L4 checksum are reported. Valid checksums are counted from the
30924 * outermost header group to the innermost header group, stopping at
30925 * the first error. This is the default checksum mode supported if
30926 * the driver doesn't explicitly configure the RX checksum mode.
30928 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
30930 * When configured with this checksum mode, the checksum status is
30931 * reported using 'all ok' mode. In the RX completion record, one
30932 * bit indicates if the IP checksum is valid for all the parsed
30933 * header groups with an IP checksum. Another bit indicates if the
30934 * L4 checksum is valid for all the parsed header groups with an L4
30935 * checksum. The number of header groups that were parsed by the
30936 * chip and passed in the delivered packet is also reported.
30938 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
30940 * Any rx_csum_v2_mode value larger than or equal to this is not
30943 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
30944 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
30945 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
30946 uint8_t unused0[5];
30949 /* hwrm_vnic_cfg_output (size:128b/16B) */
30950 struct hwrm_vnic_cfg_output {
30951 /* The specific error status for the command. */
30952 uint16_t error_code;
30953 /* The HWRM command request type. */
30955 /* The sequence ID from the original command. */
30957 /* The length of the response data in number of bytes. */
30959 uint8_t unused_0[7];
30961 * This field is used in Output records to indicate that the output
30962 * is completely written to RAM. This field should be read as '1'
30963 * to indicate that the output has been completely written.
30964 * When writing a command completion or response to an internal processor,
30965 * the order of writes has to be such that this field is written last.
30970 /******************
30972 ******************/
30975 /* hwrm_vnic_qcfg_input (size:256b/32B) */
30976 struct hwrm_vnic_qcfg_input {
30977 /* The HWRM command request type. */
30980 * The completion ring to send the completion event on. This should
30981 * be the NQ ID returned from the `nq_alloc` HWRM command.
30983 uint16_t cmpl_ring;
30985 * The sequence ID is used by the driver for tracking multiple
30986 * commands. This ID is treated as opaque data by the firmware and
30987 * the value is returned in the `hwrm_resp_hdr` upon completion.
30991 * The target ID of the command:
30992 * * 0x0-0xFFF8 - The function ID
30993 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30994 * * 0xFFFD - Reserved for user-space HWRM interface
30997 uint16_t target_id;
30999 * A physical address pointer pointing to a host buffer that the
31000 * command's response data will be written. This can be either a host
31001 * physical address (HPA) or a guest physical address (GPA) and must
31002 * point to a physically contiguous block of memory.
31004 uint64_t resp_addr;
31007 * This bit must be '1' for the vf_id_valid field to be
31010 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
31011 /* Logical vnic ID */
31013 /* ID of Virtual Function whose VNIC resource is being queried. */
31015 uint8_t unused_0[6];
31018 /* hwrm_vnic_qcfg_output (size:256b/32B) */
31019 struct hwrm_vnic_qcfg_output {
31020 /* The specific error status for the command. */
31021 uint16_t error_code;
31022 /* The HWRM command request type. */
31024 /* The sequence ID from the original command. */
31026 /* The length of the response data in number of bytes. */
31028 /* Default Completion ring for the VNIC. */
31029 uint16_t dflt_ring_grp;
31031 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
31032 * there is no RSS rule.
31036 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
31037 * there is no COS rule.
31041 * RSS ID for load balancing rule/table structure.
31042 * 0xFF... (All Fs) if there is no LB rule.
31045 /* The maximum receive unit of the vnic. */
31047 uint8_t unused_0[2];
31050 * When this bit is '1', the VNIC is the default VNIC for
31053 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
31056 * When this bit is '1', the VNIC is configured to
31057 * strip VLAN in the RX path.
31058 * If set to '0', then VLAN stripping is disabled on
31061 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
31064 * When this bit is '1', the VNIC is configured to
31065 * buffer receive packets in the hardware until the host
31066 * posts new receive buffers.
31067 * If set to '0', then bd_stall is disabled on
31070 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
31073 * When this bit is '1', the VNIC is configured to
31074 * receive both RoCE and non-RoCE traffic.
31075 * If set to '0', then this VNIC is not configured to
31076 * operate in dual VNIC mode.
31078 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
31081 * When this flag is set to '1', the VNIC is configured to
31082 * receive only RoCE traffic.
31083 * When this flag is set to '0', the VNIC is not configured
31084 * to receive only RoCE traffic.
31085 * If roce_dual_vnic_mode flag and this flag both are set
31086 * to '1', then it is an invalid configuration of the
31087 * VNIC. The HWRM should not allow that type of
31088 * mis-configuration by HWRM clients.
31090 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
31093 * When a VNIC uses one destination ring group for certain
31094 * application (e.g. Receive Flow Steering) where
31095 * exact match is used to direct packets to a VNIC with one
31096 * destination ring group only, there is no need to configure
31097 * RSS indirection table for that VNIC as only one destination
31098 * ring group is used.
31100 * When this bit is set to '1', then the VNIC is enabled in a
31101 * mode where RSS is enabled in the VNIC using a RSS context
31102 * for computing RSS hash but the RSS indirection table is
31105 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
31108 * When this bit is '1', the VNIC is configured to
31109 * receive both RoCE and non-RoCE traffic, but forward only
31110 * RoCE traffic further. Also RoCE traffic can be mirrored to
31113 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
31116 * When this bit is '0', VNIC is in normal operation state.
31117 * When this bit is '1', VNIC drops all the received packets.
31119 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
31122 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
31123 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
31124 * queue association.
31128 * If the device supports the RX V2 and RX TPA start V2 completion
31129 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
31130 * used to specify the current RX checksum mode configured for all the
31131 * RX rings of a VNIC.
31133 uint8_t rx_csum_v2_mode;
31135 * This value indicates that the VNIC is configured to use the
31136 * default RX checksum mode for all the rings associated with this
31139 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
31141 * This value indicates that the VNIC is configured to use the RX
31142 * checksum ‘all_ok’ mode for all the rings associated with this
31145 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
31147 * Any rx_csum_v2_mode value larger than or equal to this is not
31150 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
31151 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
31152 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
31153 uint8_t unused_1[4];
31155 * This field is used in Output records to indicate that the output
31156 * is completely written to RAM. This field should be read as '1'
31157 * to indicate that the output has been completely written.
31158 * When writing a command completion or response to an internal processor,
31159 * the order of writes has to be such that this field is written last.
31164 /*******************
31165 * hwrm_vnic_qcaps *
31166 *******************/
31169 /* hwrm_vnic_qcaps_input (size:192b/24B) */
31170 struct hwrm_vnic_qcaps_input {
31171 /* The HWRM command request type. */
31174 * The completion ring to send the completion event on. This should
31175 * be the NQ ID returned from the `nq_alloc` HWRM command.
31177 uint16_t cmpl_ring;
31179 * The sequence ID is used by the driver for tracking multiple
31180 * commands. This ID is treated as opaque data by the firmware and
31181 * the value is returned in the `hwrm_resp_hdr` upon completion.
31185 * The target ID of the command:
31186 * * 0x0-0xFFF8 - The function ID
31187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31188 * * 0xFFFD - Reserved for user-space HWRM interface
31191 uint16_t target_id;
31193 * A physical address pointer pointing to a host buffer that the
31194 * command's response data will be written. This can be either a host
31195 * physical address (HPA) or a guest physical address (GPA) and must
31196 * point to a physically contiguous block of memory.
31198 uint64_t resp_addr;
31200 uint8_t unused_0[4];
31203 /* hwrm_vnic_qcaps_output (size:192b/24B) */
31204 struct hwrm_vnic_qcaps_output {
31205 /* The specific error status for the command. */
31206 uint16_t error_code;
31207 /* The HWRM command request type. */
31209 /* The sequence ID from the original command. */
31211 /* The length of the response data in number of bytes. */
31213 /* The maximum receive unit that is settable on a vnic. */
31215 uint8_t unused_0[2];
31218 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
31221 * When this bit is '1', the capability of stripping VLAN in
31222 * the RX path is supported on VNIC(s).
31223 * If set to '0', then VLAN stripping capability is
31224 * not supported on VNIC(s).
31226 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
31229 * When this bit is '1', the capability to buffer receive
31230 * packets in the hardware until the host posts new receive buffers
31231 * is supported on VNIC(s).
31232 * If set to '0', then bd_stall capability is not supported
31235 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
31238 * When this bit is '1', the capability to
31239 * receive both RoCE and non-RoCE traffic on VNIC(s) is
31241 * If set to '0', then the capability to receive
31242 * both RoCE and non-RoCE traffic on VNIC(s) is
31245 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
31248 * When this bit is set to '1', the capability to configure
31249 * a VNIC to receive only RoCE traffic is supported.
31250 * When this flag is set to '0', the VNIC capability to
31251 * configure to receive only RoCE traffic is not supported.
31253 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
31256 * When this bit is set to '1', then the capability to enable
31257 * a VNIC in a mode where RSS context without configuring
31258 * RSS indirection table is supported (for RSS hash computation).
31259 * When this bit is set to '0', then a VNIC can not be configured
31260 * with a mode to enable RSS context without configuring RSS
31261 * indirection table.
31263 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
31266 * When this bit is '1', the capability to
31267 * mirror the RoCE traffic is supported.
31268 * If set to '0', then the capability to mirror the
31269 * RoCE traffic is not supported.
31271 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
31274 * When this bit is '1', the outermost RSS hashing capability
31275 * is supported. If set to '0', then the outermost RSS hashing
31276 * capability is not supported.
31278 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
31281 * When this bit is '1', it indicates that firmware supports the
31282 * ability to steer incoming packets from one CoS queue to one
31283 * VNIC. This optional feature can then be enabled
31284 * using HWRM_VNIC_CFG on any VNIC. This feature is only
31285 * available when NVM option “enable_cos_classfication” is set
31286 * to 1. If set to '0', firmware does not support this feature.
31288 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
31291 * When this bit is '1', it indicates that HW and firmware supports
31292 * the use of RX V2 and RX TPA start V2 completion records for all
31293 * the RX rings of a VNIC. Once set, this feature is mandatory to
31294 * be used for the RX rings of the VNIC. Additionally, two new RX
31295 * checksum features supported by these ompletion records can be
31296 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
31297 * HW and the firmware does not support this feature.
31299 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
31302 * When this bit is '1', it indicates that HW and firmware support
31303 * vnic state change. Host drivers can change the vnic state using
31304 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
31305 * support this feature.
31307 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
31310 * When this bit is '1', it indicates that firmware supports
31311 * virtio-net functions default VNIC allocation using
31313 * This capability is available only on Proxy VEE PF. If set to '0',
31314 * firmware does not support this feature.
31316 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
31319 * When this bit is set '1', then the capability to configure the
31320 * metadata format in the RX completion is supported for the VNIC.
31321 * When this bit is set to '0', then the capability to configure
31322 * the metadata format in the RX completion is not supported for
31325 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
31328 * This field advertises the maximum concurrent TPA aggregations
31329 * supported by the VNIC on new devices that support TPA v2.
31330 * '0' means that TPA v2 is not supported.
31332 uint16_t max_aggs_supported;
31333 uint8_t unused_1[5];
31335 * This field is used in Output records to indicate that the output
31336 * is completely written to RAM. This field should be read as '1'
31337 * to indicate that the output has been completely written.
31338 * When writing a command completion or response to an internal processor,
31339 * the order of writes has to be such that this field is written last.
31344 /*********************
31345 * hwrm_vnic_tpa_cfg *
31346 *********************/
31349 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
31350 struct hwrm_vnic_tpa_cfg_input {
31351 /* The HWRM command request type. */
31354 * The completion ring to send the completion event on. This should
31355 * be the NQ ID returned from the `nq_alloc` HWRM command.
31357 uint16_t cmpl_ring;
31359 * The sequence ID is used by the driver for tracking multiple
31360 * commands. This ID is treated as opaque data by the firmware and
31361 * the value is returned in the `hwrm_resp_hdr` upon completion.
31365 * The target ID of the command:
31366 * * 0x0-0xFFF8 - The function ID
31367 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31368 * * 0xFFFD - Reserved for user-space HWRM interface
31371 uint16_t target_id;
31373 * A physical address pointer pointing to a host buffer that the
31374 * command's response data will be written. This can be either a host
31375 * physical address (HPA) or a guest physical address (GPA) and must
31376 * point to a physically contiguous block of memory.
31378 uint64_t resp_addr;
31381 * When this bit is '1', the VNIC shall be configured to
31382 * perform transparent packet aggregation (TPA) of
31383 * non-tunneled TCP packets.
31385 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
31388 * When this bit is '1', the VNIC shall be configured to
31389 * perform transparent packet aggregation (TPA) of
31390 * tunneled TCP packets.
31392 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
31395 * When this bit is '1', the VNIC shall be configured to
31396 * perform transparent packet aggregation (TPA) according
31397 * to Windows Receive Segment Coalescing (RSC) rules.
31399 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
31402 * When this bit is '1', the VNIC shall be configured to
31403 * perform transparent packet aggregation (TPA) according
31404 * to Linux Generic Receive Offload (GRO) rules.
31406 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
31409 * When this bit is '1', the VNIC shall be configured to
31410 * perform transparent packet aggregation (TPA) for TCP
31411 * packets with IP ECN set to non-zero.
31413 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
31416 * When this bit is '1', the VNIC shall be configured to
31417 * perform transparent packet aggregation (TPA) for
31418 * GRE tunneled TCP packets only if all packets have the
31419 * same GRE sequence.
31421 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
31424 * When this bit is '1' and the GRO mode is enabled,
31425 * the VNIC shall be configured to
31426 * perform transparent packet aggregation (TPA) for
31427 * TCP/IPv4 packets with consecutively increasing IPIDs.
31428 * In other words, the last packet that is being
31429 * aggregated to an already existing aggregation context
31430 * shall have IPID 1 more than the IPID of the last packet
31431 * that was aggregated in that aggregation context.
31433 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
31436 * When this bit is '1' and the GRO mode is enabled,
31437 * the VNIC shall be configured to
31438 * perform transparent packet aggregation (TPA) for
31439 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
31442 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
31445 * When this bit is '1' and the GRO mode is enabled,
31446 * the VNIC shall DMA payload data using GRO rules.
31447 * When this bit is '0', the VNIC shall DMA payload data
31448 * using the more efficient LRO rules of filling all
31449 * aggregation buffers.
31451 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
31455 * This bit must be '1' for the max_agg_segs field to be
31458 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
31460 * This bit must be '1' for the max_aggs field to be
31463 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
31465 * This bit must be '1' for the max_agg_timer field to be
31468 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
31469 /* deprecated bit. Do not use!!! */
31470 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
31471 /* Logical vnic ID */
31474 * This is the maximum number of TCP segments that can
31475 * be aggregated (unit is Log2). Max value is 31. On new
31476 * devices supporting TPA v2, the unit is multiples of 4 and
31477 * valid values are > 0 and <= 63.
31479 uint16_t max_agg_segs;
31481 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
31483 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
31485 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
31487 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
31488 /* Any segment size larger than this is not valid */
31489 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
31490 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
31491 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
31493 * This is the maximum number of aggregations this VNIC is
31494 * allowed (unit is Log2). Max value is 7. On new devices
31495 * supporting TPA v2, this is in unit of 1 and must be > 0
31496 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
31497 * to enable TPA v2.
31500 /* 1 aggregation */
31501 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
31502 /* 2 aggregations */
31503 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
31504 /* 4 aggregations */
31505 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
31506 /* 8 aggregations */
31507 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
31508 /* 16 aggregations */
31509 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
31510 /* Any aggregation size larger than this is not valid */
31511 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
31512 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
31513 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
31514 uint8_t unused_0[2];
31516 * This is the maximum amount of time allowed for
31517 * an aggregation context to complete after it was initiated.
31519 uint32_t max_agg_timer;
31521 * This is the minimum amount of payload length required to
31522 * start an aggregation context. This field is deprecated and
31523 * should be set to 0. The minimum length is set by firmware
31524 * and can be queried using hwrm_vnic_tpa_qcfg.
31526 uint32_t min_agg_len;
31529 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
31530 struct hwrm_vnic_tpa_cfg_output {
31531 /* The specific error status for the command. */
31532 uint16_t error_code;
31533 /* The HWRM command request type. */
31535 /* The sequence ID from the original command. */
31537 /* The length of the response data in number of bytes. */
31539 uint8_t unused_0[7];
31541 * This field is used in Output records to indicate that the output
31542 * is completely written to RAM. This field should be read as '1'
31543 * to indicate that the output has been completely written.
31544 * When writing a command completion or response to an internal processor,
31545 * the order of writes has to be such that this field is written last.
31550 /*********************
31551 * hwrm_vnic_rss_cfg *
31552 *********************/
31555 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
31556 struct hwrm_vnic_rss_cfg_input {
31557 /* The HWRM command request type. */
31560 * The completion ring to send the completion event on. This should
31561 * be the NQ ID returned from the `nq_alloc` HWRM command.
31563 uint16_t cmpl_ring;
31565 * The sequence ID is used by the driver for tracking multiple
31566 * commands. This ID is treated as opaque data by the firmware and
31567 * the value is returned in the `hwrm_resp_hdr` upon completion.
31571 * The target ID of the command:
31572 * * 0x0-0xFFF8 - The function ID
31573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31574 * * 0xFFFD - Reserved for user-space HWRM interface
31577 uint16_t target_id;
31579 * A physical address pointer pointing to a host buffer that the
31580 * command's response data will be written. This can be either a host
31581 * physical address (HPA) or a guest physical address (GPA) and must
31582 * point to a physically contiguous block of memory.
31584 uint64_t resp_addr;
31585 uint32_t hash_type;
31587 * When this bit is '1', the RSS hash shall be computed
31588 * over source and destination IPv4 addresses of IPv4
31591 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
31593 * When this bit is '1', the RSS hash shall be computed
31594 * over source/destination IPv4 addresses and
31595 * source/destination ports of TCP/IPv4 packets.
31597 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
31599 * When this bit is '1', the RSS hash shall be computed
31600 * over source/destination IPv4 addresses and
31601 * source/destination ports of UDP/IPv4 packets.
31603 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
31605 * When this bit is '1', the RSS hash shall be computed
31606 * over source and destination IPv4 addresses of IPv6
31609 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
31611 * When this bit is '1', the RSS hash shall be computed
31612 * over source/destination IPv6 addresses and
31613 * source/destination ports of TCP/IPv6 packets.
31615 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
31617 * When this bit is '1', the RSS hash shall be computed
31618 * over source/destination IPv6 addresses and
31619 * source/destination ports of UDP/IPv6 packets.
31621 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
31622 /* VNIC ID of VNIC associated with RSS table being configured. */
31625 * Specifies which VNIC ring table pair to configure.
31626 * Valid values range from 0 to 7.
31628 uint8_t ring_table_pair_index;
31629 /* Flags to specify different RSS hash modes. */
31630 uint8_t hash_mode_flags;
31632 * When this bit is '1', it indicates using current RSS
31633 * hash mode setting configured in the device.
31635 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
31638 * When this bit is '1', it indicates requesting support of
31639 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
31640 * l4.src, l4.dest} for tunnel packets. For none-tunnel
31641 * packets, the RSS hash is computed over the normal
31642 * src/dest l3 and src/dest l4 headers.
31644 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
31647 * When this bit is '1', it indicates requesting support of
31648 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
31649 * tunnel packets. For none-tunnel packets, the RSS hash is
31650 * computed over the normal src/dest l3 headers.
31652 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
31655 * When this bit is '1', it indicates requesting support of
31656 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
31657 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
31658 * packets, the RSS hash is computed over the normal
31659 * src/dest l3 and src/dest l4 headers.
31661 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
31664 * When this bit is '1', it indicates requesting support of
31665 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
31666 * tunnel packets. For none-tunnel packets, the RSS hash is
31667 * computed over the normal src/dest l3 headers.
31669 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
31671 /* This is the address for rss ring group table */
31672 uint64_t ring_grp_tbl_addr;
31673 /* This is the address for rss hash key table */
31674 uint64_t hash_key_tbl_addr;
31675 /* Index to the rss indirection table. */
31676 uint16_t rss_ctx_idx;
31677 uint8_t unused_1[6];
31680 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
31681 struct hwrm_vnic_rss_cfg_output {
31682 /* The specific error status for the command. */
31683 uint16_t error_code;
31684 /* The HWRM command request type. */
31686 /* The sequence ID from the original command. */
31688 /* The length of the response data in number of bytes. */
31690 uint8_t unused_0[7];
31692 * This field is used in Output records to indicate that the output
31693 * is completely written to RAM. This field should be read as '1'
31694 * to indicate that the output has been completely written.
31695 * When writing a command completion or response to an internal processor,
31696 * the order of writes has to be such that this field is written last.
31701 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
31702 struct hwrm_vnic_rss_cfg_cmd_err {
31704 * command specific error codes that goes to
31705 * the cmd_err field in Common HWRM Error Response.
31708 /* Unknown error */
31709 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
31712 * Unable to change global RSS mode to outer due to all active
31713 * interfaces are not ready to support outer RSS hashing.
31715 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
31717 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
31718 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
31719 uint8_t unused_0[7];
31722 /**********************
31723 * hwrm_vnic_rss_qcfg *
31724 **********************/
31727 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
31728 struct hwrm_vnic_rss_qcfg_input {
31729 /* The HWRM command request type. */
31732 * The completion ring to send the completion event on. This should
31733 * be the NQ ID returned from the `nq_alloc` HWRM command.
31735 uint16_t cmpl_ring;
31737 * The sequence ID is used by the driver for tracking multiple
31738 * commands. This ID is treated as opaque data by the firmware and
31739 * the value is returned in the `hwrm_resp_hdr` upon completion.
31743 * The target ID of the command:
31744 * * 0x0-0xFFF8 - The function ID
31745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31746 * * 0xFFFD - Reserved for user-space HWRM interface
31749 uint16_t target_id;
31751 * A physical address pointer pointing to a host buffer that the
31752 * command's response data will be written. This can be either a host
31753 * physical address (HPA) or a guest physical address (GPA) and must
31754 * point to a physically contiguous block of memory.
31756 uint64_t resp_addr;
31757 /* Index to the rss indirection table. */
31758 uint16_t rss_ctx_idx;
31759 uint8_t unused_0[6];
31762 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
31763 struct hwrm_vnic_rss_qcfg_output {
31764 /* The specific error status for the command. */
31765 uint16_t error_code;
31766 /* The HWRM command request type. */
31768 /* The sequence ID from the original command. */
31770 /* The length of the response data in number of bytes. */
31772 uint32_t hash_type;
31774 * When this bit is '1', the RSS hash shall be computed
31775 * over source and destination IPv4 addresses of IPv4
31778 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
31780 * When this bit is '1', the RSS hash shall be computed
31781 * over source/destination IPv4 addresses and
31782 * source/destination ports of TCP/IPv4 packets.
31784 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
31786 * When this bit is '1', the RSS hash shall be computed
31787 * over source/destination IPv4 addresses and
31788 * source/destination ports of UDP/IPv4 packets.
31790 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
31792 * When this bit is '1', the RSS hash shall be computed
31793 * over source and destination IPv4 addresses of IPv6
31796 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
31798 * When this bit is '1', the RSS hash shall be computed
31799 * over source/destination IPv6 addresses and
31800 * source/destination ports of TCP/IPv6 packets.
31802 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
31804 * When this bit is '1', the RSS hash shall be computed
31805 * over source/destination IPv6 addresses and
31806 * source/destination ports of UDP/IPv6 packets.
31808 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
31809 uint8_t unused_0[4];
31810 /* This is the value of rss hash key */
31811 uint32_t hash_key[10];
31812 /* Flags to specify different RSS hash modes. */
31813 uint8_t hash_mode_flags;
31815 * When this bit is '1', it indicates using current RSS
31816 * hash mode setting configured in the device.
31818 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
31821 * When this bit is '1', it indicates requesting support of
31822 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
31823 * l4.src, l4.dest} for tunnel packets. For none-tunnel
31824 * packets, the RSS hash is computed over the normal
31825 * src/dest l3 and src/dest l4 headers.
31827 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
31830 * When this bit is '1', it indicates requesting support of
31831 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
31832 * tunnel packets. For none-tunnel packets, the RSS hash is
31833 * computed over the normal src/dest l3 headers.
31835 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
31838 * When this bit is '1', it indicates requesting support of
31839 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
31840 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
31841 * packets, the RSS hash is computed over the normal
31842 * src/dest l3 and src/dest l4 headers.
31844 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
31847 * When this bit is '1', it indicates requesting support of
31848 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
31849 * tunnel packets. For none-tunnel packets, the RSS hash is
31850 * computed over the normal src/dest l3 headers.
31852 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
31854 uint8_t unused_1[6];
31856 * This field is used in Output records to indicate that the output
31857 * is completely written to RAM. This field should be read as '1'
31858 * to indicate that the output has been completely written.
31859 * When writing a command completion or response to an internal processor,
31860 * the order of writes has to be such that this field is written last.
31865 /**************************
31866 * hwrm_vnic_plcmodes_cfg *
31867 **************************/
31870 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
31871 struct hwrm_vnic_plcmodes_cfg_input {
31872 /* The HWRM command request type. */
31875 * The completion ring to send the completion event on. This should
31876 * be the NQ ID returned from the `nq_alloc` HWRM command.
31878 uint16_t cmpl_ring;
31880 * The sequence ID is used by the driver for tracking multiple
31881 * commands. This ID is treated as opaque data by the firmware and
31882 * the value is returned in the `hwrm_resp_hdr` upon completion.
31886 * The target ID of the command:
31887 * * 0x0-0xFFF8 - The function ID
31888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31889 * * 0xFFFD - Reserved for user-space HWRM interface
31892 uint16_t target_id;
31894 * A physical address pointer pointing to a host buffer that the
31895 * command's response data will be written. This can be either a host
31896 * physical address (HPA) or a guest physical address (GPA) and must
31897 * point to a physically contiguous block of memory.
31899 uint64_t resp_addr;
31902 * When this bit is '1', the VNIC shall be configured to
31903 * use regular placement algorithm.
31904 * By default, the regular placement algorithm shall be
31905 * enabled on the VNIC.
31907 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
31910 * When this bit is '1', the VNIC shall be configured
31911 * use the jumbo placement algorithm.
31913 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
31916 * When this bit is '1', the VNIC shall be configured
31917 * to enable Header-Data split for IPv4 packets according
31918 * to the following rules:
31919 * # If the packet is identified as TCP/IPv4, then the
31920 * packet is split at the beginning of the TCP payload.
31921 * # If the packet is identified as UDP/IPv4, then the
31922 * packet is split at the beginning of UDP payload.
31923 * # If the packet is identified as non-TCP and non-UDP
31924 * IPv4 packet, then the packet is split at the beginning
31925 * of the upper layer protocol header carried in the IPv4
31928 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
31931 * When this bit is '1', the VNIC shall be configured
31932 * to enable Header-Data split for IPv6 packets according
31933 * to the following rules:
31934 * # If the packet is identified as TCP/IPv6, then the
31935 * packet is split at the beginning of the TCP payload.
31936 * # If the packet is identified as UDP/IPv6, then the
31937 * packet is split at the beginning of UDP payload.
31938 * # If the packet is identified as non-TCP and non-UDP
31939 * IPv6 packet, then the packet is split at the beginning
31940 * of the upper layer protocol header carried in the IPv6
31943 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
31946 * When this bit is '1', the VNIC shall be configured
31947 * to enable Header-Data split for FCoE packets at the
31948 * beginning of FC payload.
31950 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
31953 * When this bit is '1', the VNIC shall be configured
31954 * to enable Header-Data split for RoCE packets at the
31955 * beginning of RoCE payload (after BTH/GRH headers).
31957 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
31960 * When this bit is '1', the VNIC shall be configured use the virtio
31961 * placement algorithm. This feature can only be configured when
31962 * proxy mode is supported on the function.
31964 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
31968 * This bit must be '1' for the jumbo_thresh_valid field to be
31971 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
31974 * This bit must be '1' for the hds_offset_valid field to be
31977 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
31980 * This bit must be '1' for the hds_threshold_valid field to be
31983 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
31986 * This bit must be '1' for the max_bds_valid field to be
31989 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
31991 /* Logical vnic ID */
31994 * When jumbo placement algorithm is enabled, this value
31995 * is used to determine the threshold for jumbo placement.
31996 * Packets with length larger than this value will be
31997 * placed according to the jumbo placement algorithm.
31999 uint16_t jumbo_thresh;
32001 * This value is used to determine the offset into
32002 * packet buffer where the split data (payload) will be
32003 * placed according to one of HDS placement algorithm.
32005 * The lengths of packet buffers provided for split data
32006 * shall be larger than this value.
32008 uint16_t hds_offset;
32010 * When one of the HDS placement algorithm is enabled, this
32011 * value is used to determine the threshold for HDS
32013 * Packets with length larger than this value will be
32014 * placed according to the HDS placement algorithm.
32015 * This value shall be in multiple of 4 bytes.
32017 uint16_t hds_threshold;
32019 * When virtio placement algorithm is enabled, this
32020 * value is used to determine the maximum number of BDs
32021 * that can be used to place an Rx Packet.
32022 * If an incoming packet does not fit in the buffers described
32023 * by the max BDs, the packet will be dropped and an error
32024 * will be reported in the completion. Valid values for this
32025 * field are between 1 and 8. If the VNIC uses header-data-
32026 * separation and/or TPA with buffer spanning enabled, valid
32027 * values for this field are between 2 and 8.
32028 * This feature can only be configured when proxy mode is
32029 * supported on the function.
32032 uint8_t unused_0[4];
32035 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
32036 struct hwrm_vnic_plcmodes_cfg_output {
32037 /* The specific error status for the command. */
32038 uint16_t error_code;
32039 /* The HWRM command request type. */
32041 /* The sequence ID from the original command. */
32043 /* The length of the response data in number of bytes. */
32045 uint8_t unused_0[7];
32047 * This field is used in Output records to indicate that the output
32048 * is completely written to RAM. This field should be read as '1'
32049 * to indicate that the output has been completely written.
32050 * When writing a command completion or response to an internal
32051 * processor, the order of writes has to be such that this field is
32057 /***************************
32058 * hwrm_vnic_plcmodes_qcfg *
32059 ***************************/
32062 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
32063 struct hwrm_vnic_plcmodes_qcfg_input {
32064 /* The HWRM command request type. */
32067 * The completion ring to send the completion event on. This should
32068 * be the NQ ID returned from the `nq_alloc` HWRM command.
32070 uint16_t cmpl_ring;
32072 * The sequence ID is used by the driver for tracking multiple
32073 * commands. This ID is treated as opaque data by the firmware and
32074 * the value is returned in the `hwrm_resp_hdr` upon completion.
32078 * The target ID of the command:
32079 * * 0x0-0xFFF8 - The function ID
32080 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32081 * * 0xFFFD - Reserved for user-space HWRM interface
32084 uint16_t target_id;
32086 * A physical address pointer pointing to a host buffer that the
32087 * command's response data will be written. This can be either a host
32088 * physical address (HPA) or a guest physical address (GPA) and must
32089 * point to a physically contiguous block of memory.
32091 uint64_t resp_addr;
32092 /* Logical vnic ID */
32094 uint8_t unused_0[4];
32097 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
32098 struct hwrm_vnic_plcmodes_qcfg_output {
32099 /* The specific error status for the command. */
32100 uint16_t error_code;
32101 /* The HWRM command request type. */
32103 /* The sequence ID from the original command. */
32105 /* The length of the response data in number of bytes. */
32109 * When this bit is '1', the VNIC is configured to
32110 * use regular placement algorithm.
32112 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
32115 * When this bit is '1', the VNIC is configured to
32116 * use the jumbo placement algorithm.
32118 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
32121 * When this bit is '1', the VNIC is configured
32122 * to enable Header-Data split for IPv4 packets.
32124 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
32127 * When this bit is '1', the VNIC is configured
32128 * to enable Header-Data split for IPv6 packets.
32130 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
32133 * When this bit is '1', the VNIC is configured
32134 * to enable Header-Data split for FCoE packets.
32136 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
32139 * When this bit is '1', the VNIC is configured
32140 * to enable Header-Data split for RoCE packets.
32142 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
32145 * When this bit is '1', the VNIC is configured
32146 * to be the default VNIC of the requesting function.
32148 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
32151 * When this bit is '1', the VNIC is configured to use the virtio
32152 * placement algorithm. This feature can only be configured when
32153 * proxy mode is supported on the function.
32155 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
32158 * When jumbo placement algorithm is enabled, this value
32159 * is used to determine the threshold for jumbo placement.
32160 * Packets with length larger than this value will be
32161 * placed according to the jumbo placement algorithm.
32163 uint16_t jumbo_thresh;
32165 * This value is used to determine the offset into
32166 * packet buffer where the split data (payload) will be
32167 * placed according to one of HDS placement algorithm.
32169 * The lengths of packet buffers provided for split data
32170 * shall be larger than this value.
32172 uint16_t hds_offset;
32174 * When one of the HDS placement algorithm is enabled, this
32175 * value is used to determine the threshold for HDS
32177 * Packets with length larger than this value will be
32178 * placed according to the HDS placement algorithm.
32179 * This value shall be in multiple of 4 bytes.
32181 uint16_t hds_threshold;
32183 * When virtio placement algorithm is enabled, this
32184 * value is used to determine the maximum number of BDs
32185 * that can be used to place an Rx Packet.
32186 * If an incoming packet does not fit in the buffers described
32187 * by the max BDs, the packet will be dropped and an error
32188 * will be reported in the completion. Valid values for this
32189 * field are between 1 and 8. If the VNIC uses header-data-
32190 * separation and/or TPA with buffer spanning enabled, valid
32191 * values for this field are between 2 and 8.
32192 * This feature can only be configured when proxy mode is supported
32196 uint8_t unused_0[3];
32198 * This field is used in Output records to indicate that the output
32199 * is completely written to RAM. This field should be read as '1'
32200 * to indicate that the output has been completely written.
32201 * When writing a command completion or response to an internal
32202 * processor, the order of writes has to be such that this field is
32208 /**********************************
32209 * hwrm_vnic_rss_cos_lb_ctx_alloc *
32210 **********************************/
32213 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
32214 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
32215 /* The HWRM command request type. */
32218 * The completion ring to send the completion event on. This should
32219 * be the NQ ID returned from the `nq_alloc` HWRM command.
32221 uint16_t cmpl_ring;
32223 * The sequence ID is used by the driver for tracking multiple
32224 * commands. This ID is treated as opaque data by the firmware and
32225 * the value is returned in the `hwrm_resp_hdr` upon completion.
32229 * The target ID of the command:
32230 * * 0x0-0xFFF8 - The function ID
32231 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32232 * * 0xFFFD - Reserved for user-space HWRM interface
32235 uint16_t target_id;
32237 * A physical address pointer pointing to a host buffer that the
32238 * command's response data will be written. This can be either a host
32239 * physical address (HPA) or a guest physical address (GPA) and must
32240 * point to a physically contiguous block of memory.
32242 uint64_t resp_addr;
32245 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
32246 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
32247 /* The specific error status for the command. */
32248 uint16_t error_code;
32249 /* The HWRM command request type. */
32251 /* The sequence ID from the original command. */
32253 /* The length of the response data in number of bytes. */
32255 /* rss_cos_lb_ctx_id is 16 b */
32256 uint16_t rss_cos_lb_ctx_id;
32257 uint8_t unused_0[5];
32259 * This field is used in Output records to indicate that the output
32260 * is completely written to RAM. This field should be read as '1'
32261 * to indicate that the output has been completely written.
32262 * When writing a command completion or response to an internal processor,
32263 * the order of writes has to be such that this field is written last.
32268 /*********************************
32269 * hwrm_vnic_rss_cos_lb_ctx_free *
32270 *********************************/
32273 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
32274 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
32275 /* The HWRM command request type. */
32278 * The completion ring to send the completion event on. This should
32279 * be the NQ ID returned from the `nq_alloc` HWRM command.
32281 uint16_t cmpl_ring;
32283 * The sequence ID is used by the driver for tracking multiple
32284 * commands. This ID is treated as opaque data by the firmware and
32285 * the value is returned in the `hwrm_resp_hdr` upon completion.
32289 * The target ID of the command:
32290 * * 0x0-0xFFF8 - The function ID
32291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32292 * * 0xFFFD - Reserved for user-space HWRM interface
32295 uint16_t target_id;
32297 * A physical address pointer pointing to a host buffer that the
32298 * command's response data will be written. This can be either a host
32299 * physical address (HPA) or a guest physical address (GPA) and must
32300 * point to a physically contiguous block of memory.
32302 uint64_t resp_addr;
32303 /* rss_cos_lb_ctx_id is 16 b */
32304 uint16_t rss_cos_lb_ctx_id;
32305 uint8_t unused_0[6];
32308 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
32309 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
32310 /* The specific error status for the command. */
32311 uint16_t error_code;
32312 /* The HWRM command request type. */
32314 /* The sequence ID from the original command. */
32316 /* The length of the response data in number of bytes. */
32318 uint8_t unused_0[7];
32320 * This field is used in Output records to indicate that the output
32321 * is completely written to RAM. This field should be read as '1'
32322 * to indicate that the output has been completely written.
32323 * When writing a command completion or response to an internal processor,
32324 * the order of writes has to be such that this field is written last.
32329 /*******************
32330 * hwrm_ring_alloc *
32331 *******************/
32334 /* hwrm_ring_alloc_input (size:704b/88B) */
32335 struct hwrm_ring_alloc_input {
32336 /* The HWRM command request type. */
32339 * The completion ring to send the completion event on. This should
32340 * be the NQ ID returned from the `nq_alloc` HWRM command.
32342 uint16_t cmpl_ring;
32344 * The sequence ID is used by the driver for tracking multiple
32345 * commands. This ID is treated as opaque data by the firmware and
32346 * the value is returned in the `hwrm_resp_hdr` upon completion.
32350 * The target ID of the command:
32351 * * 0x0-0xFFF8 - The function ID
32352 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32353 * * 0xFFFD - Reserved for user-space HWRM interface
32356 uint16_t target_id;
32358 * A physical address pointer pointing to a host buffer that the
32359 * command's response data will be written. This can be either a host
32360 * physical address (HPA) or a guest physical address (GPA) and must
32361 * point to a physically contiguous block of memory.
32363 uint64_t resp_addr;
32366 * This bit must be '1' for the ring_arb_cfg field to be
32369 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
32372 * This bit must be '1' for the stat_ctx_id_valid field to be
32375 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
32378 * This bit must be '1' for the max_bw_valid field to be
32381 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
32384 * This bit must be '1' for the rx_ring_id field to be
32387 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
32390 * This bit must be '1' for the nq_ring_id field to be
32393 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
32396 * This bit must be '1' for the rx_buf_size field to be
32399 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
32402 * This bit must be '1' for the schq_id field to be
32405 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
32408 * This bit must be '1' for the mpc_chnls_type field to be
32411 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
32415 /* L2 Completion Ring (CR) */
32416 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
32418 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
32420 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
32421 /* RoCE Notification Completion Ring (ROCE_CR) */
32422 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
32423 /* RX Aggregation Ring */
32424 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
32425 /* Notification Queue */
32426 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
32427 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
32428 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
32430 /* Ring allocation flags. */
32433 * For Rx rings, the incoming packet data can be placed at either
32434 * a 0B or 2B offset from the start of the Rx packet buffer. When
32435 * '1', the received packet will be padded with 2B of zeros at the
32436 * front of the packet. Note that this flag is only used for
32437 * Rx rings and is ignored for all other rings included Rx
32438 * Aggregation rings.
32440 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
32442 * This value is a pointer to the page table for the
32445 uint64_t page_tbl_addr;
32446 /* First Byte Offset of the first entry in the first page. */
32449 * Actual page size in 2^page_size. The supported range is increments
32450 * in powers of 2 from 16 bytes to 1GB.
32452 * Page size is 16 B.
32454 * Page size is 4 KB.
32456 * Page size is 8 KB.
32458 * Page size is 64 KB.
32460 * Page size is 2 MB.
32462 * Page size is 4 MB.
32464 * Page size is 1 GB.
32468 * This value indicates the depth of page table.
32469 * For this version of the specification, value other than 0 or
32470 * 1 shall be considered as an invalid value.
32471 * When the page_tbl_depth = 0, then it is treated as a
32472 * special case with the following.
32473 * 1. FBO and page size fields are not valid.
32474 * 2. page_tbl_addr is the physical address of the first
32475 * element of the ring.
32477 uint8_t page_tbl_depth;
32478 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
32481 * Number of 16B units in the ring. Minimum size for
32482 * a ring is 16 16B entries.
32486 * Logical ring number for the ring to be allocated.
32487 * This value determines the position in the doorbell
32488 * area where the update to the ring will be made.
32490 * For completion rings, this value is also the MSI-X
32491 * vector number for the function the completion ring is
32494 uint16_t logical_id;
32496 * This field is used only when ring_type is a TX ring.
32497 * This value indicates what completion ring the TX ring
32498 * is associated with.
32500 uint16_t cmpl_ring_id;
32502 * This field is used only when ring_type is a TX ring.
32503 * This value indicates what CoS queue the TX ring
32504 * is associated with.
32508 * When allocating a Rx ring or Rx aggregation ring, this field
32509 * specifies the size of the buffer descriptors posted to the ring.
32511 uint16_t rx_buf_size;
32513 * When allocating an Rx aggregation ring, this field
32514 * specifies the associated Rx ring ID.
32516 uint16_t rx_ring_id;
32518 * When allocating a completion ring, this field
32519 * specifies the associated NQ ring ID.
32521 uint16_t nq_ring_id;
32523 * This field is used only when ring_type is a TX ring.
32524 * This field is used to configure arbitration related
32525 * parameters for a TX ring.
32527 uint16_t ring_arb_cfg;
32528 /* Arbitration policy used for the ring. */
32529 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
32531 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
32533 * Use strict priority for the TX ring.
32534 * Priority value is specified in arb_policy_param
32536 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
32539 * Use weighted fair queue arbitration for the TX ring.
32540 * Weight is specified in arb_policy_param
32542 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
32544 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
32545 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
32546 /* Reserved field. */
32547 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
32549 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
32551 * Arbitration policy specific parameter.
32552 * # For strict priority arbitration policy, this field
32553 * represents a priority value. If set to 0, then the priority
32554 * is not specified and the HWRM is allowed to select
32555 * any priority for this TX ring.
32556 * # For weighted fair queue arbitration policy, this field
32557 * represents a weight value. If set to 0, then the weight
32558 * is not specified and the HWRM is allowed to select
32559 * any weight for this TX ring.
32561 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
32563 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
32566 * This field is reserved for the future use.
32567 * It shall be set to 0.
32569 uint32_t reserved3;
32571 * This field is used only when ring_type is a TX ring.
32572 * This input indicates what statistics context this ring
32573 * should be associated with.
32575 uint32_t stat_ctx_id;
32577 * This field is reserved for the future use.
32578 * It shall be set to 0.
32580 uint32_t reserved4;
32582 * This field is used only when ring_type is a TX ring
32583 * to specify maximum BW allocated to the TX ring.
32584 * The HWRM will translate this value into byte counter and
32585 * time interval used for this ring inside the device.
32588 /* The bandwidth value. */
32589 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
32590 UINT32_C(0xfffffff)
32591 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
32592 /* The granularity of the value (bits or bytes). */
32593 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
32594 UINT32_C(0x10000000)
32595 /* Value is in bits. */
32596 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
32597 (UINT32_C(0x0) << 28)
32598 /* Value is in bytes. */
32599 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
32600 (UINT32_C(0x1) << 28)
32601 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
32602 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
32603 /* bw_value_unit is 3 b */
32604 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
32605 UINT32_C(0xe0000000)
32606 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
32607 /* Value is in Mb or MB (base 10). */
32608 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
32609 (UINT32_C(0x0) << 29)
32610 /* Value is in Kb or KB (base 10). */
32611 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
32612 (UINT32_C(0x2) << 29)
32613 /* Value is in bits or bytes. */
32614 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
32615 (UINT32_C(0x4) << 29)
32616 /* Value is in Gb or GB (base 10). */
32617 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
32618 (UINT32_C(0x6) << 29)
32619 /* Value is in 1/100th of a percentage of total bandwidth. */
32620 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
32621 (UINT32_C(0x1) << 29)
32623 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
32624 (UINT32_C(0x7) << 29)
32625 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
32626 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
32628 * This field is used only when ring_type is a Completion ring.
32629 * This value indicates what interrupt mode should be used
32630 * on this completion ring.
32631 * Note: In the legacy interrupt mode, no more than 16
32632 * completion rings are allowed.
32636 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
32638 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
32640 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
32641 /* No Interrupt - Polled mode */
32642 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
32643 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
32644 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
32645 /* Midpath channel type */
32646 uint8_t mpc_chnls_type;
32648 * Indicate the TX ring alloc MPC channel type is a MPC channel
32649 * with destination to the TX crypto engine block.
32651 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
32653 * Indicate the RX ring alloc MPC channel type is a MPC channel
32654 * with destination to the RX crypto engine block.
32656 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
32658 * Indicate the RX ring alloc MPC channel type is a MPC channel
32659 * with destination to the TX configurable flow processing block.
32661 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
32663 * Indicate the RX ring alloc MPC channel type is a MPC channel
32664 * with destination to the RX configurable flow processing block.
32666 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
32668 * Indicate the RX ring alloc MPC channel type is a MPC channel
32669 * with destination to the primate processor block.
32671 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
32672 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
32673 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
32674 uint8_t unused_4[2];
32676 * The cq_handle is specified when allocating a completion ring. For
32677 * devices that support NQs, this cq_handle will be included in the
32678 * NQE to specify which CQ should be read to retrieve the completion
32681 uint64_t cq_handle;
32684 /* hwrm_ring_alloc_output (size:128b/16B) */
32685 struct hwrm_ring_alloc_output {
32686 /* The specific error status for the command. */
32687 uint16_t error_code;
32688 /* The HWRM command request type. */
32690 /* The sequence ID from the original command. */
32692 /* The length of the response data in number of bytes. */
32695 * Physical number of ring allocated.
32696 * This value shall be unique for a ring type.
32699 /* Logical number of ring allocated. */
32700 uint16_t logical_ring_id;
32702 * This field will tell whether to use ping or pong buffer
32703 * for first push operation.
32705 uint8_t push_buffer_index;
32706 /* Start push from ping buffer index */
32707 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
32709 /* Start push from pong buffer index */
32710 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
32712 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
32713 HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
32714 uint8_t unused_0[2];
32716 * This field is used in Output records to indicate that the output
32717 * is completely written to RAM. This field should be read as '1'
32718 * to indicate that the output has been completely written.
32719 * When writing a command completion or response to an internal processor,
32720 * the order of writes has to be such that this field is written last.
32725 /******************
32727 ******************/
32730 /* hwrm_ring_free_input (size:256b/32B) */
32731 struct hwrm_ring_free_input {
32732 /* The HWRM command request type. */
32735 * The completion ring to send the completion event on. This should
32736 * be the NQ ID returned from the `nq_alloc` HWRM command.
32738 uint16_t cmpl_ring;
32740 * The sequence ID is used by the driver for tracking multiple
32741 * commands. This ID is treated as opaque data by the firmware and
32742 * the value is returned in the `hwrm_resp_hdr` upon completion.
32746 * The target ID of the command:
32747 * * 0x0-0xFFF8 - The function ID
32748 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32749 * * 0xFFFD - Reserved for user-space HWRM interface
32752 uint16_t target_id;
32754 * A physical address pointer pointing to a host buffer that the
32755 * command's response data will be written. This can be either a host
32756 * physical address (HPA) or a guest physical address (GPA) and must
32757 * point to a physically contiguous block of memory.
32759 uint64_t resp_addr;
32762 /* L2 Completion Ring (CR) */
32763 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
32765 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
32767 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
32768 /* RoCE Notification Completion Ring (ROCE_CR) */
32769 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
32770 /* RX Aggregation Ring */
32771 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
32772 /* Notification Queue */
32773 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
32774 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
32775 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
32778 * If this bit is set to '1', ring_id in this command belongs to
32779 * virtio function. prod_idx in this command corresponds to doorbell
32780 * producer index. opaque field in this command needs to be inserted
32781 * by firmware in VEE_FLUSH completion record.
32782 * Firmware will poll the corresponding ring context to reach the
32783 * given producer index before sending successful response. It will
32784 * finish the completion using VEE_FLUSH completion record.
32786 * If this bit is '0', firmware will not treat ring_id as virtio
32787 * ring and ignore prod_idx, opaque fields.
32789 * This feature is not applicable for L2 or RoCE.
32791 #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
32792 #define HWRM_RING_FREE_INPUT_FLAGS_LAST \
32793 HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID
32794 /* Physical number of ring allocated. */
32797 * Ring BD producer index posted by the virtio block.
32798 * This field is valid if virtio_ring_valid flag is set.
32802 * User defined opaque field to be inserted into VEE_FLUSH completion
32803 * record. This field is valid if virtio_ring_valid flag is set.
32809 /* hwrm_ring_free_output (size:128b/16B) */
32810 struct hwrm_ring_free_output {
32811 /* The specific error status for the command. */
32812 uint16_t error_code;
32813 /* The HWRM command request type. */
32815 /* The sequence ID from the original command. */
32817 /* The length of the response data in number of bytes. */
32819 uint8_t unused_0[7];
32821 * This field is used in Output records to indicate that the output
32822 * is completely written to RAM. This field should be read as '1'
32823 * to indicate that the output has been completely written.
32824 * When writing a command completion or response to an internal processor,
32825 * the order of writes has to be such that this field is written last.
32830 /*******************
32831 * hwrm_ring_reset *
32832 *******************/
32835 /* hwrm_ring_reset_input (size:192b/24B) */
32836 struct hwrm_ring_reset_input {
32837 /* The HWRM command request type. */
32840 * The completion ring to send the completion event on. This should
32841 * be the NQ ID returned from the `nq_alloc` HWRM command.
32843 uint16_t cmpl_ring;
32845 * The sequence ID is used by the driver for tracking multiple
32846 * commands. This ID is treated as opaque data by the firmware and
32847 * the value is returned in the `hwrm_resp_hdr` upon completion.
32851 * The target ID of the command:
32852 * * 0x0-0xFFF8 - The function ID
32853 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32854 * * 0xFFFD - Reserved for user-space HWRM interface
32857 uint16_t target_id;
32859 * A physical address pointer pointing to a host buffer that the
32860 * command's response data will be written. This can be either a host
32861 * physical address (HPA) or a guest physical address (GPA) and must
32862 * point to a physically contiguous block of memory.
32864 uint64_t resp_addr;
32867 /* L2 Completion Ring (CR) */
32868 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
32870 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
32872 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
32873 /* RoCE Notification Completion Ring (ROCE_CR) */
32874 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
32876 * Rx Ring Group. This is to reset rx and aggregation in an atomic
32877 * operation. Completion ring associated with this ring group is
32880 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
32881 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
32882 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
32885 * Physical number of the ring. When ring type is rx_ring_grp, ring id
32886 * actually refers to ring group id.
32889 uint8_t unused_1[4];
32892 /* hwrm_ring_reset_output (size:128b/16B) */
32893 struct hwrm_ring_reset_output {
32894 /* The specific error status for the command. */
32895 uint16_t error_code;
32896 /* The HWRM command request type. */
32898 /* The sequence ID from the original command. */
32900 /* The length of the response data in number of bytes. */
32903 * This field will tell whether to use ping or pong buffer
32904 * for first push operation.
32906 uint8_t push_buffer_index;
32907 /* Start push from ping buffer index */
32908 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
32910 /* Start push from pong buffer index */
32911 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
32913 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
32914 HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
32915 uint8_t unused_0[3];
32916 /* Position of consumer index after ring reset completes. */
32917 uint8_t consumer_idx[3];
32919 * This field is used in Output records to indicate that the output
32920 * is completely written to RAM. This field should be read as '1'
32921 * to indicate that the output has been completely written.
32922 * When writing a command completion or response to an internal processor,
32923 * the order of writes has to be such that this field is written last.
32933 /* hwrm_ring_cfg_input (size:320b/40B) */
32934 struct hwrm_ring_cfg_input {
32935 /* The HWRM command request type. */
32938 * The completion ring to send the completion event on. This should
32939 * be the NQ ID returned from the `nq_alloc` HWRM command.
32941 uint16_t cmpl_ring;
32943 * The sequence ID is used by the driver for tracking multiple
32944 * commands. This ID is treated as opaque data by the firmware and
32945 * the value is returned in the `hwrm_resp_hdr` upon completion.
32949 * The target ID of the command:
32950 * * 0x0-0xFFF8 - The function ID
32951 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32952 * * 0xFFFD - Reserved for user-space HWRM interface
32955 uint16_t target_id;
32957 * A physical address pointer pointing to a host buffer that the
32958 * command's response data will be written. This can be either a host
32959 * physical address (HPA) or a guest physical address (GPA) and must
32960 * point to a physically contiguous block of memory.
32962 uint64_t resp_addr;
32966 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
32968 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
32969 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
32970 HWRM_RING_CFG_INPUT_RING_TYPE_RX
32972 /* Physical number of the ring. */
32974 /* Ring config enable bits. */
32977 * For Rx rings, the incoming packet data can be placed at either
32978 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
32980 * When '1', the received packet will be padded with 2B, 10B or 12B
32981 * of zeros at the front of the packet. The exact offset is specified
32982 * by rx_sop_pad_bytes parameter.
32983 * When '0', the received packet will not be padded.
32984 * Note that this flag is only used for Rx rings and is ignored
32985 * for all other rings included Rx Aggregation rings.
32987 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
32990 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
32991 * When rings are allocated, the PCI function on which driver issues
32992 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
32993 * the buffer descriptors (BDs) from those rings is assumed to issue
32994 * packet payload DMA using same PCI function. When proxy mode is
32995 * enabled, hardware can perform payload DMA using another PCI
32996 * function on same or different host.
32997 * When set to '0', the PCI function on which driver issues
32998 * HWRM_RING_CFG command is used for host payload DMA operation.
32999 * When set to '1', the host PCI function specified by proxy_fid is
33000 * used for host payload DMA operation.
33002 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
33005 * Tx ring packet source interface override, for Tx rings only.
33006 * When TX rings are allocated, the PCI function on which driver
33007 * issues HWRM_RING_CFG is assumed to be source interface of
33008 * packets sent from TX ring.
33009 * When set to '1', the host PCI function specified by proxy_fid
33010 * is used as source interface of the transmitted packets.
33012 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
33014 /* The schq_id field is valid */
33015 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
33017 /* Update completion ring ID associated with Tx or Rx ring. */
33018 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
33021 * When set to '1', metadata value provided by tx_metadata
33022 * field in this command is inserted in the lb_header_metadata
33023 * QP context field. When set to '0', no change done to metadata.
33024 * Firmware rejects the tx ring metadata programming with
33025 * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
33026 * metadata feature is not disabled.
33028 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
33031 * Proxy function FID value.
33032 * This value is only used when either proxy_mode_enable flag or
33033 * tx_proxy_svif_override is set to '1'.
33034 * When proxy_mode_enable is set to '1', it identifies a host PCI
33035 * function used for host payload DMA operations.
33036 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
33037 * function as source interface for all transmitted packets from
33040 uint16_t proxy_fid;
33042 * Identifies the new scheduler queue (SCHQ) to associate with the
33043 * ring. Only valid for Tx rings.
33044 * A value of zero indicates that the Tx ring should be associated
33045 * with the default scheduler queue (SCHQ).
33049 * This field is valid for TX or Rx rings. This value identifies the
33050 * new completion ring ID to associate with the TX or Rx ring.
33052 uint16_t cmpl_ring_id;
33054 * Rx SOP padding amount in bytes.
33055 * This value is only used when rx_sop_pad_enable flag is set to '1'.
33057 uint8_t rx_sop_pad_bytes;
33058 uint8_t unused_1[3];
33060 * When tx_metadata enable bit is set, value specified in this field
33061 * is copied to lb_header_metadata in the QP context.
33063 uint32_t tx_metadata;
33064 uint8_t unused_2[4];
33067 /* hwrm_ring_cfg_output (size:128b/16B) */
33068 struct hwrm_ring_cfg_output {
33069 /* The specific error status for the command. */
33070 uint16_t error_code;
33071 /* The HWRM command request type. */
33073 /* The sequence ID from the original command. */
33075 /* The length of the response data in number of bytes. */
33077 uint8_t unused_0[7];
33079 * This field is used in Output records to indicate that the output
33080 * is completely written to RAM. This field should be read as '1'
33081 * to indicate that the output has been completely written.
33082 * When writing a command completion or response to an internal
33083 * processor, the order of writes has to be such that this field is
33089 /******************
33091 ******************/
33094 /* hwrm_ring_qcfg_input (size:192b/24B) */
33095 struct hwrm_ring_qcfg_input {
33096 /* The HWRM command request type. */
33099 * The completion ring to send the completion event on. This should
33100 * be the NQ ID returned from the `nq_alloc` HWRM command.
33102 uint16_t cmpl_ring;
33104 * The sequence ID is used by the driver for tracking multiple
33105 * commands. This ID is treated as opaque data by the firmware and
33106 * the value is returned in the `hwrm_resp_hdr` upon completion.
33110 * The target ID of the command:
33111 * * 0x0-0xFFF8 - The function ID
33112 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33113 * * 0xFFFD - Reserved for user-space HWRM interface
33116 uint16_t target_id;
33118 * A physical address pointer pointing to a host buffer that the
33119 * command's response data will be written. This can be either a host
33120 * physical address (HPA) or a guest physical address (GPA) and must
33121 * point to a physically contiguous block of memory.
33123 uint64_t resp_addr;
33127 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
33129 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
33130 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
33131 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
33132 uint8_t unused_0[5];
33133 /* Physical number of the ring. */
33137 /* hwrm_ring_qcfg_output (size:256b/32B) */
33138 struct hwrm_ring_qcfg_output {
33139 /* The specific error status for the command. */
33140 uint16_t error_code;
33141 /* The HWRM command request type. */
33143 /* The sequence ID from the original command. */
33145 /* The length of the response data in number of bytes. */
33147 /* Ring config enable bits. */
33150 * For Rx rings, the incoming packet data can be placed at either
33151 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
33153 * When '1', the received packet will be padded with 2B, 10B or 12B
33154 * of zeros at the front of the packet. The exact offset is specified
33155 * by rx_sop_pad_bytes parameter.
33156 * When '0', the received packet will not be padded.
33157 * Note that this flag is only used for Rx rings and is ignored
33158 * for all other rings included Rx Aggregation rings.
33160 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
33163 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
33164 * When rings are allocated, the PCI function on which driver issues
33165 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
33166 * the buffer descriptors (BDs) from those rings is assumed to issue
33167 * packet payload DMA using same PCI function. When proxy mode is
33168 * enabled, hardware can perform payload DMA using another PCI
33169 * function on same or different host.
33170 * When set to '0', the PCI function on which driver issues
33171 * HWRM_RING_CFG command is used for host payload DMA operation.
33172 * When set to '1', the host PCI function specified by proxy_fid is
33173 * used for host payload DMA operation.
33175 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
33178 * Tx ring packet source interface override, for Tx rings only.
33179 * When TX rings are allocated, the PCI function on which driver
33180 * issues HWRM_RING_CFG is assumed to be source interface of
33181 * packets sent from TX ring.
33182 * When set to '1', the host PCI function specified by proxy_fid is
33183 * used as source interface of the transmitted packets.
33185 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
33188 * Proxy function FID value.
33189 * This value is only used when either proxy_mode_enable flag or
33190 * tx_proxy_svif_override is set to '1'.
33191 * When proxy_mode_enable is set to '1', it identifies a host PCI
33192 * function used for host payload DMA operations.
33193 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
33194 * function as source interface for all transmitted packets from the TX
33197 uint16_t proxy_fid;
33199 * Identifies the new scheduler queue (SCHQ) to associate with the
33200 * ring. Only valid for Tx rings.
33201 * A value of zero indicates that the Tx ring should be associated with
33202 * the default scheduler queue (SCHQ).
33206 * This field is used when ring_type is a TX or Rx ring.
33207 * This value indicates what completion ring the TX or Rx ring
33208 * is associated with.
33210 uint16_t cmpl_ring_id;
33212 * Rx SOP padding amount in bytes.
33213 * This value is only used when rx_sop_pad_enable flag is set to '1'.
33215 uint8_t rx_sop_pad_bytes;
33216 uint8_t unused_0[3];
33217 /* lb_header_metadata in the QP context is copied to this field. */
33218 uint32_t tx_metadata;
33219 uint8_t unused_1[7];
33221 * This field is used in Output records to indicate that the output
33222 * is completely written to RAM. This field should be read as '1'
33223 * to indicate that the output has been completely written.
33224 * When writing a command completion or response to an internal
33225 * processor, the order of writes has to be such that this field is
33231 /**************************
33232 * hwrm_ring_aggint_qcaps *
33233 **************************/
33236 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
33237 struct hwrm_ring_aggint_qcaps_input {
33238 /* The HWRM command request type. */
33241 * The completion ring to send the completion event on. This should
33242 * be the NQ ID returned from the `nq_alloc` HWRM command.
33244 uint16_t cmpl_ring;
33246 * The sequence ID is used by the driver for tracking multiple
33247 * commands. This ID is treated as opaque data by the firmware and
33248 * the value is returned in the `hwrm_resp_hdr` upon completion.
33252 * The target ID of the command:
33253 * * 0x0-0xFFF8 - The function ID
33254 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33255 * * 0xFFFD - Reserved for user-space HWRM interface
33258 uint16_t target_id;
33260 * A physical address pointer pointing to a host buffer that the
33261 * command's response data will be written. This can be either a host
33262 * physical address (HPA) or a guest physical address (GPA) and must
33263 * point to a physically contiguous block of memory.
33265 uint64_t resp_addr;
33268 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
33269 struct hwrm_ring_aggint_qcaps_output {
33270 /* The specific error status for the command. */
33271 uint16_t error_code;
33272 /* The HWRM command request type. */
33274 /* The sequence ID from the original command. */
33276 /* The length of the response data in number of bytes. */
33278 uint32_t cmpl_params;
33280 * When this bit is set to '1', int_lat_tmr_min can be configured
33281 * on completion rings.
33283 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
33286 * When this bit is set to '1', int_lat_tmr_max can be configured
33287 * on completion rings.
33289 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
33292 * When this bit is set to '1', timer_reset can be enabled
33293 * on completion rings.
33295 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
33298 * When this bit is set to '1', ring_idle can be enabled
33299 * on completion rings.
33301 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
33304 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
33305 * on completion rings.
33307 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
33310 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
33311 * on completion rings.
33313 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
33316 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
33317 * on completion rings.
33319 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
33322 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
33323 * on completion rings.
33325 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
33328 * When this bit is set to '1', num_cmpl_aggr_int can be configured
33329 * on completion rings.
33331 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
33333 uint32_t nq_params;
33335 * When this bit is set to '1', int_lat_tmr_min can be configured
33336 * on notification queues.
33338 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
33340 /* Minimum value for num_cmpl_dma_aggr */
33341 uint16_t num_cmpl_dma_aggr_min;
33342 /* Maximum value for num_cmpl_dma_aggr */
33343 uint16_t num_cmpl_dma_aggr_max;
33344 /* Minimum value for num_cmpl_dma_aggr_during_int */
33345 uint16_t num_cmpl_dma_aggr_during_int_min;
33346 /* Maximum value for num_cmpl_dma_aggr_during_int */
33347 uint16_t num_cmpl_dma_aggr_during_int_max;
33348 /* Minimum value for cmpl_aggr_dma_tmr */
33349 uint16_t cmpl_aggr_dma_tmr_min;
33350 /* Maximum value for cmpl_aggr_dma_tmr */
33351 uint16_t cmpl_aggr_dma_tmr_max;
33352 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
33353 uint16_t cmpl_aggr_dma_tmr_during_int_min;
33354 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
33355 uint16_t cmpl_aggr_dma_tmr_during_int_max;
33356 /* Minimum value for int_lat_tmr_min */
33357 uint16_t int_lat_tmr_min_min;
33358 /* Maximum value for int_lat_tmr_min */
33359 uint16_t int_lat_tmr_min_max;
33360 /* Minimum value for int_lat_tmr_max */
33361 uint16_t int_lat_tmr_max_min;
33362 /* Maximum value for int_lat_tmr_max */
33363 uint16_t int_lat_tmr_max_max;
33364 /* Minimum value for num_cmpl_aggr_int */
33365 uint16_t num_cmpl_aggr_int_min;
33366 /* Maximum value for num_cmpl_aggr_int */
33367 uint16_t num_cmpl_aggr_int_max;
33368 /* The units for timer parameters, in nanoseconds. */
33369 uint16_t timer_units;
33370 uint8_t unused_0[1];
33372 * This field is used in Output records to indicate that the output
33373 * is completely written to RAM. This field should be read as '1'
33374 * to indicate that the output has been completely written.
33375 * When writing a command completion or response to an internal processor,
33376 * the order of writes has to be such that this field is written last.
33381 /**************************************
33382 * hwrm_ring_cmpl_ring_qaggint_params *
33383 **************************************/
33386 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
33387 struct hwrm_ring_cmpl_ring_qaggint_params_input {
33388 /* The HWRM command request type. */
33391 * The completion ring to send the completion event on. This should
33392 * be the NQ ID returned from the `nq_alloc` HWRM command.
33394 uint16_t cmpl_ring;
33396 * The sequence ID is used by the driver for tracking multiple
33397 * commands. This ID is treated as opaque data by the firmware and
33398 * the value is returned in the `hwrm_resp_hdr` upon completion.
33402 * The target ID of the command:
33403 * * 0x0-0xFFF8 - The function ID
33404 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33405 * * 0xFFFD - Reserved for user-space HWRM interface
33408 uint16_t target_id;
33410 * A physical address pointer pointing to a host buffer that the
33411 * command's response data will be written. This can be either a host
33412 * physical address (HPA) or a guest physical address (GPA) and must
33413 * point to a physically contiguous block of memory.
33415 uint64_t resp_addr;
33416 /* Physical number of completion ring. */
33419 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
33421 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
33423 * Set this flag to 1 when querying parameters on a notification
33424 * queue. Set this flag to 0 when querying parameters on a
33425 * completion queue or completion ring.
33427 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
33429 uint8_t unused_0[4];
33432 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
33433 struct hwrm_ring_cmpl_ring_qaggint_params_output {
33434 /* The specific error status for the command. */
33435 uint16_t error_code;
33436 /* The HWRM command request type. */
33438 /* The sequence ID from the original command. */
33440 /* The length of the response data in number of bytes. */
33444 * When this bit is set to '1', interrupt max
33445 * timer is reset whenever a completion is received.
33447 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
33450 * When this bit is set to '1', ring idle mode
33451 * aggregation will be enabled.
33453 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
33456 * Number of completions to aggregate before DMA
33457 * during the normal mode.
33459 uint16_t num_cmpl_dma_aggr;
33461 * Number of completions to aggregate before DMA
33462 * during the interrupt mode.
33464 uint16_t num_cmpl_dma_aggr_during_int;
33466 * Timer used to aggregate completions before
33467 * DMA during the normal mode (not in interrupt mode).
33469 uint16_t cmpl_aggr_dma_tmr;
33471 * Timer used to aggregate completions before
33472 * DMA when in interrupt mode.
33474 uint16_t cmpl_aggr_dma_tmr_during_int;
33475 /* Minimum time between two interrupts. */
33476 uint16_t int_lat_tmr_min;
33478 * Maximum wait time spent aggregating
33479 * completions before signaling the interrupt after the
33480 * interrupt is enabled.
33482 uint16_t int_lat_tmr_max;
33484 * Minimum number of completions aggregated before signaling
33487 uint16_t num_cmpl_aggr_int;
33488 uint8_t unused_0[7];
33490 * This field is used in Output records to indicate that the output
33491 * is completely written to RAM. This field should be read as '1'
33492 * to indicate that the output has been completely written.
33493 * When writing a command completion or response to an internal processor,
33494 * the order of writes has to be such that this field is written last.
33499 /*****************************************
33500 * hwrm_ring_cmpl_ring_cfg_aggint_params *
33501 *****************************************/
33504 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
33505 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
33506 /* The HWRM command request type. */
33509 * The completion ring to send the completion event on. This should
33510 * be the NQ ID returned from the `nq_alloc` HWRM command.
33512 uint16_t cmpl_ring;
33514 * The sequence ID is used by the driver for tracking multiple
33515 * commands. This ID is treated as opaque data by the firmware and
33516 * the value is returned in the `hwrm_resp_hdr` upon completion.
33520 * The target ID of the command:
33521 * * 0x0-0xFFF8 - The function ID
33522 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33523 * * 0xFFFD - Reserved for user-space HWRM interface
33526 uint16_t target_id;
33528 * A physical address pointer pointing to a host buffer that the
33529 * command's response data will be written. This can be either a host
33530 * physical address (HPA) or a guest physical address (GPA) and must
33531 * point to a physically contiguous block of memory.
33533 uint64_t resp_addr;
33534 /* Physical number of completion ring. */
33538 * When this bit is set to '1', interrupt latency max
33539 * timer is reset whenever a completion is received.
33541 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
33544 * When this bit is set to '1', ring idle mode
33545 * aggregation will be enabled.
33547 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
33550 * Set this flag to 1 when configuring parameters on a
33551 * notification queue. Set this flag to 0 when configuring
33552 * parameters on a completion queue or completion ring.
33554 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
33557 * Number of completions to aggregate before DMA
33558 * during the normal mode.
33560 uint16_t num_cmpl_dma_aggr;
33562 * Number of completions to aggregate before DMA
33563 * during the interrupt mode.
33565 uint16_t num_cmpl_dma_aggr_during_int;
33567 * Timer used to aggregate completions before
33568 * DMA during the normal mode (not in interrupt mode).
33570 uint16_t cmpl_aggr_dma_tmr;
33572 * Timer used to aggregate completions before
33573 * DMA while in interrupt mode.
33575 uint16_t cmpl_aggr_dma_tmr_during_int;
33576 /* Minimum time between two interrupts. */
33577 uint16_t int_lat_tmr_min;
33579 * Maximum wait time spent aggregating
33580 * completions before signaling the interrupt after the
33581 * interrupt is enabled.
33583 uint16_t int_lat_tmr_max;
33585 * Minimum number of completions aggregated before signaling
33588 uint16_t num_cmpl_aggr_int;
33590 * Bitfield that indicates which parameters are to be applied. Only
33591 * required when configuring devices with notification queues, and
33592 * used in that case to set certain parameters on completion queues
33593 * and others on notification queues.
33597 * This bit must be '1' for the num_cmpl_dma_aggr field to be
33600 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
33603 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
33606 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
33609 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
33612 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
33615 * This bit must be '1' for the int_lat_tmr_min field to be
33618 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
33621 * This bit must be '1' for the int_lat_tmr_max field to be
33624 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
33627 * This bit must be '1' for the num_cmpl_aggr_int field to be
33630 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
33632 uint8_t unused_0[4];
33635 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
33636 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
33637 /* The specific error status for the command. */
33638 uint16_t error_code;
33639 /* The HWRM command request type. */
33641 /* The sequence ID from the original command. */
33643 /* The length of the response data in number of bytes. */
33645 uint8_t unused_0[7];
33647 * This field is used in Output records to indicate that the output
33648 * is completely written to RAM. This field should be read as '1'
33649 * to indicate that the output has been completely written.
33650 * When writing a command completion or response to an internal processor,
33651 * the order of writes has to be such that this field is written last.
33656 /***********************
33657 * hwrm_ring_grp_alloc *
33658 ***********************/
33661 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
33662 struct hwrm_ring_grp_alloc_input {
33663 /* The HWRM command request type. */
33666 * The completion ring to send the completion event on. This should
33667 * be the NQ ID returned from the `nq_alloc` HWRM command.
33669 uint16_t cmpl_ring;
33671 * The sequence ID is used by the driver for tracking multiple
33672 * commands. This ID is treated as opaque data by the firmware and
33673 * the value is returned in the `hwrm_resp_hdr` upon completion.
33677 * The target ID of the command:
33678 * * 0x0-0xFFF8 - The function ID
33679 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33680 * * 0xFFFD - Reserved for user-space HWRM interface
33683 uint16_t target_id;
33685 * A physical address pointer pointing to a host buffer that the
33686 * command's response data will be written. This can be either a host
33687 * physical address (HPA) or a guest physical address (GPA) and must
33688 * point to a physically contiguous block of memory.
33690 uint64_t resp_addr;
33692 * This value identifies the CR associated with the ring
33697 * This value identifies the main RR associated with the ring
33702 * This value identifies the aggregation RR associated with
33703 * the ring group. If this value is 0xFF... (All Fs), then no
33704 * Aggregation ring will be set.
33708 * This value identifies the statistics context associated
33709 * with the ring group.
33714 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
33715 struct hwrm_ring_grp_alloc_output {
33716 /* The specific error status for the command. */
33717 uint16_t error_code;
33718 /* The HWRM command request type. */
33720 /* The sequence ID from the original command. */
33722 /* The length of the response data in number of bytes. */
33725 * This is the ring group ID value. Use this value to program
33726 * the default ring group for the VNIC or as table entries
33727 * in an RSS/COS context.
33729 uint32_t ring_group_id;
33730 uint8_t unused_0[3];
33732 * This field is used in Output records to indicate that the output
33733 * is completely written to RAM. This field should be read as '1'
33734 * to indicate that the output has been completely written.
33735 * When writing a command completion or response to an internal processor,
33736 * the order of writes has to be such that this field is written last.
33741 /**********************
33742 * hwrm_ring_grp_free *
33743 **********************/
33746 /* hwrm_ring_grp_free_input (size:192b/24B) */
33747 struct hwrm_ring_grp_free_input {
33748 /* The HWRM command request type. */
33751 * The completion ring to send the completion event on. This should
33752 * be the NQ ID returned from the `nq_alloc` HWRM command.
33754 uint16_t cmpl_ring;
33756 * The sequence ID is used by the driver for tracking multiple
33757 * commands. This ID is treated as opaque data by the firmware and
33758 * the value is returned in the `hwrm_resp_hdr` upon completion.
33762 * The target ID of the command:
33763 * * 0x0-0xFFF8 - The function ID
33764 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33765 * * 0xFFFD - Reserved for user-space HWRM interface
33768 uint16_t target_id;
33770 * A physical address pointer pointing to a host buffer that the
33771 * command's response data will be written. This can be either a host
33772 * physical address (HPA) or a guest physical address (GPA) and must
33773 * point to a physically contiguous block of memory.
33775 uint64_t resp_addr;
33776 /* This is the ring group ID value. */
33777 uint32_t ring_group_id;
33778 uint8_t unused_0[4];
33781 /* hwrm_ring_grp_free_output (size:128b/16B) */
33782 struct hwrm_ring_grp_free_output {
33783 /* The specific error status for the command. */
33784 uint16_t error_code;
33785 /* The HWRM command request type. */
33787 /* The sequence ID from the original command. */
33789 /* The length of the response data in number of bytes. */
33791 uint8_t unused_0[7];
33793 * This field is used in Output records to indicate that the output
33794 * is completely written to RAM. This field should be read as '1'
33795 * to indicate that the output has been completely written.
33796 * When writing a command completion or response to an internal processor,
33797 * the order of writes has to be such that this field is written last.
33802 /************************
33803 * hwrm_ring_schq_alloc *
33804 ************************/
33807 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
33808 struct hwrm_ring_schq_alloc_input {
33809 /* The HWRM command request type. */
33812 * The completion ring to send the completion event on. This should
33813 * be the NQ ID returned from the `nq_alloc` HWRM command.
33815 uint16_t cmpl_ring;
33817 * The sequence ID is used by the driver for tracking multiple
33818 * commands. This ID is treated as opaque data by the firmware and
33819 * the value is returned in the `hwrm_resp_hdr` upon completion.
33823 * The target ID of the command:
33824 * * 0x0-0xFFF8 - The function ID
33825 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33826 * * 0xFFFD - Reserved for user-space HWRM interface
33829 uint16_t target_id;
33831 * A physical address pointer pointing to a host buffer that the
33832 * command's response data will be written. This can be either a host
33833 * physical address (HPA) or a guest physical address (GPA) and must
33834 * point to a physically contiguous block of memory.
33836 uint64_t resp_addr;
33839 * This bit must be '1' for the tqm_ring0 fields to be
33842 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
33844 * This bit must be '1' for the tqm_ring1 fields to be
33847 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
33849 * This bit must be '1' for the tqm_ring2 fields to be
33852 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
33854 * This bit must be '1' for the tqm_ring3 fields to be
33857 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
33859 * This bit must be '1' for the tqm_ring4 fields to be
33862 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
33864 * This bit must be '1' for the tqm_ring5 fields to be
33867 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
33869 * This bit must be '1' for the tqm_ring6 fields to be
33872 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
33874 * This bit must be '1' for the tqm_ring7 fields to be
33877 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
33878 /* Reserved for future use. */
33880 /* TQM ring 0 page size and level. */
33881 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
33882 /* TQM ring 0 PBL indirect levels. */
33883 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
33885 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
33886 /* PBL pointer is physical start address. */
33887 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
33889 /* PBL pointer points to PTE table. */
33890 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
33893 * PBL pointer points to PDE table with each entry pointing to PTE
33896 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
33898 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
33899 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
33900 /* TQM ring 0 page size. */
33901 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
33903 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
33905 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
33906 (UINT32_C(0x0) << 4)
33908 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
33909 (UINT32_C(0x1) << 4)
33911 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
33912 (UINT32_C(0x2) << 4)
33914 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
33915 (UINT32_C(0x3) << 4)
33917 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
33918 (UINT32_C(0x4) << 4)
33920 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
33921 (UINT32_C(0x5) << 4)
33922 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
33923 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
33924 /* TQM ring 1 page size and level. */
33925 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
33926 /* TQM ring 1 PBL indirect levels. */
33927 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
33929 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
33930 /* PBL pointer is physical start address. */
33931 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
33933 /* PBL pointer points to PTE table. */
33934 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
33937 * PBL pointer points to PDE table with each entry pointing to PTE
33940 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
33942 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
33943 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
33944 /* TQM ring 1 page size. */
33945 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
33947 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
33949 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
33950 (UINT32_C(0x0) << 4)
33952 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
33953 (UINT32_C(0x1) << 4)
33955 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
33956 (UINT32_C(0x2) << 4)
33958 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
33959 (UINT32_C(0x3) << 4)
33961 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
33962 (UINT32_C(0x4) << 4)
33964 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
33965 (UINT32_C(0x5) << 4)
33966 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
33967 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
33968 /* TQM ring 2 page size and level. */
33969 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
33970 /* TQM ring 2 PBL indirect levels. */
33971 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
33973 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
33974 /* PBL pointer is physical start address. */
33975 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
33977 /* PBL pointer points to PTE table. */
33978 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
33981 * PBL pointer points to PDE table with each entry pointing to PTE
33984 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
33986 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
33987 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
33988 /* TQM ring 2 page size. */
33989 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
33991 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
33993 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
33994 (UINT32_C(0x0) << 4)
33996 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
33997 (UINT32_C(0x1) << 4)
33999 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
34000 (UINT32_C(0x2) << 4)
34002 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
34003 (UINT32_C(0x3) << 4)
34005 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
34006 (UINT32_C(0x4) << 4)
34008 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
34009 (UINT32_C(0x5) << 4)
34010 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
34011 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
34012 /* TQM ring 3 page size and level. */
34013 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
34014 /* TQM ring 3 PBL indirect levels. */
34015 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
34017 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
34018 /* PBL pointer is physical start address. */
34019 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
34021 /* PBL pointer points to PTE table. */
34022 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
34025 * PBL pointer points to PDE table with each entry pointing to PTE
34028 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
34030 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
34031 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
34032 /* TQM ring 3 page size. */
34033 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
34035 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
34037 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
34038 (UINT32_C(0x0) << 4)
34040 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
34041 (UINT32_C(0x1) << 4)
34043 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
34044 (UINT32_C(0x2) << 4)
34046 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
34047 (UINT32_C(0x3) << 4)
34049 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
34050 (UINT32_C(0x4) << 4)
34052 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
34053 (UINT32_C(0x5) << 4)
34054 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
34055 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
34056 /* TQM ring 4 page size and level. */
34057 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
34058 /* TQM ring 4 PBL indirect levels. */
34059 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
34061 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
34062 /* PBL pointer is physical start address. */
34063 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
34065 /* PBL pointer points to PTE table. */
34066 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
34069 * PBL pointer points to PDE table with each entry pointing to PTE
34072 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
34074 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
34075 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
34076 /* TQM ring 4 page size. */
34077 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
34079 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
34081 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
34082 (UINT32_C(0x0) << 4)
34084 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
34085 (UINT32_C(0x1) << 4)
34087 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
34088 (UINT32_C(0x2) << 4)
34090 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
34091 (UINT32_C(0x3) << 4)
34093 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
34094 (UINT32_C(0x4) << 4)
34096 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
34097 (UINT32_C(0x5) << 4)
34098 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
34099 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
34100 /* TQM ring 5 page size and level. */
34101 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
34102 /* TQM ring 5 PBL indirect levels. */
34103 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
34105 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
34106 /* PBL pointer is physical start address. */
34107 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
34109 /* PBL pointer points to PTE table. */
34110 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
34113 * PBL pointer points to PDE table with each entry pointing to PTE
34116 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
34118 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
34119 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
34120 /* TQM ring 5 page size. */
34121 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
34123 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
34125 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
34126 (UINT32_C(0x0) << 4)
34128 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
34129 (UINT32_C(0x1) << 4)
34131 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
34132 (UINT32_C(0x2) << 4)
34134 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
34135 (UINT32_C(0x3) << 4)
34137 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
34138 (UINT32_C(0x4) << 4)
34140 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
34141 (UINT32_C(0x5) << 4)
34142 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
34143 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
34144 /* TQM ring 6 page size and level. */
34145 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
34146 /* TQM ring 6 PBL indirect levels. */
34147 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
34149 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
34150 /* PBL pointer is physical start address. */
34151 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
34153 /* PBL pointer points to PTE table. */
34154 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
34157 * PBL pointer points to PDE table with each entry pointing to PTE
34160 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
34162 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
34163 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
34164 /* TQM ring 6 page size. */
34165 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
34167 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
34169 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
34170 (UINT32_C(0x0) << 4)
34172 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
34173 (UINT32_C(0x1) << 4)
34175 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
34176 (UINT32_C(0x2) << 4)
34178 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
34179 (UINT32_C(0x3) << 4)
34181 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
34182 (UINT32_C(0x4) << 4)
34184 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
34185 (UINT32_C(0x5) << 4)
34186 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
34187 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
34188 /* TQM ring 7 page size and level. */
34189 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
34190 /* TQM ring 7 PBL indirect levels. */
34191 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
34193 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
34194 /* PBL pointer is physical start address. */
34195 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
34197 /* PBL pointer points to PTE table. */
34198 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
34201 * PBL pointer points to PDE table with each entry pointing to PTE
34204 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
34206 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
34207 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
34208 /* TQM ring 7 page size. */
34209 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
34211 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
34213 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
34214 (UINT32_C(0x0) << 4)
34216 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
34217 (UINT32_C(0x1) << 4)
34219 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
34220 (UINT32_C(0x2) << 4)
34222 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
34223 (UINT32_C(0x3) << 4)
34225 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
34226 (UINT32_C(0x4) << 4)
34228 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
34229 (UINT32_C(0x5) << 4)
34230 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
34231 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
34232 /* TQM ring 0 page directory. */
34233 uint64_t tqm_ring0_page_dir;
34234 /* TQM ring 1 page directory. */
34235 uint64_t tqm_ring1_page_dir;
34236 /* TQM ring 2 page directory. */
34237 uint64_t tqm_ring2_page_dir;
34238 /* TQM ring 3 page directory. */
34239 uint64_t tqm_ring3_page_dir;
34240 /* TQM ring 4 page directory. */
34241 uint64_t tqm_ring4_page_dir;
34242 /* TQM ring 5 page directory. */
34243 uint64_t tqm_ring5_page_dir;
34244 /* TQM ring 6 page directory. */
34245 uint64_t tqm_ring6_page_dir;
34246 /* TQM ring 7 page directory. */
34247 uint64_t tqm_ring7_page_dir;
34249 * Number of TQM ring 0 entries.
34251 * TQM fastpath rings should be sized large enough to accommodate the
34252 * maximum number of QPs (either L2 or RoCE, or both if shared)
34253 * that can be enqueued to the TQM ring.
34255 * Note that TQM ring sizes cannot be extended while the system is
34256 * operational. If a PF driver needs to extend a TQM ring, it needs
34257 * to delete the SCHQ and then reallocate it.
34259 uint32_t tqm_ring0_num_entries;
34261 * Number of TQM ring 1 entries.
34263 * TQM fastpath rings should be sized large enough to accommodate the
34264 * maximum number of QPs (either L2 or RoCE, or both if shared)
34265 * that can be enqueued to the TQM ring.
34267 * Note that TQM ring sizes cannot be extended while the system is
34268 * operational. If a PF driver needs to extend a TQM ring, it needs
34269 * to delete the SCHQ and then reallocate it.
34271 uint32_t tqm_ring1_num_entries;
34273 * Number of TQM ring 2 entries.
34275 * TQM fastpath rings should be sized large enough to accommodate the
34276 * maximum number of QPs (either L2 or RoCE, or both if shared)
34277 * that can be enqueued to the TQM ring.
34279 * Note that TQM ring sizes cannot be extended while the system is
34280 * operational. If a PF driver needs to extend a TQM ring, it needs
34281 * to delete the SCHQ and then reallocate it.
34283 uint32_t tqm_ring2_num_entries;
34285 * Number of TQM ring 3 entries.
34287 * TQM fastpath rings should be sized large enough to accommodate the
34288 * maximum number of QPs (either L2 or RoCE, or both if shared)
34289 * that can be enqueued to the TQM ring.
34291 * Note that TQM ring sizes cannot be extended while the system is
34292 * operational. If a PF driver needs to extend a TQM ring, it needs
34293 * to delete the SCHQ and then reallocate it.
34295 uint32_t tqm_ring3_num_entries;
34297 * Number of TQM ring 4 entries.
34299 * TQM fastpath rings should be sized large enough to accommodate the
34300 * maximum number of QPs (either L2 or RoCE, or both if shared)
34301 * that can be enqueued to the TQM ring.
34303 * Note that TQM ring sizes cannot be extended while the system is
34304 * operational. If a PF driver needs to extend a TQM ring, it needs
34305 * to delete the SCHQ and then reallocate it.
34307 uint32_t tqm_ring4_num_entries;
34309 * Number of TQM ring 5 entries.
34311 * TQM fastpath rings should be sized large enough to accommodate the
34312 * maximum number of QPs (either L2 or RoCE, or both if shared)
34313 * that can be enqueued to the TQM ring.
34315 * Note that TQM ring sizes cannot be extended while the system is
34316 * operational. If a PF driver needs to extend a TQM ring, it needs
34317 * to delete the SCHQ and then reallocate it.
34319 uint32_t tqm_ring5_num_entries;
34321 * Number of TQM ring 6 entries.
34323 * TQM fastpath rings should be sized large enough to accommodate the
34324 * maximum number of QPs (either L2 or RoCE, or both if shared)
34325 * that can be enqueued to the TQM ring.
34327 * Note that TQM ring sizes cannot be extended while the system is
34328 * operational. If a PF driver needs to extend a TQM ring, it needs
34329 * to delete the SCHQ and then reallocate it.
34331 uint32_t tqm_ring6_num_entries;
34333 * Number of TQM ring 7 entries.
34335 * TQM fastpath rings should be sized large enough to accommodate the
34336 * maximum number of QPs (either L2 or RoCE, or both if shared)
34337 * that can be enqueued to the TQM ring.
34339 * Note that TQM ring sizes cannot be extended while the system is
34340 * operational. If a PF driver needs to extend a TQM ring, it needs
34341 * to delete the SCHQ and then reallocate it.
34343 uint32_t tqm_ring7_num_entries;
34344 /* Number of bytes that have been allocated for each context entry. */
34345 uint16_t tqm_entry_size;
34346 uint8_t unused_0[6];
34349 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
34350 struct hwrm_ring_schq_alloc_output {
34351 /* The specific error status for the command. */
34352 uint16_t error_code;
34353 /* The HWRM command request type. */
34355 /* The sequence ID from the original command. */
34357 /* The length of the response data in number of bytes. */
34360 * This is an identifier for the SCHQ to be used in other HWRM commands
34361 * that need to reference this SCHQ. This value is greater than zero
34362 * (i.e. a schq_id of zero references the default SCHQ).
34365 uint8_t unused_0[5];
34367 * This field is used in Output records to indicate that the output
34368 * is completely written to RAM. This field should be read as '1'
34369 * to indicate that the output has been completely written.
34370 * When writing a command completion or response to an internal processor,
34371 * the order of writes has to be such that this field is written last.
34376 /**********************
34377 * hwrm_ring_schq_cfg *
34378 **********************/
34381 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
34382 struct hwrm_ring_schq_cfg_input {
34383 /* The HWRM command request type. */
34386 * The completion ring to send the completion event on. This should
34387 * be the NQ ID returned from the `nq_alloc` HWRM command.
34389 uint16_t cmpl_ring;
34391 * The sequence ID is used by the driver for tracking multiple
34392 * commands. This ID is treated as opaque data by the firmware and
34393 * the value is returned in the `hwrm_resp_hdr` upon completion.
34397 * The target ID of the command:
34398 * * 0x0-0xFFF8 - The function ID
34399 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34400 * * 0xFFFD - Reserved for user-space HWRM interface
34403 uint16_t target_id;
34405 * A physical address pointer pointing to a host buffer that the
34406 * command's response data will be written. This can be either a host
34407 * physical address (HPA) or a guest physical address (GPA) and must
34408 * point to a physically contiguous block of memory.
34410 uint64_t resp_addr;
34412 * Identifies the SCHQ being configured. A schq_id of zero refers to
34413 * the default SCHQ.
34417 * This field is an 8 bit bitmap that indicates which TCs are enabled
34418 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
34421 uint8_t tc_enabled;
34424 /* The tc_max_bw array and the max_bw parameters are valid */
34425 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
34427 /* The tc_min_bw array is valid */
34428 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
34430 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34431 uint32_t max_bw_tc0;
34432 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34433 uint32_t max_bw_tc1;
34434 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34435 uint32_t max_bw_tc2;
34436 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34437 uint32_t max_bw_tc3;
34438 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34439 uint32_t max_bw_tc4;
34440 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34441 uint32_t max_bw_tc5;
34442 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34443 uint32_t max_bw_tc6;
34444 /* Maximum bandwidth of the traffic class, specified in Mbps. */
34445 uint32_t max_bw_tc7;
34447 * Bandwidth reservation for the traffic class, specified in Mbps.
34448 * A value of zero signifies that traffic belonging to this class
34449 * shares the bandwidth reservation for the same traffic class of
34450 * the default SCHQ.
34452 uint32_t min_bw_tc0;
34454 * Bandwidth reservation for the traffic class, specified in Mbps.
34455 * A value of zero signifies that traffic belonging to this class
34456 * shares the bandwidth reservation for the same traffic class of
34457 * the default SCHQ.
34459 uint32_t min_bw_tc1;
34461 * Bandwidth reservation for the traffic class, specified in Mbps.
34462 * A value of zero signifies that traffic belonging to this class
34463 * shares the bandwidth reservation for the same traffic class of
34464 * the default SCHQ.
34466 uint32_t min_bw_tc2;
34468 * Bandwidth reservation for the traffic class, specified in Mbps.
34469 * A value of zero signifies that traffic belonging to this class
34470 * shares the bandwidth reservation for the same traffic class of
34471 * the default SCHQ.
34473 uint32_t min_bw_tc3;
34475 * Bandwidth reservation for the traffic class, specified in Mbps.
34476 * A value of zero signifies that traffic belonging to this class
34477 * shares the bandwidth reservation for the same traffic class of
34478 * the default SCHQ.
34480 uint32_t min_bw_tc4;
34482 * Bandwidth reservation for the traffic class, specified in Mbps.
34483 * A value of zero signifies that traffic belonging to this class
34484 * shares the bandwidth reservation for the same traffic class of
34485 * the default SCHQ.
34487 uint32_t min_bw_tc5;
34489 * Bandwidth reservation for the traffic class, specified in Mbps.
34490 * A value of zero signifies that traffic belonging to this class
34491 * shares the bandwidth reservation for the same traffic class of
34492 * the default SCHQ.
34494 uint32_t min_bw_tc6;
34496 * Bandwidth reservation for the traffic class, specified in Mbps.
34497 * A value of zero signifies that traffic belonging to this class
34498 * shares the bandwidth reservation for the same traffic class of
34499 * the default SCHQ.
34501 uint32_t min_bw_tc7;
34503 * Indicates the max bandwidth for all enabled traffic classes in
34504 * this SCHQ, specified in Mbps.
34507 uint8_t unused_1[4];
34510 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
34511 struct hwrm_ring_schq_cfg_output {
34512 /* The specific error status for the command. */
34513 uint16_t error_code;
34514 /* The HWRM command request type. */
34516 /* The sequence ID from the original command. */
34518 /* The length of the response data in number of bytes. */
34520 uint8_t unused_0[7];
34522 * This field is used in Output records to indicate that the output
34523 * is completely written to RAM. This field should be read as '1'
34524 * to indicate that the output has been completely written.
34525 * When writing a command completion or response to an internal processor,
34526 * the order of writes has to be such that this field is written last.
34531 /***********************
34532 * hwrm_ring_schq_free *
34533 ***********************/
34536 /* hwrm_ring_schq_free_input (size:192b/24B) */
34537 struct hwrm_ring_schq_free_input {
34538 /* The HWRM command request type. */
34541 * The completion ring to send the completion event on. This should
34542 * be the NQ ID returned from the `nq_alloc` HWRM command.
34544 uint16_t cmpl_ring;
34546 * The sequence ID is used by the driver for tracking multiple
34547 * commands. This ID is treated as opaque data by the firmware and
34548 * the value is returned in the `hwrm_resp_hdr` upon completion.
34552 * The target ID of the command:
34553 * * 0x0-0xFFF8 - The function ID
34554 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34555 * * 0xFFFD - Reserved for user-space HWRM interface
34558 uint16_t target_id;
34560 * A physical address pointer pointing to a host buffer that the
34561 * command's response data will be written. This can be either a host
34562 * physical address (HPA) or a guest physical address (GPA) and must
34563 * point to a physically contiguous block of memory.
34565 uint64_t resp_addr;
34566 /* Identifies the SCHQ being freed. */
34568 uint8_t unused_0[6];
34571 /* hwrm_ring_schq_free_output (size:128b/16B) */
34572 struct hwrm_ring_schq_free_output {
34573 /* The specific error status for the command. */
34574 uint16_t error_code;
34575 /* The HWRM command request type. */
34577 /* The sequence ID from the original command. */
34579 /* The length of the response data in number of bytes. */
34581 uint8_t unused_0[7];
34583 * This field is used in Output records to indicate that the output
34584 * is completely written to RAM. This field should be read as '1'
34585 * to indicate that the output has been completely written.
34586 * When writing a command completion or response to an internal processor,
34587 * the order of writes has to be such that this field is written last.
34592 * special reserved flow ID to identify per function default
34593 * flows for vSwitch offload
34595 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
34597 * special reserved flow ID to identify per function RoCEv1
34600 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
34602 * special reserved flow ID to identify per function RoCEv2
34605 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
34607 * special reserved flow ID to identify per function RoCEv2
34610 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
34612 /****************************
34613 * hwrm_cfa_l2_filter_alloc *
34614 ****************************/
34617 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
34618 struct hwrm_cfa_l2_filter_alloc_input {
34619 /* The HWRM command request type. */
34622 * The completion ring to send the completion event on. This should
34623 * be the NQ ID returned from the `nq_alloc` HWRM command.
34625 uint16_t cmpl_ring;
34627 * The sequence ID is used by the driver for tracking multiple
34628 * commands. This ID is treated as opaque data by the firmware and
34629 * the value is returned in the `hwrm_resp_hdr` upon completion.
34633 * The target ID of the command:
34634 * * 0x0-0xFFF8 - The function ID
34635 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34636 * * 0xFFFD - Reserved for user-space HWRM interface
34639 uint16_t target_id;
34641 * A physical address pointer pointing to a host buffer that the
34642 * command's response data will be written. This can be either a host
34643 * physical address (HPA) or a guest physical address (GPA) and must
34644 * point to a physically contiguous block of memory.
34646 uint64_t resp_addr;
34649 * Enumeration denoting the RX, TX type of the resource.
34650 * This enumeration is used for resources that are similar for both
34651 * TX and RX paths of the chip.
34653 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
34656 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
34659 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
34661 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
34662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
34664 * Setting of this flag indicates the applicability to the loopback
34667 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
34670 * Setting of this flag indicates drop action. If this flag is not
34671 * set, then it should be considered accept action.
34673 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
34676 * If this flag is set, all t_l2_* fields are invalid
34677 * and they should not be specified.
34678 * If this flag is set, then l2_* fields refer to
34679 * fields of outermost L2 header.
34681 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
34684 * Enumeration denoting NO_ROCE_L2 to support old drivers.
34685 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
34687 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
34689 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
34690 /* To support old drivers */
34691 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
34692 (UINT32_C(0x0) << 4)
34693 /* Only L2 traffic */
34694 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
34695 (UINT32_C(0x1) << 4)
34696 /* Roce & L2 traffic */
34697 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
34698 (UINT32_C(0x2) << 4)
34699 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
34700 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
34702 * Setting of this flag indicates that no XDP filter is created with
34704 * 0 - legacy behavior, XDP filter is created with L2 filter
34705 * 1 - XDP filter won't be created with L2 filter
34707 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
34710 * Setting this flag to 1 indicate the L2 fields in this command
34711 * pertain to source fields. Setting this flag to 0 indicate the
34712 * L2 fields in this command pertain to the destination fields
34713 * and this is the default/legacy behavior.
34715 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
34719 * This bit must be '1' for the l2_addr field to be
34722 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
34725 * This bit must be '1' for the l2_addr_mask field to be
34728 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
34731 * This bit must be '1' for the l2_ovlan field to be
34734 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
34737 * This bit must be '1' for the l2_ovlan_mask field to be
34740 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
34743 * This bit must be '1' for the l2_ivlan field to be
34746 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
34749 * This bit must be '1' for the l2_ivlan_mask field to be
34752 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
34755 * This bit must be '1' for the t_l2_addr field to be
34758 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
34761 * This bit must be '1' for the t_l2_addr_mask field to be
34764 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
34767 * This bit must be '1' for the t_l2_ovlan field to be
34770 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
34773 * This bit must be '1' for the t_l2_ovlan_mask field to be
34776 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
34779 * This bit must be '1' for the t_l2_ivlan field to be
34782 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
34785 * This bit must be '1' for the t_l2_ivlan_mask field to be
34788 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
34791 * This bit must be '1' for the src_type field to be
34794 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
34797 * This bit must be '1' for the src_id field to be
34800 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
34803 * This bit must be '1' for the tunnel_type field to be
34806 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
34809 * This bit must be '1' for the dst_id field to be
34812 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
34815 * This bit must be '1' for the mirror_vnic_id field to be
34818 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
34821 * This bit must be '1' for the num_vlans field to be
34824 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
34827 * This bit must be '1' for the t_num_vlans field to be
34830 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
34833 * This value sets the match value for the L2 MAC address.
34834 * Destination MAC address for RX path.
34835 * Source MAC address for TX path.
34837 uint8_t l2_addr[6];
34838 /* This value sets the match value for the number of VLANs. */
34841 * This value sets the match value for the number of VLANs
34842 * in the tunnel headers.
34844 uint8_t t_num_vlans;
34846 * This value sets the mask value for the L2 address.
34847 * A value of 0 will mask the corresponding bit from
34850 uint8_t l2_addr_mask[6];
34851 /* This value sets VLAN ID value for outer VLAN. */
34854 * This value sets the mask value for the ovlan id.
34855 * A value of 0 will mask the corresponding bit from
34858 uint16_t l2_ovlan_mask;
34859 /* This value sets VLAN ID value for inner VLAN. */
34862 * This value sets the mask value for the ivlan id.
34863 * A value of 0 will mask the corresponding bit from
34866 uint16_t l2_ivlan_mask;
34867 uint8_t unused_1[2];
34869 * This value sets the match value for the tunnel
34871 * Destination MAC address for RX path.
34872 * Source MAC address for TX path.
34874 uint8_t t_l2_addr[6];
34875 uint8_t unused_2[2];
34877 * This value sets the mask value for the tunnel L2
34879 * A value of 0 will mask the corresponding bit from
34882 uint8_t t_l2_addr_mask[6];
34883 /* This value sets VLAN ID value for tunnel outer VLAN. */
34884 uint16_t t_l2_ovlan;
34886 * This value sets the mask value for the tunnel ovlan id.
34887 * A value of 0 will mask the corresponding bit from
34890 uint16_t t_l2_ovlan_mask;
34891 /* This value sets VLAN ID value for tunnel inner VLAN. */
34892 uint16_t t_l2_ivlan;
34894 * This value sets the mask value for the tunnel ivlan id.
34895 * A value of 0 will mask the corresponding bit from
34898 uint16_t t_l2_ivlan_mask;
34899 /* This value identifies the type of source of the packet. */
34902 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
34903 /* Physical function */
34904 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
34905 /* Virtual function */
34906 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
34907 /* Virtual NIC of a function */
34908 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
34909 /* Embedded processor for CFA management */
34910 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
34911 /* Embedded processor for OOB management */
34912 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
34913 /* Embedded processor for RoCE */
34914 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
34915 /* Embedded processor for network proxy functions */
34916 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
34917 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
34918 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
34921 * This value is the id of the source.
34922 * For a network port, it represents port_id.
34923 * For a physical function, it represents fid.
34924 * For a virtual function, it represents vf_id.
34925 * For a vnic, it represents vnic_id.
34926 * For embedded processors, this id is not valid.
34929 * 1. The function ID is implied if it src_id is
34930 * not provided for a src_type that is either
34934 uint8_t tunnel_type;
34936 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34938 /* Virtual eXtensible Local Area Network (VXLAN) */
34939 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34941 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34942 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34944 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34945 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34948 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34950 /* Generic Network Virtualization Encapsulation (Geneve) */
34951 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34953 /* Multi-Protocol Label Switching (MPLS) */
34954 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34956 /* Stateless Transport Tunnel (STT) */
34957 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
34959 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34960 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34962 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34963 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34966 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
34969 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34971 /* Use fixed layer 2 ether type of 0xFFFF */
34972 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34975 * IPV6 over virtual eXtensible Local Area Network with GPE header
34978 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34980 /* Any tunneled traffic */
34981 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34983 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34984 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34987 * If set, this value shall represent the
34988 * Logical VNIC ID of the destination VNIC for the RX
34989 * path and network port id of the destination port for
34994 * Logical VNIC ID of the VNIC where traffic is
34997 uint16_t mirror_vnic_id;
34999 * This hint is provided to help in placing
35000 * the filter in the filter table.
35003 /* No preference */
35004 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
35006 /* Above the given filter */
35007 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
35009 /* Below the given filter */
35010 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
35012 /* As high as possible */
35013 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
35015 /* As low as possible */
35016 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
35018 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
35019 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
35023 * This is the ID of the filter that goes along with
35026 * This field is valid only for the following values.
35027 * 1 - Above the given filter
35028 * 2 - Below the given filter
35030 uint64_t l2_filter_id_hint;
35033 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
35034 struct hwrm_cfa_l2_filter_alloc_output {
35035 /* The specific error status for the command. */
35036 uint16_t error_code;
35037 /* The HWRM command request type. */
35039 /* The sequence ID from the original command. */
35041 /* The length of the response data in number of bytes. */
35044 * This value identifies a set of CFA data structures used for an L2
35047 uint64_t l2_filter_id;
35049 * The flow id value in bit 0-29 is the actual ID of the flow
35050 * associated with this filter and it shall be used to match
35051 * and associate the flow identifier returned in completion
35052 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
35053 * shall indicate no valid flow id.
35056 /* Indicate the flow id value. */
35057 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
35058 UINT32_C(0x3fffffff)
35059 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
35060 /* Indicate type of the flow. */
35061 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
35062 UINT32_C(0x40000000)
35064 * If this bit set to 0, then it indicates that the flow is
35067 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
35068 (UINT32_C(0x0) << 30)
35070 * If this bit is set to 1, then it indicates that the flow is
35073 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
35074 (UINT32_C(0x1) << 30)
35075 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
35076 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
35077 /* Indicate the flow direction. */
35078 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
35079 UINT32_C(0x80000000)
35080 /* If this bit set to 0, then it indicates rx flow. */
35081 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
35082 (UINT32_C(0x0) << 31)
35083 /* If this bit is set to 1, then it indicates that tx flow. */
35084 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
35085 (UINT32_C(0x1) << 31)
35086 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
35087 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
35088 uint8_t unused_0[3];
35090 * This field is used in Output records to indicate that the output
35091 * is completely written to RAM. This field should be read as '1'
35092 * to indicate that the output has been completely written.
35093 * When writing a command completion or response to an internal
35094 * processor, the order of writes has to be such that this field is
35100 /***************************
35101 * hwrm_cfa_l2_filter_free *
35102 ***************************/
35105 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
35106 struct hwrm_cfa_l2_filter_free_input {
35107 /* The HWRM command request type. */
35110 * The completion ring to send the completion event on. This should
35111 * be the NQ ID returned from the `nq_alloc` HWRM command.
35113 uint16_t cmpl_ring;
35115 * The sequence ID is used by the driver for tracking multiple
35116 * commands. This ID is treated as opaque data by the firmware and
35117 * the value is returned in the `hwrm_resp_hdr` upon completion.
35121 * The target ID of the command:
35122 * * 0x0-0xFFF8 - The function ID
35123 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35124 * * 0xFFFD - Reserved for user-space HWRM interface
35127 uint16_t target_id;
35129 * A physical address pointer pointing to a host buffer that the
35130 * command's response data will be written. This can be either a host
35131 * physical address (HPA) or a guest physical address (GPA) and must
35132 * point to a physically contiguous block of memory.
35134 uint64_t resp_addr;
35136 * This value identifies a set of CFA data structures used for an L2
35139 uint64_t l2_filter_id;
35142 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
35143 struct hwrm_cfa_l2_filter_free_output {
35144 /* The specific error status for the command. */
35145 uint16_t error_code;
35146 /* The HWRM command request type. */
35148 /* The sequence ID from the original command. */
35150 /* The length of the response data in number of bytes. */
35152 uint8_t unused_0[7];
35154 * This field is used in Output records to indicate that the output
35155 * is completely written to RAM. This field should be read as '1'
35156 * to indicate that the output has been completely written.
35157 * When writing a command completion or response to an internal
35158 * processor, the order of writes has to be such that this field is
35164 /**************************
35165 * hwrm_cfa_l2_filter_cfg *
35166 **************************/
35169 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
35170 struct hwrm_cfa_l2_filter_cfg_input {
35171 /* The HWRM command request type. */
35174 * The completion ring to send the completion event on. This should
35175 * be the NQ ID returned from the `nq_alloc` HWRM command.
35177 uint16_t cmpl_ring;
35179 * The sequence ID is used by the driver for tracking multiple
35180 * commands. This ID is treated as opaque data by the firmware and
35181 * the value is returned in the `hwrm_resp_hdr` upon completion.
35185 * The target ID of the command:
35186 * * 0x0-0xFFF8 - The function ID
35187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35188 * * 0xFFFD - Reserved for user-space HWRM interface
35191 uint16_t target_id;
35193 * A physical address pointer pointing to a host buffer that the
35194 * command's response data will be written. This can be either a host
35195 * physical address (HPA) or a guest physical address (GPA) and must
35196 * point to a physically contiguous block of memory.
35198 uint64_t resp_addr;
35201 * Enumeration denoting the RX, TX type of the resource.
35202 * This enumeration is used for resources that are similar for both
35203 * TX and RX paths of the chip.
35205 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
35208 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
35211 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
35213 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
35214 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
35216 * Setting of this flag indicates drop action. If this flag is not
35217 * set, then it should be considered accept action.
35219 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
35222 * Enumeration denoting NO_ROCE_L2 to support old drivers.
35223 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
35225 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
35227 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
35228 /* To support old drivers */
35229 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
35230 (UINT32_C(0x0) << 2)
35231 /* Only L2 traffic */
35232 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
35233 (UINT32_C(0x1) << 2)
35234 /* Roce & L2 traffic */
35235 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
35236 (UINT32_C(0x2) << 2)
35237 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
35238 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
35241 * This bit must be '1' for the dst_id field to be
35244 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
35247 * This bit must be '1' for the new_mirror_vnic_id field to be
35250 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
35253 * This value identifies a set of CFA data structures used for an L2
35256 uint64_t l2_filter_id;
35258 * If set, this value shall represent the
35259 * Logical VNIC ID of the destination VNIC for the RX
35260 * path and network port id of the destination port for
35265 * New Logical VNIC ID of the VNIC where traffic is
35268 uint32_t new_mirror_vnic_id;
35271 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
35272 struct hwrm_cfa_l2_filter_cfg_output {
35273 /* The specific error status for the command. */
35274 uint16_t error_code;
35275 /* The HWRM command request type. */
35277 /* The sequence ID from the original command. */
35279 /* The length of the response data in number of bytes. */
35281 uint8_t unused_0[7];
35283 * This field is used in Output records to indicate that the output
35284 * is completely written to RAM. This field should be read as '1'
35285 * to indicate that the output has been completely written.
35286 * When writing a command completion or response to an internal
35287 * processor, the order of writes has to be such that this field is
35293 /***************************
35294 * hwrm_cfa_l2_set_rx_mask *
35295 ***************************/
35298 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
35299 struct hwrm_cfa_l2_set_rx_mask_input {
35300 /* The HWRM command request type. */
35303 * The completion ring to send the completion event on. This should
35304 * be the NQ ID returned from the `nq_alloc` HWRM command.
35306 uint16_t cmpl_ring;
35308 * The sequence ID is used by the driver for tracking multiple
35309 * commands. This ID is treated as opaque data by the firmware and
35310 * the value is returned in the `hwrm_resp_hdr` upon completion.
35314 * The target ID of the command:
35315 * * 0x0-0xFFF8 - The function ID
35316 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35317 * * 0xFFFD - Reserved for user-space HWRM interface
35320 uint16_t target_id;
35322 * A physical address pointer pointing to a host buffer that the
35323 * command's response data will be written. This can be either a host
35324 * physical address (HPA) or a guest physical address (GPA) and must
35325 * point to a physically contiguous block of memory.
35327 uint64_t resp_addr;
35332 * When this bit is '1', the function is requested to accept
35333 * multi-cast packets specified by the multicast addr table.
35335 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
35338 * When this bit is '1', the function is requested to accept
35339 * all multi-cast packets.
35341 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
35344 * When this bit is '1', the function is requested to accept
35345 * broadcast packets.
35347 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
35350 * When this bit is '1', the function is requested to be
35351 * put in the promiscuous mode.
35353 * The HWRM should accept any function to set up
35354 * promiscuous mode.
35356 * The HWRM shall follow the semantics below for the
35357 * promiscuous mode support.
35358 * # When partitioning is not enabled on a port
35359 * (i.e. single PF on the port), then the PF shall
35360 * be allowed to be in the promiscuous mode. When the
35361 * PF is in the promiscuous mode, then it shall
35362 * receive all host bound traffic on that port.
35363 * # When partitioning is enabled on a port
35364 * (i.e. multiple PFs per port) and a PF on that
35365 * port is in the promiscuous mode, then the PF
35366 * receives all traffic within that partition as
35367 * identified by a unique identifier for the
35368 * PF (e.g. S-Tag). If a unique outer VLAN
35369 * for the PF is specified, then the setting of
35370 * promiscuous mode on that PF shall result in the
35371 * PF receiving all host bound traffic with matching
35373 * # A VF shall can be set in the promiscuous mode.
35374 * In the promiscuous mode, the VF does not receive any
35375 * traffic unless a unique outer VLAN for the
35376 * VF is specified. If a unique outer VLAN
35377 * for the VF is specified, then the setting of
35378 * promiscuous mode on that VF shall result in the
35379 * VF receiving all host bound traffic with the
35380 * matching outer VLAN.
35381 * # The HWRM shall allow the setting of promiscuous
35382 * mode on a function independently from the
35383 * promiscuous mode settings on other functions.
35385 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
35388 * If this flag is set, the corresponding RX
35389 * filters shall be set up to cover multicast/broadcast
35390 * filters for the outermost Layer 2 destination MAC
35393 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
35396 * If this flag is set, the corresponding RX
35397 * filters shall be set up to cover multicast/broadcast
35398 * filters for the VLAN-tagged packets that match the
35399 * TPID and VID fields of VLAN tags in the VLAN tag
35400 * table specified in this command.
35402 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
35405 * If this flag is set, the corresponding RX
35406 * filters shall be set up to cover multicast/broadcast
35407 * filters for non-VLAN tagged packets and VLAN-tagged
35408 * packets that match the TPID and VID fields of VLAN
35409 * tags in the VLAN tag table specified in this command.
35411 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
35414 * If this flag is set, the corresponding RX
35415 * filters shall be set up to cover multicast/broadcast
35416 * filters for non-VLAN tagged packets and VLAN-tagged
35417 * packets matching any VLAN tag.
35419 * If this flag is set, then the HWRM shall ignore
35420 * VLAN tags specified in vlan_tag_tbl.
35422 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
35423 * flags is set, then the HWRM shall ignore
35424 * VLAN tags specified in vlan_tag_tbl.
35426 * The HWRM client shall set at most one flag out of
35427 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
35429 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
35431 /* This is the address for mcast address tbl. */
35432 uint64_t mc_tbl_addr;
35434 * This value indicates how many entries in mc_tbl are valid.
35435 * Each entry is 6 bytes.
35437 uint32_t num_mc_entries;
35438 uint8_t unused_0[4];
35440 * This is the address for VLAN tag table.
35441 * Each VLAN entry in the table is 4 bytes of a VLAN tag
35442 * including TPID, PCP, DEI, and VID fields in network byte
35445 uint64_t vlan_tag_tbl_addr;
35447 * This value indicates how many entries in vlan_tag_tbl are
35448 * valid. Each entry is 4 bytes.
35450 uint32_t num_vlan_tags;
35451 uint8_t unused_1[4];
35454 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
35455 struct hwrm_cfa_l2_set_rx_mask_output {
35456 /* The specific error status for the command. */
35457 uint16_t error_code;
35458 /* The HWRM command request type. */
35460 /* The sequence ID from the original command. */
35462 /* The length of the response data in number of bytes. */
35464 uint8_t unused_0[7];
35466 * This field is used in Output records to indicate that the output
35467 * is completely written to RAM. This field should be read as '1'
35468 * to indicate that the output has been completely written.
35469 * When writing a command completion or response to an internal
35470 * processor, the order of writes has to be such that this field is
35476 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
35477 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
35479 * command specific error codes that goes to
35480 * the cmd_err field in Common HWRM Error Response.
35483 /* Unknown error */
35484 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
35486 /* Unable to complete operation due to conflict with Ntuple Filter */
35487 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
35489 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
35490 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
35491 uint8_t unused_0[7];
35494 /*******************************
35495 * hwrm_cfa_vlan_antispoof_cfg *
35496 *******************************/
35499 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
35500 struct hwrm_cfa_vlan_antispoof_cfg_input {
35501 /* The HWRM command request type. */
35504 * The completion ring to send the completion event on. This should
35505 * be the NQ ID returned from the `nq_alloc` HWRM command.
35507 uint16_t cmpl_ring;
35509 * The sequence ID is used by the driver for tracking multiple
35510 * commands. This ID is treated as opaque data by the firmware and
35511 * the value is returned in the `hwrm_resp_hdr` upon completion.
35515 * The target ID of the command:
35516 * * 0x0-0xFFF8 - The function ID
35517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35518 * * 0xFFFD - Reserved for user-space HWRM interface
35521 uint16_t target_id;
35523 * A physical address pointer pointing to a host buffer that the
35524 * command's response data will be written. This can be either a host
35525 * physical address (HPA) or a guest physical address (GPA) and must
35526 * point to a physically contiguous block of memory.
35528 uint64_t resp_addr;
35530 * Function ID of the function that is being configured.
35531 * Only valid for a VF FID configured by the PF.
35534 uint8_t unused_0[2];
35535 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
35536 uint32_t num_vlan_entries;
35538 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
35539 * antispoof table. Each table entry contains the 16-bit TPID
35540 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
35541 * all in network order to match hwrm_cfa_l2_set_rx_mask.
35542 * For an individual VLAN entry, the mask value should be 0xfff
35543 * for the 12-bit VLAN ID.
35545 uint64_t vlan_tag_mask_tbl_addr;
35548 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
35549 struct hwrm_cfa_vlan_antispoof_cfg_output {
35550 /* The specific error status for the command. */
35551 uint16_t error_code;
35552 /* The HWRM command request type. */
35554 /* The sequence ID from the original command. */
35556 /* The length of the response data in number of bytes. */
35558 uint8_t unused_0[7];
35560 * This field is used in Output records to indicate that the output
35561 * is completely written to RAM. This field should be read as '1'
35562 * to indicate that the output has been completely written.
35563 * When writing a command completion or response to an internal
35564 * processor, the order of writes has to be such that this field is
35570 /********************************
35571 * hwrm_cfa_vlan_antispoof_qcfg *
35572 ********************************/
35575 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
35576 struct hwrm_cfa_vlan_antispoof_qcfg_input {
35577 /* The HWRM command request type. */
35580 * The completion ring to send the completion event on. This should
35581 * be the NQ ID returned from the `nq_alloc` HWRM command.
35583 uint16_t cmpl_ring;
35585 * The sequence ID is used by the driver for tracking multiple
35586 * commands. This ID is treated as opaque data by the firmware and
35587 * the value is returned in the `hwrm_resp_hdr` upon completion.
35591 * The target ID of the command:
35592 * * 0x0-0xFFF8 - The function ID
35593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35594 * * 0xFFFD - Reserved for user-space HWRM interface
35597 uint16_t target_id;
35599 * A physical address pointer pointing to a host buffer that the
35600 * command's response data will be written. This can be either a host
35601 * physical address (HPA) or a guest physical address (GPA) and must
35602 * point to a physically contiguous block of memory.
35604 uint64_t resp_addr;
35606 * Function ID of the function that is being queried.
35607 * Only valid for a VF FID queried by the PF.
35610 uint8_t unused_0[2];
35612 * Maximum number of VLAN entries the firmware is allowed to DMA
35613 * to vlan_tag_mask_tbl.
35615 uint32_t max_vlan_entries;
35617 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
35618 * antispoof table to which firmware will DMA to. Each table
35619 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
35620 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
35621 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
35622 * the mask value should be 0xfff for the 12-bit VLAN ID.
35624 uint64_t vlan_tag_mask_tbl_addr;
35627 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
35628 struct hwrm_cfa_vlan_antispoof_qcfg_output {
35629 /* The specific error status for the command. */
35630 uint16_t error_code;
35631 /* The HWRM command request type. */
35633 /* The sequence ID from the original command. */
35635 /* The length of the response data in number of bytes. */
35637 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
35638 uint32_t num_vlan_entries;
35639 uint8_t unused_0[3];
35641 * This field is used in Output records to indicate that the output
35642 * is completely written to RAM. This field should be read as '1'
35643 * to indicate that the output has been completely written.
35644 * When writing a command completion or response to an internal
35645 * processor, the order of writes has to be such that this field is
35651 /********************************
35652 * hwrm_cfa_tunnel_filter_alloc *
35653 ********************************/
35656 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
35657 struct hwrm_cfa_tunnel_filter_alloc_input {
35658 /* The HWRM command request type. */
35661 * The completion ring to send the completion event on. This should
35662 * be the NQ ID returned from the `nq_alloc` HWRM command.
35664 uint16_t cmpl_ring;
35666 * The sequence ID is used by the driver for tracking multiple
35667 * commands. This ID is treated as opaque data by the firmware and
35668 * the value is returned in the `hwrm_resp_hdr` upon completion.
35672 * The target ID of the command:
35673 * * 0x0-0xFFF8 - The function ID
35674 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35675 * * 0xFFFD - Reserved for user-space HWRM interface
35678 uint16_t target_id;
35680 * A physical address pointer pointing to a host buffer that the
35681 * command's response data will be written. This can be either a host
35682 * physical address (HPA) or a guest physical address (GPA) and must
35683 * point to a physically contiguous block of memory.
35685 uint64_t resp_addr;
35688 * Setting of this flag indicates the applicability to the loopback
35691 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
35695 * This bit must be '1' for the l2_filter_id field to be
35698 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
35701 * This bit must be '1' for the l2_addr field to be
35704 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
35707 * This bit must be '1' for the l2_ivlan field to be
35710 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
35713 * This bit must be '1' for the l3_addr field to be
35716 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
35719 * This bit must be '1' for the l3_addr_type field to be
35722 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
35725 * This bit must be '1' for the t_l3_addr_type field to be
35728 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
35731 * This bit must be '1' for the t_l3_addr field to be
35734 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
35737 * This bit must be '1' for the tunnel_type field to be
35740 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
35743 * This bit must be '1' for the vni field to be
35746 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
35749 * This bit must be '1' for the dst_vnic_id field to be
35752 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
35755 * This bit must be '1' for the mirror_vnic_id field to be
35758 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
35761 * This value identifies a set of CFA data structures used for an L2
35764 uint64_t l2_filter_id;
35766 * This value sets the match value for the inner L2
35768 * Destination MAC address for RX path.
35769 * Source MAC address for TX path.
35771 uint8_t l2_addr[6];
35773 * This value sets VLAN ID value for inner VLAN.
35774 * Only 12-bits of VLAN ID are used in setting the filter.
35778 * The value of inner destination IP address to be used in filtering.
35779 * For IPv4, first four bytes represent the IP address.
35781 uint32_t l3_addr[4];
35783 * The value of tunnel destination IP address to be used in filtering.
35784 * For IPv4, first four bytes represent the IP address.
35786 uint32_t t_l3_addr[4];
35788 * This value indicates the type of inner IP address.
35791 * All others are invalid.
35793 uint8_t l3_addr_type;
35795 * This value indicates the type of tunnel IP address.
35798 * All others are invalid.
35800 uint8_t t_l3_addr_type;
35802 uint8_t tunnel_type;
35804 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
35806 /* Virtual eXtensible Local Area Network (VXLAN) */
35807 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
35809 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35810 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
35812 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35813 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
35816 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
35818 /* Generic Network Virtualization Encapsulation (Geneve) */
35819 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
35821 /* Multi-Protocol Label Switching (MPLS) */
35822 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
35824 /* Stateless Transport Tunnel (STT) */
35825 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
35827 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35828 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
35830 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35831 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35834 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35837 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35839 /* Use fixed layer 2 ether type of 0xFFFF */
35840 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35843 * IPV6 over virtual eXtensible Local Area Network with GPE header
35846 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35848 /* Any tunneled traffic */
35849 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35851 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35852 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35854 * tunnel_flags allows the user to indicate the tunnel tag detection
35855 * for the tunnel type specified in tunnel_type.
35857 uint8_t tunnel_flags;
35859 * If the tunnel_type is geneve, then this bit indicates if we
35860 * need to match the geneve OAM packet.
35861 * If the tunnel_type is nvgre or gre, then this bit indicates if
35862 * we need to detect checksum present bit in geneve header.
35863 * If the tunnel_type is mpls, then this bit indicates if we need
35864 * to match mpls packet with explicit IPV4/IPV6 null header.
35866 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
35869 * If the tunnel_type is geneve, then this bit indicates if we
35870 * need to detect the critical option bit set in the oam packet.
35871 * If the tunnel_type is nvgre or gre, then this bit indicates
35872 * if we need to match nvgre packets with key present bit set in
35874 * If the tunnel_type is mpls, then this bit indicates if we
35875 * need to match mpls packet with S bit from inner/second label.
35877 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
35880 * If the tunnel_type is geneve, then this bit indicates if we
35881 * need to match geneve packet with extended header bit set in
35883 * If the tunnel_type is nvgre or gre, then this bit indicates
35884 * if we need to match nvgre packets with sequence number
35885 * present bit set in gre header.
35886 * If the tunnel_type is mpls, then this bit indicates if we
35887 * need to match mpls packet with S bit from out/first label.
35889 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
35892 * Virtual Network Identifier (VNI). Only valid with
35893 * tunnel_types VXLAN, NVGRE, and Geneve.
35894 * Only lower 24-bits of VNI field are used
35895 * in setting up the filter.
35898 /* Logical VNIC ID of the destination VNIC. */
35899 uint32_t dst_vnic_id;
35901 * Logical VNIC ID of the VNIC where traffic is
35904 uint32_t mirror_vnic_id;
35907 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
35908 struct hwrm_cfa_tunnel_filter_alloc_output {
35909 /* The specific error status for the command. */
35910 uint16_t error_code;
35911 /* The HWRM command request type. */
35913 /* The sequence ID from the original command. */
35915 /* The length of the response data in number of bytes. */
35917 /* This value is an opaque id into CFA data structures. */
35918 uint64_t tunnel_filter_id;
35920 * The flow id value in bit 0-29 is the actual ID of the flow
35921 * associated with this filter and it shall be used to match
35922 * and associate the flow identifier returned in completion
35923 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
35924 * shall indicate no valid flow id.
35927 /* Indicate the flow id value. */
35928 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
35929 UINT32_C(0x3fffffff)
35930 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
35931 /* Indicate type of the flow. */
35932 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
35933 UINT32_C(0x40000000)
35935 * If this bit set to 0, then it indicates that the flow is
35938 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
35939 (UINT32_C(0x0) << 30)
35941 * If this bit is set to 1, then it indicates that the flow is
35944 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
35945 (UINT32_C(0x1) << 30)
35946 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
35947 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
35948 /* Indicate the flow direction. */
35949 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
35950 UINT32_C(0x80000000)
35951 /* If this bit set to 0, then it indicates rx flow. */
35952 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
35953 (UINT32_C(0x0) << 31)
35954 /* If this bit is set to 1, then it indicates that tx flow. */
35955 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
35956 (UINT32_C(0x1) << 31)
35957 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
35958 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
35959 uint8_t unused_0[3];
35961 * This field is used in Output records to indicate that the output
35962 * is completely written to RAM. This field should be read as '1'
35963 * to indicate that the output has been completely written.
35964 * When writing a command completion or response to an internal
35965 * processor, the order of writes has to be such that this field is
35971 /*******************************
35972 * hwrm_cfa_tunnel_filter_free *
35973 *******************************/
35976 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
35977 struct hwrm_cfa_tunnel_filter_free_input {
35978 /* The HWRM command request type. */
35981 * The completion ring to send the completion event on. This should
35982 * be the NQ ID returned from the `nq_alloc` HWRM command.
35984 uint16_t cmpl_ring;
35986 * The sequence ID is used by the driver for tracking multiple
35987 * commands. This ID is treated as opaque data by the firmware and
35988 * the value is returned in the `hwrm_resp_hdr` upon completion.
35992 * The target ID of the command:
35993 * * 0x0-0xFFF8 - The function ID
35994 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35995 * * 0xFFFD - Reserved for user-space HWRM interface
35998 uint16_t target_id;
36000 * A physical address pointer pointing to a host buffer that the
36001 * command's response data will be written. This can be either a host
36002 * physical address (HPA) or a guest physical address (GPA) and must
36003 * point to a physically contiguous block of memory.
36005 uint64_t resp_addr;
36006 /* This value is an opaque id into CFA data structures. */
36007 uint64_t tunnel_filter_id;
36010 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
36011 struct hwrm_cfa_tunnel_filter_free_output {
36012 /* The specific error status for the command. */
36013 uint16_t error_code;
36014 /* The HWRM command request type. */
36016 /* The sequence ID from the original command. */
36018 /* The length of the response data in number of bytes. */
36020 uint8_t unused_0[7];
36022 * This field is used in Output records to indicate that the output
36023 * is completely written to RAM. This field should be read as '1'
36024 * to indicate that the output has been completely written.
36025 * When writing a command completion or response to an internal
36026 * processor, the order of writes has to be such that this field is
36032 /***************************************
36033 * hwrm_cfa_redirect_tunnel_type_alloc *
36034 ***************************************/
36037 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
36038 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
36039 /* The HWRM command request type. */
36042 * The completion ring to send the completion event on. This should
36043 * be the NQ ID returned from the `nq_alloc` HWRM command.
36045 uint16_t cmpl_ring;
36047 * The sequence ID is used by the driver for tracking multiple
36048 * commands. This ID is treated as opaque data by the firmware and
36049 * the value is returned in the `hwrm_resp_hdr` upon completion.
36053 * The target ID of the command:
36054 * * 0x0-0xFFF8 - The function ID
36055 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36056 * * 0xFFFD - Reserved for user-space HWRM interface
36059 uint16_t target_id;
36061 * A physical address pointer pointing to a host buffer that the
36062 * command's response data will be written. This can be either a host
36063 * physical address (HPA) or a guest physical address (GPA) and must
36064 * point to a physically contiguous block of memory.
36066 uint64_t resp_addr;
36067 /* The destination function id, to whom the traffic is redirected. */
36070 uint8_t tunnel_type;
36072 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
36074 /* Virtual eXtensible Local Area Network (VXLAN) */
36075 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
36077 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36078 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
36080 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36081 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
36084 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
36086 /* Generic Network Virtualization Encapsulation (Geneve) */
36087 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
36089 /* Multi-Protocol Label Switching (MPLS) */
36090 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
36092 /* Stateless Transport Tunnel (STT) */
36093 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
36095 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
36098 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36102 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36107 /* Use fixed layer 2 ether type of 0xFFFF */
36108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
36111 * IPV6 over virtual eXtensible Local Area Network with GPE header
36114 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36116 /* Any tunneled traffic */
36117 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36119 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
36120 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
36121 /* Tunnel alloc flags. */
36124 * Setting of this flag indicates modify existing redirect tunnel
36125 * to new destination function ID.
36127 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
36129 uint8_t unused_0[4];
36132 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
36133 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
36134 /* The specific error status for the command. */
36135 uint16_t error_code;
36136 /* The HWRM command request type. */
36138 /* The sequence ID from the original command. */
36140 /* The length of the response data in number of bytes. */
36142 uint8_t unused_0[7];
36144 * This field is used in Output records to indicate that the output
36145 * is completely written to RAM. This field should be read as '1'
36146 * to indicate that the output has been completely written.
36147 * When writing a command completion or response to an internal
36148 * processor, the order of writes has to be such that this field is
36154 /**************************************
36155 * hwrm_cfa_redirect_tunnel_type_free *
36156 **************************************/
36159 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
36160 struct hwrm_cfa_redirect_tunnel_type_free_input {
36161 /* The HWRM command request type. */
36164 * The completion ring to send the completion event on. This should
36165 * be the NQ ID returned from the `nq_alloc` HWRM command.
36167 uint16_t cmpl_ring;
36169 * The sequence ID is used by the driver for tracking multiple
36170 * commands. This ID is treated as opaque data by the firmware and
36171 * the value is returned in the `hwrm_resp_hdr` upon completion.
36175 * The target ID of the command:
36176 * * 0x0-0xFFF8 - The function ID
36177 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36178 * * 0xFFFD - Reserved for user-space HWRM interface
36181 uint16_t target_id;
36183 * A physical address pointer pointing to a host buffer that the
36184 * command's response data will be written. This can be either a host
36185 * physical address (HPA) or a guest physical address (GPA) and must
36186 * point to a physically contiguous block of memory.
36188 uint64_t resp_addr;
36189 /* The destination function id, to whom the traffic is redirected. */
36192 uint8_t tunnel_type;
36194 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
36196 /* Virtual eXtensible Local Area Network (VXLAN) */
36197 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
36199 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36200 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
36202 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36203 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
36206 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
36208 /* Generic Network Virtualization Encapsulation (Geneve) */
36209 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
36211 /* Multi-Protocol Label Switching (MPLS) */
36212 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
36214 /* Stateless Transport Tunnel (STT) */
36215 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
36217 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36218 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
36220 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36221 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36224 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36227 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36229 /* Use fixed layer 2 ether type of 0xFFFF */
36230 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
36233 * IPV6 over virtual eXtensible Local Area Network with GPE header
36236 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36238 /* Any tunneled traffic */
36239 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36241 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
36242 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
36243 uint8_t unused_0[5];
36246 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
36247 struct hwrm_cfa_redirect_tunnel_type_free_output {
36248 /* The specific error status for the command. */
36249 uint16_t error_code;
36250 /* The HWRM command request type. */
36252 /* The sequence ID from the original command. */
36254 /* The length of the response data in number of bytes. */
36256 uint8_t unused_0[7];
36258 * This field is used in Output records to indicate that the output
36259 * is completely written to RAM. This field should be read as '1'
36260 * to indicate that the output has been completely written.
36261 * When writing a command completion or response to an internal
36262 * processor, the order of writes has to be such that this field is
36268 /**************************************
36269 * hwrm_cfa_redirect_tunnel_type_info *
36270 **************************************/
36273 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
36274 struct hwrm_cfa_redirect_tunnel_type_info_input {
36275 /* The HWRM command request type. */
36278 * The completion ring to send the completion event on. This should
36279 * be the NQ ID returned from the `nq_alloc` HWRM command.
36281 uint16_t cmpl_ring;
36283 * The sequence ID is used by the driver for tracking multiple
36284 * commands. This ID is treated as opaque data by the firmware and
36285 * the value is returned in the `hwrm_resp_hdr` upon completion.
36289 * The target ID of the command:
36290 * * 0x0-0xFFF8 - The function ID
36291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36292 * * 0xFFFD - Reserved for user-space HWRM interface
36295 uint16_t target_id;
36297 * A physical address pointer pointing to a host buffer that the
36298 * command's response data will be written. This can be either a host
36299 * physical address (HPA) or a guest physical address (GPA) and must
36300 * point to a physically contiguous block of memory.
36302 uint64_t resp_addr;
36303 /* The source function id. */
36306 uint8_t tunnel_type;
36308 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
36310 /* Virtual eXtensible Local Area Network (VXLAN) */
36311 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
36313 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36314 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
36316 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36317 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
36320 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
36322 /* Generic Network Virtualization Encapsulation (Geneve) */
36323 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
36325 /* Multi-Protocol Label Switching (MPLS) */
36326 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
36328 /* Stateless Transport Tunnel (STT) */
36329 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
36331 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36332 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
36334 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36335 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36338 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36341 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36343 /* Use fixed layer 2 ether type of 0xFFFF */
36344 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
36347 * IPV6 over virtual eXtensible Local Area Network with GPE header
36350 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36352 /* Any tunneled traffic */
36353 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36355 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
36356 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
36357 uint8_t unused_0[5];
36360 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
36361 struct hwrm_cfa_redirect_tunnel_type_info_output {
36362 /* The specific error status for the command. */
36363 uint16_t error_code;
36364 /* The HWRM command request type. */
36366 /* The sequence ID from the original command. */
36368 /* The length of the response data in number of bytes. */
36370 /* The destination function id, to whom the traffic is redirected. */
36372 uint8_t unused_0[5];
36374 * This field is used in Output records to indicate that the output
36375 * is completely written to RAM. This field should be read as '1'
36376 * to indicate that the output has been completely written.
36377 * When writing a command completion or response to an internal
36378 * processor, the order of writes has to be such that this field is
36384 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
36385 struct hwrm_vxlan_ipv4_hdr {
36386 /* IPv4 version and header length. */
36388 /* IPv4 header length */
36389 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
36390 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
36392 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
36393 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
36394 /* IPv4 type of service. */
36396 /* IPv4 identification. */
36398 /* IPv4 flags and offset. */
36399 uint16_t flags_frag_offset;
36402 /* IPv4 protocol. */
36404 /* IPv4 source address. */
36405 uint32_t src_ip_addr;
36406 /* IPv4 destination address. */
36407 uint32_t dest_ip_addr;
36410 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
36411 struct hwrm_vxlan_ipv6_hdr {
36412 /* IPv6 version, traffic class and flow label. */
36413 uint32_t ver_tc_flow_label;
36414 /* IPv6 version shift */
36415 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
36417 /* IPv6 version mask */
36418 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
36419 UINT32_C(0xf0000000)
36420 /* IPv6 TC shift */
36421 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
36424 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
36425 UINT32_C(0xff00000)
36426 /* IPv6 flow label shift */
36427 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
36429 /* IPv6 flow label mask */
36430 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
36432 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
36433 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
36434 /* IPv6 payload length. */
36435 uint16_t payload_len;
36436 /* IPv6 next header. */
36440 /* IPv6 source address. */
36441 uint32_t src_ip_addr[4];
36442 /* IPv6 destination address. */
36443 uint32_t dest_ip_addr[4];
36446 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
36447 struct hwrm_cfa_encap_data_vxlan {
36448 /* Source MAC address. */
36449 uint8_t src_mac_addr[6];
36452 /* Destination MAC address. */
36453 uint8_t dst_mac_addr[6];
36454 /* Number of VLAN tags. */
36455 uint8_t num_vlan_tags;
36458 /* Outer VLAN TPID. */
36459 uint16_t ovlan_tpid;
36460 /* Outer VLAN TCI. */
36461 uint16_t ovlan_tci;
36462 /* Inner VLAN TPID. */
36463 uint16_t ivlan_tpid;
36464 /* Inner VLAN TCI. */
36465 uint16_t ivlan_tci;
36466 /* L3 header fields. */
36468 /* IP version mask. */
36469 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
36470 /* IP version 4. */
36471 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
36472 /* IP version 6. */
36473 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
36474 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
36475 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
36476 /* UDP source port. */
36478 /* UDP destination port. */
36480 /* VXLAN Network Identifier. */
36483 * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
36486 uint8_t hdr_rsvd0[3];
36487 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
36489 /* VXLAN header flags field. */
36494 /*******************************
36495 * hwrm_cfa_encap_record_alloc *
36496 *******************************/
36499 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
36500 struct hwrm_cfa_encap_record_alloc_input {
36501 /* The HWRM command request type. */
36504 * The completion ring to send the completion event on. This should
36505 * be the NQ ID returned from the `nq_alloc` HWRM command.
36507 uint16_t cmpl_ring;
36509 * The sequence ID is used by the driver for tracking multiple
36510 * commands. This ID is treated as opaque data by the firmware and
36511 * the value is returned in the `hwrm_resp_hdr` upon completion.
36515 * The target ID of the command:
36516 * * 0x0-0xFFF8 - The function ID
36517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36518 * * 0xFFFD - Reserved for user-space HWRM interface
36521 uint16_t target_id;
36523 * A physical address pointer pointing to a host buffer that the
36524 * command's response data will be written. This can be either a host
36525 * physical address (HPA) or a guest physical address (GPA) and must
36526 * point to a physically contiguous block of memory.
36528 uint64_t resp_addr;
36531 * Setting of this flag indicates the applicability to the loopback
36534 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
36537 * Setting of this flag indicates this encap record is external
36538 * encap record. Resetting of this flag indicates this flag is
36539 * internal encap record and this is the default setting.
36541 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
36543 /* Encapsulation Type. */
36544 uint8_t encap_type;
36545 /* Virtual eXtensible Local Area Network (VXLAN) */
36546 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
36548 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36549 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
36551 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
36552 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
36555 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
36557 /* Generic Network Virtualization Encapsulation (Geneve) */
36558 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
36560 /* Multi-Protocol Label Switching (MPLS) */
36561 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
36564 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
36566 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36567 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
36569 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36570 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
36573 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36576 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
36578 /* Use fixed layer 2 ether type of 0xFFFF */
36579 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
36582 * IPV6 over virtual eXtensible Local Area Network with GPE header
36585 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
36587 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
36588 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
36589 uint8_t unused_0[3];
36590 /* This value is encap data used for the given encap type. */
36591 uint32_t encap_data[20];
36594 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
36595 struct hwrm_cfa_encap_record_alloc_output {
36596 /* The specific error status for the command. */
36597 uint16_t error_code;
36598 /* The HWRM command request type. */
36600 /* The sequence ID from the original command. */
36602 /* The length of the response data in number of bytes. */
36604 /* This value is an opaque id into CFA data structures. */
36605 uint32_t encap_record_id;
36606 uint8_t unused_0[3];
36608 * This field is used in Output records to indicate that the output
36609 * is completely written to RAM. This field should be read as '1'
36610 * to indicate that the output has been completely written.
36611 * When writing a command completion or response to an internal
36612 * processor, the order of writes has to be such that this field is
36618 /******************************
36619 * hwrm_cfa_encap_record_free *
36620 ******************************/
36623 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
36624 struct hwrm_cfa_encap_record_free_input {
36625 /* The HWRM command request type. */
36628 * The completion ring to send the completion event on. This should
36629 * be the NQ ID returned from the `nq_alloc` HWRM command.
36631 uint16_t cmpl_ring;
36633 * The sequence ID is used by the driver for tracking multiple
36634 * commands. This ID is treated as opaque data by the firmware and
36635 * the value is returned in the `hwrm_resp_hdr` upon completion.
36639 * The target ID of the command:
36640 * * 0x0-0xFFF8 - The function ID
36641 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36642 * * 0xFFFD - Reserved for user-space HWRM interface
36645 uint16_t target_id;
36647 * A physical address pointer pointing to a host buffer that the
36648 * command's response data will be written. This can be either a host
36649 * physical address (HPA) or a guest physical address (GPA) and must
36650 * point to a physically contiguous block of memory.
36652 uint64_t resp_addr;
36653 /* This value is an opaque id into CFA data structures. */
36654 uint32_t encap_record_id;
36655 uint8_t unused_0[4];
36658 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
36659 struct hwrm_cfa_encap_record_free_output {
36660 /* The specific error status for the command. */
36661 uint16_t error_code;
36662 /* The HWRM command request type. */
36664 /* The sequence ID from the original command. */
36666 /* The length of the response data in number of bytes. */
36668 uint8_t unused_0[7];
36670 * This field is used in Output records to indicate that the output
36671 * is completely written to RAM. This field should be read as '1'
36672 * to indicate that the output has been completely written.
36673 * When writing a command completion or response to an internal
36674 * processor, the order of writes has to be such that this field is
36680 /********************************
36681 * hwrm_cfa_ntuple_filter_alloc *
36682 ********************************/
36685 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
36686 struct hwrm_cfa_ntuple_filter_alloc_input {
36687 /* The HWRM command request type. */
36690 * The completion ring to send the completion event on. This should
36691 * be the NQ ID returned from the `nq_alloc` HWRM command.
36693 uint16_t cmpl_ring;
36695 * The sequence ID is used by the driver for tracking multiple
36696 * commands. This ID is treated as opaque data by the firmware and
36697 * the value is returned in the `hwrm_resp_hdr` upon completion.
36701 * The target ID of the command:
36702 * * 0x0-0xFFF8 - The function ID
36703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36704 * * 0xFFFD - Reserved for user-space HWRM interface
36707 uint16_t target_id;
36709 * A physical address pointer pointing to a host buffer that the
36710 * command's response data will be written. This can be either a host
36711 * physical address (HPA) or a guest physical address (GPA) and must
36712 * point to a physically contiguous block of memory.
36714 uint64_t resp_addr;
36717 * Setting of this flag indicates the applicability to the loopback
36720 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
36723 * Setting of this flag indicates drop action. If this flag is not
36724 * set, then it should be considered accept action.
36726 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
36729 * Setting of this flag indicates that a meter is expected to be
36730 * attached to this flow. This hint can be used when choosing the
36731 * action record format required for the flow.
36733 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
36736 * Setting of this flag indicates that the dst_id field contains
36737 * function ID. If this is not set it indicates dest_id is VNIC
36740 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
36743 * Setting of this flag indicates match on arp reply when ethertype
36744 * is 0x0806. If this is not set it indicates no specific arp opcode
36747 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
36750 * Setting of this flag indicates that the dst_id field contains RFS
36751 * ring table index. If this is not set it indicates dst_id is VNIC
36752 * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
36753 * can’t be set at the same time.
36755 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
36759 * This bit must be '1' for the l2_filter_id field to be
36762 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
36765 * This bit must be '1' for the ethertype field to be
36768 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
36771 * This bit must be '1' for the tunnel_type field to be
36774 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
36777 * This bit must be '1' for the src_macaddr field to be
36780 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
36783 * This bit must be '1' for the ipaddr_type field to be
36786 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
36789 * This bit must be '1' for the src_ipaddr field to be
36792 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
36795 * This bit must be '1' for the src_ipaddr_mask field to be
36798 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
36801 * This bit must be '1' for the dst_ipaddr field to be
36804 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
36807 * This bit must be '1' for the dst_ipaddr_mask field to be
36810 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
36813 * This bit must be '1' for the ip_protocol field to be
36816 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
36819 * This bit must be '1' for the src_port field to be
36822 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
36825 * This bit must be '1' for the src_port_mask field to be
36828 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
36831 * This bit must be '1' for the dst_port field to be
36834 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
36837 * This bit must be '1' for the dst_port_mask field to be
36840 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
36843 * This bit must be '1' for the pri_hint field to be
36846 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
36849 * This bit must be '1' for the ntuple_filter_id field to be
36852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
36855 * This bit must be '1' for the dst_id field to be
36858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
36861 * This bit must be '1' for the mirror_vnic_id field to be
36864 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
36867 * This bit must be '1' for the dst_macaddr field to be
36870 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
36872 /* This flag is deprecated. */
36873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
36876 * This value identifies a set of CFA data structures used for an L2
36879 uint64_t l2_filter_id;
36881 * This value indicates the source MAC address in
36882 * the Ethernet header.
36884 uint8_t src_macaddr[6];
36885 /* This value indicates the ethertype in the Ethernet header. */
36886 uint16_t ethertype;
36888 * This value indicates the type of IP address.
36891 * All others are invalid.
36893 uint8_t ip_addr_type;
36895 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
36898 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
36901 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
36903 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
36904 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
36906 * The value of protocol filed in IP header.
36907 * Applies to UDP and TCP traffic.
36911 uint8_t ip_protocol;
36913 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
36916 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
36919 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
36921 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
36922 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
36924 * If set, this value shall represent the
36925 * Logical VNIC ID of the destination VNIC for the RX
36926 * path and network port id of the destination port for
36931 * Logical VNIC ID of the VNIC where traffic is
36934 uint16_t mirror_vnic_id;
36936 * This value indicates the tunnel type for this filter.
36937 * If this field is not specified, then the filter shall
36938 * apply to both non-tunneled and tunneled packets.
36939 * If this field conflicts with the tunnel_type specified
36940 * in the l2_filter_id, then the HWRM shall return an
36941 * error for this command.
36943 uint8_t tunnel_type;
36945 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
36947 /* Virtual eXtensible Local Area Network (VXLAN) */
36948 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
36950 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36951 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
36953 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36954 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
36957 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
36959 /* Generic Network Virtualization Encapsulation (Geneve) */
36960 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
36962 /* Multi-Protocol Label Switching (MPLS) */
36963 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
36965 /* Stateless Transport Tunnel (STT) */
36966 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
36968 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36969 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
36971 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36972 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36975 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36978 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36980 /* Use fixed layer 2 ether type of 0xFFFF */
36981 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
36984 * IPV6 over virtual eXtensible Local Area Network with GPE header
36987 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36989 /* Any tunneled traffic */
36990 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36992 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
36993 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
36995 * This hint is provided to help in placing
36996 * the filter in the filter table.
36999 /* No preference */
37000 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
37002 /* Above the given filter */
37003 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
37005 /* Below the given filter */
37006 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
37008 /* As high as possible */
37009 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
37011 /* As low as possible */
37012 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
37014 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
37015 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
37017 * The value of source IP address to be used in filtering.
37018 * For IPv4, first four bytes represent the IP address.
37020 uint32_t src_ipaddr[4];
37022 * The value of source IP address mask to be used in
37024 * For IPv4, first four bytes represent the IP address mask.
37026 uint32_t src_ipaddr_mask[4];
37028 * The value of destination IP address to be used in filtering.
37029 * For IPv4, first four bytes represent the IP address.
37031 uint32_t dst_ipaddr[4];
37033 * The value of destination IP address mask to be used in
37035 * For IPv4, first four bytes represent the IP address mask.
37037 uint32_t dst_ipaddr_mask[4];
37039 * The value of source port to be used in filtering.
37040 * Applies to UDP and TCP traffic.
37044 * The value of source port mask to be used in filtering.
37045 * Applies to UDP and TCP traffic.
37047 uint16_t src_port_mask;
37049 * The value of destination port to be used in filtering.
37050 * Applies to UDP and TCP traffic.
37054 * The value of destination port mask to be used in
37056 * Applies to UDP and TCP traffic.
37058 uint16_t dst_port_mask;
37060 * This is the ID of the filter that goes along with
37063 uint64_t ntuple_filter_id_hint;
37066 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
37067 struct hwrm_cfa_ntuple_filter_alloc_output {
37068 /* The specific error status for the command. */
37069 uint16_t error_code;
37070 /* The HWRM command request type. */
37072 /* The sequence ID from the original command. */
37074 /* The length of the response data in number of bytes. */
37076 /* This value is an opaque id into CFA data structures. */
37077 uint64_t ntuple_filter_id;
37079 * The flow id value in bit 0-29 is the actual ID of the flow
37080 * associated with this filter and it shall be used to match
37081 * and associate the flow identifier returned in completion
37082 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
37083 * shall indicate no valid flow id.
37086 /* Indicate the flow id value. */
37087 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
37088 UINT32_C(0x3fffffff)
37089 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
37090 /* Indicate type of the flow. */
37091 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
37092 UINT32_C(0x40000000)
37094 * If this bit set to 0, then it indicates that the flow is
37097 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
37098 (UINT32_C(0x0) << 30)
37100 * If this bit is set to 1, then it indicates that the flow is
37103 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
37104 (UINT32_C(0x1) << 30)
37105 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
37106 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
37107 /* Indicate the flow direction. */
37108 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
37109 UINT32_C(0x80000000)
37110 /* If this bit set to 0, then it indicates rx flow. */
37111 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
37112 (UINT32_C(0x0) << 31)
37113 /* If this bit is set to 1, then it indicates that tx flow. */
37114 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
37115 (UINT32_C(0x1) << 31)
37116 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
37117 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
37118 uint8_t unused_0[3];
37120 * This field is used in Output records to indicate that the output
37121 * is completely written to RAM. This field should be read as '1'
37122 * to indicate that the output has been completely written.
37123 * When writing a command completion or response to an internal
37124 * processor, the order of writes has to be such that this field is
37130 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
37131 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
37133 * command specific error codes that goes to
37134 * the cmd_err field in Common HWRM Error Response.
37137 /* Unknown error */
37138 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
37140 /* Unable to complete operation due to conflict with Rx Mask VLAN */
37141 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
37143 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
37144 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
37145 uint8_t unused_0[7];
37148 /*******************************
37149 * hwrm_cfa_ntuple_filter_free *
37150 *******************************/
37153 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
37154 struct hwrm_cfa_ntuple_filter_free_input {
37155 /* The HWRM command request type. */
37158 * The completion ring to send the completion event on. This should
37159 * be the NQ ID returned from the `nq_alloc` HWRM command.
37161 uint16_t cmpl_ring;
37163 * The sequence ID is used by the driver for tracking multiple
37164 * commands. This ID is treated as opaque data by the firmware and
37165 * the value is returned in the `hwrm_resp_hdr` upon completion.
37169 * The target ID of the command:
37170 * * 0x0-0xFFF8 - The function ID
37171 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37172 * * 0xFFFD - Reserved for user-space HWRM interface
37175 uint16_t target_id;
37177 * A physical address pointer pointing to a host buffer that the
37178 * command's response data will be written. This can be either a host
37179 * physical address (HPA) or a guest physical address (GPA) and must
37180 * point to a physically contiguous block of memory.
37182 uint64_t resp_addr;
37183 /* This value is an opaque id into CFA data structures. */
37184 uint64_t ntuple_filter_id;
37187 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
37188 struct hwrm_cfa_ntuple_filter_free_output {
37189 /* The specific error status for the command. */
37190 uint16_t error_code;
37191 /* The HWRM command request type. */
37193 /* The sequence ID from the original command. */
37195 /* The length of the response data in number of bytes. */
37197 uint8_t unused_0[7];
37199 * This field is used in Output records to indicate that the output
37200 * is completely written to RAM. This field should be read as '1'
37201 * to indicate that the output has been completely written.
37202 * When writing a command completion or response to an internal
37203 * processor, the order of writes has to be such that this field is
37209 /******************************
37210 * hwrm_cfa_ntuple_filter_cfg *
37211 ******************************/
37214 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
37215 struct hwrm_cfa_ntuple_filter_cfg_input {
37216 /* The HWRM command request type. */
37219 * The completion ring to send the completion event on. This should
37220 * be the NQ ID returned from the `nq_alloc` HWRM command.
37222 uint16_t cmpl_ring;
37224 * The sequence ID is used by the driver for tracking multiple
37225 * commands. This ID is treated as opaque data by the firmware and
37226 * the value is returned in the `hwrm_resp_hdr` upon completion.
37230 * The target ID of the command:
37231 * * 0x0-0xFFF8 - The function ID
37232 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37233 * * 0xFFFD - Reserved for user-space HWRM interface
37236 uint16_t target_id;
37238 * A physical address pointer pointing to a host buffer that the
37239 * command's response data will be written. This can be either a host
37240 * physical address (HPA) or a guest physical address (GPA) and must
37241 * point to a physically contiguous block of memory.
37243 uint64_t resp_addr;
37246 * This bit must be '1' for the new_dst_id field to be
37249 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
37252 * This bit must be '1' for the new_mirror_vnic_id field to be
37255 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
37258 * This bit must be '1' for the new_meter_instance_id field to be
37261 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
37265 * Setting this bit to 1 indicates that dest_id field contains FID.
37266 * Setting this to 0 indicates that dest_id field contains VNIC or
37269 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
37272 * Setting of this flag indicates that the new_dst_id field contains
37273 * RFS ring table index. If this is not set it indicates new_dst_id
37274 * is VNIC or VPORT or function ID. Note dest_fid and
37275 * dest_rfs_ring_idx can’t be set at the same time.
37277 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
37279 /* This value is an opaque id into CFA data structures. */
37280 uint64_t ntuple_filter_id;
37282 * If set, this value shall represent the new
37283 * Logical VNIC ID of the destination VNIC for the RX
37284 * path and new network port id of the destination port for
37287 uint32_t new_dst_id;
37289 * New Logical VNIC ID of the VNIC where traffic is
37292 uint32_t new_mirror_vnic_id;
37294 * New meter to attach to the flow. Specifying the
37295 * invalid instance ID is used to remove any existing
37296 * meter from the flow.
37298 uint16_t new_meter_instance_id;
37300 * A value of 0xfff is considered invalid and implies the
37301 * instance is not configured.
37303 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
37305 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
37306 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
37307 uint8_t unused_1[6];
37310 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
37311 struct hwrm_cfa_ntuple_filter_cfg_output {
37312 /* The specific error status for the command. */
37313 uint16_t error_code;
37314 /* The HWRM command request type. */
37316 /* The sequence ID from the original command. */
37318 /* The length of the response data in number of bytes. */
37320 uint8_t unused_0[7];
37322 * This field is used in Output records to indicate that the output
37323 * is completely written to RAM. This field should be read as '1'
37324 * to indicate that the output has been completely written.
37325 * When writing a command completion or response to an internal
37326 * processor, the order of writes has to be such that this field is
37332 /**************************
37333 * hwrm_cfa_em_flow_alloc *
37334 **************************/
37337 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
37338 struct hwrm_cfa_em_flow_alloc_input {
37339 /* The HWRM command request type. */
37342 * The completion ring to send the completion event on. This should
37343 * be the NQ ID returned from the `nq_alloc` HWRM command.
37345 uint16_t cmpl_ring;
37347 * The sequence ID is used by the driver for tracking multiple
37348 * commands. This ID is treated as opaque data by the firmware and
37349 * the value is returned in the `hwrm_resp_hdr` upon completion.
37353 * The target ID of the command:
37354 * * 0x0-0xFFF8 - The function ID
37355 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37356 * * 0xFFFD - Reserved for user-space HWRM interface
37359 uint16_t target_id;
37361 * A physical address pointer pointing to a host buffer that the
37362 * command's response data will be written. This can be either a host
37363 * physical address (HPA) or a guest physical address (GPA) and must
37364 * point to a physically contiguous block of memory.
37366 uint64_t resp_addr;
37369 * Enumeration denoting the RX, TX type of the resource.
37370 * This enumeration is used for resources that are similar for both
37371 * TX and RX paths of the chip.
37373 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
37375 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37377 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37378 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
37379 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
37381 * Setting of this flag indicates enabling of a byte counter for a
37384 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
37386 * Setting of this flag indicates enabling of a packet counter for a
37389 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
37391 * Setting of this flag indicates de-capsulation action for the
37394 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
37396 * Setting of this flag indicates encapsulation action for the
37399 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
37401 * Setting of this flag indicates drop action. If this flag is not
37402 * set, then it should be considered accept action.
37404 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
37406 * Setting of this flag indicates that a meter is expected to be
37407 * attached to this flow. This hint can be used when choosing the
37408 * action record format required for the flow.
37410 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
37413 * This bit must be '1' for the l2_filter_id field to be
37416 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
37419 * This bit must be '1' for the tunnel_type field to be
37422 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
37425 * This bit must be '1' for the tunnel_id field to be
37428 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
37431 * This bit must be '1' for the src_macaddr field to be
37434 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
37437 * This bit must be '1' for the dst_macaddr field to be
37440 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
37443 * This bit must be '1' for the ovlan_vid field to be
37446 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
37449 * This bit must be '1' for the ivlan_vid field to be
37452 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
37455 * This bit must be '1' for the ethertype field to be
37458 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
37461 * This bit must be '1' for the src_ipaddr field to be
37464 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
37467 * This bit must be '1' for the dst_ipaddr field to be
37470 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
37473 * This bit must be '1' for the ipaddr_type field to be
37476 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
37479 * This bit must be '1' for the ip_protocol field to be
37482 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
37485 * This bit must be '1' for the src_port field to be
37488 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
37491 * This bit must be '1' for the dst_port field to be
37494 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
37497 * This bit must be '1' for the dst_id field to be
37500 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
37503 * This bit must be '1' for the mirror_vnic_id field to be
37506 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
37509 * This bit must be '1' for the encap_record_id field to be
37512 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
37515 * This bit must be '1' for the meter_instance_id field to be
37518 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
37521 * This value identifies a set of CFA data structures used for an L2
37524 uint64_t l2_filter_id;
37526 uint8_t tunnel_type;
37528 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
37530 /* Virtual eXtensible Local Area Network (VXLAN) */
37531 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
37533 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
37534 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
37536 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
37537 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
37540 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
37542 /* Generic Network Virtualization Encapsulation (Geneve) */
37543 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
37545 /* Multi-Protocol Label Switching (MPLS) */
37546 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
37548 /* Stateless Transport Tunnel (STT) */
37549 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
37551 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
37552 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
37554 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37555 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37558 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
37561 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37563 /* Use fixed layer 2 ether type of 0xFFFF */
37564 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
37567 * IPV6 over virtual eXtensible Local Area Network with GPE header
37570 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37572 /* Any tunneled traffic */
37573 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
37575 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
37576 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
37577 uint8_t unused_0[3];
37579 * Tunnel identifier.
37580 * Virtual Network Identifier (VNI). Only valid with
37581 * tunnel_types VXLAN, NVGRE, and Geneve.
37582 * Only lower 24-bits of VNI field are used
37583 * in setting up the filter.
37585 uint32_t tunnel_id;
37587 * This value indicates the source MAC address in
37588 * the Ethernet header.
37590 uint8_t src_macaddr[6];
37591 /* The meter instance to attach to the flow. */
37592 uint16_t meter_instance_id;
37594 * A value of 0xfff is considered invalid and implies the
37595 * instance is not configured.
37597 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
37599 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
37600 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
37602 * This value indicates the destination MAC address in
37603 * the Ethernet header.
37605 uint8_t dst_macaddr[6];
37607 * This value indicates the VLAN ID of the outer VLAN tag
37608 * in the Ethernet header.
37610 uint16_t ovlan_vid;
37612 * This value indicates the VLAN ID of the inner VLAN tag
37613 * in the Ethernet header.
37615 uint16_t ivlan_vid;
37616 /* This value indicates the ethertype in the Ethernet header. */
37617 uint16_t ethertype;
37619 * This value indicates the type of IP address.
37622 * All others are invalid.
37624 uint8_t ip_addr_type;
37626 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
37628 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
37630 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
37631 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
37632 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
37634 * The value of protocol filed in IP header.
37635 * Applies to UDP and TCP traffic.
37639 uint8_t ip_protocol;
37641 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
37643 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
37645 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
37646 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
37647 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
37648 uint8_t unused_1[2];
37650 * The value of source IP address to be used in filtering.
37651 * For IPv4, first four bytes represent the IP address.
37653 uint32_t src_ipaddr[4];
37655 * big_endian = True
37656 * The value of destination IP address to be used in filtering.
37657 * For IPv4, first four bytes represent the IP address.
37659 uint32_t dst_ipaddr[4];
37661 * The value of source port to be used in filtering.
37662 * Applies to UDP and TCP traffic.
37666 * The value of destination port to be used in filtering.
37667 * Applies to UDP and TCP traffic.
37671 * If set, this value shall represent the
37672 * Logical VNIC ID of the destination VNIC for the RX
37673 * path and network port id of the destination port for
37678 * Logical VNIC ID of the VNIC where traffic is
37681 uint16_t mirror_vnic_id;
37682 /* Logical ID of the encapsulation record. */
37683 uint32_t encap_record_id;
37684 uint8_t unused_2[4];
37687 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
37688 struct hwrm_cfa_em_flow_alloc_output {
37689 /* The specific error status for the command. */
37690 uint16_t error_code;
37691 /* The HWRM command request type. */
37693 /* The sequence ID from the original command. */
37695 /* The length of the response data in number of bytes. */
37697 /* This value is an opaque id into CFA data structures. */
37698 uint64_t em_filter_id;
37700 * The flow id value in bit 0-29 is the actual ID of the flow
37701 * associated with this filter and it shall be used to match
37702 * and associate the flow identifier returned in completion
37703 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
37704 * shall indicate no valid flow id.
37707 /* Indicate the flow id value. */
37708 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
37709 UINT32_C(0x3fffffff)
37710 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
37711 /* Indicate type of the flow. */
37712 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
37713 UINT32_C(0x40000000)
37715 * If this bit set to 0, then it indicates that the flow is
37718 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
37719 (UINT32_C(0x0) << 30)
37721 * If this bit is set to 1, then it indicates that the flow is
37724 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
37725 (UINT32_C(0x1) << 30)
37726 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
37727 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
37728 /* Indicate the flow direction. */
37729 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
37730 UINT32_C(0x80000000)
37731 /* If this bit set to 0, then it indicates rx flow. */
37732 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
37733 (UINT32_C(0x0) << 31)
37734 /* If this bit is set to 1, then it indicates that tx flow. */
37735 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
37736 (UINT32_C(0x1) << 31)
37737 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
37738 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
37739 uint8_t unused_0[3];
37741 * This field is used in Output records to indicate that the output
37742 * is completely written to RAM. This field should be read as '1'
37743 * to indicate that the output has been completely written.
37744 * When writing a command completion or response to an internal
37745 * processor, the order of writes has to be such that this field is
37751 /*************************
37752 * hwrm_cfa_em_flow_free *
37753 *************************/
37756 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
37757 struct hwrm_cfa_em_flow_free_input {
37758 /* The HWRM command request type. */
37761 * The completion ring to send the completion event on. This should
37762 * be the NQ ID returned from the `nq_alloc` HWRM command.
37764 uint16_t cmpl_ring;
37766 * The sequence ID is used by the driver for tracking multiple
37767 * commands. This ID is treated as opaque data by the firmware and
37768 * the value is returned in the `hwrm_resp_hdr` upon completion.
37772 * The target ID of the command:
37773 * * 0x0-0xFFF8 - The function ID
37774 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37775 * * 0xFFFD - Reserved for user-space HWRM interface
37778 uint16_t target_id;
37780 * A physical address pointer pointing to a host buffer that the
37781 * command's response data will be written. This can be either a host
37782 * physical address (HPA) or a guest physical address (GPA) and must
37783 * point to a physically contiguous block of memory.
37785 uint64_t resp_addr;
37786 /* This value is an opaque id into CFA data structures. */
37787 uint64_t em_filter_id;
37790 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
37791 struct hwrm_cfa_em_flow_free_output {
37792 /* The specific error status for the command. */
37793 uint16_t error_code;
37794 /* The HWRM command request type. */
37796 /* The sequence ID from the original command. */
37798 /* The length of the response data in number of bytes. */
37800 uint8_t unused_0[7];
37802 * This field is used in Output records to indicate that the output
37803 * is completely written to RAM. This field should be read as '1'
37804 * to indicate that the output has been completely written.
37805 * When writing a command completion or response to an internal
37806 * processor, the order of writes has to be such that this field is
37812 /************************
37813 * hwrm_cfa_meter_qcaps *
37814 ************************/
37817 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
37818 struct hwrm_cfa_meter_qcaps_input {
37819 /* The HWRM command request type. */
37822 * The completion ring to send the completion event on. This should
37823 * be the NQ ID returned from the `nq_alloc` HWRM command.
37825 uint16_t cmpl_ring;
37827 * The sequence ID is used by the driver for tracking multiple
37828 * commands. This ID is treated as opaque data by the firmware and
37829 * the value is returned in the `hwrm_resp_hdr` upon completion.
37833 * The target ID of the command:
37834 * * 0x0-0xFFF8 - The function ID
37835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37836 * * 0xFFFD - Reserved for user-space HWRM interface
37839 uint16_t target_id;
37841 * A physical address pointer pointing to a host buffer that the
37842 * command's response data will be written. This can be either a host
37843 * physical address (HPA) or a guest physical address (GPA) and must
37844 * point to a physically contiguous block of memory.
37846 uint64_t resp_addr;
37849 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
37850 struct hwrm_cfa_meter_qcaps_output {
37851 /* The specific error status for the command. */
37852 uint16_t error_code;
37853 /* The HWRM command request type. */
37855 /* The sequence ID from the original command. */
37857 /* The length of the response data in number of bytes. */
37861 * Enumeration denoting the clock at which the Meter is running
37862 * with. This enumeration is used for resources that are similar
37863 * for both TX and RX paths of the chip.
37865 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
37866 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
37868 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
37870 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
37871 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
37872 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
37873 uint8_t unused_0[4];
37875 * The minimum guaranteed number of tx meter profiles supported
37876 * for this function.
37878 uint16_t min_tx_profile;
37880 * The maximum non-guaranteed number of tx meter profiles supported
37881 * for this function.
37883 uint16_t max_tx_profile;
37885 * The minimum guaranteed number of rx meter profiles supported
37886 * for this function.
37888 uint16_t min_rx_profile;
37890 * The maximum non-guaranteed number of rx meter profiles supported
37891 * for this function.
37893 uint16_t max_rx_profile;
37895 * The minimum guaranteed number of tx meter instances supported
37896 * for this function.
37898 uint16_t min_tx_instance;
37900 * The maximum non-guaranteed number of tx meter instances supported
37901 * for this function.
37903 uint16_t max_tx_instance;
37905 * The minimum guaranteed number of rx meter instances supported
37906 * for this function.
37908 uint16_t min_rx_instance;
37910 * The maximum non-guaranteed number of rx meter instances supported
37911 * for this function.
37913 uint16_t max_rx_instance;
37914 uint8_t unused_1[7];
37916 * This field is used in Output records to indicate that the output
37917 * is completely written to RAM. This field should be read as '1'
37918 * to indicate that the output has been completely written.
37919 * When writing a command completion or response to an internal
37920 * processor, the order of writes has to be such that this field is
37926 /********************************
37927 * hwrm_cfa_meter_profile_alloc *
37928 ********************************/
37931 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
37932 struct hwrm_cfa_meter_profile_alloc_input {
37933 /* The HWRM command request type. */
37936 * The completion ring to send the completion event on. This should
37937 * be the NQ ID returned from the `nq_alloc` HWRM command.
37939 uint16_t cmpl_ring;
37941 * The sequence ID is used by the driver for tracking multiple
37942 * commands. This ID is treated as opaque data by the firmware and
37943 * the value is returned in the `hwrm_resp_hdr` upon completion.
37947 * The target ID of the command:
37948 * * 0x0-0xFFF8 - The function ID
37949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37950 * * 0xFFFD - Reserved for user-space HWRM interface
37953 uint16_t target_id;
37955 * A physical address pointer pointing to a host buffer that the
37956 * command's response data will be written. This can be either a host
37957 * physical address (HPA) or a guest physical address (GPA) and must
37958 * point to a physically contiguous block of memory.
37960 uint64_t resp_addr;
37963 * Enumeration denoting the RX, TX type of the resource.
37964 * This enumeration is used for resources that are similar for both
37965 * TX and RX paths of the chip.
37967 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
37969 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
37972 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
37974 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
37975 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
37976 /* The meter algorithm type. */
37977 uint8_t meter_type;
37978 /* RFC 2697 (srTCM) */
37979 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
37981 /* RFC 2698 (trTCM) */
37982 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
37984 /* RFC 4115 (trTCM) */
37985 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
37987 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
37988 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
37990 * This field is reserved for the future use.
37991 * It shall be set to 0.
37993 uint16_t reserved1;
37995 * This field is reserved for the future use.
37996 * It shall be set to 0.
37998 uint32_t reserved2;
37999 /* A meter rate specified in bytes-per-second. */
38000 uint32_t commit_rate;
38001 /* The bandwidth value. */
38002 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
38003 UINT32_C(0xfffffff)
38004 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
38006 /* The granularity of the value (bits or bytes). */
38007 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
38008 UINT32_C(0x10000000)
38009 /* Value is in bits. */
38010 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
38011 (UINT32_C(0x0) << 28)
38012 /* Value is in bytes. */
38013 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
38014 (UINT32_C(0x1) << 28)
38015 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
38016 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
38017 /* bw_value_unit is 3 b */
38018 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
38019 UINT32_C(0xe0000000)
38020 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
38022 /* Value is in Mb or MB (base 10). */
38023 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
38024 (UINT32_C(0x0) << 29)
38025 /* Value is in Kb or KB (base 10). */
38026 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
38027 (UINT32_C(0x2) << 29)
38028 /* Value is in bits or bytes. */
38029 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
38030 (UINT32_C(0x4) << 29)
38031 /* Value is in Gb or GB (base 10). */
38032 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
38033 (UINT32_C(0x6) << 29)
38034 /* Value is in 1/100th of a percentage of total bandwidth. */
38035 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
38036 (UINT32_C(0x1) << 29)
38038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
38039 (UINT32_C(0x7) << 29)
38040 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
38041 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
38042 /* A meter burst size specified in bytes. */
38043 uint32_t commit_burst;
38044 /* The bandwidth value. */
38045 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
38046 UINT32_C(0xfffffff)
38047 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
38049 /* The granularity of the value (bits or bytes). */
38050 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
38051 UINT32_C(0x10000000)
38052 /* Value is in bits. */
38053 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
38054 (UINT32_C(0x0) << 28)
38055 /* Value is in bytes. */
38056 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
38057 (UINT32_C(0x1) << 28)
38058 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
38059 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
38060 /* bw_value_unit is 3 b */
38061 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
38062 UINT32_C(0xe0000000)
38063 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
38065 /* Value is in Mb or MB (base 10). */
38066 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
38067 (UINT32_C(0x0) << 29)
38068 /* Value is in Kb or KB (base 10). */
38069 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
38070 (UINT32_C(0x2) << 29)
38071 /* Value is in bits or bytes. */
38072 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
38073 (UINT32_C(0x4) << 29)
38074 /* Value is in Gb or GB (base 10). */
38075 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
38076 (UINT32_C(0x6) << 29)
38077 /* Value is in 1/100th of a percentage of total bandwidth. */
38078 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
38079 (UINT32_C(0x1) << 29)
38080 /* Invalid value */
38081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
38082 (UINT32_C(0x7) << 29)
38083 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
38084 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
38085 /* A meter rate specified in bytes-per-second. */
38086 uint32_t excess_peak_rate;
38087 /* The bandwidth value. */
38088 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
38089 UINT32_C(0xfffffff)
38090 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
38092 /* The granularity of the value (bits or bytes). */
38093 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
38094 UINT32_C(0x10000000)
38095 /* Value is in bits. */
38096 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
38097 (UINT32_C(0x0) << 28)
38098 /* Value is in bytes. */
38099 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
38100 (UINT32_C(0x1) << 28)
38101 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
38102 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
38103 /* bw_value_unit is 3 b */
38104 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
38105 UINT32_C(0xe0000000)
38106 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
38108 /* Value is in Mb or MB (base 10). */
38109 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
38110 (UINT32_C(0x0) << 29)
38111 /* Value is in Kb or KB (base 10). */
38112 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
38113 (UINT32_C(0x2) << 29)
38114 /* Value is in bits or bytes. */
38115 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
38116 (UINT32_C(0x4) << 29)
38117 /* Value is in Gb or GB (base 10). */
38118 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
38119 (UINT32_C(0x6) << 29)
38120 /* Value is in 1/100th of a percentage of total bandwidth. */
38121 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
38122 (UINT32_C(0x1) << 29)
38124 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
38125 (UINT32_C(0x7) << 29)
38126 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
38127 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
38128 /* A meter burst size specified in bytes. */
38129 uint32_t excess_peak_burst;
38130 /* The bandwidth value. */
38131 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
38132 UINT32_C(0xfffffff)
38133 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
38135 /* The granularity of the value (bits or bytes). */
38136 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
38137 UINT32_C(0x10000000)
38138 /* Value is in bits. */
38139 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
38140 (UINT32_C(0x0) << 28)
38141 /* Value is in bytes. */
38142 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
38143 (UINT32_C(0x1) << 28)
38144 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
38145 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
38146 /* bw_value_unit is 3 b */
38147 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
38148 UINT32_C(0xe0000000)
38149 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
38151 /* Value is in Mb or MB (base 10). */
38152 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
38153 (UINT32_C(0x0) << 29)
38154 /* Value is in Kb or KB (base 10). */
38155 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
38156 (UINT32_C(0x2) << 29)
38157 /* Value is in bits or bytes. */
38158 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
38159 (UINT32_C(0x4) << 29)
38160 /* Value is in Gb or GB (base 10). */
38161 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
38162 (UINT32_C(0x6) << 29)
38163 /* Value is in 1/100th of a percentage of total bandwidth. */
38164 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
38165 (UINT32_C(0x1) << 29)
38167 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
38168 (UINT32_C(0x7) << 29)
38169 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
38170 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
38173 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
38174 struct hwrm_cfa_meter_profile_alloc_output {
38175 /* The specific error status for the command. */
38176 uint16_t error_code;
38177 /* The HWRM command request type. */
38179 /* The sequence ID from the original command. */
38181 /* The length of the response data in number of bytes. */
38183 /* This value identifies a meter profile in CFA. */
38184 uint16_t meter_profile_id;
38186 * A value of 0xfff is considered invalid and implies the
38187 * profile is not configured.
38189 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
38191 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
38192 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
38193 uint8_t unused_0[5];
38195 * This field is used in Output records to indicate that the output
38196 * is completely written to RAM. This field should be read as '1'
38197 * to indicate that the output has been completely written.
38198 * When writing a command completion or response to an internal
38199 * processor, the order of writes has to be such that this field is
38205 /*******************************
38206 * hwrm_cfa_meter_profile_free *
38207 *******************************/
38210 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
38211 struct hwrm_cfa_meter_profile_free_input {
38212 /* The HWRM command request type. */
38215 * The completion ring to send the completion event on. This should
38216 * be the NQ ID returned from the `nq_alloc` HWRM command.
38218 uint16_t cmpl_ring;
38220 * The sequence ID is used by the driver for tracking multiple
38221 * commands. This ID is treated as opaque data by the firmware and
38222 * the value is returned in the `hwrm_resp_hdr` upon completion.
38226 * The target ID of the command:
38227 * * 0x0-0xFFF8 - The function ID
38228 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38229 * * 0xFFFD - Reserved for user-space HWRM interface
38232 uint16_t target_id;
38234 * A physical address pointer pointing to a host buffer that the
38235 * command's response data will be written. This can be either a host
38236 * physical address (HPA) or a guest physical address (GPA) and must
38237 * point to a physically contiguous block of memory.
38239 uint64_t resp_addr;
38242 * Enumeration denoting the RX, TX type of the resource.
38243 * This enumeration is used for resources that are similar for both
38244 * TX and RX paths of the chip.
38246 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
38248 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
38251 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
38253 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
38254 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
38256 /* This value identifies a meter profile in CFA. */
38257 uint16_t meter_profile_id;
38259 * A value of 0xfff is considered invalid and implies the
38260 * profile is not configured.
38262 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
38264 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
38265 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
38266 uint8_t unused_1[4];
38269 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
38270 struct hwrm_cfa_meter_profile_free_output {
38271 /* The specific error status for the command. */
38272 uint16_t error_code;
38273 /* The HWRM command request type. */
38275 /* The sequence ID from the original command. */
38277 /* The length of the response data in number of bytes. */
38279 uint8_t unused_0[7];
38281 * This field is used in Output records to indicate that the output
38282 * is completely written to RAM. This field should be read as '1'
38283 * to indicate that the output has been completely written.
38284 * When writing a command completion or response to an internal
38285 * processor, the order of writes has to be such that this field is
38291 /******************************
38292 * hwrm_cfa_meter_profile_cfg *
38293 ******************************/
38296 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
38297 struct hwrm_cfa_meter_profile_cfg_input {
38298 /* The HWRM command request type. */
38301 * The completion ring to send the completion event on. This should
38302 * be the NQ ID returned from the `nq_alloc` HWRM command.
38304 uint16_t cmpl_ring;
38306 * The sequence ID is used by the driver for tracking multiple
38307 * commands. This ID is treated as opaque data by the firmware and
38308 * the value is returned in the `hwrm_resp_hdr` upon completion.
38312 * The target ID of the command:
38313 * * 0x0-0xFFF8 - The function ID
38314 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38315 * * 0xFFFD - Reserved for user-space HWRM interface
38318 uint16_t target_id;
38320 * A physical address pointer pointing to a host buffer that the
38321 * command's response data will be written. This can be either a host
38322 * physical address (HPA) or a guest physical address (GPA) and must
38323 * point to a physically contiguous block of memory.
38325 uint64_t resp_addr;
38328 * Enumeration denoting the RX, TX type of the resource.
38329 * This enumeration is used for resources that are similar for both
38330 * TX and RX paths of the chip.
38332 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
38334 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
38336 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
38337 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
38338 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
38339 /* The meter algorithm type. */
38340 uint8_t meter_type;
38341 /* RFC 2697 (srTCM) */
38342 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
38344 /* RFC 2698 (trTCM) */
38345 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
38347 /* RFC 4115 (trTCM) */
38348 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
38350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
38351 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
38352 /* This value identifies a meter profile in CFA. */
38353 uint16_t meter_profile_id;
38355 * A value of 0xfff is considered invalid and implies the
38356 * profile is not configured.
38358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
38360 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
38361 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
38363 * This field is reserved for the future use.
38364 * It shall be set to 0.
38367 /* A meter rate specified in bytes-per-second. */
38368 uint32_t commit_rate;
38369 /* The bandwidth value. */
38370 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
38371 UINT32_C(0xfffffff)
38372 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
38374 /* The granularity of the value (bits or bytes). */
38375 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
38376 UINT32_C(0x10000000)
38377 /* Value is in bits. */
38378 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
38379 (UINT32_C(0x0) << 28)
38380 /* Value is in bytes. */
38381 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
38382 (UINT32_C(0x1) << 28)
38383 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
38384 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
38385 /* bw_value_unit is 3 b */
38386 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
38387 UINT32_C(0xe0000000)
38388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
38390 /* Value is in Mb or MB (base 10). */
38391 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
38392 (UINT32_C(0x0) << 29)
38393 /* Value is in Kb or KB (base 10). */
38394 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
38395 (UINT32_C(0x2) << 29)
38396 /* Value is in bits or bytes. */
38397 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
38398 (UINT32_C(0x4) << 29)
38399 /* Value is in Gb or GB (base 10). */
38400 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
38401 (UINT32_C(0x6) << 29)
38402 /* Value is in 1/100th of a percentage of total bandwidth. */
38403 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
38404 (UINT32_C(0x1) << 29)
38406 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
38407 (UINT32_C(0x7) << 29)
38408 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
38409 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
38410 /* A meter burst size specified in bytes. */
38411 uint32_t commit_burst;
38412 /* The bandwidth value. */
38413 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
38414 UINT32_C(0xfffffff)
38415 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
38417 /* The granularity of the value (bits or bytes). */
38418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
38419 UINT32_C(0x10000000)
38420 /* Value is in bits. */
38421 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
38422 (UINT32_C(0x0) << 28)
38423 /* Value is in bytes. */
38424 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
38425 (UINT32_C(0x1) << 28)
38426 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
38427 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
38428 /* bw_value_unit is 3 b */
38429 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
38430 UINT32_C(0xe0000000)
38431 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
38433 /* Value is in Mb or MB (base 10). */
38434 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
38435 (UINT32_C(0x0) << 29)
38436 /* Value is in Kb or KB (base 10). */
38437 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
38438 (UINT32_C(0x2) << 29)
38439 /* Value is in bits or bytes. */
38440 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
38441 (UINT32_C(0x4) << 29)
38442 /* Value is in Gb or GB (base 10). */
38443 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
38444 (UINT32_C(0x6) << 29)
38445 /* Value is in 1/100th of a percentage of total bandwidth. */
38446 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
38447 (UINT32_C(0x1) << 29)
38448 /* Invalid value */
38449 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
38450 (UINT32_C(0x7) << 29)
38451 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
38452 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
38453 /* A meter rate specified in bytes-per-second. */
38454 uint32_t excess_peak_rate;
38455 /* The bandwidth value. */
38456 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
38457 UINT32_C(0xfffffff)
38458 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
38460 /* The granularity of the value (bits or bytes). */
38461 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
38462 UINT32_C(0x10000000)
38463 /* Value is in bits. */
38464 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
38465 (UINT32_C(0x0) << 28)
38466 /* Value is in bytes. */
38467 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
38468 (UINT32_C(0x1) << 28)
38469 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
38470 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
38471 /* bw_value_unit is 3 b */
38472 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
38473 UINT32_C(0xe0000000)
38474 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
38476 /* Value is in Mb or MB (base 10). */
38477 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
38478 (UINT32_C(0x0) << 29)
38479 /* Value is in Kb or KB (base 10). */
38480 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
38481 (UINT32_C(0x2) << 29)
38482 /* Value is in bits or bytes. */
38483 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
38484 (UINT32_C(0x4) << 29)
38485 /* Value is in Gb or GB (base 10). */
38486 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
38487 (UINT32_C(0x6) << 29)
38488 /* Value is in 1/100th of a percentage of total bandwidth. */
38489 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
38490 (UINT32_C(0x1) << 29)
38492 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
38493 (UINT32_C(0x7) << 29)
38494 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
38495 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
38496 /* A meter burst size specified in bytes. */
38497 uint32_t excess_peak_burst;
38498 /* The bandwidth value. */
38499 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
38500 UINT32_C(0xfffffff)
38501 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
38503 /* The granularity of the value (bits or bytes). */
38504 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
38505 UINT32_C(0x10000000)
38506 /* Value is in bits. */
38507 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
38508 (UINT32_C(0x0) << 28)
38509 /* Value is in bytes. */
38510 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
38511 (UINT32_C(0x1) << 28)
38512 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
38513 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
38514 /* bw_value_unit is 3 b */
38515 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
38516 UINT32_C(0xe0000000)
38517 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
38519 /* Value is in Mb or MB (base 10). */
38520 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
38521 (UINT32_C(0x0) << 29)
38522 /* Value is in Kb or KB (base 10). */
38523 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
38524 (UINT32_C(0x2) << 29)
38525 /* Value is in bits or bytes. */
38526 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
38527 (UINT32_C(0x4) << 29)
38528 /* Value is in Gb or GB (base 10). */
38529 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
38530 (UINT32_C(0x6) << 29)
38531 /* Value is in 1/100th of a percentage of total bandwidth. */
38532 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
38533 (UINT32_C(0x1) << 29)
38535 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
38536 (UINT32_C(0x7) << 29)
38537 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
38538 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
38541 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
38542 struct hwrm_cfa_meter_profile_cfg_output {
38543 /* The specific error status for the command. */
38544 uint16_t error_code;
38545 /* The HWRM command request type. */
38547 /* The sequence ID from the original command. */
38549 /* The length of the response data in number of bytes. */
38551 uint8_t unused_0[7];
38553 * This field is used in Output records to indicate that the output
38554 * is completely written to RAM. This field should be read as '1'
38555 * to indicate that the output has been completely written.
38556 * When writing a command completion or response to an internal
38557 * processor, the order of writes has to be such that this field is
38563 /*********************************
38564 * hwrm_cfa_meter_instance_alloc *
38565 *********************************/
38568 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
38569 struct hwrm_cfa_meter_instance_alloc_input {
38570 /* The HWRM command request type. */
38573 * The completion ring to send the completion event on. This should
38574 * be the NQ ID returned from the `nq_alloc` HWRM command.
38576 uint16_t cmpl_ring;
38578 * The sequence ID is used by the driver for tracking multiple
38579 * commands. This ID is treated as opaque data by the firmware and
38580 * the value is returned in the `hwrm_resp_hdr` upon completion.
38584 * The target ID of the command:
38585 * * 0x0-0xFFF8 - The function ID
38586 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38587 * * 0xFFFD - Reserved for user-space HWRM interface
38590 uint16_t target_id;
38592 * A physical address pointer pointing to a host buffer that the
38593 * command's response data will be written. This can be either a host
38594 * physical address (HPA) or a guest physical address (GPA) and must
38595 * point to a physically contiguous block of memory.
38597 uint64_t resp_addr;
38600 * Enumeration denoting the RX, TX type of the resource.
38601 * This enumeration is used for resources that are similar for both
38602 * TX and RX paths of the chip.
38604 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
38607 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
38610 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
38612 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
38613 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
38615 /* This value identifies a meter profile in CFA. */
38616 uint16_t meter_profile_id;
38618 * A value of 0xffff is considered invalid and implies the
38619 * profile is not configured.
38621 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
38623 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
38624 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
38625 uint8_t unused_1[4];
38628 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
38629 struct hwrm_cfa_meter_instance_alloc_output {
38630 /* The specific error status for the command. */
38631 uint16_t error_code;
38632 /* The HWRM command request type. */
38634 /* The sequence ID from the original command. */
38636 /* The length of the response data in number of bytes. */
38638 /* This value identifies a meter instance in CFA. */
38639 uint16_t meter_instance_id;
38641 * A value of 0xffff is considered invalid and implies the
38642 * instance is not configured.
38644 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
38646 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
38647 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
38648 uint8_t unused_0[5];
38650 * This field is used in Output records to indicate that the output
38651 * is completely written to RAM. This field should be read as '1'
38652 * to indicate that the output has been completely written.
38653 * When writing a command completion or response to an internal
38654 * processor, the order of writes has to be such that this field is
38660 /*******************************
38661 * hwrm_cfa_meter_instance_cfg *
38662 *******************************/
38665 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
38666 struct hwrm_cfa_meter_instance_cfg_input {
38667 /* The HWRM command request type. */
38670 * The completion ring to send the completion event on. This should
38671 * be the NQ ID returned from the `nq_alloc` HWRM command.
38673 uint16_t cmpl_ring;
38675 * The sequence ID is used by the driver for tracking multiple
38676 * commands. This ID is treated as opaque data by the firmware and
38677 * the value is returned in the `hwrm_resp_hdr` upon completion.
38681 * The target ID of the command:
38682 * * 0x0-0xFFF8 - The function ID
38683 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38684 * * 0xFFFD - Reserved for user-space HWRM interface
38687 uint16_t target_id;
38689 * A physical address pointer pointing to a host buffer that the
38690 * command's response data will be written. This can be either a host
38691 * physical address (HPA) or a guest physical address (GPA) and must
38692 * point to a physically contiguous block of memory.
38694 uint64_t resp_addr;
38697 * Enumeration denoting the RX, TX type of the resource.
38698 * This enumeration is used for resources that are similar for both
38699 * TX and RX paths of the chip.
38701 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
38703 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
38706 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
38708 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
38709 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
38712 * This value identifies a new meter profile to be associated with
38713 * the meter instance specified in this command.
38715 uint16_t meter_profile_id;
38717 * A value of 0xffff is considered invalid and implies the
38718 * profile is not configured.
38720 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
38722 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
38723 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
38725 * This value identifies the ID of a meter instance that needs to be
38726 * updated with a new meter profile specified in this command.
38728 uint16_t meter_instance_id;
38729 uint8_t unused_1[2];
38732 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
38733 struct hwrm_cfa_meter_instance_cfg_output {
38734 /* The specific error status for the command. */
38735 uint16_t error_code;
38736 /* The HWRM command request type. */
38738 /* The sequence ID from the original command. */
38740 /* The length of the response data in number of bytes. */
38742 uint8_t unused_0[7];
38744 * This field is used in Output records to indicate that the output
38745 * is completely written to RAM. This field should be read as '1'
38746 * to indicate that the output has been completely written.
38747 * When writing a command completion or response to an internal
38748 * processor, the order of writes has to be such that this field is
38754 /********************************
38755 * hwrm_cfa_meter_instance_free *
38756 ********************************/
38759 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
38760 struct hwrm_cfa_meter_instance_free_input {
38761 /* The HWRM command request type. */
38764 * The completion ring to send the completion event on. This should
38765 * be the NQ ID returned from the `nq_alloc` HWRM command.
38767 uint16_t cmpl_ring;
38769 * The sequence ID is used by the driver for tracking multiple
38770 * commands. This ID is treated as opaque data by the firmware and
38771 * the value is returned in the `hwrm_resp_hdr` upon completion.
38775 * The target ID of the command:
38776 * * 0x0-0xFFF8 - The function ID
38777 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38778 * * 0xFFFD - Reserved for user-space HWRM interface
38781 uint16_t target_id;
38783 * A physical address pointer pointing to a host buffer that the
38784 * command's response data will be written. This can be either a host
38785 * physical address (HPA) or a guest physical address (GPA) and must
38786 * point to a physically contiguous block of memory.
38788 uint64_t resp_addr;
38791 * Enumeration denoting the RX, TX type of the resource.
38792 * This enumeration is used for resources that are similar for both
38793 * TX and RX paths of the chip.
38795 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
38797 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
38800 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
38802 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
38803 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
38805 /* This value identifies a meter instance in CFA. */
38806 uint16_t meter_instance_id;
38808 * A value of 0xfff is considered invalid and implies the
38809 * instance is not configured.
38811 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
38813 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
38814 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
38815 uint8_t unused_1[4];
38818 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
38819 struct hwrm_cfa_meter_instance_free_output {
38820 /* The specific error status for the command. */
38821 uint16_t error_code;
38822 /* The HWRM command request type. */
38824 /* The sequence ID from the original command. */
38826 /* The length of the response data in number of bytes. */
38828 uint8_t unused_0[7];
38830 * This field is used in Output records to indicate that the output
38831 * is completely written to RAM. This field should be read as '1'
38832 * to indicate that the output has been completely written.
38833 * When writing a command completion or response to an internal
38834 * processor, the order of writes has to be such that this field is
38840 /*******************************
38841 * hwrm_cfa_decap_filter_alloc *
38842 *******************************/
38845 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
38846 struct hwrm_cfa_decap_filter_alloc_input {
38847 /* The HWRM command request type. */
38850 * The completion ring to send the completion event on. This should
38851 * be the NQ ID returned from the `nq_alloc` HWRM command.
38853 uint16_t cmpl_ring;
38855 * The sequence ID is used by the driver for tracking multiple
38856 * commands. This ID is treated as opaque data by the firmware and
38857 * the value is returned in the `hwrm_resp_hdr` upon completion.
38861 * The target ID of the command:
38862 * * 0x0-0xFFF8 - The function ID
38863 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38864 * * 0xFFFD - Reserved for user-space HWRM interface
38867 uint16_t target_id;
38869 * A physical address pointer pointing to a host buffer that the
38870 * command's response data will be written. This can be either a host
38871 * physical address (HPA) or a guest physical address (GPA) and must
38872 * point to a physically contiguous block of memory.
38874 uint64_t resp_addr;
38876 /* ovs_tunnel is 1 b */
38877 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
38881 * This bit must be '1' for the tunnel_type field to be
38884 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
38887 * This bit must be '1' for the tunnel_id field to be
38890 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
38893 * This bit must be '1' for the src_macaddr field to be
38896 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
38899 * This bit must be '1' for the dst_macaddr field to be
38902 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
38905 * This bit must be '1' for the ovlan_vid field to be
38908 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
38911 * This bit must be '1' for the ivlan_vid field to be
38914 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
38917 * This bit must be '1' for the t_ovlan_vid field to be
38920 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
38923 * This bit must be '1' for the t_ivlan_vid field to be
38926 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
38929 * This bit must be '1' for the ethertype field to be
38932 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
38935 * This bit must be '1' for the src_ipaddr field to be
38938 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
38941 * This bit must be '1' for the dst_ipaddr field to be
38944 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
38947 * This bit must be '1' for the ipaddr_type field to be
38950 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
38953 * This bit must be '1' for the ip_protocol field to be
38956 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
38959 * This bit must be '1' for the src_port field to be
38962 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
38965 * This bit must be '1' for the dst_port field to be
38968 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
38971 * This bit must be '1' for the dst_id field to be
38974 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
38977 * This bit must be '1' for the mirror_vnic_id field to be
38980 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
38983 * Tunnel identifier.
38984 * Virtual Network Identifier (VNI). Only valid with
38985 * tunnel_types VXLAN, NVGRE, and Geneve.
38986 * Only lower 24-bits of VNI field are used
38987 * in setting up the filter.
38989 uint32_t tunnel_id;
38991 uint8_t tunnel_type;
38993 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
38995 /* Virtual eXtensible Local Area Network (VXLAN) */
38996 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
38998 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38999 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
39001 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
39002 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
39005 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
39007 /* Generic Network Virtualization Encapsulation (Geneve) */
39008 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39010 /* Multi-Protocol Label Switching (MPLS) */
39011 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
39013 /* Stateless Transport Tunnel (STT) */
39014 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
39016 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39017 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
39019 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39020 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39023 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39026 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39028 /* Use fixed layer 2 ether type of 0xFFFF */
39029 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39032 * IPV6 over virtual eXtensible Local Area Network with GPE header
39035 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39037 /* Any tunneled traffic */
39038 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
39040 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39041 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
39045 * This value indicates the source MAC address in
39046 * the Ethernet header.
39048 uint8_t src_macaddr[6];
39049 uint8_t unused_2[2];
39051 * This value indicates the destination MAC address in
39052 * the Ethernet header.
39054 uint8_t dst_macaddr[6];
39056 * This value indicates the VLAN ID of the outer VLAN tag
39057 * in the Ethernet header.
39059 uint16_t ovlan_vid;
39061 * This value indicates the VLAN ID of the inner VLAN tag
39062 * in the Ethernet header.
39064 uint16_t ivlan_vid;
39066 * This value indicates the VLAN ID of the outer VLAN tag
39067 * in the tunnel Ethernet header.
39069 uint16_t t_ovlan_vid;
39071 * This value indicates the VLAN ID of the inner VLAN tag
39072 * in the tunnel Ethernet header.
39074 uint16_t t_ivlan_vid;
39075 /* This value indicates the ethertype in the Ethernet header. */
39076 uint16_t ethertype;
39078 * This value indicates the type of IP address.
39081 * All others are invalid.
39083 uint8_t ip_addr_type;
39085 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
39088 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
39091 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
39093 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
39094 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
39096 * The value of protocol filed in IP header.
39097 * Applies to UDP and TCP traffic.
39101 uint8_t ip_protocol;
39103 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
39106 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
39109 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
39111 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
39112 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
39116 * The value of source IP address to be used in filtering.
39117 * For IPv4, first four bytes represent the IP address.
39119 uint32_t src_ipaddr[4];
39121 * The value of destination IP address to be used in filtering.
39122 * For IPv4, first four bytes represent the IP address.
39124 uint32_t dst_ipaddr[4];
39126 * The value of source port to be used in filtering.
39127 * Applies to UDP and TCP traffic.
39131 * The value of destination port to be used in filtering.
39132 * Applies to UDP and TCP traffic.
39136 * If set, this value shall represent the
39137 * Logical VNIC ID of the destination VNIC for the RX
39142 * If set, this value shall represent the L2 context that matches the
39143 * L2 information of the decap filter.
39145 uint16_t l2_ctxt_ref_id;
39148 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
39149 struct hwrm_cfa_decap_filter_alloc_output {
39150 /* The specific error status for the command. */
39151 uint16_t error_code;
39152 /* The HWRM command request type. */
39154 /* The sequence ID from the original command. */
39156 /* The length of the response data in number of bytes. */
39158 /* This value is an opaque id into CFA data structures. */
39159 uint32_t decap_filter_id;
39160 uint8_t unused_0[3];
39162 * This field is used in Output records to indicate that the output
39163 * is completely written to RAM. This field should be read as '1'
39164 * to indicate that the output has been completely written.
39165 * When writing a command completion or response to an internal
39166 * processor, the order of writes has to be such that this field is
39172 /******************************
39173 * hwrm_cfa_decap_filter_free *
39174 ******************************/
39177 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
39178 struct hwrm_cfa_decap_filter_free_input {
39179 /* The HWRM command request type. */
39182 * The completion ring to send the completion event on. This should
39183 * be the NQ ID returned from the `nq_alloc` HWRM command.
39185 uint16_t cmpl_ring;
39187 * The sequence ID is used by the driver for tracking multiple
39188 * commands. This ID is treated as opaque data by the firmware and
39189 * the value is returned in the `hwrm_resp_hdr` upon completion.
39193 * The target ID of the command:
39194 * * 0x0-0xFFF8 - The function ID
39195 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39196 * * 0xFFFD - Reserved for user-space HWRM interface
39199 uint16_t target_id;
39201 * A physical address pointer pointing to a host buffer that the
39202 * command's response data will be written. This can be either a host
39203 * physical address (HPA) or a guest physical address (GPA) and must
39204 * point to a physically contiguous block of memory.
39206 uint64_t resp_addr;
39207 /* This value is an opaque id into CFA data structures. */
39208 uint32_t decap_filter_id;
39209 uint8_t unused_0[4];
39212 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
39213 struct hwrm_cfa_decap_filter_free_output {
39214 /* The specific error status for the command. */
39215 uint16_t error_code;
39216 /* The HWRM command request type. */
39218 /* The sequence ID from the original command. */
39220 /* The length of the response data in number of bytes. */
39222 uint8_t unused_0[7];
39224 * This field is used in Output records to indicate that the output
39225 * is completely written to RAM. This field should be read as '1'
39226 * to indicate that the output has been completely written.
39227 * When writing a command completion or response to an internal
39228 * processor, the order of writes has to be such that this field is
39234 /***********************
39235 * hwrm_cfa_flow_alloc *
39236 ***********************/
39239 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
39240 struct hwrm_cfa_flow_alloc_input {
39241 /* The HWRM command request type. */
39244 * The completion ring to send the completion event on. This should
39245 * be the NQ ID returned from the `nq_alloc` HWRM command.
39247 uint16_t cmpl_ring;
39249 * The sequence ID is used by the driver for tracking multiple
39250 * commands. This ID is treated as opaque data by the firmware and
39251 * the value is returned in the `hwrm_resp_hdr` upon completion.
39255 * The target ID of the command:
39256 * * 0x0-0xFFF8 - The function ID
39257 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39258 * * 0xFFFD - Reserved for user-space HWRM interface
39261 uint16_t target_id;
39263 * A physical address pointer pointing to a host buffer that the
39264 * command's response data will be written. This can be either a host
39265 * physical address (HPA) or a guest physical address (GPA) and must
39266 * point to a physically contiguous block of memory.
39268 uint64_t resp_addr;
39270 /* tunnel is 1 b */
39271 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
39273 /* num_vlan is 2 b */
39274 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
39276 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
39278 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
39279 (UINT32_C(0x0) << 1)
39281 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
39282 (UINT32_C(0x1) << 1)
39284 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
39285 (UINT32_C(0x2) << 1)
39286 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
39287 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
39288 /* Enumeration denoting the Flow Type. */
39289 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
39291 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
39293 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
39294 (UINT32_C(0x0) << 3)
39296 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
39297 (UINT32_C(0x1) << 3)
39299 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
39300 (UINT32_C(0x2) << 3)
39301 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
39302 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
39304 * when set to 1, indicates TX flow offload for function specified
39305 * in src_fid and the dst_fid should be set to invalid value. To
39306 * indicate a VM to VM flow, both of the path_tx and path_rx flags
39307 * need to be set. For virtio vSwitch offload case, the src_fid and
39308 * dst_fid is set to the same fid value. For the SRIOV vSwitch
39309 * offload case, the src_fid and dst_fid must be set to the same VF
39310 * FID belong to the children VFs of the same PF to indicate VM to
39313 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
39316 * when set to 1, indicates RX flow offload for function specified
39317 * in dst_fid and the src_fid should be set to invalid value.
39319 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
39322 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
39323 * header is required and the VXLAN VNI value is stored in the first
39324 * 24 bits of the dmac field. This flag is only valid when the flow
39327 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
39330 * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
39333 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
39340 /* Tunnel handle valid when tunnel flag is set. */
39341 uint32_t tunnel_handle;
39342 uint16_t action_flags;
39344 * Setting of this flag indicates drop action. If this flag is not
39345 * set, then it should be considered accept action.
39347 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
39349 /* recycle is 1 b */
39350 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
39353 * Setting of this flag indicates drop action. If this flag is not
39354 * set, then it should be considered accept action.
39356 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
39359 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
39361 /* tunnel is 1 b */
39362 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
39364 /* nat_src is 1 b */
39365 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
39367 /* nat_dest is 1 b */
39368 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
39370 /* nat_ipv4_address is 1 b */
39371 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
39373 /* l2_header_rewrite is 1 b */
39374 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
39376 /* ttl_decrement is 1 b */
39377 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
39380 * If set to 1 and flow direction is TX, it indicates decap of L2
39381 * header and encap of tunnel header. If set to 1 and flow direction
39382 * is RX, it indicates decap of tunnel header and encap L2 header.
39383 * The type of tunnel is specified in the tunnel_type field.
39385 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
39387 /* If set to 1, flow aging is enabled for this flow. */
39388 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
39391 * If set to 1 an attempt will be made to try to offload this flow
39392 * to the most optimal flow table resource. If set to 0, the flow
39393 * will be placed to the default flow table resource.
39395 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
39398 * If set to 1 there will be no attempt to allocate an on-chip try
39399 * to offload this flow. If set to 0, which will keep compatibility
39400 * with the older drivers, will cause the FW to attempt to allocate
39401 * an on-chip flow counter for the newly created flow. This will
39402 * keep the existing behavior with EM flows which always had an
39403 * associated flow counter.
39405 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
39408 * Tx Flow: pf or vf fid.
39412 /* VLAN tpid, valid when push_vlan flag is set. */
39413 uint16_t l2_rewrite_vlan_tpid;
39414 /* VLAN tci, valid when push_vlan flag is set. */
39415 uint16_t l2_rewrite_vlan_tci;
39416 /* Meter id, valid when meter flag is set. */
39417 uint16_t act_meter_id;
39418 /* Flow with the same l2 context tcam key. */
39419 uint16_t ref_flow_handle;
39420 /* This value sets the match value for the ethertype. */
39421 uint16_t ethertype;
39422 /* valid when num tags is 1 or 2. */
39423 uint16_t outer_vlan_tci;
39424 /* This value sets the match value for the Destination MAC address. */
39426 /* valid when num tags is 2. */
39427 uint16_t inner_vlan_tci;
39428 /* This value sets the match value for the Source MAC address. */
39430 /* The bit length of destination IP address mask. */
39431 uint8_t ip_dst_mask_len;
39432 /* The bit length of source IP address mask. */
39433 uint8_t ip_src_mask_len;
39434 /* The value of destination IPv4/IPv6 address. */
39435 uint32_t ip_dst[4];
39436 /* The source IPv4/IPv6 address. */
39437 uint32_t ip_src[4];
39439 * The value of source port.
39440 * Applies to UDP and TCP traffic.
39442 uint16_t l4_src_port;
39444 * The value of source port mask.
39445 * Applies to UDP and TCP traffic.
39447 uint16_t l4_src_port_mask;
39449 * The value of destination port.
39450 * Applies to UDP and TCP traffic.
39452 uint16_t l4_dst_port;
39454 * The value of destination port mask.
39455 * Applies to UDP and TCP traffic.
39457 uint16_t l4_dst_port_mask;
39459 * NAT IPv4/6 address based on address type flag.
39460 * 0 values are ignored.
39462 uint32_t nat_ip_address[4];
39463 /* L2 header re-write Destination MAC address. */
39464 uint16_t l2_rewrite_dmac[3];
39466 * The NAT source/destination port based on direction flag.
39467 * Applies to UDP and TCP traffic.
39468 * 0 values are ignored.
39471 /* L2 header re-write Source MAC address. */
39472 uint16_t l2_rewrite_smac[3];
39473 /* The value of ip protocol. */
39476 uint8_t tunnel_type;
39478 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
39480 /* Virtual eXtensible Local Area Network (VXLAN) */
39481 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
39483 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
39484 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
39486 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
39487 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
39490 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
39492 /* Generic Network Virtualization Encapsulation (Geneve) */
39493 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39495 /* Multi-Protocol Label Switching (MPLS) */
39496 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
39498 /* Stateless Transport Tunnel (STT) */
39499 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
39501 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39502 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
39504 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39505 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39508 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39511 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39513 /* Use fixed layer 2 ether type of 0xFFFF */
39514 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39517 * IPV6 over virtual eXtensible Local Area Network with GPE header
39520 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39522 /* Any tunneled traffic */
39523 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
39525 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39526 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
39529 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
39530 struct hwrm_cfa_flow_alloc_output {
39531 /* The specific error status for the command. */
39532 uint16_t error_code;
39533 /* The HWRM command request type. */
39535 /* The sequence ID from the original command. */
39537 /* The length of the response data in number of bytes. */
39539 /* Flow record index. */
39540 uint16_t flow_handle;
39541 uint8_t unused_0[2];
39543 * The flow id value in bit 0-29 is the actual ID of the flow
39544 * associated with this filter and it shall be used to match
39545 * and associate the flow identifier returned in completion
39546 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
39547 * shall indicate no valid flow id.
39550 /* Indicate the flow id value. */
39551 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
39552 UINT32_C(0x3fffffff)
39553 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
39554 /* Indicate type of the flow. */
39555 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
39556 UINT32_C(0x40000000)
39558 * If this bit set to 0, then it indicates that the flow is
39561 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
39562 (UINT32_C(0x0) << 30)
39564 * If this bit is set to 1, then it indicates that the flow is
39567 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
39568 (UINT32_C(0x1) << 30)
39569 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
39570 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
39571 /* Indicate the flow direction. */
39572 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
39573 UINT32_C(0x80000000)
39574 /* If this bit set to 0, then it indicates rx flow. */
39575 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
39576 (UINT32_C(0x0) << 31)
39577 /* If this bit is set to 1, then it indicates that tx flow. */
39578 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
39579 (UINT32_C(0x1) << 31)
39580 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
39581 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
39582 /* This value identifies a set of CFA data structures used for a flow. */
39583 uint64_t ext_flow_handle;
39584 uint32_t flow_counter_id;
39585 uint8_t unused_1[3];
39587 * This field is used in Output records to indicate that the output
39588 * is completely written to RAM. This field should be read as '1'
39589 * to indicate that the output has been completely written.
39590 * When writing a command completion or response to an internal
39591 * processor, the order of writes has to be such that this field is
39597 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
39598 struct hwrm_cfa_flow_alloc_cmd_err {
39600 * command specific error codes that goes to
39601 * the cmd_err field in Common HWRM Error Response.
39604 /* Unknown error */
39605 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
39606 /* No more L2 Context TCAM */
39607 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
39608 /* No more action records */
39609 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
39610 /* No more flow counters */
39611 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
39612 /* No more wild-card TCAM */
39613 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
39614 /* Hash collsion in exact match tables */
39615 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
39616 /* Key is already installed */
39617 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
39618 /* Flow Context DB is out of resource */
39619 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
39620 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
39621 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
39622 uint8_t unused_0[7];
39625 /**********************
39626 * hwrm_cfa_flow_free *
39627 **********************/
39630 /* hwrm_cfa_flow_free_input (size:256b/32B) */
39631 struct hwrm_cfa_flow_free_input {
39632 /* The HWRM command request type. */
39635 * The completion ring to send the completion event on. This should
39636 * be the NQ ID returned from the `nq_alloc` HWRM command.
39638 uint16_t cmpl_ring;
39640 * The sequence ID is used by the driver for tracking multiple
39641 * commands. This ID is treated as opaque data by the firmware and
39642 * the value is returned in the `hwrm_resp_hdr` upon completion.
39646 * The target ID of the command:
39647 * * 0x0-0xFFF8 - The function ID
39648 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39649 * * 0xFFFD - Reserved for user-space HWRM interface
39652 uint16_t target_id;
39654 * A physical address pointer pointing to a host buffer that the
39655 * command's response data will be written. This can be either a host
39656 * physical address (HPA) or a guest physical address (GPA) and must
39657 * point to a physically contiguous block of memory.
39659 uint64_t resp_addr;
39660 /* Flow record index. */
39661 uint16_t flow_handle;
39663 /* Flow counter id to be freed. */
39664 uint32_t flow_counter_id;
39665 /* This value identifies a set of CFA data structures used for a flow. */
39666 uint64_t ext_flow_handle;
39669 /* hwrm_cfa_flow_free_output (size:256b/32B) */
39670 struct hwrm_cfa_flow_free_output {
39671 /* The specific error status for the command. */
39672 uint16_t error_code;
39673 /* The HWRM command request type. */
39675 /* The sequence ID from the original command. */
39677 /* The length of the response data in number of bytes. */
39679 /* packet is 64 b */
39683 uint8_t unused_0[7];
39685 * This field is used in Output records to indicate that the output
39686 * is completely written to RAM. This field should be read as '1'
39687 * to indicate that the output has been completely written.
39688 * When writing a command completion or response to an internal
39689 * processor, the order of writes has to be such that this field is
39695 /* hwrm_cfa_flow_action_data (size:960b/120B) */
39696 struct hwrm_cfa_flow_action_data {
39697 uint16_t action_flags;
39698 /* Setting of this flag indicates accept action. */
39699 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
39701 /* Setting of this flag indicates recycle action. */
39702 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
39704 /* Setting of this flag indicates drop action. */
39705 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
39707 /* Setting of this flag indicates meter action. */
39708 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
39710 /* Setting of this flag indicates tunnel action. */
39711 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
39714 * If set to 1 and flow direction is TX, it indicates decap of L2
39715 * header and encap of tunnel header. If set to 1 and flow direction
39716 * is RX, it indicates decap of tunnel header and encap L2 header.
39718 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
39720 /* Setting of this flag indicates ttl decrement action. */
39721 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
39723 /* If set to 1, flow aging is enabled for this flow. */
39724 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
39726 /* Setting of this flag indicates encap action. */
39727 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
39729 /* Setting of this flag indicates decap action. */
39730 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
39733 uint16_t act_meter_id;
39736 /* vport number. */
39738 /* The NAT source/destination. */
39740 uint16_t unused_0[3];
39741 /* NAT IPv4/IPv6 address. */
39742 uint32_t nat_ip_address[4];
39743 /* Encapsulation Type. */
39744 uint8_t encap_type;
39745 /* Virtual eXtensible Local Area Network (VXLAN) */
39746 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
39747 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
39748 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
39749 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
39750 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
39752 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
39753 /* Generic Network Virtualization Encapsulation (Geneve) */
39754 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
39755 /* Multi-Protocol Label Switching (MPLS) */
39756 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
39758 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
39759 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39760 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
39761 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39762 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
39764 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39767 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
39768 /* Use fixed layer 2 ether type of 0xFFFF */
39769 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
39771 * IPV6 over virtual eXtensible Local Area Network with GPE header
39774 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
39775 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
39776 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
39778 /* This value is encap data for the associated encap type. */
39779 uint32_t encap_data[20];
39782 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
39783 struct hwrm_cfa_flow_tunnel_hdr_data {
39785 uint8_t tunnel_type;
39787 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
39789 /* Virtual eXtensible Local Area Network (VXLAN) */
39790 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
39792 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
39793 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
39795 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
39796 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
39799 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
39801 /* Generic Network Virtualization Encapsulation (Geneve) */
39802 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
39804 /* Multi-Protocol Label Switching (MPLS) */
39805 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
39807 /* Stateless Transport Tunnel (STT) */
39808 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
39810 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
39811 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
39813 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39814 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
39817 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
39820 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
39822 /* Use fixed layer 2 ether type of 0xFFFF */
39823 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
39826 * IPV6 over virtual eXtensible Local Area Network with GPE header
39829 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
39831 /* Any tunneled traffic */
39832 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
39834 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
39835 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
39838 * Tunnel identifier.
39839 * Virtual Network Identifier (VNI).
39841 uint32_t tunnel_id;
39844 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
39845 struct hwrm_cfa_flow_l4_key_data {
39846 /* The value of source port. */
39847 uint16_t l4_src_port;
39848 /* The value of destination port. */
39849 uint16_t l4_dst_port;
39853 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
39854 struct hwrm_cfa_flow_l3_key_data {
39855 /* The value of ip protocol. */
39856 uint8_t ip_protocol;
39857 uint8_t unused_0[7];
39858 /* The value of destination IPv4/IPv6 address. */
39859 uint32_t ip_dst[4];
39860 /* The source IPv4/IPv6 address. */
39861 uint32_t ip_src[4];
39862 /* NAT IPv4/IPv6 address. */
39863 uint32_t nat_ip_address[4];
39864 uint32_t unused[2];
39867 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
39868 struct hwrm_cfa_flow_l2_key_data {
39869 /* Destination MAC address. */
39872 /* Source MAC address. */
39875 /* L2 header re-write Destination MAC address. */
39876 uint16_t l2_rewrite_dmac[3];
39878 /* L2 header re-write Source MAC address. */
39879 uint16_t l2_rewrite_smac[3];
39881 uint16_t ethertype;
39882 /* Number of VLAN tags. */
39883 uint16_t num_vlan_tags;
39885 uint16_t l2_rewrite_vlan_tpid;
39887 uint16_t l2_rewrite_vlan_tci;
39888 uint8_t unused_3[2];
39889 /* Outer VLAN TPID. */
39890 uint16_t ovlan_tpid;
39891 /* Outer VLAN TCI. */
39892 uint16_t ovlan_tci;
39893 /* Inner VLAN TPID. */
39894 uint16_t ivlan_tpid;
39895 /* Inner VLAN TCI. */
39896 uint16_t ivlan_tci;
39900 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
39901 struct hwrm_cfa_flow_key_data {
39902 /* Flow associated tunnel L2 header key info. */
39903 uint32_t t_l2_key_data[14];
39904 /* Flow associated tunnel L2 header mask info. */
39905 uint32_t t_l2_key_mask[14];
39906 /* Flow associated tunnel L3 header key info. */
39907 uint32_t t_l3_key_data[16];
39908 /* Flow associated tunnel L3 header mask info. */
39909 uint32_t t_l3_key_mask[16];
39910 /* Flow associated tunnel L4 header key info. */
39911 uint32_t t_l4_key_data[2];
39912 /* Flow associated tunnel L4 header mask info. */
39913 uint32_t t_l4_key_mask[2];
39914 /* Flow associated tunnel header info. */
39915 uint32_t tunnel_hdr[2];
39916 /* Flow associated L2 header key info. */
39917 uint32_t l2_key_data[14];
39918 /* Flow associated L2 header mask info. */
39919 uint32_t l2_key_mask[14];
39920 /* Flow associated L3 header key info. */
39921 uint32_t l3_key_data[16];
39922 /* Flow associated L3 header mask info. */
39923 uint32_t l3_key_mask[16];
39924 /* Flow associated L4 header key info. */
39925 uint32_t l4_key_data[2];
39926 /* Flow associated L4 header mask info. */
39927 uint32_t l4_key_mask[2];
39930 /**********************
39931 * hwrm_cfa_flow_info *
39932 **********************/
39935 /* hwrm_cfa_flow_info_input (size:256b/32B) */
39936 struct hwrm_cfa_flow_info_input {
39937 /* The HWRM command request type. */
39940 * The completion ring to send the completion event on. This should
39941 * be the NQ ID returned from the `nq_alloc` HWRM command.
39943 uint16_t cmpl_ring;
39945 * The sequence ID is used by the driver for tracking multiple
39946 * commands. This ID is treated as opaque data by the firmware and
39947 * the value is returned in the `hwrm_resp_hdr` upon completion.
39951 * The target ID of the command:
39952 * * 0x0-0xFFF8 - The function ID
39953 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39954 * * 0xFFFD - Reserved for user-space HWRM interface
39957 uint16_t target_id;
39959 * A physical address pointer pointing to a host buffer that the
39960 * command's response data will be written. This can be either a host
39961 * physical address (HPA) or a guest physical address (GPA) and must
39962 * point to a physically contiguous block of memory.
39964 uint64_t resp_addr;
39965 /* Flow record index. */
39966 uint16_t flow_handle;
39967 /* Max flow handle */
39968 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
39970 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
39971 /* CNP flow handle */
39972 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
39974 /* RoCEv1 flow handle */
39975 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
39977 /* RoCEv2 flow handle */
39978 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
39980 /* Direction rx = 1 */
39981 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
39983 uint8_t unused_0[6];
39984 /* This value identifies a set of CFA data structures used for a flow. */
39985 uint64_t ext_flow_handle;
39988 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
39989 struct hwrm_cfa_flow_info_output {
39990 /* The specific error status for the command. */
39991 uint16_t error_code;
39992 /* The HWRM command request type. */
39994 /* The sequence ID from the original command. */
39996 /* The length of the response data in number of bytes. */
39999 /* When set to 1, indicates the configuration is the TX flow. */
40000 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
40001 /* When set to 1, indicates the configuration is the RX flow. */
40002 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
40003 /* profile is 8 b */
40005 /* src_fid is 16 b */
40007 /* dst_fid is 16 b */
40009 /* l2_ctxt_id is 16 b */
40010 uint16_t l2_ctxt_id;
40011 /* em_info is 64 b */
40013 /* tcam_info is 64 b */
40014 uint64_t tcam_info;
40015 /* vfp_tcam_info is 64 b */
40016 uint64_t vfp_tcam_info;
40017 /* ar_id is 16 b */
40019 /* flow_handle is 16 b */
40020 uint16_t flow_handle;
40021 /* tunnel_handle is 32 b */
40022 uint32_t tunnel_handle;
40023 /* The flow aging timer for the flow, the unit is 100 milliseconds */
40024 uint16_t flow_timer;
40025 uint8_t unused_0[6];
40026 /* Flow associated L2, L3 and L4 headers info. */
40027 uint32_t flow_key_data[130];
40028 /* Flow associated action record info. */
40029 uint32_t flow_action_info[30];
40030 uint8_t unused_1[7];
40032 * This field is used in Output records to indicate that the output
40033 * is completely written to RAM. This field should be read as '1'
40034 * to indicate that the output has been completely written.
40035 * When writing a command completion or response to an internal
40036 * processor, the order of writes has to be such that this field is
40042 /***********************
40043 * hwrm_cfa_flow_flush *
40044 ***********************/
40047 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
40048 struct hwrm_cfa_flow_flush_input {
40049 /* The HWRM command request type. */
40052 * The completion ring to send the completion event on. This should
40053 * be the NQ ID returned from the `nq_alloc` HWRM command.
40055 uint16_t cmpl_ring;
40057 * The sequence ID is used by the driver for tracking multiple
40058 * commands. This ID is treated as opaque data by the firmware and
40059 * the value is returned in the `hwrm_resp_hdr` upon completion.
40063 * The target ID of the command:
40064 * * 0x0-0xFFF8 - The function ID
40065 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40066 * * 0xFFFD - Reserved for user-space HWRM interface
40069 uint16_t target_id;
40071 * A physical address pointer pointing to a host buffer that the
40072 * command's response data will be written. This can be either a host
40073 * physical address (HPA) or a guest physical address (GPA) and must
40074 * point to a physically contiguous block of memory.
40076 uint64_t resp_addr;
40077 /* flags is 32 b */
40080 * Set to 1 to indicate the page size, page layers, and
40081 * flow_handle_table_dma_addr fields are valid. The flow flush
40082 * operation should only flush the flows from the flow table
40083 * specified. This flag is set to 0 by older driver. For older
40084 * firmware, setting this flag has no effect.
40086 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
40089 * Set to 1 to indicate flow flush operation to cleanup all the
40090 * flows, meters, CFA context memory tables etc. This flag is set to
40091 * 0 by older driver. For older firmware, setting this flag has no
40094 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
40097 * Set to 1 to indicate flow flush operation to cleanup all the
40098 * flows by the caller. This flag is set to 0 by older driver. For
40099 * older firmware, setting this flag has no effect.
40101 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
40104 * Set to 1 to indicate the flow counter IDs are included in the
40107 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
40108 UINT32_C(0x8000000)
40110 * This specifies the size of flow handle entries provided by the
40111 * driver in the flow table specified below. Only two flow handle
40112 * size enums are defined.
40114 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
40115 UINT32_C(0xc0000000)
40116 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
40118 /* The flow handle is 16bit */
40119 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
40120 (UINT32_C(0x0) << 30)
40121 /* The flow handle is 64bit */
40122 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
40123 (UINT32_C(0x1) << 30)
40124 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
40125 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
40126 /* Specify page size of the flow table memory. */
40128 /* The page size is 4K */
40129 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
40130 /* The page size is 8K */
40131 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
40132 /* The page size is 64K */
40133 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
40134 /* The page size is 256K */
40135 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
40136 /* The page size is 1M */
40137 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
40138 /* The page size is 2M */
40139 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
40140 /* The page size is 4M */
40141 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
40142 /* The page size is 1G */
40143 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
40144 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
40145 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
40146 /* FLow table memory indirect levels. */
40147 uint8_t page_level;
40148 /* PBL pointer is physical start address. */
40149 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
40150 /* PBL pointer points to PTE table. */
40151 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
40153 * PBL pointer points to PDE table with each entry pointing to PTE
40156 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
40157 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
40158 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
40159 /* number of flows in the flow table */
40160 uint16_t num_flows;
40161 /* Pointer to the PBL, or PDL depending on number of levels */
40165 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
40166 struct hwrm_cfa_flow_flush_output {
40167 /* The specific error status for the command. */
40168 uint16_t error_code;
40169 /* The HWRM command request type. */
40171 /* The sequence ID from the original command. */
40173 /* The length of the response data in number of bytes. */
40175 uint8_t unused_0[7];
40177 * This field is used in Output records to indicate that the output
40178 * is completely written to RAM. This field should be read as '1'
40179 * to indicate that the output has been completely written.
40180 * When writing a command completion or response to an internal
40181 * processor, the order of writes has to be such that this field is
40187 /***********************
40188 * hwrm_cfa_flow_stats *
40189 ***********************/
40192 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
40193 struct hwrm_cfa_flow_stats_input {
40194 /* The HWRM command request type. */
40197 * The completion ring to send the completion event on. This should
40198 * be the NQ ID returned from the `nq_alloc` HWRM command.
40200 uint16_t cmpl_ring;
40202 * The sequence ID is used by the driver for tracking multiple
40203 * commands. This ID is treated as opaque data by the firmware and
40204 * the value is returned in the `hwrm_resp_hdr` upon completion.
40208 * The target ID of the command:
40209 * * 0x0-0xFFF8 - The function ID
40210 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40211 * * 0xFFFD - Reserved for user-space HWRM interface
40214 uint16_t target_id;
40216 * A physical address pointer pointing to a host buffer that the
40217 * command's response data will be written. This can be either a host
40218 * physical address (HPA) or a guest physical address (GPA) and must
40219 * point to a physically contiguous block of memory.
40221 uint64_t resp_addr;
40223 uint16_t num_flows;
40225 uint16_t flow_handle_0;
40227 uint16_t flow_handle_1;
40229 uint16_t flow_handle_2;
40231 uint16_t flow_handle_3;
40233 uint16_t flow_handle_4;
40235 uint16_t flow_handle_5;
40237 uint16_t flow_handle_6;
40239 uint16_t flow_handle_7;
40241 uint16_t flow_handle_8;
40243 uint16_t flow_handle_9;
40244 uint8_t unused_0[2];
40245 /* Flow ID of a flow. */
40246 uint32_t flow_id_0;
40247 /* Flow ID of a flow. */
40248 uint32_t flow_id_1;
40249 /* Flow ID of a flow. */
40250 uint32_t flow_id_2;
40251 /* Flow ID of a flow. */
40252 uint32_t flow_id_3;
40253 /* Flow ID of a flow. */
40254 uint32_t flow_id_4;
40255 /* Flow ID of a flow. */
40256 uint32_t flow_id_5;
40257 /* Flow ID of a flow. */
40258 uint32_t flow_id_6;
40259 /* Flow ID of a flow. */
40260 uint32_t flow_id_7;
40261 /* Flow ID of a flow. */
40262 uint32_t flow_id_8;
40263 /* Flow ID of a flow. */
40264 uint32_t flow_id_9;
40267 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
40268 struct hwrm_cfa_flow_stats_output {
40269 /* The specific error status for the command. */
40270 uint16_t error_code;
40271 /* The HWRM command request type. */
40273 /* The sequence ID from the original command. */
40275 /* The length of the response data in number of bytes. */
40277 /* packet_0 is 64 b */
40279 /* packet_1 is 64 b */
40281 /* packet_2 is 64 b */
40283 /* packet_3 is 64 b */
40285 /* packet_4 is 64 b */
40287 /* packet_5 is 64 b */
40289 /* packet_6 is 64 b */
40291 /* packet_7 is 64 b */
40293 /* packet_8 is 64 b */
40295 /* packet_9 is 64 b */
40297 /* byte_0 is 64 b */
40299 /* byte_1 is 64 b */
40301 /* byte_2 is 64 b */
40303 /* byte_3 is 64 b */
40305 /* byte_4 is 64 b */
40307 /* byte_5 is 64 b */
40309 /* byte_6 is 64 b */
40311 /* byte_7 is 64 b */
40313 /* byte_8 is 64 b */
40315 /* byte_9 is 64 b */
40317 uint8_t unused_0[7];
40319 * This field is used in Output records to indicate that the output
40320 * is completely written to RAM. This field should be read as '1'
40321 * to indicate that the output has been completely written.
40322 * When writing a command completion or response to an internal
40323 * processor, the order of writes has to be such that this field is
40329 /***********************************
40330 * hwrm_cfa_flow_aging_timer_reset *
40331 ***********************************/
40334 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
40335 struct hwrm_cfa_flow_aging_timer_reset_input {
40336 /* The HWRM command request type. */
40339 * The completion ring to send the completion event on. This should
40340 * be the NQ ID returned from the `nq_alloc` HWRM command.
40342 uint16_t cmpl_ring;
40344 * The sequence ID is used by the driver for tracking multiple
40345 * commands. This ID is treated as opaque data by the firmware and
40346 * the value is returned in the `hwrm_resp_hdr` upon completion.
40350 * The target ID of the command:
40351 * * 0x0-0xFFF8 - The function ID
40352 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40353 * * 0xFFFD - Reserved for user-space HWRM interface
40356 uint16_t target_id;
40358 * A physical address pointer pointing to a host buffer that the
40359 * command's response data will be written. This can be either a host
40360 * physical address (HPA) or a guest physical address (GPA) and must
40361 * point to a physically contiguous block of memory.
40363 uint64_t resp_addr;
40364 /* Flow record index. */
40365 uint16_t flow_handle;
40366 uint8_t unused_0[2];
40368 * New flow timer value for the flow specified in the ext_flow_handle.
40369 * The flow timer unit is 100ms.
40371 uint32_t flow_timer;
40372 /* This value identifies a set of CFA data structures used for a flow. */
40373 uint64_t ext_flow_handle;
40376 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
40377 struct hwrm_cfa_flow_aging_timer_reset_output {
40378 /* The specific error status for the command. */
40379 uint16_t error_code;
40380 /* The HWRM command request type. */
40382 /* The sequence ID from the original command. */
40384 /* The length of the response data in number of bytes. */
40386 uint8_t unused_0[7];
40388 * This field is used in Output records to indicate that the output
40389 * is completely written to RAM. This field should be read as '1'
40390 * to indicate that the output has been completely written.
40391 * When writing a command completion or response to an internal
40392 * processor, the order of writes has to be such that this field is
40398 /***************************
40399 * hwrm_cfa_flow_aging_cfg *
40400 ***************************/
40403 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
40404 struct hwrm_cfa_flow_aging_cfg_input {
40405 /* The HWRM command request type. */
40408 * The completion ring to send the completion event on. This should
40409 * be the NQ ID returned from the `nq_alloc` HWRM command.
40411 uint16_t cmpl_ring;
40413 * The sequence ID is used by the driver for tracking multiple
40414 * commands. This ID is treated as opaque data by the firmware and
40415 * the value is returned in the `hwrm_resp_hdr` upon completion.
40419 * The target ID of the command:
40420 * * 0x0-0xFFF8 - The function ID
40421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40422 * * 0xFFFD - Reserved for user-space HWRM interface
40425 uint16_t target_id;
40427 * A physical address pointer pointing to a host buffer that the
40428 * command's response data will be written. This can be either a host
40429 * physical address (HPA) or a guest physical address (GPA) and must
40430 * point to a physically contiguous block of memory.
40432 uint64_t resp_addr;
40433 /* The bit field to enable per flow aging configuration. */
40436 * This bit must be '1' for the tcp flow timer field to be
40439 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
40442 * This bit must be '1' for the tcp finish timer field to be
40445 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
40448 * This bit must be '1' for the udp flow timer field to be
40451 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
40454 * This bit must be '1' for the eem dma interval field to be
40457 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
40460 * This bit must be '1' for the eem notice interval field to be
40463 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
40466 * This bit must be '1' for the eem context memory maximum entries
40467 * field to be configured
40469 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
40472 * This bit must be '1' for the eem context memory ID field to be
40475 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
40478 * This bit must be '1' for the eem context memory type field to be
40481 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
40484 /* Enumeration denoting the RX, TX type of the resource. */
40485 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
40487 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
40489 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
40490 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
40491 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
40493 * Enumeration denoting the enable, disable eem flow aging
40496 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
40498 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
40499 (UINT32_C(0x0) << 1)
40501 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
40502 (UINT32_C(0x1) << 1)
40503 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
40504 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
40507 * The flow aging timer for all TCP flows, the unit is 100
40510 uint32_t tcp_flow_timer;
40512 * The TCP finished timer for all TCP flows, the unit is 100
40515 uint32_t tcp_fin_timer;
40517 * The flow aging timer for all UDP flows, the unit is 100
40520 uint32_t udp_flow_timer;
40522 * The interval to dma eem ejection data to host memory, the unit is
40525 uint16_t eem_dma_interval;
40527 * The interval to notify driver to read the eem ejection data, the
40528 * unit is milliseconds.
40530 uint16_t eem_notice_interval;
40531 /* The maximum entries number in the eem context memory. */
40532 uint32_t eem_ctx_max_entries;
40533 /* The context memory ID for eem flow aging. */
40534 uint16_t eem_ctx_id;
40535 uint16_t eem_ctx_mem_type;
40537 * The content of context memory is eem ejection data, the size of
40538 * each entry is 4 bytes.
40540 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
40542 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
40543 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
40544 uint8_t unused_1[4];
40547 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
40548 struct hwrm_cfa_flow_aging_cfg_output {
40549 /* The specific error status for the command. */
40550 uint16_t error_code;
40551 /* The HWRM command request type. */
40553 /* The sequence ID from the original command. */
40555 /* The length of the response data in number of bytes. */
40557 uint8_t unused_0[7];
40559 * This field is used in Output records to indicate that the output
40560 * is completely written to RAM. This field should be read as '1'
40561 * to indicate that the output has been completely written.
40562 * When writing a command completion or response to an internal
40563 * processor, the order of writes has to be such that this field is
40569 /****************************
40570 * hwrm_cfa_flow_aging_qcfg *
40571 ****************************/
40574 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
40575 struct hwrm_cfa_flow_aging_qcfg_input {
40576 /* The HWRM command request type. */
40579 * The completion ring to send the completion event on. This should
40580 * be the NQ ID returned from the `nq_alloc` HWRM command.
40582 uint16_t cmpl_ring;
40584 * The sequence ID is used by the driver for tracking multiple
40585 * commands. This ID is treated as opaque data by the firmware and
40586 * the value is returned in the `hwrm_resp_hdr` upon completion.
40590 * The target ID of the command:
40591 * * 0x0-0xFFF8 - The function ID
40592 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40593 * * 0xFFFD - Reserved for user-space HWRM interface
40596 uint16_t target_id;
40598 * A physical address pointer pointing to a host buffer that the
40599 * command's response data will be written. This can be either a host
40600 * physical address (HPA) or a guest physical address (GPA) and must
40601 * point to a physically contiguous block of memory.
40603 uint64_t resp_addr;
40605 * The direction for the flow aging configuration, 1 is rx path, 2 is
40609 /* Enumeration denoting the RX, TX type of the resource. */
40610 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
40612 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
40614 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
40615 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
40616 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
40617 uint8_t unused_0[7];
40620 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
40621 struct hwrm_cfa_flow_aging_qcfg_output {
40622 /* The specific error status for the command. */
40623 uint16_t error_code;
40624 /* The HWRM command request type. */
40626 /* The sequence ID from the original command. */
40628 /* The length of the response data in number of bytes. */
40631 * The current flow aging timer for all TCP flows, the unit is 100
40634 uint32_t tcp_flow_timer;
40636 * The current TCP finished timer for all TCP flows, the unit is 100
40639 uint32_t tcp_fin_timer;
40641 * The current flow aging timer for all UDP flows, the unit is 100
40644 uint32_t udp_flow_timer;
40646 * The interval to dma eem ejection data to host memory, the unit is
40649 uint16_t eem_dma_interval;
40651 * The interval to notify driver to read the eem ejection data, the
40652 * unit is milliseconds.
40654 uint16_t eem_notice_interval;
40655 /* The maximum entries number in the eem context memory. */
40656 uint32_t eem_ctx_max_entries;
40657 /* The context memory ID for eem flow aging. */
40658 uint16_t eem_ctx_id;
40659 /* The context memory type for eem flow aging. */
40660 uint16_t eem_ctx_mem_type;
40661 uint8_t unused_0[7];
40663 * This field is used in Output records to indicate that the output
40664 * is completely written to RAM. This field should be read as '1'
40665 * to indicate that the output has been completely written.
40666 * When writing a command completion or response to an internal
40667 * processor, the order of writes has to be such that this field is
40673 /*****************************
40674 * hwrm_cfa_flow_aging_qcaps *
40675 *****************************/
40678 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
40679 struct hwrm_cfa_flow_aging_qcaps_input {
40680 /* The HWRM command request type. */
40683 * The completion ring to send the completion event on. This should
40684 * be the NQ ID returned from the `nq_alloc` HWRM command.
40686 uint16_t cmpl_ring;
40688 * The sequence ID is used by the driver for tracking multiple
40689 * commands. This ID is treated as opaque data by the firmware and
40690 * the value is returned in the `hwrm_resp_hdr` upon completion.
40694 * The target ID of the command:
40695 * * 0x0-0xFFF8 - The function ID
40696 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40697 * * 0xFFFD - Reserved for user-space HWRM interface
40700 uint16_t target_id;
40702 * A physical address pointer pointing to a host buffer that the
40703 * command's response data will be written. This can be either a host
40704 * physical address (HPA) or a guest physical address (GPA) and must
40705 * point to a physically contiguous block of memory.
40707 uint64_t resp_addr;
40709 * The direction for the flow aging configuration, 1 is rx path, 2 is
40713 /* Enumeration denoting the RX, TX type of the resource. */
40714 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
40716 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
40718 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
40719 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
40720 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
40721 uint8_t unused_0[7];
40724 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
40725 struct hwrm_cfa_flow_aging_qcaps_output {
40726 /* The specific error status for the command. */
40727 uint16_t error_code;
40728 /* The HWRM command request type. */
40730 /* The sequence ID from the original command. */
40732 /* The length of the response data in number of bytes. */
40735 * The maximum flow aging timer for all TCP flows, the unit is 100
40738 uint32_t max_tcp_flow_timer;
40740 * The maximum TCP finished timer for all TCP flows, the unit is 100
40743 uint32_t max_tcp_fin_timer;
40745 * The maximum flow aging timer for all UDP flows, the unit is 100
40748 uint32_t max_udp_flow_timer;
40749 /* The maximum aging flows that HW can support. */
40750 uint32_t max_aging_flows;
40751 uint8_t unused_0[7];
40753 * This field is used in Output records to indicate that the output
40754 * is completely written to RAM. This field should be read as '1'
40755 * to indicate that the output has been completely written.
40756 * When writing a command completion or response to an internal
40757 * processor, the order of writes has to be such that this field is
40763 /**********************************
40764 * hwrm_cfa_tcp_flag_process_qcfg *
40765 **********************************/
40768 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
40769 struct hwrm_cfa_tcp_flag_process_qcfg_input {
40770 /* The HWRM command request type. */
40773 * The completion ring to send the completion event on. This should
40774 * be the NQ ID returned from the `nq_alloc` HWRM command.
40776 uint16_t cmpl_ring;
40778 * The sequence ID is used by the driver for tracking multiple
40779 * commands. This ID is treated as opaque data by the firmware and
40780 * the value is returned in the `hwrm_resp_hdr` upon completion.
40784 * The target ID of the command:
40785 * * 0x0-0xFFF8 - The function ID
40786 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40787 * * 0xFFFD - Reserved for user-space HWRM interface
40790 uint16_t target_id;
40792 * A physical address pointer pointing to a host buffer that the
40793 * command's response data will be written. This can be either a host
40794 * physical address (HPA) or a guest physical address (GPA) and must
40795 * point to a physically contiguous block of memory.
40797 uint64_t resp_addr;
40800 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
40801 struct hwrm_cfa_tcp_flag_process_qcfg_output {
40802 /* The specific error status for the command. */
40803 uint16_t error_code;
40804 /* The HWRM command request type. */
40806 /* The sequence ID from the original command. */
40808 /* The length of the response data in number of bytes. */
40810 /* The port 0 RX mirror action record ID. */
40811 uint16_t rx_ar_id_port0;
40812 /* The port 1 RX mirror action record ID. */
40813 uint16_t rx_ar_id_port1;
40815 * The port 0 RX action record ID for TX TCP flag packets from
40818 uint16_t tx_ar_id_port0;
40820 * The port 1 RX action record ID for TX TCP flag packets from
40823 uint16_t tx_ar_id_port1;
40824 uint8_t unused_0[7];
40826 * This field is used in Output records to indicate that the output
40827 * is completely written to RAM. This field should be read as '1'
40828 * to indicate that the output has been completely written.
40829 * When writing a command completion or response to an internal
40830 * processor, the order of writes has to be such that this field is
40836 /**************************
40837 * hwrm_cfa_vf_pair_alloc *
40838 **************************/
40841 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
40842 struct hwrm_cfa_vf_pair_alloc_input {
40843 /* The HWRM command request type. */
40846 * The completion ring to send the completion event on. This should
40847 * be the NQ ID returned from the `nq_alloc` HWRM command.
40849 uint16_t cmpl_ring;
40851 * The sequence ID is used by the driver for tracking multiple
40852 * commands. This ID is treated as opaque data by the firmware and
40853 * the value is returned in the `hwrm_resp_hdr` upon completion.
40857 * The target ID of the command:
40858 * * 0x0-0xFFF8 - The function ID
40859 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40860 * * 0xFFFD - Reserved for user-space HWRM interface
40863 uint16_t target_id;
40865 * A physical address pointer pointing to a host buffer that the
40866 * command's response data will be written. This can be either a host
40867 * physical address (HPA) or a guest physical address (GPA) and must
40868 * point to a physically contiguous block of memory.
40870 uint64_t resp_addr;
40871 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40873 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40875 uint8_t unused_0[4];
40876 /* VF Pair name (32 byte string). */
40877 char pair_name[32];
40880 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
40881 struct hwrm_cfa_vf_pair_alloc_output {
40882 /* The specific error status for the command. */
40883 uint16_t error_code;
40884 /* The HWRM command request type. */
40886 /* The sequence ID from the original command. */
40888 /* The length of the response data in number of bytes. */
40890 uint8_t unused_0[7];
40892 * This field is used in Output records to indicate that the output
40893 * is completely written to RAM. This field should be read as '1'
40894 * to indicate that the output has been completely written.
40895 * When writing a command completion or response to an internal
40896 * processor, the order of writes has to be such that this field is
40902 /*************************
40903 * hwrm_cfa_vf_pair_free *
40904 *************************/
40907 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
40908 struct hwrm_cfa_vf_pair_free_input {
40909 /* The HWRM command request type. */
40912 * The completion ring to send the completion event on. This should
40913 * be the NQ ID returned from the `nq_alloc` HWRM command.
40915 uint16_t cmpl_ring;
40917 * The sequence ID is used by the driver for tracking multiple
40918 * commands. This ID is treated as opaque data by the firmware and
40919 * the value is returned in the `hwrm_resp_hdr` upon completion.
40923 * The target ID of the command:
40924 * * 0x0-0xFFF8 - The function ID
40925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40926 * * 0xFFFD - Reserved for user-space HWRM interface
40929 uint16_t target_id;
40931 * A physical address pointer pointing to a host buffer that the
40932 * command's response data will be written. This can be either a host
40933 * physical address (HPA) or a guest physical address (GPA) and must
40934 * point to a physically contiguous block of memory.
40936 uint64_t resp_addr;
40937 /* VF Pair name (32 byte string). */
40938 char pair_name[32];
40941 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
40942 struct hwrm_cfa_vf_pair_free_output {
40943 /* The specific error status for the command. */
40944 uint16_t error_code;
40945 /* The HWRM command request type. */
40947 /* The sequence ID from the original command. */
40949 /* The length of the response data in number of bytes. */
40951 uint8_t unused_0[7];
40953 * This field is used in Output records to indicate that the output
40954 * is completely written to RAM. This field should be read as '1'
40955 * to indicate that the output has been completely written.
40956 * When writing a command completion or response to an internal
40957 * processor, the order of writes has to be such that this field is
40963 /*************************
40964 * hwrm_cfa_vf_pair_info *
40965 *************************/
40968 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
40969 struct hwrm_cfa_vf_pair_info_input {
40970 /* The HWRM command request type. */
40973 * The completion ring to send the completion event on. This should
40974 * be the NQ ID returned from the `nq_alloc` HWRM command.
40976 uint16_t cmpl_ring;
40978 * The sequence ID is used by the driver for tracking multiple
40979 * commands. This ID is treated as opaque data by the firmware and
40980 * the value is returned in the `hwrm_resp_hdr` upon completion.
40984 * The target ID of the command:
40985 * * 0x0-0xFFF8 - The function ID
40986 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40987 * * 0xFFFD - Reserved for user-space HWRM interface
40990 uint16_t target_id;
40992 * A physical address pointer pointing to a host buffer that the
40993 * command's response data will be written. This can be either a host
40994 * physical address (HPA) or a guest physical address (GPA) and must
40995 * point to a physically contiguous block of memory.
40997 uint64_t resp_addr;
40999 /* If this flag is set, lookup by name else lookup by index. */
41000 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
41001 /* vf pair table index. */
41002 uint16_t vf_pair_index;
41003 uint8_t unused_0[2];
41004 /* VF Pair name (32 byte string). */
41005 char vf_pair_name[32];
41008 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
41009 struct hwrm_cfa_vf_pair_info_output {
41010 /* The specific error status for the command. */
41011 uint16_t error_code;
41012 /* The HWRM command request type. */
41014 /* The sequence ID from the original command. */
41016 /* The length of the response data in number of bytes. */
41018 /* vf pair table index. */
41019 uint16_t next_vf_pair_index;
41020 /* vf pair member a's vf_fid. */
41022 /* vf pair member a's Linux logical VF number. */
41023 uint16_t vf_a_index;
41024 /* vf pair member b's vf_fid. */
41026 /* vf pair member a's Linux logical VF number. */
41027 uint16_t vf_b_index;
41028 /* vf pair state. */
41029 uint8_t pair_state;
41030 /* Pair has been allocated */
41031 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
41032 /* Both pair members are active */
41033 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
41034 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
41035 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
41036 uint8_t unused_0[5];
41037 /* VF Pair name (32 byte string). */
41038 char pair_name[32];
41039 uint8_t unused_1[7];
41041 * This field is used in Output records to indicate that the output
41042 * is completely written to RAM. This field should be read as '1'
41043 * to indicate that the output has been completely written.
41044 * When writing a command completion or response to an internal
41045 * processor, the order of writes has to be such that this field is
41051 /***********************
41052 * hwrm_cfa_pair_alloc *
41053 ***********************/
41056 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
41057 struct hwrm_cfa_pair_alloc_input {
41058 /* The HWRM command request type. */
41061 * The completion ring to send the completion event on. This should
41062 * be the NQ ID returned from the `nq_alloc` HWRM command.
41064 uint16_t cmpl_ring;
41066 * The sequence ID is used by the driver for tracking multiple
41067 * commands. This ID is treated as opaque data by the firmware and
41068 * the value is returned in the `hwrm_resp_hdr` upon completion.
41072 * The target ID of the command:
41073 * * 0x0-0xFFF8 - The function ID
41074 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41075 * * 0xFFFD - Reserved for user-space HWRM interface
41078 uint16_t target_id;
41080 * A physical address pointer pointing to a host buffer that the
41081 * command's response data will be written. This can be either a host
41082 * physical address (HPA) or a guest physical address (GPA) and must
41083 * point to a physically contiguous block of memory.
41085 uint64_t resp_addr;
41087 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
41088 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
41090 uint16_t pair_mode;
41091 /* Pair between VF on local host with PF or VF on specified host. */
41092 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
41094 /* Pair between REP on local host with PF or VF on specified host. */
41095 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
41097 /* Pair between REP on local host with REP on specified host. */
41098 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
41100 /* Pair for the proxy interface. */
41101 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
41103 /* Pair for the PF interface. */
41104 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
41106 /* Modify existing rep2fn pair and move pair to new PF. */
41107 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
41110 * Modify existing rep2fn pairs paired with same PF and move pairs
41113 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
41116 * Truflow pair between REP on local host with PF or VF on specified
41119 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
41121 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
41122 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
41123 /* Logical VF number (range: 0 -> MAX_VFS -1). */
41125 /* Logical Host (0xff-local host). */
41127 /* Logical PF (0xff-PF for command channel). */
41129 /* Logical VF number (range: 0 -> MAX_VFS -1). */
41131 /* Loopback port (0xff-internal loopback), valid for mode-3. */
41133 /* Priority used for encap of loopback packets valid for mode-3. */
41135 /* New PF for rep2fn modify, valid for mode 5. */
41136 uint16_t new_pf_fid;
41139 * This bit must be '1' for the q_ab field to be
41142 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
41144 * This bit must be '1' for the q_ba field to be
41147 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
41149 * This bit must be '1' for the fc_ab field to be
41152 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
41154 * This bit must be '1' for the fc_ba field to be
41157 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
41158 /* VF Pair name (32 byte string). */
41159 char pair_name[32];
41161 * The q_ab value specifies the logical index of the TX/RX CoS
41162 * queue to be assigned for traffic in the A to B direction of
41163 * the interface pair. The default value is 0.
41167 * The q_ba value specifies the logical index of the TX/RX CoS
41168 * queue to be assigned for traffic in the B to A direction of
41169 * the interface pair. The default value is 1.
41173 * Specifies whether RX ring flow control is disabled (0) or enabled
41174 * (1) in the A to B direction. The default value is 0, meaning that
41175 * packets will be dropped when the B-side RX rings are full.
41179 * Specifies whether RX ring flow control is disabled (0) or enabled
41180 * (1) in the B to A direction. The default value is 1, meaning that
41181 * the RX CoS queue will be flow controlled when the A-side RX rings
41185 uint8_t unused_1[4];
41188 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
41189 struct hwrm_cfa_pair_alloc_output {
41190 /* The specific error status for the command. */
41191 uint16_t error_code;
41192 /* The HWRM command request type. */
41194 /* The sequence ID from the original command. */
41196 /* The length of the response data in number of bytes. */
41198 /* Only valid for modes 1 and 2. */
41199 uint16_t rx_cfa_code_a;
41200 /* Only valid for modes 1 and 2. */
41201 uint16_t tx_cfa_action_a;
41202 /* Only valid for mode 2. */
41203 uint16_t rx_cfa_code_b;
41204 /* Only valid for mode 2. */
41205 uint16_t tx_cfa_action_b;
41206 uint8_t unused_0[7];
41208 * This field is used in Output records to indicate that the output
41209 * is completely written to RAM. This field should be read as '1'
41210 * to indicate that the output has been completely written.
41211 * When writing a command completion or response to an internal
41212 * processor, the order of writes has to be such that this field is
41218 /**********************
41219 * hwrm_cfa_pair_free *
41220 **********************/
41223 /* hwrm_cfa_pair_free_input (size:448b/56B) */
41224 struct hwrm_cfa_pair_free_input {
41225 /* The HWRM command request type. */
41228 * The completion ring to send the completion event on. This should
41229 * be the NQ ID returned from the `nq_alloc` HWRM command.
41231 uint16_t cmpl_ring;
41233 * The sequence ID is used by the driver for tracking multiple
41234 * commands. This ID is treated as opaque data by the firmware and
41235 * the value is returned in the `hwrm_resp_hdr` upon completion.
41239 * The target ID of the command:
41240 * * 0x0-0xFFF8 - The function ID
41241 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41242 * * 0xFFFD - Reserved for user-space HWRM interface
41245 uint16_t target_id;
41247 * A physical address pointer pointing to a host buffer that the
41248 * command's response data will be written. This can be either a host
41249 * physical address (HPA) or a guest physical address (GPA) and must
41250 * point to a physically contiguous block of memory.
41252 uint64_t resp_addr;
41253 /* VF Pair name (32 byte string). */
41254 char pair_name[32];
41255 /* Logical PF (0xff-PF for command channel). */
41257 uint8_t unused_0[3];
41258 /* Logical VF number (range: 0 -> MAX_VFS -1). */
41261 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
41262 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
41264 uint16_t pair_mode;
41265 /* Pair between VF on local host with PF or VF on specified host. */
41266 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
41267 /* Pair between REP on local host with PF or VF on specified host. */
41268 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
41269 /* Pair between REP on local host with REP on specified host. */
41270 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
41271 /* Pair for the proxy interface. */
41272 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
41273 /* Pair for the PF interface. */
41274 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
41275 /* Modify existing rep2fn pair and move pair to new PF. */
41276 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
41278 * Modify existing rep2fn pairs paired with same PF and move pairs
41281 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
41283 * Truflow pair between REP on local host with PF or VF on
41286 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
41287 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
41288 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
41291 /* hwrm_cfa_pair_free_output (size:128b/16B) */
41292 struct hwrm_cfa_pair_free_output {
41293 /* The specific error status for the command. */
41294 uint16_t error_code;
41295 /* The HWRM command request type. */
41297 /* The sequence ID from the original command. */
41299 /* The length of the response data in number of bytes. */
41301 uint8_t unused_0[7];
41303 * This field is used in Output records to indicate that the output
41304 * is completely written to RAM. This field should be read as '1'
41305 * to indicate that the output has been completely written.
41306 * When writing a command completion or response to an internal
41307 * processor, the order of writes has to be such that this field is
41313 /**********************
41314 * hwrm_cfa_pair_info *
41315 **********************/
41318 /* hwrm_cfa_pair_info_input (size:448b/56B) */
41319 struct hwrm_cfa_pair_info_input {
41320 /* The HWRM command request type. */
41323 * The completion ring to send the completion event on. This should
41324 * be the NQ ID returned from the `nq_alloc` HWRM command.
41326 uint16_t cmpl_ring;
41328 * The sequence ID is used by the driver for tracking multiple
41329 * commands. This ID is treated as opaque data by the firmware and
41330 * the value is returned in the `hwrm_resp_hdr` upon completion.
41334 * The target ID of the command:
41335 * * 0x0-0xFFF8 - The function ID
41336 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41337 * * 0xFFFD - Reserved for user-space HWRM interface
41340 uint16_t target_id;
41342 * A physical address pointer pointing to a host buffer that the
41343 * command's response data will be written. This can be either a host
41344 * physical address (HPA) or a guest physical address (GPA) and must
41345 * point to a physically contiguous block of memory.
41347 uint64_t resp_addr;
41349 /* If this flag is set, lookup by name else lookup by index. */
41350 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
41351 /* If this flag is set, lookup by PF id and VF id. */
41352 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
41353 /* Pair table index. */
41354 uint16_t pair_index;
41355 /* Pair pf index. */
41357 /* Pair vf index. */
41359 /* Pair name (32 byte string). */
41360 char pair_name[32];
41363 /* hwrm_cfa_pair_info_output (size:576b/72B) */
41364 struct hwrm_cfa_pair_info_output {
41365 /* The specific error status for the command. */
41366 uint16_t error_code;
41367 /* The HWRM command request type. */
41369 /* The sequence ID from the original command. */
41371 /* The length of the response data in number of bytes. */
41373 /* Pair table index. */
41374 uint16_t next_pair_index;
41375 /* Pair member a's fid. */
41377 /* Logical host number. */
41378 uint8_t host_a_index;
41379 /* Logical PF number. */
41380 uint8_t pf_a_index;
41381 /* Pair member a's Linux logical VF number. */
41382 uint16_t vf_a_index;
41384 uint16_t rx_cfa_code_a;
41385 /* Tx CFA action. */
41386 uint16_t tx_cfa_action_a;
41387 /* Pair member b's fid. */
41389 /* Logical host number. */
41390 uint8_t host_b_index;
41391 /* Logical PF number. */
41392 uint8_t pf_b_index;
41393 /* Pair member a's Linux logical VF number. */
41394 uint16_t vf_b_index;
41396 uint16_t rx_cfa_code_b;
41397 /* Tx CFA action. */
41398 uint16_t tx_cfa_action_b;
41399 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
41401 /* Pair between VF on local host with PF or VF on specified host. */
41402 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
41403 /* Pair between REP on local host with PF or VF on specified host. */
41404 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
41405 /* Pair between REP on local host with REP on specified host. */
41406 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
41407 /* Pair for the proxy interface. */
41408 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
41409 /* Pair for the PF interface. */
41410 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
41411 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
41412 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
41414 uint8_t pair_state;
41415 /* Pair has been allocated */
41416 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
41417 /* Both pair members are active */
41418 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
41419 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
41420 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
41421 /* Pair name (32 byte string). */
41422 char pair_name[32];
41423 uint8_t unused_0[7];
41425 * This field is used in Output records to indicate that the output
41426 * is completely written to RAM. This field should be read as '1'
41427 * to indicate that the output has been completely written.
41428 * When writing a command completion or response to an internal
41429 * processor, the order of writes has to be such that this field is
41435 /**********************
41436 * hwrm_cfa_vfr_alloc *
41437 **********************/
41440 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
41441 struct hwrm_cfa_vfr_alloc_input {
41442 /* The HWRM command request type. */
41445 * The completion ring to send the completion event on. This should
41446 * be the NQ ID returned from the `nq_alloc` HWRM command.
41448 uint16_t cmpl_ring;
41450 * The sequence ID is used by the driver for tracking multiple
41451 * commands. This ID is treated as opaque data by the firmware and
41452 * the value is returned in the `hwrm_resp_hdr` upon completion.
41456 * The target ID of the command:
41457 * * 0x0-0xFFF8 - The function ID
41458 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41459 * * 0xFFFD - Reserved for user-space HWRM interface
41462 uint16_t target_id;
41464 * A physical address pointer pointing to a host buffer that the
41465 * command's response data will be written. This can be either a host
41466 * physical address (HPA) or a guest physical address (GPA) and must
41467 * point to a physically contiguous block of memory.
41469 uint64_t resp_addr;
41470 /* Logical VF number (range: 0 -> MAX_VFS -1). */
41473 * This field is reserved for the future use.
41474 * It shall be set to 0.
41477 uint8_t unused_0[4];
41478 /* VF Representor name (32 byte string). */
41482 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
41483 struct hwrm_cfa_vfr_alloc_output {
41484 /* The specific error status for the command. */
41485 uint16_t error_code;
41486 /* The HWRM command request type. */
41488 /* The sequence ID from the original command. */
41490 /* The length of the response data in number of bytes. */
41493 uint16_t rx_cfa_code;
41494 /* Tx CFA action. */
41495 uint16_t tx_cfa_action;
41496 uint8_t unused_0[3];
41498 * This field is used in Output records to indicate that the output
41499 * is completely written to RAM. This field should be read as '1'
41500 * to indicate that the output has been completely written.
41501 * When writing a command completion or response to an internal
41502 * processor, the order of writes has to be such that this field is
41508 /*********************
41509 * hwrm_cfa_vfr_free *
41510 *********************/
41513 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
41514 struct hwrm_cfa_vfr_free_input {
41515 /* The HWRM command request type. */
41518 * The completion ring to send the completion event on. This should
41519 * be the NQ ID returned from the `nq_alloc` HWRM command.
41521 uint16_t cmpl_ring;
41523 * The sequence ID is used by the driver for tracking multiple
41524 * commands. This ID is treated as opaque data by the firmware and
41525 * the value is returned in the `hwrm_resp_hdr` upon completion.
41529 * The target ID of the command:
41530 * * 0x0-0xFFF8 - The function ID
41531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41532 * * 0xFFFD - Reserved for user-space HWRM interface
41535 uint16_t target_id;
41537 * A physical address pointer pointing to a host buffer that the
41538 * command's response data will be written. This can be either a host
41539 * physical address (HPA) or a guest physical address (GPA) and must
41540 * point to a physically contiguous block of memory.
41542 uint64_t resp_addr;
41543 /* VF Representor name (32 byte string). */
41545 /* Logical VF number (range: 0 -> MAX_VFS -1). */
41548 * This field is reserved for the future use.
41549 * It shall be set to 0.
41552 uint8_t unused_0[4];
41555 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
41556 struct hwrm_cfa_vfr_free_output {
41557 /* The specific error status for the command. */
41558 uint16_t error_code;
41559 /* The HWRM command request type. */
41561 /* The sequence ID from the original command. */
41563 /* The length of the response data in number of bytes. */
41565 uint8_t unused_0[7];
41567 * This field is used in Output records to indicate that the output
41568 * is completely written to RAM. This field should be read as '1'
41569 * to indicate that the output has been completely written.
41570 * When writing a command completion or response to an internal
41571 * processor, the order of writes has to be such that this field is
41577 /***************************************
41578 * hwrm_cfa_redirect_query_tunnel_type *
41579 ***************************************/
41582 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
41583 struct hwrm_cfa_redirect_query_tunnel_type_input {
41584 /* The HWRM command request type. */
41587 * The completion ring to send the completion event on. This should
41588 * be the NQ ID returned from the `nq_alloc` HWRM command.
41590 uint16_t cmpl_ring;
41592 * The sequence ID is used by the driver for tracking multiple
41593 * commands. This ID is treated as opaque data by the firmware and
41594 * the value is returned in the `hwrm_resp_hdr` upon completion.
41598 * The target ID of the command:
41599 * * 0x0-0xFFF8 - The function ID
41600 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41601 * * 0xFFFD - Reserved for user-space HWRM interface
41604 uint16_t target_id;
41606 * A physical address pointer pointing to a host buffer that the
41607 * command's response data will be written. This can be either a host
41608 * physical address (HPA) or a guest physical address (GPA) and must
41609 * point to a physically contiguous block of memory.
41611 uint64_t resp_addr;
41612 /* The source function id. */
41614 uint8_t unused_0[6];
41617 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
41618 struct hwrm_cfa_redirect_query_tunnel_type_output {
41619 /* The specific error status for the command. */
41620 uint16_t error_code;
41621 /* The HWRM command request type. */
41623 /* The sequence ID from the original command. */
41625 /* The length of the response data in number of bytes. */
41628 uint32_t tunnel_mask;
41630 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
41632 /* Virtual eXtensible Local Area Network (VXLAN) */
41633 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
41635 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
41636 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
41638 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
41639 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
41642 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
41644 /* Generic Network Virtualization Encapsulation (Geneve) */
41645 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
41647 /* Multi-Protocol Label Switching (MPLS) */
41648 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
41650 /* Stateless Transport Tunnel (STT) */
41651 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
41653 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
41654 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
41656 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
41657 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
41660 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
41663 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
41665 /* Any tunneled traffic */
41666 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
41668 /* Use fixed layer 2 ether type of 0xFFFF */
41669 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
41672 * IPV6 over virtual eXtensible Local Area Network with GPE header
41675 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
41677 uint8_t unused_0[3];
41679 * This field is used in Output records to indicate that the output
41680 * is completely written to RAM. This field should be read as '1'
41681 * to indicate that the output has been completely written.
41682 * When writing a command completion or response to an internal
41683 * processor, the order of writes has to be such that this field is
41689 /*************************
41690 * hwrm_cfa_ctx_mem_rgtr *
41691 *************************/
41694 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
41695 struct hwrm_cfa_ctx_mem_rgtr_input {
41696 /* The HWRM command request type. */
41699 * The completion ring to send the completion event on. This should
41700 * be the NQ ID returned from the `nq_alloc` HWRM command.
41702 uint16_t cmpl_ring;
41704 * The sequence ID is used by the driver for tracking multiple
41705 * commands. This ID is treated as opaque data by the firmware and
41706 * the value is returned in the `hwrm_resp_hdr` upon completion.
41710 * The target ID of the command:
41711 * * 0x0-0xFFF8 - The function ID
41712 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41713 * * 0xFFFD - Reserved for user-space HWRM interface
41716 uint16_t target_id;
41718 * A physical address pointer pointing to a host buffer that the
41719 * command's response data will be written. This can be either a host
41720 * physical address (HPA) or a guest physical address (GPA) and must
41721 * point to a physically contiguous block of memory.
41723 uint64_t resp_addr;
41725 /* Counter PBL indirect levels. */
41726 uint8_t page_level;
41727 /* PBL pointer is physical start address. */
41728 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
41729 /* PBL pointer points to PTE table. */
41730 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
41732 * PBL pointer points to PDE table with each entry pointing to PTE
41735 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
41736 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
41737 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
41740 /* 4KB page size. */
41741 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
41742 /* 8KB page size. */
41743 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
41744 /* 64KB page size. */
41745 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
41746 /* 256KB page size. */
41747 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
41748 /* 1MB page size. */
41749 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
41750 /* 2MB page size. */
41751 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
41752 /* 4MB page size. */
41753 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
41754 /* 1GB page size. */
41755 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
41756 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
41757 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
41759 /* Pointer to the PBL, or PDL depending on number of levels */
41763 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
41764 struct hwrm_cfa_ctx_mem_rgtr_output {
41765 /* The specific error status for the command. */
41766 uint16_t error_code;
41767 /* The HWRM command request type. */
41769 /* The sequence ID from the original command. */
41771 /* The length of the response data in number of bytes. */
41774 * Id/Handle to the recently register context memory. This handle is
41775 * passed to the CFA feature.
41778 uint8_t unused_0[5];
41780 * This field is used in Output records to indicate that the output
41781 * is completely written to RAM. This field should be read as '1'
41782 * to indicate that the output has been completely written.
41783 * When writing a command completion or response to an internal
41784 * processor, the order of writes has to be such that this field is
41790 /***************************
41791 * hwrm_cfa_ctx_mem_unrgtr *
41792 ***************************/
41795 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
41796 struct hwrm_cfa_ctx_mem_unrgtr_input {
41797 /* The HWRM command request type. */
41800 * The completion ring to send the completion event on. This should
41801 * be the NQ ID returned from the `nq_alloc` HWRM command.
41803 uint16_t cmpl_ring;
41805 * The sequence ID is used by the driver for tracking multiple
41806 * commands. This ID is treated as opaque data by the firmware and
41807 * the value is returned in the `hwrm_resp_hdr` upon completion.
41811 * The target ID of the command:
41812 * * 0x0-0xFFF8 - The function ID
41813 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41814 * * 0xFFFD - Reserved for user-space HWRM interface
41817 uint16_t target_id;
41819 * A physical address pointer pointing to a host buffer that the
41820 * command's response data will be written. This can be either a host
41821 * physical address (HPA) or a guest physical address (GPA) and must
41822 * point to a physically contiguous block of memory.
41824 uint64_t resp_addr;
41826 * Id/Handle to the recently register context memory. This handle is
41827 * passed to the CFA feature.
41830 uint8_t unused_0[6];
41833 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
41834 struct hwrm_cfa_ctx_mem_unrgtr_output {
41835 /* The specific error status for the command. */
41836 uint16_t error_code;
41837 /* The HWRM command request type. */
41839 /* The sequence ID from the original command. */
41841 /* The length of the response data in number of bytes. */
41843 uint8_t unused_0[7];
41845 * This field is used in Output records to indicate that the output
41846 * is completely written to RAM. This field should be read as '1'
41847 * to indicate that the output has been completely written.
41848 * When writing a command completion or response to an internal
41849 * processor, the order of writes has to be such that this field is
41855 /*************************
41856 * hwrm_cfa_ctx_mem_qctx *
41857 *************************/
41860 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
41861 struct hwrm_cfa_ctx_mem_qctx_input {
41862 /* The HWRM command request type. */
41865 * The completion ring to send the completion event on. This should
41866 * be the NQ ID returned from the `nq_alloc` HWRM command.
41868 uint16_t cmpl_ring;
41870 * The sequence ID is used by the driver for tracking multiple
41871 * commands. This ID is treated as opaque data by the firmware and
41872 * the value is returned in the `hwrm_resp_hdr` upon completion.
41876 * The target ID of the command:
41877 * * 0x0-0xFFF8 - The function ID
41878 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41879 * * 0xFFFD - Reserved for user-space HWRM interface
41882 uint16_t target_id;
41884 * A physical address pointer pointing to a host buffer that the
41885 * command's response data will be written. This can be either a host
41886 * physical address (HPA) or a guest physical address (GPA) and must
41887 * point to a physically contiguous block of memory.
41889 uint64_t resp_addr;
41891 * Id/Handle to the recently register context memory. This handle is
41892 * passed to the CFA feature.
41895 uint8_t unused_0[6];
41898 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
41899 struct hwrm_cfa_ctx_mem_qctx_output {
41900 /* The specific error status for the command. */
41901 uint16_t error_code;
41902 /* The HWRM command request type. */
41904 /* The sequence ID from the original command. */
41906 /* The length of the response data in number of bytes. */
41909 /* Counter PBL indirect levels. */
41910 uint8_t page_level;
41911 /* PBL pointer is physical start address. */
41912 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
41913 /* PBL pointer points to PTE table. */
41914 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
41916 * PBL pointer points to PDE table with each entry pointing to PTE
41919 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
41920 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
41921 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
41924 /* 4KB page size. */
41925 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
41926 /* 8KB page size. */
41927 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
41928 /* 64KB page size. */
41929 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
41930 /* 256KB page size. */
41931 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
41932 /* 1MB page size. */
41933 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
41934 /* 2MB page size. */
41935 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
41936 /* 4MB page size. */
41937 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
41938 /* 1GB page size. */
41939 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
41940 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
41941 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
41942 uint8_t unused_0[4];
41943 /* Pointer to the PBL, or PDL depending on number of levels */
41945 uint8_t unused_1[7];
41947 * This field is used in Output records to indicate that the output
41948 * is completely written to RAM. This field should be read as '1'
41949 * to indicate that the output has been completely written.
41950 * When writing a command completion or response to an internal
41951 * processor, the order of writes has to be such that this field is
41957 /**************************
41958 * hwrm_cfa_ctx_mem_qcaps *
41959 **************************/
41962 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
41963 struct hwrm_cfa_ctx_mem_qcaps_input {
41964 /* The HWRM command request type. */
41967 * The completion ring to send the completion event on. This should
41968 * be the NQ ID returned from the `nq_alloc` HWRM command.
41970 uint16_t cmpl_ring;
41972 * The sequence ID is used by the driver for tracking multiple
41973 * commands. This ID is treated as opaque data by the firmware and
41974 * the value is returned in the `hwrm_resp_hdr` upon completion.
41978 * The target ID of the command:
41979 * * 0x0-0xFFF8 - The function ID
41980 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41981 * * 0xFFFD - Reserved for user-space HWRM interface
41984 uint16_t target_id;
41986 * A physical address pointer pointing to a host buffer that the
41987 * command's response data will be written. This can be either a host
41988 * physical address (HPA) or a guest physical address (GPA) and must
41989 * point to a physically contiguous block of memory.
41991 uint64_t resp_addr;
41994 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
41995 struct hwrm_cfa_ctx_mem_qcaps_output {
41996 /* The specific error status for the command. */
41997 uint16_t error_code;
41998 /* The HWRM command request type. */
42000 /* The sequence ID from the original command. */
42002 /* The length of the response data in number of bytes. */
42005 * Indicates the maximum number of context memory which can be
42008 uint16_t max_entries;
42009 uint8_t unused_0[5];
42011 * This field is used in Output records to indicate that the output
42012 * is completely written to RAM. This field should be read as '1'
42013 * to indicate that the output has been completely written.
42014 * When writing a command completion or response to an internal
42015 * processor, the order of writes has to be such that this field is
42021 /**************************
42022 * hwrm_cfa_counter_qcaps *
42023 **************************/
42026 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
42027 struct hwrm_cfa_counter_qcaps_input {
42028 /* The HWRM command request type. */
42031 * The completion ring to send the completion event on. This should
42032 * be the NQ ID returned from the `nq_alloc` HWRM command.
42034 uint16_t cmpl_ring;
42036 * The sequence ID is used by the driver for tracking multiple
42037 * commands. This ID is treated as opaque data by the firmware and
42038 * the value is returned in the `hwrm_resp_hdr` upon completion.
42042 * The target ID of the command:
42043 * * 0x0-0xFFF8 - The function ID
42044 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42045 * * 0xFFFD - Reserved for user-space HWRM interface
42048 uint16_t target_id;
42050 * A physical address pointer pointing to a host buffer that the
42051 * command's response data will be written. This can be either a host
42052 * physical address (HPA) or a guest physical address (GPA) and must
42053 * point to a physically contiguous block of memory.
42055 uint64_t resp_addr;
42058 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
42059 struct hwrm_cfa_counter_qcaps_output {
42060 /* The specific error status for the command. */
42061 uint16_t error_code;
42062 /* The HWRM command request type. */
42064 /* The sequence ID from the original command. */
42066 /* The length of the response data in number of bytes. */
42069 /* Enumeration denoting the supported CFA counter format. */
42070 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
42072 /* CFA counter types are not supported. */
42073 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
42075 /* 64-bit packet counters followed by 64-bit byte counters format. */
42076 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
42078 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
42079 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
42082 * Minimum guaranteed number of flow counters supported for this
42083 * function, in RX direction.
42085 uint32_t min_rx_fc;
42087 * Maximum non-guaranteed number of flow counters supported for this
42088 * function, in RX direction.
42090 uint32_t max_rx_fc;
42092 * Minimum guaranteed number of flow counters supported for this
42093 * function, in TX direction.
42095 uint32_t min_tx_fc;
42097 * Maximum non-guaranteed number of flow counters supported for this
42098 * function, in TX direction.
42100 uint32_t max_tx_fc;
42102 * Minimum guaranteed number of extension flow counters supported for
42103 * this function, in RX direction.
42105 uint32_t min_rx_efc;
42107 * Maximum non-guaranteed number of extension flow counters supported
42108 * for this function, in RX direction.
42110 uint32_t max_rx_efc;
42112 * Minimum guaranteed number of extension flow counters supported for
42113 * this function, in TX direction.
42115 uint32_t min_tx_efc;
42117 * Maximum non-guaranteed number of extension flow counters supported
42118 * for this function, in TX direction.
42120 uint32_t max_tx_efc;
42122 * Minimum guaranteed number of meter drop counters supported for
42123 * this function, in RX direction.
42125 uint32_t min_rx_mdc;
42127 * Maximum non-guaranteed number of meter drop counters supported for
42128 * this function, in RX direction.
42130 uint32_t max_rx_mdc;
42132 * Minimum guaranteed number of meter drop counters supported for this
42133 * function, in TX direction.
42135 uint32_t min_tx_mdc;
42137 * Maximum non-guaranteed number of meter drop counters supported for
42138 * this function, in TX direction.
42140 uint32_t max_tx_mdc;
42142 * Maximum guaranteed number of flow counters which can be used during
42145 uint32_t max_flow_alloc_fc;
42146 uint8_t unused_1[3];
42148 * This field is used in Output records to indicate that the output
42149 * is completely written to RAM. This field should be read as '1'
42150 * to indicate that the output has been completely written.
42151 * When writing a command completion or response to an internal
42152 * processor, the order of writes has to be such that this field is
42158 /************************
42159 * hwrm_cfa_counter_cfg *
42160 ************************/
42163 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
42164 struct hwrm_cfa_counter_cfg_input {
42165 /* The HWRM command request type. */
42168 * The completion ring to send the completion event on. This should
42169 * be the NQ ID returned from the `nq_alloc` HWRM command.
42171 uint16_t cmpl_ring;
42173 * The sequence ID is used by the driver for tracking multiple
42174 * commands. This ID is treated as opaque data by the firmware and
42175 * the value is returned in the `hwrm_resp_hdr` upon completion.
42179 * The target ID of the command:
42180 * * 0x0-0xFFF8 - The function ID
42181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42182 * * 0xFFFD - Reserved for user-space HWRM interface
42185 uint16_t target_id;
42187 * A physical address pointer pointing to a host buffer that the
42188 * command's response data will be written. This can be either a host
42189 * physical address (HPA) or a guest physical address (GPA) and must
42190 * point to a physically contiguous block of memory.
42192 uint64_t resp_addr;
42194 /* Enumeration denoting the configuration mode. */
42195 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
42197 /* Disable the configuration mode. */
42198 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
42200 /* Enable the configuration mode. */
42201 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
42203 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
42204 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
42205 /* Enumeration denoting the RX, TX type of the resource. */
42206 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
42209 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
42210 (UINT32_C(0x0) << 1)
42212 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
42213 (UINT32_C(0x1) << 1)
42214 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
42215 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
42216 /* Enumeration denoting the data transfer mode. */
42217 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
42219 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
42221 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
42222 (UINT32_C(0x0) << 2)
42224 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
42225 (UINT32_C(0x1) << 2)
42226 /* Pull on async update. */
42227 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
42228 (UINT32_C(0x2) << 2)
42229 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
42230 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
42231 uint16_t counter_type;
42232 /* Flow counters. */
42233 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
42234 /* Extended flow counters. */
42235 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
42236 /* Meter drop counters. */
42237 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
42238 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
42239 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
42240 /* Ctx memory handle to be used for the counter. */
42242 /* Counter update cadence hint (only in Push mode). */
42243 uint16_t update_tmr_ms;
42244 /* Total number of entries. */
42245 uint32_t num_entries;
42249 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
42250 struct hwrm_cfa_counter_cfg_output {
42251 /* The specific error status for the command. */
42252 uint16_t error_code;
42253 /* The HWRM command request type. */
42255 /* The sequence ID from the original command. */
42257 /* The length of the response data in number of bytes. */
42259 uint8_t unused_0[7];
42261 * This field is used in Output records to indicate that the output
42262 * is completely written to RAM. This field should be read as '1'
42263 * to indicate that the output has been completely written.
42264 * When writing a command completion or response to an internal
42265 * processor, the order of writes has to be such that this field is
42271 /***************************
42272 * hwrm_cfa_counter_qstats *
42273 ***************************/
42276 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
42277 struct hwrm_cfa_counter_qstats_input {
42278 /* The HWRM command request type. */
42281 * The completion ring to send the completion event on. This should
42282 * be the NQ ID returned from the `nq_alloc` HWRM command.
42284 uint16_t cmpl_ring;
42286 * The sequence ID is used by the driver for tracking multiple
42287 * commands. This ID is treated as opaque data by the firmware and
42288 * the value is returned in the `hwrm_resp_hdr` upon completion.
42292 * The target ID of the command:
42293 * * 0x0-0xFFF8 - The function ID
42294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42295 * * 0xFFFD - Reserved for user-space HWRM interface
42298 uint16_t target_id;
42300 * A physical address pointer pointing to a host buffer that the
42301 * command's response data will be written. This can be either a host
42302 * physical address (HPA) or a guest physical address (GPA) and must
42303 * point to a physically contiguous block of memory.
42305 uint64_t resp_addr;
42307 /* Enumeration denoting the RX, TX type of the resource. */
42308 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
42310 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
42312 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
42313 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
42314 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
42315 uint16_t counter_type;
42316 uint16_t input_flow_ctx_id;
42317 uint16_t num_entries;
42318 uint16_t delta_time_ms;
42319 uint16_t meter_instance_id;
42320 uint16_t mdc_ctx_id;
42321 uint8_t unused_0[2];
42322 uint64_t expected_count;
42325 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
42326 struct hwrm_cfa_counter_qstats_output {
42327 /* The specific error status for the command. */
42328 uint16_t error_code;
42329 /* The HWRM command request type. */
42331 /* The sequence ID from the original command. */
42333 /* The length of the response data in number of bytes. */
42335 uint8_t unused_0[7];
42337 * This field is used in Output records to indicate that the output
42338 * is completely written to RAM. This field should be read as '1'
42339 * to indicate that the output has been completely written.
42340 * When writing a command completion or response to an internal
42341 * processor, the order of writes has to be such that this field is
42347 /**********************
42348 * hwrm_cfa_eem_qcaps *
42349 **********************/
42352 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
42353 struct hwrm_cfa_eem_qcaps_input {
42354 /* The HWRM command request type. */
42357 * The completion ring to send the completion event on. This should
42358 * be the NQ ID returned from the `nq_alloc` HWRM command.
42360 uint16_t cmpl_ring;
42362 * The sequence ID is used by the driver for tracking multiple
42363 * commands. This ID is treated as opaque data by the firmware and
42364 * the value is returned in the `hwrm_resp_hdr` upon completion.
42368 * The target ID of the command:
42369 * * 0x0-0xFFF8 - The function ID
42370 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42371 * * 0xFFFD - Reserved for user-space HWRM interface
42374 uint16_t target_id;
42376 * A physical address pointer pointing to a host buffer that the
42377 * command's response data will be written. This can be either a host
42378 * physical address (HPA) or a guest physical address (GPA) and must
42379 * point to a physically contiguous block of memory.
42381 uint64_t resp_addr;
42384 * When set to 1, indicates the configuration will apply to TX flows
42385 * which are to be offloaded.
42386 * Note if this bit is set then the path_rx bit can't be set.
42388 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
42391 * When set to 1, indicates the configuration will apply to RX flows
42392 * which are to be offloaded.
42393 * Note if this bit is set then the path_tx bit can't be set.
42395 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
42397 /* When set to 1, all offloaded flows will be sent to EEM. */
42398 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
42403 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
42404 struct hwrm_cfa_eem_qcaps_output {
42405 /* The specific error status for the command. */
42406 uint16_t error_code;
42407 /* The HWRM command request type. */
42409 /* The sequence ID from the original command. */
42411 /* The length of the response data in number of bytes. */
42415 * When set to 1, indicates the configuration will apply to TX flows
42416 * which are to be offloaded.
42417 * Note if this bit is set then the path_rx bit can't be set.
42419 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
42422 * When set to 1, indicates the configuration will apply to RX flows
42423 * which are to be offloaded.
42424 * Note if this bit is set then the path_tx bit can't be set.
42426 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
42429 * When set to 1, indicates the FW supports the Centralized
42430 * Memory Model. The concept designates one entity for the
42431 * memory allocation while all others ‘subscribe’ to it.
42433 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
42436 * When set to 1, indicates the FW supports the Detached
42437 * Centralized Memory Model. The memory is allocated and managed
42438 * as a separate entity. All PFs and VFs will be granted direct
42439 * or semi-direct access to the allocated memory while none of
42440 * which can interfere with the management of the memory.
42442 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
42445 uint32_t supported;
42447 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
42448 * If set to 0, EEM KEY0 table is not supported.
42450 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
42453 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
42454 * If set to 0, EEM KEY1 table is not supported.
42456 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
42459 * If set to 1, then EEM External Record table is supported.
42460 * If set to 0, EEM External Record table is not supported.
42461 * (This table includes action record, EFC pointers, encap pointers)
42463 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
42466 * If set to 1, then EEM External Flow Counters table is supported.
42467 * If set to 0, EEM External Flow Counters table is not supported.
42469 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
42472 * If set to 1, then FID table used for implicit flow flush is
42474 * If set to 0, then FID table used for implicit flow flush is
42477 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
42480 * The maximum number of entries supported by EEM. When configuring
42481 * the host memory, the number of numbers of entries that can
42483 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
42485 * Any value that are not these values, the FW will round down to the
42486 * closest support number of entries.
42488 uint32_t max_entries_supported;
42489 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
42490 uint16_t key_entry_size;
42491 /* The entry size in bytes of each entry in the EEM RECORD tables. */
42492 uint16_t record_entry_size;
42493 /* The entry size in bytes of each entry in the EEM EFC tables. */
42494 uint16_t efc_entry_size;
42495 /* The FID size in bytes of each entry in the EEM FID tables. */
42496 uint16_t fid_entry_size;
42497 uint8_t unused_1[7];
42499 * This field is used in Output records to indicate that the output
42500 * is completely written to RAM. This field should be read as '1'
42501 * to indicate that the output has been completely written.
42502 * When writing a command completion or response to an internal
42503 * processor, the order of writes has to be such that this field is
42509 /********************
42510 * hwrm_cfa_eem_cfg *
42511 ********************/
42514 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
42515 struct hwrm_cfa_eem_cfg_input {
42516 /* The HWRM command request type. */
42519 * The completion ring to send the completion event on. This should
42520 * be the NQ ID returned from the `nq_alloc` HWRM command.
42522 uint16_t cmpl_ring;
42524 * The sequence ID is used by the driver for tracking multiple
42525 * commands. This ID is treated as opaque data by the firmware and
42526 * the value is returned in the `hwrm_resp_hdr` upon completion.
42530 * The target ID of the command:
42531 * * 0x0-0xFFF8 - The function ID
42532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42533 * * 0xFFFD - Reserved for user-space HWRM interface
42536 uint16_t target_id;
42538 * A physical address pointer pointing to a host buffer that the
42539 * command's response data will be written. This can be either a host
42540 * physical address (HPA) or a guest physical address (GPA) and must
42541 * point to a physically contiguous block of memory.
42543 uint64_t resp_addr;
42546 * When set to 1, indicates the configuration will apply to TX flows
42547 * which are to be offloaded.
42548 * Note if this bit is set then the path_rx bit can't be set.
42550 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
42553 * When set to 1, indicates the configuration will apply to RX flows
42554 * which are to be offloaded.
42555 * Note if this bit is set then the path_tx bit can't be set.
42557 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
42559 /* When set to 1, all offloaded flows will be sent to EEM. */
42560 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
42562 /* When set to 1, secondary, 0 means primary. */
42563 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
42566 * Group_id which used by Firmware to identify memory pools belonging
42567 * to certain group.
42572 * Configured EEM with the given number of entries. All the EEM tables
42573 * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
42574 * tables will be configured using this value. Current minimum value
42575 * is 32k. Current maximum value is 128M.
42577 uint32_t num_entries;
42579 /* Configured EEM with the given context if for KEY0 table. */
42580 uint16_t key0_ctx_id;
42581 /* Configured EEM with the given context if for KEY1 table. */
42582 uint16_t key1_ctx_id;
42583 /* Configured EEM with the given context if for RECORD table. */
42584 uint16_t record_ctx_id;
42585 /* Configured EEM with the given context if for EFC table. */
42586 uint16_t efc_ctx_id;
42587 /* Configured EEM with the given context if for EFC table. */
42588 uint16_t fid_ctx_id;
42593 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
42594 struct hwrm_cfa_eem_cfg_output {
42595 /* The specific error status for the command. */
42596 uint16_t error_code;
42597 /* The HWRM command request type. */
42599 /* The sequence ID from the original command. */
42601 /* The length of the response data in number of bytes. */
42603 uint8_t unused_0[7];
42605 * This field is used in Output records to indicate that the output
42606 * is completely written to RAM. This field should be read as '1'
42607 * to indicate that the output has been completely written.
42608 * When writing a command completion or response to an internal
42609 * processor, the order of writes has to be such that this field is
42615 /*********************
42616 * hwrm_cfa_eem_qcfg *
42617 *********************/
42620 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
42621 struct hwrm_cfa_eem_qcfg_input {
42622 /* The HWRM command request type. */
42625 * The completion ring to send the completion event on. This should
42626 * be the NQ ID returned from the `nq_alloc` HWRM command.
42628 uint16_t cmpl_ring;
42630 * The sequence ID is used by the driver for tracking multiple
42631 * commands. This ID is treated as opaque data by the firmware and
42632 * the value is returned in the `hwrm_resp_hdr` upon completion.
42636 * The target ID of the command:
42637 * * 0x0-0xFFF8 - The function ID
42638 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42639 * * 0xFFFD - Reserved for user-space HWRM interface
42642 uint16_t target_id;
42644 * A physical address pointer pointing to a host buffer that the
42645 * command's response data will be written. This can be either a host
42646 * physical address (HPA) or a guest physical address (GPA) and must
42647 * point to a physically contiguous block of memory.
42649 uint64_t resp_addr;
42651 /* When set to 1, indicates the configuration is the TX flow. */
42652 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
42653 /* When set to 1, indicates the configuration is the RX flow. */
42654 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
42658 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
42659 struct hwrm_cfa_eem_qcfg_output {
42660 /* The specific error status for the command. */
42661 uint16_t error_code;
42662 /* The HWRM command request type. */
42664 /* The sequence ID from the original command. */
42666 /* The length of the response data in number of bytes. */
42669 /* When set to 1, indicates the configuration is the TX flow. */
42670 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
42672 /* When set to 1, indicates the configuration is the RX flow. */
42673 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
42675 /* When set to 1, all offloaded flows will be sent to EEM. */
42676 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
42678 /* The number of entries the FW has configured for EEM. */
42679 uint32_t num_entries;
42680 /* Configured EEM with the given context if for KEY0 table. */
42681 uint16_t key0_ctx_id;
42682 /* Configured EEM with the given context if for KEY1 table. */
42683 uint16_t key1_ctx_id;
42684 /* Configured EEM with the given context if for RECORD table. */
42685 uint16_t record_ctx_id;
42686 /* Configured EEM with the given context if for EFC table. */
42687 uint16_t efc_ctx_id;
42688 /* Configured EEM with the given context if for EFC table. */
42689 uint16_t fid_ctx_id;
42690 uint8_t unused_2[5];
42692 * This field is used in Output records to indicate that the output
42693 * is completely written to RAM. This field should be read as '1'
42694 * to indicate that the output has been completely written.
42695 * When writing a command completion or response to an internal
42696 * processor, the order of writes has to be such that this field is
42702 /*******************
42703 * hwrm_cfa_eem_op *
42704 *******************/
42707 /* hwrm_cfa_eem_op_input (size:192b/24B) */
42708 struct hwrm_cfa_eem_op_input {
42709 /* The HWRM command request type. */
42712 * The completion ring to send the completion event on. This should
42713 * be the NQ ID returned from the `nq_alloc` HWRM command.
42715 uint16_t cmpl_ring;
42717 * The sequence ID is used by the driver for tracking multiple
42718 * commands. This ID is treated as opaque data by the firmware and
42719 * the value is returned in the `hwrm_resp_hdr` upon completion.
42723 * The target ID of the command:
42724 * * 0x0-0xFFF8 - The function ID
42725 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42726 * * 0xFFFD - Reserved for user-space HWRM interface
42729 uint16_t target_id;
42731 * A physical address pointer pointing to a host buffer that the
42732 * command's response data will be written. This can be either a host
42733 * physical address (HPA) or a guest physical address (GPA) and must
42734 * point to a physically contiguous block of memory.
42736 uint64_t resp_addr;
42739 * When set to 1, indicates the host memory which is passed will be
42740 * used for the TX flow offload function specified in fid.
42741 * Note if this bit is set then the path_rx bit can't be set.
42743 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
42745 * When set to 1, indicates the host memory which is passed will be
42746 * used for the RX flow offload function specified in fid.
42747 * Note if this bit is set then the path_tx bit can't be set.
42749 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
42751 /* The number of EEM key table entries to be configured. */
42753 /* This value is reserved and should not be used. */
42754 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
42756 * To properly stop EEM and ensure there are no DMA's, the caller
42757 * must disable EEM for the given PF, using this call. This will
42758 * safely disable EEM and ensure that all DMA'ed to the
42759 * keys/records/efc have been completed.
42761 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
42763 * Once the EEM host memory has been configured, EEM options have
42764 * been configured. Then the caller should enable EEM for the given
42765 * PF. Note once this call has been made, then the EEM mechanism
42766 * will be active and DMA's will occur as packets are processed.
42768 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
42770 * Clear EEM settings for the given PF so that the register values
42771 * are reset back to there initial state.
42773 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
42774 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
42775 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
42778 /* hwrm_cfa_eem_op_output (size:128b/16B) */
42779 struct hwrm_cfa_eem_op_output {
42780 /* The specific error status for the command. */
42781 uint16_t error_code;
42782 /* The HWRM command request type. */
42784 /* The sequence ID from the original command. */
42786 /* The length of the response data in number of bytes. */
42788 uint8_t unused_0[7];
42790 * This field is used in Output records to indicate that the output
42791 * is completely written to RAM. This field should be read as '1'
42792 * to indicate that the output has been completely written.
42793 * When writing a command completion or response to an internal
42794 * processor, the order of writes has to be such that this field is
42800 /********************************
42801 * hwrm_cfa_adv_flow_mgnt_qcaps *
42802 ********************************/
42805 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
42806 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
42807 /* The HWRM command request type. */
42810 * The completion ring to send the completion event on. This should
42811 * be the NQ ID returned from the `nq_alloc` HWRM command.
42813 uint16_t cmpl_ring;
42815 * The sequence ID is used by the driver for tracking multiple
42816 * commands. This ID is treated as opaque data by the firmware and
42817 * the value is returned in the `hwrm_resp_hdr` upon completion.
42821 * The target ID of the command:
42822 * * 0x0-0xFFF8 - The function ID
42823 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42824 * * 0xFFFD - Reserved for user-space HWRM interface
42827 uint16_t target_id;
42829 * A physical address pointer pointing to a host buffer that the
42830 * command's response data will be written. This can be either a host
42831 * physical address (HPA) or a guest physical address (GPA) and must
42832 * point to a physically contiguous block of memory.
42834 uint64_t resp_addr;
42835 uint32_t unused_0[4];
42838 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
42839 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
42840 /* The specific error status for the command. */
42841 uint16_t error_code;
42842 /* The HWRM command request type. */
42844 /* The sequence ID from the original command. */
42846 /* The length of the response data in number of bytes. */
42850 * Value of 1 to indicate firmware support 16-bit flow handle.
42851 * Value of 0 to indicate firmware not support 16-bit flow handle.
42853 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
42856 * Value of 1 to indicate firmware support 64-bit flow handle.
42857 * Value of 0 to indicate firmware not support 64-bit flow handle.
42859 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
42862 * Value of 1 to indicate firmware support flow batch delete
42863 * operation through HWRM_CFA_FLOW_FLUSH command.
42864 * Value of 0 to indicate that the firmware does not support flow
42865 * batch delete operation.
42867 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
42870 * Value of 1 to indicate that the firmware support flow reset all
42871 * operation through HWRM_CFA_FLOW_FLUSH command.
42872 * Value of 0 indicates firmware does not support flow reset all
42875 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
42878 * Value of 1 to indicate that firmware supports use of FID as
42879 * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
42880 * Value of 0 indicates firmware does not support use of FID as
42883 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
42886 * Value of 1 to indicate that firmware supports TX EEM flows.
42887 * Value of 0 indicates firmware does not support TX EEM flows.
42889 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
42892 * Value of 1 to indicate that firmware supports RX EEM flows.
42893 * Value of 0 indicates firmware does not support RX EEM flows.
42895 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
42898 * Value of 1 to indicate that firmware supports the dynamic
42899 * allocation of an on-chip flow counter which can be used for EEM
42900 * flows. Value of 0 indicates firmware does not support the dynamic
42901 * allocation of an on-chip flow counter.
42903 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
42906 * Value of 1 to indicate that firmware supports setting of
42907 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
42908 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
42910 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
42913 * Value of 1 to indicate that firmware supports untagged matching
42914 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
42915 * indicates firmware does not support untagged matching.
42917 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
42920 * Value of 1 to indicate that firmware supports XDP filter. Value
42921 * of 0 indicates firmware does not support XDP filter.
42923 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
42926 * Value of 1 to indicate that the firmware support L2 header source
42927 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
42928 * Value of 0 indicates firmware does not support L2 header source
42931 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
42934 * If set to 1, firmware is capable of supporting ARP ethertype as
42935 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
42936 * RX direction. By default, this flag should be 0 for older version
42939 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
42942 * Value of 1 to indicate that firmware supports setting of
42943 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
42944 * command. Value of 0 indicates firmware does not support
42945 * rfs_ring_tbl_idx in dst_id field.
42947 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
42950 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
42951 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
42952 * direction. By default, this flag should be 0 for older version
42955 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
42958 * When this bit is '1', it indicates that core firmware is
42959 * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
42960 * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
42962 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
42965 * If set to 1, firmware is capable of supporting L2/ROCE as
42966 * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
42967 * By default, this flag should be 0 for older version of firmware.
42969 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
42972 * If set to 1, firmware is capable of HW LAG. This bit is only
42973 * advertised if the calling function is a PAXC function.
42975 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \
42977 uint8_t unused_0[3];
42979 * This field is used in Output records to indicate that the output
42980 * is completely written to RAM. This field should be read as '1'
42981 * to indicate that the output has been completely written.
42982 * When writing a command completion or response to an internal
42983 * processor, the order of writes has to be such that this field is
42989 /******************
42991 ******************/
42994 /* hwrm_cfa_tflib_input (size:1024b/128B) */
42995 struct hwrm_cfa_tflib_input {
42996 /* The HWRM command request type. */
42999 * The completion ring to send the completion event on. This should
43000 * be the NQ ID returned from the `nq_alloc` HWRM command.
43002 uint16_t cmpl_ring;
43004 * The sequence ID is used by the driver for tracking multiple
43005 * commands. This ID is treated as opaque data by the firmware and
43006 * the value is returned in the `hwrm_resp_hdr` upon completion.
43010 * The target ID of the command:
43011 * * 0x0-0xFFF8 - The function ID
43012 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43013 * * 0xFFFD - Reserved for user-space HWRM interface
43016 uint16_t target_id;
43018 * A physical address pointer pointing to a host buffer that the
43019 * command's response data will be written. This can be either a host
43020 * physical address (HPA) or a guest physical address (GPA) and must
43021 * point to a physically contiguous block of memory.
43023 uint64_t resp_addr;
43024 /* TFLIB message type. */
43026 /* TFLIB message subtype. */
43027 uint16_t tf_subtype;
43029 uint8_t unused0[4];
43030 /* TFLIB request data. */
43031 uint32_t tf_req[26];
43034 /* hwrm_cfa_tflib_output (size:5632b/704B) */
43035 struct hwrm_cfa_tflib_output {
43036 /* The specific error status for the command. */
43037 uint16_t error_code;
43038 /* The HWRM command request type. */
43040 /* The sequence ID from the original command. */
43042 /* The length of the response data in number of bytes. */
43044 /* TFLIB message type. */
43046 /* TFLIB message subtype. */
43047 uint16_t tf_subtype;
43048 /* TFLIB response code */
43049 uint32_t tf_resp_code;
43050 /* TFLIB response data. */
43051 uint32_t tf_resp[170];
43053 uint8_t unused1[7];
43055 * This field is used in Output records to indicate that the output
43056 * is completely written to RAM. This field should be read as '1'
43057 * to indicate that the output has been completely written.
43058 * When writing a command completion or response to an internal
43059 * processor, the order of writes has to be such that this field is
43070 /* hwrm_tf_input (size:1024b/128B) */
43071 struct hwrm_tf_input {
43072 /* The HWRM command request type. */
43075 * The completion ring to send the completion event on. This should
43076 * be the NQ ID returned from the `nq_alloc` HWRM command.
43078 uint16_t cmpl_ring;
43080 * The sequence ID is used by the driver for tracking multiple
43081 * commands. This ID is treated as opaque data by the firmware and
43082 * the value is returned in the `hwrm_resp_hdr` upon completion.
43086 * The target ID of the command:
43087 * * 0x0-0xFFF8 - The function ID
43088 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43089 * * 0xFFFD - Reserved for user-space HWRM interface
43092 uint16_t target_id;
43094 * A physical address pointer pointing to a host buffer that the
43095 * command's response data will be written. This can be either a host
43096 * physical address (HPA) or a guest physical address (GPA) and must
43097 * point to a physically contiguous block of memory.
43099 uint64_t resp_addr;
43100 /* TF message type. */
43102 /* TF message subtype. */
43105 uint8_t unused0[4];
43106 /* TF request data. */
43110 /* hwrm_tf_output (size:5632b/704B) */
43111 struct hwrm_tf_output {
43112 /* The specific error status for the command. */
43113 uint16_t error_code;
43114 /* The HWRM command request type. */
43116 /* The sequence ID from the original command. */
43118 /* The length of the response data in number of bytes. */
43120 /* TF message type. */
43122 /* TF message subtype. */
43124 /* TF response code */
43125 uint32_t resp_code;
43126 /* TF response data. */
43127 uint32_t resp[170];
43129 uint8_t unused1[7];
43131 * This field is used in Output records to indicate that the
43132 * output is completely written to RAM. This field should be
43133 * read as '1' to indicate that the output has been
43134 * completely written. When writing a command completion or
43135 * response to an internal processor, the order of writes has
43136 * to be such that this field is written last.
43141 /***********************
43142 * hwrm_tf_version_get *
43143 ***********************/
43146 /* hwrm_tf_version_get_input (size:128b/16B) */
43147 struct hwrm_tf_version_get_input {
43148 /* The HWRM command request type. */
43151 * The completion ring to send the completion event on. This should
43152 * be the NQ ID returned from the `nq_alloc` HWRM command.
43154 uint16_t cmpl_ring;
43156 * The sequence ID is used by the driver for tracking multiple
43157 * commands. This ID is treated as opaque data by the firmware and
43158 * the value is returned in the `hwrm_resp_hdr` upon completion.
43162 * The target ID of the command:
43163 * * 0x0-0xFFF8 - The function ID
43164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43165 * * 0xFFFD - Reserved for user-space HWRM interface
43168 uint16_t target_id;
43170 * A physical address pointer pointing to a host buffer that the
43171 * command's response data will be written. This can be either a host
43172 * physical address (HPA) or a guest physical address (GPA) and must
43173 * point to a physically contiguous block of memory.
43175 uint64_t resp_addr;
43178 /* hwrm_tf_version_get_output (size:128b/16B) */
43179 struct hwrm_tf_version_get_output {
43180 /* The specific error status for the command. */
43181 uint16_t error_code;
43182 /* The HWRM command request type. */
43184 /* The sequence ID from the original command. */
43186 /* The length of the response data in number of bytes. */
43188 /* Version Major number. */
43190 /* Version Minor number. */
43192 /* Version Update number. */
43195 uint8_t unused0[4];
43197 * This field is used in Output records to indicate that the output
43198 * is completely written to RAM. This field should be read as '1'
43199 * to indicate that the output has been completely written.
43200 * When writing a command completion or response to an internal
43201 * processor, the order of writes has to be such that this field is
43207 /************************
43208 * hwrm_tf_session_open *
43209 ************************/
43212 /* hwrm_tf_session_open_input (size:640b/80B) */
43213 struct hwrm_tf_session_open_input {
43214 /* The HWRM command request type. */
43217 * The completion ring to send the completion event on. This should
43218 * be the NQ ID returned from the `nq_alloc` HWRM command.
43220 uint16_t cmpl_ring;
43222 * The sequence ID is used by the driver for tracking multiple
43223 * commands. This ID is treated as opaque data by the firmware and
43224 * the value is returned in the `hwrm_resp_hdr` upon completion.
43228 * The target ID of the command:
43229 * * 0x0-0xFFF8 - The function ID
43230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43231 * * 0xFFFD - Reserved for user-space HWRM interface
43234 uint16_t target_id;
43236 * A physical address pointer pointing to a host buffer that the
43237 * command's response data will be written. This can be either a host
43238 * physical address (HPA) or a guest physical address (GPA) and must
43239 * point to a physically contiguous block of memory.
43241 uint64_t resp_addr;
43242 /* Name of the session. */
43243 uint8_t session_name[64];
43246 /* hwrm_tf_session_open_output (size:192b/24B) */
43247 struct hwrm_tf_session_open_output {
43248 /* The specific error status for the command. */
43249 uint16_t error_code;
43250 /* The HWRM command request type. */
43252 /* The sequence ID from the original command. */
43254 /* The length of the response data in number of bytes. */
43257 * Unique session identifier for the session created by the
43260 uint32_t fw_session_id;
43262 * Unique session client identifier for the first client on
43263 * the newly created session.
43265 uint32_t fw_session_client_id;
43267 /* Indicates if the shared session has been created. */
43268 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
43271 * If this bit set to 0, then it indicates the shared session
43272 * has been created by another session.
43274 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \
43277 * If this bit is set to 1, then it indicates the shared session
43278 * is created by this session.
43280 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \
43282 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \
43283 HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR
43285 uint8_t unused1[3];
43287 * This field is used in Output records to indicate that the output
43288 * is completely written to RAM. This field should be read as '1'
43289 * to indicate that the output has been completely written.
43290 * When writing a command completion or response to an internal
43291 * processor, the order of writes has to be such that this field is
43297 /**************************
43298 * hwrm_tf_session_attach *
43299 **************************/
43302 /* hwrm_tf_session_attach_input (size:704b/88B) */
43303 struct hwrm_tf_session_attach_input {
43304 /* The HWRM command request type. */
43307 * The completion ring to send the completion event on. This should
43308 * be the NQ ID returned from the `nq_alloc` HWRM command.
43310 uint16_t cmpl_ring;
43312 * The sequence ID is used by the driver for tracking multiple
43313 * commands. This ID is treated as opaque data by the firmware and
43314 * the value is returned in the `hwrm_resp_hdr` upon completion.
43318 * The target ID of the command:
43319 * * 0x0-0xFFF8 - The function ID
43320 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43321 * * 0xFFFD - Reserved for user-space HWRM interface
43324 uint16_t target_id;
43326 * A physical address pointer pointing to a host buffer that the
43327 * command's response data will be written. This can be either a host
43328 * physical address (HPA) or a guest physical address (GPA) and must
43329 * point to a physically contiguous block of memory.
43331 uint64_t resp_addr;
43333 * Unique session identifier for the session that the attach
43334 * request want to attach to. This value originates from the
43335 * shared session memory that the attach request opened by
43336 * way of the 'attach name' that was passed in to the core
43338 * The fw_session_id of the attach session includes PCIe bus
43339 * info to distinguish the PF and session info to identify
43340 * the associated TruFlow session.
43342 uint32_t attach_fw_session_id;
43345 /* Name of the session it self. */
43346 uint8_t session_name[64];
43349 /* hwrm_tf_session_attach_output (size:128b/16B) */
43350 struct hwrm_tf_session_attach_output {
43351 /* The specific error status for the command. */
43352 uint16_t error_code;
43353 /* The HWRM command request type. */
43355 /* The sequence ID from the original command. */
43357 /* The length of the response data in number of bytes. */
43360 * Unique session identifier for the session created by the
43361 * firmware. It includes PCIe bus info to distinguish the PF
43362 * and session info to identify the associated TruFlow
43363 * session. This fw_session_id is unique to the attach
43366 uint32_t fw_session_id;
43368 uint8_t unused0[3];
43370 * This field is used in Output records to indicate that the output
43371 * is completely written to RAM. This field should be read as '1'
43372 * to indicate that the output has been completely written.
43373 * When writing a command completion or response to an internal
43374 * processor, the order of writes has to be such that this field is
43380 /****************************
43381 * hwrm_tf_session_register *
43382 ****************************/
43385 /* hwrm_tf_session_register_input (size:704b/88B) */
43386 struct hwrm_tf_session_register_input {
43387 /* The HWRM command request type. */
43390 * The completion ring to send the completion event on. This should
43391 * be the NQ ID returned from the `nq_alloc` HWRM command.
43393 uint16_t cmpl_ring;
43395 * The sequence ID is used by the driver for tracking multiple
43396 * commands. This ID is treated as opaque data by the firmware and
43397 * the value is returned in the `hwrm_resp_hdr` upon completion.
43401 * The target ID of the command:
43402 * * 0x0-0xFFF8 - The function ID
43403 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43404 * * 0xFFFD - Reserved for user-space HWRM interface
43407 uint16_t target_id;
43409 * A physical address pointer pointing to a host buffer that the
43410 * command's response data will be written. This can be either a host
43411 * physical address (HPA) or a guest physical address (GPA) and must
43412 * point to a physically contiguous block of memory.
43414 uint64_t resp_addr;
43416 * Unique session identifier for the session that the
43417 * register request want to create a new client on. This
43418 * value originates from the first open request.
43419 * The fw_session_id of the attach session includes PCIe bus
43420 * info to distinguish the PF and session info to identify
43421 * the associated TruFlow session.
43423 uint32_t fw_session_id;
43426 /* Name of the session client. */
43427 uint8_t session_client_name[64];
43430 /* hwrm_tf_session_register_output (size:128b/16B) */
43431 struct hwrm_tf_session_register_output {
43432 /* The specific error status for the command. */
43433 uint16_t error_code;
43434 /* The HWRM command request type. */
43436 /* The sequence ID from the original command. */
43438 /* The length of the response data in number of bytes. */
43441 * Unique session client identifier for the session created
43442 * by the firmware. It includes the session the client it
43443 * attached to and session client info.
43445 uint32_t fw_session_client_id;
43447 uint8_t unused0[3];
43449 * This field is used in Output records to indicate that the output
43450 * is completely written to RAM. This field should be read as '1'
43451 * to indicate that the output has been completely written.
43452 * When writing a command completion or response to an internal
43453 * processor, the order of writes has to be such that this field is
43459 /******************************
43460 * hwrm_tf_session_unregister *
43461 ******************************/
43464 /* hwrm_tf_session_unregister_input (size:192b/24B) */
43465 struct hwrm_tf_session_unregister_input {
43466 /* The HWRM command request type. */
43469 * The completion ring to send the completion event on. This should
43470 * be the NQ ID returned from the `nq_alloc` HWRM command.
43472 uint16_t cmpl_ring;
43474 * The sequence ID is used by the driver for tracking multiple
43475 * commands. This ID is treated as opaque data by the firmware and
43476 * the value is returned in the `hwrm_resp_hdr` upon completion.
43480 * The target ID of the command:
43481 * * 0x0-0xFFF8 - The function ID
43482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43483 * * 0xFFFD - Reserved for user-space HWRM interface
43486 uint16_t target_id;
43488 * A physical address pointer pointing to a host buffer that the
43489 * command's response data will be written. This can be either a host
43490 * physical address (HPA) or a guest physical address (GPA) and must
43491 * point to a physically contiguous block of memory.
43493 uint64_t resp_addr;
43495 * Unique session identifier for the session that the
43496 * unregister request want to close a session client on.
43498 uint32_t fw_session_id;
43500 * Unique session client identifier for the session that the
43501 * unregister request want to close.
43503 uint32_t fw_session_client_id;
43506 /* hwrm_tf_session_unregister_output (size:128b/16B) */
43507 struct hwrm_tf_session_unregister_output {
43508 /* The specific error status for the command. */
43509 uint16_t error_code;
43510 /* The HWRM command request type. */
43512 /* The sequence ID from the original command. */
43514 /* The length of the response data in number of bytes. */
43517 uint8_t unused0[7];
43519 * This field is used in Output records to indicate that the output
43520 * is completely written to RAM. This field should be read as '1'
43521 * to indicate that the output has been completely written.
43522 * When writing a command completion or response to an internal
43523 * processor, the order of writes has to be such that this field is
43529 /*************************
43530 * hwrm_tf_session_close *
43531 *************************/
43534 /* hwrm_tf_session_close_input (size:192b/24B) */
43535 struct hwrm_tf_session_close_input {
43536 /* The HWRM command request type. */
43539 * The completion ring to send the completion event on. This should
43540 * be the NQ ID returned from the `nq_alloc` HWRM command.
43542 uint16_t cmpl_ring;
43544 * The sequence ID is used by the driver for tracking multiple
43545 * commands. This ID is treated as opaque data by the firmware and
43546 * the value is returned in the `hwrm_resp_hdr` upon completion.
43550 * The target ID of the command:
43551 * * 0x0-0xFFF8 - The function ID
43552 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43553 * * 0xFFFD - Reserved for user-space HWRM interface
43556 uint16_t target_id;
43558 * A physical address pointer pointing to a host buffer that the
43559 * command's response data will be written. This can be either a host
43560 * physical address (HPA) or a guest physical address (GPA) and must
43561 * point to a physically contiguous block of memory.
43563 uint64_t resp_addr;
43564 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43565 uint32_t fw_session_id;
43567 uint8_t unused0[4];
43570 /* hwrm_tf_session_close_output (size:128b/16B) */
43571 struct hwrm_tf_session_close_output {
43572 /* The specific error status for the command. */
43573 uint16_t error_code;
43574 /* The HWRM command request type. */
43576 /* The sequence ID from the original command. */
43578 /* The length of the response data in number of bytes. */
43581 uint8_t unused0[7];
43583 * This field is used in Output records to indicate that the output
43584 * is completely written to RAM. This field should be read as '1'
43585 * to indicate that the output has been completely written.
43586 * When writing a command completion or response to an internal
43587 * processor, the order of writes has to be such that this field
43593 /************************
43594 * hwrm_tf_session_qcfg *
43595 ************************/
43598 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
43599 struct hwrm_tf_session_qcfg_input {
43600 /* The HWRM command request type. */
43603 * The completion ring to send the completion event on. This should
43604 * be the NQ ID returned from the `nq_alloc` HWRM command.
43606 uint16_t cmpl_ring;
43608 * The sequence ID is used by the driver for tracking multiple
43609 * commands. This ID is treated as opaque data by the firmware and
43610 * the value is returned in the `hwrm_resp_hdr` upon completion.
43614 * The target ID of the command:
43615 * * 0x0-0xFFF8 - The function ID
43616 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43617 * * 0xFFFD - Reserved for user-space HWRM interface
43620 uint16_t target_id;
43622 * A physical address pointer pointing to a host buffer that the
43623 * command's response data will be written. This can be either a host
43624 * physical address (HPA) or a guest physical address (GPA) and must
43625 * point to a physically contiguous block of memory.
43627 uint64_t resp_addr;
43628 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43629 uint32_t fw_session_id;
43631 uint8_t unused0[4];
43634 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
43635 struct hwrm_tf_session_qcfg_output {
43636 /* The specific error status for the command. */
43637 uint16_t error_code;
43638 /* The HWRM command request type. */
43640 /* The sequence ID from the original command. */
43642 /* The length of the response data in number of bytes. */
43644 /* RX action control settings flags. */
43645 uint8_t rx_act_flags;
43647 * A value of 1 in this field indicates that Global Flow ID
43648 * reporting into cfa_code and cfa_metadata is enabled.
43650 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
43653 * A value of 1 in this field indicates that both inner and outer
43654 * are stripped and inner tag is passed.
43657 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
43660 * A value of 1 in this field indicates that the re-use of
43661 * existing tunnel L2 header SMAC is enabled for
43662 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
43664 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
43666 /* TX Action control settings flags. */
43667 uint8_t tx_act_flags;
43669 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
43672 * When set to 1 any GRE tunnels will include the
43673 * optional Key field.
43675 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
43678 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
43679 * field of the outer header is inherited from the inner header
43680 * (if present) or the fixed value as taken from the encap
43683 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
43686 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
43687 * field of the outer header is inherited from the inner header
43688 * (if present) or the fixed value as taken from the encap record.
43690 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
43693 uint8_t unused0[5];
43695 * This field is used in Output records to indicate that the output
43696 * is completely written to RAM. This field should be read as '1'
43697 * to indicate that the output has been completely written.
43698 * When writing a command completion or response to an internal
43699 * processor, the order of writes has to be such that this field
43705 /******************************
43706 * hwrm_tf_session_resc_qcaps *
43707 ******************************/
43710 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
43711 struct hwrm_tf_session_resc_qcaps_input {
43712 /* The HWRM command request type. */
43715 * The completion ring to send the completion event on. This should
43716 * be the NQ ID returned from the `nq_alloc` HWRM command.
43718 uint16_t cmpl_ring;
43720 * The sequence ID is used by the driver for tracking multiple
43721 * commands. This ID is treated as opaque data by the firmware and
43722 * the value is returned in the `hwrm_resp_hdr` upon completion.
43726 * The target ID of the command:
43727 * * 0x0-0xFFF8 - The function ID
43728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43729 * * 0xFFFD - Reserved for user-space HWRM interface
43732 uint16_t target_id;
43734 * A physical address pointer pointing to a host buffer that the
43735 * command's response data will be written. This can be either a host
43736 * physical address (HPA) or a guest physical address (GPA) and must
43737 * point to a physically contiguous block of memory.
43739 uint64_t resp_addr;
43740 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43741 uint32_t fw_session_id;
43742 /* Control flags. */
43744 /* Indicates the flow direction. */
43745 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
43746 /* If this bit set to 0, then it indicates rx flow. */
43747 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43748 /* If this bit is set to 1, then it indicates that tx flow. */
43749 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43750 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
43751 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
43753 * Defines the size of the provided qcaps_addr array
43754 * buffer. The size should be set to the Resource Manager
43755 * provided max number of qcaps entries which is device
43756 * specific. Resource Manager gets the max size from HCAPI
43759 uint16_t qcaps_size;
43761 * This is the DMA address for the qcaps output data array
43762 * buffer. Array is of tf_rm_resc_req_entry type and is
43765 uint64_t qcaps_addr;
43768 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
43769 struct hwrm_tf_session_resc_qcaps_output {
43770 /* The specific error status for the command. */
43771 uint16_t error_code;
43772 /* The HWRM command request type. */
43774 /* The sequence ID from the original command. */
43776 /* The length of the response data in number of bytes. */
43778 /* Control flags. */
43780 /* Session reservation strategy. */
43781 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
43783 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
43785 /* Static partitioning. */
43786 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
43789 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
43792 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
43795 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
43797 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
43798 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
43800 * Size of the returned qcaps_addr data array buffer. The
43801 * value cannot exceed the size defined by the input msg,
43808 uint8_t unused1[7];
43810 * This field is used in Output records to indicate that the output
43811 * is completely written to RAM. This field should be read as '1'
43812 * to indicate that the output has been completely written.
43813 * When writing a command completion or response to an internal
43814 * processor, the order of writes has to be such that this field is
43820 /******************************
43821 * hwrm_tf_session_resc_alloc *
43822 ******************************/
43825 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
43826 struct hwrm_tf_session_resc_alloc_input {
43827 /* The HWRM command request type. */
43830 * The completion ring to send the completion event on. This should
43831 * be the NQ ID returned from the `nq_alloc` HWRM command.
43833 uint16_t cmpl_ring;
43835 * The sequence ID is used by the driver for tracking multiple
43836 * commands. This ID is treated as opaque data by the firmware and
43837 * the value is returned in the `hwrm_resp_hdr` upon completion.
43841 * The target ID of the command:
43842 * * 0x0-0xFFF8 - The function ID
43843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43844 * * 0xFFFD - Reserved for user-space HWRM interface
43847 uint16_t target_id;
43849 * A physical address pointer pointing to a host buffer that the
43850 * command's response data will be written. This can be either a host
43851 * physical address (HPA) or a guest physical address (GPA) and must
43852 * point to a physically contiguous block of memory.
43854 uint64_t resp_addr;
43855 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43856 uint32_t fw_session_id;
43857 /* Control flags. */
43859 /* Indicates the flow direction. */
43860 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
43861 /* If this bit set to 0, then it indicates rx flow. */
43862 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43863 /* If this bit is set to 1, then it indicates that tx flow. */
43864 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43865 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
43866 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
43868 * Defines the array size of the provided req_addr and
43869 * resv_addr array buffers. Should be set to the number of
43874 * This is the DMA address for the request input data array
43875 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
43876 * array buffer is provided by the 'req_size' field in this
43881 * This is the DMA address for the resc output data array
43882 * buffer. Array is of tf_rm_resc_entry type. Size of the array
43883 * buffer is provided by the 'req_size' field in this
43886 uint64_t resc_addr;
43889 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
43890 struct hwrm_tf_session_resc_alloc_output {
43891 /* The specific error status for the command. */
43892 uint16_t error_code;
43893 /* The HWRM command request type. */
43895 /* The sequence ID from the original command. */
43897 /* The length of the response data in number of bytes. */
43900 * Size of the returned tf_rm_resc_entry data array. The value
43901 * cannot exceed the req_size defined by the input msg. The data
43902 * array is returned using the resv_addr specified DMA
43903 * address also provided by the input msg.
43907 uint8_t unused0[5];
43909 * This field is used in Output records to indicate that the output
43910 * is completely written to RAM. This field should be read as '1'
43911 * to indicate that the output has been completely written.
43912 * When writing a command completion or response to an internal
43913 * processor, the order of writes has to be such that this field is
43919 /*****************************
43920 * hwrm_tf_session_resc_free *
43921 *****************************/
43924 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
43925 struct hwrm_tf_session_resc_free_input {
43926 /* The HWRM command request type. */
43929 * The completion ring to send the completion event on. This should
43930 * be the NQ ID returned from the `nq_alloc` HWRM command.
43932 uint16_t cmpl_ring;
43934 * The sequence ID is used by the driver for tracking multiple
43935 * commands. This ID is treated as opaque data by the firmware and
43936 * the value is returned in the `hwrm_resp_hdr` upon completion.
43940 * The target ID of the command:
43941 * * 0x0-0xFFF8 - The function ID
43942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43943 * * 0xFFFD - Reserved for user-space HWRM interface
43946 uint16_t target_id;
43948 * A physical address pointer pointing to a host buffer that the
43949 * command's response data will be written. This can be either a host
43950 * physical address (HPA) or a guest physical address (GPA) and must
43951 * point to a physically contiguous block of memory.
43953 uint64_t resp_addr;
43954 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43955 uint32_t fw_session_id;
43956 /* Control flags. */
43958 /* Indicates the flow direction. */
43959 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
43960 /* If this bit set to 0, then it indicates rx flow. */
43961 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43962 /* If this bit is set to 1, then it indicates that tx flow. */
43963 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43964 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
43965 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
43967 * Defines the size, in bytes, of the provided free_addr
43970 uint16_t free_size;
43972 * This is the DMA address for the free input data array
43973 * buffer. Array is of tf_rm_resc_entry type. Size of the
43974 * buffer is provided by the 'free_size' field of this
43977 uint64_t free_addr;
43980 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
43981 struct hwrm_tf_session_resc_free_output {
43982 /* The specific error status for the command. */
43983 uint16_t error_code;
43984 /* The HWRM command request type. */
43986 /* The sequence ID from the original command. */
43988 /* The length of the response data in number of bytes. */
43991 uint8_t unused0[7];
43993 * This field is used in Output records to indicate that the output
43994 * is completely written to RAM. This field should be read as '1'
43995 * to indicate that the output has been completely written.
43996 * When writing a command completion or response to an internal
43997 * processor, the order of writes has to be such that this field is
44003 /******************************
44004 * hwrm_tf_session_resc_flush *
44005 ******************************/
44008 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
44009 struct hwrm_tf_session_resc_flush_input {
44010 /* The HWRM command request type. */
44013 * The completion ring to send the completion event on. This should
44014 * be the NQ ID returned from the `nq_alloc` HWRM command.
44016 uint16_t cmpl_ring;
44018 * The sequence ID is used by the driver for tracking multiple
44019 * commands. This ID is treated as opaque data by the firmware and
44020 * the value is returned in the `hwrm_resp_hdr` upon completion.
44024 * The target ID of the command:
44025 * * 0x0-0xFFF8 - The function ID
44026 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44027 * * 0xFFFD - Reserved for user-space HWRM interface
44030 uint16_t target_id;
44032 * A physical address pointer pointing to a host buffer that the
44033 * command's response data will be written. This can be either a host
44034 * physical address (HPA) or a guest physical address (GPA) and must
44035 * point to a physically contiguous block of memory.
44037 uint64_t resp_addr;
44038 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44039 uint32_t fw_session_id;
44040 /* Control flags. */
44042 /* Indicates the flow direction. */
44043 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
44044 /* If this bit set to 0, then it indicates rx flow. */
44045 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44046 /* If this bit is set to 1, then it indicates that tx flow. */
44047 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44048 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
44049 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
44051 * Defines the size, in bytes, of the provided flush_addr
44054 uint16_t flush_size;
44056 * This is the DMA address for the flush input data array
44057 * buffer. Array of tf_rm_resc_entry type. Size of the
44058 * buffer is provided by the 'flush_size' field in this
44061 uint64_t flush_addr;
44064 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
44065 struct hwrm_tf_session_resc_flush_output {
44066 /* The specific error status for the command. */
44067 uint16_t error_code;
44068 /* The HWRM command request type. */
44070 /* The sequence ID from the original command. */
44072 /* The length of the response data in number of bytes. */
44075 uint8_t unused0[7];
44077 * This field is used in Output records to indicate that the output
44078 * is completely written to RAM. This field should be read as '1'
44079 * to indicate that the output has been completely written.
44080 * When writing a command completion or response to an internal
44081 * processor, the order of writes has to be such that this field is
44087 /*****************************
44088 * hwrm_tf_session_resc_info *
44089 *****************************/
44092 /* hwrm_tf_session_resc_info_input (size:320b/40B) */
44093 struct hwrm_tf_session_resc_info_input {
44094 /* The HWRM command request type. */
44097 * The completion ring to send the completion event on. This should
44098 * be the NQ ID returned from the `nq_alloc` HWRM command.
44100 uint16_t cmpl_ring;
44102 * The sequence ID is used by the driver for tracking multiple
44103 * commands. This ID is treated as opaque data by the firmware and
44104 * the value is returned in the `hwrm_resp_hdr` upon completion.
44108 * The target ID of the command:
44109 * * 0x0-0xFFF8 - The function ID
44110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44111 * * 0xFFFD - Reserved for user-space HWRM interface
44114 uint16_t target_id;
44116 * A physical address pointer pointing to a host buffer that the
44117 * command's response data will be written. This can be either a host
44118 * physical address (HPA) or a guest physical address (GPA) and must
44119 * point to a physically contiguous block of memory.
44121 uint64_t resp_addr;
44122 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44123 uint32_t fw_session_id;
44124 /* Control flags. */
44126 /* Indicates the flow direction. */
44127 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
44128 /* If this bit set to 0, then it indicates rx flow. */
44129 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44130 /* If this bit is set to 1, then it indicates tx flow. */
44131 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44132 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \
44133 HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX
44135 * Defines the array size of the provided req_addr and
44136 * resv_addr array buffers. Should be set to the number of
44141 * This is the DMA address for the request input data array
44142 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
44143 * array buffer is provided by the 'req_size' field in this
44148 * This is the DMA address for the resc output data array
44149 * buffer. Array is of tf_rm_resc_entry type. Size of the array
44150 * buffer is provided by the 'req_size' field in this
44153 uint64_t resc_addr;
44156 /* hwrm_tf_session_resc_info_output (size:128b/16B) */
44157 struct hwrm_tf_session_resc_info_output {
44158 /* The specific error status for the command. */
44159 uint16_t error_code;
44160 /* The HWRM command request type. */
44162 /* The sequence ID from the original command. */
44164 /* The length of the response data in number of bytes. */
44167 * Size of the returned tf_rm_resc_entry data array. The value
44168 * cannot exceed the req_size defined by the input msg. The data
44169 * array is returned using the resv_addr specified DMA
44170 * address also provided by the input msg.
44174 uint8_t unused0[5];
44176 * This field is used in Output records to indicate that the output
44177 * is completely written to RAM. This field should be read as '1'
44178 * to indicate that the output has been completely written.
44179 * When writing a command completion or response to an internal
44180 * processor, the order of writes has to be such that this field is
44186 /* TruFlow RM capability of a resource. */
44187 /* tf_rm_resc_req_entry (size:64b/8B) */
44188 struct tf_rm_resc_req_entry {
44189 /* Type of the resource, defined globally in HCAPI RM. */
44191 /* Minimum value. */
44193 /* Maximum value. */
44197 /* TruFlow RM reservation information. */
44198 /* tf_rm_resc_entry (size:64b/8B) */
44199 struct tf_rm_resc_entry {
44200 /* Type of the resource, defined globally in HCAPI RM. */
44202 /* Start offset. */
44204 /* Number of resources. */
44208 /************************
44209 * hwrm_tf_tbl_type_get *
44210 ************************/
44213 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
44214 struct hwrm_tf_tbl_type_get_input {
44215 /* The HWRM command request type. */
44218 * The completion ring to send the completion event on. This should
44219 * be the NQ ID returned from the `nq_alloc` HWRM command.
44221 uint16_t cmpl_ring;
44223 * The sequence ID is used by the driver for tracking multiple
44224 * commands. This ID is treated as opaque data by the firmware and
44225 * the value is returned in the `hwrm_resp_hdr` upon completion.
44229 * The target ID of the command:
44230 * * 0x0-0xFFF8 - The function ID
44231 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44232 * * 0xFFFD - Reserved for user-space HWRM interface
44235 uint16_t target_id;
44237 * A physical address pointer pointing to a host buffer that the
44238 * command's response data will be written. This can be either a host
44239 * physical address (HPA) or a guest physical address (GPA) and must
44240 * point to a physically contiguous block of memory.
44242 uint64_t resp_addr;
44243 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44244 uint32_t fw_session_id;
44245 /* Control flags. */
44247 /* Indicates the flow direction. */
44248 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
44249 /* If this bit set to 0, then it indicates rx flow. */
44250 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44251 /* If this bit is set to 1, then it indicates that tx flow. */
44252 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44253 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
44254 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
44256 uint8_t unused0[2];
44258 * Type of the resource, defined globally in the
44259 * hwrm_tf_resc_type enum.
44262 /* Index of the type to retrieve. */
44266 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
44267 struct hwrm_tf_tbl_type_get_output {
44268 /* The specific error status for the command. */
44269 uint16_t error_code;
44270 /* The HWRM command request type. */
44272 /* The sequence ID from the original command. */
44274 /* The length of the response data in number of bytes. */
44276 /* Response code. */
44277 uint32_t resp_code;
44278 /* Response size. */
44282 /* Response data. */
44285 uint8_t unused1[7];
44287 * This field is used in Output records to indicate that the output
44288 * is completely written to RAM. This field should be read as '1'
44289 * to indicate that the output has been completely written.
44290 * When writing a command completion or response to an internal
44291 * processor, the order of writes has to be such that this field
44297 /************************
44298 * hwrm_tf_tbl_type_set *
44299 ************************/
44302 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
44303 struct hwrm_tf_tbl_type_set_input {
44304 /* The HWRM command request type. */
44307 * The completion ring to send the completion event on. This should
44308 * be the NQ ID returned from the `nq_alloc` HWRM command.
44310 uint16_t cmpl_ring;
44312 * The sequence ID is used by the driver for tracking multiple
44313 * commands. This ID is treated as opaque data by the firmware and
44314 * the value is returned in the `hwrm_resp_hdr` upon completion.
44318 * The target ID of the command:
44319 * * 0x0-0xFFF8 - The function ID
44320 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44321 * * 0xFFFD - Reserved for user-space HWRM interface
44324 uint16_t target_id;
44326 * A physical address pointer pointing to a host buffer that the
44327 * command's response data will be written. This can be either a host
44328 * physical address (HPA) or a guest physical address (GPA) and must
44329 * point to a physically contiguous block of memory.
44331 uint64_t resp_addr;
44332 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44333 uint32_t fw_session_id;
44334 /* Control flags. */
44336 /* Indicates the flow direction. */
44337 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
44338 /* If this bit set to 0, then it indicates rx flow. */
44339 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44340 /* If this bit is set to 1, then it indicates that tx flow. */
44341 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44342 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
44343 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
44345 uint8_t unused0[2];
44347 * Type of the resource, defined globally in the
44348 * hwrm_tf_resc_type enum.
44351 /* Index of the type to retrieve. */
44353 /* Size of the data to set. */
44356 uint8_t unused1[6];
44357 /* Data to be set. */
44361 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
44362 struct hwrm_tf_tbl_type_set_output {
44363 /* The specific error status for the command. */
44364 uint16_t error_code;
44365 /* The HWRM command request type. */
44367 /* The sequence ID from the original command. */
44369 /* The length of the response data in number of bytes. */
44372 uint8_t unused0[7];
44374 * This field is used in Output records to indicate that the output
44375 * is completely written to RAM. This field should be read as '1'
44376 * to indicate that the output has been completely written.
44377 * When writing a command completion or response to an internal
44378 * processor, the order of writes has to be such that this field
44384 /**************************
44385 * hwrm_tf_ctxt_mem_alloc *
44386 **************************/
44389 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
44390 struct hwrm_tf_ctxt_mem_alloc_input {
44391 /* The HWRM command request type. */
44394 * The completion ring to send the completion event on. This should
44395 * be the NQ ID returned from the `nq_alloc` HWRM command.
44397 uint16_t cmpl_ring;
44399 * The sequence ID is used by the driver for tracking multiple
44400 * commands. This ID is treated as opaque data by the firmware and
44401 * the value is returned in the `hwrm_resp_hdr` upon completion.
44405 * The target ID of the command:
44406 * * 0x0-0xFFF8 - The function ID
44407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44408 * * 0xFFFD - Reserved for user-space HWRM interface
44411 uint16_t target_id;
44413 * A physical address pointer pointing to a host buffer that the
44414 * command's response data will be written. This can be either a host
44415 * physical address (HPA) or a guest physical address (GPA) and must
44416 * point to a physically contiguous block of memory.
44418 uint64_t resp_addr;
44419 /* Size in KB of memory to be allocated. */
44421 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44422 uint32_t fw_session_id;
44425 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
44426 struct hwrm_tf_ctxt_mem_alloc_output {
44427 /* The specific error status for the command. */
44428 uint16_t error_code;
44429 /* The HWRM command request type. */
44431 /* The sequence ID from the original command. */
44433 /* The length of the response data in number of bytes. */
44435 /* Pointer to the PBL, or PDL depending on number of levels */
44437 /* Size of memory allocated. */
44439 /* Counter PBL indirect levels. */
44440 uint8_t page_level;
44441 /* PBL pointer is physical start address. */
44442 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
44443 /* PBL pointer points to PTE table. */
44444 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
44446 * PBL pointer points to PDE table with each entry pointing
44449 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
44450 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
44451 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
44454 /* 4KB page size. */
44455 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
44456 /* 8KB page size. */
44457 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
44458 /* 64KB page size. */
44459 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
44460 /* 128KB page size. */
44461 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
44462 /* 256KB page size. */
44463 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
44464 /* 512KB page size. */
44465 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
44466 /* 1MB page size. */
44467 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
44468 /* 2MB page size. */
44469 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
44470 /* 4MB page size. */
44471 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
44472 /* 8MB page size. */
44473 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
44474 /* 1GB page size. */
44475 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
44476 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
44477 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
44481 * This field is used in Output records to indicate that the
44482 * output is completely written to RAM. This field should be
44483 * read as '1' to indicate that the output has been
44484 * completely written. When writing a command completion or
44485 * response to an internal processor, the order of writes has
44486 * to be such that this field is written last.
44491 /*************************
44492 * hwrm_tf_ctxt_mem_free *
44493 *************************/
44496 /* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
44497 struct hwrm_tf_ctxt_mem_free_input {
44498 /* The HWRM command request type. */
44501 * The completion ring to send the completion event on. This should
44502 * be the NQ ID returned from the `nq_alloc` HWRM command.
44504 uint16_t cmpl_ring;
44506 * The sequence ID is used by the driver for tracking multiple
44507 * commands. This ID is treated as opaque data by the firmware and
44508 * the value is returned in the `hwrm_resp_hdr` upon completion.
44512 * The target ID of the command:
44513 * * 0x0-0xFFF8 - The function ID
44514 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44515 * * 0xFFFD - Reserved for user-space HWRM interface
44518 uint16_t target_id;
44520 * A physical address pointer pointing to a host buffer that the
44521 * command's response data will be written. This can be either a host
44522 * physical address (HPA) or a guest physical address (GPA) and must
44523 * point to a physically contiguous block of memory.
44525 uint64_t resp_addr;
44526 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44527 uint32_t fw_session_id;
44528 /* Counter PBL indirect levels. */
44529 uint8_t page_level;
44530 /* PBL pointer is physical start address. */
44531 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
44532 /* PBL pointer points to PTE table. */
44533 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
44535 * PBL pointer points to PDE table with each entry pointing
44538 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
44539 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
44540 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
44543 /* 4KB page size. */
44544 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
44545 /* 8KB page size. */
44546 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
44547 /* 64KB page size. */
44548 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
44549 /* 128KB page size. */
44550 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
44551 /* 256KB page size. */
44552 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
44553 /* 512KB page size. */
44554 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
44555 /* 1MB page size. */
44556 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
44557 /* 2MB page size. */
44558 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
44559 /* 4MB page size. */
44560 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
44561 /* 8MB page size. */
44562 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
44563 /* 1GB page size. */
44564 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
44565 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
44566 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
44568 uint8_t unused0[2];
44569 /* Pointer to the PBL, or PDL depending on number of levels */
44571 /* Size of memory allocated. */
44574 uint8_t unused1[4];
44577 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
44578 struct hwrm_tf_ctxt_mem_free_output {
44579 /* The specific error status for the command. */
44580 uint16_t error_code;
44581 /* The HWRM command request type. */
44583 /* The sequence ID from the original command. */
44585 /* The length of the response data in number of bytes. */
44588 uint8_t unused0[7];
44590 * This field is used in Output records to indicate that the
44591 * output is completely written to RAM. This field should be
44592 * read as '1' to indicate that the output has been
44593 * completely written. When writing a command completion or
44594 * response to an internal processor, the order of writes has
44595 * to be such that this field is written last.
44600 /*************************
44601 * hwrm_tf_ctxt_mem_rgtr *
44602 *************************/
44605 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
44606 struct hwrm_tf_ctxt_mem_rgtr_input {
44607 /* The HWRM command request type. */
44610 * The completion ring to send the completion event on. This should
44611 * be the NQ ID returned from the `nq_alloc` HWRM command.
44613 uint16_t cmpl_ring;
44615 * The sequence ID is used by the driver for tracking multiple
44616 * commands. This ID is treated as opaque data by the firmware and
44617 * the value is returned in the `hwrm_resp_hdr` upon completion.
44621 * The target ID of the command:
44622 * * 0x0-0xFFF8 - The function ID
44623 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44624 * * 0xFFFD - Reserved for user-space HWRM interface
44627 uint16_t target_id;
44629 * A physical address pointer pointing to a host buffer that the
44630 * command's response data will be written. This can be either a host
44631 * physical address (HPA) or a guest physical address (GPA) and must
44632 * point to a physically contiguous block of memory.
44634 uint64_t resp_addr;
44635 /* Control flags. */
44637 /* Counter PBL indirect levels. */
44638 uint8_t page_level;
44639 /* PBL pointer is physical start address. */
44640 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
44641 /* PBL pointer points to PTE table. */
44642 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
44644 * PBL pointer points to PDE table with each entry pointing
44647 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
44648 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
44649 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
44652 /* 4KB page size. */
44653 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
44654 /* 8KB page size. */
44655 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
44656 /* 64KB page size. */
44657 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
44658 /* 128KB page size. */
44659 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
44660 /* 256KB page size. */
44661 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
44662 /* 512KB page size. */
44663 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
44664 /* 1MB page size. */
44665 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
44666 /* 2MB page size. */
44667 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
44668 /* 4MB page size. */
44669 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
44670 /* 8MB page size. */
44671 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
44672 /* 1GB page size. */
44673 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
44674 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
44675 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
44676 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44677 uint32_t fw_session_id;
44678 /* Pointer to the PBL, or PDL depending on number of levels */
44682 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
44683 struct hwrm_tf_ctxt_mem_rgtr_output {
44684 /* The specific error status for the command. */
44685 uint16_t error_code;
44686 /* The HWRM command request type. */
44688 /* The sequence ID from the original command. */
44690 /* The length of the response data in number of bytes. */
44693 * Id/Handle to the recently register context memory. This
44694 * handle is passed to the TF session.
44698 uint8_t unused0[5];
44700 * This field is used in Output records to indicate that the
44701 * output is completely written to RAM. This field should be
44702 * read as '1' to indicate that the output has been
44703 * completely written. When writing a command completion or
44704 * response to an internal processor, the order of writes has
44705 * to be such that this field is written last.
44710 /***************************
44711 * hwrm_tf_ctxt_mem_unrgtr *
44712 ***************************/
44715 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
44716 struct hwrm_tf_ctxt_mem_unrgtr_input {
44717 /* The HWRM command request type. */
44720 * The completion ring to send the completion event on. This should
44721 * be the NQ ID returned from the `nq_alloc` HWRM command.
44723 uint16_t cmpl_ring;
44725 * The sequence ID is used by the driver for tracking multiple
44726 * commands. This ID is treated as opaque data by the firmware and
44727 * the value is returned in the `hwrm_resp_hdr` upon completion.
44731 * The target ID of the command:
44732 * * 0x0-0xFFF8 - The function ID
44733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44734 * * 0xFFFD - Reserved for user-space HWRM interface
44737 uint16_t target_id;
44739 * A physical address pointer pointing to a host buffer that the
44740 * command's response data will be written. This can be either a host
44741 * physical address (HPA) or a guest physical address (GPA) and must
44742 * point to a physically contiguous block of memory.
44744 uint64_t resp_addr;
44746 * Id/Handle to the recently register context memory. This
44747 * handle is passed to the TF session.
44751 uint8_t unused0[2];
44752 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44753 uint32_t fw_session_id;
44756 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
44757 struct hwrm_tf_ctxt_mem_unrgtr_output {
44758 /* The specific error status for the command. */
44759 uint16_t error_code;
44760 /* The HWRM command request type. */
44762 /* The sequence ID from the original command. */
44764 /* The length of the response data in number of bytes. */
44767 uint8_t unused0[7];
44769 * This field is used in Output records to indicate that the
44770 * output is completely written to RAM. This field should be
44771 * read as '1' to indicate that the output has been
44772 * completely written. When writing a command completion or
44773 * response to an internal processor, the order of writes has
44774 * to be such that this field is written last.
44779 /************************
44780 * hwrm_tf_ext_em_qcaps *
44781 ************************/
44784 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
44785 struct hwrm_tf_ext_em_qcaps_input {
44786 /* The HWRM command request type. */
44789 * The completion ring to send the completion event on. This should
44790 * be the NQ ID returned from the `nq_alloc` HWRM command.
44792 uint16_t cmpl_ring;
44794 * The sequence ID is used by the driver for tracking multiple
44795 * commands. This ID is treated as opaque data by the firmware and
44796 * the value is returned in the `hwrm_resp_hdr` upon completion.
44800 * The target ID of the command:
44801 * * 0x0-0xFFF8 - The function ID
44802 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44803 * * 0xFFFD - Reserved for user-space HWRM interface
44806 uint16_t target_id;
44808 * A physical address pointer pointing to a host buffer that the
44809 * command's response data will be written. This can be either a host
44810 * physical address (HPA) or a guest physical address (GPA) and must
44811 * point to a physically contiguous block of memory.
44813 uint64_t resp_addr;
44814 /* Control flags. */
44816 /* Indicates the flow direction. */
44817 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
44819 /* If this bit set to 0, then it indicates rx flow. */
44820 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
44822 /* If this bit is set to 1, then it indicates that tx flow. */
44823 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
44825 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
44826 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
44827 /* When set to 1, all offloaded flows will be sent to EXT EM. */
44828 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
44830 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44831 uint32_t fw_session_id;
44834 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
44835 struct hwrm_tf_ext_em_qcaps_output {
44836 /* The specific error status for the command. */
44837 uint16_t error_code;
44838 /* The HWRM command request type. */
44840 /* The sequence ID from the original command. */
44842 /* The length of the response data in number of bytes. */
44846 * When set to 1, indicates the FW supports the Centralized
44847 * Memory Model. The concept designates one entity for the
44848 * memory allocation while all others ‘subscribe’ to it.
44850 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
44853 * When set to 1, indicates the FW supports the Detached
44854 * Centralized Memory Model. The memory is allocated and managed
44855 * as a separate entity. All PFs and VFs will be granted direct
44856 * or semi-direct access to the allocated memory while none of
44857 * which can interfere with the management of the memory.
44859 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
44861 /* When set to 1, indicates FW support for host based EEM memory. */
44862 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
44864 /* When set to 1, indicates FW support for on-chip based EEM memory. */
44865 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
44869 /* Support flags. */
44870 uint32_t supported;
44872 * If set to 1, then EXT EM KEY0 table is supported using
44874 * If set to 0, EXT EM KEY0 table is not supported.
44876 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
44879 * If set to 1, then EXT EM KEY1 table is supported using
44881 * If set to 0, EXT EM KEY1 table is not supported.
44883 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
44886 * If set to 1, then EXT EM External Record table is supported.
44887 * If set to 0, EXT EM External Record table is not
44888 * supported. (This table includes action record, EFC
44889 * pointers, encap pointers)
44891 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
44894 * If set to 1, then EXT EM External Flow Counters table is
44896 * If set to 0, EXT EM External Flow Counters table is not
44899 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
44902 * If set to 1, then FID table used for implicit flow flush
44904 * If set to 0, then FID table used for implicit flow flush
44905 * is not supported.
44907 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
44910 * If set to 1, then table scopes are supported.
44911 * If set to 0, then table scopes are not supported.
44913 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
44916 * The maximum number of entries supported by EXT EM. When
44917 * configuring the host memory the number of numbers of
44918 * entries that can supported are -
44919 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
44921 * Any value that are not these values, the FW will round
44922 * down to the closest support number of entries.
44924 uint32_t max_entries_supported;
44926 * The entry size in bytes of each entry in the EXT EM
44927 * KEY0/KEY1 tables.
44929 uint16_t key_entry_size;
44931 * The entry size in bytes of each entry in the EXT EM RECORD
44934 uint16_t record_entry_size;
44935 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
44936 uint16_t efc_entry_size;
44937 /* The FID size in bytes of each entry in the EXT EM FID tables. */
44938 uint16_t fid_entry_size;
44939 /* Maximum number of ctxt mem allocations allowed. */
44940 uint32_t max_ctxt_mem_allocs;
44942 * Maximum number of static buckets that can be assigned to lookup
44945 uint32_t max_static_buckets;
44947 uint8_t unused1[7];
44949 * This field is used in Output records to indicate that the
44950 * output is completely written to RAM. This field should be
44951 * read as '1' to indicate that the output has been
44952 * completely written. When writing a command completion or
44953 * response to an internal processor, the order of writes has
44954 * to be such that this field is written last.
44959 /*********************
44960 * hwrm_tf_ext_em_op *
44961 *********************/
44964 /* hwrm_tf_ext_em_op_input (size:256b/32B) */
44965 struct hwrm_tf_ext_em_op_input {
44966 /* The HWRM command request type. */
44969 * The completion ring to send the completion event on. This should
44970 * be the NQ ID returned from the `nq_alloc` HWRM command.
44972 uint16_t cmpl_ring;
44974 * The sequence ID is used by the driver for tracking multiple
44975 * commands. This ID is treated as opaque data by the firmware and
44976 * the value is returned in the `hwrm_resp_hdr` upon completion.
44980 * The target ID of the command:
44981 * * 0x0-0xFFF8 - The function ID
44982 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44983 * * 0xFFFD - Reserved for user-space HWRM interface
44986 uint16_t target_id;
44988 * A physical address pointer pointing to a host buffer that the
44989 * command's response data will be written. This can be either a host
44990 * physical address (HPA) or a guest physical address (GPA) and must
44991 * point to a physically contiguous block of memory.
44993 uint64_t resp_addr;
44994 /* Control flags. */
44996 /* Indicates the flow direction. */
44997 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
44998 /* If this bit set to 0, then it indicates rx flow. */
44999 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45000 /* If this bit is set to 1, then it indicates that tx flow. */
45001 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45002 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
45003 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
45006 /* The number of EXT EM key table entries to be configured. */
45008 /* This value is reserved and should not be used. */
45009 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
45011 * To properly stop EXT EM and ensure there are no DMA's,
45012 * the caller must disable EXT EM for the given PF, using
45013 * this call. This will safely disable EXT EM and ensure
45014 * that all DMA'ed to the keys/records/efc have been
45017 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
45019 * Once the EXT EM host memory has been configured, EXT EM
45020 * options have been configured. Then the caller should
45021 * enable EXT EM for the given PF. Note once this call has
45022 * been made, then the EXT EM mechanism will be active and
45023 * DMA's will occur as packets are processed.
45025 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
45027 * Clear EXT EM settings for the given PF so that the
45028 * register values are reset back to their initial state.
45030 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
45031 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
45032 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
45035 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45036 uint32_t fw_session_id;
45041 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
45042 struct hwrm_tf_ext_em_op_output {
45043 /* The specific error status for the command. */
45044 uint16_t error_code;
45045 /* The HWRM command request type. */
45047 /* The sequence ID from the original command. */
45049 /* The length of the response data in number of bytes. */
45052 uint8_t unused0[7];
45054 * This field is used in Output records to indicate that the
45055 * output is completely written to RAM. This field should be
45056 * read as '1' to indicate that the output has been
45057 * completely written. When writing a command completion or
45058 * response to an internal processor, the order of writes has
45059 * to be such that this field is written last.
45064 /**********************
45065 * hwrm_tf_ext_em_cfg *
45066 **********************/
45069 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
45070 struct hwrm_tf_ext_em_cfg_input {
45071 /* The HWRM command request type. */
45074 * The completion ring to send the completion event on. This should
45075 * be the NQ ID returned from the `nq_alloc` HWRM command.
45077 uint16_t cmpl_ring;
45079 * The sequence ID is used by the driver for tracking multiple
45080 * commands. This ID is treated as opaque data by the firmware and
45081 * the value is returned in the `hwrm_resp_hdr` upon completion.
45085 * The target ID of the command:
45086 * * 0x0-0xFFF8 - The function ID
45087 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45088 * * 0xFFFD - Reserved for user-space HWRM interface
45091 uint16_t target_id;
45093 * A physical address pointer pointing to a host buffer that the
45094 * command's response data will be written. This can be either a host
45095 * physical address (HPA) or a guest physical address (GPA) and must
45096 * point to a physically contiguous block of memory.
45098 uint64_t resp_addr;
45099 /* Control flags. */
45101 /* Indicates the flow direction. */
45102 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
45104 /* If this bit set to 0, then it indicates rx flow. */
45105 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
45107 /* If this bit is set to 1, then it indicates that tx flow. */
45108 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
45110 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
45111 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
45112 /* When set to 1, all offloaded flows will be sent to EXT EM. */
45113 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
45115 /* When set to 1, secondary, 0 means primary. */
45116 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
45119 * Group_id which used by Firmware to identify memory pools belonging
45120 * to certain group.
45124 * Dynamically reconfigure EEM pending cache every 1/10th of second.
45125 * If set to 0 it will disable the EEM HW flush of the pending cache.
45127 uint8_t flush_interval;
45131 * Configured EXT EM with the given number of entries. All
45132 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
45133 * same number of entries and all tables will be configured
45134 * using this value. Current minimum value is 32k. Current
45135 * maximum value is 128M.
45137 uint32_t num_entries;
45140 * This bit must be '1' for the group_id field to be
45143 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
45146 * This bit must be '1' for the flush_interval field to be
45149 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
45152 * This bit must be '1' for the num_entries field to be
45155 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
45158 * This bit must be '1' for the key0_ctx_id field to be
45161 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
45164 * This bit must be '1' for the key1_ctx_id field to be
45167 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
45170 * This bit must be '1' for the record_ctx_id field to be
45173 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
45176 * This bit must be '1' for the efc_ctx_id field to be
45179 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
45182 * This bit must be '1' for the fid_ctx_id field to be
45185 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
45188 * This bit must be '1' for the action_ctx_id field to be
45191 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
45194 * This bit must be '1' for the action_tbl_scope field to be
45197 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
45200 * This bit must be '1' for the lkup_ctx_id field to be
45203 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
45206 * This bit must be '1' for the lkup_tbl_scope field to be
45209 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
45212 * This bit must be '1' for the lkup_static_buckets field to be
45215 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
45217 /* Configured EXT EM with the given context if for KEY0 table. */
45218 uint16_t key0_ctx_id;
45219 /* Configured EXT EM with the given context if for KEY1 table. */
45220 uint16_t key1_ctx_id;
45221 /* Configured EXT EM with the given context if for RECORD table. */
45222 uint16_t record_ctx_id;
45223 /* Configured EXT EM with the given context if for EFC table. */
45224 uint16_t efc_ctx_id;
45225 /* Configured EXT EM with the given context if for EFC table. */
45226 uint16_t fid_ctx_id;
45227 /* Context id of action table scope. */
45228 uint16_t action_ctx_id;
45229 /* Table scope id used for action record entries. */
45230 uint16_t action_tbl_scope;
45231 /* Context id of lookup table scope. */
45232 uint16_t lkup_ctx_id;
45233 /* Table scope id used for EM lookup entries. */
45234 uint16_t lkup_tbl_scope;
45238 * Number of 32B static buckets to be allocated at the beginning
45241 uint32_t lkup_static_buckets;
45242 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45243 uint32_t fw_session_id;
45248 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
45249 struct hwrm_tf_ext_em_cfg_output {
45250 /* The specific error status for the command. */
45251 uint16_t error_code;
45252 /* The HWRM command request type. */
45254 /* The sequence ID from the original command. */
45256 /* The length of the response data in number of bytes. */
45259 uint8_t unused0[7];
45261 * This field is used in Output records to indicate that the
45262 * output is completely written to RAM. This field should be
45263 * read as '1' to indicate that the output has been
45264 * completely written. When writing a command completion or
45265 * response to an internal processor, the order of writes has
45266 * to be such that this field is written last.
45271 /***********************
45272 * hwrm_tf_ext_em_qcfg *
45273 ***********************/
45276 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
45277 struct hwrm_tf_ext_em_qcfg_input {
45278 /* The HWRM command request type. */
45281 * The completion ring to send the completion event on. This should
45282 * be the NQ ID returned from the `nq_alloc` HWRM command.
45284 uint16_t cmpl_ring;
45286 * The sequence ID is used by the driver for tracking multiple
45287 * commands. This ID is treated as opaque data by the firmware and
45288 * the value is returned in the `hwrm_resp_hdr` upon completion.
45292 * The target ID of the command:
45293 * * 0x0-0xFFF8 - The function ID
45294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45295 * * 0xFFFD - Reserved for user-space HWRM interface
45298 uint16_t target_id;
45300 * A physical address pointer pointing to a host buffer that the
45301 * command's response data will be written. This can be either a host
45302 * physical address (HPA) or a guest physical address (GPA) and must
45303 * point to a physically contiguous block of memory.
45305 uint64_t resp_addr;
45306 /* Control flags. */
45308 /* Indicates the flow direction. */
45309 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
45310 /* If this bit set to 0, then it indicates rx flow. */
45311 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45312 /* If this bit is set to 1, then it indicates that tx flow. */
45313 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45314 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
45315 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
45316 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45317 uint32_t fw_session_id;
45320 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
45321 struct hwrm_tf_ext_em_qcfg_output {
45322 /* The specific error status for the command. */
45323 uint16_t error_code;
45324 /* The HWRM command request type. */
45326 /* The sequence ID from the original command. */
45328 /* The length of the response data in number of bytes. */
45330 /* Control flags. */
45332 /* Indicates the flow direction. */
45333 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
45335 /* If this bit set to 0, then it indicates rx flow. */
45336 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
45338 /* If this bit is set to 1, then it indicates that tx flow. */
45339 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
45341 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
45342 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
45343 /* When set to 1, all offloaded flows will be sent to EXT EM. */
45344 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
45346 /* The number of entries the FW has configured for EXT EM. */
45347 uint32_t num_entries;
45348 /* Configured EXT EM with the given context if for KEY0 table. */
45349 uint16_t key0_ctx_id;
45350 /* Configured EXT EM with the given context if for KEY1 table. */
45351 uint16_t key1_ctx_id;
45352 /* Configured EXT EM with the given context if for RECORD table. */
45353 uint16_t record_ctx_id;
45354 /* Configured EXT EM with the given context if for EFC table. */
45355 uint16_t efc_ctx_id;
45356 /* Configured EXT EM with the given context if for EFC table. */
45357 uint16_t fid_ctx_id;
45360 uint32_t supported;
45361 /* This bit must be '1' for the group_id field is set. */
45362 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
45364 /* This bit must be '1' for the flush_interval field is set. */
45365 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
45367 /* This bit must be '1' for the num_entries field is set. */
45368 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
45370 /* This bit must be '1' for the key0_ctx_id field is set. */
45371 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
45373 /* This bit must be '1' for the key1_ctx_id field is set. */
45374 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
45376 /* This bit must be '1' for the record_ctx_id field is set. */
45377 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
45379 /* This bit must be '1' for the efc_ctx_id field is set. */
45380 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
45382 /* This bit must be '1' for the fid_ctx_id field is set. */
45383 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
45385 /* This bit must be '1' for the action_ctx_id field is set. */
45386 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
45388 /* This bit must be '1' for the action_tbl_scope field is set. */
45389 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
45391 /* This bit must be '1' for the lkup_ctx_id field is set. */
45392 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
45394 /* This bit must be '1' for the lkup_tbl_scope field is set. */
45395 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
45397 /* This bit must be '1' for the lkup_static_buckets field is set. */
45398 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
45401 * Group id is used by firmware to identify memory pools belonging
45402 * to certain group.
45405 /* EEM pending cache flush interval in 1/10th of second. */
45406 uint8_t flush_interval;
45409 /* Context id of action table scope. */
45410 uint16_t action_ctx_id;
45411 /* Table scope id used for action record entries. */
45412 uint16_t action_tbl_scope;
45413 /* Context id of lookup table scope. */
45414 uint16_t lkup_ctx_id;
45415 /* Table scope id used for EM lookup entries. */
45416 uint16_t lkup_tbl_scope;
45418 * Number of 32B static buckets to be allocated at the beginning
45421 uint32_t lkup_static_buckets;
45423 uint8_t unused2[7];
45425 * This field is used in Output records to indicate that the
45426 * output is completely written to RAM. This field should be
45427 * read as '1' to indicate that the output has been
45428 * completely written. When writing a command completion or
45429 * response to an internal processor, the order of writes has
45430 * to be such that this field is written last.
45435 /*********************
45436 * hwrm_tf_em_insert *
45437 *********************/
45440 /* hwrm_tf_em_insert_input (size:832b/104B) */
45441 struct hwrm_tf_em_insert_input {
45442 /* The HWRM command request type. */
45445 * The completion ring to send the completion event on. This should
45446 * be the NQ ID returned from the `nq_alloc` HWRM command.
45448 uint16_t cmpl_ring;
45450 * The sequence ID is used by the driver for tracking multiple
45451 * commands. This ID is treated as opaque data by the firmware and
45452 * the value is returned in the `hwrm_resp_hdr` upon completion.
45456 * The target ID of the command:
45457 * * 0x0-0xFFF8 - The function ID
45458 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45459 * * 0xFFFD - Reserved for user-space HWRM interface
45462 uint16_t target_id;
45464 * A physical address pointer pointing to a host buffer that the
45465 * command's response data will be written. This can be either a host
45466 * physical address (HPA) or a guest physical address (GPA) and must
45467 * point to a physically contiguous block of memory.
45469 uint64_t resp_addr;
45470 /* Firmware Session Id. */
45471 uint32_t fw_session_id;
45472 /* Control Flags. */
45474 /* Indicates the flow direction. */
45475 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
45476 /* If this bit set to 0, then it indicates rx flow. */
45477 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45478 /* If this bit is set to 1, then it indicates that tx flow. */
45479 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45480 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
45481 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
45482 /* Reported match strength. */
45484 /* Index to action. */
45485 uint32_t action_ptr;
45486 /* Index of EM record. */
45487 uint32_t em_record_idx;
45488 /* EM Key value. */
45489 uint64_t em_key[8];
45490 /* Number of bits in em_key. */
45491 uint16_t em_key_bitlen;
45493 uint16_t unused0[3];
45496 /* hwrm_tf_em_insert_output (size:128b/16B) */
45497 struct hwrm_tf_em_insert_output {
45498 /* The specific error status for the command. */
45499 uint16_t error_code;
45500 /* The HWRM command request type. */
45502 /* The sequence ID from the original command. */
45504 /* The length of the response data in number of bytes. */
45506 /* EM record pointer index. */
45507 uint16_t rptr_index;
45508 /* EM record offset 0~3. */
45509 uint8_t rptr_entry;
45510 /* Number of word entries consumed by the key. */
45511 uint8_t num_of_entries;
45516 /**************************
45517 * hwrm_tf_em_hash_insert *
45518 **************************/
45521 /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
45522 struct hwrm_tf_em_hash_insert_input {
45523 /* The HWRM command request type. */
45526 * The completion ring to send the completion event on. This should
45527 * be the NQ ID returned from the `nq_alloc` HWRM command.
45529 uint16_t cmpl_ring;
45531 * The sequence ID is used by the driver for tracking multiple
45532 * commands. This ID is treated as opaque data by the firmware and
45533 * the value is returned in the `hwrm_resp_hdr` upon completion.
45537 * The target ID of the command:
45538 * * 0x0-0xFFF8 - The function ID
45539 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45540 * * 0xFFFD - Reserved for user-space HWRM interface
45543 uint16_t target_id;
45545 * A physical address pointer pointing to a host buffer that the
45546 * command's response data will be written. This can be either a host
45547 * physical address (HPA) or a guest physical address (GPA) and must
45548 * point to a physically contiguous block of memory.
45550 uint64_t resp_addr;
45551 /* Firmware Session Id. */
45552 uint32_t fw_session_id;
45553 /* Control Flags. */
45555 /* Indicates the flow direction. */
45556 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
45557 /* If this bit set to 0, then it indicates rx flow. */
45558 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45559 /* If this bit is set to 1, then it indicates that tx flow. */
45560 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45561 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
45562 HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
45563 /* Number of bits in the EM record. */
45564 uint16_t em_record_size_bits;
45565 /* CRC32 hash of key. */
45566 uint32_t key0_hash;
45567 /* Lookup3 hash of key. */
45568 uint32_t key1_hash;
45569 /* Index of EM record. */
45570 uint32_t em_record_idx;
45574 uint64_t em_record[11];
45577 /* hwrm_tf_em_hash_insert_output (size:128b/16B) */
45578 struct hwrm_tf_em_hash_insert_output {
45579 /* The specific error status for the command. */
45580 uint16_t error_code;
45581 /* The HWRM command request type. */
45583 /* The sequence ID from the original command. */
45585 /* The length of the response data in number of bytes. */
45587 /* EM record pointer index. */
45588 uint16_t rptr_index;
45589 /* EM record offset 0~3. */
45590 uint8_t rptr_entry;
45591 /* Number of word entries consumed by the key. */
45592 uint8_t num_of_entries;
45597 /*********************
45598 * hwrm_tf_em_delete *
45599 *********************/
45602 /* hwrm_tf_em_delete_input (size:832b/104B) */
45603 struct hwrm_tf_em_delete_input {
45604 /* The HWRM command request type. */
45607 * The completion ring to send the completion event on. This should
45608 * be the NQ ID returned from the `nq_alloc` HWRM command.
45610 uint16_t cmpl_ring;
45612 * The sequence ID is used by the driver for tracking multiple
45613 * commands. This ID is treated as opaque data by the firmware and
45614 * the value is returned in the `hwrm_resp_hdr` upon completion.
45618 * The target ID of the command:
45619 * * 0x0-0xFFF8 - The function ID
45620 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45621 * * 0xFFFD - Reserved for user-space HWRM interface
45624 uint16_t target_id;
45626 * A physical address pointer pointing to a host buffer that the
45627 * command's response data will be written. This can be either a host
45628 * physical address (HPA) or a guest physical address (GPA) and must
45629 * point to a physically contiguous block of memory.
45631 uint64_t resp_addr;
45633 uint32_t fw_session_id;
45634 /* Control flags. */
45636 /* Indicates the flow direction. */
45637 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
45638 /* If this bit set to 0, then it indicates rx flow. */
45639 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45640 /* If this bit is set to 1, then it indicates that tx flow. */
45641 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45642 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
45643 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
45646 /* EM internal flow hanndle. */
45647 uint64_t flow_handle;
45649 uint64_t em_key[8];
45650 /* Number of bits in em_key. */
45651 uint16_t em_key_bitlen;
45653 uint16_t unused1[3];
45656 /* hwrm_tf_em_delete_output (size:128b/16B) */
45657 struct hwrm_tf_em_delete_output {
45658 /* The specific error status for the command. */
45659 uint16_t error_code;
45660 /* The HWRM command request type. */
45662 /* The sequence ID from the original command. */
45664 /* The length of the response data in number of bytes. */
45666 /* Original stack allocation index. */
45669 uint16_t unused0[3];
45672 /*******************
45673 * hwrm_tf_em_move *
45674 *******************/
45677 /* hwrm_tf_em_move_input (size:320b/40B) */
45678 struct hwrm_tf_em_move_input {
45679 /* The HWRM command request type. */
45682 * The completion ring to send the completion event on. This should
45683 * be the NQ ID returned from the `nq_alloc` HWRM command.
45685 uint16_t cmpl_ring;
45687 * The sequence ID is used by the driver for tracking multiple
45688 * commands. This ID is treated as opaque data by the firmware and
45689 * the value is returned in the `hwrm_resp_hdr` upon completion.
45693 * The target ID of the command:
45694 * * 0x0-0xFFF8 - The function ID
45695 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45696 * * 0xFFFD - Reserved for user-space HWRM interface
45699 uint16_t target_id;
45701 * A physical address pointer pointing to a host buffer that the
45702 * command's response data will be written. This can be either a host
45703 * physical address (HPA) or a guest physical address (GPA) and must
45704 * point to a physically contiguous block of memory.
45706 uint64_t resp_addr;
45708 uint32_t fw_session_id;
45709 /* Control flags. */
45711 /* Indicates the flow direction. */
45712 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
45713 /* If this bit set to 0, then it indicates rx flow. */
45714 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45715 /* If this bit is set to 1, then it indicates tx flow. */
45716 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45717 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \
45718 HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX
45719 /* Number of EM entry blocks */
45720 uint16_t num_blocks;
45721 /* New index for entry */
45722 uint32_t new_index;
45725 /* EM internal flow handle. */
45726 uint64_t flow_handle;
45729 /* hwrm_tf_em_move_output (size:128b/16B) */
45730 struct hwrm_tf_em_move_output {
45731 /* The specific error status for the command. */
45732 uint16_t error_code;
45733 /* The HWRM command request type. */
45735 /* The sequence ID from the original command. */
45737 /* The length of the response data in number of bytes. */
45739 /* Index of old entry. */
45742 uint16_t unused0[3];
45745 /********************
45746 * hwrm_tf_tcam_set *
45747 ********************/
45750 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
45751 struct hwrm_tf_tcam_set_input {
45752 /* The HWRM command request type. */
45755 * The completion ring to send the completion event on. This should
45756 * be the NQ ID returned from the `nq_alloc` HWRM command.
45758 uint16_t cmpl_ring;
45760 * The sequence ID is used by the driver for tracking multiple
45761 * commands. This ID is treated as opaque data by the firmware and
45762 * the value is returned in the `hwrm_resp_hdr` upon completion.
45766 * The target ID of the command:
45767 * * 0x0-0xFFF8 - The function ID
45768 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45769 * * 0xFFFD - Reserved for user-space HWRM interface
45772 uint16_t target_id;
45774 * A physical address pointer pointing to a host buffer that the
45775 * command's response data will be written. This can be either a host
45776 * physical address (HPA) or a guest physical address (GPA) and must
45777 * point to a physically contiguous block of memory.
45779 uint64_t resp_addr;
45780 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45781 uint32_t fw_session_id;
45782 /* Control flags. */
45784 /* Indicates the flow direction. */
45785 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
45786 /* If this bit set to 0, then it indicates rx flow. */
45787 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45788 /* If this bit is set to 1, then it indicates that tx flow. */
45789 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45790 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
45791 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
45793 * Indicate device data is being sent via DMA, the device
45794 * data is packing does not change.
45796 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
45798 * TCAM type of the resource, defined globally in the
45799 * hwrm_tf_resc_type enum.
45802 /* Index of TCAM entry. */
45804 /* Number of bytes in the TCAM key. */
45806 /* Number of bytes in the TCAM result. */
45807 uint8_t result_size;
45809 * Offset from which the mask bytes start in the device data
45810 * array, key offset is always 0.
45812 uint8_t mask_offset;
45813 /* Offset from which the result bytes start in the device data array. */
45814 uint8_t result_offset;
45816 uint8_t unused0[6];
45818 * TCAM key located at offset 0, mask located at mask_offsec
45819 * and result at result_offsec for the device.
45821 uint8_t dev_data[88];
45824 /* hwrm_tf_tcam_set_output (size:128b/16B) */
45825 struct hwrm_tf_tcam_set_output {
45826 /* The specific error status for the command. */
45827 uint16_t error_code;
45828 /* The HWRM command request type. */
45830 /* The sequence ID from the original command. */
45832 /* The length of the response data in number of bytes. */
45835 uint8_t unused0[7];
45837 * This field is used in Output records to indicate that the
45838 * output is completely written to RAM. This field should be
45839 * read as '1' to indicate that the output has been
45840 * completely written. When writing a command completion or
45841 * response to an internal processor, the order of writes has
45842 * to be such that this field is written last.
45847 /********************
45848 * hwrm_tf_tcam_get *
45849 ********************/
45852 /* hwrm_tf_tcam_get_input (size:256b/32B) */
45853 struct hwrm_tf_tcam_get_input {
45854 /* The HWRM command request type. */
45857 * The completion ring to send the completion event on. This should
45858 * be the NQ ID returned from the `nq_alloc` HWRM command.
45860 uint16_t cmpl_ring;
45862 * The sequence ID is used by the driver for tracking multiple
45863 * commands. This ID is treated as opaque data by the firmware and
45864 * the value is returned in the `hwrm_resp_hdr` upon completion.
45868 * The target ID of the command:
45869 * * 0x0-0xFFF8 - The function ID
45870 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45871 * * 0xFFFD - Reserved for user-space HWRM interface
45874 uint16_t target_id;
45876 * A physical address pointer pointing to a host buffer that the
45877 * command's response data will be written. This can be either a host
45878 * physical address (HPA) or a guest physical address (GPA) and must
45879 * point to a physically contiguous block of memory.
45881 uint64_t resp_addr;
45882 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45883 uint32_t fw_session_id;
45884 /* Control flags. */
45886 /* Indicates the flow direction. */
45887 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45888 /* If this bit set to 0, then it indicates rx flow. */
45889 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45890 /* If this bit is set to 1, then it indicates that tx flow. */
45891 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45892 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
45893 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
45895 * TCAM type of the resource, defined globally in the
45896 * hwrm_tf_resc_type enum.
45899 /* Index of a TCAM entry. */
45905 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
45906 struct hwrm_tf_tcam_get_output {
45907 /* The specific error status for the command. */
45908 uint16_t error_code;
45909 /* The HWRM command request type. */
45911 /* The sequence ID from the original command. */
45913 /* The length of the response data in number of bytes. */
45915 /* Number of bytes in the TCAM key. */
45917 /* Number of bytes in the TCAM entry. */
45918 uint8_t result_size;
45919 /* Offset from which the mask bytes start in the device data array. */
45920 uint8_t mask_offset;
45921 /* Offset from which the result bytes start in the device data array. */
45922 uint8_t result_offset;
45924 uint8_t unused0[4];
45926 * TCAM key located at offset 0, mask located at mask_offsec
45927 * and result at result_offsec for the device.
45929 uint8_t dev_data[272];
45931 uint8_t unused1[7];
45933 * This field is used in Output records to indicate that the
45934 * output is completely written to RAM. This field should be
45935 * read as '1' to indicate that the output has been
45936 * completely written. When writing a command completion or
45937 * response to an internal processor, the order of writes has
45938 * to be such that this field is written last.
45943 /*********************
45944 * hwrm_tf_tcam_move *
45945 *********************/
45948 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
45949 struct hwrm_tf_tcam_move_input {
45950 /* The HWRM command request type. */
45953 * The completion ring to send the completion event on. This should
45954 * be the NQ ID returned from the `nq_alloc` HWRM command.
45956 uint16_t cmpl_ring;
45958 * The sequence ID is used by the driver for tracking multiple
45959 * commands. This ID is treated as opaque data by the firmware and
45960 * the value is returned in the `hwrm_resp_hdr` upon completion.
45964 * The target ID of the command:
45965 * * 0x0-0xFFF8 - The function ID
45966 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45967 * * 0xFFFD - Reserved for user-space HWRM interface
45970 uint16_t target_id;
45972 * A physical address pointer pointing to a host buffer that the
45973 * command's response data will be written. This can be either a host
45974 * physical address (HPA) or a guest physical address (GPA) and must
45975 * point to a physically contiguous block of memory.
45977 uint64_t resp_addr;
45978 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45979 uint32_t fw_session_id;
45980 /* Control flags. */
45982 /* Indicates the flow direction. */
45983 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
45984 /* If this bit set to 0, then it indicates rx flow. */
45985 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45986 /* If this bit is set to 1, then it indicates that tx flow. */
45987 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45988 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
45989 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
45991 * TCAM type of the resource, defined globally in the
45992 * hwrm_tf_resc_type enum.
45995 /* Number of TCAM index pairs to be swapped for the device. */
45999 /* TCAM index pairs to be swapped for the device. */
46000 uint16_t idx_pairs[48];
46003 /* hwrm_tf_tcam_move_output (size:128b/16B) */
46004 struct hwrm_tf_tcam_move_output {
46005 /* The specific error status for the command. */
46006 uint16_t error_code;
46007 /* The HWRM command request type. */
46009 /* The sequence ID from the original command. */
46011 /* The length of the response data in number of bytes. */
46014 uint8_t unused0[7];
46016 * This field is used in Output records to indicate that the
46017 * output is completely written to RAM. This field should be
46018 * read as '1' to indicate that the output has been
46019 * completely written. When writing a command completion or
46020 * response to an internal processor, the order of writes has
46021 * to be such that this field is written last.
46026 /*********************
46027 * hwrm_tf_tcam_free *
46028 *********************/
46031 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
46032 struct hwrm_tf_tcam_free_input {
46033 /* The HWRM command request type. */
46036 * The completion ring to send the completion event on. This should
46037 * be the NQ ID returned from the `nq_alloc` HWRM command.
46039 uint16_t cmpl_ring;
46041 * The sequence ID is used by the driver for tracking multiple
46042 * commands. This ID is treated as opaque data by the firmware and
46043 * the value is returned in the `hwrm_resp_hdr` upon completion.
46047 * The target ID of the command:
46048 * * 0x0-0xFFF8 - The function ID
46049 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46050 * * 0xFFFD - Reserved for user-space HWRM interface
46053 uint16_t target_id;
46055 * A physical address pointer pointing to a host buffer that the
46056 * command's response data will be written. This can be either a host
46057 * physical address (HPA) or a guest physical address (GPA) and must
46058 * point to a physically contiguous block of memory.
46060 uint64_t resp_addr;
46061 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46062 uint32_t fw_session_id;
46063 /* Control flags. */
46065 /* Indicates the flow direction. */
46066 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
46067 /* If this bit set to 0, then it indicates rx flow. */
46068 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46069 /* If this bit is set to 1, then it indicates that tx flow. */
46070 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46071 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
46072 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
46074 * TCAM type of the resource, defined globally in the
46075 * hwrm_tf_resc_type enum.
46078 /* Number of TCAM index to be deleted for the device. */
46082 /* TCAM index list to be deleted for the device. */
46083 uint16_t idx_list[48];
46086 /* hwrm_tf_tcam_free_output (size:128b/16B) */
46087 struct hwrm_tf_tcam_free_output {
46088 /* The specific error status for the command. */
46089 uint16_t error_code;
46090 /* The HWRM command request type. */
46092 /* The sequence ID from the original command. */
46094 /* The length of the response data in number of bytes. */
46097 uint8_t unused0[7];
46099 * This field is used in Output records to indicate that the
46100 * output is completely written to RAM. This field should be
46101 * read as '1' to indicate that the output has been
46102 * completely written. When writing a command completion or
46103 * response to an internal processor, the order of writes has
46104 * to be such that this field is written last.
46109 /**************************
46110 * hwrm_tf_global_cfg_set *
46111 **************************/
46114 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
46115 struct hwrm_tf_global_cfg_set_input {
46116 /* The HWRM command request type. */
46119 * The completion ring to send the completion event on. This should
46120 * be the NQ ID returned from the `nq_alloc` HWRM command.
46122 uint16_t cmpl_ring;
46124 * The sequence ID is used by the driver for tracking multiple
46125 * commands. This ID is treated as opaque data by the firmware and
46126 * the value is returned in the `hwrm_resp_hdr` upon completion.
46130 * The target ID of the command:
46131 * * 0x0-0xFFF8 - The function ID
46132 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46133 * * 0xFFFD - Reserved for user-space HWRM interface
46136 uint16_t target_id;
46138 * A physical address pointer pointing to a host buffer that the
46139 * command's response data will be written. This can be either a host
46140 * physical address (HPA) or a guest physical address (GPA) and must
46141 * point to a physically contiguous block of memory.
46143 uint64_t resp_addr;
46144 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46145 uint32_t fw_session_id;
46146 /* Control flags. */
46148 /* Indicates the flow direction. */
46149 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
46150 /* If this bit set to 0, then it indicates rx flow. */
46151 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46152 /* If this bit is set to 1, then it indicates that tx flow. */
46153 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46154 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
46155 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
46156 /* Global Cfg type */
46158 /* Offset of the type */
46160 /* Size of the data to set in bytes */
46163 uint8_t unused0[6];
46166 /* Mask of data to set, 0 indicates no mask */
46170 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
46171 struct hwrm_tf_global_cfg_set_output {
46172 /* The specific error status for the command. */
46173 uint16_t error_code;
46174 /* The HWRM command request type. */
46176 /* The sequence ID from the original command. */
46178 /* The length of the response data in number of bytes. */
46181 uint8_t unused0[7];
46183 * This field is used in Output records to indicate that the
46184 * output is completely written to RAM. This field should be
46185 * read as '1' to indicate that the output has been
46186 * completely written. When writing a command completion or
46187 * response to an internal processor, the order of writes has
46188 * to be such that this field is written last.
46193 /**************************
46194 * hwrm_tf_global_cfg_get *
46195 **************************/
46198 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
46199 struct hwrm_tf_global_cfg_get_input {
46200 /* The HWRM command request type. */
46203 * The completion ring to send the completion event on. This should
46204 * be the NQ ID returned from the `nq_alloc` HWRM command.
46206 uint16_t cmpl_ring;
46208 * The sequence ID is used by the driver for tracking multiple
46209 * commands. This ID is treated as opaque data by the firmware and
46210 * the value is returned in the `hwrm_resp_hdr` upon completion.
46214 * The target ID of the command:
46215 * * 0x0-0xFFF8 - The function ID
46216 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46217 * * 0xFFFD - Reserved for user-space HWRM interface
46220 uint16_t target_id;
46222 * A physical address pointer pointing to a host buffer that the
46223 * command's response data will be written. This can be either a host
46224 * physical address (HPA) or a guest physical address (GPA) and must
46225 * point to a physically contiguous block of memory.
46227 uint64_t resp_addr;
46228 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46229 uint32_t fw_session_id;
46230 /* Control flags. */
46232 /* Indicates the flow direction. */
46233 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
46234 /* If this bit set to 0, then it indicates rx flow. */
46235 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46236 /* If this bit is set to 1, then it indicates that tx flow. */
46237 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46238 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
46239 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
46240 /* Global Cfg type */
46242 /* Offset of the type */
46244 /* Size of the data to set in bytes */
46247 uint8_t unused0[6];
46250 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
46251 struct hwrm_tf_global_cfg_get_output {
46252 /* The specific error status for the command. */
46253 uint16_t error_code;
46254 /* The HWRM command request type. */
46256 /* The sequence ID from the original command. */
46258 /* The length of the response data in number of bytes. */
46260 /* Size of the data read in bytes */
46263 uint8_t unused0[6];
46268 /**********************
46269 * hwrm_tf_if_tbl_get *
46270 **********************/
46273 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
46274 struct hwrm_tf_if_tbl_get_input {
46275 /* The HWRM command request type. */
46278 * The completion ring to send the completion event on. This should
46279 * be the NQ ID returned from the `nq_alloc` HWRM command.
46281 uint16_t cmpl_ring;
46283 * The sequence ID is used by the driver for tracking multiple
46284 * commands. This ID is treated as opaque data by the firmware and
46285 * the value is returned in the `hwrm_resp_hdr` upon completion.
46289 * The target ID of the command:
46290 * * 0x0-0xFFF8 - The function ID
46291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46292 * * 0xFFFD - Reserved for user-space HWRM interface
46295 uint16_t target_id;
46297 * A physical address pointer pointing to a host buffer that the
46298 * command's response data will be written. This can be either a host
46299 * physical address (HPA) or a guest physical address (GPA) and must
46300 * point to a physically contiguous block of memory.
46302 uint64_t resp_addr;
46303 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46304 uint32_t fw_session_id;
46305 /* Control flags. */
46307 /* Indicates the flow direction. */
46308 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
46309 /* If this bit set to 0, then it indicates rx flow. */
46310 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46311 /* If this bit is set to 1, then it indicates that tx flow. */
46312 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46313 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
46314 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
46315 /* Size of the data to set. */
46318 * Type of the resource, defined globally in the
46319 * hwrm_tf_resc_type enum.
46322 /* Index of the type to retrieve. */
46326 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
46327 struct hwrm_tf_if_tbl_get_output {
46328 /* The specific error status for the command. */
46329 uint16_t error_code;
46330 /* The HWRM command request type. */
46332 /* The sequence ID from the original command. */
46334 /* The length of the response data in number of bytes. */
46336 /* Response code. */
46337 uint32_t resp_code;
46338 /* Response size. */
46342 /* Response data. */
46345 uint8_t unused1[7];
46347 * This field is used in Output records to indicate that the output
46348 * is completely written to RAM. This field should be read as '1'
46349 * to indicate that the output has been completely written.
46350 * When writing a command completion or response to an internal
46351 * processor, the order of writes has to be such that this field
46357 /***************************
46358 * hwrm_tf_if_tbl_type_set *
46359 ***************************/
46362 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
46363 struct hwrm_tf_if_tbl_set_input {
46364 /* The HWRM command request type. */
46367 * The completion ring to send the completion event on. This should
46368 * be the NQ ID returned from the `nq_alloc` HWRM command.
46370 uint16_t cmpl_ring;
46372 * The sequence ID is used by the driver for tracking multiple
46373 * commands. This ID is treated as opaque data by the firmware and
46374 * the value is returned in the `hwrm_resp_hdr` upon completion.
46378 * The target ID of the command:
46379 * * 0x0-0xFFF8 - The function ID
46380 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46381 * * 0xFFFD - Reserved for user-space HWRM interface
46384 uint16_t target_id;
46386 * A physical address pointer pointing to a host buffer that the
46387 * command's response data will be written. This can be either a host
46388 * physical address (HPA) or a guest physical address (GPA) and must
46389 * point to a physically contiguous block of memory.
46391 uint64_t resp_addr;
46392 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46393 uint32_t fw_session_id;
46394 /* Control flags. */
46396 /* Indicates the flow direction. */
46397 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
46398 /* If this bit set to 0, then it indicates rx flow. */
46399 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46400 /* If this bit is set to 1, then it indicates that tx flow. */
46401 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46402 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
46403 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
46405 uint8_t unused0[2];
46407 * Type of the resource, defined globally in the
46408 * hwrm_tf_resc_type enum.
46411 /* Index of the type to set. */
46413 /* Size of the data to set. */
46416 uint8_t unused1[6];
46417 /* Data to be set. */
46421 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
46422 struct hwrm_tf_if_tbl_set_output {
46423 /* The specific error status for the command. */
46424 uint16_t error_code;
46425 /* The HWRM command request type. */
46427 /* The sequence ID from the original command. */
46429 /* The length of the response data in number of bytes. */
46432 uint8_t unused0[7];
46434 * This field is used in Output records to indicate that the output
46435 * is completely written to RAM. This field should be read as '1'
46436 * to indicate that the output has been completely written.
46437 * When writing a command completion or response to an internal
46438 * processor, the order of writes has to be such that this field
46444 /*****************************
46445 * hwrm_tf_tbl_type_bulk_get *
46446 *****************************/
46449 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
46450 struct hwrm_tf_tbl_type_bulk_get_input {
46451 /* The HWRM command request type. */
46454 * The completion ring to send the completion event on. This should
46455 * be the NQ ID returned from the `nq_alloc` HWRM command.
46457 uint16_t cmpl_ring;
46459 * The sequence ID is used by the driver for tracking multiple
46460 * commands. This ID is treated as opaque data by the firmware and
46461 * the value is returned in the `hwrm_resp_hdr` upon completion.
46465 * The target ID of the command:
46466 * * 0x0-0xFFF8 - The function ID
46467 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46468 * * 0xFFFD - Reserved for user-space HWRM interface
46471 uint16_t target_id;
46473 * A physical address pointer pointing to a host buffer that the
46474 * command's response data will be written. This can be either a host
46475 * physical address (HPA) or a guest physical address (GPA) and must
46476 * point to a physically contiguous block of memory.
46478 uint64_t resp_addr;
46479 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
46480 uint32_t fw_session_id;
46481 /* Control flags. */
46483 /* Indicates the flow direction. */
46484 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
46485 /* If this bit set to 0, then it indicates rx flow. */
46486 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
46487 /* If this bit is set to 1, then it indicates that tx flow. */
46488 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
46489 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
46490 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
46492 uint8_t unused0[2];
46494 * Type of the resource, defined globally in the
46495 * hwrm_tf_resc_type enum.
46498 /* Starting index of the type to retrieve. */
46499 uint32_t start_index;
46500 /* Number of entries to retrieve. */
46501 uint32_t num_entries;
46502 /* Number of entries to retrieve. */
46504 /* Host memory where data will be stored. */
46505 uint64_t host_addr;
46508 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
46509 struct hwrm_tf_tbl_type_bulk_get_output {
46510 /* The specific error status for the command. */
46511 uint16_t error_code;
46512 /* The HWRM command request type. */
46514 /* The sequence ID from the original command. */
46516 /* The length of the response data in number of bytes. */
46518 /* Response code. */
46519 uint32_t resp_code;
46520 /* Response size. */
46525 * This field is used in Output records to indicate that the output
46526 * is completely written to RAM. This field should be read as '1'
46527 * to indicate that the output has been completely written.
46528 * When writing a command completion or response to an internal
46529 * processor, the order of writes has to be such that this field
46535 /******************************
46536 * hwrm_tunnel_dst_port_query *
46537 ******************************/
46540 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
46541 struct hwrm_tunnel_dst_port_query_input {
46542 /* The HWRM command request type. */
46545 * The completion ring to send the completion event on. This should
46546 * be the NQ ID returned from the `nq_alloc` HWRM command.
46548 uint16_t cmpl_ring;
46550 * The sequence ID is used by the driver for tracking multiple
46551 * commands. This ID is treated as opaque data by the firmware and
46552 * the value is returned in the `hwrm_resp_hdr` upon completion.
46556 * The target ID of the command:
46557 * * 0x0-0xFFF8 - The function ID
46558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46559 * * 0xFFFD - Reserved for user-space HWRM interface
46562 uint16_t target_id;
46564 * A physical address pointer pointing to a host buffer that the
46565 * command's response data will be written. This can be either a host
46566 * physical address (HPA) or a guest physical address (GPA) and must
46567 * point to a physically contiguous block of memory.
46569 uint64_t resp_addr;
46571 uint8_t tunnel_type;
46572 /* Virtual eXtensible Local Area Network (VXLAN) */
46573 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
46575 /* Generic Network Virtualization Encapsulation (Geneve) */
46576 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
46578 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
46579 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
46581 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
46582 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
46584 /* Use fixed layer 2 ether type of 0xFFFF */
46585 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
46587 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
46588 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
46590 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
46591 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
46592 uint8_t unused_0[7];
46595 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
46596 struct hwrm_tunnel_dst_port_query_output {
46597 /* The specific error status for the command. */
46598 uint16_t error_code;
46599 /* The HWRM command request type. */
46601 /* The sequence ID from the original command. */
46603 /* The length of the response data in number of bytes. */
46606 * This field represents the identifier of L4 destination port
46607 * used for the given tunnel type. This field is valid for
46608 * specific tunnel types that use layer 4 (e.g. UDP)
46609 * transports for tunneling.
46611 uint16_t tunnel_dst_port_id;
46613 * This field represents the value of L4 destination port
46614 * identified by tunnel_dst_port_id. This field is valid for
46615 * specific tunnel types that use layer 4 (e.g. UDP)
46616 * transports for tunneling.
46617 * This field is in network byte order.
46619 * A value of 0 means that the destination port is not
46622 uint16_t tunnel_dst_port_val;
46623 uint8_t unused_0[3];
46625 * This field is used in Output records to indicate that the output
46626 * is completely written to RAM. This field should be read as '1'
46627 * to indicate that the output has been completely written.
46628 * When writing a command completion or response to an internal processor,
46629 * the order of writes has to be such that this field is written last.
46634 /******************************
46635 * hwrm_tunnel_dst_port_alloc *
46636 ******************************/
46639 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
46640 struct hwrm_tunnel_dst_port_alloc_input {
46641 /* The HWRM command request type. */
46644 * The completion ring to send the completion event on. This should
46645 * be the NQ ID returned from the `nq_alloc` HWRM command.
46647 uint16_t cmpl_ring;
46649 * The sequence ID is used by the driver for tracking multiple
46650 * commands. This ID is treated as opaque data by the firmware and
46651 * the value is returned in the `hwrm_resp_hdr` upon completion.
46655 * The target ID of the command:
46656 * * 0x0-0xFFF8 - The function ID
46657 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46658 * * 0xFFFD - Reserved for user-space HWRM interface
46661 uint16_t target_id;
46663 * A physical address pointer pointing to a host buffer that the
46664 * command's response data will be written. This can be either a host
46665 * physical address (HPA) or a guest physical address (GPA) and must
46666 * point to a physically contiguous block of memory.
46668 uint64_t resp_addr;
46670 uint8_t tunnel_type;
46671 /* Virtual eXtensible Local Area Network (VXLAN) */
46672 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
46674 /* Generic Network Virtualization Encapsulation (Geneve) */
46675 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
46677 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
46678 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
46680 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
46681 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
46683 /* Use fixed layer 2 ether type of 0xFFFF */
46684 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
46686 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
46687 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
46689 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
46690 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
46693 * This field represents the value of L4 destination port used
46694 * for the given tunnel type. This field is valid for
46695 * specific tunnel types that use layer 4 (e.g. UDP)
46696 * transports for tunneling.
46698 * This field is in network byte order.
46700 * A value of 0 shall fail the command.
46702 uint16_t tunnel_dst_port_val;
46703 uint8_t unused_1[4];
46706 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
46707 struct hwrm_tunnel_dst_port_alloc_output {
46708 /* The specific error status for the command. */
46709 uint16_t error_code;
46710 /* The HWRM command request type. */
46712 /* The sequence ID from the original command. */
46714 /* The length of the response data in number of bytes. */
46717 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
46718 * types that has l4 destination port parameters.
46720 uint16_t tunnel_dst_port_id;
46721 uint8_t unused_0[5];
46723 * This field is used in Output records to indicate that the output
46724 * is completely written to RAM. This field should be read as '1'
46725 * to indicate that the output has been completely written.
46726 * When writing a command completion or response to an internal processor,
46727 * the order of writes has to be such that this field is written last.
46732 /*****************************
46733 * hwrm_tunnel_dst_port_free *
46734 *****************************/
46737 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
46738 struct hwrm_tunnel_dst_port_free_input {
46739 /* The HWRM command request type. */
46742 * The completion ring to send the completion event on. This should
46743 * be the NQ ID returned from the `nq_alloc` HWRM command.
46745 uint16_t cmpl_ring;
46747 * The sequence ID is used by the driver for tracking multiple
46748 * commands. This ID is treated as opaque data by the firmware and
46749 * the value is returned in the `hwrm_resp_hdr` upon completion.
46753 * The target ID of the command:
46754 * * 0x0-0xFFF8 - The function ID
46755 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46756 * * 0xFFFD - Reserved for user-space HWRM interface
46759 uint16_t target_id;
46761 * A physical address pointer pointing to a host buffer that the
46762 * command's response data will be written. This can be either a host
46763 * physical address (HPA) or a guest physical address (GPA) and must
46764 * point to a physically contiguous block of memory.
46766 uint64_t resp_addr;
46768 uint8_t tunnel_type;
46769 /* Virtual eXtensible Local Area Network (VXLAN) */
46770 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
46772 /* Generic Network Virtualization Encapsulation (Geneve) */
46773 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
46775 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
46776 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
46778 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
46779 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
46781 /* Use fixed layer 2 ether type of 0xFFFF */
46782 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
46784 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
46785 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
46787 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
46788 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
46791 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
46792 * types that has l4 destination port parameters.
46794 uint16_t tunnel_dst_port_id;
46795 uint8_t unused_1[4];
46798 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
46799 struct hwrm_tunnel_dst_port_free_output {
46800 /* The specific error status for the command. */
46801 uint16_t error_code;
46802 /* The HWRM command request type. */
46804 /* The sequence ID from the original command. */
46806 /* The length of the response data in number of bytes. */
46808 uint8_t unused_1[7];
46810 * This field is used in Output records to indicate that the output
46811 * is completely written to RAM. This field should be read as '1'
46812 * to indicate that the output has been completely written.
46813 * When writing a command completion or response to an internal processor,
46814 * the order of writes has to be such that this field is written last.
46819 /* Periodic statistics context DMA to host. */
46820 /* ctx_hw_stats (size:1280b/160B) */
46821 struct ctx_hw_stats {
46822 /* Number of received unicast packets */
46823 uint64_t rx_ucast_pkts;
46824 /* Number of received multicast packets */
46825 uint64_t rx_mcast_pkts;
46826 /* Number of received broadcast packets */
46827 uint64_t rx_bcast_pkts;
46828 /* Number of discarded packets on receive path */
46829 uint64_t rx_discard_pkts;
46830 /* Number of packets on receive path with error */
46831 uint64_t rx_error_pkts;
46832 /* Number of received bytes for unicast traffic */
46833 uint64_t rx_ucast_bytes;
46834 /* Number of received bytes for multicast traffic */
46835 uint64_t rx_mcast_bytes;
46836 /* Number of received bytes for broadcast traffic */
46837 uint64_t rx_bcast_bytes;
46838 /* Number of transmitted unicast packets */
46839 uint64_t tx_ucast_pkts;
46840 /* Number of transmitted multicast packets */
46841 uint64_t tx_mcast_pkts;
46842 /* Number of transmitted broadcast packets */
46843 uint64_t tx_bcast_pkts;
46844 /* Number of packets on transmit path with error */
46845 uint64_t tx_error_pkts;
46846 /* Number of discarded packets on transmit path */
46847 uint64_t tx_discard_pkts;
46848 /* Number of transmitted bytes for unicast traffic */
46849 uint64_t tx_ucast_bytes;
46850 /* Number of transmitted bytes for multicast traffic */
46851 uint64_t tx_mcast_bytes;
46852 /* Number of transmitted bytes for broadcast traffic */
46853 uint64_t tx_bcast_bytes;
46854 /* Number of TPA packets */
46856 /* Number of TPA bytes */
46857 uint64_t tpa_bytes;
46858 /* Number of TPA events */
46859 uint64_t tpa_events;
46860 /* Number of TPA aborts */
46861 uint64_t tpa_aborts;
46865 * Extended periodic statistics context DMA to host. On cards that
46866 * support TPA v2, additional TPA related stats exist and can be retrieved
46867 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
46869 /* ctx_hw_stats_ext (size:1408b/176B) */
46870 struct ctx_hw_stats_ext {
46871 /* Number of received unicast packets */
46872 uint64_t rx_ucast_pkts;
46873 /* Number of received multicast packets */
46874 uint64_t rx_mcast_pkts;
46875 /* Number of received broadcast packets */
46876 uint64_t rx_bcast_pkts;
46877 /* Number of discarded packets on receive path */
46878 uint64_t rx_discard_pkts;
46879 /* Number of packets on receive path with error */
46880 uint64_t rx_error_pkts;
46881 /* Number of received bytes for unicast traffic */
46882 uint64_t rx_ucast_bytes;
46883 /* Number of received bytes for multicast traffic */
46884 uint64_t rx_mcast_bytes;
46885 /* Number of received bytes for broadcast traffic */
46886 uint64_t rx_bcast_bytes;
46887 /* Number of transmitted unicast packets */
46888 uint64_t tx_ucast_pkts;
46889 /* Number of transmitted multicast packets */
46890 uint64_t tx_mcast_pkts;
46891 /* Number of transmitted broadcast packets */
46892 uint64_t tx_bcast_pkts;
46893 /* Number of packets on transmit path with error */
46894 uint64_t tx_error_pkts;
46895 /* Number of discarded packets on transmit path */
46896 uint64_t tx_discard_pkts;
46897 /* Number of transmitted bytes for unicast traffic */
46898 uint64_t tx_ucast_bytes;
46899 /* Number of transmitted bytes for multicast traffic */
46900 uint64_t tx_mcast_bytes;
46901 /* Number of transmitted bytes for broadcast traffic */
46902 uint64_t tx_bcast_bytes;
46903 /* Number of TPA eligible packets */
46904 uint64_t rx_tpa_eligible_pkt;
46905 /* Number of TPA eligible bytes */
46906 uint64_t rx_tpa_eligible_bytes;
46907 /* Number of TPA packets */
46908 uint64_t rx_tpa_pkt;
46909 /* Number of TPA bytes */
46910 uint64_t rx_tpa_bytes;
46911 /* Number of TPA errors */
46912 uint64_t rx_tpa_errors;
46913 /* Number of TPA events */
46914 uint64_t rx_tpa_events;
46917 /* Periodic Engine statistics context DMA to host. */
46918 /* ctx_eng_stats (size:512b/64B) */
46919 struct ctx_eng_stats {
46921 * Count of data bytes into the Engine.
46922 * This includes any user supplied prefix,
46923 * but does not include any predefined
46926 uint64_t eng_bytes_in;
46927 /* Count of data bytes out of the Engine. */
46928 uint64_t eng_bytes_out;
46930 * Count, in 4-byte (dword) units, of bytes
46931 * that are input as auxiliary data.
46932 * This includes the aux_cmd data.
46934 uint64_t aux_bytes_in;
46936 * Count, in 4-byte (dword) units, of bytes
46937 * that are output as auxiliary data.
46938 * This count is the buffer space for aux_data
46939 * output provided in the RQE, not the actual
46942 uint64_t aux_bytes_out;
46943 /* Count of number of commands executed. */
46946 * Count of number of error commands.
46947 * These are the commands with a
46948 * non-zero status value.
46950 uint64_t error_commands;
46952 * Compression/Encryption Engine usage,
46953 * the unit is count of clock cycles
46955 uint64_t cce_engine_usage;
46957 * De-Compression/De-cryption Engine usage,
46958 * the unit is count of clock cycles
46960 uint64_t cdd_engine_usage;
46963 /***********************
46964 * hwrm_stat_ctx_alloc *
46965 ***********************/
46968 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
46969 struct hwrm_stat_ctx_alloc_input {
46970 /* The HWRM command request type. */
46973 * The completion ring to send the completion event on. This should
46974 * be the NQ ID returned from the `nq_alloc` HWRM command.
46976 uint16_t cmpl_ring;
46978 * The sequence ID is used by the driver for tracking multiple
46979 * commands. This ID is treated as opaque data by the firmware and
46980 * the value is returned in the `hwrm_resp_hdr` upon completion.
46984 * The target ID of the command:
46985 * * 0x0-0xFFF8 - The function ID
46986 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46987 * * 0xFFFD - Reserved for user-space HWRM interface
46990 uint16_t target_id;
46992 * A physical address pointer pointing to a host buffer that the
46993 * command's response data will be written. This can be either a host
46994 * physical address (HPA) or a guest physical address (GPA) and must
46995 * point to a physically contiguous block of memory.
46997 uint64_t resp_addr;
46999 * This is the address for statistic block.
47000 * > For new versions of the chip, this address should be 128B
47003 uint64_t stats_dma_addr;
47005 * The statistic block update period in ms.
47006 * e.g. 250ms, 500ms, 750ms, 1000ms.
47007 * If update_period_ms is 0, then the stats update
47008 * shall be never done and the DMA address shall not be used.
47009 * In this case, the stat block can only be read by
47010 * hwrm_stat_ctx_query command.
47011 * On Ethernet/L2 based devices:
47012 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
47013 * ctx_hw_stats_ext is used for DMA,
47015 * ctx_hw_stats is used for DMA.
47017 uint32_t update_period_ms;
47019 * This field is used to specify statistics context specific
47020 * configuration flags.
47022 uint8_t stat_ctx_flags;
47024 * When this bit is set to '1', the statistics context shall be
47025 * allocated for RoCE traffic only. In this case, traffic other
47026 * than offloaded RoCE traffic shall not be included in this
47027 * statistic context.
47028 * When this bit is set to '0', the statistics context shall be
47029 * used for network traffic or engine traffic.
47031 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
47034 * This is the size of the structure (ctx_hw_stats or
47035 * ctx_hw_stats_ext) that the driver has allocated to be used
47036 * for the periodic DMA updates.
47038 uint16_t stats_dma_length;
47041 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
47042 struct hwrm_stat_ctx_alloc_output {
47043 /* The specific error status for the command. */
47044 uint16_t error_code;
47045 /* The HWRM command request type. */
47047 /* The sequence ID from the original command. */
47049 /* The length of the response data in number of bytes. */
47051 /* This is the statistics context ID value. */
47052 uint32_t stat_ctx_id;
47053 uint8_t unused_0[3];
47055 * This field is used in Output records to indicate that the output
47056 * is completely written to RAM. This field should be read as '1'
47057 * to indicate that the output has been completely written.
47058 * When writing a command completion or response to an internal processor,
47059 * the order of writes has to be such that this field is written last.
47064 /**********************
47065 * hwrm_stat_ctx_free *
47066 **********************/
47069 /* hwrm_stat_ctx_free_input (size:192b/24B) */
47070 struct hwrm_stat_ctx_free_input {
47071 /* The HWRM command request type. */
47074 * The completion ring to send the completion event on. This should
47075 * be the NQ ID returned from the `nq_alloc` HWRM command.
47077 uint16_t cmpl_ring;
47079 * The sequence ID is used by the driver for tracking multiple
47080 * commands. This ID is treated as opaque data by the firmware and
47081 * the value is returned in the `hwrm_resp_hdr` upon completion.
47085 * The target ID of the command:
47086 * * 0x0-0xFFF8 - The function ID
47087 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47088 * * 0xFFFD - Reserved for user-space HWRM interface
47091 uint16_t target_id;
47093 * A physical address pointer pointing to a host buffer that the
47094 * command's response data will be written. This can be either a host
47095 * physical address (HPA) or a guest physical address (GPA) and must
47096 * point to a physically contiguous block of memory.
47098 uint64_t resp_addr;
47099 /* ID of the statistics context that is being queried. */
47100 uint32_t stat_ctx_id;
47101 uint8_t unused_0[4];
47104 /* hwrm_stat_ctx_free_output (size:128b/16B) */
47105 struct hwrm_stat_ctx_free_output {
47106 /* The specific error status for the command. */
47107 uint16_t error_code;
47108 /* The HWRM command request type. */
47110 /* The sequence ID from the original command. */
47112 /* The length of the response data in number of bytes. */
47114 /* This is the statistics context ID value. */
47115 uint32_t stat_ctx_id;
47116 uint8_t unused_0[3];
47118 * This field is used in Output records to indicate that the output
47119 * is completely written to RAM. This field should be read as '1'
47120 * to indicate that the output has been completely written.
47121 * When writing a command completion or response to an internal processor,
47122 * the order of writes has to be such that this field is written last.
47127 /***********************
47128 * hwrm_stat_ctx_query *
47129 ***********************/
47132 /* hwrm_stat_ctx_query_input (size:192b/24B) */
47133 struct hwrm_stat_ctx_query_input {
47134 /* The HWRM command request type. */
47137 * The completion ring to send the completion event on. This should
47138 * be the NQ ID returned from the `nq_alloc` HWRM command.
47140 uint16_t cmpl_ring;
47142 * The sequence ID is used by the driver for tracking multiple
47143 * commands. This ID is treated as opaque data by the firmware and
47144 * the value is returned in the `hwrm_resp_hdr` upon completion.
47148 * The target ID of the command:
47149 * * 0x0-0xFFF8 - The function ID
47150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47151 * * 0xFFFD - Reserved for user-space HWRM interface
47154 uint16_t target_id;
47156 * A physical address pointer pointing to a host buffer that the
47157 * command's response data will be written. This can be either a host
47158 * physical address (HPA) or a guest physical address (GPA) and must
47159 * point to a physically contiguous block of memory.
47161 uint64_t resp_addr;
47162 /* ID of the statistics context that is being queried. */
47163 uint32_t stat_ctx_id;
47166 * This bit is set to 1 when request is for a counter mask,
47167 * representing the width of each of the stats counters, rather
47168 * than counters themselves.
47170 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
47171 uint8_t unused_0[3];
47174 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
47175 struct hwrm_stat_ctx_query_output {
47176 /* The specific error status for the command. */
47177 uint16_t error_code;
47178 /* The HWRM command request type. */
47180 /* The sequence ID from the original command. */
47182 /* The length of the response data in number of bytes. */
47184 /* Number of transmitted unicast packets */
47185 uint64_t tx_ucast_pkts;
47186 /* Number of transmitted multicast packets */
47187 uint64_t tx_mcast_pkts;
47188 /* Number of transmitted broadcast packets */
47189 uint64_t tx_bcast_pkts;
47190 /* Number of packets discarded in transmit path */
47191 uint64_t tx_discard_pkts;
47192 /* Number of packets in transmit path with error */
47193 uint64_t tx_error_pkts;
47194 /* Number of transmitted bytes for unicast traffic */
47195 uint64_t tx_ucast_bytes;
47196 /* Number of transmitted bytes for multicast traffic */
47197 uint64_t tx_mcast_bytes;
47198 /* Number of transmitted bytes for broadcast traffic */
47199 uint64_t tx_bcast_bytes;
47200 /* Number of received unicast packets */
47201 uint64_t rx_ucast_pkts;
47202 /* Number of received multicast packets */
47203 uint64_t rx_mcast_pkts;
47204 /* Number of received broadcast packets */
47205 uint64_t rx_bcast_pkts;
47206 /* Number of packets discarded in receive path */
47207 uint64_t rx_discard_pkts;
47208 /* Number of packets in receive path with errors */
47209 uint64_t rx_error_pkts;
47210 /* Number of received bytes for unicast traffic */
47211 uint64_t rx_ucast_bytes;
47212 /* Number of received bytes for multicast traffic */
47213 uint64_t rx_mcast_bytes;
47214 /* Number of received bytes for broadcast traffic */
47215 uint64_t rx_bcast_bytes;
47216 /* Number of aggregated unicast packets */
47217 uint64_t rx_agg_pkts;
47218 /* Number of aggregated unicast bytes */
47219 uint64_t rx_agg_bytes;
47220 /* Number of aggregation events */
47221 uint64_t rx_agg_events;
47222 /* Number of aborted aggregations */
47223 uint64_t rx_agg_aborts;
47224 uint8_t unused_0[7];
47226 * This field is used in Output records to indicate that the output
47227 * is completely written to RAM. This field should be read as '1'
47228 * to indicate that the output has been completely written.
47229 * When writing a command completion or response to an internal processor,
47230 * the order of writes has to be such that this field is written last.
47235 /***************************
47236 * hwrm_stat_ext_ctx_query *
47237 ***************************/
47240 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
47241 struct hwrm_stat_ext_ctx_query_input {
47242 /* The HWRM command request type. */
47245 * The completion ring to send the completion event on. This should
47246 * be the NQ ID returned from the `nq_alloc` HWRM command.
47248 uint16_t cmpl_ring;
47250 * The sequence ID is used by the driver for tracking multiple
47251 * commands. This ID is treated as opaque data by the firmware and
47252 * the value is returned in the `hwrm_resp_hdr` upon completion.
47256 * The target ID of the command:
47257 * * 0x0-0xFFF8 - The function ID
47258 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47259 * * 0xFFFD - Reserved for user-space HWRM interface
47262 uint16_t target_id;
47264 * A physical address pointer pointing to a host buffer that the
47265 * command's response data will be written. This can be either a host
47266 * physical address (HPA) or a guest physical address (GPA) and must
47267 * point to a physically contiguous block of memory.
47269 uint64_t resp_addr;
47270 /* ID of the extended statistics context that is being queried. */
47271 uint32_t stat_ctx_id;
47274 * This bit is set to 1 when request is for a counter mask,
47275 * representing the width of each of the stats counters, rather
47276 * than counters themselves.
47278 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
47280 uint8_t unused_0[3];
47283 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
47284 struct hwrm_stat_ext_ctx_query_output {
47285 /* The specific error status for the command. */
47286 uint16_t error_code;
47287 /* The HWRM command request type. */
47289 /* The sequence ID from the original command. */
47291 /* The length of the response data in number of bytes. */
47293 /* Number of received unicast packets */
47294 uint64_t rx_ucast_pkts;
47295 /* Number of received multicast packets */
47296 uint64_t rx_mcast_pkts;
47297 /* Number of received broadcast packets */
47298 uint64_t rx_bcast_pkts;
47299 /* Number of discarded packets on receive path */
47300 uint64_t rx_discard_pkts;
47301 /* Number of packets on receive path with error */
47302 uint64_t rx_error_pkts;
47303 /* Number of received bytes for unicast traffic */
47304 uint64_t rx_ucast_bytes;
47305 /* Number of received bytes for multicast traffic */
47306 uint64_t rx_mcast_bytes;
47307 /* Number of received bytes for broadcast traffic */
47308 uint64_t rx_bcast_bytes;
47309 /* Number of transmitted unicast packets */
47310 uint64_t tx_ucast_pkts;
47311 /* Number of transmitted multicast packets */
47312 uint64_t tx_mcast_pkts;
47313 /* Number of transmitted broadcast packets */
47314 uint64_t tx_bcast_pkts;
47315 /* Number of packets on transmit path with error */
47316 uint64_t tx_error_pkts;
47317 /* Number of discarded packets on transmit path */
47318 uint64_t tx_discard_pkts;
47319 /* Number of transmitted bytes for unicast traffic */
47320 uint64_t tx_ucast_bytes;
47321 /* Number of transmitted bytes for multicast traffic */
47322 uint64_t tx_mcast_bytes;
47323 /* Number of transmitted bytes for broadcast traffic */
47324 uint64_t tx_bcast_bytes;
47325 /* Number of TPA eligible packets */
47326 uint64_t rx_tpa_eligible_pkt;
47327 /* Number of TPA eligible bytes */
47328 uint64_t rx_tpa_eligible_bytes;
47329 /* Number of TPA packets */
47330 uint64_t rx_tpa_pkt;
47331 /* Number of TPA bytes */
47332 uint64_t rx_tpa_bytes;
47333 /* Number of TPA errors */
47334 uint64_t rx_tpa_errors;
47335 /* Number of TPA events */
47336 uint64_t rx_tpa_events;
47337 uint8_t unused_0[7];
47339 * This field is used in Output records to indicate that the output
47340 * is completely written to RAM. This field should be read as '1'
47341 * to indicate that the output has been completely written.
47342 * When writing a command completion or response to an internal processor,
47343 * the order of writes has to be such that this field is written last.
47348 /***************************
47349 * hwrm_stat_ctx_eng_query *
47350 ***************************/
47353 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
47354 struct hwrm_stat_ctx_eng_query_input {
47355 /* The HWRM command request type. */
47358 * The completion ring to send the completion event on. This should
47359 * be the NQ ID returned from the `nq_alloc` HWRM command.
47361 uint16_t cmpl_ring;
47363 * The sequence ID is used by the driver for tracking multiple
47364 * commands. This ID is treated as opaque data by the firmware and
47365 * the value is returned in the `hwrm_resp_hdr` upon completion.
47369 * The target ID of the command:
47370 * * 0x0-0xFFF8 - The function ID
47371 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47372 * * 0xFFFD - Reserved for user-space HWRM interface
47375 uint16_t target_id;
47377 * A physical address pointer pointing to a host buffer that the
47378 * command's response data will be written. This can be either a host
47379 * physical address (HPA) or a guest physical address (GPA) and must
47380 * point to a physically contiguous block of memory.
47382 uint64_t resp_addr;
47383 /* ID of the statistics context that is being queried. */
47384 uint32_t stat_ctx_id;
47385 uint8_t unused_0[4];
47388 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
47389 struct hwrm_stat_ctx_eng_query_output {
47390 /* The specific error status for the command. */
47391 uint16_t error_code;
47392 /* The HWRM command request type. */
47394 /* The sequence ID from the original command. */
47396 /* The length of the response data in number of bytes. */
47399 * Count of data bytes into the Engine.
47400 * This includes any user supplied prefix,
47401 * but does not include any predefined
47404 uint64_t eng_bytes_in;
47405 /* Count of data bytes out of the Engine. */
47406 uint64_t eng_bytes_out;
47408 * Count, in 4-byte (dword) units, of bytes
47409 * that are input as auxiliary data.
47410 * This includes the aux_cmd data.
47412 uint64_t aux_bytes_in;
47414 * Count, in 4-byte (dword) units, of bytes
47415 * that are output as auxiliary data.
47416 * This count is the buffer space for aux_data
47417 * output provided in the RQE, not the actual
47420 uint64_t aux_bytes_out;
47421 /* Count of number of commands executed. */
47424 * Count of number of error commands.
47425 * These are the commands with a
47426 * non-zero status value.
47428 uint64_t error_commands;
47430 * Compression/Encryption Engine usage,
47431 * the unit is count of clock cycles
47433 uint64_t cce_engine_usage;
47435 * De-Compression/De-cryption Engine usage,
47436 * the unit is count of clock cycles
47438 uint64_t cdd_engine_usage;
47439 uint8_t unused_0[7];
47441 * This field is used in Output records to indicate that the output
47442 * is completely written to RAM. This field should be read as '1'
47443 * to indicate that the output has been completely written.
47444 * When writing a command completion or response to an internal processor,
47445 * the order of writes has to be such that this field is written last.
47450 /***************************
47451 * hwrm_stat_ctx_clr_stats *
47452 ***************************/
47455 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
47456 struct hwrm_stat_ctx_clr_stats_input {
47457 /* The HWRM command request type. */
47460 * The completion ring to send the completion event on. This should
47461 * be the NQ ID returned from the `nq_alloc` HWRM command.
47463 uint16_t cmpl_ring;
47465 * The sequence ID is used by the driver for tracking multiple
47466 * commands. This ID is treated as opaque data by the firmware and
47467 * the value is returned in the `hwrm_resp_hdr` upon completion.
47471 * The target ID of the command:
47472 * * 0x0-0xFFF8 - The function ID
47473 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47474 * * 0xFFFD - Reserved for user-space HWRM interface
47477 uint16_t target_id;
47479 * A physical address pointer pointing to a host buffer that the
47480 * command's response data will be written. This can be either a host
47481 * physical address (HPA) or a guest physical address (GPA) and must
47482 * point to a physically contiguous block of memory.
47484 uint64_t resp_addr;
47485 /* ID of the statistics context that is being queried. */
47486 uint32_t stat_ctx_id;
47487 uint8_t unused_0[4];
47490 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
47491 struct hwrm_stat_ctx_clr_stats_output {
47492 /* The specific error status for the command. */
47493 uint16_t error_code;
47494 /* The HWRM command request type. */
47496 /* The sequence ID from the original command. */
47498 /* The length of the response data in number of bytes. */
47500 uint8_t unused_0[7];
47502 * This field is used in Output records to indicate that the output
47503 * is completely written to RAM. This field should be read as '1'
47504 * to indicate that the output has been completely written.
47505 * When writing a command completion or response to an internal processor,
47506 * the order of writes has to be such that this field is written last.
47511 /********************
47512 * hwrm_pcie_qstats *
47513 ********************/
47516 /* hwrm_pcie_qstats_input (size:256b/32B) */
47517 struct hwrm_pcie_qstats_input {
47518 /* The HWRM command request type. */
47521 * The completion ring to send the completion event on. This should
47522 * be the NQ ID returned from the `nq_alloc` HWRM command.
47524 uint16_t cmpl_ring;
47526 * The sequence ID is used by the driver for tracking multiple
47527 * commands. This ID is treated as opaque data by the firmware and
47528 * the value is returned in the `hwrm_resp_hdr` upon completion.
47532 * The target ID of the command:
47533 * * 0x0-0xFFF8 - The function ID
47534 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47535 * * 0xFFFD - Reserved for user-space HWRM interface
47538 uint16_t target_id;
47540 * A physical address pointer pointing to a host buffer that the
47541 * command's response data will be written. This can be either a host
47542 * physical address (HPA) or a guest physical address (GPA) and must
47543 * point to a physically contiguous block of memory.
47545 uint64_t resp_addr;
47547 * The size of PCIe statistics block in bytes.
47548 * Firmware will DMA the PCIe statistics to
47549 * the host with this field size in the response.
47551 uint16_t pcie_stat_size;
47552 uint8_t unused_0[6];
47554 * This is the host address where
47555 * PCIe statistics will be stored
47557 uint64_t pcie_stat_host_addr;
47560 /* hwrm_pcie_qstats_output (size:128b/16B) */
47561 struct hwrm_pcie_qstats_output {
47562 /* The specific error status for the command. */
47563 uint16_t error_code;
47564 /* The HWRM command request type. */
47566 /* The sequence ID from the original command. */
47568 /* The length of the response data in number of bytes. */
47570 /* The size of PCIe statistics block in bytes. */
47571 uint16_t pcie_stat_size;
47572 uint8_t unused_0[5];
47574 * This field is used in Output records to indicate that the output
47575 * is completely written to RAM. This field should be read as '1'
47576 * to indicate that the output has been completely written.
47577 * When writing a command completion or response to an internal processor,
47578 * the order of writes has to be such that this field is written last.
47583 /* PCIe Statistics Formats */
47584 /* pcie_ctx_hw_stats (size:768b/96B) */
47585 struct pcie_ctx_hw_stats {
47586 /* Number of physical layer receiver errors */
47587 uint64_t pcie_pl_signal_integrity;
47588 /* Number of DLLP CRC errors detected by Data Link Layer */
47589 uint64_t pcie_dl_signal_integrity;
47591 * Number of TLP LCRC and sequence number errors detected
47592 * by Data Link Layer
47594 uint64_t pcie_tl_signal_integrity;
47595 /* Number of times LTSSM entered Recovery state */
47596 uint64_t pcie_link_integrity;
47597 /* Report number of TLP bits that have been transmitted in Mbps */
47598 uint64_t pcie_tx_traffic_rate;
47599 /* Report number of TLP bits that have been received in Mbps */
47600 uint64_t pcie_rx_traffic_rate;
47601 /* Number of DLLP bytes that have been transmitted */
47602 uint64_t pcie_tx_dllp_statistics;
47603 /* Number of DLLP bytes that have been received */
47604 uint64_t pcie_rx_dllp_statistics;
47606 * Number of times spent in each phase of gen3
47609 uint64_t pcie_equalization_time;
47610 /* Records the last 16 transitions of the LTSSM */
47611 uint32_t pcie_ltssm_histogram[4];
47613 * Record the last 8 reasons on why LTSSM transitioned
47616 uint64_t pcie_recovery_histogram;
47619 /**********************
47620 * hwrm_exec_fwd_resp *
47621 **********************/
47624 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
47625 struct hwrm_exec_fwd_resp_input {
47626 /* The HWRM command request type. */
47629 * The completion ring to send the completion event on. This should
47630 * be the NQ ID returned from the `nq_alloc` HWRM command.
47632 uint16_t cmpl_ring;
47634 * The sequence ID is used by the driver for tracking multiple
47635 * commands. This ID is treated as opaque data by the firmware and
47636 * the value is returned in the `hwrm_resp_hdr` upon completion.
47640 * The target ID of the command:
47641 * * 0x0-0xFFF8 - The function ID
47642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47643 * * 0xFFFD - Reserved for user-space HWRM interface
47646 uint16_t target_id;
47648 * A physical address pointer pointing to a host buffer that the
47649 * command's response data will be written. This can be either a host
47650 * physical address (HPA) or a guest physical address (GPA) and must
47651 * point to a physically contiguous block of memory.
47653 uint64_t resp_addr;
47655 * This is an encapsulated request. This request should
47656 * be executed by the HWRM and the response should be
47657 * provided in the response buffer inside the encapsulated
47660 uint32_t encap_request[26];
47662 * This value indicates the target id of the response to
47663 * the encapsulated request.
47664 * 0x0 - 0xFFF8 - Used for function ids
47665 * 0xFFF8 - 0xFFFE - Reserved for internal processors
47668 uint16_t encap_resp_target_id;
47669 uint8_t unused_0[6];
47672 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
47673 struct hwrm_exec_fwd_resp_output {
47674 /* The specific error status for the command. */
47675 uint16_t error_code;
47676 /* The HWRM command request type. */
47678 /* The sequence ID from the original command. */
47680 /* The length of the response data in number of bytes. */
47682 uint8_t unused_0[7];
47684 * This field is used in Output records to indicate that the output
47685 * is completely written to RAM. This field should be read as '1'
47686 * to indicate that the output has been completely written.
47687 * When writing a command completion or response to an internal processor,
47688 * the order of writes has to be such that this field is written last.
47693 /************************
47694 * hwrm_reject_fwd_resp *
47695 ************************/
47698 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
47699 struct hwrm_reject_fwd_resp_input {
47700 /* The HWRM command request type. */
47703 * The completion ring to send the completion event on. This should
47704 * be the NQ ID returned from the `nq_alloc` HWRM command.
47706 uint16_t cmpl_ring;
47708 * The sequence ID is used by the driver for tracking multiple
47709 * commands. This ID is treated as opaque data by the firmware and
47710 * the value is returned in the `hwrm_resp_hdr` upon completion.
47714 * The target ID of the command:
47715 * * 0x0-0xFFF8 - The function ID
47716 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47717 * * 0xFFFD - Reserved for user-space HWRM interface
47720 uint16_t target_id;
47722 * A physical address pointer pointing to a host buffer that the
47723 * command's response data will be written. This can be either a host
47724 * physical address (HPA) or a guest physical address (GPA) and must
47725 * point to a physically contiguous block of memory.
47727 uint64_t resp_addr;
47729 * This is an encapsulated request. This request should
47730 * be rejected by the HWRM and the error response should be
47731 * provided in the response buffer inside the encapsulated
47734 uint32_t encap_request[26];
47736 * This value indicates the target id of the response to
47737 * the encapsulated request.
47738 * 0x0 - 0xFFF8 - Used for function ids
47739 * 0xFFF8 - 0xFFFE - Reserved for internal processors
47742 uint16_t encap_resp_target_id;
47743 uint8_t unused_0[6];
47746 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
47747 struct hwrm_reject_fwd_resp_output {
47748 /* The specific error status for the command. */
47749 uint16_t error_code;
47750 /* The HWRM command request type. */
47752 /* The sequence ID from the original command. */
47754 /* The length of the response data in number of bytes. */
47756 uint8_t unused_0[7];
47758 * This field is used in Output records to indicate that the output
47759 * is completely written to RAM. This field should be read as '1'
47760 * to indicate that the output has been completely written.
47761 * When writing a command completion or response to an internal processor,
47762 * the order of writes has to be such that this field is written last.
47772 /* hwrm_fwd_resp_input (size:1024b/128B) */
47773 struct hwrm_fwd_resp_input {
47774 /* The HWRM command request type. */
47777 * The completion ring to send the completion event on. This should
47778 * be the NQ ID returned from the `nq_alloc` HWRM command.
47780 uint16_t cmpl_ring;
47782 * The sequence ID is used by the driver for tracking multiple
47783 * commands. This ID is treated as opaque data by the firmware and
47784 * the value is returned in the `hwrm_resp_hdr` upon completion.
47788 * The target ID of the command:
47789 * * 0x0-0xFFF8 - The function ID
47790 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47791 * * 0xFFFD - Reserved for user-space HWRM interface
47794 uint16_t target_id;
47796 * A physical address pointer pointing to a host buffer that the
47797 * command's response data will be written. This can be either a host
47798 * physical address (HPA) or a guest physical address (GPA) and must
47799 * point to a physically contiguous block of memory.
47801 uint64_t resp_addr;
47803 * This value indicates the target id of the encapsulated
47805 * 0x0 - 0xFFF8 - Used for function ids
47806 * 0xFFF8 - 0xFFFE - Reserved for internal processors
47809 uint16_t encap_resp_target_id;
47811 * This value indicates the completion ring the encapsulated
47812 * response will be optionally completed on. If the value is
47813 * -1, then no CR completion shall be generated for the
47814 * encapsulated response. Any other value must be a
47815 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
47816 * is provided, then a CR completion shall be generated for
47817 * the encapsulated response.
47819 uint16_t encap_resp_cmpl_ring;
47820 /* This field indicates the length of encapsulated response. */
47821 uint16_t encap_resp_len;
47825 * This is the host address where the encapsulated response
47827 * This area must be 16B aligned and must be cleared to zero
47828 * before the original request is made.
47830 uint64_t encap_resp_addr;
47831 /* This is an encapsulated response. */
47832 uint32_t encap_resp[24];
47835 /* hwrm_fwd_resp_output (size:128b/16B) */
47836 struct hwrm_fwd_resp_output {
47837 /* The specific error status for the command. */
47838 uint16_t error_code;
47839 /* The HWRM command request type. */
47841 /* The sequence ID from the original command. */
47843 /* The length of the response data in number of bytes. */
47845 uint8_t unused_0[7];
47847 * This field is used in Output records to indicate that the output
47848 * is completely written to RAM. This field should be read as '1'
47849 * to indicate that the output has been completely written.
47850 * When writing a command completion or response to an internal processor,
47851 * the order of writes has to be such that this field is written last.
47856 /*****************************
47857 * hwrm_fwd_async_event_cmpl *
47858 *****************************/
47861 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
47862 struct hwrm_fwd_async_event_cmpl_input {
47863 /* The HWRM command request type. */
47866 * The completion ring to send the completion event on. This should
47867 * be the NQ ID returned from the `nq_alloc` HWRM command.
47869 uint16_t cmpl_ring;
47871 * The sequence ID is used by the driver for tracking multiple
47872 * commands. This ID is treated as opaque data by the firmware and
47873 * the value is returned in the `hwrm_resp_hdr` upon completion.
47877 * The target ID of the command:
47878 * * 0x0-0xFFF8 - The function ID
47879 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47880 * * 0xFFFD - Reserved for user-space HWRM interface
47883 uint16_t target_id;
47885 * A physical address pointer pointing to a host buffer that the
47886 * command's response data will be written. This can be either a host
47887 * physical address (HPA) or a guest physical address (GPA) and must
47888 * point to a physically contiguous block of memory.
47890 uint64_t resp_addr;
47892 * This value indicates the target id of the encapsulated
47893 * asynchronous event.
47894 * 0x0 - 0xFFF8 - Used for function ids
47895 * 0xFFF8 - 0xFFFE - Reserved for internal processors
47896 * 0xFFFF - Broadcast to all children VFs (only applicable when
47897 * a PF is the requester)
47899 uint16_t encap_async_event_target_id;
47900 uint8_t unused_0[6];
47901 /* This is an encapsulated asynchronous event completion. */
47902 uint32_t encap_async_event_cmpl[4];
47905 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
47906 struct hwrm_fwd_async_event_cmpl_output {
47907 /* The specific error status for the command. */
47908 uint16_t error_code;
47909 /* The HWRM command request type. */
47911 /* The sequence ID from the original command. */
47913 /* The length of the response data in number of bytes. */
47915 uint8_t unused_0[7];
47917 * This field is used in Output records to indicate that the output
47918 * is completely written to RAM. This field should be read as '1'
47919 * to indicate that the output has been completely written.
47920 * When writing a command completion or response to an internal processor,
47921 * the order of writes has to be such that this field is written last.
47926 /**************************
47927 * hwrm_nvm_raw_write_blk *
47928 **************************/
47931 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
47932 struct hwrm_nvm_raw_write_blk_input {
47933 /* The HWRM command request type. */
47936 * The completion ring to send the completion event on. This should
47937 * be the NQ ID returned from the `nq_alloc` HWRM command.
47939 uint16_t cmpl_ring;
47941 * The sequence ID is used by the driver for tracking multiple
47942 * commands. This ID is treated as opaque data by the firmware and
47943 * the value is returned in the `hwrm_resp_hdr` upon completion.
47947 * The target ID of the command:
47948 * * 0x0-0xFFF8 - The function ID
47949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47950 * * 0xFFFD - Reserved for user-space HWRM interface
47953 uint16_t target_id;
47955 * A physical address pointer pointing to a host buffer that the
47956 * command's response data will be written. This can be either a host
47957 * physical address (HPA) or a guest physical address (GPA) and must
47958 * point to a physically contiguous block of memory.
47960 uint64_t resp_addr;
47962 * 64-bit Host Source Address.
47963 * This is the location of the source data to be written.
47965 uint64_t host_src_addr;
47967 * 32-bit Destination Address.
47968 * This is the NVRAM byte-offset where the source data will be written to.
47970 uint32_t dest_addr;
47971 /* Length of data to be written, in bytes. */
47975 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
47976 struct hwrm_nvm_raw_write_blk_output {
47977 /* The specific error status for the command. */
47978 uint16_t error_code;
47979 /* The HWRM command request type. */
47981 /* The sequence ID from the original command. */
47983 /* The length of the response data in number of bytes. */
47985 uint8_t unused_0[7];
47987 * This field is used in Output records to indicate that the output
47988 * is completely written to RAM. This field should be read as '1'
47989 * to indicate that the output has been completely written.
47990 * When writing a command completion or response to an internal processor,
47991 * the order of writes has to be such that this field is written last.
48001 /* hwrm_nvm_read_input (size:320b/40B) */
48002 struct hwrm_nvm_read_input {
48003 /* The HWRM command request type. */
48006 * The completion ring to send the completion event on. This should
48007 * be the NQ ID returned from the `nq_alloc` HWRM command.
48009 uint16_t cmpl_ring;
48011 * The sequence ID is used by the driver for tracking multiple
48012 * commands. This ID is treated as opaque data by the firmware and
48013 * the value is returned in the `hwrm_resp_hdr` upon completion.
48017 * The target ID of the command:
48018 * * 0x0-0xFFF8 - The function ID
48019 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48020 * * 0xFFFD - Reserved for user-space HWRM interface
48023 uint16_t target_id;
48025 * A physical address pointer pointing to a host buffer that the
48026 * command's response data will be written. This can be either a host
48027 * physical address (HPA) or a guest physical address (GPA) and must
48028 * point to a physically contiguous block of memory.
48030 uint64_t resp_addr;
48032 * 64-bit Host Destination Address.
48033 * This is the host address where the data will be written to.
48035 uint64_t host_dest_addr;
48036 /* The 0-based index of the directory entry. */
48038 uint8_t unused_0[2];
48039 /* The NVRAM byte-offset to read from. */
48041 /* The length of the data to be read, in bytes. */
48043 uint8_t unused_1[4];
48046 /* hwrm_nvm_read_output (size:128b/16B) */
48047 struct hwrm_nvm_read_output {
48048 /* The specific error status for the command. */
48049 uint16_t error_code;
48050 /* The HWRM command request type. */
48052 /* The sequence ID from the original command. */
48054 /* The length of the response data in number of bytes. */
48056 uint8_t unused_0[7];
48058 * This field is used in Output records to indicate that the output
48059 * is completely written to RAM. This field should be read as '1'
48060 * to indicate that the output has been completely written.
48061 * When writing a command completion or response to an internal processor,
48062 * the order of writes has to be such that this field is written last.
48067 /*********************
48068 * hwrm_nvm_raw_dump *
48069 *********************/
48072 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
48073 struct hwrm_nvm_raw_dump_input {
48074 /* The HWRM command request type. */
48077 * The completion ring to send the completion event on. This should
48078 * be the NQ ID returned from the `nq_alloc` HWRM command.
48080 uint16_t cmpl_ring;
48082 * The sequence ID is used by the driver for tracking multiple
48083 * commands. This ID is treated as opaque data by the firmware and
48084 * the value is returned in the `hwrm_resp_hdr` upon completion.
48088 * The target ID of the command:
48089 * * 0x0-0xFFF8 - The function ID
48090 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48091 * * 0xFFFD - Reserved for user-space HWRM interface
48094 uint16_t target_id;
48096 * A physical address pointer pointing to a host buffer that the
48097 * command's response data will be written. This can be either a host
48098 * physical address (HPA) or a guest physical address (GPA) and must
48099 * point to a physically contiguous block of memory.
48101 uint64_t resp_addr;
48103 * 64-bit Host Destination Address.
48104 * This is the host address where the data will be written to.
48106 uint64_t host_dest_addr;
48107 /* 32-bit NVRAM byte-offset to read from. */
48109 /* Total length of NVRAM contents to be read, in bytes. */
48113 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
48114 struct hwrm_nvm_raw_dump_output {
48115 /* The specific error status for the command. */
48116 uint16_t error_code;
48117 /* The HWRM command request type. */
48119 /* The sequence ID from the original command. */
48121 /* The length of the response data in number of bytes. */
48123 uint8_t unused_0[7];
48125 * This field is used in Output records to indicate that the output
48126 * is completely written to RAM. This field should be read as '1'
48127 * to indicate that the output has been completely written.
48128 * When writing a command completion or response to an internal processor,
48129 * the order of writes has to be such that this field is written last.
48134 /****************************
48135 * hwrm_nvm_get_dir_entries *
48136 ****************************/
48139 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
48140 struct hwrm_nvm_get_dir_entries_input {
48141 /* The HWRM command request type. */
48144 * The completion ring to send the completion event on. This should
48145 * be the NQ ID returned from the `nq_alloc` HWRM command.
48147 uint16_t cmpl_ring;
48149 * The sequence ID is used by the driver for tracking multiple
48150 * commands. This ID is treated as opaque data by the firmware and
48151 * the value is returned in the `hwrm_resp_hdr` upon completion.
48155 * The target ID of the command:
48156 * * 0x0-0xFFF8 - The function ID
48157 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48158 * * 0xFFFD - Reserved for user-space HWRM interface
48161 uint16_t target_id;
48163 * A physical address pointer pointing to a host buffer that the
48164 * command's response data will be written. This can be either a host
48165 * physical address (HPA) or a guest physical address (GPA) and must
48166 * point to a physically contiguous block of memory.
48168 uint64_t resp_addr;
48170 * 64-bit Host Destination Address.
48171 * This is the host address where the directory will be written.
48173 uint64_t host_dest_addr;
48176 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
48177 struct hwrm_nvm_get_dir_entries_output {
48178 /* The specific error status for the command. */
48179 uint16_t error_code;
48180 /* The HWRM command request type. */
48182 /* The sequence ID from the original command. */
48184 /* The length of the response data in number of bytes. */
48186 uint8_t unused_0[7];
48188 * This field is used in Output records to indicate that the output
48189 * is completely written to RAM. This field should be read as '1'
48190 * to indicate that the output has been completely written.
48191 * When writing a command completion or response to an internal processor,
48192 * the order of writes has to be such that this field is written last.
48197 /*************************
48198 * hwrm_nvm_get_dir_info *
48199 *************************/
48202 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
48203 struct hwrm_nvm_get_dir_info_input {
48204 /* The HWRM command request type. */
48207 * The completion ring to send the completion event on. This should
48208 * be the NQ ID returned from the `nq_alloc` HWRM command.
48210 uint16_t cmpl_ring;
48212 * The sequence ID is used by the driver for tracking multiple
48213 * commands. This ID is treated as opaque data by the firmware and
48214 * the value is returned in the `hwrm_resp_hdr` upon completion.
48218 * The target ID of the command:
48219 * * 0x0-0xFFF8 - The function ID
48220 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48221 * * 0xFFFD - Reserved for user-space HWRM interface
48224 uint16_t target_id;
48226 * A physical address pointer pointing to a host buffer that the
48227 * command's response data will be written. This can be either a host
48228 * physical address (HPA) or a guest physical address (GPA) and must
48229 * point to a physically contiguous block of memory.
48231 uint64_t resp_addr;
48234 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
48235 struct hwrm_nvm_get_dir_info_output {
48236 /* The specific error status for the command. */
48237 uint16_t error_code;
48238 /* The HWRM command request type. */
48240 /* The sequence ID from the original command. */
48242 /* The length of the response data in number of bytes. */
48244 /* Number of directory entries in the directory. */
48246 /* Size of each directory entry, in bytes. */
48247 uint32_t entry_length;
48248 uint8_t unused_0[7];
48250 * This field is used in Output records to indicate that the output
48251 * is completely written to RAM. This field should be read as '1'
48252 * to indicate that the output has been completely written.
48253 * When writing a command completion or response to an internal processor,
48254 * the order of writes has to be such that this field is written last.
48259 /******************
48261 ******************/
48264 /* hwrm_nvm_write_input (size:384b/48B) */
48265 struct hwrm_nvm_write_input {
48266 /* The HWRM command request type. */
48269 * The completion ring to send the completion event on. This should
48270 * be the NQ ID returned from the `nq_alloc` HWRM command.
48272 uint16_t cmpl_ring;
48274 * The sequence ID is used by the driver for tracking multiple
48275 * commands. This ID is treated as opaque data by the firmware and
48276 * the value is returned in the `hwrm_resp_hdr` upon completion.
48280 * The target ID of the command:
48281 * * 0x0-0xFFF8 - The function ID
48282 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48283 * * 0xFFFD - Reserved for user-space HWRM interface
48286 uint16_t target_id;
48288 * A physical address pointer pointing to a host buffer that the
48289 * command's response data will be written. This can be either a host
48290 * physical address (HPA) or a guest physical address (GPA) and must
48291 * point to a physically contiguous block of memory.
48293 uint64_t resp_addr;
48295 * 64-bit Host Source Address.
48296 * This is where the source data is.
48298 uint64_t host_src_addr;
48300 * The Directory Entry Type (valid values are defined in the
48301 * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
48305 * Directory ordinal.
48306 * The 0-based instance of the combined Directory Entry Type and Extension.
48308 uint16_t dir_ordinal;
48309 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
48311 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
48314 * Length of data to write, in bytes.May be
48315 * less than or equal to the allocated size for the directory entry.
48316 * The data length stored in the directory entry will be updated to
48317 * reflect this value once the write is complete.
48319 uint32_t dir_data_length;
48324 * When this bit is '1', the original active image
48325 * will not be removed. TBD: what purpose is this?
48327 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
48330 * The requested length of the allocated NVM for the item, in bytes.
48331 * This value may be greater than or equal to the specified data length (dir_data_length).
48332 * If this value is less than the specified data length, it will be ignored.
48333 * The response will contain the actual allocated item length, which may
48334 * be greater than the requested item length.
48335 * The purpose for allocating more than the required number of bytes for
48336 * an item's data is to pre-allocate extra storage (padding) to accommodate
48337 * the potential future growth of an item (e.g. upgraded firmware with
48338 * a size increase, log growth, expanded configuration data).
48340 uint32_t dir_item_length;
48344 /* hwrm_nvm_write_output (size:128b/16B) */
48345 struct hwrm_nvm_write_output {
48346 /* The specific error status for the command. */
48347 uint16_t error_code;
48348 /* The HWRM command request type. */
48350 /* The sequence ID from the original command. */
48352 /* The length of the response data in number of bytes. */
48355 * Length of the allocated NVM for the item, in bytes. The value may be
48356 * greater than or equal to the specified data length or the requested item length.
48357 * The actual item length used when creating a new directory entry will
48358 * be a multiple of an NVM block size.
48360 uint32_t dir_item_length;
48361 /* The directory index of the created or modified item. */
48365 * This field is used in Output records to indicate that the output
48366 * is completely written to RAM. This field should be read as '1'
48367 * to indicate that the output has been completely written.
48368 * When writing a command completion or response to an internal processor,
48369 * the order of writes has to be such that this field is written last.
48374 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
48375 struct hwrm_nvm_write_cmd_err {
48377 * command specific error codes that goes to
48378 * the cmd_err field in Common HWRM Error Response.
48381 /* Unknown error */
48382 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48383 /* Unable to complete operation due to fragmentation */
48384 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
48385 /* nvm is completely full. */
48386 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
48387 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
48388 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
48389 uint8_t unused_0[7];
48392 /*******************
48393 * hwrm_nvm_modify *
48394 *******************/
48397 /* hwrm_nvm_modify_input (size:320b/40B) */
48398 struct hwrm_nvm_modify_input {
48399 /* The HWRM command request type. */
48402 * The completion ring to send the completion event on. This should
48403 * be the NQ ID returned from the `nq_alloc` HWRM command.
48405 uint16_t cmpl_ring;
48407 * The sequence ID is used by the driver for tracking multiple
48408 * commands. This ID is treated as opaque data by the firmware and
48409 * the value is returned in the `hwrm_resp_hdr` upon completion.
48413 * The target ID of the command:
48414 * * 0x0-0xFFF8 - The function ID
48415 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48416 * * 0xFFFD - Reserved for user-space HWRM interface
48419 uint16_t target_id;
48421 * A physical address pointer pointing to a host buffer that the
48422 * command's response data will be written. This can be either a host
48423 * physical address (HPA) or a guest physical address (GPA) and must
48424 * point to a physically contiguous block of memory.
48426 uint64_t resp_addr;
48428 * 64-bit Host Source Address.
48429 * This is where the modified data is.
48431 uint64_t host_src_addr;
48432 /* 16-bit directory entry index. */
48436 * This flag indicates the sender wants to modify a continuous NVRAM
48437 * area using a batch of this HWRM requests. The offset of a request
48438 * must be continuous to the end of previous request's. Firmware does
48439 * not update the directory entry until receiving the last request,
48440 * which is indicated by the batch_last flag.
48441 * This flag is set usually when a sender does not have a block of
48442 * memory that is big enough to hold the entire NVRAM data for send
48445 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
48447 * This flag can be used only when the batch_mode flag is set.
48448 * It indicates this request is the last of batch requests.
48450 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
48451 /* 32-bit NVRAM byte-offset to modify content from. */
48454 * Length of data to be modified, in bytes. The length shall
48458 uint8_t unused_1[4];
48461 /* hwrm_nvm_modify_output (size:128b/16B) */
48462 struct hwrm_nvm_modify_output {
48463 /* The specific error status for the command. */
48464 uint16_t error_code;
48465 /* The HWRM command request type. */
48467 /* The sequence ID from the original command. */
48469 /* The length of the response data in number of bytes. */
48471 uint8_t unused_0[7];
48473 * This field is used in Output records to indicate that the output
48474 * is completely written to RAM. This field should be read as '1'
48475 * to indicate that the output has been completely written.
48476 * When writing a command completion or response to an internal processor,
48477 * the order of writes has to be such that this field is written last.
48482 /***************************
48483 * hwrm_nvm_find_dir_entry *
48484 ***************************/
48487 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
48488 struct hwrm_nvm_find_dir_entry_input {
48489 /* The HWRM command request type. */
48492 * The completion ring to send the completion event on. This should
48493 * be the NQ ID returned from the `nq_alloc` HWRM command.
48495 uint16_t cmpl_ring;
48497 * The sequence ID is used by the driver for tracking multiple
48498 * commands. This ID is treated as opaque data by the firmware and
48499 * the value is returned in the `hwrm_resp_hdr` upon completion.
48503 * The target ID of the command:
48504 * * 0x0-0xFFF8 - The function ID
48505 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48506 * * 0xFFFD - Reserved for user-space HWRM interface
48509 uint16_t target_id;
48511 * A physical address pointer pointing to a host buffer that the
48512 * command's response data will be written. This can be either a host
48513 * physical address (HPA) or a guest physical address (GPA) and must
48514 * point to a physically contiguous block of memory.
48516 uint64_t resp_addr;
48519 * This bit must be '1' for the dir_idx_valid field to be
48522 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
48524 /* Directory Entry Index */
48526 /* Directory Entry (Image) Type */
48529 * Directory ordinal.
48530 * The instance of this Directory Type
48532 uint16_t dir_ordinal;
48533 /* The Directory Entry Extension flags. */
48535 /* This value indicates the search option using dir_ordinal. */
48536 uint8_t opt_ordinal;
48537 /* This value indicates the search option using dir_ordinal. */
48538 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
48539 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
48540 /* Equal to specified ordinal value. */
48541 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
48542 /* Greater than or equal to specified ordinal value */
48543 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
48544 /* Greater than specified ordinal value */
48545 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
48546 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
48547 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
48548 uint8_t unused_0[3];
48551 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
48552 struct hwrm_nvm_find_dir_entry_output {
48553 /* The specific error status for the command. */
48554 uint16_t error_code;
48555 /* The HWRM command request type. */
48557 /* The sequence ID from the original command. */
48559 /* The length of the response data in number of bytes. */
48561 /* Allocated NVRAM for this directory entry, in bytes. */
48562 uint32_t dir_item_length;
48563 /* Size of the stored data for this directory entry, in bytes. */
48564 uint32_t dir_data_length;
48566 * Firmware version.
48567 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
48570 /* Directory ordinal. */
48571 uint16_t dir_ordinal;
48572 /* Directory Entry Index */
48574 uint8_t unused_0[7];
48576 * This field is used in Output records to indicate that the output
48577 * is completely written to RAM. This field should be read as '1'
48578 * to indicate that the output has been completely written.
48579 * When writing a command completion or response to an internal processor,
48580 * the order of writes has to be such that this field is written last.
48585 /****************************
48586 * hwrm_nvm_erase_dir_entry *
48587 ****************************/
48590 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
48591 struct hwrm_nvm_erase_dir_entry_input {
48592 /* The HWRM command request type. */
48595 * The completion ring to send the completion event on. This should
48596 * be the NQ ID returned from the `nq_alloc` HWRM command.
48598 uint16_t cmpl_ring;
48600 * The sequence ID is used by the driver for tracking multiple
48601 * commands. This ID is treated as opaque data by the firmware and
48602 * the value is returned in the `hwrm_resp_hdr` upon completion.
48606 * The target ID of the command:
48607 * * 0x0-0xFFF8 - The function ID
48608 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48609 * * 0xFFFD - Reserved for user-space HWRM interface
48612 uint16_t target_id;
48614 * A physical address pointer pointing to a host buffer that the
48615 * command's response data will be written. This can be either a host
48616 * physical address (HPA) or a guest physical address (GPA) and must
48617 * point to a physically contiguous block of memory.
48619 uint64_t resp_addr;
48620 /* Directory Entry Index */
48622 uint8_t unused_0[6];
48625 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
48626 struct hwrm_nvm_erase_dir_entry_output {
48627 /* The specific error status for the command. */
48628 uint16_t error_code;
48629 /* The HWRM command request type. */
48631 /* The sequence ID from the original command. */
48633 /* The length of the response data in number of bytes. */
48635 uint8_t unused_0[7];
48637 * This field is used in Output records to indicate that the output
48638 * is completely written to RAM. This field should be read as '1'
48639 * to indicate that the output has been completely written.
48640 * When writing a command completion or response to an internal processor,
48641 * the order of writes has to be such that this field is written last.
48646 /*************************
48647 * hwrm_nvm_get_dev_info *
48648 *************************/
48651 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
48652 struct hwrm_nvm_get_dev_info_input {
48653 /* The HWRM command request type. */
48656 * The completion ring to send the completion event on. This should
48657 * be the NQ ID returned from the `nq_alloc` HWRM command.
48659 uint16_t cmpl_ring;
48661 * The sequence ID is used by the driver for tracking multiple
48662 * commands. This ID is treated as opaque data by the firmware and
48663 * the value is returned in the `hwrm_resp_hdr` upon completion.
48667 * The target ID of the command:
48668 * * 0x0-0xFFF8 - The function ID
48669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48670 * * 0xFFFD - Reserved for user-space HWRM interface
48673 uint16_t target_id;
48675 * A physical address pointer pointing to a host buffer that the
48676 * command's response data will be written. This can be either a host
48677 * physical address (HPA) or a guest physical address (GPA) and must
48678 * point to a physically contiguous block of memory.
48680 uint64_t resp_addr;
48683 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
48684 struct hwrm_nvm_get_dev_info_output {
48685 /* The specific error status for the command. */
48686 uint16_t error_code;
48687 /* The HWRM command request type. */
48689 /* The sequence ID from the original command. */
48691 /* The length of the response data in number of bytes. */
48693 /* Manufacturer ID. */
48694 uint16_t manufacturer_id;
48696 uint16_t device_id;
48697 /* Sector size of the NVRAM device. */
48698 uint32_t sector_size;
48699 /* Total size, in bytes of the NVRAM device. */
48700 uint32_t nvram_size;
48701 uint32_t reserved_size;
48703 * Available size that can be used, in bytes. Available size is the
48704 * NVRAM size take away the used size and reserved size.
48706 uint32_t available_size;
48707 /* This field represents the major version of NVM cfg */
48708 uint8_t nvm_cfg_ver_maj;
48709 /* This field represents the minor version of NVM cfg */
48710 uint8_t nvm_cfg_ver_min;
48711 /* This field represents the update version of NVM cfg */
48712 uint8_t nvm_cfg_ver_upd;
48715 * If set to 1, firmware will provide various firmware version
48716 * information stored in the flash.
48718 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
48721 * This field represents the board package name stored in the flash.
48722 * (ASCII chars with NULL at the end).
48726 * This field represents the major version of HWRM firmware, stored in
48729 uint16_t hwrm_fw_major;
48731 * This field represents the minor version of HWRM firmware, stored in
48734 uint16_t hwrm_fw_minor;
48736 * This field represents the build version of HWRM firmware, stored in
48739 uint16_t hwrm_fw_build;
48741 * This field can be used to represent firmware branches or customer
48742 * specific releases tied to a specific (major, minor, build) version
48743 * of the HWRM firmware.
48745 uint16_t hwrm_fw_patch;
48747 * This field represents the major version of mgmt firmware, stored in
48750 uint16_t mgmt_fw_major;
48752 * This field represents the minor version of mgmt firmware, stored in
48755 uint16_t mgmt_fw_minor;
48757 * This field represents the build version of mgmt firmware, stored in
48760 uint16_t mgmt_fw_build;
48762 * This field can be used to represent firmware branches or customer
48763 * specific releases tied to a specific (major, minor, build) version
48764 * of the mgmt firmware.
48766 uint16_t mgmt_fw_patch;
48768 * This field represents the major version of roce firmware, stored in
48771 uint16_t roce_fw_major;
48773 * This field represents the minor version of roce firmware, stored in
48776 uint16_t roce_fw_minor;
48778 * This field represents the build version of roce firmware, stored in
48781 uint16_t roce_fw_build;
48783 * This field can be used to represent firmware branches or customer
48784 * specific releases tied to a specific (major, minor, build) version
48785 * of the roce firmware.
48787 uint16_t roce_fw_patch;
48788 uint8_t unused_0[7];
48790 * This field is used in Output records to indicate that the output
48791 * is completely written to RAM. This field should be read as '1'
48792 * to indicate that the output has been completely written.
48793 * When writing a command completion or response to an internal processor,
48794 * the order of writes has to be such that this field is written last.
48799 /**************************
48800 * hwrm_nvm_mod_dir_entry *
48801 **************************/
48804 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
48805 struct hwrm_nvm_mod_dir_entry_input {
48806 /* The HWRM command request type. */
48809 * The completion ring to send the completion event on. This should
48810 * be the NQ ID returned from the `nq_alloc` HWRM command.
48812 uint16_t cmpl_ring;
48814 * The sequence ID is used by the driver for tracking multiple
48815 * commands. This ID is treated as opaque data by the firmware and
48816 * the value is returned in the `hwrm_resp_hdr` upon completion.
48820 * The target ID of the command:
48821 * * 0x0-0xFFF8 - The function ID
48822 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48823 * * 0xFFFD - Reserved for user-space HWRM interface
48826 uint16_t target_id;
48828 * A physical address pointer pointing to a host buffer that the
48829 * command's response data will be written. This can be either a host
48830 * physical address (HPA) or a guest physical address (GPA) and must
48831 * point to a physically contiguous block of memory.
48833 uint64_t resp_addr;
48836 * This bit must be '1' for the checksum field to be
48839 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
48840 /* Directory Entry Index */
48843 * Directory ordinal.
48844 * The (0-based) instance of this Directory Type.
48846 uint16_t dir_ordinal;
48848 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
48849 * extension flag definitions).
48852 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
48855 * If valid, then this field updates the checksum
48856 * value of the content in the directory entry.
48861 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
48862 struct hwrm_nvm_mod_dir_entry_output {
48863 /* The specific error status for the command. */
48864 uint16_t error_code;
48865 /* The HWRM command request type. */
48867 /* The sequence ID from the original command. */
48869 /* The length of the response data in number of bytes. */
48871 uint8_t unused_0[7];
48873 * This field is used in Output records to indicate that the output
48874 * is completely written to RAM. This field should be read as '1'
48875 * to indicate that the output has been completely written.
48876 * When writing a command completion or response to an internal processor,
48877 * the order of writes has to be such that this field is written last.
48882 /**************************
48883 * hwrm_nvm_verify_update *
48884 **************************/
48887 /* hwrm_nvm_verify_update_input (size:192b/24B) */
48888 struct hwrm_nvm_verify_update_input {
48889 /* The HWRM command request type. */
48892 * The completion ring to send the completion event on. This should
48893 * be the NQ ID returned from the `nq_alloc` HWRM command.
48895 uint16_t cmpl_ring;
48897 * The sequence ID is used by the driver for tracking multiple
48898 * commands. This ID is treated as opaque data by the firmware and
48899 * the value is returned in the `hwrm_resp_hdr` upon completion.
48903 * The target ID of the command:
48904 * * 0x0-0xFFF8 - The function ID
48905 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48906 * * 0xFFFD - Reserved for user-space HWRM interface
48909 uint16_t target_id;
48911 * A physical address pointer pointing to a host buffer that the
48912 * command's response data will be written. This can be either a host
48913 * physical address (HPA) or a guest physical address (GPA) and must
48914 * point to a physically contiguous block of memory.
48916 uint64_t resp_addr;
48917 /* Directory Entry Type, to be verified. */
48920 * Directory ordinal.
48921 * The instance of the Directory Type to be verified.
48923 uint16_t dir_ordinal;
48925 * The Directory Entry Extension flags.
48926 * The "UPDATE" extension flag must be set in this value.
48927 * A corresponding directory entry with the same type and ordinal values but *without*
48928 * the "UPDATE" extension flag must also exist. The other flags of the extension must
48929 * be identical between the active and update entries.
48932 uint8_t unused_0[2];
48935 /* hwrm_nvm_verify_update_output (size:128b/16B) */
48936 struct hwrm_nvm_verify_update_output {
48937 /* The specific error status for the command. */
48938 uint16_t error_code;
48939 /* The HWRM command request type. */
48941 /* The sequence ID from the original command. */
48943 /* The length of the response data in number of bytes. */
48945 uint8_t unused_0[7];
48947 * This field is used in Output records to indicate that the output
48948 * is completely written to RAM. This field should be read as '1'
48949 * to indicate that the output has been completely written.
48950 * When writing a command completion or response to an internal processor,
48951 * the order of writes has to be such that this field is written last.
48956 /***************************
48957 * hwrm_nvm_install_update *
48958 ***************************/
48961 /* hwrm_nvm_install_update_input (size:192b/24B) */
48962 struct hwrm_nvm_install_update_input {
48963 /* The HWRM command request type. */
48966 * The completion ring to send the completion event on. This should
48967 * be the NQ ID returned from the `nq_alloc` HWRM command.
48969 uint16_t cmpl_ring;
48971 * The sequence ID is used by the driver for tracking multiple
48972 * commands. This ID is treated as opaque data by the firmware and
48973 * the value is returned in the `hwrm_resp_hdr` upon completion.
48977 * The target ID of the command:
48978 * * 0x0-0xFFF8 - The function ID
48979 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48980 * * 0xFFFD - Reserved for user-space HWRM interface
48983 uint16_t target_id;
48985 * A physical address pointer pointing to a host buffer that the
48986 * command's response data will be written. This can be either a host
48987 * physical address (HPA) or a guest physical address (GPA) and must
48988 * point to a physically contiguous block of memory.
48990 uint64_t resp_addr;
48992 * Installation type. If the value 3 through 0xffff is used,
48993 * only packaged items with that type value will be installed and
48994 * conditional installation directives for those packaged items
48995 * will be over-ridden (i.e. 'create' or 'replace' will be treated
48998 uint32_t install_type;
49000 * Perform a normal package installation. Conditional installation
49001 * directives (e.g. 'create' and 'replace') of packaged items
49002 * will be followed.
49004 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
49006 * Install all packaged items regardless of installation directive
49007 * (i.e. treat all packaged items as though they have an installation
49008 * directive of 'install').
49010 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
49011 UINT32_C(0xffffffff)
49012 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
49013 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
49015 /* If set to 1, then securely erase all unused locations in persistent storage. */
49016 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
49019 * If set to 1, then unspecified images, images not in the package file,
49020 * will be safely deleted.
49021 * When combined with erase_unused_space then unspecified images will be
49024 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
49027 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
49028 * Allow additional time for this command to complete if this bit is set to 1.
49030 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
49033 * If set to 1, FW will verify the package in the "UPDATE" NVM item
49034 * without installing it. This flag is for FW internal use only.
49035 * Users should not set this flag. The request will otherwise fail.
49037 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
49039 uint8_t unused_0[2];
49042 /* hwrm_nvm_install_update_output (size:192b/24B) */
49043 struct hwrm_nvm_install_update_output {
49044 /* The specific error status for the command. */
49045 uint16_t error_code;
49046 /* The HWRM command request type. */
49048 /* The sequence ID from the original command. */
49050 /* The length of the response data in number of bytes. */
49053 * Bit-mask of successfully installed items.
49054 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
49055 * A value of 0 indicates that no items were successfully installed.
49057 uint64_t installed_items;
49058 /* result is 8 b */
49060 /* There was no problem with the package installation. */
49061 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
49062 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
49063 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
49064 /* problem_item is 8 b */
49065 uint8_t problem_item;
49066 /* There was no problem with any packaged items. */
49067 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
49069 /* There was a problem with the NVM package itself. */
49070 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
49072 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
49073 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
49074 /* reset_required is 8 b */
49075 uint8_t reset_required;
49077 * No reset is required for installed/updated firmware or
49078 * microcode to take effect.
49080 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
49083 * A PCIe reset (e.g. system reboot) is
49084 * required for newly installed/updated firmware or
49085 * microcode to take effect.
49087 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
49090 * A controller power reset (e.g. system power-cycle) is
49091 * required for newly installed/updated firmware or
49092 * microcode to take effect. Some newly installed/updated
49093 * firmware or microcode may still take effect upon the
49096 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
49098 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
49099 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
49100 uint8_t unused_0[4];
49102 * This field is used in Output records to indicate that the output
49103 * is completely written to RAM. This field should be read as '1'
49104 * to indicate that the output has been completely written.
49105 * When writing a command completion or response to an internal processor,
49106 * the order of writes has to be such that this field is written last.
49111 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
49112 struct hwrm_nvm_install_update_cmd_err {
49114 * command specific error codes that goes to
49115 * the cmd_err field in Common HWRM Error Response.
49118 /* Unknown error */
49119 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
49120 /* Unable to complete operation due to fragmentation */
49121 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
49122 /* nvm is completely full. */
49123 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
49124 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
49125 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
49126 uint8_t unused_0[7];
49129 /******************
49131 ******************/
49134 /* hwrm_nvm_flush_input (size:128b/16B) */
49135 struct hwrm_nvm_flush_input {
49136 /* The HWRM command request type. */
49139 * The completion ring to send the completion event on. This should
49140 * be the NQ ID returned from the `nq_alloc` HWRM command.
49142 uint16_t cmpl_ring;
49144 * The sequence ID is used by the driver for tracking multiple
49145 * commands. This ID is treated as opaque data by the firmware and
49146 * the value is returned in the `hwrm_resp_hdr` upon completion.
49150 * The target ID of the command:
49151 * * 0x0-0xFFF8 - The function ID
49152 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49153 * * 0xFFFD - Reserved for user-space HWRM interface
49156 uint16_t target_id;
49158 * A physical address pointer pointing to a host buffer that the
49159 * command's response data will be written. This can be either a host
49160 * physical address (HPA) or a guest physical address (GPA) and must
49161 * point to a physically contiguous block of memory.
49163 uint64_t resp_addr;
49166 /* hwrm_nvm_flush_output (size:128b/16B) */
49167 struct hwrm_nvm_flush_output {
49168 /* The specific error status for the command. */
49169 uint16_t error_code;
49170 /* The HWRM command request type. */
49172 /* The sequence ID from the original command. */
49174 /* The length of the response data in number of bytes. */
49176 uint8_t unused_0[7];
49178 * This field is used in Output records to indicate that the output
49179 * is completely written to RAM. This field should be read as '1'
49180 * to indicate that the output has been completely written.
49181 * When writing a command completion or response to an internal processor,
49182 * the order of writes has to be such that this field is written last.
49187 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
49188 struct hwrm_nvm_flush_cmd_err {
49190 * command specific error codes that goes to
49191 * the cmd_err field in Common HWRM Error Response.
49194 /* Unknown error */
49195 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
49196 /* flush could not be performed */
49197 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
49198 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
49199 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
49200 uint8_t unused_0[7];
49203 /*************************
49204 * hwrm_nvm_get_variable *
49205 *************************/
49208 /* hwrm_nvm_get_variable_input (size:320b/40B) */
49209 struct hwrm_nvm_get_variable_input {
49210 /* The HWRM command request type. */
49213 * The completion ring to send the completion event on. This should
49214 * be the NQ ID returned from the `nq_alloc` HWRM command.
49216 uint16_t cmpl_ring;
49218 * The sequence ID is used by the driver for tracking multiple
49219 * commands. This ID is treated as opaque data by the firmware and
49220 * the value is returned in the `hwrm_resp_hdr` upon completion.
49224 * The target ID of the command:
49225 * * 0x0-0xFFF8 - The function ID
49226 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49227 * * 0xFFFD - Reserved for user-space HWRM interface
49230 uint16_t target_id;
49232 * A physical address pointer pointing to a host buffer that the
49233 * command's response data will be written. This can be either a host
49234 * physical address (HPA) or a guest physical address (GPA) and must
49235 * point to a physically contiguous block of memory.
49237 uint64_t resp_addr;
49239 * This is the host address where
49240 * nvm variable will be stored
49242 uint64_t dest_data_addr;
49243 /* size of data in bits */
49245 /* nvm cfg option number */
49246 uint16_t option_num;
49248 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
49250 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
49252 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
49253 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
49255 * Number of dimensions for this nvm configuration variable.
49256 * This value indicates how many of the indexN values to use.
49257 * A value of 0 means that none of the indexN values are valid.
49258 * A value of 1 requires at index0 is valued, a value of 2
49259 * requires that index0 and index1 are valid, and so forth
49261 uint16_t dimensions;
49262 /* index for the 1st dimensions */
49264 /* index for the 2nd dimensions */
49266 /* index for the 3rd dimensions */
49268 /* index for the 4th dimensions */
49272 * When this bit is set to 1, the factory default value will be returned,
49273 * 0 returns the operational value.
49275 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
49280 /* hwrm_nvm_get_variable_output (size:128b/16B) */
49281 struct hwrm_nvm_get_variable_output {
49282 /* The specific error status for the command. */
49283 uint16_t error_code;
49284 /* The HWRM command request type. */
49286 /* The sequence ID from the original command. */
49288 /* The length of the response data in number of bytes. */
49290 /* size of data of the actual variable retrieved in bits */
49293 * option_num is the option number for the data retrieved. It is possible in the
49294 * future that the option number returned would be different than requested. This
49295 * condition could occur if an option is deprecated and a new option id is defined
49296 * with similar characteristics, but has a slightly different definition. This
49297 * also makes it convenient for the caller to identify the variable result with
49298 * the option id from the response.
49300 uint16_t option_num;
49302 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
49304 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
49306 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
49307 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
49308 uint8_t unused_0[3];
49310 * This field is used in Output records to indicate that the output
49311 * is completely written to RAM. This field should be read as '1'
49312 * to indicate that the output has been completely written.
49313 * When writing a command completion or response to an internal processor,
49314 * the order of writes has to be such that this field is written last.
49319 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
49320 struct hwrm_nvm_get_variable_cmd_err {
49322 * command specific error codes that goes to
49323 * the cmd_err field in Common HWRM Error Response.
49326 /* Unknown error */
49327 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
49328 /* variable does not exist */
49329 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
49330 /* configuration is corrupted and the variable cannot be saved */
49331 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
49332 /* length specified is too small */
49333 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
49334 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
49335 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
49336 uint8_t unused_0[7];
49339 /*************************
49340 * hwrm_nvm_set_variable *
49341 *************************/
49344 /* hwrm_nvm_set_variable_input (size:320b/40B) */
49345 struct hwrm_nvm_set_variable_input {
49346 /* The HWRM command request type. */
49349 * The completion ring to send the completion event on. This should
49350 * be the NQ ID returned from the `nq_alloc` HWRM command.
49352 uint16_t cmpl_ring;
49354 * The sequence ID is used by the driver for tracking multiple
49355 * commands. This ID is treated as opaque data by the firmware and
49356 * the value is returned in the `hwrm_resp_hdr` upon completion.
49360 * The target ID of the command:
49361 * * 0x0-0xFFF8 - The function ID
49362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49363 * * 0xFFFD - Reserved for user-space HWRM interface
49366 uint16_t target_id;
49368 * A physical address pointer pointing to a host buffer that the
49369 * command's response data will be written. This can be either a host
49370 * physical address (HPA) or a guest physical address (GPA) and must
49371 * point to a physically contiguous block of memory.
49373 uint64_t resp_addr;
49375 * This is the host address where
49376 * nvm variable will be copied from
49378 uint64_t src_data_addr;
49379 /* size of data in bits */
49381 /* nvm cfg option number */
49382 uint16_t option_num;
49384 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
49386 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
49388 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
49389 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
49391 * Number of dimensions for this nvm configuration variable.
49392 * This value indicates how many of the indexN values to use.
49393 * A value of 0 means that none of the indexN values are valid.
49394 * A value of 1 requires at index0 is valued, a value of 2
49395 * requires that index0 and index1 are valid, and so forth
49397 uint16_t dimensions;
49398 /* index for the 1st dimensions */
49400 /* index for the 2nd dimensions */
49402 /* index for the 3rd dimensions */
49404 /* index for the 4th dimensions */
49408 * When this bit is 1, flush internal cache after this write operation
49409 * (see hwrm_nvm_flush command.)
49411 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
49413 /* encryption method */
49414 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
49416 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
49417 /* No encryption. */
49418 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
49419 (UINT32_C(0x0) << 1)
49420 /* one-way encryption. */
49421 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
49422 (UINT32_C(0x1) << 1)
49423 /* symmetric AES256 encryption. */
49424 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
49425 (UINT32_C(0x2) << 1)
49426 /* SHA1 digest appended to plaintext contents, for authentication */
49427 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
49428 (UINT32_C(0x3) << 1)
49429 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
49430 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
49431 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
49433 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
49434 /* When this bit is 1, update the factory default region */
49435 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
49440 /* hwrm_nvm_set_variable_output (size:128b/16B) */
49441 struct hwrm_nvm_set_variable_output {
49442 /* The specific error status for the command. */
49443 uint16_t error_code;
49444 /* The HWRM command request type. */
49446 /* The sequence ID from the original command. */
49448 /* The length of the response data in number of bytes. */
49450 uint8_t unused_0[7];
49452 * This field is used in Output records to indicate that the output
49453 * is completely written to RAM. This field should be read as '1'
49454 * to indicate that the output has been completely written.
49455 * When writing a command completion or response to an internal processor,
49456 * the order of writes has to be such that this field is written last.
49461 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
49462 struct hwrm_nvm_set_variable_cmd_err {
49464 * command specific error codes that goes to
49465 * the cmd_err field in Common HWRM Error Response.
49468 /* Unknown error */
49469 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
49470 /* variable does not exist */
49471 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
49472 /* configuration is corrupted and the variable cannot be saved */
49473 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
49474 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
49475 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
49476 uint8_t unused_0[7];
49479 /****************************
49480 * hwrm_nvm_validate_option *
49481 ****************************/
49484 /* hwrm_nvm_validate_option_input (size:320b/40B) */
49485 struct hwrm_nvm_validate_option_input {
49486 /* The HWRM command request type. */
49489 * The completion ring to send the completion event on. This should
49490 * be the NQ ID returned from the `nq_alloc` HWRM command.
49492 uint16_t cmpl_ring;
49494 * The sequence ID is used by the driver for tracking multiple
49495 * commands. This ID is treated as opaque data by the firmware and
49496 * the value is returned in the `hwrm_resp_hdr` upon completion.
49500 * The target ID of the command:
49501 * * 0x0-0xFFF8 - The function ID
49502 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49503 * * 0xFFFD - Reserved for user-space HWRM interface
49506 uint16_t target_id;
49508 * A physical address pointer pointing to a host buffer that the
49509 * command's response data will be written. This can be either a host
49510 * physical address (HPA) or a guest physical address (GPA) and must
49511 * point to a physically contiguous block of memory.
49513 uint64_t resp_addr;
49515 * This is the host address where
49516 * nvm variable will be copied from
49518 uint64_t src_data_addr;
49519 /* size of data in bits */
49521 /* nvm cfg option number */
49522 uint16_t option_num;
49524 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
49527 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
49529 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
49530 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
49532 * Number of dimensions for this nvm configuration variable.
49533 * This value indicates how many of the indexN values to use.
49534 * A value of 0 means that none of the indexN values are valid.
49535 * A value of 1 requires at index0 is valued, a value of 2
49536 * requires that index0 and index1 are valid, and so forth
49538 uint16_t dimensions;
49539 /* index for the 1st dimensions */
49541 /* index for the 2nd dimensions */
49543 /* index for the 3rd dimensions */
49545 /* index for the 4th dimensions */
49547 uint8_t unused_0[2];
49550 /* hwrm_nvm_validate_option_output (size:128b/16B) */
49551 struct hwrm_nvm_validate_option_output {
49552 /* The specific error status for the command. */
49553 uint16_t error_code;
49554 /* The HWRM command request type. */
49556 /* The sequence ID from the original command. */
49558 /* The length of the response data in number of bytes. */
49561 /* indicates that the value provided for the option is not matching with the saved data. */
49562 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
49563 /* indicates that the value provided for the option is matching the saved data. */
49564 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
49565 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
49566 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
49567 uint8_t unused_0[6];
49569 * This field is used in Output records to indicate that the output
49570 * is completely written to RAM. This field should be read as '1'
49571 * to indicate that the output has been completely written.
49572 * When writing a command completion or response to an internal processor,
49573 * the order of writes has to be such that this field is written last.
49578 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
49579 struct hwrm_nvm_validate_option_cmd_err {
49581 * command specific error codes that goes to
49582 * the cmd_err field in Common HWRM Error Response.
49585 /* Unknown error */
49586 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
49587 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
49588 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
49589 uint8_t unused_0[7];
49597 /* hwrm_oem_cmd_input (size:1024b/128B) */
49598 struct hwrm_oem_cmd_input {
49599 /* The HWRM command request type. */
49602 * The completion ring to send the completion event on. This should
49603 * be the NQ ID returned from the `nq_alloc` HWRM command.
49605 uint16_t cmpl_ring;
49607 * The sequence ID is used by the driver for tracking multiple
49608 * commands. This ID is treated as opaque data by the firmware and
49609 * the value is returned in the `hwrm_resp_hdr` upon completion.
49613 * The target ID of the command:
49614 * * 0x0-0xFFF8 - The function ID
49615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49616 * * 0xFFFD - Reserved for user-space HWRM interface
49619 uint16_t target_id;
49621 * A physical address pointer pointing to a host buffer that the
49622 * command's response data will be written. This can be either a host
49623 * physical address (HPA) or a guest physical address (GPA) and must
49624 * point to a physically contiguous block of memory.
49626 uint64_t resp_addr;
49629 /* This field contains the vendor specific command data. */
49630 uint32_t oem_data[26];
49633 /* hwrm_oem_cmd_output (size:768b/96B) */
49634 struct hwrm_oem_cmd_output {
49635 /* The specific error status for the command. */
49636 uint16_t error_code;
49637 /* The HWRM command request type. */
49639 /* The sequence ID from the original command. */
49641 /* The length of the response data in number of bytes. */
49645 /* This field contains the vendor specific response data. */
49646 uint32_t oem_data[18];
49647 uint8_t unused_1[7];
49649 * This field is used in Output records to indicate that the output
49650 * is completely written to RAM. This field should be read as '1'
49651 * to indicate that the output has been completely written.
49652 * When writing a command completion or response to an internal processor,
49653 * the order of writes has to be such that this field is written last.
49660 ******************/
49663 /* hwrm_fw_reset_input (size:192b/24B) */
49664 struct hwrm_fw_reset_input {
49665 /* The HWRM command request type. */
49668 * The completion ring to send the completion event on. This should
49669 * be the NQ ID returned from the `nq_alloc` HWRM command.
49671 uint16_t cmpl_ring;
49673 * The sequence ID is used by the driver for tracking multiple
49674 * commands. This ID is treated as opaque data by the firmware and
49675 * the value is returned in the `hwrm_resp_hdr` upon completion.
49679 * The target ID of the command:
49680 * * 0x0-0xFFF8 - The function ID
49681 * * 0xFFF8-0xFFFE - Reserved for internal processors
49684 uint16_t target_id;
49686 * A physical address pointer pointing to a host buffer that the
49687 * command's response data will be written. This can be either a host
49688 * physical address (HPA) or a guest physical address (GPA) and must
49689 * point to a physically contiguous block of memory.
49691 uint64_t resp_addr;
49692 /* Type of embedded processor. */
49693 uint8_t embedded_proc_type;
49694 /* Boot Processor */
49695 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
49697 /* Management Processor */
49698 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
49700 /* Network control processor */
49701 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
49703 /* RoCE control processor */
49704 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
49707 * Host (in multi-host environment): This is only valid if requester is IPC.
49708 * Reinit host hardware resources and PCIe.
49710 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
49713 * AP processor complex (in multi-host environment).
49714 * Use host_idx to control which core is reset
49716 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
49718 /* Reset all blocks of the chip (including all processors) */
49719 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
49722 * Host (in multi-host environment): This is only valid if requester is IPC.
49723 * Reinit host hardware resources.
49725 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
49727 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
49728 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
49729 /* Type of self reset. */
49730 uint8_t selfrst_status;
49731 /* No Self Reset */
49732 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
49734 /* Self Reset as soon as possible to do so safely */
49735 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
49737 /* Self Reset on PCIe Reset */
49738 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
49740 /* Self Reset immediately after notification to all clients. */
49741 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
49743 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
49744 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
49746 * Indicate which host is being reset. 0 means first host.
49747 * Only valid when embedded_proc_type is host in multihost
49753 * When this bit is '1', then the core firmware initiates
49754 * the reset only after graceful shut down of all registered instances.
49755 * If not, the device will continue with the existing firmware.
49757 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
49758 uint8_t unused_0[4];
49761 /* hwrm_fw_reset_output (size:128b/16B) */
49762 struct hwrm_fw_reset_output {
49763 /* The specific error status for the command. */
49764 uint16_t error_code;
49765 /* The HWRM command request type. */
49767 /* The sequence ID from the original command. */
49769 /* The length of the response data in number of bytes. */
49771 /* Type of self reset. */
49772 uint8_t selfrst_status;
49773 /* No Self Reset */
49774 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
49776 /* Self Reset as soon as possible to do so safely */
49777 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
49779 /* Self Reset on PCIe Reset */
49780 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
49782 /* Self Reset immediately after notification to all clients. */
49783 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
49785 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
49786 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
49787 uint8_t unused_0[6];
49789 * This field is used in Output records to indicate that the output
49790 * is completely written to RAM. This field should be read as '1'
49791 * to indicate that the output has been completely written.
49792 * When writing a command completion or response to an internal processor,
49793 * the order of writes has to be such that this field is written last.
49798 /**********************
49799 * hwrm_port_ts_query *
49800 ***********************/
49803 /* hwrm_port_ts_query_input (size:192b/24B) */
49804 struct hwrm_port_ts_query_input {
49805 /* The HWRM command request type. */
49808 * The completion ring to send the completion event on. This should
49809 * be the NQ ID returned from the `nq_alloc` HWRM command.
49811 uint16_t cmpl_ring;
49813 * The sequence ID is used by the driver for tracking multiple
49814 * commands. This ID is treated as opaque data by the firmware and
49815 * the value is returned in the `hwrm_resp_hdr` upon completion.
49819 * The target ID of the command:
49820 * * 0x0-0xFFF8 - The function ID
49821 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49822 * * 0xFFFD - Reserved for user-space HWRM interface
49825 uint16_t target_id;
49827 * A physical address pointer pointing to a host buffer that the
49828 * command's response data will be written. This can be either a host
49829 * physical address (HPA) or a guest physical address (GPA) and must
49830 * point to a physically contiguous block of memory.
49832 uint64_t resp_addr;
49835 * Enumeration denoting the RX, TX type of the resource.
49836 * This enumeration is used for resources that are similar for both
49837 * TX and RX paths of the chip.
49839 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
49841 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
49843 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
49844 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
49845 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
49847 * If set, the response includes the current value of the free
49850 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
49851 /* Port ID of port that is being queried. */
49853 uint8_t unused_0[2];
49856 /* hwrm_port_ts_query_output (size:192b/24B) */
49857 struct hwrm_port_ts_query_output {
49858 /* The specific error status for the command. */
49859 uint16_t error_code;
49860 /* The HWRM command request type. */
49862 /* The sequence ID from the original command. */
49864 /* The length of the response data in number of bytes. */
49867 * Timestamp value of PTP message captured, or current value of
49868 * free running timer.
49870 uint32_t ptp_msg_ts[2];
49871 /* Sequence ID of the PTP message captured. */
49872 uint16_t ptp_msg_seqid;
49873 uint8_t unused_0[5];
49875 * This field is used in Output records to indicate that the output
49876 * is completely written to RAM. This field should be read as '1'
49877 * to indicate that the output has been completely written.
49878 * When writing a command completion or response to an internal processor,
49879 * the order of writes has to be such that this field is written last.
49885 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
49886 * offset: 0x31001F0). Host software is expected to read from this
49887 * location for a defined signature. If it exists, the software can
49888 * assume the presence of this structure and the validity of the
49889 * FW_STATUS location in the next field.
49891 /* hcomm_status (size:64b/8B) */
49892 struct hcomm_status {
49895 * This field defines the version of the structure. The latest
49896 * version value is 1.
49898 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
49899 #define HCOMM_STATUS_VER_SFT 0
49900 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
49901 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
49903 * This field is to store the signature value to indicate the
49904 * presence of the structure.
49906 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
49907 #define HCOMM_STATUS_SIGNATURE_SFT 8
49908 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
49909 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
49910 uint32_t fw_status_loc;
49911 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
49912 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
49913 /* PCIE configuration space */
49914 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
49916 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
49918 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
49920 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
49921 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
49922 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
49924 * This offset where the fw_status register is located. The value
49925 * is generally 4-byte aligned.
49927 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
49928 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
49930 /* This is the GRC offset where the hcomm_status struct resides. */
49931 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
49933 /**************************
49934 * hwrm_port_phy_i2c_read *
49935 **************************/
49938 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
49939 struct hwrm_port_phy_i2c_read_input {
49940 /* The HWRM command request type. */
49943 * The completion ring to send the completion event on. This should
49944 * be the NQ ID returned from the `nq_alloc` HWRM command.
49946 uint16_t cmpl_ring;
49948 * The sequence ID is used by the driver for tracking multiple
49949 * commands. This ID is treated as opaque data by the firmware and
49950 * the value is returned in the `hwrm_resp_hdr` upon completion.
49954 * The target ID of the command:
49955 * * 0x0-0xFFF8 - The function ID
49956 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49957 * * 0xFFFD - Reserved for user-space HWRM interface
49960 uint16_t target_id;
49962 * A physical address pointer pointing to a host buffer that the
49963 * command's response data will be written. This can be either a host
49964 * physical address (HPA) or a guest physical address (GPA) and must
49965 * point to a physically contiguous block of memory.
49967 uint64_t resp_addr;
49971 * This bit must be '1' for the page_offset field to be
49974 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL
49975 /* Port ID of port. */
49977 /* 8-bit I2C slave address. */
49978 uint8_t i2c_slave_addr;
49980 /* The page number that is being accessed over I2C. */
49981 uint16_t page_number;
49982 /* Offset within the page that is being accessed over I2C. */
49983 uint16_t page_offset;
49985 * Length of data to read, in bytes starting at the offset
49986 * specified above. If the offset is not specified, then
49987 * the data shall be read from the beginning of the page.
49989 uint8_t data_length;
49990 uint8_t unused_1[7];
49993 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
49994 struct hwrm_port_phy_i2c_read_output {
49995 /* The specific error status for the command. */
49996 uint16_t error_code;
49997 /* The HWRM command request type. */
49999 /* The sequence ID from the original command. */
50001 /* The length of the response data in number of bytes. */
50003 /* Up to 64B of data. */
50005 uint8_t unused_0[7];
50007 * This field is used in Output records to indicate that the output
50008 * is completely written to RAM. This field should be read as '1'
50009 * to indicate that the output has been completely written.
50010 * When writing a command completion or response to an internal processor,
50011 * the order of writes has to be such that this field is written last.
50015 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */