1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* Engine CKV - The device's serial number. */
71 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
72 /* Engine CKV - Per-function random nonce data. */
73 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
74 /* Engine CKV - Initialization vector. */
75 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
76 /* Engine CKV - Authentication tag. */
77 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
78 /* Engine CKV - The encrypted data. */
79 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
80 /* Engine CKV - Supported algorithms. */
81 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
82 /* Engine CKV - The EC curve name and ECC public key information. */
83 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
84 /* Engine CKV - The ECDSA signature. */
85 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
86 #define TLV_TYPE_LAST \
87 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
90 /* tlv (size:64b/8B) */
93 * The command discriminator is used to differentiate between various
94 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
95 * command messages as well as newer TLV encapsulated HWRM commands.
97 * For TLV encapsulated messages this field must be 0x8000.
103 * Indicates the presence of additional TLV encapsulated data
106 #define TLV_FLAGS_MORE UINT32_C(0x1)
107 /* Last TLV in a sequence of TLVs. */
108 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
109 /* More TLVs follow this TLV. */
110 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
112 * When an HWRM receiver detects a TLV type that it does not
113 * support with the TLV required flag set, the receiver must
114 * reject the HWRM message with an error code indicating an
115 * unsupported TLV type.
117 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
119 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
121 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
122 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
124 * This field defines the TLV type value which is divided into
125 * two ranges to differentiate between global and local TLV types.
126 * Global TLV types must be unique across all defined TLV types.
127 * Local TLV types are valid only for extensions to a given
128 * HWRM message and may be repeated across different HWRM message
129 * types. There is a direct correlation of each HWRM message type
130 * to a single global TLV type value.
132 * Global TLV range: `0 - (63k-1)`
134 * Local TLV range: `63k - (64k-1)`
138 * Length of the message data encapsulated by this TLV in bytes.
139 * This length does not include the size of the TLV header itself
140 * and it must be an integer multiple of 8B.
143 } __attribute__((packed));
146 /* input (size:128b/16B) */
149 * This value indicates what type of request this is. The format
150 * for the rest of the command is determined by this field.
154 * This value indicates the what completion ring the request will
155 * be optionally completed on. If the value is -1, then no
156 * CR completion will be generated. Any other value must be a
157 * valid CR ring_id value for this function.
160 /* This value indicates the command sequence number. */
163 * Target ID of this command.
165 * 0x0 - 0xFFF8 - Used for function ids
166 * 0xFFF8 - 0xFFFE - Reserved for internal processors
171 * This is the host address where the response will be written
172 * when the request is complete. This area must be 16B aligned
173 * and must be cleared to zero before the request is made.
176 } __attribute__((packed));
179 /* output (size:64b/8B) */
182 * Pass/Fail or error type
184 * Note: receiver to verify the in parameters, and fail the call
185 * with an error when appropriate
188 /* This field returns the type of original request. */
190 /* This field provides original sequence number of the command. */
193 * This field is the length of the response in bytes. The
194 * last byte of the response is a valid flag that will read
195 * as '1' when the command has been completely written to
199 } __attribute__((packed));
201 /* Short Command Structure */
202 /* hwrm_short_input (size:128b/16B) */
203 struct hwrm_short_input {
205 * This field indicates the type of request in the request buffer.
206 * The format for the rest of the command (request) is determined
211 * This field indicates a signature that is used to identify short
212 * form of the command listed here. This field shall be set to
216 /* Signature indicating this is a short form of HWRM command */
217 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
218 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
219 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
220 /* Reserved for future use. */
222 /* This value indicates the length of the request. */
225 * This is the host address where the request was written.
226 * This area must be 16B aligned.
229 } __attribute__((packed));
233 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
234 * # So only structure definition is provided here.
236 /* cmd_nums (size:64b/8B) */
239 * This version of the specification defines the commands listed in
240 * the table below. The following are general implementation
241 * requirements for these commands:
243 * # All commands listed below that are marked neither
244 * reserved nor experimental shall be implemented by the HWRM.
245 * # A HWRM client compliant to this specification should not use
246 * commands outside of the list below.
247 * # A HWRM client compliant to this specification should not use
248 * command numbers marked reserved below.
249 * # A command marked experimental below may not be implemented
251 * # A command marked experimental may change in the
252 * future version of the HWRM specification.
253 * # A command not listed below may be implemented by the HWRM.
254 * The behavior of commands that are not listed below is outside
255 * the scope of this specification.
258 #define HWRM_VER_GET UINT32_C(0x0)
259 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
260 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
261 /* Reserved for future use. */
262 #define HWRM_RESERVED1 UINT32_C(0x10)
263 #define HWRM_FUNC_RESET UINT32_C(0x11)
264 #define HWRM_FUNC_GETFID UINT32_C(0x12)
265 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
266 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
267 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
268 #define HWRM_FUNC_QCFG UINT32_C(0x16)
269 #define HWRM_FUNC_CFG UINT32_C(0x17)
270 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
271 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
272 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
273 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
274 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
275 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
276 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
277 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
278 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
279 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
281 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
282 #define HWRM_PORT_QSTATS UINT32_C(0x23)
283 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
285 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
287 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
288 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
289 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
291 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
292 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
293 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
294 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
295 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
296 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
297 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
298 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
299 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
300 #define HWRM_QUEUE_CFG UINT32_C(0x32)
301 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
302 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
303 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
304 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
305 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
306 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
307 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
308 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
310 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
312 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
314 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
315 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
316 #define HWRM_VNIC_FREE UINT32_C(0x41)
317 #define HWRM_VNIC_CFG UINT32_C(0x42)
318 #define HWRM_VNIC_QCFG UINT32_C(0x43)
319 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
321 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
322 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
323 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
324 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
325 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
326 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
327 #define HWRM_RING_ALLOC UINT32_C(0x50)
328 #define HWRM_RING_FREE UINT32_C(0x51)
329 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
330 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
331 #define HWRM_RING_RESET UINT32_C(0x5e)
332 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
333 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
334 /* Reserved for future use. */
335 #define HWRM_RESERVED5 UINT32_C(0x64)
336 /* Reserved for future use. */
337 #define HWRM_RESERVED6 UINT32_C(0x65)
338 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
339 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
340 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
341 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
342 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
343 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
344 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
345 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
346 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
348 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
350 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
351 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
352 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
353 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
355 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
357 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
359 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
360 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
361 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
362 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
363 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
364 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
365 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
366 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
367 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
368 #define HWRM_FW_RESET UINT32_C(0xc0)
369 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
371 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
373 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
375 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
377 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
379 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
380 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
381 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
382 #define HWRM_FWD_RESP UINT32_C(0xd2)
383 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
384 #define HWRM_OEM_CMD UINT32_C(0xd4)
385 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
386 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
387 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
388 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
389 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
391 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
393 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
395 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
397 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
399 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
401 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
403 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
405 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
407 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
409 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
411 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
413 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
415 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
417 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
419 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
421 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
423 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
424 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
425 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
426 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
428 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
430 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
432 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
434 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
435 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
436 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
437 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
438 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
439 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
440 /* Engine CKV - Add a new CKEK used to encrypt keys. */
441 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
442 /* Engine CKV - Delete a previously added CKEK. */
443 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
444 /* Engine CKV - Add a new key to the key vault. */
445 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
446 /* Engine CKV - Delete a key from the key vault. */
447 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
448 /* Engine CKV - Delete all keys from the key vault. */
449 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
450 /* Engine CKV - Get random data. */
451 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
452 /* Engine CKV - Generate and encrypt a new AES key. */
453 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
454 /* Engine - Query the available queue groups configuration. */
455 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
456 /* Engine - Query the queue groups assigned to a function. */
457 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
458 /* Engine - Query the available queue group meter profile configuration. */
459 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
460 /* Engine - Query the configuration of a queue group meter profile. */
461 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
462 /* Engine - Allocate a queue group meter profile. */
463 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
464 /* Engine - Free a queue group meter profile. */
465 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
466 /* Engine - Query the meters assigned to a queue group. */
467 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
468 /* Engine - Bind a queue group meter profile to a queue group. */
469 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
470 /* Engine - Unbind a queue group meter profile from a queue group. */
471 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
472 /* Engine - Bind a queue group to a function. */
473 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
474 /* Engine - Query the scheduling group configuration. */
475 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
476 /* Engine - Query the queue groups assigned to a scheduling group. */
477 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
478 /* Engine - Query the configuration of a scheduling group's meter profiles. */
479 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
480 /* Engine - Configure a scheduling group's meter profiles. */
481 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
482 /* Engine - Bind a queue group to a scheduling group. */
483 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
484 /* Engine - Unbind a queue group from its scheduling group. */
485 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
486 /* Engine - Query the Engine configuration. */
487 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
488 /* Engine - Configure the statistics accumulator for an Engine. */
489 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
490 /* Engine - Clear the statistics accumulator for an Engine. */
491 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
492 /* Engine - Query the statistics accumulator for an Engine. */
493 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
494 /* Engine - Allocate an Engine RQ. */
495 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
496 /* Engine - Free an Engine RQ. */
497 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
498 /* Engine - Allocate an Engine CQ. */
499 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
500 /* Engine - Free an Engine CQ. */
501 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
502 /* Engine - Allocate an NQ. */
503 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
504 /* Engine - Free an NQ. */
505 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
506 /* Engine - Set the on-die RQE credit update location. */
507 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
509 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
511 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
513 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
515 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
517 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
519 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
521 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
523 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
525 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
527 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
529 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
531 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
533 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
535 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
536 #define HWRM_DBG_DUMP UINT32_C(0xff14)
538 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
540 #define HWRM_DBG_CFG UINT32_C(0xff16)
542 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
544 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
546 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
548 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
550 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
551 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
552 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
553 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
554 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
555 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
556 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
557 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
558 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
559 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
560 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
561 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
562 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
563 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
564 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
565 #define HWRM_NVM_READ UINT32_C(0xfffd)
566 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
567 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
568 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
569 uint16_t unused_0[3];
570 } __attribute__((packed));
573 /* ret_codes (size:64b/8B) */
576 /* Request was successfully executed by the HWRM. */
577 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
578 /* The HWRM failed to execute the request. */
579 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
581 * The request contains invalid argument(s) or input
584 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
586 * The requester is not allowed to access the requested
587 * resource. This error code shall be provided in a
588 * response to a request to query or modify an existing
589 * resource that is not accessible by the requester.
591 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
593 * The HWRM is unable to allocate the requested resource.
594 * This code only applies to requests for HWRM resource
597 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
599 * Invalid combination of flags is specified in the
602 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
604 * Invalid combination of enables fields is specified in
607 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
609 * Request contains a required TLV that is not supported by
610 * the installed version of firmware.
612 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
614 * No firmware buffer available to accept the request. Driver
615 * should retry the request.
617 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
619 * Generic HWRM execution error that represents an
622 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
624 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
625 /* Unsupported or invalid command */
626 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
627 #define HWRM_ERR_CODE_LAST \
628 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
629 uint16_t unused_0[3];
630 } __attribute__((packed));
633 /* hwrm_err_output (size:128b/16B) */
634 struct hwrm_err_output {
636 * Pass/Fail or error type
638 * Note: receiver to verify the in parameters, and fail the call
639 * with an error when appropriate
642 /* This field returns the type of original request. */
644 /* This field provides original sequence number of the command. */
647 * This field is the length of the response in bytes. The
648 * last byte of the response is a valid flag that will read
649 * as '1' when the command has been completely written to
653 /* debug info for this error response. */
655 /* debug info for this error response. */
658 * In the case of an error response, command specific error
659 * code is returned in this field.
663 * This field is used in Output records to indicate that the output
664 * is completely written to RAM. This field should be read as '1'
665 * to indicate that the output has been completely written.
666 * When writing a command completion or response to an internal processor,
667 * the order of writes has to be such that this field is written last.
670 } __attribute__((packed));
672 * Following is the signature for HWRM message field that indicates not
673 * applicable (All F's). Need to cast it the size of the field if needed.
675 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
676 /* hwrm_func_buf_rgtr */
677 #define HWRM_MAX_REQ_LEN 128
678 /* hwrm_selftest_qlist */
679 #define HWRM_MAX_RESP_LEN 280
680 /* 7 bit indirection table index. */
681 #define HW_HASH_INDEX_SIZE 0x80
682 #define HW_HASH_KEY_SIZE 40
683 /* valid key for HWRM response */
684 #define HWRM_RESP_VALID_KEY 1
685 #define HWRM_VERSION_MAJOR 1
686 #define HWRM_VERSION_MINOR 9
687 #define HWRM_VERSION_UPDATE 2
688 /* non-zero means beta version */
689 #define HWRM_VERSION_RSVD 6
690 #define HWRM_VERSION_STR "1.9.2.6"
697 /* hwrm_ver_get_input (size:192b/24B) */
698 struct hwrm_ver_get_input {
699 /* The HWRM command request type. */
702 * The completion ring to send the completion event on. This should
703 * be the NQ ID returned from the `nq_alloc` HWRM command.
707 * The sequence ID is used by the driver for tracking multiple
708 * commands. This ID is treated as opaque data by the firmware and
709 * the value is returned in the `hwrm_resp_hdr` upon completion.
713 * The target ID of the command:
714 * * 0x0-0xFFF8 - The function ID
715 * * 0xFFF8-0xFFFE - Reserved for internal processors
720 * A physical address pointer pointing to a host buffer that the
721 * command's response data will be written. This can be either a host
722 * physical address (HPA) or a guest physical address (GPA) and must
723 * point to a physically contiguous block of memory.
727 * This field represents the major version of HWRM interface
728 * specification supported by the driver HWRM implementation.
729 * The interface major version is intended to change only when
730 * non backward compatible changes are made to the HWRM
731 * interface specification.
733 uint8_t hwrm_intf_maj;
735 * This field represents the minor version of HWRM interface
736 * specification supported by the driver HWRM implementation.
737 * A change in interface minor version is used to reflect
738 * significant backward compatible modification to HWRM
739 * interface specification.
740 * This can be due to addition or removal of functionality.
741 * HWRM interface specifications with the same major version
742 * but different minor versions are compatible.
744 uint8_t hwrm_intf_min;
746 * This field represents the update version of HWRM interface
747 * specification supported by the driver HWRM implementation.
748 * The interface update version is used to reflect minor
749 * changes or bug fixes to a released HWRM interface
752 uint8_t hwrm_intf_upd;
754 } __attribute__((packed));
756 /* hwrm_ver_get_output (size:1408b/176B) */
757 struct hwrm_ver_get_output {
758 /* The specific error status for the command. */
760 /* The HWRM command request type. */
762 /* The sequence ID from the original command. */
764 /* The length of the response data in number of bytes. */
767 * This field represents the major version of HWRM interface
768 * specification supported by the HWRM implementation.
769 * The interface major version is intended to change only when
770 * non backward compatible changes are made to the HWRM
771 * interface specification.
772 * A HWRM implementation that is compliant with this
773 * specification shall provide value of 1 in this field.
775 uint8_t hwrm_intf_maj_8b;
777 * This field represents the minor version of HWRM interface
778 * specification supported by the HWRM implementation.
779 * A change in interface minor version is used to reflect
780 * significant backward compatible modification to HWRM
781 * interface specification.
782 * This can be due to addition or removal of functionality.
783 * HWRM interface specifications with the same major version
784 * but different minor versions are compatible.
785 * A HWRM implementation that is compliant with this
786 * specification shall provide value of 2 in this field.
788 uint8_t hwrm_intf_min_8b;
790 * This field represents the update version of HWRM interface
791 * specification supported by the HWRM implementation.
792 * The interface update version is used to reflect minor
793 * changes or bug fixes to a released HWRM interface
795 * A HWRM implementation that is compliant with this
796 * specification shall provide value of 2 in this field.
798 uint8_t hwrm_intf_upd_8b;
799 uint8_t hwrm_intf_rsvd_8b;
801 * This field represents the major version of HWRM firmware.
802 * A change in firmware major version represents a major
805 uint8_t hwrm_fw_maj_8b;
807 * This field represents the minor version of HWRM firmware.
808 * A change in firmware minor version represents significant
809 * firmware functionality changes.
811 uint8_t hwrm_fw_min_8b;
813 * This field represents the build version of HWRM firmware.
814 * A change in firmware build version represents bug fixes
815 * to a released firmware.
817 uint8_t hwrm_fw_bld_8b;
819 * This field is a reserved field. This field can be used to
820 * represent firmware branches or customer specific releases
821 * tied to a specific (major,minor,update) version of the
824 uint8_t hwrm_fw_rsvd_8b;
826 * This field represents the major version of mgmt firmware.
827 * A change in major version represents a major release.
829 uint8_t mgmt_fw_maj_8b;
831 * This field represents the minor version of mgmt firmware.
832 * A change in minor version represents significant
833 * functionality changes.
835 uint8_t mgmt_fw_min_8b;
837 * This field represents the build version of mgmt firmware.
838 * A change in update version represents bug fixes.
840 uint8_t mgmt_fw_bld_8b;
842 * This field is a reserved field. This field can be used to
843 * represent firmware branches or customer specific releases
844 * tied to a specific (major,minor,update) version
846 uint8_t mgmt_fw_rsvd_8b;
848 * This field represents the major version of network
850 * A change in major version represents a major release.
852 uint8_t netctrl_fw_maj_8b;
854 * This field represents the minor version of network
856 * A change in minor version represents significant
857 * functionality changes.
859 uint8_t netctrl_fw_min_8b;
861 * This field represents the build version of network
863 * A change in update version represents bug fixes.
865 uint8_t netctrl_fw_bld_8b;
867 * This field is a reserved field. This field can be used to
868 * represent firmware branches or customer specific releases
869 * tied to a specific (major,minor,update) version
871 uint8_t netctrl_fw_rsvd_8b;
873 * This field is used to indicate device's capabilities and
876 uint32_t dev_caps_cfg;
878 * If set to 1, then secure firmware update behavior
880 * If set to 0, then secure firmware update behavior is
883 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
886 * If set to 1, then firmware based DCBX agent is supported.
887 * If set to 0, then firmware based DCBX agent capability
888 * is not supported on this device.
890 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
893 * If set to 1, then HWRM short command format is supported.
894 * If set to 0, then HWRM short command format is not supported.
896 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
899 * If set to 1, then HWRM short command format is required.
900 * If set to 0, then HWRM short command format is not required.
902 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
905 * This field represents the major version of RoCE firmware.
906 * A change in major version represents a major release.
908 uint8_t roce_fw_maj_8b;
910 * This field represents the minor version of RoCE firmware.
911 * A change in minor version represents significant
912 * functionality changes.
914 uint8_t roce_fw_min_8b;
916 * This field represents the build version of RoCE firmware.
917 * A change in update version represents bug fixes.
919 uint8_t roce_fw_bld_8b;
921 * This field is a reserved field. This field can be used to
922 * represent firmware branches or customer specific releases
923 * tied to a specific (major,minor,update) version
925 uint8_t roce_fw_rsvd_8b;
927 * This field represents the name of HWRM FW (ASCII chars
928 * with NULL at the end).
930 char hwrm_fw_name[16];
932 * This field represents the name of mgmt FW (ASCII chars
933 * with NULL at the end).
935 char mgmt_fw_name[16];
937 * This field represents the name of network control
938 * firmware (ASCII chars with NULL at the end).
940 char netctrl_fw_name[16];
942 * This field is reserved for future use.
943 * The responder should set it to 0.
944 * The requester should ignore this field.
946 uint8_t reserved2[16];
948 * This field represents the name of RoCE FW (ASCII chars
949 * with NULL at the end).
951 char roce_fw_name[16];
952 /* This field returns the chip number. */
954 /* This field returns the revision of chip. */
956 /* This field returns the chip metal number. */
958 /* This field returns the bond id of the chip. */
959 uint8_t chip_bond_id;
960 /* This value indicates the type of platform used for chip implementation. */
961 uint8_t chip_platform_type;
963 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
964 /* FPGA platform of the chip. */
965 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
966 /* Palladium platform of the chip. */
967 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
968 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
969 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
971 * This field returns the maximum value of request window that
972 * is supported by the HWRM. The request window is mapped
973 * into device address space using MMIO.
975 uint16_t max_req_win_len;
977 * This field returns the maximum value of response buffer in
980 uint16_t max_resp_len;
982 * This field returns the default request timeout value in
985 uint16_t def_req_timeout;
987 * This field will indicate if any subsystems is not fully
992 * If set to 1, device is not ready.
993 * If set to 0, device is ready to accept all HWRM commands.
995 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
997 * If set to 1, external version present.
998 * If set to 0, external version not present.
1000 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1001 uint8_t unused_0[2];
1003 * For backward compatibility this field must be set to 1.
1004 * Older drivers might look for this field to be 1 before
1005 * processing the message.
1009 * This field represents the major version of HWRM interface
1010 * specification supported by the HWRM implementation.
1011 * The interface major version is intended to change only when
1012 * non backward compatible changes are made to the HWRM
1013 * interface specification. A HWRM implementation that is
1014 * compliant with this specification shall provide value of 1
1017 uint16_t hwrm_intf_major;
1019 * This field represents the minor version of HWRM interface
1020 * specification supported by the HWRM implementation.
1021 * A change in interface minor version is used to reflect
1022 * significant backward compatible modification to HWRM
1023 * interface specification. This can be due to addition or
1024 * removal of functionality. HWRM interface specifications
1025 * with the same major version but different minor versions are
1026 * compatible. A HWRM implementation that is compliant with
1027 * this specification shall provide value of 2 in this field.
1029 uint16_t hwrm_intf_minor;
1031 * This field represents the update version of HWRM interface
1032 * specification supported by the HWRM implementation. The
1033 * interface update version is used to reflect minor changes or
1034 * bug fixes to a released HWRM interface specification.
1035 * A HWRM implementation that is compliant with this
1036 * specification shall provide value of 2 in this field.
1038 uint16_t hwrm_intf_build;
1040 * This field represents the patch version of HWRM interface
1041 * specification supported by the HWRM implementation.
1043 uint16_t hwrm_intf_patch;
1045 * This field represents the major version of HWRM firmware.
1046 * A change in firmware major version represents a major
1049 uint16_t hwrm_fw_major;
1051 * This field represents the minor version of HWRM firmware.
1052 * A change in firmware minor version represents significant
1053 * firmware functionality changes.
1055 uint16_t hwrm_fw_minor;
1057 * This field represents the build version of HWRM firmware.
1058 * A change in firmware build version represents bug fixes to
1059 * a released firmware.
1061 uint16_t hwrm_fw_build;
1063 * This field is a reserved field.
1064 * This field can be used to represent firmware branches or customer
1065 * specific releases tied to a specific (major,minor,update) version
1066 * of the HWRM firmware.
1068 uint16_t hwrm_fw_patch;
1070 * This field represents the major version of mgmt firmware.
1071 * A change in major version represents a major release.
1073 uint16_t mgmt_fw_major;
1075 * This field represents the minor version of HWRM firmware.
1076 * A change in firmware minor version represents significant
1077 * firmware functionality changes.
1079 uint16_t mgmt_fw_minor;
1081 * This field represents the build version of mgmt firmware.
1082 * A change in update version represents bug fixes.
1084 uint16_t mgmt_fw_build;
1086 * This field is a reserved field. This field can be used to
1087 * represent firmware branches or customer specific releases
1088 * tied to a specific (major,minor,update) version.
1090 uint16_t mgmt_fw_patch;
1092 * This field represents the major version of network control
1093 * firmware. A change in major version represents
1096 uint16_t netctrl_fw_major;
1098 * This field represents the minor version of network control
1099 * firmware. A change in minor version represents significant
1100 * functionality changes.
1102 uint16_t netctrl_fw_minor;
1104 * This field represents the build version of network control
1105 * firmware. A change in update version represents bug fixes.
1107 uint16_t netctrl_fw_build;
1109 * This field is a reserved field. This field can be used to
1110 * represent firmware branches or customer specific releases
1111 * tied to a specific (major,minor,update) version
1113 uint16_t netctrl_fw_patch;
1115 * This field represents the major version of RoCE firmware.
1116 * A change in major version represents a major release.
1118 uint16_t roce_fw_major;
1120 * This field represents the minor version of RoCE firmware.
1121 * A change in minor version represents significant
1122 * functionality changes.
1124 uint16_t roce_fw_minor;
1126 * This field represents the build version of RoCE firmware.
1127 * A change in update version represents bug fixes.
1129 uint16_t roce_fw_build;
1131 * This field is a reserved field. This field can be used to
1132 * represent firmware branches or customer specific releases
1133 * tied to a specific (major,minor,update) version
1135 uint16_t roce_fw_patch;
1137 * This field returns the maximum extended request length acceptable
1138 * by the device which allows requests greater than mailbox size when
1139 * used with the short cmd request format.
1141 uint16_t max_ext_req_len;
1142 uint8_t unused_1[5];
1144 * This field is used in Output records to indicate that the output
1145 * is completely written to RAM. This field should be read as '1'
1146 * to indicate that the output has been completely written.
1147 * When writing a command completion or response to an internal processor,
1148 * the order of writes has to be such that this field is written last.
1151 } __attribute__((packed));
1153 /* bd_base (size:64b/8B) */
1156 /* This value identifies the type of buffer descriptor. */
1157 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1158 #define BD_BASE_TYPE_SFT 0
1160 * Indicates that this BD is 16B long and is used for
1161 * normal L2 packet transmission.
1163 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1165 * Indicates that this BD is 1BB long and is an empty
1166 * TX BD. Not valid for use by the driver.
1168 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1170 * Indicates that this BD is 16B long and is an RX Producer
1171 * (ie. empty) buffer descriptor.
1173 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1175 * Indicates that this BD is 16B long and is an RX
1176 * Producer Buffer BD.
1178 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1180 * Indicates that this BD is 16B long and is an
1181 * RX Producer Assembly Buffer Descriptor.
1183 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1185 * Indicates that this BD is 32B long and is used for
1186 * normal L2 packet transmission.
1188 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1189 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG
1190 uint8_t unused_1[7];
1191 } __attribute__((packed));
1193 /* tx_bd_short (size:128b/16B) */
1194 struct tx_bd_short {
1196 * All bits in this field must be valid on the first BD of a packet.
1197 * Only the packet_end bit must be valid for the remaining BDs
1200 uint16_t flags_type;
1201 /* This value identifies the type of buffer descriptor. */
1202 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1203 #define TX_BD_SHORT_TYPE_SFT 0
1205 * Indicates that this BD is 16B long and is used for
1206 * normal L2 packet transmission.
1208 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1209 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1211 * All bits in this field must be valid on the first BD of a packet.
1212 * Only the packet_end bit must be valid for the remaining BDs
1215 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1216 #define TX_BD_SHORT_FLAGS_SFT 6
1218 * If set to 1, the packet ends with the data in the buffer
1219 * pointed to by this descriptor. This flag must be
1220 * valid on every BD.
1222 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1224 * If set to 1, the device will not generate a completion for
1225 * this transmit packet unless there is an error in it's
1228 * is set to 0, then the packet will be completed normally.
1230 * This bit must be valid only on the first BD of a packet.
1232 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1234 * This value indicates how many 16B BD locations are consumed
1235 * in the ring by this packet.
1236 * A value of 1 indicates that this BD is the only BD (and that
1237 * the it is a short BD). A value
1238 * of 3 indicates either 3 short BDs or 1 long BD and one short
1239 * BD in the packet. A value of 0 indicates
1240 * that there are 32 BD locations in the packet (the maximum).
1242 * This field is valid only on the first BD of a packet.
1244 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1245 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1247 * This value is a hint for the length of the entire packet.
1248 * It is used by the chip to optimize internal processing.
1250 * The packet will be dropped if the hint is too short.
1252 * This field is valid only on the first BD of a packet.
1254 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1255 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1256 /* indicates packet length < 512B */
1257 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1258 /* indicates 512 <= packet length < 1KB */
1259 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1260 /* indicates 1KB <= packet length < 2KB */
1261 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1262 /* indicates packet length >= 2KB */
1263 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1264 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1265 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1267 * If set to 1, the device immediately updates the Send Consumer
1268 * Index after the buffer associated with this descriptor has
1269 * been transferred via DMA to NIC memory from host memory. An
1270 * interrupt may or may not be generated according to the state
1271 * of the interrupt avoidance mechanisms. If this bit
1272 * is set to 0, then the Consumer Index is only updated as soon
1273 * as one of the host interrupt coalescing conditions has been met.
1275 * This bit must be valid on the first BD of a packet.
1277 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1279 * This is the length of the host physical buffer this BD describes
1282 * This field must be valid on all BDs of a packet.
1286 * The opaque data field is pass through to the completion and can be
1287 * used for any data that the driver wants to associate with the
1290 * This field must be valid on the first BD of a packet.
1294 * This is the host physical address for the portion of the packet
1295 * described by this TX BD.
1297 * This value must be valid on all BDs of a packet.
1300 } __attribute__((packed));
1302 /* tx_bd_long (size:128b/16B) */
1304 /* This value identifies the type of buffer descriptor. */
1305 uint16_t flags_type;
1307 * This value indicates the type of buffer descriptor.
1310 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1311 #define TX_BD_LONG_TYPE_SFT 0
1313 * Indicates that this BD is 32B long and is used for
1314 * normal L2 packet transmission.
1316 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1317 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1319 * All bits in this field must be valid on the first BD of a packet.
1320 * Only the packet_end bit must be valid for the remaining BDs
1323 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1324 #define TX_BD_LONG_FLAGS_SFT 6
1326 * If set to 1, the packet ends with the data in the buffer
1327 * pointed to by this descriptor. This flag must be
1328 * valid on every BD.
1330 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1332 * If set to 1, the device will not generate a completion for
1333 * this transmit packet unless there is an error in it's
1336 * is set to 0, then the packet will be completed normally.
1338 * This bit must be valid only on the first BD of a packet.
1340 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1342 * This value indicates how many 16B BD locations are consumed
1343 * in the ring by this packet.
1344 * A value of 1 indicates that this BD is the only BD (and that
1345 * the it is a short BD). A value
1346 * of 3 indicates either 3 short BDs or 1 long BD and one short
1347 * BD in the packet. A value of 0 indicates
1348 * that there are 32 BD locations in the packet (the maximum).
1350 * This field is valid only on the first BD of a packet.
1352 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1353 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1355 * This value is a hint for the length of the entire packet.
1356 * It is used by the chip to optimize internal processing.
1358 * The packet will be dropped if the hint is too short.
1360 * This field is valid only on the first BD of a packet.
1362 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1363 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1364 /* indicates packet length < 512B */
1365 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1366 /* indicates 512 <= packet length < 1KB */
1367 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1368 /* indicates 1KB <= packet length < 2KB */
1369 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1370 /* indicates packet length >= 2KB */
1371 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1372 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1374 * If set to 1, the device immediately updates the Send Consumer
1375 * Index after the buffer associated with this descriptor has
1376 * been transferred via DMA to NIC memory from host memory. An
1377 * interrupt may or may not be generated according to the state
1378 * of the interrupt avoidance mechanisms. If this bit
1379 * is set to 0, then the Consumer Index is only updated as soon
1380 * as one of the host interrupt coalescing conditions has been met.
1382 * This bit must be valid on the first BD of a packet.
1384 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1386 * This is the length of the host physical buffer this BD describes
1389 * This field must be valid on all BDs of a packet.
1393 * The opaque data field is pass through to the completion and can be
1394 * used for any data that the driver wants to associate with the
1397 * This field must be valid on the first BD of a packet.
1401 * This is the host physical address for the portion of the packet
1402 * described by this TX BD.
1404 * This value must be valid on all BDs of a packet.
1407 } __attribute__((packed));
1409 /* tx_bd_long_hi (size:128b/16B) */
1410 struct tx_bd_long_hi {
1412 * All bits in this field must be valid on the first BD of a packet.
1413 * Their value on other BDs of the packet will be ignored.
1417 * If set to 1, the controller replaces the TCP/UPD checksum
1418 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1419 * checksum field of the encapsulated TCP/UDP packets with the
1420 * hardware calculated TCP/UDP checksum for the packet associated
1421 * with this descriptor. The flag is ignored if the LSO flag is set.
1423 * This bit must be valid on the first BD of a packet.
1425 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1427 * If set to 1, the controller replaces the IP checksum of the
1428 * normal packets, or the inner IP checksum of the encapsulated
1429 * packets with the hardware calculated IP checksum for the
1430 * packet associated with this descriptor.
1432 * This bit must be valid on the first BD of a packet.
1434 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1436 * If set to 1, the controller will not append an Ethernet CRC
1437 * to the end of the frame.
1439 * This bit must be valid on the first BD of a packet.
1441 * Packet must be 64B or longer when this flag is set. It is not
1442 * useful to use this bit with any form of TX offload such as
1443 * CSO or LSO. The intent is that the packet from the host already
1444 * has a valid Ethernet CRC on the packet.
1446 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1448 * If set to 1, the device will record the time at which the packet
1449 * was actually transmitted at the TX MAC.
1451 * This bit must be valid on the first BD of a packet.
1453 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1455 * If set to 1, The controller replaces the tunnel IP checksum
1456 * field with hardware calculated IP checksum for the IP header
1457 * of the packet associated with this descriptor.
1459 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1460 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1461 * bit is set, outer UDP checksum will be calculated for the following
1463 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1464 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1465 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1466 * checksum will not be calculated.
1467 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1468 * as part of LSO operation.
1470 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1472 * If set to 1, the device will treat this packet with LSO(Large
1473 * Send Offload) processing for both normal or encapsulated
1474 * packets, which is a form of TCP segmentation. When this bit
1475 * is 1, the hdr_size and mss fields must be valid. The driver
1476 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1477 * flags since the controller will replace the appropriate
1478 * checksum fields for segmented packets.
1480 * When this bit is 1, the hdr_size and mss fields must be valid.
1482 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1484 * If set to zero when LSO is '1', then the IPID will be treated
1485 * as a 16b number and will be wrapped if it exceeds a value of
1488 * If set to one when LSO is '1', then the IPID will be treated
1489 * as a 15b number and will be wrapped if it exceeds a value 0f
1492 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1494 * If set to zero when LSO is '1', then the IPID of the tunnel
1495 * IP header will not be modified during LSO operations.
1497 * If set to one when LSO is '1', then the IPID of the tunnel
1498 * IP header will be incremented for each subsequent segment of an
1501 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1504 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1506 * If set to '1', then the RoCE ICRC will be appended to the
1507 * packet. Packet must be a valid RoCE format packet.
1509 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1511 * If set to '1', then the FCoE CRC will be appended to the
1512 * packet. Packet must be a valid FCoE format packet.
1514 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1517 * When LSO is '1', this field must contain the offset of the
1518 * TCP payload from the beginning of the packet in as
1519 * 16b words. In case of encapsulated/tunneling packet, this field
1520 * contains the offset of the inner TCP payload from beginning of the
1521 * packet as 16-bit words.
1523 * This value must be valid on the first BD of a packet.
1525 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1526 #define TX_BD_LONG_HDR_SIZE_SFT 0
1529 * This is the MSS value that will be used to do the LSO processing.
1530 * The value is the length in bytes of the TCP payload for each
1531 * segment generated by the LSO operation.
1533 * This value must be valid on the first BD of a packet.
1535 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1536 #define TX_BD_LONG_MSS_SFT 0
1539 * This value selects a CFA action to perform on the packet.
1540 * Set this value to zero if no CFA action is desired.
1542 * This value must be valid on the first BD of a packet.
1544 uint16_t cfa_action;
1546 * This value is action meta-data that defines CFA edit operations
1547 * that are done in addition to any action editing.
1550 /* When key=1, This is the VLAN tag VID value. */
1551 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1552 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1553 /* When key=1, This is the VLAN tag DE value. */
1554 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1555 /* When key=1, This is the VLAN tag PRI value. */
1556 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1557 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1558 /* When key=1, This is the VLAN tag TPID select value. */
1559 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1560 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1562 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1564 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1566 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1568 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1570 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1571 /* Value programmed in CFA VLANTPID register. */
1572 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1573 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1574 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1575 /* When key=1, This is the VLAN tag TPID select value. */
1576 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1577 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1579 * This field identifies the type of edit to be performed
1582 * This value must be valid on the first BD of a packet.
1584 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1585 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1587 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1589 * - meta[17:16] - TPID select value (0 = 0x8100).
1590 * - meta[15:12] - PRI/DE value.
1591 * - meta[11:0] - VID value.
1593 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1594 #define TX_BD_LONG_CFA_META_KEY_LAST \
1595 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1596 } __attribute__((packed));
1598 /* tx_bd_empty (size:128b/16B) */
1599 struct tx_bd_empty {
1600 /* This value identifies the type of buffer descriptor. */
1602 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1603 #define TX_BD_EMPTY_TYPE_SFT 0
1605 * Indicates that this BD is 1BB long and is an empty
1606 * TX BD. Not valid for use by the driver.
1608 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1609 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1610 uint8_t unused_1[3];
1612 uint8_t unused_3[3];
1613 uint8_t unused_4[8];
1614 } __attribute__((packed));
1616 /* rx_prod_pkt_bd (size:128b/16B) */
1617 struct rx_prod_pkt_bd {
1618 /* This value identifies the type of buffer descriptor. */
1619 uint16_t flags_type;
1620 /* This value identifies the type of buffer descriptor. */
1621 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
1622 #define RX_PROD_PKT_BD_TYPE_SFT 0
1624 * Indicates that this BD is 16B long and is an RX Producer
1625 * (ie. empty) buffer descriptor.
1627 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
1628 #define RX_PROD_PKT_BD_TYPE_LAST \
1629 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
1630 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
1631 #define RX_PROD_PKT_BD_FLAGS_SFT 6
1633 * If set to 1, the packet will be placed at the address plus
1634 * 2B. The 2 Bytes of padding will be written as zero.
1636 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
1638 * If set to 1, the packet write will be padded out to the
1639 * nearest cache-line with zero value padding.
1641 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
1643 * This value is the number of additional buffers in the ring that
1644 * describe the buffer space to be consumed for the this packet.
1645 * If the value is zero, then the packet must fit within the
1646 * space described by this BD. If this value is 1 or more, it
1647 * indicates how many additional "buffer" BDs are in the ring
1648 * immediately following this BD to be used for the same
1651 * Even if the packet to be placed does not need all the
1652 * additional buffers, they will be consumed anyway.
1654 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
1655 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
1657 * This is the length in Bytes of the host physical buffer where
1658 * data for the packet may be placed in host memory.
1662 * The opaque data field is pass through to the completion and can be
1663 * used for any data that the driver wants to associate with this
1664 * receive buffer set.
1668 * This is the host physical address where data for the packet may
1669 * by placed in host memory.
1672 } __attribute__((packed));
1674 /* rx_prod_bfr_bd (size:128b/16B) */
1675 struct rx_prod_bfr_bd {
1676 /* This value identifies the type of buffer descriptor. */
1677 uint16_t flags_type;
1678 /* This value identifies the type of buffer descriptor. */
1679 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
1680 #define RX_PROD_BFR_BD_TYPE_SFT 0
1682 * Indicates that this BD is 16B long and is an RX
1683 * Producer Buffer BD.
1685 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
1686 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
1687 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
1688 #define RX_PROD_BFR_BD_FLAGS_SFT 6
1690 * This is the length in Bytes of the host physical buffer where
1691 * data for the packet may be placed in host memory.
1694 /* This field is not used. */
1697 * This is the host physical address where data for the packet may
1698 * by placed in host memory.
1701 } __attribute__((packed));
1703 /* rx_prod_agg_bd (size:128b/16B) */
1704 struct rx_prod_agg_bd {
1705 /* This value identifies the type of buffer descriptor. */
1706 uint16_t flags_type;
1707 /* This value identifies the type of buffer descriptor. */
1708 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
1709 #define RX_PROD_AGG_BD_TYPE_SFT 0
1711 * Indicates that this BD is 16B long and is an
1712 * RX Producer Assembly Buffer Descriptor.
1714 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
1715 #define RX_PROD_AGG_BD_TYPE_LAST \
1716 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
1717 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
1718 #define RX_PROD_AGG_BD_FLAGS_SFT 6
1720 * If set to 1, the packet write will be padded out to the
1721 * nearest cache-line with zero value padding.
1723 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
1725 * This is the length in Bytes of the host physical buffer where
1726 * data for the packet may be placed in host memory.
1730 * The opaque data field is pass through to the completion and can be
1731 * used for any data that the driver wants to associate with this
1732 * receive assembly buffer.
1736 * This is the host physical address where data for the packet may
1737 * by placed in host memory.
1740 } __attribute__((packed));
1742 /* cmpl_base (size:128b/16B) */
1746 * This field indicates the exact type of the completion.
1747 * By convention, the LSB identifies the length of the
1748 * record in 16B units. Even values indicate 16B
1749 * records. Odd values indicate 32B
1752 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
1753 #define CMPL_BASE_TYPE_SFT 0
1756 * Completion of TX packet. Length = 16B
1758 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
1761 * Completion of and L2 RX packet. Length = 32B
1763 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
1765 * RX Aggregation Buffer completion :
1766 * Completion of an L2 aggregation buffer in support of
1767 * TPA, HDS, or Jumbo packet completion. Length = 16B
1769 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
1771 * RX L2 TPA Start Completion:
1772 * Completion at the beginning of a TPA operation.
1775 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
1777 * RX L2 TPA End Completion:
1778 * Completion at the end of a TPA operation.
1781 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
1783 * Statistics Ejection Completion:
1784 * Completion of statistics data ejection buffer.
1787 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
1789 * HWRM Command Completion:
1790 * Completion of an HWRM command.
1792 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
1793 /* Forwarded HWRM Request */
1794 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
1795 /* Forwarded HWRM Response */
1796 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
1797 /* HWRM Asynchronous Event Information */
1798 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1799 /* CQ Notification */
1800 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
1801 /* SRQ Threshold Event */
1802 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
1803 /* DBQ Threshold Event */
1804 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
1805 /* QP Async Notification */
1806 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
1807 /* Function Async Notification */
1808 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
1809 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
1815 * This value is written by the NIC such that it will be different
1816 * for each pass through the completion queue. The even passes
1817 * will write 1. The odd passes will write 0.
1820 #define CMPL_BASE_V UINT32_C(0x1)
1821 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
1822 #define CMPL_BASE_INFO3_SFT 1
1825 } __attribute__((packed));
1827 /* tx_cmpl (size:128b/16B) */
1829 uint16_t flags_type;
1831 * This field indicates the exact type of the completion.
1832 * By convention, the LSB identifies the length of the
1833 * record in 16B units. Even values indicate 16B
1834 * records. Odd values indicate 32B
1837 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
1838 #define TX_CMPL_TYPE_SFT 0
1841 * Completion of TX packet. Length = 16B
1843 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
1844 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
1845 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1846 #define TX_CMPL_FLAGS_SFT 6
1848 * When this bit is '1', it indicates a packet that has an
1849 * error of some type. Type of error is indicated in
1852 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
1854 * When this bit is '1', it indicates that the packet completed
1855 * was transmitted using the push acceleration data provided
1856 * by the driver. When this bit is '0', it indicates that the
1857 * packet had not push acceleration data written or was executed
1858 * as a normal packet even though push data was provided.
1860 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
1861 /* unused1 is 16 b */
1864 * This is a copy of the opaque field from the first TX BD of this
1865 * transmitted packet.
1870 * This value is written by the NIC such that it will be different
1871 * for each pass through the completion queue. The even passes
1872 * will write 1. The odd passes will write 0.
1874 #define TX_CMPL_V UINT32_C(0x1)
1875 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1876 #define TX_CMPL_ERRORS_SFT 1
1878 * This error indicates that there was some sort of problem
1879 * with the BDs for the packet.
1881 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
1882 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
1884 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
1887 * BDs were not formatted correctly.
1889 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
1890 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
1891 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
1893 * When this bit is '1', it indicates that the length of
1894 * the packet was zero. No packet was transmitted.
1896 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
1898 * When this bit is '1', it indicates that the packet
1899 * was longer than the programmed limit in TDI. No
1900 * packet was transmitted.
1902 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
1904 * When this bit is '1', it indicates that one or more of the
1905 * BDs associated with this packet generated a PCI error.
1906 * This probably means the address was not valid.
1908 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
1910 * When this bit is '1', it indicates that the packet was longer
1911 * than indicated by the hint. No packet was transmitted.
1913 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
1915 * When this bit is '1', it indicates that the packet was
1916 * dropped due to Poison TLP error on one or more of the
1917 * TLPs in the PXP completion.
1919 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
1920 /* unused2 is 16 b */
1922 /* unused3 is 32 b */
1924 } __attribute__((packed));
1926 /* rx_pkt_cmpl (size:128b/16B) */
1927 struct rx_pkt_cmpl {
1928 uint16_t flags_type;
1930 * This field indicates the exact type of the completion.
1931 * By convention, the LSB identifies the length of the
1932 * record in 16B units. Even values indicate 16B
1933 * records. Odd values indicate 32B
1936 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
1937 #define RX_PKT_CMPL_TYPE_SFT 0
1940 * Completion of and L2 RX packet. Length = 32B
1942 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
1943 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
1944 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1945 #define RX_PKT_CMPL_FLAGS_SFT 6
1947 * When this bit is '1', it indicates a packet that has an
1948 * error of some type. Type of error is indicated in
1951 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
1952 /* This field indicates how the packet was placed in the buffer. */
1953 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
1954 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
1957 * Packet was placed using normal algorithm.
1959 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
1962 * Packet was placed using jumbo algorithm.
1964 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
1966 * Header/Data Separation:
1967 * Packet was placed using Header/Data separation algorithm.
1968 * The separation location is indicated by the itype field.
1970 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
1971 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
1972 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
1973 /* This bit is '1' if the RSS field in this completion is valid. */
1974 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
1976 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
1978 * This value indicates what the inner packet determined for the
1981 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
1982 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
1985 * Indicates that the packet type was not known.
1987 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
1988 (UINT32_C(0x0) << 12)
1991 * Indicates that the packet was an IP packet, but further
1992 * classification was not possible.
1994 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
1995 (UINT32_C(0x1) << 12)
1998 * Indicates that the packet was IP and TCP.
1999 * This indicates that the payload_offset field is valid.
2001 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2002 (UINT32_C(0x2) << 12)
2005 * Indicates that the packet was IP and UDP.
2006 * This indicates that the payload_offset field is valid.
2008 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2009 (UINT32_C(0x3) << 12)
2012 * Indicates that the packet was recognized as a FCoE.
2013 * This also indicates that the payload_offset field is valid.
2015 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2016 (UINT32_C(0x4) << 12)
2019 * Indicates that the packet was recognized as a RoCE.
2020 * This also indicates that the payload_offset field is valid.
2022 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2023 (UINT32_C(0x5) << 12)
2026 * Indicates that the packet was recognized as ICMP.
2027 * This indicates that the payload_offset field is valid.
2029 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2030 (UINT32_C(0x7) << 12)
2032 * PtP packet wo/timestamp:
2033 * Indicates that the packet was recognized as a PtP
2036 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2037 (UINT32_C(0x8) << 12)
2039 * PtP packet w/timestamp:
2040 * Indicates that the packet was recognized as a PtP
2041 * packet and that a timestamp was taken for the packet.
2043 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2044 (UINT32_C(0x9) << 12)
2045 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2046 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2048 * This is the length of the data for the packet stored in the
2049 * buffer(s) identified by the opaque value. This includes
2050 * the packet BD and any associated buffer BDs. This does not include
2051 * the the length of any data places in aggregation BDs.
2055 * This is a copy of the opaque field from the RX BD this completion
2059 uint8_t agg_bufs_v1;
2061 * This value is written by the NIC such that it will be different
2062 * for each pass through the completion queue. The even passes
2063 * will write 1. The odd passes will write 0.
2065 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2067 * This value is the number of aggregation buffers that follow this
2068 * entry in the completion ring that are a part of this packet.
2069 * If the value is zero, then the packet is completely contained
2070 * in the buffer space provided for the packet in the RX ring.
2072 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2073 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2074 /* unused1 is 2 b */
2075 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2076 #define RX_PKT_CMPL_UNUSED1_SFT 6
2078 * This is the RSS hash type for the packet. The value is packed
2079 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2081 * The value of tuple_extrac_op provides the information about
2082 * what fields the hash was computed on.
2083 * * 0: The RSS hash was computed over source IP address,
2084 * destination IP address, source port, and destination port of inner
2085 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2086 * the packet headers are considered inner packet headers for the RSS
2087 * hash computation purpose.
2088 * * 1: The RSS hash was computed over source IP address and destination
2089 * IP address of inner IP header. Note: For non-tunneled packets,
2090 * the packet headers are considered inner packet headers for the RSS
2091 * hash computation purpose.
2092 * * 2: The RSS hash was computed over source IP address,
2093 * destination IP address, source port, and destination port of
2094 * IP and TCP or UDP headers of outer tunnel headers.
2095 * Note: For non-tunneled packets, this value is not applicable.
2096 * * 3: The RSS hash was computed over source IP address and
2097 * destination IP address of IP header of outer tunnel headers.
2098 * Note: For non-tunneled packets, this value is not applicable.
2100 * Note that 4-tuples values listed above are applicable
2101 * for layer 4 protocols supported and enabled for RSS in the hardware,
2102 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2103 * enabled for TCP traffic only, then the values of tuple_extract_op
2104 * corresponding to 4-tuples are only valid for TCP traffic.
2106 uint8_t rss_hash_type;
2108 * This value indicates the offset in bytes from the beginning of the packet
2109 * where the inner payload starts. This value is valid for TCP, UDP,
2110 * FCoE, and RoCE packets.
2112 * A value of zero indicates that header is 256B into the packet.
2114 uint8_t payload_offset;
2115 /* unused2 is 8 b */
2118 * This value is the RSS hash value calculated for the packet
2119 * based on the mode bits and key value in the VNIC.
2122 } __attribute__((packed));
2124 /* rx_pkt_cmpl_hi (size:128b/16B) */
2125 struct rx_pkt_cmpl_hi {
2128 * This indicates that the ip checksum was calculated for the
2129 * inner packet and that the ip_cs_error field indicates if there
2132 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2134 * This indicates that the TCP, UDP or ICMP checksum was
2135 * calculated for the inner packet and that the l4_cs_error field
2136 * indicates if there was an error.
2138 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2140 * This indicates that the ip checksum was calculated for the
2141 * tunnel header and that the t_ip_cs_error field indicates if there
2144 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2146 * This indicates that the UDP checksum was
2147 * calculated for the tunnel packet and that the t_l4_cs_error field
2148 * indicates if there was an error.
2150 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2151 /* This value indicates what format the metadata field is. */
2152 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2153 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2154 /* No metadata informtaion. Value is zero. */
2155 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
2157 * The metadata field contains the VLAN tag and TPID value.
2158 * - metadata[11:0] contains the vlan VID value.
2159 * - metadata[12] contains the vlan DE value.
2160 * - metadata[15:13] contains the vlan PRI value.
2161 * - metadata[31:16] contains the vlan TPID value.
2163 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
2164 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2165 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
2167 * This field indicates the IP type for the inner-most IP header.
2168 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2169 * This value is only valid if itype indicates a packet
2170 * with an IP header.
2172 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2174 * This is data from the CFA block as indicated by the meta_format
2178 /* When meta_format=1, this value is the VLAN VID. */
2179 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2180 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2181 /* When meta_format=1, this value is the VLAN DE. */
2182 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2183 /* When meta_format=1, this value is the VLAN PRI. */
2184 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2185 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2186 /* When meta_format=1, this value is the VLAN TPID. */
2187 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2188 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2191 * This value is written by the NIC such that it will be different
2192 * for each pass through the completion queue. The even passes
2193 * will write 1. The odd passes will write 0.
2195 #define RX_PKT_CMPL_V2 \
2197 #define RX_PKT_CMPL_ERRORS_MASK \
2199 #define RX_PKT_CMPL_ERRORS_SFT 1
2201 * This error indicates that there was some sort of problem with
2202 * the BDs for the packet that was found after part of the
2203 * packet was already placed. The packet should be treated as
2206 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2208 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2209 /* No buffer error */
2210 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2211 (UINT32_C(0x0) << 1)
2214 * Packet did not fit into packet buffer provided.
2215 * For regular placement, this means the packet did not fit
2216 * in the buffer provided. For HDS and jumbo placement, this
2217 * means that the packet could not be placed into 7 physical
2220 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2221 (UINT32_C(0x1) << 1)
2224 * All BDs needed for the packet were not on-chip when
2225 * the packet arrived.
2227 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2228 (UINT32_C(0x2) << 1)
2231 * BDs were not formatted correctly.
2233 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2234 (UINT32_C(0x3) << 1)
2235 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2236 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
2238 * This indicates that there was an error in the IP header
2241 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2244 * This indicates that there was an error in the TCP, UDP
2247 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2250 * This indicates that there was an error in the tunnel
2251 * IP header checksum.
2253 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2256 * This indicates that there was an error in the tunnel
2259 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2262 * This indicates that there was a CRC error on either an FCoE
2263 * or RoCE packet. The itype indicates the packet type.
2265 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2268 * This indicates that there was an error in the tunnel
2269 * portion of the packet when this
2270 * field is non-zero.
2272 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2274 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2276 * No additional error occurred on the tunnel portion
2277 * of the packet of the packet does not have a tunnel.
2279 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2280 (UINT32_C(0x0) << 9)
2282 * Indicates that IP header version does not match
2283 * expectation from L2 Ethertype for IPv4 and IPv6
2284 * in the tunnel header.
2286 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2287 (UINT32_C(0x1) << 9)
2289 * Indicates that header length is out of range in the
2290 * tunnel header. Valid for
2293 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2294 (UINT32_C(0x2) << 9)
2296 * Indicates that the physical packet is shorter than that
2297 * claimed by the PPPoE header length for a tunnel PPPoE
2300 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2301 (UINT32_C(0x3) << 9)
2303 * Indicates that physical packet is shorter than that claimed
2304 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2305 * tunnel packet packets.
2307 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2308 (UINT32_C(0x4) << 9)
2310 * Indicates that the physical packet is shorter than that
2311 * claimed by the tunnel UDP header length for a tunnel
2312 * UDP packet that is not fragmented.
2314 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2315 (UINT32_C(0x5) << 9)
2317 * indicates that the IPv4 TTL or IPv6 hop limit check
2318 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2319 * for IPv4, and IPv6.
2321 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2322 (UINT32_C(0x6) << 9)
2323 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2324 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2326 * This indicates that there was an error in the inner
2327 * portion of the packet when this
2328 * field is non-zero.
2330 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2332 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2334 * No additional error occurred on the tunnel portion
2335 * of the packet of the packet does not have a tunnel.
2337 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2338 (UINT32_C(0x0) << 12)
2340 * Indicates that IP header version does not match
2341 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2342 * option other than VFT was parsed on
2345 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2346 (UINT32_C(0x1) << 12)
2348 * indicates that header length is out of range. Valid for
2351 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2352 (UINT32_C(0x2) << 12)
2354 * indicates that the IPv4 TTL or IPv6 hop limit check
2355 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2357 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2358 (UINT32_C(0x3) << 12)
2360 * Indicates that physical packet is shorter than that
2361 * claimed by the l3 header length. Valid for IPv4,
2362 * IPv6 packet or RoCE packets.
2364 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2365 (UINT32_C(0x4) << 12)
2367 * Indicates that the physical packet is shorter than that
2368 * claimed by the UDP header length for a UDP packet that is
2371 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2372 (UINT32_C(0x5) << 12)
2374 * Indicates that TCP header length > IP payload. Valid for
2377 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2378 (UINT32_C(0x6) << 12)
2379 /* Indicates that TCP header length < 5. Valid for TCP. */
2380 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2381 (UINT32_C(0x7) << 12)
2383 * Indicates that TCP option headers result in a TCP header
2384 * size that does not match data offset in TCP header. Valid
2387 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2388 (UINT32_C(0x8) << 12)
2389 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2390 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2392 * This field identifies the CFA action rule that was used for this
2398 * This value holds the reordering sequence number for the packet.
2399 * If the reordering sequence is not valid, then this value is zero.
2400 * The reordering domain for the packet is in the bottom 8 to 10b of
2401 * the rss_hash value. The bottom 20b of this value contain the
2402 * ordering domain value for the packet.
2404 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2405 #define RX_PKT_CMPL_REORDER_SFT 0
2406 } __attribute__((packed));
2408 /* rx_tpa_start_cmpl (size:128b/16B) */
2409 struct rx_tpa_start_cmpl {
2410 uint16_t flags_type;
2412 * This field indicates the exact type of the completion.
2413 * By convention, the LSB identifies the length of the
2414 * record in 16B units. Even values indicate 16B
2415 * records. Odd values indicate 32B
2418 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2419 #define RX_TPA_START_CMPL_TYPE_SFT 0
2421 * RX L2 TPA Start Completion:
2422 * Completion at the beginning of a TPA operation.
2425 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2426 #define RX_TPA_START_CMPL_TYPE_LAST \
2427 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2428 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2429 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2430 /* This bit will always be '0' for TPA start completions. */
2431 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2432 /* This field indicates how the packet was placed in the buffer. */
2433 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2434 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2437 * TPA Packet was placed using jumbo algorithm. This means
2438 * that the first buffer will be filled with data before
2439 * moving to aggregation buffers. Each aggregation buffer
2440 * will be filled before moving to the next aggregation
2443 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2444 (UINT32_C(0x1) << 7)
2446 * Header/Data Separation:
2447 * Packet was placed using Header/Data separation algorithm.
2448 * The separation location is indicated by the itype field.
2450 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2451 (UINT32_C(0x2) << 7)
2454 * Packet will be placed using GRO/Jumbo where the first
2455 * packet is filled with data. Subsequent packets will be
2456 * placed such that any one packet does not span two
2457 * aggregation buffers unless it starts at the beginning of
2458 * an aggregation buffer.
2460 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2461 (UINT32_C(0x5) << 7)
2463 * GRO/Header-Data Separation:
2464 * Packet will be placed using GRO/HDS where the header
2465 * is in the first packet.
2466 * Payload of each packet will be
2467 * placed such that any one packet does not span two
2468 * aggregation buffers unless it starts at the beginning of
2469 * an aggregation buffer.
2471 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2472 (UINT32_C(0x6) << 7)
2473 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2474 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2475 /* This bit is '1' if the RSS field in this completion is valid. */
2476 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2478 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2480 * This value indicates what the inner packet determined for the
2483 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2484 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2487 * Indicates that the packet was IP and TCP.
2489 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2490 (UINT32_C(0x2) << 12)
2491 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2492 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2494 * This value indicates the amount of packet data written to the
2495 * buffer the opaque field in this completion corresponds to.
2499 * This is a copy of the opaque field from the RX BD this completion
2504 * This value is written by the NIC such that it will be different
2505 * for each pass through the completion queue. The even passes
2506 * will write 1. The odd passes will write 0.
2510 * This value is written by the NIC such that it will be different
2511 * for each pass through the completion queue. The even passes
2512 * will write 1. The odd passes will write 0.
2514 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2515 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2517 * This is the RSS hash type for the packet. The value is packed
2518 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2520 * The value of tuple_extrac_op provides the information about
2521 * what fields the hash was computed on.
2522 * * 0: The RSS hash was computed over source IP address,
2523 * destination IP address, source port, and destination port of inner
2524 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2525 * the packet headers are considered inner packet headers for the RSS
2526 * hash computation purpose.
2527 * * 1: The RSS hash was computed over source IP address and destination
2528 * IP address of inner IP header. Note: For non-tunneled packets,
2529 * the packet headers are considered inner packet headers for the RSS
2530 * hash computation purpose.
2531 * * 2: The RSS hash was computed over source IP address,
2532 * destination IP address, source port, and destination port of
2533 * IP and TCP or UDP headers of outer tunnel headers.
2534 * Note: For non-tunneled packets, this value is not applicable.
2535 * * 3: The RSS hash was computed over source IP address and
2536 * destination IP address of IP header of outer tunnel headers.
2537 * Note: For non-tunneled packets, this value is not applicable.
2539 * Note that 4-tuples values listed above are applicable
2540 * for layer 4 protocols supported and enabled for RSS in the hardware,
2541 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2542 * enabled for TCP traffic only, then the values of tuple_extract_op
2543 * corresponding to 4-tuples are only valid for TCP traffic.
2545 uint8_t rss_hash_type;
2547 * This is the aggregation ID that the completion is associated
2548 * with. Use this number to correlate the TPA start completion
2549 * with the TPA end completion.
2552 /* unused2 is 9 b */
2553 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2554 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2556 * This is the aggregation ID that the completion is associated
2557 * with. Use this number to correlate the TPA start completion
2558 * with the TPA end completion.
2560 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
2561 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
2563 * This value is the RSS hash value calculated for the packet
2564 * based on the mode bits and key value in the VNIC.
2567 } __attribute__((packed));
2569 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
2570 struct rx_tpa_start_cmpl_hi {
2573 * This indicates that the ip checksum was calculated for the
2574 * inner packet and that the sum passed for all segments
2575 * included in the aggregation.
2577 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2579 * This indicates that the TCP, UDP or ICMP checksum was
2580 * calculated for the inner packet and that the sum passed
2581 * for all segments included in the aggregation.
2583 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2585 * This indicates that the ip checksum was calculated for the
2586 * tunnel header and that the sum passed for all segments
2587 * included in the aggregation.
2589 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2591 * This indicates that the UDP checksum was
2592 * calculated for the tunnel packet and that the sum passed for
2593 * all segments included in the aggregation.
2595 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2596 /* This value indicates what format the metadata field is. */
2597 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2598 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
2599 /* No metadata informtaion. Value is zero. */
2600 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
2601 (UINT32_C(0x0) << 4)
2603 * The metadata field contains the VLAN tag and TPID value.
2604 * - metadata[11:0] contains the vlan VID value.
2605 * - metadata[12] contains the vlan DE value.
2606 * - metadata[15:13] contains the vlan PRI value.
2607 * - metadata[31:16] contains the vlan TPID value.
2609 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
2610 (UINT32_C(0x1) << 4)
2611 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
2612 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
2614 * This field indicates the IP type for the inner-most IP header.
2615 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2617 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2619 * This is data from the CFA block as indicated by the meta_format
2623 /* When meta_format=1, this value is the VLAN VID. */
2624 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2625 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
2626 /* When meta_format=1, this value is the VLAN DE. */
2627 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
2628 /* When meta_format=1, this value is the VLAN PRI. */
2629 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2630 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
2631 /* When meta_format=1, this value is the VLAN TPID. */
2632 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2633 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
2636 * This value is written by the NIC such that it will be different
2637 * for each pass through the completion queue. The even passes
2638 * will write 1. The odd passes will write 0.
2640 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
2642 * This field identifies the CFA action rule that was used for this
2647 * This is the size in bytes of the inner most L4 header.
2648 * This can be subtracted from the payload_offset to determine
2649 * the start of the inner most L4 header.
2651 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
2653 * This is the offset from the beginning of the packet in bytes for
2654 * the outer L3 header. If there is no outer L3 header, then this
2657 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
2658 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
2660 * This is the offset from the beginning of the packet in bytes for
2661 * the inner most L2 header.
2663 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
2664 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
2666 * This is the offset from the beginning of the packet in bytes for
2667 * the inner most L3 header.
2669 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
2670 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
2672 * This is the size in bytes of the inner most L4 header.
2673 * This can be subtracted from the payload_offset to determine
2674 * the start of the inner most L4 header.
2676 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
2677 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
2678 } __attribute__((packed));
2680 /* rx_tpa_end_cmpl (size:128b/16B) */
2681 struct rx_tpa_end_cmpl {
2682 uint16_t flags_type;
2684 * This field indicates the exact type of the completion.
2685 * By convention, the LSB identifies the length of the
2686 * record in 16B units. Even values indicate 16B
2687 * records. Odd values indicate 32B
2690 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
2691 #define RX_TPA_END_CMPL_TYPE_SFT 0
2693 * RX L2 TPA End Completion:
2694 * Completion at the end of a TPA operation.
2697 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
2698 #define RX_TPA_END_CMPL_TYPE_LAST \
2699 RX_TPA_END_CMPL_TYPE_RX_TPA_END
2700 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2701 #define RX_TPA_END_CMPL_FLAGS_SFT 6
2703 * When this bit is '1', it indicates a packet that has an
2704 * error of some type. Type of error is indicated in
2707 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
2708 /* This field indicates how the packet was placed in the buffer. */
2709 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2710 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
2713 * TPA Packet was placed using jumbo algorithm. This means
2714 * that the first buffer will be filled with data before
2715 * moving to aggregation buffers. Each aggregation buffer
2716 * will be filled before moving to the next aggregation
2719 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
2720 (UINT32_C(0x1) << 7)
2722 * Header/Data Separation:
2723 * Packet was placed using Header/Data separation algorithm.
2724 * The separation location is indicated by the itype field.
2726 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
2727 (UINT32_C(0x2) << 7)
2730 * Packet will be placed using GRO/Jumbo where the first
2731 * packet is filled with data. Subsequent packets will be
2732 * placed such that any one packet does not span two
2733 * aggregation buffers unless it starts at the beginning of
2734 * an aggregation buffer.
2736 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2737 (UINT32_C(0x5) << 7)
2739 * GRO/Header-Data Separation:
2740 * Packet will be placed using GRO/HDS where the header
2741 * is in the first packet.
2742 * Payload of each packet will be
2743 * placed such that any one packet does not span two
2744 * aggregation buffers unless it starts at the beginning of
2745 * an aggregation buffer.
2747 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2748 (UINT32_C(0x6) << 7)
2749 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
2750 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
2752 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
2753 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
2755 * This value indicates what the inner packet determined for the
2758 * Indicates that the packet was IP and TCP. This indicates
2759 * that the ip_cs field is valid and that the tcp_udp_cs
2760 * field is valid and contains the TCP checksum.
2761 * This also indicates that the payload_offset field is valid.
2763 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2764 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
2766 * This value is zero for TPA End completions.
2767 * There is no data in the buffer that corresponds to the opaque
2768 * value in this completion.
2772 * This is a copy of the opaque field from the RX BD this completion
2777 * This value is written by the NIC such that it will be different
2778 * for each pass through the completion queue. The even passes
2779 * will write 1. The odd passes will write 0.
2781 uint8_t agg_bufs_v1;
2783 * This value is written by the NIC such that it will be different
2784 * for each pass through the completion queue. The even passes
2785 * will write 1. The odd passes will write 0.
2787 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
2789 * This value is the number of aggregation buffers that follow this
2790 * entry in the completion ring that are a part of this aggregation
2792 * If the value is zero, then the packet is completely contained
2793 * in the buffer space provided in the aggregation start completion.
2795 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
2796 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
2797 /* This value is the number of segments in the TPA operation. */
2800 * This value indicates the offset in bytes from the beginning of the packet
2801 * where the inner payload starts. This value is valid for TCP, UDP,
2802 * FCoE, and RoCE packets.
2804 * A value of zero indicates an offset of 256 bytes.
2806 uint8_t payload_offset;
2808 /* unused2 is 1 b */
2809 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
2811 * This is the aggregation ID that the completion is associated
2812 * with. Use this number to correlate the TPA start completion
2813 * with the TPA end completion.
2815 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
2816 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
2818 * For non-GRO packets, this value is the
2819 * timestamp delta between earliest and latest timestamp values for
2820 * TPA packet. If packets were not time stamped, then delta will be
2823 * For GRO packets, this field is zero except for the following
2826 * Timestamp present indication. When '0', no Timestamp
2827 * option is in the packet. When '1', then a Timestamp
2828 * option is present in the packet.
2831 } __attribute__((packed));
2833 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
2834 struct rx_tpa_end_cmpl_hi {
2836 * This value is the number of duplicate ACKs that have been
2837 * received as part of the TPA operation.
2839 uint32_t tpa_dup_acks;
2841 * This value is the number of duplicate ACKs that have been
2842 * received as part of the TPA operation.
2844 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
2845 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
2847 * This value is the valid when TPA completion is active. It
2848 * indicates the length of the longest segment of the TPA operation
2849 * for LRO mode and the length of the first segment in GRO mode.
2851 * This value may be used by GRO software to re-construct the original
2852 * packet stream from the TPA packet. This is the length of all
2853 * but the last segment for GRO. In LRO mode this value may be used
2854 * to indicate MSS size to the stack.
2856 uint16_t tpa_seg_len;
2857 /* unused4 is 16 b */
2861 * This value is written by the NIC such that it will be different
2862 * for each pass through the completion queue. The even passes
2863 * will write 1. The odd passes will write 0.
2865 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
2866 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2867 #define RX_TPA_END_CMPL_ERRORS_SFT 1
2869 * This error indicates that there was some sort of problem with
2870 * the BDs for the packet that was found after part of the
2871 * packet was already placed. The packet should be treated as
2874 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2875 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2877 * This error occurs when there is a fatal HW problem in
2878 * the chip only. It indicates that there were not
2879 * BDs on chip but that there was adequate reservation.
2880 * provided by the TPA block.
2882 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2883 (UINT32_C(0x2) << 1)
2885 * This error occurs when TPA block was not configured to
2886 * reserve adequate BDs for TPA operations on this RX
2887 * ring. All data for the TPA operation was not placed.
2889 * This error can also be generated when the number of
2890 * segments is not programmed correctly in TPA and the
2891 * 33 total aggregation buffers allowed for the TPA
2892 * operation has been exceeded.
2894 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
2895 (UINT32_C(0x4) << 1)
2896 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
2897 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
2898 /* unused5 is 16 b */
2901 * This is the opaque value that was completed for the TPA start
2902 * completion that corresponds to this TPA end completion.
2904 uint32_t start_opaque;
2905 } __attribute__((packed));
2907 /* rx_abuf_cmpl (size:128b/16B) */
2908 struct rx_abuf_cmpl {
2911 * This field indicates the exact type of the completion.
2912 * By convention, the LSB identifies the length of the
2913 * record in 16B units. Even values indicate 16B
2914 * records. Odd values indicate 32B
2917 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
2918 #define RX_ABUF_CMPL_TYPE_SFT 0
2920 * RX Aggregation Buffer completion :
2921 * Completion of an L2 aggregation buffer in support of
2922 * TPA, HDS, or Jumbo packet completion. Length = 16B
2924 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
2925 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
2927 * This is the length of the data for the packet stored in this
2928 * aggregation buffer identified by the opaque value. This does not
2929 * include the length of any
2930 * data placed in other aggregation BDs or in the packet or buffer
2931 * BDs. This length does not include any space added due to
2932 * hdr_offset register during HDS placement mode.
2936 * This is a copy of the opaque field from the RX BD this aggregation
2937 * buffer corresponds to.
2942 * This value is written by the NIC such that it will be different
2943 * for each pass through the completion queue. The even passes
2944 * will write 1. The odd passes will write 0.
2946 #define RX_ABUF_CMPL_V UINT32_C(0x1)
2947 /* unused3 is 32 b */
2949 } __attribute__((packed));
2951 /* eject_cmpl (size:128b/16B) */
2955 * This field indicates the exact type of the completion.
2956 * By convention, the LSB identifies the length of the
2957 * record in 16B units. Even values indicate 16B
2958 * records. Odd values indicate 32B
2961 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
2962 #define EJECT_CMPL_TYPE_SFT 0
2964 * Statistics Ejection Completion:
2965 * Completion of statistics data ejection buffer.
2968 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
2969 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
2971 * This is the length of the statistics data stored in this
2976 * This is a copy of the opaque field from the RX BD this ejection
2977 * buffer corresponds to.
2982 * This value is written by the NIC such that it will be different
2983 * for each pass through the completion queue. The even passes
2984 * will write 1. The odd passes will write 0.
2986 #define EJECT_CMPL_V UINT32_C(0x1)
2987 /* unused3 is 32 b */
2989 } __attribute__((packed));
2991 /* hwrm_cmpl (size:128b/16B) */
2995 * This field indicates the exact type of the completion.
2996 * By convention, the LSB identifies the length of the
2997 * record in 16B units. Even values indicate 16B
2998 * records. Odd values indicate 32B
3001 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3002 #define HWRM_CMPL_TYPE_SFT 0
3004 * HWRM Command Completion:
3005 * Completion of an HWRM command.
3007 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3008 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3009 /* This is the sequence_id of the HWRM command that has completed. */
3010 uint16_t sequence_id;
3011 /* unused2 is 32 b */
3015 * This value is written by the NIC such that it will be different
3016 * for each pass through the completion queue. The even passes
3017 * will write 1. The odd passes will write 0.
3019 #define HWRM_CMPL_V UINT32_C(0x1)
3020 /* unused4 is 32 b */
3022 } __attribute__((packed));
3024 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3025 struct hwrm_fwd_req_cmpl {
3027 * This field indicates the exact type of the completion.
3028 * By convention, the LSB identifies the length of the
3029 * record in 16B units. Even values indicate 16B
3030 * records. Odd values indicate 32B
3033 uint16_t req_len_type;
3035 * This field indicates the exact type of the completion.
3036 * By convention, the LSB identifies the length of the
3037 * record in 16B units. Even values indicate 16B
3038 * records. Odd values indicate 32B
3041 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3042 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3043 /* Forwarded HWRM Request */
3044 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3045 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3046 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3047 /* Length of forwarded request in bytes. */
3048 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3049 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3051 * Source ID of this request.
3052 * Typically used in forwarding requests and responses.
3053 * 0x0 - 0xFFF8 - Used for function ids
3054 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3058 /* unused1 is 32 b */
3060 /* Address of forwarded request. */
3061 uint32_t req_buf_addr_v[2];
3063 * This value is written by the NIC such that it will be different
3064 * for each pass through the completion queue. The even passes
3065 * will write 1. The odd passes will write 0.
3067 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3068 /* Address of forwarded request. */
3069 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3070 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3071 } __attribute__((packed));
3073 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3074 struct hwrm_fwd_resp_cmpl {
3077 * This field indicates the exact type of the completion.
3078 * By convention, the LSB identifies the length of the
3079 * record in 16B units. Even values indicate 16B
3080 * records. Odd values indicate 32B
3083 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3084 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3085 /* Forwarded HWRM Response */
3086 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3087 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3088 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3090 * Source ID of this response.
3091 * Typically used in forwarding requests and responses.
3092 * 0x0 - 0xFFF8 - Used for function ids
3093 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3097 /* Length of forwarded response in bytes. */
3099 /* unused2 is 16 b */
3101 /* Address of forwarded request. */
3102 uint32_t resp_buf_addr_v[2];
3104 * This value is written by the NIC such that it will be different
3105 * for each pass through the completion queue. The even passes
3106 * will write 1. The odd passes will write 0.
3108 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3109 /* Address of forwarded request. */
3110 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3111 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3112 } __attribute__((packed));
3114 /* hwrm_async_event_cmpl (size:128b/16B) */
3115 struct hwrm_async_event_cmpl {
3118 * This field indicates the exact type of the completion.
3119 * By convention, the LSB identifies the length of the
3120 * record in 16B units. Even values indicate 16B
3121 * records. Odd values indicate 32B
3124 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3125 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3126 /* HWRM Asynchronous Event Information */
3127 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3128 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3129 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3130 /* Identifiers of events. */
3132 /* Link status changed */
3133 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3135 /* Link MTU changed */
3136 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3138 /* Link speed changed */
3139 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3141 /* DCB Configuration changed */
3142 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3144 /* Port connection not allowed */
3145 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3147 /* Link speed configuration was not allowed */
3148 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3150 /* Link speed configuration change */
3151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3153 /* Port PHY configuration change */
3154 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3156 /* Function driver unloaded */
3157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3159 /* Function driver loaded */
3160 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3162 /* Function FLR related processing has completed */
3163 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3165 /* PF driver unloaded */
3166 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3168 /* PF driver loaded */
3169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3171 /* VF Function Level Reset (FLR) */
3172 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3174 /* VF MAC Address Change */
3175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3177 /* PF-VF communication channel status change. */
3178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3180 /* VF Configuration Change */
3181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3183 /* LLFC/PFC Configuration Change */
3184 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3187 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3189 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3190 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3191 /* Event specific data */
3192 uint32_t event_data2;
3195 * This value is written by the NIC such that it will be different
3196 * for each pass through the completion queue. The even passes
3197 * will write 1. The odd passes will write 0.
3199 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3201 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3202 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3203 /* 8-lsb timestamp from POR (100-msec resolution) */
3204 uint8_t timestamp_lo;
3205 /* 16-lsb timestamp from POR (100-msec resolution) */
3206 uint16_t timestamp_hi;
3207 /* Event specific data */
3208 uint32_t event_data1;
3209 } __attribute__((packed));
3211 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3212 struct hwrm_async_event_cmpl_link_status_change {
3215 * This field indicates the exact type of the completion.
3216 * By convention, the LSB identifies the length of the
3217 * record in 16B units. Even values indicate 16B
3218 * records. Odd values indicate 32B
3221 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3223 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3224 /* HWRM Asynchronous Event Information */
3225 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3227 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3228 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3229 /* Identifiers of events. */
3231 /* Link status changed */
3232 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3234 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3235 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3236 /* Event specific data */
3237 uint32_t event_data2;
3240 * This value is written by the NIC such that it will be different
3241 * for each pass through the completion queue. The even passes
3242 * will write 1. The odd passes will write 0.
3244 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3247 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3249 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3250 /* 8-lsb timestamp from POR (100-msec resolution) */
3251 uint8_t timestamp_lo;
3252 /* 16-lsb timestamp from POR (100-msec resolution) */
3253 uint16_t timestamp_hi;
3254 /* Event specific data */
3255 uint32_t event_data1;
3256 /* Indicates link status change */
3257 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3260 * If this bit set to 0, then it indicates that the link
3261 * was up and it went down.
3263 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3266 * If this bit is set to 1, then it indicates that the link
3267 * was down and it went up.
3269 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3271 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3272 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3273 /* Indicates the physical port this link status change occur */
3274 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3276 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3279 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3281 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3283 } __attribute__((packed));
3285 /*******************
3287 *******************/
3290 /* hwrm_func_reset_input (size:192b/24B) */
3291 struct hwrm_func_reset_input {
3292 /* The HWRM command request type. */
3295 * The completion ring to send the completion event on. This should
3296 * be the NQ ID returned from the `nq_alloc` HWRM command.
3300 * The sequence ID is used by the driver for tracking multiple
3301 * commands. This ID is treated as opaque data by the firmware and
3302 * the value is returned in the `hwrm_resp_hdr` upon completion.
3306 * The target ID of the command:
3307 * * 0x0-0xFFF8 - The function ID
3308 * * 0xFFF8-0xFFFE - Reserved for internal processors
3313 * A physical address pointer pointing to a host buffer that the
3314 * command's response data will be written. This can be either a host
3315 * physical address (HPA) or a guest physical address (GPA) and must
3316 * point to a physically contiguous block of memory.
3321 * This bit must be '1' for the vf_id_valid field to be
3324 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
3326 * The ID of the VF that this PF is trying to reset.
3327 * Only the parent PF shall be allowed to reset a child VF.
3329 * A parent PF driver shall use this field only when a specific child VF
3330 * is requested to be reset.
3333 /* This value indicates the level of a function reset. */
3334 uint8_t func_reset_level;
3336 * Reset the caller function and its children VFs (if any). If no
3337 * children functions exist, then reset the caller function only.
3339 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
3341 /* Reset the caller function only */
3342 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
3345 * Reset all children VFs of the caller function driver if the
3346 * caller is a PF driver.
3347 * It is an error to specify this level by a VF driver.
3348 * It is an error to specify this level by a PF driver with
3351 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
3354 * Reset a specific VF of the caller function driver if the caller
3355 * is the parent PF driver.
3356 * It is an error to specify this level by a VF driver.
3357 * It is an error to specify this level by a PF driver that is not
3358 * the parent of the VF that is being requested to reset.
3360 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
3362 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
3363 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
3365 } __attribute__((packed));
3367 /* hwrm_func_reset_output (size:128b/16B) */
3368 struct hwrm_func_reset_output {
3369 /* The specific error status for the command. */
3370 uint16_t error_code;
3371 /* The HWRM command request type. */
3373 /* The sequence ID from the original command. */
3375 /* The length of the response data in number of bytes. */
3377 uint8_t unused_0[7];
3379 * This field is used in Output records to indicate that the output
3380 * is completely written to RAM. This field should be read as '1'
3381 * to indicate that the output has been completely written.
3382 * When writing a command completion or response to an internal processor,
3383 * the order of writes has to be such that this field is written last.
3386 } __attribute__((packed));
3388 /********************
3389 * hwrm_func_getfid *
3390 ********************/
3393 /* hwrm_func_getfid_input (size:192b/24B) */
3394 struct hwrm_func_getfid_input {
3395 /* The HWRM command request type. */
3398 * The completion ring to send the completion event on. This should
3399 * be the NQ ID returned from the `nq_alloc` HWRM command.
3403 * The sequence ID is used by the driver for tracking multiple
3404 * commands. This ID is treated as opaque data by the firmware and
3405 * the value is returned in the `hwrm_resp_hdr` upon completion.
3409 * The target ID of the command:
3410 * * 0x0-0xFFF8 - The function ID
3411 * * 0xFFF8-0xFFFE - Reserved for internal processors
3416 * A physical address pointer pointing to a host buffer that the
3417 * command's response data will be written. This can be either a host
3418 * physical address (HPA) or a guest physical address (GPA) and must
3419 * point to a physically contiguous block of memory.
3424 * This bit must be '1' for the pci_id field to be
3427 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
3429 * This value is the PCI ID of the queried function.
3430 * If ARI is enabled, then it is
3431 * Bus Number (8b):Function Number(8b). Otherwise, it is
3432 * Bus Number (8b):Device Number (5b):Function Number(3b).
3435 uint8_t unused_0[2];
3436 } __attribute__((packed));
3438 /* hwrm_func_getfid_output (size:128b/16B) */
3439 struct hwrm_func_getfid_output {
3440 /* The specific error status for the command. */
3441 uint16_t error_code;
3442 /* The HWRM command request type. */
3444 /* The sequence ID from the original command. */
3446 /* The length of the response data in number of bytes. */
3449 * FID value. This value is used to identify operations on the PCI
3450 * bus as belonging to a particular PCI function.
3453 uint8_t unused_0[5];
3455 * This field is used in Output records to indicate that the output
3456 * is completely written to RAM. This field should be read as '1'
3457 * to indicate that the output has been completely written.
3458 * When writing a command completion or response to an internal processor,
3459 * the order of writes has to be such that this field is written last.
3462 } __attribute__((packed));
3464 /**********************
3465 * hwrm_func_vf_alloc *
3466 **********************/
3469 /* hwrm_func_vf_alloc_input (size:192b/24B) */
3470 struct hwrm_func_vf_alloc_input {
3471 /* The HWRM command request type. */
3474 * The completion ring to send the completion event on. This should
3475 * be the NQ ID returned from the `nq_alloc` HWRM command.
3479 * The sequence ID is used by the driver for tracking multiple
3480 * commands. This ID is treated as opaque data by the firmware and
3481 * the value is returned in the `hwrm_resp_hdr` upon completion.
3485 * The target ID of the command:
3486 * * 0x0-0xFFF8 - The function ID
3487 * * 0xFFF8-0xFFFE - Reserved for internal processors
3492 * A physical address pointer pointing to a host buffer that the
3493 * command's response data will be written. This can be either a host
3494 * physical address (HPA) or a guest physical address (GPA) and must
3495 * point to a physically contiguous block of memory.
3500 * This bit must be '1' for the first_vf_id field to be
3503 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
3505 * This value is used to identify a Virtual Function (VF).
3506 * The scope of VF ID is local within a PF.
3508 uint16_t first_vf_id;
3509 /* The number of virtual functions requested. */
3511 } __attribute__((packed));
3513 /* hwrm_func_vf_alloc_output (size:128b/16B) */
3514 struct hwrm_func_vf_alloc_output {
3515 /* The specific error status for the command. */
3516 uint16_t error_code;
3517 /* The HWRM command request type. */
3519 /* The sequence ID from the original command. */
3521 /* The length of the response data in number of bytes. */
3523 /* The ID of the first VF allocated. */
3524 uint16_t first_vf_id;
3525 uint8_t unused_0[5];
3527 * This field is used in Output records to indicate that the output
3528 * is completely written to RAM. This field should be read as '1'
3529 * to indicate that the output has been completely written.
3530 * When writing a command completion or response to an internal processor,
3531 * the order of writes has to be such that this field is written last.
3534 } __attribute__((packed));
3536 /*********************
3537 * hwrm_func_vf_free *
3538 *********************/
3541 /* hwrm_func_vf_free_input (size:192b/24B) */
3542 struct hwrm_func_vf_free_input {
3543 /* The HWRM command request type. */
3546 * The completion ring to send the completion event on. This should
3547 * be the NQ ID returned from the `nq_alloc` HWRM command.
3551 * The sequence ID is used by the driver for tracking multiple
3552 * commands. This ID is treated as opaque data by the firmware and
3553 * the value is returned in the `hwrm_resp_hdr` upon completion.
3557 * The target ID of the command:
3558 * * 0x0-0xFFF8 - The function ID
3559 * * 0xFFF8-0xFFFE - Reserved for internal processors
3564 * A physical address pointer pointing to a host buffer that the
3565 * command's response data will be written. This can be either a host
3566 * physical address (HPA) or a guest physical address (GPA) and must
3567 * point to a physically contiguous block of memory.
3572 * This bit must be '1' for the first_vf_id field to be
3575 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
3577 * This value is used to identify a Virtual Function (VF).
3578 * The scope of VF ID is local within a PF.
3580 uint16_t first_vf_id;
3582 * The number of virtual functions requested.
3583 * 0xFFFF - Cleanup all children of this PF.
3586 } __attribute__((packed));
3588 /* hwrm_func_vf_free_output (size:128b/16B) */
3589 struct hwrm_func_vf_free_output {
3590 /* The specific error status for the command. */
3591 uint16_t error_code;
3592 /* The HWRM command request type. */
3594 /* The sequence ID from the original command. */
3596 /* The length of the response data in number of bytes. */
3598 uint8_t unused_0[7];
3600 * This field is used in Output records to indicate that the output
3601 * is completely written to RAM. This field should be read as '1'
3602 * to indicate that the output has been completely written.
3603 * When writing a command completion or response to an internal processor,
3604 * the order of writes has to be such that this field is written last.
3607 } __attribute__((packed));
3609 /********************
3610 * hwrm_func_vf_cfg *
3611 ********************/
3614 /* hwrm_func_vf_cfg_input (size:448b/56B) */
3615 struct hwrm_func_vf_cfg_input {
3616 /* The HWRM command request type. */
3619 * The completion ring to send the completion event on. This should
3620 * be the NQ ID returned from the `nq_alloc` HWRM command.
3624 * The sequence ID is used by the driver for tracking multiple
3625 * commands. This ID is treated as opaque data by the firmware and
3626 * the value is returned in the `hwrm_resp_hdr` upon completion.
3630 * The target ID of the command:
3631 * * 0x0-0xFFF8 - The function ID
3632 * * 0xFFF8-0xFFFE - Reserved for internal processors
3637 * A physical address pointer pointing to a host buffer that the
3638 * command's response data will be written. This can be either a host
3639 * physical address (HPA) or a guest physical address (GPA) and must
3640 * point to a physically contiguous block of memory.
3645 * This bit must be '1' for the mtu field to be
3648 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
3651 * This bit must be '1' for the guest_vlan field to be
3654 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
3657 * This bit must be '1' for the async_event_cr field to be
3660 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
3663 * This bit must be '1' for the dflt_mac_addr field to be
3666 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
3669 * This bit must be '1' for the num_rsscos_ctxs field to be
3672 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
3675 * This bit must be '1' for the num_cmpl_rings field to be
3678 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
3681 * This bit must be '1' for the num_tx_rings field to be
3684 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
3687 * This bit must be '1' for the num_rx_rings field to be
3690 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
3693 * This bit must be '1' for the num_l2_ctxs field to be
3696 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
3699 * This bit must be '1' for the num_vnics field to be
3702 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
3705 * This bit must be '1' for the num_stat_ctxs field to be
3708 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
3711 * This bit must be '1' for the num_hw_ring_grps field to be
3714 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
3717 * The maximum transmission unit requested on the function.
3718 * The HWRM should make sure that the mtu of
3719 * the function does not exceed the mtu of the physical
3720 * port that this function is associated with.
3722 * In addition to requesting mtu per function, it is
3723 * possible to configure mtu per transmit ring.
3724 * By default, the mtu of each transmit ring associated
3725 * with a function is equal to the mtu of the function.
3726 * The HWRM should make sure that the mtu of each transmit
3727 * ring that is assigned to a function has a valid mtu.
3731 * The guest VLAN for the function being configured.
3732 * This field's format is same as 802.1Q Tag's
3733 * Tag Control Information (TCI) format that includes both
3734 * Priority Code Point (PCP) and VLAN Identifier (VID).
3736 uint16_t guest_vlan;
3738 * ID of the target completion ring for receiving asynchronous
3739 * event completions. If this field is not valid, then the
3740 * HWRM shall use the default completion ring of the function
3741 * that is being configured as the target completion ring for
3742 * providing any asynchronous event completions for that
3744 * If this field is valid, then the HWRM shall use the
3745 * completion ring identified by this ID as the target
3746 * completion ring for providing any asynchronous event
3747 * completions for the function that is being configured.
3749 uint16_t async_event_cr;
3751 * This value is the current MAC address requested by the VF
3752 * driver to be configured on this VF. A value of
3753 * 00-00-00-00-00-00 indicates no MAC address configuration
3754 * is requested by the VF driver.
3755 * The parent PF driver may reject or overwrite this
3758 uint8_t dflt_mac_addr[6];
3761 * This bit requests that the firmware test to see if all the assets
3762 * requested in this command (i.e. number of TX rings) are available.
3763 * The firmware will return an error if the requested assets are
3764 * not available. The firwmare will NOT reserve the assets if they
3767 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
3770 * This bit requests that the firmware test to see if all the assets
3771 * requested in this command (i.e. number of RX rings) are available.
3772 * The firmware will return an error if the requested assets are
3773 * not available. The firwmare will NOT reserve the assets if they
3776 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
3779 * This bit requests that the firmware test to see if all the assets
3780 * requested in this command (i.e. number of CMPL rings) are available.
3781 * The firmware will return an error if the requested assets are
3782 * not available. The firwmare will NOT reserve the assets if they
3785 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
3788 * This bit requests that the firmware test to see if all the assets
3789 * requested in this command (i.e. number of RSS ctx) are available.
3790 * The firmware will return an error if the requested assets are
3791 * not available. The firwmare will NOT reserve the assets if they
3794 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
3797 * This bit requests that the firmware test to see if all the assets
3798 * requested in this command (i.e. number of ring groups) are available.
3799 * The firmware will return an error if the requested assets are
3800 * not available. The firwmare will NOT reserve the assets if they
3803 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
3806 * This bit requests that the firmware test to see if all the assets
3807 * requested in this command (i.e. number of stat ctx) are available.
3808 * The firmware will return an error if the requested assets are
3809 * not available. The firwmare will NOT reserve the assets if they
3812 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
3815 * This bit requests that the firmware test to see if all the assets
3816 * requested in this command (i.e. number of VNICs) are available.
3817 * The firmware will return an error if the requested assets are
3818 * not available. The firwmare will NOT reserve the assets if they
3821 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
3824 * This bit requests that the firmware test to see if all the assets
3825 * requested in this command (i.e. number of L2 ctx) are available.
3826 * The firmware will return an error if the requested assets are
3827 * not available. The firwmare will NOT reserve the assets if they
3830 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
3832 /* The number of RSS/COS contexts requested for the VF. */
3833 uint16_t num_rsscos_ctxs;
3834 /* The number of completion rings requested for the VF. */
3835 uint16_t num_cmpl_rings;
3836 /* The number of transmit rings requested for the VF. */
3837 uint16_t num_tx_rings;
3838 /* The number of receive rings requested for the VF. */
3839 uint16_t num_rx_rings;
3840 /* The number of L2 contexts requested for the VF. */
3841 uint16_t num_l2_ctxs;
3842 /* The number of vnics requested for the VF. */
3844 /* The number of statistic contexts requested for the VF. */
3845 uint16_t num_stat_ctxs;
3846 /* The number of HW ring groups requested for the VF. */
3847 uint16_t num_hw_ring_grps;
3848 uint8_t unused_0[4];
3849 } __attribute__((packed));
3851 /* hwrm_func_vf_cfg_output (size:128b/16B) */
3852 struct hwrm_func_vf_cfg_output {
3853 /* The specific error status for the command. */
3854 uint16_t error_code;
3855 /* The HWRM command request type. */
3857 /* The sequence ID from the original command. */
3859 /* The length of the response data in number of bytes. */
3861 uint8_t unused_0[7];
3863 * This field is used in Output records to indicate that the output
3864 * is completely written to RAM. This field should be read as '1'
3865 * to indicate that the output has been completely written.
3866 * When writing a command completion or response to an internal processor,
3867 * the order of writes has to be such that this field is written last.
3870 } __attribute__((packed));
3872 /*******************
3874 *******************/
3877 /* hwrm_func_qcaps_input (size:192b/24B) */
3878 struct hwrm_func_qcaps_input {
3879 /* The HWRM command request type. */
3882 * The completion ring to send the completion event on. This should
3883 * be the NQ ID returned from the `nq_alloc` HWRM command.
3887 * The sequence ID is used by the driver for tracking multiple
3888 * commands. This ID is treated as opaque data by the firmware and
3889 * the value is returned in the `hwrm_resp_hdr` upon completion.
3893 * The target ID of the command:
3894 * * 0x0-0xFFF8 - The function ID
3895 * * 0xFFF8-0xFFFE - Reserved for internal processors
3900 * A physical address pointer pointing to a host buffer that the
3901 * command's response data will be written. This can be either a host
3902 * physical address (HPA) or a guest physical address (GPA) and must
3903 * point to a physically contiguous block of memory.
3907 * Function ID of the function that is being queried.
3908 * 0xFF... (All Fs) if the query is for the requesting
3912 uint8_t unused_0[6];
3913 } __attribute__((packed));
3915 /* hwrm_func_qcaps_output (size:640b/80B) */
3916 struct hwrm_func_qcaps_output {
3917 /* The specific error status for the command. */
3918 uint16_t error_code;
3919 /* The HWRM command request type. */
3921 /* The sequence ID from the original command. */
3923 /* The length of the response data in number of bytes. */
3926 * FID value. This value is used to identify operations on the PCI
3927 * bus as belonging to a particular PCI function.
3931 * Port ID of port that this function is associated with.
3932 * Valid only for the PF.
3933 * 0xFF... (All Fs) if this function is not associated with
3935 * 0xFF... (All Fs) if this function is called from a VF.
3939 /* If 1, then Push mode is supported on this function. */
3940 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
3943 * If 1, then the global MSI-X auto-masking is enabled for the
3946 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
3949 * If 1, then the Precision Time Protocol (PTP) processing
3950 * is supported on this function.
3951 * The HWRM should enable PTP on only a single Physical
3952 * Function (PF) per port.
3954 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
3957 * If 1, then RDMA over Converged Ethernet (RoCE) v1
3958 * is supported on this function.
3960 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
3963 * If 1, then RDMA over Converged Ethernet (RoCE) v2
3964 * is supported on this function.
3966 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
3969 * If 1, then control and configuration of WoL magic packet
3970 * are supported on this function.
3972 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
3975 * If 1, then control and configuration of bitmap pattern
3976 * packet are supported on this function.
3978 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
3981 * If set to 1, then the control and configuration of rate limit
3982 * of an allocated TX ring on the queried function is supported.
3984 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
3987 * If 1, then control and configuration of minimum and
3988 * maximum bandwidths are supported on the queried function.
3990 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
3993 * If the query is for a VF, then this flag shall be ignored.
3994 * If this query is for a PF and this flag is set to 1,
3995 * then the PF has the capability to set the rate limits
3996 * on the TX rings of its children VFs.
3997 * If this query is for a PF and this flag is set to 0, then
3998 * the PF does not have the capability to set the rate limits
3999 * on the TX rings of its children VFs.
4001 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
4004 * If the query is for a VF, then this flag shall be ignored.
4005 * If this query is for a PF and this flag is set to 1,
4006 * then the PF has the capability to set the minimum and/or
4007 * maximum bandwidths for its children VFs.
4008 * If this query is for a PF and this flag is set to 0, then
4009 * the PF does not have the capability to set the minimum or
4010 * maximum bandwidths for its children VFs.
4012 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
4015 * Standard TX Ring mode is used for the allocation of TX ring
4016 * and underlying scheduling resources that allow bandwidth
4017 * reservation and limit settings on the queried function.
4018 * If set to 1, then standard TX ring mode is supported
4019 * on the queried function.
4020 * If set to 0, then standard TX ring mode is not available
4021 * on the queried function.
4023 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
4026 * If the query is for a VF, then this flag shall be ignored,
4027 * If this query is for a PF and this flag is set to 1,
4028 * then the PF has the capability to detect GENEVE tunnel
4031 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
4034 * If the query is for a VF, then this flag shall be ignored,
4035 * If this query is for a PF and this flag is set to 1,
4036 * then the PF has the capability to detect NVGRE tunnel
4039 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
4042 * If the query is for a VF, then this flag shall be ignored,
4043 * If this query is for a PF and this flag is set to 1,
4044 * then the PF has the capability to detect GRE tunnel
4047 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
4050 * If the query is for a VF, then this flag shall be ignored,
4051 * If this query is for a PF and this flag is set to 1,
4052 * then the PF has the capability to detect MPLS tunnel
4055 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
4058 * If the query is for a VF, then this flag shall be ignored,
4059 * If this query is for a PF and this flag is set to 1,
4060 * then the PF has the capability to support pcie stats.
4062 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
4065 * This value is current MAC address configured for this
4066 * function. A value of 00-00-00-00-00-00 indicates no
4067 * MAC address is currently configured.
4069 uint8_t mac_address[6];
4071 * The maximum number of RSS/COS contexts that can be
4072 * allocated to the function.
4074 uint16_t max_rsscos_ctx;
4076 * The maximum number of completion rings that can be
4077 * allocated to the function.
4079 uint16_t max_cmpl_rings;
4081 * The maximum number of transmit rings that can be
4082 * allocated to the function.
4084 uint16_t max_tx_rings;
4086 * The maximum number of receive rings that can be
4087 * allocated to the function.
4089 uint16_t max_rx_rings;
4091 * The maximum number of L2 contexts that can be
4092 * allocated to the function.
4094 uint16_t max_l2_ctxs;
4096 * The maximum number of VNICs that can be
4097 * allocated to the function.
4101 * The identifier for the first VF enabled on a PF. This
4102 * is valid only on the PF with SR-IOV enabled.
4103 * 0xFF... (All Fs) if this command is called on a PF with
4104 * SR-IOV disabled or on a VF.
4106 uint16_t first_vf_id;
4108 * The maximum number of VFs that can be
4109 * allocated to the function. This is valid only on the
4110 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
4111 * command is called on a PF with SR-IOV disabled or
4116 * The maximum number of statistic contexts that can be
4117 * allocated to the function.
4119 uint16_t max_stat_ctx;
4121 * The maximum number of Encapsulation records that can be
4122 * offloaded by this function.
4124 uint32_t max_encap_records;
4126 * The maximum number of decapsulation records that can
4127 * be offloaded by this function.
4129 uint32_t max_decap_records;
4131 * The maximum number of Exact Match (EM) flows that can be
4132 * offloaded by this function on the TX side.
4134 uint32_t max_tx_em_flows;
4136 * The maximum number of Wildcard Match (WM) flows that can
4137 * be offloaded by this function on the TX side.
4139 uint32_t max_tx_wm_flows;
4141 * The maximum number of Exact Match (EM) flows that can be
4142 * offloaded by this function on the RX side.
4144 uint32_t max_rx_em_flows;
4146 * The maximum number of Wildcard Match (WM) flows that can
4147 * be offloaded by this function on the RX side.
4149 uint32_t max_rx_wm_flows;
4151 * The maximum number of multicast filters that can
4152 * be supported by this function on the RX side.
4154 uint32_t max_mcast_filters;
4156 * The maximum value of flow_id that can be supported
4157 * in completion records.
4159 uint32_t max_flow_id;
4161 * The maximum number of HW ring groups that can be
4162 * supported on this function.
4164 uint32_t max_hw_ring_grps;
4166 * The maximum number of strict priority transmit rings
4167 * that can be allocated to the function.
4168 * This number indicates the maximum number of TX rings
4169 * that can be assigned strict priorities out of the
4170 * maximum number of TX rings that can be allocated
4171 * (max_tx_rings) to the function.
4173 uint16_t max_sp_tx_rings;
4176 * This field is used in Output records to indicate that the output
4177 * is completely written to RAM. This field should be read as '1'
4178 * to indicate that the output has been completely written.
4179 * When writing a command completion or response to an internal processor,
4180 * the order of writes has to be such that this field is written last.
4183 } __attribute__((packed));
4190 /* hwrm_func_qcfg_input (size:192b/24B) */
4191 struct hwrm_func_qcfg_input {
4192 /* The HWRM command request type. */
4195 * The completion ring to send the completion event on. This should
4196 * be the NQ ID returned from the `nq_alloc` HWRM command.
4200 * The sequence ID is used by the driver for tracking multiple
4201 * commands. This ID is treated as opaque data by the firmware and
4202 * the value is returned in the `hwrm_resp_hdr` upon completion.
4206 * The target ID of the command:
4207 * * 0x0-0xFFF8 - The function ID
4208 * * 0xFFF8-0xFFFE - Reserved for internal processors
4213 * A physical address pointer pointing to a host buffer that the
4214 * command's response data will be written. This can be either a host
4215 * physical address (HPA) or a guest physical address (GPA) and must
4216 * point to a physically contiguous block of memory.
4220 * Function ID of the function that is being queried.
4221 * 0xFF... (All Fs) if the query is for the requesting
4225 uint8_t unused_0[6];
4226 } __attribute__((packed));
4228 /* hwrm_func_qcfg_output (size:640b/80B) */
4229 struct hwrm_func_qcfg_output {
4230 /* The specific error status for the command. */
4231 uint16_t error_code;
4232 /* The HWRM command request type. */
4234 /* The sequence ID from the original command. */
4236 /* The length of the response data in number of bytes. */
4239 * FID value. This value is used to identify operations on the PCI
4240 * bus as belonging to a particular PCI function.
4244 * Port ID of port that this function is associated with.
4245 * 0xFF... (All Fs) if this function is not associated with
4250 * This value is the current VLAN setting for this
4251 * function. The value of 0 for this field indicates
4252 * no priority tagging or VLAN is used.
4253 * This field's format is same as 802.1Q Tag's
4254 * Tag Control Information (TCI) format that includes both
4255 * Priority Code Point (PCP) and VLAN Identifier (VID).
4260 * If 1, then magic packet based Out-Of-Box WoL is enabled on
4261 * the port associated with this function.
4263 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
4266 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
4267 * on the port associated with this function.
4269 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
4272 * If set to 1, then FW based DCBX agent is enabled and running on
4273 * the port associated with this function.
4274 * If set to 0, then DCBX agent is not running in the firmware.
4276 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
4279 * Standard TX Ring mode is used for the allocation of TX ring
4280 * and underlying scheduling resources that allow bandwidth
4281 * reservation and limit settings on the queried function.
4282 * If set to 1, then standard TX ring mode is enabled
4283 * on the queried function.
4284 * If set to 0, then the standard TX ring mode is disabled
4285 * on the queried function. In this extended TX ring resource
4286 * mode, the minimum and maximum bandwidth settings are not
4287 * supported to allow the allocation of TX rings to span multiple
4290 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
4293 * If set to 1 then FW based LLDP agent is enabled and running on
4294 * the port associated with this function.
4295 * If set to 0 then the LLDP agent is not running in the firmware.
4297 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
4300 * If set to 1, then multi-host mode is active for this function.
4301 * If set to 0, then multi-host mode is inactive for this function
4302 * or not applicable for this device.
4304 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
4307 * This value is current MAC address configured for this
4308 * function. A value of 00-00-00-00-00-00 indicates no
4309 * MAC address is currently configured.
4311 uint8_t mac_address[6];
4313 * This value is current PCI ID of this
4314 * function. If ARI is enabled, then it is
4315 * Bus Number (8b):Function Number(8b). Otherwise, it is
4316 * Bus Number (8b):Device Number (4b):Function Number(4b).
4317 * If multi-host mode is active, the 4 lsb will indicate
4318 * the PF index for this function.
4322 * The number of RSS/COS contexts currently
4323 * allocated to the function.
4325 uint16_t alloc_rsscos_ctx;
4327 * The number of completion rings currently allocated to
4328 * the function. This does not include the rings allocated
4329 * to any children functions if any.
4331 uint16_t alloc_cmpl_rings;
4333 * The number of transmit rings currently allocated to
4334 * the function. This does not include the rings allocated
4335 * to any children functions if any.
4337 uint16_t alloc_tx_rings;
4339 * The number of receive rings currently allocated to
4340 * the function. This does not include the rings allocated
4341 * to any children functions if any.
4343 uint16_t alloc_rx_rings;
4344 /* The allocated number of L2 contexts to the function. */
4345 uint16_t alloc_l2_ctx;
4346 /* The allocated number of vnics to the function. */
4347 uint16_t alloc_vnics;
4349 * The maximum transmission unit of the function.
4350 * For rings allocated on this function, this default
4351 * value is used if ring MTU is not specified.
4355 * The maximum receive unit of the function.
4356 * For vnics allocated on this function, this default
4357 * value is used if vnic MRU is not specified.
4360 /* The statistics context assigned to a function. */
4361 uint16_t stat_ctx_id;
4363 * The HWRM shall return Unknown value for this field
4364 * when this command is used to query VF's configuration.
4366 uint8_t port_partition_type;
4367 /* Single physical function */
4368 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
4369 /* Multiple physical functions */
4370 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
4371 /* Network Partitioning 1.0 */
4372 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
4373 /* Network Partitioning 1.5 */
4374 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
4375 /* Network Partitioning 2.0 */
4376 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
4378 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
4380 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
4381 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
4383 * This field will indicate number of physical functions on this port_partition.
4384 * HWRM shall return unavail (i.e. value of 0) for this field
4385 * when this command is used to query VF's configuration or
4386 * from older firmware that doesn't support this field.
4388 uint8_t port_pf_cnt;
4389 /* number of PFs is not available */
4390 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
4391 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
4392 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
4394 * The default VNIC ID assigned to a function that is
4397 uint16_t dflt_vnic_id;
4398 uint16_t max_mtu_configured;
4400 * Minimum BW allocated for this function.
4401 * The HWRM will translate this value into byte counter and
4402 * time interval used for the scheduler inside the device.
4403 * A value of 0 indicates the minimum bandwidth is not
4407 /* The bandwidth value. */
4408 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
4410 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
4411 /* The granularity of the value (bits or bytes). */
4412 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
4413 UINT32_C(0x10000000)
4414 /* Value is in bits. */
4415 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
4416 (UINT32_C(0x0) << 28)
4417 /* Value is in bytes. */
4418 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
4419 (UINT32_C(0x1) << 28)
4420 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
4421 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
4422 /* bw_value_unit is 3 b */
4423 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
4424 UINT32_C(0xe0000000)
4425 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
4426 /* Value is in Mb or MB (base 10). */
4427 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
4428 (UINT32_C(0x0) << 29)
4429 /* Value is in Kb or KB (base 10). */
4430 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
4431 (UINT32_C(0x2) << 29)
4432 /* Value is in bits or bytes. */
4433 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
4434 (UINT32_C(0x4) << 29)
4435 /* Value is in Gb or GB (base 10). */
4436 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
4437 (UINT32_C(0x6) << 29)
4438 /* Value is in 1/100th of a percentage of total bandwidth. */
4439 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
4440 (UINT32_C(0x1) << 29)
4442 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
4443 (UINT32_C(0x7) << 29)
4444 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
4445 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
4447 * Maximum BW allocated for this function.
4448 * The HWRM will translate this value into byte counter and
4449 * time interval used for the scheduler inside the device.
4450 * A value of 0 indicates that the maximum bandwidth is not
4454 /* The bandwidth value. */
4455 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
4457 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
4458 /* The granularity of the value (bits or bytes). */
4459 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
4460 UINT32_C(0x10000000)
4461 /* Value is in bits. */
4462 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
4463 (UINT32_C(0x0) << 28)
4464 /* Value is in bytes. */
4465 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
4466 (UINT32_C(0x1) << 28)
4467 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
4468 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
4469 /* bw_value_unit is 3 b */
4470 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
4471 UINT32_C(0xe0000000)
4472 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
4473 /* Value is in Mb or MB (base 10). */
4474 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
4475 (UINT32_C(0x0) << 29)
4476 /* Value is in Kb or KB (base 10). */
4477 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
4478 (UINT32_C(0x2) << 29)
4479 /* Value is in bits or bytes. */
4480 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
4481 (UINT32_C(0x4) << 29)
4482 /* Value is in Gb or GB (base 10). */
4483 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
4484 (UINT32_C(0x6) << 29)
4485 /* Value is in 1/100th of a percentage of total bandwidth. */
4486 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
4487 (UINT32_C(0x1) << 29)
4489 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
4490 (UINT32_C(0x7) << 29)
4491 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
4492 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
4494 * This value indicates the Edge virtual bridge mode for the
4495 * domain that this function belongs to.
4498 /* No Edge Virtual Bridging (EVB) */
4499 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
4500 /* Virtual Ethernet Bridge (VEB) */
4501 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
4502 /* Virtual Ethernet Port Aggregator (VEPA) */
4503 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
4504 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
4505 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
4508 * This value indicates the PCIE device cache line size.
4509 * The cache line size allows the DMA writes to terminate and
4510 * start at the cache boundary.
4512 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
4514 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
4515 /* Cache Line Size 64 bytes */
4516 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
4518 /* Cache Line Size 128 bytes */
4519 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
4521 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
4522 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
4523 /* Reserved for future. */
4524 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
4526 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2
4528 * The number of VFs that are allocated to the function.
4529 * This is valid only on the PF with SR-IOV enabled.
4530 * 0xFF... (All Fs) if this command is called on a PF with
4531 * SR-IOV disabled or on a VF.
4535 * The number of allocated multicast filters for this
4536 * function on the RX side.
4538 uint32_t alloc_mcast_filters;
4540 * The number of allocated HW ring groups for this
4543 uint32_t alloc_hw_ring_grps;
4545 * The number of strict priority transmit rings out of
4546 * currently allocated TX rings to the function
4549 uint16_t alloc_sp_tx_rings;
4551 * The number of statistics contexts
4552 * currently reserved for the function.
4554 uint16_t alloc_stat_ctx;
4556 * This field specifies how many NQs are reserved for the PF.
4557 * Remaining NQs that belong to the PF are available for VFs.
4558 * Once a PF has created VFs, it cannot change how many NQs are
4559 * reserved for itself (since the NQs must be contiguous in HW).
4561 uint16_t alloc_msix;
4562 uint8_t unused_2[5];
4564 * This field is used in Output records to indicate that the output
4565 * is completely written to RAM. This field should be read as '1'
4566 * to indicate that the output has been completely written.
4567 * When writing a command completion or response to an internal processor,
4568 * the order of writes has to be such that this field is written last.
4571 } __attribute__((packed));
4573 /***********************
4574 * hwrm_func_vlan_qcfg *
4575 ***********************/
4578 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
4579 struct hwrm_func_vlan_qcfg_input {
4580 /* The HWRM command request type. */
4583 * The completion ring to send the completion event on. This should
4584 * be the NQ ID returned from the `nq_alloc` HWRM command.
4588 * The sequence ID is used by the driver for tracking multiple
4589 * commands. This ID is treated as opaque data by the firmware and
4590 * the value is returned in the `hwrm_resp_hdr` upon completion.
4594 * The target ID of the command:
4595 * * 0x0-0xFFF8 - The function ID
4596 * * 0xFFF8-0xFFFE - Reserved for internal processors
4601 * A physical address pointer pointing to a host buffer that the
4602 * command's response data will be written. This can be either a host
4603 * physical address (HPA) or a guest physical address (GPA) and must
4604 * point to a physically contiguous block of memory.
4608 * Function ID of the function that is being
4610 * If set to 0xFF... (All Fs), then the configuration is
4611 * for the requesting function.
4614 uint8_t unused_0[6];
4615 } __attribute__((packed));
4617 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
4618 struct hwrm_func_vlan_qcfg_output {
4619 /* The specific error status for the command. */
4620 uint16_t error_code;
4621 /* The HWRM command request type. */
4623 /* The sequence ID from the original command. */
4625 /* The length of the response data in number of bytes. */
4627 uint8_t unused_0[7];
4629 * This field is used in Output records to indicate that the output
4630 * is completely written to RAM. This field should be read as '1'
4631 * to indicate that the output has been completely written.
4632 * When writing a command completion or response to an internal processor,
4633 * the order of writes has to be such that this field is written last.
4636 /* S-TAG VLAN identifier configured for the function. */
4638 /* S-TAG PCP value configured for the function. */
4642 * S-TAG TPID value configured for the function. This field is specified in
4643 * network byte order.
4646 /* C-TAG VLAN identifier configured for the function. */
4648 /* C-TAG PCP value configured for the function. */
4652 * C-TAG TPID value configured for the function. This field is specified in
4653 * network byte order.
4661 } __attribute__((packed));
4663 /**********************
4664 * hwrm_func_vlan_cfg *
4665 **********************/
4668 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
4669 struct hwrm_func_vlan_cfg_input {
4670 /* The HWRM command request type. */
4673 * The completion ring to send the completion event on. This should
4674 * be the NQ ID returned from the `nq_alloc` HWRM command.
4678 * The sequence ID is used by the driver for tracking multiple
4679 * commands. This ID is treated as opaque data by the firmware and
4680 * the value is returned in the `hwrm_resp_hdr` upon completion.
4684 * The target ID of the command:
4685 * * 0x0-0xFFF8 - The function ID
4686 * * 0xFFF8-0xFFFE - Reserved for internal processors
4691 * A physical address pointer pointing to a host buffer that the
4692 * command's response data will be written. This can be either a host
4693 * physical address (HPA) or a guest physical address (GPA) and must
4694 * point to a physically contiguous block of memory.
4698 * Function ID of the function that is being
4700 * If set to 0xFF... (All Fs), then the configuration is
4701 * for the requesting function.
4704 uint8_t unused_0[2];
4707 * This bit must be '1' for the stag_vid field to be
4710 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
4712 * This bit must be '1' for the ctag_vid field to be
4715 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
4717 * This bit must be '1' for the stag_pcp field to be
4720 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
4722 * This bit must be '1' for the ctag_pcp field to be
4725 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
4727 * This bit must be '1' for the stag_tpid field to be
4730 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
4732 * This bit must be '1' for the ctag_tpid field to be
4735 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
4736 /* S-TAG VLAN identifier configured for the function. */
4738 /* S-TAG PCP value configured for the function. */
4742 * S-TAG TPID value configured for the function. This field is specified in
4743 * network byte order.
4746 /* C-TAG VLAN identifier configured for the function. */
4748 /* C-TAG PCP value configured for the function. */
4752 * C-TAG TPID value configured for the function. This field is specified in
4753 * network byte order.
4760 uint8_t unused_3[4];
4761 } __attribute__((packed));
4763 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
4764 struct hwrm_func_vlan_cfg_output {
4765 /* The specific error status for the command. */
4766 uint16_t error_code;
4767 /* The HWRM command request type. */
4769 /* The sequence ID from the original command. */
4771 /* The length of the response data in number of bytes. */
4773 uint8_t unused_0[7];
4775 * This field is used in Output records to indicate that the output
4776 * is completely written to RAM. This field should be read as '1'
4777 * to indicate that the output has been completely written.
4778 * When writing a command completion or response to an internal processor,
4779 * the order of writes has to be such that this field is written last.
4782 } __attribute__((packed));
4789 /* hwrm_func_cfg_input (size:704b/88B) */
4790 struct hwrm_func_cfg_input {
4791 /* The HWRM command request type. */
4794 * The completion ring to send the completion event on. This should
4795 * be the NQ ID returned from the `nq_alloc` HWRM command.
4799 * The sequence ID is used by the driver for tracking multiple
4800 * commands. This ID is treated as opaque data by the firmware and
4801 * the value is returned in the `hwrm_resp_hdr` upon completion.
4805 * The target ID of the command:
4806 * * 0x0-0xFFF8 - The function ID
4807 * * 0xFFF8-0xFFFE - Reserved for internal processors
4812 * A physical address pointer pointing to a host buffer that the
4813 * command's response data will be written. This can be either a host
4814 * physical address (HPA) or a guest physical address (GPA) and must
4815 * point to a physically contiguous block of memory.
4819 * Function ID of the function that is being
4821 * If set to 0xFF... (All Fs), then the the configuration is
4822 * for the requesting function.
4826 * This field specifies how many NQs will be reserved for the PF.
4827 * Remaining NQs that belong to the PF become available for VFs.
4828 * Once a PF has created VFs, it cannot change how many NQs are
4829 * reserved for itself (since the NQs must be contiguous in HW).
4834 * When this bit is '1', the function is disabled with
4835 * source MAC address check.
4836 * This is an anti-spoofing check. If this flag is set,
4837 * then the function shall be configured to disallow
4838 * transmission of frames with the source MAC address that
4839 * is configured for this function.
4841 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
4844 * When this bit is '1', the function is enabled with
4845 * source MAC address check.
4846 * This is an anti-spoofing check. If this flag is set,
4847 * then the function shall be configured to allow
4848 * transmission of frames with the source MAC address that
4849 * is configured for this function.
4851 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
4854 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
4856 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
4858 * Standard TX Ring mode is used for the allocation of TX ring
4859 * and underlying scheduling resources that allow bandwidth
4860 * reservation and limit settings on the queried function.
4861 * If set to 1, then standard TX ring mode is requested to be
4862 * enabled on the function being configured.
4864 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
4867 * Standard TX Ring mode is used for the allocation of TX ring
4868 * and underlying scheduling resources that allow bandwidth
4869 * reservation and limit settings on the queried function.
4870 * If set to 1, then the standard TX ring mode is requested to
4871 * be disabled on the function being configured. In this extended
4872 * TX ring resource mode, the minimum and maximum bandwidth settings
4873 * are not supported to allow the allocation of TX rings to
4874 * span multiple scheduler nodes.
4876 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
4879 * If this bit is set, virtual mac address configured
4880 * in this command will be persistent over warm boot.
4882 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
4885 * This bit only applies to the VF. If this bit is set, the statistic
4886 * context counters will not be cleared when the statistic context is freed
4887 * or a function reset is called on VF. This bit will be cleared when the PF
4888 * is unloaded or a function reset is called on the PF.
4890 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
4893 * This bit requests that the firmware test to see if all the assets
4894 * requested in this command (i.e. number of TX rings) are available.
4895 * The firmware will return an error if the requested assets are
4896 * not available. The firwmare will NOT reserve the assets if they
4899 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
4902 * This bit requests that the firmware test to see if all the assets
4903 * requested in this command (i.e. number of RX rings) are available.
4904 * The firmware will return an error if the requested assets are
4905 * not available. The firwmare will NOT reserve the assets if they
4908 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
4911 * This bit requests that the firmware test to see if all the assets
4912 * requested in this command (i.e. number of CMPL rings) are available.
4913 * The firmware will return an error if the requested assets are
4914 * not available. The firwmare will NOT reserve the assets if they
4917 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
4920 * This bit requests that the firmware test to see if all the assets
4921 * requested in this command (i.e. number of RSS ctx) are available.
4922 * The firmware will return an error if the requested assets are
4923 * not available. The firwmare will NOT reserve the assets if they
4926 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
4929 * This bit requests that the firmware test to see if all the assets
4930 * requested in this command (i.e. number of ring groups) are available.
4931 * The firmware will return an error if the requested assets are
4932 * not available. The firwmare will NOT reserve the assets if they
4935 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
4938 * This bit requests that the firmware test to see if all the assets
4939 * requested in this command (i.e. number of stat ctx) are available.
4940 * The firmware will return an error if the requested assets are
4941 * not available. The firwmare will NOT reserve the assets if they
4944 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
4947 * This bit requests that the firmware test to see if all the assets
4948 * requested in this command (i.e. number of VNICs) are available.
4949 * The firmware will return an error if the requested assets are
4950 * not available. The firwmare will NOT reserve the assets if they
4953 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
4956 * This bit requests that the firmware test to see if all the assets
4957 * requested in this command (i.e. number of L2 ctx) are available.
4958 * The firmware will return an error if the requested assets are
4959 * not available. The firwmare will NOT reserve the assets if they
4962 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
4966 * This bit must be '1' for the mtu field to be
4969 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
4972 * This bit must be '1' for the mru field to be
4975 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
4978 * This bit must be '1' for the num_rsscos_ctxs field to be
4981 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
4984 * This bit must be '1' for the num_cmpl_rings field to be
4987 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
4990 * This bit must be '1' for the num_tx_rings field to be
4993 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
4996 * This bit must be '1' for the num_rx_rings field to be
4999 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
5002 * This bit must be '1' for the num_l2_ctxs field to be
5005 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
5008 * This bit must be '1' for the num_vnics field to be
5011 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
5014 * This bit must be '1' for the num_stat_ctxs field to be
5017 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
5020 * This bit must be '1' for the dflt_mac_addr field to be
5023 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
5026 * This bit must be '1' for the dflt_vlan field to be
5029 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
5032 * This bit must be '1' for the dflt_ip_addr field to be
5035 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
5038 * This bit must be '1' for the min_bw field to be
5041 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
5044 * This bit must be '1' for the max_bw field to be
5047 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
5050 * This bit must be '1' for the async_event_cr field to be
5053 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
5056 * This bit must be '1' for the vlan_antispoof_mode field to be
5059 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
5062 * This bit must be '1' for the allowed_vlan_pris field to be
5065 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
5068 * This bit must be '1' for the evb_mode field to be
5071 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
5074 * This bit must be '1' for the num_mcast_filters field to be
5077 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
5080 * This bit must be '1' for the num_hw_ring_grps field to be
5083 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
5086 * This bit must be '1' for the cache_linesize field to be
5089 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
5092 * This bit must be '1' for the num_msix field to be
5095 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
5098 * The maximum transmission unit of the function.
5099 * The HWRM should make sure that the mtu of
5100 * the function does not exceed the mtu of the physical
5101 * port that this function is associated with.
5103 * In addition to configuring mtu per function, it is
5104 * possible to configure mtu per transmit ring.
5105 * By default, the mtu of each transmit ring associated
5106 * with a function is equal to the mtu of the function.
5107 * The HWRM should make sure that the mtu of each transmit
5108 * ring that is assigned to a function has a valid mtu.
5112 * The maximum receive unit of the function.
5113 * The HWRM should make sure that the mru of
5114 * the function does not exceed the mru of the physical
5115 * port that this function is associated with.
5117 * In addition to configuring mru per function, it is
5118 * possible to configure mru per vnic.
5119 * By default, the mru of each vnic associated
5120 * with a function is equal to the mru of the function.
5121 * The HWRM should make sure that the mru of each vnic
5122 * that is assigned to a function has a valid mru.
5126 * The number of RSS/COS contexts requested for the
5129 uint16_t num_rsscos_ctxs;
5131 * The number of completion rings requested for the
5132 * function. This does not include the rings allocated
5133 * to any children functions if any.
5135 uint16_t num_cmpl_rings;
5137 * The number of transmit rings requested for the function.
5138 * This does not include the rings allocated to any
5139 * children functions if any.
5141 uint16_t num_tx_rings;
5143 * The number of receive rings requested for the function.
5144 * This does not include the rings allocated
5145 * to any children functions if any.
5147 uint16_t num_rx_rings;
5148 /* The requested number of L2 contexts for the function. */
5149 uint16_t num_l2_ctxs;
5150 /* The requested number of vnics for the function. */
5152 /* The requested number of statistic contexts for the function. */
5153 uint16_t num_stat_ctxs;
5155 * The number of HW ring groups that should
5156 * be reserved for this function.
5158 uint16_t num_hw_ring_grps;
5159 /* The default MAC address for the function being configured. */
5160 uint8_t dflt_mac_addr[6];
5162 * The default VLAN for the function being configured.
5163 * This field's format is same as 802.1Q Tag's
5164 * Tag Control Information (TCI) format that includes both
5165 * Priority Code Point (PCP) and VLAN Identifier (VID).
5169 * The default IP address for the function being configured.
5170 * This address is only used in enabling source property check.
5172 uint32_t dflt_ip_addr[4];
5174 * Minimum BW allocated for this function.
5175 * The HWRM will translate this value into byte counter and
5176 * time interval used for the scheduler inside the device.
5179 /* The bandwidth value. */
5180 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
5182 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
5183 /* The granularity of the value (bits or bytes). */
5184 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
5185 UINT32_C(0x10000000)
5186 /* Value is in bits. */
5187 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
5188 (UINT32_C(0x0) << 28)
5189 /* Value is in bytes. */
5190 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
5191 (UINT32_C(0x1) << 28)
5192 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
5193 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
5194 /* bw_value_unit is 3 b */
5195 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
5196 UINT32_C(0xe0000000)
5197 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
5198 /* Value is in Mb or MB (base 10). */
5199 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
5200 (UINT32_C(0x0) << 29)
5201 /* Value is in Kb or KB (base 10). */
5202 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
5203 (UINT32_C(0x2) << 29)
5204 /* Value is in bits or bytes. */
5205 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
5206 (UINT32_C(0x4) << 29)
5207 /* Value is in Gb or GB (base 10). */
5208 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
5209 (UINT32_C(0x6) << 29)
5210 /* Value is in 1/100th of a percentage of total bandwidth. */
5211 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
5212 (UINT32_C(0x1) << 29)
5214 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
5215 (UINT32_C(0x7) << 29)
5216 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
5217 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
5219 * Maximum BW allocated for this function.
5220 * The HWRM will translate this value into byte counter and
5221 * time interval used for the scheduler inside the device.
5224 /* The bandwidth value. */
5225 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
5227 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
5228 /* The granularity of the value (bits or bytes). */
5229 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
5230 UINT32_C(0x10000000)
5231 /* Value is in bits. */
5232 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
5233 (UINT32_C(0x0) << 28)
5234 /* Value is in bytes. */
5235 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
5236 (UINT32_C(0x1) << 28)
5237 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
5238 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
5239 /* bw_value_unit is 3 b */
5240 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
5241 UINT32_C(0xe0000000)
5242 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
5243 /* Value is in Mb or MB (base 10). */
5244 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
5245 (UINT32_C(0x0) << 29)
5246 /* Value is in Kb or KB (base 10). */
5247 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
5248 (UINT32_C(0x2) << 29)
5249 /* Value is in bits or bytes. */
5250 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
5251 (UINT32_C(0x4) << 29)
5252 /* Value is in Gb or GB (base 10). */
5253 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
5254 (UINT32_C(0x6) << 29)
5255 /* Value is in 1/100th of a percentage of total bandwidth. */
5256 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
5257 (UINT32_C(0x1) << 29)
5259 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
5260 (UINT32_C(0x7) << 29)
5261 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
5262 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
5264 * ID of the target completion ring for receiving asynchronous
5265 * event completions. If this field is not valid, then the
5266 * HWRM shall use the default completion ring of the function
5267 * that is being configured as the target completion ring for
5268 * providing any asynchronous event completions for that
5270 * If this field is valid, then the HWRM shall use the
5271 * completion ring identified by this ID as the target
5272 * completion ring for providing any asynchronous event
5273 * completions for the function that is being configured.
5275 uint16_t async_event_cr;
5276 /* VLAN Anti-spoofing mode. */
5277 uint8_t vlan_antispoof_mode;
5278 /* No VLAN anti-spoofing checks are enabled */
5279 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
5281 /* Validate VLAN against the configured VLAN(s) */
5282 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
5284 /* Insert VLAN if it does not exist, otherwise discard */
5285 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
5287 /* Insert VLAN if it does not exist, override VLAN if it exists */
5288 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
5290 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
5291 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
5293 * This bit field defines VLAN PRIs that are allowed on
5295 * If nth bit is set, then VLAN PRI n is allowed on this
5298 uint8_t allowed_vlan_pris;
5300 * The HWRM shall allow a PF driver to change EVB mode for the
5301 * partition it belongs to.
5302 * The HWRM shall not allow a VF driver to change the EVB mode.
5303 * The HWRM shall take into account the switching of EVB mode
5304 * from one to another and reconfigure hardware resources as
5306 * The switching from VEB to VEPA mode requires
5307 * the disabling of the loopback traffic. Additionally,
5308 * source knock outs are handled differently in VEB and VEPA
5312 /* No Edge Virtual Bridging (EVB) */
5313 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
5314 /* Virtual Ethernet Bridge (VEB) */
5315 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
5316 /* Virtual Ethernet Port Aggregator (VEPA) */
5317 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
5318 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
5319 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
5322 * This value indicates the PCIE device cache line size.
5323 * The cache line size allows the DMA writes to terminate and
5324 * start at the cache boundary.
5326 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
5328 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
5329 /* Cache Line Size 64 bytes */
5330 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
5332 /* Cache Line Size 128 bytes */
5333 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
5335 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
5336 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
5337 /* Reserved for future. */
5338 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
5340 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2
5342 * The number of multicast filters that should
5343 * be reserved for this function on the RX side.
5345 uint16_t num_mcast_filters;
5346 } __attribute__((packed));
5348 /* hwrm_func_cfg_output (size:128b/16B) */
5349 struct hwrm_func_cfg_output {
5350 /* The specific error status for the command. */
5351 uint16_t error_code;
5352 /* The HWRM command request type. */
5354 /* The sequence ID from the original command. */
5356 /* The length of the response data in number of bytes. */
5358 uint8_t unused_0[7];
5360 * This field is used in Output records to indicate that the output
5361 * is completely written to RAM. This field should be read as '1'
5362 * to indicate that the output has been completely written.
5363 * When writing a command completion or response to an internal processor,
5364 * the order of writes has to be such that this field is written last.
5367 } __attribute__((packed));
5369 /********************
5370 * hwrm_func_qstats *
5371 ********************/
5374 /* hwrm_func_qstats_input (size:192b/24B) */
5375 struct hwrm_func_qstats_input {
5376 /* The HWRM command request type. */
5379 * The completion ring to send the completion event on. This should
5380 * be the NQ ID returned from the `nq_alloc` HWRM command.
5384 * The sequence ID is used by the driver for tracking multiple
5385 * commands. This ID is treated as opaque data by the firmware and
5386 * the value is returned in the `hwrm_resp_hdr` upon completion.
5390 * The target ID of the command:
5391 * * 0x0-0xFFF8 - The function ID
5392 * * 0xFFF8-0xFFFE - Reserved for internal processors
5397 * A physical address pointer pointing to a host buffer that the
5398 * command's response data will be written. This can be either a host
5399 * physical address (HPA) or a guest physical address (GPA) and must
5400 * point to a physically contiguous block of memory.
5404 * Function ID of the function that is being queried.
5405 * 0xFF... (All Fs) if the query is for the requesting
5409 uint8_t unused_0[6];
5410 } __attribute__((packed));
5412 /* hwrm_func_qstats_output (size:1408b/176B) */
5413 struct hwrm_func_qstats_output {
5414 /* The specific error status for the command. */
5415 uint16_t error_code;
5416 /* The HWRM command request type. */
5418 /* The sequence ID from the original command. */
5420 /* The length of the response data in number of bytes. */
5422 /* Number of transmitted unicast packets on the function. */
5423 uint64_t tx_ucast_pkts;
5424 /* Number of transmitted multicast packets on the function. */
5425 uint64_t tx_mcast_pkts;
5426 /* Number of transmitted broadcast packets on the function. */
5427 uint64_t tx_bcast_pkts;
5429 * Number of transmitted packets that were discarded due to
5430 * internal NIC resource problems. For transmit, this
5431 * can only happen if TMP is configured to allow dropping
5432 * in HOL blocking conditions, which is not a normal
5435 uint64_t tx_discard_pkts;
5437 * Number of dropped packets on transmit path on the function.
5438 * These are packets that have been marked for drop by
5439 * the TE CFA block or are packets that exceeded the
5440 * transmit MTU limit for the function.
5442 uint64_t tx_drop_pkts;
5443 /* Number of transmitted bytes for unicast traffic on the function. */
5444 uint64_t tx_ucast_bytes;
5445 /* Number of transmitted bytes for multicast traffic on the function. */
5446 uint64_t tx_mcast_bytes;
5447 /* Number of transmitted bytes for broadcast traffic on the function. */
5448 uint64_t tx_bcast_bytes;
5449 /* Number of received unicast packets on the function. */
5450 uint64_t rx_ucast_pkts;
5451 /* Number of received multicast packets on the function. */
5452 uint64_t rx_mcast_pkts;
5453 /* Number of received broadcast packets on the function. */
5454 uint64_t rx_bcast_pkts;
5456 * Number of received packets that were discarded on the function
5457 * due to resource limitations. This can happen for 3 reasons.
5458 * # The BD used for the packet has a bad format.
5459 * # There were no BDs available in the ring for the packet.
5460 * # There were no BDs available on-chip for the packet.
5462 uint64_t rx_discard_pkts;
5464 * Number of dropped packets on received path on the function.
5465 * These are packets that have been marked for drop by the
5468 uint64_t rx_drop_pkts;
5469 /* Number of received bytes for unicast traffic on the function. */
5470 uint64_t rx_ucast_bytes;
5471 /* Number of received bytes for multicast traffic on the function. */
5472 uint64_t rx_mcast_bytes;
5473 /* Number of received bytes for broadcast traffic on the function. */
5474 uint64_t rx_bcast_bytes;
5475 /* Number of aggregated unicast packets on the function. */
5476 uint64_t rx_agg_pkts;
5477 /* Number of aggregated unicast bytes on the function. */
5478 uint64_t rx_agg_bytes;
5479 /* Number of aggregation events on the function. */
5480 uint64_t rx_agg_events;
5481 /* Number of aborted aggregations on the function. */
5482 uint64_t rx_agg_aborts;
5483 uint8_t unused_0[7];
5485 * This field is used in Output records to indicate that the output
5486 * is completely written to RAM. This field should be read as '1'
5487 * to indicate that the output has been completely written.
5488 * When writing a command completion or response to an internal processor,
5489 * the order of writes has to be such that this field is written last.
5492 } __attribute__((packed));
5494 /***********************
5495 * hwrm_func_clr_stats *
5496 ***********************/
5499 /* hwrm_func_clr_stats_input (size:192b/24B) */
5500 struct hwrm_func_clr_stats_input {
5501 /* The HWRM command request type. */
5504 * The completion ring to send the completion event on. This should
5505 * be the NQ ID returned from the `nq_alloc` HWRM command.
5509 * The sequence ID is used by the driver for tracking multiple
5510 * commands. This ID is treated as opaque data by the firmware and
5511 * the value is returned in the `hwrm_resp_hdr` upon completion.
5515 * The target ID of the command:
5516 * * 0x0-0xFFF8 - The function ID
5517 * * 0xFFF8-0xFFFE - Reserved for internal processors
5522 * A physical address pointer pointing to a host buffer that the
5523 * command's response data will be written. This can be either a host
5524 * physical address (HPA) or a guest physical address (GPA) and must
5525 * point to a physically contiguous block of memory.
5529 * Function ID of the function.
5530 * 0xFF... (All Fs) if the query is for the requesting
5534 uint8_t unused_0[6];
5535 } __attribute__((packed));
5537 /* hwrm_func_clr_stats_output (size:128b/16B) */
5538 struct hwrm_func_clr_stats_output {
5539 /* The specific error status for the command. */
5540 uint16_t error_code;
5541 /* The HWRM command request type. */
5543 /* The sequence ID from the original command. */
5545 /* The length of the response data in number of bytes. */
5547 uint8_t unused_0[7];
5549 * This field is used in Output records to indicate that the output
5550 * is completely written to RAM. This field should be read as '1'
5551 * to indicate that the output has been completely written.
5552 * When writing a command completion or response to an internal processor,
5553 * the order of writes has to be such that this field is written last.
5556 } __attribute__((packed));
5558 /**************************
5559 * hwrm_func_vf_resc_free *
5560 **************************/
5563 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
5564 struct hwrm_func_vf_resc_free_input {
5565 /* The HWRM command request type. */
5568 * The completion ring to send the completion event on. This should
5569 * be the NQ ID returned from the `nq_alloc` HWRM command.
5573 * The sequence ID is used by the driver for tracking multiple
5574 * commands. This ID is treated as opaque data by the firmware and
5575 * the value is returned in the `hwrm_resp_hdr` upon completion.
5579 * The target ID of the command:
5580 * * 0x0-0xFFF8 - The function ID
5581 * * 0xFFF8-0xFFFE - Reserved for internal processors
5586 * A physical address pointer pointing to a host buffer that the
5587 * command's response data will be written. This can be either a host
5588 * physical address (HPA) or a guest physical address (GPA) and must
5589 * point to a physically contiguous block of memory.
5593 * This value is used to identify a Virtual Function (VF).
5594 * The scope of VF ID is local within a PF.
5597 uint8_t unused_0[6];
5598 } __attribute__((packed));
5600 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
5601 struct hwrm_func_vf_resc_free_output {
5602 /* The specific error status for the command. */
5603 uint16_t error_code;
5604 /* The HWRM command request type. */
5606 /* The sequence ID from the original command. */
5608 /* The length of the response data in number of bytes. */
5610 uint8_t unused_0[7];
5612 * This field is used in Output records to indicate that the output
5613 * is completely written to RAM. This field should be read as '1'
5614 * to indicate that the output has been completely written.
5615 * When writing a command completion or response to an internal processor,
5616 * the order of writes has to be such that this field is written last.
5619 } __attribute__((packed));
5621 /*******************************
5622 * hwrm_func_vf_vnic_ids_query *
5623 *******************************/
5626 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
5627 struct hwrm_func_vf_vnic_ids_query_input {
5628 /* The HWRM command request type. */
5631 * The completion ring to send the completion event on. This should
5632 * be the NQ ID returned from the `nq_alloc` HWRM command.
5636 * The sequence ID is used by the driver for tracking multiple
5637 * commands. This ID is treated as opaque data by the firmware and
5638 * the value is returned in the `hwrm_resp_hdr` upon completion.
5642 * The target ID of the command:
5643 * * 0x0-0xFFF8 - The function ID
5644 * * 0xFFF8-0xFFFE - Reserved for internal processors
5649 * A physical address pointer pointing to a host buffer that the
5650 * command's response data will be written. This can be either a host
5651 * physical address (HPA) or a guest physical address (GPA) and must
5652 * point to a physically contiguous block of memory.
5656 * This value is used to identify a Virtual Function (VF).
5657 * The scope of VF ID is local within a PF.
5660 uint8_t unused_0[2];
5661 /* Max number of vnic ids in vnic id table */
5662 uint32_t max_vnic_id_cnt;
5663 /* This is the address for VF VNIC ID table */
5664 uint64_t vnic_id_tbl_addr;
5665 } __attribute__((packed));
5667 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
5668 struct hwrm_func_vf_vnic_ids_query_output {
5669 /* The specific error status for the command. */
5670 uint16_t error_code;
5671 /* The HWRM command request type. */
5673 /* The sequence ID from the original command. */
5675 /* The length of the response data in number of bytes. */
5678 * Actual number of vnic ids
5680 * Each VNIC ID is written as a 32-bit number.
5682 uint32_t vnic_id_cnt;
5683 uint8_t unused_0[3];
5685 * This field is used in Output records to indicate that the output
5686 * is completely written to RAM. This field should be read as '1'
5687 * to indicate that the output has been completely written.
5688 * When writing a command completion or response to an internal processor,
5689 * the order of writes has to be such that this field is written last.
5692 } __attribute__((packed));
5694 /**********************
5695 * hwrm_func_drv_rgtr *
5696 **********************/
5699 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
5700 struct hwrm_func_drv_rgtr_input {
5701 /* The HWRM command request type. */
5704 * The completion ring to send the completion event on. This should
5705 * be the NQ ID returned from the `nq_alloc` HWRM command.
5709 * The sequence ID is used by the driver for tracking multiple
5710 * commands. This ID is treated as opaque data by the firmware and
5711 * the value is returned in the `hwrm_resp_hdr` upon completion.
5715 * The target ID of the command:
5716 * * 0x0-0xFFF8 - The function ID
5717 * * 0xFFF8-0xFFFE - Reserved for internal processors
5722 * A physical address pointer pointing to a host buffer that the
5723 * command's response data will be written. This can be either a host
5724 * physical address (HPA) or a guest physical address (GPA) and must
5725 * point to a physically contiguous block of memory.
5730 * When this bit is '1', the function driver is requesting
5731 * all requests from its children VF drivers to be
5732 * forwarded to itself.
5733 * This flag can only be set by the PF driver.
5734 * If a VF driver sets this flag, it should be ignored
5737 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
5739 * When this bit is '1', the function is requesting none of
5740 * the requests from its children VF drivers to be
5741 * forwarded to itself.
5742 * This flag can only be set by the PF driver.
5743 * If a VF driver sets this flag, it should be ignored
5746 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
5748 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
5749 * fields shall be ignored and ver_maj, ver_min, ver_upd
5750 * and ver_patch shall be used for the driver version information.
5751 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
5752 * fields shall be used for the driver version information and
5753 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
5755 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
5758 * This bit must be '1' for the os_type field to be
5761 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
5764 * This bit must be '1' for the ver field to be
5767 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
5770 * This bit must be '1' for the timestamp field to be
5773 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
5776 * This bit must be '1' for the vf_req_fwd field to be
5779 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
5782 * This bit must be '1' for the async_event_fwd field to be
5785 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
5787 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
5790 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
5791 /* Other OS not listed below. */
5792 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
5794 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
5796 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
5798 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
5800 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
5802 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
5803 /* VMware ESXi OS. */
5804 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
5805 /* Microsoft Windows 8 64-bit OS. */
5806 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
5807 /* Microsoft Windows Server 2012 R2 OS. */
5808 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
5810 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
5811 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
5812 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
5813 /* This is the 8bit major version of the driver. */
5815 /* This is the 8bit minor version of the driver. */
5817 /* This is the 8bit update version of the driver. */
5819 uint8_t unused_0[3];
5821 * This is a 32-bit timestamp provided by the driver for
5823 * The timestamp is in multiples of 1ms.
5826 uint8_t unused_1[4];
5828 * This is a 256-bit bit mask provided by the PF driver for
5829 * letting the HWRM know what commands issued by the VF driver
5830 * to the HWRM should be forwarded to the PF driver.
5831 * Nth bit refers to the Nth req_type.
5833 * Setting Nth bit to 1 indicates that requests from the
5834 * VF driver with req_type equal to N shall be forwarded to
5835 * the parent PF driver.
5837 * This field is not valid for the VF driver.
5839 uint32_t vf_req_fwd[8];
5841 * This is a 256-bit bit mask provided by the function driver
5842 * (PF or VF driver) to indicate the list of asynchronous event
5843 * completions to be forwarded.
5845 * Nth bit refers to the Nth event_id.
5847 * Setting Nth bit to 1 by the function driver shall result in
5848 * the HWRM forwarding asynchronous event completion with
5849 * event_id equal to N.
5851 * If all bits are set to 0 (value of 0), then the HWRM shall
5852 * not forward any asynchronous event completion to this
5855 uint32_t async_event_fwd[8];
5856 /* This is the 16bit major version of the driver. */
5858 /* This is the 16bit minor version of the driver. */
5860 /* This is the 16bit update version of the driver. */
5862 /* This is the 16bit patch version of the driver. */
5864 } __attribute__((packed));
5866 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
5867 struct hwrm_func_drv_rgtr_output {
5868 /* The specific error status for the command. */
5869 uint16_t error_code;
5870 /* The HWRM command request type. */
5872 /* The sequence ID from the original command. */
5874 /* The length of the response data in number of bytes. */
5876 uint8_t unused_0[7];
5878 * This field is used in Output records to indicate that the output
5879 * is completely written to RAM. This field should be read as '1'
5880 * to indicate that the output has been completely written.
5881 * When writing a command completion or response to an internal processor,
5882 * the order of writes has to be such that this field is written last.
5885 } __attribute__((packed));
5887 /************************
5888 * hwrm_func_drv_unrgtr *
5889 ************************/
5892 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
5893 struct hwrm_func_drv_unrgtr_input {
5894 /* The HWRM command request type. */
5897 * The completion ring to send the completion event on. This should
5898 * be the NQ ID returned from the `nq_alloc` HWRM command.
5902 * The sequence ID is used by the driver for tracking multiple
5903 * commands. This ID is treated as opaque data by the firmware and
5904 * the value is returned in the `hwrm_resp_hdr` upon completion.
5908 * The target ID of the command:
5909 * * 0x0-0xFFF8 - The function ID
5910 * * 0xFFF8-0xFFFE - Reserved for internal processors
5915 * A physical address pointer pointing to a host buffer that the
5916 * command's response data will be written. This can be either a host
5917 * physical address (HPA) or a guest physical address (GPA) and must
5918 * point to a physically contiguous block of memory.
5923 * When this bit is '1', the function driver is notifying
5924 * the HWRM to prepare for the shutdown.
5926 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
5928 uint8_t unused_0[4];
5929 } __attribute__((packed));
5931 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
5932 struct hwrm_func_drv_unrgtr_output {
5933 /* The specific error status for the command. */
5934 uint16_t error_code;
5935 /* The HWRM command request type. */
5937 /* The sequence ID from the original command. */
5939 /* The length of the response data in number of bytes. */
5941 uint8_t unused_0[7];
5943 * This field is used in Output records to indicate that the output
5944 * is completely written to RAM. This field should be read as '1'
5945 * to indicate that the output has been completely written.
5946 * When writing a command completion or response to an internal processor,
5947 * the order of writes has to be such that this field is written last.
5950 } __attribute__((packed));
5952 /**********************
5953 * hwrm_func_buf_rgtr *
5954 **********************/
5957 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
5958 struct hwrm_func_buf_rgtr_input {
5959 /* The HWRM command request type. */
5962 * The completion ring to send the completion event on. This should
5963 * be the NQ ID returned from the `nq_alloc` HWRM command.
5967 * The sequence ID is used by the driver for tracking multiple
5968 * commands. This ID is treated as opaque data by the firmware and
5969 * the value is returned in the `hwrm_resp_hdr` upon completion.
5973 * The target ID of the command:
5974 * * 0x0-0xFFF8 - The function ID
5975 * * 0xFFF8-0xFFFE - Reserved for internal processors
5980 * A physical address pointer pointing to a host buffer that the
5981 * command's response data will be written. This can be either a host
5982 * physical address (HPA) or a guest physical address (GPA) and must
5983 * point to a physically contiguous block of memory.
5988 * This bit must be '1' for the vf_id field to be
5991 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
5993 * This bit must be '1' for the err_buf_addr field to be
5996 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
5998 * This value is used to identify a Virtual Function (VF).
5999 * The scope of VF ID is local within a PF.
6003 * This field represents the number of pages used for request
6006 uint16_t req_buf_num_pages;
6008 * This field represents the page size used for request
6011 uint16_t req_buf_page_size;
6013 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
6015 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
6017 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
6019 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
6021 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
6023 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
6025 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
6026 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
6027 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
6028 /* The length of the request buffer per VF in bytes. */
6029 uint16_t req_buf_len;
6030 /* The length of the response buffer in bytes. */
6031 uint16_t resp_buf_len;
6032 uint8_t unused_0[2];
6033 /* This field represents the page address of page #0. */
6034 uint64_t req_buf_page_addr0;
6035 /* This field represents the page address of page #1. */
6036 uint64_t req_buf_page_addr1;
6037 /* This field represents the page address of page #2. */
6038 uint64_t req_buf_page_addr2;
6039 /* This field represents the page address of page #3. */
6040 uint64_t req_buf_page_addr3;
6041 /* This field represents the page address of page #4. */
6042 uint64_t req_buf_page_addr4;
6043 /* This field represents the page address of page #5. */
6044 uint64_t req_buf_page_addr5;
6045 /* This field represents the page address of page #6. */
6046 uint64_t req_buf_page_addr6;
6047 /* This field represents the page address of page #7. */
6048 uint64_t req_buf_page_addr7;
6049 /* This field represents the page address of page #8. */
6050 uint64_t req_buf_page_addr8;
6051 /* This field represents the page address of page #9. */
6052 uint64_t req_buf_page_addr9;
6054 * This field is used to receive the error reporting from
6055 * the chipset. Only applicable for PFs.
6057 uint64_t error_buf_addr;
6059 * This field is used to receive the response forwarded by the
6062 uint64_t resp_buf_addr;
6063 } __attribute__((packed));
6065 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
6066 struct hwrm_func_buf_rgtr_output {
6067 /* The specific error status for the command. */
6068 uint16_t error_code;
6069 /* The HWRM command request type. */
6071 /* The sequence ID from the original command. */
6073 /* The length of the response data in number of bytes. */
6075 uint8_t unused_0[7];
6077 * This field is used in Output records to indicate that the output
6078 * is completely written to RAM. This field should be read as '1'
6079 * to indicate that the output has been completely written.
6080 * When writing a command completion or response to an internal processor,
6081 * the order of writes has to be such that this field is written last.
6084 } __attribute__((packed));
6086 /************************
6087 * hwrm_func_buf_unrgtr *
6088 ************************/
6091 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
6092 struct hwrm_func_buf_unrgtr_input {
6093 /* The HWRM command request type. */
6096 * The completion ring to send the completion event on. This should
6097 * be the NQ ID returned from the `nq_alloc` HWRM command.
6101 * The sequence ID is used by the driver for tracking multiple
6102 * commands. This ID is treated as opaque data by the firmware and
6103 * the value is returned in the `hwrm_resp_hdr` upon completion.
6107 * The target ID of the command:
6108 * * 0x0-0xFFF8 - The function ID
6109 * * 0xFFF8-0xFFFE - Reserved for internal processors
6114 * A physical address pointer pointing to a host buffer that the
6115 * command's response data will be written. This can be either a host
6116 * physical address (HPA) or a guest physical address (GPA) and must
6117 * point to a physically contiguous block of memory.
6122 * This bit must be '1' for the vf_id field to be
6125 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
6127 * This value is used to identify a Virtual Function (VF).
6128 * The scope of VF ID is local within a PF.
6131 uint8_t unused_0[2];
6132 } __attribute__((packed));
6134 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
6135 struct hwrm_func_buf_unrgtr_output {
6136 /* The specific error status for the command. */
6137 uint16_t error_code;
6138 /* The HWRM command request type. */
6140 /* The sequence ID from the original command. */
6142 /* The length of the response data in number of bytes. */
6144 uint8_t unused_0[7];
6146 * This field is used in Output records to indicate that the output
6147 * is completely written to RAM. This field should be read as '1'
6148 * to indicate that the output has been completely written.
6149 * When writing a command completion or response to an internal processor,
6150 * the order of writes has to be such that this field is written last.
6153 } __attribute__((packed));
6155 /**********************
6156 * hwrm_func_drv_qver *
6157 **********************/
6160 /* hwrm_func_drv_qver_input (size:192b/24B) */
6161 struct hwrm_func_drv_qver_input {
6162 /* The HWRM command request type. */
6165 * The completion ring to send the completion event on. This should
6166 * be the NQ ID returned from the `nq_alloc` HWRM command.
6170 * The sequence ID is used by the driver for tracking multiple
6171 * commands. This ID is treated as opaque data by the firmware and
6172 * the value is returned in the `hwrm_resp_hdr` upon completion.
6176 * The target ID of the command:
6177 * * 0x0-0xFFF8 - The function ID
6178 * * 0xFFF8-0xFFFE - Reserved for internal processors
6183 * A physical address pointer pointing to a host buffer that the
6184 * command's response data will be written. This can be either a host
6185 * physical address (HPA) or a guest physical address (GPA) and must
6186 * point to a physically contiguous block of memory.
6189 /* Reserved for future use. */
6192 * Function ID of the function that is being queried.
6193 * 0xFF... (All Fs) if the query is for the requesting
6197 uint8_t unused_0[2];
6198 } __attribute__((packed));
6200 /* hwrm_func_drv_qver_output (size:192b/24B) */
6201 struct hwrm_func_drv_qver_output {
6202 /* The specific error status for the command. */
6203 uint16_t error_code;
6204 /* The HWRM command request type. */
6206 /* The sequence ID from the original command. */
6208 /* The length of the response data in number of bytes. */
6210 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
6213 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
6214 /* Other OS not listed below. */
6215 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
6217 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
6219 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
6221 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
6223 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
6225 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
6226 /* VMware ESXi OS. */
6227 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
6228 /* Microsoft Windows 8 64-bit OS. */
6229 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
6230 /* Microsoft Windows Server 2012 R2 OS. */
6231 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
6233 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
6234 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
6235 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
6236 /* This is the 8bit major version of the driver. */
6238 /* This is the 8bit minor version of the driver. */
6240 /* This is the 8bit update version of the driver. */
6242 uint8_t unused_0[2];
6244 * This field is used in Output records to indicate that the output
6245 * is completely written to RAM. This field should be read as '1'
6246 * to indicate that the output has been completely written.
6247 * When writing a command completion or response to an internal processor,
6248 * the order of writes has to be such that this field is written last.
6251 /* This is the 16bit major version of the driver. */
6253 /* This is the 16bit minor version of the driver. */
6255 /* This is the 16bit update version of the driver. */
6257 /* This is the 16bit patch version of the driver. */
6259 } __attribute__((packed));
6261 /****************************
6262 * hwrm_func_resource_qcaps *
6263 ****************************/
6266 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
6267 struct hwrm_func_resource_qcaps_input {
6268 /* The HWRM command request type. */
6271 * The completion ring to send the completion event on. This should
6272 * be the NQ ID returned from the `nq_alloc` HWRM command.
6276 * The sequence ID is used by the driver for tracking multiple
6277 * commands. This ID is treated as opaque data by the firmware and
6278 * the value is returned in the `hwrm_resp_hdr` upon completion.
6282 * The target ID of the command:
6283 * * 0x0-0xFFF8 - The function ID
6284 * * 0xFFF8-0xFFFE - Reserved for internal processors
6289 * A physical address pointer pointing to a host buffer that the
6290 * command's response data will be written. This can be either a host
6291 * physical address (HPA) or a guest physical address (GPA) and must
6292 * point to a physically contiguous block of memory.
6296 * Function ID of the function that is being queried.
6297 * 0xFF... (All Fs) if the query is for the requesting
6301 uint8_t unused_0[6];
6302 } __attribute__((packed));
6304 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
6305 struct hwrm_func_resource_qcaps_output {
6306 /* The specific error status for the command. */
6307 uint16_t error_code;
6308 /* The HWRM command request type. */
6310 /* The sequence ID from the original command. */
6312 /* The length of the response data in number of bytes. */
6314 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
6316 /* Maximum guaranteed number of MSI-X vectors supported by function */
6318 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
6319 uint16_t vf_reservation_strategy;
6320 /* The PF driver should evenly divide its remaining resources among all VFs. */
6321 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
6323 /* The PF driver should only reserve minimal resources for each VF. */
6324 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
6327 * The PF driver should not reserve any resources for each VF until the
6328 * the VF interface is brought up.
6330 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
6332 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
6333 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
6334 /* Minimum guaranteed number of RSS/COS contexts */
6335 uint16_t min_rsscos_ctx;
6336 /* Maximum non-guaranteed number of RSS/COS contexts */
6337 uint16_t max_rsscos_ctx;
6338 /* Minimum guaranteed number of completion rings */
6339 uint16_t min_cmpl_rings;
6340 /* Maximum non-guaranteed number of completion rings */
6341 uint16_t max_cmpl_rings;
6342 /* Minimum guaranteed number of transmit rings */
6343 uint16_t min_tx_rings;
6344 /* Maximum non-guaranteed number of transmit rings */
6345 uint16_t max_tx_rings;
6346 /* Minimum guaranteed number of receive rings */
6347 uint16_t min_rx_rings;
6348 /* Maximum non-guaranteed number of receive rings */
6349 uint16_t max_rx_rings;
6350 /* Minimum guaranteed number of L2 contexts */
6351 uint16_t min_l2_ctxs;
6352 /* Maximum non-guaranteed number of L2 contexts */
6353 uint16_t max_l2_ctxs;
6354 /* Minimum guaranteed number of VNICs */
6356 /* Maximum non-guaranteed number of VNICs */
6358 /* Minimum guaranteed number of statistic contexts */
6359 uint16_t min_stat_ctx;
6360 /* Maximum non-guaranteed number of statistic contexts */
6361 uint16_t max_stat_ctx;
6362 /* Minimum guaranteed number of ring groups */
6363 uint16_t min_hw_ring_grps;
6364 /* Maximum non-guaranteed number of ring groups */
6365 uint16_t max_hw_ring_grps;
6367 * Maximum number of inputs into the transmit scheduler for this function.
6368 * The number of TX rings assigned to the function cannot exceed this value.
6370 uint16_t max_tx_scheduler_inputs;
6371 uint8_t unused_0[7];
6373 * This field is used in Output records to indicate that the output
6374 * is completely written to RAM. This field should be read as '1'
6375 * to indicate that the output has been completely written.
6376 * When writing a command completion or response to an internal processor,
6377 * the order of writes has to be such that this field is written last.
6380 } __attribute__((packed));
6382 /*****************************
6383 * hwrm_func_vf_resource_cfg *
6384 *****************************/
6387 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
6388 struct hwrm_func_vf_resource_cfg_input {
6389 /* The HWRM command request type. */
6392 * The completion ring to send the completion event on. This should
6393 * be the NQ ID returned from the `nq_alloc` HWRM command.
6397 * The sequence ID is used by the driver for tracking multiple
6398 * commands. This ID is treated as opaque data by the firmware and
6399 * the value is returned in the `hwrm_resp_hdr` upon completion.
6403 * The target ID of the command:
6404 * * 0x0-0xFFF8 - The function ID
6405 * * 0xFFF8-0xFFFE - Reserved for internal processors
6410 * A physical address pointer pointing to a host buffer that the
6411 * command's response data will be written. This can be either a host
6412 * physical address (HPA) or a guest physical address (GPA) and must
6413 * point to a physically contiguous block of memory.
6416 /* VF ID that is being configured by PF */
6418 /* Maximum guaranteed number of MSI-X vectors for the function */
6420 /* Minimum guaranteed number of RSS/COS contexts */
6421 uint16_t min_rsscos_ctx;
6422 /* Maximum non-guaranteed number of RSS/COS contexts */
6423 uint16_t max_rsscos_ctx;
6424 /* Minimum guaranteed number of completion rings */
6425 uint16_t min_cmpl_rings;
6426 /* Maximum non-guaranteed number of completion rings */
6427 uint16_t max_cmpl_rings;
6428 /* Minimum guaranteed number of transmit rings */
6429 uint16_t min_tx_rings;
6430 /* Maximum non-guaranteed number of transmit rings */
6431 uint16_t max_tx_rings;
6432 /* Minimum guaranteed number of receive rings */
6433 uint16_t min_rx_rings;
6434 /* Maximum non-guaranteed number of receive rings */
6435 uint16_t max_rx_rings;
6436 /* Minimum guaranteed number of L2 contexts */
6437 uint16_t min_l2_ctxs;
6438 /* Maximum non-guaranteed number of L2 contexts */
6439 uint16_t max_l2_ctxs;
6440 /* Minimum guaranteed number of VNICs */
6442 /* Maximum non-guaranteed number of VNICs */
6444 /* Minimum guaranteed number of statistic contexts */
6445 uint16_t min_stat_ctx;
6446 /* Maximum non-guaranteed number of statistic contexts */
6447 uint16_t max_stat_ctx;
6448 /* Minimum guaranteed number of ring groups */
6449 uint16_t min_hw_ring_grps;
6450 /* Maximum non-guaranteed number of ring groups */
6451 uint16_t max_hw_ring_grps;
6452 uint8_t unused_0[4];
6453 } __attribute__((packed));
6455 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
6456 struct hwrm_func_vf_resource_cfg_output {
6457 /* The specific error status for the command. */
6458 uint16_t error_code;
6459 /* The HWRM command request type. */
6461 /* The sequence ID from the original command. */
6463 /* The length of the response data in number of bytes. */
6465 /* Reserved number of RSS/COS contexts */
6466 uint16_t reserved_rsscos_ctx;
6467 /* Reserved number of completion rings */
6468 uint16_t reserved_cmpl_rings;
6469 /* Reserved number of transmit rings */
6470 uint16_t reserved_tx_rings;
6471 /* Reserved number of receive rings */
6472 uint16_t reserved_rx_rings;
6473 /* Reserved number of L2 contexts */
6474 uint16_t reserved_l2_ctxs;
6475 /* Reserved number of VNICs */
6476 uint16_t reserved_vnics;
6477 /* Reserved number of statistic contexts */
6478 uint16_t reserved_stat_ctx;
6479 /* Reserved number of ring groups */
6480 uint16_t reserved_hw_ring_grps;
6481 uint8_t unused_0[7];
6483 * This field is used in Output records to indicate that the output
6484 * is completely written to RAM. This field should be read as '1'
6485 * to indicate that the output has been completely written.
6486 * When writing a command completion or response to an internal processor,
6487 * the order of writes has to be such that this field is written last.
6490 } __attribute__((packed));
6492 /*********************************
6493 * hwrm_func_backing_store_qcaps *
6494 *********************************/
6497 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
6498 struct hwrm_func_backing_store_qcaps_input {
6499 /* The HWRM command request type. */
6502 * The completion ring to send the completion event on. This should
6503 * be the NQ ID returned from the `nq_alloc` HWRM command.
6507 * The sequence ID is used by the driver for tracking multiple
6508 * commands. This ID is treated as opaque data by the firmware and
6509 * the value is returned in the `hwrm_resp_hdr` upon completion.
6513 * The target ID of the command:
6514 * * 0x0-0xFFF8 - The function ID
6515 * * 0xFFF8-0xFFFE - Reserved for internal processors
6520 * A physical address pointer pointing to a host buffer that the
6521 * command's response data will be written. This can be either a host
6522 * physical address (HPA) or a guest physical address (GPA) and must
6523 * point to a physically contiguous block of memory.
6526 } __attribute__((packed));
6528 /* hwrm_func_backing_store_qcaps_output (size:512b/64B) */
6529 struct hwrm_func_backing_store_qcaps_output {
6530 /* The specific error status for the command. */
6531 uint16_t error_code;
6532 /* The HWRM command request type. */
6534 /* The sequence ID from the original command. */
6536 /* The length of the response data in number of bytes. */
6538 /* Maximum number of QP context entries supported for this function. */
6539 uint32_t qp_max_entries;
6541 * Minimum number of QP context entries that are needed to be reserved
6542 * for QP1 for the PF and its VFs. PF drivers must allocate at least
6543 * this many QP context entries, even if RoCE will not be used.
6545 uint16_t qp_min_qp1_entries;
6546 /* Maximum number of QP context entries that can be used for L2. */
6547 uint16_t qp_max_l2_entries;
6548 /* Number of bytes that must be allocated for each context entry. */
6549 uint16_t qp_entry_size;
6550 /* Maximum number of SRQ context entries that can be used for L2. */
6551 uint16_t srq_max_l2_entries;
6552 /* Maximum number of SRQ context entries supported for this function. */
6553 uint32_t srq_max_entries;
6554 /* Number of bytes that must be allocated for each context entry. */
6555 uint16_t srq_entry_size;
6556 /* Maximum number of CQ context entries that can be used for L2. */
6557 uint16_t cq_max_l2_entries;
6558 /* Maximum number of CQ context entries supported for this function. */
6559 uint32_t cq_max_entries;
6560 /* Number of bytes that must be allocated for each context entry. */
6561 uint16_t cq_entry_size;
6562 /* Maximum number of VNIC context entries supported for this function. */
6563 uint16_t vnic_max_vnic_entries;
6564 /* Maximum number of Ring table context entries supported for this function. */
6565 uint16_t vnic_max_ring_table_entries;
6566 /* Number of bytes that must be allocated for each context entry. */
6567 uint16_t vnic_entry_size;
6568 /* Maximum number of statistic context entries supported for this function. */
6569 uint32_t stat_max_entries;
6570 /* Number of bytes that must be allocated for each context entry. */
6571 uint16_t stat_entry_size;
6572 /* Maximum number of TQM context entries supported per ring. */
6573 uint16_t tqm_max_entries_per_ring;
6574 /* Number of bytes that must be allocated for each context entry. */
6575 uint16_t tqm_entry_size;
6576 /* Number of bytes that must be allocated for each context entry. */
6577 uint16_t mrav_entry_size;
6578 /* Maximum number of MR/AV context entries supported for this function. */
6579 uint32_t mrav_max_entries;
6580 /* Maximum number of Timer context entries supported for this function. */
6581 uint32_t tim_max_entries;
6582 /* Number of bytes that must be allocated for each context entry. */
6583 uint16_t tim_entry_size;
6586 * This field is used in Output records to indicate that the output
6587 * is completely written to RAM. This field should be read as '1'
6588 * to indicate that the output has been completely written.
6589 * When writing a command completion or response to an internal processor,
6590 * the order of writes has to be such that this field is written last.
6593 } __attribute__((packed));
6595 /*******************************
6596 * hwrm_func_backing_store_cfg *
6597 *******************************/
6600 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
6601 struct hwrm_func_backing_store_cfg_input {
6602 /* The HWRM command request type. */
6605 * The completion ring to send the completion event on. This should
6606 * be the NQ ID returned from the `nq_alloc` HWRM command.
6610 * The sequence ID is used by the driver for tracking multiple
6611 * commands. This ID is treated as opaque data by the firmware and
6612 * the value is returned in the `hwrm_resp_hdr` upon completion.
6616 * The target ID of the command:
6617 * * 0x0-0xFFF8 - The function ID
6618 * * 0xFFF8-0xFFFE - Reserved for internal processors
6623 * A physical address pointer pointing to a host buffer that the
6624 * command's response data will be written. This can be either a host
6625 * physical address (HPA) or a guest physical address (GPA) and must
6626 * point to a physically contiguous block of memory.
6631 * When set, the firmware only uses on-chip resources and does not
6632 * expect any backing store to be provided by the host driver. This
6633 * mode provides minimal L2 functionality (e.g. limited L2 resources,
6636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
6640 * This bit must be '1' for the qp fields to be
6643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
6646 * This bit must be '1' for the srq fields to be
6649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
6652 * This bit must be '1' for the cq fields to be
6655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
6658 * This bit must be '1' for the vnic fields to be
6661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
6664 * This bit must be '1' for the stat fields to be
6667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
6670 * This bit must be '1' for the tqm_sp fields to be
6673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
6676 * This bit must be '1' for the tqm_ring0 fields to be
6679 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
6682 * This bit must be '1' for the tqm_ring1 fields to be
6685 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
6688 * This bit must be '1' for the tqm_ring2 fields to be
6691 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
6694 * This bit must be '1' for the tqm_ring3 fields to be
6697 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
6700 * This bit must be '1' for the tqm_ring4 fields to be
6703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
6706 * This bit must be '1' for the tqm_ring5 fields to be
6709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
6712 * This bit must be '1' for the tqm_ring6 fields to be
6715 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
6718 * This bit must be '1' for the tqm_ring7 fields to be
6721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
6724 * This bit must be '1' for the mrav fields to be
6727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
6730 * This bit must be '1' for the tim fields to be
6733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
6735 /* QPC page size and level. */
6736 uint8_t qpc_pg_size_qpc_lvl;
6737 /* QPC PBL indirect levels. */
6738 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
6740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
6741 /* PBL pointer is physical start address. */
6742 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
6744 /* PBL pointer points to PTE table. */
6745 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
6747 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6748 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
6750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
6751 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
6752 /* QPC page size. */
6753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
6755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
6757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
6758 (UINT32_C(0x0) << 4)
6760 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
6761 (UINT32_C(0x1) << 4)
6763 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
6764 (UINT32_C(0x2) << 4)
6766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
6767 (UINT32_C(0x3) << 4)
6769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
6770 (UINT32_C(0x4) << 4)
6772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
6773 (UINT32_C(0x5) << 4)
6774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
6775 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
6776 /* SRQ page size and level. */
6777 uint8_t srq_pg_size_srq_lvl;
6778 /* SRQ PBL indirect levels. */
6779 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
6781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
6782 /* PBL pointer is physical start address. */
6783 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
6785 /* PBL pointer points to PTE table. */
6786 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
6788 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
6791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
6792 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
6793 /* SRQ page size. */
6794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
6796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
6798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
6799 (UINT32_C(0x0) << 4)
6801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
6802 (UINT32_C(0x1) << 4)
6804 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
6805 (UINT32_C(0x2) << 4)
6807 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
6808 (UINT32_C(0x3) << 4)
6810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
6811 (UINT32_C(0x4) << 4)
6813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
6814 (UINT32_C(0x5) << 4)
6815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
6816 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
6817 /* CQ page size and level. */
6818 uint8_t cq_pg_size_cq_lvl;
6819 /* CQ PBL indirect levels. */
6820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
6822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
6823 /* PBL pointer is physical start address. */
6824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
6826 /* PBL pointer points to PTE table. */
6827 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
6829 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
6832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
6833 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
6835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
6837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
6839 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
6840 (UINT32_C(0x0) << 4)
6842 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
6843 (UINT32_C(0x1) << 4)
6845 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
6846 (UINT32_C(0x2) << 4)
6848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
6849 (UINT32_C(0x3) << 4)
6851 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
6852 (UINT32_C(0x4) << 4)
6854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
6855 (UINT32_C(0x5) << 4)
6856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
6857 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
6858 /* VNIC page size and level. */
6859 uint8_t vnic_pg_size_vnic_lvl;
6860 /* VNIC PBL indirect levels. */
6861 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
6863 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
6864 /* PBL pointer is physical start address. */
6865 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
6867 /* PBL pointer points to PTE table. */
6868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
6870 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6871 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
6873 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
6874 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
6875 /* VNIC page size. */
6876 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
6878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
6880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
6881 (UINT32_C(0x0) << 4)
6883 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
6884 (UINT32_C(0x1) << 4)
6886 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
6887 (UINT32_C(0x2) << 4)
6889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
6890 (UINT32_C(0x3) << 4)
6892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
6893 (UINT32_C(0x4) << 4)
6895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
6896 (UINT32_C(0x5) << 4)
6897 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
6898 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
6899 /* Stat page size and level. */
6900 uint8_t stat_pg_size_stat_lvl;
6901 /* Stat PBL indirect levels. */
6902 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
6904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
6905 /* PBL pointer is physical start address. */
6906 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
6908 /* PBL pointer points to PTE table. */
6909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
6911 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6912 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
6914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
6915 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
6916 /* Stat page size. */
6917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
6919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
6921 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
6922 (UINT32_C(0x0) << 4)
6924 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
6925 (UINT32_C(0x1) << 4)
6927 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
6928 (UINT32_C(0x2) << 4)
6930 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
6931 (UINT32_C(0x3) << 4)
6933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
6934 (UINT32_C(0x4) << 4)
6936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
6937 (UINT32_C(0x5) << 4)
6938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
6939 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
6940 /* TQM slow path page size and level. */
6941 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
6942 /* TQM slow path PBL indirect levels. */
6943 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
6945 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
6946 /* PBL pointer is physical start address. */
6947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
6949 /* PBL pointer points to PTE table. */
6950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
6952 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6953 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
6955 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
6956 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
6957 /* TQM slow path page size. */
6958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
6960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
6962 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
6963 (UINT32_C(0x0) << 4)
6965 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
6966 (UINT32_C(0x1) << 4)
6968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
6969 (UINT32_C(0x2) << 4)
6971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
6972 (UINT32_C(0x3) << 4)
6974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
6975 (UINT32_C(0x4) << 4)
6977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
6978 (UINT32_C(0x5) << 4)
6979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
6980 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
6981 /* TQM ring 0 page size and level. */
6982 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
6983 /* TQM ring 0 PBL indirect levels. */
6984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
6986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
6987 /* PBL pointer is physical start address. */
6988 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
6990 /* PBL pointer points to PTE table. */
6991 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
6993 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
6994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
6996 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
6997 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
6998 /* TQM ring 0 page size. */
6999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
7001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
7003 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
7004 (UINT32_C(0x0) << 4)
7006 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
7007 (UINT32_C(0x1) << 4)
7009 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
7010 (UINT32_C(0x2) << 4)
7012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
7013 (UINT32_C(0x3) << 4)
7015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
7016 (UINT32_C(0x4) << 4)
7018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
7019 (UINT32_C(0x5) << 4)
7020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
7021 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
7022 /* TQM ring 1 page size and level. */
7023 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
7024 /* TQM ring 1 PBL indirect levels. */
7025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
7027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
7028 /* PBL pointer is physical start address. */
7029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
7031 /* PBL pointer points to PTE table. */
7032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
7034 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
7037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
7038 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
7039 /* TQM ring 1 page size. */
7040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
7042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
7044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
7045 (UINT32_C(0x0) << 4)
7047 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
7048 (UINT32_C(0x1) << 4)
7050 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
7051 (UINT32_C(0x2) << 4)
7053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
7054 (UINT32_C(0x3) << 4)
7056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
7057 (UINT32_C(0x4) << 4)
7059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
7060 (UINT32_C(0x5) << 4)
7061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
7062 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
7063 /* TQM ring 2 page size and level. */
7064 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
7065 /* TQM ring 2 PBL indirect levels. */
7066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
7068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
7069 /* PBL pointer is physical start address. */
7070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
7072 /* PBL pointer points to PTE table. */
7073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
7075 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7076 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
7078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
7079 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
7080 /* TQM ring 2 page size. */
7081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
7083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
7085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
7086 (UINT32_C(0x0) << 4)
7088 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
7089 (UINT32_C(0x1) << 4)
7091 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
7092 (UINT32_C(0x2) << 4)
7094 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
7095 (UINT32_C(0x3) << 4)
7097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
7098 (UINT32_C(0x4) << 4)
7100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
7101 (UINT32_C(0x5) << 4)
7102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
7103 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
7104 /* TQM ring 3 page size and level. */
7105 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
7106 /* TQM ring 3 PBL indirect levels. */
7107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
7109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
7110 /* PBL pointer is physical start address. */
7111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
7113 /* PBL pointer points to PTE table. */
7114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
7116 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7117 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
7119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
7120 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
7121 /* TQM ring 3 page size. */
7122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
7124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
7126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
7127 (UINT32_C(0x0) << 4)
7129 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
7130 (UINT32_C(0x1) << 4)
7132 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
7133 (UINT32_C(0x2) << 4)
7135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
7136 (UINT32_C(0x3) << 4)
7138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
7139 (UINT32_C(0x4) << 4)
7141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
7142 (UINT32_C(0x5) << 4)
7143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
7144 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
7145 /* TQM ring 4 page size and level. */
7146 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
7147 /* TQM ring 4 PBL indirect levels. */
7148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
7150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
7151 /* PBL pointer is physical start address. */
7152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
7154 /* PBL pointer points to PTE table. */
7155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
7157 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7158 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
7160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
7161 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
7162 /* TQM ring 4 page size. */
7163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
7165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
7167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
7168 (UINT32_C(0x0) << 4)
7170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
7171 (UINT32_C(0x1) << 4)
7173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
7174 (UINT32_C(0x2) << 4)
7176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
7177 (UINT32_C(0x3) << 4)
7179 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
7180 (UINT32_C(0x4) << 4)
7182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
7183 (UINT32_C(0x5) << 4)
7184 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
7185 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
7186 /* TQM ring 5 page size and level. */
7187 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
7188 /* TQM ring 5 PBL indirect levels. */
7189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
7191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
7192 /* PBL pointer is physical start address. */
7193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
7195 /* PBL pointer points to PTE table. */
7196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
7198 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7199 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
7201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
7202 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
7203 /* TQM ring 5 page size. */
7204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
7206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
7208 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
7209 (UINT32_C(0x0) << 4)
7211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
7212 (UINT32_C(0x1) << 4)
7214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
7215 (UINT32_C(0x2) << 4)
7217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
7218 (UINT32_C(0x3) << 4)
7220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
7221 (UINT32_C(0x4) << 4)
7223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
7224 (UINT32_C(0x5) << 4)
7225 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
7226 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
7227 /* TQM ring 6 page size and level. */
7228 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
7229 /* TQM ring 6 PBL indirect levels. */
7230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
7232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
7233 /* PBL pointer is physical start address. */
7234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
7236 /* PBL pointer points to PTE table. */
7237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
7239 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7240 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
7242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
7243 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
7244 /* TQM ring 6 page size. */
7245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
7247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
7249 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
7250 (UINT32_C(0x0) << 4)
7252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
7253 (UINT32_C(0x1) << 4)
7255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
7256 (UINT32_C(0x2) << 4)
7258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
7259 (UINT32_C(0x3) << 4)
7261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
7262 (UINT32_C(0x4) << 4)
7264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
7265 (UINT32_C(0x5) << 4)
7266 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
7267 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
7268 /* TQM ring 7 page size and level. */
7269 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
7270 /* TQM ring 7 PBL indirect levels. */
7271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
7273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
7274 /* PBL pointer is physical start address. */
7275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
7277 /* PBL pointer points to PTE table. */
7278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
7280 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7281 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
7283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
7284 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
7285 /* TQM ring 7 page size. */
7286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
7288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
7290 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
7291 (UINT32_C(0x0) << 4)
7293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
7294 (UINT32_C(0x1) << 4)
7296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
7297 (UINT32_C(0x2) << 4)
7299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
7300 (UINT32_C(0x3) << 4)
7302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
7303 (UINT32_C(0x4) << 4)
7305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
7306 (UINT32_C(0x5) << 4)
7307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
7308 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
7309 /* MR/AV page size and level. */
7310 uint8_t mrav_pg_size_mrav_lvl;
7311 /* MR/AV PBL indirect levels. */
7312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
7314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
7315 /* PBL pointer is physical start address. */
7316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
7318 /* PBL pointer points to PTE table. */
7319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
7321 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7322 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
7324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
7325 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
7326 /* MR/AV page size. */
7327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
7329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
7331 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
7332 (UINT32_C(0x0) << 4)
7334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
7335 (UINT32_C(0x1) << 4)
7337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
7338 (UINT32_C(0x2) << 4)
7340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
7341 (UINT32_C(0x3) << 4)
7343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
7344 (UINT32_C(0x4) << 4)
7346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
7347 (UINT32_C(0x5) << 4)
7348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
7349 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
7350 /* Timer page size and level. */
7351 uint8_t tim_pg_size_tim_lvl;
7352 /* Timer PBL indirect levels. */
7353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
7355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
7356 /* PBL pointer is physical start address. */
7357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
7359 /* PBL pointer points to PTE table. */
7360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
7362 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7363 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
7365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
7366 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
7367 /* Timer page size. */
7368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
7370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
7372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
7373 (UINT32_C(0x0) << 4)
7375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
7376 (UINT32_C(0x1) << 4)
7378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
7379 (UINT32_C(0x2) << 4)
7381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
7382 (UINT32_C(0x3) << 4)
7384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
7385 (UINT32_C(0x4) << 4)
7387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
7388 (UINT32_C(0x5) << 4)
7389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
7390 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
7391 /* QP page directory. */
7392 uint64_t qpc_page_dir;
7393 /* SRQ page directory. */
7394 uint64_t srq_page_dir;
7395 /* CQ page directory. */
7396 uint64_t cq_page_dir;
7397 /* VNIC page directory. */
7398 uint64_t vnic_page_dir;
7399 /* Stat page directory. */
7400 uint64_t stat_page_dir;
7401 /* TQM slowpath page directory. */
7402 uint64_t tqm_sp_page_dir;
7403 /* TQM ring 0 page directory. */
7404 uint64_t tqm_ring0_page_dir;
7405 /* TQM ring 1 page directory. */
7406 uint64_t tqm_ring1_page_dir;
7407 /* TQM ring 2 page directory. */
7408 uint64_t tqm_ring2_page_dir;
7409 /* TQM ring 3 page directory. */
7410 uint64_t tqm_ring3_page_dir;
7411 /* TQM ring 4 page directory. */
7412 uint64_t tqm_ring4_page_dir;
7413 /* TQM ring 5 page directory. */
7414 uint64_t tqm_ring5_page_dir;
7415 /* TQM ring 6 page directory. */
7416 uint64_t tqm_ring6_page_dir;
7417 /* TQM ring 7 page directory. */
7418 uint64_t tqm_ring7_page_dir;
7419 /* MR/AV page directory. */
7420 uint64_t mrav_page_dir;
7421 /* Timer page directory. */
7422 uint64_t tim_page_dir;
7423 /* Number of QPs. */
7424 uint32_t qp_num_entries;
7425 /* Number of SRQs. */
7426 uint32_t srq_num_entries;
7427 /* Number of CQs. */
7428 uint32_t cq_num_entries;
7429 /* Number of Stats. */
7430 uint32_t stat_num_entries;
7431 /* Number of TQM slowpath entries. */
7432 uint32_t tqm_sp_num_entries;
7433 /* Number of TQM ring 0 entries. */
7434 uint32_t tqm_ring0_num_entries;
7435 /* Number of TQM ring 1 entries. */
7436 uint32_t tqm_ring1_num_entries;
7437 /* Number of TQM ring 2 entries. */
7438 uint32_t tqm_ring2_num_entries;
7439 /* Number of TQM ring 3 entries. */
7440 uint32_t tqm_ring3_num_entries;
7441 /* Number of TQM ring 4 entries. */
7442 uint32_t tqm_ring4_num_entries;
7443 /* Number of TQM ring 5 entries. */
7444 uint32_t tqm_ring5_num_entries;
7445 /* Number of TQM ring 6 entries. */
7446 uint32_t tqm_ring6_num_entries;
7447 /* Number of TQM ring 7 entries. */
7448 uint32_t tqm_ring7_num_entries;
7449 /* Number of MR/AV entries. */
7450 uint32_t mrav_num_entries;
7451 /* Number of Timer entries. */
7452 uint32_t tim_num_entries;
7453 /* Number of entries to reserve for QP1 */
7454 uint16_t qp_num_qp1_entries;
7455 /* Number of entries to reserve for L2 */
7456 uint16_t qp_num_l2_entries;
7457 /* Number of bytes that have been allocated for each context entry. */
7458 uint16_t qp_entry_size;
7459 /* Number of entries to reserve for L2 */
7460 uint16_t srq_num_l2_entries;
7461 /* Number of bytes that have been allocated for each context entry. */
7462 uint16_t srq_entry_size;
7463 /* Number of entries to reserve for L2 */
7464 uint16_t cq_num_l2_entries;
7465 /* Number of bytes that have been allocated for each context entry. */
7466 uint16_t cq_entry_size;
7467 /* Number of entries to reserve for VNIC entries */
7468 uint16_t vnic_num_vnic_entries;
7469 /* Number of entries to reserve for Ring table entries */
7470 uint16_t vnic_num_ring_table_entries;
7471 /* Number of bytes that have been allocated for each context entry. */
7472 uint16_t vnic_entry_size;
7473 /* Number of bytes that have been allocated for each context entry. */
7474 uint16_t stat_entry_size;
7475 /* Number of bytes that have been allocated for each context entry. */
7476 uint16_t tqm_entry_size;
7477 /* Number of bytes that have been allocated for each context entry. */
7478 uint16_t mrav_entry_size;
7479 /* Number of bytes that have been allocated for each context entry. */
7480 uint16_t tim_entry_size;
7481 } __attribute__((packed));
7483 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
7484 struct hwrm_func_backing_store_cfg_output {
7485 /* The specific error status for the command. */
7486 uint16_t error_code;
7487 /* The HWRM command request type. */
7489 /* The sequence ID from the original command. */
7491 /* The length of the response data in number of bytes. */
7493 uint8_t unused_0[7];
7495 * This field is used in Output records to indicate that the output
7496 * is completely written to RAM. This field should be read as '1'
7497 * to indicate that the output has been completely written.
7498 * When writing a command completion or response to an internal processor,
7499 * the order of writes has to be such that this field is written last.
7502 } __attribute__((packed));
7504 /********************************
7505 * hwrm_func_backing_store_qcfg *
7506 ********************************/
7509 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
7510 struct hwrm_func_backing_store_qcfg_input {
7511 /* The HWRM command request type. */
7514 * The completion ring to send the completion event on. This should
7515 * be the NQ ID returned from the `nq_alloc` HWRM command.
7519 * The sequence ID is used by the driver for tracking multiple
7520 * commands. This ID is treated as opaque data by the firmware and
7521 * the value is returned in the `hwrm_resp_hdr` upon completion.
7525 * The target ID of the command:
7526 * * 0x0-0xFFF8 - The function ID
7527 * * 0xFFF8-0xFFFE - Reserved for internal processors
7532 * A physical address pointer pointing to a host buffer that the
7533 * command's response data will be written. This can be either a host
7534 * physical address (HPA) or a guest physical address (GPA) and must
7535 * point to a physically contiguous block of memory.
7538 } __attribute__((packed));
7540 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
7541 struct hwrm_func_backing_store_qcfg_output {
7542 /* The specific error status for the command. */
7543 uint16_t error_code;
7544 /* The HWRM command request type. */
7546 /* The sequence ID from the original command. */
7548 /* The length of the response data in number of bytes. */
7552 * When set, the firmware only uses on-chip resources and does not
7553 * expect any backing store to be provided by the host driver. This
7554 * mode provides minimal L2 functionality (e.g. limited L2 resources,
7557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
7559 uint8_t unused_0[4];
7561 * This bit must be '1' for the qp fields to be
7564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
7567 * This bit must be '1' for the srq fields to be
7570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
7573 * This bit must be '1' for the cq fields to be
7576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
7579 * This bit must be '1' for the vnic fields to be
7582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
7585 * This bit must be '1' for the stat fields to be
7588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
7591 * This bit must be '1' for the tqm_sp fields to be
7594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
7597 * This bit must be '1' for the tqm_ring0 fields to be
7600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
7603 * This bit must be '1' for the tqm_ring1 fields to be
7606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
7609 * This bit must be '1' for the tqm_ring2 fields to be
7612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
7615 * This bit must be '1' for the tqm_ring3 fields to be
7618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
7621 * This bit must be '1' for the tqm_ring4 fields to be
7624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
7627 * This bit must be '1' for the tqm_ring5 fields to be
7630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
7633 * This bit must be '1' for the tqm_ring6 fields to be
7636 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
7639 * This bit must be '1' for the tqm_ring7 fields to be
7642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
7645 * This bit must be '1' for the mrav fields to be
7648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
7651 * This bit must be '1' for the tim fields to be
7654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
7656 /* QPC page size and level. */
7657 uint8_t qpc_pg_size_qpc_lvl;
7658 /* QPC PBL indirect levels. */
7659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
7661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
7662 /* PBL pointer is physical start address. */
7663 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
7665 /* PBL pointer points to PTE table. */
7666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
7668 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7669 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
7671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
7672 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
7673 /* QPC page size. */
7674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
7676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
7678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
7679 (UINT32_C(0x0) << 4)
7681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
7682 (UINT32_C(0x1) << 4)
7684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
7685 (UINT32_C(0x2) << 4)
7687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
7688 (UINT32_C(0x3) << 4)
7690 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
7691 (UINT32_C(0x4) << 4)
7693 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
7694 (UINT32_C(0x5) << 4)
7695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
7696 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
7697 /* SRQ page size and level. */
7698 uint8_t srq_pg_size_srq_lvl;
7699 /* SRQ PBL indirect levels. */
7700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
7702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
7703 /* PBL pointer is physical start address. */
7704 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
7706 /* PBL pointer points to PTE table. */
7707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
7709 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7710 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
7712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
7713 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
7714 /* SRQ page size. */
7715 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
7717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
7719 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
7720 (UINT32_C(0x0) << 4)
7722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
7723 (UINT32_C(0x1) << 4)
7725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
7726 (UINT32_C(0x2) << 4)
7728 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
7729 (UINT32_C(0x3) << 4)
7731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
7732 (UINT32_C(0x4) << 4)
7734 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
7735 (UINT32_C(0x5) << 4)
7736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
7737 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
7738 /* CQ page size and level. */
7739 uint8_t cq_pg_size_cq_lvl;
7740 /* CQ PBL indirect levels. */
7741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
7743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
7744 /* PBL pointer is physical start address. */
7745 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
7747 /* PBL pointer points to PTE table. */
7748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
7750 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7751 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
7753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
7754 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
7756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
7758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
7760 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
7761 (UINT32_C(0x0) << 4)
7763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
7764 (UINT32_C(0x1) << 4)
7766 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
7767 (UINT32_C(0x2) << 4)
7769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
7770 (UINT32_C(0x3) << 4)
7772 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
7773 (UINT32_C(0x4) << 4)
7775 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
7776 (UINT32_C(0x5) << 4)
7777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
7778 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
7779 /* VNIC page size and level. */
7780 uint8_t vnic_pg_size_vnic_lvl;
7781 /* VNIC PBL indirect levels. */
7782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
7784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
7785 /* PBL pointer is physical start address. */
7786 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
7788 /* PBL pointer points to PTE table. */
7789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
7791 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7792 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
7794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
7795 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
7796 /* VNIC page size. */
7797 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
7799 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
7801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
7802 (UINT32_C(0x0) << 4)
7804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
7805 (UINT32_C(0x1) << 4)
7807 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
7808 (UINT32_C(0x2) << 4)
7810 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
7811 (UINT32_C(0x3) << 4)
7813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
7814 (UINT32_C(0x4) << 4)
7816 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
7817 (UINT32_C(0x5) << 4)
7818 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
7819 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
7820 /* Stat page size and level. */
7821 uint8_t stat_pg_size_stat_lvl;
7822 /* Stat PBL indirect levels. */
7823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
7825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
7826 /* PBL pointer is physical start address. */
7827 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
7829 /* PBL pointer points to PTE table. */
7830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
7832 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7833 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
7835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
7836 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
7837 /* Stat page size. */
7838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
7840 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
7842 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
7843 (UINT32_C(0x0) << 4)
7845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
7846 (UINT32_C(0x1) << 4)
7848 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
7849 (UINT32_C(0x2) << 4)
7851 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
7852 (UINT32_C(0x3) << 4)
7854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
7855 (UINT32_C(0x4) << 4)
7857 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
7858 (UINT32_C(0x5) << 4)
7859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
7860 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
7861 /* TQM slow path page size and level. */
7862 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
7863 /* TQM slow path PBL indirect levels. */
7864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
7866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
7867 /* PBL pointer is physical start address. */
7868 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
7870 /* PBL pointer points to PTE table. */
7871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
7873 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7874 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
7876 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
7877 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
7878 /* TQM slow path page size. */
7879 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
7881 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
7883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
7884 (UINT32_C(0x0) << 4)
7886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
7887 (UINT32_C(0x1) << 4)
7889 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
7890 (UINT32_C(0x2) << 4)
7892 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
7893 (UINT32_C(0x3) << 4)
7895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
7896 (UINT32_C(0x4) << 4)
7898 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
7899 (UINT32_C(0x5) << 4)
7900 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
7901 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
7902 /* TQM ring 0 page size and level. */
7903 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
7904 /* TQM ring 0 PBL indirect levels. */
7905 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
7907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
7908 /* PBL pointer is physical start address. */
7909 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
7911 /* PBL pointer points to PTE table. */
7912 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
7914 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7915 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
7917 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
7918 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
7919 /* TQM ring 0 page size. */
7920 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
7922 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
7924 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
7925 (UINT32_C(0x0) << 4)
7927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
7928 (UINT32_C(0x1) << 4)
7930 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
7931 (UINT32_C(0x2) << 4)
7933 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
7934 (UINT32_C(0x3) << 4)
7936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
7937 (UINT32_C(0x4) << 4)
7939 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
7940 (UINT32_C(0x5) << 4)
7941 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
7942 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
7943 /* TQM ring 1 page size and level. */
7944 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
7945 /* TQM ring 1 PBL indirect levels. */
7946 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
7948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
7949 /* PBL pointer is physical start address. */
7950 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
7952 /* PBL pointer points to PTE table. */
7953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
7955 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7956 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
7958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
7959 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
7960 /* TQM ring 1 page size. */
7961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
7963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
7965 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
7966 (UINT32_C(0x0) << 4)
7968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
7969 (UINT32_C(0x1) << 4)
7971 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
7972 (UINT32_C(0x2) << 4)
7974 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
7975 (UINT32_C(0x3) << 4)
7977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
7978 (UINT32_C(0x4) << 4)
7980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
7981 (UINT32_C(0x5) << 4)
7982 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
7983 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
7984 /* TQM ring 2 page size and level. */
7985 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
7986 /* TQM ring 2 PBL indirect levels. */
7987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
7989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
7990 /* PBL pointer is physical start address. */
7991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
7993 /* PBL pointer points to PTE table. */
7994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
7996 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7997 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
7999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
8000 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
8001 /* TQM ring 2 page size. */
8002 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
8004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
8006 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
8007 (UINT32_C(0x0) << 4)
8009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
8010 (UINT32_C(0x1) << 4)
8012 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
8013 (UINT32_C(0x2) << 4)
8015 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
8016 (UINT32_C(0x3) << 4)
8018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
8019 (UINT32_C(0x4) << 4)
8021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
8022 (UINT32_C(0x5) << 4)
8023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
8024 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
8025 /* TQM ring 3 page size and level. */
8026 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
8027 /* TQM ring 3 PBL indirect levels. */
8028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
8030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
8031 /* PBL pointer is physical start address. */
8032 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
8034 /* PBL pointer points to PTE table. */
8035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
8037 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8038 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
8040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
8041 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
8042 /* TQM ring 3 page size. */
8043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
8045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
8047 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
8048 (UINT32_C(0x0) << 4)
8050 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
8051 (UINT32_C(0x1) << 4)
8053 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
8054 (UINT32_C(0x2) << 4)
8056 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
8057 (UINT32_C(0x3) << 4)
8059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
8060 (UINT32_C(0x4) << 4)
8062 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
8063 (UINT32_C(0x5) << 4)
8064 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
8065 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
8066 /* TQM ring 4 page size and level. */
8067 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
8068 /* TQM ring 4 PBL indirect levels. */
8069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
8071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
8072 /* PBL pointer is physical start address. */
8073 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
8075 /* PBL pointer points to PTE table. */
8076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
8078 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8079 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
8081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
8082 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
8083 /* TQM ring 4 page size. */
8084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
8086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
8088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
8089 (UINT32_C(0x0) << 4)
8091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
8092 (UINT32_C(0x1) << 4)
8094 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
8095 (UINT32_C(0x2) << 4)
8097 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
8098 (UINT32_C(0x3) << 4)
8100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
8101 (UINT32_C(0x4) << 4)
8103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
8104 (UINT32_C(0x5) << 4)
8105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
8106 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
8107 /* TQM ring 5 page size and level. */
8108 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
8109 /* TQM ring 5 PBL indirect levels. */
8110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
8112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
8113 /* PBL pointer is physical start address. */
8114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
8116 /* PBL pointer points to PTE table. */
8117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
8119 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8120 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
8122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
8123 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
8124 /* TQM ring 5 page size. */
8125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
8127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
8129 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
8130 (UINT32_C(0x0) << 4)
8132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
8133 (UINT32_C(0x1) << 4)
8135 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
8136 (UINT32_C(0x2) << 4)
8138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
8139 (UINT32_C(0x3) << 4)
8141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
8142 (UINT32_C(0x4) << 4)
8144 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
8145 (UINT32_C(0x5) << 4)
8146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
8147 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
8148 /* TQM ring 6 page size and level. */
8149 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
8150 /* TQM ring 6 PBL indirect levels. */
8151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
8153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
8154 /* PBL pointer is physical start address. */
8155 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
8157 /* PBL pointer points to PTE table. */
8158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
8160 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
8163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
8164 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
8165 /* TQM ring 6 page size. */
8166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
8168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
8170 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
8171 (UINT32_C(0x0) << 4)
8173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
8174 (UINT32_C(0x1) << 4)
8176 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
8177 (UINT32_C(0x2) << 4)
8179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
8180 (UINT32_C(0x3) << 4)
8182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
8183 (UINT32_C(0x4) << 4)
8185 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
8186 (UINT32_C(0x5) << 4)
8187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
8188 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
8189 /* TQM ring 7 page size and level. */
8190 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
8191 /* TQM ring 7 PBL indirect levels. */
8192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
8194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
8195 /* PBL pointer is physical start address. */
8196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
8198 /* PBL pointer points to PTE table. */
8199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
8201 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
8204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
8205 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
8206 /* TQM ring 7 page size. */
8207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
8209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
8211 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
8212 (UINT32_C(0x0) << 4)
8214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
8215 (UINT32_C(0x1) << 4)
8217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
8218 (UINT32_C(0x2) << 4)
8220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
8221 (UINT32_C(0x3) << 4)
8223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
8224 (UINT32_C(0x4) << 4)
8226 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
8227 (UINT32_C(0x5) << 4)
8228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
8229 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
8230 /* MR/AV page size and level. */
8231 uint8_t mrav_pg_size_mrav_lvl;
8232 /* MR/AV PBL indirect levels. */
8233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
8235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
8236 /* PBL pointer is physical start address. */
8237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
8239 /* PBL pointer points to PTE table. */
8240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
8242 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
8245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
8246 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
8247 /* MR/AV page size. */
8248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
8250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
8252 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
8253 (UINT32_C(0x0) << 4)
8255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
8256 (UINT32_C(0x1) << 4)
8258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
8259 (UINT32_C(0x2) << 4)
8261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
8262 (UINT32_C(0x3) << 4)
8264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
8265 (UINT32_C(0x4) << 4)
8267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
8268 (UINT32_C(0x5) << 4)
8269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
8270 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
8271 /* Timer page size and level. */
8272 uint8_t tim_pg_size_tim_lvl;
8273 /* Timer PBL indirect levels. */
8274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
8276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
8277 /* PBL pointer is physical start address. */
8278 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
8280 /* PBL pointer points to PTE table. */
8281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
8283 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
8286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
8287 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
8288 /* Timer page size. */
8289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
8291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
8293 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
8294 (UINT32_C(0x0) << 4)
8296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
8297 (UINT32_C(0x1) << 4)
8299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
8300 (UINT32_C(0x2) << 4)
8302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
8303 (UINT32_C(0x3) << 4)
8305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
8306 (UINT32_C(0x4) << 4)
8308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
8309 (UINT32_C(0x5) << 4)
8310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
8311 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
8312 /* QP page directory. */
8313 uint64_t qpc_page_dir;
8314 /* SRQ page directory. */
8315 uint64_t srq_page_dir;
8316 /* CQ page directory. */
8317 uint64_t cq_page_dir;
8318 /* VNIC page directory. */
8319 uint64_t vnic_page_dir;
8320 /* Stat page directory. */
8321 uint64_t stat_page_dir;
8322 /* TQM slowpath page directory. */
8323 uint64_t tqm_sp_page_dir;
8324 /* TQM ring 0 page directory. */
8325 uint64_t tqm_ring0_page_dir;
8326 /* TQM ring 1 page directory. */
8327 uint64_t tqm_ring1_page_dir;
8328 /* TQM ring 2 page directory. */
8329 uint64_t tqm_ring2_page_dir;
8330 /* TQM ring 3 page directory. */
8331 uint64_t tqm_ring3_page_dir;
8332 /* TQM ring 4 page directory. */
8333 uint64_t tqm_ring4_page_dir;
8334 /* TQM ring 5 page directory. */
8335 uint64_t tqm_ring5_page_dir;
8336 /* TQM ring 6 page directory. */
8337 uint64_t tqm_ring6_page_dir;
8338 /* TQM ring 7 page directory. */
8339 uint64_t tqm_ring7_page_dir;
8340 /* MR/AV page directory. */
8341 uint64_t mrav_page_dir;
8342 /* Timer page directory. */
8343 uint64_t tim_page_dir;
8344 /* Number of entries to reserve for QP1 */
8345 uint16_t qp_num_qp1_entries;
8346 /* Number of entries to reserve for L2 */
8347 uint16_t qp_num_l2_entries;
8348 /* Number of QPs. */
8349 uint32_t qp_num_entries;
8350 /* Number of SRQs. */
8351 uint32_t srq_num_entries;
8352 /* Number of entries to reserve for L2 */
8353 uint16_t srq_num_l2_entries;
8354 /* Number of entries to reserve for L2 */
8355 uint16_t cq_num_l2_entries;
8356 /* Number of CQs. */
8357 uint32_t cq_num_entries;
8358 /* Number of entries to reserve for VNIC entries */
8359 uint16_t vnic_num_vnic_entries;
8360 /* Number of entries to reserve for Ring table entries */
8361 uint16_t vnic_num_ring_table_entries;
8362 /* Number of Stats. */
8363 uint32_t stat_num_entries;
8364 /* Number of TQM slowpath entries. */
8365 uint32_t tqm_sp_num_entries;
8366 /* Number of TQM ring 0 entries. */
8367 uint32_t tqm_ring0_num_entries;
8368 /* Number of TQM ring 1 entries. */
8369 uint32_t tqm_ring1_num_entries;
8370 /* Number of TQM ring 2 entries. */
8371 uint32_t tqm_ring2_num_entries;
8372 /* Number of TQM ring 3 entries. */
8373 uint32_t tqm_ring3_num_entries;
8374 /* Number of TQM ring 4 entries. */
8375 uint32_t tqm_ring4_num_entries;
8376 /* Number of TQM ring 5 entries. */
8377 uint32_t tqm_ring5_num_entries;
8378 /* Number of TQM ring 6 entries. */
8379 uint32_t tqm_ring6_num_entries;
8380 /* Number of TQM ring 7 entries. */
8381 uint32_t tqm_ring7_num_entries;
8382 /* Number of MR/AV entries. */
8383 uint32_t mrav_num_entries;
8384 /* Number of Timer entries. */
8385 uint32_t tim_num_entries;
8386 uint8_t unused_1[7];
8388 * This field is used in Output records to indicate that the output
8389 * is completely written to RAM. This field should be read as '1'
8390 * to indicate that the output has been completely written.
8391 * When writing a command completion or response to an internal processor,
8392 * the order of writes has to be such that this field is written last.
8395 } __attribute__((packed));
8397 /*********************
8398 * hwrm_port_phy_cfg *
8399 *********************/
8402 /* hwrm_port_phy_cfg_input (size:448b/56B) */
8403 struct hwrm_port_phy_cfg_input {
8404 /* The HWRM command request type. */
8407 * The completion ring to send the completion event on. This should
8408 * be the NQ ID returned from the `nq_alloc` HWRM command.
8412 * The sequence ID is used by the driver for tracking multiple
8413 * commands. This ID is treated as opaque data by the firmware and
8414 * the value is returned in the `hwrm_resp_hdr` upon completion.
8418 * The target ID of the command:
8419 * * 0x0-0xFFF8 - The function ID
8420 * * 0xFFF8-0xFFFE - Reserved for internal processors
8425 * A physical address pointer pointing to a host buffer that the
8426 * command's response data will be written. This can be either a host
8427 * physical address (HPA) or a guest physical address (GPA) and must
8428 * point to a physically contiguous block of memory.
8433 * When this bit is set to '1', the PHY for the port shall
8436 * # If this bit is set to 1, then the HWRM shall reset the
8437 * PHY after applying PHY configuration changes specified
8439 * # In order to guarantee that PHY configuration changes
8440 * specified in this command take effect, the HWRM
8441 * client should set this flag to 1.
8442 * # If this bit is not set to 1, then the HWRM may reset
8443 * the PHY depending on the current PHY configuration and
8444 * settings specified in this command.
8446 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
8448 /* deprecated bit. Do not use!!! */
8449 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
8452 * When this bit is set to '1', the link shall be forced to
8453 * the force_link_speed value.
8455 * When this bit is set to '1', the HWRM client should
8456 * not enable any of the auto negotiation related
8457 * fields represented by auto_XXX fields in this command.
8458 * When this bit is set to '1' and the HWRM client has
8459 * enabled a auto_XXX field in this command, then the
8460 * HWRM shall ignore the enabled auto_XXX field.
8462 * When this bit is set to zero, the link
8463 * shall be allowed to autoneg.
8465 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
8468 * When this bit is set to '1', the auto-negotiation process
8469 * shall be restarted on the link.
8471 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
8474 * When this bit is set to '1', Energy Efficient Ethernet
8475 * (EEE) is requested to be enabled on this link.
8476 * If EEE is not supported on this port, then this flag
8477 * shall be ignored by the HWRM.
8479 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
8482 * When this bit is set to '1', Energy Efficient Ethernet
8483 * (EEE) is requested to be disabled on this link.
8484 * If EEE is not supported on this port, then this flag
8485 * shall be ignored by the HWRM.
8487 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
8490 * When this bit is set to '1' and EEE is enabled on this
8491 * link, then TX LPI is requested to be enabled on the link.
8492 * If EEE is not supported on this port, then this flag
8493 * shall be ignored by the HWRM.
8494 * If EEE is disabled on this port, then this flag shall be
8495 * ignored by the HWRM.
8497 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
8500 * When this bit is set to '1' and EEE is enabled on this
8501 * link, then TX LPI is requested to be disabled on the link.
8502 * If EEE is not supported on this port, then this flag
8503 * shall be ignored by the HWRM.
8504 * If EEE is disabled on this port, then this flag shall be
8505 * ignored by the HWRM.
8507 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
8510 * When set to 1, then the HWRM shall enable FEC autonegotitation
8511 * on this port if supported.
8512 * When set to 0, then this flag shall be ignored.
8513 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
8516 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
8519 * When set to 1, then the HWRM shall disable FEC autonegotiation
8520 * on this port if supported.
8521 * When set to 0, then this flag shall be ignored.
8522 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
8525 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
8528 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
8529 * on this port if supported.
8530 * When set to 0, then this flag shall be ignored.
8531 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
8534 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
8537 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
8538 * on this port if supported.
8539 * When set to 0, then this flag shall be ignored.
8540 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
8543 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
8546 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
8547 * on this port if supported.
8548 * When set to 0, then this flag shall be ignored.
8549 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
8552 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
8555 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
8556 * on this port if supported.
8557 * When set to 0, then this flag shall be ignored.
8558 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
8561 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
8564 * When this bit is set to '1', the link shall be forced to
8567 * # When this bit is set to '1", all other
8568 * command input settings related to the link speed shall
8570 * Once the link state is forced down, it can be
8571 * explicitly cleared from that state by setting this flag
8573 * # If this flag is set to '0', then the link shall be
8574 * cleared from forced down state if the link is in forced
8576 * There may be conditions (e.g. out-of-band or sideband
8577 * configuration changes for the link) outside the scope
8578 * of the HWRM implementation that may clear forced down
8581 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
8585 * This bit must be '1' for the auto_mode field to be
8588 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
8591 * This bit must be '1' for the auto_duplex field to be
8594 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
8597 * This bit must be '1' for the auto_pause field to be
8600 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
8603 * This bit must be '1' for the auto_link_speed field to be
8606 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
8609 * This bit must be '1' for the auto_link_speed_mask field to be
8612 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
8615 * This bit must be '1' for the wirespeed field to be
8618 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
8621 * This bit must be '1' for the lpbk field to be
8624 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
8627 * This bit must be '1' for the preemphasis field to be
8630 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
8633 * This bit must be '1' for the force_pause field to be
8636 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
8639 * This bit must be '1' for the eee_link_speed_mask field to be
8642 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
8645 * This bit must be '1' for the tx_lpi_timer field to be
8648 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
8650 /* Port ID of port that is to be configured. */
8653 * This is the speed that will be used if the force
8654 * bit is '1'. If unsupported speed is selected, an error
8655 * will be generated.
8657 uint16_t force_link_speed;
8658 /* 100Mb link speed */
8659 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
8660 /* 1Gb link speed */
8661 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
8662 /* 2Gb link speed */
8663 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
8664 /* 25Gb link speed */
8665 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
8666 /* 10Gb link speed */
8667 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
8668 /* 20Mb link speed */
8669 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
8670 /* 25Gb link speed */
8671 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
8672 /* 40Gb link speed */
8673 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
8674 /* 50Gb link speed */
8675 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
8676 /* 100Gb link speed */
8677 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
8678 /* 10Mb link speed */
8679 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
8680 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
8681 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
8683 * This value is used to identify what autoneg mode is
8684 * used when the link speed is not being forced.
8687 /* Disable autoneg or autoneg disabled. No speeds are selected. */
8688 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
8689 /* Select all possible speeds for autoneg mode. */
8690 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
8692 * Select only the auto_link_speed speed for autoneg mode. This mode has
8693 * been DEPRECATED. An HWRM client should not use this mode.
8695 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
8697 * Select the auto_link_speed or any speed below that speed for autoneg.
8698 * This mode has been DEPRECATED. An HWRM client should not use this mode.
8700 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
8702 * Select the speeds based on the corresponding link speed mask value
8705 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
8706 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
8707 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
8709 * This is the duplex setting that will be used if the autoneg_mode
8710 * is "one_speed" or "one_or_below".
8712 uint8_t auto_duplex;
8713 /* Half Duplex will be requested. */
8714 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
8715 /* Full duplex will be requested. */
8716 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
8717 /* Both Half and Full dupex will be requested. */
8718 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
8719 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
8720 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
8722 * This value is used to configure the pause that will be
8723 * used for autonegotiation.
8724 * Add text on the usage of auto_pause and force_pause.
8728 * When this bit is '1', Generation of tx pause messages
8729 * has been requested. Disabled otherwise.
8731 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
8734 * When this bit is '1', Reception of rx pause messages
8735 * has been requested. Disabled otherwise.
8737 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
8740 * When set to 1, the advertisement of pause is enabled.
8742 * # When the auto_mode is not set to none and this flag is
8743 * set to 1, then the auto_pause bits on this port are being
8744 * advertised and autoneg pause results are being interpreted.
8745 * # When the auto_mode is not set to none and this
8746 * flag is set to 0, the pause is forced as indicated in
8747 * force_pause, and also advertised as auto_pause bits, but
8748 * the autoneg results are not interpreted since the pause
8749 * configuration is being forced.
8750 * # When the auto_mode is set to none and this flag is set to
8751 * 1, auto_pause bits should be ignored and should be set to 0.
8753 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
8757 * This is the speed that will be used if the autoneg_mode
8758 * is "one_speed" or "one_or_below". If an unsupported speed
8759 * is selected, an error will be generated.
8761 uint16_t auto_link_speed;
8762 /* 100Mb link speed */
8763 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
8764 /* 1Gb link speed */
8765 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
8766 /* 2Gb link speed */
8767 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
8768 /* 25Gb link speed */
8769 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
8770 /* 10Gb link speed */
8771 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
8772 /* 20Mb link speed */
8773 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
8774 /* 25Gb link speed */
8775 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
8776 /* 40Gb link speed */
8777 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
8778 /* 50Gb link speed */
8779 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
8780 /* 100Gb link speed */
8781 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
8782 /* 10Mb link speed */
8783 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
8784 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
8785 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
8787 * This is a mask of link speeds that will be used if
8788 * autoneg_mode is "mask". If unsupported speed is enabled
8789 * an error will be generated.
8791 uint16_t auto_link_speed_mask;
8792 /* 100Mb link speed (Half-duplex) */
8793 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
8795 /* 100Mb link speed (Full-duplex) */
8796 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
8798 /* 1Gb link speed (Half-duplex) */
8799 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
8801 /* 1Gb link speed (Full-duplex) */
8802 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
8804 /* 2Gb link speed */
8805 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
8807 /* 25Gb link speed */
8808 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
8810 /* 10Gb link speed */
8811 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
8813 /* 20Gb link speed */
8814 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
8816 /* 25Gb link speed */
8817 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
8819 /* 40Gb link speed */
8820 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
8822 /* 50Gb link speed */
8823 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
8825 /* 100Gb link speed */
8826 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
8828 /* 10Mb link speed (Half-duplex) */
8829 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
8831 /* 10Mb link speed (Full-duplex) */
8832 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
8834 /* This value controls the wirespeed feature. */
8836 /* Wirespeed feature is disabled. */
8837 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
8838 /* Wirespeed feature is enabled. */
8839 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
8840 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
8841 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
8842 /* This value controls the loopback setting for the PHY. */
8844 /* No loopback is selected. Normal operation. */
8845 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
8847 * The HW will be configured with local loopback such that
8848 * host data is sent back to the host without modification.
8850 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
8852 * The HW will be configured with remote loopback such that
8853 * port logic will send packets back out the transmitter that
8856 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
8858 * The HW will be configured with external loopback such that
8859 * host data is sent on the trasmitter and based on the external
8860 * loopback connection the data will be received without modification.
8862 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
8863 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
8864 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
8866 * This value is used to configure the pause that will be
8867 * used for force mode.
8869 uint8_t force_pause;
8871 * When this bit is '1', Generation of tx pause messages
8872 * is supported. Disabled otherwise.
8874 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
8876 * When this bit is '1', Reception of rx pause messages
8877 * is supported. Disabled otherwise.
8879 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
8882 * This value controls the pre-emphasis to be used for the
8883 * link. Driver should not set this value (use
8884 * enable.preemphasis = 0) unless driver is sure of setting.
8885 * Normally HWRM FW will determine proper pre-emphasis.
8887 uint32_t preemphasis;
8889 * Setting for link speed mask that is used to
8890 * advertise speeds during autonegotiation when EEE is enabled.
8891 * This field is valid only when EEE is enabled.
8892 * The speeds specified in this field shall be a subset of
8893 * speeds specified in auto_link_speed_mask.
8894 * If EEE is enabled,then at least one speed shall be provided
8897 uint16_t eee_link_speed_mask;
8899 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
8901 /* 100Mb link speed (Full-duplex) */
8902 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
8905 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
8907 /* 1Gb link speed (Full-duplex) */
8908 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
8911 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
8914 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
8916 /* 10Gb link speed */
8917 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
8919 uint8_t unused_2[2];
8921 * Reuested setting of TX LPI timer in microseconds.
8922 * This field is valid only when EEE is enabled and TX LPI is
8925 uint32_t tx_lpi_timer;
8926 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
8927 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
8929 } __attribute__((packed));
8931 /* hwrm_port_phy_cfg_output (size:128b/16B) */
8932 struct hwrm_port_phy_cfg_output {
8933 /* The specific error status for the command. */
8934 uint16_t error_code;
8935 /* The HWRM command request type. */
8937 /* The sequence ID from the original command. */
8939 /* The length of the response data in number of bytes. */
8941 uint8_t unused_0[7];
8943 * This field is used in Output records to indicate that the output
8944 * is completely written to RAM. This field should be read as '1'
8945 * to indicate that the output has been completely written.
8946 * When writing a command completion or response to an internal processor,
8947 * the order of writes has to be such that this field is written last.
8950 } __attribute__((packed));
8952 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
8953 struct hwrm_port_phy_cfg_cmd_err {
8955 * command specific error codes that goes to
8956 * the cmd_err field in Common HWRM Error Response.
8960 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
8961 /* Unable to complete operation due to invalid speed */
8962 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
8964 * retry the command since the phy is not ready.
8965 * retry count is returned in opaque_0.
8966 * This is only valid for the first command and
8967 * this value will not change for successive calls.
8968 * but if a 0 is returned at any time then this should
8969 * be treated as an un recoverable failure,
8971 * retry interval in milli seconds is returned in opaque_1.
8972 * This specifies the time that user should wait before
8973 * issuing the next port_phy_cfg command.
8975 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
8976 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
8977 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
8978 uint8_t unused_0[7];
8979 } __attribute__((packed));
8981 /**********************
8982 * hwrm_port_phy_qcfg *
8983 **********************/
8986 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
8987 struct hwrm_port_phy_qcfg_input {
8988 /* The HWRM command request type. */
8991 * The completion ring to send the completion event on. This should
8992 * be the NQ ID returned from the `nq_alloc` HWRM command.
8996 * The sequence ID is used by the driver for tracking multiple
8997 * commands. This ID is treated as opaque data by the firmware and
8998 * the value is returned in the `hwrm_resp_hdr` upon completion.
9002 * The target ID of the command:
9003 * * 0x0-0xFFF8 - The function ID
9004 * * 0xFFF8-0xFFFE - Reserved for internal processors
9009 * A physical address pointer pointing to a host buffer that the
9010 * command's response data will be written. This can be either a host
9011 * physical address (HPA) or a guest physical address (GPA) and must
9012 * point to a physically contiguous block of memory.
9015 /* Port ID of port that is to be queried. */
9017 uint8_t unused_0[6];
9018 } __attribute__((packed));
9020 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
9021 struct hwrm_port_phy_qcfg_output {
9022 /* The specific error status for the command. */
9023 uint16_t error_code;
9024 /* The HWRM command request type. */
9026 /* The sequence ID from the original command. */
9028 /* The length of the response data in number of bytes. */
9030 /* This value indicates the current link status. */
9032 /* There is no link or cable detected. */
9033 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
9034 /* There is no link, but a cable has been detected. */
9035 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
9036 /* There is a link. */
9037 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
9038 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
9039 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
9041 /* This value indicates the current link speed of the connection. */
9042 uint16_t link_speed;
9043 /* 100Mb link speed */
9044 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
9045 /* 1Gb link speed */
9046 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
9047 /* 2Gb link speed */
9048 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
9049 /* 25Gb link speed */
9050 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
9051 /* 10Gb link speed */
9052 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
9053 /* 20Mb link speed */
9054 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
9055 /* 25Gb link speed */
9056 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
9057 /* 40Gb link speed */
9058 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
9059 /* 50Gb link speed */
9060 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
9061 /* 100Gb link speed */
9062 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
9063 /* 10Mb link speed */
9064 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
9065 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
9066 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
9068 * This value is indicates the duplex of the current
9072 /* Half Duplex connection. */
9073 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
9074 /* Full duplex connection. */
9075 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
9076 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
9077 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
9079 * This value is used to indicate the current
9080 * pause configuration. When autoneg is enabled, this value
9081 * represents the autoneg results of pause configuration.
9085 * When this bit is '1', Generation of tx pause messages
9086 * is supported. Disabled otherwise.
9088 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
9090 * When this bit is '1', Reception of rx pause messages
9091 * is supported. Disabled otherwise.
9093 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
9095 * The supported speeds for the port. This is a bit mask.
9096 * For each speed that is supported, the corrresponding
9097 * bit will be set to '1'.
9099 uint16_t support_speeds;
9100 /* 100Mb link speed (Half-duplex) */
9101 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
9103 /* 100Mb link speed (Full-duplex) */
9104 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
9106 /* 1Gb link speed (Half-duplex) */
9107 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
9109 /* 1Gb link speed (Full-duplex) */
9110 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
9112 /* 2Gb link speed */
9113 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
9115 /* 25Gb link speed */
9116 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
9118 /* 10Gb link speed */
9119 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
9121 /* 20Gb link speed */
9122 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
9124 /* 25Gb link speed */
9125 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
9127 /* 40Gb link speed */
9128 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
9130 /* 50Gb link speed */
9131 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
9133 /* 100Gb link speed */
9134 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
9136 /* 10Mb link speed (Half-duplex) */
9137 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
9139 /* 10Mb link speed (Full-duplex) */
9140 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
9143 * Current setting of forced link speed.
9144 * When the link speed is not being forced, this
9145 * value shall be set to 0.
9147 uint16_t force_link_speed;
9148 /* 100Mb link speed */
9149 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
9150 /* 1Gb link speed */
9151 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
9152 /* 2Gb link speed */
9153 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
9154 /* 25Gb link speed */
9155 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
9156 /* 10Gb link speed */
9157 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
9158 /* 20Mb link speed */
9159 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
9160 /* 25Gb link speed */
9161 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
9162 /* 40Gb link speed */
9163 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
9165 /* 50Gb link speed */
9166 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
9168 /* 100Gb link speed */
9169 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
9171 /* 10Mb link speed */
9172 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
9174 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
9175 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
9176 /* Current setting of auto negotiation mode. */
9178 /* Disable autoneg or autoneg disabled. No speeds are selected. */
9179 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
9180 /* Select all possible speeds for autoneg mode. */
9181 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
9183 * Select only the auto_link_speed speed for autoneg mode. This mode has
9184 * been DEPRECATED. An HWRM client should not use this mode.
9186 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
9188 * Select the auto_link_speed or any speed below that speed for autoneg.
9189 * This mode has been DEPRECATED. An HWRM client should not use this mode.
9191 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
9193 * Select the speeds based on the corresponding link speed mask value
9196 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
9197 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
9198 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
9200 * Current setting of pause autonegotiation.
9201 * Move autoneg_pause flag here.
9205 * When this bit is '1', Generation of tx pause messages
9206 * has been requested. Disabled otherwise.
9208 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
9211 * When this bit is '1', Reception of rx pause messages
9212 * has been requested. Disabled otherwise.
9214 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
9217 * When set to 1, the advertisement of pause is enabled.
9219 * # When the auto_mode is not set to none and this flag is
9220 * set to 1, then the auto_pause bits on this port are being
9221 * advertised and autoneg pause results are being interpreted.
9222 * # When the auto_mode is not set to none and this
9223 * flag is set to 0, the pause is forced as indicated in
9224 * force_pause, and also advertised as auto_pause bits, but
9225 * the autoneg results are not interpreted since the pause
9226 * configuration is being forced.
9227 * # When the auto_mode is set to none and this flag is set to
9228 * 1, auto_pause bits should be ignored and should be set to 0.
9230 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
9233 * Current setting for auto_link_speed. This field is only
9234 * valid when auto_mode is set to "one_speed" or "one_or_below".
9236 uint16_t auto_link_speed;
9237 /* 100Mb link speed */
9238 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
9239 /* 1Gb link speed */
9240 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
9241 /* 2Gb link speed */
9242 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
9243 /* 25Gb link speed */
9244 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
9245 /* 10Gb link speed */
9246 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
9247 /* 20Mb link speed */
9248 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
9249 /* 25Gb link speed */
9250 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
9251 /* 40Gb link speed */
9252 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
9253 /* 50Gb link speed */
9254 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
9255 /* 100Gb link speed */
9256 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
9257 /* 10Mb link speed */
9258 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
9260 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
9261 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
9263 * Current setting for auto_link_speed_mask that is used to
9264 * advertise speeds during autonegotiation.
9265 * This field is only valid when auto_mode is set to "mask".
9266 * The speeds specified in this field shall be a subset of
9267 * supported speeds on this port.
9269 uint16_t auto_link_speed_mask;
9270 /* 100Mb link speed (Half-duplex) */
9271 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
9273 /* 100Mb link speed (Full-duplex) */
9274 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
9276 /* 1Gb link speed (Half-duplex) */
9277 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
9279 /* 1Gb link speed (Full-duplex) */
9280 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
9282 /* 2Gb link speed */
9283 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
9285 /* 25Gb link speed */
9286 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
9288 /* 10Gb link speed */
9289 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
9291 /* 20Gb link speed */
9292 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
9294 /* 25Gb link speed */
9295 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
9297 /* 40Gb link speed */
9298 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
9300 /* 50Gb link speed */
9301 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
9303 /* 100Gb link speed */
9304 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
9306 /* 10Mb link speed (Half-duplex) */
9307 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
9309 /* 10Mb link speed (Full-duplex) */
9310 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
9312 /* Current setting for wirespeed. */
9314 /* Wirespeed feature is disabled. */
9315 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
9316 /* Wirespeed feature is enabled. */
9317 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
9318 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
9319 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
9320 /* Current setting for loopback. */
9322 /* No loopback is selected. Normal operation. */
9323 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
9325 * The HW will be configured with local loopback such that
9326 * host data is sent back to the host without modification.
9328 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
9330 * The HW will be configured with remote loopback such that
9331 * port logic will send packets back out the transmitter that
9334 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
9336 * The HW will be configured with external loopback such that
9337 * host data is sent on the trasmitter and based on the external
9338 * loopback connection the data will be received without modification.
9340 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
9341 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
9342 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
9344 * Current setting of forced pause.
9345 * When the pause configuration is not being forced, then
9346 * this value shall be set to 0.
9348 uint8_t force_pause;
9350 * When this bit is '1', Generation of tx pause messages
9351 * is supported. Disabled otherwise.
9353 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
9355 * When this bit is '1', Reception of rx pause messages
9356 * is supported. Disabled otherwise.
9358 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
9360 * This value indicates the current status of the optics module on
9363 uint8_t module_status;
9364 /* Module is inserted and accepted */
9365 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
9367 /* Module is rejected and transmit side Laser is disabled. */
9368 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
9370 /* Module mismatch warning. */
9371 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
9373 /* Module is rejected and powered down. */
9374 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
9376 /* Module is not inserted. */
9377 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
9379 /* Module status is not applicable. */
9380 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
9382 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
9383 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
9384 /* Current setting for preemphasis. */
9385 uint32_t preemphasis;
9386 /* This field represents the major version of the PHY. */
9388 /* This field represents the minor version of the PHY. */
9390 /* This field represents the build version of the PHY. */
9392 /* This value represents a PHY type. */
9395 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
9398 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
9400 /* BASE-KR4 (Deprecated) */
9401 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
9404 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
9407 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
9409 /* BASE-KR2 (Deprecated) */
9410 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
9413 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
9416 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
9419 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
9421 /* EEE capable BASE-T */
9422 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
9424 /* SGMII connected external PHY */
9425 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
9427 /* 25G_BASECR_CA_L */
9428 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
9430 /* 25G_BASECR_CA_S */
9431 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
9433 /* 25G_BASECR_CA_N */
9434 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
9437 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
9440 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
9443 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
9446 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
9449 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
9452 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
9455 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
9458 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
9461 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
9464 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
9466 /* 40G_ACTIVE_CABLE */
9467 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
9470 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
9473 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
9476 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
9478 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
9479 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
9480 /* This value represents a media type. */
9483 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
9485 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
9486 /* Direct Attached Copper */
9487 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
9489 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
9490 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
9491 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
9492 /* This value represents a transceiver type. */
9493 uint8_t xcvr_pkg_type;
9494 /* PHY and MAC are in the same package */
9495 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
9497 /* PHY and MAC are in different packages */
9498 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
9500 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
9501 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
9502 uint8_t eee_config_phy_addr;
9503 /* This field represents PHY address. */
9504 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
9506 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
9508 * This field represents flags related to EEE configuration.
9509 * These EEE configuration flags are valid only when the
9510 * auto_mode is not set to none (in other words autonegotiation
9513 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
9515 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
9517 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
9518 * Speeds for autoneg with EEE mode enabled
9519 * are based on eee_link_speed_mask.
9521 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
9524 * This flag is valid only when eee_enabled is set to 1.
9526 * # If eee_enabled is set to 0, then EEE mode is disabled
9527 * and this flag shall be ignored.
9528 * # If eee_enabled is set to 1 and this flag is set to 1,
9529 * then Energy Efficient Ethernet (EEE) mode is enabled
9531 * # If eee_enabled is set to 1 and this flag is set to 0,
9532 * then Energy Efficient Ethernet (EEE) mode is enabled
9533 * but is currently not in use.
9535 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
9538 * This flag is valid only when eee_enabled is set to 1.
9540 * # If eee_enabled is set to 0, then EEE mode is disabled
9541 * and this flag shall be ignored.
9542 * # If eee_enabled is set to 1 and this flag is set to 1,
9543 * then Energy Efficient Ethernet (EEE) mode is enabled
9544 * and TX LPI is enabled.
9545 * # If eee_enabled is set to 1 and this flag is set to 0,
9546 * then Energy Efficient Ethernet (EEE) mode is enabled
9547 * but TX LPI is disabled.
9549 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
9552 * When set to 1, the parallel detection is used to determine
9553 * the speed of the link partner.
9555 * Parallel detection is used when a autonegotiation capable
9556 * device is connected to a link parter that is not capable
9557 * of autonegotiation.
9559 uint8_t parallel_detect;
9561 * When set to 1, the parallel detection is used to determine
9562 * the speed of the link partner.
9564 * Parallel detection is used when a autonegotiation capable
9565 * device is connected to a link parter that is not capable
9566 * of autonegotiation.
9568 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
9570 * The advertised speeds for the port by the link partner.
9571 * Each advertised speed will be set to '1'.
9573 uint16_t link_partner_adv_speeds;
9574 /* 100Mb link speed (Half-duplex) */
9575 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
9577 /* 100Mb link speed (Full-duplex) */
9578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
9580 /* 1Gb link speed (Half-duplex) */
9581 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
9583 /* 1Gb link speed (Full-duplex) */
9584 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
9586 /* 2Gb link speed */
9587 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
9589 /* 25Gb link speed */
9590 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
9592 /* 10Gb link speed */
9593 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
9595 /* 20Gb link speed */
9596 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
9598 /* 25Gb link speed */
9599 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
9601 /* 40Gb link speed */
9602 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
9604 /* 50Gb link speed */
9605 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
9607 /* 100Gb link speed */
9608 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
9610 /* 10Mb link speed (Half-duplex) */
9611 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
9613 /* 10Mb link speed (Full-duplex) */
9614 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
9617 * The advertised autoneg for the port by the link partner.
9618 * This field is deprecated and should be set to 0.
9620 uint8_t link_partner_adv_auto_mode;
9621 /* Disable autoneg or autoneg disabled. No speeds are selected. */
9622 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
9624 /* Select all possible speeds for autoneg mode. */
9625 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
9628 * Select only the auto_link_speed speed for autoneg mode. This mode has
9629 * been DEPRECATED. An HWRM client should not use this mode.
9631 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
9634 * Select the auto_link_speed or any speed below that speed for autoneg.
9635 * This mode has been DEPRECATED. An HWRM client should not use this mode.
9637 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
9640 * Select the speeds based on the corresponding link speed mask value
9643 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
9645 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
9646 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
9647 /* The advertised pause settings on the port by the link partner. */
9648 uint8_t link_partner_adv_pause;
9650 * When this bit is '1', Generation of tx pause messages
9651 * is supported. Disabled otherwise.
9653 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
9656 * When this bit is '1', Reception of rx pause messages
9657 * is supported. Disabled otherwise.
9659 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
9662 * Current setting for link speed mask that is used to
9663 * advertise speeds during autonegotiation when EEE is enabled.
9664 * This field is valid only when eee_enabled flags is set to 1.
9665 * The speeds specified in this field shall be a subset of
9666 * speeds specified in auto_link_speed_mask.
9668 uint16_t adv_eee_link_speed_mask;
9670 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
9672 /* 100Mb link speed (Full-duplex) */
9673 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
9676 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
9678 /* 1Gb link speed (Full-duplex) */
9679 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
9682 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
9685 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
9687 /* 10Gb link speed */
9688 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
9691 * Current setting for link speed mask that is advertised by
9692 * the link partner when EEE is enabled.
9693 * This field is valid only when eee_enabled flags is set to 1.
9695 uint16_t link_partner_adv_eee_link_speed_mask;
9697 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
9699 /* 100Mb link speed (Full-duplex) */
9700 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
9703 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
9705 /* 1Gb link speed (Full-duplex) */
9706 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
9709 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
9712 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
9714 /* 10Gb link speed */
9715 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
9717 uint32_t xcvr_identifier_type_tx_lpi_timer;
9719 * Current setting of TX LPI timer in microseconds.
9720 * This field is valid only when_eee_enabled flag is set to 1
9721 * and tx_lpi_enabled is set to 1.
9723 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
9725 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
9726 /* This value represents transceiver identifier type. */
9727 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
9728 UINT32_C(0xff000000)
9729 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
9731 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
9732 (UINT32_C(0x0) << 24)
9733 /* SFP/SFP+/SFP28 */
9734 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
9735 (UINT32_C(0x3) << 24)
9737 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
9738 (UINT32_C(0xc) << 24)
9740 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
9741 (UINT32_C(0xd) << 24)
9743 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
9744 (UINT32_C(0x11) << 24)
9745 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
9746 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
9748 * This value represents the current configuration of
9749 * Forward Error Correction (FEC) on the port.
9753 * When set to 1, then FEC is not supported on this port. If this flag
9754 * is set to 1, then all other FEC configuration flags shall be ignored.
9755 * When set to 0, then FEC is supported as indicated by other
9756 * configuration flags.
9757 * If no cable is attached and the HWRM does not yet know the FEC
9758 * capability, then the HWRM shall set this flag to 1 when reporting
9761 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
9764 * When set to 1, then FEC autonegotiation is supported on this port.
9765 * When set to 0, then FEC autonegotiation is not supported on this port.
9767 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
9770 * When set to 1, then FEC autonegotiation is enabled on this port.
9771 * When set to 0, then FEC autonegotiation is disabled if supported.
9772 * This flag should be ignored if FEC autonegotiation is not supported on this port.
9774 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
9777 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
9778 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
9780 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
9783 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
9784 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
9785 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
9787 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
9790 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
9791 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
9793 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
9796 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
9797 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
9798 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
9800 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
9803 * This value is indicates the duplex of the current
9806 uint8_t duplex_state;
9807 /* Half Duplex connection. */
9808 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
9809 /* Full duplex connection. */
9810 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
9811 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
9812 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
9813 /* Option flags fields. */
9814 uint8_t option_flags;
9815 /* When this bit is '1', Media auto detect is enabled. */
9816 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
9819 * Up to 16 bytes of null padded ASCII string representing
9821 * If the string is set to null, then the vendor name is not
9824 char phy_vendor_name[16];
9826 * Up to 16 bytes of null padded ASCII string that
9827 * identifies vendor specific part number of the PHY.
9828 * If the string is set to null, then the vendor specific
9829 * part number is not available.
9831 char phy_vendor_partnumber[16];
9832 uint8_t unused_2[7];
9834 * This field is used in Output records to indicate that the output
9835 * is completely written to RAM. This field should be read as '1'
9836 * to indicate that the output has been completely written.
9837 * When writing a command completion or response to an internal processor,
9838 * the order of writes has to be such that this field is written last.
9841 } __attribute__((packed));
9843 /*********************
9844 * hwrm_port_mac_cfg *
9845 *********************/
9848 /* hwrm_port_mac_cfg_input (size:320b/40B) */
9849 struct hwrm_port_mac_cfg_input {
9850 /* The HWRM command request type. */
9853 * The completion ring to send the completion event on. This should
9854 * be the NQ ID returned from the `nq_alloc` HWRM command.
9858 * The sequence ID is used by the driver for tracking multiple
9859 * commands. This ID is treated as opaque data by the firmware and
9860 * the value is returned in the `hwrm_resp_hdr` upon completion.
9864 * The target ID of the command:
9865 * * 0x0-0xFFF8 - The function ID
9866 * * 0xFFF8-0xFFFE - Reserved for internal processors
9871 * A physical address pointer pointing to a host buffer that the
9872 * command's response data will be written. This can be either a host
9873 * physical address (HPA) or a guest physical address (GPA) and must
9874 * point to a physically contiguous block of memory.
9878 * In this field, there are a number of CoS mappings related flags
9879 * that are used to configure CoS mappings and their corresponding
9880 * priorities in the hardware.
9881 * For the priorities of CoS mappings, the HWRM uses the following
9882 * priority order (high to low) by default:
9888 * A subset of CoS mappings can be enabled.
9889 * If a priority is not specified for an enabled CoS mapping, the
9890 * priority will be assigned in the above order for the enabled CoS
9891 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
9892 * enabled and their priorities are not specified, the following
9893 * priority order (high to low) will be used by the HWRM:
9898 * vlan_pri CoS mapping together with default CoS with lower priority
9899 * are enabled by default by the HWRM.
9903 * When this bit is '1', this command will configure
9904 * the MAC to match the current link state of the PHY.
9905 * If the link is not established on the PHY, then this
9906 * bit has no effect.
9908 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
9911 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
9912 * is requested to be enabled.
9914 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
9917 * When this bit is set to '1', tunnel VLAN PRI field to
9918 * CoS mapping is requested to be enabled.
9920 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
9923 * When this bit is set to '1', the IP DSCP to CoS mapping is
9924 * requested to be enabled.
9926 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
9929 * When this bit is '1', the HWRM is requested to
9930 * enable timestamp capture capability on the receive side
9933 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
9936 * When this bit is '1', the HWRM is requested to
9937 * disable timestamp capture capability on the receive side
9940 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
9943 * When this bit is '1', the HWRM is requested to
9944 * enable timestamp capture capability on the transmit side
9947 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
9950 * When this bit is '1', the HWRM is requested to
9951 * disable timestamp capture capability on the transmit side
9954 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
9957 * When this bit is '1', the Out-Of-Box WoL is requested to
9958 * be enabled on this port.
9960 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
9963 * When this bit is '1', the the Out-Of-Box WoL is requested to
9964 * be disabled on this port.
9966 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
9969 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
9970 * is requested to be disabled.
9972 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
9975 * When this bit is set to '1', tunnel VLAN PRI field to
9976 * CoS mapping is requested to be disabled.
9978 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
9981 * When this bit is set to '1', the IP DSCP to CoS mapping is
9982 * requested to be disabled.
9984 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
9988 * This bit must be '1' for the ipg field to be
9991 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
9994 * This bit must be '1' for the lpbk field to be
9997 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
10000 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
10003 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
10006 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
10009 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
10012 * This bit must be '1' for the dscp2cos_map_pri field to be
10015 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
10018 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
10021 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
10024 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
10027 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
10030 * This bit must be '1' for the cos_field_cfg field to be
10033 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
10035 /* Port ID of port that is to be configured. */
10038 * This value is used to configure the minimum IPG that will
10039 * be sent between packets by this port.
10042 /* This value controls the loopback setting for the MAC. */
10044 /* No loopback is selected. Normal operation. */
10045 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
10047 * The HW will be configured with local loopback such that
10048 * host data is sent back to the host without modification.
10050 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
10052 * The HW will be configured with remote loopback such that
10053 * port logic will send packets back out the transmitter that
10056 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
10057 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
10058 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
10060 * This value controls the priority setting of VLAN PRI to CoS
10061 * mapping based on VLAN Tags of inner packet headers of
10062 * tunneled packets or packet headers of non-tunneled packets.
10064 * # Each XXX_pri variable shall have a unique priority value
10065 * when it is being specified.
10066 * # When comparing priorities of mappings, higher value
10067 * indicates higher priority.
10068 * For example, a value of 0-3 is returned where 0 is being
10069 * the lowest priority and 3 is being the highest priority.
10071 uint8_t vlan_pri2cos_map_pri;
10072 /* Reserved field. */
10075 * This value controls the priority setting of VLAN PRI to CoS
10076 * mapping based on VLAN Tags of tunneled header.
10077 * This mapping only applies when tunneled headers
10080 * # Each XXX_pri variable shall have a unique priority value
10081 * when it is being specified.
10082 * # When comparing priorities of mappings, higher value
10083 * indicates higher priority.
10084 * For example, a value of 0-3 is returned where 0 is being
10085 * the lowest priority and 3 is being the highest priority.
10087 uint8_t tunnel_pri2cos_map_pri;
10089 * This value controls the priority setting of IP DSCP to CoS
10090 * mapping based on inner IP header of tunneled packets or
10091 * IP header of non-tunneled packets.
10093 * # Each XXX_pri variable shall have a unique priority value
10094 * when it is being specified.
10095 * # When comparing priorities of mappings, higher value
10096 * indicates higher priority.
10097 * For example, a value of 0-3 is returned where 0 is being
10098 * the lowest priority and 3 is being the highest priority.
10100 uint8_t dscp2pri_map_pri;
10102 * This is a 16-bit bit mask that is used to request a
10103 * specific configuration of time stamp capture of PTP messages
10104 * on the receive side of this port.
10105 * This field shall be ignored if the ptp_rx_ts_capture_enable
10106 * flag is not set in this command.
10107 * Otherwise, if bit 'i' is set, then the HWRM is being
10108 * requested to configure the receive side of the port to
10109 * capture the time stamp of every received PTP message
10110 * with messageType field value set to i.
10112 uint16_t rx_ts_capture_ptp_msg_type;
10114 * This is a 16-bit bit mask that is used to request a
10115 * specific configuration of time stamp capture of PTP messages
10116 * on the transmit side of this port.
10117 * This field shall be ignored if the ptp_tx_ts_capture_enable
10118 * flag is not set in this command.
10119 * Otherwise, if bit 'i' is set, then the HWRM is being
10120 * requested to configure the transmit sied of the port to
10121 * capture the time stamp of every transmitted PTP message
10122 * with messageType field value set to i.
10124 uint16_t tx_ts_capture_ptp_msg_type;
10125 /* Configuration of CoS fields. */
10126 uint8_t cos_field_cfg;
10128 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
10131 * This field is used to specify selection of VLAN PRI value
10132 * based on whether one or two VLAN Tags are present in
10133 * the inner packet headers of tunneled packets or
10134 * non-tunneled packets.
10135 * This field is valid only if inner VLAN PRI to CoS mapping
10137 * If VLAN PRI to CoS mapping is not enabled, then this
10138 * field shall be ignored.
10140 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
10142 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
10145 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
10146 * present in the inner packet headers
10148 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
10149 (UINT32_C(0x0) << 1)
10151 * Select outer VLAN Tag PRI when 2 VLAN Tags are
10152 * present in the inner packet headers.
10153 * No VLAN PRI shall be selected for this configuration
10154 * if only one VLAN Tag is present in the inner
10157 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
10158 (UINT32_C(0x1) << 1)
10160 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
10161 * are present in the inner packet headers
10163 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
10164 (UINT32_C(0x2) << 1)
10166 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
10167 (UINT32_C(0x3) << 1)
10168 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
10169 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
10171 * This field is used to specify selection of tunnel VLAN
10172 * PRI value based on whether one or two VLAN Tags are
10173 * present in tunnel headers.
10174 * This field is valid only if tunnel VLAN PRI to CoS mapping
10176 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
10177 * field shall be ignored.
10179 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
10181 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
10184 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
10185 * present in the tunnel packet headers
10187 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
10188 (UINT32_C(0x0) << 3)
10190 * Select outer VLAN Tag PRI when 2 VLAN Tags are
10191 * present in the tunnel packet headers.
10192 * No tunnel VLAN PRI shall be selected for this
10193 * configuration if only one VLAN Tag is present in
10194 * the tunnel packet headers.
10196 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
10197 (UINT32_C(0x1) << 3)
10199 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
10200 * are present in the tunnel packet headers
10202 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
10203 (UINT32_C(0x2) << 3)
10205 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
10206 (UINT32_C(0x3) << 3)
10207 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
10208 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
10210 * This field shall be used to provide default CoS value
10211 * that has been configured on this port.
10212 * This field is valid only if default CoS mapping
10214 * If default CoS mapping is not enabled, then this
10215 * field shall be ignored.
10217 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
10219 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
10221 uint8_t unused_0[3];
10222 } __attribute__((packed));
10224 /* hwrm_port_mac_cfg_output (size:128b/16B) */
10225 struct hwrm_port_mac_cfg_output {
10226 /* The specific error status for the command. */
10227 uint16_t error_code;
10228 /* The HWRM command request type. */
10230 /* The sequence ID from the original command. */
10232 /* The length of the response data in number of bytes. */
10235 * This is the configured maximum length of Ethernet packet
10236 * payload that is allowed to be received on the port.
10237 * This value does not include the number of bytes used by
10238 * Ethernet header and trailer (CRC).
10242 * This is the configured maximum length of Ethernet packet
10243 * payload that is allowed to be transmitted on the port.
10244 * This value does not include the number of bytes used by
10245 * Ethernet header and trailer (CRC).
10248 /* Current configuration of the IPG value. */
10250 /* Current value of the loopback value. */
10252 /* No loopback is selected. Normal operation. */
10253 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
10255 * The HW will be configured with local loopback such that
10256 * host data is sent back to the host without modification.
10258 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
10260 * The HW will be configured with remote loopback such that
10261 * port logic will send packets back out the transmitter that
10264 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
10265 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
10266 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
10269 * This field is used in Output records to indicate that the output
10270 * is completely written to RAM. This field should be read as '1'
10271 * to indicate that the output has been completely written.
10272 * When writing a command completion or response to an internal processor,
10273 * the order of writes has to be such that this field is written last.
10276 } __attribute__((packed));
10278 /**********************
10279 * hwrm_port_mac_qcfg *
10280 **********************/
10283 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
10284 struct hwrm_port_mac_qcfg_input {
10285 /* The HWRM command request type. */
10288 * The completion ring to send the completion event on. This should
10289 * be the NQ ID returned from the `nq_alloc` HWRM command.
10291 uint16_t cmpl_ring;
10293 * The sequence ID is used by the driver for tracking multiple
10294 * commands. This ID is treated as opaque data by the firmware and
10295 * the value is returned in the `hwrm_resp_hdr` upon completion.
10299 * The target ID of the command:
10300 * * 0x0-0xFFF8 - The function ID
10301 * * 0xFFF8-0xFFFE - Reserved for internal processors
10304 uint16_t target_id;
10306 * A physical address pointer pointing to a host buffer that the
10307 * command's response data will be written. This can be either a host
10308 * physical address (HPA) or a guest physical address (GPA) and must
10309 * point to a physically contiguous block of memory.
10311 uint64_t resp_addr;
10312 /* Port ID of port that is to be configured. */
10314 uint8_t unused_0[6];
10315 } __attribute__((packed));
10317 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
10318 struct hwrm_port_mac_qcfg_output {
10319 /* The specific error status for the command. */
10320 uint16_t error_code;
10321 /* The HWRM command request type. */
10323 /* The sequence ID from the original command. */
10325 /* The length of the response data in number of bytes. */
10328 * This is the configured maximum length of Ethernet packet
10329 * payload that is allowed to be received on the port.
10330 * This value does not include the number of bytes used by the
10331 * Ethernet header and trailer (CRC).
10335 * This is the configured maximum length of Ethernet packet
10336 * payload that is allowed to be transmitted on the port.
10337 * This value does not include the number of bytes used by the
10338 * Ethernet header and trailer (CRC).
10342 * The minimum IPG that will
10343 * be sent between packets by this port.
10346 /* The loopback setting for the MAC. */
10348 /* No loopback is selected. Normal operation. */
10349 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
10351 * The HW will be configured with local loopback such that
10352 * host data is sent back to the host without modification.
10354 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
10356 * The HW will be configured with remote loopback such that
10357 * port logic will send packets back out the transmitter that
10360 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
10361 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
10362 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
10364 * Priority setting for VLAN PRI to CoS mapping.
10365 * # Each XXX_pri variable shall have a unique priority value
10366 * when it is being used.
10367 * # When comparing priorities of mappings, higher value
10368 * indicates higher priority.
10369 * For example, a value of 0-3 is returned where 0 is being
10370 * the lowest priority and 3 is being the highest priority.
10371 * # If the correspoding CoS mapping is not enabled, then this
10372 * field should be ignored.
10373 * # This value indicates the normalized priority value retained
10376 uint8_t vlan_pri2cos_map_pri;
10378 * In this field, a number of CoS mappings related flags
10379 * are used to indicate configured CoS mappings.
10383 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
10386 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
10389 * When this bit is set to '1', tunnel VLAN PRI field to
10390 * CoS mapping is enabled.
10392 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
10395 * When this bit is set to '1', the IP DSCP to CoS mapping is
10398 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
10401 * When this bit is '1', the Out-Of-Box WoL is enabled on this
10404 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
10406 /* When this bit is '1', PTP is enabled for RX on this port. */
10407 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
10409 /* When this bit is '1', PTP is enabled for TX on this port. */
10410 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
10413 * Priority setting for tunnel VLAN PRI to CoS mapping.
10414 * # Each XXX_pri variable shall have a unique priority value
10415 * when it is being used.
10416 * # When comparing priorities of mappings, higher value
10417 * indicates higher priority.
10418 * For example, a value of 0-3 is returned where 0 is being
10419 * the lowest priority and 3 is being the highest priority.
10420 * # If the correspoding CoS mapping is not enabled, then this
10421 * field should be ignored.
10422 * # This value indicates the normalized priority value retained
10425 uint8_t tunnel_pri2cos_map_pri;
10427 * Priority setting for DSCP to PRI mapping.
10428 * # Each XXX_pri variable shall have a unique priority value
10429 * when it is being used.
10430 * # When comparing priorities of mappings, higher value
10431 * indicates higher priority.
10432 * For example, a value of 0-3 is returned where 0 is being
10433 * the lowest priority and 3 is being the highest priority.
10434 * # If the correspoding CoS mapping is not enabled, then this
10435 * field should be ignored.
10436 * # This value indicates the normalized priority value retained
10439 uint8_t dscp2pri_map_pri;
10441 * This is a 16-bit bit mask that represents the
10442 * current configuration of time stamp capture of PTP messages
10443 * on the receive side of this port.
10444 * If bit 'i' is set, then the receive side of the port
10445 * is configured to capture the time stamp of every
10446 * received PTP message with messageType field value set
10448 * If all bits are set to 0 (i.e. field value set 0),
10449 * then the receive side of the port is not configured
10450 * to capture timestamp for PTP messages.
10451 * If all bits are set to 1, then the receive side of the
10452 * port is configured to capture timestamp for all PTP
10455 uint16_t rx_ts_capture_ptp_msg_type;
10457 * This is a 16-bit bit mask that represents the
10458 * current configuration of time stamp capture of PTP messages
10459 * on the transmit side of this port.
10460 * If bit 'i' is set, then the transmit side of the port
10461 * is configured to capture the time stamp of every
10462 * received PTP message with messageType field value set
10464 * If all bits are set to 0 (i.e. field value set 0),
10465 * then the transmit side of the port is not configured
10466 * to capture timestamp for PTP messages.
10467 * If all bits are set to 1, then the transmit side of the
10468 * port is configured to capture timestamp for all PTP
10471 uint16_t tx_ts_capture_ptp_msg_type;
10472 /* Configuration of CoS fields. */
10473 uint8_t cos_field_cfg;
10475 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
10478 * This field is used for selecting VLAN PRI value
10479 * based on whether one or two VLAN Tags are present in
10480 * the inner packet headers of tunneled packets or
10481 * non-tunneled packets.
10483 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
10485 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
10488 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
10489 * present in the inner packet headers
10491 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
10492 (UINT32_C(0x0) << 1)
10494 * Select outer VLAN Tag PRI when 2 VLAN Tags are
10495 * present in the inner packet headers.
10496 * No VLAN PRI is selected for this configuration
10497 * if only one VLAN Tag is present in the inner
10500 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
10501 (UINT32_C(0x1) << 1)
10503 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
10504 * are present in the inner packet headers
10506 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
10507 (UINT32_C(0x2) << 1)
10509 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
10510 (UINT32_C(0x3) << 1)
10511 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
10512 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
10514 * This field is used for selecting tunnel VLAN PRI value
10515 * based on whether one or two VLAN Tags are present in
10516 * the tunnel headers of tunneled packets. This selection
10517 * does not apply to non-tunneled packets.
10519 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
10521 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
10524 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
10525 * present in the tunnel packet headers
10527 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
10528 (UINT32_C(0x0) << 3)
10530 * Select outer VLAN Tag PRI when 2 VLAN Tags are
10531 * present in the tunnel packet headers.
10532 * No VLAN PRI is selected for this configuration
10533 * if only one VLAN Tag is present in the tunnel
10536 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
10537 (UINT32_C(0x1) << 3)
10539 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
10540 * are present in the tunnel packet headers
10542 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
10543 (UINT32_C(0x2) << 3)
10545 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
10546 (UINT32_C(0x3) << 3)
10547 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
10548 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
10550 * This field is used to provide default CoS value that
10551 * has been configured on this port.
10553 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
10555 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
10558 * This field is used in Output records to indicate that the output
10559 * is completely written to RAM. This field should be read as '1'
10560 * to indicate that the output has been completely written.
10561 * When writing a command completion or response to an internal processor,
10562 * the order of writes has to be such that this field is written last.
10565 } __attribute__((packed));
10567 /**************************
10568 * hwrm_port_mac_ptp_qcfg *
10569 **************************/
10572 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
10573 struct hwrm_port_mac_ptp_qcfg_input {
10574 /* The HWRM command request type. */
10577 * The completion ring to send the completion event on. This should
10578 * be the NQ ID returned from the `nq_alloc` HWRM command.
10580 uint16_t cmpl_ring;
10582 * The sequence ID is used by the driver for tracking multiple
10583 * commands. This ID is treated as opaque data by the firmware and
10584 * the value is returned in the `hwrm_resp_hdr` upon completion.
10588 * The target ID of the command:
10589 * * 0x0-0xFFF8 - The function ID
10590 * * 0xFFF8-0xFFFE - Reserved for internal processors
10593 uint16_t target_id;
10595 * A physical address pointer pointing to a host buffer that the
10596 * command's response data will be written. This can be either a host
10597 * physical address (HPA) or a guest physical address (GPA) and must
10598 * point to a physically contiguous block of memory.
10600 uint64_t resp_addr;
10601 /* Port ID of port that is being queried. */
10603 uint8_t unused_0[6];
10604 } __attribute__((packed));
10606 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
10607 struct hwrm_port_mac_ptp_qcfg_output {
10608 /* The specific error status for the command. */
10609 uint16_t error_code;
10610 /* The HWRM command request type. */
10612 /* The sequence ID from the original command. */
10614 /* The length of the response data in number of bytes. */
10617 * In this field, a number of PTP related flags
10618 * are used to indicate configured PTP capabilities.
10622 * When this bit is set to '1', the PTP related registers are
10623 * directly accessible by the host.
10625 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
10628 * When this bit is set to '1', the PTP information is accessible
10629 * via HWRM commands.
10631 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
10633 uint8_t unused_0[3];
10634 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
10635 uint32_t rx_ts_reg_off_lower;
10636 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
10637 uint32_t rx_ts_reg_off_upper;
10638 /* Offset of the PTP register for the sequence ID for RX. */
10639 uint32_t rx_ts_reg_off_seq_id;
10640 /* Offset of the first PTP source ID for RX. */
10641 uint32_t rx_ts_reg_off_src_id_0;
10642 /* Offset of the second PTP source ID for RX. */
10643 uint32_t rx_ts_reg_off_src_id_1;
10644 /* Offset of the third PTP source ID for RX. */
10645 uint32_t rx_ts_reg_off_src_id_2;
10646 /* Offset of the domain ID for RX. */
10647 uint32_t rx_ts_reg_off_domain_id;
10648 /* Offset of the PTP FIFO register for RX. */
10649 uint32_t rx_ts_reg_off_fifo;
10650 /* Offset of the PTP advance FIFO register for RX. */
10651 uint32_t rx_ts_reg_off_fifo_adv;
10652 /* PTP timestamp granularity for RX. */
10653 uint32_t rx_ts_reg_off_granularity;
10654 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
10655 uint32_t tx_ts_reg_off_lower;
10656 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
10657 uint32_t tx_ts_reg_off_upper;
10658 /* Offset of the PTP register for the sequence ID for TX. */
10659 uint32_t tx_ts_reg_off_seq_id;
10660 /* Offset of the PTP FIFO register for TX. */
10661 uint32_t tx_ts_reg_off_fifo;
10662 /* PTP timestamp granularity for TX. */
10663 uint32_t tx_ts_reg_off_granularity;
10664 uint8_t unused_1[7];
10666 * This field is used in Output records to indicate that the output
10667 * is completely written to RAM. This field should be read as '1'
10668 * to indicate that the output has been completely written.
10669 * When writing a command completion or response to an internal processor,
10670 * the order of writes has to be such that this field is written last.
10673 } __attribute__((packed));
10675 /********************
10676 * hwrm_port_qstats *
10677 ********************/
10680 /* hwrm_port_qstats_input (size:320b/40B) */
10681 struct hwrm_port_qstats_input {
10682 /* The HWRM command request type. */
10685 * The completion ring to send the completion event on. This should
10686 * be the NQ ID returned from the `nq_alloc` HWRM command.
10688 uint16_t cmpl_ring;
10690 * The sequence ID is used by the driver for tracking multiple
10691 * commands. This ID is treated as opaque data by the firmware and
10692 * the value is returned in the `hwrm_resp_hdr` upon completion.
10696 * The target ID of the command:
10697 * * 0x0-0xFFF8 - The function ID
10698 * * 0xFFF8-0xFFFE - Reserved for internal processors
10701 uint16_t target_id;
10703 * A physical address pointer pointing to a host buffer that the
10704 * command's response data will be written. This can be either a host
10705 * physical address (HPA) or a guest physical address (GPA) and must
10706 * point to a physically contiguous block of memory.
10708 uint64_t resp_addr;
10709 /* Port ID of port that is being queried. */
10711 uint8_t unused_0[6];
10713 * This is the host address where
10714 * Tx port statistics will be stored
10716 uint64_t tx_stat_host_addr;
10718 * This is the host address where
10719 * Rx port statistics will be stored
10721 uint64_t rx_stat_host_addr;
10722 } __attribute__((packed));
10724 /* hwrm_port_qstats_output (size:128b/16B) */
10725 struct hwrm_port_qstats_output {
10726 /* The specific error status for the command. */
10727 uint16_t error_code;
10728 /* The HWRM command request type. */
10730 /* The sequence ID from the original command. */
10732 /* The length of the response data in number of bytes. */
10734 /* The size of TX port statistics block in bytes. */
10735 uint16_t tx_stat_size;
10736 /* The size of RX port statistics block in bytes. */
10737 uint16_t rx_stat_size;
10738 uint8_t unused_0[3];
10740 * This field is used in Output records to indicate that the output
10741 * is completely written to RAM. This field should be read as '1'
10742 * to indicate that the output has been completely written.
10743 * When writing a command completion or response to an internal processor,
10744 * the order of writes has to be such that this field is written last.
10747 } __attribute__((packed));
10749 /************************
10750 * hwrm_port_qstats_ext *
10751 ************************/
10754 /* hwrm_port_qstats_ext_input (size:320b/40B) */
10755 struct hwrm_port_qstats_ext_input {
10756 /* The HWRM command request type. */
10759 * The completion ring to send the completion event on. This should
10760 * be the NQ ID returned from the `nq_alloc` HWRM command.
10762 uint16_t cmpl_ring;
10764 * The sequence ID is used by the driver for tracking multiple
10765 * commands. This ID is treated as opaque data by the firmware and
10766 * the value is returned in the `hwrm_resp_hdr` upon completion.
10770 * The target ID of the command:
10771 * * 0x0-0xFFF8 - The function ID
10772 * * 0xFFF8-0xFFFE - Reserved for internal processors
10775 uint16_t target_id;
10777 * A physical address pointer pointing to a host buffer that the
10778 * command's response data will be written. This can be either a host
10779 * physical address (HPA) or a guest physical address (GPA) and must
10780 * point to a physically contiguous block of memory.
10782 uint64_t resp_addr;
10783 /* Port ID of port that is being queried. */
10786 * The size of TX port extended
10787 * statistics block in bytes.
10789 uint16_t tx_stat_size;
10791 * The size of RX port extended
10792 * statistics block in bytes
10794 uint16_t rx_stat_size;
10795 uint8_t unused_0[2];
10797 * This is the host address where
10798 * Tx port statistics will be stored
10800 uint64_t tx_stat_host_addr;
10802 * This is the host address where
10803 * Rx port statistics will be stored
10805 uint64_t rx_stat_host_addr;
10806 } __attribute__((packed));
10808 /* hwrm_port_qstats_ext_output (size:128b/16B) */
10809 struct hwrm_port_qstats_ext_output {
10810 /* The specific error status for the command. */
10811 uint16_t error_code;
10812 /* The HWRM command request type. */
10814 /* The sequence ID from the original command. */
10816 /* The length of the response data in number of bytes. */
10818 /* The size of TX port statistics block in bytes. */
10819 uint16_t tx_stat_size;
10820 /* The size of RX port statistics block in bytes. */
10821 uint16_t rx_stat_size;
10822 uint8_t unused_0[3];
10824 * This field is used in Output records to indicate that the output
10825 * is completely written to RAM. This field should be read as '1'
10826 * to indicate that the output has been completely written.
10827 * When writing a command completion or response to an internal processor,
10828 * the order of writes has to be such that this field is written last.
10831 } __attribute__((packed));
10833 /*************************
10834 * hwrm_port_lpbk_qstats *
10835 *************************/
10838 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
10839 struct hwrm_port_lpbk_qstats_input {
10840 /* The HWRM command request type. */
10843 * The completion ring to send the completion event on. This should
10844 * be the NQ ID returned from the `nq_alloc` HWRM command.
10846 uint16_t cmpl_ring;
10848 * The sequence ID is used by the driver for tracking multiple
10849 * commands. This ID is treated as opaque data by the firmware and
10850 * the value is returned in the `hwrm_resp_hdr` upon completion.
10854 * The target ID of the command:
10855 * * 0x0-0xFFF8 - The function ID
10856 * * 0xFFF8-0xFFFE - Reserved for internal processors
10859 uint16_t target_id;
10861 * A physical address pointer pointing to a host buffer that the
10862 * command's response data will be written. This can be either a host
10863 * physical address (HPA) or a guest physical address (GPA) and must
10864 * point to a physically contiguous block of memory.
10866 uint64_t resp_addr;
10867 } __attribute__((packed));
10869 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
10870 struct hwrm_port_lpbk_qstats_output {
10871 /* The specific error status for the command. */
10872 uint16_t error_code;
10873 /* The HWRM command request type. */
10875 /* The sequence ID from the original command. */
10877 /* The length of the response data in number of bytes. */
10879 /* Number of transmitted unicast frames */
10880 uint64_t lpbk_ucast_frames;
10881 /* Number of transmitted multicast frames */
10882 uint64_t lpbk_mcast_frames;
10883 /* Number of transmitted broadcast frames */
10884 uint64_t lpbk_bcast_frames;
10885 /* Number of transmitted bytes for unicast traffic */
10886 uint64_t lpbk_ucast_bytes;
10887 /* Number of transmitted bytes for multicast traffic */
10888 uint64_t lpbk_mcast_bytes;
10889 /* Number of transmitted bytes for broadcast traffic */
10890 uint64_t lpbk_bcast_bytes;
10891 /* Total Tx Drops for loopback traffic reported by STATS block */
10892 uint64_t tx_stat_discard;
10893 /* Total Tx Error Drops for loopback traffic reported by STATS block */
10894 uint64_t tx_stat_error;
10895 /* Total Rx Drops for loopback traffic reported by STATS block */
10896 uint64_t rx_stat_discard;
10897 /* Total Rx Error Drops for loopback traffic reported by STATS block */
10898 uint64_t rx_stat_error;
10899 uint8_t unused_0[7];
10901 * This field is used in Output records to indicate that the output
10902 * is completely written to RAM. This field should be read as '1'
10903 * to indicate that the output has been completely written.
10904 * When writing a command completion or response to an internal processor,
10905 * the order of writes has to be such that this field is written last.
10908 } __attribute__((packed));
10910 /***********************
10911 * hwrm_port_clr_stats *
10912 ***********************/
10915 /* hwrm_port_clr_stats_input (size:192b/24B) */
10916 struct hwrm_port_clr_stats_input {
10917 /* The HWRM command request type. */
10920 * The completion ring to send the completion event on. This should
10921 * be the NQ ID returned from the `nq_alloc` HWRM command.
10923 uint16_t cmpl_ring;
10925 * The sequence ID is used by the driver for tracking multiple
10926 * commands. This ID is treated as opaque data by the firmware and
10927 * the value is returned in the `hwrm_resp_hdr` upon completion.
10931 * The target ID of the command:
10932 * * 0x0-0xFFF8 - The function ID
10933 * * 0xFFF8-0xFFFE - Reserved for internal processors
10936 uint16_t target_id;
10938 * A physical address pointer pointing to a host buffer that the
10939 * command's response data will be written. This can be either a host
10940 * physical address (HPA) or a guest physical address (GPA) and must
10941 * point to a physically contiguous block of memory.
10943 uint64_t resp_addr;
10944 /* Port ID of port that is being queried. */
10946 uint8_t unused_0[6];
10947 } __attribute__((packed));
10949 /* hwrm_port_clr_stats_output (size:128b/16B) */
10950 struct hwrm_port_clr_stats_output {
10951 /* The specific error status for the command. */
10952 uint16_t error_code;
10953 /* The HWRM command request type. */
10955 /* The sequence ID from the original command. */
10957 /* The length of the response data in number of bytes. */
10959 uint8_t unused_0[7];
10961 * This field is used in Output records to indicate that the output
10962 * is completely written to RAM. This field should be read as '1'
10963 * to indicate that the output has been completely written.
10964 * When writing a command completion or response to an internal processor,
10965 * the order of writes has to be such that this field is written last.
10968 } __attribute__((packed));
10970 /****************************
10971 * hwrm_port_lpbk_clr_stats *
10972 ****************************/
10975 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
10976 struct hwrm_port_lpbk_clr_stats_input {
10977 /* The HWRM command request type. */
10980 * The completion ring to send the completion event on. This should
10981 * be the NQ ID returned from the `nq_alloc` HWRM command.
10983 uint16_t cmpl_ring;
10985 * The sequence ID is used by the driver for tracking multiple
10986 * commands. This ID is treated as opaque data by the firmware and
10987 * the value is returned in the `hwrm_resp_hdr` upon completion.
10991 * The target ID of the command:
10992 * * 0x0-0xFFF8 - The function ID
10993 * * 0xFFF8-0xFFFE - Reserved for internal processors
10996 uint16_t target_id;
10998 * A physical address pointer pointing to a host buffer that the
10999 * command's response data will be written. This can be either a host
11000 * physical address (HPA) or a guest physical address (GPA) and must
11001 * point to a physically contiguous block of memory.
11003 uint64_t resp_addr;
11004 } __attribute__((packed));
11006 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
11007 struct hwrm_port_lpbk_clr_stats_output {
11008 /* The specific error status for the command. */
11009 uint16_t error_code;
11010 /* The HWRM command request type. */
11012 /* The sequence ID from the original command. */
11014 /* The length of the response data in number of bytes. */
11016 uint8_t unused_0[7];
11018 * This field is used in Output records to indicate that the output
11019 * is completely written to RAM. This field should be read as '1'
11020 * to indicate that the output has been completely written.
11021 * When writing a command completion or response to an internal processor,
11022 * the order of writes has to be such that this field is written last.
11025 } __attribute__((packed));
11027 /**********************
11028 * hwrm_port_ts_query *
11029 **********************/
11032 /* hwrm_port_ts_query_input (size:192b/24B) */
11033 struct hwrm_port_ts_query_input {
11034 /* The HWRM command request type. */
11037 * The completion ring to send the completion event on. This should
11038 * be the NQ ID returned from the `nq_alloc` HWRM command.
11040 uint16_t cmpl_ring;
11042 * The sequence ID is used by the driver for tracking multiple
11043 * commands. This ID is treated as opaque data by the firmware and
11044 * the value is returned in the `hwrm_resp_hdr` upon completion.
11048 * The target ID of the command:
11049 * * 0x0-0xFFF8 - The function ID
11050 * * 0xFFF8-0xFFFE - Reserved for internal processors
11053 uint16_t target_id;
11055 * A physical address pointer pointing to a host buffer that the
11056 * command's response data will be written. This can be either a host
11057 * physical address (HPA) or a guest physical address (GPA) and must
11058 * point to a physically contiguous block of memory.
11060 uint64_t resp_addr;
11063 * Enumeration denoting the RX, TX type of the resource.
11064 * This enumeration is used for resources that are similar for both
11065 * TX and RX paths of the chip.
11067 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
11069 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
11071 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
11072 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
11073 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
11074 /* Port ID of port that is being queried. */
11076 uint8_t unused_0[2];
11077 } __attribute__((packed));
11079 /* hwrm_port_ts_query_output (size:192b/24B) */
11080 struct hwrm_port_ts_query_output {
11081 /* The specific error status for the command. */
11082 uint16_t error_code;
11083 /* The HWRM command request type. */
11085 /* The sequence ID from the original command. */
11087 /* The length of the response data in number of bytes. */
11089 /* Timestamp value of PTP message captured. */
11090 uint64_t ptp_msg_ts;
11091 /* Sequence ID of the PTP message captured. */
11092 uint16_t ptp_msg_seqid;
11093 uint8_t unused_0[5];
11095 * This field is used in Output records to indicate that the output
11096 * is completely written to RAM. This field should be read as '1'
11097 * to indicate that the output has been completely written.
11098 * When writing a command completion or response to an internal processor,
11099 * the order of writes has to be such that this field is written last.
11102 } __attribute__((packed));
11104 /***********************
11105 * hwrm_port_phy_qcaps *
11106 ***********************/
11109 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
11110 struct hwrm_port_phy_qcaps_input {
11111 /* The HWRM command request type. */
11114 * The completion ring to send the completion event on. This should
11115 * be the NQ ID returned from the `nq_alloc` HWRM command.
11117 uint16_t cmpl_ring;
11119 * The sequence ID is used by the driver for tracking multiple
11120 * commands. This ID is treated as opaque data by the firmware and
11121 * the value is returned in the `hwrm_resp_hdr` upon completion.
11125 * The target ID of the command:
11126 * * 0x0-0xFFF8 - The function ID
11127 * * 0xFFF8-0xFFFE - Reserved for internal processors
11130 uint16_t target_id;
11132 * A physical address pointer pointing to a host buffer that the
11133 * command's response data will be written. This can be either a host
11134 * physical address (HPA) or a guest physical address (GPA) and must
11135 * point to a physically contiguous block of memory.
11137 uint64_t resp_addr;
11138 /* Port ID of port that is being queried. */
11140 uint8_t unused_0[6];
11141 } __attribute__((packed));
11143 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
11144 struct hwrm_port_phy_qcaps_output {
11145 /* The specific error status for the command. */
11146 uint16_t error_code;
11147 /* The HWRM command request type. */
11149 /* The sequence ID from the original command. */
11151 /* The length of the response data in number of bytes. */
11153 /* PHY capability flags */
11156 * If set to 1, then this field indicates that the
11157 * link is capable of supporting EEE.
11159 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
11162 * If set to 1, then this field indicates that the
11163 * PHY is capable of supporting external loopback.
11165 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
11168 * Reserved field. The HWRM shall set this field to 0.
11169 * An HWRM client shall ignore this field.
11171 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
11173 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
11174 /* Number of front panel ports for this device. */
11176 /* Not supported or unknown */
11177 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
11178 /* single port device */
11179 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
11180 /* 2-port device */
11181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
11182 /* 3-port device */
11183 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
11184 /* 4-port device */
11185 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
11186 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
11187 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
11189 * This is a bit mask to indicate what speeds are supported
11190 * as forced speeds on this link.
11191 * For each speed that can be forced on this link, the
11192 * corresponding mask bit shall be set to '1'.
11194 uint16_t supported_speeds_force_mode;
11195 /* 100Mb link speed (Half-duplex) */
11196 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
11198 /* 100Mb link speed (Full-duplex) */
11199 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
11201 /* 1Gb link speed (Half-duplex) */
11202 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
11204 /* 1Gb link speed (Full-duplex) */
11205 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
11207 /* 2Gb link speed */
11208 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
11210 /* 25Gb link speed */
11211 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
11213 /* 10Gb link speed */
11214 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
11216 /* 20Gb link speed */
11217 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
11219 /* 25Gb link speed */
11220 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
11222 /* 40Gb link speed */
11223 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
11225 /* 50Gb link speed */
11226 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
11228 /* 100Gb link speed */
11229 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
11231 /* 10Mb link speed (Half-duplex) */
11232 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
11234 /* 10Mb link speed (Full-duplex) */
11235 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
11238 * This is a bit mask to indicate what speeds are supported
11239 * for autonegotiation on this link.
11240 * For each speed that can be autonegotiated on this link, the
11241 * corresponding mask bit shall be set to '1'.
11243 uint16_t supported_speeds_auto_mode;
11244 /* 100Mb link speed (Half-duplex) */
11245 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
11247 /* 100Mb link speed (Full-duplex) */
11248 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
11250 /* 1Gb link speed (Half-duplex) */
11251 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
11253 /* 1Gb link speed (Full-duplex) */
11254 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
11256 /* 2Gb link speed */
11257 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
11259 /* 25Gb link speed */
11260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
11262 /* 10Gb link speed */
11263 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
11265 /* 20Gb link speed */
11266 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
11268 /* 25Gb link speed */
11269 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
11271 /* 40Gb link speed */
11272 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
11274 /* 50Gb link speed */
11275 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
11277 /* 100Gb link speed */
11278 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
11280 /* 10Mb link speed (Half-duplex) */
11281 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
11283 /* 10Mb link speed (Full-duplex) */
11284 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
11287 * This is a bit mask to indicate what speeds are supported
11288 * for EEE on this link.
11289 * For each speed that can be autonegotiated when EEE is enabled
11290 * on this link, the corresponding mask bit shall be set to '1'.
11291 * This field is only valid when the eee_suppotred is set to '1'.
11293 uint16_t supported_speeds_eee_mode;
11295 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
11297 /* 100Mb link speed (Full-duplex) */
11298 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
11301 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
11303 /* 1Gb link speed (Full-duplex) */
11304 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
11307 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
11310 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
11312 /* 10Gb link speed */
11313 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
11315 uint32_t tx_lpi_timer_low;
11317 * The lowest value of TX LPI timer that can be set on this link
11318 * when EEE is enabled. This value is in microseconds.
11319 * This field is valid only when_eee_supported is set to '1'.
11321 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
11323 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
11325 * Reserved field. The HWRM shall set this field to 0.
11326 * An HWRM client shall ignore this field.
11328 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
11329 UINT32_C(0xff000000)
11330 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
11331 uint32_t valid_tx_lpi_timer_high;
11333 * The highest value of TX LPI timer that can be set on this link
11334 * when EEE is enabled. This value is in microseconds.
11335 * This field is valid only when_eee_supported is set to '1'.
11337 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
11339 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
11341 * This field is used in Output records to indicate that the output
11342 * is completely written to RAM. This field should be read as '1'
11343 * to indicate that the output has been completely written.
11344 * When writing a command completion or response to an internal processor,
11345 * the order of writes has to be such that this field is written last.
11347 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
11348 UINT32_C(0xff000000)
11349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
11350 } __attribute__((packed));
11352 /***************************
11353 * hwrm_port_phy_i2c_write *
11354 ***************************/
11357 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */
11358 struct hwrm_port_phy_i2c_write_input {
11359 /* The HWRM command request type. */
11362 * The completion ring to send the completion event on. This should
11363 * be the NQ ID returned from the `nq_alloc` HWRM command.
11365 uint16_t cmpl_ring;
11367 * The sequence ID is used by the driver for tracking multiple
11368 * commands. This ID is treated as opaque data by the firmware and
11369 * the value is returned in the `hwrm_resp_hdr` upon completion.
11373 * The target ID of the command:
11374 * * 0x0-0xFFF8 - The function ID
11375 * * 0xFFF8-0xFFFE - Reserved for internal processors
11378 uint16_t target_id;
11380 * A physical address pointer pointing to a host buffer that the
11381 * command's response data will be written. This can be either a host
11382 * physical address (HPA) or a guest physical address (GPA) and must
11383 * point to a physically contiguous block of memory.
11385 uint64_t resp_addr;
11389 * This bit must be '1' for the page_offset field to be
11392 #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \
11394 /* Port ID of port. */
11396 /* 8-bit I2C slave address. */
11397 uint8_t i2c_slave_addr;
11399 /* The page number that is being accessed over I2C. */
11400 uint16_t page_number;
11401 /* Offset within the page that is being accessed over I2C. */
11402 uint16_t page_offset;
11404 * Length of data to write, in bytes starting at the offset
11405 * specified above. If the offset is not specified, then
11406 * the data shall be written from the beginning of the page.
11408 uint8_t data_length;
11409 uint8_t unused_1[7];
11410 /* Up to 64B of data. */
11412 } __attribute__((packed));
11414 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */
11415 struct hwrm_port_phy_i2c_write_output {
11416 /* The specific error status for the command. */
11417 uint16_t error_code;
11418 /* The HWRM command request type. */
11420 /* The sequence ID from the original command. */
11422 /* The length of the response data in number of bytes. */
11424 uint8_t unused_0[7];
11426 * This field is used in Output records to indicate that the output
11427 * is completely written to RAM. This field should be read as '1'
11428 * to indicate that the output has been completely written.
11429 * When writing a command completion or response to an internal processor,
11430 * the order of writes has to be such that this field is written last.
11433 } __attribute__((packed));
11435 /**************************
11436 * hwrm_port_phy_i2c_read *
11437 **************************/
11440 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
11441 struct hwrm_port_phy_i2c_read_input {
11442 /* The HWRM command request type. */
11445 * The completion ring to send the completion event on. This should
11446 * be the NQ ID returned from the `nq_alloc` HWRM command.
11448 uint16_t cmpl_ring;
11450 * The sequence ID is used by the driver for tracking multiple
11451 * commands. This ID is treated as opaque data by the firmware and
11452 * the value is returned in the `hwrm_resp_hdr` upon completion.
11456 * The target ID of the command:
11457 * * 0x0-0xFFF8 - The function ID
11458 * * 0xFFF8-0xFFFE - Reserved for internal processors
11461 uint16_t target_id;
11463 * A physical address pointer pointing to a host buffer that the
11464 * command's response data will be written. This can be either a host
11465 * physical address (HPA) or a guest physical address (GPA) and must
11466 * point to a physically contiguous block of memory.
11468 uint64_t resp_addr;
11472 * This bit must be '1' for the page_offset field to be
11475 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \
11477 /* Port ID of port. */
11479 /* 8-bit I2C slave address. */
11480 uint8_t i2c_slave_addr;
11482 /* The page number that is being accessed over I2C. */
11483 uint16_t page_number;
11484 /* Offset within the page that is being accessed over I2C. */
11485 uint16_t page_offset;
11487 * Length of data to read, in bytes starting at the offset
11488 * specified above. If the offset is not specified, then
11489 * the data shall be read from the beginning of the page.
11491 uint8_t data_length;
11492 uint8_t unused_1[7];
11493 } __attribute__((packed));
11495 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
11496 struct hwrm_port_phy_i2c_read_output {
11497 /* The specific error status for the command. */
11498 uint16_t error_code;
11499 /* The HWRM command request type. */
11501 /* The sequence ID from the original command. */
11503 /* The length of the response data in number of bytes. */
11505 /* Up to 64B of data. */
11507 uint8_t unused_0[7];
11509 * This field is used in Output records to indicate that the output
11510 * is completely written to RAM. This field should be read as '1'
11511 * to indicate that the output has been completely written.
11512 * When writing a command completion or response to an internal processor,
11513 * the order of writes has to be such that this field is written last.
11516 } __attribute__((packed));
11518 /*********************
11519 * hwrm_port_led_cfg *
11520 *********************/
11523 /* hwrm_port_led_cfg_input (size:512b/64B) */
11524 struct hwrm_port_led_cfg_input {
11525 /* The HWRM command request type. */
11528 * The completion ring to send the completion event on. This should
11529 * be the NQ ID returned from the `nq_alloc` HWRM command.
11531 uint16_t cmpl_ring;
11533 * The sequence ID is used by the driver for tracking multiple
11534 * commands. This ID is treated as opaque data by the firmware and
11535 * the value is returned in the `hwrm_resp_hdr` upon completion.
11539 * The target ID of the command:
11540 * * 0x0-0xFFF8 - The function ID
11541 * * 0xFFF8-0xFFFE - Reserved for internal processors
11544 uint16_t target_id;
11546 * A physical address pointer pointing to a host buffer that the
11547 * command's response data will be written. This can be either a host
11548 * physical address (HPA) or a guest physical address (GPA) and must
11549 * point to a physically contiguous block of memory.
11551 uint64_t resp_addr;
11554 * This bit must be '1' for the led0_id field to be
11557 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
11560 * This bit must be '1' for the led0_state field to be
11563 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
11566 * This bit must be '1' for the led0_color field to be
11569 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
11572 * This bit must be '1' for the led0_blink_on field to be
11575 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
11578 * This bit must be '1' for the led0_blink_off field to be
11581 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
11584 * This bit must be '1' for the led0_group_id field to be
11587 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
11590 * This bit must be '1' for the led1_id field to be
11593 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
11596 * This bit must be '1' for the led1_state field to be
11599 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
11602 * This bit must be '1' for the led1_color field to be
11605 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
11608 * This bit must be '1' for the led1_blink_on field to be
11611 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
11614 * This bit must be '1' for the led1_blink_off field to be
11617 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
11620 * This bit must be '1' for the led1_group_id field to be
11623 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
11626 * This bit must be '1' for the led2_id field to be
11629 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
11632 * This bit must be '1' for the led2_state field to be
11635 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
11638 * This bit must be '1' for the led2_color field to be
11641 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
11644 * This bit must be '1' for the led2_blink_on field to be
11647 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
11650 * This bit must be '1' for the led2_blink_off field to be
11653 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
11656 * This bit must be '1' for the led2_group_id field to be
11659 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
11662 * This bit must be '1' for the led3_id field to be
11665 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
11668 * This bit must be '1' for the led3_state field to be
11671 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
11674 * This bit must be '1' for the led3_color field to be
11677 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
11680 * This bit must be '1' for the led3_blink_on field to be
11683 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
11686 * This bit must be '1' for the led3_blink_off field to be
11689 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
11692 * This bit must be '1' for the led3_group_id field to be
11695 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
11697 /* Port ID of port whose LEDs are configured. */
11700 * The number of LEDs that are being configured.
11701 * Up to 4 LEDs can be configured with this command.
11704 /* Reserved field. */
11706 /* An identifier for the LED #0. */
11708 /* The requested state of the LED #0. */
11709 uint8_t led0_state;
11710 /* Default state of the LED */
11711 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
11713 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
11715 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
11717 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
11718 /* Blink Alternately */
11719 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
11720 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
11721 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
11722 /* The requested color of LED #0. */
11723 uint8_t led0_color;
11725 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
11727 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
11729 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
11730 /* Green or Amber */
11731 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
11732 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
11733 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
11736 * If the LED #0 state is "blink" or "blinkalt", then
11737 * this field represents the requested time in milliseconds
11738 * to keep LED on between cycles.
11740 uint16_t led0_blink_on;
11742 * If the LED #0 state is "blink" or "blinkalt", then
11743 * this field represents the requested time in milliseconds
11744 * to keep LED off between cycles.
11746 uint16_t led0_blink_off;
11748 * An identifier for the group of LEDs that LED #0 belongs
11750 * If set to 0, then the LED #0 shall not be grouped and
11751 * shall be treated as an individual resource.
11752 * For all other non-zero values of this field, LED #0 shall
11753 * be grouped together with the LEDs with the same group ID
11756 uint8_t led0_group_id;
11757 /* Reserved field. */
11759 /* An identifier for the LED #1. */
11761 /* The requested state of the LED #1. */
11762 uint8_t led1_state;
11763 /* Default state of the LED */
11764 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
11766 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
11768 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
11770 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
11771 /* Blink Alternately */
11772 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
11773 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
11774 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
11775 /* The requested color of LED #1. */
11776 uint8_t led1_color;
11778 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
11780 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
11782 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
11783 /* Green or Amber */
11784 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
11785 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
11786 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
11789 * If the LED #1 state is "blink" or "blinkalt", then
11790 * this field represents the requested time in milliseconds
11791 * to keep LED on between cycles.
11793 uint16_t led1_blink_on;
11795 * If the LED #1 state is "blink" or "blinkalt", then
11796 * this field represents the requested time in milliseconds
11797 * to keep LED off between cycles.
11799 uint16_t led1_blink_off;
11801 * An identifier for the group of LEDs that LED #1 belongs
11803 * If set to 0, then the LED #1 shall not be grouped and
11804 * shall be treated as an individual resource.
11805 * For all other non-zero values of this field, LED #1 shall
11806 * be grouped together with the LEDs with the same group ID
11809 uint8_t led1_group_id;
11810 /* Reserved field. */
11812 /* An identifier for the LED #2. */
11814 /* The requested state of the LED #2. */
11815 uint8_t led2_state;
11816 /* Default state of the LED */
11817 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
11819 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
11821 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
11823 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
11824 /* Blink Alternately */
11825 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
11826 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
11827 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
11828 /* The requested color of LED #2. */
11829 uint8_t led2_color;
11831 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
11833 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
11835 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
11836 /* Green or Amber */
11837 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
11838 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
11839 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
11842 * If the LED #2 state is "blink" or "blinkalt", then
11843 * this field represents the requested time in milliseconds
11844 * to keep LED on between cycles.
11846 uint16_t led2_blink_on;
11848 * If the LED #2 state is "blink" or "blinkalt", then
11849 * this field represents the requested time in milliseconds
11850 * to keep LED off between cycles.
11852 uint16_t led2_blink_off;
11854 * An identifier for the group of LEDs that LED #2 belongs
11856 * If set to 0, then the LED #2 shall not be grouped and
11857 * shall be treated as an individual resource.
11858 * For all other non-zero values of this field, LED #2 shall
11859 * be grouped together with the LEDs with the same group ID
11862 uint8_t led2_group_id;
11863 /* Reserved field. */
11865 /* An identifier for the LED #3. */
11867 /* The requested state of the LED #3. */
11868 uint8_t led3_state;
11869 /* Default state of the LED */
11870 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
11872 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
11874 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
11876 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
11877 /* Blink Alternately */
11878 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
11879 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
11880 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
11881 /* The requested color of LED #3. */
11882 uint8_t led3_color;
11884 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
11886 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
11888 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
11889 /* Green or Amber */
11890 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
11891 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
11892 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
11895 * If the LED #3 state is "blink" or "blinkalt", then
11896 * this field represents the requested time in milliseconds
11897 * to keep LED on between cycles.
11899 uint16_t led3_blink_on;
11901 * If the LED #3 state is "blink" or "blinkalt", then
11902 * this field represents the requested time in milliseconds
11903 * to keep LED off between cycles.
11905 uint16_t led3_blink_off;
11907 * An identifier for the group of LEDs that LED #3 belongs
11909 * If set to 0, then the LED #3 shall not be grouped and
11910 * shall be treated as an individual resource.
11911 * For all other non-zero values of this field, LED #3 shall
11912 * be grouped together with the LEDs with the same group ID
11915 uint8_t led3_group_id;
11916 /* Reserved field. */
11918 } __attribute__((packed));
11920 /* hwrm_port_led_cfg_output (size:128b/16B) */
11921 struct hwrm_port_led_cfg_output {
11922 /* The specific error status for the command. */
11923 uint16_t error_code;
11924 /* The HWRM command request type. */
11926 /* The sequence ID from the original command. */
11928 /* The length of the response data in number of bytes. */
11930 uint8_t unused_0[7];
11932 * This field is used in Output records to indicate that the output
11933 * is completely written to RAM. This field should be read as '1'
11934 * to indicate that the output has been completely written.
11935 * When writing a command completion or response to an internal processor,
11936 * the order of writes has to be such that this field is written last.
11939 } __attribute__((packed));
11941 /**********************
11942 * hwrm_port_led_qcfg *
11943 **********************/
11946 /* hwrm_port_led_qcfg_input (size:192b/24B) */
11947 struct hwrm_port_led_qcfg_input {
11948 /* The HWRM command request type. */
11951 * The completion ring to send the completion event on. This should
11952 * be the NQ ID returned from the `nq_alloc` HWRM command.
11954 uint16_t cmpl_ring;
11956 * The sequence ID is used by the driver for tracking multiple
11957 * commands. This ID is treated as opaque data by the firmware and
11958 * the value is returned in the `hwrm_resp_hdr` upon completion.
11962 * The target ID of the command:
11963 * * 0x0-0xFFF8 - The function ID
11964 * * 0xFFF8-0xFFFE - Reserved for internal processors
11967 uint16_t target_id;
11969 * A physical address pointer pointing to a host buffer that the
11970 * command's response data will be written. This can be either a host
11971 * physical address (HPA) or a guest physical address (GPA) and must
11972 * point to a physically contiguous block of memory.
11974 uint64_t resp_addr;
11975 /* Port ID of port whose LED configuration is being queried. */
11977 uint8_t unused_0[6];
11978 } __attribute__((packed));
11980 /* hwrm_port_led_qcfg_output (size:448b/56B) */
11981 struct hwrm_port_led_qcfg_output {
11982 /* The specific error status for the command. */
11983 uint16_t error_code;
11984 /* The HWRM command request type. */
11986 /* The sequence ID from the original command. */
11988 /* The length of the response data in number of bytes. */
11991 * The number of LEDs that are configured on this port.
11992 * Up to 4 LEDs can be returned in the response.
11995 /* An identifier for the LED #0. */
11997 /* The type of LED #0. */
12000 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
12002 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
12004 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
12005 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
12006 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
12007 /* The current state of the LED #0. */
12008 uint8_t led0_state;
12009 /* Default state of the LED */
12010 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
12012 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
12014 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
12016 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
12017 /* Blink Alternately */
12018 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
12019 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
12020 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
12021 /* The color of LED #0. */
12022 uint8_t led0_color;
12024 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
12026 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
12028 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
12029 /* Green or Amber */
12030 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
12031 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
12032 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
12035 * If the LED #0 state is "blink" or "blinkalt", then
12036 * this field represents the requested time in milliseconds
12037 * to keep LED on between cycles.
12039 uint16_t led0_blink_on;
12041 * If the LED #0 state is "blink" or "blinkalt", then
12042 * this field represents the requested time in milliseconds
12043 * to keep LED off between cycles.
12045 uint16_t led0_blink_off;
12047 * An identifier for the group of LEDs that LED #0 belongs
12049 * If set to 0, then the LED #0 is not grouped.
12050 * For all other non-zero values of this field, LED #0 is
12051 * grouped together with the LEDs with the same group ID
12054 uint8_t led0_group_id;
12055 /* An identifier for the LED #1. */
12057 /* The type of LED #1. */
12060 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
12062 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
12064 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
12065 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
12066 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
12067 /* The current state of the LED #1. */
12068 uint8_t led1_state;
12069 /* Default state of the LED */
12070 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
12072 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
12074 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
12076 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
12077 /* Blink Alternately */
12078 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
12079 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
12080 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
12081 /* The color of LED #1. */
12082 uint8_t led1_color;
12084 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
12086 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
12088 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
12089 /* Green or Amber */
12090 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
12091 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
12092 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
12095 * If the LED #1 state is "blink" or "blinkalt", then
12096 * this field represents the requested time in milliseconds
12097 * to keep LED on between cycles.
12099 uint16_t led1_blink_on;
12101 * If the LED #1 state is "blink" or "blinkalt", then
12102 * this field represents the requested time in milliseconds
12103 * to keep LED off between cycles.
12105 uint16_t led1_blink_off;
12107 * An identifier for the group of LEDs that LED #1 belongs
12109 * If set to 0, then the LED #1 is not grouped.
12110 * For all other non-zero values of this field, LED #1 is
12111 * grouped together with the LEDs with the same group ID
12114 uint8_t led1_group_id;
12115 /* An identifier for the LED #2. */
12117 /* The type of LED #2. */
12120 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
12122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
12124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
12125 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
12126 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
12127 /* The current state of the LED #2. */
12128 uint8_t led2_state;
12129 /* Default state of the LED */
12130 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
12132 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
12134 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
12136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
12137 /* Blink Alternately */
12138 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
12139 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
12140 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
12141 /* The color of LED #2. */
12142 uint8_t led2_color;
12144 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
12146 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
12148 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
12149 /* Green or Amber */
12150 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
12151 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
12152 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
12155 * If the LED #2 state is "blink" or "blinkalt", then
12156 * this field represents the requested time in milliseconds
12157 * to keep LED on between cycles.
12159 uint16_t led2_blink_on;
12161 * If the LED #2 state is "blink" or "blinkalt", then
12162 * this field represents the requested time in milliseconds
12163 * to keep LED off between cycles.
12165 uint16_t led2_blink_off;
12167 * An identifier for the group of LEDs that LED #2 belongs
12169 * If set to 0, then the LED #2 is not grouped.
12170 * For all other non-zero values of this field, LED #2 is
12171 * grouped together with the LEDs with the same group ID
12174 uint8_t led2_group_id;
12175 /* An identifier for the LED #3. */
12177 /* The type of LED #3. */
12180 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
12182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
12184 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
12185 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
12186 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
12187 /* The current state of the LED #3. */
12188 uint8_t led3_state;
12189 /* Default state of the LED */
12190 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
12192 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
12194 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
12196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
12197 /* Blink Alternately */
12198 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
12199 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
12200 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
12201 /* The color of LED #3. */
12202 uint8_t led3_color;
12204 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
12206 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
12208 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
12209 /* Green or Amber */
12210 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
12211 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
12212 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
12215 * If the LED #3 state is "blink" or "blinkalt", then
12216 * this field represents the requested time in milliseconds
12217 * to keep LED on between cycles.
12219 uint16_t led3_blink_on;
12221 * If the LED #3 state is "blink" or "blinkalt", then
12222 * this field represents the requested time in milliseconds
12223 * to keep LED off between cycles.
12225 uint16_t led3_blink_off;
12227 * An identifier for the group of LEDs that LED #3 belongs
12229 * If set to 0, then the LED #3 is not grouped.
12230 * For all other non-zero values of this field, LED #3 is
12231 * grouped together with the LEDs with the same group ID
12234 uint8_t led3_group_id;
12235 uint8_t unused_4[6];
12237 * This field is used in Output records to indicate that the output
12238 * is completely written to RAM. This field should be read as '1'
12239 * to indicate that the output has been completely written.
12240 * When writing a command completion or response to an internal processor,
12241 * the order of writes has to be such that this field is written last.
12244 } __attribute__((packed));
12246 /***********************
12247 * hwrm_port_led_qcaps *
12248 ***********************/
12251 /* hwrm_port_led_qcaps_input (size:192b/24B) */
12252 struct hwrm_port_led_qcaps_input {
12253 /* The HWRM command request type. */
12256 * The completion ring to send the completion event on. This should
12257 * be the NQ ID returned from the `nq_alloc` HWRM command.
12259 uint16_t cmpl_ring;
12261 * The sequence ID is used by the driver for tracking multiple
12262 * commands. This ID is treated as opaque data by the firmware and
12263 * the value is returned in the `hwrm_resp_hdr` upon completion.
12267 * The target ID of the command:
12268 * * 0x0-0xFFF8 - The function ID
12269 * * 0xFFF8-0xFFFE - Reserved for internal processors
12272 uint16_t target_id;
12274 * A physical address pointer pointing to a host buffer that the
12275 * command's response data will be written. This can be either a host
12276 * physical address (HPA) or a guest physical address (GPA) and must
12277 * point to a physically contiguous block of memory.
12279 uint64_t resp_addr;
12280 /* Port ID of port whose LED configuration is being queried. */
12282 uint8_t unused_0[6];
12283 } __attribute__((packed));
12285 /* hwrm_port_led_qcaps_output (size:384b/48B) */
12286 struct hwrm_port_led_qcaps_output {
12287 /* The specific error status for the command. */
12288 uint16_t error_code;
12289 /* The HWRM command request type. */
12291 /* The sequence ID from the original command. */
12293 /* The length of the response data in number of bytes. */
12296 * The number of LEDs that are configured on this port.
12297 * Up to 4 LEDs can be returned in the response.
12300 /* Reserved for future use. */
12302 /* An identifier for the LED #0. */
12304 /* The type of LED #0. */
12307 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
12309 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
12311 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
12312 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
12313 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
12315 * An identifier for the group of LEDs that LED #0 belongs
12317 * If set to 0, then the LED #0 cannot be grouped.
12318 * For all other non-zero values of this field, LED #0 is
12319 * grouped together with the LEDs with the same group ID
12322 uint8_t led0_group_id;
12324 /* The states supported by LED #0. */
12325 uint16_t led0_state_caps;
12327 * If set to 1, this LED is enabled.
12328 * If set to 0, this LED is disabled.
12330 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
12333 * If set to 1, off state is supported on this LED.
12334 * If set to 0, off state is not supported on this LED.
12336 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
12339 * If set to 1, on state is supported on this LED.
12340 * If set to 0, on state is not supported on this LED.
12342 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
12345 * If set to 1, blink state is supported on this LED.
12346 * If set to 0, blink state is not supported on this LED.
12348 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
12351 * If set to 1, blink_alt state is supported on this LED.
12352 * If set to 0, blink_alt state is not supported on this LED.
12354 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
12356 /* The colors supported by LED #0. */
12357 uint16_t led0_color_caps;
12359 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
12362 * If set to 1, Amber color is supported on this LED.
12363 * If set to 0, Amber color is not supported on this LED.
12365 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
12368 * If set to 1, Green color is supported on this LED.
12369 * If set to 0, Green color is not supported on this LED.
12371 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
12373 /* An identifier for the LED #1. */
12375 /* The type of LED #1. */
12378 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
12380 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
12382 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
12383 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
12384 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
12386 * An identifier for the group of LEDs that LED #1 belongs
12388 * If set to 0, then the LED #0 cannot be grouped.
12389 * For all other non-zero values of this field, LED #0 is
12390 * grouped together with the LEDs with the same group ID
12393 uint8_t led1_group_id;
12395 /* The states supported by LED #1. */
12396 uint16_t led1_state_caps;
12398 * If set to 1, this LED is enabled.
12399 * If set to 0, this LED is disabled.
12401 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
12404 * If set to 1, off state is supported on this LED.
12405 * If set to 0, off state is not supported on this LED.
12407 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
12410 * If set to 1, on state is supported on this LED.
12411 * If set to 0, on state is not supported on this LED.
12413 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
12416 * If set to 1, blink state is supported on this LED.
12417 * If set to 0, blink state is not supported on this LED.
12419 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
12422 * If set to 1, blink_alt state is supported on this LED.
12423 * If set to 0, blink_alt state is not supported on this LED.
12425 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
12427 /* The colors supported by LED #1. */
12428 uint16_t led1_color_caps;
12430 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
12433 * If set to 1, Amber color is supported on this LED.
12434 * If set to 0, Amber color is not supported on this LED.
12436 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
12439 * If set to 1, Green color is supported on this LED.
12440 * If set to 0, Green color is not supported on this LED.
12442 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
12444 /* An identifier for the LED #2. */
12446 /* The type of LED #2. */
12449 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
12451 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
12453 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
12454 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
12455 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
12457 * An identifier for the group of LEDs that LED #0 belongs
12459 * If set to 0, then the LED #0 cannot be grouped.
12460 * For all other non-zero values of this field, LED #0 is
12461 * grouped together with the LEDs with the same group ID
12464 uint8_t led2_group_id;
12466 /* The states supported by LED #2. */
12467 uint16_t led2_state_caps;
12469 * If set to 1, this LED is enabled.
12470 * If set to 0, this LED is disabled.
12472 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
12475 * If set to 1, off state is supported on this LED.
12476 * If set to 0, off state is not supported on this LED.
12478 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
12481 * If set to 1, on state is supported on this LED.
12482 * If set to 0, on state is not supported on this LED.
12484 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
12487 * If set to 1, blink state is supported on this LED.
12488 * If set to 0, blink state is not supported on this LED.
12490 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
12493 * If set to 1, blink_alt state is supported on this LED.
12494 * If set to 0, blink_alt state is not supported on this LED.
12496 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
12498 /* The colors supported by LED #2. */
12499 uint16_t led2_color_caps;
12501 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
12504 * If set to 1, Amber color is supported on this LED.
12505 * If set to 0, Amber color is not supported on this LED.
12507 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
12510 * If set to 1, Green color is supported on this LED.
12511 * If set to 0, Green color is not supported on this LED.
12513 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
12515 /* An identifier for the LED #3. */
12517 /* The type of LED #3. */
12520 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
12522 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
12524 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
12525 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
12526 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
12528 * An identifier for the group of LEDs that LED #3 belongs
12530 * If set to 0, then the LED #0 cannot be grouped.
12531 * For all other non-zero values of this field, LED #0 is
12532 * grouped together with the LEDs with the same group ID
12535 uint8_t led3_group_id;
12537 /* The states supported by LED #3. */
12538 uint16_t led3_state_caps;
12540 * If set to 1, this LED is enabled.
12541 * If set to 0, this LED is disabled.
12543 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
12546 * If set to 1, off state is supported on this LED.
12547 * If set to 0, off state is not supported on this LED.
12549 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
12552 * If set to 1, on state is supported on this LED.
12553 * If set to 0, on state is not supported on this LED.
12555 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
12558 * If set to 1, blink state is supported on this LED.
12559 * If set to 0, blink state is not supported on this LED.
12561 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
12564 * If set to 1, blink_alt state is supported on this LED.
12565 * If set to 0, blink_alt state is not supported on this LED.
12567 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
12569 /* The colors supported by LED #3. */
12570 uint16_t led3_color_caps;
12572 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
12575 * If set to 1, Amber color is supported on this LED.
12576 * If set to 0, Amber color is not supported on this LED.
12578 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
12581 * If set to 1, Green color is supported on this LED.
12582 * If set to 0, Green color is not supported on this LED.
12584 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
12586 uint8_t unused_4[3];
12588 * This field is used in Output records to indicate that the output
12589 * is completely written to RAM. This field should be read as '1'
12590 * to indicate that the output has been completely written.
12591 * When writing a command completion or response to an internal processor,
12592 * the order of writes has to be such that this field is written last.
12595 } __attribute__((packed));
12597 /***********************
12598 * hwrm_queue_qportcfg *
12599 ***********************/
12602 /* hwrm_queue_qportcfg_input (size:192b/24B) */
12603 struct hwrm_queue_qportcfg_input {
12604 /* The HWRM command request type. */
12607 * The completion ring to send the completion event on. This should
12608 * be the NQ ID returned from the `nq_alloc` HWRM command.
12610 uint16_t cmpl_ring;
12612 * The sequence ID is used by the driver for tracking multiple
12613 * commands. This ID is treated as opaque data by the firmware and
12614 * the value is returned in the `hwrm_resp_hdr` upon completion.
12618 * The target ID of the command:
12619 * * 0x0-0xFFF8 - The function ID
12620 * * 0xFFF8-0xFFFE - Reserved for internal processors
12623 uint16_t target_id;
12625 * A physical address pointer pointing to a host buffer that the
12626 * command's response data will be written. This can be either a host
12627 * physical address (HPA) or a guest physical address (GPA) and must
12628 * point to a physically contiguous block of memory.
12630 uint64_t resp_addr;
12633 * Enumeration denoting the RX, TX type of the resource.
12634 * This enumeration is used for resources that are similar for both
12635 * TX and RX paths of the chip.
12637 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
12639 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
12641 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
12642 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
12643 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
12645 * Port ID of port for which the queue configuration is being
12646 * queried. This field is only required when sent by IPC.
12650 * Drivers will set this capability when it can use
12651 * queue_idx_service_profile to map the queues to application.
12653 uint8_t drv_qmap_cap;
12655 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
12657 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
12658 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
12659 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
12661 } __attribute__((packed));
12663 /* hwrm_queue_qportcfg_output (size:256b/32B) */
12664 struct hwrm_queue_qportcfg_output {
12665 /* The specific error status for the command. */
12666 uint16_t error_code;
12667 /* The HWRM command request type. */
12669 /* The sequence ID from the original command. */
12671 /* The length of the response data in number of bytes. */
12674 * The maximum number of queues that can be configured on this
12676 * Valid values range from 1 through 8.
12678 uint8_t max_configurable_queues;
12680 * The maximum number of lossless queues that can be configured
12682 * Valid values range from 0 through 8.
12684 uint8_t max_configurable_lossless_queues;
12686 * Bitmask indicating which queues can be configured by the
12687 * hwrm_queue_cfg command.
12689 * Each bit represents a specific queue where bit 0 represents
12690 * queue 0 and bit 7 represents queue 7.
12691 * # A value of 0 indicates that the queue is not configurable
12692 * by the hwrm_queue_cfg command.
12693 * # A value of 1 indicates that the queue is configurable.
12694 * # A hwrm_queue_cfg command shall return error when trying to
12695 * configure a queue not configurable.
12697 uint8_t queue_cfg_allowed;
12698 /* Information about queue configuration. */
12699 uint8_t queue_cfg_info;
12701 * If this flag is set to '1', then the queues are
12702 * configured asymmetrically on TX and RX sides.
12703 * If this flag is set to '0', then the queues are
12704 * configured symmetrically on TX and RX sides. For
12705 * symmetric configuration, the queue configuration
12706 * including queue ids and service profiles on the
12707 * TX side is the same as the corresponding queue
12708 * configuration on the RX side.
12710 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
12713 * Bitmask indicating which queues can be configured by the
12714 * hwrm_queue_pfcenable_cfg command.
12716 * Each bit represents a specific priority where bit 0 represents
12717 * priority 0 and bit 7 represents priority 7.
12718 * # A value of 0 indicates that the priority is not configurable by
12719 * the hwrm_queue_pfcenable_cfg command.
12720 * # A value of 1 indicates that the priority is configurable.
12721 * # A hwrm_queue_pfcenable_cfg command shall return error when
12722 * trying to configure a priority that is not configurable.
12724 uint8_t queue_pfcenable_cfg_allowed;
12726 * Bitmask indicating which queues can be configured by the
12727 * hwrm_queue_pri2cos_cfg command.
12729 * Each bit represents a specific queue where bit 0 represents
12730 * queue 0 and bit 7 represents queue 7.
12731 * # A value of 0 indicates that the queue is not configurable
12732 * by the hwrm_queue_pri2cos_cfg command.
12733 * # A value of 1 indicates that the queue is configurable.
12734 * # A hwrm_queue_pri2cos_cfg command shall return error when
12735 * trying to configure a queue that is not configurable.
12737 uint8_t queue_pri2cos_cfg_allowed;
12739 * Bitmask indicating which queues can be configured by the
12740 * hwrm_queue_pri2cos_cfg command.
12742 * Each bit represents a specific queue where bit 0 represents
12743 * queue 0 and bit 7 represents queue 7.
12744 * # A value of 0 indicates that the queue is not configurable
12745 * by the hwrm_queue_pri2cos_cfg command.
12746 * # A value of 1 indicates that the queue is configurable.
12747 * # A hwrm_queue_pri2cos_cfg command shall return error when
12748 * trying to configure a queue not configurable.
12750 uint8_t queue_cos2bw_cfg_allowed;
12752 * ID of CoS Queue 0.
12755 * # This ID can be used on any subsequent call to an hwrm command
12756 * that takes a queue id.
12757 * # IDs must always be queried by this command before any use
12758 * by the driver or software.
12759 * # Any driver or software should not make any assumptions about
12761 * # A value of 0xff indicates that the queue is not available.
12762 * # Available queues may not be in sequential order.
12765 /* This value is applicable to CoS queues only. */
12766 uint8_t queue_id0_service_profile;
12767 /* Lossy (best-effort) */
12768 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
12770 /* Lossless (legacy) */
12771 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
12773 /* Lossless RoCE */
12774 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
12776 /* Lossy RoCE CNP */
12777 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12780 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
12782 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12783 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
12785 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
12786 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
12788 * ID of CoS Queue 1.
12791 * # This ID can be used on any subsequent call to an hwrm command
12792 * that takes a queue id.
12793 * # IDs must always be queried by this command before any use
12794 * by the driver or software.
12795 * # Any driver or software should not make any assumptions about
12797 * # A value of 0xff indicates that the queue is not available.
12798 * # Available queues may not be in sequential order.
12801 /* This value is applicable to CoS queues only. */
12802 uint8_t queue_id1_service_profile;
12803 /* Lossy (best-effort) */
12804 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
12806 /* Lossless (legacy) */
12807 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
12809 /* Lossless RoCE */
12810 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
12812 /* Lossy RoCE CNP */
12813 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12816 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
12818 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12819 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
12821 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
12822 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
12824 * ID of CoS Queue 2.
12827 * # This ID can be used on any subsequent call to an hwrm command
12828 * that takes a queue id.
12829 * # IDs must always be queried by this command before any use
12830 * by the driver or software.
12831 * # Any driver or software should not make any assumptions about
12833 * # A value of 0xff indicates that the queue is not available.
12834 * # Available queues may not be in sequential order.
12837 /* This value is applicable to CoS queues only. */
12838 uint8_t queue_id2_service_profile;
12839 /* Lossy (best-effort) */
12840 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
12842 /* Lossless (legacy) */
12843 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
12845 /* Lossless RoCE */
12846 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
12848 /* Lossy RoCE CNP */
12849 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12852 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
12854 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12855 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
12857 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
12858 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
12860 * ID of CoS Queue 3.
12863 * # This ID can be used on any subsequent call to an hwrm command
12864 * that takes a queue id.
12865 * # IDs must always be queried by this command before any use
12866 * by the driver or software.
12867 * # Any driver or software should not make any assumptions about
12869 * # A value of 0xff indicates that the queue is not available.
12870 * # Available queues may not be in sequential order.
12873 /* This value is applicable to CoS queues only. */
12874 uint8_t queue_id3_service_profile;
12875 /* Lossy (best-effort) */
12876 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
12878 /* Lossless (legacy) */
12879 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
12881 /* Lossless RoCE */
12882 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
12884 /* Lossy RoCE CNP */
12885 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12888 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
12890 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12891 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
12893 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
12894 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
12896 * ID of CoS Queue 4.
12899 * # This ID can be used on any subsequent call to an hwrm command
12900 * that takes a queue id.
12901 * # IDs must always be queried by this command before any use
12902 * by the driver or software.
12903 * # Any driver or software should not make any assumptions about
12905 * # A value of 0xff indicates that the queue is not available.
12906 * # Available queues may not be in sequential order.
12909 /* This value is applicable to CoS queues only. */
12910 uint8_t queue_id4_service_profile;
12911 /* Lossy (best-effort) */
12912 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
12914 /* Lossless (legacy) */
12915 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
12917 /* Lossless RoCE */
12918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
12920 /* Lossy RoCE CNP */
12921 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12924 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
12926 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12927 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
12929 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
12930 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
12932 * ID of CoS Queue 5.
12935 * # This ID can be used on any subsequent call to an hwrm command
12936 * that takes a queue id.
12937 * # IDs must always be queried by this command before any use
12938 * by the driver or software.
12939 * # Any driver or software should not make any assumptions about
12941 * # A value of 0xff indicates that the queue is not available.
12942 * # Available queues may not be in sequential order.
12945 /* This value is applicable to CoS queues only. */
12946 uint8_t queue_id5_service_profile;
12947 /* Lossy (best-effort) */
12948 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
12950 /* Lossless (legacy) */
12951 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
12953 /* Lossless RoCE */
12954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
12956 /* Lossy RoCE CNP */
12957 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12960 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
12962 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12963 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
12965 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
12966 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
12968 * ID of CoS Queue 6.
12971 * # This ID can be used on any subsequent call to an hwrm command
12972 * that takes a queue id.
12973 * # IDs must always be queried by this command before any use
12974 * by the driver or software.
12975 * # Any driver or software should not make any assumptions about
12977 * # A value of 0xff indicates that the queue is not available.
12978 * # Available queues may not be in sequential order.
12981 /* This value is applicable to CoS queues only. */
12982 uint8_t queue_id6_service_profile;
12983 /* Lossy (best-effort) */
12984 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
12986 /* Lossless (legacy) */
12987 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
12989 /* Lossless RoCE */
12990 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
12992 /* Lossy RoCE CNP */
12993 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
12996 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
12998 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12999 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
13001 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
13002 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
13004 * ID of CoS Queue 7.
13007 * # This ID can be used on any subsequent call to an hwrm command
13008 * that takes a queue id.
13009 * # IDs must always be queried by this command before any use
13010 * by the driver or software.
13011 * # Any driver or software should not make any assumptions about
13013 * # A value of 0xff indicates that the queue is not available.
13014 * # Available queues may not be in sequential order.
13017 /* This value is applicable to CoS queues only. */
13018 uint8_t queue_id7_service_profile;
13019 /* Lossy (best-effort) */
13020 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
13022 /* Lossless (legacy) */
13023 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
13025 /* Lossless RoCE */
13026 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
13028 /* Lossy RoCE CNP */
13029 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
13032 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
13034 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13035 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
13037 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
13038 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
13040 * This field is used in Output records to indicate that the output
13041 * is completely written to RAM. This field should be read as '1'
13042 * to indicate that the output has been completely written.
13043 * When writing a command completion or response to an internal processor,
13044 * the order of writes has to be such that this field is written last.
13047 } __attribute__((packed));
13049 /*******************
13050 * hwrm_queue_qcfg *
13051 *******************/
13054 /* hwrm_queue_qcfg_input (size:192b/24B) */
13055 struct hwrm_queue_qcfg_input {
13056 /* The HWRM command request type. */
13059 * The completion ring to send the completion event on. This should
13060 * be the NQ ID returned from the `nq_alloc` HWRM command.
13062 uint16_t cmpl_ring;
13064 * The sequence ID is used by the driver for tracking multiple
13065 * commands. This ID is treated as opaque data by the firmware and
13066 * the value is returned in the `hwrm_resp_hdr` upon completion.
13070 * The target ID of the command:
13071 * * 0x0-0xFFF8 - The function ID
13072 * * 0xFFF8-0xFFFE - Reserved for internal processors
13075 uint16_t target_id;
13077 * A physical address pointer pointing to a host buffer that the
13078 * command's response data will be written. This can be either a host
13079 * physical address (HPA) or a guest physical address (GPA) and must
13080 * point to a physically contiguous block of memory.
13082 uint64_t resp_addr;
13085 * Enumeration denoting the RX, TX type of the resource.
13086 * This enumeration is used for resources that are similar for both
13087 * TX and RX paths of the chip.
13089 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
13091 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13093 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13094 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
13095 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
13096 /* Queue ID of the queue. */
13098 } __attribute__((packed));
13100 /* hwrm_queue_qcfg_output (size:128b/16B) */
13101 struct hwrm_queue_qcfg_output {
13102 /* The specific error status for the command. */
13103 uint16_t error_code;
13104 /* The HWRM command request type. */
13106 /* The sequence ID from the original command. */
13108 /* The length of the response data in number of bytes. */
13111 * This value is a the estimate packet length used in the
13114 uint32_t queue_len;
13115 /* This value is applicable to CoS queues only. */
13116 uint8_t service_profile;
13117 /* Lossy (best-effort) */
13118 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
13120 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
13121 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13122 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
13123 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
13124 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
13125 /* Information about queue configuration. */
13126 uint8_t queue_cfg_info;
13128 * If this flag is set to '1', then the queue is
13129 * configured asymmetrically on TX and RX sides.
13130 * If this flag is set to '0', then this queue is
13131 * configured symmetrically on TX and RX sides.
13133 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
13137 * This field is used in Output records to indicate that the output
13138 * is completely written to RAM. This field should be read as '1'
13139 * to indicate that the output has been completely written.
13140 * When writing a command completion or response to an internal processor,
13141 * the order of writes has to be such that this field is written last.
13144 } __attribute__((packed));
13146 /******************
13148 ******************/
13151 /* hwrm_queue_cfg_input (size:320b/40B) */
13152 struct hwrm_queue_cfg_input {
13153 /* The HWRM command request type. */
13156 * The completion ring to send the completion event on. This should
13157 * be the NQ ID returned from the `nq_alloc` HWRM command.
13159 uint16_t cmpl_ring;
13161 * The sequence ID is used by the driver for tracking multiple
13162 * commands. This ID is treated as opaque data by the firmware and
13163 * the value is returned in the `hwrm_resp_hdr` upon completion.
13167 * The target ID of the command:
13168 * * 0x0-0xFFF8 - The function ID
13169 * * 0xFFF8-0xFFFE - Reserved for internal processors
13172 uint16_t target_id;
13174 * A physical address pointer pointing to a host buffer that the
13175 * command's response data will be written. This can be either a host
13176 * physical address (HPA) or a guest physical address (GPA) and must
13177 * point to a physically contiguous block of memory.
13179 uint64_t resp_addr;
13182 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
13183 * This enumeration is used for resources that are similar for both
13184 * TX and RX paths of the chip.
13186 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
13187 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
13189 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13191 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13192 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
13193 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
13194 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
13195 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
13198 * This bit must be '1' for the dflt_len field to be
13201 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
13203 * This bit must be '1' for the service_profile field to be
13206 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
13207 /* Queue ID of queue that is to be configured by this function. */
13210 * This value is a the estimate packet length used in the
13212 * Set to 0xFF... (All Fs) to not adjust this value.
13215 /* This value is applicable to CoS queues only. */
13216 uint8_t service_profile;
13217 /* Lossy (best-effort) */
13218 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
13220 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
13221 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13222 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
13223 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
13224 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
13225 uint8_t unused_0[7];
13226 } __attribute__((packed));
13228 /* hwrm_queue_cfg_output (size:128b/16B) */
13229 struct hwrm_queue_cfg_output {
13230 /* The specific error status for the command. */
13231 uint16_t error_code;
13232 /* The HWRM command request type. */
13234 /* The sequence ID from the original command. */
13236 /* The length of the response data in number of bytes. */
13238 uint8_t unused_0[7];
13240 * This field is used in Output records to indicate that the output
13241 * is completely written to RAM. This field should be read as '1'
13242 * to indicate that the output has been completely written.
13243 * When writing a command completion or response to an internal processor,
13244 * the order of writes has to be such that this field is written last.
13247 } __attribute__((packed));
13249 /*****************************
13250 * hwrm_queue_pfcenable_qcfg *
13251 *****************************/
13254 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
13255 struct hwrm_queue_pfcenable_qcfg_input {
13256 /* The HWRM command request type. */
13259 * The completion ring to send the completion event on. This should
13260 * be the NQ ID returned from the `nq_alloc` HWRM command.
13262 uint16_t cmpl_ring;
13264 * The sequence ID is used by the driver for tracking multiple
13265 * commands. This ID is treated as opaque data by the firmware and
13266 * the value is returned in the `hwrm_resp_hdr` upon completion.
13270 * The target ID of the command:
13271 * * 0x0-0xFFF8 - The function ID
13272 * * 0xFFF8-0xFFFE - Reserved for internal processors
13275 uint16_t target_id;
13277 * A physical address pointer pointing to a host buffer that the
13278 * command's response data will be written. This can be either a host
13279 * physical address (HPA) or a guest physical address (GPA) and must
13280 * point to a physically contiguous block of memory.
13282 uint64_t resp_addr;
13284 * Port ID of port for which the table is being configured.
13285 * The HWRM needs to check whether this function is allowed
13286 * to configure pri2cos mapping on this port.
13289 uint8_t unused_0[6];
13290 } __attribute__((packed));
13292 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
13293 struct hwrm_queue_pfcenable_qcfg_output {
13294 /* The specific error status for the command. */
13295 uint16_t error_code;
13296 /* The HWRM command request type. */
13298 /* The sequence ID from the original command. */
13300 /* The length of the response data in number of bytes. */
13303 /* If set to 1, then PFC is enabled on PRI 0. */
13304 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
13306 /* If set to 1, then PFC is enabled on PRI 1. */
13307 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
13309 /* If set to 1, then PFC is enabled on PRI 2. */
13310 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
13312 /* If set to 1, then PFC is enabled on PRI 3. */
13313 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
13315 /* If set to 1, then PFC is enabled on PRI 4. */
13316 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
13318 /* If set to 1, then PFC is enabled on PRI 5. */
13319 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
13321 /* If set to 1, then PFC is enabled on PRI 6. */
13322 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
13324 /* If set to 1, then PFC is enabled on PRI 7. */
13325 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
13327 uint8_t unused_0[3];
13329 * This field is used in Output records to indicate that the output
13330 * is completely written to RAM. This field should be read as '1'
13331 * to indicate that the output has been completely written.
13332 * When writing a command completion or response to an internal processor,
13333 * the order of writes has to be such that this field is written last.
13336 } __attribute__((packed));
13338 /****************************
13339 * hwrm_queue_pfcenable_cfg *
13340 ****************************/
13343 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
13344 struct hwrm_queue_pfcenable_cfg_input {
13345 /* The HWRM command request type. */
13348 * The completion ring to send the completion event on. This should
13349 * be the NQ ID returned from the `nq_alloc` HWRM command.
13351 uint16_t cmpl_ring;
13353 * The sequence ID is used by the driver for tracking multiple
13354 * commands. This ID is treated as opaque data by the firmware and
13355 * the value is returned in the `hwrm_resp_hdr` upon completion.
13359 * The target ID of the command:
13360 * * 0x0-0xFFF8 - The function ID
13361 * * 0xFFF8-0xFFFE - Reserved for internal processors
13364 uint16_t target_id;
13366 * A physical address pointer pointing to a host buffer that the
13367 * command's response data will be written. This can be either a host
13368 * physical address (HPA) or a guest physical address (GPA) and must
13369 * point to a physically contiguous block of memory.
13371 uint64_t resp_addr;
13373 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
13374 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
13376 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
13377 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
13379 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
13380 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
13382 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
13383 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
13385 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
13386 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
13388 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
13389 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
13391 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
13392 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
13394 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
13395 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
13398 * Port ID of port for which the table is being configured.
13399 * The HWRM needs to check whether this function is allowed
13400 * to configure pri2cos mapping on this port.
13403 uint8_t unused_0[2];
13404 } __attribute__((packed));
13406 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
13407 struct hwrm_queue_pfcenable_cfg_output {
13408 /* The specific error status for the command. */
13409 uint16_t error_code;
13410 /* The HWRM command request type. */
13412 /* The sequence ID from the original command. */
13414 /* The length of the response data in number of bytes. */
13416 uint8_t unused_0[7];
13418 * This field is used in Output records to indicate that the output
13419 * is completely written to RAM. This field should be read as '1'
13420 * to indicate that the output has been completely written.
13421 * When writing a command completion or response to an internal processor,
13422 * the order of writes has to be such that this field is written last.
13425 } __attribute__((packed));
13427 /***************************
13428 * hwrm_queue_pri2cos_qcfg *
13429 ***************************/
13432 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
13433 struct hwrm_queue_pri2cos_qcfg_input {
13434 /* The HWRM command request type. */
13437 * The completion ring to send the completion event on. This should
13438 * be the NQ ID returned from the `nq_alloc` HWRM command.
13440 uint16_t cmpl_ring;
13442 * The sequence ID is used by the driver for tracking multiple
13443 * commands. This ID is treated as opaque data by the firmware and
13444 * the value is returned in the `hwrm_resp_hdr` upon completion.
13448 * The target ID of the command:
13449 * * 0x0-0xFFF8 - The function ID
13450 * * 0xFFF8-0xFFFE - Reserved for internal processors
13453 uint16_t target_id;
13455 * A physical address pointer pointing to a host buffer that the
13456 * command's response data will be written. This can be either a host
13457 * physical address (HPA) or a guest physical address (GPA) and must
13458 * point to a physically contiguous block of memory.
13460 uint64_t resp_addr;
13463 * Enumeration denoting the RX, TX type of the resource.
13464 * This enumeration is used for resources that are similar for both
13465 * TX and RX paths of the chip.
13467 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
13469 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13471 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13472 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
13473 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
13475 * When this bit is set to '0', the query is
13476 * for VLAN PRI field in tunnel headers.
13477 * When this bit is set to '1', the query is
13478 * for VLAN PRI field in inner packet headers.
13480 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
13482 * Port ID of port for which the table is being configured.
13483 * The HWRM needs to check whether this function is allowed
13484 * to configure pri2cos mapping on this port.
13487 uint8_t unused_0[3];
13488 } __attribute__((packed));
13490 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
13491 struct hwrm_queue_pri2cos_qcfg_output {
13492 /* The specific error status for the command. */
13493 uint16_t error_code;
13494 /* The HWRM command request type. */
13496 /* The sequence ID from the original command. */
13498 /* The length of the response data in number of bytes. */
13501 * CoS Queue assigned to priority 0. This value can only
13502 * be changed before traffic has started.
13503 * A value of 0xff indicates that no CoS queue is assigned to the
13504 * specified priority.
13506 uint8_t pri0_cos_queue_id;
13508 * CoS Queue assigned to priority 1. This value can only
13509 * be changed before traffic has started.
13510 * A value of 0xff indicates that no CoS queue is assigned to the
13511 * specified priority.
13513 uint8_t pri1_cos_queue_id;
13515 * CoS Queue assigned to priority 2 This value can only
13516 * be changed before traffic has started.
13517 * A value of 0xff indicates that no CoS queue is assigned to the
13518 * specified priority.
13520 uint8_t pri2_cos_queue_id;
13522 * CoS Queue assigned to priority 3. This value can only
13523 * be changed before traffic has started.
13524 * A value of 0xff indicates that no CoS queue is assigned to the
13525 * specified priority.
13527 uint8_t pri3_cos_queue_id;
13529 * CoS Queue assigned to priority 4. This value can only
13530 * be changed before traffic has started.
13531 * A value of 0xff indicates that no CoS queue is assigned to the
13532 * specified priority.
13534 uint8_t pri4_cos_queue_id;
13536 * CoS Queue assigned to priority 5. This value can only
13537 * be changed before traffic has started.
13538 * A value of 0xff indicates that no CoS queue is assigned to the
13539 * specified priority.
13541 uint8_t pri5_cos_queue_id;
13543 * CoS Queue assigned to priority 6. This value can only
13544 * be changed before traffic has started.
13545 * A value of 0xff indicates that no CoS queue is assigned to the
13546 * specified priority.
13548 uint8_t pri6_cos_queue_id;
13550 * CoS Queue assigned to priority 7. This value can only
13551 * be changed before traffic has started.
13552 * A value of 0xff indicates that no CoS queue is assigned to the
13553 * specified priority.
13555 uint8_t pri7_cos_queue_id;
13556 /* Information about queue configuration. */
13557 uint8_t queue_cfg_info;
13559 * If this flag is set to '1', then the PRI to CoS
13560 * configuration is asymmetric on TX and RX sides.
13561 * If this flag is set to '0', then PRI to CoS configuration
13562 * is symmetric on TX and RX sides.
13564 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
13566 uint8_t unused_0[6];
13568 * This field is used in Output records to indicate that the output
13569 * is completely written to RAM. This field should be read as '1'
13570 * to indicate that the output has been completely written.
13571 * When writing a command completion or response to an internal processor,
13572 * the order of writes has to be such that this field is written last.
13575 } __attribute__((packed));
13577 /**************************
13578 * hwrm_queue_pri2cos_cfg *
13579 **************************/
13582 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
13583 struct hwrm_queue_pri2cos_cfg_input {
13584 /* The HWRM command request type. */
13587 * The completion ring to send the completion event on. This should
13588 * be the NQ ID returned from the `nq_alloc` HWRM command.
13590 uint16_t cmpl_ring;
13592 * The sequence ID is used by the driver for tracking multiple
13593 * commands. This ID is treated as opaque data by the firmware and
13594 * the value is returned in the `hwrm_resp_hdr` upon completion.
13598 * The target ID of the command:
13599 * * 0x0-0xFFF8 - The function ID
13600 * * 0xFFF8-0xFFFE - Reserved for internal processors
13603 uint16_t target_id;
13605 * A physical address pointer pointing to a host buffer that the
13606 * command's response data will be written. This can be either a host
13607 * physical address (HPA) or a guest physical address (GPA) and must
13608 * point to a physically contiguous block of memory.
13610 uint64_t resp_addr;
13613 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
13614 * This enumeration is used for resources that are similar for both
13615 * TX and RX paths of the chip.
13617 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
13618 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
13620 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13622 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13623 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
13624 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
13625 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
13626 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
13628 * When this bit is set to '0', the mapping is requested
13629 * for VLAN PRI field in tunnel headers.
13630 * When this bit is set to '1', the mapping is requested
13631 * for VLAN PRI field in inner packet headers.
13633 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
13636 * This bit must be '1' for the pri0_cos_queue_id field to be
13639 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
13642 * This bit must be '1' for the pri1_cos_queue_id field to be
13645 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
13648 * This bit must be '1' for the pri2_cos_queue_id field to be
13651 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
13654 * This bit must be '1' for the pri3_cos_queue_id field to be
13657 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
13660 * This bit must be '1' for the pri4_cos_queue_id field to be
13663 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
13666 * This bit must be '1' for the pri5_cos_queue_id field to be
13669 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
13672 * This bit must be '1' for the pri6_cos_queue_id field to be
13675 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
13678 * This bit must be '1' for the pri7_cos_queue_id field to be
13681 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
13684 * Port ID of port for which the table is being configured.
13685 * The HWRM needs to check whether this function is allowed
13686 * to configure pri2cos mapping on this port.
13690 * CoS Queue assigned to priority 0. This value can only
13691 * be changed before traffic has started.
13693 uint8_t pri0_cos_queue_id;
13695 * CoS Queue assigned to priority 1. This value can only
13696 * be changed before traffic has started.
13698 uint8_t pri1_cos_queue_id;
13700 * CoS Queue assigned to priority 2 This value can only
13701 * be changed before traffic has started.
13703 uint8_t pri2_cos_queue_id;
13705 * CoS Queue assigned to priority 3. This value can only
13706 * be changed before traffic has started.
13708 uint8_t pri3_cos_queue_id;
13710 * CoS Queue assigned to priority 4. This value can only
13711 * be changed before traffic has started.
13713 uint8_t pri4_cos_queue_id;
13715 * CoS Queue assigned to priority 5. This value can only
13716 * be changed before traffic has started.
13718 uint8_t pri5_cos_queue_id;
13720 * CoS Queue assigned to priority 6. This value can only
13721 * be changed before traffic has started.
13723 uint8_t pri6_cos_queue_id;
13725 * CoS Queue assigned to priority 7. This value can only
13726 * be changed before traffic has started.
13728 uint8_t pri7_cos_queue_id;
13729 uint8_t unused_0[7];
13730 } __attribute__((packed));
13732 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
13733 struct hwrm_queue_pri2cos_cfg_output {
13734 /* The specific error status for the command. */
13735 uint16_t error_code;
13736 /* The HWRM command request type. */
13738 /* The sequence ID from the original command. */
13740 /* The length of the response data in number of bytes. */
13742 uint8_t unused_0[7];
13744 * This field is used in Output records to indicate that the output
13745 * is completely written to RAM. This field should be read as '1'
13746 * to indicate that the output has been completely written.
13747 * When writing a command completion or response to an internal processor,
13748 * the order of writes has to be such that this field is written last.
13751 } __attribute__((packed));
13753 /**************************
13754 * hwrm_queue_cos2bw_qcfg *
13755 **************************/
13758 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
13759 struct hwrm_queue_cos2bw_qcfg_input {
13760 /* The HWRM command request type. */
13763 * The completion ring to send the completion event on. This should
13764 * be the NQ ID returned from the `nq_alloc` HWRM command.
13766 uint16_t cmpl_ring;
13768 * The sequence ID is used by the driver for tracking multiple
13769 * commands. This ID is treated as opaque data by the firmware and
13770 * the value is returned in the `hwrm_resp_hdr` upon completion.
13774 * The target ID of the command:
13775 * * 0x0-0xFFF8 - The function ID
13776 * * 0xFFF8-0xFFFE - Reserved for internal processors
13779 uint16_t target_id;
13781 * A physical address pointer pointing to a host buffer that the
13782 * command's response data will be written. This can be either a host
13783 * physical address (HPA) or a guest physical address (GPA) and must
13784 * point to a physically contiguous block of memory.
13786 uint64_t resp_addr;
13788 * Port ID of port for which the table is being configured.
13789 * The HWRM needs to check whether this function is allowed
13790 * to configure TC BW assignment on this port.
13793 uint8_t unused_0[6];
13794 } __attribute__((packed));
13796 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
13797 struct hwrm_queue_cos2bw_qcfg_output {
13798 /* The specific error status for the command. */
13799 uint16_t error_code;
13800 /* The HWRM command request type. */
13802 /* The sequence ID from the original command. */
13804 /* The length of the response data in number of bytes. */
13806 /* ID of CoS Queue 0. */
13811 * Minimum BW allocated to CoS Queue.
13812 * The HWRM will translate this value into byte counter and
13813 * time interval used for this COS inside the device.
13815 uint32_t queue_id0_min_bw;
13816 /* The bandwidth value. */
13817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
13818 UINT32_C(0xfffffff)
13819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
13821 /* The granularity of the value (bits or bytes). */
13822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
13823 UINT32_C(0x10000000)
13824 /* Value is in bits. */
13825 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
13826 (UINT32_C(0x0) << 28)
13827 /* Value is in bytes. */
13828 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
13829 (UINT32_C(0x1) << 28)
13830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
13831 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
13832 /* bw_value_unit is 3 b */
13833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
13834 UINT32_C(0xe0000000)
13835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
13837 /* Value is in Mb or MB (base 10). */
13838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
13839 (UINT32_C(0x0) << 29)
13840 /* Value is in Kb or KB (base 10). */
13841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
13842 (UINT32_C(0x2) << 29)
13843 /* Value is in bits or bytes. */
13844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
13845 (UINT32_C(0x4) << 29)
13846 /* Value is in Gb or GB (base 10). */
13847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
13848 (UINT32_C(0x6) << 29)
13849 /* Value is in 1/100th of a percentage of total bandwidth. */
13850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13851 (UINT32_C(0x1) << 29)
13853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
13854 (UINT32_C(0x7) << 29)
13855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
13856 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
13858 * Maximum BW allocated to CoS Queue.
13859 * The HWRM will translate this value into byte counter and
13860 * time interval used for this COS inside the device.
13862 uint32_t queue_id0_max_bw;
13863 /* The bandwidth value. */
13864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
13865 UINT32_C(0xfffffff)
13866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
13868 /* The granularity of the value (bits or bytes). */
13869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
13870 UINT32_C(0x10000000)
13871 /* Value is in bits. */
13872 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
13873 (UINT32_C(0x0) << 28)
13874 /* Value is in bytes. */
13875 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
13876 (UINT32_C(0x1) << 28)
13877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
13878 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
13879 /* bw_value_unit is 3 b */
13880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
13881 UINT32_C(0xe0000000)
13882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
13884 /* Value is in Mb or MB (base 10). */
13885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
13886 (UINT32_C(0x0) << 29)
13887 /* Value is in Kb or KB (base 10). */
13888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
13889 (UINT32_C(0x2) << 29)
13890 /* Value is in bits or bytes. */
13891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
13892 (UINT32_C(0x4) << 29)
13893 /* Value is in Gb or GB (base 10). */
13894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
13895 (UINT32_C(0x6) << 29)
13896 /* Value is in 1/100th of a percentage of total bandwidth. */
13897 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
13898 (UINT32_C(0x1) << 29)
13900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
13901 (UINT32_C(0x7) << 29)
13902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
13903 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
13904 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13905 uint8_t queue_id0_tsa_assign;
13906 /* Strict Priority */
13907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
13909 /* Enhanced Transmission Selection */
13910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
13913 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
13916 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
13919 * Priority level for strict priority. Valid only when the
13920 * tsa_assign is 0 - Strict Priority (SP)
13921 * 0..7 - Valid values.
13922 * 8..255 - Reserved.
13924 uint8_t queue_id0_pri_lvl;
13926 * Weight used to allocate remaining BW for this COS after
13927 * servicing guaranteed bandwidths for all COS.
13929 uint8_t queue_id0_bw_weight;
13930 /* ID of CoS Queue 1. */
13933 * Minimum BW allocated to CoS Queue.
13934 * The HWRM will translate this value into byte counter and
13935 * time interval used for this COS inside the device.
13937 uint32_t queue_id1_min_bw;
13938 /* The bandwidth value. */
13939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
13940 UINT32_C(0xfffffff)
13941 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
13943 /* The granularity of the value (bits or bytes). */
13944 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
13945 UINT32_C(0x10000000)
13946 /* Value is in bits. */
13947 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
13948 (UINT32_C(0x0) << 28)
13949 /* Value is in bytes. */
13950 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
13951 (UINT32_C(0x1) << 28)
13952 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
13953 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
13954 /* bw_value_unit is 3 b */
13955 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
13956 UINT32_C(0xe0000000)
13957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
13959 /* Value is in Mb or MB (base 10). */
13960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
13961 (UINT32_C(0x0) << 29)
13962 /* Value is in Kb or KB (base 10). */
13963 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
13964 (UINT32_C(0x2) << 29)
13965 /* Value is in bits or bytes. */
13966 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
13967 (UINT32_C(0x4) << 29)
13968 /* Value is in Gb or GB (base 10). */
13969 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
13970 (UINT32_C(0x6) << 29)
13971 /* Value is in 1/100th of a percentage of total bandwidth. */
13972 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
13973 (UINT32_C(0x1) << 29)
13975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
13976 (UINT32_C(0x7) << 29)
13977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
13978 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
13980 * Maximum BW allocated to CoS queue.
13981 * The HWRM will translate this value into byte counter and
13982 * time interval used for this COS inside the device.
13984 uint32_t queue_id1_max_bw;
13985 /* The bandwidth value. */
13986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
13987 UINT32_C(0xfffffff)
13988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
13990 /* The granularity of the value (bits or bytes). */
13991 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
13992 UINT32_C(0x10000000)
13993 /* Value is in bits. */
13994 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
13995 (UINT32_C(0x0) << 28)
13996 /* Value is in bytes. */
13997 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
13998 (UINT32_C(0x1) << 28)
13999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
14000 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
14001 /* bw_value_unit is 3 b */
14002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
14003 UINT32_C(0xe0000000)
14004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
14006 /* Value is in Mb or MB (base 10). */
14007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
14008 (UINT32_C(0x0) << 29)
14009 /* Value is in Kb or KB (base 10). */
14010 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
14011 (UINT32_C(0x2) << 29)
14012 /* Value is in bits or bytes. */
14013 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
14014 (UINT32_C(0x4) << 29)
14015 /* Value is in Gb or GB (base 10). */
14016 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
14017 (UINT32_C(0x6) << 29)
14018 /* Value is in 1/100th of a percentage of total bandwidth. */
14019 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14020 (UINT32_C(0x1) << 29)
14022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
14023 (UINT32_C(0x7) << 29)
14024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
14025 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
14026 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14027 uint8_t queue_id1_tsa_assign;
14028 /* Strict Priority */
14029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
14031 /* Enhanced Transmission Selection */
14032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
14035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
14038 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
14041 * Priority level for strict priority. Valid only when the
14042 * tsa_assign is 0 - Strict Priority (SP)
14043 * 0..7 - Valid values.
14044 * 8..255 - Reserved.
14046 uint8_t queue_id1_pri_lvl;
14048 * Weight used to allocate remaining BW for this COS after
14049 * servicing guaranteed bandwidths for all COS.
14051 uint8_t queue_id1_bw_weight;
14052 /* ID of CoS Queue 2. */
14055 * Minimum BW allocated to CoS Queue.
14056 * The HWRM will translate this value into byte counter and
14057 * time interval used for this COS inside the device.
14059 uint32_t queue_id2_min_bw;
14060 /* The bandwidth value. */
14061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
14062 UINT32_C(0xfffffff)
14063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
14065 /* The granularity of the value (bits or bytes). */
14066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
14067 UINT32_C(0x10000000)
14068 /* Value is in bits. */
14069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
14070 (UINT32_C(0x0) << 28)
14071 /* Value is in bytes. */
14072 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
14073 (UINT32_C(0x1) << 28)
14074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
14075 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
14076 /* bw_value_unit is 3 b */
14077 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
14078 UINT32_C(0xe0000000)
14079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
14081 /* Value is in Mb or MB (base 10). */
14082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
14083 (UINT32_C(0x0) << 29)
14084 /* Value is in Kb or KB (base 10). */
14085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
14086 (UINT32_C(0x2) << 29)
14087 /* Value is in bits or bytes. */
14088 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
14089 (UINT32_C(0x4) << 29)
14090 /* Value is in Gb or GB (base 10). */
14091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
14092 (UINT32_C(0x6) << 29)
14093 /* Value is in 1/100th of a percentage of total bandwidth. */
14094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14095 (UINT32_C(0x1) << 29)
14097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
14098 (UINT32_C(0x7) << 29)
14099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
14100 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
14102 * Maximum BW allocated to CoS queue.
14103 * The HWRM will translate this value into byte counter and
14104 * time interval used for this COS inside the device.
14106 uint32_t queue_id2_max_bw;
14107 /* The bandwidth value. */
14108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
14109 UINT32_C(0xfffffff)
14110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
14112 /* The granularity of the value (bits or bytes). */
14113 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
14114 UINT32_C(0x10000000)
14115 /* Value is in bits. */
14116 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
14117 (UINT32_C(0x0) << 28)
14118 /* Value is in bytes. */
14119 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
14120 (UINT32_C(0x1) << 28)
14121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
14122 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
14123 /* bw_value_unit is 3 b */
14124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
14125 UINT32_C(0xe0000000)
14126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
14128 /* Value is in Mb or MB (base 10). */
14129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
14130 (UINT32_C(0x0) << 29)
14131 /* Value is in Kb or KB (base 10). */
14132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
14133 (UINT32_C(0x2) << 29)
14134 /* Value is in bits or bytes. */
14135 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
14136 (UINT32_C(0x4) << 29)
14137 /* Value is in Gb or GB (base 10). */
14138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
14139 (UINT32_C(0x6) << 29)
14140 /* Value is in 1/100th of a percentage of total bandwidth. */
14141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14142 (UINT32_C(0x1) << 29)
14144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
14145 (UINT32_C(0x7) << 29)
14146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
14147 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
14148 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14149 uint8_t queue_id2_tsa_assign;
14150 /* Strict Priority */
14151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
14153 /* Enhanced Transmission Selection */
14154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
14157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
14160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
14163 * Priority level for strict priority. Valid only when the
14164 * tsa_assign is 0 - Strict Priority (SP)
14165 * 0..7 - Valid values.
14166 * 8..255 - Reserved.
14168 uint8_t queue_id2_pri_lvl;
14170 * Weight used to allocate remaining BW for this COS after
14171 * servicing guaranteed bandwidths for all COS.
14173 uint8_t queue_id2_bw_weight;
14174 /* ID of CoS Queue 3. */
14177 * Minimum BW allocated to CoS Queue.
14178 * The HWRM will translate this value into byte counter and
14179 * time interval used for this COS inside the device.
14181 uint32_t queue_id3_min_bw;
14182 /* The bandwidth value. */
14183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
14184 UINT32_C(0xfffffff)
14185 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
14187 /* The granularity of the value (bits or bytes). */
14188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
14189 UINT32_C(0x10000000)
14190 /* Value is in bits. */
14191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
14192 (UINT32_C(0x0) << 28)
14193 /* Value is in bytes. */
14194 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
14195 (UINT32_C(0x1) << 28)
14196 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
14197 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
14198 /* bw_value_unit is 3 b */
14199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
14200 UINT32_C(0xe0000000)
14201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
14203 /* Value is in Mb or MB (base 10). */
14204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
14205 (UINT32_C(0x0) << 29)
14206 /* Value is in Kb or KB (base 10). */
14207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
14208 (UINT32_C(0x2) << 29)
14209 /* Value is in bits or bytes. */
14210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
14211 (UINT32_C(0x4) << 29)
14212 /* Value is in Gb or GB (base 10). */
14213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
14214 (UINT32_C(0x6) << 29)
14215 /* Value is in 1/100th of a percentage of total bandwidth. */
14216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14217 (UINT32_C(0x1) << 29)
14219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
14220 (UINT32_C(0x7) << 29)
14221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
14222 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
14224 * Maximum BW allocated to CoS queue.
14225 * The HWRM will translate this value into byte counter and
14226 * time interval used for this COS inside the device.
14228 uint32_t queue_id3_max_bw;
14229 /* The bandwidth value. */
14230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
14231 UINT32_C(0xfffffff)
14232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
14234 /* The granularity of the value (bits or bytes). */
14235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
14236 UINT32_C(0x10000000)
14237 /* Value is in bits. */
14238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
14239 (UINT32_C(0x0) << 28)
14240 /* Value is in bytes. */
14241 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
14242 (UINT32_C(0x1) << 28)
14243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
14244 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
14245 /* bw_value_unit is 3 b */
14246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
14247 UINT32_C(0xe0000000)
14248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
14250 /* Value is in Mb or MB (base 10). */
14251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
14252 (UINT32_C(0x0) << 29)
14253 /* Value is in Kb or KB (base 10). */
14254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
14255 (UINT32_C(0x2) << 29)
14256 /* Value is in bits or bytes. */
14257 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
14258 (UINT32_C(0x4) << 29)
14259 /* Value is in Gb or GB (base 10). */
14260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
14261 (UINT32_C(0x6) << 29)
14262 /* Value is in 1/100th of a percentage of total bandwidth. */
14263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14264 (UINT32_C(0x1) << 29)
14266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
14267 (UINT32_C(0x7) << 29)
14268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
14269 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
14270 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14271 uint8_t queue_id3_tsa_assign;
14272 /* Strict Priority */
14273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
14275 /* Enhanced Transmission Selection */
14276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
14279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
14282 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
14285 * Priority level for strict priority. Valid only when the
14286 * tsa_assign is 0 - Strict Priority (SP)
14287 * 0..7 - Valid values.
14288 * 8..255 - Reserved.
14290 uint8_t queue_id3_pri_lvl;
14292 * Weight used to allocate remaining BW for this COS after
14293 * servicing guaranteed bandwidths for all COS.
14295 uint8_t queue_id3_bw_weight;
14296 /* ID of CoS Queue 4. */
14299 * Minimum BW allocated to CoS Queue.
14300 * The HWRM will translate this value into byte counter and
14301 * time interval used for this COS inside the device.
14303 uint32_t queue_id4_min_bw;
14304 /* The bandwidth value. */
14305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
14306 UINT32_C(0xfffffff)
14307 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
14309 /* The granularity of the value (bits or bytes). */
14310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
14311 UINT32_C(0x10000000)
14312 /* Value is in bits. */
14313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
14314 (UINT32_C(0x0) << 28)
14315 /* Value is in bytes. */
14316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
14317 (UINT32_C(0x1) << 28)
14318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
14319 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
14320 /* bw_value_unit is 3 b */
14321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
14322 UINT32_C(0xe0000000)
14323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
14325 /* Value is in Mb or MB (base 10). */
14326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
14327 (UINT32_C(0x0) << 29)
14328 /* Value is in Kb or KB (base 10). */
14329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
14330 (UINT32_C(0x2) << 29)
14331 /* Value is in bits or bytes. */
14332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
14333 (UINT32_C(0x4) << 29)
14334 /* Value is in Gb or GB (base 10). */
14335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
14336 (UINT32_C(0x6) << 29)
14337 /* Value is in 1/100th of a percentage of total bandwidth. */
14338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14339 (UINT32_C(0x1) << 29)
14341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
14342 (UINT32_C(0x7) << 29)
14343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
14344 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
14346 * Maximum BW allocated to CoS queue.
14347 * The HWRM will translate this value into byte counter and
14348 * time interval used for this COS inside the device.
14350 uint32_t queue_id4_max_bw;
14351 /* The bandwidth value. */
14352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
14353 UINT32_C(0xfffffff)
14354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
14356 /* The granularity of the value (bits or bytes). */
14357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
14358 UINT32_C(0x10000000)
14359 /* Value is in bits. */
14360 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
14361 (UINT32_C(0x0) << 28)
14362 /* Value is in bytes. */
14363 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
14364 (UINT32_C(0x1) << 28)
14365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
14366 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
14367 /* bw_value_unit is 3 b */
14368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
14369 UINT32_C(0xe0000000)
14370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
14372 /* Value is in Mb or MB (base 10). */
14373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
14374 (UINT32_C(0x0) << 29)
14375 /* Value is in Kb or KB (base 10). */
14376 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
14377 (UINT32_C(0x2) << 29)
14378 /* Value is in bits or bytes. */
14379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
14380 (UINT32_C(0x4) << 29)
14381 /* Value is in Gb or GB (base 10). */
14382 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
14383 (UINT32_C(0x6) << 29)
14384 /* Value is in 1/100th of a percentage of total bandwidth. */
14385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14386 (UINT32_C(0x1) << 29)
14388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
14389 (UINT32_C(0x7) << 29)
14390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
14391 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
14392 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14393 uint8_t queue_id4_tsa_assign;
14394 /* Strict Priority */
14395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
14397 /* Enhanced Transmission Selection */
14398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
14401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
14404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
14407 * Priority level for strict priority. Valid only when the
14408 * tsa_assign is 0 - Strict Priority (SP)
14409 * 0..7 - Valid values.
14410 * 8..255 - Reserved.
14412 uint8_t queue_id4_pri_lvl;
14414 * Weight used to allocate remaining BW for this COS after
14415 * servicing guaranteed bandwidths for all COS.
14417 uint8_t queue_id4_bw_weight;
14418 /* ID of CoS Queue 5. */
14421 * Minimum BW allocated to CoS Queue.
14422 * The HWRM will translate this value into byte counter and
14423 * time interval used for this COS inside the device.
14425 uint32_t queue_id5_min_bw;
14426 /* The bandwidth value. */
14427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
14428 UINT32_C(0xfffffff)
14429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
14431 /* The granularity of the value (bits or bytes). */
14432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
14433 UINT32_C(0x10000000)
14434 /* Value is in bits. */
14435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
14436 (UINT32_C(0x0) << 28)
14437 /* Value is in bytes. */
14438 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
14439 (UINT32_C(0x1) << 28)
14440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
14441 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
14442 /* bw_value_unit is 3 b */
14443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
14444 UINT32_C(0xe0000000)
14445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
14447 /* Value is in Mb or MB (base 10). */
14448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
14449 (UINT32_C(0x0) << 29)
14450 /* Value is in Kb or KB (base 10). */
14451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
14452 (UINT32_C(0x2) << 29)
14453 /* Value is in bits or bytes. */
14454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
14455 (UINT32_C(0x4) << 29)
14456 /* Value is in Gb or GB (base 10). */
14457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
14458 (UINT32_C(0x6) << 29)
14459 /* Value is in 1/100th of a percentage of total bandwidth. */
14460 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14461 (UINT32_C(0x1) << 29)
14463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
14464 (UINT32_C(0x7) << 29)
14465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
14466 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
14468 * Maximum BW allocated to CoS queue.
14469 * The HWRM will translate this value into byte counter and
14470 * time interval used for this COS inside the device.
14472 uint32_t queue_id5_max_bw;
14473 /* The bandwidth value. */
14474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
14475 UINT32_C(0xfffffff)
14476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
14478 /* The granularity of the value (bits or bytes). */
14479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
14480 UINT32_C(0x10000000)
14481 /* Value is in bits. */
14482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
14483 (UINT32_C(0x0) << 28)
14484 /* Value is in bytes. */
14485 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
14486 (UINT32_C(0x1) << 28)
14487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
14488 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
14489 /* bw_value_unit is 3 b */
14490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
14491 UINT32_C(0xe0000000)
14492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
14494 /* Value is in Mb or MB (base 10). */
14495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
14496 (UINT32_C(0x0) << 29)
14497 /* Value is in Kb or KB (base 10). */
14498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
14499 (UINT32_C(0x2) << 29)
14500 /* Value is in bits or bytes. */
14501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
14502 (UINT32_C(0x4) << 29)
14503 /* Value is in Gb or GB (base 10). */
14504 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
14505 (UINT32_C(0x6) << 29)
14506 /* Value is in 1/100th of a percentage of total bandwidth. */
14507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14508 (UINT32_C(0x1) << 29)
14510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
14511 (UINT32_C(0x7) << 29)
14512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
14513 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
14514 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14515 uint8_t queue_id5_tsa_assign;
14516 /* Strict Priority */
14517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
14519 /* Enhanced Transmission Selection */
14520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
14523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
14526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
14529 * Priority level for strict priority. Valid only when the
14530 * tsa_assign is 0 - Strict Priority (SP)
14531 * 0..7 - Valid values.
14532 * 8..255 - Reserved.
14534 uint8_t queue_id5_pri_lvl;
14536 * Weight used to allocate remaining BW for this COS after
14537 * servicing guaranteed bandwidths for all COS.
14539 uint8_t queue_id5_bw_weight;
14540 /* ID of CoS Queue 6. */
14543 * Minimum BW allocated to CoS Queue.
14544 * The HWRM will translate this value into byte counter and
14545 * time interval used for this COS inside the device.
14547 uint32_t queue_id6_min_bw;
14548 /* The bandwidth value. */
14549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
14550 UINT32_C(0xfffffff)
14551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
14553 /* The granularity of the value (bits or bytes). */
14554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
14555 UINT32_C(0x10000000)
14556 /* Value is in bits. */
14557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
14558 (UINT32_C(0x0) << 28)
14559 /* Value is in bytes. */
14560 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
14561 (UINT32_C(0x1) << 28)
14562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
14563 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
14564 /* bw_value_unit is 3 b */
14565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
14566 UINT32_C(0xe0000000)
14567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
14569 /* Value is in Mb or MB (base 10). */
14570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
14571 (UINT32_C(0x0) << 29)
14572 /* Value is in Kb or KB (base 10). */
14573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
14574 (UINT32_C(0x2) << 29)
14575 /* Value is in bits or bytes. */
14576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
14577 (UINT32_C(0x4) << 29)
14578 /* Value is in Gb or GB (base 10). */
14579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
14580 (UINT32_C(0x6) << 29)
14581 /* Value is in 1/100th of a percentage of total bandwidth. */
14582 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14583 (UINT32_C(0x1) << 29)
14585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
14586 (UINT32_C(0x7) << 29)
14587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
14588 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
14590 * Maximum BW allocated to CoS queue.
14591 * The HWRM will translate this value into byte counter and
14592 * time interval used for this COS inside the device.
14594 uint32_t queue_id6_max_bw;
14595 /* The bandwidth value. */
14596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
14597 UINT32_C(0xfffffff)
14598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
14600 /* The granularity of the value (bits or bytes). */
14601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
14602 UINT32_C(0x10000000)
14603 /* Value is in bits. */
14604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
14605 (UINT32_C(0x0) << 28)
14606 /* Value is in bytes. */
14607 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
14608 (UINT32_C(0x1) << 28)
14609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
14610 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
14611 /* bw_value_unit is 3 b */
14612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
14613 UINT32_C(0xe0000000)
14614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
14616 /* Value is in Mb or MB (base 10). */
14617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
14618 (UINT32_C(0x0) << 29)
14619 /* Value is in Kb or KB (base 10). */
14620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
14621 (UINT32_C(0x2) << 29)
14622 /* Value is in bits or bytes. */
14623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
14624 (UINT32_C(0x4) << 29)
14625 /* Value is in Gb or GB (base 10). */
14626 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
14627 (UINT32_C(0x6) << 29)
14628 /* Value is in 1/100th of a percentage of total bandwidth. */
14629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14630 (UINT32_C(0x1) << 29)
14632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
14633 (UINT32_C(0x7) << 29)
14634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
14635 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
14636 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14637 uint8_t queue_id6_tsa_assign;
14638 /* Strict Priority */
14639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
14641 /* Enhanced Transmission Selection */
14642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
14645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
14648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
14651 * Priority level for strict priority. Valid only when the
14652 * tsa_assign is 0 - Strict Priority (SP)
14653 * 0..7 - Valid values.
14654 * 8..255 - Reserved.
14656 uint8_t queue_id6_pri_lvl;
14658 * Weight used to allocate remaining BW for this COS after
14659 * servicing guaranteed bandwidths for all COS.
14661 uint8_t queue_id6_bw_weight;
14662 /* ID of CoS Queue 7. */
14665 * Minimum BW allocated to CoS Queue.
14666 * The HWRM will translate this value into byte counter and
14667 * time interval used for this COS inside the device.
14669 uint32_t queue_id7_min_bw;
14670 /* The bandwidth value. */
14671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
14672 UINT32_C(0xfffffff)
14673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
14675 /* The granularity of the value (bits or bytes). */
14676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
14677 UINT32_C(0x10000000)
14678 /* Value is in bits. */
14679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
14680 (UINT32_C(0x0) << 28)
14681 /* Value is in bytes. */
14682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
14683 (UINT32_C(0x1) << 28)
14684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
14685 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
14686 /* bw_value_unit is 3 b */
14687 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
14688 UINT32_C(0xe0000000)
14689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
14691 /* Value is in Mb or MB (base 10). */
14692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
14693 (UINT32_C(0x0) << 29)
14694 /* Value is in Kb or KB (base 10). */
14695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
14696 (UINT32_C(0x2) << 29)
14697 /* Value is in bits or bytes. */
14698 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
14699 (UINT32_C(0x4) << 29)
14700 /* Value is in Gb or GB (base 10). */
14701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
14702 (UINT32_C(0x6) << 29)
14703 /* Value is in 1/100th of a percentage of total bandwidth. */
14704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14705 (UINT32_C(0x1) << 29)
14707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
14708 (UINT32_C(0x7) << 29)
14709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
14710 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
14712 * Maximum BW allocated to CoS queue.
14713 * The HWRM will translate this value into byte counter and
14714 * time interval used for this COS inside the device.
14716 uint32_t queue_id7_max_bw;
14717 /* The bandwidth value. */
14718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
14719 UINT32_C(0xfffffff)
14720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
14722 /* The granularity of the value (bits or bytes). */
14723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
14724 UINT32_C(0x10000000)
14725 /* Value is in bits. */
14726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
14727 (UINT32_C(0x0) << 28)
14728 /* Value is in bytes. */
14729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
14730 (UINT32_C(0x1) << 28)
14731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
14732 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
14733 /* bw_value_unit is 3 b */
14734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
14735 UINT32_C(0xe0000000)
14736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
14738 /* Value is in Mb or MB (base 10). */
14739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
14740 (UINT32_C(0x0) << 29)
14741 /* Value is in Kb or KB (base 10). */
14742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
14743 (UINT32_C(0x2) << 29)
14744 /* Value is in bits or bytes. */
14745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
14746 (UINT32_C(0x4) << 29)
14747 /* Value is in Gb or GB (base 10). */
14748 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
14749 (UINT32_C(0x6) << 29)
14750 /* Value is in 1/100th of a percentage of total bandwidth. */
14751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14752 (UINT32_C(0x1) << 29)
14754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
14755 (UINT32_C(0x7) << 29)
14756 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
14757 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
14758 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14759 uint8_t queue_id7_tsa_assign;
14760 /* Strict Priority */
14761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
14763 /* Enhanced Transmission Selection */
14764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
14767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
14770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
14773 * Priority level for strict priority. Valid only when the
14774 * tsa_assign is 0 - Strict Priority (SP)
14775 * 0..7 - Valid values.
14776 * 8..255 - Reserved.
14778 uint8_t queue_id7_pri_lvl;
14780 * Weight used to allocate remaining BW for this COS after
14781 * servicing guaranteed bandwidths for all COS.
14783 uint8_t queue_id7_bw_weight;
14784 uint8_t unused_2[4];
14786 * This field is used in Output records to indicate that the output
14787 * is completely written to RAM. This field should be read as '1'
14788 * to indicate that the output has been completely written.
14789 * When writing a command completion or response to an internal processor,
14790 * the order of writes has to be such that this field is written last.
14793 } __attribute__((packed));
14795 /*************************
14796 * hwrm_queue_cos2bw_cfg *
14797 *************************/
14800 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
14801 struct hwrm_queue_cos2bw_cfg_input {
14802 /* The HWRM command request type. */
14805 * The completion ring to send the completion event on. This should
14806 * be the NQ ID returned from the `nq_alloc` HWRM command.
14808 uint16_t cmpl_ring;
14810 * The sequence ID is used by the driver for tracking multiple
14811 * commands. This ID is treated as opaque data by the firmware and
14812 * the value is returned in the `hwrm_resp_hdr` upon completion.
14816 * The target ID of the command:
14817 * * 0x0-0xFFF8 - The function ID
14818 * * 0xFFF8-0xFFFE - Reserved for internal processors
14821 uint16_t target_id;
14823 * A physical address pointer pointing to a host buffer that the
14824 * command's response data will be written. This can be either a host
14825 * physical address (HPA) or a guest physical address (GPA) and must
14826 * point to a physically contiguous block of memory.
14828 uint64_t resp_addr;
14832 * If this bit is set to 1, then all queue_id0 related
14833 * parameters in this command are valid.
14835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
14838 * If this bit is set to 1, then all queue_id1 related
14839 * parameters in this command are valid.
14841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
14844 * If this bit is set to 1, then all queue_id2 related
14845 * parameters in this command are valid.
14847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
14850 * If this bit is set to 1, then all queue_id3 related
14851 * parameters in this command are valid.
14853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
14856 * If this bit is set to 1, then all queue_id4 related
14857 * parameters in this command are valid.
14859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
14862 * If this bit is set to 1, then all queue_id5 related
14863 * parameters in this command are valid.
14865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
14868 * If this bit is set to 1, then all queue_id6 related
14869 * parameters in this command are valid.
14871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
14874 * If this bit is set to 1, then all queue_id7 related
14875 * parameters in this command are valid.
14877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
14880 * Port ID of port for which the table is being configured.
14881 * The HWRM needs to check whether this function is allowed
14882 * to configure TC BW assignment on this port.
14885 /* ID of CoS Queue 0. */
14889 * Minimum BW allocated to CoS Queue.
14890 * The HWRM will translate this value into byte counter and
14891 * time interval used for this COS inside the device.
14893 uint32_t queue_id0_min_bw;
14894 /* The bandwidth value. */
14895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
14896 UINT32_C(0xfffffff)
14897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
14899 /* The granularity of the value (bits or bytes). */
14900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
14901 UINT32_C(0x10000000)
14902 /* Value is in bits. */
14903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
14904 (UINT32_C(0x0) << 28)
14905 /* Value is in bytes. */
14906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
14907 (UINT32_C(0x1) << 28)
14908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
14909 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
14910 /* bw_value_unit is 3 b */
14911 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
14912 UINT32_C(0xe0000000)
14913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
14915 /* Value is in Mb or MB (base 10). */
14916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
14917 (UINT32_C(0x0) << 29)
14918 /* Value is in Kb or KB (base 10). */
14919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
14920 (UINT32_C(0x2) << 29)
14921 /* Value is in bits or bytes. */
14922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
14923 (UINT32_C(0x4) << 29)
14924 /* Value is in Gb or GB (base 10). */
14925 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
14926 (UINT32_C(0x6) << 29)
14927 /* Value is in 1/100th of a percentage of total bandwidth. */
14928 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14929 (UINT32_C(0x1) << 29)
14931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
14932 (UINT32_C(0x7) << 29)
14933 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
14934 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
14936 * Maximum BW allocated to CoS Queue.
14937 * The HWRM will translate this value into byte counter and
14938 * time interval used for this COS inside the device.
14940 uint32_t queue_id0_max_bw;
14941 /* The bandwidth value. */
14942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
14943 UINT32_C(0xfffffff)
14944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
14946 /* The granularity of the value (bits or bytes). */
14947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
14948 UINT32_C(0x10000000)
14949 /* Value is in bits. */
14950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
14951 (UINT32_C(0x0) << 28)
14952 /* Value is in bytes. */
14953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
14954 (UINT32_C(0x1) << 28)
14955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
14956 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
14957 /* bw_value_unit is 3 b */
14958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
14959 UINT32_C(0xe0000000)
14960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
14962 /* Value is in Mb or MB (base 10). */
14963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
14964 (UINT32_C(0x0) << 29)
14965 /* Value is in Kb or KB (base 10). */
14966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
14967 (UINT32_C(0x2) << 29)
14968 /* Value is in bits or bytes. */
14969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
14970 (UINT32_C(0x4) << 29)
14971 /* Value is in Gb or GB (base 10). */
14972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
14973 (UINT32_C(0x6) << 29)
14974 /* Value is in 1/100th of a percentage of total bandwidth. */
14975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
14976 (UINT32_C(0x1) << 29)
14978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
14979 (UINT32_C(0x7) << 29)
14980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
14981 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
14982 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14983 uint8_t queue_id0_tsa_assign;
14984 /* Strict Priority */
14985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
14987 /* Enhanced Transmission Selection */
14988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
14991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
14994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
14997 * Priority level for strict priority. Valid only when the
14998 * tsa_assign is 0 - Strict Priority (SP)
14999 * 0..7 - Valid values.
15000 * 8..255 - Reserved.
15002 uint8_t queue_id0_pri_lvl;
15004 * Weight used to allocate remaining BW for this COS after
15005 * servicing guaranteed bandwidths for all COS.
15007 uint8_t queue_id0_bw_weight;
15008 /* ID of CoS Queue 1. */
15011 * Minimum BW allocated to CoS Queue.
15012 * The HWRM will translate this value into byte counter and
15013 * time interval used for this COS inside the device.
15015 uint32_t queue_id1_min_bw;
15016 /* The bandwidth value. */
15017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
15018 UINT32_C(0xfffffff)
15019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
15021 /* The granularity of the value (bits or bytes). */
15022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
15023 UINT32_C(0x10000000)
15024 /* Value is in bits. */
15025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
15026 (UINT32_C(0x0) << 28)
15027 /* Value is in bytes. */
15028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
15029 (UINT32_C(0x1) << 28)
15030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
15031 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
15032 /* bw_value_unit is 3 b */
15033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
15034 UINT32_C(0xe0000000)
15035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
15037 /* Value is in Mb or MB (base 10). */
15038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
15039 (UINT32_C(0x0) << 29)
15040 /* Value is in Kb or KB (base 10). */
15041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
15042 (UINT32_C(0x2) << 29)
15043 /* Value is in bits or bytes. */
15044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
15045 (UINT32_C(0x4) << 29)
15046 /* Value is in Gb or GB (base 10). */
15047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
15048 (UINT32_C(0x6) << 29)
15049 /* Value is in 1/100th of a percentage of total bandwidth. */
15050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15051 (UINT32_C(0x1) << 29)
15053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
15054 (UINT32_C(0x7) << 29)
15055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
15056 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
15058 * Maximum BW allocated to CoS queue.
15059 * The HWRM will translate this value into byte counter and
15060 * time interval used for this COS inside the device.
15062 uint32_t queue_id1_max_bw;
15063 /* The bandwidth value. */
15064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
15065 UINT32_C(0xfffffff)
15066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
15068 /* The granularity of the value (bits or bytes). */
15069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
15070 UINT32_C(0x10000000)
15071 /* Value is in bits. */
15072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
15073 (UINT32_C(0x0) << 28)
15074 /* Value is in bytes. */
15075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
15076 (UINT32_C(0x1) << 28)
15077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
15078 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
15079 /* bw_value_unit is 3 b */
15080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
15081 UINT32_C(0xe0000000)
15082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
15084 /* Value is in Mb or MB (base 10). */
15085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
15086 (UINT32_C(0x0) << 29)
15087 /* Value is in Kb or KB (base 10). */
15088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
15089 (UINT32_C(0x2) << 29)
15090 /* Value is in bits or bytes. */
15091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
15092 (UINT32_C(0x4) << 29)
15093 /* Value is in Gb or GB (base 10). */
15094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
15095 (UINT32_C(0x6) << 29)
15096 /* Value is in 1/100th of a percentage of total bandwidth. */
15097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15098 (UINT32_C(0x1) << 29)
15100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
15101 (UINT32_C(0x7) << 29)
15102 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
15103 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
15104 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15105 uint8_t queue_id1_tsa_assign;
15106 /* Strict Priority */
15107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
15109 /* Enhanced Transmission Selection */
15110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
15113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
15116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
15119 * Priority level for strict priority. Valid only when the
15120 * tsa_assign is 0 - Strict Priority (SP)
15121 * 0..7 - Valid values.
15122 * 8..255 - Reserved.
15124 uint8_t queue_id1_pri_lvl;
15126 * Weight used to allocate remaining BW for this COS after
15127 * servicing guaranteed bandwidths for all COS.
15129 uint8_t queue_id1_bw_weight;
15130 /* ID of CoS Queue 2. */
15133 * Minimum BW allocated to CoS Queue.
15134 * The HWRM will translate this value into byte counter and
15135 * time interval used for this COS inside the device.
15137 uint32_t queue_id2_min_bw;
15138 /* The bandwidth value. */
15139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
15140 UINT32_C(0xfffffff)
15141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
15143 /* The granularity of the value (bits or bytes). */
15144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
15145 UINT32_C(0x10000000)
15146 /* Value is in bits. */
15147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
15148 (UINT32_C(0x0) << 28)
15149 /* Value is in bytes. */
15150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
15151 (UINT32_C(0x1) << 28)
15152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
15153 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
15154 /* bw_value_unit is 3 b */
15155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
15156 UINT32_C(0xe0000000)
15157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
15159 /* Value is in Mb or MB (base 10). */
15160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
15161 (UINT32_C(0x0) << 29)
15162 /* Value is in Kb or KB (base 10). */
15163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
15164 (UINT32_C(0x2) << 29)
15165 /* Value is in bits or bytes. */
15166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
15167 (UINT32_C(0x4) << 29)
15168 /* Value is in Gb or GB (base 10). */
15169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
15170 (UINT32_C(0x6) << 29)
15171 /* Value is in 1/100th of a percentage of total bandwidth. */
15172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15173 (UINT32_C(0x1) << 29)
15175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
15176 (UINT32_C(0x7) << 29)
15177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
15178 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
15180 * Maximum BW allocated to CoS queue.
15181 * The HWRM will translate this value into byte counter and
15182 * time interval used for this COS inside the device.
15184 uint32_t queue_id2_max_bw;
15185 /* The bandwidth value. */
15186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
15187 UINT32_C(0xfffffff)
15188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
15190 /* The granularity of the value (bits or bytes). */
15191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
15192 UINT32_C(0x10000000)
15193 /* Value is in bits. */
15194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
15195 (UINT32_C(0x0) << 28)
15196 /* Value is in bytes. */
15197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
15198 (UINT32_C(0x1) << 28)
15199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
15200 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
15201 /* bw_value_unit is 3 b */
15202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
15203 UINT32_C(0xe0000000)
15204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
15206 /* Value is in Mb or MB (base 10). */
15207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
15208 (UINT32_C(0x0) << 29)
15209 /* Value is in Kb or KB (base 10). */
15210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
15211 (UINT32_C(0x2) << 29)
15212 /* Value is in bits or bytes. */
15213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
15214 (UINT32_C(0x4) << 29)
15215 /* Value is in Gb or GB (base 10). */
15216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
15217 (UINT32_C(0x6) << 29)
15218 /* Value is in 1/100th of a percentage of total bandwidth. */
15219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15220 (UINT32_C(0x1) << 29)
15222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
15223 (UINT32_C(0x7) << 29)
15224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
15225 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
15226 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15227 uint8_t queue_id2_tsa_assign;
15228 /* Strict Priority */
15229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
15231 /* Enhanced Transmission Selection */
15232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
15235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
15238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
15241 * Priority level for strict priority. Valid only when the
15242 * tsa_assign is 0 - Strict Priority (SP)
15243 * 0..7 - Valid values.
15244 * 8..255 - Reserved.
15246 uint8_t queue_id2_pri_lvl;
15248 * Weight used to allocate remaining BW for this COS after
15249 * servicing guaranteed bandwidths for all COS.
15251 uint8_t queue_id2_bw_weight;
15252 /* ID of CoS Queue 3. */
15255 * Minimum BW allocated to CoS Queue.
15256 * The HWRM will translate this value into byte counter and
15257 * time interval used for this COS inside the device.
15259 uint32_t queue_id3_min_bw;
15260 /* The bandwidth value. */
15261 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
15262 UINT32_C(0xfffffff)
15263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
15265 /* The granularity of the value (bits or bytes). */
15266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
15267 UINT32_C(0x10000000)
15268 /* Value is in bits. */
15269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
15270 (UINT32_C(0x0) << 28)
15271 /* Value is in bytes. */
15272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
15273 (UINT32_C(0x1) << 28)
15274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
15275 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
15276 /* bw_value_unit is 3 b */
15277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
15278 UINT32_C(0xe0000000)
15279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
15281 /* Value is in Mb or MB (base 10). */
15282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
15283 (UINT32_C(0x0) << 29)
15284 /* Value is in Kb or KB (base 10). */
15285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
15286 (UINT32_C(0x2) << 29)
15287 /* Value is in bits or bytes. */
15288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
15289 (UINT32_C(0x4) << 29)
15290 /* Value is in Gb or GB (base 10). */
15291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
15292 (UINT32_C(0x6) << 29)
15293 /* Value is in 1/100th of a percentage of total bandwidth. */
15294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15295 (UINT32_C(0x1) << 29)
15297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
15298 (UINT32_C(0x7) << 29)
15299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
15300 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
15302 * Maximum BW allocated to CoS queue.
15303 * The HWRM will translate this value into byte counter and
15304 * time interval used for this COS inside the device.
15306 uint32_t queue_id3_max_bw;
15307 /* The bandwidth value. */
15308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
15309 UINT32_C(0xfffffff)
15310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
15312 /* The granularity of the value (bits or bytes). */
15313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
15314 UINT32_C(0x10000000)
15315 /* Value is in bits. */
15316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
15317 (UINT32_C(0x0) << 28)
15318 /* Value is in bytes. */
15319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
15320 (UINT32_C(0x1) << 28)
15321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
15322 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
15323 /* bw_value_unit is 3 b */
15324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
15325 UINT32_C(0xe0000000)
15326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
15328 /* Value is in Mb or MB (base 10). */
15329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
15330 (UINT32_C(0x0) << 29)
15331 /* Value is in Kb or KB (base 10). */
15332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
15333 (UINT32_C(0x2) << 29)
15334 /* Value is in bits or bytes. */
15335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
15336 (UINT32_C(0x4) << 29)
15337 /* Value is in Gb or GB (base 10). */
15338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
15339 (UINT32_C(0x6) << 29)
15340 /* Value is in 1/100th of a percentage of total bandwidth. */
15341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15342 (UINT32_C(0x1) << 29)
15344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
15345 (UINT32_C(0x7) << 29)
15346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
15347 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
15348 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15349 uint8_t queue_id3_tsa_assign;
15350 /* Strict Priority */
15351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
15353 /* Enhanced Transmission Selection */
15354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
15357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
15360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
15363 * Priority level for strict priority. Valid only when the
15364 * tsa_assign is 0 - Strict Priority (SP)
15365 * 0..7 - Valid values.
15366 * 8..255 - Reserved.
15368 uint8_t queue_id3_pri_lvl;
15370 * Weight used to allocate remaining BW for this COS after
15371 * servicing guaranteed bandwidths for all COS.
15373 uint8_t queue_id3_bw_weight;
15374 /* ID of CoS Queue 4. */
15377 * Minimum BW allocated to CoS Queue.
15378 * The HWRM will translate this value into byte counter and
15379 * time interval used for this COS inside the device.
15381 uint32_t queue_id4_min_bw;
15382 /* The bandwidth value. */
15383 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
15384 UINT32_C(0xfffffff)
15385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
15387 /* The granularity of the value (bits or bytes). */
15388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
15389 UINT32_C(0x10000000)
15390 /* Value is in bits. */
15391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
15392 (UINT32_C(0x0) << 28)
15393 /* Value is in bytes. */
15394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
15395 (UINT32_C(0x1) << 28)
15396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
15397 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
15398 /* bw_value_unit is 3 b */
15399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
15400 UINT32_C(0xe0000000)
15401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
15403 /* Value is in Mb or MB (base 10). */
15404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
15405 (UINT32_C(0x0) << 29)
15406 /* Value is in Kb or KB (base 10). */
15407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
15408 (UINT32_C(0x2) << 29)
15409 /* Value is in bits or bytes. */
15410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
15411 (UINT32_C(0x4) << 29)
15412 /* Value is in Gb or GB (base 10). */
15413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
15414 (UINT32_C(0x6) << 29)
15415 /* Value is in 1/100th of a percentage of total bandwidth. */
15416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15417 (UINT32_C(0x1) << 29)
15419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
15420 (UINT32_C(0x7) << 29)
15421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
15422 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
15424 * Maximum BW allocated to CoS queue.
15425 * The HWRM will translate this value into byte counter and
15426 * time interval used for this COS inside the device.
15428 uint32_t queue_id4_max_bw;
15429 /* The bandwidth value. */
15430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
15431 UINT32_C(0xfffffff)
15432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
15434 /* The granularity of the value (bits or bytes). */
15435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
15436 UINT32_C(0x10000000)
15437 /* Value is in bits. */
15438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
15439 (UINT32_C(0x0) << 28)
15440 /* Value is in bytes. */
15441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
15442 (UINT32_C(0x1) << 28)
15443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
15444 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
15445 /* bw_value_unit is 3 b */
15446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
15447 UINT32_C(0xe0000000)
15448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
15450 /* Value is in Mb or MB (base 10). */
15451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
15452 (UINT32_C(0x0) << 29)
15453 /* Value is in Kb or KB (base 10). */
15454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
15455 (UINT32_C(0x2) << 29)
15456 /* Value is in bits or bytes. */
15457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
15458 (UINT32_C(0x4) << 29)
15459 /* Value is in Gb or GB (base 10). */
15460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
15461 (UINT32_C(0x6) << 29)
15462 /* Value is in 1/100th of a percentage of total bandwidth. */
15463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15464 (UINT32_C(0x1) << 29)
15466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
15467 (UINT32_C(0x7) << 29)
15468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
15469 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
15470 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15471 uint8_t queue_id4_tsa_assign;
15472 /* Strict Priority */
15473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
15475 /* Enhanced Transmission Selection */
15476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
15479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
15482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
15485 * Priority level for strict priority. Valid only when the
15486 * tsa_assign is 0 - Strict Priority (SP)
15487 * 0..7 - Valid values.
15488 * 8..255 - Reserved.
15490 uint8_t queue_id4_pri_lvl;
15492 * Weight used to allocate remaining BW for this COS after
15493 * servicing guaranteed bandwidths for all COS.
15495 uint8_t queue_id4_bw_weight;
15496 /* ID of CoS Queue 5. */
15499 * Minimum BW allocated to CoS Queue.
15500 * The HWRM will translate this value into byte counter and
15501 * time interval used for this COS inside the device.
15503 uint32_t queue_id5_min_bw;
15504 /* The bandwidth value. */
15505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
15506 UINT32_C(0xfffffff)
15507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
15509 /* The granularity of the value (bits or bytes). */
15510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
15511 UINT32_C(0x10000000)
15512 /* Value is in bits. */
15513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
15514 (UINT32_C(0x0) << 28)
15515 /* Value is in bytes. */
15516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
15517 (UINT32_C(0x1) << 28)
15518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
15519 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
15520 /* bw_value_unit is 3 b */
15521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
15522 UINT32_C(0xe0000000)
15523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
15525 /* Value is in Mb or MB (base 10). */
15526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
15527 (UINT32_C(0x0) << 29)
15528 /* Value is in Kb or KB (base 10). */
15529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
15530 (UINT32_C(0x2) << 29)
15531 /* Value is in bits or bytes. */
15532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
15533 (UINT32_C(0x4) << 29)
15534 /* Value is in Gb or GB (base 10). */
15535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
15536 (UINT32_C(0x6) << 29)
15537 /* Value is in 1/100th of a percentage of total bandwidth. */
15538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15539 (UINT32_C(0x1) << 29)
15541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
15542 (UINT32_C(0x7) << 29)
15543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
15544 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
15546 * Maximum BW allocated to CoS queue.
15547 * The HWRM will translate this value into byte counter and
15548 * time interval used for this COS inside the device.
15550 uint32_t queue_id5_max_bw;
15551 /* The bandwidth value. */
15552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
15553 UINT32_C(0xfffffff)
15554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
15556 /* The granularity of the value (bits or bytes). */
15557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
15558 UINT32_C(0x10000000)
15559 /* Value is in bits. */
15560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
15561 (UINT32_C(0x0) << 28)
15562 /* Value is in bytes. */
15563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
15564 (UINT32_C(0x1) << 28)
15565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
15566 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
15567 /* bw_value_unit is 3 b */
15568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
15569 UINT32_C(0xe0000000)
15570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
15572 /* Value is in Mb or MB (base 10). */
15573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
15574 (UINT32_C(0x0) << 29)
15575 /* Value is in Kb or KB (base 10). */
15576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
15577 (UINT32_C(0x2) << 29)
15578 /* Value is in bits or bytes. */
15579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
15580 (UINT32_C(0x4) << 29)
15581 /* Value is in Gb or GB (base 10). */
15582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
15583 (UINT32_C(0x6) << 29)
15584 /* Value is in 1/100th of a percentage of total bandwidth. */
15585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15586 (UINT32_C(0x1) << 29)
15588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
15589 (UINT32_C(0x7) << 29)
15590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
15591 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
15592 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15593 uint8_t queue_id5_tsa_assign;
15594 /* Strict Priority */
15595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
15597 /* Enhanced Transmission Selection */
15598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
15601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
15604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
15607 * Priority level for strict priority. Valid only when the
15608 * tsa_assign is 0 - Strict Priority (SP)
15609 * 0..7 - Valid values.
15610 * 8..255 - Reserved.
15612 uint8_t queue_id5_pri_lvl;
15614 * Weight used to allocate remaining BW for this COS after
15615 * servicing guaranteed bandwidths for all COS.
15617 uint8_t queue_id5_bw_weight;
15618 /* ID of CoS Queue 6. */
15621 * Minimum BW allocated to CoS Queue.
15622 * The HWRM will translate this value into byte counter and
15623 * time interval used for this COS inside the device.
15625 uint32_t queue_id6_min_bw;
15626 /* The bandwidth value. */
15627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
15628 UINT32_C(0xfffffff)
15629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
15631 /* The granularity of the value (bits or bytes). */
15632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
15633 UINT32_C(0x10000000)
15634 /* Value is in bits. */
15635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
15636 (UINT32_C(0x0) << 28)
15637 /* Value is in bytes. */
15638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
15639 (UINT32_C(0x1) << 28)
15640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
15641 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
15642 /* bw_value_unit is 3 b */
15643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
15644 UINT32_C(0xe0000000)
15645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
15647 /* Value is in Mb or MB (base 10). */
15648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
15649 (UINT32_C(0x0) << 29)
15650 /* Value is in Kb or KB (base 10). */
15651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
15652 (UINT32_C(0x2) << 29)
15653 /* Value is in bits or bytes. */
15654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
15655 (UINT32_C(0x4) << 29)
15656 /* Value is in Gb or GB (base 10). */
15657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
15658 (UINT32_C(0x6) << 29)
15659 /* Value is in 1/100th of a percentage of total bandwidth. */
15660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15661 (UINT32_C(0x1) << 29)
15663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
15664 (UINT32_C(0x7) << 29)
15665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
15666 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
15668 * Maximum BW allocated to CoS queue.
15669 * The HWRM will translate this value into byte counter and
15670 * time interval used for this COS inside the device.
15672 uint32_t queue_id6_max_bw;
15673 /* The bandwidth value. */
15674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
15675 UINT32_C(0xfffffff)
15676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
15678 /* The granularity of the value (bits or bytes). */
15679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
15680 UINT32_C(0x10000000)
15681 /* Value is in bits. */
15682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
15683 (UINT32_C(0x0) << 28)
15684 /* Value is in bytes. */
15685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
15686 (UINT32_C(0x1) << 28)
15687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
15688 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
15689 /* bw_value_unit is 3 b */
15690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
15691 UINT32_C(0xe0000000)
15692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
15694 /* Value is in Mb or MB (base 10). */
15695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
15696 (UINT32_C(0x0) << 29)
15697 /* Value is in Kb or KB (base 10). */
15698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
15699 (UINT32_C(0x2) << 29)
15700 /* Value is in bits or bytes. */
15701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
15702 (UINT32_C(0x4) << 29)
15703 /* Value is in Gb or GB (base 10). */
15704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
15705 (UINT32_C(0x6) << 29)
15706 /* Value is in 1/100th of a percentage of total bandwidth. */
15707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15708 (UINT32_C(0x1) << 29)
15710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
15711 (UINT32_C(0x7) << 29)
15712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
15713 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
15714 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15715 uint8_t queue_id6_tsa_assign;
15716 /* Strict Priority */
15717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
15719 /* Enhanced Transmission Selection */
15720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
15723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
15726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
15729 * Priority level for strict priority. Valid only when the
15730 * tsa_assign is 0 - Strict Priority (SP)
15731 * 0..7 - Valid values.
15732 * 8..255 - Reserved.
15734 uint8_t queue_id6_pri_lvl;
15736 * Weight used to allocate remaining BW for this COS after
15737 * servicing guaranteed bandwidths for all COS.
15739 uint8_t queue_id6_bw_weight;
15740 /* ID of CoS Queue 7. */
15743 * Minimum BW allocated to CoS Queue.
15744 * The HWRM will translate this value into byte counter and
15745 * time interval used for this COS inside the device.
15747 uint32_t queue_id7_min_bw;
15748 /* The bandwidth value. */
15749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
15750 UINT32_C(0xfffffff)
15751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
15753 /* The granularity of the value (bits or bytes). */
15754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
15755 UINT32_C(0x10000000)
15756 /* Value is in bits. */
15757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
15758 (UINT32_C(0x0) << 28)
15759 /* Value is in bytes. */
15760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
15761 (UINT32_C(0x1) << 28)
15762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
15763 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
15764 /* bw_value_unit is 3 b */
15765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
15766 UINT32_C(0xe0000000)
15767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
15769 /* Value is in Mb or MB (base 10). */
15770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
15771 (UINT32_C(0x0) << 29)
15772 /* Value is in Kb or KB (base 10). */
15773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
15774 (UINT32_C(0x2) << 29)
15775 /* Value is in bits or bytes. */
15776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
15777 (UINT32_C(0x4) << 29)
15778 /* Value is in Gb or GB (base 10). */
15779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
15780 (UINT32_C(0x6) << 29)
15781 /* Value is in 1/100th of a percentage of total bandwidth. */
15782 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15783 (UINT32_C(0x1) << 29)
15785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
15786 (UINT32_C(0x7) << 29)
15787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
15788 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
15790 * Maximum BW allocated to CoS queue.
15791 * The HWRM will translate this value into byte counter and
15792 * time interval used for this COS inside the device.
15794 uint32_t queue_id7_max_bw;
15795 /* The bandwidth value. */
15796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
15797 UINT32_C(0xfffffff)
15798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
15800 /* The granularity of the value (bits or bytes). */
15801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
15802 UINT32_C(0x10000000)
15803 /* Value is in bits. */
15804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
15805 (UINT32_C(0x0) << 28)
15806 /* Value is in bytes. */
15807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
15808 (UINT32_C(0x1) << 28)
15809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
15810 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
15811 /* bw_value_unit is 3 b */
15812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
15813 UINT32_C(0xe0000000)
15814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
15816 /* Value is in Mb or MB (base 10). */
15817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
15818 (UINT32_C(0x0) << 29)
15819 /* Value is in Kb or KB (base 10). */
15820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
15821 (UINT32_C(0x2) << 29)
15822 /* Value is in bits or bytes. */
15823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
15824 (UINT32_C(0x4) << 29)
15825 /* Value is in Gb or GB (base 10). */
15826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
15827 (UINT32_C(0x6) << 29)
15828 /* Value is in 1/100th of a percentage of total bandwidth. */
15829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15830 (UINT32_C(0x1) << 29)
15832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
15833 (UINT32_C(0x7) << 29)
15834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
15835 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
15836 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15837 uint8_t queue_id7_tsa_assign;
15838 /* Strict Priority */
15839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
15841 /* Enhanced Transmission Selection */
15842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
15845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
15848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
15851 * Priority level for strict priority. Valid only when the
15852 * tsa_assign is 0 - Strict Priority (SP)
15853 * 0..7 - Valid values.
15854 * 8..255 - Reserved.
15856 uint8_t queue_id7_pri_lvl;
15858 * Weight used to allocate remaining BW for this COS after
15859 * servicing guaranteed bandwidths for all COS.
15861 uint8_t queue_id7_bw_weight;
15862 uint8_t unused_1[5];
15863 } __attribute__((packed));
15865 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
15866 struct hwrm_queue_cos2bw_cfg_output {
15867 /* The specific error status for the command. */
15868 uint16_t error_code;
15869 /* The HWRM command request type. */
15871 /* The sequence ID from the original command. */
15873 /* The length of the response data in number of bytes. */
15875 uint8_t unused_0[7];
15877 * This field is used in Output records to indicate that the output
15878 * is completely written to RAM. This field should be read as '1'
15879 * to indicate that the output has been completely written.
15880 * When writing a command completion or response to an internal processor,
15881 * the order of writes has to be such that this field is written last.
15884 } __attribute__((packed));
15886 /*************************
15887 * hwrm_queue_dscp_qcaps *
15888 *************************/
15891 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
15892 struct hwrm_queue_dscp_qcaps_input {
15893 /* The HWRM command request type. */
15896 * The completion ring to send the completion event on. This should
15897 * be the NQ ID returned from the `nq_alloc` HWRM command.
15899 uint16_t cmpl_ring;
15901 * The sequence ID is used by the driver for tracking multiple
15902 * commands. This ID is treated as opaque data by the firmware and
15903 * the value is returned in the `hwrm_resp_hdr` upon completion.
15907 * The target ID of the command:
15908 * * 0x0-0xFFF8 - The function ID
15909 * * 0xFFF8-0xFFFE - Reserved for internal processors
15912 uint16_t target_id;
15914 * A physical address pointer pointing to a host buffer that the
15915 * command's response data will be written. This can be either a host
15916 * physical address (HPA) or a guest physical address (GPA) and must
15917 * point to a physically contiguous block of memory.
15919 uint64_t resp_addr;
15921 * Port ID of port for which the table is being configured.
15922 * The HWRM needs to check whether this function is allowed
15923 * to configure pri2cos mapping on this port.
15926 uint8_t unused_0[7];
15927 } __attribute__((packed));
15929 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
15930 struct hwrm_queue_dscp_qcaps_output {
15931 /* The specific error status for the command. */
15932 uint16_t error_code;
15933 /* The HWRM command request type. */
15935 /* The sequence ID from the original command. */
15937 /* The length of the response data in number of bytes. */
15939 /* The number of bits provided by the hardware for the DSCP value. */
15940 uint8_t num_dscp_bits;
15942 /* Max number of DSCP-MASK-PRI entries supported. */
15943 uint16_t max_entries;
15944 uint8_t unused_1[3];
15946 * This field is used in Output records to indicate that the output
15947 * is completely written to RAM. This field should be read as '1'
15948 * to indicate that the output has been completely written.
15949 * When writing a command completion or response to an internal processor,
15950 * the order of writes has to be such that this field is written last.
15953 } __attribute__((packed));
15955 /****************************
15956 * hwrm_queue_dscp2pri_qcfg *
15957 ****************************/
15960 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
15961 struct hwrm_queue_dscp2pri_qcfg_input {
15962 /* The HWRM command request type. */
15965 * The completion ring to send the completion event on. This should
15966 * be the NQ ID returned from the `nq_alloc` HWRM command.
15968 uint16_t cmpl_ring;
15970 * The sequence ID is used by the driver for tracking multiple
15971 * commands. This ID is treated as opaque data by the firmware and
15972 * the value is returned in the `hwrm_resp_hdr` upon completion.
15976 * The target ID of the command:
15977 * * 0x0-0xFFF8 - The function ID
15978 * * 0xFFF8-0xFFFE - Reserved for internal processors
15981 uint16_t target_id;
15983 * A physical address pointer pointing to a host buffer that the
15984 * command's response data will be written. This can be either a host
15985 * physical address (HPA) or a guest physical address (GPA) and must
15986 * point to a physically contiguous block of memory.
15988 uint64_t resp_addr;
15990 * This is the host address where the 24-bits DSCP-MASK-PRI
15991 * tuple(s) will be copied to.
15993 uint64_t dest_data_addr;
15995 * Port ID of port for which the table is being configured.
15996 * The HWRM needs to check whether this function is allowed
15997 * to configure pri2cos mapping on this port.
16001 /* Size of the buffer pointed to by dest_data_addr. */
16002 uint16_t dest_data_buffer_size;
16003 uint8_t unused_1[4];
16004 } __attribute__((packed));
16006 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
16007 struct hwrm_queue_dscp2pri_qcfg_output {
16008 /* The specific error status for the command. */
16009 uint16_t error_code;
16010 /* The HWRM command request type. */
16012 /* The sequence ID from the original command. */
16014 /* The length of the response data in number of bytes. */
16017 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
16018 * by the dest_data_addr.
16020 uint16_t entry_cnt;
16022 * This is the default PRI which un-initialized DSCP values are
16025 uint8_t default_pri;
16026 uint8_t unused_0[4];
16028 * This field is used in Output records to indicate that the output
16029 * is completely written to RAM. This field should be read as '1'
16030 * to indicate that the output has been completely written.
16031 * When writing a command completion or response to an internal processor,
16032 * the order of writes has to be such that this field is written last.
16035 } __attribute__((packed));
16037 /***************************
16038 * hwrm_queue_dscp2pri_cfg *
16039 ***************************/
16042 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
16043 struct hwrm_queue_dscp2pri_cfg_input {
16044 /* The HWRM command request type. */
16047 * The completion ring to send the completion event on. This should
16048 * be the NQ ID returned from the `nq_alloc` HWRM command.
16050 uint16_t cmpl_ring;
16052 * The sequence ID is used by the driver for tracking multiple
16053 * commands. This ID is treated as opaque data by the firmware and
16054 * the value is returned in the `hwrm_resp_hdr` upon completion.
16058 * The target ID of the command:
16059 * * 0x0-0xFFF8 - The function ID
16060 * * 0xFFF8-0xFFFE - Reserved for internal processors
16063 uint16_t target_id;
16065 * A physical address pointer pointing to a host buffer that the
16066 * command's response data will be written. This can be either a host
16067 * physical address (HPA) or a guest physical address (GPA) and must
16068 * point to a physically contiguous block of memory.
16070 uint64_t resp_addr;
16072 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
16073 * will be copied from.
16075 uint64_t src_data_addr;
16077 /* use_hw_default_pri is 1 b */
16078 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
16082 * This bit must be '1' for the default_pri field to be
16085 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
16088 * Port ID of port for which the table is being configured.
16089 * The HWRM needs to check whether this function is allowed
16090 * to configure pri2cos mapping on this port.
16094 * This is the default PRI which un-initialized DSCP values will be
16097 uint8_t default_pri;
16099 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
16100 * to by src_data_addr.
16102 uint16_t entry_cnt;
16103 uint8_t unused_0[4];
16104 } __attribute__((packed));
16106 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
16107 struct hwrm_queue_dscp2pri_cfg_output {
16108 /* The specific error status for the command. */
16109 uint16_t error_code;
16110 /* The HWRM command request type. */
16112 /* The sequence ID from the original command. */
16114 /* The length of the response data in number of bytes. */
16116 uint8_t unused_0[7];
16118 * This field is used in Output records to indicate that the output
16119 * is completely written to RAM. This field should be read as '1'
16120 * to indicate that the output has been completely written.
16121 * When writing a command completion or response to an internal processor,
16122 * the order of writes has to be such that this field is written last.
16125 } __attribute__((packed));
16127 /*******************
16128 * hwrm_vnic_alloc *
16129 *******************/
16132 /* hwrm_vnic_alloc_input (size:192b/24B) */
16133 struct hwrm_vnic_alloc_input {
16134 /* The HWRM command request type. */
16137 * The completion ring to send the completion event on. This should
16138 * be the NQ ID returned from the `nq_alloc` HWRM command.
16140 uint16_t cmpl_ring;
16142 * The sequence ID is used by the driver for tracking multiple
16143 * commands. This ID is treated as opaque data by the firmware and
16144 * the value is returned in the `hwrm_resp_hdr` upon completion.
16148 * The target ID of the command:
16149 * * 0x0-0xFFF8 - The function ID
16150 * * 0xFFF8-0xFFFE - Reserved for internal processors
16153 uint16_t target_id;
16155 * A physical address pointer pointing to a host buffer that the
16156 * command's response data will be written. This can be either a host
16157 * physical address (HPA) or a guest physical address (GPA) and must
16158 * point to a physically contiguous block of memory.
16160 uint64_t resp_addr;
16163 * When this bit is '1', this VNIC is requested to
16164 * be the default VNIC for this function.
16166 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
16167 uint8_t unused_0[4];
16168 } __attribute__((packed));
16170 /* hwrm_vnic_alloc_output (size:128b/16B) */
16171 struct hwrm_vnic_alloc_output {
16172 /* The specific error status for the command. */
16173 uint16_t error_code;
16174 /* The HWRM command request type. */
16176 /* The sequence ID from the original command. */
16178 /* The length of the response data in number of bytes. */
16180 /* Logical vnic ID */
16182 uint8_t unused_0[3];
16184 * This field is used in Output records to indicate that the output
16185 * is completely written to RAM. This field should be read as '1'
16186 * to indicate that the output has been completely written.
16187 * When writing a command completion or response to an internal processor,
16188 * the order of writes has to be such that this field is written last.
16191 } __attribute__((packed));
16193 /******************
16195 ******************/
16198 /* hwrm_vnic_free_input (size:192b/24B) */
16199 struct hwrm_vnic_free_input {
16200 /* The HWRM command request type. */
16203 * The completion ring to send the completion event on. This should
16204 * be the NQ ID returned from the `nq_alloc` HWRM command.
16206 uint16_t cmpl_ring;
16208 * The sequence ID is used by the driver for tracking multiple
16209 * commands. This ID is treated as opaque data by the firmware and
16210 * the value is returned in the `hwrm_resp_hdr` upon completion.
16214 * The target ID of the command:
16215 * * 0x0-0xFFF8 - The function ID
16216 * * 0xFFF8-0xFFFE - Reserved for internal processors
16219 uint16_t target_id;
16221 * A physical address pointer pointing to a host buffer that the
16222 * command's response data will be written. This can be either a host
16223 * physical address (HPA) or a guest physical address (GPA) and must
16224 * point to a physically contiguous block of memory.
16226 uint64_t resp_addr;
16227 /* Logical vnic ID */
16229 uint8_t unused_0[4];
16230 } __attribute__((packed));
16232 /* hwrm_vnic_free_output (size:128b/16B) */
16233 struct hwrm_vnic_free_output {
16234 /* The specific error status for the command. */
16235 uint16_t error_code;
16236 /* The HWRM command request type. */
16238 /* The sequence ID from the original command. */
16240 /* The length of the response data in number of bytes. */
16242 uint8_t unused_0[7];
16244 * This field is used in Output records to indicate that the output
16245 * is completely written to RAM. This field should be read as '1'
16246 * to indicate that the output has been completely written.
16247 * When writing a command completion or response to an internal processor,
16248 * the order of writes has to be such that this field is written last.
16251 } __attribute__((packed));
16258 /* hwrm_vnic_cfg_input (size:320b/40B) */
16259 struct hwrm_vnic_cfg_input {
16260 /* The HWRM command request type. */
16263 * The completion ring to send the completion event on. This should
16264 * be the NQ ID returned from the `nq_alloc` HWRM command.
16266 uint16_t cmpl_ring;
16268 * The sequence ID is used by the driver for tracking multiple
16269 * commands. This ID is treated as opaque data by the firmware and
16270 * the value is returned in the `hwrm_resp_hdr` upon completion.
16274 * The target ID of the command:
16275 * * 0x0-0xFFF8 - The function ID
16276 * * 0xFFF8-0xFFFE - Reserved for internal processors
16279 uint16_t target_id;
16281 * A physical address pointer pointing to a host buffer that the
16282 * command's response data will be written. This can be either a host
16283 * physical address (HPA) or a guest physical address (GPA) and must
16284 * point to a physically contiguous block of memory.
16286 uint64_t resp_addr;
16289 * When this bit is '1', the VNIC is requested to
16290 * be the default VNIC for the function.
16292 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
16295 * When this bit is '1', the VNIC is being configured to
16296 * strip VLAN in the RX path.
16297 * If set to '0', then VLAN stripping is disabled on
16300 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
16303 * When this bit is '1', the VNIC is being configured to
16304 * buffer receive packets in the hardware until the host
16305 * posts new receive buffers.
16306 * If set to '0', then bd_stall is being configured to be
16307 * disabled on this VNIC.
16309 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
16312 * When this bit is '1', the VNIC is being configured to
16313 * receive both RoCE and non-RoCE traffic.
16314 * If set to '0', then this VNIC is not configured to be
16315 * operating in dual VNIC mode.
16317 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
16320 * When this flag is set to '1', the VNIC is requested to
16321 * be configured to receive only RoCE traffic.
16322 * If this flag is set to '0', then this flag shall be
16323 * ignored by the HWRM.
16324 * If roce_dual_vnic_mode flag is set to '1'
16325 * or roce_mirroring_capable_vnic_mode flag to 1,
16326 * then the HWRM client shall not set this flag to '1'.
16328 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
16331 * When a VNIC uses one destination ring group for certain
16332 * application (e.g. Receive Flow Steering) where
16333 * exact match is used to direct packets to a VNIC with one
16334 * destination ring group only, there is no need to configure
16335 * RSS indirection table for that VNIC as only one destination
16336 * ring group is used.
16338 * This flag is used to enable a mode where
16339 * RSS is enabled in the VNIC using a RSS context
16340 * for computing RSS hash but the RSS indirection table is
16341 * not configured using hwrm_vnic_rss_cfg.
16343 * If this mode is enabled, then the driver should not program
16344 * RSS indirection table for the RSS context that is used for
16345 * computing RSS hash only.
16347 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
16350 * When this bit is '1', the VNIC is being configured to
16351 * receive both RoCE and non-RoCE traffic, but forward only the
16352 * RoCE traffic further. Also, RoCE traffic can be mirrored to
16355 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
16359 * This bit must be '1' for the dflt_ring_grp field to be
16362 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
16365 * This bit must be '1' for the rss_rule field to be
16368 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
16371 * This bit must be '1' for the cos_rule field to be
16374 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
16377 * This bit must be '1' for the lb_rule field to be
16380 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
16383 * This bit must be '1' for the mru field to be
16386 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
16389 * This bit must be '1' for the default_rx_ring_id field to be
16392 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
16395 * This bit must be '1' for the default_cmpl_ring_id field to be
16398 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
16400 /* Logical vnic ID */
16403 * Default Completion ring for the VNIC. This ring will
16404 * be chosen if packet does not match any RSS rules and if
16405 * there is no COS rule.
16407 uint16_t dflt_ring_grp;
16409 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
16410 * there is no RSS rule.
16414 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
16415 * there is no COS rule.
16419 * RSS ID for load balancing rule/table structure.
16420 * 0xFF... (All Fs) if there is no LB rule.
16424 * The maximum receive unit of the vnic.
16425 * Each vnic is associated with a function.
16426 * The vnic mru value overwrites the mru setting of the
16427 * associated function.
16428 * The HWRM shall make sure that vnic mru does not exceed
16429 * the mru of the port the function is associated with.
16433 * Default Rx ring for the VNIC. This ring will
16434 * be chosen if packet does not match any RSS rules.
16435 * The aggregation ring associated with the Rx ring is
16436 * implied based on the Rx ring specified when the
16437 * aggregation ring was allocated.
16439 uint16_t default_rx_ring_id;
16441 * Default completion ring for the VNIC. This ring will
16442 * be chosen if packet does not match any RSS rules.
16444 uint16_t default_cmpl_ring_id;
16445 } __attribute__((packed));
16447 /* hwrm_vnic_cfg_output (size:128b/16B) */
16448 struct hwrm_vnic_cfg_output {
16449 /* The specific error status for the command. */
16450 uint16_t error_code;
16451 /* The HWRM command request type. */
16453 /* The sequence ID from the original command. */
16455 /* The length of the response data in number of bytes. */
16457 uint8_t unused_0[7];
16459 * This field is used in Output records to indicate that the output
16460 * is completely written to RAM. This field should be read as '1'
16461 * to indicate that the output has been completely written.
16462 * When writing a command completion or response to an internal processor,
16463 * the order of writes has to be such that this field is written last.
16466 } __attribute__((packed));
16468 /******************
16470 ******************/
16473 /* hwrm_vnic_qcfg_input (size:256b/32B) */
16474 struct hwrm_vnic_qcfg_input {
16475 /* The HWRM command request type. */
16478 * The completion ring to send the completion event on. This should
16479 * be the NQ ID returned from the `nq_alloc` HWRM command.
16481 uint16_t cmpl_ring;
16483 * The sequence ID is used by the driver for tracking multiple
16484 * commands. This ID is treated as opaque data by the firmware and
16485 * the value is returned in the `hwrm_resp_hdr` upon completion.
16489 * The target ID of the command:
16490 * * 0x0-0xFFF8 - The function ID
16491 * * 0xFFF8-0xFFFE - Reserved for internal processors
16494 uint16_t target_id;
16496 * A physical address pointer pointing to a host buffer that the
16497 * command's response data will be written. This can be either a host
16498 * physical address (HPA) or a guest physical address (GPA) and must
16499 * point to a physically contiguous block of memory.
16501 uint64_t resp_addr;
16504 * This bit must be '1' for the vf_id_valid field to be
16507 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
16508 /* Logical vnic ID */
16510 /* ID of Virtual Function whose VNIC resource is being queried. */
16512 uint8_t unused_0[6];
16513 } __attribute__((packed));
16515 /* hwrm_vnic_qcfg_output (size:256b/32B) */
16516 struct hwrm_vnic_qcfg_output {
16517 /* The specific error status for the command. */
16518 uint16_t error_code;
16519 /* The HWRM command request type. */
16521 /* The sequence ID from the original command. */
16523 /* The length of the response data in number of bytes. */
16525 /* Default Completion ring for the VNIC. */
16526 uint16_t dflt_ring_grp;
16528 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
16529 * there is no RSS rule.
16533 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
16534 * there is no COS rule.
16538 * RSS ID for load balancing rule/table structure.
16539 * 0xFF... (All Fs) if there is no LB rule.
16542 /* The maximum receive unit of the vnic. */
16544 uint8_t unused_0[2];
16547 * When this bit is '1', the VNIC is the default VNIC for
16550 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
16553 * When this bit is '1', the VNIC is configured to
16554 * strip VLAN in the RX path.
16555 * If set to '0', then VLAN stripping is disabled on
16558 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
16561 * When this bit is '1', the VNIC is configured to
16562 * buffer receive packets in the hardware until the host
16563 * posts new receive buffers.
16564 * If set to '0', then bd_stall is disabled on
16567 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
16570 * When this bit is '1', the VNIC is configured to
16571 * receive both RoCE and non-RoCE traffic.
16572 * If set to '0', then this VNIC is not configured to
16573 * operate in dual VNIC mode.
16575 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
16578 * When this flag is set to '1', the VNIC is configured to
16579 * receive only RoCE traffic.
16580 * When this flag is set to '0', the VNIC is not configured
16581 * to receive only RoCE traffic.
16582 * If roce_dual_vnic_mode flag and this flag both are set
16583 * to '1', then it is an invalid configuration of the
16584 * VNIC. The HWRM should not allow that type of
16585 * mis-configuration by HWRM clients.
16587 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
16590 * When a VNIC uses one destination ring group for certain
16591 * application (e.g. Receive Flow Steering) where
16592 * exact match is used to direct packets to a VNIC with one
16593 * destination ring group only, there is no need to configure
16594 * RSS indirection table for that VNIC as only one destination
16595 * ring group is used.
16597 * When this bit is set to '1', then the VNIC is enabled in a
16598 * mode where RSS is enabled in the VNIC using a RSS context
16599 * for computing RSS hash but the RSS indirection table is
16602 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
16605 * When this bit is '1', the VNIC is configured to
16606 * receive both RoCE and non-RoCE traffic, but forward only
16607 * RoCE traffic further. Also RoCE traffic can be mirrored to
16610 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
16612 uint8_t unused_1[7];
16614 * This field is used in Output records to indicate that the output
16615 * is completely written to RAM. This field should be read as '1'
16616 * to indicate that the output has been completely written.
16617 * When writing a command completion or response to an internal processor,
16618 * the order of writes has to be such that this field is written last.
16621 } __attribute__((packed));
16623 /*******************
16624 * hwrm_vnic_qcaps *
16625 *******************/
16628 /* hwrm_vnic_qcaps_input (size:192b/24B) */
16629 struct hwrm_vnic_qcaps_input {
16630 /* The HWRM command request type. */
16633 * The completion ring to send the completion event on. This should
16634 * be the NQ ID returned from the `nq_alloc` HWRM command.
16636 uint16_t cmpl_ring;
16638 * The sequence ID is used by the driver for tracking multiple
16639 * commands. This ID is treated as opaque data by the firmware and
16640 * the value is returned in the `hwrm_resp_hdr` upon completion.
16644 * The target ID of the command:
16645 * * 0x0-0xFFF8 - The function ID
16646 * * 0xFFF8-0xFFFE - Reserved for internal processors
16649 uint16_t target_id;
16651 * A physical address pointer pointing to a host buffer that the
16652 * command's response data will be written. This can be either a host
16653 * physical address (HPA) or a guest physical address (GPA) and must
16654 * point to a physically contiguous block of memory.
16656 uint64_t resp_addr;
16658 uint8_t unused_0[4];
16659 } __attribute__((packed));
16661 /* hwrm_vnic_qcaps_output (size:192b/24B) */
16662 struct hwrm_vnic_qcaps_output {
16663 /* The specific error status for the command. */
16664 uint16_t error_code;
16665 /* The HWRM command request type. */
16667 /* The sequence ID from the original command. */
16669 /* The length of the response data in number of bytes. */
16671 /* The maximum receive unit that is settable on a vnic. */
16673 uint8_t unused_0[2];
16676 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
16679 * When this bit is '1', the capability of stripping VLAN in
16680 * the RX path is supported on VNIC(s).
16681 * If set to '0', then VLAN stripping capability is
16682 * not supported on VNIC(s).
16684 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
16687 * When this bit is '1', the capability to buffer receive
16688 * packets in the hardware until the host posts new receive buffers
16689 * is supported on VNIC(s).
16690 * If set to '0', then bd_stall capability is not supported
16693 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
16696 * When this bit is '1', the capability to
16697 * receive both RoCE and non-RoCE traffic on VNIC(s) is
16699 * If set to '0', then the capability to receive
16700 * both RoCE and non-RoCE traffic on VNIC(s) is
16703 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
16706 * When this bit is set to '1', the capability to configure
16707 * a VNIC to receive only RoCE traffic is supported.
16708 * When this flag is set to '0', the VNIC capability to
16709 * configure to receive only RoCE traffic is not supported.
16711 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
16714 * When this bit is set to '1', then the capability to enable
16715 * a VNIC in a mode where RSS context without configuring
16716 * RSS indirection table is supported (for RSS hash computation).
16717 * When this bit is set to '0', then a VNIC can not be configured
16718 * with a mode to enable RSS context without configuring RSS
16719 * indirection table.
16721 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
16724 * When this bit is '1', the capability to
16725 * mirror the the RoCE traffic is supported.
16726 * If set to '0', then the capability to mirror the
16727 * RoCE traffic is not supported.
16729 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
16732 * When this bit is '1', the outermost RSS hashing capability
16733 * is supported. If set to '0', then the outermost RSS hashing
16734 * capability is not supported.
16736 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
16738 uint8_t unused_1[7];
16740 * This field is used in Output records to indicate that the output
16741 * is completely written to RAM. This field should be read as '1'
16742 * to indicate that the output has been completely written.
16743 * When writing a command completion or response to an internal processor,
16744 * the order of writes has to be such that this field is written last.
16747 } __attribute__((packed));
16749 /*********************
16750 * hwrm_vnic_tpa_cfg *
16751 *********************/
16754 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
16755 struct hwrm_vnic_tpa_cfg_input {
16756 /* The HWRM command request type. */
16759 * The completion ring to send the completion event on. This should
16760 * be the NQ ID returned from the `nq_alloc` HWRM command.
16762 uint16_t cmpl_ring;
16764 * The sequence ID is used by the driver for tracking multiple
16765 * commands. This ID is treated as opaque data by the firmware and
16766 * the value is returned in the `hwrm_resp_hdr` upon completion.
16770 * The target ID of the command:
16771 * * 0x0-0xFFF8 - The function ID
16772 * * 0xFFF8-0xFFFE - Reserved for internal processors
16775 uint16_t target_id;
16777 * A physical address pointer pointing to a host buffer that the
16778 * command's response data will be written. This can be either a host
16779 * physical address (HPA) or a guest physical address (GPA) and must
16780 * point to a physically contiguous block of memory.
16782 uint64_t resp_addr;
16785 * When this bit is '1', the VNIC shall be configured to
16786 * perform transparent packet aggregation (TPA) of
16787 * non-tunneled TCP packets.
16789 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
16792 * When this bit is '1', the VNIC shall be configured to
16793 * perform transparent packet aggregation (TPA) of
16794 * tunneled TCP packets.
16796 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
16799 * When this bit is '1', the VNIC shall be configured to
16800 * perform transparent packet aggregation (TPA) according
16801 * to Windows Receive Segment Coalescing (RSC) rules.
16803 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
16806 * When this bit is '1', the VNIC shall be configured to
16807 * perform transparent packet aggregation (TPA) according
16808 * to Linux Generic Receive Offload (GRO) rules.
16810 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
16813 * When this bit is '1', the VNIC shall be configured to
16814 * perform transparent packet aggregation (TPA) for TCP
16815 * packets with IP ECN set to non-zero.
16817 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
16820 * When this bit is '1', the VNIC shall be configured to
16821 * perform transparent packet aggregation (TPA) for
16822 * GRE tunneled TCP packets only if all packets have the
16823 * same GRE sequence.
16825 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
16828 * When this bit is '1' and the GRO mode is enabled,
16829 * the VNIC shall be configured to
16830 * perform transparent packet aggregation (TPA) for
16831 * TCP/IPv4 packets with consecutively increasing IPIDs.
16832 * In other words, the last packet that is being
16833 * aggregated to an already existing aggregation context
16834 * shall have IPID 1 more than the IPID of the last packet
16835 * that was aggregated in that aggregation context.
16837 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
16840 * When this bit is '1' and the GRO mode is enabled,
16841 * the VNIC shall be configured to
16842 * perform transparent packet aggregation (TPA) for
16843 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
16846 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
16850 * This bit must be '1' for the max_agg_segs field to be
16853 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
16855 * This bit must be '1' for the max_aggs field to be
16858 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
16860 * This bit must be '1' for the max_agg_timer field to be
16863 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
16865 * This bit must be '1' for the min_agg_len field to be
16868 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
16869 /* Logical vnic ID */
16872 * This is the maximum number of TCP segments that can
16873 * be aggregated (unit is Log2). Max value is 31.
16875 uint16_t max_agg_segs;
16877 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
16879 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
16881 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
16883 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
16884 /* Any segment size larger than this is not valid */
16885 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
16886 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
16887 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
16889 * This is the maximum number of aggregations this VNIC is
16890 * allowed (unit is Log2). Max value is 7
16893 /* 1 aggregation */
16894 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
16895 /* 2 aggregations */
16896 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
16897 /* 4 aggregations */
16898 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
16899 /* 8 aggregations */
16900 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
16901 /* 16 aggregations */
16902 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
16903 /* Any aggregation size larger than this is not valid */
16904 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
16905 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
16906 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
16907 uint8_t unused_0[2];
16909 * This is the maximum amount of time allowed for
16910 * an aggregation context to complete after it was initiated.
16912 uint32_t max_agg_timer;
16914 * This is the minimum amount of payload length required to
16915 * start an aggregation context.
16917 uint32_t min_agg_len;
16918 } __attribute__((packed));
16920 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
16921 struct hwrm_vnic_tpa_cfg_output {
16922 /* The specific error status for the command. */
16923 uint16_t error_code;
16924 /* The HWRM command request type. */
16926 /* The sequence ID from the original command. */
16928 /* The length of the response data in number of bytes. */
16930 uint8_t unused_0[7];
16932 * This field is used in Output records to indicate that the output
16933 * is completely written to RAM. This field should be read as '1'
16934 * to indicate that the output has been completely written.
16935 * When writing a command completion or response to an internal processor,
16936 * the order of writes has to be such that this field is written last.
16939 } __attribute__((packed));
16941 /**********************
16942 * hwrm_vnic_tpa_qcfg *
16943 **********************/
16946 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
16947 struct hwrm_vnic_tpa_qcfg_input {
16948 /* The HWRM command request type. */
16951 * The completion ring to send the completion event on. This should
16952 * be the NQ ID returned from the `nq_alloc` HWRM command.
16954 uint16_t cmpl_ring;
16956 * The sequence ID is used by the driver for tracking multiple
16957 * commands. This ID is treated as opaque data by the firmware and
16958 * the value is returned in the `hwrm_resp_hdr` upon completion.
16962 * The target ID of the command:
16963 * * 0x0-0xFFF8 - The function ID
16964 * * 0xFFF8-0xFFFE - Reserved for internal processors
16967 uint16_t target_id;
16969 * A physical address pointer pointing to a host buffer that the
16970 * command's response data will be written. This can be either a host
16971 * physical address (HPA) or a guest physical address (GPA) and must
16972 * point to a physically contiguous block of memory.
16974 uint64_t resp_addr;
16975 /* Logical vnic ID */
16977 uint8_t unused_0[6];
16978 } __attribute__((packed));
16980 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
16981 struct hwrm_vnic_tpa_qcfg_output {
16982 /* The specific error status for the command. */
16983 uint16_t error_code;
16984 /* The HWRM command request type. */
16986 /* The sequence ID from the original command. */
16988 /* The length of the response data in number of bytes. */
16992 * When this bit is '1', the VNIC is configured to
16993 * perform transparent packet aggregation (TPA) of
16994 * non-tunneled TCP packets.
16996 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \
16999 * When this bit is '1', the VNIC is configured to
17000 * perform transparent packet aggregation (TPA) of
17001 * tunneled TCP packets.
17003 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \
17006 * When this bit is '1', the VNIC is configured to
17007 * perform transparent packet aggregation (TPA) according
17008 * to Windows Receive Segment Coalescing (RSC) rules.
17010 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \
17013 * When this bit is '1', the VNIC is configured to
17014 * perform transparent packet aggregation (TPA) according
17015 * to Linux Generic Receive Offload (GRO) rules.
17017 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \
17020 * When this bit is '1', the VNIC is configured to
17021 * perform transparent packet aggregation (TPA) for TCP
17022 * packets with IP ECN set to non-zero.
17024 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \
17027 * When this bit is '1', the VNIC is configured to
17028 * perform transparent packet aggregation (TPA) for
17029 * GRE tunneled TCP packets only if all packets have the
17030 * same GRE sequence.
17032 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
17035 * When this bit is '1' and the GRO mode is enabled,
17036 * the VNIC is configured to
17037 * perform transparent packet aggregation (TPA) for
17038 * TCP/IPv4 packets with consecutively increasing IPIDs.
17039 * In other words, the last packet that is being
17040 * aggregated to an already existing aggregation context
17041 * shall have IPID 1 more than the IPID of the last packet
17042 * that was aggregated in that aggregation context.
17044 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \
17047 * When this bit is '1' and the GRO mode is enabled,
17048 * the VNIC is configured to
17049 * perform transparent packet aggregation (TPA) for
17050 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
17053 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \
17056 * This is the maximum number of TCP segments that can
17057 * be aggregated (unit is Log2). Max value is 31.
17059 uint16_t max_agg_segs;
17061 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
17063 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
17065 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
17067 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
17068 /* Any segment size larger than this is not valid */
17069 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
17070 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \
17071 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX
17073 * This is the maximum number of aggregations this VNIC is
17074 * allowed (unit is Log2). Max value is 7
17077 /* 1 aggregation */
17078 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
17079 /* 2 aggregations */
17080 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
17081 /* 4 aggregations */
17082 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
17083 /* 8 aggregations */
17084 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
17085 /* 16 aggregations */
17086 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
17087 /* Any aggregation size larger than this is not valid */
17088 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
17089 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \
17090 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX
17092 * This is the maximum amount of time allowed for
17093 * an aggregation context to complete after it was initiated.
17095 uint32_t max_agg_timer;
17097 * This is the minimum amount of payload length required to
17098 * start an aggregation context.
17100 uint32_t min_agg_len;
17101 uint8_t unused_0[7];
17103 * This field is used in Output records to indicate that the output
17104 * is completely written to RAM. This field should be read as '1'
17105 * to indicate that the output has been completely written.
17106 * When writing a command completion or response to an internal processor,
17107 * the order of writes has to be such that this field is written last.
17110 } __attribute__((packed));
17112 /*********************
17113 * hwrm_vnic_rss_cfg *
17114 *********************/
17117 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
17118 struct hwrm_vnic_rss_cfg_input {
17119 /* The HWRM command request type. */
17122 * The completion ring to send the completion event on. This should
17123 * be the NQ ID returned from the `nq_alloc` HWRM command.
17125 uint16_t cmpl_ring;
17127 * The sequence ID is used by the driver for tracking multiple
17128 * commands. This ID is treated as opaque data by the firmware and
17129 * the value is returned in the `hwrm_resp_hdr` upon completion.
17133 * The target ID of the command:
17134 * * 0x0-0xFFF8 - The function ID
17135 * * 0xFFF8-0xFFFE - Reserved for internal processors
17138 uint16_t target_id;
17140 * A physical address pointer pointing to a host buffer that the
17141 * command's response data will be written. This can be either a host
17142 * physical address (HPA) or a guest physical address (GPA) and must
17143 * point to a physically contiguous block of memory.
17145 uint64_t resp_addr;
17146 uint32_t hash_type;
17148 * When this bit is '1', the RSS hash shall be computed
17149 * over source and destination IPv4 addresses of IPv4
17152 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
17154 * When this bit is '1', the RSS hash shall be computed
17155 * over source/destination IPv4 addresses and
17156 * source/destination ports of TCP/IPv4 packets.
17158 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
17160 * When this bit is '1', the RSS hash shall be computed
17161 * over source/destination IPv4 addresses and
17162 * source/destination ports of UDP/IPv4 packets.
17164 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
17166 * When this bit is '1', the RSS hash shall be computed
17167 * over source and destination IPv4 addresses of IPv6
17170 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
17172 * When this bit is '1', the RSS hash shall be computed
17173 * over source/destination IPv6 addresses and
17174 * source/destination ports of TCP/IPv6 packets.
17176 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
17178 * When this bit is '1', the RSS hash shall be computed
17179 * over source/destination IPv6 addresses and
17180 * source/destination ports of UDP/IPv6 packets.
17182 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
17183 /* VNIC ID of VNIC associated with RSS table being configured. */
17186 * Specifies which VNIC ring table pair to configure.
17187 * Valid values range from 0 to 7.
17189 uint8_t ring_table_pair_index;
17190 /* Flags to specify different RSS hash modes. */
17191 uint8_t hash_mode_flags;
17193 * When this bit is '1', it indicates using current RSS
17194 * hash mode setting configured in the device.
17196 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
17199 * When this bit is '1', it indicates requesting support of
17200 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
17201 * l4.src, l4.dest} for tunnel packets. For none-tunnel
17202 * packets, the RSS hash is computed over the normal
17203 * src/dest l3 and src/dest l4 headers.
17205 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
17208 * When this bit is '1', it indicates requesting support of
17209 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
17210 * tunnel packets. For none-tunnel packets, the RSS hash is
17211 * computed over the normal src/dest l3 headers.
17213 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
17216 * When this bit is '1', it indicates requesting support of
17217 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
17218 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
17219 * packets, the RSS hash is computed over the normal
17220 * src/dest l3 and src/dest l4 headers.
17222 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
17225 * When this bit is '1', it indicates requesting support of
17226 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
17227 * tunnel packets. For none-tunnel packets, the RSS hash is
17228 * computed over the normal src/dest l3 headers.
17230 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
17232 /* This is the address for rss ring group table */
17233 uint64_t ring_grp_tbl_addr;
17234 /* This is the address for rss hash key table */
17235 uint64_t hash_key_tbl_addr;
17236 /* Index to the rss indirection table. */
17237 uint16_t rss_ctx_idx;
17238 uint8_t unused_1[6];
17239 } __attribute__((packed));
17241 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
17242 struct hwrm_vnic_rss_cfg_output {
17243 /* The specific error status for the command. */
17244 uint16_t error_code;
17245 /* The HWRM command request type. */
17247 /* The sequence ID from the original command. */
17249 /* The length of the response data in number of bytes. */
17251 uint8_t unused_0[7];
17253 * This field is used in Output records to indicate that the output
17254 * is completely written to RAM. This field should be read as '1'
17255 * to indicate that the output has been completely written.
17256 * When writing a command completion or response to an internal processor,
17257 * the order of writes has to be such that this field is written last.
17260 } __attribute__((packed));
17262 /**********************
17263 * hwrm_vnic_rss_qcfg *
17264 **********************/
17267 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
17268 struct hwrm_vnic_rss_qcfg_input {
17269 /* The HWRM command request type. */
17272 * The completion ring to send the completion event on. This should
17273 * be the NQ ID returned from the `nq_alloc` HWRM command.
17275 uint16_t cmpl_ring;
17277 * The sequence ID is used by the driver for tracking multiple
17278 * commands. This ID is treated as opaque data by the firmware and
17279 * the value is returned in the `hwrm_resp_hdr` upon completion.
17283 * The target ID of the command:
17284 * * 0x0-0xFFF8 - The function ID
17285 * * 0xFFF8-0xFFFE - Reserved for internal processors
17288 uint16_t target_id;
17290 * A physical address pointer pointing to a host buffer that the
17291 * command's response data will be written. This can be either a host
17292 * physical address (HPA) or a guest physical address (GPA) and must
17293 * point to a physically contiguous block of memory.
17295 uint64_t resp_addr;
17296 /* Index to the rss indirection table. */
17297 uint16_t rss_ctx_idx;
17298 uint8_t unused_0[6];
17299 } __attribute__((packed));
17301 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
17302 struct hwrm_vnic_rss_qcfg_output {
17303 /* The specific error status for the command. */
17304 uint16_t error_code;
17305 /* The HWRM command request type. */
17307 /* The sequence ID from the original command. */
17309 /* The length of the response data in number of bytes. */
17311 uint32_t hash_type;
17313 * When this bit is '1', the RSS hash shall be computed
17314 * over source and destination IPv4 addresses of IPv4
17317 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
17319 * When this bit is '1', the RSS hash shall be computed
17320 * over source/destination IPv4 addresses and
17321 * source/destination ports of TCP/IPv4 packets.
17323 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
17325 * When this bit is '1', the RSS hash shall be computed
17326 * over source/destination IPv4 addresses and
17327 * source/destination ports of UDP/IPv4 packets.
17329 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
17331 * When this bit is '1', the RSS hash shall be computed
17332 * over source and destination IPv4 addresses of IPv6
17335 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
17337 * When this bit is '1', the RSS hash shall be computed
17338 * over source/destination IPv6 addresses and
17339 * source/destination ports of TCP/IPv6 packets.
17341 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
17343 * When this bit is '1', the RSS hash shall be computed
17344 * over source/destination IPv6 addresses and
17345 * source/destination ports of UDP/IPv6 packets.
17347 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
17348 uint8_t unused_0[4];
17349 /* This is the value of rss hash key */
17350 uint32_t hash_key[10];
17351 /* Flags to specify different RSS hash modes. */
17352 uint8_t hash_mode_flags;
17354 * When this bit is '1', it indicates using current RSS
17355 * hash mode setting configured in the device.
17357 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
17360 * When this bit is '1', it indicates requesting support of
17361 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
17362 * l4.src, l4.dest} for tunnel packets. For none-tunnel
17363 * packets, the RSS hash is computed over the normal
17364 * src/dest l3 and src/dest l4 headers.
17366 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
17369 * When this bit is '1', it indicates requesting support of
17370 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
17371 * tunnel packets. For none-tunnel packets, the RSS hash is
17372 * computed over the normal src/dest l3 headers.
17374 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
17377 * When this bit is '1', it indicates requesting support of
17378 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
17379 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
17380 * packets, the RSS hash is computed over the normal
17381 * src/dest l3 and src/dest l4 headers.
17383 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
17386 * When this bit is '1', it indicates requesting support of
17387 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
17388 * tunnel packets. For none-tunnel packets, the RSS hash is
17389 * computed over the normal src/dest l3 headers.
17391 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
17393 uint8_t unused_1[6];
17395 * This field is used in Output records to indicate that the output
17396 * is completely written to RAM. This field should be read as '1'
17397 * to indicate that the output has been completely written.
17398 * When writing a command completion or response to an internal processor,
17399 * the order of writes has to be such that this field is written last.
17402 } __attribute__((packed));
17404 /**************************
17405 * hwrm_vnic_plcmodes_cfg *
17406 **************************/
17409 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
17410 struct hwrm_vnic_plcmodes_cfg_input {
17411 /* The HWRM command request type. */
17414 * The completion ring to send the completion event on. This should
17415 * be the NQ ID returned from the `nq_alloc` HWRM command.
17417 uint16_t cmpl_ring;
17419 * The sequence ID is used by the driver for tracking multiple
17420 * commands. This ID is treated as opaque data by the firmware and
17421 * the value is returned in the `hwrm_resp_hdr` upon completion.
17425 * The target ID of the command:
17426 * * 0x0-0xFFF8 - The function ID
17427 * * 0xFFF8-0xFFFE - Reserved for internal processors
17430 uint16_t target_id;
17432 * A physical address pointer pointing to a host buffer that the
17433 * command's response data will be written. This can be either a host
17434 * physical address (HPA) or a guest physical address (GPA) and must
17435 * point to a physically contiguous block of memory.
17437 uint64_t resp_addr;
17440 * When this bit is '1', the VNIC shall be configured to
17441 * use regular placement algorithm.
17442 * By default, the regular placement algorithm shall be
17443 * enabled on the VNIC.
17445 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
17448 * When this bit is '1', the VNIC shall be configured
17449 * use the jumbo placement algorithm.
17451 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
17454 * When this bit is '1', the VNIC shall be configured
17455 * to enable Header-Data split for IPv4 packets according
17456 * to the following rules:
17457 * # If the packet is identified as TCP/IPv4, then the
17458 * packet is split at the beginning of the TCP payload.
17459 * # If the packet is identified as UDP/IPv4, then the
17460 * packet is split at the beginning of UDP payload.
17461 * # If the packet is identified as non-TCP and non-UDP
17462 * IPv4 packet, then the packet is split at the beginning
17463 * of the upper layer protocol header carried in the IPv4
17466 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
17469 * When this bit is '1', the VNIC shall be configured
17470 * to enable Header-Data split for IPv6 packets according
17471 * to the following rules:
17472 * # If the packet is identified as TCP/IPv6, then the
17473 * packet is split at the beginning of the TCP payload.
17474 * # If the packet is identified as UDP/IPv6, then the
17475 * packet is split at the beginning of UDP payload.
17476 * # If the packet is identified as non-TCP and non-UDP
17477 * IPv6 packet, then the packet is split at the beginning
17478 * of the upper layer protocol header carried in the IPv6
17481 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
17484 * When this bit is '1', the VNIC shall be configured
17485 * to enable Header-Data split for FCoE packets at the
17486 * beginning of FC payload.
17488 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
17491 * When this bit is '1', the VNIC shall be configured
17492 * to enable Header-Data split for RoCE packets at the
17493 * beginning of RoCE payload (after BTH/GRH headers).
17495 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
17499 * This bit must be '1' for the jumbo_thresh_valid field to be
17502 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
17505 * This bit must be '1' for the hds_offset_valid field to be
17508 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
17511 * This bit must be '1' for the hds_threshold_valid field to be
17514 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
17516 /* Logical vnic ID */
17519 * When jumbo placement algorithm is enabled, this value
17520 * is used to determine the threshold for jumbo placement.
17521 * Packets with length larger than this value will be
17522 * placed according to the jumbo placement algorithm.
17524 uint16_t jumbo_thresh;
17526 * This value is used to determine the offset into
17527 * packet buffer where the split data (payload) will be
17528 * placed according to one of of HDS placement algorithm.
17530 * The lengths of packet buffers provided for split data
17531 * shall be larger than this value.
17533 uint16_t hds_offset;
17535 * When one of the HDS placement algorithm is enabled, this
17536 * value is used to determine the threshold for HDS
17538 * Packets with length larger than this value will be
17539 * placed according to the HDS placement algorithm.
17540 * This value shall be in multiple of 4 bytes.
17542 uint16_t hds_threshold;
17543 uint8_t unused_0[6];
17544 } __attribute__((packed));
17546 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
17547 struct hwrm_vnic_plcmodes_cfg_output {
17548 /* The specific error status for the command. */
17549 uint16_t error_code;
17550 /* The HWRM command request type. */
17552 /* The sequence ID from the original command. */
17554 /* The length of the response data in number of bytes. */
17556 uint8_t unused_0[7];
17558 * This field is used in Output records to indicate that the output
17559 * is completely written to RAM. This field should be read as '1'
17560 * to indicate that the output has been completely written.
17561 * When writing a command completion or response to an internal processor,
17562 * the order of writes has to be such that this field is written last.
17565 } __attribute__((packed));
17567 /***************************
17568 * hwrm_vnic_plcmodes_qcfg *
17569 ***************************/
17572 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
17573 struct hwrm_vnic_plcmodes_qcfg_input {
17574 /* The HWRM command request type. */
17577 * The completion ring to send the completion event on. This should
17578 * be the NQ ID returned from the `nq_alloc` HWRM command.
17580 uint16_t cmpl_ring;
17582 * The sequence ID is used by the driver for tracking multiple
17583 * commands. This ID is treated as opaque data by the firmware and
17584 * the value is returned in the `hwrm_resp_hdr` upon completion.
17588 * The target ID of the command:
17589 * * 0x0-0xFFF8 - The function ID
17590 * * 0xFFF8-0xFFFE - Reserved for internal processors
17593 uint16_t target_id;
17595 * A physical address pointer pointing to a host buffer that the
17596 * command's response data will be written. This can be either a host
17597 * physical address (HPA) or a guest physical address (GPA) and must
17598 * point to a physically contiguous block of memory.
17600 uint64_t resp_addr;
17601 /* Logical vnic ID */
17603 uint8_t unused_0[4];
17604 } __attribute__((packed));
17606 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
17607 struct hwrm_vnic_plcmodes_qcfg_output {
17608 /* The specific error status for the command. */
17609 uint16_t error_code;
17610 /* The HWRM command request type. */
17612 /* The sequence ID from the original command. */
17614 /* The length of the response data in number of bytes. */
17618 * When this bit is '1', the VNIC is configured to
17619 * use regular placement algorithm.
17621 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
17624 * When this bit is '1', the VNIC is configured to
17625 * use the jumbo placement algorithm.
17627 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
17630 * When this bit is '1', the VNIC is configured
17631 * to enable Header-Data split for IPv4 packets.
17633 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
17636 * When this bit is '1', the VNIC is configured
17637 * to enable Header-Data split for IPv6 packets.
17639 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
17642 * When this bit is '1', the VNIC is configured
17643 * to enable Header-Data split for FCoE packets.
17645 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
17648 * When this bit is '1', the VNIC is configured
17649 * to enable Header-Data split for RoCE packets.
17651 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
17654 * When this bit is '1', the VNIC is configured
17655 * to be the default VNIC of the requesting function.
17657 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
17660 * When jumbo placement algorithm is enabled, this value
17661 * is used to determine the threshold for jumbo placement.
17662 * Packets with length larger than this value will be
17663 * placed according to the jumbo placement algorithm.
17665 uint16_t jumbo_thresh;
17667 * This value is used to determine the offset into
17668 * packet buffer where the split data (payload) will be
17669 * placed according to one of of HDS placement algorithm.
17671 * The lengths of packet buffers provided for split data
17672 * shall be larger than this value.
17674 uint16_t hds_offset;
17676 * When one of the HDS placement algorithm is enabled, this
17677 * value is used to determine the threshold for HDS
17679 * Packets with length larger than this value will be
17680 * placed according to the HDS placement algorithm.
17681 * This value shall be in multiple of 4 bytes.
17683 uint16_t hds_threshold;
17684 uint8_t unused_0[5];
17686 * This field is used in Output records to indicate that the output
17687 * is completely written to RAM. This field should be read as '1'
17688 * to indicate that the output has been completely written.
17689 * When writing a command completion or response to an internal processor,
17690 * the order of writes has to be such that this field is written last.
17693 } __attribute__((packed));
17695 /**********************************
17696 * hwrm_vnic_rss_cos_lb_ctx_alloc *
17697 **********************************/
17700 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
17701 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
17702 /* The HWRM command request type. */
17705 * The completion ring to send the completion event on. This should
17706 * be the NQ ID returned from the `nq_alloc` HWRM command.
17708 uint16_t cmpl_ring;
17710 * The sequence ID is used by the driver for tracking multiple
17711 * commands. This ID is treated as opaque data by the firmware and
17712 * the value is returned in the `hwrm_resp_hdr` upon completion.
17716 * The target ID of the command:
17717 * * 0x0-0xFFF8 - The function ID
17718 * * 0xFFF8-0xFFFE - Reserved for internal processors
17721 uint16_t target_id;
17723 * A physical address pointer pointing to a host buffer that the
17724 * command's response data will be written. This can be either a host
17725 * physical address (HPA) or a guest physical address (GPA) and must
17726 * point to a physically contiguous block of memory.
17728 uint64_t resp_addr;
17729 } __attribute__((packed));
17731 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
17732 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
17733 /* The specific error status for the command. */
17734 uint16_t error_code;
17735 /* The HWRM command request type. */
17737 /* The sequence ID from the original command. */
17739 /* The length of the response data in number of bytes. */
17741 /* rss_cos_lb_ctx_id is 16 b */
17742 uint16_t rss_cos_lb_ctx_id;
17743 uint8_t unused_0[5];
17745 * This field is used in Output records to indicate that the output
17746 * is completely written to RAM. This field should be read as '1'
17747 * to indicate that the output has been completely written.
17748 * When writing a command completion or response to an internal processor,
17749 * the order of writes has to be such that this field is written last.
17752 } __attribute__((packed));
17754 /*********************************
17755 * hwrm_vnic_rss_cos_lb_ctx_free *
17756 *********************************/
17759 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
17760 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
17761 /* The HWRM command request type. */
17764 * The completion ring to send the completion event on. This should
17765 * be the NQ ID returned from the `nq_alloc` HWRM command.
17767 uint16_t cmpl_ring;
17769 * The sequence ID is used by the driver for tracking multiple
17770 * commands. This ID is treated as opaque data by the firmware and
17771 * the value is returned in the `hwrm_resp_hdr` upon completion.
17775 * The target ID of the command:
17776 * * 0x0-0xFFF8 - The function ID
17777 * * 0xFFF8-0xFFFE - Reserved for internal processors
17780 uint16_t target_id;
17782 * A physical address pointer pointing to a host buffer that the
17783 * command's response data will be written. This can be either a host
17784 * physical address (HPA) or a guest physical address (GPA) and must
17785 * point to a physically contiguous block of memory.
17787 uint64_t resp_addr;
17788 /* rss_cos_lb_ctx_id is 16 b */
17789 uint16_t rss_cos_lb_ctx_id;
17790 uint8_t unused_0[6];
17791 } __attribute__((packed));
17793 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
17794 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
17795 /* The specific error status for the command. */
17796 uint16_t error_code;
17797 /* The HWRM command request type. */
17799 /* The sequence ID from the original command. */
17801 /* The length of the response data in number of bytes. */
17803 uint8_t unused_0[7];
17805 * This field is used in Output records to indicate that the output
17806 * is completely written to RAM. This field should be read as '1'
17807 * to indicate that the output has been completely written.
17808 * When writing a command completion or response to an internal processor,
17809 * the order of writes has to be such that this field is written last.
17812 } __attribute__((packed));
17814 /*******************
17815 * hwrm_ring_alloc *
17816 *******************/
17819 /* hwrm_ring_alloc_input (size:640b/80B) */
17820 struct hwrm_ring_alloc_input {
17821 /* The HWRM command request type. */
17824 * The completion ring to send the completion event on. This should
17825 * be the NQ ID returned from the `nq_alloc` HWRM command.
17827 uint16_t cmpl_ring;
17829 * The sequence ID is used by the driver for tracking multiple
17830 * commands. This ID is treated as opaque data by the firmware and
17831 * the value is returned in the `hwrm_resp_hdr` upon completion.
17835 * The target ID of the command:
17836 * * 0x0-0xFFF8 - The function ID
17837 * * 0xFFF8-0xFFFE - Reserved for internal processors
17840 uint16_t target_id;
17842 * A physical address pointer pointing to a host buffer that the
17843 * command's response data will be written. This can be either a host
17844 * physical address (HPA) or a guest physical address (GPA) and must
17845 * point to a physically contiguous block of memory.
17847 uint64_t resp_addr;
17850 * This bit must be '1' for the ring_arb_cfg field to be
17853 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
17856 * This bit must be '1' for the stat_ctx_id_valid field to be
17859 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
17862 * This bit must be '1' for the max_bw_valid field to be
17865 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
17868 * This bit must be '1' for the rx_ring_id field to be
17871 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
17874 * This bit must be '1' for the nq_ring_id field to be
17877 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
17880 * This bit must be '1' for the rx_buf_size field to be
17883 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
17887 /* L2 Completion Ring (CR) */
17888 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
17890 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
17892 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
17893 /* RoCE Notification Completion Ring (ROCE_CR) */
17894 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
17895 /* RX Aggregation Ring */
17896 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
17897 /* Notification Queue */
17898 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
17899 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
17900 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
17901 uint8_t unused_0[3];
17903 * This value is a pointer to the page table for the
17906 uint64_t page_tbl_addr;
17907 /* First Byte Offset of the first entry in the first page. */
17910 * Actual page size in 2^page_size. The supported range is increments
17911 * in powers of 2 from 16 bytes to 1GB.
17913 * Page size is 16 B.
17915 * Page size is 4 KB.
17917 * Page size is 8 KB.
17919 * Page size is 64 KB.
17921 * Page size is 2 MB.
17923 * Page size is 4 MB.
17925 * Page size is 1 GB.
17929 * This value indicates the depth of page table.
17930 * For this version of the specification, value other than 0 or
17931 * 1 shall be considered as an invalid value.
17932 * When the page_tbl_depth = 0, then it is treated as a
17933 * special case with the following.
17934 * 1. FBO and page size fields are not valid.
17935 * 2. page_tbl_addr is the physical address of the first
17936 * element of the ring.
17938 uint8_t page_tbl_depth;
17939 uint8_t unused_1[2];
17941 * Number of 16B units in the ring. Minimum size for
17942 * a ring is 16 16B entries.
17946 * Logical ring number for the ring to be allocated.
17947 * This value determines the position in the doorbell
17948 * area where the update to the ring will be made.
17950 * For completion rings, this value is also the MSI-X
17951 * vector number for the function the completion ring is
17954 uint16_t logical_id;
17956 * This field is used only when ring_type is a TX ring.
17957 * This value indicates what completion ring the TX ring
17958 * is associated with.
17960 uint16_t cmpl_ring_id;
17962 * This field is used only when ring_type is a TX ring.
17963 * This value indicates what CoS queue the TX ring
17964 * is associated with.
17968 * When allocating a Rx ring or Rx aggregation ring, this field
17969 * specifies the size of the buffer descriptors posted to the ring.
17971 uint16_t rx_buf_size;
17973 * When allocating an Rx aggregation ring, this field
17974 * specifies the associated Rx ring ID.
17976 uint16_t rx_ring_id;
17978 * When allocating a completion ring, this field
17979 * specifies the associated NQ ring ID.
17981 uint16_t nq_ring_id;
17983 * This field is used only when ring_type is a TX ring.
17984 * This field is used to configure arbitration related
17985 * parameters for a TX ring.
17987 uint16_t ring_arb_cfg;
17988 /* Arbitration policy used for the ring. */
17989 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
17991 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
17993 * Use strict priority for the TX ring.
17994 * Priority value is specified in arb_policy_param
17996 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
17999 * Use weighted fair queue arbitration for the TX ring.
18000 * Weight is specified in arb_policy_param
18002 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
18004 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
18005 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
18006 /* Reserved field. */
18007 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
18009 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
18011 * Arbitration policy specific parameter.
18012 * # For strict priority arbitration policy, this field
18013 * represents a priority value. If set to 0, then the priority
18014 * is not specified and the HWRM is allowed to select
18015 * any priority for this TX ring.
18016 * # For weighted fair queue arbitration policy, this field
18017 * represents a weight value. If set to 0, then the weight
18018 * is not specified and the HWRM is allowed to select
18019 * any weight for this TX ring.
18021 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
18023 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
18026 * This field is reserved for the future use.
18027 * It shall be set to 0.
18029 uint32_t reserved3;
18031 * This field is used only when ring_type is a TX ring.
18032 * This input indicates what statistics context this ring
18033 * should be associated with.
18035 uint32_t stat_ctx_id;
18037 * This field is reserved for the future use.
18038 * It shall be set to 0.
18040 uint32_t reserved4;
18042 * This field is used only when ring_type is a TX ring
18043 * to specify maximum BW allocated to the TX ring.
18044 * The HWRM will translate this value into byte counter and
18045 * time interval used for this ring inside the device.
18048 /* The bandwidth value. */
18049 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
18050 UINT32_C(0xfffffff)
18051 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
18052 /* The granularity of the value (bits or bytes). */
18053 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
18054 UINT32_C(0x10000000)
18055 /* Value is in bits. */
18056 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
18057 (UINT32_C(0x0) << 28)
18058 /* Value is in bytes. */
18059 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
18060 (UINT32_C(0x1) << 28)
18061 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
18062 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
18063 /* bw_value_unit is 3 b */
18064 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
18065 UINT32_C(0xe0000000)
18066 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
18067 /* Value is in Mb or MB (base 10). */
18068 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
18069 (UINT32_C(0x0) << 29)
18070 /* Value is in Kb or KB (base 10). */
18071 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
18072 (UINT32_C(0x2) << 29)
18073 /* Value is in bits or bytes. */
18074 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
18075 (UINT32_C(0x4) << 29)
18076 /* Value is in Gb or GB (base 10). */
18077 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
18078 (UINT32_C(0x6) << 29)
18079 /* Value is in 1/100th of a percentage of total bandwidth. */
18080 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18081 (UINT32_C(0x1) << 29)
18083 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
18084 (UINT32_C(0x7) << 29)
18085 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
18086 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
18088 * This field is used only when ring_type is a Completion ring.
18089 * This value indicates what interrupt mode should be used
18090 * on this completion ring.
18091 * Note: In the legacy interrupt mode, no more than 16
18092 * completion rings are allowed.
18096 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
18098 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
18100 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
18101 /* No Interrupt - Polled mode */
18102 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
18103 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
18104 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
18105 uint8_t unused_4[3];
18106 } __attribute__((packed));
18108 /* hwrm_ring_alloc_output (size:128b/16B) */
18109 struct hwrm_ring_alloc_output {
18110 /* The specific error status for the command. */
18111 uint16_t error_code;
18112 /* The HWRM command request type. */
18114 /* The sequence ID from the original command. */
18116 /* The length of the response data in number of bytes. */
18119 * Physical number of ring allocated.
18120 * This value shall be unique for a ring type.
18123 /* Logical number of ring allocated. */
18124 uint16_t logical_ring_id;
18125 uint8_t unused_0[3];
18127 * This field is used in Output records to indicate that the output
18128 * is completely written to RAM. This field should be read as '1'
18129 * to indicate that the output has been completely written.
18130 * When writing a command completion or response to an internal processor,
18131 * the order of writes has to be such that this field is written last.
18134 } __attribute__((packed));
18136 /******************
18138 ******************/
18141 /* hwrm_ring_free_input (size:192b/24B) */
18142 struct hwrm_ring_free_input {
18143 /* The HWRM command request type. */
18146 * The completion ring to send the completion event on. This should
18147 * be the NQ ID returned from the `nq_alloc` HWRM command.
18149 uint16_t cmpl_ring;
18151 * The sequence ID is used by the driver for tracking multiple
18152 * commands. This ID is treated as opaque data by the firmware and
18153 * the value is returned in the `hwrm_resp_hdr` upon completion.
18157 * The target ID of the command:
18158 * * 0x0-0xFFF8 - The function ID
18159 * * 0xFFF8-0xFFFE - Reserved for internal processors
18162 uint16_t target_id;
18164 * A physical address pointer pointing to a host buffer that the
18165 * command's response data will be written. This can be either a host
18166 * physical address (HPA) or a guest physical address (GPA) and must
18167 * point to a physically contiguous block of memory.
18169 uint64_t resp_addr;
18172 /* L2 Completion Ring (CR) */
18173 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
18175 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
18177 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
18178 /* RoCE Notification Completion Ring (ROCE_CR) */
18179 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
18180 /* RX Aggregation Ring */
18181 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
18182 /* Notification Queue */
18183 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
18184 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
18185 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
18187 /* Physical number of ring allocated. */
18189 uint8_t unused_1[4];
18190 } __attribute__((packed));
18192 /* hwrm_ring_free_output (size:128b/16B) */
18193 struct hwrm_ring_free_output {
18194 /* The specific error status for the command. */
18195 uint16_t error_code;
18196 /* The HWRM command request type. */
18198 /* The sequence ID from the original command. */
18200 /* The length of the response data in number of bytes. */
18202 uint8_t unused_0[7];
18204 * This field is used in Output records to indicate that the output
18205 * is completely written to RAM. This field should be read as '1'
18206 * to indicate that the output has been completely written.
18207 * When writing a command completion or response to an internal processor,
18208 * the order of writes has to be such that this field is written last.
18211 } __attribute__((packed));
18213 /**************************************
18214 * hwrm_ring_cmpl_ring_qaggint_params *
18215 **************************************/
18218 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
18219 struct hwrm_ring_cmpl_ring_qaggint_params_input {
18220 /* The HWRM command request type. */
18223 * The completion ring to send the completion event on. This should
18224 * be the NQ ID returned from the `nq_alloc` HWRM command.
18226 uint16_t cmpl_ring;
18228 * The sequence ID is used by the driver for tracking multiple
18229 * commands. This ID is treated as opaque data by the firmware and
18230 * the value is returned in the `hwrm_resp_hdr` upon completion.
18234 * The target ID of the command:
18235 * * 0x0-0xFFF8 - The function ID
18236 * * 0xFFF8-0xFFFE - Reserved for internal processors
18239 uint16_t target_id;
18241 * A physical address pointer pointing to a host buffer that the
18242 * command's response data will be written. This can be either a host
18243 * physical address (HPA) or a guest physical address (GPA) and must
18244 * point to a physically contiguous block of memory.
18246 uint64_t resp_addr;
18247 /* Physical number of completion ring. */
18249 uint8_t unused_0[6];
18250 } __attribute__((packed));
18252 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
18253 struct hwrm_ring_cmpl_ring_qaggint_params_output {
18254 /* The specific error status for the command. */
18255 uint16_t error_code;
18256 /* The HWRM command request type. */
18258 /* The sequence ID from the original command. */
18260 /* The length of the response data in number of bytes. */
18264 * When this bit is set to '1', interrupt max
18265 * timer is reset whenever a completion is received.
18267 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
18270 * When this bit is set to '1', ring idle mode
18271 * aggregation will be enabled.
18273 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
18276 * Number of completions to aggregate before DMA
18277 * during the normal mode.
18279 uint16_t num_cmpl_dma_aggr;
18281 * Number of completions to aggregate before DMA
18282 * during the interrupt mode.
18284 uint16_t num_cmpl_dma_aggr_during_int;
18286 * Timer in unit of 80-nsec used to aggregate completions before
18287 * DMA during the normal mode (not in interrupt mode).
18289 uint16_t cmpl_aggr_dma_tmr;
18291 * Timer in unit of 80-nsec used to aggregate completions before
18292 * DMA during the interrupt mode.
18294 uint16_t cmpl_aggr_dma_tmr_during_int;
18295 /* Minimum time (in unit of 80-nsec) between two interrupts. */
18296 uint16_t int_lat_tmr_min;
18298 * Maximum wait time (in unit of 80-nsec) spent aggregating
18299 * completions before signaling the interrupt after the
18300 * interrupt is enabled.
18302 uint16_t int_lat_tmr_max;
18304 * Minimum number of completions aggregated before signaling
18307 uint16_t num_cmpl_aggr_int;
18308 uint8_t unused_0[7];
18310 * This field is used in Output records to indicate that the output
18311 * is completely written to RAM. This field should be read as '1'
18312 * to indicate that the output has been completely written.
18313 * When writing a command completion or response to an internal processor,
18314 * the order of writes has to be such that this field is written last.
18317 } __attribute__((packed));
18319 /*****************************************
18320 * hwrm_ring_cmpl_ring_cfg_aggint_params *
18321 *****************************************/
18324 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
18325 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
18326 /* The HWRM command request type. */
18329 * The completion ring to send the completion event on. This should
18330 * be the NQ ID returned from the `nq_alloc` HWRM command.
18332 uint16_t cmpl_ring;
18334 * The sequence ID is used by the driver for tracking multiple
18335 * commands. This ID is treated as opaque data by the firmware and
18336 * the value is returned in the `hwrm_resp_hdr` upon completion.
18340 * The target ID of the command:
18341 * * 0x0-0xFFF8 - The function ID
18342 * * 0xFFF8-0xFFFE - Reserved for internal processors
18345 uint16_t target_id;
18347 * A physical address pointer pointing to a host buffer that the
18348 * command's response data will be written. This can be either a host
18349 * physical address (HPA) or a guest physical address (GPA) and must
18350 * point to a physically contiguous block of memory.
18352 uint64_t resp_addr;
18353 /* Physical number of completion ring. */
18357 * When this bit is set to '1', interrupt latency max
18358 * timer is reset whenever a completion is received.
18360 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
18363 * When this bit is set to '1', ring idle mode
18364 * aggregation will be enabled.
18366 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
18369 * Set this flag to 1 when configuring parameters on a
18370 * notification queue. Set this flag to 0 when configuring
18371 * parameters on a completion queue.
18373 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
18376 * Number of completions to aggregate before DMA
18377 * during the normal mode.
18379 uint16_t num_cmpl_dma_aggr;
18381 * Number of completions to aggregate before DMA
18382 * during the interrupt mode.
18384 uint16_t num_cmpl_dma_aggr_during_int;
18386 * Timer in unit of 80-nsec used to aggregate completions before
18387 * DMA during the normal mode (not in interrupt mode).
18389 uint16_t cmpl_aggr_dma_tmr;
18391 * Timer in unit of 80-nsec used to aggregate completions before
18392 * DMA during the interrupt mode.
18394 uint16_t cmpl_aggr_dma_tmr_during_int;
18395 /* Minimum time (in unit of 80-nsec) between two interrupts. */
18396 uint16_t int_lat_tmr_min;
18398 * Maximum wait time (in unit of 80-nsec) spent aggregating
18399 * cmpls before signaling the interrupt after the
18400 * interrupt is enabled.
18402 uint16_t int_lat_tmr_max;
18404 * Minimum number of completions aggregated before signaling
18407 uint16_t num_cmpl_aggr_int;
18409 * Bitfield that indicates which parameters are to be applied. Only
18410 * required when configuring devices with notification queues, and
18411 * used in that case to set certain parameters on completion queues
18412 * and others on notification queues.
18416 * This bit must be '1' for the num_cmpl_dma_aggr field to be
18419 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
18422 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
18425 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
18428 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
18431 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
18434 * This bit must be '1' for the int_lat_tmr_min field to be
18437 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
18440 * This bit must be '1' for the int_lat_tmr_max field to be
18443 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
18446 * This bit must be '1' for the num_cmpl_aggr_int field to be
18449 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
18451 uint8_t unused_0[4];
18452 } __attribute__((packed));
18454 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
18455 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
18456 /* The specific error status for the command. */
18457 uint16_t error_code;
18458 /* The HWRM command request type. */
18460 /* The sequence ID from the original command. */
18462 /* The length of the response data in number of bytes. */
18464 uint8_t unused_0[7];
18466 * This field is used in Output records to indicate that the output
18467 * is completely written to RAM. This field should be read as '1'
18468 * to indicate that the output has been completely written.
18469 * When writing a command completion or response to an internal processor,
18470 * the order of writes has to be such that this field is written last.
18473 } __attribute__((packed));
18475 /*******************
18476 * hwrm_ring_reset *
18477 *******************/
18480 /* hwrm_ring_reset_input (size:192b/24B) */
18481 struct hwrm_ring_reset_input {
18482 /* The HWRM command request type. */
18485 * The completion ring to send the completion event on. This should
18486 * be the NQ ID returned from the `nq_alloc` HWRM command.
18488 uint16_t cmpl_ring;
18490 * The sequence ID is used by the driver for tracking multiple
18491 * commands. This ID is treated as opaque data by the firmware and
18492 * the value is returned in the `hwrm_resp_hdr` upon completion.
18496 * The target ID of the command:
18497 * * 0x0-0xFFF8 - The function ID
18498 * * 0xFFF8-0xFFFE - Reserved for internal processors
18501 uint16_t target_id;
18503 * A physical address pointer pointing to a host buffer that the
18504 * command's response data will be written. This can be either a host
18505 * physical address (HPA) or a guest physical address (GPA) and must
18506 * point to a physically contiguous block of memory.
18508 uint64_t resp_addr;
18511 /* L2 Completion Ring (CR) */
18512 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
18514 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
18516 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
18517 /* RoCE Notification Completion Ring (ROCE_CR) */
18518 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
18519 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
18520 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
18522 /* Physical number of the ring. */
18524 uint8_t unused_1[4];
18525 } __attribute__((packed));
18527 /* hwrm_ring_reset_output (size:128b/16B) */
18528 struct hwrm_ring_reset_output {
18529 /* The specific error status for the command. */
18530 uint16_t error_code;
18531 /* The HWRM command request type. */
18533 /* The sequence ID from the original command. */
18535 /* The length of the response data in number of bytes. */
18537 uint8_t unused_0[7];
18539 * This field is used in Output records to indicate that the output
18540 * is completely written to RAM. This field should be read as '1'
18541 * to indicate that the output has been completely written.
18542 * When writing a command completion or response to an internal processor,
18543 * the order of writes has to be such that this field is written last.
18546 } __attribute__((packed));
18548 /***********************
18549 * hwrm_ring_grp_alloc *
18550 ***********************/
18553 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
18554 struct hwrm_ring_grp_alloc_input {
18555 /* The HWRM command request type. */
18558 * The completion ring to send the completion event on. This should
18559 * be the NQ ID returned from the `nq_alloc` HWRM command.
18561 uint16_t cmpl_ring;
18563 * The sequence ID is used by the driver for tracking multiple
18564 * commands. This ID is treated as opaque data by the firmware and
18565 * the value is returned in the `hwrm_resp_hdr` upon completion.
18569 * The target ID of the command:
18570 * * 0x0-0xFFF8 - The function ID
18571 * * 0xFFF8-0xFFFE - Reserved for internal processors
18574 uint16_t target_id;
18576 * A physical address pointer pointing to a host buffer that the
18577 * command's response data will be written. This can be either a host
18578 * physical address (HPA) or a guest physical address (GPA) and must
18579 * point to a physically contiguous block of memory.
18581 uint64_t resp_addr;
18583 * This value identifies the CR associated with the ring
18588 * This value identifies the main RR associated with the ring
18593 * This value identifies the aggregation RR associated with
18594 * the ring group. If this value is 0xFF... (All Fs), then no
18595 * Aggregation ring will be set.
18599 * This value identifies the statistics context associated
18600 * with the ring group.
18603 } __attribute__((packed));
18605 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
18606 struct hwrm_ring_grp_alloc_output {
18607 /* The specific error status for the command. */
18608 uint16_t error_code;
18609 /* The HWRM command request type. */
18611 /* The sequence ID from the original command. */
18613 /* The length of the response data in number of bytes. */
18616 * This is the ring group ID value. Use this value to program
18617 * the default ring group for the VNIC or as table entries
18618 * in an RSS/COS context.
18620 uint32_t ring_group_id;
18621 uint8_t unused_0[3];
18623 * This field is used in Output records to indicate that the output
18624 * is completely written to RAM. This field should be read as '1'
18625 * to indicate that the output has been completely written.
18626 * When writing a command completion or response to an internal processor,
18627 * the order of writes has to be such that this field is written last.
18630 } __attribute__((packed));
18632 /**********************
18633 * hwrm_ring_grp_free *
18634 **********************/
18637 /* hwrm_ring_grp_free_input (size:192b/24B) */
18638 struct hwrm_ring_grp_free_input {
18639 /* The HWRM command request type. */
18642 * The completion ring to send the completion event on. This should
18643 * be the NQ ID returned from the `nq_alloc` HWRM command.
18645 uint16_t cmpl_ring;
18647 * The sequence ID is used by the driver for tracking multiple
18648 * commands. This ID is treated as opaque data by the firmware and
18649 * the value is returned in the `hwrm_resp_hdr` upon completion.
18653 * The target ID of the command:
18654 * * 0x0-0xFFF8 - The function ID
18655 * * 0xFFF8-0xFFFE - Reserved for internal processors
18658 uint16_t target_id;
18660 * A physical address pointer pointing to a host buffer that the
18661 * command's response data will be written. This can be either a host
18662 * physical address (HPA) or a guest physical address (GPA) and must
18663 * point to a physically contiguous block of memory.
18665 uint64_t resp_addr;
18666 /* This is the ring group ID value. */
18667 uint32_t ring_group_id;
18668 uint8_t unused_0[4];
18669 } __attribute__((packed));
18671 /* hwrm_ring_grp_free_output (size:128b/16B) */
18672 struct hwrm_ring_grp_free_output {
18673 /* The specific error status for the command. */
18674 uint16_t error_code;
18675 /* The HWRM command request type. */
18677 /* The sequence ID from the original command. */
18679 /* The length of the response data in number of bytes. */
18681 uint8_t unused_0[7];
18683 * This field is used in Output records to indicate that the output
18684 * is completely written to RAM. This field should be read as '1'
18685 * to indicate that the output has been completely written.
18686 * When writing a command completion or response to an internal processor,
18687 * the order of writes has to be such that this field is written last.
18690 } __attribute__((packed));
18692 /****************************
18693 * hwrm_cfa_l2_filter_alloc *
18694 ****************************/
18697 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
18698 struct hwrm_cfa_l2_filter_alloc_input {
18699 /* The HWRM command request type. */
18702 * The completion ring to send the completion event on. This should
18703 * be the NQ ID returned from the `nq_alloc` HWRM command.
18705 uint16_t cmpl_ring;
18707 * The sequence ID is used by the driver for tracking multiple
18708 * commands. This ID is treated as opaque data by the firmware and
18709 * the value is returned in the `hwrm_resp_hdr` upon completion.
18713 * The target ID of the command:
18714 * * 0x0-0xFFF8 - The function ID
18715 * * 0xFFF8-0xFFFE - Reserved for internal processors
18718 uint16_t target_id;
18720 * A physical address pointer pointing to a host buffer that the
18721 * command's response data will be written. This can be either a host
18722 * physical address (HPA) or a guest physical address (GPA) and must
18723 * point to a physically contiguous block of memory.
18725 uint64_t resp_addr;
18728 * Enumeration denoting the RX, TX type of the resource.
18729 * This enumeration is used for resources that are similar for both
18730 * TX and RX paths of the chip.
18732 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
18735 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
18738 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
18740 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
18741 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
18742 /* Setting of this flag indicates the applicability to the loopback path. */
18743 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
18746 * Setting of this flag indicates drop action. If this flag is not set,
18747 * then it should be considered accept action.
18749 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
18752 * If this flag is set, all t_l2_* fields are invalid
18753 * and they should not be specified.
18754 * If this flag is set, then l2_* fields refer to
18755 * fields of outermost L2 header.
18757 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
18761 * This bit must be '1' for the l2_addr field to be
18764 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
18767 * This bit must be '1' for the l2_addr_mask field to be
18770 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
18773 * This bit must be '1' for the l2_ovlan field to be
18776 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
18779 * This bit must be '1' for the l2_ovlan_mask field to be
18782 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
18785 * This bit must be '1' for the l2_ivlan field to be
18788 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
18791 * This bit must be '1' for the l2_ivlan_mask field to be
18794 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
18797 * This bit must be '1' for the t_l2_addr field to be
18800 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
18803 * This bit must be '1' for the t_l2_addr_mask field to be
18806 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
18809 * This bit must be '1' for the t_l2_ovlan field to be
18812 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
18815 * This bit must be '1' for the t_l2_ovlan_mask field to be
18818 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
18821 * This bit must be '1' for the t_l2_ivlan field to be
18824 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
18827 * This bit must be '1' for the t_l2_ivlan_mask field to be
18830 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
18833 * This bit must be '1' for the src_type field to be
18836 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
18839 * This bit must be '1' for the src_id field to be
18842 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
18845 * This bit must be '1' for the tunnel_type field to be
18848 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
18851 * This bit must be '1' for the dst_id field to be
18854 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
18857 * This bit must be '1' for the mirror_vnic_id field to be
18860 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
18863 * This value sets the match value for the L2 MAC address.
18864 * Destination MAC address for RX path.
18865 * Source MAC address for TX path.
18867 uint8_t l2_addr[6];
18868 uint8_t unused_0[2];
18870 * This value sets the mask value for the L2 address.
18871 * A value of 0 will mask the corresponding bit from
18874 uint8_t l2_addr_mask[6];
18875 /* This value sets VLAN ID value for outer VLAN. */
18878 * This value sets the mask value for the ovlan id.
18879 * A value of 0 will mask the corresponding bit from
18882 uint16_t l2_ovlan_mask;
18883 /* This value sets VLAN ID value for inner VLAN. */
18886 * This value sets the mask value for the ivlan id.
18887 * A value of 0 will mask the corresponding bit from
18890 uint16_t l2_ivlan_mask;
18891 uint8_t unused_1[2];
18893 * This value sets the match value for the tunnel
18895 * Destination MAC address for RX path.
18896 * Source MAC address for TX path.
18898 uint8_t t_l2_addr[6];
18899 uint8_t unused_2[2];
18901 * This value sets the mask value for the tunnel L2
18903 * A value of 0 will mask the corresponding bit from
18906 uint8_t t_l2_addr_mask[6];
18907 /* This value sets VLAN ID value for tunnel outer VLAN. */
18908 uint16_t t_l2_ovlan;
18910 * This value sets the mask value for the tunnel ovlan id.
18911 * A value of 0 will mask the corresponding bit from
18914 uint16_t t_l2_ovlan_mask;
18915 /* This value sets VLAN ID value for tunnel inner VLAN. */
18916 uint16_t t_l2_ivlan;
18918 * This value sets the mask value for the tunnel ivlan id.
18919 * A value of 0 will mask the corresponding bit from
18922 uint16_t t_l2_ivlan_mask;
18923 /* This value identifies the type of source of the packet. */
18926 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
18927 /* Physical function */
18928 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
18929 /* Virtual function */
18930 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
18931 /* Virtual NIC of a function */
18932 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
18933 /* Embedded processor for CFA management */
18934 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
18935 /* Embedded processor for OOB management */
18936 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
18937 /* Embedded processor for RoCE */
18938 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
18939 /* Embedded processor for network proxy functions */
18940 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
18941 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
18942 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
18945 * This value is the id of the source.
18946 * For a network port, it represents port_id.
18947 * For a physical function, it represents fid.
18948 * For a virtual function, it represents vf_id.
18949 * For a vnic, it represents vnic_id.
18950 * For embedded processors, this id is not valid.
18953 * 1. The function ID is implied if it src_id is
18954 * not provided for a src_type that is either
18958 uint8_t tunnel_type;
18960 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
18962 /* Virtual eXtensible Local Area Network (VXLAN) */
18963 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
18965 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
18966 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
18968 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
18969 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
18972 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
18974 /* Generic Network Virtualization Encapsulation (Geneve) */
18975 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
18977 /* Multi-Protocol Lable Switching (MPLS) */
18978 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
18980 /* Stateless Transport Tunnel (STT) */
18981 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
18983 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
18984 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
18986 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
18987 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
18989 /* Any tunneled traffic */
18990 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
18992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
18993 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
18996 * If set, this value shall represent the
18997 * Logical VNIC ID of the destination VNIC for the RX
18998 * path and network port id of the destination port for
19003 * Logical VNIC ID of the VNIC where traffic is
19006 uint16_t mirror_vnic_id;
19008 * This hint is provided to help in placing
19009 * the filter in the filter table.
19012 /* No preference */
19013 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
19015 /* Above the given filter */
19016 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
19018 /* Below the given filter */
19019 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
19021 /* As high as possible */
19022 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
19024 /* As low as possible */
19025 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
19027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
19028 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
19032 * This is the ID of the filter that goes along with
19035 * This field is valid only for the following values.
19036 * 1 - Above the given filter
19037 * 2 - Below the given filter
19039 uint64_t l2_filter_id_hint;
19040 } __attribute__((packed));
19042 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
19043 struct hwrm_cfa_l2_filter_alloc_output {
19044 /* The specific error status for the command. */
19045 uint16_t error_code;
19046 /* The HWRM command request type. */
19048 /* The sequence ID from the original command. */
19050 /* The length of the response data in number of bytes. */
19053 * This value identifies a set of CFA data structures used for an L2
19056 uint64_t l2_filter_id;
19058 * This is the ID of the flow associated with this
19060 * This value shall be used to match and associate the
19061 * flow identifier returned in completion records.
19062 * A value of 0xFFFFFFFF shall indicate no flow id.
19065 uint8_t unused_0[3];
19067 * This field is used in Output records to indicate that the output
19068 * is completely written to RAM. This field should be read as '1'
19069 * to indicate that the output has been completely written.
19070 * When writing a command completion or response to an internal processor,
19071 * the order of writes has to be such that this field is written last.
19074 } __attribute__((packed));
19076 /***************************
19077 * hwrm_cfa_l2_filter_free *
19078 ***************************/
19081 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
19082 struct hwrm_cfa_l2_filter_free_input {
19083 /* The HWRM command request type. */
19086 * The completion ring to send the completion event on. This should
19087 * be the NQ ID returned from the `nq_alloc` HWRM command.
19089 uint16_t cmpl_ring;
19091 * The sequence ID is used by the driver for tracking multiple
19092 * commands. This ID is treated as opaque data by the firmware and
19093 * the value is returned in the `hwrm_resp_hdr` upon completion.
19097 * The target ID of the command:
19098 * * 0x0-0xFFF8 - The function ID
19099 * * 0xFFF8-0xFFFE - Reserved for internal processors
19102 uint16_t target_id;
19104 * A physical address pointer pointing to a host buffer that the
19105 * command's response data will be written. This can be either a host
19106 * physical address (HPA) or a guest physical address (GPA) and must
19107 * point to a physically contiguous block of memory.
19109 uint64_t resp_addr;
19111 * This value identifies a set of CFA data structures used for an L2
19114 uint64_t l2_filter_id;
19115 } __attribute__((packed));
19117 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
19118 struct hwrm_cfa_l2_filter_free_output {
19119 /* The specific error status for the command. */
19120 uint16_t error_code;
19121 /* The HWRM command request type. */
19123 /* The sequence ID from the original command. */
19125 /* The length of the response data in number of bytes. */
19127 uint8_t unused_0[7];
19129 * This field is used in Output records to indicate that the output
19130 * is completely written to RAM. This field should be read as '1'
19131 * to indicate that the output has been completely written.
19132 * When writing a command completion or response to an internal processor,
19133 * the order of writes has to be such that this field is written last.
19136 } __attribute__((packed));
19138 /**************************
19139 * hwrm_cfa_l2_filter_cfg *
19140 **************************/
19143 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
19144 struct hwrm_cfa_l2_filter_cfg_input {
19145 /* The HWRM command request type. */
19148 * The completion ring to send the completion event on. This should
19149 * be the NQ ID returned from the `nq_alloc` HWRM command.
19151 uint16_t cmpl_ring;
19153 * The sequence ID is used by the driver for tracking multiple
19154 * commands. This ID is treated as opaque data by the firmware and
19155 * the value is returned in the `hwrm_resp_hdr` upon completion.
19159 * The target ID of the command:
19160 * * 0x0-0xFFF8 - The function ID
19161 * * 0xFFF8-0xFFFE - Reserved for internal processors
19164 uint16_t target_id;
19166 * A physical address pointer pointing to a host buffer that the
19167 * command's response data will be written. This can be either a host
19168 * physical address (HPA) or a guest physical address (GPA) and must
19169 * point to a physically contiguous block of memory.
19171 uint64_t resp_addr;
19174 * Enumeration denoting the RX, TX type of the resource.
19175 * This enumeration is used for resources that are similar for both
19176 * TX and RX paths of the chip.
19178 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
19180 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19182 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19183 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
19184 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
19186 * Setting of this flag indicates drop action. If this flag is not set,
19187 * then it should be considered accept action.
19189 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
19192 * This bit must be '1' for the dst_id field to be
19195 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
19198 * This bit must be '1' for the new_mirror_vnic_id field to be
19201 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
19204 * This value identifies a set of CFA data structures used for an L2
19207 uint64_t l2_filter_id;
19209 * If set, this value shall represent the
19210 * Logical VNIC ID of the destination VNIC for the RX
19211 * path and network port id of the destination port for
19216 * New Logical VNIC ID of the VNIC where traffic is
19219 uint32_t new_mirror_vnic_id;
19220 } __attribute__((packed));
19222 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
19223 struct hwrm_cfa_l2_filter_cfg_output {
19224 /* The specific error status for the command. */
19225 uint16_t error_code;
19226 /* The HWRM command request type. */
19228 /* The sequence ID from the original command. */
19230 /* The length of the response data in number of bytes. */
19232 uint8_t unused_0[7];
19234 * This field is used in Output records to indicate that the output
19235 * is completely written to RAM. This field should be read as '1'
19236 * to indicate that the output has been completely written.
19237 * When writing a command completion or response to an internal processor,
19238 * the order of writes has to be such that this field is written last.
19241 } __attribute__((packed));
19243 /***************************
19244 * hwrm_cfa_l2_set_rx_mask *
19245 ***************************/
19248 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
19249 struct hwrm_cfa_l2_set_rx_mask_input {
19250 /* The HWRM command request type. */
19253 * The completion ring to send the completion event on. This should
19254 * be the NQ ID returned from the `nq_alloc` HWRM command.
19256 uint16_t cmpl_ring;
19258 * The sequence ID is used by the driver for tracking multiple
19259 * commands. This ID is treated as opaque data by the firmware and
19260 * the value is returned in the `hwrm_resp_hdr` upon completion.
19264 * The target ID of the command:
19265 * * 0x0-0xFFF8 - The function ID
19266 * * 0xFFF8-0xFFFE - Reserved for internal processors
19269 uint16_t target_id;
19271 * A physical address pointer pointing to a host buffer that the
19272 * command's response data will be written. This can be either a host
19273 * physical address (HPA) or a guest physical address (GPA) and must
19274 * point to a physically contiguous block of memory.
19276 uint64_t resp_addr;
19281 * When this bit is '1', the function is requested to accept
19282 * multi-cast packets specified by the multicast addr table.
19284 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
19287 * When this bit is '1', the function is requested to accept
19288 * all multi-cast packets.
19290 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
19293 * When this bit is '1', the function is requested to accept
19294 * broadcast packets.
19296 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
19299 * When this bit is '1', the function is requested to be
19300 * put in the promiscuous mode.
19302 * The HWRM should accept any function to set up
19303 * promiscuous mode.
19305 * The HWRM shall follow the semantics below for the
19306 * promiscuous mode support.
19307 * # When partitioning is not enabled on a port
19308 * (i.e. single PF on the port), then the PF shall
19309 * be allowed to be in the promiscuous mode. When the
19310 * PF is in the promiscuous mode, then it shall
19311 * receive all host bound traffic on that port.
19312 * # When partitioning is enabled on a port
19313 * (i.e. multiple PFs per port) and a PF on that
19314 * port is in the promiscuous mode, then the PF
19315 * receives all traffic within that partition as
19316 * identified by a unique identifier for the
19317 * PF (e.g. S-Tag). If a unique outer VLAN
19318 * for the PF is specified, then the setting of
19319 * promiscuous mode on that PF shall result in the
19320 * PF receiving all host bound traffic with matching
19322 * # A VF shall can be set in the promiscuous mode.
19323 * In the promiscuous mode, the VF does not receive any
19324 * traffic unless a unique outer VLAN for the
19325 * VF is specified. If a unique outer VLAN
19326 * for the VF is specified, then the setting of
19327 * promiscuous mode on that VF shall result in the
19328 * VF receiving all host bound traffic with the
19329 * matching outer VLAN.
19330 * # The HWRM shall allow the setting of promiscuous
19331 * mode on a function independently from the
19332 * promiscuous mode settings on other functions.
19334 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
19337 * If this flag is set, the corresponding RX
19338 * filters shall be set up to cover multicast/broadcast
19339 * filters for the outermost Layer 2 destination MAC
19342 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
19345 * If this flag is set, the corresponding RX
19346 * filters shall be set up to cover multicast/broadcast
19347 * filters for the VLAN-tagged packets that match the
19348 * TPID and VID fields of VLAN tags in the VLAN tag
19349 * table specified in this command.
19351 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
19354 * If this flag is set, the corresponding RX
19355 * filters shall be set up to cover multicast/broadcast
19356 * filters for non-VLAN tagged packets and VLAN-tagged
19357 * packets that match the TPID and VID fields of VLAN
19358 * tags in the VLAN tag table specified in this command.
19360 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
19363 * If this flag is set, the corresponding RX
19364 * filters shall be set up to cover multicast/broadcast
19365 * filters for non-VLAN tagged packets and VLAN-tagged
19366 * packets matching any VLAN tag.
19368 * If this flag is set, then the HWRM shall ignore
19369 * VLAN tags specified in vlan_tag_tbl.
19371 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
19372 * flags is set, then the HWRM shall ignore
19373 * VLAN tags specified in vlan_tag_tbl.
19375 * The HWRM client shall set at most one flag out of
19376 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
19378 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
19380 /* This is the address for mcast address tbl. */
19381 uint64_t mc_tbl_addr;
19383 * This value indicates how many entries in mc_tbl are valid.
19384 * Each entry is 6 bytes.
19386 uint32_t num_mc_entries;
19387 uint8_t unused_0[4];
19389 * This is the address for VLAN tag table.
19390 * Each VLAN entry in the table is 4 bytes of a VLAN tag
19391 * including TPID, PCP, DEI, and VID fields in network byte
19394 uint64_t vlan_tag_tbl_addr;
19396 * This value indicates how many entries in vlan_tag_tbl are
19397 * valid. Each entry is 4 bytes.
19399 uint32_t num_vlan_tags;
19400 uint8_t unused_1[4];
19401 } __attribute__((packed));
19403 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
19404 struct hwrm_cfa_l2_set_rx_mask_output {
19405 /* The specific error status for the command. */
19406 uint16_t error_code;
19407 /* The HWRM command request type. */
19409 /* The sequence ID from the original command. */
19411 /* The length of the response data in number of bytes. */
19413 uint8_t unused_0[7];
19415 * This field is used in Output records to indicate that the output
19416 * is completely written to RAM. This field should be read as '1'
19417 * to indicate that the output has been completely written.
19418 * When writing a command completion or response to an internal processor,
19419 * the order of writes has to be such that this field is written last.
19422 } __attribute__((packed));
19424 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
19425 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
19427 * command specific error codes that goes to
19428 * the cmd_err field in Common HWRM Error Response.
19431 /* Unknown error */
19432 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
19434 /* Unable to complete operation due to conflict with Ntuple Filter */
19435 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
19437 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
19438 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
19439 uint8_t unused_0[7];
19440 } __attribute__((packed));
19442 /*******************************
19443 * hwrm_cfa_vlan_antispoof_cfg *
19444 *******************************/
19447 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
19448 struct hwrm_cfa_vlan_antispoof_cfg_input {
19449 /* The HWRM command request type. */
19452 * The completion ring to send the completion event on. This should
19453 * be the NQ ID returned from the `nq_alloc` HWRM command.
19455 uint16_t cmpl_ring;
19457 * The sequence ID is used by the driver for tracking multiple
19458 * commands. This ID is treated as opaque data by the firmware and
19459 * the value is returned in the `hwrm_resp_hdr` upon completion.
19463 * The target ID of the command:
19464 * * 0x0-0xFFF8 - The function ID
19465 * * 0xFFF8-0xFFFE - Reserved for internal processors
19468 uint16_t target_id;
19470 * A physical address pointer pointing to a host buffer that the
19471 * command's response data will be written. This can be either a host
19472 * physical address (HPA) or a guest physical address (GPA) and must
19473 * point to a physically contiguous block of memory.
19475 uint64_t resp_addr;
19477 * Function ID of the function that is being configured.
19478 * Only valid for a VF FID configured by the PF.
19481 uint8_t unused_0[2];
19482 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
19483 uint32_t num_vlan_entries;
19485 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
19486 * antispoof table. Each table entry contains the 16-bit TPID
19487 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
19488 * all in network order to match hwrm_cfa_l2_set_rx_mask.
19489 * For an individual VLAN entry, the mask value should be 0xfff
19490 * for the 12-bit VLAN ID.
19492 uint64_t vlan_tag_mask_tbl_addr;
19493 } __attribute__((packed));
19495 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
19496 struct hwrm_cfa_vlan_antispoof_cfg_output {
19497 /* The specific error status for the command. */
19498 uint16_t error_code;
19499 /* The HWRM command request type. */
19501 /* The sequence ID from the original command. */
19503 /* The length of the response data in number of bytes. */
19505 uint8_t unused_0[7];
19507 * This field is used in Output records to indicate that the output
19508 * is completely written to RAM. This field should be read as '1'
19509 * to indicate that the output has been completely written.
19510 * When writing a command completion or response to an internal processor,
19511 * the order of writes has to be such that this field is written last.
19514 } __attribute__((packed));
19516 /********************************
19517 * hwrm_cfa_vlan_antispoof_qcfg *
19518 ********************************/
19521 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
19522 struct hwrm_cfa_vlan_antispoof_qcfg_input {
19523 /* The HWRM command request type. */
19526 * The completion ring to send the completion event on. This should
19527 * be the NQ ID returned from the `nq_alloc` HWRM command.
19529 uint16_t cmpl_ring;
19531 * The sequence ID is used by the driver for tracking multiple
19532 * commands. This ID is treated as opaque data by the firmware and
19533 * the value is returned in the `hwrm_resp_hdr` upon completion.
19537 * The target ID of the command:
19538 * * 0x0-0xFFF8 - The function ID
19539 * * 0xFFF8-0xFFFE - Reserved for internal processors
19542 uint16_t target_id;
19544 * A physical address pointer pointing to a host buffer that the
19545 * command's response data will be written. This can be either a host
19546 * physical address (HPA) or a guest physical address (GPA) and must
19547 * point to a physically contiguous block of memory.
19549 uint64_t resp_addr;
19551 * Function ID of the function that is being queried.
19552 * Only valid for a VF FID queried by the PF.
19555 uint8_t unused_0[2];
19557 * Maximum number of VLAN entries the firmware is allowed to DMA
19558 * to vlan_tag_mask_tbl.
19560 uint32_t max_vlan_entries;
19562 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
19563 * antispoof table to which firmware will DMA to. Each table
19564 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
19565 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
19566 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
19567 * the mask value should be 0xfff for the 12-bit VLAN ID.
19569 uint64_t vlan_tag_mask_tbl_addr;
19570 } __attribute__((packed));
19572 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
19573 struct hwrm_cfa_vlan_antispoof_qcfg_output {
19574 /* The specific error status for the command. */
19575 uint16_t error_code;
19576 /* The HWRM command request type. */
19578 /* The sequence ID from the original command. */
19580 /* The length of the response data in number of bytes. */
19582 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
19583 uint32_t num_vlan_entries;
19584 uint8_t unused_0[3];
19586 * This field is used in Output records to indicate that the output
19587 * is completely written to RAM. This field should be read as '1'
19588 * to indicate that the output has been completely written.
19589 * When writing a command completion or response to an internal processor,
19590 * the order of writes has to be such that this field is written last.
19593 } __attribute__((packed));
19595 /********************************
19596 * hwrm_cfa_ntuple_filter_alloc *
19597 ********************************/
19600 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
19601 struct hwrm_cfa_ntuple_filter_alloc_input {
19602 /* The HWRM command request type. */
19605 * The completion ring to send the completion event on. This should
19606 * be the NQ ID returned from the `nq_alloc` HWRM command.
19608 uint16_t cmpl_ring;
19610 * The sequence ID is used by the driver for tracking multiple
19611 * commands. This ID is treated as opaque data by the firmware and
19612 * the value is returned in the `hwrm_resp_hdr` upon completion.
19616 * The target ID of the command:
19617 * * 0x0-0xFFF8 - The function ID
19618 * * 0xFFF8-0xFFFE - Reserved for internal processors
19621 uint16_t target_id;
19623 * A physical address pointer pointing to a host buffer that the
19624 * command's response data will be written. This can be either a host
19625 * physical address (HPA) or a guest physical address (GPA) and must
19626 * point to a physically contiguous block of memory.
19628 uint64_t resp_addr;
19630 /* Setting of this flag indicates the applicability to the loopback path. */
19631 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
19634 * Setting of this flag indicates drop action. If this flag is not set,
19635 * then it should be considered accept action.
19637 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
19640 * Setting of this flag indicates that a meter is expected to be attached
19641 * to this flow. This hint can be used when choosing the action record
19642 * format required for the flow.
19644 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
19648 * This bit must be '1' for the l2_filter_id field to be
19651 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
19654 * This bit must be '1' for the ethertype field to be
19657 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
19660 * This bit must be '1' for the tunnel_type field to be
19663 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
19666 * This bit must be '1' for the src_macaddr field to be
19669 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
19672 * This bit must be '1' for the ipaddr_type field to be
19675 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
19678 * This bit must be '1' for the src_ipaddr field to be
19681 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
19684 * This bit must be '1' for the src_ipaddr_mask field to be
19687 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
19690 * This bit must be '1' for the dst_ipaddr field to be
19693 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
19696 * This bit must be '1' for the dst_ipaddr_mask field to be
19699 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
19702 * This bit must be '1' for the ip_protocol field to be
19705 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
19708 * This bit must be '1' for the src_port field to be
19711 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
19714 * This bit must be '1' for the src_port_mask field to be
19717 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
19720 * This bit must be '1' for the dst_port field to be
19723 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
19726 * This bit must be '1' for the dst_port_mask field to be
19729 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
19732 * This bit must be '1' for the pri_hint field to be
19735 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
19738 * This bit must be '1' for the ntuple_filter_id field to be
19741 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
19744 * This bit must be '1' for the dst_id field to be
19747 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
19750 * This bit must be '1' for the mirror_vnic_id field to be
19753 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
19756 * This bit must be '1' for the dst_macaddr field to be
19759 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
19762 * This value identifies a set of CFA data structures used for an L2
19765 uint64_t l2_filter_id;
19767 * This value indicates the source MAC address in
19768 * the Ethernet header.
19770 uint8_t src_macaddr[6];
19771 /* This value indicates the ethertype in the Ethernet header. */
19772 uint16_t ethertype;
19774 * This value indicates the type of IP address.
19777 * All others are invalid.
19779 uint8_t ip_addr_type;
19781 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
19784 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
19787 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
19789 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
19790 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
19792 * The value of protocol filed in IP header.
19793 * Applies to UDP and TCP traffic.
19797 uint8_t ip_protocol;
19799 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
19802 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
19805 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
19807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
19808 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
19810 * If set, this value shall represent the
19811 * Logical VNIC ID of the destination VNIC for the RX
19812 * path and network port id of the destination port for
19817 * Logical VNIC ID of the VNIC where traffic is
19820 uint16_t mirror_vnic_id;
19822 * This value indicates the tunnel type for this filter.
19823 * If this field is not specified, then the filter shall
19824 * apply to both non-tunneled and tunneled packets.
19825 * If this field conflicts with the tunnel_type specified
19826 * in the l2_filter_id, then the HWRM shall return an
19827 * error for this command.
19829 uint8_t tunnel_type;
19831 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
19833 /* Virtual eXtensible Local Area Network (VXLAN) */
19834 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
19836 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
19837 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
19839 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
19840 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
19843 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
19845 /* Generic Network Virtualization Encapsulation (Geneve) */
19846 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
19848 /* Multi-Protocol Lable Switching (MPLS) */
19849 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
19851 /* Stateless Transport Tunnel (STT) */
19852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
19854 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
19855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
19857 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
19858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
19860 /* Any tunneled traffic */
19861 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
19863 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
19864 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
19866 * This hint is provided to help in placing
19867 * the filter in the filter table.
19870 /* No preference */
19871 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
19873 /* Above the given filter */
19874 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
19876 /* Below the given filter */
19877 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
19879 /* As high as possible */
19880 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
19882 /* As low as possible */
19883 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
19885 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
19886 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
19888 * The value of source IP address to be used in filtering.
19889 * For IPv4, first four bytes represent the IP address.
19891 uint32_t src_ipaddr[4];
19893 * The value of source IP address mask to be used in
19895 * For IPv4, first four bytes represent the IP address mask.
19897 uint32_t src_ipaddr_mask[4];
19899 * The value of destination IP address to be used in filtering.
19900 * For IPv4, first four bytes represent the IP address.
19902 uint32_t dst_ipaddr[4];
19904 * The value of destination IP address mask to be used in
19906 * For IPv4, first four bytes represent the IP address mask.
19908 uint32_t dst_ipaddr_mask[4];
19910 * The value of source port to be used in filtering.
19911 * Applies to UDP and TCP traffic.
19915 * The value of source port mask to be used in filtering.
19916 * Applies to UDP and TCP traffic.
19918 uint16_t src_port_mask;
19920 * The value of destination port to be used in filtering.
19921 * Applies to UDP and TCP traffic.
19925 * The value of destination port mask to be used in
19927 * Applies to UDP and TCP traffic.
19929 uint16_t dst_port_mask;
19931 * This is the ID of the filter that goes along with
19934 uint64_t ntuple_filter_id_hint;
19935 } __attribute__((packed));
19937 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
19938 struct hwrm_cfa_ntuple_filter_alloc_output {
19939 /* The specific error status for the command. */
19940 uint16_t error_code;
19941 /* The HWRM command request type. */
19943 /* The sequence ID from the original command. */
19945 /* The length of the response data in number of bytes. */
19947 /* This value is an opaque id into CFA data structures. */
19948 uint64_t ntuple_filter_id;
19950 * This is the ID of the flow associated with this
19952 * This value shall be used to match and associate the
19953 * flow identifier returned in completion records.
19954 * A value of 0xFFFFFFFF shall indicate no flow id.
19957 uint8_t unused_0[3];
19959 * This field is used in Output records to indicate that the output
19960 * is completely written to RAM. This field should be read as '1'
19961 * to indicate that the output has been completely written.
19962 * When writing a command completion or response to an internal processor,
19963 * the order of writes has to be such that this field is written last.
19966 } __attribute__((packed));
19968 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
19969 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
19971 * command specific error codes that goes to
19972 * the cmd_err field in Common HWRM Error Response.
19975 /* Unknown error */
19976 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
19978 /* Unable to complete operation due to conflict with Rx Mask VLAN */
19979 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
19981 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
19982 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
19983 uint8_t unused_0[7];
19984 } __attribute__((packed));
19986 /*******************************
19987 * hwrm_cfa_ntuple_filter_free *
19988 *******************************/
19991 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
19992 struct hwrm_cfa_ntuple_filter_free_input {
19993 /* The HWRM command request type. */
19996 * The completion ring to send the completion event on. This should
19997 * be the NQ ID returned from the `nq_alloc` HWRM command.
19999 uint16_t cmpl_ring;
20001 * The sequence ID is used by the driver for tracking multiple
20002 * commands. This ID is treated as opaque data by the firmware and
20003 * the value is returned in the `hwrm_resp_hdr` upon completion.
20007 * The target ID of the command:
20008 * * 0x0-0xFFF8 - The function ID
20009 * * 0xFFF8-0xFFFE - Reserved for internal processors
20012 uint16_t target_id;
20014 * A physical address pointer pointing to a host buffer that the
20015 * command's response data will be written. This can be either a host
20016 * physical address (HPA) or a guest physical address (GPA) and must
20017 * point to a physically contiguous block of memory.
20019 uint64_t resp_addr;
20020 /* This value is an opaque id into CFA data structures. */
20021 uint64_t ntuple_filter_id;
20022 } __attribute__((packed));
20024 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
20025 struct hwrm_cfa_ntuple_filter_free_output {
20026 /* The specific error status for the command. */
20027 uint16_t error_code;
20028 /* The HWRM command request type. */
20030 /* The sequence ID from the original command. */
20032 /* The length of the response data in number of bytes. */
20034 uint8_t unused_0[7];
20036 * This field is used in Output records to indicate that the output
20037 * is completely written to RAM. This field should be read as '1'
20038 * to indicate that the output has been completely written.
20039 * When writing a command completion or response to an internal processor,
20040 * the order of writes has to be such that this field is written last.
20043 } __attribute__((packed));
20045 /******************************
20046 * hwrm_cfa_ntuple_filter_cfg *
20047 ******************************/
20050 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
20051 struct hwrm_cfa_ntuple_filter_cfg_input {
20052 /* The HWRM command request type. */
20055 * The completion ring to send the completion event on. This should
20056 * be the NQ ID returned from the `nq_alloc` HWRM command.
20058 uint16_t cmpl_ring;
20060 * The sequence ID is used by the driver for tracking multiple
20061 * commands. This ID is treated as opaque data by the firmware and
20062 * the value is returned in the `hwrm_resp_hdr` upon completion.
20066 * The target ID of the command:
20067 * * 0x0-0xFFF8 - The function ID
20068 * * 0xFFF8-0xFFFE - Reserved for internal processors
20071 uint16_t target_id;
20073 * A physical address pointer pointing to a host buffer that the
20074 * command's response data will be written. This can be either a host
20075 * physical address (HPA) or a guest physical address (GPA) and must
20076 * point to a physically contiguous block of memory.
20078 uint64_t resp_addr;
20081 * This bit must be '1' for the new_dst_id field to be
20084 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
20087 * This bit must be '1' for the new_mirror_vnic_id field to be
20090 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
20093 * This bit must be '1' for the new_meter_instance_id field to be
20096 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
20098 uint8_t unused_0[4];
20099 /* This value is an opaque id into CFA data structures. */
20100 uint64_t ntuple_filter_id;
20102 * If set, this value shall represent the new
20103 * Logical VNIC ID of the destination VNIC for the RX
20104 * path and new network port id of the destination port for
20107 uint32_t new_dst_id;
20109 * New Logical VNIC ID of the VNIC where traffic is
20112 uint32_t new_mirror_vnic_id;
20114 * New meter to attach to the flow. Specifying the
20115 * invalid instance ID is used to remove any existing
20116 * meter from the flow.
20118 uint16_t new_meter_instance_id;
20120 * A value of 0xfff is considered invalid and implies the
20121 * instance is not configured.
20123 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
20125 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
20126 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
20127 uint8_t unused_1[6];
20128 } __attribute__((packed));
20130 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
20131 struct hwrm_cfa_ntuple_filter_cfg_output {
20132 /* The specific error status for the command. */
20133 uint16_t error_code;
20134 /* The HWRM command request type. */
20136 /* The sequence ID from the original command. */
20138 /* The length of the response data in number of bytes. */
20140 uint8_t unused_0[7];
20142 * This field is used in Output records to indicate that the output
20143 * is completely written to RAM. This field should be read as '1'
20144 * to indicate that the output has been completely written.
20145 * When writing a command completion or response to an internal processor,
20146 * the order of writes has to be such that this field is written last.
20149 } __attribute__((packed));
20151 /**************************
20152 * hwrm_cfa_em_flow_alloc *
20153 **************************/
20156 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
20157 struct hwrm_cfa_em_flow_alloc_input {
20158 /* The HWRM command request type. */
20161 * The completion ring to send the completion event on. This should
20162 * be the NQ ID returned from the `nq_alloc` HWRM command.
20164 uint16_t cmpl_ring;
20166 * The sequence ID is used by the driver for tracking multiple
20167 * commands. This ID is treated as opaque data by the firmware and
20168 * the value is returned in the `hwrm_resp_hdr` upon completion.
20172 * The target ID of the command:
20173 * * 0x0-0xFFF8 - The function ID
20174 * * 0xFFF8-0xFFFE - Reserved for internal processors
20177 uint16_t target_id;
20179 * A physical address pointer pointing to a host buffer that the
20180 * command's response data will be written. This can be either a host
20181 * physical address (HPA) or a guest physical address (GPA) and must
20182 * point to a physically contiguous block of memory.
20184 uint64_t resp_addr;
20187 * Enumeration denoting the RX, TX type of the resource.
20188 * This enumeration is used for resources that are similar for both
20189 * TX and RX paths of the chip.
20191 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
20193 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
20195 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
20196 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
20197 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
20199 * Setting of this flag indicates enabling of a byte counter for a given
20202 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
20204 * Setting of this flag indicates enabling of a packet counter for a given
20207 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
20208 /* Setting of this flag indicates de-capsulation action for the given flow. */
20209 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
20210 /* Setting of this flag indicates encapsulation action for the given flow. */
20211 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
20213 * Setting of this flag indicates drop action. If this flag is not set,
20214 * then it should be considered accept action.
20216 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
20218 * Setting of this flag indicates that a meter is expected to be attached
20219 * to this flow. This hint can be used when choosing the action record
20220 * format required for the flow.
20222 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
20225 * This bit must be '1' for the l2_filter_id field to be
20228 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
20231 * This bit must be '1' for the tunnel_type field to be
20234 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
20237 * This bit must be '1' for the tunnel_id field to be
20240 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
20243 * This bit must be '1' for the src_macaddr field to be
20246 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
20249 * This bit must be '1' for the dst_macaddr field to be
20252 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
20255 * This bit must be '1' for the ovlan_vid field to be
20258 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
20261 * This bit must be '1' for the ivlan_vid field to be
20264 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
20267 * This bit must be '1' for the ethertype field to be
20270 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
20273 * This bit must be '1' for the src_ipaddr field to be
20276 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
20279 * This bit must be '1' for the dst_ipaddr field to be
20282 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
20285 * This bit must be '1' for the ipaddr_type field to be
20288 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
20291 * This bit must be '1' for the ip_protocol field to be
20294 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
20297 * This bit must be '1' for the src_port field to be
20300 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
20303 * This bit must be '1' for the dst_port field to be
20306 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
20309 * This bit must be '1' for the dst_id field to be
20312 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
20315 * This bit must be '1' for the mirror_vnic_id field to be
20318 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
20321 * This bit must be '1' for the encap_record_id field to be
20324 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
20327 * This bit must be '1' for the meter_instance_id field to be
20330 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
20333 * This value identifies a set of CFA data structures used for an L2
20336 uint64_t l2_filter_id;
20338 uint8_t tunnel_type;
20340 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
20342 /* Virtual eXtensible Local Area Network (VXLAN) */
20343 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20345 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
20346 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
20348 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
20349 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
20352 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
20354 /* Generic Network Virtualization Encapsulation (Geneve) */
20355 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
20357 /* Multi-Protocol Lable Switching (MPLS) */
20358 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
20360 /* Stateless Transport Tunnel (STT) */
20361 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
20363 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
20364 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
20366 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20367 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20369 /* Any tunneled traffic */
20370 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
20372 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
20373 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
20374 uint8_t unused_0[3];
20376 * Tunnel identifier.
20377 * Virtual Network Identifier (VNI). Only valid with
20378 * tunnel_types VXLAN, NVGRE, and Geneve.
20379 * Only lower 24-bits of VNI field are used
20380 * in setting up the filter.
20382 uint32_t tunnel_id;
20384 * This value indicates the source MAC address in
20385 * the Ethernet header.
20387 uint8_t src_macaddr[6];
20388 /* The meter instance to attach to the flow. */
20389 uint16_t meter_instance_id;
20391 * A value of 0xfff is considered invalid and implies the
20392 * instance is not configured.
20394 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
20396 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
20397 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
20399 * This value indicates the destination MAC address in
20400 * the Ethernet header.
20402 uint8_t dst_macaddr[6];
20404 * This value indicates the VLAN ID of the outer VLAN tag
20405 * in the Ethernet header.
20407 uint16_t ovlan_vid;
20409 * This value indicates the VLAN ID of the inner VLAN tag
20410 * in the Ethernet header.
20412 uint16_t ivlan_vid;
20413 /* This value indicates the ethertype in the Ethernet header. */
20414 uint16_t ethertype;
20416 * This value indicates the type of IP address.
20419 * All others are invalid.
20421 uint8_t ip_addr_type;
20423 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
20425 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
20427 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
20428 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
20429 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
20431 * The value of protocol filed in IP header.
20432 * Applies to UDP and TCP traffic.
20436 uint8_t ip_protocol;
20438 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
20440 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
20442 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
20443 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
20444 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
20445 uint8_t unused_1[2];
20447 * The value of source IP address to be used in filtering.
20448 * For IPv4, first four bytes represent the IP address.
20450 uint32_t src_ipaddr[4];
20452 * big_endian = True
20453 * The value of destination IP address to be used in filtering.
20454 * For IPv4, first four bytes represent the IP address.
20456 uint32_t dst_ipaddr[4];
20458 * The value of source port to be used in filtering.
20459 * Applies to UDP and TCP traffic.
20463 * The value of destination port to be used in filtering.
20464 * Applies to UDP and TCP traffic.
20468 * If set, this value shall represent the
20469 * Logical VNIC ID of the destination VNIC for the RX
20470 * path and network port id of the destination port for
20475 * Logical VNIC ID of the VNIC where traffic is
20478 uint16_t mirror_vnic_id;
20479 /* Logical ID of the encapsulation record. */
20480 uint32_t encap_record_id;
20481 uint8_t unused_2[4];
20482 } __attribute__((packed));
20484 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
20485 struct hwrm_cfa_em_flow_alloc_output {
20486 /* The specific error status for the command. */
20487 uint16_t error_code;
20488 /* The HWRM command request type. */
20490 /* The sequence ID from the original command. */
20492 /* The length of the response data in number of bytes. */
20494 /* This value is an opaque id into CFA data structures. */
20495 uint64_t em_filter_id;
20497 * This is the ID of the flow associated with this
20499 * This value shall be used to match and associate the
20500 * flow identifier returned in completion records.
20501 * A value of 0xFFFFFFFF shall indicate no flow id.
20504 uint8_t unused_0[3];
20506 * This field is used in Output records to indicate that the output
20507 * is completely written to RAM. This field should be read as '1'
20508 * to indicate that the output has been completely written.
20509 * When writing a command completion or response to an internal processor,
20510 * the order of writes has to be such that this field is written last.
20513 } __attribute__((packed));
20515 /*************************
20516 * hwrm_cfa_em_flow_free *
20517 *************************/
20520 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
20521 struct hwrm_cfa_em_flow_free_input {
20522 /* The HWRM command request type. */
20525 * The completion ring to send the completion event on. This should
20526 * be the NQ ID returned from the `nq_alloc` HWRM command.
20528 uint16_t cmpl_ring;
20530 * The sequence ID is used by the driver for tracking multiple
20531 * commands. This ID is treated as opaque data by the firmware and
20532 * the value is returned in the `hwrm_resp_hdr` upon completion.
20536 * The target ID of the command:
20537 * * 0x0-0xFFF8 - The function ID
20538 * * 0xFFF8-0xFFFE - Reserved for internal processors
20541 uint16_t target_id;
20543 * A physical address pointer pointing to a host buffer that the
20544 * command's response data will be written. This can be either a host
20545 * physical address (HPA) or a guest physical address (GPA) and must
20546 * point to a physically contiguous block of memory.
20548 uint64_t resp_addr;
20549 /* This value is an opaque id into CFA data structures. */
20550 uint64_t em_filter_id;
20551 } __attribute__((packed));
20553 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
20554 struct hwrm_cfa_em_flow_free_output {
20555 /* The specific error status for the command. */
20556 uint16_t error_code;
20557 /* The HWRM command request type. */
20559 /* The sequence ID from the original command. */
20561 /* The length of the response data in number of bytes. */
20563 uint8_t unused_0[7];
20565 * This field is used in Output records to indicate that the output
20566 * is completely written to RAM. This field should be read as '1'
20567 * to indicate that the output has been completely written.
20568 * When writing a command completion or response to an internal processor,
20569 * the order of writes has to be such that this field is written last.
20572 } __attribute__((packed));
20574 /************************
20575 * hwrm_cfa_em_flow_cfg *
20576 ************************/
20579 /* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
20580 struct hwrm_cfa_em_flow_cfg_input {
20581 /* The HWRM command request type. */
20584 * The completion ring to send the completion event on. This should
20585 * be the NQ ID returned from the `nq_alloc` HWRM command.
20587 uint16_t cmpl_ring;
20589 * The sequence ID is used by the driver for tracking multiple
20590 * commands. This ID is treated as opaque data by the firmware and
20591 * the value is returned in the `hwrm_resp_hdr` upon completion.
20595 * The target ID of the command:
20596 * * 0x0-0xFFF8 - The function ID
20597 * * 0xFFF8-0xFFFE - Reserved for internal processors
20600 uint16_t target_id;
20602 * A physical address pointer pointing to a host buffer that the
20603 * command's response data will be written. This can be either a host
20604 * physical address (HPA) or a guest physical address (GPA) and must
20605 * point to a physically contiguous block of memory.
20607 uint64_t resp_addr;
20610 * This bit must be '1' for the new_dst_id field to be
20613 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \
20616 * This bit must be '1' for the new_mirror_vnic_id field to be
20619 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
20622 * This bit must be '1' for the new_meter_instance_id field to be
20625 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
20627 uint8_t unused_0[4];
20628 /* This value is an opaque id into CFA data structures. */
20629 uint64_t em_filter_id;
20631 * If set, this value shall represent the new
20632 * Logical VNIC ID of the destination VNIC for the RX
20633 * path and network port id of the destination port for
20636 uint32_t new_dst_id;
20638 * New Logical VNIC ID of the VNIC where traffic is
20641 uint32_t new_mirror_vnic_id;
20643 * New meter to attach to the flow. Specifying the
20644 * invalid instance ID is used to remove any existing
20645 * meter from the flow.
20647 uint16_t new_meter_instance_id;
20649 * A value of 0xfff is considered invalid and implies the
20650 * instance is not configured.
20652 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
20654 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
20655 HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
20656 uint8_t unused_1[6];
20657 } __attribute__((packed));
20659 /* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
20660 struct hwrm_cfa_em_flow_cfg_output {
20661 /* The specific error status for the command. */
20662 uint16_t error_code;
20663 /* The HWRM command request type. */
20665 /* The sequence ID from the original command. */
20667 /* The length of the response data in number of bytes. */
20669 uint8_t unused_0[7];
20671 * This field is used in Output records to indicate that the output
20672 * is completely written to RAM. This field should be read as '1'
20673 * to indicate that the output has been completely written.
20674 * When writing a command completion or response to an internal processor,
20675 * the order of writes has to be such that this field is written last.
20678 } __attribute__((packed));
20680 /******************************
20681 * hwrm_tunnel_dst_port_query *
20682 ******************************/
20685 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
20686 struct hwrm_tunnel_dst_port_query_input {
20687 /* The HWRM command request type. */
20690 * The completion ring to send the completion event on. This should
20691 * be the NQ ID returned from the `nq_alloc` HWRM command.
20693 uint16_t cmpl_ring;
20695 * The sequence ID is used by the driver for tracking multiple
20696 * commands. This ID is treated as opaque data by the firmware and
20697 * the value is returned in the `hwrm_resp_hdr` upon completion.
20701 * The target ID of the command:
20702 * * 0x0-0xFFF8 - The function ID
20703 * * 0xFFF8-0xFFFE - Reserved for internal processors
20706 uint16_t target_id;
20708 * A physical address pointer pointing to a host buffer that the
20709 * command's response data will be written. This can be either a host
20710 * physical address (HPA) or a guest physical address (GPA) and must
20711 * point to a physically contiguous block of memory.
20713 uint64_t resp_addr;
20715 uint8_t tunnel_type;
20716 /* Virtual eXtensible Local Area Network (VXLAN) */
20717 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
20719 /* Generic Network Virtualization Encapsulation (Geneve) */
20720 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
20722 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20723 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20725 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
20726 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
20728 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
20729 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
20730 uint8_t unused_0[7];
20731 } __attribute__((packed));
20733 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
20734 struct hwrm_tunnel_dst_port_query_output {
20735 /* The specific error status for the command. */
20736 uint16_t error_code;
20737 /* The HWRM command request type. */
20739 /* The sequence ID from the original command. */
20741 /* The length of the response data in number of bytes. */
20744 * This field represents the identifier of L4 destination port
20745 * used for the given tunnel type. This field is valid for
20746 * specific tunnel types that use layer 4 (e.g. UDP)
20747 * transports for tunneling.
20749 uint16_t tunnel_dst_port_id;
20751 * This field represents the value of L4 destination port
20752 * identified by tunnel_dst_port_id. This field is valid for
20753 * specific tunnel types that use layer 4 (e.g. UDP)
20754 * transports for tunneling.
20755 * This field is in network byte order.
20757 * A value of 0 means that the destination port is not
20760 uint16_t tunnel_dst_port_val;
20761 uint8_t unused_0[3];
20763 * This field is used in Output records to indicate that the output
20764 * is completely written to RAM. This field should be read as '1'
20765 * to indicate that the output has been completely written.
20766 * When writing a command completion or response to an internal processor,
20767 * the order of writes has to be such that this field is written last.
20770 } __attribute__((packed));
20772 /******************************
20773 * hwrm_tunnel_dst_port_alloc *
20774 ******************************/
20777 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
20778 struct hwrm_tunnel_dst_port_alloc_input {
20779 /* The HWRM command request type. */
20782 * The completion ring to send the completion event on. This should
20783 * be the NQ ID returned from the `nq_alloc` HWRM command.
20785 uint16_t cmpl_ring;
20787 * The sequence ID is used by the driver for tracking multiple
20788 * commands. This ID is treated as opaque data by the firmware and
20789 * the value is returned in the `hwrm_resp_hdr` upon completion.
20793 * The target ID of the command:
20794 * * 0x0-0xFFF8 - The function ID
20795 * * 0xFFF8-0xFFFE - Reserved for internal processors
20798 uint16_t target_id;
20800 * A physical address pointer pointing to a host buffer that the
20801 * command's response data will be written. This can be either a host
20802 * physical address (HPA) or a guest physical address (GPA) and must
20803 * point to a physically contiguous block of memory.
20805 uint64_t resp_addr;
20807 uint8_t tunnel_type;
20808 /* Virtual eXtensible Local Area Network (VXLAN) */
20809 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20811 /* Generic Network Virtualization Encapsulation (Geneve) */
20812 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
20814 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20815 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20817 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
20818 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
20820 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
20821 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
20824 * This field represents the value of L4 destination port used
20825 * for the given tunnel type. This field is valid for
20826 * specific tunnel types that use layer 4 (e.g. UDP)
20827 * transports for tunneling.
20829 * This field is in network byte order.
20831 * A value of 0 shall fail the command.
20833 uint16_t tunnel_dst_port_val;
20834 uint8_t unused_1[4];
20835 } __attribute__((packed));
20837 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
20838 struct hwrm_tunnel_dst_port_alloc_output {
20839 /* The specific error status for the command. */
20840 uint16_t error_code;
20841 /* The HWRM command request type. */
20843 /* The sequence ID from the original command. */
20845 /* The length of the response data in number of bytes. */
20848 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
20849 * types that has l4 destination port parameters.
20851 uint16_t tunnel_dst_port_id;
20852 uint8_t unused_0[5];
20854 * This field is used in Output records to indicate that the output
20855 * is completely written to RAM. This field should be read as '1'
20856 * to indicate that the output has been completely written.
20857 * When writing a command completion or response to an internal processor,
20858 * the order of writes has to be such that this field is written last.
20861 } __attribute__((packed));
20863 /*****************************
20864 * hwrm_tunnel_dst_port_free *
20865 *****************************/
20868 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
20869 struct hwrm_tunnel_dst_port_free_input {
20870 /* The HWRM command request type. */
20873 * The completion ring to send the completion event on. This should
20874 * be the NQ ID returned from the `nq_alloc` HWRM command.
20876 uint16_t cmpl_ring;
20878 * The sequence ID is used by the driver for tracking multiple
20879 * commands. This ID is treated as opaque data by the firmware and
20880 * the value is returned in the `hwrm_resp_hdr` upon completion.
20884 * The target ID of the command:
20885 * * 0x0-0xFFF8 - The function ID
20886 * * 0xFFF8-0xFFFE - Reserved for internal processors
20889 uint16_t target_id;
20891 * A physical address pointer pointing to a host buffer that the
20892 * command's response data will be written. This can be either a host
20893 * physical address (HPA) or a guest physical address (GPA) and must
20894 * point to a physically contiguous block of memory.
20896 uint64_t resp_addr;
20898 uint8_t tunnel_type;
20899 /* Virtual eXtensible Local Area Network (VXLAN) */
20900 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
20902 /* Generic Network Virtualization Encapsulation (Geneve) */
20903 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
20905 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20906 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20908 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
20909 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
20911 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
20912 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
20915 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
20916 * types that has l4 destination port parameters.
20918 uint16_t tunnel_dst_port_id;
20919 uint8_t unused_1[4];
20920 } __attribute__((packed));
20922 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
20923 struct hwrm_tunnel_dst_port_free_output {
20924 /* The specific error status for the command. */
20925 uint16_t error_code;
20926 /* The HWRM command request type. */
20928 /* The sequence ID from the original command. */
20930 /* The length of the response data in number of bytes. */
20932 uint8_t unused_1[7];
20934 * This field is used in Output records to indicate that the output
20935 * is completely written to RAM. This field should be read as '1'
20936 * to indicate that the output has been completely written.
20937 * When writing a command completion or response to an internal processor,
20938 * the order of writes has to be such that this field is written last.
20941 } __attribute__((packed));
20943 /* ctx_hw_stats (size:1280b/160B) */
20944 struct ctx_hw_stats {
20945 /* Number of received unicast packets */
20946 uint64_t rx_ucast_pkts;
20947 /* Number of received multicast packets */
20948 uint64_t rx_mcast_pkts;
20949 /* Number of received broadcast packets */
20950 uint64_t rx_bcast_pkts;
20951 /* Number of discarded packets on received path */
20952 uint64_t rx_discard_pkts;
20953 /* Number of dropped packets on received path */
20954 uint64_t rx_drop_pkts;
20955 /* Number of received bytes for unicast traffic */
20956 uint64_t rx_ucast_bytes;
20957 /* Number of received bytes for multicast traffic */
20958 uint64_t rx_mcast_bytes;
20959 /* Number of received bytes for broadcast traffic */
20960 uint64_t rx_bcast_bytes;
20961 /* Number of transmitted unicast packets */
20962 uint64_t tx_ucast_pkts;
20963 /* Number of transmitted multicast packets */
20964 uint64_t tx_mcast_pkts;
20965 /* Number of transmitted broadcast packets */
20966 uint64_t tx_bcast_pkts;
20967 /* Number of discarded packets on transmit path */
20968 uint64_t tx_discard_pkts;
20969 /* Number of dropped packets on transmit path */
20970 uint64_t tx_drop_pkts;
20971 /* Number of transmitted bytes for unicast traffic */
20972 uint64_t tx_ucast_bytes;
20973 /* Number of transmitted bytes for multicast traffic */
20974 uint64_t tx_mcast_bytes;
20975 /* Number of transmitted bytes for broadcast traffic */
20976 uint64_t tx_bcast_bytes;
20977 /* Number of TPA packets */
20979 /* Number of TPA bytes */
20980 uint64_t tpa_bytes;
20981 /* Number of TPA events */
20982 uint64_t tpa_events;
20983 /* Number of TPA aborts */
20984 uint64_t tpa_aborts;
20985 } __attribute__((packed));
20987 /***********************
20988 * hwrm_stat_ctx_alloc *
20989 ***********************/
20992 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
20993 struct hwrm_stat_ctx_alloc_input {
20994 /* The HWRM command request type. */
20997 * The completion ring to send the completion event on. This should
20998 * be the NQ ID returned from the `nq_alloc` HWRM command.
21000 uint16_t cmpl_ring;
21002 * The sequence ID is used by the driver for tracking multiple
21003 * commands. This ID is treated as opaque data by the firmware and
21004 * the value is returned in the `hwrm_resp_hdr` upon completion.
21008 * The target ID of the command:
21009 * * 0x0-0xFFF8 - The function ID
21010 * * 0xFFF8-0xFFFE - Reserved for internal processors
21013 uint16_t target_id;
21015 * A physical address pointer pointing to a host buffer that the
21016 * command's response data will be written. This can be either a host
21017 * physical address (HPA) or a guest physical address (GPA) and must
21018 * point to a physically contiguous block of memory.
21020 uint64_t resp_addr;
21021 /* This is the address for statistic block. */
21022 uint64_t stats_dma_addr;
21024 * The statistic block update period in ms.
21025 * e.g. 250ms, 500ms, 750ms, 1000ms.
21026 * If update_period_ms is 0, then the stats update
21027 * shall be never done and the DMA address shall not be used.
21028 * In this case, the stat block can only be read by
21029 * hwrm_stat_ctx_query command.
21031 uint32_t update_period_ms;
21033 * This field is used to specify statistics context specific
21034 * configuration flags.
21036 uint8_t stat_ctx_flags;
21038 * When this bit is set to '1', the statistics context shall be
21039 * allocated for RoCE traffic only. In this case, traffic other
21040 * than offloaded RoCE traffic shall not be included in this
21041 * statistic context.
21042 * When this bit is set to '0', the statistics context shall be
21043 * used for the network traffic other than offloaded RoCE traffic.
21045 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
21046 uint8_t unused_0[3];
21047 } __attribute__((packed));
21049 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
21050 struct hwrm_stat_ctx_alloc_output {
21051 /* The specific error status for the command. */
21052 uint16_t error_code;
21053 /* The HWRM command request type. */
21055 /* The sequence ID from the original command. */
21057 /* The length of the response data in number of bytes. */
21059 /* This is the statistics context ID value. */
21060 uint32_t stat_ctx_id;
21061 uint8_t unused_0[3];
21063 * This field is used in Output records to indicate that the output
21064 * is completely written to RAM. This field should be read as '1'
21065 * to indicate that the output has been completely written.
21066 * When writing a command completion or response to an internal processor,
21067 * the order of writes has to be such that this field is written last.
21070 } __attribute__((packed));
21072 /**********************
21073 * hwrm_stat_ctx_free *
21074 **********************/
21077 /* hwrm_stat_ctx_free_input (size:192b/24B) */
21078 struct hwrm_stat_ctx_free_input {
21079 /* The HWRM command request type. */
21082 * The completion ring to send the completion event on. This should
21083 * be the NQ ID returned from the `nq_alloc` HWRM command.
21085 uint16_t cmpl_ring;
21087 * The sequence ID is used by the driver for tracking multiple
21088 * commands. This ID is treated as opaque data by the firmware and
21089 * the value is returned in the `hwrm_resp_hdr` upon completion.
21093 * The target ID of the command:
21094 * * 0x0-0xFFF8 - The function ID
21095 * * 0xFFF8-0xFFFE - Reserved for internal processors
21098 uint16_t target_id;
21100 * A physical address pointer pointing to a host buffer that the
21101 * command's response data will be written. This can be either a host
21102 * physical address (HPA) or a guest physical address (GPA) and must
21103 * point to a physically contiguous block of memory.
21105 uint64_t resp_addr;
21106 /* ID of the statistics context that is being queried. */
21107 uint32_t stat_ctx_id;
21108 uint8_t unused_0[4];
21109 } __attribute__((packed));
21111 /* hwrm_stat_ctx_free_output (size:128b/16B) */
21112 struct hwrm_stat_ctx_free_output {
21113 /* The specific error status for the command. */
21114 uint16_t error_code;
21115 /* The HWRM command request type. */
21117 /* The sequence ID from the original command. */
21119 /* The length of the response data in number of bytes. */
21121 /* This is the statistics context ID value. */
21122 uint32_t stat_ctx_id;
21123 uint8_t unused_0[3];
21125 * This field is used in Output records to indicate that the output
21126 * is completely written to RAM. This field should be read as '1'
21127 * to indicate that the output has been completely written.
21128 * When writing a command completion or response to an internal processor,
21129 * the order of writes has to be such that this field is written last.
21132 } __attribute__((packed));
21134 /***********************
21135 * hwrm_stat_ctx_query *
21136 ***********************/
21139 /* hwrm_stat_ctx_query_input (size:192b/24B) */
21140 struct hwrm_stat_ctx_query_input {
21141 /* The HWRM command request type. */
21144 * The completion ring to send the completion event on. This should
21145 * be the NQ ID returned from the `nq_alloc` HWRM command.
21147 uint16_t cmpl_ring;
21149 * The sequence ID is used by the driver for tracking multiple
21150 * commands. This ID is treated as opaque data by the firmware and
21151 * the value is returned in the `hwrm_resp_hdr` upon completion.
21155 * The target ID of the command:
21156 * * 0x0-0xFFF8 - The function ID
21157 * * 0xFFF8-0xFFFE - Reserved for internal processors
21160 uint16_t target_id;
21162 * A physical address pointer pointing to a host buffer that the
21163 * command's response data will be written. This can be either a host
21164 * physical address (HPA) or a guest physical address (GPA) and must
21165 * point to a physically contiguous block of memory.
21167 uint64_t resp_addr;
21168 /* ID of the statistics context that is being queried. */
21169 uint32_t stat_ctx_id;
21170 uint8_t unused_0[4];
21171 } __attribute__((packed));
21173 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
21174 struct hwrm_stat_ctx_query_output {
21175 /* The specific error status for the command. */
21176 uint16_t error_code;
21177 /* The HWRM command request type. */
21179 /* The sequence ID from the original command. */
21181 /* The length of the response data in number of bytes. */
21183 /* Number of transmitted unicast packets */
21184 uint64_t tx_ucast_pkts;
21185 /* Number of transmitted multicast packets */
21186 uint64_t tx_mcast_pkts;
21187 /* Number of transmitted broadcast packets */
21188 uint64_t tx_bcast_pkts;
21189 /* Number of transmitted packets with error */
21190 uint64_t tx_err_pkts;
21191 /* Number of dropped packets on transmit path */
21192 uint64_t tx_drop_pkts;
21193 /* Number of transmitted bytes for unicast traffic */
21194 uint64_t tx_ucast_bytes;
21195 /* Number of transmitted bytes for multicast traffic */
21196 uint64_t tx_mcast_bytes;
21197 /* Number of transmitted bytes for broadcast traffic */
21198 uint64_t tx_bcast_bytes;
21199 /* Number of received unicast packets */
21200 uint64_t rx_ucast_pkts;
21201 /* Number of received multicast packets */
21202 uint64_t rx_mcast_pkts;
21203 /* Number of received broadcast packets */
21204 uint64_t rx_bcast_pkts;
21205 /* Number of received packets with error */
21206 uint64_t rx_err_pkts;
21207 /* Number of dropped packets on received path */
21208 uint64_t rx_drop_pkts;
21209 /* Number of received bytes for unicast traffic */
21210 uint64_t rx_ucast_bytes;
21211 /* Number of received bytes for multicast traffic */
21212 uint64_t rx_mcast_bytes;
21213 /* Number of received bytes for broadcast traffic */
21214 uint64_t rx_bcast_bytes;
21215 /* Number of aggregated unicast packets */
21216 uint64_t rx_agg_pkts;
21217 /* Number of aggregated unicast bytes */
21218 uint64_t rx_agg_bytes;
21219 /* Number of aggregation events */
21220 uint64_t rx_agg_events;
21221 /* Number of aborted aggregations */
21222 uint64_t rx_agg_aborts;
21223 uint8_t unused_0[7];
21225 * This field is used in Output records to indicate that the output
21226 * is completely written to RAM. This field should be read as '1'
21227 * to indicate that the output has been completely written.
21228 * When writing a command completion or response to an internal processor,
21229 * the order of writes has to be such that this field is written last.
21232 } __attribute__((packed));
21234 /***************************
21235 * hwrm_stat_ctx_clr_stats *
21236 ***************************/
21239 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
21240 struct hwrm_stat_ctx_clr_stats_input {
21241 /* The HWRM command request type. */
21244 * The completion ring to send the completion event on. This should
21245 * be the NQ ID returned from the `nq_alloc` HWRM command.
21247 uint16_t cmpl_ring;
21249 * The sequence ID is used by the driver for tracking multiple
21250 * commands. This ID is treated as opaque data by the firmware and
21251 * the value is returned in the `hwrm_resp_hdr` upon completion.
21255 * The target ID of the command:
21256 * * 0x0-0xFFF8 - The function ID
21257 * * 0xFFF8-0xFFFE - Reserved for internal processors
21260 uint16_t target_id;
21262 * A physical address pointer pointing to a host buffer that the
21263 * command's response data will be written. This can be either a host
21264 * physical address (HPA) or a guest physical address (GPA) and must
21265 * point to a physically contiguous block of memory.
21267 uint64_t resp_addr;
21268 /* ID of the statistics context that is being queried. */
21269 uint32_t stat_ctx_id;
21270 uint8_t unused_0[4];
21271 } __attribute__((packed));
21273 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
21274 struct hwrm_stat_ctx_clr_stats_output {
21275 /* The specific error status for the command. */
21276 uint16_t error_code;
21277 /* The HWRM command request type. */
21279 /* The sequence ID from the original command. */
21281 /* The length of the response data in number of bytes. */
21283 uint8_t unused_0[7];
21285 * This field is used in Output records to indicate that the output
21286 * is completely written to RAM. This field should be read as '1'
21287 * to indicate that the output has been completely written.
21288 * When writing a command completion or response to an internal processor,
21289 * the order of writes has to be such that this field is written last.
21292 } __attribute__((packed));
21294 /********************
21295 * hwrm_pcie_qstats *
21296 ********************/
21299 /* hwrm_pcie_qstats_input (size:256b/32B) */
21300 struct hwrm_pcie_qstats_input {
21301 /* The HWRM command request type. */
21304 * The completion ring to send the completion event on. This should
21305 * be the NQ ID returned from the `nq_alloc` HWRM command.
21307 uint16_t cmpl_ring;
21309 * The sequence ID is used by the driver for tracking multiple
21310 * commands. This ID is treated as opaque data by the firmware and
21311 * the value is returned in the `hwrm_resp_hdr` upon completion.
21315 * The target ID of the command:
21316 * * 0x0-0xFFF8 - The function ID
21317 * * 0xFFF8-0xFFFE - Reserved for internal processors
21320 uint16_t target_id;
21322 * A physical address pointer pointing to a host buffer that the
21323 * command's response data will be written. This can be either a host
21324 * physical address (HPA) or a guest physical address (GPA) and must
21325 * point to a physically contiguous block of memory.
21327 uint64_t resp_addr;
21329 * The size of PCIe statistics block in bytes.
21330 * Firmware will DMA the PCIe statistics to
21331 * the host with this field size in the response.
21333 uint16_t pcie_stat_size;
21334 uint8_t unused_0[6];
21336 * This is the host address where
21337 * PCIe statistics will be stored
21339 uint64_t pcie_stat_host_addr;
21340 } __attribute__((packed));
21342 /* hwrm_pcie_qstats_output (size:128b/16B) */
21343 struct hwrm_pcie_qstats_output {
21344 /* The specific error status for the command. */
21345 uint16_t error_code;
21346 /* The HWRM command request type. */
21348 /* The sequence ID from the original command. */
21350 /* The length of the response data in number of bytes. */
21352 /* The size of PCIe statistics block in bytes. */
21353 uint16_t pcie_stat_size;
21354 uint8_t unused_0[5];
21356 * This field is used in Output records to indicate that the output
21357 * is completely written to RAM. This field should be read as '1'
21358 * to indicate that the output has been completely written.
21359 * When writing a command completion or response to an internal processor,
21360 * the order of writes has to be such that this field is written last.
21363 } __attribute__((packed));
21365 /* Port Tx Statistics Formats */
21366 /* tx_port_stats (size:3264b/408B) */
21367 struct tx_port_stats {
21368 /* Total Number of 64 Bytes frames transmitted */
21369 uint64_t tx_64b_frames;
21370 /* Total Number of 65-127 Bytes frames transmitted */
21371 uint64_t tx_65b_127b_frames;
21372 /* Total Number of 128-255 Bytes frames transmitted */
21373 uint64_t tx_128b_255b_frames;
21374 /* Total Number of 256-511 Bytes frames transmitted */
21375 uint64_t tx_256b_511b_frames;
21376 /* Total Number of 512-1023 Bytes frames transmitted */
21377 uint64_t tx_512b_1023b_frames;
21378 /* Total Number of 1024-1518 Bytes frames transmitted */
21379 uint64_t tx_1024b_1518_frames;
21381 * Total Number of each good VLAN (exludes FCS errors)
21382 * frame transmitted which is 1519 to 1522 bytes in length
21383 * inclusive (excluding framing bits but including FCS bytes).
21385 uint64_t tx_good_vlan_frames;
21386 /* Total Number of 1519-2047 Bytes frames transmitted */
21387 uint64_t tx_1519b_2047_frames;
21388 /* Total Number of 2048-4095 Bytes frames transmitted */
21389 uint64_t tx_2048b_4095b_frames;
21390 /* Total Number of 4096-9216 Bytes frames transmitted */
21391 uint64_t tx_4096b_9216b_frames;
21392 /* Total Number of 9217-16383 Bytes frames transmitted */
21393 uint64_t tx_9217b_16383b_frames;
21394 /* Total Number of good frames transmitted */
21395 uint64_t tx_good_frames;
21396 /* Total Number of frames transmitted */
21397 uint64_t tx_total_frames;
21398 /* Total number of unicast frames transmitted */
21399 uint64_t tx_ucast_frames;
21400 /* Total number of multicast frames transmitted */
21401 uint64_t tx_mcast_frames;
21402 /* Total number of broadcast frames transmitted */
21403 uint64_t tx_bcast_frames;
21404 /* Total number of PAUSE control frames transmitted */
21405 uint64_t tx_pause_frames;
21407 * Total number of PFC/per-priority PAUSE
21408 * control frames transmitted
21410 uint64_t tx_pfc_frames;
21411 /* Total number of jabber frames transmitted */
21412 uint64_t tx_jabber_frames;
21413 /* Total number of frames transmitted with FCS error */
21414 uint64_t tx_fcs_err_frames;
21415 /* Total number of control frames transmitted */
21416 uint64_t tx_control_frames;
21417 /* Total number of over-sized frames transmitted */
21418 uint64_t tx_oversz_frames;
21419 /* Total number of frames with single deferral */
21420 uint64_t tx_single_dfrl_frames;
21421 /* Total number of frames with multiple deferrals */
21422 uint64_t tx_multi_dfrl_frames;
21423 /* Total number of frames with single collision */
21424 uint64_t tx_single_coll_frames;
21425 /* Total number of frames with multiple collisions */
21426 uint64_t tx_multi_coll_frames;
21427 /* Total number of frames with late collisions */
21428 uint64_t tx_late_coll_frames;
21429 /* Total number of frames with excessive collisions */
21430 uint64_t tx_excessive_coll_frames;
21431 /* Total number of fragmented frames transmitted */
21432 uint64_t tx_frag_frames;
21433 /* Total number of transmit errors */
21435 /* Total number of single VLAN tagged frames transmitted */
21436 uint64_t tx_tagged_frames;
21437 /* Total number of double VLAN tagged frames transmitted */
21438 uint64_t tx_dbl_tagged_frames;
21439 /* Total number of runt frames transmitted */
21440 uint64_t tx_runt_frames;
21441 /* Total number of TX FIFO under runs */
21442 uint64_t tx_fifo_underruns;
21444 * Total number of PFC frames with PFC enabled bit for
21445 * Pri 0 transmitted
21447 uint64_t tx_pfc_ena_frames_pri0;
21449 * Total number of PFC frames with PFC enabled bit for
21450 * Pri 1 transmitted
21452 uint64_t tx_pfc_ena_frames_pri1;
21454 * Total number of PFC frames with PFC enabled bit for
21455 * Pri 2 transmitted
21457 uint64_t tx_pfc_ena_frames_pri2;
21459 * Total number of PFC frames with PFC enabled bit for
21460 * Pri 3 transmitted
21462 uint64_t tx_pfc_ena_frames_pri3;
21464 * Total number of PFC frames with PFC enabled bit for
21465 * Pri 4 transmitted
21467 uint64_t tx_pfc_ena_frames_pri4;
21469 * Total number of PFC frames with PFC enabled bit for
21470 * Pri 5 transmitted
21472 uint64_t tx_pfc_ena_frames_pri5;
21474 * Total number of PFC frames with PFC enabled bit for
21475 * Pri 6 transmitted
21477 uint64_t tx_pfc_ena_frames_pri6;
21479 * Total number of PFC frames with PFC enabled bit for
21480 * Pri 7 transmitted
21482 uint64_t tx_pfc_ena_frames_pri7;
21483 /* Total number of EEE LPI Events on TX */
21484 uint64_t tx_eee_lpi_events;
21485 /* EEE LPI Duration Counter on TX */
21486 uint64_t tx_eee_lpi_duration;
21488 * Total number of Link Level Flow Control (LLFC) messages
21491 uint64_t tx_llfc_logical_msgs;
21492 /* Total number of HCFC messages transmitted */
21493 uint64_t tx_hcfc_msgs;
21494 /* Total number of TX collisions */
21495 uint64_t tx_total_collisions;
21496 /* Total number of transmitted bytes */
21498 /* Total number of end-to-end HOL frames */
21499 uint64_t tx_xthol_frames;
21500 /* Total Tx Drops per Port reported by STATS block */
21501 uint64_t tx_stat_discard;
21502 /* Total Tx Error Drops per Port reported by STATS block */
21503 uint64_t tx_stat_error;
21504 } __attribute__((packed));
21506 /* Port Rx Statistics Formats */
21507 /* rx_port_stats (size:4224b/528B) */
21508 struct rx_port_stats {
21509 /* Total Number of 64 Bytes frames received */
21510 uint64_t rx_64b_frames;
21511 /* Total Number of 65-127 Bytes frames received */
21512 uint64_t rx_65b_127b_frames;
21513 /* Total Number of 128-255 Bytes frames received */
21514 uint64_t rx_128b_255b_frames;
21515 /* Total Number of 256-511 Bytes frames received */
21516 uint64_t rx_256b_511b_frames;
21517 /* Total Number of 512-1023 Bytes frames received */
21518 uint64_t rx_512b_1023b_frames;
21519 /* Total Number of 1024-1518 Bytes frames received */
21520 uint64_t rx_1024b_1518_frames;
21522 * Total Number of each good VLAN (exludes FCS errors)
21523 * frame received which is 1519 to 1522 bytes in length
21524 * inclusive (excluding framing bits but including FCS bytes).
21526 uint64_t rx_good_vlan_frames;
21527 /* Total Number of 1519-2047 Bytes frames received */
21528 uint64_t rx_1519b_2047b_frames;
21529 /* Total Number of 2048-4095 Bytes frames received */
21530 uint64_t rx_2048b_4095b_frames;
21531 /* Total Number of 4096-9216 Bytes frames received */
21532 uint64_t rx_4096b_9216b_frames;
21533 /* Total Number of 9217-16383 Bytes frames received */
21534 uint64_t rx_9217b_16383b_frames;
21535 /* Total number of frames received */
21536 uint64_t rx_total_frames;
21537 /* Total number of unicast frames received */
21538 uint64_t rx_ucast_frames;
21539 /* Total number of multicast frames received */
21540 uint64_t rx_mcast_frames;
21541 /* Total number of broadcast frames received */
21542 uint64_t rx_bcast_frames;
21543 /* Total number of received frames with FCS error */
21544 uint64_t rx_fcs_err_frames;
21545 /* Total number of control frames received */
21546 uint64_t rx_ctrl_frames;
21547 /* Total number of PAUSE frames received */
21548 uint64_t rx_pause_frames;
21549 /* Total number of PFC frames received */
21550 uint64_t rx_pfc_frames;
21552 * Total number of frames received with an unsupported
21555 uint64_t rx_unsupported_opcode_frames;
21557 * Total number of frames received with an unsupported
21558 * DA for pause and PFC
21560 uint64_t rx_unsupported_da_pausepfc_frames;
21561 /* Total number of frames received with an unsupported SA */
21562 uint64_t rx_wrong_sa_frames;
21563 /* Total number of received packets with alignment error */
21564 uint64_t rx_align_err_frames;
21565 /* Total number of received frames with out-of-range length */
21566 uint64_t rx_oor_len_frames;
21567 /* Total number of received frames with error termination */
21568 uint64_t rx_code_err_frames;
21570 * Total number of received frames with a false carrier is
21571 * detected during idle, as defined by RX_ER samples active
21572 * and RXD is 0xE. The event is reported along with the
21573 * statistics generated on the next received frame. Only
21574 * one false carrier condition can be detected and logged
21577 * Carrier event, valid for 10M/100M speed modes only.
21579 uint64_t rx_false_carrier_frames;
21580 /* Total number of over-sized frames received */
21581 uint64_t rx_ovrsz_frames;
21582 /* Total number of jabber packets received */
21583 uint64_t rx_jbr_frames;
21584 /* Total number of received frames with MTU error */
21585 uint64_t rx_mtu_err_frames;
21586 /* Total number of received frames with CRC match */
21587 uint64_t rx_match_crc_frames;
21588 /* Total number of frames received promiscuously */
21589 uint64_t rx_promiscuous_frames;
21591 * Total number of received frames with one or two VLAN
21594 uint64_t rx_tagged_frames;
21595 /* Total number of received frames with two VLAN tags */
21596 uint64_t rx_double_tagged_frames;
21597 /* Total number of truncated frames received */
21598 uint64_t rx_trunc_frames;
21599 /* Total number of good frames (without errors) received */
21600 uint64_t rx_good_frames;
21602 * Total number of received PFC frames with transition from
21603 * XON to XOFF on Pri 0
21605 uint64_t rx_pfc_xon2xoff_frames_pri0;
21607 * Total number of received PFC frames with transition from
21608 * XON to XOFF on Pri 1
21610 uint64_t rx_pfc_xon2xoff_frames_pri1;
21612 * Total number of received PFC frames with transition from
21613 * XON to XOFF on Pri 2
21615 uint64_t rx_pfc_xon2xoff_frames_pri2;
21617 * Total number of received PFC frames with transition from
21618 * XON to XOFF on Pri 3
21620 uint64_t rx_pfc_xon2xoff_frames_pri3;
21622 * Total number of received PFC frames with transition from
21623 * XON to XOFF on Pri 4
21625 uint64_t rx_pfc_xon2xoff_frames_pri4;
21627 * Total number of received PFC frames with transition from
21628 * XON to XOFF on Pri 5
21630 uint64_t rx_pfc_xon2xoff_frames_pri5;
21632 * Total number of received PFC frames with transition from
21633 * XON to XOFF on Pri 6
21635 uint64_t rx_pfc_xon2xoff_frames_pri6;
21637 * Total number of received PFC frames with transition from
21638 * XON to XOFF on Pri 7
21640 uint64_t rx_pfc_xon2xoff_frames_pri7;
21642 * Total number of received PFC frames with PFC enabled
21645 uint64_t rx_pfc_ena_frames_pri0;
21647 * Total number of received PFC frames with PFC enabled
21650 uint64_t rx_pfc_ena_frames_pri1;
21652 * Total number of received PFC frames with PFC enabled
21655 uint64_t rx_pfc_ena_frames_pri2;
21657 * Total number of received PFC frames with PFC enabled
21660 uint64_t rx_pfc_ena_frames_pri3;
21662 * Total number of received PFC frames with PFC enabled
21665 uint64_t rx_pfc_ena_frames_pri4;
21667 * Total number of received PFC frames with PFC enabled
21670 uint64_t rx_pfc_ena_frames_pri5;
21672 * Total number of received PFC frames with PFC enabled
21675 uint64_t rx_pfc_ena_frames_pri6;
21677 * Total number of received PFC frames with PFC enabled
21680 uint64_t rx_pfc_ena_frames_pri7;
21681 /* Total Number of frames received with SCH CRC error */
21682 uint64_t rx_sch_crc_err_frames;
21683 /* Total Number of under-sized frames received */
21684 uint64_t rx_undrsz_frames;
21685 /* Total Number of fragmented frames received */
21686 uint64_t rx_frag_frames;
21687 /* Total number of RX EEE LPI Events */
21688 uint64_t rx_eee_lpi_events;
21689 /* EEE LPI Duration Counter on RX */
21690 uint64_t rx_eee_lpi_duration;
21692 * Total number of physical type Link Level Flow Control
21693 * (LLFC) messages received
21695 uint64_t rx_llfc_physical_msgs;
21697 * Total number of logical type Link Level Flow Control
21698 * (LLFC) messages received
21700 uint64_t rx_llfc_logical_msgs;
21702 * Total number of logical type Link Level Flow Control
21703 * (LLFC) messages received with CRC error
21705 uint64_t rx_llfc_msgs_with_crc_err;
21706 /* Total number of HCFC messages received */
21707 uint64_t rx_hcfc_msgs;
21708 /* Total number of HCFC messages received with CRC error */
21709 uint64_t rx_hcfc_msgs_with_crc_err;
21710 /* Total number of received bytes */
21712 /* Total number of bytes received in runt frames */
21713 uint64_t rx_runt_bytes;
21714 /* Total number of runt frames received */
21715 uint64_t rx_runt_frames;
21716 /* Total Rx Discards per Port reported by STATS block */
21717 uint64_t rx_stat_discard;
21718 uint64_t rx_stat_err;
21719 } __attribute__((packed));
21721 /* Port Rx Statistics extended Formats */
21722 /* rx_port_stats_ext (size:320b/40B) */
21723 struct rx_port_stats_ext {
21724 /* Number of times link state changed to down */
21725 uint64_t link_down_events;
21726 /* Number of times the idle rings with pause bit are found */
21727 uint64_t continuous_pause_events;
21728 /* Number of times the active rings pause bit resumed back */
21729 uint64_t resume_pause_events;
21730 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
21731 uint64_t continuous_roce_pause_events;
21732 /* Number of times, the ROCE cos queue PFC is enabled back */
21733 uint64_t resume_roce_pause_events;
21734 } __attribute__((packed));
21736 /* PCIe Statistics Formats */
21737 /* pcie_ctx_hw_stats (size:768b/96B) */
21738 struct pcie_ctx_hw_stats {
21739 /* Number of physical layer receiver errors */
21740 uint64_t pcie_pl_signal_integrity;
21741 /* Number of DLLP CRC errors detected by Data Link Layer */
21742 uint64_t pcie_dl_signal_integrity;
21744 * Number of TLP LCRC and sequence number errors detected
21745 * by Data Link Layer
21747 uint64_t pcie_tl_signal_integrity;
21748 /* Number of times LTSSM entered Recovery state */
21749 uint64_t pcie_link_integrity;
21750 /* Number of TLP bytes that have been trasmitted */
21751 uint64_t pcie_tx_traffic_rate;
21752 /* Number of TLP bytes that have been received */
21753 uint64_t pcie_rx_traffic_rate;
21754 /* Number of DLLP bytes that have been trasmitted */
21755 uint64_t pcie_tx_dllp_statistics;
21756 /* Number of DLLP bytes that have been received */
21757 uint64_t pcie_rx_dllp_statistics;
21759 * Number of times spent in each phase of gen3
21762 uint64_t pcie_equalization_time;
21763 /* Records the last 16 transitions of the LTSSM */
21764 uint32_t pcie_ltssm_histogram[4];
21766 * Record the last 8 reasons on why LTSSM transitioned
21769 uint64_t pcie_recovery_histogram;
21770 } __attribute__((packed));
21772 /**********************
21773 * hwrm_exec_fwd_resp *
21774 **********************/
21777 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
21778 struct hwrm_exec_fwd_resp_input {
21779 /* The HWRM command request type. */
21782 * The completion ring to send the completion event on. This should
21783 * be the NQ ID returned from the `nq_alloc` HWRM command.
21785 uint16_t cmpl_ring;
21787 * The sequence ID is used by the driver for tracking multiple
21788 * commands. This ID is treated as opaque data by the firmware and
21789 * the value is returned in the `hwrm_resp_hdr` upon completion.
21793 * The target ID of the command:
21794 * * 0x0-0xFFF8 - The function ID
21795 * * 0xFFF8-0xFFFE - Reserved for internal processors
21798 uint16_t target_id;
21800 * A physical address pointer pointing to a host buffer that the
21801 * command's response data will be written. This can be either a host
21802 * physical address (HPA) or a guest physical address (GPA) and must
21803 * point to a physically contiguous block of memory.
21805 uint64_t resp_addr;
21807 * This is an encapsulated request. This request should
21808 * be executed by the HWRM and the response should be
21809 * provided in the response buffer inside the encapsulated
21812 uint32_t encap_request[26];
21814 * This value indicates the target id of the response to
21815 * the encapsulated request.
21816 * 0x0 - 0xFFF8 - Used for function ids
21817 * 0xFFF8 - 0xFFFE - Reserved for internal processors
21820 uint16_t encap_resp_target_id;
21821 uint8_t unused_0[6];
21822 } __attribute__((packed));
21824 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
21825 struct hwrm_exec_fwd_resp_output {
21826 /* The specific error status for the command. */
21827 uint16_t error_code;
21828 /* The HWRM command request type. */
21830 /* The sequence ID from the original command. */
21832 /* The length of the response data in number of bytes. */
21834 uint8_t unused_0[7];
21836 * This field is used in Output records to indicate that the output
21837 * is completely written to RAM. This field should be read as '1'
21838 * to indicate that the output has been completely written.
21839 * When writing a command completion or response to an internal processor,
21840 * the order of writes has to be such that this field is written last.
21843 } __attribute__((packed));
21845 /************************
21846 * hwrm_reject_fwd_resp *
21847 ************************/
21850 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
21851 struct hwrm_reject_fwd_resp_input {
21852 /* The HWRM command request type. */
21855 * The completion ring to send the completion event on. This should
21856 * be the NQ ID returned from the `nq_alloc` HWRM command.
21858 uint16_t cmpl_ring;
21860 * The sequence ID is used by the driver for tracking multiple
21861 * commands. This ID is treated as opaque data by the firmware and
21862 * the value is returned in the `hwrm_resp_hdr` upon completion.
21866 * The target ID of the command:
21867 * * 0x0-0xFFF8 - The function ID
21868 * * 0xFFF8-0xFFFE - Reserved for internal processors
21871 uint16_t target_id;
21873 * A physical address pointer pointing to a host buffer that the
21874 * command's response data will be written. This can be either a host
21875 * physical address (HPA) or a guest physical address (GPA) and must
21876 * point to a physically contiguous block of memory.
21878 uint64_t resp_addr;
21880 * This is an encapsulated request. This request should
21881 * be rejected by the HWRM and the error response should be
21882 * provided in the response buffer inside the encapsulated
21885 uint32_t encap_request[26];
21887 * This value indicates the target id of the response to
21888 * the encapsulated request.
21889 * 0x0 - 0xFFF8 - Used for function ids
21890 * 0xFFF8 - 0xFFFE - Reserved for internal processors
21893 uint16_t encap_resp_target_id;
21894 uint8_t unused_0[6];
21895 } __attribute__((packed));
21897 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
21898 struct hwrm_reject_fwd_resp_output {
21899 /* The specific error status for the command. */
21900 uint16_t error_code;
21901 /* The HWRM command request type. */
21903 /* The sequence ID from the original command. */
21905 /* The length of the response data in number of bytes. */
21907 uint8_t unused_0[7];
21909 * This field is used in Output records to indicate that the output
21910 * is completely written to RAM. This field should be read as '1'
21911 * to indicate that the output has been completely written.
21912 * When writing a command completion or response to an internal processor,
21913 * the order of writes has to be such that this field is written last.
21916 } __attribute__((packed));
21923 /* hwrm_fwd_resp_input (size:1024b/128B) */
21924 struct hwrm_fwd_resp_input {
21925 /* The HWRM command request type. */
21928 * The completion ring to send the completion event on. This should
21929 * be the NQ ID returned from the `nq_alloc` HWRM command.
21931 uint16_t cmpl_ring;
21933 * The sequence ID is used by the driver for tracking multiple
21934 * commands. This ID is treated as opaque data by the firmware and
21935 * the value is returned in the `hwrm_resp_hdr` upon completion.
21939 * The target ID of the command:
21940 * * 0x0-0xFFF8 - The function ID
21941 * * 0xFFF8-0xFFFE - Reserved for internal processors
21944 uint16_t target_id;
21946 * A physical address pointer pointing to a host buffer that the
21947 * command's response data will be written. This can be either a host
21948 * physical address (HPA) or a guest physical address (GPA) and must
21949 * point to a physically contiguous block of memory.
21951 uint64_t resp_addr;
21953 * This value indicates the target id of the encapsulated
21955 * 0x0 - 0xFFF8 - Used for function ids
21956 * 0xFFF8 - 0xFFFE - Reserved for internal processors
21959 uint16_t encap_resp_target_id;
21961 * This value indicates the completion ring the encapsulated
21962 * response will be optionally completed on. If the value is
21963 * -1, then no CR completion shall be generated for the
21964 * encapsulated response. Any other value must be a
21965 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
21966 * is provided, then a CR completion shall be generated for
21967 * the encapsulated response.
21969 uint16_t encap_resp_cmpl_ring;
21970 /* This field indicates the length of encapsulated response. */
21971 uint16_t encap_resp_len;
21975 * This is the host address where the encapsulated response
21977 * This area must be 16B aligned and must be cleared to zero
21978 * before the original request is made.
21980 uint64_t encap_resp_addr;
21981 /* This is an encapsulated response. */
21982 uint32_t encap_resp[24];
21983 } __attribute__((packed));
21985 /* hwrm_fwd_resp_output (size:128b/16B) */
21986 struct hwrm_fwd_resp_output {
21987 /* The specific error status for the command. */
21988 uint16_t error_code;
21989 /* The HWRM command request type. */
21991 /* The sequence ID from the original command. */
21993 /* The length of the response data in number of bytes. */
21995 uint8_t unused_0[7];
21997 * This field is used in Output records to indicate that the output
21998 * is completely written to RAM. This field should be read as '1'
21999 * to indicate that the output has been completely written.
22000 * When writing a command completion or response to an internal processor,
22001 * the order of writes has to be such that this field is written last.
22004 } __attribute__((packed));
22006 /**************************
22007 * hwrm_nvm_raw_write_blk *
22008 **************************/
22011 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
22012 struct hwrm_nvm_raw_write_blk_input {
22013 /* The HWRM command request type. */
22016 * The completion ring to send the completion event on. This should
22017 * be the NQ ID returned from the `nq_alloc` HWRM command.
22019 uint16_t cmpl_ring;
22021 * The sequence ID is used by the driver for tracking multiple
22022 * commands. This ID is treated as opaque data by the firmware and
22023 * the value is returned in the `hwrm_resp_hdr` upon completion.
22027 * The target ID of the command:
22028 * * 0x0-0xFFF8 - The function ID
22029 * * 0xFFF8-0xFFFE - Reserved for internal processors
22032 uint16_t target_id;
22034 * A physical address pointer pointing to a host buffer that the
22035 * command's response data will be written. This can be either a host
22036 * physical address (HPA) or a guest physical address (GPA) and must
22037 * point to a physically contiguous block of memory.
22039 uint64_t resp_addr;
22041 * 64-bit Host Source Address.
22042 * This is the loation of the source data to be written.
22044 uint64_t host_src_addr;
22046 * 32-bit Destination Address.
22047 * This is the NVRAM byte-offset where the source data will be written to.
22049 uint32_t dest_addr;
22050 /* Length of data to be written, in bytes. */
22052 } __attribute__((packed));
22054 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
22055 struct hwrm_nvm_raw_write_blk_output {
22056 /* The specific error status for the command. */
22057 uint16_t error_code;
22058 /* The HWRM command request type. */
22060 /* The sequence ID from the original command. */
22062 /* The length of the response data in number of bytes. */
22064 uint8_t unused_0[7];
22066 * This field is used in Output records to indicate that the output
22067 * is completely written to RAM. This field should be read as '1'
22068 * to indicate that the output has been completely written.
22069 * When writing a command completion or response to an internal processor,
22070 * the order of writes has to be such that this field is written last.
22073 } __attribute__((packed));
22080 /* hwrm_nvm_read_input (size:320b/40B) */
22081 struct hwrm_nvm_read_input {
22082 /* The HWRM command request type. */
22085 * The completion ring to send the completion event on. This should
22086 * be the NQ ID returned from the `nq_alloc` HWRM command.
22088 uint16_t cmpl_ring;
22090 * The sequence ID is used by the driver for tracking multiple
22091 * commands. This ID is treated as opaque data by the firmware and
22092 * the value is returned in the `hwrm_resp_hdr` upon completion.
22096 * The target ID of the command:
22097 * * 0x0-0xFFF8 - The function ID
22098 * * 0xFFF8-0xFFFE - Reserved for internal processors
22101 uint16_t target_id;
22103 * A physical address pointer pointing to a host buffer that the
22104 * command's response data will be written. This can be either a host
22105 * physical address (HPA) or a guest physical address (GPA) and must
22106 * point to a physically contiguous block of memory.
22108 uint64_t resp_addr;
22110 * 64-bit Host Destination Address.
22111 * This is the host address where the data will be written to.
22113 uint64_t host_dest_addr;
22114 /* The 0-based index of the directory entry. */
22116 uint8_t unused_0[2];
22117 /* The NVRAM byte-offset to read from. */
22119 /* The length of the data to be read, in bytes. */
22121 uint8_t unused_1[4];
22122 } __attribute__((packed));
22124 /* hwrm_nvm_read_output (size:128b/16B) */
22125 struct hwrm_nvm_read_output {
22126 /* The specific error status for the command. */
22127 uint16_t error_code;
22128 /* The HWRM command request type. */
22130 /* The sequence ID from the original command. */
22132 /* The length of the response data in number of bytes. */
22134 uint8_t unused_0[7];
22136 * This field is used in Output records to indicate that the output
22137 * is completely written to RAM. This field should be read as '1'
22138 * to indicate that the output has been completely written.
22139 * When writing a command completion or response to an internal processor,
22140 * the order of writes has to be such that this field is written last.
22143 } __attribute__((packed));
22145 /*********************
22146 * hwrm_nvm_raw_dump *
22147 *********************/
22150 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
22151 struct hwrm_nvm_raw_dump_input {
22152 /* The HWRM command request type. */
22155 * The completion ring to send the completion event on. This should
22156 * be the NQ ID returned from the `nq_alloc` HWRM command.
22158 uint16_t cmpl_ring;
22160 * The sequence ID is used by the driver for tracking multiple
22161 * commands. This ID is treated as opaque data by the firmware and
22162 * the value is returned in the `hwrm_resp_hdr` upon completion.
22166 * The target ID of the command:
22167 * * 0x0-0xFFF8 - The function ID
22168 * * 0xFFF8-0xFFFE - Reserved for internal processors
22171 uint16_t target_id;
22173 * A physical address pointer pointing to a host buffer that the
22174 * command's response data will be written. This can be either a host
22175 * physical address (HPA) or a guest physical address (GPA) and must
22176 * point to a physically contiguous block of memory.
22178 uint64_t resp_addr;
22180 * 64-bit Host Destination Address.
22181 * This is the host address where the data will be written to.
22183 uint64_t host_dest_addr;
22184 /* 32-bit NVRAM byte-offset to read from. */
22186 /* Total length of NVRAM contents to be read, in bytes. */
22188 } __attribute__((packed));
22190 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
22191 struct hwrm_nvm_raw_dump_output {
22192 /* The specific error status for the command. */
22193 uint16_t error_code;
22194 /* The HWRM command request type. */
22196 /* The sequence ID from the original command. */
22198 /* The length of the response data in number of bytes. */
22200 uint8_t unused_0[7];
22202 * This field is used in Output records to indicate that the output
22203 * is completely written to RAM. This field should be read as '1'
22204 * to indicate that the output has been completely written.
22205 * When writing a command completion or response to an internal processor,
22206 * the order of writes has to be such that this field is written last.
22209 } __attribute__((packed));
22211 /****************************
22212 * hwrm_nvm_get_dir_entries *
22213 ****************************/
22216 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
22217 struct hwrm_nvm_get_dir_entries_input {
22218 /* The HWRM command request type. */
22221 * The completion ring to send the completion event on. This should
22222 * be the NQ ID returned from the `nq_alloc` HWRM command.
22224 uint16_t cmpl_ring;
22226 * The sequence ID is used by the driver for tracking multiple
22227 * commands. This ID is treated as opaque data by the firmware and
22228 * the value is returned in the `hwrm_resp_hdr` upon completion.
22232 * The target ID of the command:
22233 * * 0x0-0xFFF8 - The function ID
22234 * * 0xFFF8-0xFFFE - Reserved for internal processors
22237 uint16_t target_id;
22239 * A physical address pointer pointing to a host buffer that the
22240 * command's response data will be written. This can be either a host
22241 * physical address (HPA) or a guest physical address (GPA) and must
22242 * point to a physically contiguous block of memory.
22244 uint64_t resp_addr;
22246 * 64-bit Host Destination Address.
22247 * This is the host address where the directory will be written.
22249 uint64_t host_dest_addr;
22250 } __attribute__((packed));
22252 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
22253 struct hwrm_nvm_get_dir_entries_output {
22254 /* The specific error status for the command. */
22255 uint16_t error_code;
22256 /* The HWRM command request type. */
22258 /* The sequence ID from the original command. */
22260 /* The length of the response data in number of bytes. */
22262 uint8_t unused_0[7];
22264 * This field is used in Output records to indicate that the output
22265 * is completely written to RAM. This field should be read as '1'
22266 * to indicate that the output has been completely written.
22267 * When writing a command completion or response to an internal processor,
22268 * the order of writes has to be such that this field is written last.
22271 } __attribute__((packed));
22273 /*************************
22274 * hwrm_nvm_get_dir_info *
22275 *************************/
22278 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
22279 struct hwrm_nvm_get_dir_info_input {
22280 /* The HWRM command request type. */
22283 * The completion ring to send the completion event on. This should
22284 * be the NQ ID returned from the `nq_alloc` HWRM command.
22286 uint16_t cmpl_ring;
22288 * The sequence ID is used by the driver for tracking multiple
22289 * commands. This ID is treated as opaque data by the firmware and
22290 * the value is returned in the `hwrm_resp_hdr` upon completion.
22294 * The target ID of the command:
22295 * * 0x0-0xFFF8 - The function ID
22296 * * 0xFFF8-0xFFFE - Reserved for internal processors
22299 uint16_t target_id;
22301 * A physical address pointer pointing to a host buffer that the
22302 * command's response data will be written. This can be either a host
22303 * physical address (HPA) or a guest physical address (GPA) and must
22304 * point to a physically contiguous block of memory.
22306 uint64_t resp_addr;
22307 } __attribute__((packed));
22309 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
22310 struct hwrm_nvm_get_dir_info_output {
22311 /* The specific error status for the command. */
22312 uint16_t error_code;
22313 /* The HWRM command request type. */
22315 /* The sequence ID from the original command. */
22317 /* The length of the response data in number of bytes. */
22319 /* Number of directory entries in the directory. */
22321 /* Size of each directory entry, in bytes. */
22322 uint32_t entry_length;
22323 uint8_t unused_0[7];
22325 * This field is used in Output records to indicate that the output
22326 * is completely written to RAM. This field should be read as '1'
22327 * to indicate that the output has been completely written.
22328 * When writing a command completion or response to an internal processor,
22329 * the order of writes has to be such that this field is written last.
22332 } __attribute__((packed));
22334 /******************
22336 ******************/
22339 /* hwrm_nvm_write_input (size:384b/48B) */
22340 struct hwrm_nvm_write_input {
22341 /* The HWRM command request type. */
22344 * The completion ring to send the completion event on. This should
22345 * be the NQ ID returned from the `nq_alloc` HWRM command.
22347 uint16_t cmpl_ring;
22349 * The sequence ID is used by the driver for tracking multiple
22350 * commands. This ID is treated as opaque data by the firmware and
22351 * the value is returned in the `hwrm_resp_hdr` upon completion.
22355 * The target ID of the command:
22356 * * 0x0-0xFFF8 - The function ID
22357 * * 0xFFF8-0xFFFE - Reserved for internal processors
22360 uint16_t target_id;
22362 * A physical address pointer pointing to a host buffer that the
22363 * command's response data will be written. This can be either a host
22364 * physical address (HPA) or a guest physical address (GPA) and must
22365 * point to a physically contiguous block of memory.
22367 uint64_t resp_addr;
22369 * 64-bit Host Source Address.
22370 * This is where the source data is.
22372 uint64_t host_src_addr;
22373 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
22376 * Directory ordinal.
22377 * The 0-based instance of the combined Directory Entry Type and Extension.
22379 uint16_t dir_ordinal;
22380 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
22382 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
22385 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
22386 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
22388 uint32_t dir_data_length;
22393 * When this bit is '1', the original active image
22394 * will not be removed. TBD: what purpose is this?
22396 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
22399 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
22400 * If this value is less than the specified data length, it will be ignored.
22401 * The response will contain the actual allocated item length, which may be greater than the requested item length.
22402 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
22403 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
22405 uint32_t dir_item_length;
22407 } __attribute__((packed));
22409 /* hwrm_nvm_write_output (size:128b/16B) */
22410 struct hwrm_nvm_write_output {
22411 /* The specific error status for the command. */
22412 uint16_t error_code;
22413 /* The HWRM command request type. */
22415 /* The sequence ID from the original command. */
22417 /* The length of the response data in number of bytes. */
22420 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
22421 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
22423 uint32_t dir_item_length;
22424 /* The directory index of the created or modified item. */
22428 * This field is used in Output records to indicate that the output
22429 * is completely written to RAM. This field should be read as '1'
22430 * to indicate that the output has been completely written.
22431 * When writing a command completion or response to an internal processor,
22432 * the order of writes has to be such that this field is written last.
22435 } __attribute__((packed));
22437 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
22438 struct hwrm_nvm_write_cmd_err {
22440 * command specific error codes that goes to
22441 * the cmd_err field in Common HWRM Error Response.
22444 /* Unknown error */
22445 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
22446 /* Unable to complete operation due to fragmentation */
22447 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
22448 /* nvm is completely full. */
22449 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
22450 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
22451 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
22452 uint8_t unused_0[7];
22453 } __attribute__((packed));
22455 /*******************
22456 * hwrm_nvm_modify *
22457 *******************/
22460 /* hwrm_nvm_modify_input (size:320b/40B) */
22461 struct hwrm_nvm_modify_input {
22462 /* The HWRM command request type. */
22465 * The completion ring to send the completion event on. This should
22466 * be the NQ ID returned from the `nq_alloc` HWRM command.
22468 uint16_t cmpl_ring;
22470 * The sequence ID is used by the driver for tracking multiple
22471 * commands. This ID is treated as opaque data by the firmware and
22472 * the value is returned in the `hwrm_resp_hdr` upon completion.
22476 * The target ID of the command:
22477 * * 0x0-0xFFF8 - The function ID
22478 * * 0xFFF8-0xFFFE - Reserved for internal processors
22481 uint16_t target_id;
22483 * A physical address pointer pointing to a host buffer that the
22484 * command's response data will be written. This can be either a host
22485 * physical address (HPA) or a guest physical address (GPA) and must
22486 * point to a physically contiguous block of memory.
22488 uint64_t resp_addr;
22490 * 64-bit Host Source Address.
22491 * This is where the modified data is.
22493 uint64_t host_src_addr;
22494 /* 16-bit directory entry index. */
22496 uint8_t unused_0[2];
22497 /* 32-bit NVRAM byte-offset to modify content from. */
22500 * Length of data to be modified, in bytes. The length shall
22504 uint8_t unused_1[4];
22505 } __attribute__((packed));
22507 /* hwrm_nvm_modify_output (size:128b/16B) */
22508 struct hwrm_nvm_modify_output {
22509 /* The specific error status for the command. */
22510 uint16_t error_code;
22511 /* The HWRM command request type. */
22513 /* The sequence ID from the original command. */
22515 /* The length of the response data in number of bytes. */
22517 uint8_t unused_0[7];
22519 * This field is used in Output records to indicate that the output
22520 * is completely written to RAM. This field should be read as '1'
22521 * to indicate that the output has been completely written.
22522 * When writing a command completion or response to an internal processor,
22523 * the order of writes has to be such that this field is written last.
22526 } __attribute__((packed));
22528 /***************************
22529 * hwrm_nvm_find_dir_entry *
22530 ***************************/
22533 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
22534 struct hwrm_nvm_find_dir_entry_input {
22535 /* The HWRM command request type. */
22538 * The completion ring to send the completion event on. This should
22539 * be the NQ ID returned from the `nq_alloc` HWRM command.
22541 uint16_t cmpl_ring;
22543 * The sequence ID is used by the driver for tracking multiple
22544 * commands. This ID is treated as opaque data by the firmware and
22545 * the value is returned in the `hwrm_resp_hdr` upon completion.
22549 * The target ID of the command:
22550 * * 0x0-0xFFF8 - The function ID
22551 * * 0xFFF8-0xFFFE - Reserved for internal processors
22554 uint16_t target_id;
22556 * A physical address pointer pointing to a host buffer that the
22557 * command's response data will be written. This can be either a host
22558 * physical address (HPA) or a guest physical address (GPA) and must
22559 * point to a physically contiguous block of memory.
22561 uint64_t resp_addr;
22564 * This bit must be '1' for the dir_idx_valid field to be
22567 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
22569 /* Directory Entry Index */
22571 /* Directory Entry (Image) Type */
22574 * Directory ordinal.
22575 * The instance of this Directory Type
22577 uint16_t dir_ordinal;
22578 /* The Directory Entry Extension flags. */
22580 /* This value indicates the search option using dir_ordinal. */
22581 uint8_t opt_ordinal;
22582 /* This value indicates the search option using dir_ordinal. */
22583 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
22584 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
22585 /* Equal to specified ordinal value. */
22586 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
22587 /* Greater than or equal to specified ordinal value */
22588 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
22589 /* Greater than specified ordinal value */
22590 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
22591 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
22592 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
22593 uint8_t unused_0[3];
22594 } __attribute__((packed));
22596 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
22597 struct hwrm_nvm_find_dir_entry_output {
22598 /* The specific error status for the command. */
22599 uint16_t error_code;
22600 /* The HWRM command request type. */
22602 /* The sequence ID from the original command. */
22604 /* The length of the response data in number of bytes. */
22606 /* Allocated NVRAM for this directory entry, in bytes. */
22607 uint32_t dir_item_length;
22608 /* Size of the stored data for this directory entry, in bytes. */
22609 uint32_t dir_data_length;
22611 * Firmware version.
22612 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
22615 /* Directory ordinal. */
22616 uint16_t dir_ordinal;
22617 /* Directory Entry Index */
22619 uint8_t unused_0[7];
22621 * This field is used in Output records to indicate that the output
22622 * is completely written to RAM. This field should be read as '1'
22623 * to indicate that the output has been completely written.
22624 * When writing a command completion or response to an internal processor,
22625 * the order of writes has to be such that this field is written last.
22628 } __attribute__((packed));
22630 /****************************
22631 * hwrm_nvm_erase_dir_entry *
22632 ****************************/
22635 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
22636 struct hwrm_nvm_erase_dir_entry_input {
22637 /* The HWRM command request type. */
22640 * The completion ring to send the completion event on. This should
22641 * be the NQ ID returned from the `nq_alloc` HWRM command.
22643 uint16_t cmpl_ring;
22645 * The sequence ID is used by the driver for tracking multiple
22646 * commands. This ID is treated as opaque data by the firmware and
22647 * the value is returned in the `hwrm_resp_hdr` upon completion.
22651 * The target ID of the command:
22652 * * 0x0-0xFFF8 - The function ID
22653 * * 0xFFF8-0xFFFE - Reserved for internal processors
22656 uint16_t target_id;
22658 * A physical address pointer pointing to a host buffer that the
22659 * command's response data will be written. This can be either a host
22660 * physical address (HPA) or a guest physical address (GPA) and must
22661 * point to a physically contiguous block of memory.
22663 uint64_t resp_addr;
22664 /* Directory Entry Index */
22666 uint8_t unused_0[6];
22667 } __attribute__((packed));
22669 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
22670 struct hwrm_nvm_erase_dir_entry_output {
22671 /* The specific error status for the command. */
22672 uint16_t error_code;
22673 /* The HWRM command request type. */
22675 /* The sequence ID from the original command. */
22677 /* The length of the response data in number of bytes. */
22679 uint8_t unused_0[7];
22681 * This field is used in Output records to indicate that the output
22682 * is completely written to RAM. This field should be read as '1'
22683 * to indicate that the output has been completely written.
22684 * When writing a command completion or response to an internal processor,
22685 * the order of writes has to be such that this field is written last.
22688 } __attribute__((packed));
22691 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */